Intel® CoreTM 2 Duo processor
and Mobile Intel® GME965
Express Chipset
Development Kit User Manual
June 2007
Document Number: 316704-001
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Contents
1
2
3
About This Manual ............................................................................................6
1.1
1.2
1.3
1.4
Content Overview...................................................................................6
Text Conventions ...................................................................................6
Glossary of Terms and Acronyms..............................................................8
Support Options...................................................................................13
1.4.1
1.4.2
Electronic Support Systems ......................................................13
Additional Technical Support.....................................................13
1.5
1.6
Product Literature.................................................................................13
Related Documents...............................................................................14
Getting Started...............................................................................................15
2.1
Overview ............................................................................................15
2.1.1 Development Board Features ....................................................15
2.2
2.3
Included Hardware and Documentation ...................................................17
Software Key Features ..........................................................................17
2.3.1
AMI BIOS...............................................................................18
2.4
2.5
2.6
Before You Begin..................................................................................18
Setting Up the Development Board .........................................................20
Configuring the BIOS............................................................................22
Theory of Operation ........................................................................................24
3.1
3.2
3.3
3.4
Block Diagram .....................................................................................24
Mechanical Form Factor.........................................................................24
Thermal Management ...........................................................................25
System Features and Operation..............................................................25
3.4.1
3.4.2
3.4.3
Mobile Intel® GME965 GMCH.....................................................25
ICH8-M..................................................................................27
POST Code Debugger...............................................................31
3.5
3.6
3.7
Clock Generation..................................................................................31
Power Management States.....................................................................31
Power Measurement Support..................................................................33
4
Hardware Reference........................................................................................39
4.1
4.2
Primary Features..................................................................................39
Back Panel Connectors..........................................................................41
4.2.1
TV-Out D-Connector ................................................................42
4.3
4.4
4.5
4.6
Configuration Settings...........................................................................43
Power On and Reset Buttons..................................................................47
LEDs ..................................................................................................48
Other Headers, Slots and Sockets...........................................................49
4.6.1
4.6.2
H8 Programming Headers.........................................................49
Expansion Slots and Sockets.....................................................50
Appendix A
. Heatsink Installation Instructions ....................................................................64
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Figures
Figure 1. Development Board Block Diagram.......................................................24
Figure 2. Development Board Component Locations.............................................39
Figure 3. Back Panel Connector Locations...........................................................42
Figure 4. D-Connector to Component Video Cable................................................43
Figure 5. D-Connector to Composite Video Cable.................................................43
Figure 6. D-Connector to S-Video Cable .............................................................43
Figure 7. Configuration Jumper and Switch Locations ...........................................44
Figure 8. LED Locations ...................................................................................48
Figure 9. Heatsink and Backplate ......................................................................64
Figure 10. Backplate Pins.................................................................................65
Figure 11. Applying the Thermal Grease.............................................................66
Figure 12. Squeezing Activation Arm..................................................................66
Figure 13. Installing the Heatsink......................................................................67
Figure 14. Plugging in the Fan ..........................................................................68
Figure 15. Completed Assembly ........................................................................68
Tables
Table 1. Text Conventions..................................................................................7
Table 2. Terms and Acronyms.............................................................................8
Table 3. Acronyms .........................................................................................10
Table 4. Intel Literature Centers........................................................................13
Table 5. Related Documents .............................................................................14
Table 6. Development Board feature Set Summary..............................................15
Table 7. BIOS Location Strapping Options...........................................................30
Table 8. Primary System Clocks ........................................................................31
Table 9. Power Management States ...................................................................32
Table 10. Power Management M-States..............................................................32
Table 11. Sleep Signals and M-State Definition....................................................33
Table 12. Development Board Voltage Rails ........................................................34
Table 13. Development Board Component Location Legend...................................40
Table 14. Back Panel Connector Definitions.........................................................42
Table 15. Supported Configuration Jumper/Switch Settings...................................44
Table 16. LED Functions...................................................................................48
Table 17. Expansion Slots and Sockets...............................................................50
Table 18. PCI Express* (x16) Pinout (J6B2)........................................................51
Table 19. ADD2 Slot (J6B2)..............................................................................54
Table 20. MEC Slot (J6B2)................................................................................57
Table 21. PCI Express* (x1) Pinout (J6B1, J7B1, J8B4).........................................60
Table 22. IDE Connector ..................................................................................60
Table 23. SATA Port 0 ‘Direct Connect’ Connector Pinout (J8J1).............................61
Table 24. SATA Ports 1 and 2 ‘Cable Connect’ Connector Pinout (J7J3, J7H1)...........61
Table 25. SATA Power Connection (J7H2)...........................................................62
Table 26. Fan Connectors (J2B3, J2C1) ..............................................................62
Table 27. Fan Connector (J2F1) ........................................................................62
Table 28. Front Panel Connector........................................................................62
Table 29. USB Headers ....................................................................................63
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Revision History
Document
Number
Revision
Number
Description
Revision Date
316704
001
Initial public release.
June 2007
§
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About This Manual
1 About This Manual
This user’s manual describes the use of the Intel® CoreTM 2 Duo processor and Mobile
Intel® GME965 Express Chipset development kit. This manual has been written for
OEMs, system evaluators, and embedded system developers. This document defines
all jumpers, headers, LED functions, and their locations on the development board,
along with subsystem features and POST codes. This manual assumes basic familiarity
in the fundamental concepts involved with installing and configuring hardware for a
personal computer system.
For the latest information about the Intel® CoreTM 2 Duo processor and Mobile Intel®
GME965 Express Chipset Development Kit, visit:
For design documents related to this platform please visit:
Chipset:
1.1
Content Overview
Chapter 1.0, “About This Manual” — This chapter contains a description of conventions
used in this manual. The last few sections explain how to obtain literature and contact
customer support.
Chapter 2.0, “Getting Started”— Provides complete instructions on how to configure
the development board and processor assembly by setting jumpers, connecting
peripherals and providing power.
Chapter 3.0, “Theory of Operation” — This chapter provides information on the system
design.
Chapter 4.0, “Hardware Reference”— This chapter provides a description of jumper
settings and functions, development board debug capabilities, and pinout information
for connectors.
Appendix A, “Heatsink Installation Instructions” gives detailed installation instructions
for the Intel® CoreTM 2 Duo processor heatsink.
1.2
Text Conventions
The notations listed in Table 1 may be used throughout this manual.
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Table 1. Text Conventions
Notation
Definition
#
The pound symbol (#) appended to a signal name indicates that the signal
is active low. (e.g., PRSNT1#)
Variables
Variables are shown in italics. Variables must be replaced with correct
values.
Instructions
Instruction mnemonics are shown in uppercase. When you are
programming, instructions are not case-sensitive. You may use either
uppercase or lowercase.
Numbers
Hexadecimal numbers are represented by a string of hexadecimal digits
followed by the character H. A zero prefix is added to numbers that begin
with A through F. (For example, FF is shown as 0FFH.) Decimal and binary
numbers are represented by their customary notations. (That is, 255 is a
decimal number and 1111 is a binary number. In some cases, the letter B
is added for clarity.)
Units of Measure
The following abbreviations are used to represent units of measure:
A
GByte
KByte
KΩ
amps, amperes
gigabytes
kilobytes
kilo-ohms
mA
MByte
MHz
ms
mW
ns
milliamps, milliamperes
megabytes
megahertz
milliseconds
milliwatts
nanoseconds
picofarads
pF
W
watts
V
volts
µA
µF
µs
µW
microamps, microamperes
microfarads
microseconds
microwatts
Signal Names
Signal names are shown in uppercase. When several signals share a
common name, an individual signal is represented by the signal name
followed by a number, while the group is represented by the signal name
followed by a variable (n). For example, the lower chip-select signals are
named CS0#, CS1#, CS2#, and so on; they are collectively called CSn#.
A pound symbol (#) appended to a signal name identifies an active-low
signal. Port pins are represented by the port abbreviation, a period, and
the pin number (e.g., P1.0).
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1.3
Glossary of Terms and Acronyms
Table 2 defines conventions and terminology used throughout this document.
Table 2. Terms and Acronyms
Term/Acronym
Definition
Aggressor
Anti-etch
A network that transmits a coupled signal to another network.
Any plane-split, void or cutout in a VCC or GND plane.
Assisted Gunning
Transceiver Logic+
The front-side bus uses a bus technology called AGTL+, or Assisted
Gunning Transceiver Logic. AGTL+ buffers are open-drain, and require
pull-up resistors to provide the high logic level and termination. AGTL+
output buffers differ from GTL+ buffers with the addition of an active
pMOS pull-up transistor to assist the pull-up resistors during the first clock
of a low-to-high voltage transition.
Asynchronous
GTL+
The processor does not utilize CMOS voltage levels on any signals that
connect to the processor. As a result, legacy input signals such as A20M#,
IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, and
STPCLK# utilize GTL+ input buffers. Legacy output signals (FERR# and
IERR#) and non-AGTL+ signals (THERMTRIP# and PROCHOT#) also
utilize GTL+ output buffers. All of these signals follow the same DC
requirements as AGTL+ signals, however the outputs are not actively
driven high (during a logical 0 to 1 transition) by the processor (the major
difference between GTL+ and AGTL+). These signals do not have setup or
hold time specifications in relation to BCLK[1:0], and are therefore
referred to as “Asynchronous GTL+ Signals”. However, all of the
Asynchronous GTL+ signals are required to be asserted for at least two
BCLKs in order for the processor to recognize them.
Bus Agent
Crosstalk
A component or group of components that, when combined, represent a
single load on the AGTL+ bus.
The reception on a victim network of a signal imposed by aggressor
network(s) through inductive and capacitive coupling between the
networks.
Backward Crosstalk - Coupling that creates a signal in a victim network
that travels in the opposite direction as the aggressor’s signal.
Forward Crosstalk - Coupling that creates a signal in a victim network that
travels in the same direction as the aggressor’s signal.
Even Mode Crosstalk - Coupling from a signal or multiple aggressors when
all the aggressors switch in the same direction that the victim is switching.
Odd Mode Crosstalk - Coupling from a signal or multiple aggressors when
all the aggressors switch in the opposite direction that the victim is
switching.
Flight Time
Flight time is a term in the timing equation that includes the signal
propagation delay, any effects the system has on the TCO (time from
clock-in to data-out) of the driver, plus any adjustments to the signal at
the receiver needed to ensure the setup time of the receiver. More
precisely, flight time is defined as:
The time difference between a signal at the input pin of a receiving agent
crossing the switching voltage (adjusted to meet the receiver
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Term/Acronym
Definition
manufacturer’s conditions required for AC timing specifications; i.e.,
ringback, etc.) and the output pin of the driving agent crossing the
switching voltage when the driver is driving a test load used to specify the
driver’s AC timings.
Maximum and Minimum Flight Time - Flight time variations are caused by
many different parameters. The more obvious causes include variation of
the board dielectric constant, changes in load condition, crosstalk, power
noise, variation in termination resistance, and differences in I/O buffer
performance as a function of temperature, voltage, and manufacturing
process. Some less obvious causes include effects of Simultaneous
Switching Output (SSO) and packaging effects.
Maximum flight time is the largest acceptable flight time a network will
experience under all conditions.
Minimum flight time is the smallest acceptable flight time a network will
experience under all conditions.
Infrared Data
Assoc.
The Infrared Data Association (IrDA) has outlined a specification for serial
communication between two devices via a bi-directional infrared data
port. The development board has such a port and it is located on the rear
of the platform between the two USB connectors.
IMVP6+
The Intel Mobile Voltage Positioning specification for the Intel® Core™ 2
Duo Processor. It is a DC-DC converter module that supplies the required
voltage and current to a single processor.
Inter-Symbol
Interference
Inter-symbol interference is the effect of a previous signal (or transition)
on the interconnect delay. For example, when a signal is transmitted down
a line and the reflections due to the transition have not completely
dissipated, the following data transition launched onto the bus is affected.
ISI is dependent upon frequency, time delay of the line, and the reflection
coefficient at the driver and receiver. ISI may impact both timing and
signal integrity.
Media Expansion
Card
The Media Expansion Card (MEC) provides digital display options through
the SDVO interface. The MEC card also incorporates video-in via a x1 PCI
Express* port.
Network
Overshoot
Pad
The network is the trace of a Printed Circuit Board (PCB) that completes
an electrical connection between two or more components.
The maximum voltage observed for a signal at the device pad, measured
with respect to VCC.
The electrical contact point of a semiconductor die to the package
substrate. A pad is only observable in simulations.
Pin
The contact point of a component package to the traces on a substrate,
such as the motherboard. Signal quality and timings may be measured at
the pin.
Power-Good
Ringback
“Power-Good,” “PWRGOOD,” or “CPUPWRGOOD” (an active high signal)
indicates that all of the system power supplies and clocks are stable.
PWRGOOD should go active at a predetermined time after system
voltages are stable and should go inactive as soon as any of these
voltages fail their specifications.
The voltage to which a signal changes after reaching its maximum
absolute value. Ringback may be caused by reflections, driver oscillations,
or other transmission line phenomena.
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Term/Acronym
Definition
System Bus
The System Bus is the microprocessor bus of the processor.
Setup Window
The time between the beginning of Setup to Clock (TSU_MIN) and the
arrival of a valid clock edge. This window may be different for each type of
bus agent in the system.
Simultaneous
Switching Output
Simultaneous Switching Output (SSO) effects are differences in electrical
timing parameters and degradation in signal quality caused by multiple
signal outputs simultaneously switching voltage levels in the opposite
direction from a single signal or in the same direction. These are called
odd mode and even mode switching, respectively. This simultaneous
switching of multiple outputs creates higher current swings that may
cause additional propagation delay (“push-out”) or a decrease in
propagation delay (“pull-in”). These SSO effects may impact the setup
and/or hold times and are not always taken into account by simulations.
System timing budgets should include margin for SSO effects.
Stub
The branch from the bus trunk terminating at the pad of an agent.
The main connection, excluding interconnect branches, from one end.
Trunk
System
Management Bus
A two-wire interface through which various system components may
communicate.
Undershoot
VCC (CPU core)
Victim
The minimum voltage extending below VSS observed for a signal at the
device pad.
VCC (CPU core) is the core power for the processor. The system bus is
terminated to VCC (CPU core).
A network that receives a coupled crosstalk signal from another network is
called the victim network.
Table 3 defines the acronyms used throughout this document.
Table 3. Acronyms
Acronym
Definition
AC
Audio Codec
ACPI
ADD2
ADD2N
AGTL
AMC
ASF
Advanced Configuration and Power Interface
Advanced Digital Display 2
Advanced Digital Display 2 Normal
Assisted Gunning Transceiver Logic
Audio/Modem Codec.
Alert Standard Format
AMI
American Megatrends Inc. (BIOS developer)
Advanced Technology Attachment (disk drive interface)
Advance Technology Extended (motherboard form factor)
Ball Grid Array
ATA
ATX
BGA
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Acronym
Definition
BIOS
Basic Input/Output System
CK-SSCD
Spread Spectrum Differential Clock
Common Mode Choke
CMC
CMOS
CPU
Complementary Metal-Oxide-Semiconductor
Central Processing Unit (processor)
Double Data Rate
DDR
DMI
Direct Memory Interface
ECC
Error Correcting Code
EEPROM
EHCI
EMA
EMI
Electrically Erasable Programmable Read-Only Memory
Enhanced Host Controller Interface
Extended Media Access
Electro Magnetic Interference
Electrostatic Discharge
ESD
EV
Engineering Validation
EVMC
FCBGA
FCPGA
FIFO
FS
Electrical Validation Margining Card
Flip Chip Ball Grid Array
Flip Chip Pin Grid Array
First In First Out - describes a type of buffer
Full-speed. Refers to USB
Front Side Bus
FSB
FWH
GMCH
HDA
HDMI
HS
Firmware Hub
Graphics Memory Controller Hub
High Definition Audio
High Definition Media Interface
High-speed. Refers to USB
I/O Controller Hub
ICH
IDE
Integrated Drive Electronics
Intel Mobile Voltage Positioning
Internet Protocol/Internet Protocol version 6
Infrared Data Association
Inter-Symbol Interference
Keyboard Controller
IMVP
IP/IPv6
IrDA
ISI
KBC
LAI
Logic Analyzer Interface
LAN
Local Area Network
LED
Light Emitting Diode
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Acronym
Definition
LOM
LPC
LAN on Motherboard
Low Pin Count
LS
Low-speed. Refers to USB
LVDS
mBGA
MC
Low Voltage Differential Signaling
Mini Ball Grid Array
Modem Codec
MEC
MHz
OEM
PCIe
PCM
POST
PLC
Media Expansion Card
Mega-Hertz
Original Equipment Manufacturer
PCI Express*
Pulse Code Modulation
Power On Self Test
Platform LAN Connect
Redundant Array of Inexpensive Disks
Real Time Clock
RAID
RTC
SATA
SIO
Serial ATA
Super Input/Output
SKU
SMBus
StockKeeping Unit
System Management Bus
Small Outline Dual In-line Memory Module
Serial Presence Detect
Serial Peripheral Interface
SODIMM
SPD
SPI
SPWG
SSO
STR
Standard Panels Working Group - http://www.spwg.org/
Simultaneous Switching Output
Suspend To RAM
TCO
Total Cost of Ownership
TCP
Transmission Control Protocol
Time Division Multiplexed
Time Domain Reflectometry
Micro Ball Grid Array
TDM
TDR
µBGA
UDP
User Datagram Protocol
UHCI
USB
Universal Host Controller Interface
Universal Serial Bus
VGA
VID
Video Graphics Adapter
Voltage Identification
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Acronym
Definition
VREG
XDP
Voltage Regulator
eXtended Debug Port
1.4
Support Options
1.4.1
Electronic Support Systems
product support. This information is available 24 hours per day, 7 days per week,
providing technical information whenever you need it.
1.4.2
Additional Technical Support
If you require additional technical support, please contact your Intel Representative or
local distributor.
1.5
Product Literature
In order to order hard copies of product literature the following instructions should be
followed:
1. Determine the SKU Number
If you do not know the SKU # of the document you are ordering, please select
the back button to view the document again. The SKU # is the first 6 digits of
the number on the PDF file, such as: 12345612.pdf or at the bottom of the
download page for that document.
2. Call, Mail or Email a request
Call: To place an order for a publication or text in hardcopy or CD form,
please contact our Intel® Literature Fulfillment Centers listed in Table 4.
Table 4. Intel Literature Centers
Location
U.S. and Canada
Telephone Number
1-800-548-4725
International
Fax
1-303-675-2148
1-303-675-2120
Mail a request to:
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Intel Literature Fulfilment Center
P.O. Box 5937
Denver, Colorado 80217-9808
USA
Please make sure to include in your mailed/emailed request:
SKU #
Company Name
Your Name (first, last)
Full mailing address
Daytime Phone Number in case of questions
Note: Please be aware not all documents are available in all media types. Some may only be
available as a download.
1.6
Related Documents
Table 5 provides a summary of publicly available documents related to this
development kit. For additional documentation, please contact your Intel
Representative.
Table 5. Related Documents
Document Title
Location
Intel® Core™2 Duo Processor for Mobile
Intel® 965 Express Chipset Family
Datasheet
745.htm
Mobile Intel® 965 Express Chipset Family
Datasheet
273.htm
Intel® I/O Controller Hub 8 (ICH8) Family
Datasheet
13056.htm
Intel® Centrino® Pro processor technology
and Intel® Centrino® Duo processor
technology Design Guide For Intel®
Core™2 Duo Mobile Processor, Mobile
Intel® 965 Express Chipset Family and
Intel® 82801HBM ICH8M & Intel®
82801HEM ICH8M-E I/O Controller Hub
Based Systems
Contact your Intel representative for access to
this document
Intel® Core™2 Duo Mobile Processor,
Mobile Intel® 965 Express Chipset Family
and ICH8M I/O Controller Hub Schematics
Contact your Intel representative for access to
this document
§
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Getting Started
2 Getting Started
This chapter identifies the development kit’s key components, features and
specifications. It also details basic development board setup and operation.
2.1
Overview
The development board consists of a baseboard populated with the Intel® CoreTM
Duo processor, the Mobile Intel® GME965 Express Chipset, other system board
components and peripheral connectors.
2
Note: The development board is shipped as an open system allowing for maximum flexibility
in changing hardware configuration and peripherals. Since the board is not in a
protective chassis, take extra precaution when handling and operating the system.
2.1.1
Development Board Features
Features of the development board are summarized in Table 6.
Table 6. Development Board feature Set Summary
Development Board
Implementation
Comments
Intel® CoreTM 2 Duo processor with
4 MByte L2 Cache on 65nm process
478 pin Flip Chip Pin Grid Array (Micro-
FCPGA) package
Processor
FSB 533/667/800 MHz support
Mobile Intel® GME965 Express
Chipset (GMCH)
1299-pin Micro-FCBGA Package
676-pin BGA Package
F
Chipset
E
Intel® I/O Controller Hub 8-M
Enhanced (ICH8M-E)
A
T
U
R
E
Two DDR2 RAM SO-DIMM slots.
Maximum 4GB of DDR2 Memory (RAM)
using 1Gb technology and stacked SO-
DIMMs.
Memory
Supports DDR2 frequency of 533 or
667MHz
One PCI Express* Graphics Slot
One dual channel LVDS Connector
One VGA Connector
The Mobile Intel® GME965 Express Chipset
(GMCH) has 2 video pipes which allows
support of dual independent display.
Video
PCI
18-bpp and 24-bpp LVDS panel support
One TV D-Connector supporting S-
Video, Composite video and
Component video
Support for two SDVO channels via x16
PCIe connector (through ADD2 or MEC
cards)
One 5V PCI slot
PCI revision 2.3 compliant (33MHz)
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Getting Started
Development Board
Implementation
Comments
Three x1 connectors
Revision 1.1 compliant
F
One x16 connector
There are Five x1 PCI Express* slots but
slots 2 and 4 are not intended for use with
PCI Express* add-in cards. Only slots 1, 3
and 5 are supported.
PCI Express*
On-Board LAN
E
A
T
U
R
E
10/100/1000 Mbps connectivity
from the Intel® 82566MM Gigabit
Platform LAN Connect component
The 82566MM is connected to the ICH via
the ICH’s GLCI and LCI interfaces.
SPI
Two 16Mbit devices
PATA 33/66/100
3 SATA Ports
1 Channel
ATA/Storage
2 Cable Connector and 1 Direct Connect
Connector. RAID 0/1 support.
10 USB 2.0/1.1 Ports
Five ports provided on rear-panel, four
provided via headers (J6H3, J6H3) and
one via the PCI Express* docking
connector
USB
LPC
One LPC slot
Includes sideband headers
40-pin TSOP socket
ACPI compliant
BIOS
AMI BIOS installed in an 8Mb FWH
Hitachi H8S/2104 micro-controller
Two PS/2 ports
SMC/KBC
One scan matrix keyboard
connector
CK-505 clock synthesizer and
DB800M clock buffer
Clocks
Super I/O
RTC
SMSC SIO1007-JV
Supports IrDA and UART serial interfaces
Battery-backed Real Time Clock
Processor temperature sensor
Thermal
Monitoring
Processor
Voltage
IMVP-6+ for processor core
Regulator
Desktop Mode
Mobile Mode
ATX Power Supply
Power Supply
Battery Pack (smart battery support)
AC Mobile Brick
Port 80 display
Through Add-in card. Four seven-segment
displays
Debug
Interfaces
Extended Debug Port (XDP)
XDP connector
Intel® AMT
support
Intel® Active Management
Technology 2.5
Supported on the development board with
M0, M1, and M-off management states
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Getting Started
Development Board
Implementation
Comments
ACPI Compliant
S0 – Power On
S3 – Suspend to RAM
S4 – Suspend to Disk
Power
Management
S5 – Soft Off
M0 – All Wells powered
M1 – Main Well down. Only ME power on
M-off – ME powered off
10 layer board – 12” x 10.2”
Form Factor
ATX 2.2 like form factor
Note: Review the document provided with the Development Kit titled “Important Safety and
Regulatory Information”. This document contains safety warnings and cautions that
must be observed when using this development kit.
2.2
Included Hardware and Documentation
The following hardware and documentation is included in the development kit:
•
•
One development board
One Intel® CoreTM 2 Duo processor with 4 MB L2 Cache on 65nm process in
the 478 pin Flip-Chip Pin Grid Array (Micro-FCPGA) package (Installed)
•
•
•
•
•
One Firmware Hub (FWH) (Installed)
One GMCH (GME965) heatsink (Installed)
One Type 2032, socketed 3 V lithium coin cell battery (Installed)
One 256 MByte DDR2 SODIMM (200 Pin)
One CPU thermal solution and CPU back plate (included in kit box – not
populated on board)
•
•
•
One cable kit
One Development Kit User’s Manual
One Port 80 add-in card
2.3
Software Key Features
The driver CD included in the kit contains all of the software drivers necessary for
basic system functionality under the following operating systems: Windows* XP/XP
Embedded, Vista and Linux*.
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Note: While every care was taken to ensure the latest versions of drivers were provided on
the enclosed CD at time of publication, newer revisions may be available. Updated
drivers for Intel components can be found at:
For all third-party components, please contact the appropriate vendor for updated
drivers.
Note: Software in the kit is provided free by the vendor and is only licensed for evaluation
purposes. Refer to the documentation in your evaluation kit for further details on any
terms and conditions that may be applicable to the granted licenses. Customers using
the tools that work with Microsoft* products must license those products. Any targets
created by those tools should also have appropriate licenses. Software included in the
kit is subject to change.
software from other third-party vendors.
2.3.1
AMI BIOS
This development kit ships with AMI* BIOS pre-boot firmware from AMI* pre-
installed. AMI* BIOS provides an industry-standard BIOS platform to run most
standard operating systems, including Windows* XP/XP Embedded, Linux*, and
others.
The AMI* BIOS Application Kit (available through AMI*) includes complete source
code, a reference manual, and a Windows-based expert system, BIOStart*, to enable
easy and rapid configuration of customized firmware for your system.
The following features of AMI* BIOS are enabled in the development board:
•
•
•
•
•
•
•
•
•
DDR2 SDRAM detection, configuration, and initialization
Mobile Intel® GME965 Express Chipset configuration
POST codes displayed to port 80h
PCI/PCI Express* device enumeration and configuration
Integrated video configuration and initialization
Super I/O configuration
CPU microcode update
Active Management Technology
RAID 0/1 Support
2.4
Before You Begin
The following additional hardware may be necessary to successfully set up and
operate the development board.
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VGA Monitor: Any standard VGA or multi-resolution monitor may be used. The setup
instructions in this chapter assume the use of a standard VGA monitor, TV, or flat
panel monitor.
Keyboard: The development board can support either a PS/2 or USB style keyboard.
Mouse: The development board can support either a PS/2 or USB style mouse.
Hard Drives and Optical Disc Drives: Up to Three SATA drives and two IDE devices
(master and slave) may be connected to the development board. An optical disc drive
may be used to load the OS. All these storage devices may be attached to the board
simultaneously.
Video Adapter: Integrated video is output from the VGA connector on the back panel
of the development board. Alternately, a standard PCI Express* video adapter, ADD2
card or MEC video adapter may be used for additional display flexibility. Please contact
the respective vendors for drivers and necessary software for adapters not provided
with this development kit. Check the BIOS and the graphics driver, where appropriate,
for the proper video output settings.
Note: The enclosed driver CD includes drivers necessary for LAN, Integrated graphics, and
system INF utilities.
Network Adapter: A Gigabit network interface is provided on the development
board. The network interface will not be operational until after all the necessary
drivers have been installed. A standard PCI/PCI Express* adapter may be used in
conjunction with, or in place of, the onboard network adapter. Please contact the
respective vendors for drivers and necessary software for adapters not provided with
this development kit.
You must supply appropriate network cables to utilize the LAN connector or any other
installed network cards.
Power Supply: The development board has the option to be powered from two
different power sources: an ATX power supply or AC to DC adapter. The development
board contains all of the voltage regulators necessary to power the system.
There are two main supported power supply configurations, Desktop and Mobile. The
Desktop solution consists of only using the ATX power supply. The Mobile solution
consists of only using the AC to DC adapter.
Warning:The power supply cord is the main disconnect device to mains (AC power). The socket
outlet shall be installed near the equipment and shall be readily accessible.
Note: Desktop peripherals, including add-in cards, will not work in mobile power mode. If
desktop peripherals are used, the development board must be powered using desktop
power mode.
If using an ATX power supply, select a power supply that complies with the "ATX12V"
Note: If the power button on the ATX power supply is used to shut down the system, wait at
least five seconds before turning the system on again to avoid damaging the system.
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Getting Started
Other Devices and Adapters: The development board functions much like a
standard desktop computer motherboard. Most PC-compatible peripherals can be
attached and configured to work with the development board.
2.5
Setting Up the Development Board
Once the necessary hardware (described in Section 2.4) has been gathered, follow the
steps below to set up the development board.
Note: To locate items discussed in the procedure below, please refer to Chapter 4.
1. Create a safe work environment.
Ensure a static-free work environment before removing any components from
their anti-static packaging. The development board is susceptible to
electrostatic discharge (ESD) damage, and such damage may cause product
failure or unpredictable operation. A flame retardant work surface must also
be used.
Caution: It is recommended that an ESD wrist strap be used when handling the
development board.
2. Inspect the contents of your kit.
Check for damage that may have occurred during shipment. Contact your
sales representative if any items are missing or damaged.
Caution: Since the development board is not in a protective chassis, use caution
when connecting cables to this product.
Caution: Standby voltage is constantly applied to the development board. Remove
power before any hardware (peripherals, keyboards, mice, monitors,
accessories, add-in cards, etc) is added or removed from the board.
Note:
The development board is a standard ATX form factor. An ATX chassis may
be used if a protected environment is desired. If a chassis is not used,
standoffs must be used to elevate the development board off the working
surface to protect the memory and board components from any
accidental contact to metal objects.
3. Check the jumper default position setting. Refer to Figure 7 for jumper location.
Jumper J5H2 is used to clear the CMOS memory. Make sure this jumper is set to
1-x for normal operation.
4. Be sure to populate the following hardware on your development board:
•
•
•
One Intel® CoreTM 2 Duo processor
One processor thermal solution
One 256 MByte DDR2 667 SODIMM (200-pin) into connector J5P1.
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Getting Started
Note:
Ensure that the processor has been locked into the socket by turning the
socket screw fully clockwise.
Note:
For proper installation of the CPU thermal solution, please refer
to Appendix A
5. Connect a SATA or IDE hard disk drive.
6. Connect any additional storage devices to the development board.
7. Connect the keyboard and mouse.
Connect a PS/2-style or USB mouse and keyboard (see Figure 3 on page 38
for connector locations).
Note:
J1A1 (on the baseboard) is a stacked PS/2 connector. The bottom
connector is for the keyboard and the top is for the mouse.
8. Connect an Ethernet cable (optional).
9. Connect the monitor through the VGA connector.
10. Connect the power supply.
Connect an appropriate power supply to the development board. Make sure
the power supply is not plugged into an electrical outlet (turned off). After
connecting the power supply board connectors, plug the power supply cord
into an electrical outlet.
11. Power up the development board.
Power and Reset are implemented on the development board through buttons
located on SW1C1 and SW1C2, respectively. See Figure 7 for switch locations.
Turn on the power to the monitor and development board. Ensure that the
fansink on the processor is operating.
Note:
The power button may have to be pressed twice to turn the power on.
12. Install operating system and necessary drivers.
Depending on the operating system chosen, all necessary drivers for
components included in this development kit can be found on the enclosed
CD. Please see Section 2.3 for information on obtaining updated drivers.
2.6
Configuring the BIOS
AMI* BIOS is pre-loaded on the development board. The default BIOS settings may
need to be modified to enable/disable various features of the development board. The
BIOS settings are configured through a menu-driven user interface which is accessible
during the Power On Self Test (POST). The Delete key on the attached keyboard
should be pressed during POST to enter the interface. For AMI BIOS POST codes, visit:
For BIOS Updates please contact your Intel Sales Representative.
§
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Theory of Operation
3 Theory of Operation
3.1
Block Diagram
Figure 1. Development Board Block Diagram
3.2
Mechanical Form Factor
The development board conforms to the ATX form factor. For extra protection in a
development environment, you may want to install the development board in an ATX
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Theory of Operation
chassis. Internal and rear panel system I/O connectors are described in Section 3.4.
An overview of connector and slot locations is provided in Chapter 4.
3.3
Thermal Management
The objective of thermal management is to ensure that the temperature of each
component is maintained within specified functional limits. The functional temperature
limit is the range within which the electrical circuits can be expected to meet their
specified performance requirements. Operation outside the functional limit can
degrade system performance and cause reliability problems.
The development kit is shipped with a heatsink thermal solution for installation on the
processor. This thermal solution has been tested in an open-air environment at room
temperature and is sufficient for development purposes. The designer must ensure
that adequate thermal management is provided for if the system is used in other
environments or enclosures.
3.4
System Features and Operation
The following section provide a detailed view of the system features and operation of
the development board.
3.4.1
Mobile Intel® GME965 GMCH
The Mobile Intel® GME965 Express Chipset GMCH provides the processor interface
optimized for Intel® CoreTM 2 Duo processors, system memory interface, DMI and
internal graphics. It provides flexibility and scalability in graphics and memory
subsystem performance. The following list describes the development board’s
implementation of the Mobile Intel® GME965 Express Chipset GMCH features.
A list of features follows:
•
•
•
•
1299-ball Micro-FCBGA package
533/667/800 MHz Front Side Bus
36-bit host bus addressing
System memory controller (DDR2 implemented)
o
o
o
Supports Dual Channel and Single Channel operation
Two 200-pin SODIMM slots
DDR2 533/667
•
•
Direct Media Interface (DMI)
Integrated graphics based on the Intel Graphics Media Accelerator X3100
o
Directly supports on-board VGA, TV D-Connector and LVDS interfaces.
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Theory of Operation
•
SDVO interface via PCI Express* x16 connector provides maximum display
flexibility
o
Can drive up to two display outputs
3.4.1.1
System Memory
The development board supports DDR2 533/667 main memory. Two 200-pin SODIMM
connectors (one per channel) on the development board support unbuffered, non-ECC,
single and double-sided DDR2 533/667 MHz SODIMMs. These SODIMMs provide the
ability to use up to 1 Gbit technology for a maximum of 4 GBytes system memory.
Note: Memory that utilizes 128 MBit technology is not supported on the Mobile Intel®
GME965 Express Chipset.
Note: The SODIMM connectors are on the back side of the development board.
Caution: Standby voltage may be applied to the SODIMM sockets when the system is in the
S3, S4 and S5 states. Therefore, do not insert or remove SODIMMs unless the
system is unplugged.
3.4.1.2
DMI
The Mobile Intel® GME965 Express Chipset GMCH’s Direct Media Interface (DMI)
provides high-speed bi-directional chip-to-chip interconnect for communication with
the ICH8-M.
3.4.1.3
Advanced Graphics and Display Interfaces
The development board has five options for displaying video: VGA, LVDS, TV-Out,
SDVO, or PCI Express* Graphics. SDVO and PCI Express* Graphics are multiplexed on
the same pins within the Mobile Intel® GME965 Express Chipset. The development
board contains one SDVO/PCI Express* Graphics Slot (J6B2) for a PCI Express*
compatible graphics card or an SDVO compatible graphics card, one LVDS connector
(J6F1), one TV-Out connector (J2A1), and one 15-pin VGA connector (J2A2).
3.4.1.3.1 VGA Connector
A standard 15 pin D-Sub connector on the rear panel provides access to the analog
output of the Mobile Intel® GME965 Express Chipset. This can be connected to any
capable analog CRT or flat panel display with compatible input.
When used in conjunction with the other display options, the displays can operate in
Dual Independent mode. This allows unique content to appear on each display at
unique refresh rates and timings.
3.4.1.3.2 LVDS Flat Panel Interface
The development board provides one 50-pin LVDS video interface connector. The
interface is compliant with the SPWG 3.5 (for 18-bpp panels) and proposed SPWG 4.0
(for 24-bpp panels) standards.
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Theory of Operation
3.4.1.4
PCI Express x16 Slot
The development board provides access to one x16 PCI Express* connector. Any
industry standard x1 or x16 PCI Express* video adapter may be used with this
interface. Additionally, any industry standard non-graphics x1, x4 or x8 adapter may
also be used. x2 adapters are not part of the PCI Express* specification but x2 non-
graphics devices are also supported.
Note: The AMI BIOS that is included with the development board is configured to allow x2,
x4 and x8 non-graphics support through the x16 PCI Express* connector. If the user
wishes to use another BIOS on the development board then the BIOS may need to be
modified to support this feature.
3.4.2
ICH8-M
The ICH8-M is a highly integrated multifunctional I/O controller hub that provides the
interface to the system peripherals and integrates many of the functions needed in
today’s PC platforms. The following sections describe the development board
implementation of the ICH8-M features, which are listed below:
•
•
•
•
•
•
•
•
•
•
Three PCI Express* (x1) connectors
One PCI connectors
LPC interface
System Bus Management
ACPI* 3.0 compliant
Real Time Clock
676-ball mBGA package
Three SATA drive connectors
One IDE connector
Ten Universal Serial Bus (USB) 2.0 ports (five ports provided on rear-panel,
four provided via headers (J6H3, J6H4) and one on the docking connector.
3.4.2.1
PCI Express* Slots
The development board has three x1 PCI Express* slots for add-in cards. The PCI
Express* interface is compliant to the PCI Express* Rev. 1.1 Specification.
Note: There are actually Five x1 PCI Express* slots but slots 2 and 4 are not intended for
use with PCI Express* add-in cards. Only slots 1, 3 and 5 are supported.
3.4.2.2
PCI Slots
The development board has one 5V PCI slot for add-in cards. The PCI bus is compliant
to the PCI Rev. 2.3 Specification at 32-bit/33 MHz
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Theory of Operation
3.4.2.3
On-Board LAN
The development board has one RJ-45 interface – at connector J5A1 - through which
10/100/1000 ethernet is available. The ethernet MAC is located in the ICH8-M and the
PHY is located externally in the 82566MM LAN Connect Interface (LCI) device. The
82566MM is connected to the ICH8-M via two interfaces: LCI for 10/100 Mbps traffic
and GLCI (Gigabit LCI) for 1000Mbps traffic. Intel® Active Management Technology is
optionally supported through these components.
Information on Intel® Active Management Technology can be found at:
Note: Further details on the location of the RJ-45 interface can be found in Section 4.2.
3.4.2.4
High Definition Audio
Intel® High Definition Audio is not supported on the development board.
3.4.2.5
ATA/ Storage
The development board has one parallel ATA IDE connector and three serial ATA
connectors.
The parallel ATA IDE Connector is a standard 40-pin connector at J7J4. This connector
supports up to two Ultra ATA/100 hard drives; one master and one slave.
There are three SATA connectors on the development board – one ‘Direct Connect’
connector and two ‘Cable Connect’ connectors. The ‘Direct Connect’ connector, located
at J8J1, provides both signaling and power while the ‘Cable Connect’ connectors,
located at J7H1 and J7J3, only provides signals (the user typically uses an ATX power
supply for the drive power). A green LED at location CR6J1 indicates activity on the
ATA channel.
The development board also supports ‘ATA swap’ capability for both the parallel IDE
channel and the serial ATA channels. A device can be powered down by software and
the port can then be disabled, allowing removal and insertion of a new device. The
parallel IDE device should be powered from the power connector, J4J2, on the
development board to utilize the hot swap feature. This feature requires customer-
developed software support.
Note: Desktop hard drives must be powered using the external ATX power supply, not the
onboard power supply.
The Mobile Intel® GME965 Express Chipset includes Intel® Matrix Storage Technology,
providing greater performance and reliability through features such as Native
Command Queuing (NCQ) and RAID 0/1. For more information about Intel® Matrix
Storage Technology, refer to Intel’s website at:
3.4.2.6
USB Connectors
The ICH8-M provides a total of ten USB 2.0 ports. Three ports are routed to a triple-
stack USB connector at J3A1. Two ports are routed to a combination RJ-45/dual USB
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Theory of Operation
connector at J5A1. Four ports are routed to USB front panel headers at J6H3 and
J6H4. The last is routed to the PCI-Express* docking connector at J9C1.
There are Five UHCI Host Controllers and two EHCI Host Controllers. Each UHCI Host
Controller includes a root hub with two separate USB ports each, for a total of ten
legacy USB ports. The first EHCI Host Controller includes a root hub that supports up
to six USB 2.0 ports and the second EHCI Host Controller includes a root hub that
supports up to four USB 2.0 ports.
The connection to either the UHCI or EHCI controllers is dynamic and dependant on
the particular USB device. As such, all ports support High Speed, Full Speed, and Low
Speed (HS/FS/LS).
3.4.2.7
LPC Super I/O (SIO)/LPC Slot
An SMSC SIO1007-JV serves as the SIO on the development board. Shunting the
jumper at J7D1 to the 2-3 positions can disable the SIO by holding it in reset. This
allows other SIO solutions to be tested in the LPC slot at J8E1. A sideband header is
provided at J9G1 for this purpose. This sideband header also has signals for LPC
power management. Information on this header is on sheet 44 of the development
board schematics.
3.4.2.8
3.4.2.9
Serial, IrDA
The SMSC SIO incorporates a serial port, and IrDA (Infrared), as well as general
purpose IOs (GPIO). The Serial Port connector is provided at J2A2, and the IrDA
transceiver is located at U4A1. The IrDA transceiver on the development board
supports SIR (slow IR), FIR (Fast IR) and CIR (Consumer IR). The option to select
between these is supported through software.
BIOS Firmware Hub (FWH)
An 8-Mbit Flash device used on the development board to store system and video. The
reference designator location of the FWH device is U8G1. The BIOS can be upgraded
using an MS-DOS* based utility called FWHFlash and is addressable on the LPC bus off
of the ICH8-M. FWHFlash is available on request from your Intel representative.
3.4.2.10 SPI
The Serial Peripheral Interface on ICH8-M is used to support two compatible flash
devices at locations U7E1 and U6D2. By default, the SPI flash is used to store
configuration data for the LAN controller. Optionally it may be used for BIOS and AMT
firmware storage.
It is necessary to set certain strapping options to enable either a FWH-based or SPI-
based BIOS. Optionally, it is also possible to direct BIOS access to the PCI interface.
Table 7 describes these strapping options.
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Theory of Operation
Table 7. BIOS Location Strapping Options
ICH8-M Signal
GNT#0
SPI_CS1#
BIOS Location
SPI
0
1
1
1
0
1
PCI
LPC (Default)
Note: GNT#0 is configurable via jumper J8E2. Further details on its location can be found in
Section 4.3. SPI_CS1# is configurable via stuffing option R7U12. By default R7U12 is
not stuffed resulting in a SPI_CS1# strapping value of 1.
3.4.2.11 System Management Controller (SMC)/Keyboard Controller
The Hitachi* H8S/2104RV serves as both SMC and KBC for the development board.
The SMC/KBC controller supports two PS/2 ports, battery monitoring and charging,
EMA support, wake/runtime SCI events, and power sequencing control. The two PS/2
ports on the development board are for legacy keyboard and mouse. The keyboard
plugs into the bottom jack and the mouse plugs into the top jack at J1A1. Scan matrix
keyboards can be supported via an optional connector at J9E1.
3.4.2.12 Clocks
The development board uses a CK-505 clock synthesizer and DB800 clock buffer
compatible solution. The FSB frequency is determined from decoding the processor
BSEL[2:0] pin settings. This pin settings may be strapped using the jumpers at J1G2,
J1G5 and J1G8. Refer to Figure 7 and Table 15 for further information on these
jumpers.
3.4.2.13 Real Time Clock
An on-board battery at BT5H1 maintains power to the real time clock (RTC) when in a
mechanical off state. A CR2032 battery is installed on the development board.
Warning:Risk of explosion if the lithium battery is replaced by an incorrect type. Dispose of
used batteries according to the vendor's instructions.
3.4.2.14 Thermal Monitoring
The processor has a thermal diode for temperature monitoring. The SMC throttles the
processor if it becomes hot. If the temperature of the processor rises too high, the
SMC alternately blinks the CAPS lock and NUM lock LEDs on the development board,
and the development board shuts down.
A 3-pin fan header J3C1 is provided to support Tachometer output measurement for
GMCH. The development board supports PWM based speed control. As part of the
thermal measurement, the speed of the fan is varied based on the temperature
measurement.
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3.4.3
POST Code Debugger
A Port 80-83 Add-in card can be plugged into to the development board at the TPM
header (J9A1). This card decodes the LPC bus BIOS POST codes and displays them on
four 7-segment LED displays.
For AMI* BIOS POST codes, please visit: http://www.ami.com
3.5
Clock Generation
The development board uses a CK-505 and DB800 compatible solution. The FSB
frequency is determined from decoding the processor BSEL[2:0] pin settings.
The clock generator provides Processor, GMCH, ICH8-M, PCI, PCI Express*, SATA, and
USB reference clocks. Clocking for DDR2 is provided by the GMCH.
Table 8. Primary System Clocks
Clock Name
Speed
CPU
133 MHz @ 533 FSB Speed
166 MHz @ 667 FSB Speed
200 MHz @ 800 FSB Speed
DDR2
133 MHz @ 533 Memory Speed
166 MHz @ 667 Memory Speed
PCI Express* and DMI
100 MHz
100MHz
33MHz
48MHz
14MHz
SATA
PCI
USB
Super I/O
3.6
Power Management States
Table 9 and Table 10 lists the power management states that have been defined for
the baseboard.
The Manageability Engine (ME) operates at various power levels, called M-states. M0
is the highest power state, followed by M1 and M-off. The Manageability Engine
provides some of the functionality required to implement Intel® Active Management
Technology (iAMT) on the development board. Further information on iAMT can be
found here: http://www.intel.com/technology/manage/iamt/
Table 9. Power Management States
State
Description
G0/S0/C0
G0/S0/C2
Full on
STPCLK# signal active
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State
Description
Deep Sleep: DPSLP# signal active
G0/S0/C3
G0/S0/C4
G1/S3
G1/S4
G2/S5
G3
Deeper Sleep: DPRSLP# signal active
Suspend To RAM (all switched rails are turned off)
Suspend To Disk
Soft Off
Mechanical Off
Table 10. Power Management M-States
M-
State
Description
Main
System
Memory
Manageability
Subsystem2
Clocks
Subsystem1
M0
M1
Full on. All
manageability
functions
Powered
Off
Powered and
active
Powered
Powered
supported
Manageability
functions that only
require memory
are supported
Powered - Self
refresh.
Powered
Off
Only
BCLK pair
to MCH is
active3
M-off
Manageability is
disabled
Off
Off
Off
NOTES:
1.
2.
Memory subsystem is the memory and memory-related power supplies to the MCH.
Manageability Subsystem includes manageability functions in the chipset, SPI flash, and
LAN devices.
3.
In M1 the clock is powered, however only the BCLK pair to the MCH is active.
Everything besides the PLL in the clock chip is disabled and powered down.
Note: While in an M-state other than M-off, the traditional hardware definition of the S-State
as defined by the SLP signals is overridden by the ICH8M. This allows devices
controlled by SLP_S3# and SLP_S4#, such as system memory, to be available to the
Manageability system as needed. Even though the SLP signals may be driven
differently in M-States, the S-State information is retained in the ICH8M for transition
to M-off. S4_STATE# is the new signal to indicate S4 transition.
Table 11 provides a truth table of the SLP signals in various system states and M-
States. The ICH8M provides all of the SLP signals shown in the table below.
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Table 11. Sleep Signals and M-State Definition
Signal
SLP_S3#
High
SLP_S4#
SLP_S5#
High
S4_STATE#
High
SLP_M#
High
High
High
High
High
High
Low
Low
High
High
Low
Low
S0/M0
Low
Low
Low
Low
Low
Low
High
Low
Low
Low
High
High
Low
High
Low
Low
High
Low
Low
High
High
Low
Low
High
High
High
Low
Low
Low
High
Low
Low
Low
S3/M1
S4/M1
S5/M1
High
High
Low
S3/M-off
S4/M-off
S5/M-off
High
High
High
Low
S0 (Non-AMT)
S3 (Non-AMT)
S4 (Non-AMT)
S5 (Non-AMT)
3.7
Power Measurement Support
Power measurement resistors are provided on the development board to measure the
power of most subsystems. All power measurement resistors have a tolerance of 1%.
The value of these power measurement resistors are 0.002Ω by default. Power on a
particular subsystem is calculated using the following formula:
V 2
P =
R
R = value of the sense resistor (typically 0.002Ω)
V = the voltage difference measured across the sense resistor
Use of an oscilloscope or high precision digital multi-meter tool such as the Agilent*
34401A digital multi-meter is recommended. Meters such as this have 6½ digits of
accuracy and can provide a much greater accuracy in power measurement than a
common 3½ digit multi-meter.
Table 12 summarizes all the power measurement resistors located on the
development board. All resistors are 0.002 Ω unless otherwise noted. Reference
designators marked with an asterisk are “not stuffed” on the development board.
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Theory of Operation
Table 12. Development Board Voltage Rails
Component
/ Interface
Voltage
Plane
Supply
Rail
Reference
Designator
CPU VR
CPU VR
CPU VR
CPU VR
CPU VR
CPU
5V
+V5S
+VBAT
+V5S_IMVP6
+VDC_PHASE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+V1.05S_CPU
+VCCA_PROC
1.5S_VIN
R1B1
R2P12
Battery
Variable
Variable
Variable
1.05V
1.5V
6208_1_PHASE_LOUT
6208_2_PHASE_LOUT
6208_3_PHASE_LOUT
+V1.05S
R3D1
R2D1
R2D2
R3T2* and R3R7*
R3U1 (0.01Ω)
R5V3
CPU
+V1.5S
GMCH VR
GMCH VR
GMCH VR
GMCH VR
GMCH VR
GMCH VR
GMCH VR
GMCH
Battery
Battery
5 V
+VBATA
+VBATA
VGMCH_IN
R5F16
+V5S
+V5S_GVR
R3F12
Battery
3.3V
+VBAT
GVR_VBAT
R3V2
V3.3S_TVDAC_R2
+VBATA
+V3.3S_TVDAC
V1.25M_VIN
+V1.05M
R3E2 (0.01Ω)
R4V4
Battery
1.05 V
1.05V
+V1.05OUT
+V1.05S
R4F13 (0.01Ω)
R6E1
+VCC_GMCH
+VCCP_GMCH
GMCH
VCCP
+V1.05S
R5U26
(1.05V)
GMCH
GMCH
GMCH
GMCH
GMCH
GMCH
1.05V
1.25S
1.05V
1.25S
1.05V
+V1.05S
+V1.25S
+VCC_PEG
+VCC_PEG
+VCC_DMI
+VCC_DMI
+VCC_AXM
+VCC_GFX
R6T14
R6T13*
R6T11
R6E2*
R6R1
+V1.05S
+V1.25S
+V1.05M
V_GFX
(1.05S)
+VCC_GFXCORE
R3F8
GMCH
GMCH
GMCH
GMCH
GMCH
GMCH
GMCH
GMCH
GMCH
1.25V
1.25V
1.25V
1.25V
1.25V
1.25V
1.25V
1.25V
1.5V
+V1.25S
+V1.25M
+V1.25S
+V1.25S
+V1.25M
+V1.25M
+V1.25M
+V1.25S
+V1.5S
+V1.25S_PEGPLL
R5E3
+V1.25M_A_SM_CK
+V1.25S_DMI
R5P5
R6D5
R5U24
R4D6
R4R2
R4C27
R4F9
+V1.25S_MCH_PLL
V1.25M_MCH_PLL2
+V1.25M_A_SM
+V1.25M_AXD
+V1.25S_AXF
TVDAC_FB
R5U8
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Theory of Operation
Component
/ Interface
Voltage
Plane
Supply
Rail
Reference
Designator
GMCH
GMCH
GMCH
GMCH
GMCH
GMCH
GMCH
GMCH
PCI-E Gfx
PCI-E Gfx
PCI-E Gfx
PCI-E Gfx
ICH
1.8V
1.8V
1.8V
1.8V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
Battery
Battery
1.05V
1.05V
1.25V
1.5V
1.5V
1.5V
1.5V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
+V1.8
+V1.8_GMCH
+V1.8
+V1.8_GMCH
+V1.8_SM_CK
R5D1
R5D2
+V1.8_TXLVDS
+V1.8_DLVDS
R5U25
R5E5
+V1.8
+V3.3S
+V3.3S_HV
R5U2
+V3.3S
+V3.3S_SYNC
R5F9
+VCCA_TVDAC
+V3.3S
+V3.3S_DAC_BG
+V3.3S_PEG_BG
+V3.3S_PEG
R5U19 (0.03Ω)
R6E3
+V3.3S
R6C1
+V3.3
+V3.3S_PEG
R6P2*
R6N9
+VBATS
+VBAT_S4
+V1.05S
+V1.05S
+V1.25S
+V1.5S
+V12S_PEG
+V12S_PEG
R6N5*
R7F12
R6V11
R6G3
+V1.05S_ICH
ICH
+V1.05S_ICH_IO
+V1.25S_DMI_ICH
+V1.5S_PCIE_ICH
+V1.5S_SATA_ICH
+V1.5S_USB_ICH
+V1.5S_APLL_ICH
+V3.3S_DMI_ICH
+V3.3S_GLAN_ICH
+V3.3M_ICH
ICH
ICH
R6F13
R8G2
ICH
+V1.5S
ICH
+V1.5S
R8F7
ICH
+V1.5S
R8G2
ICH
+V3.3S
R6G4
ICH
+V3.3S
R6F2
ICH
+V3.3M
R7U3
ICH
+V3.3A
+V3.3A_ICH
R6V12
R8F4
ICH
+V3.3A
+V3.3A_USB_ICH
+V3.3S_IDE_ICH
+V3.3S_VCCPCORE_ICH
+V3.3M_VCCPAUX
+V3.3S_PCI_ICH
+V3.3S_SATA_ICH
ICH
+V3.3S
R8G1
ICH
+V3.3S
R8V14
R7F1
ICH
+V3.3M
ICH
+V3.3S
R8F5
ICH
+V3.3S
R8G7
ICH
+V3.3S_1.5S_HDA_IO
+V3.3S_1.5S_HDA_IO_IC
H
R7V4 (0.022Ω)
Memory
Memory
Memory
Battery
0.9 V
1.8V
+VBATA
+V0.9
1.8_VIN
+V0.9_R
R5N13
R4B13
R5C2
+V1.8
+V1.8_DIMM0
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Theory of Operation
Component
/ Interface
Voltage
Plane
Supply
Rail
Reference
Designator
Memory
Memory
Memory
LAN
1.8V
3.3V
3.3V
3.3V
1.8V
1V
+V1.8
+V3.3M
+V1.8_DIMM1
+V3.3M_DIMM0
+V3.3M_DIMM1
+V3.3M_LAN
+V1.8_LAN_M
+V1.0_LAN_M_IN
+V3.3S_PCI
R5B10
R4C1 (0.022Ω)
R4B26 (0.022Ω)
R6A23
+V3.3M
+V3.3M_LAN_SW
+V1.8_LAN
+V1.0_LAN_M
+V3.3S
LAN
R6M1
LAN
R6M3
PCI
3.3V
3.3V
3.3V
5V
R9D2
PCI
+V3.3
+V3.3_PCISLT3
+V3.3_PCISLT3
+V5S_PCI
R8C5*
PCI
+V3.3S_PCI
+V5S
R9D3
PCI
R9B1
PCI
5V
+V5
+V5_PCISLT3
+V5_PCISLT3
+V5_PCI
R8B3*
PCI
5V
+V5S_PCI
+V5
R9B2
PCI
5V
R9A11*
R8B1
PCI
12V
12V
12V
12V
12V
12V
+V12S
+V12S_PCI
PCI-E
PCI-E
PCI-E
PCI-E
PCI-E
+V12S
+V12S_PCIESLOT1
+V12S_PCIESLOT2
+V12S_PCIESLOT3
+V12S_PCIESLOT4
+V12S_PCIESLOT5
R7N11
R7C20
R8B2
+V12S
+V12S
+V12S
R8C7
R7N9
+V12S
PCI-E
PCI-E
3.3V
3.3V
3.3V
3.3V
3.3V
3.3 V
1.5 V
1.5 V
3.3 V
5V
+V3.3S
+V3.3S
+V3.3S_PCIESLOT1
+V3.3S_PCIESLOT2
+V3.3S_PCIESLOT3
+V3.3S_PCIESLOT4
+V3.3S_PCIESLOT5
+V3.3S_1.5S_HDA_IO
+V3.3S_1.5S_HDA_IO
+V3.3A_1.5A_HDA_IO
+V3.3A_1.5A_HDA_IO
+V5S_LVDS_BKLT
+VCC_LVDS_BKLT
+V3.3S_L
R7N10
R7R1
R7N5
R8D2
R7N8
R7W5
R7H6*
R8E8*
R8E7
PCI-E
+V3.3S
PCI-E
+V3.3S
PCI-E
+V3.3S
Audio
+V3.3S
Audio
+V1.5S
Audio
+V1.5A_HDA_IO
+V3.3A
Audio
Panel Bklt
Panel Bklt
Panel LVDS
Panel LVDS
Panel LVDS
+V5S
R6U8
R6F1
Battery
3.3V
5V
+VBAT
+V3.3S
+V5S
R6U13
R6U16*
R6F9
+V3.3S_L
3.3V
+V3.3S
+V3.3S_LVDS_DDC
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Theory of Operation
Component
/ Interface
Voltage
Plane
Supply
Rail
Reference
Designator
Panel LVDS
CK505
CK505
CK505
LPC
5V
3.3V
3.3V
0.9V
3.3V
5V
+V5S
+V3.3M_CK505
+V3.3S
+V3.3S_LVDS_DDC
VDD_CK505
R6U9*
R5G11
R7C10
R5V11
R8F2
+V3.3S_DB800
+VDDIO_CLK
+V3.3_LPCSLOT
+V5_LPCSLOT
V5_R1_TPM
IO_VOUT_D
+V3.3
LPC
+V5
R8E2
TPM
5V
+V5
R9M7
TPM
3.3V
3.3V
3.3V
5V
+V3.3S
V3.3S_R1_TPM
V3.3A_R1_TPM
+V3.3A_KBC
R9M8
TPM
+V3.3A
R9A8
SMC
+V3.3A
R8H1
PS2
+V5
+V5_PS2
R1A1
SIO
3.3V
3.3V
3.3V
5V
+V3.3S
+V3.3S_SIO
R7E1
IR
+V3.3S
+V3.3S_IR
R4M3
FWH
+V3.3S
+V3.3S_FWH
R8V17
R5W9
R7H7
USB
+V5A
+V5A_USBPWR_IN1
+V5A_USBPWR_IN2
+V5A_USBPWR_IN3
+V5S_PATA
USB
5V
+V5A
USB
5V
+V5A
R3B5
IDE
5V
+V5S
R5Y6
IDE
12V
3.3V
3.3V
5V
+V12S
+V12S_PATA
R3Y2
SPI
+V3.3M
+V3.3M_SPI
R6D8
SATA
SATA
SATA
SATA
SATA
SATA
System
System
System
System
System
System
System
System
+V3.3S
+V3.3S_SATA_P0
+V5S_SATA_P0
+V12S_SATA_P0
+V3.3S_SATA_P1
+V5S_SATA_P1
+V12S_SATA_P1
+VBS
R8Y2
+V5S
R8H6
12V
3.3V
5V
+V12S
R8W11
R7H9
+V3.3S
+V5S
R8H7
12V
Battery
Battery
Battery
Battery
3.3V
5V
+V12S
R8H2
+VCHGR_OUT
+V_BC_OUT
+VBATA
+VBATA
51120VBST2_LR
‘51120_+V5A_MBL_QL
+V1.25M_OUT
+V1.5S
R1W15 (0.02Ω)
R2H5 (0.005Ω)
R3H20
R3H5
+VBS
51120DRVH1_+VBATA
51120DRVH2_+VBATA_Q
+V3.3A_MBL
R3G3
+V5A_MBL
R3J1
1.25V
1.5V
+V1.25M
R4V2
+V1.5S_SW
R5G23
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Theory of Operation
Component
/ Interface
Voltage
Plane
Supply
Rail
Reference
Designator
System
System
System
System
System
System
ATX
ATX
ATX
ATX
ATX
+V5A
+V3.3A
+V5_ATX
+V3.3_ATX
+VBATA
R4J1*
R4W23*
R4Y1
+V12_ATX
-V12_ATX
-V12A
R4Y2
+V5SB_ATX
+VAC_BRCK_IN
+V5SB_ATXA
NEG_SENSE
R5H17
R1G8
+VAC_B
RCK
§
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Hardware Reference
4 Hardware Reference
This section provides reference information on the hardware, including locations of
development board components, connector pinout information and jumper settings.
4.1
Primary Features
Figure 2 shows the major components of the development board and Table 13 gives a
brief description of each component.
Figure 2. Development Board Component Locations
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Table 13. Development Board Component Location Legend
Reference
Designator
Function
BT5H1
J1C1
J1D1
J1F4
J1G1
J1G3
J1G4
J1G6
J1G7
J1H1
J2B3
J2F1
J2F2
J2G2
J3C1
J3J4
CMOS Battery
Reserved
XDP Connector
CPU FSB Sideband Signals
Reserved
Reserved
Reserved
AC Brick Connector
Battery Connector B
Battery Connector A
CPU Fan Connector
Reserved
Reserved
Reserved
GMCH Fan Connector
Reserved
J4J1
ATX Power Connector
PATA Power Connector
PCI Express Slot 1
PCI Express x16 Graphics Port
HDA Header for External HDMI Support
Reserved
J4J2
J6B1
J6B2
J6C2
J6C3
J6F1
J6H3
J6H4
J6H5
J6J1
LVDS Connector
USB Ports 7 and 8
USB Ports 2 and 4
Front Panel Header
Reserved
J7B1
J7D2
J7H1
J7H2
J7J3
PCI Express Slot 5
Reserved
SATA Port 2, Cable Connect
SATA Power Connector
SATA Port 1, Cable Connect
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Reference
Designator
Function
J7J4
J8A1
J8A2
J8B3
J8B4
J8D1
J8E1
J8G2
J8J1
PATA Connector
Reserved
Reserved
PCI Slot 3
PCI Express Slot 3
PCI Express Slot 4
LPC Slot
Extended Mobile Access Header
SATA Port 0, Direct Connect
Trusted Platform Module Header
PCI Express Docking Interface
Scan Matrix Key Board Connector
HDA Header for MDC Interposer
LPC Hot Docking Connector
HDA Header for MDC Interposer
LPC Side Band Header
PCI-Edge Connector
J9A1
J9C1
J9E1
J9E2
J9E3
J9E4
J9G1
S9B1
U2E1
U5E1
U6A1
U6D2
U6H2
U7C2
U7E1
U7E6
U7F1
U8G1
U9G2
Intel® CoreTM 2 Duo processor
Mobile Intel® GME965 Express Graphics Memory Controller Hub
82566MM Gigabit Ethernet Phy
16Mb SPI Flash
CK505 Clock Synthesizer
DB800 Clock Buffer
16Mb SPI Flash
Super I/O
Intel® I/O Controller Hub 8-M (ICH8-M)
Firmware Hub
H8S/2104 KSC
4.2
Back Panel Connectors
This section describes the panel connectors on the development board. Figure 3 shows
these connectors.
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Figure 3. Back Panel Connector Locations
n
o
p
q
r
s
t
u
Table 14. Back Panel Connector Definitions
Item
Description
Ref
Des
Item
Description
Ref Des
1
2
3
4
PS/2 Mouse
TV-Out D-Connector
Serial Port
J1A1
J2A1
J2A2
J3A1
5
6
7
8
RJ-45 LAN
PS/2 Keyboard
VGA
J5A1
J1A1
J2A2
J5A1
3 USB Ports
2 USB Ports
4.2.1
TV-Out D-Connector
The TV-Out D-connector supplies the necessary signals to support the Composite, S-
Video, and Component TV standards. Component video (Figure 4) and Composite
video (Figure 5) is connected to the development board using D-connector to
Component Video cable (with three RCA receptacles at one end and D-mating
connector on other end). S-video (Figure 6) is connected to development board using
D-connector to S-Video cable (with 4-pin DIN connector one end and D-mating
connector on other end).
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Hardware Reference
Figure 4. D-Connector to Component Video Cable
Figure 5. D-Connector to Composite Video Cable
Figure 6. D-Connector to S-Video Cable
4.3
Configuration Settings
Note: Do not move jumpers with the power on. Always turn off the power and unplug the
power cord from the computer before changing jumper settings. Failure to do so may
cause damage to the development board.
Figure 7 shows the location of the configuration jumpers and switches.
Table 15 summarizes the jumpers and switches and gives their default and optional
settings.
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The unsupported jumpers must remain in their default position or the operation of the
development board is unpredictable. The development board is shipped with the
jumpers and switches shunted in the default locations.
Figure 7. Configuration Jumper and Switch Locations
Table 15. Supported Configuration Jumper/Switch Settings
Reference
Designator
Function
BSEL0
Default Setting
Optional Setting
J1G2
J1G5
J1G8
J1J1
J1J2
J2B2
2-3: Tied to logic high
Empty: Tied to logic low
1-2: Processor BSEL Select
1-2: Processor BSEL Select
1-2: Processor BSEL Select
BSEL1
2-3: Tied to logic low
Empty: Tied to logic high
BSEL2
2-3: Tied to logic low
Empty: Tied to logic high
Reserved
Reserved
CPU VID Code
OUT
Do not alter jumper setting
OUT
Do not alter jumper setting
OUT
15-16: Activate Override
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Reference
Designator
Function
Default Setting
Optional Setting
Override
For each VID signal
IN: Tied to logic low
OUT: Tied to logic high
13 and 14 = VID0
11 and 12 = VID1
9 and 10 = VID2
7 and 8 = VID3
5 and 6 = VID4
3 and 4 = VID5
1 and 2 = VID6
J2F3
J2G1
Reserved
OUT
Do not alter jumper setting
GFX VID Code
Override
OUT
1-2: Activate Override
For each VID signal
IN: Tied to logic low
OUT: Tied to logic high
3 and 4 = VID0
5 and 6 = VID1
7 and 8 = VID2
9 and 10 = VID3
11 and 12 = VID4
13 and 14 = VR_ENABLE
15 and 16 = No Function
J2H1
J2H2
J2H3
J2J1
J2J2
J2J3
J2J4
J2J5
J2J6
J3B2
Force
Shutdown
OUT: Normal Operation
IN: Force the board to shutdown
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OUT
Do not alter jumper setting
OUT
Do not alter jumper setting
OUT
Do not alter jumper setting
OUT
Do not alter jumper setting
OUT
Do not alter jumper setting
OUT
Do not alter jumper setting
OUT
Do not alter jumper setting
OUT
Do not alter jumper setting
Thermal
Diode
Connection
1-2 and 3-4: Normal operation
OUT: Disconnect CPU thermal
diode from thermal sensor
IN: Latch the power on
J3G1
Power On
Latch
OUT: Normal operation
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Reference
Designator
Function
Reserved
Reserved
Reserved
Default Setting
Optional Setting
J3J1
J3J2
J3J3
OUT
Do not alter jumper setting
OUT
Do not alter jumper setting
OUT
Do not alter jumper setting
J4H1
J5H1
ME G3 to M1
OUT: Normal operation
IN: Jump power state from G3 to M1
Reserved
OUT
Do not alter jumper setting
J5H2
J6G1
Clear CMOS
Reserved
OUT: Normal operation
IN: Clear CMOS
OUT
Do not alter jumper setting
J6H2
J7D1
J7J1
J7J2
Reserved
IN
Do not alter jumper setting
Super IO
Reset
1-2: Normal operation
2-3: Hold Super IO in reset
Reserved
OUT
Do not alter jumper setting
SATA Power
Enable
IN: (SATA Port-1) Hot
Plug/Removal Supported
OUT: (SATA Port-1) Hot
Plug/Removal not Supported
(SATA Port -2) Device not
connected through cable
(SATA Port -2) Device
connected through cable
J8B1
J8B2
J8E2
Remote H8
Programming
1-2: Normal operation
2-3: Program H8
Remote H8
Programming
1-2: Normal operation
2-3: Program H8
Boot BIOS
Location
OUT: Normal operation.
Boot through LPC (If
R7U12 is NO STUFF)
IN: PCI or SPI (Depends on
R7U12 stuffing)
J8F1
J8F2
J8G1
Reserved
OUT
Do not alter jumper setting
BIOS
Recovery
OUT: Normal operation IN: BIOS recovery
Reserved
OUT
Do not alter jumper setting
J9F1
J9F2
J9G2
H8 Reset
1-2: Normal operation
2-3: Hold H8 in reset
2-3: LAN Disable
LAN Enable
1-2: LAN Enable
Boot Block
IN: Normal operation
OUT: Program H8
Programming
J9H1
J9H2
Virtual
Docking
OUT: Normal operation
IN: Virtual docking enabled
1Hz clock and
OUT: Normal operation, clock
IN: Clock disabled, enable H8
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Reference
Designator
Function
Default Setting
Optional Setting
H8
Programming
NMI
enabled
programming
J9H3
J9H4
J9H5
KBC Disable
OUT: Normal operation,
Keyboard Controller
enabled
IN: Keyboard Controller
disabled
SMC MD0
IN: Normal operation.
External programming
allowed
OUT: No external programming
OUT: SATA device not present
SATA Device
Detect
IN: SATA device present
J9H6
J9H7
SMC MD2
SMC MD1
OUT: Normal operation
IN: Advanced single chip mode
OUT: No external programming
IN: Normal operation.
External programming
allowed
J9H8
J9H9
Lid Position
OUT: Lid Open
IN: Lid Closed
Virtual
OUT: Normal operation
IN: Virtual battery mode
Battery
SW1C1
SW1C2
SW8E1
SW9H1
Power Button
Reset Button
Net Detect
N/A
N/A
N/A
N/A
N/A
N/A
Virtual
1-2: Normal operation
2-3: Virtual docking enabled
Docking
SW9H2
SW9J1
Virtual
Battery
1-2: Normal operation
OUT: Lid Open
2-3: Virtual battery mode
IN: Lid Closed
Lid Position
Note: A jumper consists of two or more pins mounted on the motherboard. When a jumper
cap is placed over two pins, it is designated as IN. When there are more than two
pins on the jumper, the pins to be shorted are indicated as 1-2 (to short pin 1 to pin
2), or 2-3 (to short pin 2 to pin 3). When no jumper cap is to be placed on the
jumper, it is designated as OUT. When a switch is designated as 1-2 the switch slide
is positioned such that pins 1 and 2 are shorted together.
4.4
Power On and Reset Buttons
The development board has two push buttons that implement POWER and RESET
functionality. The POWER button releases power to the entire development board,
causing the board to boot. The RESET button will force all systems to warm reset. The
two buttons are located near the CPU close to the edge of the development board. The
POWER button is located at SW1C1 and the RESET button is located at SW1C2.
Note: If the development board is powered from an external ATX power supply (not a power
brick), the Power button may need to be pressed twice to turn on the system.
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4.5
LEDs
The development board has a number of LEDs. These LEDs provide status for various
functions on the development board. Figure 8 indicates the location of the LEDs and
Table 16 describes their function.
Figure 8. LED Locations
Table 16. LED Functions
Function
Reference
Designator
Keyboard Number Lock
Keyboard Scroll Lock
Keyboard Caps Lock
System State S0
System State S3
System State S4
System State S5
ATA Activity
CR9G1
CR9G2
CR9G3
CR5H5
CR3G2
CR5H3
CR5H4
CR6J1
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Function
Reference
Designator
VID 0
VID 1
VID 2
VID 3
VID 4
VID 5
VID 6
M0/M1
CR1B1
CR1B2
CR1B3
CR1B4
CR1B5
CR1B6
CR1B7
CR4H1
CR5J1
CR8G1
System Power Good
Reserved
4.6
Other Headers, Slots and Sockets
4.6.1
H8 Programming Headers
The microcontroller firmware for system management/keyboard/mouse control can be
upgraded in two ways. The user can either use a special DOS* utility known as
KSCFlash (in-circuit) or use an external computer connected (remote) to the system
via the serial port on the development board. KSCFlash is available on request from
your Intel representative.
If the user chooses to use an external computer connected to the system via the serial
port, there are four jumpers that must be set correctly first. Please refer to Table 15
for a summary of these jumpers and refer to Figure 7 for the location of each jumper.
Required Hardware: one Null Modem Cable and a Host Unit with a serial COM port
(System used to flash the development board)
Here is the sequence of events necessary to program the H8 via the serial port.
1. Extract all files (keep them in the same folder) to a single directory of your
choice on the host machine or on a floppy disk.
2. Connect a NULL modem cable to the serial ports of each platform (host and
unit to be flashed).
3. With the development board powered off, move the following jumpers to the
programming stuffing option.
a. J9G2 (remove) (default: 1-2), Sets SMC_INIT_CLK high.
b. J8B1 (2-3) (default: 1-2), link the Host Unit to on-board H8.
c. J8B2 (2-3) (default: 1-2), link the Host Unit to on-board H8.
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d. J9H2 (1-2) (default: 1-X), disable 1 Hz Clock.
4. Attach an ATX power supply or AC to DC adapter to the system and power up
the development board.
5. From the directory where you extracted the files, run the “kscflash ksc.bin /
remote” command to program the H8 via the serial port.
6. Follow the instructions the flash utility provides.
7. With the development board powered off, return the jumpers to their default
setting.
Note: Make sure the development board is not powered on, and the power supply is
disconnected before moving any of the jumpers.
4.6.2
Expansion Slots and Sockets
Following is a list of the slots and sockets available for attaching additional devices.
Refer to Figure 2 for locations.
Table 17. Expansion Slots and Sockets
Reference
Designator
Slot/Socket Description
Detail
U2E1
J5P1
478 Pin Grid Array (Micro-FCPGA) Processor Socket
DDR2 - Channel 0 - SODIMM slot
DDR2 - Channel 1 - SODIMM slot
LVDS Graphics Interface
PCI Express* (x16)
J5N1
J8F1
J6B2
Table 18
Table 19
Table 20
Table 21
Table 21
Table 21
J6B2
ADD2 Slot
J6B2
Media Expansion Card Slot
PCI Express* (x1) Slot 3
PCI Express* (x1) Slot 5
PCI Express* (x1) Slot 1
PCI 2.3 Slot 3
J8B4
J7B1
J6B1
J8B3
J7J4
IDE Interface Connector
SATA ‘Direct Connect’ Connector
SATA ‘Cable Connect’ Connector
SATA Desk Top Power Connector
Intel Firmware Hub Socket
Battery
Table 22
Table 23
Table 24
Table 25
J8J1
J7J3, J7H1
J6H3
U8G1
BT5H1
J2B3, J2C1
J2F1
Fan Connectors
Table 26
Table 27
Fan Connector
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Reference
Designator
Slot/Socket Description
Detail
J6H5
Front Panel Header
USB Header
Table 28
Table 29
J6H3, J6H4
4.6.2.1
478 Pin Grid Array (Micro-FCPGA) Socket
The pin locking mechanism on the CPU socket is released by rotating the screw on the
socket 180 degrees counter-clockwise. CPU pins are keyed so as to only allow
insertion in one orientation. DO NOT FORCE CPU into socket. Once the CPU is properly
seated into the socket, turn the screw 180 degrees clock-wise to secure the CPU in the
socket. Note that the slot on the screw aligns with the lock and unlock legend on the
case of the CPU socket.
Caution: Please refer to the heatsink installation instructions in Appendix A prior to inserting
the heatsink as the CPU and socket can be easily damaged.
Caution: Only insert Intel® CoreTM 2 Duo Mobile processors that are intended for operation
with the Mobile Intel® 965 Express Chipset Family into the development board.
These processors have a pinout known as Socket-P. Earlier Intel® CoreTM 2 Duo
Mobile processors that have a pinout known as Socket-M are mechanically
compatible with the processor socket but not electrically compatible. Insertion of
these processors will cause damage to the processor and the development board.
4.6.2.2
PCI Express* (x16)
The development board has one x16 lane PCI Express* Graphics slot and supports
either x1, x2, x4, x8 or x16 modes. The slot is wired “lane reversed” which connects
the Mobile Intel® GME965 Express Chipset lanes 0 through 15 to lanes 15 through 0
on the slot. The Mobile Intel® GME965 Express Chipset will internally un-reverse this
wiring since its CFG9 power-on strap is tied low.
Table 18. PCI Express* (x16) Pinout (J6B2)
Pin
A1
Description
Pin
B1
Description
+12V
PRSNT1#
+12V
A2
A3
A4
A5
A6
A7
A8
A9
A10
B2
B3
B4
B5
B6
B7
B8
B9
B10
+12V
+12V
+12V
GND
GND
JTAG2 (TCK)
JTAG3 (TDI)
JTAG4 (TDO)
JTAG5 (TMS)
+3.3V
SMCLK
SMDAT
GND
+3.3V
JTAG1 (TRST#)
+3.3VAUX
+3.3V
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Pin
Description
Pin
Description
A11
PERST#
B11
WAKE#
Key
A12
A13
A14
A15
A16
A17
A18
GND
B12
B13
B14
B15
B16
B17
B18
RSVD
REFCLK+
REFCLK-
GND
GND
LANE 0 (T+)
LANE 0 (T-)
GND
LANE 0 (R+)
LANE 0 (R-)
GND
PRSNT2*
GND
End of x1 Connector
LANE 1 (T+)
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
RSVD
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
GND
LANE 1 (T-)
GND
LANE 1 (R+)
LANE 1 (R-)
GND
GND
LANE 2 (T+)
LANE 2 (T-)
GND
GND
LANE 2 (R+)
LANE 2 (R-)
GND
GND
LANE 3 (T+)
LANE 3 (T-)
GND
GND
LANE 3 (R+)
LANE 3 (R-)
GND
RSVD
PRSNT2#
GND
RSVD
End of x4 Connector
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
RSVD
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
LANE 4 (T+)
GND
LANE 4 (T-)
GND
LANE 4 (R+)
LANE 4 (R-)
GND
GND
LANE 5 (T+)
LANE 5 (T-)
GND
GND
LANE 5 (R+)
LANE 5 (R-)
GND
GND
LANE 6 (T+)
LANE 6 (T-)
GND
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Pin
Description
Pin
Description
GND
A43
A44
A45
A46
A47
A48
A49
LANE 6 (R+)
LANE 6 (R-)
GND
B43
B44
B45
B46
B47
B48
B49
GND
LANE 7 (T+)
LANE 7 (T-)
GND
GND
LANE 7 (R+)
LANE 7 (R-)
GND
PRSNT#2
GND
End of x8 Connector
LANE 8 (T+)
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
RSVD
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
GND
LANE 8 (T-)
GND
LANE 8 (R+)
LANE 8 (R-)
GND
GND
LANE 9 (T+)
LANE 9 (T-)
GND
GND
LANE 9 (R+)
LANE 9 (R-)
GND
GND
LANE 10 (T+)
LANE 10 (T-)
GND
GND
LANE 10 (R+)
LANE 10 (R-)
GND
GND
LANE 11 (T+)
LANE 11 (T-)
GND
GND
LANE 11 (R+)
LANE 11 (R-)
GND
GND
LANE 12 (T+)
LANE 12 (T-)
GND
GND
LANE 12 (R+)
LANE 12 (R-)
GND
GND
LANE 13 (T+)
LANE 13 (T-)
GND
GND
LANE 13 (R+)
LANE 13 (R-)
GND
GND
LANE 14 (T+)
LANE 14 (T-)
GND
GND
LANE 14 (R+)
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Pin
Description
Pin
Description
GND
A77
A78
A79
A80
A81
A82
LANE 14 (R-)
GND
B77
B78
B79
B80
B81
B82
LANE 15 (T+)
LANE 15 (T-)
GND
GND
LANE 15 (R+)
LANE 15 (R-)
GND
PRST2#
RSVD
4.6.2.3
ADD2/Media Expansion Card (MEC) Slot
When not being used for PCI Express*, the x16 slot can be used for Serial Digital
Video Out (SDVO). An ADD2N card can be inserted into the SDVO slot to enable the
use of third party vendor transmitters to output video formats such as DVI, TV, LVDS
and HDMI. Table 19 describes the ADD2N interface pin-out.
The SDVO interface will also support a Media Expansion Card (MEC), which provide TV
Capture over the PCI Express* x1 port in addition to the standard ADD2 card video
out capabilities. Table 20 describes the MEC interface pin-out.
Table 19. ADD2 Slot (J6B2)
Pin
A1
Description
N/C
Pin
B1
Description
12 V
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
12 V
12 V
GND
N/C
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
12 V
Reserved
GND
N/C
TDI
N/C
TDO
N/C
GND
3.3 V
N/C
3.3 V
3.3 V
RESET
N/C
N/C
Key
A12
A13
A14
A15
A16
A17
GND
B12
B13
B14
B15
B16
B17
Reserved
GND
N/C
N/C
SDVOB_Red+
SDVOB_Red-
GND
GND
SDVO_TVClkIn+
SDVO_TVClkIn-
SDVO_CtrlClk
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Pin
Description
Pin
Description
A18
GND
B18
GND
End of x1 Connector
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
Reserved
GND
B19
B20
SDVO_Green+
SDVO_Green-
GND
SDVOB_Int+
SDVOB_Int-
GND
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
GND
SDVOB_Blue+
SDVOB_Blue-
GND
GND
SDVO_Stall+
SDVO_Stall-
GND
GND
SDVOB_Clk+
SDVOB_Clk-
GND
GND
N/C
N/C
Reserved
SDVO_CtrlData
GND
GND
Reserved
End of x4 Connector
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
Reserved
GND
B33
B34
B35
B36
B37
B38
SDVOC_Red+
SDVOC_Red-
GND
N/C
N/C
GND
GND
SDVOC_Green+
SDVOC_Green-
GND
GND
SDVOC_Int+
SDVOC_Int-
GND
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
GND
SDVOC_Blue+
SDVOC_Blue-
GND
GND
N/C
N/C
GND
GND
SDVOC_Clk+
SDVOC_Clk-
GND
GND
N/C
N/C
N/C
GND
GND
End of x8 Connector
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Pin
Description
Reserved
Pin
Description
N/C
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
GND
N/C
N/C
GND
GND
N/C
N/C
GND
GND
N/C
N/C
GND
GND
N/C
N/C
GND
GND
N/C
N/C
GND
GND
N/C
N/C
GND
GND
N/C
N/C
GND
GND
N/C
N/C
GND
GND
N/C
N/C
GND
GND
N/C
N/C
GND
GND
N/C
N/C
GND
GND
N/C
N/C
GND
GND
N/C
N/C
GND
GND
N/C
N/C
GND
GND
N/C
N/C
GND
N/C
N/C
GND
Reserved
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Table 20. MEC Slot (J6B2)
Pin
A1
Description
Pin
B1
Description
12 V
N/C
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
12 V
12 V
GND
N/C
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
12 V
Reserved
GND
N/C
N/C
N/C
N/C
GND
N/C
3.3 V
N/C
3.3 V
3.3 V
RESET
+3.3VA
WAKE#
Key
A12
A13
A14
A15
A16
A17
A18
GND
B12
B13
B14
B15
B16
B17
B18
Reserved
GND
REFCLK+
REFCLK-
GND
Lane 0 (T+)
Lane 0 (T-)
GND
Lane 0 (R+)
Lane 0 (R-)
GND
SDVO_CtrlClk
GND
End of x1 Connector
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
Reserved
GND
N/C
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
N/C
N/C
GND
N/C
GND
GND
GND
N/C
N/C
N/C
GND
N/C
GND
GND
GND
N/C
N/C
N/C
GND
N/C
Reserved
SDVOB_CtrlData
GND
GND
Reserved
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Pin
Description
Pin
Description
End of x4 Connector
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
Reserved
GND
N/C
B33
N/C
N/C
B34
B35
GND
GND
N/C
N/C
B36
GND
GND
N/C
B37
B38
N/C
B39
GND
GND
N/C
N/C
B40
GND
GND
N/C
B41
B42
N/C
B43
GND
GND
N/C
N/C
B44
GND
GND
N/C
B45
B46
N/C
B47
GND
MEC_Enable
GND
N/C
B48
GND
B49
End of x8 Connector
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
Reserved
GND
N/C
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
SDVOC_CLK+
SDVOC_CLK-
GND
N/C
GND
GND
GND
N/C
SDVOC_Blue+
SDVOC_Blue-
GND
N/C
GND
GND
GND
SDVOC_Green+
SDVOC_Green-
GND
SDVOC_Int+
SDVOC_Int-
GND
B60
B61
B62
B63
B64
B65
GND
SDVOC_Red+
SDVOC_Red-
GND
GND
N/C
N/C
GND
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Pin
Description
GND
Pin
Description
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
SDVOB_Clk+
SDVOB_Clk-
GND
GND
N/C
N/C
GND
GND
SDVOB_Blue+
SDVOB_Blue-
GND
GND
SDVO_Stall+
SDVO_Stall-
GND
GND
SDVOB_Green+
SDVOB_Green-
GND
GND
SDVOB_Int+
SDVOB_Int-
GND
GND
SDVOB_Red+
SDVOB_Red-
GND
GND
SDVO_TVClkIn+
SDVO_TVClkIn-
GND
N/C
Reserved
4.6.2.4
PCI Express* (x1)
The three PCI Express* x1 connectors allow the use of any industry standard PCI
Express* device. The pin configuration of the connectors is given below.
Table 21. PCI Express* (x1) Pinout (J6B1, J7B1, J8B4)
Pin
A1
Description
Pin
B1
Description
+12V
PRSNT1#
+12V
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
+12V
+12V
+12V
GND
GND
JTAG2 (TCK)
JTAG3 (TDI)
JTAG4 (TDO)
JTAG5 (TMS)
+3.3V
SMCLK
SMDAT
GND
+3.3V
JTAG1 (TRST#)
+3.3VAUX
WAKE#
+3.3V
PERST#
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Pin
Description
Pin
Key
Description
A12
A13
A14
A15
A16
A17
A18
GND
B12
B13
B14
B15
B16
B17
B18
RSVD
REFCLK+
REFCLK-
GND
GND
LANE 0 (T+)
LANE 0 (T-)
GND
LANE 0 (R+)
LANE 0 (R-)
GND
PRSNT2*
GND
4.6.2.5
IDE Connector
The IDE interface can support up to two devices, a master and a slave. Ensure that
the jumpers on the devices are properly selected for the given configuration. Mobile
devices with an IDE interface will require an adapter to connect to this port.
Table 22. IDE Connector
Pin
Signal
Reset
Pin
Signal
Ground
1
2
3
Data 7
4
Data 8
5
Data 6
6
Data 9
7
Data 5
8
Data 10
Data 11
Data 12
Data 13
Data 14
Data 15
Key
9
Data 4
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Data 3
Data 2
Data 1
Data 0
Ground
DDRQ
Ground
I/O Write
I/O Read
I/O HRDY
DDACK
IRQ
Ground
Ground
Cable Select
Ground
No Connect
DMA66_Detect
Address 2
Chip Select 3
Ground
Address 1
Address 0
Chip Select 1
Activity
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4.6.2.6
SATA Pinout
Up to three SATA devices may be supported by the SATA connectors on the
development board. Table 23 describes the SATA ‘Direct Connect’ connector and Table
24 describes the SATA ‘Cable Connect’ connectors.
Table 23. SATA Port 0 ‘Direct Connect’ Connector Pinout (J8J1)
Pin
Signal
2
3
5
6
TX
TX#
RX#
RX
8, 9, 10
+3.3V
+5V
14, 15, 16
20, 21, 22
1, 4, 7, 11
12, 13, 17, 19
+12V
GND
GND
Table 24. SATA Ports 1 and 2 ‘Cable Connect’ Connector Pinout (J7J3, J7H1)
Pin
Signal
2
3
5
6
TX
TX#
RX#
RX
1, 4, 7
GND
Table 25. SATA Power Connection (J7H2)
Pin
Signal
+3.3V
1, 3
3, 4
5
+5V
+12V
GND
6, 7, 8, 9, 10
4.6.2.7
Fan Connectors
The development board implements three fan connectors. The connectors at J2B3 and
J2C1 have a speed controlled power supply. The connector at J2F1 has a fixed power
supply.
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Connector J2B3 is used to power the CPU fan. Connectors J2C1 and J2F1 are not used
in the default operation of the development board.
Table 26. Fan Connectors (J2B3, J2C1)
Pin
Signal
1
2
3
+V
TACH
GND
Table 27. Fan Connector (J2F1)
Pin
Signal
1
2
3
+5V
NC
GND
4.6.2.8
Front Panel Header (J6H5)
The front panel header allows connection of the LEDs and switches typically found in
an ATX chassis to the development board.
Table 28. Front Panel Connector
Pin
Signal
FRONT1
Definition
1
2
3
5 volt front panel LED supply
5 volt front panel LED supply
FRONT2
ATA_LED#
Indicates PATA or SATA activity –
Active Low
4
GND
Ground
5
GND
Ground
6
PWR_CONN_D
RST_PUSH#_D
GND
System Power – Active Low
System Reset – Active Low
Ground
7
8
9
+V5
5 volt supply
No Connect
No Connect
Ground
10
11
12
13
14
15
N/C
N/C
GND
GND
Ground
N/C
No Connect
Reserved
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16
+V5
5 volt supply
4.6.2.9
USB Headers (J6H3, J6H4)
The USB headers implement 4 additional USB ports on the development board.
Connector J6H3 implements ports 7 and 8 and connector J6H4 implements ports 2
and 4.
Table 29. USB Headers
Pin
Signal
Definition
1
+V5A_L_USBPWR
+V5A_L_USBPWR
USB_PNx
USB_PNy
USB_PPx
USB_PPy
GND
5 volt – Always On
5 volt – Always On
Data- (USB Port x)
Data- (USB Port y)
Data+ (USB Port x)
Data+ (USB Port y)
Ground
2
3
4
5
6
7
8
GND
Ground
9
N/C
No Connect
10
N/C
No Connect
§
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Appendix A. Heatsink Installation
Instructions
It is necessary for the Intel® CoreTM 2 Duo processor to have a thermal solution
attached to it in order to keep it within its operating temperature.
Caution: An ESD wrist strap must be used when handling the board and installing the
heatsink/fan assembly.
A heatsink is included in the kit. To install the heatsink:
1. Remove the heatsink from its package and separate the fan heatsink portion
from the heatsink backplate.
Figure 9. Heatsink and Backplate
2. Examine the base of the heatsink, where contact with the processor die is
made. This surface should be clean of all materials and greases. Wipe the
bottom surface clean with isopropyl alcohol.
3. Place the backplate on the underside of the development board so that the
pins protrude through the holes in the development board around the
processor.
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Figure 10. Backplate Pins
4. Clean the die of the processor with isopropyl alcohol before the heatsink is
attached to the processor. This ensures that the surface of the die is clean.
5. Remove the tube of thermal grease from the package and use it to coat the
exposed die of the CPU with the thermal grease.
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Figure 11. Applying the Thermal Grease
6. Pick up the heatsink and squeeze the activation arm until it comes in contact
with the base plate that is attached to the heatsink base. This will cause the
springs on the heatsink attachment mechanism to compress.
Figure 12. Squeezing Activation Arm
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7. While keeping the activation arm compressed, place the heatsink over the pins
of the heatsink backplate. Lower the heatsink until the lugs have inserted into
the base of the heatsink. Slide the heatsink over the lugs on the backplate
pins so that the base is directly over the processor die and the pins on the
backplate have travelled the entire length of the channel in the heatsink base.
Slowly let go of the activation arm until the base of the heatsink makes
contact with the processor die. The heatsink base should be flat on top of the
processor die.
Figure 13. Installing the Heatsink
8. Plug the fan connector for the heatsink onto the CPU fan header (J2B3) on the
motherboard.
Note: The CPU fan header (J2B3) is a 3-pin connector. This is a change from the Mobile
Intel® 945GM Express Chipset Development Kit which has a 2-pin CPU fan header. As
a result, it is not possible to use the heatsink from the Intel® 945GM Express Chipset
Development Kit even though the heatsink and backplate are mechanically
compatible.
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Figure 14. Plugging in the Fan
Figure 15. Completed Assembly
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