EM78P447N
8-Bit Microcontroller
with OTP ROM
Product
Specification
DOC. VERSION 1.1
ELAN MICROELECTRONICS CORP.
March 2005
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Contents
Contents
1
2
3
4
GENERAL DESCRIPTION ......................................................................................... 1
FEATURES ................................................................................................................. 1
PIN ASSIGNMENT ..................................................................................................... 3
FUNCTION DESCRIPTION........................................................................................ 6
4.1 Operational Registers......................................................................................... 7
4.1.1 R0 (Indirect Addressing Register) .......................................................................7
4.1.2 R1 (Time Clock /Counter)....................................................................................7
4.1.3 R2 (Program Counter) & Stack ...........................................................................7
4.1.4 R3 (Status Register)..........................................................................................10
4.1.5 R4 (RAM Select Register).................................................................................10
4.1.6 R5~R7 (Port 5 ~ Port7) .....................................................................................10
4.1.7 R8~R1F and R20~R3E (General Purpose Register)........................................10
4.1.8 R3F (Interrupt Status Register) .........................................................................11
4.2 Special Purpose Registers ............................................................................... 11
4.2.1 A (Accumulator).................................................................................................11
4.2.2 CONT (Control Register)...................................................................................11
4.2.3 IOC5 ~ IOC7 (I/O Port Control Register) ..........................................................12
4.2.4 IOCB (Wake-up Control Register for Port6)......................................................12
4.2.5 IOCE (WDT Control Register)...........................................................................13
4.2.6 IOCF (Interrupt Mask Register).........................................................................14
4.3 TCC/WDT & Prescaler ..................................................................................... 15
4.4 I/O Ports ........................................................................................................... 16
4.5 RESET and Wake-up ....................................................................................... 17
4.5.1 RESET ..............................................................................................................17
4.5.2 The Status of RST, T, and P of STATUS Register.............................................21
4.6 Interrupt............................................................................................................ 22
4.7 Oscillator .......................................................................................................... 23
4.7.1 Oscillator Modes................................................................................................23
4.7.2 Crystal Oscillator/Ceramic Resonators(XTAL)..................................................24
4.7.3 External RC Oscillator Mode.............................................................................25
4.8 CODE Option Register..................................................................................... 26
4.8.1 Code Option Register (Word 0).........................................................................26
4.8.2 Customer ID Register (Word 1).........................................................................28
4.9 Power On Considerations ................................................................................ 28
4.10 External Power On Reset Circuit...................................................................... 28
4.11 Residue-Voltage Protection.............................................................................. 29
4.12 Instruction Set .................................................................................................. 30
4.13 Timing Diagram ................................................................................................ 33
Product Specification (V1.1) 03.30.2005
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Contents
5
6
ABSOLUTE MAXIMUM RATINGS........................................................................... 34
DC ELECTRICAL CHARACTERISTICS.................................................................. 34
6.1 DC Electrical Characteristic.............................................................................. 34
6.2 AC Electrical Characteristic.............................................................................. 35
6.3 Device Characteristic ....................................................................................... 36
APPENDIX
A
B
Package Types......................................................................................................... 50
Package Information............................................................................................... 50
Specification Revision History
Doc. Version
Revision Description
Initial version
Date
1.0
1.1
10/29/2004
03/30/2005
Add four kinds of package type
iv •
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EM78P447N
8-Bit Microcontroller with OTP ROM
1 GENERAL DESCRIPTION
EM78P447N is an 8-bit microprocessor with low-power and high-speed CMOS
technology and high noise immunity. It is equipped with 4K*13-bits Electrical One Time
Programmable Read Only Memory (OTP-ROM). It provides three PROTECTION bits
to prevent user’s code in the OTP memory from being intruded. Seven OPTION bits
are also available to meet user’s requirements.
With its OTP-ROM feature, the EM78P447N is able to offer a convenient way of
developing and verifying user’s programs. Moreover, user can take advantage of
ELAN Writer to easily program his development code.
2 FEATURES
ꢀ
Operating voltage range: 2.5V~5.5V.
ꢀ
ꢀ
Operating temperature range: -40°C~85°C.
Operating frequency rang( base on 2 clocks)
• Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.5V.
• RC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.5V.
ꢀ
Low power consumption:
• Less then 2.2 mA at 5V/4MHz
• Typically 35 µA, at 3V/32KHz
• Typically 2 µA, during sleep mode
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
4K × 13 bits on chip ROM
Three protection bits to prevent intrusion of OTP memory codes
One configuration register to accommodate user’s requirements
148× 8 bits on chip registers(SRAM, general purpose register)
3 bi-directional I/O ports
5 level stacks for subroutine nesting
8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and
overflow interrupt
ꢀ
ꢀ
ꢀ
Two clocks per instruction cycle
Power down (SLEEP) mode
Two available interruptions
• TCC overflow interrupt
• External interrupt
Product Specification (V1.1) 03.30.2005
• 1
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EM78P447N
8-Bit Microcontroller with OTP ROM
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Programmable free running watchdog timer
10 programmable pull-high pins
2 programmable open-drain pins
2 programmable R-option pins
Package types:
• 20 pin DIP 300mil
• 20 pin SOP 300mil
:EM78P447NDP
:EM78P447NDM
• 24 pin Skinny DIP 300mil :EM78P447NCK
• 24 pin SOP 300mil
• 28 pin DIP 600mil
• 28 pin SOP 300mil
• 28 pin SSOP 209mil
• 32 pin DIP 600mil
• 32 pin SOP 450mil
:EM78P447NCM
:EM78P447NAP
:EM78P447NAM
:EM78P447NAS
:EM78P447NBP
:EM78P447NBWM
ꢀ
ꢀ
99.9% single instruction cycle commands
The transient point of system frequency between HXT and LXT is around 400KHz
2 •
Product Specification (V1.1) 03.30.2005
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EM78P447N
8-Bit Microcontroller with OTP ROM
3 PIN ASSIGNMENT
P55
P54
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P56
2
P57
TCC
VDD
NC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
/RESET
OSCI
OSCO
P77
Vss
TCC
VDD
/INT
P50
28
27
26
25
24
23
22
21
20
19
18
17
16
15
/RESET
OSCI
OSCO
P77
/RESET
OSCI
OSCO
P77
1
2
TCC
VDD
NC
3
2
4
3
3
5
Vss
4
4
Vss
6
/INT
P50
P51
P52
P53
P60
P61
P62
P63
P64
5
P76
P76
5
/INT
P50
7
P76
6
P75
P75
P51
6
P75
8
7
P74
P74
7
P74
P51
9
P52
8
P73
8
10
11
12
13
14
15
16
P73
P72
P71
P70
P67
P66
P65
P52
P73
P53
9
9
P72
P60
P53
P60
P61
P62
P63
P64
P72
10
11
12
13
14
10
11
12
13
14
P71
P61
P71
P70
P62
P70
P67
P63
P67
P66
P64
Vss
P66
P65
P65
DIP
DIP
SSOP
SOP
SOP
P54
TCC
VDD
Vss
1
2
24
23
22
21
20
19
18
17
16
15
14
13
/RESET
OSCI
OSCO
P77
3
20
/RESET
OSCI
OSCO
P77
P54
1
2
4
TCC
VDD
Vss
19
18
17
16
15
14
13
12
11
/INT
P50
P51
P52
P53
P60
P61
P62
5
P76
3
6
P75
4
7
P74
/INT
P50
P51
P52
P53
P60
5
P76
8
P67
6
P75
9
P66
7
P74
10
11
12
P65
8
P73
P64
9
P72
P63
10
P71
SkinnyDIP
SOP
DIP
SOP
Fig. 1 Pin Assignment
Product Specification (V1.1) 03.30.2005
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EM78P447N
8-Bit Microcontroller with OTP ROM
Table 1 EM78P447NAP and EM78P447NAM Pin Description
Symbol Pin No.
Type
Function
VDD
2
-
■ Power supply.
■ XTAL type: Crystal input terminal or external clock input pin.
■ RC type: RC oscillator input pin.
OSCI
27
I
I/O
I
■ XTAL type: Output terminal for crystal oscillator or external clock input pin.
■ RC type: Instruction clock output.
■ External clock signal input.
OSCO
26
■ The real time clock/counter (with Schmitt trigger input pin) must be tied to
VDD or VSS if not in use.
TCC
1
■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain in reset condition.
/RESET
28
I
P50~P53 6~9
P60~P67 10~17
I/O
I/O
■ P50~P53 are bi-directional I/O pins.
■ P60~P67 are bi-directional I/O pins. These can be pulled-high internally by
software control.
■ P70~P77 are bi-directional I/O pins.
■ P74~P75 can be pulled-high internally by software control.
■ P76~P77 can have open-drain output by software control.
■ P70 and P71 can also be defined as the R-option pins.
P70~P77 18~25
I/O
/INT
VSS
NC
5
4
3
I
-
-
■ External interrupt pin triggered by falling edge.
■ Ground.
■ No connection.
Table 2 EM78P447NAS Pin Description
Symbol Pin No.
Type
Function
VDD
3
-
■ Power supply.
■ XTAL type: Crystal input terminal or external clock input pin.
■ RC type: RC oscillator input pin.
OSCI
27
I
I/O
I
■ XTAL type: Output terminal for crystal oscillator or external clock input pin.
■ RC type: Instruction clock output.
■ External clock signal input.
OSCO
26
■ The real time clock/counter (with Schmitt trigger input pin) must be tied to
VDD or VSS if not in use.
TCC
2
■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain in reset condition.
/RESET
28
I
P50~P53 5~8
I/O
I/O
■ P50~P53 are bi-directional I/O pins.
9~13,
P60~P67
■ P60~P67 are bi-directional I/O pins. These can be pulled -high internally by
software control.
15~17
■ P70~P77 are bi-directional I/O pins.
■ P74~P75 can be pulled -high internally by software control.
■ P76~P77 can have open-drain output by software control.
■ P70 and P71 can also be defined as the R-option pins.
P70~P77 18~25
I/O
/INT
VSS
4
I
■ External interrupt pin triggered by falling edge.
■ Ground.
1,14
-
4 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
Table 3 EM78P447NBP and EM78P447NBWM Pin Description
Symbol
Pin No.
Type
Function
VDD
4
-
■ Power supply.
■ XTAL type: Crystal input terminal or external clock input pin.
■ RC type: RC oscillator input pin.
OSCI
29
I
■ XTAL type: Output terminal for crystal oscillator or external clock input pin.
■ RC type: Instruction clock output.
OSCO
28
I/O
■ External clock signal input.
■ The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use.
TCC
3
I
■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will keep in reset condition.
/RESET
P50~P57
30
I
8~11,2~1,
32~31
I/O
I/O
■ P50~P57 are bi-directional I/O pins.
■ P60~P67 are bi-directional I/O pins. These can be pulled -high internally by
software control.
P60~P67 12~19
■ P70~P77 are bi-directional I/O pins.
■ P74~P75 can be pulled-high internally by software control.
■ P76~P77 can have open-drain output by software control.
■ P70 and P71 can also be defined as the R-option pins.
P70~P77 20~27
I/O
/INT
VSS
NC
7
6
5
I
-
-
■ External interrupt pin triggered by falling edge.
■ Ground.
■ No connection.
Table 4 EM78P447NCK and EN78P447NCM Pin Description
Symbol
Pin No.
Type
Function
VDD
3
-
■ Power supply.
■ XTAL type: Crystal input terminal or external clock input pin.
■ RC type: RC oscillator input pin.
OSCI
23
I
I/O
I
■ XTAL type: Output terminal for crystal oscillator or external clock input pin.
■ RC type: Instruction clock output.
■ External clock signal input.
OSCO
22
■ The real time clock/counter (with Schmitt trigger input pin) must be tied to
VDD or VSS if not in use.
TCC
2
■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain in reset condition.
/RESET
24
I
P50~P54 6~9,1
P60~P67 10~17
I/O
I/O
■ P50~P54 are bi-directional I/O pins.
■ P60~P67 are bi-directional I/O pins. These can be pulled-high internally by
software control.
■ P74~P77 are bi-directional I/O pins.
P74~P77 18~21
I/O
■ P74~P75 can be pulled-high internally by software control.
■ P76~P77 can have open-drain output by software control.
/INT
VSS
NC
5
4
3
I
-
-
■ External interrupt pin triggered by falling edge.
■ Ground.
■ No connection.
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EM78P447N
8-Bit Microcontroller with OTP ROM
Table 5 EM78P447NDK and EM78P447NDM Pin Description
Symbol
Pin No.
Type
Function
VDD
3
-
■ Power supply.
■ XTAL type: Crystal input terminal or external clock input pin.
■ RC type: RC oscillator input pin.
OSCI
19
I
I/O
I
■ XTAL type: Output terminal for crystal oscillator or external clock input pin.
■ RC type: Instruction clock output.
■ External clock signal input.
OSCO
18
■ The real time clock/counter (with Schmitt trigger input pin) must be tied to
VDD or VSS if not in use.
TCC
2
■ Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain in reset condition.
/RESET
20
I
P50~P54 6~9,1
P60 10
I/O
I/O
■ P50~P54 are bi-directional I/O pins.
■ P60 are bi-directional I/O pins. This can be pulled-high internally by
software control.
■ P74~P77 are bi-directional I/O pins.
■ P74~P75 can be pulled-high internally by software control.
■ P76~P77 can have open-drain output by software control.
■ P71 can also be defined as the R-option pins.
P71~P77 11~17
I/O
/INT
VSS
NC
5
4
3
I
-
-
■ External interrupt pin triggered by falling edge.
■ Ground.
■ No connection.
4 FUNCTION DESCRIPTION
O S C I O S C O
/R E S E T
T C C /IN T
W D T T im er
S T A C K 1
S T A C K 2
S T A C K 3
S T A C K 4
S T A C K 5
P C
O scillator/T im ing
C ontrol
P rescale
r
R O M
W D T
T im -e out
Interrupt
C ontrol
Instruction
R egister
R 1(TC C )
A LU
A C C
Instruction
D ecoder
S leep
&
W ake
R A M
R 4
R 3
C ontrol
D A TA & C O N TR O L B U S
IO C 6
R6
IO C 5
R 5
IO C 7
R 7
PPPPPPPP
66666666
01234567
PPPPPPPP
55555555
01234567
PPPPPPPP
77777777
01234567
Fig. 2 Functional Block Diagram
6 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
4.1 Operational Registers
4.1.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to act as an indirect
addressing pointer. Any instruction using R0 as a pointer actually accesses data
pointed by the RAM Select Register (R4).
4.1.2 R1 (Time Clock /Counter)
ꢀ
Increased by an external signal edge, which is defined by TE bit (CONT-4) through
the TCC pin, or by the instruction cycle clock.
ꢀ
ꢀ
ꢀ
ꢀ
Writable and readable as any other registers.
Defined by resetting PAB (CONT-3).
The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.
The contents of the prescaler counter will be cleared only when TCC register is
written a value.
4.1.3 R2 (Program Counter) & Stack
ꢀ
Depending on the device type, R2 and hardware stack are 10-bit wide. The
structure is depicted in Fig.3.
ꢀ
Generating 1024×13 bits on-chip OTP ROM addresses to the relative
programming instruction codes. One program page is 1024 words long.
ꢀ
ꢀ
R2 is set as all "0"s when under RESET condition.
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows PC to go to any location within a page.
ꢀ
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into
the stack. Thus, the subroutine entry address can be located anywhere within a
page.
ꢀ
ꢀ
ꢀ
ꢀ
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
of the top-level stack.
"ADD R2,A" allows the contents of ‘A’ to be added to the current PC, and the ninth
and tenth bits of the PC are cleared.
"MOV R2,A" allows to load an address from the "A" register to the lower 8 bits of
the PC, and the ninth and tenth bits of the PC are cleared.
Any instruction that writes to R2 (e.g. "ADD R2,A", "MOV R2,A", "BC R2,6",⋅⋅⋅⋅⋅) will
cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the
computed jump is limited to the first 256 locations of a page.
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EM78P447N
8-Bit Microcontroller with OTP ROM
ꢀ
All instruction are single instruction cycle (fclk/2 or fclk/4) except for the instruction
that would change the contents of R2. Such instruction will need one more
instruction cycle.
R3
000H
001H
002H
A11 A10 A9 A8
A7
~
A0
Hardware Vector
Software Vector
CALL
RET
RETL
On-chip Program
Memory
RETI
00 PAGE0 0000~03FF
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
01 PAGE1 0400~07FF
10 PAGE2 0800~0BFF
11 PAGE3 0C00~0FFF
Reset Vector
FFFH
Fig. 3 Program Counter Organization
8 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
Aaddress
R PAGE registers
IOC PAGE registers
R0
R1
R2
R3
R4
R5
R6
R7
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
(Indirect Addressing Register)
(Time Clock Counter)
(Program Counter)
(Status Register)
(RAM Select Register)
(Port5)
Reserve
(Control Register)
Reserve
CONT
Reserve
Reserve
IOC5
IOC6
IOC7
(I/O Port Control Register)
(I/O Port Control Register)
(I/O Port Control Register)
Reserve
(Port6)
(Port7)
General Register
General Register
General Register
General Register
General Register
General Register
General Register
General Register
Reserve
Reserve
IOCB
(Wake-Up Control Register for Port6 )
Reverse
Reverse
(WDT,SLEEP2,Open Drain,R -Option
Control Register)
IOCE
IOCF
(Interrupt Mask Register)
10
1F
General Registers
20
：
Bank0
Bank1
Bank2
Bank3
3E
R3F
3F
(Interrupt Status Register)
Fig. 4 Data Memory Configuration
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EM78P447N
8-Bit Microcontroller with OTP ROM
4.1.4 R3 (Status Register)
7
6
5
4
3
2
1
0
GP
PS1
PS0
T
P
Z
DC
C
Bit 7 (GP) General read/write bit.
Bits 6 (PS1) ~ 5 (PS0) Page select bits. PS1~PS0 are used to pre-select a program
memory page. When executing a "JMP", "CALL", or other instructions
which causes the program counter to change (e.g. MOV R2, A), PS1~PS0
are loaded into the 11th and 12th bits of the program counter and select one
of the available program memory pages. Note that RET (RETL, RETI)
instruction does not change the PS0~PS1 bits. That is, the return will
always be to the page from where the subroutine was called, regardless of
the PS1~PS0 bits current setting.
PS1
PS0
Program memory page [Address]
0
0
1
1
0
1
0
1
Page 0 [000-3FF]
Page 1 [400-7FF]
Page 2 [800-BFF]
Page 3 [C00-FFF]
Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and "WDTC" commands, or during
power up, and reset to 0 with the WDT time-out.
Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and
reset to 0 by a "SLEP" command.
Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC) Auxiliary carry flag.
Bit 0 (C) Carry flag
4.1.5 R4 (RAM Select Register)
Bits 7~6 determine which bank is activated among the 4 banks.
Bits 5~0 are used to select the registers (address: 00~3F) in the indirect addressing
mode.
If no indirect addressing is used, the RSR can be used as an 8-bit general-purpose
read/writer register.
See the configuration of the data memory in Fig. 4.
4.1.6 R5~R7 (Port 5 ~ Port7)
R5, R6 and R7 are I/O registers
4.1.7 R8~R1F and R20~R3E (General Purpose Register)
R8~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.
10 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
4.1.8 R3F (Interrupt Status Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
EXIF
-
-
TCIF
Bit 3 (EXIF) External interrupt flag. Set by falling edge on /INT pin, flag cleared by
software
Bit 0 (TCIF) the TCC overflow interrupt flag. Set as TCC overflows; flag cleared by
software.
Bits 1, 2, 4~7 are not used and read are as “0”.
"1" means interrupt request, "0" means non-interrupt.
R3F can be cleared by instruction, but cannot be set by instruction.
IOCF is the interrupt mask register.
Note that reading R3F will obtain the result of the R3F "logic AND" and IOCF.
4.2 Special Purpose Registers
4.2.1 A (Accumulator)
ꢀ
ꢀ
Internal data transfer, or instruction operand holding.
It cannot be addressed.
4.2.2 CONT (Control Register)
7
6
5
4
3
2
1
0
/PHEN
/INT
TS
TE
PAB
PSR2
PSR1
PSR0
Bit 7 (/PHEN) Control bit used to enable the pull-high of P60~P67, P74 and P75 pins
0: Enable internal pull-high.
1: Disable internal pull-high.
CONT register is both readable and writable.
Bit 6 (/INT)
Bit 5 (TS)
Interrupt enable flag
0: masked by DISI or hardware interrupt
1: enabled by ENI/RETI instructions
TCC signal source
0: internal instruction cycle clock
1: transition on TCC pin
Product Specification (V1.1) 03.30.2005
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EM78P447N
8-Bit Microcontroller with OTP ROM
Bit 4 (TE)
TCC signal edge
0: increment if the transition from low to high takes place on TCC pin
1: increment if the transition from high to low takes place on TCC pin
Bit 3 (PAB) Prescaler assignment bit.
0: TCC
1: WDT
Bit 2 (PSR2) ~ Bit 0 (PSR0) TCC/WDT prescaler bits.
PSR2
PSR1
PSR0
TCC Rate
1:2
WDT Rate
1:1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:2
1:8
1:4
1:16
1:8
1:32
1:16
1:32
1:64
1:128
1:64
1:128
1:256
4.2.3 IOC5 ~ IOC7 (I/O Port Control Register)
ꢀ
"1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin
as output.
ꢀ
IOC5 and IOC7 registers are both readable and writable.
4.2.4 IOCB (Wake-up Control Register for Port6)
7
6
5
4
3
2
1
0
/WUE7
/WUE6
/WUE5
/WUE4
/WUE3
/WUE2
/WUE1
/WUE0
Bit 7 (/WUE7) Control bit is used to enable the wake-up function of P67 pin.
Bit 6 (/WUE6) Control bit is used to enable the wake-up function of P66 pin.
Bit 5 (/WUE5) Control bit is used to enable the wake-up function of P65 pin.
Bit 4 (/WUE4) Control bit is used to enable the wake-up function of P64 pin.
Bit 3 (/WUE3) Control bit is used to enable the wake-up function of P63 pin.
Bit 2 (/WUE2) Control bit is used to enable the wake-up function of P62 pin.
Bit 1 (/WUE1) Control bit is used to enable the wake-up function of P61 pin.
Bit 0 (/WUE0) Control bit is used to enable the wake-up function of P60 pin.
0: Enable internal wake-up.
1: Disable internal wake-up.
IOCB Register is both readable and writable.
12 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
4.2.5 IOCE (WDT Control Register)
7
6
5
4
3
2
1
0
-
ODE
WDTE
SLPC
ROC
-
-
/WUE
Bit 6 (ODE) Control bit is used to enable the open-drain of P76 and P77 pins
0: Disable open-drain output.
1: Enable open-drain output.
The ODE bit can be read and written.
Bit 5 (WDTE) Control bit used to enable Watchdog timer.
The WDTE bit is useful only when ENWDT, the CODE Option bit, is "0".
It is only when the ENWDT bit is "0" that WDTE bit. is able to
disabled/enabled the WDT.
0: Disable WDT.
1: Enable WDT.
The WDTE bit is not used if ENWDT, the CODE Option bit ENWDT, is
"1". That is, if the ENWDT bit is "1", WDT is always disabled no matter
what the WDTE bit status is.
The WDTE bit can be read and written.
Bit 4 (SLPC) This bit is set by hardware at the low level trigger of wake-up signal and
is cleared by software. SLPC is used to control the oscillator operation.
The oscillator is disabled (oscillator is stopped, and the controller enters
into SLEEP2 mode) on the high-to-low transition and is enabled
(controller is awakened from SLEEP2 mode) on low-to-high transition.
In order to ensure the stable output of the oscillator, once the oscillator is
enabled again, there is a delay for approximately 18ms1 (oscillator
start-up timer, OST) before the next instruction of the program is
executed. The OST is always activated by a wake-up event from sleep
mode regardless of the Code Option bit ENWDT status is "0" or
otherwise. After waking up, the WDT is enabled if the Code Option
ENWDT is "1". The block diagram of SLEEP2 mode and wake-up
invoked by an input trigger is depicted in Fig. 5. The SLPC bit can be
read and written.
Bit 3 (ROC) ROC is used for the R-option. Setting ROC to "1" will enable the status
of R-option pins (P70, P71) for the controller to read. Clearing ROC will
disable the R-option function. Otherwise, the R-option function is
introduced. Users must connect the P71 pin or/and P70 pin to VSS with
a 430KΩ external resistor (Rex). If Rex is connected/disconnected with
VDD, the status of P70 (P71) will be read as "0"/"1" (refer to Fig. 7(b)).
The ROC bit can be read and written.
1 <Note>: Vdd = 5V, set up time period = 16.2ms ± 30%
Vdd = 3V, set up time period = 19.6ms ± 30%
Product Specification (V1.1) 03.30.2005
• 13
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EM78P447N
8-Bit Microcontroller with OTP ROM
Bit 0 (/WUE) Control bit is used to enable the wake-up function of P74 and P75.
0: Enable the wake-up function.
1: Disable the wake-up function.
The /WUE bit can be read and written.
Bits 1~2, and 7 Not used.
4.2.6 IOCF (Interrupt Mask Register)
7
6
5
4
3
2
1
0
-
-
-
-
EXIE
-
-
TCIE
Bit 3 (EXIE) EXIF interrupt enable bit.
0: disable EXIF interrupt
1: enable EXIF interrupt
Bit 0 (TCIE) TCIF interrupt enable bit.
0: disable TCIF interrupt
1: enable TCIF interrupt
Bits 1, 2 and 4~7 Not used.
Individual interrupt is enabled by setting its associated control bit in the IOCF to "1".
Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction
(refer to Fig. 9).
ꢀ
IOCF Register is Both Readable and Writable.
/WUE0
Oscillator
Enable
Disable
/WUE1
Reset
PR
Q
Q
D
CLK
CL
VCC
/WUE7
Clear
from S/W
Set
8
P60~P67
VCC
/WUE
2
/PHEN
P74~P75
Fig. 5 Sleep Mode and Wake-Up Circuits on I/O Ports Block Diagram
14 •
Product Specification (V1.1) 03.30.2005
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EM78P447N
8-Bit Microcontroller with OTP ROM
4.3 TCC/WDT & Prescaler
An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is
available for either the TCC or WDT only at any given time, and the PAB bit of the
CONT register is used to determine the prescaler assignment. The PSR0~PSR2 bits
determine the ratio. The prescaler is cleared each time the instruction is written to TCC
under TCC mode. The WDT and prescaler, when assigned to WDT mode, are cleared
by the “WDTC” or “SLEP” instructions. Fig. 6 depicts the circuit diagram of TCC/WDT.
ꢀ
R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or
external clock input (edge selectable from TCC pin). If TCC signal source is from
internal clock, TCC will increase by 1 at every instruction cycle (without prescaler).
Referring to Fig. 6, CLK=Fosc/2 or CLK=Fosc/4 selection is determined by the
CODE Option bit CLK status. CLK=Fosc/2 is used if CLK bit is "0", and
CLK=Fosc/4 is used if CLK bit is "1". If TCC signal source comes from external
clock input, TCC is increased by 1 at every falling edge or rising edge of TCC pin.
ꢀ
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on
running even after the oscillator driver has been turned off (i.e. in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled any time during normal
mode by software programming. Refer to WDTE bit of IOCE register. Without
prescaler, the WDT time-out period is approximately 18 ms2 (default).
Data Bus
CLK(=Fosc/2)
0
1
1
0
TCC
Pin
M
U
X
M
U
X
SYNC
2 cycles
TCC(R1)
TE
TCC overflow interrupt
TS
PAB
0
1
M
U
X
8-bit Counter
8-to-1 MUX
WDT
PSR0~PSR2
PAB
WDTE
(in IOCE)
PAB
0
1
MUX
WDT timeuot
Fig. 6 TCC and WDT Block Diagram
2 <Note>: Vdd = 5V, set up time period = 16.2ms ± 30%
Vdd = 3V, set up time period = 19.6ms ± 30%
Product Specification (V1.1) 03.30.2005
• 15
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EM78P447N
8-Bit Microcontroller with OTP ROM
4.4 I/O Ports
The I/O registers, Port 5, Port 6, and Port 7, are bi-directional tri-state I/O ports. The
functions of Pull-high, R-option, and Open-drain can be performed internally by CONT
and IOCE respectively. There is input status change wake-up function on Port 6, P74,
and P75. Each I/O pin can be defined as "input" or "output" pin by the I/O control
register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both readable
and writable. The I/O interface circuits for Port 5, Port 6, and Port 7 are shown in
Figures. 7(a) and (b) respectively.
PCRD
PR
Q
Q
D
CLK
CL
PCWR
IOD
PR
PORT
Q
Q
D
PDWR
PDRD
CLK
CL
0
M
U
X
1
Fig. 7 (a) The I/O Port and I/O Control Register Circuit
PCRD
VCC
ROC
PR
Q
Q
D
Weakly
Pull-up
CLK
CL
PCWR
IOD
PR
PORT
Q
Q
D
PDWR
PDRD
CLK
CL
0
M
U
X
Rex*
1
*The Rex is 430K ohm external resistor
Fig.7 (b) The I/O Port with R-Option (P70, P71) Circuit
16 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
4.5 RESET and Wake-up
4.5.1 RESET
A RESET is initiated by one of the following events-
(1) Power on reset, or
(2) /RESET pin input “low”, or
(3) WDT timeout. (if enabled)
The device is kept in a RESET condition for a period of approx. 18ms3 (one oscillator
start-up timer period) after the reset is detected. Once the RESET occurs, the following
functions are performed (refer to Fig.8).
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
The oscillator starts or is running
The Program Counter (R2) is set to all "1".
When power is switched on, bits 5~6 of R3 and the upper 2 bits of R4 are cleared.
All I/O port pins are configured as input mode (high-impedance state).
The Watchdog timer and prescaler are cleared.
Upon power on, the bits 5~6 of R3 are cleared.
Upon power on, the upper 2 bits of R4 are cleared.
The bits of CONT register are set to all "1" except bit 6 (INT flag).
IOCB register is set to ”1” (disable P60 ~ P67 wake-up function).
Bits 3 and 6 of IOCE register are cleared, and Bits 0, 4, and 5 are set to "1".
Bits 0 and 3 of R3F register and Bits 0 and 3 of IOCF registers are cleared.
The sleep (power down) mode is asserted by executing the “SLEP” instruction. While
entering sleep mode, WDT (if enabled) is cleared but keeps on running. The controller
can be awakened by-
(1) External reset input on /RESET pin;
(2) WDT time-out (if enabled)
The above two cases will cause the controller EM78P447N to reset. The T and P flags
of R3 can be used to determine the source of the reset (wake-up).
In addition to the basic SLEEP1 MODE, EM78P447N has another sleep mode
(designated as SLEEP2 MODE and is invoked by clearing the IOCE register “SLPC”
bit). In the SLEEP2 MODE, the controller can be awakened by-
3 NOTE: Vdd = 5V, set up time period = 16.2ms ± 30%
Vdd = 3V, set up time period = 19.6ms ± 30%
Product Specification (V1.1) 03.30.2005
• 17
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EM78P447N
8-Bit Microcontroller with OTP ROM
(A) Any of the wake-up pins is “0” as illustrated in Figure. 5. Upon waking, the controller
will continue to execute the succeeding address. Under this case, before entering
SLEEP2 MODE, the wake-up function of the trigger sources (P60~P67 and
P74~P75) should be selected (e.g., input pin) and enabled (e.g., pull-high, wake-up
control). It should be noted that after waking up, the WDT is enabled if the Code
Option bit ENWDT is “0”. The WDT operation (to be enabled or disabled) should be
appropriately controlled by software after waking up.
(B) WDT time-out (if enabled) or external reset input on /RESET pin will trigger a
controller reset.
Table 6 Usage of Sleep1 and Sleep2 Mode
Usage of Sleep1 and Sleep2 Mode
SLEEP2
SLEEP1
(a) Before SLEEP
(a) Before SLEEP
1. Set Port6 or P74 or P75 Input
1. Execute SLEP instruction
2. Enable Pull-High and set WDT
prescaler over 1:1 (Set CONT.7 and
CONT.3 ~ CONT.0)
3. Enable Wake-up (Set IOCB or IOCE.0)
4. Execute Seep2 (Set IOCE.4)
(b) After Wake-up
(b) After Wake-up
1. Reset
1. Next instruction
2. Disable Wake-up
3. Disable WDT (Set IOCE.5)
If Port6 Input Status Changed Wake-up is used to wake-up the EM78P447S (Case [a]
above), the following instructions must be executed before entering SLEEP2 mode:
MOV
A, @11111111b ; Set Port6 input
R6
IOW
; Set Port6 pull-high, WDT prescaler,
prescaler must set over 1:1
MOV
A, @0xxx1010b
CONTW
MOV
A, @00000000b ; Enable Port6 wake-up function
IOW
RB
MOV
IOW
A, @xx00xxx1b ; Enable SLEEP2
RE
After
Wake-up
NOP
MOV
IOW
MOV
IOW
A, @11111111b ; Disable Port6 wake-up function
RB
A, @ xx01xxx1b ; Disable WDT
RE
18 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
NOTE
ꢀ
ꢀ
After waking up from the SLEEP2 mode, WDT is automatically enabled. The
WDT enabled/disabled operation after waking up from SLEEP2 mode should be
appropriately defined in the software.
To avoid reset from occurring when the port6 status changed interrupt enters
into interrupt vector or is used to wake-up the MCU, the WDT prescaler must be
set above 1:1 ratio.
Table 7 The Summary of the Initialized Values for Registers
Address Name
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
Bit Name
C57
C56
C55
C54
C53 C52 C51 C50
Type
Power-On
/RESET and WDT
Wake-Up from Pin
Change
A
0
0
B
1
1
A
0
0
B
1
1
A
0
0
B
1
1
A
0
0
B
1
1
-
1
1
-
1
1
-
1
1
-
1
1
N/A
N/A
IOC5
IOC6
IOC7
CONT
0
P
0
P
0
P
0
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
C67
1
1
C66
1
1
C65
1
1
C64
1
1
C63 C62 C61 C60
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
C77
1
1
C76
1
1
C75
1
1
C74
1
1
C73 C72 C71 C70
N/A
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
/PHEN
/INT
0
P
TS
1
1
TE
1
1
PAB PSR2 PSR1 PSR0
N/A
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
0x00
0x01
0x02
0x03
0x04
R0(IAR) Power-On
/RESET and WDT
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
R1(TCC) Power-On
-
0
0
-
0
0
-
0
0
-
0
0
-
0
0
-
0
0
-
0
0
-
0
0
/RESET and WDT
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
1
1
-
1
1
-
1
1
-
1
1
-
1
1
-
1
1
-
1
1
-
1
1
R2(PC)
R3(SR)
Power-On
/RESET and WDT
Wake-Up from Pin
Change
**0/P
**0/P
**0/P
**0/P **0/P **0/P **0/P **0/P
Bit Name
Power-On
GP
0
0
PS1
0
0
PS0
0
0
T
1
t
P
1
t
Z
U
P
DC
U
P
C
U
P
/RESET and WDT
Wake-Up from Pin
Change
P
P
P
t
t
P
P
P
Bit Name
RSR.1
RSR.0
-
U
P
-
U
P
-
U
P
-
U
P
-
U
P
-
U
P
R4(RSR) Power-On
/RESET and WDT
Product Specification (V1.1) 03.30.2005
0
0
0
0
• 19
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EM78P447N
8-Bit Microcontroller with OTP ROM
Address Name
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
P57
U
P
P56
U
P
P55
U
P
P54
U
P
P53 P52 P51 P50
0x05
0x06
0x07
R5(P5)
R6(P6)
R7(P7)
U
P
U
P
U
P
U
P
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
P67
U
P
P66
U
P
P65
U
P
P64
U
P
P63 P62 P61 P60
U
P
U
P
U
P
U
P
P
P
P
P
P
P
P
P
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
P77
U
P
P76
U
P
P75
U
P
P74
U
P
P73 P72 P71 P70
U
P
U
P
U
P
U
P
P
P
P
P
P
P
P
P
Bit Name
-
-
-
-
EXIF
-
-
TCIF
0x3F R3F(ISR) Power-On
/RESET and WDT
U
U
U
U
U
U
U
U
0
0
U
U
U
U
0
0
Wake-Up from Pin
Change
U
U
U
U
P
U
U
P
/WUE3 /WUE2 /WUE1 /WUE0
/WUE7 /WUE6 /WUE5 /WUE4
Bit Name
0x0B
IOCB
Power-On
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
/RESET and WDT
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
ODE
WDTE
SLPC
ROC
-
-
/WUE
0x0E
0x0F
0x08
IOCE
IOCF
R8
Power-On
U
U
0
0
1
1
1
1
0
0
U
U
U
U
1
1
/RESET and WDT
Wake-Up from Pin
Change
U
P
1
1
P
U
U
P
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
-
U
U
-
U
U
-
U
U
-
U
U
EXIE
0
0
-
U
U
-
U
U
TCIE
0
0
U
U
U
U
P
U
U
P
-
0
0
-
0
0
-
0
0
-
0
0
-
0
0
-
0
0
-
0
0
-
0
0
P
-
P
-
P
-
P
-
P
-
P
-
P
-
P
-
Bit Name
0x09~0x3E
R9~R3E Power-On
/RESET and WDT
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
Wake-Up from Pin
Change
** To execute next instruction after the ”SLPC” bit status of IOCE register being on
high-to-low transition.
X：Not used. U: Unknown or don’t care. P: Previous value before reset. t: Check
Table 7
20 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
4.5.2 The Status of RST, T, and P of STATUS Register
A RESET condition is initiated by one of the following events:
1. A power-on condition,
2. A high-low-high pulse on /RESET pin, and
3. Watchdog timer time-out.
The values of T and P (listed in Table 8 below) are used to verify the event that
triggered the processor to wake up.
Table 8 shows the events that may affect the status of T and P.
Table 8 The Values of RST, T and P after RESET
Reset Type
T
P
Power on
1
1
/RESET during Operating mode
*P
*P
/RESET wake-up during SLEEP1 mode
/RESET wake-up during SLEEP2 mode
WDT during Operating mode
1
0
*P
0
*P
*P
0
WDT wake-up during SLEEP1 mode
WDT wake-up during SLEEP2 mode
Wake-Up on pin change during SLEEP2 mode
0
0
*P
*P
*P
*P: Previous status before reset
Table 9 The Events that may Affect the T and P Status
Event
T
1
P
1
Power on
WDTC instruction
1
1
WDT time-out
0
*P
0
SLEP instruction
1
Wake-Up on pin change during SLEEP2 mode
*P
*P
*P: Previous value before reset
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EM78P447N
8-Bit Microcontroller with OTP ROM
VDD
D
CLK
Q
CLK
Oscillator
CLR
Power-on
Reset
Voltage
Detector
WDTE
WDT Timeout
Setup Time
RESET
WDT
/RESET
Fig. 8 Controller Reset Block Diagram
4.6 Interrupt
The EM78P447N has two interrupts listed below:
(1) TCC overflow interrupt
(2) External interrupt (/INT pin).
R3F is the interrupt status register that records the interrupt requests in the relative
flags/bits. IOCF is the interrupt mask register. The global interrupt is enabled by the
ENI instruction and is disabled by the DISI instruction. When one of the interrupts
(enabled) occurs, the next instruction will be fetched from address 001H. Once in the
interrupt service routine, the source of an interrupt can be determined by polling the flag
bits in R3F. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine and before interrupts are enabled to avoid recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (R3F) is set regardless of the
status of its mask bit or the execution of ENI. Note that the outcome of R3F are the
logic AND of R3F and IOCF (refer to Fig. 9). The RETI instruction ends the interrupt
routine and enables the global interrupt (the execution of ENI).
When an interrupt is generated by the INT instruction (enabled), the next instruction will
be fetched from address 002H.
22 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
VCC
P
D
Q
IRQn
IRQm
R
/IRQn
CLK
INT
_
Q
C
L
RFRD
RF
ENI/DISI
P
IOD
Q
D
R
CLK
_
Q
IOCFWR
C
L
IOCF
/RESET
IOCFRD
RFWR
Fig. 9 Interrupt Input Circuit
4.7 Oscillator
4.7.1 Oscillator Modes
The EM78P447N can operate in three different oscillator modes, i.e., high XTAL (HXT)
oscillator mode, low XTAL (LXT) oscillator mode, and External RC oscillator mode
(ERC) oscillator mode. User can select one of them by programming MS, HLF and
HLP in the Code Option Register. Table 10 depicts how these three modes are
defined.
The maximum limit for operational frequencies of crystal/resonator under different
VDDs is listed in Table 10.
Table 10 Oscillator Modes Defined by MS and HLP
Mode
MS
0
HLF
HLP
ERC(External RC oscillator mode)
HXT(High XTAL oscillator mode)
LXT(Low XTAL oscillator mode)
*X
1
*X
*X
0
1
1
0
NOTE
1. X, Don’t care
2. The transient point of system frequency between HXT and LXY is around 400 KHz.
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EM78P447N
8-Bit Microcontroller with OTP ROM
Table 11 The Summary of Maximum Operating Speeds
Conditions
VDD
2.3
Fxt max.(MHz)
4.0
8.0
Two cycles with two clocks
3.0
5.0
20.0
4.7.2 Crystal Oscillator/Ceramic Resonators(XTAL)
EM78P447N can be driven by an external clock signal through the OSCI pin as shown
in Fig. 10 below.
In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or
ceramic resonator to generate oscillation. Fig. 12 depicts such circuit. The same thing
applies whether it is in the HXT mode or in the LXT mode. Table 12 provides the
recommended values of C1 and C2. Since each resonator has its own attribute, user
should refer to its specification for appropriate values of C1 and C2. RS. A serial
resistor may be necessary for AT strip cut crystal or low frequency mode.
OSCI
Ext. Clock
OSCO
EM78P447S
Fig. 10 Crystal/Resonator Circuit
C1
OSCI
EM78P447S
XTAL
OSCO
C2
RS
Fig. 11 Crystal/Resonator Circuit
24 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
Table 12 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator
Oscillator Type
Frequency Mode Frequency
C1(pF)
100~150
20~40
10~30
25
C2(pF)
100~150
20~40
10~30
15
455 kHz
Ceramic Resonators
HXT
LXT
2.0 MHz
4.0 MHz
32.768kHz
100KHz
200KHz
455KHz
1.0MHz
2.0MHz
4.0MHz
25
25
25
25
Crystal Oscillator
20~40
15~30
15
20~150
15~30
15
HXT
15
15
4.7.3 External RC Oscillator Mode
For some applications that do not need a very precise timing calculation, the RC
oscillator (Fig. 15) offers a lot of cost savings. Nevertheless, it should be noted that the
frequency of the RC oscillator is influenced by the supply voltage, the values of the
resistor (Rext), the capacitor (Cext), and even by the operation temperature.
Moreover, the frequency also changes slightly from one chip to another due to the
manufacturing process variation.
In order to maintain a stable system frequency, the values of the Cext should not be
less than 20pF, and that the value of Rext should not be greater than 1 M ohm. If they
cannot be kept in this range, the frequency is easily affected by noise, humidity, and
leakage.
The smaller the Rext in the RC oscillator, the faster its frequency will be. On the
contrary, for very low Rext values, for instance, 1 KΩ, the oscillator becomes unstable
because the NMOS cannot discharge the current of the capacitance correctly.
Based on the above reasons, it must be kept in mind that all of the supply voltage, the
operation temperature, the components of the RC oscillator, the package types, the
way the PCB is layout, will affect the system frequency.
VCC
Rext
OSCI
Cext
EM78P447S
Fig. 12 External RC Oscillator Mode Circuit
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EM78P447N
8-Bit Microcontroller with OTP ROM
Table 13 RC Oscillator Frequencies
Cext
Rext
Average Fosc 5V,25°C
Average Fosc 3V,25°C
3.3k
5.1k
10k
100k
3.3k
5.1k
10k
100k
3.3k
5.1k
10k
4.32 MHz
2.83 MHz
1.62MHz
184 KHz
1.39 MHz
950 KHz
500 KHz
54KHz
580 KHz
390 KHz
200 KHz
21 KHz
3.56 MHz
2.8 MHz
1.57 MHz
187 KHz
1.35 MHz
930 KHz
490 KHz
55 KHz
550 KHz
380 KHz
200 KHz
21 KHz
20 pF
100 pF
300 pF
100k
NOTE
1. Measured on DIP packages.
2. For design reference only.
4.8 CODE Option Register
The EM78P447N has one CODE option word that is not a part of the normal program
memory. The option bits cannot be accessed during normal program execution.
Code Option Register and Customer ID Register arrangement distribution:
Word 0
Word 1
Bit12~Bit0
Bit12~Bit0
4.8.1 Code Option Register (Word 0)
Word 0
Bit12 Bit11 Bit10
EC
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
PR2
Bit1
Bit0
-
-
-
CLKS ENWDTB TYPE
HLF
OSC HLP
PR1
PR0
Bit 12 、11 : Not used.
Reserved.
The bit set to “1” all the time.
Bit 10 (EC): Error recovery Bit.
0: Enable
1: Disable
Bit 9:
Not used.
Reserved.
The bit set to “0” all the time.
26 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
Bit 8 (CLKS): Instruction period option bit.
0: two oscillator periods.
1: four oscillator periods.
Refer to the section on Instruction Set.
Bit 7(ENWDTB): Watchdog timer enable bit.
0: Enable
1: Disable
Bit 6:
Type selection for EM78P447NA or EM78P447NB
0: EM78P447NB
1: EM78P447NA
Bit 5 (HLF): XTAL frequency selection
0: XTAL2 type (low frequency, 32.768KHz)
1: XTAL1 type (high frequency)
This bit will affect system oscillation only when Bit4 (OSC) is “1”. When OSC is”0”, HLF
must be “0”.
NOTE
The transient point of system frequency between HXT and LXY is around 400 KHz.
Bit 4 (OSC): Oscillator type selection.
0:RC type
1:XTAL type (XTAL1 and XTAL2)
Bit 3 (HLP): Power selection.
0: Low power
1: High power
Bit 2~0 (PR2~PR0): Protect Bit
PR2~PR0 are protect bits, protect type as following
PR2
0
PR1
0
PR0
0
Protect
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Disable
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
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EM78P447N
8-Bit Microcontroller with OTP ROM
4.8.2 Customer ID Register (Word 1)
Word 1
Bit 12~Bit 0
XXXXXXXXXXXXX
Bit 12~0: Customer’s ID code
4.9 Power On Considerations
Any microcontroller is not guaranteed to start and operate properly before the power
supply stays at its steady state. EM78P447N is equipped with Power On Voltage
Detector(POVD) with a detecting level is 2.0V. It will work well if Vdd rises fast enough
(10 ms or less). In many critical applications, however, extra devices are still required
to assist in solving power-up problems.
4.10 External Power On Reset Circuit
The circuit shown in Fig.16 implements an external RC to produce the reset pulse. The
pulse width (time constant) should be kept long enough for Vdd to reached minimum
operation voltage. This circuit is used when the power supply has slow rise time.
Because the current leakage from the /RESET pin is about ±5µA, it is recommended
that R should not be greater than 40 K. In this way, the /RESET pin voltage is held
below 0.2V. The diode (D) acts as a short circuit at the moment of power down. The
capacitor C will discharge rapidly and fully. Rin, the current-limited resistor, will prevent
high current or ESD (electrostatic discharge) from flowing to pin /RESET.
Vdd
R
/RESET
D
EM78P447N
Rin
C
Fig. 13 External Power-Up Reset Circuit
28 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
4.11 Residue-Voltage Protection
When battery is replaced, device power (Vdd) is taken off but residue-voltage remains.
The residue-voltage may trips below Vdd minimum, but not to zero. This condition may
cause a poor power on reset. Fig.16 and Fig.17 show how to build the residue-voltage
protection circuit.
Vdd
Vdd
33K
EM78P447N
Q1
10K
/RESET
40K
1N4684
Fig. 14 The Residue Voltage Protection Circuit 1
Vdd
Vdd
R1
R2
EM78P447N
/RESET
Q1
40K
Fig. 15 The Residue Voltage Protection Circuit 2
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EM78P447N
8-Bit Microcontroller with OTP ROM
4.12 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator periods), unless the program counter is
changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or
logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", ⋅⋅⋅⋅). In this case, the
execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain
applications, try modifying the instruction as follows:
(A) Change one instruction cycle to consist of 4 oscillator periods.
(B) Executed within two instruction cycles, "JMP", "CALL", "RET", "RETL", "RETI", or
the conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") instructions which
were tested to be true. Also execute within two instruction cycles, the instructions
that are written to the program counter.
Case (A) is selected by the CODE Option bit, called CLK. One instruction cycle
consists of two oscillator clocks if CLK is low, and four oscillator clocks if CLK is high.
Note that once the 4 oscillator periods within one instruction cycle is selected as in
Case (A), the internal clock source to TCC should be CLK=Fosc/4, not Fosc/ 2 as
indicated in Fig. 5.
In addition, the instruction set has the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
The symbol "R" represents a register designator that specifies which one of the
registers (including operational registers and general purpose registers) is to be utilized
by the instruction. "b" represents a bit field designator that selects the value for the bit
which is located in the register "R", and affects operation. "k" represents an 8 or 10-bit
constant or literal value.
30 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
INSTRUCTION
BINARY
HEX
MNEMONIC
NOP
OPERATION
STATUS AFFECTED
0 0000 0000 000
0 0000 0000 001
0 0000 0000 010
0 0000 0000 011
0 0000 0000 100
0 0000 0000 rrrr
0 0000 0001 000
0 0000 0001 001
0 0000 0001 010
0000
0001
0002
0003
0004
000r
0010
0011
0012
No Operation
None
C
DAA
Decimal Adjust A
A → CONT
CONTW
SLEP
WDTC
IOW R
ENI
None
T,P
0 → WDT, Stop oscillator
0 → WDT
T,P
None <Note1>
None
None
None
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
DISI
RET
[Top of Stack] → PC,
Enable Interrupt
0 0000 0001 011
0013
RETI
None
0 0000 0001 100
0 0000 0001 rrrr
0014
001r
CONTR
IOR R
None
CONT → A
IOCR → A
None <Note1>
R2+A → R2,
Bits 8~9 of R2 unchanged
0 0000 0010 000
0020
TBL
Z,C,DC
0 0000 01rr rrrr
0 0000 1000 000
0 0000 11rr rrrr
0 0001 00rr rrrr
0 0001 01rr rrrr
0 0001 10rr rrrr
0 0001 11rr rrrr
0 0010 00rr rrrr
0 0010 01rr rrrr
0 0010 10rr rrrr
0 0010 11rr rrrr
0 0011 00rr rrrr
0 0011 01rr rrrr
0 0011 10rr rrrr
0 0011 11rr rrrr
0 0100 00rr rrrr
0 0100 01rr rrrr
0 0100 10rr rrrr
0 0100 11rr rrrr
0 0101 00rr rrrr
0 0101 01rr rrrr
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
MOV R,A
CLRA
None
A → R
Z
0 → A
CLR R
Z
0 → R
SUB A,R
SUB R,A
DECA R
DEC R
Z,C,DC
R-A → A
R-A → R
R-1 → A
R-1 → R
A ∨ R → A
A ∨ R → R
A & R → A
A & R → R
A ⊕ R → A
A ⊕ R → R
A + R → A
A + R → R
R → A
Z,C,DC
Z
Z
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
Z
Z
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
R → R
/R → A
/R → R
INCA R
INC R
R+1 → A
R+1 → R
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EM78P447N
8-Bit Microcontroller with OTP ROM
INSTRUCTION
HEX
MNEMONIC
OPERATION
STATUS AFFECTED
BINARY
0 0101 10rr rrrr
0 0101 11rr rrrr
05rr
05rr
DJZA R
DJZ R
None
None
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1),
R(0) → C, C → A(7)
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
R(7) → C, C → A(0)
R(n) → R(n+1),
R(7) → C, C → R(0)
R(0-3) → A(4-7),
R(4-7) → A(0-3)
0 0110 00rr rrrr
0 0110 01rr rrrr
0 0110 10rr rrrr
0 0110 11rr rrrr
0 0111 00rr rrrr
06rr
06rr
06rr
06rr
07rr
RRCA R
RRC R
C
C
RLCA R
RLC R
C
C
SWAPA R
None
0 0111 01rr rrrr
0 0111 10rr rrrr
0 0111 11rr rrrr
0 100b bbrr rrrr
0 101b bbrr rrrr
0 110b bbrr rrrr
0 111b bbrr rrrr
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
SWAP R
JZA R
None
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
None
JZ R
None
BC R,b
BS R,b
JBC R,b
JBS R,b
None <Note2>
None <Note3>
None
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
None
PC+1 → [SP],
(Page, k) → PC
1 00kk kkkk kkkk
1kkk
CALL k
None
1 01kk kkkk kkkk
1 1000 kkkk kkkk
1 1001 kkkk kkkk
1 1010 kkkk kkkk
1 1011 kkkk kkkk
1 1100 kkkk kkkk
1 1101 kkkk kkkk
1 1110 0000 010
1 1111 kkkk kkkk
1kkk
18kk
19kk
1Akk
1Bkk
1Ckk
1Dkk
1E02
1Fkk
JMP k
None
None
Z
(Page, k) → PC
k → A
MOV A,k
OR A,k
AND A,k
XOR A,k
RETL k
SUB A,k
INT
A ∨ k → A
Z
A & k → A
Z
A ⊕ k → A
None
Z,C,DC
None
Z,C,DC
k → A, [Top of Stack] → PC
k-A → A
PC+1 → [SP], 002H → PC
k+A → A
ADD A,k
NOTE
ꢀ
ꢀ
ꢀ
This instruction is applicable to IOC5 ~ IOC7, IOCB, IOCE, IOCF only.
This instruction is not recommended for R3F operation.
This instruction cannot operate under R3F.
32 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
4.13 Timing Diagram
AC Test Input/Output Waveform
2.4
0.4
2.0
0.8
2.0
0.8
TEST POINTS
AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are
made at 2.0V for logic "1",and 0.8V for logic "0".
RESET Timing (CLK="0")
Instruction 1
Executed
NOP
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins
CLK
TCC
Ttcc
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EM78P447N
8-Bit Microcontroller with OTP ROM
5 ABSOLUTE MAXIMUM RATINGS
Items
Rating
Temperature under bias
Storage temperature
Input voltage
to
to
to
to
to
to
-40°C
85°C
-65°C
150°C
VSS-0.3V
VSS-0.3V
32.768KHz
2.5V
VDD+0.5V
VDD+0.5V
20MHz
5.5V
Output voltage
Operating Frequency (2clk)
Operating Voltage
6 DC ELECTRICAL CHARACTERISTICS
6.1 DC Electrical Characteristic
(Ta= 25 °C, VDD= 5.0V±5%, VSS= 0V )
Symbol
Parameter
XTAL: VDD to 3V
XTAL: VDD to 5V
ERC: VDD to 5V
Condition
Min
DC
Typ.
Max
8.0
Unit
MHz
MHz
KHz
Two cycle with two clocks
Two cycle with two clocks
R: 5.1KΩ, C: 100 pF
FXT
DC
20.0
ERC
IIL
950
F±30%
F±30%
Input Leakage Current for
input pins
VIN = VDD, VSS
±1
µA
VIH1
VIL1
Input High Voltage (VDD=5V) Ports 5, 6,7
2.0
2.0
V
V
Input Low Voltage (VDD=5V)
Ports 5, 6,7
0.8
Input High Threshold Voltage
(VDD=5V)
VIHT1
VILT1
VIHX1
VILX1
/RESET, TCC,INT
V
V
V
V
Input Low Threshold Voltage
(VDD=5V)
Clock Input High Voltage
(VDD=5V)
/RESET, TCC,INT
OSCI
0.8
3.5
Clock Input Low Voltage
(VDD=5V)
OSCI
1.5
0.4
VIH2
VIL2
Input High Voltage (VDD=3V) Ports 5, 6,7
1.5
1.5
V
V
Input Low Voltage (VDD=3V)
Ports 5, 6,7
Input High Threshold Voltage
(VDD=3V)
VIHT2
VILT2
VIHX2
VILX2
VOH1
VOL1
VOL2
IPH
/RESET, TCC,INT
V
V
Input Low Threshold Voltage
(VDD=3V)
Clock Input High Voltage
(VDD=3V)
/RESET, TCC,INT
OSCI
0.4
0.9
2.1
2.4
V
Clock Input Low Voltage
(VDD=3V)
OSCI
V
Output High Voltage
(Ports 5, 6, 7)
Output Low Voltage
(Ports 5, 6)
Output Low Voltage
(Port7)
IOH = -10.0 mA
IOL = 9.0 mA
IOL = 14.0 mA
V
0.4
0.4
V
V
Pull-high active, input pin at
VSS
Pull-high current
-50
-100
-240
µA
All input and I/O pins at VDD,
output pin floating, WDT
disabled
ISB1
Power down current
1
µA
34 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
Symbol
Parameter
Condition
Min
Typ.
Max
Unit
All input and I/O pins at VDD,
output pin floating, WDT
enabled
ISB2
Power down current
7
µA
/RESET= 'High', Fosc=32KHz
(Crystal type,CLKS="0"),
output pin floating, WDT
disabled
/RESET= 'High', Fosc=32KHz
(Crystal type,CLKS="0"),
output pin floating, WDT
enabled
/RESET= 'High', Fosc=4MHz
(Crystal type, CLKS="0"),
output pin floating, WDT
enabled
/RESET= 'High', Fosc=10MHz
(Crystal type, CLKS="0"),
output pin floating, WDT
enabled
Operating supply current
(VDD=3V)
at two cycles/four clocks
ICC1
ICC2
ICC3
ICC4
25
30
30
35
µA
µA
Operating supply current
(VDD=3V)
at two cycles/four clocks
Operating supply current
(VDD=5V)
at two cycles/two clocks
1.6
2.8
2.2
5.0
mA
mA
Operating supply current
(VDD=5V)
at two cycles/four clocks
6.2 AC Electrical Characteristic
(Ta=- -40°C ~ 85 °C, VDD=5V±5%, VSS=0V)
Symbol
Parameter
Conditions
Min
45
Typ
Max
Unit
Dclk
Input CLK duty cycle
50
55
%
ns
ns
ns
ms
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
Crystal type
RC type
100
500
60000
Instruction cycle time
(CLKS="0")
Tins
100000
Ttcc
TCC input period
(Tins+20)/N*
11.3
Tdrh
Trst
Device reset hold time
/RESET pulse width
16.2
21.6
21.6
Ta = 25°C
Ta = 25°C
Ta = 25°C
2000
Twdt
Tset
Thold
Tdelay
Tiod
Ttrr1
Ttrf1
Ttrr2
Ttrf2
Tdrc
Watchdog timer period
Input pin setup time
11.3
16.2
0
Input pin hold time
15
45
20
25
55
Output pin delay time
I/O delay for EMI enable
Rising time for EMI enable
Falling time for EMI enable
Rising time for EMI enable
Falling time for EMI enable
ERC delay time
Cload=20pF
Cload=150pF
Cload=150pF
Cload=150pF
Cload=300pF
Cload=300pF
Ta = 25°C
50
4
5
6
190
190
380
380
1
200
200
400
400
3
210
210
420
420
5
* Data in Typ. is measured at 5V ,25°C
* N= selected prescaler ratio.
Product Specification (V1.1) 03.30.2005
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EM78P447N
8-Bit Microcontroller with OTP ROM
6.3 Device characteristic
The graphic provided in the following pages were derived based on a limited number of
samples and are shown here for reference only. The device characteristic illustrated
herein are not guaranteed for it accuracy. In some graphic, the data maybe out of the
specified warranted operating range.
Vih/Vil (Input pins with schmitt inverter)
2
1.5
1
Vih max(-40℃ to 85℃ )
Vih typ 25℃
Vih min(-40℃ to 85℃)
Vil max(-40℃ to 85℃ )
Vil typ 25℃
Vil min(-40℃ to 85℃)
0.5
0
2.5
3
3.5
4
4.5
5
5.5
Vdd(Volt)
Fig. 16 Vih, Vil of TCC, /INT, /RESET Pin
Vth (Input thershold voltage) of I/O pins
2
1.8
1.6
1.4
1.2
1
Typ 25 ℃
Max (-40 ℃ to 85
Min (-40 ℃ to 85 ℃)
0.8
0.6
0.4
0.2
0
2.5
3
3.5
4
4.5
5
5.5
VDD(Volt)
Fig. 17 Vth（Threshold Voltage）of P60~P67, P70~P77 VS. VDD
36 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
Voh/Ioh (VDD=5V)
0
-5
-10
-15
-20
-25
Min 85 ℃
Typ 25 ℃
Max -40 ℃
0
1
2
3
4
5
Voh(Volt)
Fig.18 Port5, Port6, and Port7 Voh vs. Ioh,VDD=5V
Product Specification (V1.1) 03.30.2005
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EM78P447N
8-Bit Microcontroller with OTP ROM
Voh/Ioh (VDD=3V)
0
-2
-4
-6
-8
Min 85 ℃
Typ 25 ℃
Max -40 ℃
-10
0
0.5
1
1.5
2
2.5
3
Voh(Volt)
Fig.19 Port5, Port6, and Port7 Voh vs. Ioh, VDD=3V
38 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
Vol/Iol (VDD=5V)
90
80
70
60
50
40
30
20
10
0
Max -40 ℃
Typ 25 ℃
Min 85 ℃
0
1
2
3
4
5
6
Vol(Volt)
Fig. 20 Port5, and Port6 Vol vs, Iol, VDD=5V
Product Specification (V1.1) 03.30.2005
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EM78P447N
8-Bit Microcontroller with OTP ROM
Vol/Iol (VDD=3V)
40
35
30
25
20
15
10
5
Max -40 ℃
Typ 25 ℃
Min 85 ℃
0
0
0.5
1
1.5
2
2.5
3
Vol(Volt)
Fig. 21 Port5, and Port6 Vol vs. Iol, VDD=3V
40 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
Vol/Iol (5V)
100
90
80
70
60
50
40
30
20
10
0
Max -40 ℃
Typ 25 ℃
Min 85 ℃
0
1
2
3
4
5
6
Vol(Volt)
Fig. 22 Port7 Vol vs. Iol, VDD=5V
Product Specification (V1.1) 03.30.2005
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EM78P447N
8-Bit Microcontroller with OTP ROM
Vol/Iol (3V)
45
40
35
30
25
20
15
10
5
Max -40 ℃
Typ 25 ℃
Min 85 ℃
0
0
0.5
1
1.5
2
2.5
3
Vol(Volt)
Fig. 23 Port7 Vol vs. Iol, VDD=3V
42 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
WDT Time_out
35
30
25
20
15
10
5
Max 85 ℃
Max 75 ℃
Typ 25 ℃
Min 0 ℃
Min -40 ℃
0
2
3
4
5
6
VDD (Volt)
Fig. 24 WDT Time Out Period vs. VDD, Prescaler Set to 1 : 1
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EM78P447N
8-Bit Microcontroller with OTP ROM
Cext=100pF, Typical RC OSC Frequency
1.4
1.2
1
R=3.3k
R=5.1k
R=10k
0.8
0.6
0.4
0.2
0
R=100k
2.5
3
3.5
4
4.5
5
5.5
VDD(Volt)
Fig. 25 Typical RC OSC Frequency vs. VDD （Cext=100pF, Temperature at 25 ℃）
44 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
ERC OSC Frequency vs Temp.(Cext=100pF, Rext=5.1K)
1.005
1
0.995
0.99
0.985
0.98
3V
5V
-40
-20
0
20
40
60
80
Temperature( )
℃
Fig. 26 Typical RC OSC Frequency vs. Temperature（R and C are ideal component）
Four conditions exist with the operating current ICC1 to ICC4. these conditions are as
follows：
ICC1：VDD=3V, Fosc=32 kHz, 2clock, WDT disable.
ICC2：VDD=3V, Fosc=32 kHz, 2clock, WDT enable.
ICC3：VDD=5V, Fosc=4 MHz, 2clock, WDT enable.
ICC4：VDD=5V, Fosc=10 MHz, 2clock, WDT enable.
Typical ICC1 and ICC2 vs. Temperature
21
Typ ICC2
18
Typ ICC1
15
12
9
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 27 Typical Operating Current（ICC1 and ICC2）vs. Temperature
Product Specification (V1.1) 03.30.2005
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EM78P447N
8-Bit Microcontroller with OTP ROM
Maximum ICC1 and ICC2 vs. Temperature
27
24
21
18
15
Max ICC2
Max ICC1
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 28 Maximum Operating Current（ICC1 and ICC2）vs. Temperature
Typical ICC3 and ICC4 vs. Temperature
4
3.5
3
Typ ICC4
2.5
2
Typ ICC3
1.5
1
0.5
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 29 Typical Operating Current（ICC3 and ICC4）vs. Temperature
46 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
Maximum ICC3 and ICC4 vs. Temperature
4.5
4
Max ICC4
Max ICC3
3.5
3
2.5
2
1.5
1
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 30 Maximum Operating Current（ICC3 and ICC4）vs. Temperature
Two conditions exist with the standby current ISB1 and ISB2. these conditions are as
follow：
ISB1：VDD=5V, WDT disable
ISB2：VDD=5V, WDT enable
Typical ISB1 and ISB2 vs. Temperature
12
9
Typ ISB2
6
3
Typ ISB1
0
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 31 Typical Standby Current（ISB1 and ISB2）vs. Temperature
Product Specification (V1.1) 03.30.2005
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EM78P447N
8-Bit Microcontroller with OTP ROM
Maximum ISB1 and ISB2 vs. Temperature
15
12
9
Max ISB2
6
3
Max ISB1
0
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 32 Maximum Standby Current（ISB1 and ISB2）vs. Temperature
Operating voltage (-40℃~85℃)
25
20
15
10
5
0
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (Volt)
Fig. 33 Operating Voltage In Temperature Range from -40 ℃to 85 ℃
48 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
EM78P447N HXT I-V
3
2.5
2
1.5
1
Max
Min
0.5
0
0
1
2
3
4
5
6
Volt(V)
Fig. 34 EM78P447N I-V Curve Operating at 4 MHz
EM78P447N LXT I-V
40
35
30
25
20
15
10
5
Max
Min
0
0
1
2
3
4
5
6
Volt(V)
Fig. 35 EM78P447N I-V Curve Operating at 32.768 kHz
Product Specification (V1.1) 03.30.2005
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EM78P447N
8-Bit Microcontroller with OTP ROM
APPENDIX
A Package Types
OTP MCU
EM78P447NCP
EM78P447NCM
EM78P447NDK
EM78P447NDM
EM78P447NAP
EM78P447NAM
EM78P447NAS
EM78P447NBP
EM78P447NBWM
Package Type
DIP
Pin Count
Package Size
300 mil
300 mil
300 mil
300 mil
600 mil
300 mil
209 mil
600 mil
450 mil
20
20
24
24
28
28
28
32
32
SOP
Skinny DIP
SOP
DIP
SOP
SSOP
DIP
SOP
B Package Information
20-Lead plastic dual inline package（DIP）－ 300 mil
Symbal Min Normal Max
E
A
A1
A2
c
4.450
0.381
3.175
3.302
3.429
0.203 0.254 0.356
D
25.883 26.060 26.237
E1
E
eB
B
B1
L
e
θ
6.220
7.370
8.510
6.438
7.620
9.020
6.655
7.870
9.530
0.356 0.457 0.559
1.143 1.524 1.778
3.048 3.302 3.556
2.540(TYP)
0
15
TITLE:
PDIP-20L 300M IL PACKAGE OUTLINE
DIM ENSION
File:
D20
Edtion: A
Unit:mm
Scale:Free
M aterial:
Sheet:1of1
50 •
Product Specification (V1.1) 03.30.2005
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EM78P447N
8-Bit Microcontroller with OTP ROM
24-Lead plastic dual inline skinny package（DIP）－ 300 mil
13
24
Symbal Min Normal
A
Max
5.334
E
A1
A2
c
0.381
3.175
0.203
3.302
0.254
3.429
0.356
D
31.750 31.801 31.852
E1
E
eB
B
B1
L
6.426
7.370
8.380
0.356
1.470
3.048
6.628
7.620
6.830
7.870
9.520
0.559
1.630
3.556
12
1
8.950
0.457
1.520
3.302
e
θ
2.540(TYP)
0
15
e
TITLE:
PDIP-24L SKINNY 300M IL PACKAGE
OUTLINE DIM ENSION
File:
K24
Edtion: A
Unit:mm
Scale:Free
M aterial:
Sheet:1of1
28-Lead plastic dual inline package（DIP）－ 600 mil
Product Specification (V1.1) 03.30.2005
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EM78P447N
8-Bit Microcontroller with OTP ROM
32-Lead plastic dual inline package（DIP）－ 600 mil
20-Lead plastic small outline package（SOP）－ 300 mil
Symbal
Min
2.350
0.102
Normal
Max
2.650
0.300
A
A1
b
0.406(TYP)
c
E
0.230
7.400
0.320
7.600
H
D
L
e
θ
10.000
12.600
0.630
10.650
12.900
1.100
0.838
1.27(TYP)
0
8
b
e
c
TITLE:
SOP-20L(300M IL)PACKAGE OUTLINE
DIM ENSION
File:
Edtion: A
SO20
Unit:mm
Scale:Free
M aterial:
Sheet:1of1
52 •
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EM78P447N
8-Bit Microcontroller with OTP ROM
24-Lead plastic small outline package（SOP）－ 300 mil
Symbal
Min
2.350
0.102
Normal
Max
2.650
0.300
A
A1
b
0.406(TYP)
c
E
0.230
7.400
0.320
7.600
H
D
L
10.000
15.200
0.630
10.650
15.600
1.100
0.838
e
1.27(TYP)
θ
0
8
b
e
c
TITLE:
SOP-24L(300M IL)PACKAGE OUTLINE
DIM ENSION
File:
Edtion: A
SO24
Unit:mm
Scale:Free
M aterial:
Sheet:1of1
28-Lead plastic small outline package（SOP）－ 300 mil
Product Specification (V1.1) 03.30.2005
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EM78P447N
8-Bit Microcontroller with OTP ROM
32-Lead plastic small outline package（SOP）－ 300 mil
28-Lead Shrink Small Outline Package（SSOP）－ 209 mil
54 •
Product Specification (V1.1) 03.30.2005
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