FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-27401-7E
ASSP
Power Supply Monitor
with Watch-Dog Timer
MB3773
■ DESCRIPTION
MB3773 generates the reset signal to protect an arbitrary system when the power-supply voltage momentarily is
intercepted or decreased. It is IC for the power-supply voltage watch and “Power on reset” is generated at the
normal return of the power supply. MB3773 sends the microprocessor the reset signal when decreasing more
than the voltage, which the power supply of the system specified, and the computer data is protected from an
accidental deletion.
In addition, the watchdog timer for the operation diagnosis of the system is built into, and various microprocessor
systems can provide the fail-safe function. If MB3773 does not receive the clock pulse from the processor for an
specified period, MB3773 generates the reset signal.
■ FEATURES
• Precision voltage detection (VS = 4.2 V ± 2.5 %)
• Detection threshold voltage has hysteresis function
• Low voltage output for reset signal (VCC = 0.8 V Typ)
• Precision reference voltage output (VR = 1.245 V ± 1.5%)
• With built-in watchdog timer of edge trigger input.
• External parts are few.(1 piece in capacity)
• The reset signal outputs the positive and negative both theories reason.
■ PACKAGES
(FPT-8P-M01)
(SIP-8P-M03)
(DIP-8P-M01)
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields.
However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages
to this high impedance circuit.
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MB3773
■ BLOCK DIAGRAM
VCC
5
Reference AMP.
=: 1.24 V
=: 1.24 V
Reference Voltage Generator
+
_
VREF
6
=: 100
=: 1.2 µA
COMP.O
kΩ
=: 10 µA
+
_
+
_
=: 10 µA
COMP.S
+
_
R
S
Q
VS
7
=: 40 kΩ
Inhibit
Watch
Dog
CK
3
Timer
P.G
4
GND
2
1
8
CT
RESET
RESET
3
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MB3773
■ FUNCTIONAL DESCRIPTIONS
Comp.S is comparator including hysteresis. it compare the reference voltage and the voltage of Vs, so that when
the voltage of Vs terminal falls below approximately 1.23 V, reset signal outputs.
Instantaneous breaks or drops in the power can be detected as abnormal conditions by the MB3773 within a
2 µs interval.
However because momentary breaks or drops of this duration do not cause problems in actual systems in some
cases, a delayed trigger function can be created by connecting capacitors to the Vs terminal.
Comp.O is comparator for turning on/off the output and, compare the voltage of the Cr terminal and the threshold
voltage. Because the RESET/RESET outputs have built-in pull-up circuit, there is no need to connect to external
pull-up resistor when connected to a high impedance load such as CMOS logic IC.
(It corresponds to 500 kΩ at Vcc = 5 V.) when the voltage of the CK terminal changes from the “high” level into
the “Low” level, pulse generator is sent to the watch-dog timer by generating the pulse momentarily at the time
of drop from the threshold level.
When power-supply voltages fall more than detecting voltages, the watch-dog timer becomes a interdiction.
The Reference amplifier is a op-amp to output the reference voltage.
If the comparator is put up outside, two or more power-supply voltage monitor and overvoltage monitor can be
done.
If it uses a comparator of the open-collector output, and the output of the comparator is connected with the Vs
terminal of MB3773 without the pull-up resistor, it is possible to voltage monitor with reset-hold time.
4
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MB3773
• MB3773 Basic Operation
VCC
VCC
Logic Circuit
TPR (ms) =: 1000 · CT (µF)
TWD (ms) =: 100 · CT (µF)
RESET
RESET
CK
CT
RESET
RESET
CK
TWR (ms) =:
20 · CT (µF)
Example : CT = 0.1 µF
TRR (ms) =: 100 (ms)
GND
TWD (ms) =: 10 (ms)
TWR (ms) =: 2 (ms)
VCC
VSH
VSL
0.8 V
CK
TCK
CT
TPR
RESET
TWD
TWR
TPR
(1) (2)
(3)(4)(5)
(5)
(6)(7)
(8)(9)
(10)
(11) (12)
5
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MB3773
■ OPERATION SEQUENCE
(1) When Vcc rises to about 0.8 V, RESET goes “Low” and RESET goes “High”.
The pull-up current of approximately 1 µA (Vcc = 0.8 V) is output from RESET.
(2) When Vcc rises to VSH (=: 4.3V) , the charge with CT starts.
At this time, the output is being reset.
(3) When CT begins charging, RESET goes “High” and RESET goes “Low”.
After TPR reset of the output is released.
Reset hold time: TPR (ms) =: 1000 × CT (µF)
After releasing reset, the discharge of CT starts, and watch-dog timer operation starts.
TPR is not influenced by the CK input.
(4) C changes from the discharge into the charge if the clock (Negative edge) is input to the CK terminal
while discharging CT.
(5) C changes from the charge into the discharge when the voltage of CT reaches a constant
threshold (=: 1.4 V) .
(4) and (5) are repeated while a normal clock is input by the logic system.
(6) When the clock is cut off, gets, and the voltage of CT falls on threshold (=: 0.4 V) of reset on, RESET goes
“Low” and RESET goes “High”.
Discharge time of CT until reset is output: TWD is watch-dog timer monitoring time.
TWD (ms) =: 100 × CT (µF)
Because the charging time of CT is added at accurate time from stop of the clock and getting to the output
of reset of the clock, TWD becomes maximum TWD + TWR by minimum TWD.
(7) Reset time in operating watch-dog timer:TWR is charging time where the voltage of CT goes up to off
threshold (=: 1.4 V) for reset.
TWR (ms) =: 20 × CT (µF)
Reset of the output is released after CT reaches an off threshold for reset, and CT starts the discharge,
after that if the clock is normally input, operation repeats (4) and (5) , when the clock is cut off, operation
repeats (6) and (7) .
(8) When Vcc falls on VSL (=: 4.2 V) , reset is output. CT is rapidly discharged of at the same time.
(9) When Vcc goes up to VSH, the charge with CT is started.
When Vcc is momentarily low,
After falling VSL or less Vcc, the time to going up is the standard value of the Vcc input pulse width in VSH or
more.
After the charge of CT is discharged, the charge is started if it is TPI or more.
(10) Reset of the output is released after TPR, after Vcc becomes VSH or more, and the watch-dog timer starts.
After that, when Vcc becomes VSL or less, (8) to (10) is repeated.
(11) While power supply is off, when Vcc becomes VSL or less, reset is output.
(12) The reset output is maintained until Vcc becomes 0.8 V when Vcc falls on 0 V.
6
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MB3773
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Supply voltage
Symbol
Unit
Min
− 0.3
− 0.3
− 0.3
− 0.3
Max
VCC
VS
+ 18
V
VCC + 0.3 ( ≤ +18)
V
V
Input voltage
VCK
VOH
PD
+ 18
VCC + 0.3 ( ≤ +18)
200
RESET, RESET Supply voltage
Power dissipation (Ta ≤ +85 °C)
Storage temperature
V
mW
°C
TSTG
− 55
+ 125
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Min
+ 3.5
0
Max
+ 16
20
Supply voltage
VCC
IOL
V
RESET, RESET sink current
VREF output current
mA
µA
ms
µs
IOUT
tWD
− 200
0.1
+ 5
Watch clock setting time
CK Rising/falling time
1000
100
10
tFC, tRC
CT
Terminal capacitance
0.001
µF
°C
Operating ambient temperature
Ta
− 40
+ 85
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
7
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MB3773
■ ELECTORICAL CHARACTERISTICS
(1) DC Characteristics
(VCC = 5 V, Ta = + 25 °C)
Value
Parameter
Supply current
Symbol
ICC
Condition
Unit
Min
Typ
600
Max
900
Watch dog timer operating
µA
VCC
4.10
4.05
4.20
4.15
50
4.20
4.20
4.30
4.30
100
4.30
4.35
4.40
4.45
150
VSL
Ta = − 40 °C to + 85 °C
Detection voltage
V
VCC
VSH
VHYS
VREF
Ta = − 40 °C to + 85 °C
Hysteresis width
VCC
mV
V
1.227 1.245 1.263
1.215 1.245 1.275
Reference voltage
Ta = − 40 °C to + 85 °C
VCC = 3.5 V to 16 V
Reference voltage change rate
∆VREF1
3
10
mV
mV
V
Reference voltage output
loading change rate
∆VREF2
IOUT = − 200 µA to + 5 µA
− 5
+ 5
CK threshold voltage
VTH
IIH
Ta = − 40 °C to + 85 °C
VCK = 5.0 V
0.8
1.25
0
2.0
1.0
CK input current
µA
µA
V
IIL
VCK = 0.0 V
− 1.0 − 0.1
Watch dog timer operating
VCT = 1.0 V
CT discharge current
ICTD
7
10
14
VOH1
VOH2
VOL1
VOL2
VOL3
VOL4
IOL1
VS open, IRESET = − 5 µA
VS = 0 V, IRESET = − 5 µA
VS = 0 V, IRESET = 3 mA
VS = 0 V, IRESET = 10 mA
VS open, IRESET = 3 mA
VS open, IRESET = 10 mA
VS = 0 V, VRESET = 1.0 V
VS open, VRESET = 1.0 V
4.5
4.5
4.9
4.9
0.2
0.3
0.2
0.3
60
High level output voltage
0.4
0.5
0.4
0.5
Output saturation voltage
Output sink current
V
20
20
mA
IOL2
60
Power on reset operating
VCT = 1.0 V
CT charge current
ICTU
0.5
1.2
0.8
0.8
2.5
1.2
1.2
µA
V
VRESET = 0.4 V,
IRESET = 0.2 mA
Min supply voltage for RESET
Min supply voltage for RESET
VCCL1
VCCL2
VRESET = VCC − 0.1 V,
RL (pin 2 − GND) = 1 MΩ
V
8
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MB3773
(2)AC Characteristics
Parameter
(VCC = 5 V, Ta = + 25 °C)
Value
Symbol
TPI
Condition
Unit
Min
Typ Max
5 V
4 V
VCC input pulse width
CK input pulse width
8.0
3.0
µs
µs
VCC
CK
TCKW
or
CK input frequency
TCK
TWD
TWR
20
5
µs
ms
ms
Watch dog timer watching time
Watch dog timer reset time
CT = 0.1 µF
CT = 0.1 µF
10
2
15
3
1
Rising reset hold time
TPR
TPD1
TPD2
tR
50
100
2
150 ms
CT = 0.1 µF, V CC
RESET, RL = 2.2 kΩ,
CL = 100 pF
10
µs
10
Output propagation
delay time from VCC
RESET, RL = 2.2 kΩ,
CL = 100 pF
3
RL = 2.2 kΩ,
CL = 100 pF
Output rising time*
Output falling time*
1.0
0.1
1.5
µs
0.5
RL = 2.2 kΩ,
CL = 100 pF
tF
* : Output rising/falling time are measured at 10 % to 90 % of voltage.
9
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MB3773
■ TYPICAL CHARACTERISTIC CURVES
Supply current vs. Supply voltage
Output voltage vs. Supply voltage
(RESET terminal)
6.0
0.75
Ta =+85 °C
Ta =+25 °C
Pull up 2.2 kΩ
0.65
5.0
Ta = −40 °C, +25 °C, +85 °C
Ta =-40 °C
0.55
0.45
0.35
4.0
3.0
2.0
1.0
CT =0.1 mF
Ta =-40 °C
Ta =+25 °C
Ta =+85 °C
0.25
0.15
0
1.0
2.0
3.0
4.0
5.0
6.0 7.0
0
2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0
Supply voltage VCC (V)
Supply voltage VCC (V)
Detection voltage
Output voltage vs. Supply voltage
(VSH, VSL) vs. Temperature
(RESET terminal)
(RESET, RESET terminal)
4.50
6.0
5.0
Pull up 2.2 kΩ
VSH
VSL
4.44
4.30
4.20
4.10
4.0
3.0
2.0
1.0
Ta =+85 °C
Ta =+25 °C
Ta =-40 °C
4.00
0
1.0 2.0
3.0 4.0
5.0
6.0
7.0
-40 -20
0
20
40
60
80 100
Supply voltage VCC (V)
Temperature Ta ( °C)
Output saturation voltage
vs. Output sink current
Output saturation voltage
vs. Output sink current
(RESET terminal)
(RESET terminal)
500
400
300
200
C T =0.1mF
Ta =-40 °C
CT =0.1mF
400
Ta =-40 °C
300
200
100
Ta =+25 °C
Ta =+85 °C
Ta =+25 °C
Ta =+85 °C
100
0
2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0
0
2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0
Output sink current IOL8 (mA)
Output sink current IOL2 (mA)
(Continued)
10
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MB3773
High level output voltage
vs. High level output current
High level output voltage
vs. High level output current
(RESET terminal)
(RESET terminal)
5.0
4.5
5.0
4.5
CT =0.1 mF
CT =0.1 mF
Ta =+25 °C
Ta =+85 °C
Ta =+25 °C
Ta =+85 °C
Ta =-40 °C
Ta =-40 °C
4.0
4.0
0
-5
-10
-15
0
-5
-10
-15
High level output current IOH8 (µA)
High level output current IOH2 (µA)
Reference voltage
vs. Supply voltage
Reference voltage
vs. Reference current
1.255
1.250
1.246
1.244
1.242
1.240
1.238
1.236
1.234
CT =0.1 mF
Ta =+25 °C
Ta =+85 °C
Ta =-40 °C
CT =0.1 mF
Ta =+25 °C
1.245
1.240
Ta =+85 °C
Ta =-40 °C
0
-40
-80
-120
-160
-200 -240
0
3.0 5.0 7.0 9.0 11.0 13.0 15.0 17.0 19.0 21.0
Supply voltage VCC (V)
Reference current IREF (µA)
Reference voltage
vs. Temperature
Rising reset hold time
vs. Temperature
1.27
160
VCC =5 V
CT =0.1 mF
1.26
1.25
140
120
100
80
1.24
1.23
1.22
1.21
60
40
0
-40 -20
0
20 40 60 80 100
-40 -20
0
20 40 60 80 100
Temperature Ta ( °C)
Temperature Ta ( °C)
(Continued)
11
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MB3773
(Continued)
Reset time vs.
Temperature
Watchdog timer watching time
vs. Temperature
(At watch dog timer)
16
14
VCC = 5 V
CT = 0.1 mF
VCC =5 V
CT =0.1 mF
3
2
12
10
8
1
6
4
0
0
-40 -20
0
20 40
60
80 100
-40 -20
0
20
40
60
80 100
Temperature Ta ( °C)
Temperature Ta ( °C)
C
T
terminal capacitance
vs.
CT
terminal capacitance
vs. Reset time
C
T
terminal capacitance
vs. Rising reset hold time
Watchdog timer watching time
(at watch dog timer)
10 6
10 5
10 4
10 6
10 5
10 4
10 2
10 1
10 0
10 3
10 3
Ta =+25 °C
+85 °C
Ta =-40 °C
10 2
10 2
Ta =
Ta =-40 °C
+25 °C +85 °C
10 1
10 1
Ta =
Ta =+25 °C +85 °C
10 -1
10 -2
10 -3
-40 °C
10 0
10 -1
10 -2
10 0
10 -1
10 -2
10 -3
10 -3
10 - 10 - 10 - 10 0 10 1 10 2
3
2
1
10 -3 10 -2 10 -1 10 0 10 1 10 2
10 -3 10 -2 10 -1 10 0 10 1 10 2
CT
terminal capacitance CT (µF)
C
T
terminal capacitance CT (µF)
C
T
terminal capacitance CT (µF)
12
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MB3773
■ APPLICATION CIRCUIT
EXAMPLE 1: Monitoring 5V Supply Voltage and Watchdog Timer
VCC (5V)
MB3773
Logic circuit
8
7
6
5
1
2
3
4
RESET
RESET
CK
CT
GND
Notes : • Supply voltage is monitored using VS.
• Detection voltage are VSH and VSL.
EXAMPLE 2: 5V Supply Voltage Monitoring (external fine-tuning type)
VCC (5V)
MB3773
R1
R2
Logic circuit
RESET
1
2
3
4
8
7
6
5
RESET
CK
CT
GND
Notes : • Vs detection voltage can be adjusted externally.
• Based on selecting R1 and R2 values that are sufficiently lower than the resistance of the IC’s
internal voltage divider, the detection voltage can be set according to the resistance ratio of
R1 and R2 (See the table below.)
R1 (kΩ)
10
R2 (kΩ)
3.9
Detection voltage: VSL (V)
Detection voltage: VSH (V)
4.4
4.1
4.5
4.2
9.1
3.9
13
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MB3773
EXAMPLE 3: With Forced Reset (with reset hold)
(a)
VCC
MB3773
Logic circuit
1
2
3
4
8
7
6
5
RESET
RESET
CK
CT
SW
GND
Note : Grounding pin 7 at the time of SW ON sets RESET (pin 8) to Low and RESET (pin 2) to High.
(b)
VCC
MB3773
Logic circuit
1
2
3
4
8
7
6
5
RESET
RESET
CK
Tr
10 kΩ
10 kΩ
Cr
GND
RESIN
Note : Feeding the signal to terminal RESIN and turning on Tr sets the RESET terminal to Low and
the RESET terminal to High.
14
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MB3773
EXAMPLE 4: Monitoring Two Supply Voltages (with hysteresis, reset output and NMI)
VCC2(12 V)
VCC1 (5 V)
Logic circuit
MB3773
RESET
1
2
3
4
8
7
6
5
RESET
CK
CT
30 kΩ
R3
NMI or port
GND
180 kΩ
10 kΩ
R4
R6
+
+
_
_
Comp. 1
1.2 kΩ
R1
Comp. 2
4.7 kΩ
5.1 kΩ
R2
R5
Example : Comp. 1, Comp. 2
: MB4204, MB47393
Notes : • The 5 V supply voltage is monitored by the MB3773.
• The 12 V supply voltage is monitored by the external circuit. Its output is connected to the NMI
terminal and, when voltage drops, Comp. 2 interrupts the logic circuit.
• Use VCC1 ( = 5 V) to power the comparators (Comp. 1 and Comp. 2) in the external circuit shown
above.
• The detection voltage of the VCC2 ( = 12 V) supply voltage is approximately 9.2 V/9.4 V and has
a hysteresis width of approximately 0.2 V.
VCC2 detection voltage and hysteresis width can be found using the following formulas:
R3 + (R4 // R5)
→ Detection voltage
× VREF
V2H =
V2L =
R4 // R5
R3 + R5
R5
(Approximately 9.4 V in the above illustration)
(Approximately 9.2 V in the above illustration)
× VREF
→ Hysteresis width VHYS = V2H − V2L
15
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MB3773
EXAMPLE 5: Monitoring Two Supply Voltages (with hysteresis and reset output)
VCC2 (12 V)
VCC1 (5 V)
20 kΩ
Logic circuit
RESET
MB3773
R6
1
2
3
4
8
7
6
5
RESET
CK
30 kΩ
Diode
CT
R3
GND
180 kΩ
R4
+
+
_
_
Comp. 1
1.2 kΩ
Comp. 2
R1
5.1 kΩ
4.7 kΩ
R5
R2
Example : Comp. 1, Comp. 2
: MB4204, MB47393
Notes : • When either 5 V or 12 V supply voltage decreases below its detection voltage (VSL),
the MB3773 RESET terminal is set to High and the MB3773 RESET terminal is set to Low.
• Use VCC1 ( = 5 V) to power the comparators (Comp. 1 and Comp. 2) in the external circuit shown
above.
• The detection voltage of the VCC2 ( = 12 V) supply voltage is approximately 9.2 V/9.4 V and has a
hysteresis width of approximately 0.2 V. For the formulas for finding hysteresis width and detection
voltage, see section 4.
16
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MB3773
EXAMPLE 6: Monitoring Low voltage and Overvoltage Monitoring (with hysteresis)
VCC (5 V)
20 kΩ
R6
MB3773
Logic circuit
1
2
3
4
8
7
6
5
RESET
RESET
CK
30 kΩ
Diode
CT
R3
GND
180 kΩ
R4
+
_
+
_
Comp. 1
1.2 kΩ
R1
Comp. 2
5.6 kΩ
4.7 kΩ
R6
R5
Example : Comp. 1, Comp. 2
: MB4204, MB47393
RESET
VCC
0
V2L V2H
V1L V1H
Notes : • Comp. 1 and Comp. 2 are used to monitor for overvoltage while the MB3773 is used to monitor
for low voltage. Detection voltages V1L/V1H at the time of low voltage are approximately 4.2 V/4.3 V.
Detection voltages V2L/V2H at the time of overvoltage are approximately 6.0 V/6.1 V.
For the formulas for finding hysteresis width and detection voltage, see EXAMPLE 4.
• Use VCC ( = 5 V) to power the comparators (Comp. 1 and Comp. 2) in the external circuit shown
above.
17
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MB3773
EXAMPLE 7: Monitoring Supply Voltage Using Delayed Trigger
VCC
VCC
5V
4V
MB3773
Logic circuit
1
2
3
4
8
7
6
5
RESET
RESET
CK
CT
C1
GND
Note : Adding voltage such as shown in the figure to VCC increases the minimum input pulse
width by 50 µs (C1 = 1000 pF).
18
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MB3773
EXAMPLE 8: Stopping Watch-dog Timer (Monitoring only supply voltage)
These are example application circuits in which the MB3773 monitors supply voltage alone without resetting the
microprocessor even if the latter, used in standby mode, stops sending the clock pulse to the MB3773.
• The watch-dog timer is inhibited by clamping the CT terminal voltage to VREF.
The supply voltage is constantly monitored even while the watch-dog timer is inhibited.
For this reason, a reset signal is output at the occurrence of either instantaneous disruption or a sudden drop
to low voltage.
Note that in application examples (a) and (b), the hold signal is inactive when the watch-dog timer is inhibited at
the time of resetting.
If the hold signal is active when tie microprocessor is reset, the solution is to add a gate, as in examples (c)
and (d).
(a) Using NPN transistor
VCC(5 V)
MB3773
Logic circuit
1
2
3
4
8
7
6
5
RESET
RESET
CK
HALT
GND
R2=1 kΩ
R1=1 MΩ
CT
(b) Using PNP transistor
VCC (5 V)
MB3773
Logic circuit
1
8
7
6
5
RESET
RESET
CK
2
3
4
HALT
GND
R2=1 kΩ
R1=51 kΩ
CT
(Continued)
19
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MB3773
(Continued)
(c) Using NPN transistor
VCC (5 V)
MB3773
Logic circuit
1
2
3
4
8
7
6
5
RESET
RESET
CK
R1=1 MΩ
HALT
GND
R2=1 kΩ
CT
(d) Using PNP transistor
VCC (5 V)
MB3773
Logic circuit
1
2
3
4
8
7
6
5
RESET
RESET
CK
R1=51 kΩ
HALT
GND
R2=1 kΩ
CT
20
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MB3773
EXAMPLE 9: Reducing Reset Hold Time
VCC( = 5 V)
VCC ( = 5 V)
MB3773
MB3773
Logic circuit
RESET
Logic circuit
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
RESET
RESET
CK
RESET
CK
CT
CT
GND
GND
(a) TPR reduction method
(b) Standard usage
Notes : • RESET is the only output that can be used.
• Standard TPR, TWD and TWR value can be found using the following formulas.
Formulas: TPR (ms) =: 100 × CT (µF)
TWD (ms) =: 100 × CT (µF)
TWR (ms) =: 16 × CT (µF)
• The above formulas become standard values in determining TPR, TWD and TWR.
Reset hold time is compared below between the reduction circuit and the standard circuit.
CT = 0.1 µF
TPR reduction circuit
10 ms
Standard circuit
100 ms
TPR =:
TWD =:
TWR =:
10 ms
10 ms
1.6 ms
2.0 ms
21
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MB3773
EXAMPLE 10: Circuit for Monitoring Multiple Microprocessor
VCC ( = 5 V)
FF1
FF2
FF3
S
S
S
D1 Q1
D2 Q2
D3 Q3
CK1 Q1
CK2 Q2
CK3 Q3
R
R
R
R2
R1
*
*
*
RESET
RESET
RESET
RESET
CK
RESET
CK
RESET
CK
GND
GND
GND
1
2
8
7
3
4
6
5
CT
Figure 1
*: Microprocessor
Notes : •
MB3773
connects from FF1 and FF2 outputs Q1 and Q2 to the NOR input.
• Depending on timing, these connections may not be necessary.
• Example : R1 = R2 = 2.2 kΩ
CT = 0.1 µF
CK1
Q1
CK2
Q2
CK3
Q3
NOR
Output
Figure 2
22
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MB3773
Description of Application Circuits
Using one MB3773, this application circuit monitors multiple microprocessor in one system. Signals from each
microprocessor are sent to FF1, FF2 and FF3 clock inputs. Figure 2 shows these timings. Each flip-flop operates
using signals sent from microprocessor as its clock pulse. When even one signal stops, the relevant receiving
flip-flop stops operating. As a result, cyclical pulses are not generated at output Q3. Since the clock pulse stops
arriving at the CK terminal of the MB3773, the MB3773 generates a reset signal.
Note that output Q3 frequency f will be in the following range, where the clock frequencies of CK1, CK2 and CK3
are f1, f2 and f3 respectively.
1
f0
1
f
1
1
1
---- ≤-- ≤
+
+
---- ---- ----
f1 f2 f3
where f0 is the lowest frequency among f1, f2 and f3
.
23
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MB3773
EXAMPLE 11: Circuit for Limiting Upper Clock Input Frequency
VCC (5 V)
R2
RESET
1
2
3
4
8
7
6
5
RESET
CT
R1=10 kΩ
CK
GND
Tr1
C2
Notes : • This is an example application to limit upper frequency fH of clock pulses sent from
the microprocessor.
If the CK cycle sent from the microprocessor exceeds fH, the circuit generates a reset signal.
(The lower frequency has already been set using CT.)
• When a clock pulse such as shown below is sent to terminal CK, a short T2 prevents C2 voltage
from reaching the CK input threshold level (=: 1.25 V), and will cause a reset signal to be output.
The T1 value can be found using the following formula :
T1 =: 0.3 C2R2
where VCC = 5 V, T3 ≥ 3.0 µs, T2 ≥ 20 µs
T2
CK waveform
T3
C2 voltage
T1
Example : Setting C and R allow the upper T1 value to be set (See the table below).
C
R
T1
0.01 µF
0.1 µF
10 kΩ
10 kΩ
30 µs
300 µs
24
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MB3773
■ NOTES ON USE
• Take account of common impedance when designing the earth line on a printed wiring board.
• Take measures against static electricity.
- For semiconductors, use antistatic or conductive containers.
- When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container.
- The work table, tools and measuring instruments must be grounded.
- The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series.
• Do not apply a negative voltage
- Applying a negative voltage of −0.3 V or less to an LSI may generate a parasitic transistor, resulting in
malfunction.
■ ORDERING INFORMATION
Part number
Package
Remarks
8-pin plastic DIP
(DIP-8P-M01)
MB3773P
MB3773PS
MB3773PF
8-pin plastic SIP
(SIP-8P-M03)
8-pin plastic SOP
(FPT-8P-M01)
25
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MB3773
■ PACKAGE DIMENSIONS
8-pin plastic DIP
(DIP-8P-M01)
+0.40
–0.30
9.40
.370 +.016
–.012
1 PIN INDEX
6.20±0.25
(.244±.010)
0.51(.020)MIN
4.36(.172)MAX
3.00(.118)MIN
+0.30
0.25±0.05
(.010±.002)
0.46±0.08
(.018±.003)
+0.30
–0
15°MAX
0.99
1.52
–0
7.62(.300)
TYP
.039 +.012
–0
.060 +.012
–0
+0.35
–0.30
0.89
2.54(.100)
TYP
.035 +.014
–.012
C
1994 FUJITSU LIMITED D08006S-2C-3
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
(Continued)
26
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MB3773
Note 1 : *1 : These dimensions include resin protrusion.
8-pin plastic FPT
(FPT-8P-M01)
Note 2 : *2 : These dimensions do not include resin protrusion.
Note 3 : Pins width and pins thickness include plating thickness.
Note 4 : Pins width do not include tie bar cutting remainder.
*1 6.35 +0.25
–0.20
.250 +.010
–.008
0.17 +0.03
.007 +.001
–0.04
–.002
8
5
*2 5.30±0.30 7.80±0.40
(.209±.012) (.307±.016)
INDEX
Details of "A" part
2.00 +0.25
–0.15
(Mounting height)
.079 +.010
–.006
0.25(.010)
0~8˚
"A"
1
4
1.27(.050)
0.47±0.08
(.019±.003)
M
0.13(.005)
0.50±0.20
(.020±.008)
0.10 +0.10
.004 +.004
(Stand off)
–0.05
–.002
0.60±0.15
(.024±.006)
0.10(.004)
C
2002 FUJITSU LIMITED F08002S-c-6-7
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
(Continued)
27
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MB3773
(Continued)
8-pin plastic SIP
(SIP-8P-M03)
3.26±0.25
(.128±.010)
+0.15
–0.35
19.65
.774 +.006
–.014
INDEX-1
6.20±0.25
(.244±.010)
8.20±0.30
(.323±.012)
INDEX-2
+0.30
–0
0.99
4.00±0.30
(.157±.012)
.039 +.012
–0
+0.30
–0
1.52
2.54(.100)
TYP
0.50±0.08
(.020±.003)
0.25±0.05
(.010±.002)
.060 +.012
–0
C
1994 FUJITSU LIMITED S08010S-3C-2
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
28
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MB3773
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
F0308
FUJITSU LIMITED Printed in Japan
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