Cypress Computer Hardware CY7C67300 User Manual

CY7C67300

EZ-Host™ Programmable Embedded USB Host and

Peripheral Controller with Automotive AEC Grade Support

EZ-Host Features

■ Single chip programmable USB dual-role (Host/Peripheral)

controller with two configurable Serial Interface Engines (SIEs)

and four USB ports

■ On-chip 16-bit DMA/mailbox data path interface

■ Supports 12 MHz external crystal or clock

■ 3.3V operation

■ Support for USB On-The-Go (OTG) protocol

■ Automotive AEC grade option (–40°C to 85°C)

■ Package option—100-pin TQFP

■ On-chip 48 MHz 16-bit processor with dynamically switchable

clock speed

■ Configurable IO block supporting a variety of IO options or up

to 32 bits of General Purpose IO (GPIO)

Typical Applications

EZ-Host is a very powerful and flexible dual role USB controller

that supports a wide variety of applications. It is primarily

intended to enable host capability in applications such as:

■ 4K x 16 internal masked ROM containing built in BIOS that

supports a communication ready state with access to I C™

EEPROM Interface, external ROM, UART, or USB

■ 8K x 16 internal RAM for code and data buffering

■ Extended memory interface port for external SRAM and ROM

■ Set top boxes

■ Printers

■ KVM switches

■ Kiosks

■ 16-bit parallel Host Port Interface (HPI) with a DMA/mailbox

data path for an external processor to directly access all of the

on-chip memory and control on-chip SIEs

■ Automotive applications

■ Wireless access points

■ Fast serial port supports from 9600 baud to 2.0M baud

■ SPI support in both master and slave

CY7C67300 Block Diagram

CY7C67300

Timer 0

Timer 1

nRESET

Control

UART I/F

I2C

EEPROM I/F

Watchdog

CY16

16-bit RISC CORE

HSS I/F

Vbus, ID

D+,D-

OTG

PWM

USB-A

GPIO [31:0]

SIE1

SPI I/F

IDE I/F

HPI I/F

D+,D-

USB-B

Host/

Peripheral

USB Ports

USB-A

4Kx16

ROM BIOS

8Kx16

RAM

SIE2

D+,D-

USB-B

GPIO

External MEM I/F

(SRAM/ROM)

Mobile

Power

PLL

Booster

SHARED INPUT/OUTPUT PINS

A[15:0]

D[15:0] CTRL[9:0]

Cypress Semiconductor Corporation

Document #: 38-08015 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 28, 2008

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Table 1. Interface Options for GPIO Pins (continued)

GPIO Pins

GPIO10

GPIO9

GPIO8

GPIO7

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

HPI

D10

IDE

D10

PWM

HSS

SPI

UART

I2C

OTG

[1]

SCK

nSSI

[1]

MISO

Table 2. Interface Options for External Memory Bus Pins

MEM Pins

D15

HPI

IDE

PWM

HSS

SPI

UART

I2C

OTG

[2]

CTS

RTS

RXD

[2]

D14

D13

D12

D11

D10

[2]

TXD

[2]

MOSI

[2]

SCK

nSSI

[2]

MISO

D[7:0]

A[18:0]

CONTROL

USB Interface

EZ-Host has two built in Host/Peripheral SIEs and four USB transceivers that meet the USB 2.0 specification requirements for full and

low speed (high speed is not supported). In Host mode, EZ-Host supports four downstream ports, each support control, interrupt, bulk,

and isochronous transfers. In Peripheral mode, EZ-Host supports one peripheral port with eight endpoints for each of the two SIEs.

Endpoint 0 is dedicated as the control endpoint and only supports control transfers. Endpoints 1 though 7 support interrupt, bulk (up

to 64 bytes/packet), or isochronous transfers (up to 1023 Bytes/packet size). EZ-Host also supports a combination of Host and

Peripheral ports simultaneously as shown in T a ble 3.

Table 3. USB Port Configuration Options

Port Configurations

Port 1A

OTG

Host

Port 1B

Port 2A

Port 2B

OTG

–

Host

–

Host

–

OTG + 2 Hosts

OTG + 1 Host

OTG + 1 Peripheral

4 Hosts

–

Host

–

Peripheral

–

Peripheral

Host

3 Hosts

Any Combination of Ports

Any Port

2 Hosts

1 Host

Note

2. Alternate interface location.

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Table 3. USB Port Configuration Options (continued)

Port Configurations

2 Hosts + 1 Peripheral

Port 1A

Port 1B

Port 2A

Port 2B

Host

Peripheral

–

2 Hosts + 1 Peripheral

1 Host + 1 Peripheral

2 Peripherals

Host

–

Peripheral

–

Host

–

Peripheral

Host

–

Peripheral

–

Host

–

Peripheral

–

Host

–

Peripheral

–

Host

Peripheral

–

Peripheral

–

Host

–

Peripheral

–

Host

–

Peripheral

–

Host

–

Host

–

Peripheral

–

2 Peripherals

Peripheral

–

Peripheral

–

2 Peripherals

–

Peripheral

2 Peripherals

Peripheral

1 Peripheral

Any Port

USB Features

OTG Interface

EZ-Host has one USB port that is compatible with the USB

On-The-Go supplement to the USB 2.0 specification. The USB

OTG port has a various hardware features to support Session

Request Protocol (SRP) and Host Negotiation Protocol (HNP).

OTG is only supported on USB PORT 1A.

■ USB 2.0-compliant for full and low speed

■ Up to four downstream USB host ports

■ Up to two upstream USB peripheral ports

■ Configurable endpointbuffers (pointerand length), must reside

in internal RAM

OTG Features

■ Internal charge pump to supply and control VBUS

■ VBUS valid status (above 4.4V)

■ Up to eight available peripheral endpoints (one control

endpoint)

■ Supports control, interrupt, bulk, and isochronous transfers

■ Internal DMA channels for each endpoint

■ VBUS status for 2.4V< VBUS <0.8V

■ ID pin status

■ Internal pull up and pull down resistors

■ Switchable 2K ohm internal discharge resistor on VBUS

■ Switchable 500 ohm internal pull up resistor on VBUS

■ Internal series termination resistors on USB data lines

USB Pins

■ Individually switchable internal pull up and pull down resistors

on the USB data lines

Table 4. USB Interface Pins

OTG Pins

Pin Name

Pin Number

DM1A

DP1A

DM1B

DP1B

DM2A

DP2A

DM2B

DP2B

Table 5. OTG Interface Pins

Pin Name

Pin Number

DM1A

DP1A

OTGVBUS

OTGID

CSwitchA

CSwitchB

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Merge Mode

External Memory Interface

Merge modes enabled through the External Memory Control

accordance with the following:

EZ-Host provides a robust interface to a wide variety of external

memory arrays. All available external memory array locations

can contain either code or data. The CY16 RISC processor

directly addresses a flat memory space from 0x0000 to 0xFFFF.

■ nXMEMSEL is active from 0x8000 to 0xBFFF

External Memory Interface Features

■ nXRAMSELisactivefrom0x4000to0x7FFFwhenRAMMerge

is disabled; nXRAMSEL is active from 0x4000 to 0xBFFF when

RAM Merge is enabled

■ Supports 8-bit or 16-bit SRAM or ROM

■ SRAM or ROM can be used for code or data space

■ Direct addressing of SRAM or ROM

■ nXROMSEL is active from 0xC100 to 0xDFFF when ROM

Merge is disabled; nXROMSEL is active from 0x8000 to

0xDFFF (excluding the 0xC000 to 0xC0FF area) when ROM

Merge is enabled

■ Two external memory mapped page registers

External Memory Access Strobes

Program Memory Hole Description

Access to external memory is sampled asynchronously on the

rising edge of strobes with a minimum of one wait state cycle. Up

to seven wait state cycles may be inserted for external memory

access. Each additional wait state cycle stretches the external

memory access time by 21 ns (you must be running in internal

memory when changing wait states). An external memory device

with 12 ns access time is necessary to support 48 MHz code

execution.

Code residing in the 0xC000-0xC0FF address space is not

accessible by the CPU.

DMA to External Memory Prohibited

EZ-Host supports an internal DMA engine to rapidly move data

between different functional blocks within the chip. This DMA

engine is used for SIE1, SIE2, HPI, SPI, HSS, and IDE but it can

only transfer data between the specified block and internal RAM

or ROM. Setting up the DMA engine to transfer to or from an

external memory space might result in internal RAM data

Page Registers

EZ-Host allows extended data or program code to be stored in

external SRAM, or ROM. The total size of extended memory can

be up to 512K bytes. The CY16 processor can access extended

memory via two address regions of 0x8000-0x9FFF and

0xA000-0xBFFF. The page register 0xC018 can be used to

control the address region 0x8000-0x9FFF and the page register

0xC01A controls the address region of 0xA000-0xBFFF.

corruption

because

the

hardware

(for

example,

HSS/HPI/SIE1/SIE2/IDE) does not explicitly check the address

range. For example, setting up a DMA transfer to external

address 0x8000 might result in a DMA transfer into address

0x0000.

External Memory Related Resource Considerations:

Figure 1 illustrates that when the nXMEMSEL pin is asserted the

upper CPU address pins are driven by the contents of the Page

x registers.

■ By default A[18:15] are not available for general addressing

and are driven high on power up. The Upper Address Enable

general addressing purposes.

Figure 1. Page n Registers External Address Pins Logic

■ 47K ohm external pull up on pin A15 for 12 MHz crystal

operation.

nXMEMSEL Pin

■ During the 3 ms BIOS boot procedure the CPU external

memory bus is active.

0000 + PC[14:0]

A[18:0]

■ ROM boot load value 0xC3B6 located at 0xC100.

PAGEx Register[5:0] + PC[12:0]

■ HPI, HSS, SPI, SIE1, SIE2, and IDE cannot DMA to external

memory arrays.

Where:

■ Page 1 banking is always enabled and is in effect from 0x8000

to 0x9FFF.

x = 1 or 2

PC = Program Counter

A = CPU Address Bus

■ Page 2 banking is always enabled and is in effect from 0xA000

to 0xBFFF.

■ CPU memory bus strobes may wiggle when chip selects are

Note:

inactive.

PAGE 1 Register Active Range = 8000h to 9FFFh

PAGE 2 Register Active Range = A000h to BFFFh

nXMEMSEL Pin Active Range = 8000h to BFFFh

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External Memory Interface Pins

Table 6. External Memory Interface Pins (continued)

Table 6. External Memory Interface Pins

Pin Name

Pin Number

Pin Name

Pin Number

nWR

nRD

nXMEMSEL (optional nCS)

nXROMSEL (ROM nCS)

External Memory Interface Block Diagrams

nXRAMSEL (RAM nCS)

Figure 2 illustrates how to connect a 64k × 8 memory array

(SRAM/ROM) to the EZ-Host external memory interface.

A18

A17

A16

A15

A14

A13

A12

A11

A10

Figure 2. Interfacing to 64k × 8 Memory Array

Interfacing to 64K x 8 External Memory Array

EZ-Host

CY7C67300

External Memory Array

64K x 8

A[15:0]

D[7:0]

nXRAMSEL

nWR

nRD

Figure 3 illustrates the interface for connecting a 16-bit ROM or

16-bit RAM to the EZ-Host external memory interface. In 16-bit

mode, up to 256K words of external ROM or RAM are supported.

Note that the address lines do not map directly.

Figure 3. Interfacing up to 256k × 16 for External Code/Data

nBEL/A0

nBEH

D15

D14

D13

D12

D11

D10

Up to 256k x 16 External Code/Data (Page Mode)

EZ-Host

CY7C67300

External Memory Array

Up to 256k x 16

A[18:1]

A[17:0]

D[15:0]

nXMEMSEL

nBEL

BLE

nBEH

BHE

nWR

nRD

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Figure 4 illustrates the interface for connecting an 8-bit ROM or

8-bit RAM to the EZ-Host external memory interface. In 8-bit

mode, up to 512K bytes of external ROM or RAM are supported.

I C EEPROM Interface

EZ-Host provides a master-only I²C interface for external serial

EEPROMs. The serial EEPROM can be used to store application

specific code and data. Use the I²C interface for loading code out

of EEPROM, it is not a general I²C interface. The I²C EEPROM

interface is a BIOS implementation and is exposed through

GPIO pins. Refer to the BIOS documentation for additional

details on this interface.

Figure 4. Interfacing up to 512k × 8 for External Code/Data

Up to 512k x 8 External Code/Data (Page Mode)

EZ-Host

CY7C67300

External Memory Array

Up to 512k x8

I C EEPROM Features

■ Supports EEPROMs up to 64 KB (512K bit)

■ Auto-detection of EEPROM size

A[18:0]

D[7:0]

nXMEMSEL

nWR

I C EEPROM Pins

Table 8. I C EEPROM Interface Pins

nRD

Pin Name

Pin Number

GPIO Number

SMALL EEPROM

SCK

SDA

GPIO31

GPIO30

General Purpose IO Interface (GPIO)

LARGE EEPROM

EZ-Host has up to 32 GPIO signals available. Several other

optional interfaces use GPIO pins as well and may reduce the

overall number of available GPIOs.

SCK

SDA

GPIO30

GPIO31

GPIO Description

Serial Peripheral Interface

All Inputs are sampled asynchronously with state changes

occurring at a rate of up to two 48 MHz clock cycles. GPIO pins

are latched directly into registers, a single flip-flop.

EZ-Host provides a SPI interface for added connectivity. EZ-Host

may be configured as either an SPI master or SPI slave. The SPI

interface can be exposed through GPIO pins or the External

Memory port.

Unused Pin Descriptions

Ensure to tristate unused USB pins with the D+ line pulled high

through the internal pull up resistor and the D– line pulled low

through the internal pull down resistor.

SPI Features

■ Master or slave mode operation

Configure unused GPIO pins as outputs so they are driven low.

■ DMA block transfer and PIO byte transfer modes

■ Full duplex or half duplex data communication

■ 8-byte receive FIFO and 8-byte transmit FIFO

■ Selectable master SPI clock rates from 250 kHz to 12 MHz

■ Selectable master SPI clock phase and polarity

■ Slave SPI signaling synchronization and filtering

■ Slave SPI clock rates up to 2 MHz

UART Interface

EZ-Host has a built in UART interface. The UART interface

supports data rates from 900 to 115.2K baud. It can be used as

a development port or for other interface requirements. The

UART interface is exposed through GPIO pins.

UART Features

■ Supports baud rates of 900 to 115.2K

■ 8-N-1

■ Maskable interrupts for block and byte transfer modes

UART Pins.

■ Individual bit transfer for non-byte aligned serial communi-

cation in PIO mode

Table 7. UART Interface Pins

■ Programmable delay timing for the active/inactive master SPI

clock

Pin Name

Pin Number

■ Auto or manual control for master mode slave select signal

■ Complete access to internal memory

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SPI Pins

HSS Pins

The SPI port has a few different pin location options as shown in

T a ble 9. The port location is selectable via the GPIO control

The HSS port has a few different pin location options as shown

in T a ble 10. The port location is selectable via the GPIO control

Table 10. HSS Interface Pins

Table 9. SPI Interface Pins

Pin Name

Pin Number

Pin Name

Default Location

nSSI

Pin Number

Default Location

CTS

56 or 65

RTS

SCK

RXD

MOSI

TXD

MISO

Alternate Location

nSSI

CTS

RTS

RXD

TXD

SCK

MOSI

MISO

Programmable Pulse/PWM Interface

High-Speed Serial Interface

EZ-Host has four built in PWM output channels. Each channel

provides a programmable timing generator sequence that can be

used to interface to various image sensors or other applications.

The PWM interface is exposed through GPIO pins.

EZ-Host provides an HSS interface. The HSS interface is a

programmable serial connection with baud rate from 9600 baud

to 2.0M baud. The HSS interface supports both byte and block

mode operations and also hardware and software handshaking.

Complete control of EZ-Host can be accomplished through this

interface via an extensible API and communication protocol. The

HSS interface can be exposed through GPIO pins or the External

Memory port.

Programmable Pulse/PWM Features

■ Four independent programmable waveform generators

■ Programmable predefined frequencies ranging from 5.90 KHz

to 48 MHz

HSS Features

■ Configurable polarity

■ 8 bits, no parity code

■ Continuous and one-shot mode available

■ Programmable baud rate from 9600 baud to 2M baud

■ Selectable 1- or 2-stop bit on transmit

■ Programmable inter-character gap timing for Block Transmit

■ 8-byte receive FIFO

Programmable Pulse/PWM Pins.

Table 11. PWM Interface Pins

Pin Name

PWM3

Pin Number

■ Glitch filter on receive

PWM2

■ Block mode transfer directly to/from EZ-Host internal memory

(DMA transfer)

PWM1

PWM0

■ Selectable CTS/RTS hardware signal handshake protocol

■ Selectable XON/XOFF software handshake protocol

■ Programmable Receive interrupt, Block Transfer Done inter-

rupts

■ Complete access to internal memory

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Table 12. HPI Interface Pins (continued)^{[3, 4]}

Host Port Interface

EZ-Host has an HPI interface. The HPI interface provides DMA

access to the EZ-Host internal memory by an external host, plus

a bidirectional mailbox register for supporting high level commu-

nication protocols. This port is designed to be the primary

high-speed connection to a host processor. Complete control of

EZ-Host can be accomplished through this interface via an

extensible API and communication protocol. Other than the

hardware communication protocols, a host processor has

identical control over EZ-Host whether connecting to the HPI or

HSS port. The HPI interface is exposed through GPIO pins.

D11

D10

HPI Features

■ 16-bit data bus interface

■ 16 MB/s throughput

■ Auto-increment of address pointer for fast block mode transfers

■ Direct memory access (DMA) to internal memory

■ Bidirectional Mailbox register

■ Byte swapping

The two HPI address pins are used to address one of four

possible HPI port registers as shown in T a ble 13.

Table 13. HPI Addressing

HPI A[1:0]

HPI Data

■ Complete access to internal memory

■ Complete control of SIEs through HPI

■ Dedicated HPI status register

HPI Mailbox

HPI Address

HPI Status

HPI Pins

[3, 4]

Table 12. HPI Interface Pins

IDE Interface

Pin Name

INT

Pin Number

EZ-Host has an IDE interface. The IDE interface supports PIO

mode 0-4 as specified in the Information Technology-AT

Attachment–4 with Packet Interface Extension (ATA/ATAPI-4)

Specification, T13/1153D Rev 18. There is no need for firmware

to use programmable wait states. The CPU read/write cycle is

automatically extended as needed for direct CPU to IDE

read/write accesses.

nRD

nWR

nCS

The EZ-Host IDE interface also has a BLOCK transfer mode that

allows EZ-Host to read/write large blocks of data to/from the IDE

data register and move it to/from the EZ-Host on-chip memory

directly without intervention of the CPU. The IDE interface is

exposed through GPIO pins. T a ble 14 on page 10 lists the

achieved throughput for maximum block mode data transfer rate

(with IDE_IORDY true) for the various IDE PIO modes.

D15

D14

D13

D12

Notes

3. HPI_INT is for the Outgoing Mailbox interrupt.

4. HPI strobes are negative logic sampled on rising edge.

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Table 14. IDE Throughput

Mode

ATA/ATAPI-4

Min Cycle Time

Actual

Min Cycle Time

ATA/ATPI-4

Max Transfer Rate

Actual

Max Transfer Rate

PIO Mode 0

PIO Mode 1

PIO Mode 2

PIO Mode 3

PIO Mode 4

600 ns

383 ns

240

30T = 625 ns

20T = 416.7 ns

13T = 270.8 ns

10T = 208.3 ns

8T = 166.7 ns

3.33 MB/s

5.22 MB/s

8.33 MB/s

11.11 MB/s

16.67 MB/s

3.2 MB/s

4.8 MB/s

7.38 MB/s

9.6 MB/s

12.0 MB/s

180 ns

120 ns

T = System clock period = 1/48 MHz.

IDE Features

Charge Pump Interface

VBUS for the USB OTG port can be produced by EZ-Host using

its built in charge pump and some external components. Ensure

the circuit connections look similar to the following diagram.

■ Programmable IO mode 0–4

■ Block mode transfers

■ Directmemoryaccessto/frominternalmemorythroughtheIDE

data register

Figure 5. Charge Pump

IDE Pins

CSWITCHA

CY7C67300

Table 15. IDE Interface Pins

Pin Name

IORDY

IOR

IOW

CS1

CS0

Pin Number

CSWITCHB

VBUS

OTGVBUS

Component details:

■ D1 and D2: Schottky diodes with a current rating greater than

60 mA

■ C1: Ceramic capacitor with a capacitance of 0.1 µF

■ C2: Make capacitor value no more that 6.5 µF since that is the

maximum capacitance allowed by the USB OTG specifications

for a dual role device. The minimum value of C2 is 1 µF. There

are no restrictions on the type of capacitor for C2.

D15

D14

D13

D12

D11

D10

If the VBUS charge pump circuit is not to be used, CSWITCHA,

CSWITCHB, and OTGVBUS can be left unconnected.

Charge Pump Features

■ Meets OTG Supplement Requirements, see T a ble 134, DC

Characteristics: Charge Pump on page 84 for details.

Charge Pump Pins

Table 16. Charge Pump Interface Pins

Pin Name

OTGVBUS

CSwitchA

CSwitchB

Pin Number

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Booster Pins

Booster Interface

EZ-Host has an on chip power booster circuit for use with power

supplies that range between 2.7V and 3.6V. The booster circuit

boosts the power to 3.3V nominal to supply power for the entire

chip. The booster circuit requires an external inductor, diode, and

capacitor. During power down mode, the circuit is disabled to

save power. Figure 6 shows how to connect the booster circuit.

Table 17. Charge Pump Interface Pins

Pin Name

BOOSTVcc

VSWITCH

Pin Number

Crystal Interface

Figure 6. Power Supply Connection With Booster

The recommended crystal circuit to be used with EZ-Host is

shown in Figure 8 If an oscillator is used instead of a crystal

circuit, connect it to XTALIN and leave XTALOUT unconnected.

For further information about the crystal requirements, see T a ble

132, Crystal Requirements on page 83.

BOOSTVcc

2.7V to 3.6V

Power Supply

Noted that the CLKSEL pin (pin 38) is sampled after reset to

determine what crystal or clock source frequency is used. For

normal operation, 12 MHz is required so the CLKSEL pin must

VSWITCH

have a 47K ohm pull up resistor to V_CC.

Figure 8. Crystal Interface

3.3V

XTALIN

VCC

AVCC

CY7C67300

12MHz

Parallel Resonant

Fundamental Mode

500uW

Component details:

■ L1: Inductor with inductance of 10 µH and a current rating of at

least 250 mA

20-33pf ±5%

XTALOUT

■ D1: Schottky diode with a current rating of at least 250 mA

C2 = 22 pF

C1 = 22 pF

■ C1:Tantalumorceramiccapacitorwithacapacitanceofatleast

2.2 µF

Figure 7 shows how to connect the power supply when the

booster circuit is not being used.

Figure 7. Power Supply Connection Without Booster

Crystal Pins

Table 18. Crystal Pins

Pin Name

XTALIN

Pin Number

BOOSTVcc

3.0V to 3.6V

Power Supply

XTALOUT

VSWITCH

VCC

AVCC

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Boot Configuration Interface

Operational Modes

EZ-Host can boot into any one of four modes. The mode it boots

into is determined by the TTL voltage level of GPIO[31:30] at the

time nRESET is deasserted. T a ble 19 shows the different boot

pin combinations possible. After a reset pin event occurs, the

BIOS bootup procedure executes for up to 3 ms. GPIO[31:30]

are sampled by the BIOS during bootup only. After bootup these

pins are available to the application as GPIOs.

The operational modes are discussed in the following sections.

Coprocessor Mode

EZ-Host can act as a coprocessor to an external host processor.

In this mode, an external host processor drives EZ-Host and is

the main processor rather then EZ-Host’s own 16-bit internal

CPU. An external host processor may interface to EZ-Host

through one of the following three interfaces in coprocessor

mode:

Table 19. Boot Configuration Interface

GPIO31 GPIO30

Boot Mode

■ HPI mode, a 16 bit parallel interface with up to 16 MB transfer

rate

(Pin 39) (Pin 40)

Host Port Interface (HPI)

High-Speed Serial (HSS)

■ HSS mode, a serial interface with up to 2M baud transfer rate

■ SPI mode, a serial interface with up to 2 Mb/s transfer rate

Serial Peripheral Interface (SPI,

slave mode)

At bootup GPIO[31:30] determine which of these three interfaces

are used for coprocessor mode. See T a ble 19 for details.

Bootloading begins from the selected interface after POR + 3 ms

of BIOS bootup.

I²C EEPROM (Standalone Mode)

Ensure that GPIO[31:30] is pulled high or low as needed using

resistors tied to V_CCor GND with resistor values between 5K

ohms and 15K ohms. Do not tie GPIO[31:30] directly to V_CCor

GND. Note that in standalone mode, the pull ups on those two

pins are used for the serial I2C EEPROM (if implemented). Make

sure that the resistors used for these pull ups conform to the

serial EEPROM manufacturer's requirements.

Standalone Mode

In standalone mode, there is no external processor connected to

EZ-Host. Instead, EZ-Host’s own internal 16-bit CPU is the main

processor and firmware is typically downloaded from an

EEPROM. Optionally, firmware may also be downloaded via

USB. See T a ble 19 for booting into standalone mode.

If any mode other then standalone is chosen, EZ-Host is in

coprocessor mode. The device powers up with the appropriate

communication interface enabled according to its boot pins and

waits idle until a coprocessor communicates with it. See the

BIOS documentation for greater detail of the boot process.

After booting into standalone mode (GPIO[31:30] = ‘11’), the

following pins are affected:

■ GPIO[31:30] are configured as output pins to examine the

EEPROM contents

■ GPIO[28:27] are enabled for debug UART mode

■ GPIO[29] is configured for as OTGID for OTG applications on

PORT1A

❐ If OTGID is logic 1 then PORT1A (OTG) is configured as a

USB peripheral

❐ If OTGID is logic 0 then PORT1A (OTG) is configured as a

USB host

■ Ports 1B, 2A, and 2B default as USB peripheral ports

■ All other pins remain INPUT pins.

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Minimum Hardware Requirements for Standalone Mode – Peripheral Only

Figure 9. Minimum Standalone Hardware Configuration – Peripheral Only

EZ-Host

CY7C67300

Reset

Logic

nRESET

VCC, AVCC,

BoostVCC

VReg

VBus

D+

DPlus

Standard-B

or Mini-B

DMinus

D-

GND

SHIELD

VCC

Bootstrap Options

47Kohm

Vcc Vcc

Pin 38

10k 10k

GPIO[30]

GPIO[31]

SCL*

SDA*

Int. 16k x8

Code / Data

Bootloading Firmware

VCC

Up to 64k x8

EEPROM

SCL

SDA

Reserved

22pf

GND

XIN

GND, AGND,

BoostGND

12MHz

XOUT

Parallel Resonant

*Bootloading begins after POR + 3ms BIOS bootup

Fundamental Mode

500uW

20-33pf ±5%

*GPIO[31:30]

Up to 2k x8

>2k x8 to 64k x8 SDA SCL

SCL SDA

Sleep

Power Savings and Reset Description

Sleep mode is the main chip power down mode and is also used

for USB suspend. Sleep mode is entered by setting the Sleep

Enable (bit 1) of the Power control register [0xC00A]. During

Sleep mode (USB Suspend) the following events and states are

true:

This sections describes the different modes for resetting the chip

and ways to save power.

Power Saving Mode Description

EZ-Host has one main power saving mode, Sleep. For detailed

information about Sleep mode, see the Sleep section that

follows.

■ GPIO pins maintain their configuration during sleep (in

suspend)

■ External Memory address pins are driven low

■ XTALOUT is turned off

Sleep mode is used for USB applications to support USB

suspend and non USB applications as the main chip power down

mode.

■ Internal PLL is turned off

In addition, EZ-Host is capable of slowing down the CPU clock

speed through the CPU Speed register [0xC008] without

affecting other peripheral timing. Reducing the CPU clock speed

from 48 MHz to 24 MHz reduces the overall current draw by

around 8 mA while reducing it from 48 MHz to 3 MHz reduces

the overall current draw by approximately 15 mA.

■ Ensure that firmware disables the charge pump (OTG Control

0.2V. Otherwise OTGVBUS only drops to V_CC– (2 schottky

diode drops).

■ Booster circuit is turned off

■ USB transceivers is turned off

■ CPU goes into suspend mode until a programmable wakeup

event

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External (Remote) Wakeup Source

Memory Map

There are several possible events available to wake EZ-Host

from Sleep mode as shown in T a ble 20. These may also be used

as remote wakeup options for USB applications. See the Power

Control Register [0xC00A] [R/W] on page 19 for details.

The memory map is discussed in the following sections.

Mapping

The total memory space directly addressable by the CY16

processor is 64K (0x0000-0xFFFF). Program, data, and IO are

contained within this 64K space. This memory space is byte

addressable. Figure 10 on page 15 shows the various memory

region address locations.

Upon wakeup, code begins executing within 200 µs, the time it

takes the PLL to stabilize.

[5, 6]

Table 20. Wakeup Sources

Wakeup Source

Event

(if enabled)

Internal Memory

USB Resume

OTGVBUS

OTGID

D+/D– Signaling

Level

Of the internal memory, 15K bytes are allocated for user's

program and data. The lower memory space from 0x0000 to

0x04A2 is reserved for interrupt vectors, general purpose

registers, USB control registers, stack, and other BIOS variables.

The upper internal memory space contains EZ-Host control

registers from 0xC000 to 0xC0FF and the BIOS ROM itself from

0xE000 to 0xFFFF. For more information about the reserved

lower memory or the BIOS ROM, refer to the Programmer’s

documentation and/or the BIOS documentation.

Any Edge

Read

HPI

HSS

Read

SPI

Read

IRQ1 (GPIO 25)

IRQ0 (GPIO 24)

Any Edge

During development with the EZ-Host toolset, leave the lower

area of user's space (0x04A4 to 0x1000) available to load the

GDB stub. The GDB stub is required to allow the toolset debug

access into EZ-Host.

Power-On-Reset Description

The chip select pins are not active during accesses to internal

memory.

The length of the power-on-reset event can be defined by (V_CC

ramp to valid) + (Crystal startup). A typical application might use

a 12 ms power-on-reset event = ~7 ms + ~5 ms, respectively.

External Memory

Reset Pin

Up to 32 KB of external memory from 0x4000 - 0xBFFF is

available via one chip select line (nXRAMSEL) with RAM Merge

enabled (BIOS default). Additionally, another 8 KB region from

0xC100 - 0xDFFF is available via a second chip select line

(nXROMSEL) giving 40 KB of total available external memory.

Together with the internal 15 KB, this gives a total of either ~48

KB (one chip select) or ~56 KB (two chip selects) of available

memory for either code or data.

The Reset pin is active low and requires a minimum pulse

duration of sixteen 12 MHz clock cycles (1.3 µs). A reset event

restores all registers to their default POR settings. Code

execution then begins 200 µs later at 0xFF00 with an immediate

jump to 0xE000, the start of BIOS. Refer to BIOS documentation

for additional details.

USB Reset

Note

that

the

memory

map

and

names

(nXRAMSEL/nXROMSEL) define specific memory regions for

RAM vs. ROM. This allows the BIOS to look in the upper external

memory space at 0xC100 for SCAN vectors (enabling code to be

loaded/executed from ROM). If no SCAN vectors are required in

the design (external memory is used exclusively for data), then

all external memory regions can be used for RAM. Similarly, the

external memory can be used exclusively for code space (ROM).

A USB Reset affects registers 0xC090 and 0xC0B0, all other

registers remain unchanged.

If more external memory is required, EZ-Host has enough

address lines to support up to 512 KB. However, this requires

complex code banking/paging schemes via the Extended Page

registers.

For further information about setting up the external memory, see

the External Memory Interface on page 5.

Notes

5. Read data is discarded (dummy data).

6. HPI_INT asserts on a USB Resume.

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Figure 10. Memory Map

Internal Memory

HW INT's

SW INT's

0x0000 - 0x00FF

Primary Registers

Swap Registers

HPI Int / Mailbox

0x0100 - 0x011F

0x0120 - 0x013F

0x0140 - 0x0148

0x014A - 0x01FF

LCP Variables

0x0200 - 0x02FF

USB Registers

0x0300 - 0x030F

0x0310 - 0x03FF

0x0400 - 0x04A2

Slave Setup Packet

BIOS Stack

USB Slave & OTG

USER SPACE

~15K

0x04A4 - 0x3FFF

External Memory

USER SPACE

16K

0x4000 - 0x7FFF

0x8000 - 0x9FFF

Bank

Selected

Extended Page 1

USER SPACE

0xC018

Up to 64 8K Banks

Bank

Selected

Extended Page 2

0xA000 - 0xBFFF

0xC100 - 0xDFFF

USER SPACE

0xC01A

Up to 64 8K Banks

Control Registers

0xC000 - 0xC0FF

0xE000 - 0xFFFF

USER SPACE ~8K

BIOS

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Registers

Table 21. Processor Control Registers

Address

R/W

Some registers have different functions for a read vs. a write

access or USB host vs. USB device mode. Therefore, registers

of this type have multiple definitions for the same address.

CPU Flags Register

0xC000

Hardware Revision Register

CPU Speed Register

0xC002

0xC004

0xC008

0xC00A

0xC00E

0xC014

0xC03C

0xC03E

R/W

The default register values listed in this data sheet may be

altered to some other value during the BIOS initialization. Refer

to the BIOS documentation for register initialization information.

R/W

Power Control Register

Interrupt Enable Register

Breakpoint Register

Processor Control Registers

There are nine registers dedicated to general processor control.

Each of these registers are covered in this section and are

summarized in T a ble 21.

USB Diagnostic Register

Memory Diagnostic Register

CPU Flags Register [0xC000] [R]

Table 22. CPU Flags Register

Bit #

Field

Reserved...

Read/Write

Default

Bit #

...Reserved

Global

Interrupt

Enable

Negative

Flag

Overflow

Flag

Carry

Flag

Zero

Flag

Field

Read/Write

Default

Overflow Flag (Bit 2)

The CPU Flags register is a read only register that gives

processor flags status.

The Overflow Flag bit indicates if an overflow condition occurred.

An overflow condition can occur if an arithmetic result was either

larger than the destination operand size (for addition) or smaller

than the destination operand must allow for subtraction.

Global Interrupt Enable (Bit 4)

The Global Interrupt Enable bit indicates if the Global Interrupts

are enabled.

1: Overflow occurred

0: Overflow did not occur

1: Enabled

0: Disabled

Carry Flag (Bit 1)

The Carry Flag bit indicates if an arithmetic operation resulted in

a Carry for addition, or Borrow for subtraction.

Negative Flag (Bit 3)

The Negative Flag bit indicates if an arithmetic operation results

in a negative answer.

1: Carry/Borrow occurred

0: Carry/Borrow did not occur

1: MS result bit is ‘1’

Zero Flag (Bit 0)

0: MS result bit is not ‘1’

The Zero Flag bit indicates if an instruction execution resulted in

a ‘0’.

1: Zero occurred

0: Zero did not occur

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Bank Register [0xC002] [R/W]

Table 23. Bank Register

Bit #

Field

Address...

Read/Write

Default

R/W

Bit #

...Address

R/W

Field

Reserved

Read/Write

Default

R/W

The Bank register maps registers R0–R15 into RAM. The eleven MSBs of this register are used as a base address for registers

R0–R15. A register address is automatically generated by:

1. Shifting the four LSBs of the register address left by 1.

2. ORing the four shifted bits of the register address with the twelve MSBs of the Bank register.

3. Forcing the LSB to zero.

For example, if the Bank register is left at its default value of 0x0100, and R2 is read, then the physical address 0x0102 is read. Refer

to T a ble 24 for details.

Table 24. Bank Register Example

Bank

Hex Value

0x0100

Binary Value

0000 0001 0000 0000

0000 0000 0001 1100

0000 0001 0001 1100

R14

0x000E << 1 = 0x001C

0x011C

RAM Location

Address (Bits [15:4])

The Address field is used as a base address for all register addresses to start from.

Reserved

Write all reserved bits with ’0’.

Hardware Revision Register [0xC004] [R]

Table 25. Revision Register

Bit #

Field

Revision...

...Revision

Read/Write

Default

Bit #

Field

Read/Write

Default

The Hardware Revision register is a read only register that indicates the silicon revision number. The first silicon revision is represented

by 0x0101. This number is increased by one for each new silicon revision.

Revision (Bits [15:0])

The Revision field contains the silicon revision number.

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CPU Speed Register [0xC008] [R/W]

Table 26. CPU Speed Register

Bit #

Field

Reserved...

Read/Write

Default

Bit #

Field

...Reserved

CPU Speed

Read/Write

Default

R/W

The CPU Speed register allows the processor to operate at a user selected speed. This register only affects the CPU, all other

peripheral timing is still based on the 48 MHz system clock (unless otherwise noted).

CPU Speed (Bits[3:0])

The CPU Speed field is a divisor that selects the operating speed of the processor as defined in T a ble 27.

Table 27. CPU Speed Definition

CPU Speed [3:0]

0000

Processor Speed

48 MHz/1

0001

48 MHz/2

0010

48 MHz/3

0011

48 MHz/4

0100

48 MHz/5

0101

48 MHz/6

0110

48 MHz/7

0111

48 MHz/8

1000

48 MHz/9

1001

48 MHz/10

48 MHz/11

48 MHz/12

48 MHz/13

48 MHz/14

48 MHz/15

48 MHz/16

1010

1011

1100

1101

1110

1111

Reserved

Write all reserved bits with ’0’.

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Power Control Register [0xC00A] [R/W]

Table 28. Power Control Register

Bit #

Host/Device

OTG

Wake

Enable

Reserved

HSS

Wake

Enable

SPI

Wake

Enable

Wake

Field

Enable

Read/Write

Default

R/W

Bit #

HPI

Wake

Enable

Reserved

GPI

Wake

Enable

Reserved

Boost 3V

Sleep

Enable

Halt

Enable

Field

Read/Write

Default

R/W

OTG Wake Enable (Bit 11)

The Power Control register controls the power down and wakeup

options. Either the sleep mode or the halt mode options can be

selected. All other writable bits in this register can be used as a

wakeup source while in sleep mode.

The OTG Wake Enable bit enables or disables a wakeup

condition to occur on either an OTG VBUS_Valid or OTG ID

transition (IRQ20).

1: Enable wakeup on OTG VBUS valid or OTG ID transition

0: Disable wakeup on OTG VBUS valid or OTG ID transition

Host/Device 2B Wake Enable (Bit 15)

The Host/Device 2B Wake Enable bit enables or disables a

wakeup condition to occur on a Host/Device 2B transition. This

wakeup from the SIE port does not cause an interrupt to the

on-chip CPU.

HSS Wake Enable (Bit 9)

The HSS Wake Enable bit enables or disables a wakeup

condition to occur on an HSS Rx serial input transition. The

processor may take several hundreds of microseconds before

being operational after wakeup. Therefore, the incoming data

byte that causes the wakeup is discarded.

1: Enable wakeup on Host/Device 2B transition

0: Disable wakeup on Host/Device 2B transition

1: Enable wakeup on HSS Rx serial input transition

0: Disable wakeup on HSS Rx serial input transition

Host/Device 2A Wake Enable (Bit 14)

The Host/Device 2A Wake Enable bit enables or disables a

wakeup condition to occur on an Host/Device 2A transition. This

wakeup from the SIE port does not cause an interrupt to the

on-chip CPU.

SPI Wake Enable (Bit 8)

The SPI Wake Enable bit enables or disables a wakeup condition

to occur on a falling SPI_nSS input transition. The processor

may take several hundreds of microseconds before being opera-

tional after wakeup. Therefore, the incoming data byte that

causes the wakeup is discarded.

1: Enable wakeup on Host/Device 2A transition

0: Disable wakeup on Host/Device 2A transition

Host/Device 1B Wake Enable (Bit 13)

1: Enable wakeup on falling SPI nSS input transition

0: Disable SPI_nSS interrupt

The Host/Device 1B Wake Enable bit enables or disables a

wakeup condition to occur on an Host/Device 1B transition. This

wakeup from the SIE port does not cause an interrupt to the

on-chip CPU.

HPI Wake Enable (Bit 7)

The HPI Wake Enable bit enables or disables a wakeup

condition to occur on an HPI interface read.

1: Enable wakeup on Host/Device 1B transition

0: Disable wakeup on Host/Device 1B transition

1: Enable wakeup on HPI interface read

0: Disable wakeup on HPI interface read

Host/Device 1A Wake Enable (Bit 12)

The Host/Device 1A Wake Enable bit enables or disables a

wakeup condition to occur on an Host/Device 1A transition. This

wakeup from the SIE port does not cause an interrupt to the

on-chip CPU.

GPI Wake Enable (Bit 4)

The GPI Wake Enable bit enables or disables a wakeup

condition to occur on a GPIO(25:24) transition.

1: Enable wakeup on GPIO(25:24) transition

0: Disable wakeup on GPIO(25:24) transition

1: Enable wakeup on Host/Device 1A transition

0: Disable wakeup on Host/Device 1A transition

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Boost 3V OK (Bit 2)

Halt Enable (Bit 0)

The Boost 3V OK bit is a read only bit that returns the status of

the OTG Boost circuit.

Setting this bit to ‘1’ immediately initiates HALT mode. While in

HALT mode, only the CPU is stopped. The internal clock still runs

and all peripherals still operate, including the USB engines. The

power saving using HALT in most cases is minimal, but in appli-

cations that are very CPU intensive the incremental savings may

provide some benefit.

1: Boost circuit not ok and internal voltage rails are below 3.0V

0: Boost circuit ok and internal voltage rails are at or above 3.0V

Sleep Enable (Bit 1)

The HALT state is exited when any enabled interrupt is triggered.

Upon exiting the HALT state, one or two instructions immediately

following the HALT instruction may be executed before the

waking interrupt is serviced (you may want to follow the HALT

instruction with two NOPs).

Setting this bit to ‘1’ immediately initiates SLEEP mode. While in

SLEEP mode, the entire chip is paused, achieving the lowest

standby power state. All operations are paused, the internal

clock is stopped, the booster circuit and OTG VBUS charge

pump are all powered down, and the USB transceivers are

powered down. All counters and timers are paused but retain

their values; enabled PWM outputs freeze in their current states.

SLEEP mode exits by any activity selected in this register. When

SLEEP mode ends, instruction execution resumes within 0.5 ms.

1: Enable Halt mode

0: No function

Reserved

1: Enable Sleep mode

0: No function

Write all reserved bits with ’0’.

Interrupt Enable Register [0xC00E] [R/W]

Table 29. Interrupt Enable Register

Bit #

Reserved

OTG

Interrupt

Enable

SPI

Interrupt

Enable

Reserved

Host/Device 2 Host/Device 1

Interrupt

Enable

Interrupt

Enable

Field

Read/Write

Default

R/W

Bit #

HSS

Interrupt

Enable

In Mailbox

Interrupt

Enable

Out Mailbox

Interrupt

Enable

Reserved

UART

Interrupt

Enable

GPIO

Interrupt

Enable

Timer 1

Interrupt

Enable

Timer 0

Interrupt

Enable

Field

Read/Write

Default

R/W

Host/Device 2 Interrupt Enable (Bit 9)

The Interrupt Enable register allows control of the hardware

interrupt vectors.

The Host/Device 2 Interrupt Enable bit enables or disables all of

the following Host/Device 2 hardware interrupts: Host 2 USB

Done, Host 2 USB SOF/EOP, Host 2 Wakeup/Insert/Remove,

Device 2 Reset, Device 2 SOF/EOP or WakeUp from USB,

Device 2 Endpoint n.

OTG Interrupt Enable (Bit 12)

The OTG Interrupt Enable bit enables or disables the OTG

ID/OTG4.4V Valid hardware interrupt.

1: Enable Host 2 and Device 2 interrupt

0: Disable Host 2 and Device 2 interrupt

1: Enable OTG interrupt

0: Disable OTG interrupt

Host/Device 1 Interrupt Enable (Bit 8)

SPI Interrupt Enable (Bit 11)

The Host/Device 1 Interrupt Enable bit enables or disables all of

the following Host/Device 1 hardware interrupts: Host 1 USB

Done, Host 1 USB SOF/EOP, Host 1 Wakeup/Insert/Remove,

Device 1 Reset, Device 1 SOF/EOP or WakeUp from USB,

Device 1Endpoint n.

The SPI Interrupt Enable bit enables or disables the following

three SPI hardware interrupts: SPI TX, SPI RX, and SPI DMA

Block Done.

1: Enable SPI interrupt

0: Disable SPI interrupt

1: Enable Host 1 and Device 1 interrupt

0: Disable Host 1 and Device 1 interrupt

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HSS Interrupt Enable (Bit 7)

GPIO Interrupt Enable (Bit 2)

The HSS Interrupt Enable bit enables or disables the following

High-speed Serial Interface hardware interrupts: HSS Block

Done and HSS RX Full.

The GPIO Interrupt Enable bit enables or disables the General

Purpose IO pins interrupt (see the GPIO Control Register

[0xC006] [R/W] on page 50). When the GPIO bit is reset, all

pending GPIO interrupts are also cleared

1: Enable HSS interrupt

0: Disable HSS interrupt

1: Enable GPIO interrupt

0: Disable GPIO interrupt

In Mailbox Interrupt Enable (Bit 6)

Timer 1 Interrupt Enable (Bit 1)

The In Mailbox Interrupt Enable bit enables or disables the HPI:

Incoming Mailbox hardware interrupt.

The Timer 1 Interrupt Enable bit enables or disables the TImer1

Interrupt Enable. When this bit is reset, all pending Timer 1 inter-

rupts are cleared.

1: Enable MBXI interrupt

0: Disable MBXI interrupt

1: Enable TM1 interrupt

0: Disable TM1 interrupt

Out Mailbox Interrupt Enable (Bit 5)

The Out Mailbox Interrupt Enable bit enables or disables the HPI:

Outgoing Mailbox hardware interrupt.

Timer 0 Interrupt Enable (Bit 0)

The Timer 0 Interrupt Enable bit enables or disables the TImer0

Interrupt Enable. When this bit is reset, all pending Timer 0 inter-

rupts are cleared.

1: Enable MBXO interrupt

0: Disable MBXO interrupt

1: Enable TM0 interrupt

0: Disable TM0 interrupt

UART Interrupt Enable (Bit 3)

The UART Interrupt Enable bit enables or disables the following

UART hardware interrupts: UART TX, and UART RX.

Reserved

1: Enable UART interrupt

0: Disable UART interrupt

Write all reserved bits with ’0’.

Breakpoint Register [0xC014] [R/W]

Table 30. Breakpoint Register

Bit #

Field

Address...

...Address

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

Address (Bits [15:0])

The Breakpoint register holds the breakpoint address. When the

program counter matches this address, the INT127 interrupt

occurs. To clear this interrupt, write a zero value to this register.

The Address field is a 16-bit field containing the breakpoint

address.

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USB Diagnostic Register [0xC03C] [R/W]

Table 31. USB Diagnostic Register

Bit #

Port 2B

Diagnostic

Enable

Port 2A

Diagnostic

Enable

Port 1B

Diagnostic

Enable

Port 1A

Diagnostic

Enable

Reserved...

Field

Read/Write

Default

R/W

Bit #

...Reserved

Pull-down

Enable

LS Pull-up

Enable

FS Pull-up

Enable

Reserved

Force Select

Field

Read/Write

Default

R/W

Pull-down Enable (Bit 6)

The USB Diagnostic register provides control of diagnostic

modes. It is intended for use by device characterization tests, not

for normal operations. This register is read/write by the on-chip

CPU but is write-only via the HPI port.

The Pull-down Enable bit enables or disables full-speed pull

down resistors (pull down on both D+ and D–) for testing.

1: Enable pull down resistors on both D+ and D–

0: Disable pull down resistors on both D+ and D–

Port 2B Diagnostic Enable (Bit 15)

LS Pull-up Enable (Bit 5)

The Port 2B Diagnostic Enable bit enables or disables Port 2B

for the test conditions selected in this register.

The LS Pull-up Enable bit enables or disables a low-speed pull

up resistor (pull up on D–) for testing.

1: Apply any of the following enabled test conditions: J/K, DCK,

SE0, RSF, RSL, PRD

1: Enable low-speed pull up resistor on D–

0: Pull-up resistor is not connected on D–

0: Do not apply test conditions

FS Pull-up Enable (Bit 4)

Port 2A Diagnostic Enable (Bit 14)

The FS Pull-up Enable bit enables or disables a full-speed pull

up resistor (pull up on D+) for testing.

The Port 2A Diagnostic Enable bit enables or disables Port 2A

for the test conditions selected in this register.

1: Enable full-speed pull up resistor on D+

0: Pull up resistor is not connected on D+

1: Apply any of the following enabled test conditions: J/K, DCK,

SE0, RSF, RSL, PRD

0: Do not apply test conditions

Force Select (Bits [2:0])

Port 1B Diagnostic Enable (Bit 13)

The Force Select field bit selects several different test condition

states on the data lines (D+/D–). Refer to T a ble 32 for details.

The Port 1B Diagnostic Enable bit enables or disables Port 1B

for the test conditions selected in this register.

Table 32. Force Select Definition

1: Apply any of the following enabled test conditions: J/K, DCK,

SE0, RSF, RSL, PRD

Force Select [2:0]

Data Line State

Assert SE0

Toggle JK

Assert J

1xx

01x

001

000

0: Do not apply test conditions

Port 1A Diagnostic Enable (Bit 12)

The Port 1A Diagnostic Enable bit enables or disables Port 1A

for the test conditions selected in this register.

Assert K

1: Apply any of the following enabled test conditions: J/K, DCK,

SE0, RSF, RSL, PRD

Reserved

Write all reserved bits with ’0’.

0: Do not apply test conditions

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Memory Diagnostic Register [0xC03E] [W]

Table 33. Memory Diagnostic Register

Bit #

Reserved

Memory

Arbitration

Select

Field

Read/Write

Default

Bit #

Reserved

Monitor

Enable

Field

Read/Write

Default

Reserved

The Memory Diagnostic register provides control of diagnostic

modes.

Write all reserved bits with ’0’.

External Memory Registers

Memory Arbitration Select (Bits[10:8])

There are four registers dedicated to controlling the external

memory interface. Each of these registers are covered in this

section and are summarized in T a ble 35.

The Memory Arbitration Select field is defined in T a ble 34.

Table 34. Memory Arbitration Select

Table 35. External Memory Control Registers

Memory Arbitration

Memory Arbitration Timing

Select [3:0]

Address

0xC018

0xC01A

0xC038

0xC03A

R/W

111

110

101

100

011

010

001

000

1/8, 7 of every 8 cycles dead

2/8, 6 of every 8 cycles dead

3/8, 5 of every 8 cycles dead

4/8, 4 of every 8 cycles dead

5/8, 3 of every 8 cycles dead

6/8, 2 of every 8 cycles dead

7/8, 1 of every 8 cycles dead

8/8, all cycles available

Extended Page 1 Map Register

Extended Page 2 Map Register

Upper Address Enable Register

External Memory Control Register

R/W

Monitor Enable (Bit 0)

The Monitor Enable bit enables or disables monitor mode. In

monitor mode the internal address bus is echoed to the external

address pins.

1: Enable monitor mode

0: Disable monitor mode

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Extended Page n Map Register [R/W]

■ Extended Page 1 Map Register 0xC018

■ Extended Page 2 Map Register 0xC01A

Table 36. Extended Page n Map Register

Bit #

Field

Address...

...Address

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

reflect the content of this register when the CPU accesses the

address 0x8000-0x9FFF. For the SRAM mode, the address pin

on [4:0] (Page n address [17:13]) is used.

The Extended Page n Map register contains the Page n

high-order address bits. These bits are always appended to

accesses to the Page n Memory mapped space.

Set bit [8] (Page n address [21]) to ‘0’, so that Page n

reads/writes access external areas (SRAM, ROM or periph-

erals). nXMEMSEL is the external chip select for this space.

Address (Bits [15:0])

The Address field contains the high-order bits 28 to 13 of the

Page n address. The address pins [8:0] (Page n address [21:13])

Upper Address Enable Register [0xC038] [R/W]

Table 37. External Memory Control Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

Reserved

Upper

Address

Enable

Reserved

Field

Read/Write

Default

R/W

Upper Address Enable (Bit 3)

The Upper Address Enable register enables/disables the four

most significant bits of the external address A[18:15]. This

on power up, pins A[18:15] are driven high.

The Upper Address Enable bit enables/disables the four most

significant bits of the external address A[18:15].

1: Enable A[18:15] of the external memory interface for general

addressing.

0: Disable A[18:15], not available.

Reserved

Write all reserved bits with ’0’.

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External Memory Control Register [0xC03A] [R/W]

Table 38. External Memory Control Register

Bit #

Reserved

XRAM Merge XROM Merge XMEM Width

XMEM Wait

Select

Field

Enable

R/W

Enable

R/W

Select

R/W

Read/Write

Default

R/W

Bit #

XROM Width

Select

XROM Wait

Select

XRAM Width

Select

XRAM Wait

Select

Field

Read/Write

Default

R/W

XROM Wait Select (Bits[6:4])

The External Memory Control register provides control of Wait

States for the external SRAM or ROM. All wait states are based

off of 48 MHz.

The XROM Wait Select field selects the external ROM wait state

from 0 to 7.

XRAM Width Select (Bit 3)

XRAM Merge Enable (Bit 13)

The XRAM Width Select bit selects the external RAM width.

1: External memory = 8

The XRAM Merge Enable bit enables or disables the RAM merge

feature. When the RAM merge feature is enabled, the

nXRAMSEL is active whenever the nXMEMSEL is active.

0: External memory = 16

1: Enable RAM merge

0: Disable RAM merge

XRAM Wait Select (Bits[2:0])

The XRAM Wait Select field selects the external RAM wait state

from 0 to 7.

XROM Merge Enable (Bit 12)

Reserved

The XROM Merge Enable bit enables or disables the ROM

merge feature. When the ROM merge feature is enabled, the

nXROMSEL is active whenever the nXMEMSEL is active.

Write all reserved bits with ’0’.

Timer Registers

1: Enable ROM merge

0: Disable ROM merge

There are three registers dedicated to timer operations. Each of

these registers are discussed in this section and are summarized

in T a ble 39.

XMEM Width Select (Bit 11)

The XMEM Width Select bit selects the extended memory width.

1: Extended memory = 8

Table 39. Timer Registers

Watchdog Timer Register

Timer 0 Register

Address

0xC00C

0xC010

0xC012

R/W

0: Extended memory = 16

XMEM Wait Select (Bits [10:8])

The XMEM Wait Select field selects the extended memory wait

state from 0 to 7.

Timer 1 Register

XROM Width Select (Bit 7)

The XROM Width Select bit selects the external ROM width.

1: External memory = 8

0: External memory = 16

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Watchdog Timer Register [0xC00C] [R/W]

Table 40. Watchdog Timer Register

Bit #

Field

Reserved...

Read/Write

Default

R/W

Bit #

...Reserved

Timeout

Flag

Period

Select

Lock

Enable

WDT

Enable

Reset

Strobe

Field

Read/Write

Default

R/W

Lock Enable (Bit 2)

The Watchdog Timer register provides status and control over

the Watchdog timer. The Watchdog timer can also interrupt the

processor.

The Lock Enable bit does not allow any writes to this register until

a reset. In doing so the Watchdog timer can be set up and

enabled permanently so that it can only be cleared on reset (the

WDT Enable bit is ignored).

Timeout Flag (Bit 5)

1: Watchdog timer permanently set

The Timeout Flag bit indicates if the Watchdog timer expired. The

processor can read this bit after exiting a reset to determine if a

Watchdog timeout occurred. This bit is cleared on the next

external hardware reset.

0: Watchdog timer not permanently set

WDT Enable (Bit 1)

The WDT Enable bit enables or disables the Watchdog timer.

1: Enable Watchdog timer operation

0: Disable Watchdog timer operation

1: Watchdog timer expired.

0: Watchdog timer did not expire.

Period Select (Bits [4:3])

Reset Strobe (Bit 0)

The Period Select field is defined in T a ble 41. If this time expires

before the Reset Strobe bit is set, the internal processor is reset.

The Reset Strobe is a write-only bit that resets the Watchdog

timer count. Set this bit to ‘1’ before the count expires to avoid a

Watchdog trigger

Table 41. Period Select Definition

Period Select[4:3]

WDT Period Value

1.4 ms

1: Reset Count

Reserved

5.5 ms

Write all reserved bits with ’0’.

22.0 ms

66.0 ms

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Timer n Register [R/W]

■ Timer 0 Register 0xC010

■ Timer 1 Register 0xC012

Table 42. Timer n Register

Bit #

Field

Count...

...Count

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

functions for both USB host and USB peripheral options and is

covered in this section and summarized in T a ble 43. USB Host

only registers are covered in UART Interface on page 7, and USB

device only registers are covered in External Memory Registers

on page 23.

The Timer n Register sets the Timer n count. Both Timer 0 and

Timer 1 decrement by one every 1 µs clock tick. Each can

provide an interrupt to the CPU when the timer reaches zero.

Count (Bits [15:0])

Table 43. General USB Registers

The Count field sets the Timer count.

Address (SIE1/SIE2)

R/W

General USB Registers

USB n Control Register 0xC08A/0xC0AA

R/W

There is one set of registers dedicated to general USB control.

This set consists of two identical registers: one for Host/Device

Port 1 and one for Host/Device Port 2. This register set has

USB n Control Register [R/W]

■ USB 1 Control Register 0xC08A

■ USB 2 Control Register 0xC0AA

Table 44. USB n Control Register

Bit #

Port B

D+

Status

Port B

D–

Status

Port A

D+

Status

Port A

D–

Status

LOB

LOA

Mode

Select

Port B

Resistors

Enable

Field

Read/Write

Default

R/W

Bit #

Port A

Resistors

Enable

Port B

Force D±

State

Port A

Force D±

State

Suspend

Enable

Port B

SOF/EOP

Enable

Port A

SOF/EOP

Enable

Field

Read/Write

Default

R/W

Port B D+ Status (Bit 15)

The USB n Control register is used in both host and device mode.

It monitors and controls the SIE and the data lines of the USB

ports. This register can be accessed by the HPI interface.

The Port B D+ Status bit is a read only bit that indicates the value

of DATA+ on Port B.

1: D+ is HIGH

0: D+ is LOW

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Port B D– Status (Bit 14)

enabled. When the Mode Select is set for Device mode, a single

pull up resistor on either D+ or D–, determined by the LOA bit, is

enabled. See T a ble 45 for details.

The Port B D– Status bit is a read only bit that indicates the value

of DATA– on Port B.

1: Enable pull up/pull down resistors

0: Disable pull up/pull down resistors

1: D– is HIGH

0: D– is LOW

Table 45. USB Data Line Pull Up and Pull Down Resistors

Port A D+ Status (Bit 13)

Port n

Resistors

Enable

The Port A D+ Status bit is a read only bit that indicates the value

of DATA+ on Port A.

L0A/ Mode

L0B Select

Function

1: D+ is HIGH

0: D+ is LOW

Pull up/Pull down on D+ and

D– Disabled

Pull down on D+ and

D– Enabled

Port A D– Status (Bit 12)

The Port A D– Status bit is a read only bit that indicates the value

of DATA– on Port A.

Pull up on USB D– Enabled

Pull up on USB D+ Enabled

1: D– is HIGH

0: D– is LOW

Port B Force D± State (Bits [6:5])

LOB (Bit 11)

The Port B Force D± State field controls the forcing state of the

D+ D– data lines for Port B. This field forces the state of the Port

B data lines independent of the Port Select bit setting. See

T a ble 46 for details.

The LOB bit selects the speed of Port B.

1: Port B is set to low-speed mode

0: Port B is set to full-speed mode

Port A Force D± State (Bits [4:3])

LOA (Bit 10)

The Port A Force D± State field controls the forcing state of the

D+ D– data lines for Port A. This field forces the state of the Port

A data lines independent of the Port Select bit setting. See

T a ble 46 for details.

The LOA bit selects the speed of Port A.

1: Port A is set to low-speed mode

0: Port A is set to full-speed mode

Table 46. Port A/B Force D± State

Mode Select (Bit 9)

Port A/B Force D± State

Function

The Mode Select bit sets the SIE for host or device operation.

When set for device operation only one USB port is supported.

The active port is selected by the Port Select bit in the Host n

Count register.

MSb

LSb

Normal Operation

Force USB Reset, SE0 State

Force J-State

1: Host mode

0: Device mode

Force K-State

Port B Resistors Enable (Bit 8)

Suspend Enable (Bit 2)

The Port B Resistors Enable bit enables or disables the pull

up/pull down resistors on Port B. When enabled, the Mode

Select bit and LOB bit of this register set the pull up/pull down

resistors appropriately. When the Mode Select is set for Host

mode, the pull down resistors on the data lines (D+ and D–) are

enabled. When the Mode Select is set for Device mode, a single

pull up resistor on either D+ or D–, determined by the LOB bit, is

enabled. See T a ble 45 for details.

The Suspend Enable bit enables or disables the suspend feature

on both ports. When suspend is enabled the USB transceivers

are powered down and cannot transmit or received USB packets

but can still monitor for a wakeup condition.

1: Enable suspend

0: Disable suspend

Port B SOF/EOP Enable (Bit 1)

1: Enable pull up/pull down resistors

0: Disable pull up/pull down resistors

The Port B SOF/EOP Enable bit is only applicable in host mode.

In device mode, this bit must be written as ‘0’. In host mode this

bit enables or disables SOFs or EOPs for Port B. Either SOFs or

EOPs are generated depending on the LOB bit in the USB n

Control register when Port B is active.

Port A Resistors Enable (Bit 7)

The Port A Resistors Enable bit enables or disables the pull

up/pull down resistors on Port A. When enabled, the Mode

Select bit and LOA bit of this register set the pull up/pull down

resistors appropriately. When the Mode Select is set for Host

mode, the pull down resistors on the data lines (D+ and D–) are

1: Enable SOFs or EOPs

0: Disable SOFs or EOPs

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Port A SOF/EOP Enable (Bit 0)

Reserved

The Port A SOF/EOP Enable bit is only applicable in host mode.

In device mode this bit must be written as ‘0’. In host mode this

bit enables or disables SOFs or EOPs for Port A. Either SOFs or

EOPs are generated depending on the LOA bit in the USB n

Control register when Port A is active.

Write all reserved bits with ’0’.

1: Enable SOFs or EOPs

0: Disable SOFs or EOPs

USB Host Only Registers

There are twelve sets of dedicated registers for USB host only operation. Each set consists of two identical registers (unless otherwise

noted), one for Host Port 1 and one for Host Port 2. These register sets are covered in this section and summarized in T a ble 47.

Table 47. USB Host Only Register

Address (Host 1/Host 2)

0xC080/0xC0A0

R/W

Host n Control Register

Host n Address Register

Host n Count Register

0xC082/0xC0A2

0xC084/0xC0A4

0xC086/0xC0A6

0xC088/0xC0A8

0xC08C/0xC0AC

0xC090/0xC0B0

0xC092/0xC0B2

0xC094/0xC0B4

0xC096/0xC0B6

Host n Endpoint Status Register

Host n PID Register

Host n Count Result Register

Host n Device Address Register

Host n Interrupt Enable Register

Host n Status Register

R/W

Host n SOF/EOP Count Register

Host n SOF/EOP Counter Register

Host n Frame Register

Host n Control Register [R/W]

■ Host 1 Control Register 0xC080

■ Host 2 Control Register 0xC0A0

Table 48. Host n Control Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

Preamble

Enable

Sequence

Select

Sync

ISO

Reserved

Arm

Field

Enable

R/W

Enable

Read/Write

Default

R/W

Preamble Enable (Bit 7)

The Host n Control register allows high level USB transaction

control.

The Preamble Enable bit enables or disables the transmission of

a preamble packet before all low-speed packets. Set this bit only

when communicating with a low-speed device.

1: Enable Preamble packet

0: Disable Preamble packet

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Sequence Select (Bit 6)

ISO Enable (Bit 4)

The Sequence Select bit sets the data toggle for the next packet.

This bit has no effect on receiving data packets; sequence

checking must be handled in firmware.

The ISO Enable bit enables or disables an isochronous trans-

action.

1: Enable isochronous transaction

0: Disable isochronous transaction

1: Send DATA1

0: Send DATA0

Arm Enable (Bit 0)

Sync Enable (Bit 5)

The Arm Enable bit arms an endpoint and starts a transaction.

This bit is automatically cleared to ‘0’ when a transaction is

complete.

The Sync Enable bit synchronizes the transfer with the SOF

packet in full-speed mode and the EOP packet in low-speed

mode.

1: Arm endpoint and begin transaction

0: Endpoint disarmed

1: The next enabled packet is transferred after the SOF or EOP

packet is transmitted

Reserved

0: The next enabled packet is transferred as soon as the SIE is

free

Write all reserved bits with ’0’.

Host n Address Register [R/W]

■ Host 1 Address Register 0xC082

■ Host 2 Address Register 0xC0A2

Table 49. Host n Address Register

Bit #

Field

Address...

...Address

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

Address (Bits [15:0])

The Host n Address register is used as the base pointer into

memory space for the current host transactions.

The Address field sets the address pointer into internal RAM or

ROM.

Host n Count Register [R/W]

■ Host 1 Count Register 0xC084.

■ Host 2 Count Register 0xC0A4.

Table 50. Host n Count Register

Bit #

Reserved

Port

Reserved

...Count

Count...

Field

Select

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

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Table 51. Port Select Definition

The Host n Count register is used to hold the number of bytes

(packet length) for the current transaction. The maximum packet

length is 1023 bytes in ISO mode. The Host Count value is used

to determine how many bytes to transmit, or the maximum

number of bytes to receive. If the number of received bytes is

greater then the Host Count value then an overflow condition is

flagged by the Overflow bit in the Host n Endpoint Status register.

Host/Device 1

Port Select

Host/Device 2

Active Port

Count (Bits [9:0])

Port Select (Bit 14)

The Count field sets the value for the current transaction data

packet length. This value is retained when switching between

host and device mode, and back again.

The Port Select bit selects which of the two active ports is

selected and is summarized in T a ble 51.

1: Port 1B or Port 2B is enabled

0: Port 1A or Port 2A is enabled

Reserved

Write all reserved bits with ’0’.

Host n Endpoint Status Register [R]

■ Host 1 Endpoint Status Register 0xC086

■ Host 2 Endpoint Status Register 0xC0A6

Table 52. Host n Endpoint Status Register

Bit #

Reserved

Overflow

Flag

Underflow

Flag

Reserved

Field

Read/Write

Default

Bit #

Stall

Flag

NAK

Flag

Length

Exception

Flag

Reserved

Sequence

Status

Timeout

Flag

Error

Flag

ACK

Flag

Field

Read/Write

Default

Stall Flag (Bit 7)

The Host n Endpoint Status register is a read only register that

provides status for the last USB transaction.

The Stall Flag bit indicates that the peripheral device replied with

a Stall in the last transaction.

1: Device returned Stall

Overflow Flag (Bit 11)

0: Device did not return Stall

The Overflow Flag bit indicates that the received data in the last

data transaction exceeded the maximum length specified in the

Host n Count register. The Overflow Flag must be checked in

response to a Length Exception signified by the Length

Exception Flag set to ‘1’.

NAK Flag (Bit 6)

The NAK Flag bit indicates that the peripheral device replied with

a NAK in the last transaction.

1: Device returned NAK

1: Overflow condition occurred

0: Device did not return NAK

0: Overflow condition did not occur

Length Exception Flag (Bit 5)

Underflow Flag (Bit 10)

The Length Exception Flag bit indicates that the received data in

the data stage of the last transaction does not equal the

maximum Host Count specified in the Host n Count register. A

Length Exception can either mean an overflow or underflow and

the Overflow and Underflow flags (bits 11 and 10, respectively)

must be checked to determine which event occurred.

The Underflow Flag bit indicates that the received data in the last

data transaction was less than the maximum length specified in

the Host n Count register. The Underflow Flag must be checked

in response to a Length Exception signified by the Length

Exception Flag set to ‘1’.

1: Underflow condition occurred

1: An overflow or underflow condition occurred

0: An overflow or underflow condition did not occur

0: Underflow condition did not occur

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Sequence Status (Bit 3)

a STALL. Overflow and Underflow are not considered errors and

do not affect this bit. CRC5 and CRC16 errors result in an Error

flag along with receiving incorrect packet types.

The Sequence Status bit indicates the state of the last received

data toggle from the device. Firmware is responsible for

monitoring and handling the sequence status. The Sequence bit

is only valid if the ACK bit is set to ‘1’. The Sequence bit is set to

‘0’ when an error is detected in the transaction and the Error bit

is set.

1: Error detected

0: No error detected

ACK Flag (Bit 0)

1: DATA1

0: DATA0

The ACK Flag bit indicates two different conditions depending on

the transfer type. For non-isochronous transfers, this bit repre-

sents a transaction ending by receiving or sending an ACK

packet. For isochronous transfers, this bit represents a

successful transaction that is not represented by an ACK packet.

Timeout Flag (Bit 2)

The Timeout Flag bit indicates if a timeout condition occurred for

the last transaction. A timeout condition can occur when a device

either takes too long to respond to a USB host request or takes

too long to respond with a handshake.

1: For non-isochronous transfers, the transaction was ACKed.

For isochronous transfers, the transaction was completed

successfully

1: Timeout occurred

0: For non-isochronous transfers, the transaction was not

ACKed. For isochronous transfers, the transaction did not

complete successfully

0: Timeout did not occur

Error Flag (Bit 1)

The Error Flag bit indicates a transaction failed for any reason

other than the following: timeout, receiving a NAK, or receiving

Host n PID Register [W]

■ Host 1 PID Register 0xC086

■ Host 2 PID Register 0xC0A6

Table 53. Host n PID Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

Field

PID Select

Endpoint Select

Read/Write

Default

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Endpoint Select (Bits [3:0])

The Host n PID register is a write only register that provides the

PID and Endpoint information to the USB SIE to be used in the

next transaction.

The Endpoint field allows addressing of up to 16 different

endpoints.

Reserved

PID Select (Bits [7:4])

Write all reserved bits with ’0’.

The PID Select field is defined in T a ble 54. ACK and NAK tokens

are automatically sent based on settings in the Host n Control

Table 54. PID Select Definition

PID TYPE

PID Select [7:4]

1101 (D Hex)

1001 (9 Hex)

0001 (1 Hex)

0101 (5 Hex)

1100 (C Hex)

1010 (A Hex)

1110 (E Hex)

0011 (3 Hex)

1011 (B Hex)

SETUP

OUT

SOF

PREAMBLE

NAK

STALL

DATA0

DATA1

Host n Count Result Register [R]

■ Host 1 Count Result Register 0xC088

■ Host 2 Count Result Register 0xC0A8

Table 55. Host n Count Result Register

Bit #

Field

Result...

...Result

Read/Write

Default

Bit #

Field

Read/Write

Default

Result (Bits [15:0])

The Host n Count Result register is a read only register that

contains the size difference in bytes between the Host Count

Value specified in the Host n Count register and the last packet

received. If an overflow or underflow condition occurs, that is the

received packet length differs from the value specified in the Host

n Count register, the Length Exception Flag bit in the Host n

Endpoint Status register is set. The value in this register is only

value when the Length Exception Flag bit is set and the Error

Flag bit is not set, both bits are in the Host n Endpoint Status

The Result field contains the differences in bytes between the

received packet and the value specified in the Host n Count

‘111111’, a 2’s complement value indicating the additional byte

count of the received packet. If an underflow condition occurs,

Result [15:0] indicates the excess bytes count (number of bytes

not used).

Reserved

Write all reserved bits with ’0’.

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Host n Device Address Register [W]

■ Host 1 Device Address Register 0xC088

■ Host 2 Device Address Register 0xC0A8

Table 56. Host n Device Address Register

Bit #

Field

Reserved...

Read/Write

Default

Bit #

Field

...Reserved

Address

Read/Write

Default

Address (Bits [6:0])

The Host n Device Address register is a write only register that

contains the USB Device Address that the host wants to commu-

nicate with.

The Address field contains the value of the USB address for the

next device that the host is going to communicate with. This

value must be written by firmware.

Reserved

Write all reserved bits with ’0’.

Host n Interrupt Enable Register [R/W]

■ Host 1 Interrupt Enable Register 0xC08C

■ Host 2 Interrupt Enable Register 0xC0AC

Table 57. Host n Interrupt Enable Register

Bit #

VBUS

Interrupt

Enable

ID Interrupt

Enable

Reserved

SOF/EOP

Interrupt

Enable

Reserved

Field

Read/Write

Default

R/W

Bit #

Port B

Port A

Port B Connect Port A Connect

Reserved

Done

Interrupt

Enable

Wake Interrupt Wake Interrupt

Change

Interrupt

Enable

Change

Interrupt

Enable

Field

Read/Write

Default

R/W

1: Enable VBUS interrupt

0: Disable VBUS interrupt

The Host n Interrupt Enable register enables control over host

related interrupts.

ID Interrupt Enable (Bit 14)

In this register a bit set to ‘1’ enables the corresponding interrupt

while ‘0’ disables the interrupt.

The ID Interrupt Enable bit enables or disables the OTG ID

interrupt. When enabled this interrupt triggers on both the rising

and falling edge of the OTG ID pin (only supported in Port 1A).

This bit is only available for Host 1 and is a reserved bit in Host 2.

VBUS Interrupt Enable (Bit 15)

The VBUS Interrupt Enable bit enables or disables the OTG

VBUS interrupt. When enabled this interrupt triggers on both the

rising and falling edge of VBUS at the 4.4V status (only

supported in Port 1A). This bit is only available for Host 1 and is

a reserved bit in Host 2.

1: Enable ID interrupt

0: Disable ID interrupt

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SOF/EOP Interrupt Enable (Bit 9)

1: Enable Connect Change interrupt

0: Disable Connect Change interrupt

The SOF/EOP Interrupt Enable bit enables or disables the

SOF/EOP timer interrupt

Port A Connect Change Interrupt Enable (Bit 4)

1: Enable SOF/EOP timer interrupt

0: Disable SOF/EOP timer interrupt

The Port A Connect Change Interrupt Enable bit enables or

disables the Connect Change interrupt on Port A. This interrupt

triggers when either a device is inserted (SE0 state to J state) or

a device is removed (J state to SE0 state).

Port B Wake Interrupt Enable (Bit 7)

The Port B Wake Interrupt Enable bit enables or disables the

remote wakeup interrupt for Port B

1: Enable Connect Change interrupt

0: Disable Connect Change interrupt

1: Enable remote wakeup interrupt for Port B

0: Disable remote wakeup interrupt for Port B

Done Interrupt Enable (Bit 0)

The Done Interrupt Enable bit enables or disables the USB

Transfer Done interrupt. The USB Transfer Done triggers when

either the host responds with an ACK, or a device responds with

any of the following: ACK, NAK, STALL, or Timeout. This

interrupt is used for both Port A and Port B.

Port A Wake Interrupt Enable (Bit 6)

The Port A Wake Interrupt Enable bit enables or disables the

remote wakeup interrupt for Port A

1: Enable remote wakeup interrupt for Port A

0: Disable remote wakeup interrupt for Port A

1: Enable USB Transfer Done interrupt

0: Disable USB Transfer Done interrupt

Port B Connect Change Interrupt Enable (Bit 5)

Reserved

The Port B Connect Change Interrupt Enable bit enables or

disables the Port B Connect Change interrupt on Port B. This

interrupt triggers when either a device is inserted (SE0 state to J

state) or a device is removed (J state to SE0 state).

Write all reserved bits with ’0’.

Host n Status Register [R/W]

■ Host 1 Status Register 0xC090

■ Host 2 Status Register 0xC0B0

Table 58. Host n Status Register

Bit #

VBUS Interrupt

Flag

ID Interrupt

Flag

Reserved

SOF/EOP

Interrupt Flag

Reserved

Field

Read/Write

Default

R/W

Bit #

Port B

Wake Interrupt

Flag

Port A

Wake Interrupt

Flag

Port B Connect Port A Connect

Port B

SE0

Status

Port A

SE0

Status

Reserved Done Interrupt

Flag

Change

ChangeInterrupt

Flag

Field

Interrupt Flag

Read/Write

Default

R/W

1: Interrupt triggered

The Host n Status register provides status information for host

operation. Pending interrupts can be cleared by writing a ‘1’ to

the corresponding bit. This register can be accessed by the HPI

interface.

0: Interrupt did not trigger

ID Interrupt Flag (Bit 14)

The ID Interrupt Flag bit indicates the status of the OTG ID

interrupt (only for Port 1A). When enabled this interrupt triggers

on both the rising and falling edge of the OTG ID pin. This bit is

only available for Host 1 and is a reserved bit in Host 2.

VBUS Interrupt Flag (Bit 15)

The VBUS Interrupt Flag bit indicates the status of the OTG

VBUS interrupt (only for Port 1A). When enabled this interrupt

triggers on both the rising and falling edge of VBUS at 4.4V. This

bit is only available for Host 1 and is a reserved bit in Host 2.

1: Interrupt triggered

0: Interrupt did not trigger

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SOF/EOP Interrupt Flag (Bit 9)

triggers ‘1’ on either a rising edge or falling edge of a USB Reset

condition (device inserted or removed). Together with the Port A

SE0 Status bit, it can be determined whether a device was

inserted or removed.

The SOF/EOP Interrupt Flag bit indicates the status of the

SOF/EOP Timer interrupt. This bit triggers ‘1’ when the

SOF/EOP timer expires.

1: Interrupt triggered

0: Interrupt did not trigger

Port B SE0 Status (Bit 3)

Port B Wake Interrupt Flag (Bit 7)

The Port B SE0 Status bit indicates if Port B is in a SE0 state or

not. Together with the Port B Connect Change Interrupt Flag bit,

it can be determined whether a device was inserted (non-SE0

condition) or removed (SE0 condition).

The Port B Wake Interrupt Flag bit indicates remote wakeup on

PortB.

1: Interrupt triggered

0: Interrupt did not trigger

1: SE0 condition

0: Non-SE0 condition

Port A Wake Interrupt Flag (Bit 6)

The Port A Wake Interrupt Flag bit indicates remote wakeup on

PortA.

Port A SE0 Status (Bit 2)

The Port A SE0 Status bit indicates if Port A is in a SE0 state or

not. Together with the Port A Connect change Interrupt Flag bit,

it can be determined whether a device was inserted (non-SE0

condition) or removed (SE0 condition).

1: Interrupt triggered

0: Interrupt did not trigger

Port B Connect Change Interrupt Flag (Bit 5)

1: SE0 condition

The Port B Connect Change Interrupt Flag bit indicates the

status of the Connect Change interrupt on Port B. This bit

triggers ‘1’ on either a rising edge or falling edge of a USB Reset

condition (device inserted or removed). Together with the Port B

SE0 Status bit, it can be determined whether a device was

inserted or removed.

0: Non-SE0 condition

Done Interrupt Flag (Bit 0)

The Done Interrupt Flag bit indicates the status of the USB

Transfer Done interrupt. The USB Transfer Done triggers when

either the host responds with an ACK, or a device responds with

any of the following: ACK, NAK, STALL, or Timeout. This

interrupt is used for both Port A and Port B.

1: Interrupt triggered

0: Interrupt did not trigger

1: Interrupt triggered

Port A Connect Change Interrupt Flag (Bit 4)

0: Interrupt did not trigger

The Port A Connect Change Interrupt Flag bit indicates the

status of the Connect Change interrupt on Port A. This bit

Host n SOF/EOP Count Register [R/W]

■ Host 1 SOF/EOP Count Register 0xC092

■ Host 2 SOF/EOP Count Register 0xC0B2

Table 59. Host n SOF/EOP Count Register

Bit #

Field

Reserved

Count...

Read/Write

Default

R/W

Bit #

Field

...Count

Read/Write

Default

R/W

read, the value returned is the programmed SOF/EOP count

value.

The Host n SOF/EOP Count register contains the SOF/EOP

Count Value that is loaded into the SOF/EOP counter. This value

is loaded each time the SOF/EOP counter counts down to zero.

The default value set in this register at power up is 0x2EE0 which

generates a 1 ms time frame. The SOF/EOP counter is a down

counter decremented at a 12 MHz rate. When this register is

Count (Bits [13:0])

The Count field sets the SOF/EOP counter duration.

Reserved

Write all reserved bits with ’0’.

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Host n SOF/EOP Counter Register [R]

■ Host 1 SOF/EOP Counter Register 0xC094

■ Host 2 SOF/EOP Counter Register 0xC0B4

Table 60. Host n SOF/EOP Counter Register

Bit #

Field

Reserved

Counter...

Read/Write

Default

Bit #

Field

...Counter

Read/Write

Default

Counter (Bits [13:0])

The Host n SOF/EOP Counter register contains the current value

of the SOF/EOP down counter. This value can be used to

determine the time remaining in the current frame.

The Counter field contains the current value of the SOF/EOP

down counter.

Host n Frame Register [R]

■ Host 1 Frame Register 0xC096

■ Host 2 Frame Register 0xC0B6

Table 61. Host n Frame Register

Bit #

Field

Reserved

Frame...

Read/Write

Default

Bit #

Field

...Frame

Read/Write

Default

Frame (Bits [10:0])

The Host n Frame register maintains the next frame number to

be transmitted (current frame number + 1). This value is updated

after each SOF transmission. This register resets to 0x0000 after

each CPU write to the Host n SOF/EOP Count register (Host 1:

0xC092 Host 2: 0xC0B2).

The Frame field contains the next frame number to be trans-

mitted.

Reserved

Write all reserved bits with ’0’.

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USB Device Only Registers

There are eleven sets of USB Device Only registers. All sets consist of at least two registers, one for Device Port 1 and one for Device

Port 2. In addition, each Device port has eight possible endpoints. This gives each endpoint register set eight registers for each Device

Port for a total of sixteen registers per set. The USB Device Only registers are covered in this section and summarized in T a ble 62.

Table 62. USB Device Only Registers

Address (Device 1/Device 2)

0x02n0

R/W

Device n Endpoint n Control Register

Device n Endpoint n Address Register

Device n Endpoint n Count Register

Device n Endpoint n Status Register

Device n Endpoint n Count Result Register

Device n Port Select Register

0x02n2

0x02n4

0x02n6

0x02n8

0xC084/0xC0A4

0xC08C/0xC0AC

0xC08E/0xC0AE

0xC090/0xCB0

0xC092/0xC0B2

0xC094/0xC0B4

Device n Interrupt Enable Register

Device n Address Register

Device n Status Register

Device n Frame Number Register

Device n SOF/EOP Count Register

Device n Endpoint n Control Register [R/W]

■ Device n Endpoint 0 Control Register [Device 1: 0x0200 Device 2: 0x0280]

■ Device n Endpoint 1 Control Register [Device 1: 0x0210 Device 2: 0x0290]

■ Device n Endpoint 2 Control Register [Device 1: 0x0220 Device 2: 0x02A0]

■ Device n Endpoint 3 Control Register [Device 1: 0x0230 Device 2: 0x02B0]

■ Device n Endpoint 4 Control Register [Device 1: 0x0240 Device 2: 0x02C0]

■ Device n Endpoint 5 Control Register [Device 1: 0x0250 Device 2: 0x02D0]

■ Device n Endpoint 6 Control Register [Device 1: 0x0260 Device 2: 0x02E0]

■ Device n Endpoint 7 Control Register [Device 1: 0x0270 Device 2: 0x02F0]

Table 63. Device n Endpoint n Control Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

IN/OUT

Ignore

Enable

Sequence

Select

Stall

Enable

ISO

Enable

NAK

Interrupt

Enable

Direction

Select

Enable

Arm

Enable

Field

Read/Write

Default

R/W

IN/OUT Ignore Enable (Bit 7)

The Device n Endpoint n Control register provides control over a

single EP in device mode. There are a total of eight endpoints for

each of the two ports. All endpoints have the same definition for

their Device n Endpoint n Control register.

The IN/OUT Ignore Enable bit forces endpoint 0 (EP0) to ignore

all IN and OUT requests. Set this bit so that EP0 only accepts

Setup packets at the start of each transfer. Clear this bit to accept

IN/OUT transactions. This bit only applies to EP0.

1: Ignore IN/OUT requests

0: Do not ignore IN/OUT requests

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Sequence Select (Bit 6)

Direction Select (Bit 2)

The Sequence Select bit determines whether a DATA0 or a

DATA1 is sent for the next data toggle. This bit has no effect on

receiving data packets; sequence checking must be handled in

firmware.

The Direction Select bit needs to be set according to the

expected direction of the next data stage in the next transaction.

If the data stage direction is different from what is set in this bit,

it gets NAKed and either the IN Exception Flag or the OUT

Exception Flag is set in the Device n Endpoint n Status register.

If a setup packet is received and the Direction Select bit is set

incorrectly, the setup is ACKed and the Setup Status Flag is set

(refer to the setup bit of the Device n Endpoint n Status Register

[R/W] on page 41 for details).

1: Send a DATA1

0: Send a DATA0

Stall Enable (Bit 5)

The Stall Enable bit sends a Stall in response to the next request

(unless it is a setup request, which are always ACKed). This is a

sticky bit and continues to respond with Stalls until cleared by

firmware.

1: OUT transfer (host to device)

0: IN transfer (device to host)

Enable (Bit 1)

1: Send Stall

Set the Enable bit to allow transfers to the endpoint. If Enable is

set to ‘0’ then all USB traffic to this endpoint is ignored. If Enable

is set ‘1’ and Arm Enable (bit 0) is set ‘0’ then NAKs are automat-

ically returned from this endpoint (except setup packets which

are always ACKed as long as the Enable bit is set).

0: Do not send Stall

ISO Enable (Bit 4)

The ISO Enable bit enables and disables an isochronous trans-

action. This bit is only valid for EPs 1–7 and has no function for

EP0.

1: Enable transfers to an endpoint

0: Do not allow transfers to an endpoint

1: Enable isochronous transaction

0: Disable isochronous transaction

Arm Enable (Bit 0)

NAK Interrupt Enable (Bit 3)

The Arm Enable bit arms the endpoint to transfer or receive a

packet. This bit is cleared to ‘0’ when a transaction is complete.

The NAK Interrupt Enable bit enables and disables the gener-

ation of an Endpoint n interrupt when the device responds to the

host with a NAK. The Endpoint n Interrupt Enable bit in the

Device n Interrupt Enable register must also be set. When a NAK

is sent to the host, the corresponding EP Interrupt Flag in the

Device n Status register is set. In addition, the NAK Flag in the

Device n Endpoint n Status register is set.

1: Arm endpoint

0: Endpoint disarmed

Reserved

Write all reserved bits with ’0’.

1: Enable NAK interrupt

0: Disable NAK interrupt

Device n Endpoint n Address Register [R/W]

■ Device n Endpoint 0 Address Register [Device 1: 0x0202 Device 2: 0x0282]

■ Device n Endpoint 1 Address Register [Device 1: 0x0212 Device 2: 0x0292]

■ Device n Endpoint 2 Address Register [Device 1: 0x0222 Device 2: 0x02A2]

■ Device n Endpoint 3 Address Register [Device 1: 0x0232 Device 2: 0x02B2]

■ Device n Endpoint 4 Address Register [Device 1: 0x0242 Device 2: 0x02C2]

■ Device n Endpoint 5 Address Register [Device 1: 0x0252 Device 2: 0x02D2]

■ Device n Endpoint 6 Address Register [Device 1: 0x0262 Device 2: 0x02E2]

■ Device n Endpoint 7 Address Register [Device 1: 0x0272 Device 2: 0x02F2]

Table 64. Device n Endpoint n Address Register

Bit #

Field

Address...

...Address

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

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Address (Bits [15:0])

The Device n Endpoint n Address register is used as the base

pointer into memory space for the current Endpoint transaction.

There are a total of eight endpoints for each of the two ports. All

endpoints have the same definition for their Device n Endpoint n

Address register.

The Address field sets the base address for the current trans-

action on a signal endpoint.

Device n Endpoint n Count Register [R/W]

■ Device n Endpoint 0 Count Register [Device 1: 0x0204 Device 2: 0x0284]

■ Device n Endpoint 1 Count Register [Device 1: 0x0214 Device 2: 0x0294]

■ Device n Endpoint 2 Count Register [Device 1: 0x0224 Device 2: 0x02A4]

■ Device n Endpoint 3 Count Register [Device 1: 0x0234 Device 2: 0x02B4]

■ Device n Endpoint 4 Count Register [Device 1: 0x0244 Device 2: 0x02C4]

■ Device n Endpoint 5 Count Register [Device 1: 0x0254 Device 2: 0x02D4]

■ Device n Endpoint 6 Count Register [Device 1: 0x0264 Device 2: 0x02E4]

■ Device n Endpoint 7 Count Register [Device 1: 0x0274 Device 2: 0x02F4]

Table 65. Device n Endpoint n Count Register

Bit #

Field

Reserved

Count...

Read/Write

Default

R/W

Bit #

Field

...Count

Read/Write

Default

R/W

Count (Bits [9:0])

The Device n Endpoint n Count register designates the

maximum packet size that can be received from the host for OUT

transfers for a single endpoint. This register also designates the

packet size to be sent to the host in response to the next IN token

for a single endpoint. The maximum packet length is 1023 bytes

in ISO mode. There are a total of eight endpoints for each of the

two ports. All endpoints have the same definition for their Device

n Endpoint n Count register.

The Count field sets the current transaction packet length for a

single endpoint.

Reserved

Write all reserved bits with ’0’.

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Device n Endpoint n Status Register [R/W]

■ Device n Endpoint 0 Status Register [Device 1: 0x0206 Device 2: 0x0286]

■ Device n Endpoint 1 Status Register [Device 1: 0x0216 Device 2: 0x0296]

■ Device n Endpoint 2 Status Register [Device 1: 0x0226 Device 2: 0x02A6]

■ Device n Endpoint 3 Status Register [Device 1: 0x0236 Device 2: 0x02B6]

■ Device n Endpoint 4 Status Register [Device 1: 0x0246 Device 2: 0x02C6]

■ Device n Endpoint 5 Status Register [Device 1: 0x0256 Device 2: 0x02D6]

■ Device n Endpoint 6 Status Register [Device 1: 0x0266 Device 2: 0x02E6]

■ Device n Endpoint 7 Status Register [Device 1: 0x0276 Device 2: 0x02F6]

Table 66. Device n Endpoint n Status Register

Bit #

Reserved

Overflow

Flag

Underflow

Flag

OUT

Field

Exception Flag Exception Flag

Read/Write

Default

R/W

Bit #

Stall

Flag

NAK

Flag

Length

Setup

Flag

Sequence

Flag

Timeout

Flag

Error

ACK

Flag

Field

Exception Flag

Flag

R/W

Read/Write

Default

R/W

OUT Exception Flag (Bit 9)

The Device n Endpoint n Status register provides packet status

information for the last transaction received or transmitted. This

by firmware. There are a total of eight endpoints for each of the

two ports. All endpoints have the same definition for their Device

n Endpoint n Status register.

The OUT Exception Flag bit indicates when the device received

an OUT packet when armed for an IN.

1: Received OUT when armed for IN

0: Received IN when armed for IN

IN Exception Flag (Bit 8)

The Device n Endpoint n Status register is a memory based

operations are initiated. After initialization, do not write to this

The IN Exception Flag bit indicates when the device received an

IN packet when armed for an OUT.

1: Received IN when armed for OUT

0: Received OUT when armed for OUT

Overflow Flag (Bit 11)

The Overflow Flag bit indicates that the received data in the last

data transaction exceeded the maximum length specified in the

Device n Endpoint n Count register. The Overflow Flag must be

checked in response to a Length Exception signified by the

Length Exception Flag set to ‘1’.

Stall Flag (Bit 7)

The Stall Flag bit indicates that a Stall packet was sent to the

host.

1: Stall packet was sent to the host

0: Stall packet was not sent

1: Overflow condition occurred

0: Overflow condition did not occur

NAK Flag (Bit 6)

The NAK Flag bit indicates that a NAK packet was sent to the

host.

Underflow Flag (Bit 10)

The Underflow Flag bit indicates that the received data in the last

data transaction was less then the maximum length specified in

the Device n Endpoint n Count register. The Underflow Flag must

be checked in response to a Length Exception signified by the

Length Exception Flag set to ‘1’.

1: NAK packet was sent to the host

0: NAK packet was not sent

Length Exception Flag (Bit 5)

1: Underflow condition occurred

The Length Exception Flag bit indicates the received data in the

data stage of the last transaction does not equal the maximum

Endpoint Count specified in the Device n Endpoint n Count

0: Underflow condition did not occur

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underflow and the Overflow and Underflow flags (bits 11 and 10

respectively) must be checked to determine which event

occurred.

Timeout Flag (Bit 2)

The Timeout Flag bit indicates whether a timeout condition

occurred on the last transaction. On the device side, a timeout

can occur if the device sends a data packet in response to an IN

request but then does not receive a handshake packet in a

predetermined time. It can also occur if the device does not

receive the data stage of an OUT transfer in time.

1: An overflow or underflow condition occurred

0: An overflow or underflow condition did not occur

Setup Flag (Bit 4)

1: Timeout occurred

The Setup Flag bit indicates that a setup packet was received.

In device mode setup packets are stored at memory location

0x0300 for Device 1 and 0x0308 for Device 2. Setup packets are

always accepted regardless of the Direction Select and Arm

Enable bit settings as long as the Device n EP n Control register

Enable bit is set.

0: Timeout condition did not occur

Error Flag (Bit 2)

The Error Flag bit is set if a CRC5 and CRC16 error occurs, or if

an incorrect packet type is received. Overflow and underflow are

not considered errors and do not affect this bit.

1: Setup packet was received

0: Setup packet was not received

1: Error occurred

0: Error did not occur

Sequence Flag (Bit 3)

The Sequence Flag bit indicates whether the last data toggle

received was a DATA1 or a DATA0. This bit has no effect on

receiving data packets; sequence checking must be handled in

firmware.

ACK Flag (Bit 0)

The ACK Flag bit indicates whether the last transaction was

ACKed.

1: ACK occurred

1: DATA1 was received

0: DATA0 was received

0: ACK did not occur

Device n Endpoint n Count Result Register [R/W]

■ Device n Endpoint 0 Count Result Register [Device 1: 0x0208 Device 2: 0x0288]

■ Device n Endpoint 1 Count Result Register [Device 1: 0x0218 Device 2: 0x0298]

■ Device n Endpoint 2 Count Result Register [Device 1: 0x0228 Device 2: 0x02A8]

■ Device n Endpoint 3 Count Result Register [Device 1: 0x0238 Device 2: 0x02B8]

■ Device n Endpoint 4 Count Result Register [Device 1: 0x0248 Device 2: 0x02C8]

■ Device n Endpoint 5 Count Result Register [Device 1: 0x0258 Device 2: 0x02D8]

■ Device n Endpoint 6 Count Result Register [Device 1: 0x0268 Device 2: 0x02E8]

■ Device n Endpoint 7 Count Result Register [Device 1: 0x0278 Device 2: 0x02F8]

Table 67. Device n Endpoint n Count Result Register

Bit #

Field

Result...

...Result

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

Endpoint n Count register, the Length Exception Flag bit in the

Device n Endpoint n Status register is set. The value in this

and the Error Flag bit is not set; both bits are in the Device n

Endpoint n Status register.

The Device n Endpoint n Count Result register contains the size

difference in bytes between the Endpoint Count specified in the

Device n Endpoint n Count register and the last packet received.

If an overflow or underflow condition occurs, that is, the received

packet length differs from the value specified in the Device n

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The Device

Endpoint

Count Result register is

additional byte count of the received packet. If an underflow

condition occurs, Result [15:0] indicates the excess bytes count

(number of bytes not used).

memory-based register that must be initialized to 0x0000 before

USB Device operations are initiated. After initialization, do not

write to this register again.

Reserved

Result (Bits [15:0])

Write all reserved bits with ‘0’.

The Result field contains the differences in bytes between the

received packet and the value specified in the Device n Endpoint

n Count register. If an overflow condition occurs, Result [15:10]

is set to ‘111111’, a 2’s complement value indicating the

Device n Port Select Register [R/W]

■ Device n Port Select Register 0xC084

■ Device n Port Select Register 0xC0A4

Table 68. Device n Port Select Register

Bit #

Reserved

Port

Select

Reserved...

Field

Read/Write

Default

R/W

Bit #

Field

...Reserved

Read/Write

Default

Port Select (Bit 14)

The Device n Port Select register selects either port A or port B

for the static device port.

The Port Select bit selects which of the two ports is enabled.

1: Port 1B or Port 2B is enabled

0: Port 1A or Port 2A is enabled

Device n Interrupt Enable Register [R/W]

■ Device 1 Interrupt Enable Register 0xC08C

■ Device 2 Interrupt Enable Register 0xC0AC

Table 69. Device n Interrupt Enable Register

Bit #

VBUS

Interrupt

Enable

ID Interrupt

Enable

Reserved

SOF/EOP

Timeout

Interrupt

Enable

Reserved

SOF/EOP

Interrupt

Enable

Reset

Interrupt

Enable

Field

Read/Write

Default

R/W

Bit #

EP7 Interrupt EP6 Interrupt EP5 Interrupt EP4 Interrupt EP3 Interrupt EP2 Interrupt EP1 Interrupt EP0 Interrupt

Field

Enable

R/W

Enable

R/W

Enable

R/W

Enable

R/W

Enable

R/W

Enable

R/W

Enable

R/W

Enable

R/W

Read/Write

Default

VBUS Interrupt Enable (Bit 15)

The Device n Interrupt Enable register provides control over

device related interrupts including eight different endpoint inter-

rupts.

The VBUS Interrupt Enable bit enables or disables the OTG

VBUS interrupt. When enabled, this interrupt triggers on both the

rising and falling edge of VBUS at the 4.4V status (only

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supported in Port 1A). This bit is only available for Device 1 and

is a reserved bit in Device 2.

Enable bit in the Device n Endpoint Control register can also be

set so that NAK responses trigger this interrupt.

1: Enable VBUS interrupt

0: Disable VBUS interrupt

1: Enable EP6 Transaction Done interrupt

0: Disable EP6 Transaction Done interrupt

ID Interrupt Enable (Bit 14)

EP5 Interrupt Enable (Bit 5)

The ID Interrupt Enable bit enables or disables the OTG ID

interrupt. When enabled, this interrupt triggers on both the rising

and falling edge of the OTG ID pin (only supported in Port 1A).

This bit is only available for Device 1 and is a reserved bit in

Device 2.

The EP5 Interrupt Enable bit enables or disables endpoint five

(EP5) Transaction Done interrupt. An EPx Transaction Done

interrupt triggers when any of the following responses or events

occur in a transaction for the device’s supplied Endpoint:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, the NAK Interrupt

Enable bit in the Device n Endpoint Control register can also be

set so that NAK responses trigger this interrupt.

1: Enable ID interrupt

0: Disable ID interrupt

1: Enable EP5 Transaction Done interrupt

0: Disable EP5 Transaction Done interrupt

SOF/EOP Timeout Interrupt Enable (Bit 11)

The SOF/EOP Timeout Interrupt Enable bit enables or disables

the SOF/EOP Timeout Interrupt. When enabled this interrupt

triggers when the USB host fails to send a SOF or EOP packet

within the time period specified in the Device n SOF/EOP Count

number of times the SOF/EOP Timeout Interrupt triggers

between receiving SOF/EOPs.

EP4 Interrupt Enable (Bit 4)

The EP4 Interrupt Enable bit enables or disables endpoint four

(EP4) Transaction Done interrupt. An EPx Transaction Done

interrupt triggers when any of the following responses or events

occur in a transaction for the device’s supplied Endpoint:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, the NAK Interrupt

Enable bit in the Device n Endpoint Control register can also be

set so that NAK responses trigger this interrupt.

1: SOF/EOP timeout occurred

0: SOF/EOP timeout did not occur

SOF/EOP Interrupt Enable (Bit 9)

1: Enable EP4 Transaction Done interrupt

0: Disable EP4 Transaction Done interrupt

The SOF/EOP Interrupt Enable bit enables or disables the

SOF/EOP received interrupt.

EP3 Interrupt Enable (Bit 3)

1: Enable SOF/EOP received interrupt

0: Disable SOF/EOP received interrupt

The EP3 Interrupt Enable bit enables or disables endpoint three

(EP3) Transaction Done interrupt. An EPx Transaction Done

interrupt triggers when any of the following responses or events

occur in a transaction for the device’s supplied Endpoint:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, the NAK Interrupt

Enable bit in the Device n Endpoint Control register can also be

set so that NAK responses trigger this interrupt.

Reset Interrupt Enable (Bit 8)

The Reset Interrupt Enable bit enables or disables the USB

Reset Detected interrupt

1: Enable USB Reset Detected interrupt

0: Disable USB Reset Detected interrupt

1: Enable EP3 Transaction Done interrupt

0: Disable EP3 Transaction Done interrupt

EP7 Interrupt Enable (Bit 7)

The EP7 Interrupt Enable bit enables or disables endpoint seven

(EP7) Transaction Done interrupt. An EPx Transaction Done

interrupt triggers when any of the following responses or events

occur in a transaction for the device’s supplied Endpoint:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, the NAK Interrupt

Enable bit in the Device n Endpoint Control register can also be

set so that NAK responses trigger this interrupt.

EP2 Interrupt Enable (Bit 2)

The EP2 Interrupt Enable bit enables or disables endpoint two

(EP2) Transaction Done interrupt. An EPx Transaction Done

interrupt triggers when any of the following responses or events

occur in a transaction for the device’s supplied Endpoint:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, the NAK Interrupt

Enable bit in the Device n Endpoint Control register can also be

set so that NAK responses trigger this interrupt.

1: Enable EP7 Transaction Done interrupt

0: Disable EP7 Transaction Done interrupt

1: Enable EP2 Transaction Done interrupt

0: Disable EP2 Transaction Done interrupt

EP6 Interrupt Enable (Bit 6)

The EP6 Interrupt Enable bit enables or disables endpoint six

(EP6) Transaction Done interrupt. An EPx Transaction Done

interrupt triggers when any of the following responses or events

occur in a transaction for the device’s supplied Endpoint:

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, the NAK Interrupt

EP1 Interrupt Enable (Bit 1)

The EP1 Interrupt Enable bit enables or disables endpoint one

(EP1) Transaction Done interrupt. An EPx Transaction Done

interrupt triggers when any of the following responses or events

occur in a transaction for the device’s supplied Endpoint:

send/receive ACK, send STALL, Timeout occurs, IN Exception

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Error, or OUT Exception Error. In addition, the NAK Interrupt

Enable bit in the Device n Endpoint Control register can also be

set so that NAK responses trigger this interrupt.

send/receive ACK, send STALL, Timeout occurs, IN Exception

Error, or OUT Exception Error. In addition, the NAK Interrupt

Enable bit in the Device n Endpoint Control register can also be

set so that NAK responses trigger this interrupt.

1: Enable EP1 Transaction Done interrupt

0: Disable EP1 Transaction Done interrupt

1: Enable EP0 Transaction Done interrupt

0: Disable EP0 Transaction Done interrupt

EP0 Interrupt Enable (Bit 0)

Reserved

The EP0 Interrupt Enable bit enables or disables endpoint zero

(EP0) Transaction Done interrupt. An EPx Transaction Done

interrupt triggers when any of the following responses or events

occur in a transaction for the device’s supplied Endpoint:

Write all reserved bits with ’0’.

Device n Address Register [W]

■ Device 1 Address Register 0xC08E

■ Device 2 Address Register 0xC0AE

Table 70. Device n Address Register

Bit #

Field

Reserved...

Read/Write

Default

Bit #

Field

...Reserved

Address

Read/Write

Default

Address (Bits [6:0])

The Device n Address register holds the device address

assigned by the host. This register initializes to the default

address 0 at reset but must be updated by firmware when the

host assigns a new address. Only USB data sent to the address

contained in this register gets a respond—all others are ignored.

The Address field contains the USB address of the device

assigned by the host.

Reserved

Write all reserved bits with ’0’.

Device n Status Register [R/W]

■ Device 1 Status Register 0xC090

■ Device 2 Status Register 0xC0B0

Table 71. Device n Status Register

Bit #

VBUS Inter-

rupt

ID Interrupt

Flag

Reserved

SOF/EOP

Interrupt Flag

Reset Interrupt

Flag

Field

Flag

Read/Write

Default

R/W

Bit #

EP7 Interrupt EP6 Interrupt EP5 Interrupt EP4 Interrupt EP3 Interrupt EP2 Interrupt EP1 Interrupt EP0 Interrupt

Field

Flag

R/W

Flag

R/W

Flag

R/W

Flag

R/W

Flag

R/W

Flag

R/W

Flag

R/W

Flag

R/W

Read/Write

Default

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EP6 Interrupt Flag (Bit 6)

The Device n Status register provides status information for

device operation. Pending interrupts can be cleared by writing a

‘1’ to the corresponding bit. This register can be accessed by the

HPI interface.

The EP6 Interrupt Flag bit indicates if the endpoint six (EP6)

Transaction Done interrupt triggered. An EPx Transaction Done

interrupt triggers when any of the following responses or events

occur in a transaction for the device’s supplied EP: send/receive

ACK, send STALL, Timeout occurs, IN Exception Error, or OUT

Exception Error. In addition, if the NAK Interrupt Enable bit in the

Device n Endpoint Control register is set, this interrupt also

triggers when the device NAKs host requests.

VBUS Interrupt Flag (Bit 15)

The VBUS Interrupt Flag bit indicates the status of the OTG

VBUS interrupt (only for Port 1A). When enabled this interrupt

triggers on both the rising and falling edge of VBUS at 4.4V. This

bit is only available for Device 1 and is a reserved bit in Device 2.

1: Interrupt triggered

0: Interrupt did not trigger

1: Interrupt triggered

EP5 Interrupt Flag (Bit 5)

0: Interrupt did not trigger

The EP5 Interrupt Flag bit indicates if the endpoint five (EP5)

Transaction Done interrupt triggered. An EPx Transaction Done

interrupt triggers when any of the following responses or events

occur in a transaction for the device’s supplied EP: send/receive

ACK, send STALL, Timeout occurs, IN Exception Error, or OUT

Exception Error. In addition, if the NAK Interrupt Enable bit in the

Device n Endpoint Control register is set, this interrupt also

triggers when the device NAKs host requests.

ID Interrupt Flag (Bit 14)

The ID Interrupt Flag bit indicates the status of the OTG ID

interrupt (only for Port 1A). When enabled this interrupt triggers

on both the rising and falling edge of the OTG ID pin. This bit is

only available for Device 1 and is a reserved bit in Device 2.

1: Interrupt triggered

0: Interrupt did not trigger

1: Interrupt triggered

SOF/EOP Interrupt Flag (Bit 9)

0: Interrupt did not trigger

The SOF/EOP Interrupt Flag bit indicates if the SOF/EOP

received interrupt triggered.

EP4 Interrupt Flag (Bit 4)

The EP4 Interrupt Flag bit indicates if the endpoint four (EP4)

Transaction Done interrupt triggered. An EPx Transaction Done

interrupt triggers when any of the following responses or events

occur in a transaction for the device’s supplied EP: send/receive

ACK, send STALL, Timeout occurs, IN Exception Error, or OUT

Exception Error. In addition, if the NAK Interrupt Enable bit in the

Device n Endpoint Control register is set, this interrupt also

triggers when the device NAKs host requests.

1: Interrupt triggered

0: Interrupt did not trigger

Reset Interrupt Flag (Bit 8)

The Reset Interrupt Flag bit indicates if the USB Reset Detected

interrupt triggered.

1: Interrupt triggered

0: Interrupt did not trigger

EP7 Interrupt Flag (Bit 7)

EP3 Interrupt Flag (Bit 3)

The EP7 Interrupt Flag bit indicates if the endpoint seven (EP7)

Transaction Done interrupt triggered. An EPx Transaction Done

interrupt triggers when any of the following responses or events

occur in a transaction for the device’s supplied EP: send/receive

ACK, send STALL, Timeout occurs, IN Exception Error, or OUT

Exception Error. In addition, if the NAK Interrupt Enable bit in the

Device n Endpoint Control register is set, this interrupt also

triggers when the device NAKs host requests.

The EP3 Interrupt Flag bit indicates if the endpoint three (EP3)

Transaction Done interrupt triggered. An EPx Transaction Done

interrupt triggers when any of the following responses or events

occur in a transaction for the device’s supplied EP: send/receive

ACK, send STALL, Timeout occurs, IN Exception Error, or OUT

Exception Error. In addition, if the NAK Interrupt Enable bit in the

Device n Endpoint Control register is set, this interrupt also

triggers when the device NAKs host requests.

1: Interrupt triggered

0: Interrupt did not trigger

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EP2 Interrupt Flag (Bit 2)

Device n Endpoint Control register is set, this interrupt also

triggers when the device NAKs host requests.

The EP2 Interrupt Flag bit indicates if the endpoint two (EP2)

Transaction Done interrupt triggered. An EPx Transaction Done

interrupt triggers when any of the following responses or events

occur in a transaction for the device’s supplied EP: send/receive

ACK, send STALL, Timeout occurs, IN Exception Error, or OUT

Exception Error. In addition, if the NAK Interrupt Enable bit in the

Device n Endpoint Control register is set, this interrupt also

triggers when the device NAKs host requests.

1: Interrupt triggered

0: Interrupt did not trigger

EP0 Interrupt Flag (Bit 0)

The EP0 Interrupt Flag bit indicates if the endpoint zero (EP0)

Transaction Done interrupt triggered. An EPx Transaction Done

interrupt triggers when any of the following responses or events

occur in a transaction for the device’s supplied EP: send/receive

ACK, send STALL, Timeout occurs, IN Exception Error, or OUT

Exception Error. In addition, if the NAK Interrupt Enable bit in the

Device n Endpoint Control register is set, this interrupt also

triggers when the device NAKs host requests.

1: Interrupt triggered

0: Interrupt did not trigger

EP1 Interrupt Flag (Bit 1)

The EP1 Interrupt Flag bit indicates if the endpoint one (EP1)

Transaction Done interrupt triggered. An EPx Transaction Done

interrupt triggers when any of the following responses or events

occur in a transaction for the device’s supplied EP: send/receive

ACK, send STALL, Timeout occurs, IN Exception Error, or OUT

Exception Error. In addition, if the NAK Interrupt Enable bit in the

1: Interrupt triggered

0: Interrupt did not trigger

Reserved

Write all reserved bits with ’0’.

Device n Frame Number Register [R]

■ Device 1 Frame Number Register 0xC092

■ Device 2 Frame Number Register 0xC0B2

Table 72. Device n Frame Number Register

Bit #

SOF/EOP

Timeout Flag

SOF/EOP

Timeout Interrupt Counter

Reserved

Frame...

Field

Read/Write

Default

Bit #

Field

...Frame

Read/Write

Default

SOF/EOP Timeout Interrupt Counter (Bits [14:12])

The Device n Frame Number register is a read only register that

contains the Frame number of the last SOF packet received. This

The SOF/EOP Timeout Interrupt Counter field increments by 1

from 0 to 7 for each SOF/EOP Timeout Interrupt. This field resets

to 0 when a SOF/EOP is received. This field is only updated

when the SOF/EOP Timeout Interrupt Enable bit in the Device n

Interrupt Enable register is set.

SOF/EOP Timeout Flag (Bit 15)

The SOF/EOP Timeout Flag bit indicates when an SOF/EOP

Timeout Interrupt occurs.

Frame (Bits [10:0])

The Frame field contains the frame number from the last

received SOF packet in full-speed mode. This field no function

for low-speed mode. If a SOF Timeout occurs, this field contains

the last received Frame number.

1: An SOF/EOP Timeout interrupt occurred

0: An SOF/EOP Timeout interrupt did not occur

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Device n SOF/EOP Count Register [W]

■ Device 1 SOF/EOP Count Register 0xC094

■ Device 2 SOF/EOP Count Register 0xC0B4

Table 73. Device n SOF/EOP Count Register

Bit #

Field

Reserved

Count...

Read/Write

Default

Bit #

Field

...Count

Read/Write

Default

Reserved

The Device n SOF/EOP Count register is written with the time

expected between receiving a SOF/EOP. If the SOF/EOP

counter expires before an SOF/EOP is received, an SOF/EOP

Timeout Interrupt can be generated. The SOF/EOP Timeout

Interrupt Enable and SOF/EOP Timeout Interrupt Flag are

located in the Device n Interrupt Enable and Status registers

respectively.

Write all reserved bits with ’0’.

OTG Control Registers

There is one register dedicated for On-The-Go operation. This

Table 74. OTG Register

Set the SOF/EOP count slightly greater than the expected

SOF/EOP interval. The SOF/EOP counter decrements at a

12 MHz rate. Therefore, in the case of an expected 1 ms

SOF/EOP interval, the SOF/EOP count is set slightly greater

than 0x2EE0.

Address

R/W

OTG Control Register

C098H

R/W

Count (Bits [13:0])

The Count field contains the current value of the SOF/EOP down

counter. At power up and reset, this value is set to 0x2EE0 and

for expected 1 ms SOF/EOP intervals, this SOF/EOP count is

increased slightly.

OTG Control Register [0xC098] [R/W]

Table 75. OTG Control Register

Bit #

Reserved

VBUS

Pull-up Enable

Receive

Disable

Charge Pump

Enable

VBUS

D+

D–

Field

Discharge Enable Pull-up Enable

Pull-up Enable

Read/Write

Default

R/W

Bit #

D+

D–

Reserved

OTG Data

Status

VBUS Valid

Flag

Field

Pull-down Enable

Read/Write

Default

R/W

VBUS Pull-up Enable (Bit 13)

The OTG Control register allows control and monitoring over the

OTG port on Port1A. Note that the D± pull up and pull down bits

override the setting in the USB 0 Control register for this port.

The VBUS Pull-up Enable bit enables or disables a 500 ohm pull

up resistor onto OTG VBus.

1: 500 ohm pull up resistor enabled

0: 500 ohm pull up resistor disabled

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Receive Disable (Bit 12)

OTG Data Status (Bit 2)

The Receive Disable bit enables or powers down (disables) the

OTG receiver section.

The OTG Data Status bit is a read only bit and indicates the TTL

logic state of the OTG VBus pin.

1: OTG receiver powered down and disabled

0: OTG receiver enabled

1: OTG VBus is greater then 2.4V

0: OTG VBus is less then 0.8V

Charge Pump Enable (Bit 11)

ID Status (Bit 1)

The Charge Pump Enable bit enables or disables the OTG VBus

charge pump.

The ID Status bit is a read only bit that indicates the state of the

OTG ID pin on Port A.

1: OTG VBus charge pump enabled

0: OTG VBus charge pump disabled

1: OTG ID Pin is not connected directly to ground (>10K ohm)

0: OTG ID Pin is connected directly ground (< 10 ohm)

VBUS Discharge Enable (Bit 10)

VBUS Valid Flag (Bit 0)

The VBUS Discharge Enable bit enables or disables a 2K ohm

discharge pull down resistor onto OTG VBus.

The VBUS Valid Flag bit indicates whether OTG VBus is greater

then 4.4V. After turning on VBUS, firmware must wait at least 10

µs before this reading this bit.

1: 2K ohm pull down resistor enabled

0: 2K ohm pull down resistor disabled

1: OTG VBus is greater then 4.4V

0: OTG VBus is less then 4.4V

D+ Pull-up Enable (Bit 9)

Reserved

The D+ Pull-up Enable bit enables or disables a pull up resistor

on the OTG D+ data line.

Write all reserved bits with ’0’.

1: OTG D+ dataline pull up resistor enabled

0: OTG D+ dataline pull up resistor disabled

GPIO Registers

There are seven registers dedicated for GPIO operations. These

seven registers are covered in this section and summarized in

T a ble 76.

D– Pull-up Enable (Bit 8)

The D– Pull-up Enable bit enables or disables a pull up resistor

on the OTG D– data line.

Table 76. GPIO Registers

1: OTG D– dataline pull up resistor enabled

0: OTG D– dataline pull up resistor disabled

GPIO Control Register

Address

0xC006

R/W

D+ Pull-down Enable (Bit 7)

GPIO0 Output Data Register

GPIO0 Input Data Register

GPIO0 Direction Register

GPIO1 Output Data Register

GPIO1 Input Data Register

GPIO1 Direction Register

0xC01E

0xC020

0xC022

0xC024

0xC026

0xC028

The D+ Pull-down Enable bit enables or disables a pull down

resistor on the OTG D+ data line.

R/W

1: OTG D+ dataline pull down resistor enabled

0: OTG D+ dataline pull down resistor disabled

D– Pull-down Enable (Bit 6)

R/W

The D– Pull-down Enable bit enables or disables a pull down

resistor on the OTG D– data line.

1: OTG D– dataline pull down resistor enabled

0: OTG D– dataline pull down resistor disabled

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GPIO Control Register [0xC006] [R/W]

Table 77. GPIO Control Register

Bit #

Write Protect

Enable

Reserved

SAS

Enable

Mode

Select

Field

Read/Write

Default

R/W

Bit #

HSS

Enable

HSS XD

Enable

SPI

Enable

SPI XD

Enable

Interrupt 1

Polarity Select

Interrupt 1

Enable

Interrupt 0

Polarity Select

Interrupt 0

Enable

Field

Read/Write

Default

R/W

HSS Enable (Bit 7)

The GPIO Control register configures the GPIO pins for various

interface options. It also controls the polarity of the GPIO

interrupt on IRQ1 (GPIO25) and IRQ0 (GPIO24).

The HSS Enable bit routes HSS to GPIO[26, 18:16]. If the HSS

XD Enable bit is set, it overrides this bit and HSS is routed to

XD[15:12].

1: HSS is routed to GPIO

Write Protect Enable (Bit 15)

0: HSS is not routed to GPIOs. GPIO[26, 18:16] are free for other

purposes

The Write Protect Enable bit enables or disables the GPIO write

protect. When Write Protect is enabled, the GPIO Mode Select

[15:8] field is read only until a chip reset.

HSS XD Enable (Bit 6)

1: Enable Write Protect

0: Disable Write Protect

The HSS XD Enable bit routes HSS to XD[15:12] (external

memory data bus). This bit overrides the HSS Enable bit.

1: HSS is routed to XD[15:12]

UD (Bit 14)

0: HSS is not routed to XD[15:12]

The UD bit routes the Host/Device 1A Port’s transmitter enable

status to GPIO[30]. This is for use with an external ESD

protection circuit when needed.

SPI Enable (Bit 5)

The SPI Enable bit routes SPI to GPIO[11:8]. If the SAS Enable

bit is set, it overrides the SPI Enable and routes SPI_nSSI to

GPIO15. If the SPI XD Enable bit is set, it overrides both bits and

the SPI is routed to XD[11:8] (external memory data bus).

1: Route the signal to GPIO[30]

0: Do not route the signal to GPIO[30]

SAS Enable (Bit 11)

1: SPI is routed to GPIO[11:8]

The SAS Enable bit, when in SPI mode, reroutes the SPI port

SPI_nSSI pin to GPIO[15] rather then GPIO[9] or XD[9] (per

SG/SX).

0: SPI is not routed to GPIO[11:8]. GPIO[11:8] are free for other

purposes

SPI XD Enable (Bit 4)

1: Reroute SPI_nss to GPIO[30]

0: Leave SPI_nss on GPIO[9]

The SPI XD Enable bit routes SPI to XD[11:8] (external memory

data bus). This bit overrides the SPI Enable bit.

Mode Select (Bits [10:8])

1: SPI is routed to XD[11:8]

The Mode Select field selects how GPIO[15:0] and GPIO[24:19]

are used as defined in T a ble 78.

0: SPI is not routed to XD[11:8]

Interrupt 1 Polarity Select (Bit 3)

Table 78. Mode Select Definition

The Interrupt 1 Polarity Select bit selects the polarity for IRQ1.

1: Sets IRQ1 to rising edge

Mode Select

GPIO Configuration

[10:8]

111

110

Reserved

0: Sets IRQ1 to falling edge

SCAN — (HW) Scan diagnostic. For produc-

tion test only. Not for normal operation

Interrupt 1 Enable (Bit 2)

The Interrupt 1 Enable bit enables or disables IRQ1. The GPIO

bit on the interrupt Enable register must also be set in order for

this for this interrupt to be enabled.

101

100

011

010

001

000

HPI — Host Port Interface

IDE — Integrated Drive Electronics or

Reserved

1: Enable IRQ1

0: Disable IRQ1

GPIO — General Purpose Input Output

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Interrupt 0 Polarity Select (Bit 1)

Reserved

The Interrupt 0 Polarity Select bit selects the polarity for IRQ0.

1: Sets IRQ0 to rising edge

Write all reserved bits with ’0’.

0: Sets IRQ0 to falling edge

Interrupt 0 Enable (Bit 0)

The Interrupt 0 Enable bit enables or disables IRQ0. The GPIO

bit on the interrupt Enable register must also be set in order for

this for this interrupt to be enabled.

1: Enable IRQ0

0: Disable IRQ0

GPIO n Output Data Register [R/W]

■ GPIO 0 Output Data Register 0xC01E

■ GPIO 1 Output Data Register 0xC024

Table 79. GPIO n Output Data Register

Bit #

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

Field

Data...

...Data

Read/Write

Default

R/W

Bit #

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

Field

Read/Write

Default

R/W

Data (Bits [15:0])

The GPIO n Output Data register controls the output data of the

GPIO pins. The GPIO 0 Output Data register controls GPIO15 to

GPIO0 while the GPIO 1 Output Data register controls GPIO31

to GPIO16. When read, this register reads back the last data

written, not the data on pins configured as inputs (see Input Data

The Data field[15:0] writes to the corresponding GPIO 15–0 or

GPIO31–16 pins as output data.

GPIO n Input Data Register [R]

■ GPIO 0 Input Data Register 0xC020

■ GPIO 1 Input Data Register 0xC026

Table 80. GPIO n Input Data Register

Bit #

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

Field

Data...

...Data

Read/Write

Default

Bit #

23/7

22/6

21//5

20/4

19/3

18/2

17/1

16/0

Field

Read/Write

Default

Data (Bits [15:0])

The GPIO n Input Data register reads the input data of the GPIO

pins. The GPIO 0 Input Data register reads from GPIO15 to

GPIO0 while the GPIO 1 Input Data register reads from GPIO31

to GPIO16.

The Data field[15:0] contains the voltage values on the corre-

sponding GPIO15–0 or GPIO31–16 input pins.

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GPIO n Direction Register [R/W]

■ GPIO 0 Direction Register 0xC022

■ GPIO 1 Direction Register 0xC028

Table 81. GPIO n Direction Register

Bit #

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

Field

Direction Select...

Read/Write

Default

R/W

Bit #

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

Field

...Direction Select

Read/Write

Default

R/W

IDE Registers

The GPIO n Direction register controls the direction of the GPIO

data pins (input/output). The GPIO 0 Direction register controls

GPIO15 to GPIO0 while the GPIO 1 Direction register controls

GPIO31 to GPIO16.

In addition to the standard IDE PIO Port registers, there are four

registers dedicated to IDE operation. These registers are

covered in this section and summarized in T a ble 82.

Table 82. IDE Registers

Direction Select (Bits [15:0])

Address

0xC048

R/W

The Direction Select field[15:0] configures the corresponding

GPIO15–0 or GPIO31–16 pins as either input or output. When

any bit of this register is set to ‘1’, the corresponding GPIO data

pin becomes an output. When any bit of this register is set to ‘0’,

the corresponding GPIO data pin becomes an input.

IDE Mode Register

IDE Start Address Register 0xC04A

IDE Stop Address Register 0xC04C

IDE Control Register

0xC04E

IDE PIO Port Registers

0xC050-0xC06F

IDE Mode Register [0xC048] [R/ W]

Table 83. IDE Mode Register

Bit #

Field

Reserved...

Read/Write

Default

Bit #

Field

...Reserved

Mode Select

Read/Write

Default

R/W

Mode Select (Bits [2:0])

The IDE Mode register allows the selection of IDE PIO Modes 0,

1, 2, 3, or 4. The default setting is zero which means IDE PIO

Mode 0.

The Mode Select field sets PIO Mode 0 to 4 in IDE mode. Refer

to T a ble 84 on page 53 for a definition of this field.

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Table 84. Mode Select Definition

Mode Select [2:0]

Mode

IDE PIO Mode 0

IDE PIO Mode 1

IDE PIO Mode 2

IDE PIO Mode 3

IDE PIO Mode 4

Reserved

000

001

010

011

100

101

110

111

Reserved

Disable IDE port operations

Reserved

Write all reserved bits with ’0’.

IDE Start Address Register [0xC04A] [R/W]

Table 85. IDE Start Address Register

Bit #

Field

Address...

...Address

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

The hardware keeps an internal memory address counter. The

two MSBs of the addresses are not modified by the address

counter. Therefore, the IDE Start Address and IDE Stop Address

must reside within the same 16K byte block.

The IDE Start Address register holds the start address for an IDE

block transfer. This register is byte addressed and IDE block

transfers are 16-bit words, therefore the LSB of the start address

is ignored. Block transfers begin at IDE Start Address and end

with the final word at IDE Stop Address. When IDE Start Address

equals IDE Stop Address, the block transfer moves one word of

data.

Address (Bits [15:0])

The Address field sets the start address for an IDE block transfer.

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IDE Stop Address Register [0xC04C] [R/W]

Table 86. IDE Stop Address Register

Bit #

Field

Address...

...Address

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

The hardware keeps an internal memory address counter. The

two MSBs of the addresses are not modified by the address

counter. Therefore the IDE Start Address and IDE Stop Address

must reside within the same 16K byte block.

The IDE Stop Address register holds the stop address for an IDE

block transfer. This register is byte addressed and IDE block

transfers are 16-bit words, therefore the LSB of the stop address

is ignored. Block transfers begin at IDE Start Address and end

with the final word at IDE Stop Address. When IDE Start Address

equals IDE Stop Address, the block transfer moves one word of

data.

Address (Bits [15:0])

The Address field sets the stop address for an IDE block transfer.

IDE Control Register [0xC04E] [R/W]

Table 87. IDE Control Register

Bit #

Field

Reserved...

Read/Write

Default

Bit #

...Reserved

Direction

Select

IDE

Interrupt

Enable

Done

Flag

IDE

Enable

Field

Read/Write

Default

R/W

Done Flag (Bit 1)

The IDE Control register controls block transfers in IDE mode.

The Done Flag bit is automatically set to ‘1’ by hardware when a

block transfer is complete. The CPU clears this bit by writing a

‘0’ to it. When IDE Interrupt Enable is set this bit generates the

signal for the cpuide_intr interrupt.

Direction Select (Bit 3)

The Direction Select bit sets the block mode transfer direction.

1: Data is written to the external device

0: Data is read from the external device

1: Block transfer is complete

0: Clears IDE Done Flag

IDE Enable (Bit 0)

IDE Interrupt Enable (Bit 2)

The IDE Enable bit starts a block transfer. It is reset to ‘0’ when

the block transfer is complete

The IDE Interrupt Enable bit enables or disables the block

transfer done interrupt. When enabled, the Done Flag is sent to

the CPU as cpuide_intr interrupt. When disabled, the cpuide_intr

is set LOW.

1: Start block transfer

0: Block transfer complete

1: Enable block transfer done interrupt

0: Disable block transfer done interrupt

Reserved

Write all reserved bits with ’0’.

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IDE PIO Port Registers [0xC050 - 0xC06F] [R/W]

All IDE PIO Port registers [0xC050 - 0xC06F] in T a ble 88 are defined in detail in the Information Technology-AT Attachment -4 with

Packet Interface Extension (ATA/ATAPI-4) Specification, T13/1153D Rev 18. The table Address column denotes the CY7C67300

register address for the corresponding ATA/ATAPI register. The IDE_nCS[1:0] field defines the ATA interface CS addressing bits and

the IDE_A[2:0] field define the ATA interface address bits. The combination of IDE_nCS and IDE_A are the ATA interface register

address.

Table 88. IDE PIO Port Registers

Address

0xC050

0xC052

ATA/ATAPI Register

IDE_nCS[1:0]

IDE_A[2:0]

‘000’

DATA Register

‘10’

Read: Error Register

Write: Feature Register

‘001’

0xC054

0xC056

0xC058

0xC05A

0xC05C

0xC05E

Sector Count Register

Sector Number Register

Cylinder Low Register

Cylinder High Register

Device/Head Register

‘10’

‘010’

‘011’

‘100’

‘101’

‘110’

‘111’

Read: Status Register

Write: Command Register

0xC060

0xC062

0xC064

0xC066

0xC068

0xC06A

0xC06C

Not Defined

‘01’

‘000’

‘001’

‘010’

‘011’

‘100’

‘101’

‘110’

Read: Alternate Status Register

Write: Device Control Register

0xC06E

Not Defined

‘01’

‘111’

HSS Registers

There are eight registers dedicated to HSS operation. Each of these registers are covered in this section and summarized in T a ble 89.

Table 89. HSS Registers

Address

R/W

HSS Control Register

HSS Baud Rate Register

HSS Transmit Gap Register

HSS Data Register

0xC070

0xC072

0xC074

0xC076

0xC078

0xC07A

0xC07C

0xC07E

R/W

HSS Receive Address Register

HSS Receive Length Register

HSS Transmit Address Register

HSS Transmit Length Register

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HSS Control Register [0xC070] [R/W]

Table 90. HSS Control Register

Bit #

HSS

Enable

RTS

Polarity

Select

CTS

Polarity

Select

XOFF

Enable

CTS

Enable

Receive

Interrupt

Enable

Done

Interrupt

Enable

Field

Read/Write

Default

R/W

Bit #

Transmit

Receive

One

Transmit

Ready

Packet

Mode

Receive

Overflow

Flag

Receive

Packet Ready

Flag

Receive

Ready

Flag

Done Interrupt Done Interrupt

Stop Bit

Field

Enable

R/W

Enable

R/W

Select

Read/Write

Default

R/W

Receive Interrupt Enable (Bit 9)

The HSS Control register provides high level status and control

over the HSS port.

The Receive Interrupt Enable bit enables or disables the Receive

Ready and Receive Packet Ready interrupts.

1: Enable the Receive Ready and Receive Packet Ready inter-

rupts

HSS Enable (Bit 15)

The HSS Enable bit enables or disables HSS operation.

1: Enables HSS operation

0: Disable the Receive Ready and Receive Packet Ready inter-

rupts

0: Disables HSS operation

Done Interrupt Enable (Bit 8)

RTS Polarity Select (Bit 14)

The Done Interrupt Enable bit enables or disables the Transmit

Done and Receive Done interrupts.

The RTS Polarity Select bit selects the polarity of RTS.

1: RTS is true when LOW

1: Enable the Transmit Done and Receive Done interrupts

0: Disable the Transmit Done and Receive Done interrupts

0: RTS is true when HIGH

Transmit Done Interrupt Flag (Bit 7)

CTS Polarity Select (Bit 13)

The Transmit Done Interrupt Flag bit indicates the status of the

Transmit Done Interrupt. It sets when a block transmit is finished.

To clear the interrupt, write a ‘1’ to this bit.

The CTS Polarity Select bit selects the polarity of CTS.

1: CTS is true when LOW

0: CTS is true when HIGH

1: Interrupt triggered

XOFF (Bit 12)

0: Interrupt did not trigger

The XOFF bit is a read only bit that indicates if an XOFF was

received. This bit is automatically cleared when an XON is

received.

Receive Done Interrupt Flag (Bit 6)

The Receive Done Interrupt Flag bit indicates the status of the

Receive Done Interrupt. It sets when a block transmit is finished.

To clear the interrupt, write a ‘1’ to this bit.

1: XOFF received

0: XON received

1: Interrupt triggered

XOFF Enable (Bit 11)

0: Interrupt did not trigger

The XOFF Enable bit enables or disables XON/XOFF software

handshaking.

One Stop Bit (Bit 5)

The One Stop Bit bit selects between one and two stop bits for

transmit byte mode. In receive mode, the number of stop bits

may vary and does not need to be fixed.

1: Enable XON/XOFF software handshaking

0: Disable XON/XOFF software handshaking

1: One stop bit

0: Two stop bits

CTS Enable (Bit 10)

The CTS Enable bit enables or disables CTS/RTS hardware

handshaking.

1: Enable CTS/RTS hardware handshaking

0: Disable CTS/RTS hardware handshaking

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Transmit Ready (Bit 4)

1: Overflow occurred

The Transmit Ready bit is a read only bit that indicates if the HSS

Transmit FIFO is ready for the CPU to load new data for trans-

mission.

0: Overflow did not occur

Receive Packet Ready Flag (Bit 1)

The Receive Packet Ready Flag bit is a read only bit that

indicates if the HSS receive FIFO is full with eight bytes or not.

1: HSS transmit FIFO ready for loading

0: HSS transmit FIFO not ready for loading

1: HSS receive FIFO is full

Packet Mode Select (Bit 3)

0: HSS receive FIFO is not full

The Packet Mode Select bit selects between Receive Packet

Ready and Receive Ready as the interrupt source for the RxIntr

interrupt.

Receive Ready Flag (Bit 0)

The Receive Ready Flag is a read only bit that indicates if the

HSS receive FIFO is empty or not.

1: Selects Receive Packet Ready as the source

0: Selects Receive Ready as the source

1: HSS receive FIFO is not empty (one or more bytes is reading

for reading)

Receive Overflow Flag (Bit 2)

0: HSS receive FIFO is empty

The Receive Overflow Flag bit indicates if the Receive FIFO

overflowed when set. This flag can be cleared by writing a ‘1’ to

this bit.

HSS Baud Rate Register [0xC072] [R/W]

Table 91. HSS Baud Rate Register

Bit #

Baud...

R/W

Field

Reserved

Read/Write

Default

R/W

Bit #

Field

...Baud

Read/Write

Default

R/W

Reserved

Write all reserved bits with ’0’.

The HSS Baud Rate register sets the HSS Baud Rate. At reset,

the default value is 0x0017 which sets the baud rate to 2.0 MHz.

Baud (Bits [12:0])

The Baud field is the baud rate divisor minus one, in units of 1/48

MHz. Therefore the Baud Rate = 48 MHz/(Baud + 1). This puts

a constraint on the Baud Value as follows:

(24 – 1) ≤ Baud ≥ (5000 – 1)

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HSS Transmit Gap Register [0xC074] [R/W]

Table 92. HSS Transmit Gap Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

Field

Transmit Gap Select

Read/Write

Default

R/W

Reserved

Write all reserved bits with ’0’.

The HSS Transmit Gap register is only valid in block transmit

mode. It allows for a programmable number of stop bits to be

inserted, thus overwriting the One Stop Bit in the HSS Control

alent to two stop bits.

Transmit Gap Select (Bits [7:0])

The Transmit Gap Select field sets the inactive time between

transmitted bytes. The inactive time = (Transmit Gap Select –7)

* bit time. Therefore a Transmit Gap Select Value of 8 is equal to

having one Stop bit.

HSS Data Register [0xC076] [R/W]

Table 93. HSS Data Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

Field

Data

Read/Write

Default

R/W

Data (Bits [7:0])

The HSS Data register contains data received on the HSS port

(not for block receive mode) when read. This receive data is valid

when the Receive Ready bit of the HSS Control register is set to

‘1’. Writing to this register initiates a single byte transfer of data.

The Transmit Ready Flag in the HSS Control register must read

‘1’ before writing to this register (this avoids disrupting the

previous/current transmission).

The Data field contains the data received or to be transmitted on

the HSS port.

Reserved

Write all reserved bits with ’0’.

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HSS Receive Address Register [0xC078] [R/W]

Table 94. HSS Receive Address Register

Bit #

Field

Address...

...Address

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

Address (Bits [15:0])

The HSS Receive Address register is used as the base pointer

address for the next HSS block receive transfer.

The Address field sets the base pointer address for the next HSS

block receive transfer.

HSS Receive Counter Register [0xC07A] [R/W]

Table 95. HSS Receive Counter Register

Bit #

Field

Reserved

Counter...

Read/Write

Default

R/W

Bit #

Field

...Counter

Read/Write

Default

R/W

Counter (Bits [9:0])

The HSS Receive Counter register designates the block byte

length for the next HSS receive transfer. Load this register with

the word count minus one to start the block receive transfer. As

each byte is received this register value is decremented. When

read, this register indicates the remaining length of the transfer.

The Counter field value is equal to the word count minus one

giving a maximum value of 0x03FF (1023) or 2048 bytes. When

the transfer is complete this register returns 0x03FF until

reloaded.

Reserved

Write all reserved bits with ’0’.

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HSS Transmit Address Register [0xC07C] [R/W]

Table 96. HSS Transmit Address Register

Bit #

Field

Address...

...Address

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

Address (Bits [15:0])

The HSS Transmit Address register is used as the base pointer

address for the next HSS block transmit transfer.

The Address field sets the base pointer address for the next HSS

block transmit transfer.

HSS Transmit Counter Register [0xC07E] [R/W]

Table 97. HSS Transmit Counter Register

Bit #

Field

Reserved

Counter...

Read/Write

Default

R/W

Bit #

Field

...Counter

Read/Write

Default

R/W

Counter (Bits [9:0])

The HSS Transmit Counter register designates the block byte

length for the next HSS transmit transfer. Load this register with

the word count minus one to start the block transmit transfer. As

each byte is transmitted this register value is decremented.

When read, this register indicates the remaining length of the

transfer.

The Counter field value is equal to the word count minus one

giving a maximum value of 0x03FF (1023) or 2048 bytes. When

the transfer is complete this register returns 0x03FF until

reloaded.

Reserved

Write all reserved bits with ’0’.

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HPI Registers

Table 98. HPI Registers

There are five registers dedicated to HPI operation. In addition,

there is an HPI status port which can be addressed over HPI.

Each of these registers is covered in this section and are summa-

rized in T a ble 98.

HPI Breakpoint Register

Interrupt Routing Register

SIE1msg Register

Address

0x0140

R/W

0x0142

0x0144

0x0148

0xC0C6

SIE2msg Register

HPI Mailbox Register

R/W

HPI Breakpoint Register [0x0140] [R]

Table 99. HPI Breakpoint Register

Bit #

Field

Address...

...Address

Read/Write

Default

Bit #

Field

Read/Write

Default

When the program counter matches the Breakpoint Address, the

INT127 interrupt triggers. To clear this interrupt, write a zero a to

this register.

The HPI Breakpoint register is a special on-chip memory location

that the external processor can access using normal HPI

memory read/write cycles. This register is read only by the CPU

but is read/write by the HPI port. The contents of this register

have the same effect as the Breakpoint register [0xC014]. This

special Breakpoint register is used by software debuggers that

interface through the HPI port instead of the serial port.

Address (Bits [15:0])

The Address field is a 16-bit field containing the breakpoint

address.

Interrupt Routing Register [0x0142] [R]

Table 100. Interrupt Routing Register

Bit #

VBUS to HPI

Enable

ID to HPI

Enable

SOF/EOP2 to SOF/EOP2 to SOF/EOP1 to SOF/EOP1 to Reset2 to HPI HPI Swap 1

Field

HPI Enable

CPU Enable

HPI Enable

CPU Enable

Enable

Read/Write

Default

Bit #

Resume2 to

HPI Enable

Resume1 to

HPI Enable

Reserved

Done2 to HPI Done1 to HPI Reset1 to HPI HPI Swap 0

Field

Enable

Read/Write

Default

where the interrupts are routed. The individual interrupt enable

is handled in the SIE interrupt enable register.

The Interrupt Routing register allows the HPI port to take over

some or all of the SIE interrupts that usually go to the on-chip

CPU. This register is read only by the CPU but is read/write by

the HPI port. By setting the appropriate bit to ‘1’, the SIE interrupt

is routed to the HPI port to become the HPI_INTR signal and also

readable in the HPI Status register. The bits in this register select

VBUS to HPI Enable (Bit 15)

The VBUS to HPI Enable bit routes the OTG VBUS interrupt to

the HPI port instead of the on-chip CPU.

1: Route signal to HPI port

0: Do not route signal to HPI port

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ID to HPI Enable (Bit 14)

Resume2 to HPI Enable (Bit 7)

The ID to HPI Enable bit routes the OTG ID interrupt to the HPI

port instead of the on-chip CPU.

The Resume2 to HPI Enable bit routes the USB Resume

interrupt that occurs on Host 2 to the HPI port instead of the

on-chip CPU.

1: Route signal to HPI port

0: Do not route signal to HPI port

SOF/EOP2 to HPI Enable (Bit 13)

Resume1 to HPI Enable (Bit 6)

The SOF/EOP2 to HPI Enable bit routes the SOF/EOP2 interrupt

to the HPI port.

The Resume1 to HPI Enable bit routes the USB Resume

interrupt that occurs on Host 1 to the HPI port instead of the

on-chip CPU.

1: Route signal to HPI port

0: Do not route signal to HPI port

1: Route signal to HPI port

SOF/EOP2 to CPU Enable (Bit 12)

0: Do not route signal to HPI port

The SOF/EOP2 to CPU Enable bit routes the SOF/EOP2

interrupt to the on-chip CPU. Since the SOF/EOP2 interrupt can

be routed to both the on-chip CPU and the HPI port, the firmware

must ensure only one of the two (CPU, HPI) resets the interrupt.

Done2 to HPI Enable (Bit 3)

The Done2 to HPI Enable bit routes the Done interrupt for

Host/Device 2 to the HPI port instead of the on-chip CPU.

1: Route signal to CPU

1: Route signal to HPI port

0: Do not route signal to CPU

0: Do not route signal to HPI port

SOF/EOP1 to HPI Enable (Bit 11)

Done1 to HPI Enable (Bit 2)

The SOF/EOP1 to HPI Enable bit routes the SOF/EOP1 interrupt

to the HPI port.

The Done1 to HPI Enable bit routes the Done interrupt for

Host/Device 1 to the HPI port instead of the on-chip CPU.

1: Route signal to HPI port

0: Do not route signal to HPI port

SOF/EOP1 to CPU Enable (Bit 10)

Reset1 to HPI Enable (Bit 1)

The SOF/EOP1 to CPU Enable bit routes the SOF/EOP1

interrupt to the on-chip CPU. Since the SOF/EOP1 interrupt can

be routed to both the on-chip CPU and the HPI port, the firmware

must ensure only one of the two (CPU, HPI) resets the interrupt.

The Reset1 to HPI Enable bit routes the USB Reset interrupt that

occurs on Device 1 to the HPI port instead of the on-chip CPU.

1: Route signal to HPI port

0: Do not route signal to HPI port

1: Route signal to CPU

HPI Swap 0 Enable (Bit 0)

0: Do not route signal to CPU

Both HPI Swap bits (bits 8 and 0) must be set to identical values.

When set to ‘00’, the most significant data byte goes to

HPI_D[15:8] and the least significant byte goes to HPI_D[7:0].

This is the default setting. By setting to ‘11’, the most significant

data byte goes to HPI_D[7:0] and the least significant byte goes

to HPI_D[15:8].

Reset2 to HPI Enable (Bit 9)

The Reset2 to HPI Enable bit routes the USB Reset interrupt that

occurs on Device 2 to the HPI port instead of the on-chip CPU.

1: Route signal to HPI port

0: Do not route signal to HPI port

HPI Swap 1 Enable (Bit 8)

Both HPI Swap bits (bits 8 and 0) must be set to identical values.

When set to ‘00’, the most significant data byte goes to

HPI_D[15:8] and the least significant byte goes to HPI_D[7:0].

This is the default setting. By setting to ‘11’, the most significant

data byte goes to HPI_D[7:0] and the least significant byte goes

to HPI_D[15:8].

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SIEXmsg Register [W]

■ SIE1msg Register 0x0144

■ SIE2msg Register 0x0148

Table 101. SIEXmsg Register

Bit #

Field

Data...

...Data

Read/Write

Default

Bit #

Field

Read/Write

Default

Data (Bits [15:0])

The SIEXmsg register allows an interrupt to be generated on the

HPI port. Any write to this register causes the SIEXmsg flag in

the HPI Status Port to go high and also causes an interrupt on

the HPI_INTR pin. The SIEXmsg flag is automatically cleared

when the HPI port reads from this register.

The Data field[15:0] simply needs to have any value written to it

to cause SIExmsg flag in the HPI Status Port to go high.

HPI Mailbox Register [0xC0C6] [R/W]

Table 102. HPI Mailbox Register

Bit #

Field

Message...

...Message

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

In addition, when the CY7C67300 writes to this register, the

HPI_INTR signal on the HPI port asserts, signaling the external

processor that there is data in the mailbox to read. The

HPI_INTR signal deasserts when the external host processor

reads from this register.

The HPI Mailbox register provides a common mailbox between

the CY7C67300 and the external host processor.

If enabled, the HPI Mailbox RX Full interrupt triggers when the

external host processor writes to this register. When the

CY7C67300 reads this register the HPI Mailbox RX Full interrupt

is automatically cleared.

Message (Bits [15:0])

The Message field contains the message that the host processor

wrote to the HPI Mailbox register.

If enabled, the HPI Mailbox TX Empty interrupt triggers when the

external host processor reads from this register. The HPI Mailbox

TX Empty interrupt automatically clears when the CY7C67300

writes to this register.

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HPI Status Port [] [HPI: R]

Table 103. HPI Status Port

Bit #

VBUS

Flag

Reserved

SOF/EOP2

Flag

Reserved

SOF/EOP1

Flag

Reset2

Flag

Mailbox In

Flag

Field

Read/Write

Default

Bit #

Resume2

Flag

Resume1

Flag

SIE2msg

SIE1msg

Done2

Flag

Done1

Flag

Reset1

Flag

Mailbox Out

Flag

Field

Read/Write

Default

Mailbox In Flag (Bit 8)

The HPI Status Port provides the external host processor with

the MailBox status bits plus several SIE status bits. This register

is not accessible from the on-chip CPU. The additional SIE status

bits are provided to aid external device driver firmware devel-

opment, and are not recommended for applications that do not

have an intimate relationship with the on-chip BIOS.

The Mailbox In Flag bit is a read only bit that indicates if a

message is ready in the incoming mailbox. This interrupt clears

when the on-chip CPU reads from the HPI Mailbox register.

1: Interrupt triggered

0: Interrupt did not trigger

Reading from the HPI Status Port does not result in a CPU HPI

interface memory access cycle. The external host may continu-

ously poll this register without degrading the CPU or DMA perfor-

mance.

Resume2 Flag (Bit 7)

The Resume2 Flag bit is a read only bit that indicates if a USB

resume interrupt occurs on either Host/Device 2.

1: Interrupt triggered

VBUS Flag (Bit 15)

0: Interrupt did not trigger

The VBUS Flag bit is a read only bit that indicates whether OTG

VBus is greater than 4.4V. After turning on VBUS, firmware must

wait at least 10 µs before this reading this bit.

Resume1 Flag (Bit 6)

The Resume1 Flag bit is a read only bit that indicates if a USB

resume interrupt occurs on either Host/Device 1.

1: OTG VBus is greater than 4.4V

0: OTG VBus is less than 4.4V

1: Interrupt triggered

0: Interrupt did not trigger

ID Flag (Bit 14)

SIE2msg (Bit 5)

The ID Flag bit is a read only bit that indicates the state of the

OTG ID pin.

The SIE2msg Flag bit is a read only bit that indicates if the

CY7C67300 CPU wrote to the SIE2msg register. This bit is

cleared on an HPI read.

SOF/EOP2 Flag (Bit 12)

The SOF/EOP2 Flag bit is a read only bit that indicates if a

SOF/EOP interrupt occurs on either Host/Device 2.

1: The SIE2msg register was written by the CY7C67300 CPU

0: The SIE2msg register was not written by the CY7C67300 CPU

1: Interrupt triggered

SIE1msg (Bit 4)

0: Interrupt did not trigger

The SIE1msg Flag bit is a read only bit that indicates if the

CY7C67300 CPU wrote to the SIE1msg register. This bit is

cleared on an HPI read.

SOF/EOP1 Flag (Bit 10)

The SOF/EOP1 Flag bit is a read only bit that indicates if a

SOF/EOP interrupt occurs on either Host/Device 1.

1: The SIE1msg register was written by the CY7C67300 CPU

0: The SIE1msg register was not written by the CY7C67300 CPU

1: Interrupt triggered

0: Interrupt did not trigger

Done2 Flag (Bit 3)

Reset2 Flag (Bit 9)

In host mode the Done2 Flag bit is a read only bit that indicates

if a host packet done interrupt occurs on Host 2. In device mode

this read only bit indicates if an any of the endpoint interrupts

occur on Device 2. Firmware needs to determine which endpoint

interrupt occurred.

The Reset2 Flag bit is a read only bit that indicates if a USB

Reset interrupt occurs on either Host/Device 2.

1: Interrupt triggered

0: Interrupt did not trigger

1: Interrupt triggered

0: Interrupt did not trigger

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Done1 Flag (Bit 2)

The Reset1 Flag bit is a read only bit that indicates if a USB

Reset interrupt occurs on either Host/Device 1.

In host mode the Done 1 Flag bit is a read only bit that indicates

if a host packet done interrupt occurs on Host 1. In device mode

this read only bit indicates if an any of the endpoint interrupts

occur on Device 1. Firmware needs to determine which endpoint

interrupt occurred.

1: Interrupt triggered

0: Interrupt did not trigger

Mailbox Out Flag (Bit 0)

1: Interrupt triggered

The Mailbox Out Flag bit is a read only bit that indicates if a

message is ready in the outgoing mailbox. This interrupt clears

when the external host reads from the HPI Mailbox register.

0: Interrupt did not trigger

Reset1 Flag (Bit 1)

1: Interrupt triggered

0: Interrupt did not trigger

SPI Registers

There are twelve registers dedicated to SPI operation. Each of these registers is covered in this section and summarized in T a ble 104.

Table 104. SPI Registers

Address

R/W

SPI Configuration Register

SPI Control Register

0xC0C8

0xC0CA

0xC0CC

0xC0CE

0xC0D0

0xC0D2

0xC0D4

0xC0D6

0xC0D8

0xC0DA

0xC0DC

0xC0DE

R/W

SPI Interrupt Enable Register

SPI Status Register

SPI Interrupt Clear Register

SPI CRC Control Register

SPI CRC Value

R/W

SPI Data Register

SPI Transmit Address Register

SPI Transmit Count Register

SPI Receive Address Register

SPI Receive Count Register

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SPI Configuration Register [0xC0C8] [R/W]

Table 105. SPI Configuration Register

Bit #

3Wire

Enable

Phase

Select

SCK Polarity

Select

Scale Select

Reserved

Field

Read/Write

Default

R/W

Bit #

Master

Active

Enable

Master

Enable

SS Delay Select

Field

Read/Write

Default

R/W

Table 106. Scale Select Field Definition for SCK Frequency

The SPI Configuration register controls the SPI port. Fields apply

to both master and slave mode unless otherwise noted.

Scale Select [12:9]

SCK Frequency

500 KHz

1001

1010

1011

1100

1101

1110

1111

3Wire Enable (Bit 15)

375 KHz

The 3Wire Enable bit indicates if the MISO and MOSI data lines

are tied together allowing only half duplex operation.

250 KHz

375 KHz

1: MISO and MOSI data lines are tied together

250 KHz

0: Normal MISO and MOSI Full Duplex operation (not tied

together)

375 KHz

250 KHz

Phase Select (Bit 14)

Master Active Enable (Bit 7)

The Phase Select bit selects advanced or delayed SCK phase.

This field only applies to master mode.

The Master Active Enable bit is a read only bit that indicates if

the master state machine is active or idle. This field only applies

to master mode.

1: Advanced SCK phase

0: Delayed SCK phase

1: Master state machine is active

0: Master state machine is idle

SCK Polarity Select (Bit 13)

This SCK Polarity Select bit selects the polarity of SCK.

1: Positive SCK polarity

Master Enable (Bit 6)

The Master Enable bit sets the SPI interface to master or slave.

This bit is only writable when the Master Active Enable bit reads

‘0’, otherwise the value does not change.

0: Negative SCK polarity

Scale Select (Bits [12:9])

1: Master SPI interface

0: Slave SPI interface

The Scale Select field provides control over the SCK frequency,

based on 48 MHz. Refer to T a ble 106 for a definition of this field.

This field only applies to master mode.

SS Enable (Bit 5)

Table 106. Scale Select Field Definition for SCK Frequency

The SS Enable bit enables or disables the master SS output.

1: Enable master SS output

Scale Select [12:9]

SCK Frequency

12 MHz

8 MHz

0000

0001

0010

0011

0100

0101

0110

0111

1000

0: Disable master SS output (three state master SS output, for

single SS line in slave mode)

6 MHz

SS Delay Select (Bits [4:0])

4 MHz

When the SS Delay Select field is set to ‘00000’ this indicates

manual mode. In manual mode SS is controlled by the SS

Manual bit of the SPI Control register. When the SS Delay Select

field is set between ‘00001’ to ‘11111’, this value indicates the

count in half bit times of auto transfer delay for: SS low to SCK

active, SCK inactive to SS high, SS high time. This field only

applies to master mode.

3 MHz

2 MHz

1.5 MHz

1 MHz

750 KHz

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SPI Control Register [0xC0CA] [R/W]

Table 107. SPI Control Register

Bit #

SCK

Strobe

FIFO

Init

Byte

Mode

Full Duplex

Manual

Read

Enable

Transmit

Ready

Receive

Data

Ready

Field

Read/Write

Default

R/W

Bit #

Transmit

Empty

Receive

Full

Transmit Bit Length

Receive Bit Length

Field

Read/Write

Default

R/W

Read Enable (Bit 10)

The SPI Control register controls the SPI port. Fields apply to

both master and slave mode unless otherwise noted.

The Read Enable bit initiates a read phase for a master mode

transfer or sets the slave to receive (in slave mode).

1: Initiates a read phase for a master transfer or sets a slave to

receive. In master mode this bit is sticky and remains set until the

read transfer begins.

SCK Strobe (Bit 15)

The SCK Strobe bit starts the SCK strobe at the selected

frequency and polarity (set in the SPI Configuration register), but

not phase. This bit feature can only be enabled when in master

mode and must be during a period of inactivity. This bit is self

clearing.

0: Initiates the write phase for slave operation

Transmit Ready (Bit 9)

The Transmit Ready bit is a read only bit that indicates if the

transmit port is ready to empty and ready to be written.

1: SCK Strobe Enable

0: No Function

1: Ready for data to be written to the port. The transmit FIFO is

not full.

FIFO Init (Bit 14)

0: Not ready for data to be written to the port

Receive Data Ready (Bit 8)

The FIFO Init bit initializes the FIFO and clears the FIFO Error

Status bit. This bit is self clearing.

1: FIFO Init Enable

0: No Function

The Receive Data Ready bit is a read only bit that indicates if the

receive port has data ready.

1: Receive port has data ready to read

0: Receive port does not have data ready

Byte Mode (Bit 13)

The Byte Mode bit selects between PIO (byte mode) and DMA

(block mode) operation.

Transmit Empty (Bit 7)

The Transmit Empty bit is a read only bit that indicates if the

transmit FIFO is empty.

1: Set PIO (byte mode) operation

0: Set DMA (block mode) operation

1: Transmit FIFO is empty

Full Duplex (Bit 12)

0: Transmit FIFO is not empty

The Full Duplex bit selects between full duplex and half duplex

operation.

Receive Full (Bit 6)

The Receive Full bit is a read only bit that indicates if the receive

FIFO is full.

1: Enable full duplex. Full duplex is not allowed and does not set

if the 3Wire Enable bit of the SPI Configuration register is set to

‘1’

1: Receive FIFO is full

0: Enable half duplex operation

0: Receive FIFO is not full

SS Manual (Bit 11)

Transmit Bit Length (Bits [5:3])

The SS Manual bit activates or deactivates SS if the SS Delay

Select field of the SPI Control register is all zeros and is

configured as master interface. This field only applies to master

mode.

The Transmit Bit Length field controls whether a full byte or

partial byte is to be transmitted. If Transmit Bit Length is ‘000’

then a full byte is transmitted. If Transmit Bit Length is ‘001’ to

‘111’, then the value indicates the number of bits that are be

transmitted.

1: Activate SS, master drives SS line asserted LOW

0: Deactivate SS, master drives SS line deasserted HIGH

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Receive Bit Length (Bits [2:0])

The Receive Bit Length field controls whether a full byte or partial

byte is received. If Receive Bit Length is ‘000’ then a full byte is

received. If Receive Bit Length is ‘001’ to ‘111’, then the value

indicates the number of bits that are received.

SPI Interrupt Enable Register [0xC0CC] [R/W]

Table 108. SPI Interrupt Enable Register

Bit #

Field

Reserved...

Read/Write

Default

Bit #

...Reserved

Receive

Interrupt

Enable

Transmit

Interrupt

Enable

Transfer

Interrupt

Enable

Field

Read/Write

Default

R/W

1: Enables byte mode transmit interrupt

0: Disables byte mode transmit interrupt

The SPI Interrupt Enable register controls the SPI port.

Receive Interrupt Enable (Bit 2)

Transfer Interrupt Enable (Bit 0)

The Receive Interrupt Enable bit enables or disables the byte

mode receive interrupt (RxIntVal).

The Transfer Interrupt Enable bit enables or disables the block

mode interrupt (XfrBlkIntVal).

1: Enable byte mode receive interrupt

0: Disable byte mode receive interrupt

1: Enables block mode interrupt

0: Disables block mode interrupt

Transmit Interrupt Enable (Bit 1)

Reserved

The Transmit Interrupt Enable bit enables or disables the byte

mode transmit interrupt (TxIntVal).

Write all reserved bits with ’0’.

SPI Status Register [0xC0CE] [R]

Table 109. SPI Status Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

FIFO Error

Flag

Reserved

Receive

Interrupt

Flag

Transmit

Interrupt

Flag

Transfer

Interrupt

Flag

Field

Read/Write

Default

bit of the SPI Control register is set to ‘1’, then a Tx FIFO

underflow occurred. Similarly, when set with the Receive Full bit

of the SPI Control register, an Rx FIFO overflow occured.This bit

automatically clears when the SPI FIFO Init Enable bit of the SPI

Control register is set.

The SPI Status register is a read only register that provides

status for the SPI port.

FIFO Error Flag (Bit 7)

1: Indicates FIFO error

The FIFO Error Flag bit is a read only bit that indicates if a FIFO

error occurred. When this bit is set to ‘1’ and the Transmit Empty

0: Indicates no FIFO error

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Receive Interrupt Flag (Bit 2)

1: Indicates a byte mode transmit interrupt triggered

The Receive Interrupt Flag is a read only bit that indicates if a

byte mode receive interrupt triggered.

0: Indicates a byte mode transmit interrupt did not trigger

Transfer Interrupt Flag (Bit 0)

1: Indicates a byte mode receive interrupt triggered

0: Indicates a byte mode receive interrupt did not trigger

The Transfer Interrupt Flag is a read only bit that indicates a

block mode interrupt triggered.

Transmit Interrupt Flag (Bit 1)

1: Indicates a block mode interrupt triggered

The Transmit Interrupt Flag is a read only bit that indicates a byte

mode transmit interrupt triggered.

0: Indicates a block mode interrupt did not trigger

SPI Interrupt Clear Register [0xC0D0] [W]

Table 110. SPI Interrupt Clear Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

Reserved

Transmit

Interrupt

Clear

Transfer

Interrupt

Clear

Field

Read/Write

Default

Transfer Interrupt Clear (Bit 0)

The SPI Interrupt Clear register is a write only register that allows

the SPI Transmit and SPI Transfer Interrupts to be cleared.

The Transfer Interrupt Clear bit is a write only bit that clears the

block mode interrupt. This bit is self clearing.

1: Clear the block mode interrupt

0: No function

Transmit Interrupt Clear (Bit 1)

The Transmit Interrupt Clear bit is a write only bit that clears the

byte mode transmit interrupt. This bit is self clearing.

Reserved

1: Clear the byte mode transmit interrupt

0: No function

Write all reserved bits with ’0’.

SPI CRC Control Register [0xC0D2] [R/W]

Table 111. SPI CRC Control Register

Bit #

CRC Mode

CRC

Enable

CRC

Clear

Receive

CRC

One in

CRC

Zero in

CRC

Reserved...

Field

Read/Write

Default

R/W

Bit #

Field

...Reserved

Read/Write

Default

CRC Mode (Bits [15:14)

The SPI CRC Control register provides control over the CRC

source and polynomial value.

The CRCMode field selects the CRC polynomial as defined in

T a ble 112 on page 70.

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Receive CRC (Bit 11)

Table 112. CRC Mode Definition

CRCMode

The Receive CRC bit determines whether the receive bit stream

or the transmit bit stream is used for the CRC data input in full

duplex mode. This bit is a don’t care in half duplex mode.

CRC Polynomial

[15:14]

MMC 16 bit: X^16 + X^12 + X^5 + 1(CCITT

Standard)

1: Assigns the receive bit stream

0: Assigns the transmit bit stream

CRC7 7 bit: X^7+ X^3 + 1

One in CRC (Bit 10)

MST 16 bit: X^16+ X^15 + X^2 + 1

Reserved, 16 bit polynomial 1

The One in CRC bit is a read only bit that indicates if the CRC

value is all zeros or not

1: CRC value is not all zeros

0: CRC value is all zeros

CRC Enable (Bit 13)

The CRC Enable bit enables or disables the CRC operation.

1: Enables CRC operation

Zero in CRC (Bit 9)

0: Disables CRC operation

The Zero in CRC bit is a read only bit that indicates if the CRC

value is all ones or not.

CRC Clear (Bit 12)

1: CRC value is not all ones

0: CRC value is all ones

The CRC Clear bit clears the CRC with a load of all ones. This

bit is self clearing and always reads ‘0’.

1: Clear CRC with all ones

0: No Function

Reserved

Write all reserved bits with ’0’.

SPI CRC Value Register [0xC0D4] [R/W]

Table 113. SPI CRC Value Register

Bit #

Field

CRC...

...CRC

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

The SPI CRC Value register contains the CRC value.

CRC (Bits [15:0])

The CRC field contains the SPI CRC. In CRC Mode CRC7, the

CRC value is a seven bit value [6:0]. Therefore, bits [15:7] are

invalid in CRC7 mode.

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SPI Data Register [0xC0D6] [R/W]

Table 114. SPI Data Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

Field

Data

Read/Write

Default

R/W

Data (Bits [7:0])

The SPI Data register contains data received on the SPI port

when read. Reading it empties the eight byte receive FIFO in PIO

byte mode. This receive data is valid when the Receive Interrupt

Bit of the SPI Status register is set to ‘1’ (RxIntVal triggers) or the

Receive Data Ready bit of the SPI Control register is set to ‘1’.

Writing to this register in PIO byte mode initiates a transfer of

data, the number of bits defined by Transmit Bit Length field in

the SPI Control register.

The Data field contains data received or to be transmitted on the

SPI port.

Reserved

Write all reserved bits with ’0’.

SPI Transmit Address Register [0xC0D8] [R/W]

Table 115. SPI Transmit Address Register

Bit #

Field

Address...

...Address

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

Address (Bits [15:0])

The SPI Transmit Address register is used as the base address

for the SPI transmit DMA.

The Address field sets the base address for the SPI transmit

DMA.

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SPI Transmit Count Register [0xC0DA] [R/W]

Table 116. SPI Transmit Count Register

Bit #

Count...

R/W

Field

Reserved

Read/Write

Default

R/W

Bit #

Field

...Count

Read/Write

Default

R/W

Reserved

Write all reserved bits with ’0’.

The SPI Transmit Count register designates the block byte

length for the SPI transmit DMA transfer.

Count (Bits [10:0])

The Count field sets the count for the SPI transmit DMA transfer.

SPI Receive Address Register [0xC0DC [R/W]

Table 117. SPI Receive Address Register

Bit #

Field

Address...

...Address

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

Address (Bits [15:0])

The SPI Receive Address register is issued as the base address

for the SPI Receive DMA.

The Address field sets the base address for the SPI receive

DMA.

SPI Receive Count Register [0xC0DE] [R/W]

Table 118. SPI Receive Count Register

Bit #

Count...

R/W

Field

Reserved

Read/Write

Default

R/W

Bit #

Field

...Count

Read/Write

Default

R/W

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UART Registers

The SPI Receive Count register designates the block byte length

for the SPI receive DMA transfer.

There are three registers dedicated to UART operation. Each of

these registers is covered in this section and summarized in

T a ble 119.

Count (Bits [10:0])

Table 119. UART Registers

The Count field sets the count for the SPI receive DMA transfer.

UART Control Register

UART Status Register

UART Data Register

Address

0xC0E0

0xC0E2

0xC0E4

R/W

Reserved

Write all reserved bits with ’0’.

R/W

UART Control Register [0xC0E0] [R/W]

Table 120. UART Control Register

Bit #

Field

Reserved...

Read/Write

Default

Bit #

Field

...Reserved

Scale Select

Baud Select

UART Enable

Read/Write

Default

R/W

Table 121. UART Baud Select Definition

BaudSelect

The UART Control register enables or disables the UART,

allowing GPIO28 (UART_TXD) and GPIO27 (UART_RXD) to be

freed up for general use. This register must also be written to set

the baud rate, which is based on a 48 MHz clock.

Baud Rate w/DIV8 = 0 Baud Rate w/ DIV8 = 1

[3:1]

000

001

010

011

100

101

110

111

115.2 KBaud

57.6 KBaud

38.4 KBaud

28.8 KBaud

19.2 KBaud

14.4 KBaud

9.6 KBaud

14.4 KBaud

7.2 KBaud

4.8 KBaud

3.6 KBaud

2.4 KBaud

1.8 KBaud

1.2 KBaud

0.9 KBaud

Scale Select (Bit 4)

The Scale Select bit acts as a prescaler that divide the baud rate

by eight.

1: Enable prescaler

0: Disable prescaler

Baud Select (Bits [3:1])

7.2 KBaud

Refer to T a ble 121 for a definition of this field.

UART Enable (Bit 0)

The UART Enable bit enables or disables the UART.

1: Enable UART

0: Disable UART. This allows GPIO28 and GPIO27 to be used

for general use.

Reserved

Write all reserved bits with ’0’.

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UART Status Register [0xC0E2] [R]

Table 122. UART Status Register

Bit #

Field

Reserved...

Read/Write

Default

Bit #

Field

...Reserved

Receive Full

Transmit Full

Read/Write

Default

Transmit Full (Bit 0)

The UART Status register is a read only register that indicates

the status of the UART buffer.

The Transmit Full bit indicates whether the transmit buffer is full.

It can be programmed to interrupt the CPU as interrupt #4 when

the buffer is empty. This can be done though the UART bit of the

Interrupt Enable register (0xC00E). This bit is automatically set

to ‘1’ after data is written by EZ-Host to the UART Data register

(to be transmitted). This bit is automatically cleared to ‘0’ after

the data is transmitted.

Receive Full (Bit 1)

The Receive Full bit indicates whether the receive buffer is full.

It can be programmed to interrupt the CPU as interrupt #5 when

the buffer is full. This can be done though the UART bit of the

Interrupt Enable register (0xC00E). This bit is automatically

cleared when data is read from the UART Data register.

1: Transmit buffer full (transmit busy)

0: Transmit buffer is empty and ready for a new byte of data

1: Receive buffer full

0: Receive buffer empty

UART Data Register [0xC0E4] [R/W]

Table 123. UART Data Register

Bit #

Field

Reserved

Read/Write

Default

Bit #

Field

Data

Read/Write

Default

R/W

Data (Bits [7:0])

The UART Data register contains data to be transmitted or

received from the UART port. Data written to this register starts

a data transmission and also causes the UART Transmit Full

Flag of the UART Status register to set. When data received on

the UART port is read from this register, the UART Receive Full

Flag of the UART Status register is cleared.

The Data field is where the UART data to be transmitted or

received is located.

Reserved

Write all reserved bits with ’0’.

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PWM Registers

There are eleven registers dedicated to PWM operation. Each of these registers are covered in this section and summarized in

T a ble 124.

Table 124. PWM Registers

Address

0xC0E6

0xC0E8

0xC0EA

0xC0EC

0xC0EE

0xC0F0

0xC0F2

0xC0F4

0xC0F6

0xC0F8

0xC0FA

R/W

PWM Control Register

PWM Maximum Count Register

PWM0 Start Register

PWM0 Stop Register

PWM1 Start Register

PWM1 Stop Register

PWM2 Start Register

PWM2 Stop Register

PWM3 Start Register

PWM3 Stop Register

PWM Cycle Count Register

PWM Control Register [0xC0E6] [R/W]

Table 125. PWM Control Register

Bit #

PWM

Reserved

Prescale

Mode

Field

Enable

Select

R/W

Select

Read/Write

Default

R/W

Bit #

PWM 3

Polarity

Select

PWM 2

Polarity

Select

PWM 1

Polarity

Select

PWM 0

Polarity

Select

PWM 3

Enable

PWM 2

Enable

PWM 1

Enable

PWM 0

Enable

Field

Read/Write

Default

R/W

Table 126. Prescaler Select Definition

The PWM Control register provides high level control over all four

of the PWM channels.

Prescale Select [11:9]

Frequency

000

001

010

011

100

101

110

111

48.00 MHz

24.00 MHz

06.00 MHz

01.50 MHz

375 kHz

PWM Enable (Bit 15)

The PWM Enable bit starts and stops PWM operation.

1: Start operation

0: Stop operation

Prescale Select (Bits [11:9])

93.80 kHz

23.40 kHz

05.90 kHz

The Prescale Select field sets the frequency of all the PWM

channels as defined in T a ble 126.

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Mode Select (Bit 8)

PWM 0 Polarity Select (Bit 4)

The Mode Select bit selects between continuous PWM cycling

and one shot mode. The default is continuous repeat.

The PWM 0 Polarity Select bit selects the polarity for PWM 0.

1: Sets the polarity to active HIGH or rising edge pulse

0: Sets the polarity to active LOW

1: Enable One Shot mode. The mode runs the number of counter

cycles set in the PWM Cycle Count register and then stops.

PWM 3 Enable (Bit 3)

0: Enable Continuous mode. Runs in continuous mode and

starts over after the PWM cycle count is reached.

The PWM 3 Enable bit enables or disables PWM 3.

1: Enable PWM 3

PWM 3 Polarity Select (Bit 7)

0: Disable PWM 3

The PWM 3 Polarity Select bit selects the polarity for PWM 3.

1: Sets the polarity to active HIGH or rising edge pulse

0: Sets the polarity to active LOW

PWM 2 Enable (Bit 2)

The PWM 2 Enable bit enables or disables PWM 2.

1: Enable PWM 2

PWM 2 Polarity Select (Bit 6)

0: Disable PWM 2

The PWM 2 Polarity Select bit selects the polarity for PWM 2.

1: Sets the polarity to active HIGH or rising edge pulse

0: Sets the polarity to active LOW

PWM 1 Enable (Bit 1)

The PWM 1 Enable bit enables or disables PWM 1.

1: Enable PWM 1

PWM 1 Polarity Select (Bit 5)

0: Disable PWM 1

The PWM 1 Polarity Select bit selects the polarity for PWM 1.

1: Sets the polarity to active HIGH or rising edge pulse

0: Sets the polarity to active LOW

PWM 0 Enable (Bit 0)

The PWM 0 Enable bit enables or disables PWM 0.

1: Enable PWM 0

0: Disable PWM 0

PWM Maximum Count Register [0xC0E8] [R/W]

Table 127. PWM Maximum Count Register

Bit #

Field

Reserved

Count...

Read/Write

Default

R/W

Bit #

Field

...Count

Read/Write

Default

R/W

Count (Bits [9:0])

The PWM Maximum Count register designates the maximum

window for each pulse cycle. Each count tick is based on the

clock frequency set in the PWM Control register.

The Count field sets the maximum cycle time.

Reserved

Write all reserved bits with ’0’.

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PWM n Start Register [R/W]

■ PWM 0 Start Register 0xC0EA

■ PWM 1 Start Register 0xC0EE

■ PWM 2 Start Register 0xC0F2

■ PWM 3 Start Register 0xC0F6

Table 128. PWM n Start Register

Bit #

Field

Reserved

Address...

Read/Write

Default

R/W

Bit #

Field

...Address

Read/Write

Default

R/W

Address (Bits [9:0])

The PWM n Start register designates where in the window

defined by the PWM Maximum Count register to start the PWM

pulse for a supplied channel.

The Address field designates when to start the PWM pulse. If this

start value is equal to the Stop Count Value then the output stays

at false.

Reserved

Write all reserved bits with ’0’.

PWM n Stop Register [R/W]

■ PWM 0 Stop Register 0xC0EC

■ PWM 1 Stop Register 0xC0F0

■ PWM 2 Stop Register 0xC0F4

■ PWM 3 Stop Register 0xC0F8

Table 129. PWM n Stop Register

Bit #

Field

Reserved

Address...

Read/Write

Default

R/W

Bit #

Field

...Address

Read/Write

Default

R/W

stays at ‘0’. If the PWM Stop value is greater then the PWM

Maximum Count value then the output stays at true.

The PWM n Stop register designates where in the window

defined by the PWM Maximum Count register to stop the PWM

pulse for a supplied channel.

Reserved

Write all reserved bits with ’0’.

Address (Bits [9:0])

The Address field designates when to stop the PWM pulse. If the

PWM Start value is equal to the PWM Stop value then the output

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PWM Cycle Count Register [0xC0FA] [R/W]

Table 130. PWM Cycle Count Register

Bit #

Field

Count...

...Count

Read/Write

Default

R/W

Bit #

Field

Read/Write

Default

R/W

Count (Bits [9:0])

The PWM Cycle Count register designates the number of cycles

to run when in one shot mode. One shot mode is enabled by

setting the Mode Select bit of the PWM Control register to ‘1’.

The Count field designates the number of cycles (plus one) to

run when in one shot mode. For example, Cycles = PWM Cycle

Count + 1, therefore for two cycles set PWM Cycle Count = 1.

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Pin Diagram

Figure 11. EZ-Host Pin Diagram

95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

100 99 98 97 96

GND

D8/MISO

D9/nSSI

DM2B

DP2B

AGND

D10/SCK

D11/MOSI

D12/TXD

D13/RXD

D14/RTS

D15/CTS

DM2A

DP2A

GPIO8/D8/MISO

GPIO9/D9/nSSI

OTGVBUS

CSWITCHB

CSWITCHA

VSWITCH

nWR

VCC

CY7C67300

nRD

BOOSTGND

BOOSTVCC

GPIO10/D10/SCK

GPIO11/D11/MOSI

GPIO12/D12

DM1B

DP1B

GPIO13/D13

GPIO14/D14

GPIO15/D15/nSSI

AVCC

DM1A

DP1A

GPIO16/A0/TXD/PWM0

GPIO17/A1/RXD/PWM1

GPIO18/A2/RTS/PWM2

GPIO19/A0/CS0

GND

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

26 27 28 29 30

Pin Descriptions

Table 131. Pin Descriptions

Name

Type

Description

D15: External Memory Data Bus

D15/CTS

CTS: HSS CTS

D14/RTS

D13/RXD

D12/TXD

D14: External Memory Data Bus

RTS: HSS RTS

D13: External Memory Data Bus

RXD: HSS RXD (Data is received on this pin)

D12: External Memory Data Bus

TXD: HSS TXD (Data is transmitted from this pin)

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Table 131. Pin Descriptions (continued)

Name

Type

Description

D11: External Memory Data Bus

D11/MOSI

MOSI: SPI MOSI

D10/SCK

D9/nSSI

D8/MISO

D10: External Memory Data Bus

SCK: SPI SCK

D9: External Memory Data Bus

nSSI: SPI nSSI

D8: External Memory Data Bus

MISO: SPI MISO

External Memory Data Bus

A14

A13

A12

A11

A10

Output

External Memory Address Bus

nBEL/A0

nBEL: Low Byte Enable for 16-bit memories

A0: External Memory Address bit A0 for 0-8 bit memories

High Byte Enable for 16-bit memories

External Memory Write pulse

External Memory Read pulse

A16: External SRAM A16

nBEH

nWR

nRD

Output

A16

A17

A18

A17: External SRAM A17

A18: External SRAM A18

nXMEMSEL

nXROMSEL

nXRAMSEL

A15/CLKSEL

External Memory Select 0

External Memory Select 1

External Memory Select 2

A15: External SRAM A15

CLKSEL: Sampled directly after reset to determine what crystal or

clock source frequency is being used. 12 MHz is required for normal

operation so the CLKSEL pin must have a 47K ohm pull up to V_CC.

After reset this pin functions as A15.

GPIO31/SCK

GPIO30/SDA

GPIO31: General Purpose IO

SCK: I2C EEPROM SCK

GPIO30: General Purpose IO

SDA: I2C EEPROM SDA

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Table 131. Pin Descriptions (continued)

Name

Type

Description

GPIO29: General Purpose IO

GPIO29/OTGID

OTGID: Input for OTG ID pin. When used as OTGID, tie this pin high

through an external pull up resistor. Assuming V_CC= 3.0V, a 10K to

40K resistor must be used.

GPIO28: General Purpose IO

TX: UART TX (Data is transmitted from this pin)

GPIO28/TX

GPIO27/RX

GPIO27: General Purpose IO

RX: UART RX (Data is received on this pin)

GPIO26/CTS/PWM3

GPIO26: General Purpose IO

CTS: HSS CTS

PWM3: PWM channel 3

GPIO25/IRQ1

GPIO25: General Purpose IO

IRQ1: Interrupt Request 1. See Register 0xC006. This pin is also one

of two possible GPIO wakeup sources.

GPIO24/INT/

IORDY/IRQ0

GPIO24: General Purpose IO

INT: HPI INT

IORDY: IDE IORDY

IRQ0: Interrupt Request 0. See Register 0xC006. This pin is also one

of two possible GPIO wakeup sources.

GPIO23/nRD/IOR

GPIO22/nWR/IOW

GPIO23: General Purpose IO

nRD: HPI nRD

IOR: IDE IOR

GPIO22: General Purpose IO

nWR: HPI nWR

IOW: IDE IOW

GPIO21/nCS

GPIO21: General Purpose IO

nCS: HPI nCS

GPIO20/A1/CS1

GPIO20: General Purpose IO

A1: HPI A1

CS1: IDE CS1

GPIO19/A0/CS0

GPIO19: General Purpose IO

A0: HPI A0

CS0: IDE CS0

GPIO18/A2/RTS/

PWM2

GPIO18: General Purpose IO

A2: IDE A2

RTS: HSS RTS

PWM2: PWM channel 2

GPIO17/A1/RXD/

PWM1

GPIO17: General Purpose IO

A1: IDE A1

RXD: HSS RXD (Data is received on this pin)

PWM1: PWM channel 1

GPIO16/A0/TXD/

PWM0

GPIO16: General Purpose IO

A0: IDE A0

TXD: HSS TXD (Data is transmitted from this pin)

PWM0: PWM channel 0

GPIO15/D15/nSSI

GPIO15: General Purpose IO

D15: D15 for HPI or IDE

nSSI: SPI nSSI

GPIO14/D14

GPIO13/D13

GPIO12/D12

GPIO14: General Purpose IO

D14: D14 for HPI or IDE

GPIO13: General Purpose IO

D13: D13 for HPI or IDE

GPIO12: General Purpose IO

D12: D12 for HPI or IDE

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Table 131. Pin Descriptions (continued)

Name

Type

Description

GPIO11: General Purpose IO

GPIO11/D11/MOSI

D11: D11 for HPI or IDE

MOSI: SPI MOSI

GPIO10/D10/SCK

GPIO9/D9/nSSI

GPIO8/D8/MISO

GPIO10: General Purpose IO

D10: D10 for HPI or IDE

SCK: SPI SCK

GPIO9: General Purpose IO

D9: D9 for HPI or IDE

nSSI: SPI nSSI

GPIO8: General Purpose IO

D8: D8 for HPI or IDE

MISO: SPI MISO

GPIO7/D7

GPIO6/D6

GPIO5/D5

GPIO4/D4

GPIO3/D3

GPIO2/D2

GPIO1/D1

GPIO0/D0

GPIO7: General Purpose IO

D7: D7 for HPI or IDE

GPIO6: General Purpose IO

D6: D6 for HPI or IDE

GPIO5: General Purpose IO

D5: D5 for HPI or IDE

GPIO4: General Purpose IO

D4: D4 for HPI or IDE

GPIO3: General Purpose IO

D3: D3 for HPI or IDE

GPIO2: General Purpose IO

D2: D2 for HPI or IDE

GPIO1: General Purpose IO

D1: D1 for HPI or IDE

GPIO0: General Purpose IO

D0: D0 for HPI or IDE

DM1A

DP1A

USB Port 1A D–

USB Port 1A D+

DM1B

DP1B

USB Port 1B D–

USB Port 1B D+

DM2A

USB Port 2A D–

DP2A

DM2B

USB Port 2A D+

USB Port 2B D–

DP2B

USB Port 2B D+

XTALIN

XTALOUT

nRESET

Reserved

BOOSTV_CC

VSWITCH

Input

Output

Input

Crystal input or Direct Clock input

Crystal output. Leave floating if direct clock source is used.

Reset

Tie to Gnd for normal operation.

Booster Power input: 2.7V to 3.6V

Booster switching output

Power

Analog

Output

BOOSTGND

OTGVBUS

CSWITCHA

CSWITCHB

AV_CC

Ground

Analog IO

Analog

Power

Booster Ground

USB OTG Vbus

Charge Pump Capacitor

USB Power

AGND

Ground

Power

USB Ground

37, 63, 88

V_CC

Main V_CC

26, 51, 75,

100

GND

Ground

Main Ground

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Absolute Maximum Ratings

This section lists the absolute maximum ratings. Stresses above

those listed can cause permanent damage to the device.

Exposure to maximum rated conditions for extended periods can

affect device operation and reliability.

Max Output Current, per IO.......................................... 4 mA

Operating Conditions

Storage Temperature.................................. –40°C to +125°C

Ambient Temperature with Power Supplied.. –40°C to +85°C

Supply Voltage to Ground Potential..................0.0V to +3.6V

DC Input Voltage to Any General Purpose Input Pin..... 5.5V

DC Voltage Applied to XTALIN ............. –0.5V to V_CC+ 0.5V

Static Discharge Voltage.......................................... > 2000V

T_A(Ambient Temperature Under Bias)......... –40°C to +85°C

Supply Voltage (V_CC, AV_CC)...........................+3.0V to +3.6V

Supply Voltage (BoostV_CC)^[7].........................+2.7V to +3.6V

Ground Voltage.................................................................. 0V

_OSC(Oscillator or Crystal Frequency).... 12 MHz ± 500 ppm

................................................................... Parallel Resonant

Crystal Requirements (XTALIN, XTALOUT)

Table 132. Crystal Requirements

Crystal Requirements

(XTALIN, XTALOUT)

Min

Typical

Max

Unit

Parallel Resonant Frequency

Frequency Stability

Load Capacitance

MHz

PPM

–500

+500

Driver Level

500

µW

Startup Time

Mode of Vibration: Fundamental

DC Characteristics

[8]

Table 133. DC Characteristics

Parameter

Description

Supply Voltage

Conditions

Min

Typ.

Max

Unit

V_CC, AV_CC

BoosV_CC

V_IH

3.0

2.7

2.0

3.3

3.6

Supply Voltage

Input HIGH Voltage

Input LOW Voltage

Input Leakage Current

Output Voltage HIGH

Output LOW Voltage

Output Current HIGH

Output Current LOW

Input Pin Capacitance

5.5

V_IL

0.8

I_I

0< V_IN< V_CC

I_OUT= 4 mA

I_OUT= –4 mA

–10.0

2.4

+10.0

μA

V_OH

V_OL

0.4

I_OH

I_OL

C_IN

Except D+/D–

D+/D–

V_HYS

Hysteresis on nReset Pin

Supply Current

250

[9, 10]

I_CC

4 transceivers powered

100

180

[9 , 10]

I_CCB

Supply Current with Booster

Enabled

135

Notes

7. The on-chip voltage booster circuit boosts BoostV to provide a nominal 3.3V V supply.

8. All tests were conducted with Charge pump off.

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Table 133. DC Characteristics (continued)^[8]

Parameter Description

I_SLEEPSleep Current

Conditions

Min

Typ.

Max

Unit

USB Peripheral: includes 1.5K

internal pull up

210

500

μA

Without 1.5K internal pull up

μA

I_SLEEPB

Sleep Current with Booster Enabled USB Peripheral: includes 1.5K

internal pull up

190

500

Without 1.5K internal pull up

μA

Table 134. DC Characteristics: Charge Pump

Parameter

V_{A_VBUS_OUT}

T_{A_VBUS_RISE}

I_{A_VBUS_OUT}

C_{DRD_VBUS}

Description

Regulated OTGVBUS Voltage

V_BUSRise Time

Conditions

8 mA< I_LOAD< 10 mA

I_LOAD= 10 mA

Min

Typ.

Max

5.25

100

Unit

4.4

Maximum Load Current

OUTVBUS Bypass Capacitance

OTGVBUS Leakage Voltage

4.4V< V_BUS< 5.25V

OTGVBUS not driven

1.0

6.5

200

342

V_{A_VBUS_LKG}

V_{DRD_DATA_LKG}Dataline Leakage Voltage

I_CHARGE

Charge Pump Current Draw

I_LOAD= 8 mA

I_LOAD= 0 mA

I_CHARGEB

Charge Pump Current Draw with

Booster Active

I_LOAD= 8 mA

I_LOAD= 0 mA

I_{B_DSCHG_IN}

B-Device (SRP Capable) Discharge 0V< V_BUS< 5.25V

Current

V_{A_VBUS_VALID}A-Device VBUS Valid

V_{A_SESS_VALID}A-Device Session Valid

V_{B_SESS_VALID}B-Device Session Valid

4.4

0.8

0.2

2.0

4.0

0.8

V_{A_SESS_END}

B-Device Session End

Efficiency When Loaded

Data Line Pull Down

I_LOAD= 8 mA, V_CC= 3.3V

R_PD

14.25

24.8

100

R_{A_BUS_IN}

A-device V_BUSInput Impedance to V_BUSis not being driven

GND

kΩ

R_{B_SRP_UP}

B-device V_BUSSRP Pull Up

Pull up voltage = 3.0V

281

656

R_{B_SRP_DWN}

B-device V_BUSSRP Pull Down

USB Transceiver

USB 2.0 certified in full- and low-speed modes.

Notes

and I

values are the same regardless of USB host or peripheral configuration.

CCB

10. There is no appreciable difference in I and I

values when only two transceivers are powered.

CCB

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AC Timing Characteristics

Reset Timing

t_RESET

nRESET

t_IOACT

nRD or nWRL or nWRH

Reset Timing

Table 135. Reset Timing Parameters

Parameter

t_RESET

Description

nRESET Pulse Width

nRESET HIGH to nRD or nWRx active

Min

Typical

Max

Unit

clocks^[11]

µs

t_IOACT

200

Clock Timing

t_CLK

t_LOW

XTALIN

t_FALL

t_HIGH

t_RISE

Clock Timing

Table 136. Clock Timing Parameters

Parameter

Description

Min

1.5

Typical

12.0

Max

Unit

MHz

f_CLK

Clock Frequency

[12]

v_XINH

Clock Input High

3.0

3.6

(XTALOUT left floating)

t_CLK

Clock Period

83.17

83.33

83.5

t_HIGH

Clock High Time

Clock Low Time

Clock Rise Time

Clock Fall Time

t_LOW

t_RISE

5.0

t_FALL

Duty Cycle

Notes

11. Clock is 12 MHz nominal.

12. v_XINHis required to be 3.0 V to obtain an internal 50/50 duty cycle clock.

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SRAM Read Cycle^[15]

Address

t_AR

t_CR

t_RPW

t_CDH

t_RDH

t_AC

Din

Data Valid

Table 137. SRAM Read Cycle Parameters

Parameter Description

t_CRCS LOW to RD LOW

Min

Typical

Max

Unit

t_RDH

t_CDH

t_RPW

t_AR

RD HIGH to Data Hold

CS HIGH to Data Hold

RD LOW Time

[13]

RD LOW to Address Valid

RAM Access to Data Valid

[14]

t_AC

Notes

13. 0 wait state cycle.

14. t External SRAM access time = 12 ns for zero and one wait states. The External SRAM access time = 12 ns + (n – 1)*T for wait states = n, n > 1, T = 48 MHz

clock period.

15. Read timing is applicable for nXMEMSEL, nXRAMSEL, and nXROMSEL.

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SRAM Write Cycle ^[17]

Address

t_AW

t_CSW

t_WC

t_WPW

t_DW

t_DH

Dout

Data Valid

Table 138. SRAM Write Cycle Parameters

Parameter

t_AW

t_CSW

t_DW

Description

Write Address Valid to WE LOW

CS LOW to WE LOW

Min

Typical

Max

Unit

Data Valid to WE HIGH

WE Pulse Width

4.5

[16]

t_WPW

t_DH

Data Hold from WE HIGH

WE HIGH to CS HIGH

t_WC

Notes

16. t

The write pulse width = 18.8 ns min. for zero and one wait states. The write pulse = 18.8 ns + (n – 1)*T for wait states = n, n > 1, T = 48 MHz clock period.

WPW

17. Write timing is applicable for nXMEMSEL, nXRAMSEL and nXROMSEL.

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I2C EEPROM Timing-Serial IO

t_HIGH

t_LOW

t_R

t_F

SCL

t_SU.DAT

t_BUF

t_SU.STA

t_HD.DAT

t_SU.STO

t_HD.STA

SDA IN

t_AA

t_DH

SDA OUT

Table 139. I2C EEPROM Timing Parameters

Parameter Description

f_SCL

Min

Typical

Max

Unit

kHz

Clock Frequency

400

t_LOW

t_HIGH

t_AA

Clock Pulse Width Low

Clock Pulse Width High

Clock Low to Data Out Valid

1300

600

900

1300

600

t_BUF

Bus Idle Before New Transmission

Start Hold Time

t_HD.STA

t_SU.STA

t_HD.DAT

t_SU.DAT

t_R

Start Setup Time

Data In Hold Time

Data In Setup Time

Input Rise Time

100

300

t_F

Input Fall Time

t_SU.STO

t_DH

Stop Setup Time

600

Data Out Hold Time

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HPI (Host Port Interface) Write Cycle Timing

t_CYC

t_ASU

t_WP

t_AH

ADDR [1:0]

t_CSH

t_CSSU

nCS

nWR

nRD

Dout [15:0]

t_DSU

t_WDH

Table 140. HPI Write Cycle Timing Parameters

Parameter

t_ASU

Description

Min

–1

Typical

Max

Unit

Address Setup

Address Hold

t_AH

t_CSSU

t_CSH

t_DSU

t_WDH

t_WP

Chip Select Setup

Chip Select Hold

Data Setup

Write Data Hold

Write Pulse Width

Write Cycle Time

T^[18]

t_CYC

Notes

18. T = system clock period = 1/48 MHz.

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HPI (Host Port Interface) Read Cycle Timing

t_CYC

t_ASU

t_RP

t_AH

ADDR [1:0]

t_CSH

t_CSSU

nCS

t_RDH

nWR

nRD

Din [15:0]

t_ACC

t_RDH

Table 141. HPI Read Cycle Timing Parameters

Parameter

t_ASU

Description

Min

–1

Typical

Max

Unit

Address Setup

Address Hold

t_AH

–1

t_CSSU

t_CSH

t_ACC

t_RDH

Chip Select Setup

Chip Select Hold

–1

T^[18]

Data Access Time, from HPI_nRD falling

Read Data Hold, relative to the earlier of

HPI_nRD rising or HPI_nCS rising

1.5

t_RP

Read Pulse Width

Read Cycle Time

T^[18]

t_CYC

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IDE Timing

The IDE interface supports PIO mode 0-4 as specified in the Information Technology-AT Attachment–4 with Packet Interface Extension

(ATA/ATAPI-4) Specification, T13/1153D Rev 18.

HSS BYTE Mode Transmit

qt_clk

CPU may start another BYTE

transmit right after TxRdy

CPU_A[2:0]

goes high

CPUHSS_cs

CPU_wr

TxRdy flag

HSS_TxD

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

stop bit

start bit

bit 0

start of last data bit to TxRdy high:

0 min, 4 T max.

(T is qt_clk period)

TxRdy low to start bit delay:

programmable

1 or 2 stop bits.

1 stop bit shown.

Byte transmit

triggered by a

CPU write to the

HSS_TxData register

0 min, BT max when starting from IDEL.

For back to back transmit, new START Bit

begins immediately following previous STOP bit.

(BT = bit period)

qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diagram to illustrate the relationship between CPU opera-

tions and HSS port operations.

Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_TxD HIGH = data bit value ‘1’.

BT = bit time = 1/baud rate.

HSS Block Mode Transmit

HSS_TxD

GAP

BLOCK mode transmit timing is similar to BYTE mode, except the STOP bit time is controlled by the HSS_GAP value.

The BLOCK mode STOP bit time, t_GAP= (HSS_GAP – 9) BT, where BT is the bit time, and HSS_GAP is the content of the HSS

Transmit Gap register [0xC074].

The default t_GAPis 2 BT.

BT = bit time = 1/baud rate.

HSS BYTE and BLOCK Mode Receive

BT +/- 5%

received byte added to

receive FIFO during the final data bit time

BT +/- 5%

HSS_RxD

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

stop bit start bit

start bit

bit 0

10 BT +/- 5%

Receive data arrives asynchronously relative to the internal clock. Incoming data bit rate may deviate from the programmed baud rate

clock by as much as ±5% (with HSS_RATE value of 23 or higher).

BYTE mode received bytes are buffered in a FIFO. The FIFO not empty condition becomes the RxRdy flag.

BLOCK mode received bytes are written directly to the memory system.

Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_RxD HIGH = data bit value ‘1’.

BT = bit time = 1/baud rate.

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Hardware CTS/RTS Handshake

tCTShold

tCTSsetup

HSS_RTS

HSS_CTS

HSS_TxD

Start of transmission not delayed by HSS_CTS

Start of transmission delayed until HSS_CTS goes high

t_CTSsetup: HSS_CTS setup time before HSS_RTS = 1.5T min.

_CTShold: HSS_CTS hold time after START bit = 0 ns min.

T = 1/48 MHz.

When RTS/CTS hardware handshake is enabled, transmission can be help off by deasserting HSS_CTS at least 1.5T before

HSS_RTS. Transmission resumes when HSS_CTS returns HIGH. HSS_CTS must remain HIGH until START bit.

HSS_RTS is deasserted in the third data bit time.

An application may choose to hold HSS_CTS until HSS_RTS is deasserted, which always occurs after the START bit.

Table 142. Register Summary

R/W

Address Register

Bit 15

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Default High

Default Low

0000 0000

0001 0100

Bit 7

0x0140

0x0142

HPI Breakpoint

Interrupt Routing

Address...

...Address

VBUS to HPI ID to HPI

Enable Enable

SOF/EOP2 to SOF/EOP2 to SOF/EOP1to SOF/EOP1 to Reset2 to HPI HPI Swap 1

HPI Enable CPU Enable HPI Enable CPU Enable Enable Enable

Resume2 to Resume1 to Reserved

Done2 to HPI Done1 to HPI Reset1 to HPI HPI Swap 0

0000 0000

HPI Enable

Enable

1: 0x0144 SIEXmsg

2: 0x0148

Data...

xxxx xxxx

...Data

R/W

0x02n0

Device n Endpoint n Control

Reserved

IN/OUT

Ignore Enable Select

Sequence

Stall

Enable

ISO

Enable

NAK Interrupt Direction

Enable

ARM

Enable

Select

R/W

R.W

R/W

0x02n2

0x02n4

0x02n6

Device n Endpoint n Address

Device n Endpoint n Count

Device n Endpoint n Status

Address...

xxxx xxxx

...Address

Reserved

Count...

OUT

...Count

Reserved

Overflow

Flag

Underflow

Flag

Exception Flag Exception Flag

Stall

Flag

NAK

Flag

Length

Setup

Sequence

Status

Timeout

Flag

Error

Flag

ACK

Flag

xxxx xxxx

Exception Flag Flag

R/W

0x02n8

0xC000

Device n Endpoint n Count Result Result...

...Result

xxxx xxxx

0000 0000

000x xxxx

CPU Flags

Reserved...

...Reserved

Global Inter- Negative

Overflow

Flag

Carry

Flag

Zero

Flag

rupt Enable

Flag

R/W

0xC002

0xC004

0xC006

Bank

Address...

...Address

Revision...

...Revision

0000 0001

000x xxxx

xxxx xxxx

0000 0000

Reserved

Hardware Revision

GPIO Control

R/W

Write Protect UD

Enable

Reserved

SAS

Enable

Mode

Select

HSS

Enable

HSS XD

Enable

SPI

Enable

SPI XD

Enable

Interrupt 1

Polarity

Select

Interrupt 1

Enable

Interrupt 0

Polarity

Select

Interrupt 0

Enable

0000 0000

R/W

0xC008

CPU Speed

Reserved...

.Reserved

0000 0000

0000 1111

0000 0000

CPU Speed

0xC00A Power Control

Host/Device Host/Device Host/Device

2B Wake

Enable

Host/Device OTG

Reserved

HSS

Wake

Enable

SPI

Wake

Enable

2A Wake

Enable

1B Wake

Enable

1A Wake

Enable

Wake

Enable

HPI

Wake Enable

Reserved

GPI

Wake Enable

Reserved

Boost 3V

Sleep

Enable

Halt

Enable

0000 0000

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Table 142. Register Summary (continued)

R/W

Address Register

Bit 15

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Default High

Default Low

0000 0000

Bit 7

R/W

0xC00C Watchdog Timer

Reserved...

...Reserved

Timeout

Flag

Period

Select

Lock

Enable

WDT

Enable

Reset

Strobe

0000 0000

R/W

0xC00E Interrupt Enable

Reserved

OTG Interrupt SPI Interrupt Reserved

Host/Device 2 Host/Device 1 0000 0000

Enable

Interrupt

Enable

Interrupt

Enable

HSS

In Mailbox

Interrupt

Enable

Out Mailbox

Interrupt

Enable

Reserved

UART

GPIO

Timer 1

Interrupt

Enable

Timer 0

Interrupt

Enable

0001 0000

0000 0000

0000 0xxx

Interrupt

Enable

Interrupt

Enable

Interrupt

Enable

R/W

0xC098

OTG Control

Reserved

VBUS

Pull-up

Enable

Receive

Disable

Charge Pump VBUS

Enable

D+

Pull-up

Enable

D–

Pull-up

Enable

Discharge

Enable

D+ Pulldown D– Pull-down Reserved

Enable

OTG Data

Status

VBUS Valid

Flag

Enable

R/W

0: 0xC010 Timer n

1: 0xC012

Count...

...Count

Address...

...Address

Address...

...Address

Data...

1111 1111

0000 0000

xxxx xxxx

xxxx 0xxx

0xC014

Breakpoint

1: 0xC018 Extended Page n Map

2: 0xC01A

0: 0xC01E GPIO n Output Data

1: 0xC024

...Data

0: 0xC020 GPIO n Input Data

1: 0xC026

Data...

...Data

R/W

0: 0xC022 GPIO n Direction

1: 0xC028

Direction Select...

...Direction Select

Reserved

0xC038

Upper Address Enable

Reserved

Upper

Reserved

XMEM

Address

Enable

R/W

0xC03A External Memory Control

0xC03C USB Diagnostic

Reserved

XRAM

XROM

XMEM

xxxx xxxx

0000 0000

Merge Enable Merge Enable Width Select Wait Select

XROM

Width Select Wait Select

XROM

XRAM

Width Select Wait Select

XRAM

Port 2B

Diagnostic

Enable

Port 2A

Diagnostic

Enable

Port 1B

Diagnostic

Enable

Port 1A

Diagnostic

Enable

Reserved...

...Reserved

Pull-down

Enable

LS Pull-up

Enable

FS Pull-up

Enable

Reserved

Force Select

0000 0000

0xC03E Memory Diagnostic

Reserved

Memory

Arbitration

Select

Reserved

Monitor

Enable

0000 0000

R/W

0xC048

IDE Mode

Reserved...

...Reserved

Address...

... Address

Address...

...Address

Reserved...

...Reserved

0000 0000

Reserved

Mode Select

0xC04A IDE Start Address

0xC04C IDE Stop Address

0xC04E IDE Control

Direction

Select

IDE Interrupt Done

Enable

IDE

Enable

Flag

0xC050-0 IDE PIO Port

xC06E

R/W

0xC070

HSS Control

HSS

RTS

CTS

XOFF

CTS

Receive

Interrupt

Enable

Done

0000 0000

Enable

Polarity

Select

Polarity

Select

Enable

Interrupt

Enable

TransmitDone Receive Done One

Interrupt Flag Interrupt Flag Stop Bit

Transmit

Ready

Packet Mode Receive

Select Overflow Flag et Ready Flag Ready Flag

Receive Pack- Receive

R/W

0xC072

0xC074

0xC076

0xC078

HSS Baud Rate

HSS Transmit Gap

HSS Data

Reserved

...Baud

HSS Baud...

0000 0000

0001 0111

0000 0000

0000 1001

xxxx xxxx

0000 0000

Reserved

Transmit Gap Select

Reserved

Data

HSS Receive Address

Address...

...Address

Reserved

...Counter

Address..

...Address

0xC07A HSS Receive Counter

0xC07C HSS Transmit Address

Counter...

Document #: 38-08015 Rev. *J

Page 93 of 99

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CY7C67300

Table 142. Register Summary (continued)

R/W

Address Register

Bit 15

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 8

Bit 0

Default High

Default Low

0000 0000

Bit 7

Bit 1

0xC07E HSS Transmit Counter

Reserved

...Counter

Reserved

Counter...

0xC080

0xC0A0

Host n Control

Preamble

Enable

Sequence

Select

Sync

Enable

ISO

Enable

Reserved

Arm

Enable

R/W

0xC082

0xC0A2

Host n Address

Host n Count

Address...

...Address

Reserved

...Count

0000 0000

0xC084

0xC0A4

Port Select

Reserved

Count...

0xC084

0xC0A4

Device n Port Select

Host n PID

Reserved

...Reserved

Reserved

Reserved...

0xC086

0xC0A6

Overflow

Flag

Underflow

Flag

Reserved

Stall

Flag

NAK

Flag

Length

Exception Flag

Reserved

Sequence

Status

Timeout

Flag

Error

Flag

ACK

Flag

0000 0000

0xC086

0xC0A4

Host n EP Status

Reserved

PID Select

Result...

0000 0000

Endpoint Select

0xC088

0xC0A8

Host n Count Result

Host n Device Address

...Result

0xC088

0xC0A8

Reserved...

...Reserved

Address

R/W

0xC08A USB n Control

0xC0AA

Port B

D+ Status

Port B

D– Status

Port A

D+ Status

Port A

D– Status

LOB

LOA

Mode

Select

Port B Resis- xxxx 0000

tors Enable

Port A

Port B

Port A

Force D±

State

Suspend

Enable

Port B

Port A

0000 0000

Resistors

Enable

Force D+/-

State

SOF/EOP

Enable

SOF/EOP

Enable

R/W

0xC08C Host 1 Interrupt Enable

0xC08C Device 1 Interrupt Enable

VBUS

Interrupt

Enable

Interrupt

Enable

Reserved

SOF/EOP

Interrupt

Enable

Reserved

Port B

Port A

Port B Connect Port A Con-

nect Change

Reserved

Done

Interrupt

Enable

Wake Interrupt Wake Interrupt Change

Enable

Interrupt En- Interrupt

able

Enable

VBUS

Reserved

SOF/EOP

Timeout In-

terrupt En-

able

Reserved

SOF/EOP

Interrupt

Enable

Reset

0000 0000

Interrupt

Enable

Interrupt

Enable

Interrupt

Enable

EP7

Interrupt

Enable

EP6

Interrupt

Enable

EP5

Interrupt

Enable

EP4

Interrupt

Enable

EP3

Interrupt

Enable

EP2

Interrupt

Enable

EP1

Interrupt

Enable

EP0

Interrupt

Enable

R/W

0xC08E Device n Address

0xC0AE

Reserved...

...Reserved

VBUS

0000 0000

xxxx xxxx

Address

0xC090

Host 1 Status

Reserved

SOF/EOP

Interrupt Flag

Reserved

Interrupt Flag Interrupt Flag

Port B Port A

PortBConnect Port A Con-

Port B

Port A

SE0

Status

Reserved

Done

Interrupt

Flag

xxxx xxxx

Wake Interrupt Wake Interrupt Change

nect Change SE0

Flag

Interrupt Flag Interrupt Flag Status

R/W

0xC090

Device 1 Status

VBUS

Reserved

SOF/EOP

Reset

xxxx xxxx

Interrupt Flag Interrupt Flag

EP7

EP6

EP5

EP4

EP3

EP2

EP1

EP0

Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag

R/W

0xC092

0xC0B2

Host n SOF/EOP Count

Device n Frame Number

Reserved

...Count

Count...

0010 1110

1110 0000

0000 0000

0xC092

0xC0B2

SOF/EOP

Timeout

Flag

SOF/EOP

Reserved

Frame...

Timeout

Interrupt Count

...Frame

Reserved

...Counter

Reserved

...Count

0000 0000

xxxx xxxx

0010 1110

1110 0000

0000 0000

0xC094

0xC0B4

Host n SOF/EOP Counter

Device n SOF/EOP Count

Host n Frame

Counter...

Count...

0xC094

0xC0B4

0xC096

0xC0B6

Reserved

...Frame

Reserved

Frame...

R/W

0xC0AC Host 2 Interrupt Enable

SOF/EOP

Interrupt

Enable

Reserved

Port B

Port A

Port B Connect Port A Con-

Reserved

Done

Interrupt

Enable

0000 0000

Wake Interrupt Wake Interrupt Change

nect Change

Interrupt

Enable

Interrupt

Enable

Document #: 38-08015 Rev. *J

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CY7C67300

Table 142. Register Summary (continued)

R/W

Address Register

Bit 15

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 1

Bit 8

Bit 0

Reset

Interrupt

Enable

Default High

Default Low

0000 0000

Bit 7

R/W

0xC0AC Device 2 Interrupt Enable

Reserved

SOF/EOP

Timeout

Interrupt

Enable

Wake

Interrupt

Enable

SOF/EOP

Interrupt

Enable

EP7

EP6

EP5

EP4

EP3

EP2

EP1

EP0

0000 0000

xxxx xxxx

Interrupt

Enable

Interrupt

Enable

Interrupt

Enable

Interrupt

Enable

Interrupt

Enable

Interrupt

Enable

Interrupt

Enable

Interrupt

Enable

R/W

0xC0B0 Host 2 Status

Reserved

SOF/EOP

Interrupt

Flag

Reserved

Port B

Port A

Port B

Port A

Connect

Change

Port B

SE0

Status

Port A

SE0

Status

Reserved

Done

Interrupt

Flag

Wake Interrupt Wake Interrupt Connect

Flag

Change

Interrupt Flag Interrupt Flag

0xC0B0 Device 2 Status

Reserved

SOF/EOP

Timeout

Interrupt

Enable

Wake

Interrupt

Flag

SOF/EOP

Interrupt

Flag

Reset

Interrupt

Flag

xxxx xxxx

EP7

EP6

EP5

EP4

EP3

EP2

EP1

EP0

Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag

R/W

0xC0C6 HPI Mailbox

Message...

...Message

0000 0000

1000 0000

0xC0C8 SPI Configuration

3Wire

Enable

Phase

Select

SCK

Polarity Select

Scale Select

Reserved

Master

SS Delay Select

0001 1111

0000 0001

1000 0000

0000 0000

Active Enable Enable

Enable

R/W

0xC0CA SPI Control

SCK

Strobe

FIFO

Init

Byte

Mode

FullDuplex

Manual

Read

Transmit

Ready

receive

Enable

Data Ready

Transmit

Empty

Receive

Full

Transmit Bit Length

Receive Bit Length

R/W

0xC0CC SPI Interrupt Enable

0xC0CE SPI Status

Reserved...

...Reserved

Receive Inter- Transmit Inter- Transfer Inter- 0000 0000

rupt Enable

Reserved...

0000 0000

FIFO Error

Flag

Reserved

Receive

Transmit

Transfer

Interrupt Flag Interrupt Flag Interrupt Flag

0xC0D0 SPI Interrupt Clear

0xC0D2 SPI CRC Control

Reserved...

...Reserved

0000 0000

Transmit

Interrupt Clear Interrupt Clear

R/W

CRC Mode

CRC

Enable

CRC

Clear

Receive

CRC

One in CRC Zero in CRC Reserved...

0000 0000

...Reserved

CRC

0000 0000

1111 1111

xxxx xxxx

0000 0000

R/W

0xC0D4 SPI CRC Value

0xC0D6 SPI Data Port t

0xC0D8 SPI Transmit Address

0xC0DA SPI Transmit Count

0xC0DC SPI Receive Address

0xC0DE SPI Receive Count

0xC0E0 UART Control

...CRC

Reserved

Data

Address...

...Address

Reserved

...Count

Count...

Address...

...Address

Reserved

...Count

Reserved...

...Reserved

Reserved...

...Reserved

Scale Select Baud Select

UART Enable 0000 0111

0000 0000

0xC0E2 UART Status

Receive

Full

Transmit

Full

0000 0000

R/W

0xC0E4 UART Data

0xC0E6 PWM Control

Reserved

Data

0000 0000

PWM

Enable

Reserved

PWM2

Prescale

Select

Mode

Select

PWM3

PWM1

PWM0

PWM3

PWM2

Enable

PWM1

Enable

PWM0

Enable

0000 0000

Polarity Select Polarity Select Polarity Select Polarity Select Enable

R/W

0xC0E8 PWM Maximum Count

Reserved

...Count

Count...

0000 0000

PWM n Start

Reserved

...Address

Address...

0xC0EA

0xC0EE

2: 0xC0F2

3: 0xC0F6

Document #: 38-08015 Rev. *J

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CY7C67300

Table 142. Register Summary (continued)

R/W

Address Register

Bit 15

Bit 14

Bit 6

Bit 13

Bit 5

Bit 12

Bit 4

Bit 11

Bit 3

Bit 10

Bit 2

Bit 9

Bit 8

Bit 0

Default High

Default Low

0000 0000

Bit 7

Bit 1

R/W

PWM n Stop

Reserved

...Address

Address...

0xC0EC

1: 0xC0F0

2: 0xC0F4

3: 0xC0F8

0000 0000

R/W

0xC0FA PWM Cycle Count

Count...

...Count

0000 0000

HPI Status Port

VBUS

Flag

Reserved

SOF/EOP2

Flag

Reserved

SOF/EOP1

Flag

Reset2

Flag

Mailbox In

Flag

Resume2 Flag Resume1 Flag SIE2msg

SIE1msg

Done2 Flag Done1 Flag

Reset1 Flag

Mailbox Out

Flag

Document #: 38-08015 Rev. *J

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CY7C67300

Ordering Information

Table 143. Ordering Information

Ordering Code

CY7C67300-100AXI

CY7C67300-100AXA

CY7C67300-100AXIT

CY7C67300-100AXAT

CY3663

Package Type

100 TQFP

AEC

Pb-Free

Temperature Range

–40 to 85°C

100 TQFP

100 TQFP, tape and reel

Development Kit

Package Diagrams

Figure 12. 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100SA

NOTE:

16.00 0.25 SQ

1. JEDEC STD REF MS-026

14.00 0.05 SQ

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

100

3. DIMENSIONS IN MILLIMETERS

R 0.08 MIN.

0.20 MAX.

0° MIN.

STAND-OFF

0.05 MIN.

0.25

0.15 MAX.

GAUGE PLANE

R 0.08 MIN.

0.20 MAX.

0°-7°

0.50

TYP.

DETAIL

0.60 0.15

0.20 MIN.

1.00 REF.

NOTE: PKG. CAN HAVE

12° 1°

(8X)

SEATING PLANE

1.60 MAX.

TOP LEFT CORNER CHAMFER

4 CORNERS CHAMFER

1.40 0.05

0.08

51-85048-*C

0.20 MAX.

SEE DETAIL

Document #: 38-08015 Rev. *J

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CY7C67300

Document History Page

Document Title: CY7C67300 EZ-Host™ Programmable Embedded USB Host and Peripheral Controller with Automotive

AEC Grade Support

Document Number: 38-08015

Orig. of

Change

Submis-

sion Date

REV.

ECN NO.

Description of Change

111872

116989

125262

MUL

03/22/02 New Data Sheet

08/23/02 Preliminary Data Sheet

04/10/03 Added Memory Map Section and Ordering Information Section

Moved Functional Register Map Tables into Register section

General Clean-up

126210

MUL

05/23/03 Added Interface Description Section and Power Savings and Reset Section

Added Char Data

General Clean-up

127335

129395

KKV

MUL

05/29/03 Corrected font to enable correct symbol display

10/01/03 Final Data Sheet

Changed Memory Map Section and added CLKSEL to Pin Description

Added USB OTG Logo

General Clean-up

443992

VCS

See ECN Title changed indicating AEC Grade

Added information for AEC qualified including part number

Fixed misc. errors including:

Table 4-1: UART does not have alternate location

Section 4.3.4 had incorrect register address

Table 4-10 had incorrect pin definitions

Section 4.16.2 changed GPIO[31:20] to GPIO[31:30]

Corrected Table 7-6 and 7-14

566465

KKVTMP

ARI

See ECN Added the lead free information on the Ordering Information Section. Imple-

mented the new template with no numbers on the headings.

1063560

See ECN Changed Ordering Informatijon table to reflect Automotive Qualification and to

meet the MPN Part Number changes reflected in ECN 884880.

Changed the EZ-Host Pin Diagram figure to reflect the pin changes. Edited.

2514867

2544823

PYRS

See ECN To publish in Web

BHA/AESA 07/28/08 Updated template. Corrected A18 and A17 pin assignments in Tables 6 and 131.

Document #: 38-08015 Rev. *J

Page 98 of 99

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CY7C67300

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at cypress.com/sales.

Products

PSoC

PSoC Solutions

General

psoc.cypress.com

clocks.cypress.com

wireless.cypress.com

memory.cypress.com

image.cypress.com

psoc.cypress.com/solutions

psoc.cypress.com/low-power

psoc.cypress.com/precision-analog

psoc.cypress.com/lcd-drive

psoc.cypress.com/can

Clocks & Buffers

Wireless

Low Power/Low Voltage

Precision Analog

LCD Drive

Memories

Image Sensors

CAN 2.0b

USB

psoc.cypress.com/usb

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 38-08015 Rev. *J

Revised July 28, 2008

Page 99 of 99

EZ-Host is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C

components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system

conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders.

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