CY7C1012DV33
12-Mbit (512K X 24) Static RAM
Features
Functional Description
■
■
■
High speed
tAA = 10 ns
Low active power
ICC = 175 mA at 10 ns
Low CMOS standby power
ISB2 = 25 mA
The CY7C1012DV33 is a high performance CMOS static RAM
organized as 512K words by 24 bits. Each data byte is separately
controlled by the individual chip selects (CE1, CE2, and CE3).
CE1 controls the data on the I/O0 – I/O7, while CE2 controls the
data on I/O8 – I/O15, and CE3 controls the data on the data pins
I/O16 – I/O23. This device has an automatic power down feature
that significantly reduces power consumption when deselected.
❐
❐
❐
Writing the data bytes into the SRAM is accomplished when the
chip select controlling that byte is LOW and the write enable input
(WE) input is LOW. Data on the respective input and output (I/O)
pins is then written into the location specified on the address pins
(A0 – A18). Asserting all of the chip selects LOW and write enable
LOW writes all 24 bits of data into the SRAM. Output enable (OE)
is ignored while in WRITE mode.
■
■
■
■
■
Operating voltages of 3.3 ± 0.3V
2.0V data retention
Automatic power down when deselected
TTL compatible inputs and outputs
Available in Pb-free standard 119-ball PBGA
Data bytes are also individually read from the device. Reading a
byte is accomplished when the chip select controlling that byte
is LOW and write enable (WE) HIGH, while output enable (OE)
remains LOW. Under these conditions, the contents of the
memory location specified on the address pins appear on the
specified data input and output (I/O) pins. Asserting all the chip
selects LOW reads all 24 bits of data from the SRAM.
The 24 I/O pins (I/O0 – I/O23) are placed in a high impedance
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For more infor-
Logic Block Diagram
INPUT BUFFER
I/O0 – I/O7
I/O8 – I/O15
I/O16 – I/O23
512K x 24
ARRAY
A(9:0)
CE1, CE2, CE3
COLUMN
DECODER
WE
CONTROL LOGIC
OE
A(18:10)
Cypress Semiconductor Corporation
Document Number: 38-05610 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 6, 2008
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CY7C1012DV33
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage............. ...............................>2001V
(MIL-STD-883, Method 3015)
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Latch Up Current..................................................... >200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Ambient
Range
VCC
Temperature
Industrial
–40°C to +85°C
3.3V ± 0.3V
DC Electrical Characteristics Over the Operating Range
–10
Parameter
Description
Test Conditions [3]
Unit
Min
Max
VOH
VOL
VIH
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
VCC = Min, IOH = –4.0 mA
VCC = Min, IOL = 8.0 mA
2.4
V
V
0.4
VCC + 0.3
0.8
2.0
–0.3
–1
V
[2]
VIL
V
IIX
Input Leakage Current
Output Leakage Current
GND < VI < VCC
+1
μA
μA
mA
IOZ
ICC
GND < VOUT < VCC, output disabled
–1
+1
VCC Operating Supply
Current
VCC = Max, f = fMAX = 1/tRC
IOUT = 0 mA CMOS levels
175
ISB1
ISB2
Automatic CE Power Down Max VCC, CE > VIH
30
25
mA
mA
Current —TTL Inputs
VIN > VIH or VIN < VIL, f = fMAX
Automatic CE Power Down Max VCC, CE > VCC – 0.3V,
Current —CMOS Inputs
VIN > VCC – 0.3V, or VIN < 0.3V, f = 0
Notes
2.
V
(min) = –2.0V and V (max) = V + 2V for pulse durations of less than 20 ns.
IL IH CC
3. CE indicates a combination of all three chip enables. When active LOW, CE indicates the CE or CE or CE is LOW. When HIGH, CE indicates the CE CE and
1
2 ,
3
1 ,
2 ,
CE are HIGH.
3
Document Number: 38-05610 Rev. *D
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CY7C1012DV33
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
CIN
Description
Input Capacitance
I/O Capacitance
Test Conditions
Max
8
Unit
pF
TA = 25°C, f = 1 MHz, VCC = 3.3V
COUT
10
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
119-Ball
PBGA
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four layer printed circuit board
20.31
°C/W
ΘJC
Thermal Resistance
(junction to case)
8.35
°C/W
50Ω
30 pF*
R1 317 Ω
3.3V
= 1.5V
VTH
OUTPUT
OUTPUT
Z = 50Ω
0
R2
351Ω
5 pF*
*Including jig
and scope
(a)
(b)
*Capacitive Load consists of all
components of the test environment
All input pulses
3.0V
90%
10%
90%
10%
GND
Rise Time > 1V/ns
Fall Time:> 1V/ns
(c)
Note
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (3.0V). 100μs (t
) after reaching the minimum operating
power
DD
V
, normal SRAM operation begins including reduction in V to the data retention (V
, 2.0V) voltage.
CCDR
DD
DD
Document Number: 38-05610 Rev. *D
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CY7C1012DV33
AC Switching Characteristics
[5]
Over the Operating Range
–10
Parameter
Description
Unit
Min
Max
Read Cycle
[6]
tpower
tRC
VCC(Typical) to the First Access
100
10
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
tAA
Address to Data Valid
10
tOHA
tACE
Data Hold from Address Change
OE LOW to Data Valid
3
10
5
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
1
3
0
5
5
tPD
10
tWC
Write Cycle Time
10
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
tAW
7
tHA
0
tSA
0
tPWE
tSD
7
Data Setup to Write End
Data Hold from Write End
5.5
0
tHD
tLZWE
tHZWE
3
5
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
6.
7.
t
t
gives the minimum amount of time that the power supply is at typical V values until the first memory access is performed.
CC
POWER
, t
, t
, t
, t
, and t
are specified with a load capacitance of 5 pF as in part (b) of Figure 2. Transition is measured ±200 mV from steady state
HZOE HZCE HZWE LZOE LZCE
LZWE
voltage.
8. These parameters are guaranteed by design and are not tested.
9. The internal write time of the memory is defined by the overlap of CE or CE or CE LOW and WE LOW. Chip enables must be active and WE must be LOW to initiate
1
2
3
a write. The transition of any of these signals terminate the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates
the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document Number: 38-05610 Rev. *D
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CY7C1012DV33
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
Description
VCC for Data Retention
Data Retention Current
Min
Typ
Max
Unit
V
2
ICCDR
VCC = 2V, CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
25
mA
[11]
tCDR
Chip Deselect to Data Retention
Time
0
ns
ns
[12]
tR
Operation Recovery Time
tRC
Data Retention Waveform
DATA RETENTION MODE
3.0V
3.0V
VCC
CE
V
DR
>
2V
t
t
R
CDR
Switching Waveforms
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
t
LZCE
t
PD
ICC
ISB
t
PU
50%
50%
Notes
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear V ramp from V to V > 50 μs or stable at V > 50 μs.
CC(min)
CC
DR
CC(min)
13. Device is continuously selected. OE, CE = V .
IL
14. WE is HIGH for read cycle.
15. Address valid before or similar to CE transition LOW.
Document Number: 38-05610 Rev. *D
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CY7C1012DV33
Switching Waveforms (continued)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
SCE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
t
HD
HZOE
DATA VALID
DATA I/O
IN
NOTE 18
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 18
DATA I/O
DATA VALID
t
t
LZWE
HZWE
Notes
16. Data I/O is high impedance if OE = V
.
IH
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
18. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 38-05610 Rev. *D
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CY7C1012DV33
Truth Table
CE1
H
L
CE2
H
H
L
CE3
H
H
H
L
OE
X
L
WE
X
I/O0 – I/O7
High Z
I/O8 – I/O15
High Z
I/O16 – I/O23
High Z
Mode
Power
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Power Down
Read
)
H
H
H
H
L
Data Out
High Z
High Z
High Z
)
H
H
L
L
Data Out
High Z
High Z
Read
)
H
L
L
High Z
Data Out
Read
)
L
L
Full Data Out Full Data Out Full Data Out Read
)
L
H
L
H
H
L
X
X
X
X
H
Data In
High Z
High Z
High Z
Write
Write
Write
Write
)
H
H
L
L
Data In
High Z
High Z
)
H
L
L
High Z
Data In
Full Data In
High Z
)
L
L
Full Data In
High Z
Full Data In
High Z
)
L
L
L
H
Selected,
)
Outputs Disabled
Document Number: 38-05610 Rev. *D
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CY7C1012DV33
Ordering Information
Speed
Package
Name
Operating
Range
Ordering Code
(ns)
Package Type
10
CY7C1012DV33-10BGXI
51-85115 119-Ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-Free)
Industrial
Package Diagram
Figure 8. 119-Ball PBGA (14 x 22 x 2.4 mm)
51-85115-*B
Document Number: 38-05610 Rev. *D
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CY7C1012DV33
Document History Page
Document Title: CY7C1012DV33 12-Mbit (512K X 24) Static RAM
Document Number: 38-05610
Orig. of
Change
Submission
Date
Rev. ECN No.
Description of Change
**
250650
469517
SYT
NXR
See ECN New data sheet
*A
See ECN Converted from Advance Information to Preliminary
Corrected typo in the Document Title
Removed –10 and –12 speed bins from product offering
Changed J7 Ball of BGA from DNU to NC
Removed Industrial Operating range from product offering
Included the Maximum ratings for Static Discharge Voltage and Latch Up Current
on page 3
Changed ICC(Max) from 220 mA to 150 mA
Changed ISB1(Max) from 70 mA to 30 mA
Changed ISB2(Max) from 40 mA to 25 mA
Specified the Overshoot specification in footnote 1
Updated the Truth Table
Updated the Ordering Information table
*B
499604
NXR
VKN
See ECN Added note 1 for NC pins
Changed ICC specification from 150 mA to 185 mA
Updated Test Condition for ICC in DC Electrical Characteristics table
Added note for tACE, tLZCE, tHZCE, tPU, tPD, and tSCE in AC Switching Characteristics
Table on page 4
*C
*D
1462585
See ECN Converted from preliminary to final
Updated block diagram
Changed ICC specification from 185 mA to 225 mA
Updated thermal specs
2604677 VKN/PYRS
11/12/08
Removed Commercial operating range, Added Industrial operating range
Removed 8 ns speed bin, Added 10 ns speed bin,
Modified footnote# 3
Document Number: 38-05610 Rev. *D
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CY7C1012DV33
Sales, Solutions, and Legal Information
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Document Number: 38-05610 Rev. *D
Revised November 6, 2008
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