PRELIMINARY
CY14B104K, CY14B104M
4 Mbit (512K x 8/256K x 16) nvSRAM with
Real Time Clock
■ Watchdog timer
Features
■ Clock alarm with programmable interrupts
■ Capacitor or battery backup for RTC
■ 20 ns, 25 ns, and 45 ns access times
■ Internally organized as 512K x 8 (CY14B104K) or 256K x 16
(CY14B104M)
■ Commercial and industrial temperatures
■ 44 and 54-pin TSOP II package
■ Pb-free and RoHS compliance
■ Hands off automatic STORE on power down with only a small
capacitor
®
■ STORE to QuantumTrap nonvolatile elements is initiated by
software, device pin, or AutoStore on power down
®
Functional Description
■ RECALL to SRAM initiated by software or power up
■ High reliability
The Cypress CY14B104K/CY14B104M combines a 4-Mbit
nonvolatile static RAM with a full featured Real Time Clock in a
monolithic integrated circuit. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM is read and
written infinite number of times, while independent nonvolatile
data resides in the nonvolatile elements.
■ Infinite Read, Write, and RECALL cycles
■ 200,000 STORE cycles to QuantumTrap
■ 20 year data retention
The Real Time Clock function provides an accurate clock with
leap year tracking and a programmable, high accuracy oscillator.
The alarm function is programmable for periodic minutes, hours,
days or months alarms. There is also a programmable watchdog
timer for process control.
■ Single 3V +20%, –10% operation
■ Data integrity of Cypress nvSRAM combined with full featured
Real Time Clock
VCA
P
VCC
Quatrum
Trap
2048 X 2048
VRTCbat
VRTCcap
A0
A1
A2
A3
A4
A5
A6
A7
A8
A17
POWER
CONTROL
R
O
W
STORE
RECALL
STORE/RECALL
CONTROL
D
E
C
O
D
E
R
HSB
STATIC RAM
ARRAY
2048 X 2048
SOFTWARE
DETECT
A14 - A2
A18
DQ0
DQ1
DQ2
X1
X2
DQ3
RTC
DQ4
DQ5
DQ6
I
INT
N
P
U
T
B
U
F
F
E
R
S
DQ7
COLUMN I/O
MUX
A18- A0
DQ8
DQ9
DQ10
OE
COLUMN DEC
WE
DQ11
DQ12
DQ13
DQ14
CE
BLE
A9 A10
A
11 A12 A13 A14 A15 A16
DQ15
BHE
Notes
1. Address A - A for x8 configuration and Address A - A for x16 configuration.
0
18
0
17
2. Data DQ - DQ for x8 configuration and Data DQ - DQ for x16 configuration.
0
7
0
15
3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-07103 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 29, 2009
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PRELIMINARY
CY14B104K, CY14B104M
Table 1. Pin Definitions (continued)
Pin Name
I/O Type
Description
Output
Interrupt Output. Programmable to respond to the clock alarm, the watchdog timer, and the power
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).
INT
V
Ground
Ground for the Device. Must be connected to ground of the system.
SS
V
Power Supply Power Supply Inputs to the Device. 3.0V +20%, –10%
CC
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation
HSB is driven HIGH for short time with standard output high current.
HSB
V
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
CAP
nonvolatile elements.
Device Operation
AutoStore Operation
The CY14B104K/CY14B104M nvSRAM is made up of two
functional components paired in the same physical cell. These
are a SRAM memory cell and a nonvolatile QuantumTrap cell.
The SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM is transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations SRAM read and write operations are inhibited. The
CY14B104K/CY14B104M supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
page 23 for a complete description of read and write modes.
The CY14B104K/CY14B104M stores data to the nvSRAM using
one of three storage operations. These three operations are:
Hardware STORE, activated by the HSB; Software STORE,
activated by an address sequence; AutoStore, on device power
down. The AutoStore operation is a unique feature of
QuantumTrap technology and is enabled by default on the
CY14B104K/CY14B104M.
During normal operation, the device draws current from V to
CC
charge a capacitor connected to the V
pin. This stored
CAP
charge is used by the chip to perform a single STORE operation.
If the voltage on the V pin drops below V , the part
CC
SWITCH
automatically disconnects the V
pin from V . A STORE
CAP
CC
operation is initiated with power provided by the V
capacitor.
CAP
Figure 2. AutoStore Mode
Vcc
SRAM Read
The CY14B104K/CY14B104M performs a read cycle whenever
CE and OE are LOW, and WE and HSB are HIGH. The address
0.1uF
specified on pins A
or A
determines which of the 524,288
0-18
0-17
data bytes or 262,144 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
Vcc
an address transition, the outputs are valid after a delay of t
AA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at t or at t , whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
ACE
DOE
WE
VCAP
t
access time without the need for transitions on any control
AA
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
VCAP
VSS
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
Figure 2 shows the proper connection of the storage capacitor
the end of the cycle. The data on the common I/O pins DO
0-15
are written into the memory if it is valid t before the end of a
CAP
SD
WE controlled write or before the end of a CE controlled write.
The Byte Enable inputs (BHE, BLE) determine which bytes are
written, in the case of 16-bit words. Keep OE HIGH during the
entire write cycle to avoid data bus contention on common I/O
lines. If OE is left LOW, internal circuitry turns off the output
CAP
CAP
CC
up should be placed on WE to hold it inactive during power up.
This pull up is only effective if the WE signal is tri-state during
power up. Many MPUs tri-state their controls on power up. Verify
this when using the pull up. When the nvSRAM comes out of
buffers t
after WE goes LOW.
HZWE
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PRELIMINARY
CY14B104K, CY14B104M
power-on-recall, the MPU must be active or the WE held inactive
until the MPU comes out of reset.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
To reduce unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
The software sequence may be clocked with CE or OE controlled
reads. Both CE and OE must be toggled for the sequence to be
executed. After the sixth address in the sequence is entered, the
STORE cycle starts and the chip is disabled. It is important to use
read cycles and not write cycles in the sequence. The SRAM is
Hardware STORE (HSB) Operation
The CY14B104K/CY14B104M provides the HSB pin to control
and acknowledge the STORE operations. The HSB pin is used
to request a Hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B104K/CY14B104M conditionally initiates a
activated again for read and write operations after the t
STORE
cycle time.
STORE operation after t
. An actual STORE cycle begins
DELAY
only if a write to the SRAM has taken place since the last STORE
or RECALL cycle. The HSB pin also acts as an open drain driver
that is internally driven LOW to indicate a busy condition when
the STORE (initiated by any means) is in progress.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
perform the following sequence of CE or OE controlled read
operations:
SRAM read and write operations, that are in progress when HSB
is driven LOW by any means, are given time t
to complete
DELAY
before the STORE operation is initiated. However, any SRAM
write cycles requested after HSB goes LOW are inhibited until
HSB returns HIGH. In case the write latch is not set, HSB is not
driven LOW by the CY14B104K/CY14B104M but any SRAM
read and write cycles are inhibited until HSB is returned HIGH by
MPU or external source.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
During any STORE operation, regardless of how it is initiated,
the CY14B104KA/CY14B104MA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion
of
the
STORE
operation,
the
CY14B104K/CY14B104M remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
SRAM cells. After the t
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
cycle time, the SRAM is again
RECALL
Hardware RECALL (Power Up)
During power up or after any low power condition
(V < V
), an internal RECALL request is latched. When
CC
SWITCH
V
again exceeds the V
on powerup, a RECALL cycle
SWITCH
CC
is automatically initiated and takes t
to complete. During
HRECALL
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B104K/CY14B104M
Software STORE cycle is initiated by executing sequential CE or
OE controlled read cycles from six specific address locations in
exact order. During the STORE cycle, an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
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PRELIMINARY
CY14B104K, CY14B104M
Table 2. Mode Selection
[6]
Mode
I/O
Power
Standby
Active
A
- A
X
CE
H
WE
OE, BHE, BLE
15
0
X
H
L
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
L
L
L
L
X
L
X
X
Active
[7]
H
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
Disable
[7]
L
L
L
H
H
H
L
L
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
Enable
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active I
CC2
[7]
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE or OE
controlled read operations must be performed:
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
or OE controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) issued to save the
AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
Notes
6. While there are 19 address lines on the CY14B104K (18 address lines on the CY14B104M), only the 13 address lines (A - A ) are used to control software modes.
14
2
Rest of the address lines are don’t care.
7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
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PRELIMINARY
CY14B104K, CY14B104M
Setting the Clock
Data Protection
Setting the write bit ‘W’ (in the flags register at 0x7FFF0) to a ‘1’
stops updates to the time keeping registers and enables the time
to be set. The correct day, date, and time is then written into the
registers and must be in 24 hour BCD format. The time written is
referred to as the “Base Time”. This value is stored in nonvolatile
registers and used in the calculation of the current time.
Resetting the write bit to ‘0’ transfers the values of timekeeping
registers to the actual clock counters, after which the clock
resumes normal operation.
The CY14B104K/CY14B104M protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected when
V
is less than
V
.
If the
CC
SWITCH
CY14B104K/CY14B104M is in a write mode (both CE and WE
are LOW) at power up, after a RECALL or STORE, the write is
inhibited until the SRAM is enabled after t
(HSB to output
LZHSB
active). This protects against inadvertent writes during power up
or brown out conditions.
If the time written to the timekeeping registers is not in the correct
BCD format, each invalid nibble of the RTC registers continue
counting to 0xF before rolling over to 0x0 after which RTC
resumes normal operation.
Noise Considerations
Real Time Clock Operation
nvTIME Operation
Note The values entered in the timekeeping, alarm, calibration,
and interrupt registers need a STORE operation to be saved in
nonvolatile memory. Therefore, while working in AutoStore
disabled mode, the user must perform a STORE operation after
writing into the RTC registers for the RTC to work correctly.
The CY14B104K/CY14B104M offers internal registers that
contain clock, alarm, watchdog, interrupt, and control functions.
RTC registers use the last 16 address locations of the SRAM.
Internal double buffering of the clock and timer information
registers prevents accessing transitional internal clock data
during a read or write operation. Double buffering also
circumvents disrupting normal timing counts or the clock
accuracy of the internal clock when accessing clock data. Clock
and alarm registers store data in BCD format.
Backup Power
The RTC in the CY14B104K is intended for permanently
powered operation. The V
or V
pin is connected
RTCcap
RTCbat
depending on whether a capacitor or battery is chosen for the
application. When the primary power, V , fails and drops below
CC
V
the device switches to the backup power supply.
SWITCH
The clock oscillator uses very little current, which maximizes the
backup time available from the backup source. Regardless of the
clock operation with the primary source removed, the data stored
in the nvSRAM is secure, having been stored in the nonvolatile
elements when power was lost.
RTC functionality is described with respect to CY14B104K in the
following sections. The same description applies to
CY14B104M, except for the RTC register addresses. The RTC
register addresses for CY14B104K range from 0x7FFF0 to
0x7FFFF, while those for CY14B104M range from 0x3FFF0 to
for a detailed Register Map description.
During backup operation, the CY14B104K consumes
a
maximum of 300 nanoamps at room temperature. User must
choose capacitor or battery values according to the application.
Clock Operations
Backup time values based on maximum current specifications
are shown in the following table. Nominal backup times are
approximately two times longer.
The clock registers maintain time up to 9,999 years in one
second increments. The time can be set to any calendar time and
the clock automatically keeps track of days of the week and
month, leap years, and century transitions. There are eight
registers dedicated to the clock functions, which are used to set
time with a write cycle and to read time during a read cycle.
These registers contain the time of day in BCD format. Bits
defined as ‘0’ are currently not used and are reserved for future
use by Cypress.
Table 3. RTC Backup Time
Capacitor Value
Backup Time
72 hours
14 days
0.1F
0.47F
1.0F
30 days
Reading the Clock
Using a capacitor has the obvious advantage of recharging the
backup source each time the system is powered up. If a battery
is used, a 3V lithium is recommended and the CY14B104K
sources current only from the battery when the primary power is
removed. However the battery is not recharged at any time by
the CY14B104K. The battery capacity must be chosen for total
anticipated cumulative down time required over the life of the
system.
The double buffered RTC register structure reduces the chance
of reading incorrect data from the clock. The user must stop
internal updates to the CY14B104K time keeping registers
before reading clock data, to prevent reading of data in transition.
Stopping the register updates does not affect clock accuracy.
The updating process is stopped by writing a ‘1’ to the read bit
‘R’ (in the flags register at 0x7FFF0), and does not restart until a
‘0’ is written to the read bit. The RTC registers are then read while
the internal clock continues to run. After a ‘0’ is written to the read
bit (‘R’), all RTC registers are simultaneously updated within
20 ms
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x7FFF8 controls
the enable and disable of the oscillator. This bit is nonvolatile and
is shipped to customers in the “enabled” (set to 0) state. To
preserve the battery life when the system is in storage, OSCEN
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PRELIMINARY
CY14B104K, CY14B104M
must be set to ‘1’. This turns off the oscillator circuit, extending
the battery life. If the OSCEN bit goes from disabled to enabled,
it takes approximately one second (two seconds maximum) for
the oscillator to start.
toggle at a nominal frequency of 512 Hz. Any deviation
measured from the 512 Hz indicates the degree and direction of
the required correction. For example, a reading of 512.01024 Hz
indicates a +20 ppm error. Hence, a decimal value of –10
(001010b) must be loaded into the Calibration register to offset
this error.
While system power is off, If the voltage on the backup supply
(V
or V
) falls below their respective minimum level,
RTCcap
RTCbat
the oscillator may fail.The CY14B104K has the ability to detect
oscillator failure when system power is restored. This is recorded
in the OSCF (Oscillator Failed bit) of the flags register at the
Note Setting or changing the Calibration register does not affect
the test output frequency.
To set or clear CAL, set the write bit “W” (in the flags register at
0x7FFF0) to “1” to enable writes to the Flag register. Write a
value to CAL, and then reset the write bit to “0” to disable writes.
address 0x7FFF0. When the device is powered on (V
goes
CC
above V
) the OSCEN bit is checked for “enabled” status.
SWITCH
If the OSCEN bit is enabled and the oscillator is not active within
the first 5 ms, the OSCF bit is set to “1”. The system must check
for this condition and then write ‘0’ to clear the flag. Note that in
addition to setting the OSCF flag bit, the time registers are reset
the value last written to the timekeeping registers. The control or
calibration registers and the OSCEN bit are not affected by the
‘oscillator failed’ condition.
Alarm
The alarm function compares user programmed values of alarm
time and date (stored in the registers 0x7FFF1-5) with the corre-
sponding time of day and date values. When a match occurs, the
alarm internal flag (AF) is set and an interrupt is generated on
INT pin if Alarm Interrupt Enable (AIE) bit is set.
There are four alarm match fields - date, hours, minutes, and
seconds. Each of these fields has a match bit that is used to
determine if the field is used in the alarm match logic. Setting the
match bit to ‘0’ indicates that the corresponding field is used in
the match process. Depending on the match bits, the alarm
occurs as specifically as once a month or as frequently as once
every minute. Selecting none of the match bits (all 1s) indicates
that no match is required and therefore, alarm is disabled.
Selecting all match bits (all 0s) causes an exact time and date
match.
The value of OSCF must be reset to ‘0’ when the time registers
are written for the first time. This initializes the state of this bit
which may have become set when the system was first powered
on.
To reset OSCF, set the write bit “W” (in the Flags register at
0x7FFF0) to a “1” to enable writes to the Flag register. Write a
“0” to the OSCF bit and then reset the write bit to “0” to disable
writes.
Calibrating the Clock
There are two ways to detect an alarm event: by reading the AF
flag or monitoring the INT pin. The AF flag in the flags register at
0x7FFF0 indicates that a date or time match has occurred. The
AF bit is set to “1” when a match occurs. Reading the flags
register clears the alarm flag bit (and all others). A hardware
interrupt pin may also be used to detect an alarm event.
The RTC is driven by a quartz controlled crystal with a nominal
frequency of 32.768 kHz. Clock accuracy depends on the quality
of the crystal and calibration. The crystals available in market
typically have an error of +20 ppm to +35 ppm. However,
CY14B104K employs a calibration circuit that improves the
accuracy to +1/–2 ppm at 25°C. This implies an error of +2.5
seconds to -5 seconds per month.
To set, clear or enable an alarm, set the ‘W’ bit (in Flags Register
- 0x7FFF0) to ‘1’ to enable writes to Alarm Registers. After writing
the alarm value, clear the ‘W’ bit back to “0” for the changes to
take effect.
The calibration circuit adds or subtracts counts from the oscillator
divider circuit to achieve this accuracy. The number of pulses that
are suppressed (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five
calibration bits found in Calibration register at 0x7FFF8. The
calibration bits occupy the five lower order bits in the Calibration
register. These bits are set to represent any value between ‘0’
and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates
positive calibration and a ‘0’ indicates negative calibration.
Adding counts speeds the clock up and subtracting counts slows
the clock down. If a binary ‘1’ is loaded into the register, it corre-
sponds to an adjustment of 4.068 or –2.034 ppm offset in oscil-
lator error, depending on the sign.
Note CY14B104K requires the alarm match bit for seconds
(0x7FFF2 - D7) to be set to ‘0’ for proper operation of Alarm Flag
and Interrupt.
Watchdog Timer
The Watchdog Timer is a free running down counter that uses
the 32 Hz clock (31.25 ms) derived from the crystal oscillator.
The oscillator must be running for the watchdog to function. It
begins counting down from the value loaded in the Watchdog
Timer register.
The timer consists of a loadable register and a free running
counter. On power up, the watchdog time out value in register
0x7FFF7 is loaded into the Counter Load register. Counting
begins on power up and restarts from the loadable value any time
the Watchdog Strobe (WDS) bit is set to ‘1’. The counter is
compared to the terminal value of ‘0’. If the counter reaches this
value, it causes an internal flag and an optional interrupt output.
You can prevent the time out interrupt by setting WDS bit to ‘1’
prior to the counter reaching ‘0’. This causes the counter to
reload with the watchdog time out value and to be restarted. As
long as the user sets the WDS bit prior to the counter reaching
the terminal value, the interrupt and WDT flag never occur.
Calibration occurs within a 64-minute cycle. The first 62 minutes
in the cycle may, once per minute, have one second shortened
by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is
loaded into the register, only the first two minutes of the
64-minute cycle are modified. If a binary 6 is loaded, the first 12
are affected, and so on. Therefore, each calibration step has the
effect of adding 512 or subtracting 256 oscillator cycles for every
125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm
of adjustment per calibration step in the Calibration register.
To determine the required calibration, the CAL bit in the Flags
register (0x7FFF0) must be set to ‘1’. This causes the INT pin to
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PRELIMINARY
CY14B104K, CY14B104M
New time out values are written by setting the watchdog write bit
to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out
value bits D5-D0 are enabled to modify the time out value. When
WDW is ‘1’, writes to bits D5-D0 are ignored. The WDW function
enables a user to set the WDS bit without concern that the
watchdog timer value is modified. A logical diagram of the
watchdog time out value to ‘0’ disables the watchdog function.
determine the cause of the interrupt. The INT pin driver has two
bits that specify its behavior when an interrupt occurs.
An Interrupt is raised only if both a flag is raised by one of the
three sources and the respective interrupt enable bit in Interrupts
register is enabled (set to ‘1’). After an interrupt source is active,
two programmable bits, H/L and P/L, determine the behavior of
the output pin driver on INT pin. These two bits are located in the
Interrupt register and can be used to drive level or pulse mode
output from the INT pin. In pulse mode, the pulse width is
internally fixed at approximately 200 ms. This mode is intended
to reset a host microcontroller. In the level mode, the pin goes to
its active polarity until the Flags register is read by the user. This
mode is used as an interrupt to a host microcontroller. The
control bits are summarized in the following section.
The output of the watchdog timer is the flag bit WDF that is set if
the watchdog is allowed to time out. If the Watchdog Interrupt
Enable (WIE) bit in the Interrupt register is set, a hardware
interrupt on INT pin is also generated on watchdog timeout. The
flag and the hardware interrupt are both cleared when user reads
the Flags registers.
Figure 3. Watchdog Timer Block Diagram
Interrupts are only generated while working on normal power and
are not triggered when system is running in backup power mode.
Clock
Oscillator
1 Hz
Divider
Note CY14B104K generates valid interrupts only after the
32,768 KHz
Powerup Recall sequence is completed. All events on INT pin
32 Hz
must be ignored for t
duration after powerup.
HRECALL
Zero
Compare
WDF
Counter
Interrupt Register
Watchdog Interrupt Enable - WIE. When set to ‘1’, the
watchdog timer drives the INT pin and an internal flag when a
watchdog time out occurs. When WIE is set to ‘0’, the watchdog
timer only affects the WDF flag in Flags register.
Load
WDS
Register
Q
Alarm Interrupt Enable - AIE. When set to ‘1’, the alarm match
drives the INT pin and an internal flag. When AIE is set to ‘0’, the
alarm match only affects the AF Flags register.
D
WDW
Q
Power Fail Interrupt Enable - PFE. When set to ‘1’, the power
fail monitor drives the pin and an internal flag. When PFE is set
to ‘0’, the power fail monitor only affects the PF flag in Flags
register.
Watchdog
Register
write to
Watchdog
Register
.
Power Monitor
High/Low - H/L. When set to a ‘1’, the INT pin is active HIGH
The CY14B104K provides a power management scheme with
power fail interrupt capability. It also controls the internal switch
to backup power for the clock and protects the memory from low
and the driver mode is push pull. The INT pin drives high only
when V is greater than V
. When set to a ‘0’, the INT pin
CC
SWITCH
is active LOW and the drive mode is open drain. The INT pin
must be pulled up to Vcc by a 10k resistor while using the
interrupt in active LOW mode.
Pulse/Level - P/L. When set to a ‘1’ and an interrupt occurs, the
INT pin is driven for approximately 200 ms. When P/L is set to a
‘0’, the INT pin is driven high or low (determined by H/L) until the
Flags or Control register is read.
V
access. The power monitor is based on an internal band gap
CC
reference circuit that compares the V
voltage to V
CC
SWITCH
threshold.
when V is reached as V decays from power loss, a data
SWITCH
CC
STORE operation is initiated from SRAM to the nonvolatile
elements, securing the last SRAM data state. Power is also
When an enabled interrupt source activates the INT pin, an
external host reads the Flags registers to determine the cause.
Remember that all flags are cleared when the register is read. If
the INT pin is programmed for Level mode, then the condition
clears and the INT pin returns to its inactive state. If the pin is
programmed for Pulse mode, then reading the flag also clears
the flag and the pin. The pulse does not complete its specified
duration if the Flags register is read. If the INT pin is used as a
host reset, the Flags register is not read during a reset
switched from V to the backup supply (battery or capacitor) to
CC
operate the RTC oscillator.
When operating from the backup source, read and write opera-
tions to nvSRAM are inhibited and the clock functions are not
available to the user. The clock continues to operate in the
background. The updated clock data is available to the user
t
delay after V
is restored to the device (see
Flags Register
Interrupts
The Flag register has three flag bits: WDF, AF, and PF, which can
be used to generate an interrupt. They are set by the watchdog
timeout, alarm match, or power fail monitor respectively. The
processor can either poll this register or enable interrupts when
a flag is set. These flags are automatically reset once the register
is read. The flags register is automatically loaded with the value
The CY14B104K has Flags register, Interrupt register, and
Interrupt logic that can signal interrupt to the microcontroller.
There are three potential sources for interrupt: watchdog timer,
power monitor, and alarm timer. Each of these can be individually
enabled to drive the INT pin by appropriate setting in the Interrupt
register (0x7FFF6). In addition, each has an associated flag bit
in the Flags register (0x7FFF0) that the host processor uses to
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PRELIMINARY
CY14B104K, CY14B104M
Figure 4. RTC Recommended Component Configuration
Recommended Values
Y
= 32.768 KHz (6 pF)
1
C1 = 21 pF
C2 = 21 pF
Note: The recommended values for C1 and C2 include
board trace capacitance.
C1
C2
X
1
Y1
X
2
Figure 5. Interrupt Block Diagram
WDF
Watchdog
Timer
WDF - Watchdog Timer Flag
WIE - Watchdog Interrupt
Enable
WIE
PF
V
CC
P/L
PF - Power Fail Flag
PFE - Power Fail Enable
Power
Pin
Monitor
INT
AF - Alarm Flag
AIE - Alarm Interrupt Enable
PFE
Driver
VINT
P/L - Pulse Level
H/L - High/Low
H/L
V
SS
AF
Clock
Alarm
AIE
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PRELIMINARY
CY14B104K, CY14B104M
[8]
Table 4. RTC Register Map
[9]
Register
BCD Format Data
Function/Range
CY14B104K CY14B104M
D7
D6
D5
D4
D3
D2
Years
Months
D1
D0
0x7FFFF
0x7FFFE
0x3FFFF
0x3FFFE
10s Years
Years: 00–99
0
0
0
10s
Months: 01–12
Months
0x7FFFD
0x7FFFC
0x7FFFB
0x7FFFA
0x7FFF9
0x7FFF8
0x3FFFD
0x3FFFC
0x3FFFB
0x3FFFA
0x3FFF9
0x3FFF8
0
0
0
0
0
0
0
0
10s Day of Month
Day Of Month
Day of week
Day of Month: 01–31
Day of week: 01–07
Hours: 00–23
0
0
0
10s Hours
10s Minutes
Hours
Minutes
Seconds
Minutes: 00–59
10s Seconds
Seconds: 00–59
OSCEN
(0)
0
CalSign
(0)
Calibration (00000)
Calibration Values
0x7FFF7
0x7FFF6
0x7FFF5
0x3FFF7
0x3FFF6
0x3FFF5
WDS
(0)
WDW (0)
WDT (000000)
Watchdog
WIE (0) AIE (0)
PFE (0)
0
H/L
(1)
P/L (0)
0
0
Interrupts
M (1)
0
0
10s Alarm Date
10s Alarm Hours
Alarm Day
Alarm, Day of Month:
01–31
0x7FFF4
0x7FFF3
0x3FFF4
0x3FFF3
M (1)
M (1)
Alarm Hours
Alarm, Hours: 00–23
10 Alarm Minutes
Alarm Minutes
Alarm, Minutes:
00–59
0x7FFF2
0x3FFF2
M (1)
10 Alarm Seconds
Alarm, Seconds
Alarm, Seconds:
00–59
0x7FFF1
0x7FFF0
0x3FFF1
0x3FFF0
10s Centuries
AF PF
Centuries
Centuries: 00–99
WDF
OSCF
0
CAL (0) W (0) R (0)
Flags
Note
8. Upper Byte D -D (CY14B104MA) of RTC registers are reserved for future use
15
8
9. ( ) designates values shipped from the factory.
10. This is a binary value, not a BCD value.
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PRELIMINARY
CY14B104K, CY14B104M
Table 5. Register Map Detail
Register
Description
CY14B104K
CY14B104M
Time Keeping - Years
D4 D3
0x7FFFF
0x3FFFF
D7
D6
D5
10s Years
D2
D1
D0
Years
Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years;
upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The
range for the register is 0–99.
Time Keeping - Months
0x7FFFE
0x3FFFE
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
10s Month
Months
Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates
from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range
for the register is 1–12.
Time Keeping - Date
0x7FFFD
0x7FFFC
0x7FFFB
0x7FFFA
0x7FFF9
0x3FFFD
0x3FFFC
0x3FFFB
0x3FFFA
0x3FFF9
D7
D6
D5
D4
D3
D2
D1
D0
0
0
10s Day of Month
Day of Month
Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit
and operates from 0 to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3.
The range for the register is 1–31. Leap years are automatically adjusted for.
Time Keeping - Day
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
Day of Week
Lower nibble (three bits) contains a value that correlates to day of the week. Day of the week is a
ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day
value, because the day is not integrated with the date.
Time Keeping - Hours
D7
D6
D5
D4
D3
D2
D1
D0
0
0
10s Hours
Hours
Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower
digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from
0 to 2. The range for the register is 0–23.
Time Keeping - Minutes
D7
D6
D5
D4
D3
D2
D1
Minutes
D0
0
10s Minutes
Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates
from 0 to 9; upper nibble (three bits) contains the upper minutes digit and operates from 0 to 5.
The range for the register is 0–59.
Time Keeping - Seconds
D7
D6
D5
D4
D3
D2
D1
Seconds
D0
0
10s Seconds
Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates
from 0 to 9; upper nibble (three bits) contains the upper digit and operates from 0 to 5. The range
for the register is 0–59.
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PRELIMINARY
CY14B104K, CY14B104M
Table 5. Register Map Detail (continued)
Register
Description
CY14B104K
CY14B104M
Calibration/Control
D4 D3
0x7FFF8
0x3FFF8
D7
D6
D5
D2
D1
D0
OSCEN
0
Calibration
Sign
Calibration
OSCEN
Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs.
Disabling the oscillator saves battery or capacitor power during storage.
Calibration
Sign
Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from
the time-base.
Calibration
These five bits control the calibration of the clock.
WatchDog Timer
0x7FFF7
0x3FFF7
D7
D6
D5
D4
D3
D2
D1
D0
WDS
WDW
WDT
WDS
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to
0 has no effect. The bit is cleared automatically after the watchdog timer is reset. The WDS bit is
write only. Reading it always returns a 0.
WDW
Watchdog Write Enable. Setting this bit to 1 disables any WRITE to the watchdog timeout value
(D5–D0). This allows the user to set the watchdog strobe bit without disturbing the timeout value.
Setting this bit to 0 allows bits D5–D0 to be written to the watchdog register when the next write
WDT
Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this
register. It represents a multiplier of the 32 Hz count (31.25 ms). The range of timeout value is
31.25 ms (a setting of 1) to 2 seconds (setting of 3 Fh). Setting the watchdog timer register to 0
disables the timer. These bits can be written only if the WDW bit was set to 0 on a previous cycle.
Interrupt Status/Control
0x7FFF6
0x3FFF6
D7
D6
D5
D4
D3
D2
D1
D0
WIE
AIE
PFE
0
H/L
P/L
0
0
WIE
Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer
drives the INT pin and the WDF flag. When set to 0, the watchdog timeout affects only the WDF
flag.
AIE
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin and the AF flag. When
set to 0, the alarm match only affects the AF flag.
PFE
Power Fail Enable. When set to 1, the power fail monitor drives the INT pin and the PF flag. When
set to 0, the power fail monitor affects only the PF flag.
0
Reserved for future use
H/L
High/Low. When set to 1, the INT pin is driven active HIGH. When set to 0, the INT pin is open
drain, active LOW.
P/L
Pulse/Level. When set to 1, the INT pin is driven active (determined by H/L) by an interrupt source
for approximately 200 ms. When set to 0, the INT pin is driven to an active level (as set by H/L)
until the flags register is read.
Alarm - Day
0x7FFF5
0x3FFF5
D7
D6
D5
D4
D3
D2
D1
D0
M
0
10s Alarm Date
Alarm Date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date
value.
M
Match. When this bit is set to 0, the date value is used in the alarm match. Setting this bit to 1
causes the match circuit to ignore the date value.
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PRELIMINARY
CY14B104K, CY14B104M
Table 5. Register Map Detail (continued)
Register
Description
CY14B104K
CY14B104M
Alarm - Hours
D4 D3
0x7FFF4
0x3FFF4
D7
D6
D5
D2
D1
D0
M
10s Alarm Hours
Alarm Hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
M
M
M
Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1
causes the match circuit to ignore the hours value.
Alarm - Minutes
0x7FFF3
0x7FFF2
0x3FFF3
0x3FFF2
D7
D6
D5
D4
D3
D2
D1
D0
M
10s Alarm Minutes
Alarm Minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.
Match. When this bit is set to 0, the minutes value is used in the alarm match. Setting this bit to 1
causes the match circuit to ignore the minutes value.
Alarm - Seconds
D7
D6
D5
D4
D3
D2
D1
D0
M
10s Alarm Seconds
Alarm Seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.
Match. When this bit is set to 0, the seconds value is used in the alarm match. Setting this bit to
1 causes the match circuit to ignore the seconds value.
Time Keeping - Centuries
0x7FFF1
0x7FFF0
0x3FFF1
0x3FFF0
D7
D6
D5
D4
D3
D2
D1
Centuries
D0
10s Centuries
Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0
to 9; upper nibble contains the upper digit and operates from 0 to 9. The range for the register is
0-99 centuries.
Flags
D7
D6
D5
D4
D3
D2
D1
D0
WDF
AF
PF
OSCF
0
CAL
W
R
WDF
AF
Watchdog Timer Flag. This read only bit is set to 1 when the watchdog timer is allowed to reach
0 without being reset by the user. It is cleared to 0 when the Flags register is read or on power up
Alarm Flag. This read only bit is set to 1 when the time and date match the values stored in the
alarm registers with the match bits = 0. It is cleared when the Flags register is read or on power up.
PF
Power Fail Flag. This read only bit is set to 1 when power falls below the power fail threshold
V
. It is cleared to 0 when the Flags register is read or on power up.
SWITCH
OSCF
Oscillator Fail Flag. Set to 1 on power up if the oscillator is enabled and not running in the first 5
ms of operation. This indicates that RTC backup power failed and clock value is no longer valid.
This bit survives power cycle and is never cleared internally by the chip. The user must check for
this condition and write '0' to clear this flag.
CAL
W
Calibration Mode. When set to 1, a 512 Hz square wave is output on the INT pin. When set to 0,
the INT pin resumes normal operation. This bit defaults to 0 (disabled) on power up.
Write Enable: Setting the W bit to 1 freezes updates of the RTC registers. The user can then write
to RTC registers, Alarm registers, Calibration register, Interrupt register and Flags register. Setting
the W bit to 0 causes the contents of the RTC registers to be transferred to the time keeping
counters if the time has been changed (a new base time is loaded). This bit defaults to 0 on power
up.
R
Read Enable: Setting R bit to 1, stops clock updates to user RTC registers so that clock updates
are not seen during the reading process. Set R bit to 0 to resume clock updates to the holding
register. Setting this bit does not require W bit to be set to 1. This bit defaults to 0 on power up.
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PRELIMINARY
CY14B104K, CY14B104M
Transient Voltage (<20 ns) on
Any Pin to Ground Potential .................. –2.0V to V + 2.0V
Maximum Ratings
CC
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Package Power Dissipation
Capability (T = 25°C) ................................................... 1.0W
A
Storage Temperature ................................. –65°C to +150°C
Maximum Accumulated Storage Time
Surface Mount Pb Soldering
Temperature (3 Seconds).......................................... +260°C
DC Output Current (1 output at a time, 1s duration).....15 mA
At 150°C Ambient Temperature................................... 1000h
At 85°C Ambient Temperature..................... ........... 20 Years
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied ............................................ –55°C to +150°C
Latch Up Current ................................................... > 200 mA
Supply Voltage on V Relative to GND ..........–0.5V to 4.1V
CC
Operating Range
Voltage Applied to Outputs
in High-Z State.......................................–0.5V to V + 0.5V
CC
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
V
CC
Input Voltage...........................................–0.5V to Vcc + 0.5V
2.7V to 3.6V
2.7V to 3.6V
–40°C to +85°C
DC Electrical Characteristics
Over the Operating Range (V = 2.7V to 3.6V)
CC
Parameter
Description
Average V Current
Test Conditions
Min
Max
Unit
I
t
t
t
= 20 ns
= 25 ns
= 45 ns
Commercial
65
65
50
mA
mA
CC1
cc
RC
RC
RC
Values obtained without output loads (I
= 0 mA)
Industrial
OUT
70
70
52
mA
mA
I
I
Average V Current All Inputs Don’t Care, V = Max.
10
mA
mA
CC2
CC
CC
during STORE
Average current for duration t
STORE
Average V Current All I/P cycling at CMOS levels.
35
CC3
CC
at t = 200 ns, 3V,
Values obtained without output loads (I
= 0 mA).
RC
OUT
25°C typical
I
I
I
AverageV
during AutoStore
Cycle
Current All Inputs Don’t Care, V = Max.
5
5
mA
mA
CC4
CAP
CC
Average current for duration t
STORE
V
Standby Current CE > (V – 0.2V). All others V < 0.2V or > (V – 0.2V). Standby
CC IN CC
SB
CC
current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
InputLeakageCurrent V = Max, V < V < V
(except HSB)
–1
–100
–1
+1
+1
+1
μA
μA
μA
IX
CC
SS
IN
CC
InputLeakageCurrent V = Max, V < V < V
(for HSB)
CC
SS
IN
CC
I
Off State Output
Leakage Current
V
= Max, V < V
< V , CE or OE > V or BHE/BLE > V
IH
OZ
CC
SS
OUT
CC
IH
or WE < V
IL
V
V
V
V
V
Input HIGH Voltage
Input LOW Voltage
2.0
V
+ 0.5
V
V
IH
CC
V
– 0.5
SS
0.8
IL
Output HIGH Voltage I
= –2 mA
= 4 mA
2.4
61
V
OH
OL
OUT
Output LOW Voltage
Storage Capacitor
I
0.4
V
OUT
Between V
pin and V , 5V Rated
180
μF
CAP
CAP
SS
Notes
11. Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25°C (room temperature), and V = 3V. Not 100% tested.
CC
12. The HSB pin has I
= -2 uA for V of 2.4V when both active HIGH and LOW drivers are disabled. When they are enabled standard V and V are valid. This
OUT
O
H
O
H
O
L
parameter is characterized but not tested.
13. V (Storage capacitor) nominal value is 68uF.
CAP
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PRELIMINARY
CY14B104K, CY14B104M
Data Retention and Endurance
Parameter
Description
Min
20
Unit
Years
K
DATA
Data Retention
Nonvolatile STORE Operations
R
NV
200
C
Capacitance
In the following table, the capacitance parameters are listed.
Parameter Description
Input Capacitance
Output Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max
7
Unit
C
C
pF
pF
IN
A
V
= 0 to 3.0V
CC
7
OUT
Thermal Resistance
In the following table, the thermal resistance parameters are listed.
Parameter
Description
Test Conditions
44 TSOP II 54 TSOP II Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Testconditionsfollowstandard
test methods and procedures
for measuring thermal
impedance, in accordance
with EIA/JESD51.
31.11
30.73
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
5.56
6.08
°C/W
Figure 6. AC Test Loads
577Ω
R1
577Ω
3.0V
OUTPUT
3.0V
OUTPUT
R1
R2
789Ω
R2
789Ω
5 pF
30 pF
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V
Input Rise and Fall Times (10% - 90%)........................ <3 ns
Input and Output Timing Reference Levels .................... 1.5V
Note
14. These parameters are only guaranteed by design and are not tested.
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PRELIMINARY
CY14B104K, CY14B104M
Table 6. RTC Characteristics
Parameters
Description
RTC Backup Current
Test Conditions
Min
Typ
Max Units
o
I
Room Temperature (25 C)
300
450
3.3
3.6
2
nA
nA
V
BAK
o
Hot Temperature (85 C)
V
V
RTC Battery Pin Voltage
RTC Capacitor Pin Voltage
RTC Oscillator Time to Start
1.8
1.5
3.0
3.0
1
RTCbat
V
RTCcap
tOCS
sec
Notes
15. From either V
or V
RTCbat.
RTCcap
Document #: 001-07103 Rev. *K
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PRELIMINARY
CY14B104K, CY14B104M
AC Switching Characteristics
Parameters
20 ns
25 ns
45 ns
Description
Unit
Cypress
Parameters
Alt
Min
Max
Min
Max
Min
Max
Parameters
SRAM Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
20
25
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ACE
ACS
RC
AA
Read Cycle Time
20
25
45
RC
AA
Address Access Time
20
10
25
12
45
20
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Byte Enable to Data Valid
DOE
OHA
OE
OH
LZ
3
3
3
3
3
3
LZCE
HZCE
LZOE
HZOE
8
8
10
10
15
15
HZ
0
0
0
0
0
0
OLZ
OHZ
PA
PU
PD
20
10
25
12
45
20
PS
-
-
-
DBE
[14]
Byte Enable to Output Active
Byte Disable to Output Inactive
0
0
0
LZBE
8
10
15
HZBE
SRAM Write Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
20
15
15
8
25
20
20
10
0
45
30
30
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
WC
WP
CW
DW
DH
Write Pulse Width
PWE
SCE
SD
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active after End of Write
Byte Enable to End of Write
0
HD
15
0
20
0
30
0
AW
AW
AS
SA
0
0
0
HA
WR
WZ
OW
8
10
15
HZWE
LZWE
BW
3
3
3
-
15
20
30
Switching Waveforms
Figure 7. SRAM Read Cycle 1: Address Controlled
tRC
Address
Address Valid
tAA
Output Data Valid
Previous Data Valid
tOHA
Data Output
Notes
16. WE must be HIGH during SRAM read cycles.
17. Device is continuously selected with CE, OE and BHE / BLE LOW.
18. Measured ±200 mV from steady state output voltage.
19. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
20. HSB must remain HIGH during READ and WRITE cycles.
Document #: 001-07103 Rev. *K
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PRELIMINARY
CY14B104K, CY14B104M
Switching Waveforms
Figure 8. SRAM Read Cycle 2: CE Controlled
Address
CE
Address Valid
tRC
tHZCE
tACE
tAA
tLZCE
tHZOE
tDOE
OE
tHZBE
tLZOE
tDBE
BHE, BLE
tLZBE
High Impedance
Data Output
Output Data Valid
tPD
tPU
Active
ICC
Standby
Figure 9. SRAM Write Cycle 1: WE Controlled
tWC
Address
Address Valid
tSCE
tHA
CE
tBW
BHE, BLE
tAW
tPWE
WE
Data Input
Data Output
tSA
tHD
tSD
Input Data Valid
tLZWE
tHZWE
High Impedance
Previous Data
Notes
21. CE or WE must be >V during address transitions.
IH
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PRELIMINARY
CY14B104K, CY14B104M
Switching Waveforms
Figure 10. SRAM Write Cycle 2: CE Controlled
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tBW
BHE, BLE
tPWE
WE
tHD
tSD
Input Data Valid
Data Input
High Impedance
Data Output
Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled
(Not applicable for RTC register writes)
tWC
Address
CE
Address Valid
tSCE
tSA
tHA
tBW
BHE, BLE
WE
tAW
tPWE
tSD
tHD
Data Input
Input Data Valid
High Impedance
Data Output
Note
22. Only CE and WE controlled writes to RTC registers are allowed. BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register.
Document #: 001-07103 Rev. *K
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PRELIMINARY
CY14B104K, CY14B104M
AutoStore/Power Up RECALL
20 ns
25 ns
45 ns
Parameters
Description
Unit
Min
Max
Min
Max
20
Min
Max
20
t
t
t
Power Up RECALL Duration
STORE Cycle Duration
20
8
ms
ms
ns
V
HRECALL
8
8
STORE
DELAY
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
VCC Rise Time
20
25
25
V
t
2.65
2.65
2.65
SWITCH
150
150
150
μs
V
VCCRISE
V
HSB Output Driver Disable Voltage
HSB To Output Active Time
HSB High Active Time
1.9
5
1.9
5
1.9
5
HDIS
LZHSB
HHHD
t
t
μs
ns
500
500
500
Switching Waveforms
Figure 12. AutoStore or Power Up RECALL
VSWITCH
VHDIS
Note24
Note24
VVCCRISE
tSTORE
tSTORE
Note27
tHHHD
tHHHD
HSB OUT
Autostore
tDELAY
tLZHSB
tLZHSB
tDELAY
POWER-
UP
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(RWI)
Read & Write
Read & Write
POWER-UP
RECALL
BROWN
OUT
Autostore
POWER
DOWN
Autostore
POWER-UP
RECALL
Notes
23. t
starts from the time V rises above V
SWITCH.
HRECALL
CC
24. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
25. On a Hardware STORE, Software STORE / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t
.
DELAY
26. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V
SWITCH.
27. HSB pin is driven HIGH to VCC only by internal 100kOhm resistor, HSB driver is disabled.
Document #: 001-07103 Rev. *K
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PRELIMINARY
CY14B104K, CY14B104M
Software Controlled STORE and RECALL Cycle
In the following table, the software controlled STORE and RECALL cycle parameters are listed.
20 ns
25 ns
45 ns
Parameters
Description
Unit
Min
Max
Min
Max
Min
Max
t
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Address Setup Time
20
0
25
0
45
0
ns
ns
ns
ns
μs
μs
RC
SA
Clock Pulse Width
15
0
20
0
30
0
CW
Address Hold Time
HA
RECALL Duration
200
100
200
100
200
100
Soft Sequence Processing Time
SS
Switching Waveforms
Figure 13. CE and OE Controlled Software STORE and RECALL Cycle
tRC
tRC
Address
CE
Address #1
tCW
Address #6
tCW
tSA
tHA
tHA
tHA
tSA
tHA
OE
tDELAY
tHHHD
tHZCE
HSB (STORE only)
DQ (DATA)
tLZCE
tLZHSB
High Impedance
tSTORE/tRECALL
RWI
Figure 14. Autostore Enable and Disable Cycle
tRC
tRC
Address
Address #1
tCW
Address #6
tCW
tSA
CE
tSA
tHA
tHA
tHA
tHA
OE
tSS
tHZCE
tLZCE
tDELAY
DQ (DATA)
Notes
28. The software sequence is clocked with CE controlled or OE controlled reads.
29. The six consecutive addresses must be read in the order listed in Table 1. WE must be HIGH during all six consecutive cycles.
30. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
31. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
Document #: 001-07103 Rev. *K
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PRELIMINARY
CY14B104K, CY14B104M
Hardware STORE Cycle
20 ns
25 ns
45 ns
Parameters
Description
Unit
Min
Max
Min
Max
Min
Max
t
t
HSB To Output Active Time when write latch not set
Hardware STORE Pulse Width
20
25
25
ns
ns
DHSB
15
15
15
PHSB
Switching Waveforms
Figure 15. Hardware STORE Cycle
Write latch set
tPHSB
HSB (IN)
tSTORE
tHHHD
tDELAY
HSB (OUT)
DQ (Data Out)
RWI
tLZHSB
Write latch not set
tPHSB
HSB pin is driven high to VCC only by Internal
100kOhm resistor,
HSB (IN)
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
tDELAY
tDHSB
tDHSB
HSB (OUT)
RWI
Figure 16. Soft Sequence Processing
tSS
tSS
Soft Sequence
Command
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
Address #1
Address #6
tCW
CE
VCC
Notes
32. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
33. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
Document #: 001-07103 Rev. *K
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PRELIMINARY
CY14B104K, CY14B104M
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
For x8 Configuration
CE
H
L
WE
X
OE
X
Inputs and Outputs
Mode
Deselect/Power down
Power
Standby
Active
High Z
H
L
Data Out (DQ –DQ );
Read
0
7
L
H
H
High Z
Output Disabled
Write
Active
L
L
X
Data in (DQ –DQ );
Active
0
7
For x16 Configuration
CE
H
L
WE
X
OE
X
BHE
X
BLE
X
Inputs and Outputs
High-Z
High-Z
Data Out (DQ –DQ
Mode
Power
Standby
Deselect/Power down
Output Disabled
Read
X
X
H
H
Active
Active
Active
L
H
L
L
L
)
15
0
L
H
L
H
L
Data Out (DQ –DQ );
Read
0
7
DQ –DQ in High-Z
8
15
L
H
L
L
H
Data Out (DQ –DQ );
Read
Active
8
15
DQ –DQ in High-Z
0
7
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High-Z
Output Disabled
Output Disabled
Output Disabled
Write
Active
Active
Active
Active
Active
High-Z
High-Z
L
Data In (DQ –DQ
)
0
15
L
H
Data In (DQ –DQ );
Write
0
7
DQ –DQ in High-Z
8
15
L
L
X
L
H
Data In (DQ –DQ );
Write
Active
8
15
DQ –DQ in High-Z
0
7
Document #: 001-07103 Rev. *K
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PRELIMINARY
CY14B104K, CY14B104M
Part Numbering Nomenclature
CY14 B 104 K ZS P 20 X C T
Option:
T - Tape & Reel
Blank - Std.
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Speed:
20 - 20 ns
Pb-Free
25 - 25 ns
45 - 45 ns
P - 54 Pin
Blank - 44 Pin
Package:
ZS - TSOP II
Data Bus:
K - x8 + RTC
M - x16 + RTC
Density:
104 - 4 Mb
Voltage:
B - 3.0V
NVSRAM
14 - AutoStore + Software STORE + Hardware STORE
Cypress
Document #: 001-07103 Rev. *K
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PRELIMINARY
CY14B104K, CY14B104M
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
20
CY14B104K-ZS20XCT
CY14B104K-ZS20XC
CY14B104K-ZS20XIT
CY14B104K-ZS20XI
51-85087
51-85087
51-85087
51-85087
51-85160
51-85160
51-85160
51-85160
51-85087
51-85087
51-85087
51-85187
51-85160
51-85160
51-85160
51-85160
51-85087
51-85087
51-85087
51-85187
51-85160
51-85160
51-85160
51-85160
44-pin TSOPII
44-pin TSOPII
44-pin TSOPII
44-pin TSOPII
54-pin TSOPII
54-pin TSOPII
54-pin TSOPII
54-pin TSOPII
44-pin TSOPII
44-pin TSOPII
44-pin TSOPII
44-pin TSOPII
54-pin TSOPII
54-pin TSOPII
54-pin TSOPII
54-pin TSOPII
44-pin TSOPII
44-pin TSOPII
44-pin TSOPII
44-pin TSOPII
54-pin TSOPII
54-pin TSOPII
54-pin TSOPII
54-pin TSOPII
Commercial
Industrial
CY14B104M-ZSP20XCT
CY14B104M-ZSP20XC
CY14B104M-ZSP20XIT
CY14B104M-ZSP20XI
CY14B104K-ZS25XCT
CY14B104K-ZS25XC
CY14B104K-ZS25XIT
CY14B104K-ZS25XI
Commercial
Industrial
25
Commercial
Industrial
CY14B104M-ZSP25XCT
CY14B104M-ZSP25XC
CY14B104M-ZSP25XIT
CY14B104M-ZSP25XI
CY14B104K-ZS45XCT
CY14B104K-ZS45XC
CY14B104K-ZS45XIT
CY14B104K-ZS45XI
Commercial
Industrial
45
Commercial
Industrial
CY14B104M-ZSP45XCT
CY14B104M-ZSP45XC
CY14B104M-ZSP45XIT
CY14B104M-ZSP45XI
Commercial
Industrial
All parts are Pb-free. The above table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 001-07103 Rev. *K
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PRELIMINARY
CY14B104K, CY14B104M
Package Diagrams
Figure 17. 44-Pin TSOP II (51-85087)
DIMENSION IN MM (INCH)
MAX
MIN.
PIN 1 I.D.
22
1
R
O
E
K
A
X
S G
EJECTOR PIN
23
44
TOP VIEW
BOTTOM VIEW
10.262 (0.404)
10.058 (0.396)
0.400(0.016)
0.300 (0.012)
0.800 BSC
(0.0315)
BASE PLANE
0.10 (.004)
0.210 (0.0083)
0.120 (0.0047)
0°-5°
18.517 (0.729)
18.313 (0.721)
0.597 (0.0235)
0.406 (0.0160)
SEATING
PLANE
51-85087 *A
Document #: 001-07103 Rev. *K
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PRELIMINARY
CY14B104K, CY14B104M
Package Diagrams (continued)
Figure 18. 54-Pin TSOP II (51-85160)
51-85160 **
Document #: 001-07103 Rev. *K
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PRELIMINARY
CY14B104K, CY14B104M
Document History Page
Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock
Document Number: 001-07103
Submission
Date
Orig. of
Change
Rev. ECN No.
Description of Change
**
431039
489096
See ECN
See ECN
TUP
TUP
New Data Sheet
*A
Removed 48 SSOP Package
Added 44 TSOPII and 54 TSOPII Packages
Updated Part Numbering Nomenclature and Ordering Information
Added Soft Sequence Processing Time Waveform
Added RTC Characteristics Table
Added RTC Recommended Component Configuration
*B
499597
See ECN
PCI
Removed 35ns speed bin
Added 55ns speed bin. Updated AC table for the same
Changed “Unlimited” read/write to “infinite” read/write
Features section: Changed typical I at 200-ns cycle time to 8 mA
CC
Changed STORE cycles from 500K to 200K cycles.
Shaded Commercial grade in operating range table.
Modified Icc/Isb specs.
Changed V
value in DC table
CAP
Added 44 TSOP II in Thermal Resistance table
Modified part nomenclature table. Changes reflected in the ordering information
table.
*C
517793
See ECN
TUP
Removed 55ns speed bin
Changed pinout for 44TSOPII and 54TSOPII packages
Changed I to 1mA
SB
Changed I
to 3mA
CC4
Changed V
Changed V max to Vcc + 0.5V
min to 35μF
CAP
IH
Changed t
Changed t
Changed t
to 15ns
to 10ns
to 15ns
STORE
PWE
SCE
Changed t to 5ns
SD
Changed t
to 10ns
AW
Removed t
HLBL
Added Timing Parameters for BHE and BLE - t
Removed min. specification for Vswitch
, t
, t
, t
DBE LZBE HZBE BW
Changed t
to 1ns
max. of 70us
GLAX
Added t
DELAY
Changed t specification from 70us min. to 70us max.
SS
*D
*E
825240
914280
See ECN
See ECN
UHA
UHA
Changed the data sheet from Advance information to Preliminary
Changed t
Changed t
Changed t
Changed t
Changed the value of I
Changed the value of t
to 10ns in 15ns part
DBE
in 15ns part to 7ns and in 25ns part to10ns
HZBE
in 15ns part to 15ns and in 25ns part to 20ns
BW
to t
GLAX
GHAX
to 25mA
in 15ns part to 15ns
CC3
AW
Changed the figure-14 title from 54-Pb to 54 Pin
Included all the information for 45ns part in this data sheet
Document #: 001-07103 Rev. *K
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PRELIMINARY
CY14B104K, CY14B104M
Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock
Document Number: 001-07103
Submission
Date
Orig. of
Change
Rev. ECN No.
Description of Change
*F
1890926
See ECN
vsutmp8/AE- Added Footnote 1, 2 and 3.
SA
Updated Logic Block diagram
Updated Pin definition Table
Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8)
package.
Corrected typo in V min spec
IL
Changed the value of I
from 25mA to 13mA
CC3
Changed I value from 1mA to 2mA
SB
Updated ordering information table
Rearranging of Footnotes.
Changed Package diagrams title.
The pins X1 and X2 interchanged in 44TSOP II(x8) and 54TSOP II(x16) pinout
diagram.
*G
2267286
See ECN
GVCH/PYRS Rearranging of “Features”
Added BHE and BLE Information in Pin Definitions Table
Updated Figure 2 (Autostore mode)
Updated footnote 6
RTC Register Map:Register 0x1FFF6:Changed D4 from ABE to 0
Register Map Detail:0x1FFF6:Changed D4 from ABE to 0 and removed ABE
information
Changed I
Changed I
& I
from 3mA to 6mA
CC2
CC3
CC4
from 13mA to 15mA
Changed I from 2mA to 3mA
SB
Added input leakage current (I ) for HSB in DC Electrical Characteristics table
IX
Changed Vcap from 35uF min and 57uF max value to 54uF min and 82uF max
value
Corrected typo in t
Corrected typo in t
Corrected typo in t
value from 22ns to 20ns for 45ns part
DBE
value from 22ns to 15ns for 45ns part
HZBE
value from 15ns to 10ns for 15ns part
AW
Changed Vrtccap max from 2.7V to 3.6V
Changed tRECALL from 100 to 200us
Added footnote 10, 29
Reframed footnote 18, 25
Added footnote 18 to figure 8 (SRAM WRITE Cycle #1)
Added footnote 18, 26 and 27 to figure 9 (SRAM WRITE Cycle #2)
*H
2483627
See ECN
GVCH/PYRS Removed 8 mA typical I at 200 ns cycle time in Feature section
CC
Referenced footnote 9 to I
in DC Characteristics table
CC3
Changed I
from 15 mA to 35 mA
CC3
Changed Vcap minimum value from 54 uF to 61 uF
Changed t to t
AVAV
RC
Changed V
minimum value from 1.2V to 1.5V
RTCcap
Figure 12:Changed t to t and t
t
SA
AS
SCE to CW
Document #: 001-07103 Rev. *K
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PRELIMINARY
CY14B104K, CY14B104M
Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock
Document Number: 001-07103
Submission
Date
Orig. of
Change
Rev. ECN No.
Description of Change
*I
2519319
06/20/08
GVCH/PYRS Added 20 ns access speed in “Features”
Added I for tRC=20 ns for both industrial and Commercial temperature Grade
CC1
Updated Thermal resistance values for 44-TSOP II and 54-TSOP II packages
Added AC Switching Characteristics specs for 20 ns access speed
Added Software controlled STORE/RECALL cycle specs for 20 ns access speed
Updated ordering information and Part numbering nomenclature
*J
2600941
11/04/08
GVCH/PYRS Removed 15 ns access speed from “Features”
Changed part number from CY14B104K/CY14B104M to
CY14B104KA/CY14B104MA
Updated Logic block diagram
Updated footnote 1
Added footnote 2
Pin definition: Updated WE, HSB and NC pin description
Page 4: Updated SRAM READ, SRAM WRITE, Autostore operation description
Page 4: Updated Hardware store operation and Hardware RECALL (Power up)
description
Footnote 1 and 8 referenced for Mode selection Table
Updated footnote 6
Page 6: updated Data protection description
Page 6: Updated Starting and stopping the oscillator description
Page 7: Updated Calibrating the clock description
Page 7: Updated Alarm description
Page 8: Added Flags register
Added footnote 10 and 11
Updated Figure 4: Removed RF register and Changed C value from 56pF to
2
12pF
Updated Register Map Table 3
Updated Register map detail Table 4
Maximum Ratings: Added Max. Accumulated storage time
Changed Output short circuit current parameter name to DC output current
Changed I
Changed I
from 6mA to 10mA
from 6mA to 5mA
CC2
CC4
Changed I from 3mA to 5mA
SB
Updated I
I
I
and I Test conditions
CC1, CC3, SB
OZ
Changed V
voltage max value from 82uF to 180uF
CAP
Updated footnote 12 and 13
Added footnote 14
Added Data retention and Endurance Table
Updated Input Rise and Fall time in AC test Conditions
Changed tOCS value for minimum temperature from 10 to 2 sec
updated tOCS value for room temperature from 5 to 1sec
Referenced footnote 20 to t
parameter
OHA
Updated All switching waveforms
Updated footnote 20
Added Figure 11 (SRAM WRITE CYCLE:BHE and BLE controlled)
Updated t
value
DELAY
Added V
, t
and t
parameters
HDIS HHHD
LZHSB
Updated footnote 27
Added footnote 29
Software controlled STORE/RECALL Table: Changed t to t
AS
SA
Changed t
to t
GHAX
HA
Changed t value from 1ns to 1ns
HA
Added t
parameter
DHSB
Changed t
to t
HLHX
PHSB
Updated t from 70us to 100us
SS
Added truth table for SRAM operations
Updated ordering information and part numbering nomenclature
Document #: 001-07103 Rev. *K
Page 30 of 31
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PRELIMINARY
CY14B104K, CY14B104M
Document Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256K x 16) nvSRAM with Real Time Clock
Document Number: 001-07103
Submission
Date
Orig. of
Change
Rev. ECN No.
*K 2653928
Description of Change
02/04/09
GVCH/PYRS Changed Part number from CY14B104KA/CY14B104MA to
CY14B104K/CY14B104M
Updated Real Time Clock operation description
Added factory default values to register map table 3
Added footnote 9
Updated Flag register description in Table 4
Updated C1, C2 values to 21uF, 21uF respectively
Changed I
Changed V
value from 350 nA to 450 nA at hot temperature
BAK
typical value from 2.4V to 3.0V
RTCcap
Referenced Note 15 to parameters t
, t
, t
t
t
t
t
LZCE HZCE LZOE, HZOE, LZBE, LZWE, HZWE-
and t
HZBE
Added footnote 22
Updated Figure 13
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Document #: 001-07103 Rev. *K
Revised January 29, 2009
Page 31 of 31
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