FreeForm/Express S6
PCIe Spartan-6 FMC Carrier
User Manual
Connect Tech Inc.
42 Arrow Road
Guelph, Ontario
N1K 1S6
Tel:
519-836-1291
Toll:
Fax:
800-426-8979 (North America only)
519-836-4878
Email: [email protected]
Web: www.connecttech.com
CTIM-00060 | Revision 0.01 | 2011/06/27
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Customer Support Overview
If you experience difficulties after reading the manual and/or using the product, contact the
Connect Tech reseller from which you purchased the product. In most cases the reseller can help
you with product installation and difficulties.
In the event that the reseller is unable to resolve your problem, our highly qualified support staff
can assist you. Our support section is available 24 hours a day, 7 days a week on our website at:
www.connecttech.com/sub/support/support.asp. See the contact information section below for
more information on how to contact us directly. Our technical support is always free.
Contact Information
We offer three ways for you to contact us:
Mail/Courier
You may contact us by letter at:
Connect Tech Inc.
Technical Support
42 Arrow Road
Guelph, Ontario
Canada N1K 1S6
Email/Internet
You may contact us through the Internet. Our email and URL addresses on the Internet are:
Note:
Tech website for product manuals, installation guides, device driver software and technical tips.
on the Connect Tech website.
Telephone/Facsimile
Technical Support representatives are ready to answer your call Monday through Friday, from
8:30 a.m. to 5:00 p.m. Eastern Standard Time. Our numbers for calls are:
Toll Free: 800-426-8979 (North America only)
Telephone: 519-836-1291 (Live assistance available 8:30 a.m. to 5:00 p.m. EST,
Monday to Friday)
Facsimile: 519-836-4878 (on-line 24 hours)
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Limited Lifetime Warranty
Connect Tech Inc. provides a Lifetime Warranty for all Connect Tech Inc. products. Should this
product, in Connect Tech Inc.'s opinion, fail to be in good working order during the warranty
period, Connect Tech Inc. will, at its option, repair or replace this product at no charge, provided
that the product has not been subjected to abuse, misuse, accident, disaster or non-Connect Tech
Inc. authorized modification or repair.
You may obtain warranty service by delivering this product to an authorized Connect Tech Inc.
business partner or to Connect Tech Inc. along with proof of purchase. Product returned to
Connect Tech Inc. must be pre-authorized by Connect Tech Inc. with an RMA (Return Material
Authorization) number marked on the outside of the package and sent prepaid, insured and
packaged for safe shipment. Connect Tech Inc. will return this product by prepaid ground
shipment service.
The Connect Tech Inc. Lifetime Warranty is defined as the serviceable life of the product. This is
defined as the period during which all components are available. Should the product prove to be
irreparable, Connect Tech Inc. reserves the right to substitute an equivalent product if available or
to retract Lifetime Warranty if no replacement is available.
The above warranty is the only warranty authorized by Connect Tech Inc. Under no
circumstances will Connect Tech Inc. be liable in any way for any damages, including any lost
profits, lost savings or other incidental or consequential damages arising out of the use of, or
inability to use, such product.
Copyright Notice
The information contained in this document is subject to change without notice. Connect Tech
Inc. shall not be liable for errors contained herein or for incidental consequential damages in
connection with the furnishing, performance, or use of this material. This document contains
proprietary information that is protected by copyright. All rights are reserved. No part of this
document may be photocopied, reproduced, or translated to another language without the prior
written consent of Connect Tech Inc.
Copyright 1997 - 2011 by Connect Tech Inc.
Trademark Acknowledgment
Connect Tech Inc. acknowledges all trademarks, registered trademarks and/or copyrights referred
to in this document as the property of their respective owners.
Not listing all possible trademarks or copyright acknowledgments does not constitute a lack of
acknowledgment to the rightful owners of the trademarks and copyrights mentioned in this
document.
Revision History
Revision 0.00e – 2011/01/26
Revision 0.00f – 2011/03/28
Revision 0.00g – 2011/06/27
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Connect Tech Inc. | FreeForm/Express S6 - PCIe Spartan-6 FMC Carrier | User Manual
Introduction
Connect Tech’s FreeForm/Express S6 is a reconfigurable computing platform that is based on the
Xilinx Spartan-6 FPGA; featuring integrated PCI Express® blocks, advanced memory support,
and 3.125 Gbps low-power transceivers. The FreeForm/Express S6 includes an industry-standard
FPGA Mezzanine Card (FMC) connector, which provides a flexible I/O interface for future
scaling and customization. The PCIe bus bandwidth ensures high speed communication between
the host system and the application’s interfaces.
A wide range of available FMC modules adds interfaces such as ADC and digital video, which
makes the FreeForm/Express S6 a highly versatile platform for system development. It is ideally
suited for applications requiring both prototyping and field deployment including real-time data
acquisition, high performance video processing, and software defined radio. The
FreeForm/Express S6 is optimized for embedded processor designs, supporting development with
Xilinx’s MicroBlaze.
Features
Spartan-6 LX45T FPGA
PCIe x1 form factor
128MB DDR3 Memory
Low Pin Count FMC connector
o
o
o
36 LVDS pairs
1 Rocket I/O channel
I2C interface
2x 10/100/1000 Ethernet ports
1x RS-232 port
4 MB Flash for FPGA configuration
2 MB Flash for embedded code storage
200 MHz oscillator
JTAG debugging
Industrial temperature (-40 to 85C)
Lifetime warranty and free technical support.
What is an FPGA Mezzanine Card (FMC)?
An FPGA Mezzanine Card (FMC) is a standard created by VITA (VMEbus International Trade
Association). The FMC standard (VITA 57.1) defines a module size and connector interface with
generic reconfigurable I/O, making it perfect for FPGA daughter board applications. The standard
defines two pin-outs, low pin count (LPC) and high pin count (HPC); with each type using the
same connector form factor.
For more information visit http://www.vita.com/fmc.html.
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System Block Diagram
The following block diagram depicts component and connector interconnect, along with the appropriate
bus definitions.
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Hardware Description
FPGA
Description
The FreeForm/Express S6 features the Xilinx Spartan-6 LX45T FPGA in a 484 pin BGA package
(Xilinx XC6SLX45T-2FGG484I). The Spartan-6 simplifies FPGA design by providing a
integrated memory controller and PCI express end point, along with high performance general I/O,
clocking, and internal memory resources comparable to be previous generation Virtex-class
FPGAs.
For more details on the Spartan-6 capabilities, visit:
PCI Express Bus
Description
The FreeForm/Express S6 has a single x1 PCIe express lane, connected directly to the Spartan-6
FPGA. The PCIe interface is facilitated by the Spartan-6’s integrated PCI express endpoint.
Memory & Flash
Description
A single 1024 Mbit x16 DDR3 component (Micron MT41J64M16JT-15E) is connected to the
Spartan-6 FPGA, providing 128 MB of high speed memory. The Spartan-6’s integrated memory
controller provides a generic high speed interface to FPGA logic.
In addition, a 16 Mbit SPI flash component (Numonyx M25P16) is connected to the FPGA’s user
I/O for storage of embedded processor code.
Low Pin Count FMC Interface
Description
The FreeForm/Express S6 provides a single Low Pin Count FPGA Mezzanine Card (FMC) Interface.
The LPC connector provides the following features
36 LVDS pairs, 2 designated as global clocks (or 68 2.5V LVCMOS pairs)
I2C interface
1 SERDES TX / RX channel (Rocket I/O , GTP), with clock
Power : +12VDC, +3.3V DC, +2.5V DC
The FreeForm/Express S6 LPC implementation differs from the VITA 57.1 specification as follows:
VADJ is fixed to +2.5 V DC
Only LVDS or 2.5V LVCMOS I/O is supported.
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Connector
Function LPC FMC
P7
Location
Type
Samtec ASP-134603-01
Pinout
Pin
Signal
Description
Digital Ground
C1
C2
C3
C4
C5
C6
C7
C8
C9
GND
DP0_C2M_P
DP0_C2M_N
GND
Serdes pair from FPGA
Serdes pair from FPGA
Digital Ground
Digital Ground
Serdes pair to FPGA
Serdes pair to FPGA
Digital Ground
Digital Ground
LVDS pair
GND
DP0_M2C_P
DP0_M2C_N
GND
GND
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
LA06_P
LA06_N
GND
LVDS pair
Digital Ground
Digital Ground
LVDS pair
GND
LA10_P
LA10_N
GND
LVDS pair
Digital Ground
Digital Ground
LVDS pair
GND
LA14_P
LA14_N
GND
LVDS pair
Digital Ground
Digital Ground
LVDS clock capable pair
LVDS clock capable pair
Digital Ground
Digital Ground
LVDS pair
GND
LA18_P_CC
LA18_N_CC
GND
GND
LA27_P
LA27_N
GND
LVDS pair
Digital Ground
Digital Ground
I2C clock
GND
SCL
SDA
I2C data
GND
Digital Ground
Digital Ground
I2C address
GND
GA0
12P0V
+12V DC
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C36
C37
C38
C39
C40
D1
GND
Digital Ground
+12V DC
12P0V
GND
Digital Ground
+3.3V DC
3P3V
GND
Digital Ground
Power good
Digital Ground
Digital Ground
Serdes clock to FPGA
Serdes clock to FPGA
Digital Ground
Digital Ground
LVDS clock capable pair
LVDS clock capable pair
Digital Ground
LVDS pair
PG_C2M
GND
D2
D3
GND
D4
GBTCLK0_M2C_P
GBTCLK0_M2C_N
GND
D5
D6
D7
GND
D8
LA01_P_CC
LA01_N_CC
GND
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
LA05_P
LA05_N
GND
LVDS pair
Digital Ground
LVDS pair
LA09_P
LA09_N
GND
LVDS pair
Digital Ground
LVDS pair
LA13_P
LA13_N
GND
LVDS pair
Digital Ground
LVDS clock capable pair
LVDS clock capable pair
Digital Ground
LVDS pair
LA17_P_CC
LA17_N_CC
GND
LA23_P
LA23_N
GND
LVDS pair
Digital Ground
LVDS pair
LA26_P
LA26_N
GND
LVDS pair
Digital Ground
JTAG
TCK
TDI
JTAG
TDO
JTAG
3P3VAUX
TMS
+3.3V DC
JTAG
TRST_L
GA1
JTAG
I2C address
+3.3V DC
3P3V
GND
Digital Ground
+3.3V DC
3P3V
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D39
D40
G1
GND
Digital Ground
+3.3V DC
3P3V
GND
Digital Ground
LVDS clock to FPGA
LVDS clock to FPGA
Digital Ground
Digital Ground
LVDS clock capable pair
LVDS clock capable pair
Digital Ground
LVDS pair
G2
CLK1_M2C_P
CLK1_M2C_N
GND
G3
G4
G5
GND
G6
LA00_P_CC
LA00_N_CC
GND
G7
G8
G9
LA03_P
LA03_N
GND
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
G31
G32
G33
G34
G35
G36
G37
G38
G39
G40
H1
LVDS pair
Digital Ground
LVDS pair
LA08_P
LA08_N
GND
LVDS pair
Digital Ground
LVDS pair
LA12_P
LA12_N
GND
LVDS pair
Digital Ground
LVDS pair
LA16_P
LA16_N
GND
LVDS pair
Digital Ground
LVDS pair
LA20_P
LA20_N
GND
LVDS pair
Digital Ground
LVDS pair
LA22_P
LA22_N
GND
LVDS pair
Digital Ground
LVDS pair
LA25_P
LA25_N
GND
LVDS pair
Digital Ground
LVDS pair
LA29_P
LA29_N
GND
LVDS pair
Digital Ground
LVDS pair
LA31_P
LA31_N
GND
LVDS pair
Digital Ground
LVDS pair
LA33_P
LA33_N
GND
LVDS pair
Digital Ground
+2.5V DC
VADJ
GND
Digital Ground
Not used
VREF_A_M2C
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H2
PRSNT_M2C_L
GND
Present signal to FPGA
Digital Ground
LVDS clock to FPGA
LVDS clock to FPGA
Digital Ground
LVDS pair
H3
H4
CLK0_M2C_P
CLK0_M2C_N
GND
H5
H6
H7
LA02_P
LA02_N
GND
H8
LVDS pair
H9
Digital Ground
LVDS pair
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
H32
H33
H34
H35
H36
H37
H38
H39
H40
LA04_P
LA04_N
GND
LVDS pair
Digital Ground
LVDS pair
LA07_P
LA07_N
GND
LVDS pair
Digital Ground
LVDS pair
LA11_P
LA11_N
GND
LVDS pair
Digital Ground
LVDS pair
LA15_P
LA15_N
GND
LVDS pair
Digital Ground
LVDS pair
LA19_P
LA19_N
GND
LVDS pair
Digital Ground
LVDS pair
LA21_P
LA21_N
GND
LVDS pair
Digital Ground
LVDS pair
LA24_P
LA24_N
GND
LVDS pair
Digital Ground
LVDS pair
LA28_P
LA28_N
GND
LVDS pair
Digital Ground
LVDS pair
LA30_P
LA30_N
GND
LVDS pair
Digital Ground
LVDS pair
LA32_P
LA32_N
GND
LVDS pair
Digital Ground
+2.5V DC
VADJ
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Configuration
The FreeForm/Express S6 is designed so that the Spartan-6 configuration image is automatically loaded
from the on-board SPI flash at power- up. When a valid configuration is loaded, led D4 is illuminated.
JTAG configuration can be used at any time to program the FPGA.
The FreeForm/Express S6 is fitted with a x4 32 Mbit SPI flash (Winbond W25Q32BVSFIG), which can be
programmed indirectly via JTAG using Xilinx’s IMPACT.
Function JTAG programming
P5
Location
Type
1x7 0.100” header
Samtec TSW-107-08-F-S-RA
Pinout
Pin
Signal
Description
1
TRST#
Reset, not used by Xilinx
products
2
3
4
5
6
7
TMS
TDI
Select
Data In
TDO
TCK
GND
VCC
Data Out
Clock
Digital Ground
Chain power, 3.3V
Function Manual Reset
Pulls the Spartan-6 PROG_B pin to ground, resetting and
reconfiguring the FPGA
J1
Location
Type
1x2 0.100” jumper block
Pinout
Position
1-2
Description
+5V
off
floating
Default
Floating
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Function Hot Swap
When the is being configured, FPGA I/Os will be pulled
high with weak internal pull-ups
J2
Location
Type
1x2 0.100” jumper block
Pinout
Position
1-2
Description
I/Os have pullups
I/Os are floating
off
Default
Floating
Function FMC JTAG Bypass
Selects either whether or not to include the FMC module
in the JTA chain
J3
Location
Type
2x2 0.100” jumper block
Pinout
Position
1-3
Description
TDI to FMC
TDO from FMC
Bypass
2-4
3-4
off
Not applicable
Default
Bypass
Ethernet
Description
Two 10/100/1000 Ethernet ports are connected to the FPGA, via two separate RGMII capable Ethernet
physical layer devices (PHYs). The FPGA logic resources are used to implement the Ethernet media
access controller (MAC).
Connector & LEDs
Function Ethernet
P6A, P6B
Location
Type
2x5 2mm header
MLE TSHSM-205-D-06-G-V-L (or equivalent)
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Pinout
Pin Signal Description Pin Signal Description
1
3
5
MX1-
MX2-
FGND
Data
Data
2
4
6
MX1+
MX2+
FGND
Data
Data
Frame
Frame
Ground
Ground
7
9
MX3-
MX4-
Data
Data
8
MX3+
MX4+
Data
Data
10
Function Ethernet Status LEDs
Locations
Pin
Signal
D16A ETH0 Activity
D17A ETH0 Link
D16B ETH1 Activity
D17B ETH1 Link
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Serial
Description
A standard RS232 serial ports is provided on P4, with UART implementation provided by FPGA logic.
Connectors
Function RS232
P4
Locations
Type
2x5 0.100” header
Samtec TSW-105-07-L-D
Pinout
Pin
1
Signal
N/C
Pin
2
Signal
N/C
3
RXD1
TXD1
N/C
4
RTS1
CTS1
N/C
5
6
7
8
9
GND
10
N/C
Power
Description
The FreeForm/Express S6 is designed to be powered from the PCIe bus. The board requires +3.3V DC for
all circuitry. +12VDC is required for the FMC power good signal and as the FMC module’s power source.
The FreeForm/Express S6 generates all other required power rails on-board.
In addition, a programming / desktop debugging standalone power connector P1 is provided.
WARNING: Do not plug the FreeForm/Express S6 into a PCIe slot with an external power source
connected to P1. This could lead to board damage and void the product warranty.
Connectors & Jumpers
Function Standalone power
P1
Location
Type
2x3 0.100” power header, shrouded
Samtec IPL1-103-01-L-D-RA-K
Pinout
Pin
1
Signal
GND
Description
Digital Ground
Digital Ground
Digital Ground
2
GND
3
GND
4
+3.3V
+3.3V DC, used by circuitry and
power regulators
5
6
+3.3V
+12V
+3.3V DC, used by circuitry and
power regulators
+12V DC used by FMC module,
and power good circuit
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Hardware Installation
Standard computer
1. Ensure all computer power supplies are off and disconnected (remove AC line cord)
2. Install the FMC module, if required.
3. Verify all jumper settings from the relevant sections
4. Install the necessary cables for the application.
WARNING: Do not plug the FreeForm/Express S6 into a PCIe slot with an external power source
connected to P1. This could lead to board damage and void the product warranty.
5. Install the FreeForm/Express S6 module into x1 PCIe slot.
6. Connect the appropriate interface cables to the FMC bracket I/O.
7. Connect the computer’s AC line cord to the computer’s power supply.
8. Turn on the computer system.
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Cables & Interconnect
Mating Cables
Description
Location
PCB Connector
Cable Part Number
[Drawing Number]
PCB End
2x3 IPD
Interface End
Un-terminated
DB-9
Power
P1
Samtec
IPL1-103-01-L-D-RA-K
Samtec
MMSD-03-20-L-03.25-S-K
Serial
P4
Samtec
TSW-105-07-L-D
CAG104
[ CTIC-00048 ]
2x5 0.100” IDC
2x5 2mm socket
GBE
P6A, P6B
MLE
CBG065
RJ45 socket
TSHSM-205-D-06-G-V-L
[CTIC-00181 ]
Cable drawings are available upon request
Mating Connectors
Description
Location
PCB Connector
Mating Connector
Note
FMC
P7
Samtec ASP-134603-01
Samtec
ASP-134604-01
10 mm stack
8.5 mm stack
Samtec
ASP-134606-01
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FPGA Design
In general, FPGA designs developed for the FreeForm/Express S6 can be based on IP generated with
Xilinx’s CORE Generator. The following table lists the CORE Generator IP proven to be compatible,
along with their current versions numbers.
Function
IP
Version
Note
Memory
MIG
3.6
1.7
Spartan-6 FPGA GTP
Transceiver Wizard
Rocket I/O
Spartan-6 Integrated
Block for PCI Express
PCIe
1.4
4.4
A valid license is required to use this IP, contact Xilinx
for details
Ethernet
Tri Mode Ethernet MAC
For the latest reference designs developed by Connect Tech Inc., visit http://devel.connecttech.com
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FPGA Pinout
The following table lists the FPGA pin (ball) to signal mapping. The standard Spartan-6 pin name is listed,
along with the I/O standard used and bank number.
Pin Number
V20
Y20
AB20
AA3
AA20
R13
T14
AA6
AB6
Y5
Signal Name
Pin Name
IO_L74N_DOUT_BUSY_1
IO_L1P_CCLK_2
IO Standard
LVCMOS25*
Bank
cfg_busy
cfg_cclk
1
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
SSTL15_II
2
2
2
2
2
2
2
2
2
2
2
0
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
cfg_csi_b_mosi_miso0
cfg_cso_b_csn
cfg_d0_miso1
cfg_d1_miso2
cfg_d2_miso3
cfg_d3
IO_L3N_MOSI_CSI_B_MISO0_2
IO_L65N_CSO_B_2
IO_L3P_D0_DIN_MISO_MISO1_2
IO_L12P_D1_MISO2_2
IO_L12N_D2_MISO3_2
IO_L49P_D3_2
cfg_d4
IO_L49N_D4_2
cfg_d5
IO_L62P_D5_2
AB5
W9
C3
cfg_d6
IO_L62N_D6_2
cfg_d7
IO_L48P_D7_2
cfg_hswapen
cfg_init_b
IO_L1P_HSWAPEN_0
IO_L65P_INIT_B_2
Y4
AA21
Y8
cfg_m0
IO_L1N_M0_CMPMISO_2
IO_L48N_RDWR_B_VREF_2
IO_L47P_M3A0_3
cfg_rdwr_b
ddr3_a<0>
ddr3_a<1>
ddr3_a<2>
ddr3_a<3>
ddr3_a<4>
ddr3_a<5>
ddr3_a<6>
ddr3_a<7>
ddr3_a<8>
ddr3_a<9>
ddr3_a<10>
ddr3_a<11>
ddr3_a<12>
ddr3_a<13>
ddr3_a<14>
ddr3_ba<0>
ddr3_ba<1>
ddr3_ba<2>
ddr3_cas_n
ddr3_ck_n
K2
K1
IO_L47N_M3A1_3
SSTL15_II
K5
IO_L49N_M3A2_3
SSTL15_II
M6
IO_L45P_M3A3_3
SSTL15_II
H3
IO_L51N_M3A4_3
SSTL15_II
M3
IO_L44P_GCLK21_M3A5_3
IO_L44N_GCLK20_M3A6_3
IO_L49P_M3A7_3
SSTL15_II
L4
SSTL15_II
K6
SSTL15_II
G3
IO_L52P_M3A8_3
SSTL15_II
G1
IO_L52N_M3A9_3
SSTL15_II
J4
IO_L51P_M3A10_3
SSTL15_II
E1
IO_L54N_M3A11_3
SSTL15_II
F1
IO_L53N_M3A12_3
SSTL15_II
J6
IO_L55P_M3A13_3
SSTL15_II
H5
IO_L55N_M3A14_3
SSTL15_II
J3
IO_L48P_M3BA0_3
IO_L48N_M3BA1_3
IO_L50N_M3BA2_3
IO_L43N_GCLK22_IRDY2_M3CASN_3
IO_L46N_M3CLKN_3
SSTL15_II
J1
SSTL15_II
H1
SSTL15_II
M4
SSTL15_II
K3
DIFF_SSTL15_II
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Pin Number
K4
Signal Name
Pin Name
IO_L46P_M3CLK_3
IO Standard
DIFF_SSTL15_II
SSTL15_II
SSTL15_II
SSTL15_II
SSTL15_II
SSTL15_II
SSTL15_II
SSTL15_II
SSTL15_II
SSTL15_II
SSTL15_II
SSTL15_II
SSTL15_II
SSTL15_II
SSTL15_II
SSTL15_II
SSTL15_II
SSTL15_II
SSTL15_II
DIFF_SSTL15_II
DIFF_SSTL15_II
SSTL15_II
SSTL15_II
LVCMOS15
SSTL15_II
DIFF_SSTL15_II
DIFF_SSTL15_II
SSTL15_II
LVDS_25
Bank
ddr3_ck_p
ddr3_cke
ddr3_dm
3
F2
IO_L53P_M3CKE_3
IO_L42N_GCLK24_M3LDM_3
IO_L37P_M3DQ0_3
IO_L37N_M3DQ1_3
IO_L38P_M3DQ2_3
IO_L38N_M3DQ3_3
IO_L41P_GCLK27_M3DQ4_3
IO_L41N_GCLK26_M3DQ5_3
IO_L40P_M3DQ6_3
IO_L40N_M3DQ7_3
IO_L36P_M3DQ8_3
IO_L36N_M3DQ9_3
IO_L35P_M3DQ10_3
IO_L35N_M3DQ11_3
IO_L33P_M3DQ12_3
IO_L33N_M3DQ13_3
IO_L32P_M3DQ14_3
IO_L32N_M3DQ15_3
IO_L39N_M3LDQSN_3
IO_L39P_M3LDQS_3
IO_L45N_M3ODT_3
IO_L43P_GCLK23_M3RASN_3
IO_L54P_M3RESET_3
IO_L42P_GCLK25_TRDY2_M3UDM_3
IO_L34N_M3UDQSN_3
IO_L34P_M3UDQS_3
IO_L50P_M3WE_3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
0
0
0
0
N4
R3
ddr3_dq<0>
R1
ddr3_dq<1>
P2
ddr3_dq<2>
P1
ddr3_dq<3>
L3
ddr3_dq<4>
L1
ddr3_dq<5>
M2
M1
T2
ddr3_dq<6>
ddr3_dq<7>
ddr3_dq<8>
T1
ddr3_dq<9>
U3
ddr3_dq<10>
ddr3_dq<11>
ddr3_dq<12>
ddr3_dq<13>
ddr3_dq<14>
ddr3_dq<15>
ddr3_dqs_n
U1
W3
W1
Y2
Y1
N1
N3
ddr3_dqs_p
L6
ddr3_odt
M5
E3
ddr3_ras_n
ddr3_reset_n
ddr3_udm
P3
V1
ddr3_udqs_n
ddr3_udqs_p
ddr3_we_n
V2
H2
G11
H12
F16
E16
A8
fmc_clk0_m2c_n
fmc_clk0_m2c_p
fmc_clk1_m2c_n
fmc_clk1_m2c_p
fmc_dp0_c2m_n
fmc_dp0_c2m_p
fmc_dp0_m2c_n
fmc_dp0_m2c_p
fmc_gbtclk0_m2c_n
fmc_gbtclk0_m2c_p
fmc_i2c_scl
IO_L35N_GCLK16_0
IO_L35P_GCLK17_0
IO_L37N_GCLK12_0
IO_L37P_GCLK13_0
MGTTXN1_101
LVDS_25
LVDS_25
LVDS_25
B8
MGTTXP1_101
C9
MGTRXN1_101
D9
MGTRXP1_101
D11
C11
T5
MGTREFCLK1N_101
MGTREFCLK1P_101
IO_L7N_3
LVCMOS15
LVCMOS15
3
3
T6
fmc_i2c_sda
IO_L7P_3
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Pin Number
AB11
Y11
AB12
AA12
AB4
AA4
AB7
Y7
Signal Name
fmc_la00_cc_n
Pin Name
IO_L32N_GCLK28_2
IO Standard
LVDS_25
Bank
2
fmc_la00_cc_p
fmc_la01_cc_n
fmc_la01_cc_p
fmc_la02_n
fmc_la02_p
fmc_la03_n
fmc_la03_p
fmc_la04_n
fmc_la04_p
fmc_la05_n
fmc_la05_p
fmc_la06_n
fmc_la06_p
fmc_la07_n
fmc_la07_p
fmc_la08_n
fmc_la08_p
fmc_la09_n
fmc_la09_p
fmc_la10_n
fmc_la10_p
fmc_la11_n
fmc_la11_p
fmc_la12_n
fmc_la12_p
fmc_la13_n
fmc_la13_p
fmc_la14_n
fmc_la14_p
fmc_la15_n
fmc_la15_p
fmc_la16_n
fmc_la16_p
fmc_la17_cc_n
fmc_la17_cc_p
fmc_la18_cc_n
fmc_la18_cc_p
fmc_la19_n
fmc_la19_p
IO_L32P_GCLK29_2
IO_L31N_GCLK30_D15_2
IO_L31P_GCLK31_D14_2
IO_L63N_2
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L63P_2
IO_L47N_2
IO_L47P_2
R8
IO_L59N_2
R9
IO_L59P_2
U6
IO_L64N_D9_2
IO_L64P_D8_2
IO_L60N_2
T7
Y6
W6
IO_L60P_2
AB9
Y9
IO_L43N_2
IO_L43P_2
AB8
AA8
U8
IO_L45N_2
IO_L45P_2
IO_L57N_2
T8
IO_L57P_2
W8
IO_L58N_2
V7
IO_L58P_2
AB10
AA10
V9
IO_L41N_VREF_2
IO_L41P_2
IO_L50N_2
U9
IO_L50P_2
Y10
W10
W11
V11
Y12
W12
U10
T10
U12
T12
AB13
Y13
U13
U14
IO_L44N_2
IO_L44P_2
IO_L42N_2
IO_L42P_2
IO_L40N_2
IO_L40P_2
IO_L46N_2
IO_L46P_2
IO_L29N_GCLK2_2
IO_L29P_GCLK3_2
IO_L30N_GCLK0_USERCCLK_2
IO_L30P_GCLK1_D13_2
IO_L16N_VREF_2
IO_L16P_2
Revision 0.01
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Pin Number
T11
Signal Name
Pin Name
IO Standard
LVDS_25
Bank
fmc_la20_n
fmc_la20_p
fmc_la21_n
fmc_la21_p
fmc_la22_n
fmc_la22_p
fmc_la23_n
fmc_la23_p
fmc_la24_n
fmc_la24_p
fmc_la25_n
fmc_la25_p
fmc_la26_n
fmc_la26_p
fmc_la27_n
fmc_la27_p
fmc_la28_n
fmc_la28_p
fmc_la29_n
fmc_la29_p
fmc_la30_n
fmc_la30_p
fmc_la31_n
fmc_la31_p
fmc_la32_n
fmc_la32_p
fmc_la33_n
fmc_la33_p
IO_L22N_2
IO_L22P_2
IO_L23N_2
IO_L23P_2
IO_L20N_2
IO_L20P_2
IO_L18N_2
IO_L18P_2
IO_L21N_2
IO_L21P_2
IO_L6N_2
IO_L6P_2
2
R11
U15
T15
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVDS_25
LVCMOS25*
LVDS_25
LVDS_25
LVCMOS25*
LVCMOS25*
SSTL15_II
SSTL15_II
LVCMOS25*
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
0
0
0
0
3
3
0
Y14
W14
W13
V13
AB15
Y15
AB14
AA14
V15
IO_L4N_VREF_2
IO_L4P_2
U16
W15
Y16
IO_L17N_2
IO_L17P_2
Y18
IO_L5N_2
W17
W18
V17
IO_L5P_2
IO_L2N_CMPMOSI_2
IO_L2P_CMPCLK_2
IO_L15N_2
AB17
Y17
IO_L15P_2
AB16
AA16
AB19
Y19
IO_L19N_2
IO_L19P_2
IO_L13N_D10_2
IO_L13P_M1_2
IO_L14N_D12_2
IO_L14P_D11_2
IO_L70N_1
AB18
AA18
R16
F10
fmc_prsnt_m2c_l
main_clk_n
main_clk_p
mig_calib_done_led
mig_error_led
mig_rzq
IO_L34N_GCLK18_0
IO_L34P_GCLK19_0
IO_L3N_0
G9
A2
E5
IO_L4P_0
R7
IO_L1P_3
W4
mig_zio
IO_L2P_3
D5
pcie_perst
IO_L2N_0
B10
pcie_refclk_n
pcie_refclk_p
pcie_rx_n
MGTREFCLK0N_101
MGTREFCLK0P_101
MGTRXN0_101
MGTRXP0_101
A10
C7
D7
pcie_rx_p
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Pin Number
E6
Signal Name
pcie_stat_led<0>
Pin Name
IO Standard
LVCMOS25*
Bank
IO_L4N_0
0
B3
pcie_stat_led<1>
pcie_stat_led<2>
pcie_tx_n
IO_L5P_0
LVCMOS25*
LVCMOS25*
0
0
A3
IO_L5N_0
A6
MGTTXN0_101
MGTTXP0_101
B6
pcie_tx_p
M19
K19
H20
J19
rgmii0_clk
IO_L40N_GCLK10_M1A6_1
IO_L34P_A13_M1WE_1
IO_L33N_A14_M1A4_1
IO_L33P_A15_M1A10_1
IO_L36P_A9_M1BA0_1
IO_L37P_A7_M1A0_1
IO_L41N_GCLK8_M1CASN_1
IO_L37N_A6_M1A1_1
IO_L35N_A10_M1A2_1
IO_L31P_A19_M1CKE_1
IO_L31N_A18_M1A12_1
IO_L32N_A16_M1A9_1
IO_L28N_VREF_1
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
rgmii0_intn
rgmii0_mdc
rgmii0_mdio
rgmii0_resetn
rgmii0_rx_ctl
rgmii0_rxc
K17
H21
K22
H22
G22
F21
F22
E22
D22
B21
B22
C22
D21
P20
P21
U20
T22
T21
R22
L22
rgmii0_rxd<0>
rgmii0_rxd<1>
rgmii0_rxd<2>
rgmii0_rxd<3>
rgmii0_tx_ctl
rgmii0_txc
rgmii0_txd<0>
rgmii0_txd<1>
rgmii0_txd<2>
rgmii0_txd<3>
rgmii1_clk
IO_L10P_1
IO_L10N_1
IO_L20N_1
IO_L28P_1
IO_L42P_GCLK7_M1UDM_1
IO_L46P_FCS_B_M1DQ2_1
IO_L49P_M1DQ10_1
IO_L48N_M1DQ9_1
rgmii1_intn
rgmii1_mdc
rgmii1_mdio
rgmii1_resetn
rgmii1_rx_ctl
rgmii1_rxc
IO_L48P_HDC_M1DQ8_1
IO_L47N_LDC_M1DQ1_1
IO_L43N_GCLK4_M1DQ5_1
IO_L46N_FOE_B_M1DQ3_1
IO_L45N_A0_M1LDQSN_1
IO_L44N_A2_M1DQ7_1
IO_L44P_A3_M1DQ6_1
IO_L52P_M1DQ14_1
IO_L52N_M1DQ15_1
IO_L49N_M1DQ11_1
IO_L50N_M1UDQSN_1
IO_L50P_M1UDQS_1
IO_L51N_M1DQ13_1
IO_L72P_1
P22
N22
M22
M21
Y21
Y22
U22
V22
V21
W22
R17
rgmii1_rxd<0>
rgmii1_rxd<1>
rgmii1_rxd<2>
rgmii1_rxd<3>
rgmii1_tx_ctl
rgmii1_txc
rgmii1_txd<0>
rgmii1_txd<1>
rgmii1_txd<2>
rgmii1_txd<3>
rs232_cts
Revision 0.01
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Pin Number
P18
T18
Signal Name
Pin Name
IO Standard
LVCMOS25*
Bank
rs232_rts
rs232_rx
rs232_tx
tmp
IO_L71N_1
IO_L73N_1
IO_L73P_1
IO_L6N_0
IO_L7P_0
IO_L7N_0
IO_L8P_0
IO_L59P_1
IO_L72N_1
1
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
LVCMOS25*
1
1
0
0
0
0
1
1
1
1
T19
A4
F7
user_led0
user_led1
user_led2
F8
C5
U19
T17
X1_SPI_CLK
X1_SPI_CSN
X1_SPI_MISO
X1_SPI_MOSI
W20
P19
IO_L51P_M1DQ12_1
IO_L53P_1
Revision 0.01
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Specifications
Form Factor
PCIe x1, half-length
Spartan-6 LX45T FPGA
FPGA
Low Pin Count FMC connector
36 LVDS pairs
General Purpose I/O
1 Rocket I/O channel
I2C interface
128MB DDR3 RAM
Memory
4 MB Flash for FPGA configuration
2 MB Flash for embedded code storage
Ethernet
2x Gigabit Ethernet Ports
Serial
1x RS-232
[1]
Temperature
Power
-40 to 85C
+3.3V DC, +12V DC required by some FMC
Power Consumption
Dimensions
Weight
TBD
4.375” x 6.600”
TBD
Warranty and Support
Lifetime warranty and free technical support
[1] Actual operating temperature depends on the user FPGA configuration, refer to ISE reports for details
Revision 0.01
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