Compaq Network Router M LVDS User Manual

Multipoint-Low Voltage  
Differential Signaling  
(M-LVDS) Evaluation Module  
User’s Guide  
High Performance Analog  
April 2004  
SLLU039B  
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EVM IMPORTANT NOTICE  
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:  
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION  
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided  
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective  
considerations, including product safety measures typically found in the end product incorporating the goods.  
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic  
compatibility and therefore may not meet the technical requirements of the directive.  
Should this evaluation kit not meet the specifications indicated in the EVM Users Guide, the kit may be returned  
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE  
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,  
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY  
PARTICULAR PURPOSE.  
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user  
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products  
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction  
of the product, it is the users responsibility to take any and all appropriate precautions with regard to electrostatic  
discharge.  
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE  
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.  
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not  
exclusive.  
TI assumes no liability for applications assistance, customer product design, software performance, or  
infringement of patents or services described herein.  
Please read the EVM Users Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM  
Users Guide prior to handling the product. This notice contains important safety information about temperatures  
and voltages. For further safety concerns, please contact the TI application engineer.  
Persons handling the product must have electronics training and observe good laboratory practice standards.  
No license is granted under any patent right or other intellectual property right of TI covering or relating to any  
machine, process, or combination in which such TI products or services might be or are used.  
Mailing Address:  
Texas Instruments  
Post Office Box 655303  
Dallas, Texas 75265  
Copyright 2004, Texas Instruments Incorporated  
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EVM WARNINGS AND RESTRICTIONS  
It is important to operate this EVM within the supply voltage range of 3 V to 3.6 V.  
Exceeding the specified supply range may cause unexpected operation and/or irreversible  
damage to the EVM. If there are questions concerning the supply range, please contact a TI  
field representative prior to connecting the input power.  
Applying loads outside of the specified output range may result in unintended operation and/or  
possible permanent damage to the EVM. Please consult the EVM Users Guide prior to  
connecting any load to the EVM output. If there is uncertainty as to the load specification,  
please contact a TI field representative.  
During normal operation, some circuit components may have case temperatures greater than  
125°C. The EVM is designed to operate properly with certain components above 125°C as  
long as the input and output ranges are maintained. These components include but are not  
limited to linear regulators, switching transistors, pass transistors, and current sense  
resistors. These types of devices can be identified using the EVM schematic located in the  
EVM Users Guide. When placing measurement probes near these devices during operation,  
please be aware that these devices may be very warm to the touch.  
Mailing Address:  
Texas Instruments  
Post Office Box 655303  
Dallas, Texas 75265  
Copyright 2004, Texas Instruments Incorporated  
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Preface  
How to Use This Manual  
This document contains the following chapters:  
- Chapter 1The M-LVDS Evaluation Module  
- Chapter 2Test Setup  
- Chapter 3Bill of Materials, Board Layout, and PCB Construction  
- Appendix ASchematic  
Related Documentation From Texas Instruments and Others  
- Introduction to M-LVDS (SLLA108)  
- LVDS Designers Notes (SLLA014A).  
- Reducing EMI With Low Voltage Differential Signaling (SLLA030B).  
- Interface Circuits for TIA/EIA−644 (LVDS) (SLLA038B).  
- Transmission at 200 Mpbs in VME Card Cage Using LVDM (SLLA088).  
- LVDS Multidrop Connections (literature number SLLA054).  
- SN65MLVD20x data sheets, Multipoint-LVDS Line Drivers and Receivers,  
(SLLS573 and SLLS558)  
- Electromagnetic Compatibility Printed Circuit Board and Electronic  
Module Design, VEC workshop, Violette Engineering Corporation.  
FCC Warning  
This equipment is intended for use in a laboratory test environment only. It  
generates, uses, and can radiate radio frequency energy and has not been  
tested for compliance with the limits of computing devices pursuant to subpart  
J of part 15 of FCC rules, which are designed to provide reasonable protection  
against radio frequency interference. Operation of this equipment in other  
environments may cause interference with radio communications. In which  
case the user, at his own expense, is required to take the necessary measures  
to correct this interference.  
Read This First  
v
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Contents  
1
The M-LVDS Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1  
1.1  
1.2  
1.3  
1.4  
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2  
M-LVDS Standard TIA/EIA−899 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3  
M-LVDS EVM Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4  
Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5  
1.4.1 Point-to-Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5  
1.4.2 Multidrop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6  
1.4.3 Multipoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6  
1.4.4 EVM Operation With Separate Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7  
Recommended Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8  
1.5  
2
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1  
2.1  
Typical Cable Test Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
2.1.1 Point-to-Point Simplex Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
2.1.2 Point-to-Point Parallel Terminated Simplex Transmission . . . . . . . . . . . . . . . . . 2-3  
2.1.3 Two-Node Multipoint Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3  
Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5  
2.2  
3
Bill of Materials, Board Layout, and PCB Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1  
3.1  
3.2  
3.3  
Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3  
PCB Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6  
A
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1  
vii  
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Figures  
11.  
12.  
13  
14  
15  
16  
17  
18  
21  
22  
23  
24  
25  
26  
31  
32  
33  
34  
35  
36  
M-LVDS Unit Interval Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2  
Expanded Graph of Receiver Differential Input Voltage Showing Transition Region . . . . 1-4  
Point-to-Point Simplex Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5  
Parallel Termination Simplex Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5  
Multidrop or Distributed Simplex Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6  
Five-Node Multipoint Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6  
Two-Node Multipoint Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7  
EVM Configuration for Including a Ground Potential Difference Voltage Between Nodes 1-8  
Point-to-Point Simplex Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
Point-to-Point Parallel Terminated Simplex Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3  
Two-Node Multipoint Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4  
Point-to-Point Parallel Simplex Typical Eye Pattern Data . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5  
Parallel Terminated Point-to-Point Parallel Simplex Typical Eye Pattern Data . . . . . . . . . . 2-6  
Two-Node Multipoint Typical Eye Pattern Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6  
Assembly Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3  
Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3  
Second Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4  
Third Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4  
Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5  
Trace Configurations in Printed-Circuit Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7  
Tables  
11  
12  
21  
31  
32  
MLVDS Devices Supported by the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2  
Receiver Input Voltage Threshold Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4  
EVM Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
M-LVDS EVM Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
EVM Layer Stack Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8  
viii  
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Chapter 1  
The M-LVDS Evaluation Module  
This document describes the multipoint low-voltage differential-signaling  
(M-LVDS) evaluation module (EVM) used to aid designers in development and  
analysis of this new signaling technology. The Texas Instruments  
SN65MLVD200A, SN65MLVD201, SN65MLVD202A, SN65MLVD203,  
SN65MLVD204A, SN65MLVD205A, SN65MLVD206, SN65MLVD207 series  
are low-voltage differential line drivers and receivers complying with the  
M-LVDS standard (TIA/EIA899). The EVM kit contains the assembled  
Using the EVM to evaluate these devices should provide insight into the design  
of low-voltage differential circuits. The EVM board allows the designer to  
connect an input to one or both of the drivers and configure a point-to-point,  
multidrop, or multipoint data bus.  
The EVM can be used to evaluate device parameters while acting as a guide  
for high-frequency board layout. The board allows for the connection of a  
100-controlled impedance cable of varying lengths. This provides the  
designer with a tool for evaluation and successful design of an end product.  
Topic  
Page  
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2  
1.2 M-LVDS Standard TIA/EIA−899 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3  
1.3 M-LVDS EVM Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4  
1.4 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5  
1.5 Recommended Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8  
1-1  
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Overview  
1.1 Overview  
The EVM comes with all the production devices in Table 11. The  
SN65MLVD201 and SN65MLVD207 are installed on the circuit board, and can  
easily be replaced with the other devices supplied. The M-LVDS devices  
evaluated with this EVM are in the SN75ALS180 and SN75176 footprint. Use  
of these industry standard footprints allows the designer to easily configure the  
parts into a simplex or half-duplex data bus. These are all TIA/EIA899  
M-LVDS standard compliant devices. While initially intended for half-duplex or  
multipoint applications, M-LVDS devices are not precluded from being used  
in a point-to-point or multidrop configuration. In these configurations there can  
be a distinct advantage to the additional current drive provided by an M-LVDS  
driver.  
The M-LVDS devices shown in Table 11 all include output slew-rate limited  
drivers, thus the need for different nominal signaling rates. The M-LVDS  
standard recommends the transition time not exceed 0.5 of the unit interval  
(UI). The definition of transition time (t and t ) in M-LVDS is the 10% to 90%  
r
f
levels shown in Figure 11. Using the maximum transition time for each of the  
drivers and the 0.5(t ) rule results in the signaling rates shown in Table 11.  
UI  
This slew-rate control differentiates M-LVDS devices from LVDS  
(TIA/EIA644A) compliant devices. The slower transition times available with  
M-LVDS help to reduce higher frequency components in the transmitted  
signal. This reduces EMI and allows longer stubs on the main transmission  
line. For this reason it is generally better to select a driver with a specified  
signaling rate no greater than is required in the system.  
Figure 11. M-LVDS Unit Interval Definition  
t
t
f
r
90%  
50%  
10%  
UI  
Table 11. M-LVDS Devices Supported by the EVM  
Nominal  
Receiver  
Part  
Number  
Signaling Rate  
(Mbps)  
Footprints  
Status  
Type  
100  
200  
100  
200  
100  
100  
200  
200  
SN75176  
SN75176  
Type-1  
Type-1  
Type-1  
Type-1  
Type-2  
Type-2  
Type-2  
Type-2  
SN65MLVD200AD  
SN65MLVD201D  
SN65MLVD202AD  
SN65MLVD203D  
SN65MLVD204AD  
SN65MLVD205AD  
SN65MLVD206D  
SN65MLVD207D  
Production  
Production  
Production  
Production  
Production  
Production  
Production  
Production  
SN75ALS180  
SN75ALS180  
SN75176  
SN75ALS180  
SN75176  
SN75ALS180  
1-2  
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M-LVDS Standard TIA/EIA899  
The EVM has been designed with the individual driver and receiver section  
(SN75ALS180 footprint, U1) on one half of the board and the transceiver  
section (SN75176 footprint, U2) on the other half (see Figure 31). The EVM  
as delivered incorporates two 100-termination resistors at each driver  
output, receiver input, and transceiver I/O. These allow the user to evaluate  
a single driver, receiver, or transceiver, while not having to deal with a  
transmission line or additional I/Os.  
Jumpers are included to allow the two sections of the EVM to either share the  
same power and ground or be run off of independent supplies. Ground shifts  
or common-mode offsets can be introduced by the removal of these jumpers  
and using separate power supplies.  
1.2 M-LVDS Standard TIA/EIA899  
The M-LVDS standard was created in response to a demand from the data  
communications community for a general-purpose high-speed balanced  
interface standard for multipoint applications. The TIA/EIA644 standard  
defines the LVDS electrical-layer characteristics used for transmitting  
information in point-to-point and multidrop architectures. TIA/EIA644 does  
not address data transmission for multipoint architectures, therefore the need  
for development of a new standard.  
The standard, Electrical Characteristics of Multipoint-Low-Voltage Differential  
Signaling (M-LVDS) TIA/EIA899, specifies low-voltage differential signaling  
drivers and receivers for data interchange across half-duplex or multipoint  
data bus structures. M-LVDS is capable of operating at signaling rates up to  
500 Mbps. In other words, when the devices are used at the nominal signaling  
rate, the rise and fall times will be within the specified values in the standard.  
The M-LVDS standard defines the transition time (t and t ) to be 1 ns or slower  
r
f
into a test load. Using this information combined with the requirement that the  
transition time not exceed 0.5 of the unit interval (UI), gives a minimum unit  
interval of 2 ns, leading to the 500 Mpbs maximum signaling rate.  
The standard defines Type-1 and Type-2 receivers. Type-1 receivers include  
no provisions for failsafe and have their differential input voltage thresholds  
near zero volts. Type-2 receivers have their differential input voltage  
thresholds offset from zero volts to detect the absence of a voltage difference.  
Type-1 receivers maximize the differential noise margin and are intended for  
the maximum signaling rate. Type-2 receivers are intended for control signals,  
slower signaling rates, or where failsafe provisions are needed. The bus  
1-3  
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M-LVDS EVM Kit Contents  
Table 12. Receiver Input Voltage Threshold Requirements  
Receiver Type  
Type-1  
Low  
High  
2.4 V V 0.05 V  
0.05 V V 2.4 V  
ID  
ID  
Type-2  
2.4 V V 0.05 V  
0.15 V V 2.4 V  
ID  
ID  
Figure 12. Expanded Graph of Receiver Differential Input Voltage Showing Transition  
Region  
Type1 and Type2 Receiver Differential Input Thresholds  
Type 1  
Type 2  
High  
2.4  
0.15  
0.1  
High  
0.05  
0
Low  
0.05  
2.4  
Low  
Transition Region  
1.3 M-LVDS EVM Kit Contents  
The M-LVDS EVM kit contains the following:  
J
M-LVDS EVM PWB with SN65MLVD201D and SN65MLVD207D  
installed (6424409B)  
J
Additional  
SN65MLVD203,  
SN65MLVD206  
devices  
SN65MLVD200A,  
SN65MLVD204A,  
SN65MLVD202A,  
SN65MLVD205A,  
J
J
M-LVDS EVM kit documentation (users guide)  
SN65MLVD20x data sheets, Multipoint-LVDS Line Driver and  
Receiver, (SLLS573 and SLLS558)  
1-4  
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Configurations  
1.4 Configurations  
The M-LVDS EVM board allows the user to construct various bus  
configurations. The two devices on the EVM allow for point-to-point simplex,  
parallel-terminated point-to-point simplex, and two-node multipoint operation.  
All of these modes of operation can be configured through onboard jumpers,  
external cabling, and different resistor combinations. The devices which are  
delivered with the EVM change output operation but, configuration of jumpers  
to setup the transmission type is independent of the devices installed  
1.4.1 Point-to-Point  
schematic for this option is shown in Figure 21. Although this is not the  
intended mode of operation for M-LVDS, it works well for high noise or long  
higher-loss transmission lines. Due to the increased drive current, a single  
100-termination resistor on the EVM will result in a differential bus voltage  
(V ) twice as large as a doubly terminated line. This practice is acceptable  
OD  
as long as the combination of input voltage and common-mode voltage does  
not exceed absolute maximum ratings of the line circuits.  
Figure 13. Point-to-Point Simplex Circuit  
U1  
U1  
T
This configuration can also have a termination at the source and load (parallel  
terminated), thereby, keeping normal M-LVDS signal levels as shown in Figure  
14.  
The schematic for this option is shown in Figure 22. Due to the increased  
drive current, double termination can be used to improve transmission line  
characteristics .  
Figure 14. Parallel Termination Simplex Circuit  
U1  
U1  
T
T
1-5  
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Configurations  
1.4.2 Multidrop  
A multidrop configuration (see Figure 15) with two receiver nodes can be  
simulated with the EVM. To get additional receiver nodes on the same bus  
requires additional EVMs. M-LVDS controlled driver transition times and  
higher signal levels help to accommodate the multiple stubs and additional  
loads on the bus. This does not exempt good design practices, which would  
keep stubs short to help prevent excessive signal reflections.  
A bus line termination could be placed at both ends of the transmission line,  
improving the signal quality by reducing return reflections to the driver. This  
would allow the use of standard compliant TIA/EIA 644A receivers on the bus  
in addition to M-LVDS receivers.  
Figure 15. Multidrop or Distributed Simplex Circuit  
T
1.4.3 Multipoint  
The multipoint configuration is the primary application of the M-LVDS devices  
and the associated standard. The M-LVDS standard allows for any  
combination of drivers, receivers, or transceivers up to a total of 32 on the line.  
Figure 16 shows a representation of a five-node multipoint configuration  
using transceivers. Increased drive current, in addition to the wider common-  
mode input, allows M-LVDS parts to drive multiple receivers over longer line  
lengths with up to 2 V of ground noise.  
Figure 16. Five-Node Multipoint Circuit  
T
T
A two-node multipoint setup (see Figure 17) can be configured with the EVM.  
Additional EVMs are needed for more nodes. The test setup and schematic  
for this configuration is shown in Figure 23.  
1-6  
The M-LVDS Evaluation Module  
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Configurations  
Figure 17. Two-Node Multipoint Circuit  
T
T
U2  
U1  
1.4.4 EVM Operation With Separate Power Supplies  
The EVM has been designed with independent power planes for the two  
devices. The two devices can be powered with independent supplies or with  
a single supply. Sending and receiving data between backplanes, racks, or  
cabinets where separate power sources may exist can have offset ground  
potentials between nodes. Jumpers W7, 8, 9, and 10 tie the two separate  
power and ground planes together. If two separate supplies are used and  
jumpers W7, 8, 9, and 10 are removed, care should be taken to ensure the  
absolute maximum device ratings are not exceeded. Keep in mind that if  
jumpers W7, 8, 9, and 10 are not removed when using separate power  
supplies, a difference in potential between the supplies causes a current to  
flow between supplies and through the jumpers.  
The EVM can be configured with three power supplies with isolated outputs  
in such a way as to input a fixed offset between the grounds (see Figure 18).  
This induces a ground potential difference voltage between U1 and U2. To  
demonstrate this capability, the following steps should be followed.  
- Adjust PS1 and PS3 to the supply voltage (3.3 V) and current limit to  
50 mA.  
- Set PS2 to 0 V  
- Induce a ground offset by varying the output of PS2.  
PS2 Output  
The PS2 output should not exceed 2 V to remain within the device  
ratings.  
1-7  
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Recommended Equipment  
Figure 18. EVM Configuration for Including a Ground Potential Difference Voltage  
Between Nodes  
+
PS1  
+
PS2  
+
PS3  
Jumpers removed from  
W7, W8, W9, W10  
1.5 Recommended Equipment  
- 3.3 Vdc at 0.5-A power supply or multiple power supplies (with both  
devices powered and enabled the board draws about 35 mA).  
- A 100-transmission medium from the driver to the receiver, (twisted-pair  
cable recommended, CAT5 cable for example).  
- A function or pattern generator capable of supplying 3.3-V signals at the  
desired signaling rate.  
- A multiple-channel high-bandwidth oscilloscope, preferably above the  
1-GHz range  
- Differential or single ended oscilloscope probes.  
1-8  
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Chapter 2  
Test Setup  
This chapter describes how to setup and use the M-LVDS EVM.  
Topic  
Page  
2.1 Typical Cable Test Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
2.2 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5  
2-1  
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Typical Cable Test Configurations  
2.1 Typical Cable Test Configurations  
Each of the following test configurations is a transmission line consisting of a  
twisted-pair cable connected on the 2-pin connectors (P1, P2, or P3).  
Table 21 shows the possible configurations.  
In addition to the different transmission topologies, the EVM can also be  
configured to run off two or three separate power supplies, as described in the  
previous section. This would allow the user to induce a ground shift or offset  
between the two different drivers and receivers. This setup can be used with  
any transmission line test.  
Table 21. EVM Configuration Options  
Configuration  
Jumpers In  
Resistors In  
Resistors Out  
Diagram  
Point-to-point simplex transmission  
W1, 2, 7, 8, 9, 10  
R4  
R5, 6, 7  
Figure 21  
Point-to-point parallel terminated simplex  
transmission  
W1, 2, 7, 8, 9, 10  
R4, 7  
R5, 6  
Figure 22  
Two-node multipoint transmission  
W1, 2, 3, 4, 7, 8, 9, 10  
R5, 16  
R2, 4, 6, 7, 13 15 Figure 23  
2.1.1 Point-to-Point Simplex Transmission  
1) Connect a twisted-pair cable from P1 to P2.  
2) Verify resistor R4 is installed.  
3) Remove resistors R5, R6, and R7. This properly terminates the  
transmission line at one end.  
4) Enable the driver by connecting the jumper on W2 between pin 1 and  
pin 2, or U1 pin 4 to V  
.
CC  
5) Enable the receiver by connecting the jumper on W1 between pin 2 and  
pin 3, or U1 pin 3 to GND.  
Figure 21. Point-to-Point Simplex Transmission  
VCC  
Jumper  
W2  
Input Signal  
50-Ω  
Cable  
4
5
9
J2  
R7  
100  
R6  
100  
P2  
P1  
U1  
Signal Source  
with 50-Ω  
Output  
10  
R3  
49.9  
TP2  
Twisted Pair Cable  
50-Ω  
Cable  
R2  
453  
12  
50-cable or  
Active Voltage  
Probe into one  
Channel of Scope  
Terminated in  
J1  
2
R4  
100  
R5  
100  
U1  
3
11  
TP1  
VCC  
High Impedance  
W1  
Jumper  
Output Signal  
Active Voltage  
Probe  
2-2  
Test Setup  
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Typical Cable Test Configurations  
2.1.2 Point-to-Point Parallel Terminated Simplex Transmission  
1) Connect a twisted-pair cable from P1 to P2.  
2) Verify resistor R4 and R7 are installed.  
3) Remove resistors R5 and R6. This properly terminates the transmission  
line at both ends.  
4) Enable the driver by connecting the jumper on W2 between pin 1 and pin  
2, or U1 pin 4 to V  
.
CC  
5) Enable the receiver by connecting the jumper on W1 between pin 2 and  
pin 3, or U1 pin 3 to GND.  
Figure 22. Point-to-Point Parallel Terminated Simplex Transmission  
VCC  
Jumper  
W2  
Input Signal  
50-Ω  
4
5
Cable  
9
J2  
R7  
100  
R6  
100  
P2  
P1  
U1  
Signal Source  
with 50-Ω  
Output  
10  
R3  
49.9  
TP2  
Twisted Pair Cable  
50-Ω  
Cable  
R2  
453  
12  
50-cable or  
Active Voltage  
Probe into one  
Channel of Scope  
Terminated in  
J1  
2
R4  
100  
R5  
100  
U1  
3
11  
VCC  
TP1  
High Impedance  
W1  
Jumper  
Output Signal  
Active Voltage  
Probe  
2.1.3 Two-Node Multipoint Transmission  
1) Connect a twisted-pair cable between P1, P2, and P3.  
2) Verify resistor R5 and R16 are installed.  
3) Remove resistors R4, R6, R7, and R15. This properly terminates the  
transmission line at both ends.  
4) Enabling the driver in a two-node multipoint configuration will be a slightly  
more challenging task. The user can either jumper enable a single driver  
and send all of the data on the bus through a single driver, or sync the  
driver enable to the data and send data from each driver. Enable a single  
driver by connecting the jumper on W4 between pin 1 and pin 2 which  
connects U2 pin 3 to V , or by connecting the jumper on W2 between pin  
CC  
1 and pin 2 which connects U1 pin 4 to V  
.
CC  
5) Enable the receivers by connecting the jumpers on W1 and W3 between  
pin 2 and pin 3, or U1 pin 3 to GND and U2 pin 2 to GND.  
2-3  
Test Setup  
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Typical Cable Test Configurations  
Figure 23. Two-Node Multipoint Transmission  
VCC  
W2  
Jumper  
Input Signal  
50-Ω  
Cable  
4
9
J2  
R7  
100  
5
R6  
100  
P2  
P1  
U1  
Signal Source  
with 50-Ω  
Output  
R3  
49.9  
10  
TP2  
Twisted Pair Cable  
50-Ω  
Cable  
R2  
453  
12  
11  
50-cable or  
Active Voltage  
Probe into one  
Channel of Scope  
Terminated in  
J1  
2
R5  
100  
R4  
100  
U1  
3
TP1  
VCC  
VCC  
W4  
High Impedance  
W1  
Output Signal  
Input Signal  
U2  
Jumper  
Jumper  
Active Voltage  
Probe  
3
6
7
J8  
4
P3  
R16  
100  
R15  
100  
R14  
49.9  
TP4  
50-Ω  
Cable  
R13  
453  
J7  
50-cable or  
Active Voltage  
Probe into one  
Channel of Scope  
Terminated in  
1
TP3  
VCC  
2
W3  
Jumper  
High Impedance  
Output Signal  
Active Voltage  
Probe  
2-4  
Test Setup  
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Test Results  
2.2 Test Results  
The test configurations described in Section 2.1 were used to simulate point-  
to-point simplex, parallel-terminated point-to-point simplex, and two-node  
multipoint. The test results are shown in the following figures. A Tektronix  
HFS9003 was used to generate input signals, and a Tektronix TDS784D was  
used to collect the output data.  
The EVM was populated with a SN65MLVD207D and SN65MLVD201D for U1  
and U2 respectively. The eye patterns were measured with the source  
15  
(Tektronix HFS9003) generating 2 1 PRBS NRZ data. In all cases, the  
length of the transmission line is approximately 21 inches (53 cm), and adds  
to the propagation delay in the device. This can be seen in the figures below  
as a time delay from input to output  
1 is the driver input signal applied to J2. The output signal is shown below  
measured on both J1 (Figure 24 left picture), and TP1 (Figure 24 right  
picture). The receiver output in both figures shows the offset zero crossing,  
which is due to the Type-2 receiver incorporated into the SN65MLVD207  
device. The reduced offset from a Type-1 receiver can be seen in Figure 26,  
receiver number 2 output.  
Measuring the output signal on J1 with a 50-cable terminated into 50-at  
the scope will attenuate the signal due to the 453-resistor in series with the  
receiver output. The resistor is installed as a current limit for termination into  
a 50-load. As can be seen in the traces below the magnitude of trace 2 on  
the left is one-tenth of trace 2 on the right. Measuring the signal with a  
high-impedance probe on TP1 requires replacing R2, the 453-resistor, with  
a short to reduce signal roll-off. Measuring the output on TP1 allows the user  
to see absolute signal levels out of the device.  
Figure 24. Point-to-Point Parallel Simplex Typical Eye Pattern Data  
Driver  
Input  
Receiver  
Output  
Differential  
Bus  
Voltage  
50-Ohm Output Termination  
High Impedance Output Termination, R2 Shorted  
Receiver Output Scaled 10:1  
data where trace 1 is the input signal applied to J2, and trace 2 is the output  
2-5  
Test Setup  
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Test Results  
signal on TP1, R2 is shorted. Type-2 behavior is again observed on the  
SN65MLVD207 receiver output.  
Trace three shows the differential voltage on the bus. Note that the bus volt-  
ages are nominal M-LVDS levels of 1.1 V due to the lower load seen by the  
PP  
current driver.  
Figure 25. Parallel Terminated Point-to-Point Parallel Simplex Typical Eye Pattern Data  
Driver  
Input  
Receiver  
Output  
Differential  
Bus  
Voltage  
Figure 26 represents the two-node multipoint transmission eye patterns  
where trace 1 is the input signal applied to J2, and traces 2 and 3 are the output  
signals seen at TP1 and TP3 respectively with R2 and R13 shorted. The offset  
zero-crossing shows the difference between Type2 (Receiver #1 Output) and  
Type1 (Receiver #2 Output).  
Figure 26. Two-Node Multipoint Typical Eye Pattern Data  
Driver  
Input  
Receiver #1  
Output  
Receiver #2  
Output  
2-6  
Test Setup  
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Chapter 3  
Bill of Materials, Board Layout, and PCB  
Construction  
This chapter contains the bill of materials, board layout of the M-LVDS, and  
describes the printed-circuit board.  
Topic  
Page  
2.1 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
3.2 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3  
3.3 PCB Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6  
3-1  
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