AMD Computer Hardware SC3200 User Manual
AMD Geode™ SC3200 Processor  
Data Book  
February 2007  
Publication ID: 32581C  
AMD Geode™ SC3200 Processor Data Book  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Contents  
32581C  
Contents  
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
1.0 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
2.0 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
2.1 GX1 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
2.2 Video Processor Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
2.3 Core Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
2.4 Super I/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
2.5 Clock, Timers, and Reset Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
3.0 Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
3.1 Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
3.2 Strap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
3.3 Multiplexing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
3.4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49  
4.0 General Configuration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69  
4.1 Configuration Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69  
4.2 Multiplexing, Interrupt Selection, and Base Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . 70  
4.3 WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77  
4.4 High-Resolution Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79  
4.5 Clock Generators and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81  
5.0 SuperI/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87  
5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88  
5.2 Module Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89  
5.3 Configuration Structure / Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90  
5.4 Standard Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92  
5.5 Real-Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103  
5.6 System Wakeup Control (SWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114  
5.7 ACCESS.bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119  
5.8 Legacy Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127  
AMD Geode™ SC3200 Processor Data Book  
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32581C  
Contents  
6.0 Core Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139  
6.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139  
6.2 Module Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140  
6.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173  
6.4 Chipset Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188  
7.0 Video Processor Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309  
7.1 Module Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310  
7.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311  
7.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327  
8.0 Debugging and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349  
8.1 Testability (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349  
9.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351  
9.1 General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351  
9.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357  
9.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362  
10.0 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421  
10.1 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421  
10.2 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423  
Appendix A Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425  
A.1  
A.2  
Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425  
Data Book Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426  
4
AMD Geode™ SC3200 Processor Data Book  
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List of Figures  
32581C  
List of Figures  
Figure 1-1.  
Figure 3-1.  
Figure 3-2.  
Figure 4-1.  
Figure 4-2.  
Figure 4-3.  
Figure 5-1.  
Figure 5-2.  
Figure 5-3.  
Figure 5-4.  
Figure 5-5.  
Figure 5-6.  
Figure 5-7.  
Figure 5-8.  
Figure 5-9.  
Figure 5-10.  
Figure 5-11.  
Figure 5-12.  
Figure 5-13.  
Figure 5-14.  
Figure 5-15.  
Figure 5-16.  
Figure 5-17.  
Figure 5-18.  
Figure 5-19.  
Figure 6-1.  
Figure 6-2.  
Figure 6-3.  
Figure 6-4.  
Figure 6-5.  
Figure 6-6.  
Figure 6-7.  
Figure 6-8.  
Figure 6-9.  
Figure 6-10.  
Figure 6-11.  
Figure 6-12.  
Figure 6-13.  
Figure 6-14.  
Figure 6-15.  
Figure 7-1.  
Figure 7-2.  
Figure 7-3.  
Figure 7-4.  
Figure 7-5.  
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
BGU481 Ball Assignment Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
WATCHDOG Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77  
Clock Generation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81  
Recommended Oscillator External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82  
SIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87  
Detailed SIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89  
Structure of the Standard Configuration Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90  
Standard Configuration Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92  
Recommended Oscillator External Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103  
External Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104  
Divider Chain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104  
Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106  
Typical Battery Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106  
Typical Battery Current: Battery Backed Power Mode @ T = 25°C . . . . . . . . . . . . . . . . . 106  
C
Typical Battery Current: Normal Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106  
Interrupt/Status Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108  
Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119  
Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119  
ACCESS.bus Data Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120  
ACCESS.bus Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120  
A Complete ACCESS.bus Data Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121  
UART Mode Register Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129  
IRCP/SP3 Register Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133  
Core Logic Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140  
Non-Posted Fast-PCI to ISA Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146  
PCI to ISA Cycles with Delayed Transaction Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147  
ISA DMA Read from PCI Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148  
ISA DMA Write to PCI Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148  
PCI Change to Sub-ISA and Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150  
PIT Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152  
PIC Interrupt Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153  
PCI and IRQ Interrupt Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154  
SMI Generation for NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155  
General Purpose Timer and UDEF Trap SMI Tree Example . . . . . . . . . . . . . . . . . . . . . . . . 163  
PRD Table Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167  
AC97 V2.0 Codec Signal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168  
Audio SMI Tree Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170  
Typical Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171  
Video Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310  
NTSC 525 Lines, 60 Hz, Odd Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312  
NTSC 525 Lines, 60 Hz, Even Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312  
VIP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313  
Capture Video Mode Bob Example Using One Video Frame Buffer . . . . . . . . . . . . . . . . . . 315  
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32581C  
List of Figures  
Figure 7-6.  
Figure 7-7.  
Figure 7-8.  
Figure 7-9.  
Figure 7-10.  
Figure 7-11.  
Figure 7-12.  
Figure 7-13.  
Figure 7-14.  
Figure 9-1.  
Figure 9-2.  
Figure 9-3.  
Figure 9-4.  
Figure 9-5.  
Figure 9-6.  
Figure 9-7.  
Figure 9-8.  
Figure 9-9.  
Figure 9-10.  
Figure 9-11.  
Figure 9-12.  
Figure 9-13.  
Figure 9-14.  
Figure 9-15.  
Figure 9-16.  
Figure 9-17.  
Figure 9-18.  
Figure 9-19.  
Figure 9-20.  
Figure 9-21.  
Figure 9-22.  
Figure 9-23.  
Figure 9-24.  
Figure 9-25.  
Figure 9-26.  
Figure 9-27.  
Figure 9-28.  
Figure 9-29.  
Figure 9-30.  
Figure 9-31.  
Figure 9-32.  
Figure 9-33.  
Figure 9-34.  
Figure 9-35.  
Figure 9-36.  
Figure 9-37.  
Figure 9-38.  
Figure 9-39.  
Figure 9-40.  
Figure 9-41.  
Figure 9-42.  
Figure 9-43.  
Figure 9-44.  
Figure 9-45.  
Figure 9-46.  
Capture Video Mode Weave Example Using Two Video Frame Buffers . . . . . . . . . . . . . . . 316  
Video Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317  
Horizontal Downscaler Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318  
Linear Interpolation Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319  
Mixer/Blender Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320  
Graphics/Video Frame with Alpha Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322  
Color Key and Alpha Blending Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324  
TFT Power Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325  
PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326  
Differential Input Sensitivity for Common Mode Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360  
Drive level and Measurement Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362  
Memory Controller Drive Level and Measurement Points . . . . . . . . . . . . . . . . . . . . . . . . . . 363  
Memory Controller Output Valid Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365  
Read Data In Setup and Hold Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365  
Video Input Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366  
TFT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367  
ACB Signals: Rising Time and Falling Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369  
ACB Start and Stop Condition Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369  
ACB Start Condition Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370  
ACB Data Bit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370  
Testing Setup for Slew Rate and Minimum Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371  
V/I Curves for PCI Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372  
PCICLK Timing and Measurement Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373  
Load Circuits for Maximum Time Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374  
Output Timing Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375  
Input Timing Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376  
PCI Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376  
Sub-ISA Read Operation Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379  
Sub-ISA Write Operation Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380  
LPC Output Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381  
LPC Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381  
IDE Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382  
Register Transfer to/from Device Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384  
PIO Data Transfer to/from Device Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386  
Multiword DMA Data Transfer Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388  
Initiating an UltraDMA Data in Burst Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390  
Sustained UltraDMA Data In Burst Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391  
Host Pausing an UltraDMA Data In Burst Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 392  
Device Terminating an UltraDMA Data In Burst Timing Diagram . . . . . . . . . . . . . . . . . . . . 393  
Host Terminating an UltraDMA Data In Burst Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 394  
Initiating an UltraDMA Data Out Burst Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395  
Sustained UltraDMA Data Out Burst Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396  
Device Pausing an UltraDMA Data Out Burst Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 397  
Host Terminating an UltraDMA Data Out Burst Timing Diagram . . . . . . . . . . . . . . . . . . . . . 398  
Device Terminating an UltraDMA Data Out Burst Timing Diagram . . . . . . . . . . . . . . . . . . . 399  
Data Signal Rise and Fall Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402  
Source Differential Data Jitter Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402  
EOP Width Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403  
Receiver Jitter Tolerance Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403  
UART, Sharp-IR, SIR, and Consumer Remote Control Timing Diagram . . . . . . . . . . . . . . . 404  
Fast IR (MIR and FIR) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405  
Standard Parallel Port Typical Data Exchange Timing Diagram . . . . . . . . . . . . . . . . . . . . . 406  
Enhanced Parallel Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407  
ECP Forward Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408  
ECP Reverse Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409  
6
AMD Geode™ SC3200 Processor Data Book  
Download from Www.Somanuals.com. All Manuals Search And Download.  
List of Figures  
32581C  
Figure 9-47.  
Figure 9-48.  
Figure 9-49.  
Figure 9-50.  
Figure 9-51.  
Figure 9-52.  
Figure 9-53.  
Figure 9-54.  
Figure 9-55.  
Figure 9-56.  
Figure 9-57.  
Figure 9-58.  
Figure 10-1.  
Figure 10-2.  
Figure 10-3.  
AC97 Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410  
AC97 Sync Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410  
AC97 Clocks Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411  
AC97 Data TIming Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412  
AC97 Rise and Fall Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413  
AC97 Low Power Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414  
PWRBTN# Trigger and ONCTL# Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415  
GPWIO and ONCTL# Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415  
Power-Up Sequencing With PWRBTN# Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 416  
Power-Up Sequencing Without PWRBTN# Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 417  
TCK Measurement Points and Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418  
JTAG Test Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419  
Heatsink Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422  
BGU481 Package - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423  
BGU481 Package - Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424  
AMD Geode™ SC3200 Processor Data Book  
Download from Www.Somanuals.com. All Manuals Search And Download.  
7
32581C  
List of Figures  
8
AMD Geode™ SC3200 Processor Data Book  
Download from Www.Somanuals.com. All Manuals Search And Download.  
List of Tables  
32581C  
List of Tables  
Table 2-1.  
Table 2-2.  
Table 3-1.  
Table 3-2.  
Table 3-3.  
Table 3-4.  
Table 3-5.  
Table 3-6.  
Table 3-7.  
Table 4-1.  
Table 4-2.  
Table 4-3.  
Table 4-4.  
Table 4-5.  
Table 4-6.  
Table 4-7.  
Table 4-8.  
Table 5-1.  
Table 5-2.  
Table 5-3.  
Table 5-4.  
Table 5-5.  
Table 5-6.  
Table 5-7.  
Table 5-8.  
Table 5-9.  
Table 5-10.  
Table 5-11.  
Table 5-12.  
Table 5-13.  
Table 5-14.  
Table 5-15.  
Table 5-16.  
Table 5-17.  
Table 5-18.  
Table 5-19.  
Table 5-20.  
Table 5-21.  
Table 5-22.  
Table 5-23.  
Table 5-24.  
Table 5-25.  
Table 5-26.  
Table 5-27.  
Table 5-28.  
SC3200 Memory Controller Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
SC3200 Memory Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Signal Definitions Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
BGU481 Ball Assignment - Sorted by Ball Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
BGU481 Ball Assignment - Sorted Alphabetically by Signal Name . . . . . . . . . . . . . . . . . . . 40  
Strap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44  
Two-Signal/Group Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45  
Three-Signal/Group Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Four-Signal/Group Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48  
General Configuration Block Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69  
Multiplexing, Interrupt Selection, and Base Address Registers . . . . . . . . . . . . . . . . . . . . . . . 70  
WATCHDOG Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78  
High-Resolution Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80  
Crystal Oscillator Circuit Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82  
Core Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83  
Strapped Core Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83  
Clock Generator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85  
SIO Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90  
LDN Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90  
Standard Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93  
SIO Control and Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95  
SIO Control and Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95  
Relevant RTC Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96  
RTC Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97  
Relevant SWC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98  
Relevant IRCP/SP3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99  
IRCP/SP3 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99  
Relevant Serial Ports 1 and 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100  
Serial Ports 1 and 2 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100  
Relevant ACB1 and ACB2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101  
ACB1 and ACB2 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101  
Relevant Parallel Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102  
Parallel Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102  
Crystal Oscillator Circuit Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103  
System Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107  
RTC Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109  
RTC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109  
Divider Chain Control / Test Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112  
Periodic Interrupt Rate Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112  
BCD and Binary Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112  
Standard RAM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113  
Extended RAM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113  
Time Range Limits for CEIR Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114  
Banks 0 and 1 - Common Control and Status Register Map . . . . . . . . . . . . . . . . . . . . . . . . 115  
Bank 1 - CEIR Wakeup Configuration and Control Register Map . . . . . . . . . . . . . . . . . . . . 115  
AMD Geode™ SC3200 Processor Data Book  
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9
 
32581C  
List of Tables  
Table 5-29.  
Table 5-30.  
Table 5-31.  
Table 5-32.  
Table 5-33.  
Table 5-34.  
Table 5-35.  
Table 5-36.  
Table 5-37.  
Table 5-38.  
Table 5-39.  
Table 5-40.  
Table 5-41.  
Table 5-42.  
Table 5-43.  
Table 5-44.  
Table 5-45.  
Table 5-46.  
Table 5-47.  
Table 5-48.  
Table 5-49.  
Table 5-50.  
Table 5-51.  
Table 5-52.  
Table 5-53.  
Table 5-54.  
Table 5-55.  
Table 5-56.  
Table 5-57.  
Table 5-58.  
Table 5-59.  
Table 5-60.  
Table 5-61.  
Table 5-62.  
Table 6-1.  
Table 6-2.  
Table 6-3.  
Table 6-4.  
Table 6-5.  
Table 6-6.  
Table 6-7.  
Table 6-8.  
Table 6-9.  
Table 6-10.  
Table 6-11.  
Table 6-12.  
Table 6-13.  
Table 6-14.  
Table 6-15.  
Table 6-16.  
Table 6-17.  
Table 6-18.  
Table 6-19.  
Table 6-20.  
Table 6-21.  
Banks 0 and 1 - Common Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 116  
Bank 1 - CEIR Wakeup Configuration and Control Registers . . . . . . . . . . . . . . . . . . . . . . . 117  
ACB Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124  
ACB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124  
Parallel Port Register Map for First Level Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127  
Parallel Port Register Map for Second Level Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127  
Parallel Port Bit Map for First Level Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128  
Parallel Port Bit Map for Second Level Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128  
Bank 0 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129  
Bank Selection Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130  
Bank 1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130  
Bank 2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130  
Bank 3 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130  
Bank 0 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131  
Bank 1 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131  
Bank 2 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132  
Bank 3 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132  
Bank 0 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133  
Bank Selection Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134  
Bank 1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134  
Bank 2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134  
Bank 3 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135  
Bank 4 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135  
Bank 5 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135  
Bank 6 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136  
Bank 7 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136  
Bank 0 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136  
Bank 1 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137  
Bank 2 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137  
Bank 3 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137  
Bank 4 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137  
Bank 5 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138  
Bank 6 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138  
Bank 7 Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138  
Physical Region Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143  
UltraDMA/33 Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144  
Cycle Multiplexed PCI / Sub-ISA Balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149  
PIC Interrupt Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153  
Wakeup Events Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157  
Power Planes Control Signals vs. Sleep States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158  
Power Planes vs. Sleep/Global States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158  
Power Management Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158  
Device Power Management Programming Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164  
Bus Masters That Drive Specific Slots of the AC97 Interface . . . . . . . . . . . . . . . . . . . . . . . 165  
Physical Region Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166  
Cycle Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172  
PCI Configuration Address Register (0CF8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173  
F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support Summary . . . 174  
F0BAR0: GPIO Support Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177  
F0BAR1: LPC Support Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177  
F1: PCI Header Registers for SMI Status and ACPI Support Summary . . . . . . . . . . . . . . . 178  
F1BAR0: SMI Status Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178  
F1BAR1: ACPI Support Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179  
F2: PCI Header Registers for IDE Controller Support Summary . . . . . . . . . . . . . . . . . . . . . 180  
F2BAR4: IDE Controller Support Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181  
10  
AMD Geode™ SC3200 Processor Data Book  
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List of Tables  
32581C  
Table 6-22.  
Table 6-23.  
Table 6-24.  
Table 6-25.  
Table 6-26.  
Table 6-27.  
Table 6-28.  
Table 6-29.  
Table 6-30.  
Table 6-31.  
Table 6-32.  
Table 6-33.  
Table 6-34.  
Table 6-35.  
Table 6-36.  
Table 6-37.  
Table 6-38.  
Table 6-39.  
Table 6-40.  
Table 6-41.  
Table 6-42.  
Table 6-43.  
Table 6-44.  
Table 6-45.  
Table 6-46.  
Table 6-47.  
Table 6-48.  
Table 6-49.  
Table 7-1.  
Table 7-2.  
Table 7-3.  
Table 7-4.  
Table 7-5.  
Table 7-6.  
Table 7-7.  
Table 7-8.  
Table 8-1.  
Table 9-1.  
Table 9-2.  
Table 9-3.  
Table 9-4.  
Table 9-5.  
Table 9-6.  
Table 9-7.  
Table 9-8.  
Table 9-9.  
Table 9-10.  
Table 9-11.  
Table 9-12.  
Table 9-13.  
Table 9-14.  
Table 9-15.  
Table 9-16.  
Table 9-17.  
Table 9-18.  
F3: PCI Header Registers for Audio Support Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 181  
F3BAR0: Audio Support Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182  
F5: PCI Header Registers for X-Bus Expansion Support Summary . . . . . . . . . . . . . . . . . . 183  
F5BAR0: I/O Control Support Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183  
PCIUSB: USB PCI Configuration Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184  
USB_BAR: USB Controller Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185  
ISA Legacy I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186  
F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support . . . . . . . . . . . 188  
F0BAR0+I/O Offset: GPIO Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222  
F0BAR1+I/O Offset: LPC Interface Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . 226  
F1: PCI Header Registers for SMI Status and ACPI Support . . . . . . . . . . . . . . . . . . . . . . . 234  
F1BAR0+I/O Offset: SMI Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235  
F1BAR1+I/O Offset: ACPI Support Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245  
F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration . . . . . . . . . . 255  
F2BAR4+I/O Offset: IDE Controller Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . 259  
F3: PCI Header Registers for Audio Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261  
F3BAR0+Memory Offset: Audio Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 262  
F5: PCI Header Registers for X-Bus Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276  
F5BAR0+I/O Offset: X-Bus Expansion Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280  
PCIUSB: USB PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282  
USB_BAR+Memory Offset: USB Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285  
DMA Channel Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295  
DMA Page Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300  
Programmable Interval Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301  
Programmable Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303  
Keyboard Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306  
Real-Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307  
Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307  
Valid Mixing/Blending Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321  
Truth Table for Alpha Blending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323  
F4: PCI Header Registers for Video Processor Support Summary . . . . . . . . . . . . . . . . . . . 327  
F4BAR0: Video Processor Configuration Registers Summary . . . . . . . . . . . . . . . . . . . . . . 327  
F4BAR2: VIP Support Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329  
F4: PCI Header Registers for Video Processor Support Registers . . . . . . . . . . . . . . . . . . . 330  
F4BAR0+Memory Offset: Video Processor Configuration Registers . . . . . . . . . . . . . . . . . . 332  
F4BAR2+Memory Offset: VIP Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345  
JTAG Mode Instruction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349  
Electro Static Discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351  
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352  
Power Planes of External Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353  
System Conditions Used to Measure SC3200 Current During On State . . . . . . . . . . . . . . . 354  
DC Characteristics for On State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354  
DC Characteristics for Active Idle, Sleep, and Off States . . . . . . . . . . . . . . . . . . . . . . . . . . 355  
Ball Capacitance and Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355  
Balls with PU/PD Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356  
Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357  
Default Levels for Measurement of Switching Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 362  
Memory Controller Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364  
Video Input Port Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366  
TFT Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367  
ACCESS.bus Input Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368  
ACCESS.bus Output Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368  
PCI AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371  
PCI Clock Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373  
AMD Geode™ SC3200 Processor Data Book  
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11  
32581C  
List of Tables  
Table 9-19.  
Table 9-20.  
Table 9-21.  
Table 9-22.  
Table 9-23.  
Table 9-24.  
Table 9-25.  
Table 9-26.  
Table 9-27.  
Table 9-28.  
Table 9-29.  
Table 9-30.  
Table 9-31.  
Table 9-33.  
Table 9-34.  
Table 9-35.  
Table 9-36.  
Table 9-37.  
Table 9-38.  
Table 9-39.  
Table 9-40.  
Table 9-41.  
Table 9-42.  
Table 9-43.  
Table 9-44.  
Table 9-45.  
Table 10-1.  
Table 10-2.  
Table A-1.  
PCI Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374  
Measurement Condition Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375  
Sub-ISA Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377  
LPC and SERIRQ Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381  
IDE General Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382  
IDE Register Transfer to/from Device Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 383  
IDE PIO Data Transfer to/from Device Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 385  
IDE Multiword DMA Data Transfer Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387  
IDE UltraDMA Data Burst Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389  
USB Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400  
UART, Sharp-IR, SIR, and Consumer Remote Control Timing Parameters . . . . . . . . . . . . 404  
Fast IR Port Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405  
Standard Parallel Port Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406  
ECP Forward Mode Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408  
ECP Reverse Mode Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409  
AC Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410  
AC97 Sync Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410  
AC97 Clocks Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411  
AC97 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412  
AC97 Signal Rise and Fall Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413  
AC97 Low Power Mode Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414  
PWRBTN# Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415  
Power Management Event (GPWIO) and ONCTL# Timing Parameters . . . . . . . . . . . . . . . 415  
Power-Up Sequence Using the Power Button Timing Parameters . . . . . . . . . . . . . . . . . . . 416  
Power-Up Sequence Not Using the Power Button Timing Parameters . . . . . . . . . . . . . . . . 417  
JTAG Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418  
q
(×C/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421  
JC  
Case-to-Ambient Thermal Resistance Example @ 85×C . . . . . . . . . . . . . . . . . . . . . . . . . . 421  
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426  
12  
AMD Geode™ SC3200 Processor Data Book  
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Overview  
32581C  
1.0Overview  
1
1.1  
General Description  
The AMD Geode™ SC3200 processor is a member of the  
AMD Geode family of fully integrated x86 system chips.  
The SC3200 processor includes:  
• The Core Logic module includes: PC/AT functionality, a  
USB interface, an IDE interface, a PCI bus interface, an  
LPC bus interface, Advanced Configuration Power Inter-  
face (ACPI) version 1.0 compliant power management,  
and an audio codec interface.  
• The AMD Geode GX1 processor module combines  
advanced CPU performance with MMX™ support, fully  
accelerated 2D graphics, a 64-bit synchronous DRAM  
(SDRAM) interface, a PCI bus controller, and a display  
controller.  
• The SuperI/O module has: three serial ports (UART1,  
UART2, and UART3 with fast infrared), a parallel port,  
two ACCESS.bus (ACB) interfaces, and a real-time  
clock (RTC).  
• A low-power TFT Video Processor module with a Video  
Input Port (VIP), and a hardware video accelerator for  
scaling, filtering, and color space conversion.  
These features, combined with the device’s low power con-  
sumption, enable a small form factor design making it ideal  
as the core for a WebPAD™ system application.  
Figure 1-1 shows the relationships between the modules.  
GX1  
Video Processor  
Memory Controller  
Display  
Video  
Video  
Scaling  
Controller  
2D Graphics  
Accelerator  
TFT I/F  
Mixer  
CPU  
Core  
Config.  
Block  
PCI Bus  
Controller  
Video Input Port (VIP)  
Host Interface  
Fast-PCI Bus  
Clock & Reset Logic  
Fast X-Bus  
Parallel  
Port  
Core Logic  
IDE I/F  
USB  
RTC  
ACB1  
I/F  
Bridge  
PIT  
PIC  
ACB2  
I/F  
SuperI/O  
PCI/Sub-ISA  
Bus I/F  
DMAC  
UART1  
UART2  
GPIO  
Pwr Mgmnt  
Configuration  
ISA Bus I/F  
Audio Codec I/F  
LPC I/F  
ISA Bus  
I/F  
UART3  
& IR  
X-Bus  
Figure 1-1. Block Diagram  
AMD Geode™ SC3200 Processor Data Book  
13  
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32581C  
Overview  
1.2  
Features  
General Features  
Video Processor Module  
■ 32-Bit x86 processor, up to 266 MHz, with MMX instruc-  
■ Video Accelerator:  
tion set support  
— Flexible video scaling support of up to 800%  
(horizontally and vertically)  
— Bilinear interpolation filters (with two taps, and eight  
phases) to smooth output video  
■ Memory controller with 64-bit SDRAM interface  
■ 2D graphics accelerator  
■ Video/Graphics Mixer:  
■ CCIR-656 video input port with direct video for full  
— 8-bit value alpha blending  
— Three blending windows with constant alpha value  
— Color key  
screen display  
■ PC/AT functionality  
■ PCI bus controller  
■ Video Input Port (VIP):  
— Video capture or display  
■ IDE interface, two channels  
— CCIR-656 and VESA Video Interface Port v1.1  
compliant  
— Lock display timing to video input timing (GenLock)  
— Able to transfer video data into main memory  
— Direct video transfer for full screen display  
— Separate memory location for VBI  
■ USB, three ports, OHCI (OpenHost Controller Interface)  
version 1.0 compliant  
■ Audio, AC97/AMC97 version 2.0 compliant  
■ Virtual System Architecture (VSA) technology support  
■ Power management, ACPI (Advanced Configuration  
■ TFT Interface:  
Power Interface) version 1.0 compliant  
— Direct connection to TFT panels  
— 800x600 non-interlaced TFT @ 16 bpp graphics,  
up to 85 Hz  
— 1024x768 non-interlaced TFT @ 16 bpp graphics,  
up to 75 Hz  
■ Package:  
— BGU481 (481-Terminal Ball Grid Array Cavity Up)  
GX1 Processor Module  
— TFT on IDE: FPCLK max is 40 MHz  
— TFT on Parallel Port: FPCLK max is 80 MHz  
■ CPU Core:  
— 32-Bit x86, 266 MHz, with MMX compatible instruc-  
tion set support  
— 16 KB unified L1 cache  
— Integrated FPU (Floating Point Unit)  
— Re-entrant SMM (System Management Mode)  
enhanced for VSA  
Core Logic Module  
■ Audio Codec Interface:  
— AC97/AMC97 (Rev. 2.0) codec interface  
— Six DMA channels  
■ PC/AT Functionality:  
■ 2D Graphics Accelerator:  
— Programmable Interrupt Controller (PIC),  
8259A-equivalent  
— Programmable Interval Timer (PIT), 8254-equivalent  
— DMA Controller (DMAC), 8237-equivalent  
— Accelerates BitBLTs, line draw and text  
— Supports all 256 raster operations  
— Supports transparent BLTs  
— Runs at core clock frequency  
■ Power Management:  
■ Memory Controller:  
— ACPI v1.0 compliant  
— 64-Bit SDRAM interface  
— Sx state control of three power planes  
— Cx/Sx state control of clocks and PLLs  
— Thermal event input  
— Wakeup event support:  
– Three general-purpose events  
– AC97 codec event  
— 66 MHz to 100 MHz frequency range  
— Direct interface with CPU/cache, display controller  
and 2D graphic accelerator  
— Supports clock suspend and power-down/  
self-refresh  
— Up to two banks of SDRAM (8 devices total) or one  
SODIMM  
– UART2 RI# signal  
– Infrared (IR) event  
■ Display Controller:  
■ General Purpose I/Os (GPIOs):  
— Hardware graphics frame buffer compress/  
decompress  
— 27 multiplexed GPIO signals  
— Hardware cursor, 32x32 pixels  
■ Low Pin Count (LPC) Bus Interface:  
— Specification v1.0 compatible  
14  
AMD Geode™ SC3200 Processor Data Book  
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Overview  
32581C  
■ PCI Bus Interface:  
Other Features  
— PCI v2.1 compliant with wakeup capability  
— 32-Bit data path, up to 33 MHz  
— Glueless interface for an external PCI device  
— Fixed priority  
■ High-Resolution Timer:  
— 32-Bit counter with 1 μs count interval  
■ WATCHDOG Timer:  
— 3.3V signal support only  
— Interfaces to INTR, SMI, Reset  
■ Sub-ISA Bus Interface:  
■ Clocks:  
— Up to 16 MB addressing  
— Supports a chip select for ROM or Flash EPROM  
boot device  
— Input (external crystals):  
– 32.768 KHz (internal clock oscillator)  
– 27 MHz (internal clock oscillator)  
— Output:  
— Supports either:  
– M-Systems DiskOnChip DOC2000 Flash file  
system  
– NAND EEPROM  
– AC97 clock (24.576 MHz)  
– Memory controller clock (66 MHz to 100 MHz)  
– PCI clock (33 MHz)  
— Supports up to two chip selects for external I/O  
devices  
— 8-Bit (optional 16-bit) data bus width  
— Shares balls with PCI signals  
— Is not a subtractive agent  
■ JTAG Testability:  
— Bypass, Extest, Sample/Preload, IDcode, Clamp, HiZ  
■ Voltages  
— Internal logic: 266 or 233 MHz @ 1.8V  
— Standby logic: 266 or 233 MHz @ 1.8V  
— I/O: 3.3V  
— Standby I/O: 3.3V  
— Battery (if used): 3.0V  
■ IDE Interface:  
— Two IDE channels for up to four external IDE devices  
— Supports ATA-33 synchronous DMA mode transfers,  
up to 33 MB/s  
■ Universal Serial Bus (USB):  
— USB OpenHCI v1.0 compliant  
— Three ports  
SuperI/O Module  
■ Real-Time Clock (RTC):  
— DS1287, MC146818 and PC87911 compatible  
— Multi-century calendar  
■ ACCESS.bus (ACB) Interface:  
— Two ACB interface ports  
■ Parallel Port:  
— EPP 1.9 compliant  
— IEEE 1284 ECP compliant, including level 2  
■ Serial Port (UART):  
— UART1, 16550A compatible (SIN, SOUT, BOUT  
pins), used for SmartCard interface  
— UART2, 16550A compatible  
— Enhanced UART with fast Infrared (IR)  
AMD Geode™ SC3200 Processor Data Book  
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32581C  
Overview  
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AMD Geode™ SC3200 Processor Data Book  
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Architecture Overview  
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2.0Architecture Overview  
2
As illustrated in Figure 1-1 on page 13, the SC3200 pro-  
cessor contains the following modules in one integrated  
device:  
The SC3200 processor’s device ID is contained in the GX1  
module. Software can detect the revision by reading the  
DIR0 and DIR1 Configuration registers (see Configuration  
registers in the AMD Geode™ GX1 Processor Data Book).  
The AMD Geode™ SC3200 Specification Update docu-  
ment contains the specific values.  
• GX1 Module:  
— Combines advanced CPU performance with MMX  
support, fully accelerated 2D graphics, a 64-bit  
synchronous DRAM (SDRAM) interface and a PCI  
bus controller. Integrates GX1 silicon revision 8.1.1.  
2.1.1  
Memory Controller  
The GX1 module is connected to external SDRAM devices.  
For more information see Section 3.4.2 "Memory Interface  
Signals" on page 50, and the “Memory Controller” chapter  
in the AMD Geode™ GX1 Processor Data Book.  
• Video Processor Module:  
— A low-power TFT support module with a video input  
port, and a hardware video accelerator for scaling,  
filtering and color space conversion.  
There are some differences in the SC3200 processor’s  
memory controller and the stand-alone GX1 processor’s  
memory controller:  
• Core Logic Module:  
— Includes PC/AT functionality, an IDE interface, a  
Universal Serial Bus (USB) interface, ACPI v1.0  
compliant power management, and an audio codec  
interface.  
1) There is drive strength/slew control in the SC3200 that  
is not in the GX1. The bits that control this function are  
in the MC_MEM_CNTRL1 and MC_MEM_CNTRL2  
registers. In the GX1 processor, these bits are marked  
as reserved.  
• SuperI/O Module:  
— Includes two Serial Ports, an Infrared (IR) Port, a  
Parallel Port, two ACCESS.bus interfaces, and a  
Real-Time Clock (RTC).  
2) The SC3200 supports two banks of memory. The GX1  
supports four banks of memory. In addition, the  
SC3200 supports a maximum of eight devices and the  
GX1 supports up to 32 devices. With this difference,  
the MC_BANK_CFG register is different.  
2.1  
GX1 Module  
The GX1 processor (silicon revision 8.1.1) is the central  
module of the SC3200. For detailed information regarding  
the GX1 module, refer to the AMD Geode™ GX1 Proces-  
sor Data Book and the AMD Geode™ GX1 Processor Sili-  
con Revision 8.1.1 Specification Update documents.  
Table 2-1 summarizes the 32-bit registers contained in the  
SC3200 processor’s memory controller. Table 2-2 gives  
detailed register/bit formats.  
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Architecture Overview  
Reset Value  
Table 2-1. SC3200 Memory Controller Register Summary  
GX_BASE+  
Memory Offset  
Width  
(Bits)  
Type  
Name/Function  
8400h-8403h  
8404h-8407h  
8408h-840Bh  
840Ch-840Fh  
32  
32  
32  
32  
R/W  
R/W  
R/W  
R/W  
MC_MEM_CNTRL1. Memory Controller Control Register 1  
MC_MEM_CNTRL2. Memory Controller Control Register 2  
MC_BANK_CFG. Memory Controller Bank Configuration  
248C0040h  
00000801h  
41104110h  
2A733225h  
MC_SYNC_TIM1. Memory Controller Synchronous Timing  
Register 1  
8414h-8417h  
8418h-841Bh  
841Ch-841Fh  
32  
32  
32  
R/W  
R/W  
R/W  
MC_GBASE_ADD. Memory Controller Graphics Base  
Address Register  
00000000h  
00000000h  
0000000xh  
MC_DR_ADD. Memory Controller Dirty RAM Address  
Register  
MC_DR_ACC. Memory Controller Dirty RAM Access  
Register  
Table 2-2. SC3200 Memory Controller Registers  
Bit  
Description  
GX_BASE+ 8400h-8403h  
MC_MEM_CNTRL1 (R/W)  
Reset Value: 248C0040h  
31:30  
29  
MDCTL (MD[63:0] Drive Strength). 11 is strongest, 00 is weakest.  
RSVD (Reserved) Write as 0.  
28:27  
26  
MABACTL (MA[12:0] and BA[1:0] Drive Strength). 11 is strongest, 00 is weakest.  
RSVD (Reserved). Write as 0.  
25:24  
23:22  
21  
MEMCTL (RASA#, CASA#, WEA#, CS[1:0]#, CKEA, DQM[7:0] Drive Strength). 11 is strongest, 00 is weakest.  
RSVD (Reserved). Write as 0.  
RSVD (Reserved). Must be written as 0. Wait state on the X-Bus x_data during read cycles - for debug only.  
SDCLKRATE (SDRAM Clock Ratio). Selects SDRAM clock ratio.  
20:18  
000: Reserved  
001: ÷ 2  
100: ÷ 3.5  
101: ÷ 4  
010: ÷ 2.5  
011: ÷ 3 (Default)  
110: ÷ 4.5  
111: ÷ 5  
Ratio does not take effect until the SDCLKSTRT bit (bit 17 of this register) transitions from 0 to 1.  
17  
SDCLKSTRT (Start SDCLK). Start operating SDCLK using the new ratio and shift value (selected in bits [20:18] of this reg-  
ister).  
0: Clear.  
1: Enable.  
This bit must transition from zero (written to zero) to one (written to one) in order to start SDCLK or to change the shift value.  
16:8  
7:6  
RFSHRATE (Refresh Interval). This field determines the number of processor core clocks multiplied by 64 between refresh  
cycles to the DRAM. By default, the refresh interval is 00h. Refresh is turned off by default.  
RFSHSTAG (Refresh Staggering). This field determines number of clocks between the RFSH commands to each of the  
four banks during refresh cycles:  
00: 0 SDRAM clocks  
01: 1 SDRAM clocks (Default)  
10: 2 SDRAM clocks  
11: 4 SDRAM clocks  
Staggering is used to help reduce power spikes during refresh by refreshing one bank at a time. If only one bank is installed,  
this field must be written as 00.  
5
2CLKADDR (Two Clock Address Setup). Assert memory address for one extra clock before CS# is asserted.  
0: Disable.  
1: Enable.  
This can be used to compensate for address setup at high frequencies and/or high loads.  
18  
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Architecture Overview  
32581C  
Table 2-2. SC3200 Memory Controller Registers (Continued)  
Bit  
Description  
4
3
RFSHTST (Test Refresh). This bit, when set high, generates a refresh request. This bit is only used for testing purposes.  
XBUSARB (X-Bus Round Robin). When round robin is enabled, processor, graphics pipeline, and low priority display con-  
troller requests are arbitrated at the same priority level. When disabled, processor requests are arbitrated at a higher priority  
level. High priority Display Controller requests always have the highest arbitration priority.  
0: Disable.  
1: Enable round robin.  
2
SMM_MAP (SMM Region Mapping). Maps the SMM memory region at GX_BASE+400000 to physical address A0000 to  
BFFFF in SDRAM.  
0: Disable.  
1: Enable.  
1
0
RSVD (Reserved). Write as 0.  
SDRAMPRG (Program SDRAM). When this bit is set, the memory controller will program the SDRAM MRS register using  
LTMODE in MC_SYNC_TIM1.  
This bit must transition from zero (written to zero) to one (written to one) in order to program the SDRAM devices.  
GX_BASE+8404h-8407h  
MC_MEM_CNTRL2 (R/W)  
Reset Value: 00000801h  
31:14  
13:12  
RSVD (Reserved). Write as 0.  
SDCLKCTL (SDCLK High Drive/Slew Control). Controls the high drive and slew rate of SDCLK[3:0] and SDCLK_OUT.  
11 is strongest, 00 is weakest.  
11  
10  
RSVD (Reserved). Write as 0.  
SDCLKOMSK# (Enable SDCLK_OUT). Turns on the output.  
0: Enable.  
1: Disable.  
9
8
SDCLK3MSK# (Enable SDCLK3). Turns on the output.  
0: Enable.  
1: Disable.  
SDCLK2MSK# (Enable SDCLK2). Turns on the output.  
0: Enable.  
1: Disable.  
7
SDCLK1MSK# (Enable SDCLK1). Turns on the output. 0  
0: Enable.  
1: Disable.  
6
SDCLK0MSK# (Enable SDCLK0). Turns on the output.  
0: Enable.  
1: Disable.  
5:3  
SHFTSDCLK (Shift SDCLK). This function allows shifting SDCLK to meet SDRAM setup and hold time requirements. The  
shift function will not take effect until the SDCLKSTRT bit (bit 17 of MC_MEM_CNTRL1) transitions from 0 to 1:  
000: No shift  
100: Shift 2 core clocks  
101: Shift 2.5 core clocks  
110: Shift 3 core clocks  
111: Reserved  
001: Shift 0.5 core clock  
010: Shift 1 core clock  
011: Shift 1.5 core clock  
2
1
RSVD (Reserved). Write as 0.  
RD (Read Data Phase). Selects if read data is latched one or two core clock after the rising edge of SDCLK.  
0: 1 Core clock.  
1: 2 Core clocks.  
0
FSTRDMSK (Fast Read Mask). Do not allow core reads to bypass the request FIFO.  
0: Disable.  
1: Enable.  
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32581C  
Architecture Overview  
Reset Value: 41104110h  
Table 2-2. SC3200 Memory Controller Registers (Continued)  
Bit  
Description  
GX_BASE+8408h-840Bh  
MC_BANK_CFG (R/W)  
31:16  
15  
RSVD (Reserved). Write as 0070h  
RSVD (Reserved). Write as 0.  
14  
SODIMM_MOD_BNK (SODIMM Module Banks - Banks 0 and 1). Selects number of module banks installed per SODIMM  
for SODIMM:  
0: 1 Module bank (Bank 0 only)  
1: 2 Module banks (Bank 0 and 1)  
13  
12  
RSVD (Reserved). Write as 0.  
SODIMM_COMP_BNK (SODIMM Component Banks - Banks 0 and 1). Selects the number of component banks per  
module bank for SODIMM:  
0: 2 Component banks  
1: 4 Component banks  
Banks 0 and 1 must have the same number of component banks.  
RSVD (Reserved). Write as 0.  
11  
10:8  
SODIMM_SZ (SODIMM Size - Banks 0 and 1). Selects the size of SODIMM:  
000: 4 MB  
001: 8 MB  
010: 16 MB  
011: 32 MB  
100: 64 MB  
101: 128 MB  
110: 256 MB  
111: 512 MB  
This size is the total of both banks 0 and 1. Also, banks 0 and 1 must be the same size.  
RSVD (Reserved). Write as 0.  
7
6:4  
SODIMM_PG_SZ (SODIMM Page Size - Banks 0 and 1). Selects the page size of SODIMM:  
000: 1 KB  
001: 2 KB  
010: 4 KB  
011: 8 KB  
1xx: 16 KB  
111: SODIMM not installed  
Both banks 0 and 1 must have the same page size.  
3:0  
RSVD (Reserved). Write as 0.  
GX_BASE+840Ch-840Fh  
MC_SYNC_TIM1 (R/W)  
Reset Value: 2A733225h  
31  
RSVD (Reserved). Write as 0.  
30:28  
LTMODE (CAS Latency). CAS latency is the delay, in SDRAM clock cycles, between the registration of a read command  
and the availability of the first piece of output data. This parameter significantly affects system performance. Optimal setting  
should be used. If an SODIMM is used, BIOS can interrogate EEPROM across the ACCESS.bus interface to determine this  
value:  
000: Reserved  
001: Reserved  
010: 2 CLK  
011: 3 CLK  
100: 4 CLK  
101: 5 CLK  
110: 6 CLK  
111: 7 CLK  
This field will not take effect until SDRAMPRG (bit 0 of MC_MEM_CNTRL1) transitions from 0 to 1.  
27:24  
23:20  
RC (RFSH to RFSH/ACT Command Period, tRC). Minimum number of SDRAM clock between RFSH and RFSH/ACT  
commands:  
0000: Reserved  
0001: 2 CLK  
0010: 3 CLK  
0011: 4 CLK  
0100: 5 CLK  
0101: 6 CLK  
0110: 7 CLK  
0111: 8 CLK  
1000: 9 CLK  
1001: 10 CLK  
1010: 11 CLK  
1011: 12 CLK  
1100: 13 CLK  
1101: 14 CLK  
1110: 15 CLK  
1111: 16 CLK  
RAS (ACT to PRE Command Period, tRAS). Minimum number of SDRAM clocks between ACT and PRE commands:  
0000: Reserved  
0001: 2 CLK  
0010: 3 CLK  
0011: 4 CLK  
0100: 5 CLK  
0101: 6 CLK  
0110: 7 CLK  
0111: 8 CLK  
1000: 9 CLK  
1001: 10 CLK  
1010: 11 CLK  
1011: 12 CLK  
1100: 13 CLK  
1101: 14 CLK  
1110: 15 CLK  
1111: 16 CLK  
19  
RSVD (Reserved). Write as 0.  
RP (PRE to ACT Command Period, tRP). Minimum number of SDRAM clocks between PRE and ACT commands:  
18:16  
000: Reserved  
001: 1 CLK  
010: 2 CLK  
011: 3 CLK  
100: 4 CLK  
101: 5 CLK  
110: 6 CLK  
111: 7 CLK  
15  
RSVD (Reserved). Write as 0.  
14:12  
RCD (Delay Time ACT to READ/WRT Command, tRCD). Minimum number of SDRAM clock between ACT and READ/  
WRT commands. This parameter significantly affects system performance. Optimal setting should be used:  
000: Reserved  
001: 1 CLK  
010: 2 CLK  
011: 3 CLK  
100: 4 CLK  
101: 5 CLK  
110: 6 CLK  
111: 7 CLK  
20  
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32581C  
Table 2-2. SC3200 Memory Controller Registers (Continued)  
Bit  
Description  
11  
RSVD (Reserved). Write as 0.  
10:8  
RRD (ACT(0) to ACT(1) Command Period, tRRD). Minimum number of SDRAM clocks between ACT and ACT command  
to two different component banks within the same module bank. The memory controller does not perform back-to-back Acti-  
vate commands to two different component banks without a READ or WRITE command between them. Hence, this field  
should be written as 001.  
7
RSVD (Reserved). Write as 0.  
6:4  
DPL (Data-in to PRE command period, tDPL). Minimum number of SDRAM clocks from the time the last write datum is  
sampled till the bank is precharged:  
000: Reserved  
001: 1 CLK  
010: 2 CLK  
011: 3 CLK  
100: 4 CLK  
101: 5 CLK  
110: 6 CLK  
111: 7 CLK  
3:0  
RSVD (Reserved). Leave unchanged. Always returns a 101h.  
Note: Refer to the SDRAM manufacturer’s specification for more information on component banks.  
GX_BASE+8414h-8417h MC_GBASE_ADD (R/W)  
Reset Value: 00000000h  
31:18  
17  
RSVD (Reserved). Write as 0.  
TE (Test Enable TEST[3:0]).  
0: TEST[3:0] are driven low (normal operation).  
1: TEST[3:0] pins are used to output test information  
16  
TECTL (Test Enable Shared Control Pins).  
0: RASB#, CASB#, CKEB, WEB# (normal operation).  
1: RASB#, CASB#, CKEB, WEB# are used to output test information  
15:12  
11  
SEL (Select). This field is used for debug purposes only and should be left at zero for normal operation.  
RSVD (Reserved). Write as 0.  
10:0  
GBADD (Graphics Base Address). This field indicates the graphics memory base address, which is programmable on 512  
KB boundaries. This field corresponds to address bits [29:19].  
Note that BC_DRAM_TOP must be set to a value lower than the Graphics Base Address.  
GX_BASE+8418h-841Bh  
MC_DR_ADD (R/W)  
Reset Value: 00000000h  
31:10  
9:0  
RSVD (Reserved). Write as 0.  
DRADD (Dirty RAM Address). This field is the address index that is used to access the Dirty RAM with the MC_DR_ACC  
register. This field does not auto increment.  
GX_BASE+841Ch-841Fh  
MC_DR_ACC (R/W)  
Reset Value: 0000000xh  
31:2  
1
RSVD (Reserved). Write as 0.  
D (Dirty Bit). This bit is read/write accessible.  
V (Valid Bit). This bit is read/write accessible.  
0
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Architecture Overview  
2.1.2  
Fast-PCI Bus  
2.2.1  
GX1 Module Interface  
The GX1 module communicates with the Core Logic mod-  
ule via a Fast-PCI bus that can work at up to 66 MHz. The  
Fast-PCI bus is internal for the SC3200 and is connected to  
the General Configuration Block (see Section 4.0 on page  
69 for details on the General Configuration Block).  
The Video Processor is connected to the GX1 module in  
the following way:  
• The Video Processor’s DOTCLK output signal is used as  
the GX1 module’s DCLK input signal.  
• The GX1 module’s PCLK output signal is used as the  
This bus supports seven bus masters. The requests  
(REQs) are fixed in priority. The seven bus masters in order  
of priority are:  
GFXCLK input signal of the Video Processor.  
2.2.2  
Video Input Port  
1) VIP  
The Video Input Port (VIP) within the Video Processor con-  
tains a standard interface that is typically connected to a  
media processor or TV encoder. The clock is supplied by  
the externally connected device; typically at 27 MHz.  
2) IDE Channel 0  
3) IDE Channel 1  
4) Audio  
Video input can be sent to the GX1 module’s video frame  
buffer (Capture Video mode) or can be used directly (Direct  
Video mode).  
5) USB  
6) External REQ0#  
7) External REQ1#  
2.2.3  
Core Logic Module Interface  
The Video Processor interfaces to the Core Logic module  
for accessing PCI function configuration registers.  
2.1.3  
Display  
The GX1 module generates display timing, and controls  
internal VSYNC and HSYNC signals of the Video Proces-  
sor module.  
2.3  
Core Logic Module  
The Core Logic module is described in detail in Section 6.0  
"Core Logic Module" on page 139.  
The GX1 module interfaces with the Video Processor via a  
video data bus and a graphics data bus.  
The Core Logic module is connected to the Fast-PCI bus. It  
uses signal AD28 as the IDSEL for all PCI configuration  
functions except for USB which uses AD29.  
• Video data. The GX1 module uses the core clock,  
divided by 2 or 4 (typically 100 - 133 MHz). It drives the  
video data using this clock. Internal signals VID_VAL  
and VID_RDY are used as data-flow handshake signals  
between the GX1 module and the Video Processor.  
2.3.1  
Other Core Logic Module Interfaces  
The following interfaces of the Core Logic module are  
implemented via external balls of the SC3200. Each inter-  
face is listed below with a reference to the descriptions of  
the relevant balls.  
• Graphics data. The GX1 module uses the internal  
signal DCLK, supplied by the PLL of the Video  
Processor, to drive the 18-bit graphics-data bus of the  
Video Processor. Each six bits of this bus define a  
different color. Each of these 6-bit color definitions is  
expanded (by adding two zero LSB lines) to form an 8-  
bit bus, at the Video Processor.  
• IDE: See Section 3.4.9 "IDE Interface Signals" on page  
58.  
• AC97: See Section 3.4.14 "AC97 Audio Interface  
For more information about the GX1 module’s interface to  
the Video Processor, see the “Display Controller” chapter  
in the AMD Geode™ GX1 Processor Data Book.  
Signals" on page 63.  
• PCI: See Section 3.4.6 "PCI Bus Interface Signals" on  
page 53.  
• USB: See Section 3.4.10 "Universal Serial Bus (USB)  
Interface Signals" on page 59. The USB function uses  
signal AD29 as the IDSEL for PCI configuration.  
2.2  
Video Processor Module  
The Video Processor provides high resolution and graphics  
for a TFT/DSTN interface. The following subsections pro-  
vide a summary of how the Video Processor interfaces with  
the other modules of the SC3200. For detailed information  
about the Video Processor, see Section 7.0 "Video Proces-  
sor Module" on page 309.  
• LPC: See Section 3.4.8 "Low Pin Count (LPC) Bus Inter-  
face Signals" on page 58.  
22  
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• Sub-ISA: See Section 3.4.7 "Sub-ISA Interface Signals"  
on page 57, Section 6.2.5 "Sub-ISA Bus Interface" on  
page 145, and Section 4.2 "Multiplexing, Interrupt Selec-  
tion, and Base Address Registers" on page 70  
The SIO module incorporates: two Serial Ports, an Infrared  
Communication Port that supports FIR, MIR, HP-SIR,  
Sharp-IR, and Consumer Electronics-IR, a full IEEE 1284  
Parallel Port, two ACCESS.bus Interface (ACB) ports, Sys-  
tem Wakeup Control (SWC), and a Real-Time Clock (RTC)  
that provides RTC timekeeping.  
• GPIO: See Section 3.4.16 "GPIO Interface Signals" on  
page 65.  
• More detailed information about each of these interfaces  
is provided in Section 6.2 "Module Architecture" on page  
140.  
2.5  
Clock, Timers, and Reset Logic  
In addition to the four main modules (i.e., GX1, Core Logic,  
Video Processor and SIO) that make up the SC3200, the  
following blocks of logic have also been integrated into the  
SC3200:  
• Super/IO Block Interfaces: See Section 4.2 "Multi-  
plexing, Interrupt Selection, and Base Address Regis-  
ters" on page 70, Section 3.4.5 "ACCESS.bus Interface  
Signals" on page 52, Section 3.4.13 "Fast Infrared (IR)  
Port Interface Signals" on page 62, and Section 3.4.12  
"Parallel Port Interface Signals" on page 61.  
• Clock Generators as described in Section 4.5 "Clock  
Generators and PLLs" on page 81.  
• Configuration Registers as described in Section 4.2  
"Multiplexing, Interrupt Selection, and Base Address  
Registers" on page 70.  
The Core Logic module interface to the GX1 module con-  
sists of seven miscellaneous connections, the PCI bus  
interface signals, plus the display controller connections.  
Note that the PC/AT legacy signals NMI, WM_RST, and  
A20M are all virtual functions executed in SMM (System  
Management Mode) by the BIOS.  
• A WATCHDOG timer as described in Section 4.3  
"WATCHDOG" on page 77.  
• A High-Resolution timer as described in Section 4.4  
"High-Resolution Timer" on page 79.  
• PSERIAL is a one-way serial bus from the GX1 to the  
Core Logic module used to communicate power-  
management states and VSYNC information for VGA  
emulation.  
2.5.1  
Reset Logic  
This section provides a description of the reset flow of the  
SC3200.  
• IRQ13 is an input from the GX1 module indicating that a  
floating point error was detected and that INTR should  
be asserted.  
2.5.1.1 Power-On Reset  
Power-on reset is triggered by assertion of the POR# sig-  
nal. Upon power-on reset, the following things happen:  
• INTR is the level output from the integrated 8259A PICs  
and is asserted if an unmasked interrupt request (IRQn)  
is sampled active.  
• Strap balls are sampled.  
• PLL4, PLL5, and PLL6 are reset, disabling their output.  
When the POR# signal is negated, the clocks lock and  
then each PLL outputs its clock. PLL6 is the last clock  
generator to output a clock. See Section 4.5 "Clock  
Generators and PLLs" on page 81.  
• SMI# is a level-sensitive interrupt to the GX1 module  
that can be configured to assert on a number of different  
system events. After an SMI# assertion, SMM is entered  
and program execution begins at the base of the SMM  
address space. Once asserted, SMI# remains active  
until the SMI source is cleared.  
• Certain WATCHDOG and High-Resolution Timer  
register bits are cleared.  
• SUSP# and SUSPA# are handshake signals for imple-  
menting CPU Clock Stop and clock throttling.  
2.5.1.2 System Reset  
• CPU_RST resets the CPU and is asserted for approxi-  
System reset causes signal PCIRST# to be issued, thus  
triggering a reset of all PCI and LPC agents. A system  
reset is triggered by any of the following events:  
mately 100 µs after the negation of POR#.  
• PCI bus interface signals.  
• Power-on, as indicated by POR# signal assertion.  
2.4  
Super I/O Module  
• A WATCHDOG reset event (see Section 4.3.2  
"WATCHDOG Registers" on page 78).  
The SuperI/O (SIO) module is a PC98 and ACPI compliant  
SIO that offers a single-cell solution to the most commonly  
used ISA peripherals.  
• Software initiated system reset.  
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32581C  
Architecture Overview  
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Signal Definitions  
32581C  
3.0Signal Definitions  
3
This section defines the signals and describes the external  
interface of the SC3200. Figure 2-1 shows the signals  
organized by their functional groups. Where signals are  
multiplexed, the default signal name is listed first and is  
separated by a plus sign (+). A slash (/) in a signal name  
means that the function is always enabled and available  
(i.e., cycle multiplexed).  
POR#  
X32I  
X32O  
X27I  
X27O  
PCIRST#  
BOOT16+ROMCS#  
System  
Interface  
LPC_ROM+PCICLK1  
TFT_PRSNT+SDATA_OUT  
FPCI_MON+PCICLK0  
IDE_ADDR2+TFTD4  
Straps  
IDE_ADDR1+TFTD2  
IDE_ADDR0+TFTD3  
IDE_DATA15+TFTD7  
DID0+GNT0#, DID1+GNT1#  
IDE_DATA14+TFTD17  
IDE_DATA13+TFTD15  
IDE_DATA12+TFTD13  
IDE_DATA11+GPIO41  
IDE_DATA10  
MD[63:0]  
MA[12:0]  
BA[1:0]  
CS[1:0]#  
RASA#  
CASA#  
WEA#  
DQM[7:0]  
CKEA  
SDCLK[3:0]  
SDCLK_IN  
SDCLK_OUT  
AMD Geode™  
SC3200  
Processor  
IDE_DATA9  
IDE_DATA8+GPIO40  
IDE_DATA7+INTD#  
IDE_DATA6+IRQ9  
Memory  
Interface  
IDE_DATA5+CLK27M  
IDE_DATA4+FP_VDD_ON  
IDE_DATA3+TFTD12  
IDE_DATA2+TFTD14  
IDE_DATA1+TFTD16  
IDE_DATA0+TFTD6  
IDE/TFT  
Interface  
AB1C+GPIO20+DOCCS#  
AB1D+GPIO1+IOCS1#  
GPIO12+AB2C  
IDE_IOR0#+TFTD10  
IDE_IOW0#+TFTD9  
IDE_CS0#+TFTD5  
IDE_CS1#+TFTDE  
IDE_IORDY0+TFTD11  
IDE_DREQ0+TFTD8  
ACCESS.bus  
Interface  
GPIO13+AB2D  
ACK#+TFTDE  
IDE_DACK0#+TFTD0  
IDE_RST#+TFTDCK  
IRQ14+TFTD1  
AFD#/DSTRB#+TFTD2  
BUSY/WAIT#+TFTD3  
ERR#+TFTD4  
INIT#+TFTD5  
PD7+TFTD13  
PD6+TFTD1  
PD[5:0]+TFTD[11:6]  
PE+TFTD14  
Parallel Port/  
TFT Interface  
SLCT+TFTD15  
SLIN#/ASTRB#+TFTD16  
STB#/WRITE#+TFTD17  
VPD[7:0]  
VPCKIN  
Video Port  
Interface  
Note:  
Straps are not the default signal, shown with system signals for reader convenience. However, also listed in figure with the  
appropriate functional group.  
Figure 3-1. Signal Groups  
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32581C  
Signal Definitions  
POWER_EN  
PCICLK0+FPCI_MON  
PCICLK1+LPC_ROM  
PCICLK  
OVER_CUR#  
DPOS_PORT1  
DNEG_PORT1  
DPOS_PORT2  
DNEG_PORT2  
DPOS_PORT3  
DNEG_PORT3  
USB  
Interface  
INTA#, INTB#  
FRAME#  
AMD Geode™  
SC3200  
Processor  
LOCK#  
PERR#  
SERR#  
REQ[1:0]#  
GNT0#+DID0  
GNT1#+DID1  
A[23:0]/AD[23:0]  
D[7:0]/AD[31:24]  
D[11:8]/C/BE[3:0]#  
D12/PAR  
D13/TRDY#  
D14/IRDY#  
D15/STOP#  
BHE#/DEVSEL#  
SIN1  
SIN2+SDTEST3  
SOUT1+CLKSEL1  
SOUT2+CLKSEL2  
GPIO7+RTS2#+IDE_DACK1#+SDTEST0  
GPIO8+CTS2#+IDE_DREQ1+SDTEST4  
GPIO18+DTR1#/BOUT1  
GPIO6+DTR2#/BOUT2+IDE_IOR1#+SDTEST5  
GPIO11+RI2#+IRQ15  
GPIO9+DCD2#+IDE_IOW1#+SDTEST2  
Sub-ISA/PCI Bus  
Interface  
Serial Ports  
(UARTs)/IDE  
Interface  
GPIO17+TFTDCK+IOCS0#  
GPIO1+IOCS1+TFTD12  
ROMCS#/BOOT16  
GPIO10+DSR2#+IDE_IORDY1+SDTEST1  
IR Port  
Interface  
IRRX1+SIN3  
IRTX+SOUT3  
GPIO20+DOCCS#+TFTD0  
RD#+CLKSEL0  
WR#  
GPIO14+DOCR#+IOR#  
GPIO15+DOCW#+IOW#  
GPIO0+TRDE#  
BIT_CLK  
SDATA_OUT+TFT_PRSNT  
SDATA_IN  
GPIO19+INTC#+IOCHRDY  
AC97 Audio  
Interface  
SDATA_IN2  
SYNC+CLKSEL3  
AC97_CLK  
AC97_RST#  
GPIO32+LAD0  
GPIO33+LAD1  
GPIO16+PC_BEEP  
GPIO34+LAD2  
GPIO35+LAD3  
GPIO36+LDRQ#  
GPIO/LPC Bus  
Interface  
CLK32  
GPWIO[2:0]  
LED#  
ONCTL#  
PWRBTN#  
PWRCNT[1:2]  
THRM#  
GPIO37+LFRAME#  
GPIO38+IRRX2+LPCPD  
GPIO39+SERIRQ  
Power  
Management  
Interface  
TEST1+PLL6B  
TEST0+PLL2B  
GXCLK+FP_VDD_ON+TEST3  
TEST2+PLL5B  
GTEST  
Test and  
Measurement  
Interface  
TCK  
TDI  
TDO  
TMS  
TRST#  
JTAG  
Interface  
TDP, TDN  
Figure 3-1. Signal Groups (Continued)  
The remaining subsections of this chapter describe:  
• Section 3.3 "Multiplexing Configuration": Lists multi-  
plexing options and their configurations.  
• Section 3.1 "Ball Assignments": Provides a ball assign-  
ment diagram and tables listing the signals sorted  
according to ball number and alphabetically by signal  
name.  
• Section 3.4 "Signal Descriptions": Detailed descriptions  
of each signal according to functional group.  
• Section 3.2 "Strap Options": Several balls are read at  
power-up that set up the state of the SC3200. This  
section provides details regarding those balls.  
26  
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Signal Definitions  
32581C  
Table 3-1. Signal Definitions Legend  
3.1  
Ball Assignments  
The SC3200 is highly configurable as illustrated in Figure  
3-1 on page 25. Strap options and register programming  
are used to set various modes of operation and specific  
signals on specific balls. This section describes which sig-  
nals are available on which balls and provides configuration  
information:  
Mnemonic  
Definition  
A
Analog  
AV  
Ground ball: Analog  
SS  
AV  
Power ball: Analog  
CC  
• Figure 3-2 on page 28: Illustrates the BGU481 ball  
GCB  
General Configuration Block registers.  
Refer to Section 4.0 "General Configura-  
tion Block" on page 69.  
assignments.  
• Table 3-2 on page 29: Lists signals according to ball  
number. Power Rail, Signal Type, Buffer Type and,  
where relevant, Pull-Up or Pull-Down resistors are indi-  
cated for each ball in this table. For multiplexed balls, the  
necessary configuration for each signal is listed as well.  
Location of the General Configuration  
Block cannot be determined by software.  
See the AMD Geode™ SC3200 Specifi-  
cation Update document.  
I
Input ball  
• Table 3-3 on page 40: Quick reference signal list sorted  
alphabetically - listing all signal names and ball  
numbers.The tables in this chapter use several common  
abbreviations. Table 3-1 lists the mnemonics and their  
meanings  
I/O  
Bidirectional ball  
MCR[x]  
Miscellaneous Configuration Register  
Bit x: A register, located in the GCB.  
Refer to Section 4.1 "Configuration  
Block Addresses" on page 69 for further  
details.  
Notes:  
1) For each GPIO signal, there is an optional pull-up  
resistor on the relevant ball. After system reset, the  
pull-up is present.  
O
Output ball  
OD  
Open-drain  
This pull-up resistor can be disabled via registers in  
the Core Logic module. The configuration is without  
regard to the selected ball function (except for  
GPIO12, GPIO13, and GPIO16). Alternate functions  
for GPIO12, GPIO13, and GPIO16 control pull-up  
resistors.  
PD  
Pull-down in KΩ  
PMR[x]  
Pin Multiplexing Register Bit x: A regis-  
ter, located in the GCB, used to config-  
ure balls with multiple functions. Refer to  
Section 4.1 "Configuration Block  
Addresses" on page 69 for further  
details.  
For more information, see Section 6.4.1 "Bridge,  
GPIO, and LPC Registers - Function 0" on page 188.  
PU  
TS  
Pull-up in KΩ  
TRI-STATE  
2) Configuration settings listed in this table are with  
regard to the Pin Multiplexing Register (PMR). See  
Section 4.2 "Multiplexing, Interrupt Selection, and  
Base Address Registers" on page 70 for a detailed  
description of this register.  
V
V
V
#
Power ball: 1.2V  
CORE  
Power ball: 3.3V  
Ground ball  
IO  
SS  
The # symbol in a signal name indicates  
that the active or asserted state occurs  
when the signal is at a low voltage level.  
Otherwise, the signal is asserted when  
at a high voltage level.  
/
A / in a signal name indicates both func-  
tions are always enabled (i.e., cycle mul-  
tiplexed).  
+
A + in signal name indicates the function  
is available on the ball, but that either  
strapping options or register program-  
ming is required to select the desired  
function.  
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32581C  
Signal Definitions  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31  
S
A
B
A
VSS  
VSS  
VIO AD30 PCK0 REQ1# PRST# PCICK IOW# GP20 GP17 HSNC VIO VSS  
S
NC  
NC  
NC  
VSS VPLL2 PD7 VSS PD6 PD1 STB# NC  
NC  
NC D+P3 D-P3 D+P1 D-P1 VIO  
NC D+P2 D-P2 GP10 VSS  
VSS  
VIO  
B
VIO AD29 AD28 REQ0# AD23 VSS RD# WR# VSS VSNC NC  
VIO  
VSS  
VIO BUSY ACK# VIO SLIN# INIT# VSS  
NC  
NC  
VSS VSS  
S
S
S
C
C
AD26 AD24 VIO AD25 GNT0# GNT1# VIO RMCS# GP19 VIO IRTX VSS  
S
VIO  
VSS VSS AVSSP2 SLCT PD4 PD5 PD3 PD0 VIO  
VIO VIO NC PE VIO  
NC  
NC  
VIO INTB# AVSSUSB GP9 VIO GP7 GP8  
S
D
D
AD21 AD22 AD20 AD27 AD31 PCK1 VSS FRM# IOR# GP1 TRDE# VCORE VSS  
VSS PD2 ERR# AFD# VIO  
VSS INTA# AVCCUSB GP6 SOUT TDP TDN  
E
E
AD16 AD19 AD18 DVSL#  
SIN2 TRST# TDO TCK  
TMS TDI GTST VPCKI  
F
F
TRDY# IRDY# CBE2# AD17  
G
G
VSS  
VIO  
VSS VPD7  
STOP# VSS  
VIO  
VSS  
H
H
VPD6 VPD5 VPD4 VPD3  
VPD2 VPD1 VPD0 GP39  
SRR# PRR# LOCK# CBE3#  
AD13 CBE1# AD15 PAR  
J
J
AMD Geode™  
SC3200 Processor  
K
K
AD11 VIO  
VSS AD14  
GP38 VIO  
GP36 GP35 GP34 GP33  
GP32 GP13 VIO VSS  
VSS GP12 AB1D AB1C  
VSS GP37  
L
L
CBE0# AD9 AD10 AD12  
VSS AD7 VIO AD8  
AD3 AD6 AD5 VSS  
AD4 ICS1# AD1 VCORE  
VSS VSS VSS VSS  
VCORE VCORE VCORE VCORE  
AD0 IAD2 AD2 VCORE  
IDAT15 IDAT14 IDAT13 VSS  
M
M
N
N
VCORE VCORE VSS VSS VSS VCORE VCORE  
VCORE VCORE VSS VSS VSS VCORE VCORE  
VSS VSS VSS VSS VSS VSS VSS  
VSS VSS VSS VSS VSS VSS VSS  
VSS VSS VSS VSS VSS VSS VSS  
VCORE VCORE VSS VSS VSS VCORE VCORE  
VCORE VCORE VSS VSS VSS VCORE VCORE  
S
S
P
P
VCORE SDO SYNC ACCK  
VSS VSS VSS VSS  
VCORE VCORE VCORE VCORE  
VCORE ACRST# BITCK SDI  
VSS SDCK3 GXCK GP16  
R
R
T
T
U
U
V
V
W
Y
W
Y
VIO  
VSS IDAT12 IDAT11  
MD57 SDCK1 VSS  
VIO  
IDAT10 IDAT9 IDAT8 IIOR0#  
IRST# IDAT7 IDAT6 IDAT5  
MD58 MD59 MD60 MD56  
SDCK2 MD61 MD62 MD63  
AA  
AB  
AC  
AD  
AE  
AF  
AG  
AH  
AJ  
AK  
AL  
AA  
AB  
AC  
AD  
AE  
AF  
AG  
AH  
AJ  
AK  
AL  
MD24 VIO  
VSS DQM7  
IDAT4 VSS  
VIO IDAT3  
IDAT1 IDAT2 IDAT0 IDRQ0  
IIORY0 IIOW0# IAD0 IDACK0#  
MD25 MD26 MD27 DQM3  
MD52 MD29 MD30 MD31  
VSS  
VIO  
VSS MD28  
IAD1 VSS  
VIO  
S
VSS  
(Top View)  
MD50 MD49 MD54 MD53  
MD21 DQM6 DQM2 MD55  
IRQ14 ICS0# SOUT1 OVRCUR#  
GP18 SIN1 X27I TEST1  
PWRE X27O TEST0 VIO PBTN# GPW0 VSS CK32 POR# MD3 MD5 WEA# VSS  
VIO MA1 MD34 MD37 VIO  
VSS MD41 MA9 MA8 DQM1 MD13 VSS MA11 CS1# MD18 MD48 MD20 MD51  
TEST2 X32I X32O VPLL3 ONCT# GPW2 VIO GP11 MD0 VIO MD6 CASA# BA0 MA10 MD32 MD33 MD36 MD47 MD45 MD42 SDCK0 VIO MA6 MA3 VIO MD11 SDCKI MD19 VIO MD22 MD17  
VIO  
VSS  
1
VSS AVSSP3 THRM#GPW1 PCNT1 VSS IRRX1 MD1 VSS MD7 RASA# VIO  
BA1 MA2 VIO MD35 MD46 VIO MD43 DQM5 VSS MA5 MD15 VSS MD14 MD12 SDCKO MD16 VSS  
VIO  
VIO VBAT LED# VSB VSBL PCNT2SDATI2 MD2 MD4 DQM0 CS0# VSS MA0 DQM4 VSS MD38 MD39 VSS MD44 MD40 CKEA MA7 MA4 MD8 MD10 MD9 MA12 MD23 VIO  
VSS  
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31  
Note: Signal names have been abbreviated in this figure due to space constraints.  
= GND Ball  
= PWR Ball  
= Strap Option Ball  
S
= Multiplexed Ball  
Figure 3-2. BGU481 Ball Assignment Diagram  
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Signal Definitions  
Ball  
32581C  
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number  
1
1
I/O  
Buffer Power  
Rail Configuration  
Ball  
No.  
I/O  
Buffer Power  
No.  
A1  
A2  
A3  
Signal Name  
(PU/PD) Type  
Signal Name  
(PU/PD) Type  
Rail Configuration  
5, 2  
5, 2  
5, 2  
3
V
V
GND  
PWR  
I/O  
---  
---  
---  
---  
---  
PD6  
I/O  
O
IN ,  
V
V
V
SS  
IO  
A20  
A21  
A22  
T
IO  
IO  
IO  
PMR[23] = 0 and  
(PMR[27] = 0 and  
FPCI_MON = 0)  
O
14/14  
---  
AD30  
IN  
,
V
Cycle Multiplexed  
3
PCI  
IO  
TFTD1  
O
1/4  
PMR[23] = 1 and  
O
PCI  
(PMR[27] = 0 and  
FPCI_MON = 0  
D6  
I/O  
IN  
O
,
PCI  
PCI  
3
F_AD6  
O
O
14/14  
PMR[23] = 0 and  
(PMR[27] = 1 or  
FPCI_MON = 1)  
A4  
A5  
PCICLK0  
O
I
O
V
V
---  
PCI  
IO  
IO  
FPCI_MON  
IN  
Strap (See Table 3-  
4 on page 44.)  
STRP  
3
PD1  
I/O  
O
IN ,  
T
PMR[23] = 0 and  
(PD  
)
100  
O
(PMR[27] = 0 and  
FPCI_MON = 0)  
14/14  
REQ1#  
I
IN  
---  
PCI  
(PU  
)
22.5  
3
TFTD7  
O
1/4  
PMR[23] = 1 and  
(PMR[27] = 0 and  
FPCI_MON = 0)  
A6  
A7  
A8  
PCIRST#  
PCICLK  
IOW#  
O
O
V
V
V
---  
---  
PCI  
IO  
IO  
IO  
I
IN  
T
3
F_AD1  
O
O
O
14/14  
14/14  
PMR[23] = 0 and  
O
O
PMR[21] = 0 and  
PMR[2] = 0  
(PMR[27] = 1 or  
FPCI_MON = 1)  
3/5  
DOCW#  
GPIO15  
O
O
PMR[21] = 0 and  
PMR[2] = 1  
3
STB#/WRITE#  
TFTD17  
F_FRAME#  
O
3/5  
PMR[23] = 0 and  
(PMR[27] = 0 and  
FPCI_MON = 0)  
I/O  
IN  
O
,
PMR[21] = 1 and  
PMR[2] = 1  
TS  
3/5  
(PU  
)
)
22.5  
3
O
O
1/4  
PMR[23] = 1 and  
(PMR[27] = 0 and  
FPCI_MON = 0)  
3
A9  
GPIO20  
I/O  
(PU  
IN ,  
T
V
V
V
IO  
IO  
IO  
PMR[23] = 0 and  
O
22.5  
PMR[7] = 0  
3/5  
3
O
O
14/14  
PMR[23] = 0 and  
3
DOCCS#  
TFTD0  
O
O
3/5  
1/4  
PMR[23] = 0 and  
(PMR[27] = 1 or  
FPCI_MON = 1)  
(PU  
)
)
)
22.5  
PMR[7] = 1  
3
O
O
PMR[23] = 1  
A23  
A24  
A25  
NC  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
(PU  
22.5  
NC  
---  
---  
3
A10  
GPIO17  
I/O  
(PU  
IN  
O
,
TS  
3/5  
PMR[23] = 0 and  
NC  
---  
22.5  
PMR[5] = 0  
5
5
5
5
DPOS_PORT3  
I/O  
IN  
O
,
AV  
A26  
A27  
A28  
A29  
USB  
USB  
C-  
CUSB  
3
IOCS0#  
TFTDCK  
HSYNC  
O
O
O
O
3/5  
1/4  
1/4  
PMR[23] = 0 and  
(PU  
)
)
22.5  
PMR[5] = 1  
DNEG_PORT3  
DPOS_PORT1  
DNEG_PORT1  
I/O  
I/O  
I/O  
IN  
O
,
AV  
---  
---  
---  
USB  
USB  
C-  
CUSB  
3
O
PMR[23] = 1  
(PU  
22.5  
IN  
O
,
AV  
USB  
USB  
C-  
CUSB  
A11  
A12  
A13  
O
---  
---  
---  
V
PWR  
GND  
---  
---  
IO  
IN  
O
,
AV  
C-  
USB  
USB  
V
---  
---  
CUSB  
SS  
A14  
A15  
A16  
NC  
NC  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
A30  
A31  
B1  
V
V
V
V
PWR  
GND  
GND  
PWR  
I/O  
---  
---  
---  
---  
---  
---  
IO  
---  
---  
SS  
SS  
IO  
V
GND  
SS  
---  
---  
A17  
A18  
V
PWR  
I/O  
---  
---  
---  
PLL2  
B2  
---  
---  
5, 2  
3
PD7  
IN ,  
V
IO  
T
PMR[23] = 0 and  
(PMR[27] = 0 and  
FPCI_MON = 0)  
B3  
AD29  
IN  
,
V
V
V
Cycle Multiplexed  
PCI  
IO  
IO  
IO  
O
14/14  
O
PCI  
D5  
I/O  
I/O  
I/O  
I
IN  
O
,
3
PCI  
PCI  
TFTD13  
F_AD7  
O
O
O
1/4  
PMR[23] = 1 and  
(PMR[27] = 0 and  
FPCI_MON = 0)  
B4  
B5  
AD28  
D4  
IN  
O
,
Cycle Multiplexed  
PCI  
PCI  
3
O
14/14  
---  
PMR[23] = 0 and  
(PMR[27] = 1 or  
FPCI_MON = 1)  
IN  
O
,
PCI  
PCI  
A19  
V
GND  
---  
---  
SS  
REQ0#  
INPCI  
---  
(PU  
)
22.5  
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29  
   
32581C  
Signal Definitions  
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)  
1
1
Ball  
No.  
I/O  
Buffer Power  
Rail Configuration  
Ball  
No.  
I/O  
Buffer Power  
Signal Name  
(PU/PD) Type  
Signal Name  
(PU/PD) Type  
Rail Configuration  
B6  
AD23  
I/O  
IN  
O
,
V
Cycle Multiplexed  
B25  
B26  
V
SS  
GND  
---  
---  
---  
---  
---  
PCI  
IO  
PCI  
NC  
---  
---  
---  
A23  
O
GND  
O
O
PCI  
5
DPOS_PORT2  
I/O  
IN  
O
,
AV  
C-  
CUSB  
B27  
USB  
USB  
B7  
B8  
V
---  
---  
---  
---  
SS  
5
DNEG_PORT2  
GPIO10  
I/O  
I/O  
IN  
O
,
AV  
C-  
CUSB  
---  
RD#  
O
V
B28  
B29  
USB  
USB  
3/5  
IO  
CLKSEL0  
I
IN  
Strap (See Table 3-  
4 on page 44.)  
STRP  
(PD  
)
IN  
,
V
IO  
PMR[18] = 0 and  
PMR[8] = 0  
100  
TS  
(PU  
)
O
22.5  
8/8  
B9  
WR#  
O
O
3/5  
V
IO  
IO  
DSR2#  
I
IN  
PMR[18] = 1 and  
PMR[8] = 0  
TS  
B10  
B11  
V
GND  
O
---  
---  
---  
---  
SS  
(PU  
)
)
)
22.5  
VSYNC  
NC  
O
V
1/4  
IDE_IORDY1  
SDTEST1  
I
IN  
PMR[18] = 0 and  
PMR[8] = 1  
TS1  
(PU  
22.5  
B12  
B13  
---  
---  
---  
---  
---  
O
O
PMR[18] = 1 and  
PMR[8] = 1  
2/5  
V
PWR  
---  
---  
---  
---  
IO  
(PU  
22.5  
B14  
V
GND  
---  
SS  
B30  
B31  
C1  
V
V
GND  
PWR  
I/O  
---  
---  
IN  
---  
---  
---  
SS  
IO  
B15  
B16  
NC  
---  
---  
---  
---  
---  
---  
---  
---  
V
PWR  
IO  
AD26  
,
V
Cycle Multiplexed  
PCI  
IO  
5, 2  
3
BUSY/WAIT#  
I
IN  
V
IO  
B17  
T
PMR[23] = 0 and  
O
PCI  
(PMR[27] = 0 and  
FPCI_MON = 0)  
D2  
I/O  
I/O  
I/O  
IN  
O
,
PCI  
PCI  
3
TFTD3  
O
O
I
O
O
1/4  
1/4  
PMR[23] = 1 and  
C2  
AD24  
D0  
IN  
O
,
V
Cycle Multiplexed  
(PMR[27] = 0 and  
FPCI_MON = 0)  
PCI  
PCI  
IO  
3
F_C/BE1#  
ACK#  
PMR[23] = 0 and  
IN  
O
,
PCI  
PCI  
(PMR[27] = 1 or  
FPCI_MON = 1)  
C3  
C4  
V
PWR  
I/O  
---  
IN  
---  
---  
IO  
5, 2  
3
IN  
V
IO  
B18  
T
PMR[23] = 0 and  
AD25  
,
V
Cycle Multiplexed  
(PMR[27] = 0 and  
FPCI_MON = 0)  
PCI  
IO  
O
PCI  
3
TFTDE  
O
O
O
O
1/4  
1/4  
PMR[23] = 1 and  
D1  
I/O  
IN  
O
,
PCI  
PCI  
(PMR[27] = 0 and  
FPCI_MON = 0)  
C5  
C6  
GNT0#  
DID0  
O
I
O
V
V
---  
PCI  
IO  
IO  
3
FPCICLK  
PMR[23] = 0 and  
IN  
Strap (See Table 3-  
4 on page 44.)  
(PMR[27] = 1 or  
FPCI_MON = 1)  
STRP  
(PD  
)
100  
B19  
B20  
V
PWR  
O
---  
---  
V
---  
GNT1#  
DID1  
O
O
---  
IO  
PCI  
5,2  
3
SLIN#/ASTRB#  
TFTD16  
F_IRDY#  
INIT#  
O
I
IN  
Strap (See Table 3-  
4 on page 44.)  
14/14  
IO  
PMR[23] = 0 and  
STRP  
(PD  
)
)
(PMR[27] = 0 and  
FPCI_MON = 0)  
100  
C7  
C8  
V
PWR  
---  
---  
---  
---  
IO  
3
O
O
O
1/4  
PMR[23] = 1 and  
ROMCS#  
BOOT16  
O
O
V
V
3/5  
IO  
IO  
(PMR[27] = 0 and  
FPCI_MON = 0)  
I
IN  
Strap (See Table 3-  
4 on page 44.)  
STRP  
(PD  
100  
3
O
O
14/14  
14/14  
PMR[23] = 0 and  
(PMR[27] = 1 or  
FPCI_MON = 1)  
C9  
GPIO19  
I/O  
IN  
O
,
V
PMR[9] = 0 and  
PMR[4] = 0  
TS  
IO  
(PU  
)
22.5  
3/5  
5,2  
3
O
V
IO  
B21  
PMR[23] = 0 and  
INTC#  
I
IN  
PMR[9] = 0 and  
PMR[4] = 1  
TS  
(PMR[27] = 0 and  
FPCI_MON = 0)  
(PU  
)
)
22.5  
IOCHRDY  
I
IN  
PMR[9] = 1 and  
PMR[4] = 1  
TS1  
3
TFTD5  
O
O
1/4  
PMR[23] = 1 and  
(PU  
22.5  
(PMR[27] = 0 and  
FPCI_MON = 0)  
C10  
C11  
V
PWR  
O
---  
---  
---  
IO  
3
SMI_O  
O
O
IRTX  
O
O
V
PMR[6] = 0  
14/14  
---  
PMR[23] = 0 and  
8/8  
8/8  
IO  
(PMR[27] = 1 or  
FPCI_MON = 1)  
SOUT3  
O
PMR[6] = 1  
C12  
C13  
C14  
V
GND  
PWR  
GND  
---  
---  
---  
---  
---  
B22  
V
GND  
---  
---  
SS  
SS  
V
---  
---  
---  
---  
B23  
B24  
NC  
---  
---  
---  
---  
---  
---  
---  
IO  
V
GND  
V
SS  
SS  
30  
AMD Geode™ SC3200 Processor Data Book  
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Signal Definitions  
Ball  
32581C  
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)  
1
1
I/O  
Buffer Power  
Rail Configuration  
Ball  
No.  
I/O  
Buffer Power  
Rail Configuration  
No.  
C15  
C16  
Signal Name  
(PU/PD) Type  
Signal Name  
(PU/PD) Type  
V
GND  
GND  
I
---  
---  
---  
---  
---  
---  
C28  
GPIO9  
I/O  
(PU  
IN  
O
,
V
PMR[18] = 0 and  
PMR[8] = 0  
SS  
TS  
1/4  
IO  
)
22.5  
AV  
SSPLL2  
DCD2#  
I
IN  
PMR[18] = 1 and  
PMR[8] = 0  
TS  
5,2  
3
SLCT  
IN  
V
C17  
T
IO  
IO  
IO  
IO  
IO  
PMR[23] = 0 and  
(PMR[27] = 0 and  
FPCI_MON = 0)  
(PU  
)
)
)
22.5  
IDE_IOW1#  
SDTEST2  
O
O
PMR[18] = 0 and  
PMR[8] = 1  
1/4  
2/5  
(PU  
22.5  
22.5  
3
TFTD15  
F_C/BE3#  
PD4  
O
O
O
O
1/4  
1/4  
PMR[23] = 1 and  
O
(PU  
O
PMR[18] = 1 and  
PMR[8] = 1  
(PMR[27] = 0 and  
FPCI_MON = 0)  
3
C29  
C30  
V
PWR  
I/O  
---  
---  
V
---  
PMR[23] = 0 and  
IO  
(PMR[27] = 1 or  
FPCI_MON = 1)  
GPIO7  
IN  
O
,
PMR[17] = 0 and  
PMR[8] = 0  
TS  
1/4  
IO  
(PU  
)
22.5  
3
C18  
I/O  
O
IN ,  
V
V
V
V
T
PMR[23] = 0 and  
RTS2#  
O
O
O
O
PMR[17] = 1 and  
PMR[8] = 0  
1/4  
1/4  
2/5  
O
(PMR[27] = 0 and  
FPCI_MON = 0)  
14/14  
(PU  
)
)
)
)
22.5  
22.5  
22.5  
22.5  
IDE_DACK1#  
SDTEST0  
GPIO8  
O
(PU  
PMR[17] = 0 and  
PMR[8] = 1  
3
TFTD10  
F_AD4  
PD5  
O
1/4  
PMR[23] = 1 and  
(PMR[27] = 0 and  
FPCI_MON = 0)  
O
(PU  
PMR[17] = 1 and  
PMR[8] = 1  
3
O
O
14/14  
PMR[23] = 0 and  
(PMR[27] = 1 or  
FPCI_MON = 1)  
C31  
I/O  
(PU  
IN  
O
,
V
PMR[17] = 0 and  
PMR[8] = 0  
TS  
8/8  
IO  
5,2  
5,2  
5,2  
3
I/O  
O
IN ,  
C19  
T
PMR[23] = 0 and  
CTS2#  
I
IN  
PMR[17] = 1 and  
PMR[8] = 0  
TS  
O
(PMR[27] = 0 and  
FPCI_MON = 0)  
14/14  
(PU  
)
)
)
22.5  
IDE_DREQ1  
SDTEST4  
AD21  
I
IN  
PMR[17] = 0 and  
PMR[8] = 1  
TS1  
3
TFTD11  
F_AD5  
PD3  
O
1/4  
PMR[23] = 1 and  
(PU  
22.5  
(PMR[27] = 0 and  
FPCI_MON = 0)  
O
O
PMR[17] = 1 and  
PMR[8] = 1  
2/5  
(PU  
22.5  
3
O
O
14/14  
PMR[23] = 0 and  
(PMR[27] = 1 or  
FPCI_MON = 1)  
D1  
D2  
D3  
D4  
I/O  
IN  
O
,
V
V
V
V
Cycle Multiplexed  
Cycle Multiplexed  
Cycle Multiplexed  
Cycle Multiplexed  
PCI  
IO  
IO  
IO  
IO  
PCI  
3
I/O  
O
IN ,  
C20  
T
PMR[23] = 0 and  
A21  
O
O
PCI  
O
(PMR[27] = 0 and  
FPCI_MON = 0)  
14/14  
AD22  
I/O  
IN  
O
,
PCI  
PCI  
3
TFTD9  
F_AD3  
PD0  
O
1/4  
PMR[23] = 1 and  
A22  
O
O
(PMR[27] = 0 and  
FPCI_MON = 0)  
PCI  
AD20  
I/O  
IN  
O
,
PCI  
PCI  
3
O
O
14/14  
PMR[23] = 0 and  
(PMR[27] = 1 or  
FPCI_MON = 1)  
A20  
O
O
PCI  
3
I/O  
O
IN ,  
AD27  
I/O  
IN  
O
,
C21  
T
PMR[23] = 0 and  
PCI  
PCI  
O
(PMR[27] = 0 and  
14/14  
FPCI_MON = 0)  
D3  
I/O  
I/O  
I/O  
IN  
O
,
PCI  
PCI  
3
TFTD6  
F_AD0  
O
1/4  
PMR[23] = 1 and  
(PMR[27] = 0 and  
FPCI_MON = 0)  
D5  
D6  
AD31  
D7  
IN  
O
,
V
V
Cycle Multiplexed  
PCI  
PCI  
IO  
IO  
3
O
O
14/14  
---  
PMR[23] = 0 and  
IN  
O
,
(PMR[27] = 1 or  
FPCI_MON = 1)  
PCI  
PCI  
C22  
V
PWR  
---  
---  
IO  
PCICLK1  
O
I
O
---  
PCI  
C23  
C24  
C25  
NC  
NC  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
LPC_ROM  
IN  
Strap (See Table 3-  
4 on page 44.)  
STRP  
(PD  
)
100  
D7  
D8  
V
GND  
I/O  
---  
---  
---  
---  
SS  
V
PWR  
IO  
FRAME#  
IN  
O
,
V
PCI  
IO  
C26  
INTB#  
I
IN  
V
---  
PCI  
IO  
(PU  
)
22.5  
(PU  
)
PCI  
22.5  
D9  
IOR#  
O
O
O
V
PMR[21] = 0 and  
PMR[2] = 0  
C27  
AV  
GND  
---  
---  
---  
3/5  
3/5  
IO  
SSUSB  
DOCR#  
GPIO14  
O
PMR[21] = 0 and  
PMR[2] = 1  
I/O  
IN  
O
,
PMR[21] = 1 and  
PMR[2] = 1  
TS  
3/5  
(PU  
)
22.5  
AMD Geode™ SC3200 Processor Data Book  
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31  
32581C  
Signal Definitions  
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)  
1
1
Ball  
No.  
I/O  
Buffer Power  
Ball  
No.  
I/O  
Buffer Power  
Signal Name  
(PU/PD) Type  
Rail Configuration  
Signal Name  
(PU/PD) Type  
Rail Configuration  
3
D10  
GPIO1  
I/O  
(PU  
IN ,  
T
V
V
V
D26  
INTA#  
I
IN  
V
---  
IO  
IO  
IO  
PMR[23] = 0 and  
PMR[13] = 0  
PCI  
IO  
IO  
)
)
)
(PU  
)
)
O
22.5  
22.5  
3/5  
D27  
D28  
AV  
PWR  
---  
---  
---  
3
IOCS1#  
TFTD12  
O
O
CCUSB  
3/5  
PMR[23] = 0 and  
(PU  
22.5  
PMR[13] = 1  
GPIO6  
I/O  
(PU  
22.5  
IN  
O
,
V
PMR[18] = 0 and  
PMR[8] = 0  
TS  
3
O
O
1/4  
1/4  
PMR[23] = 1  
(PU  
22.5  
DTR2#/BOUT2  
IDE_IOR1#  
SDTEST5  
O
O
O
O
O
PMR[18] = 1 and  
PMR[8] = 0  
1/4  
(PU  
)
)
)
D11  
TRDE#  
GPIO0  
O
O
V
V
PMR[12] = 0  
PMR[12] = 1  
22.5  
22.5  
22.5  
3/5  
IO  
IO  
O
(PU  
PMR[18] = 0 and  
PMR[8] = 1  
I/O  
IN  
O
,
1/4  
2/5  
8/8  
TS  
3/5  
(PU  
)
22.5  
O
(PU  
PMR[18] = 1 and  
PMR[8] = 1  
D12  
D13  
D14  
D15  
D16  
D17  
V
V
V
V
PWR  
GND  
PWR  
PWR  
---  
---  
---  
---  
---  
---  
---  
CORE  
---  
---  
---  
---  
---  
---  
---  
SS  
D29  
SOUT2  
O
V
---  
IO  
IO  
CLKSEL2  
I
IN  
Strap (See Table 3-  
4 on page 44.)  
STRP  
(PD  
)
100  
IO  
D30  
D31  
TDP  
TDN  
I/O  
Diode  
WIRE  
---  
---  
---  
NC  
PE  
---  
I
---  
IN  
5, 2  
3
I/O  
I/O  
V
V
V
IO  
IO  
T
IO  
PMR[23] = 0 and  
(PU  
22.5  
(PMR[27] = 0 and  
FPCI_MON = 0)  
(PU/PD under soft-  
ware control.)  
E1  
E2  
E3  
E4  
AD16  
IN  
O
,
Cycle Multiplexed  
Cycle Multiplexed  
Cycle Multiplexed  
Cycle Multiplexed  
PCI  
PD  
)
22.5  
PCI  
A16  
O
O
PCI  
3
TFTD14  
O
O
O
O
1/4  
1/4  
PMR[23] = 1 and  
AD19  
I/O  
IN  
O
,
V
V
V
PCI  
PCI  
IO  
IO  
IO  
(PMR[27] = 0 and  
FPCI_MON = 0)  
A19  
O
O
3
PCI  
F_C/BE2#  
PMR[23] = 0 and  
(PMR[27] = 1 or  
FPCI_MON = 1)  
AD18  
I/O  
IN  
O
,
PCI  
PCI  
D18  
D19  
V
V
PWR  
GND  
I/O  
---  
---  
---  
---  
---  
IO  
A18  
O
O
PCI  
---  
SS  
DEVSEL#  
I/O  
IN  
O
,
PCI  
PCI  
(PU  
)
)
5, 2  
5, 2  
5, 2  
3
PD2  
IN ,  
T
V
22.5  
D20  
IO  
IO  
IO  
PMR[23] = 0 and  
O
(PMR[27] = 0 and  
FPCI_MON = 0)  
14/14  
BHE#  
O
I
O
PCI  
E28  
E29  
SIN2  
IN  
V
V
PMR[28] = 0  
PMR[28] = 1  
---  
3
TS  
2/5  
PCI  
IO  
IO  
TFTD8  
O
O
O
1/4  
PMR[23] = 1 and  
(PMR[27] = 0 and  
FPCI_MON = 0)  
SDTEST3  
TRST#  
O
O
I
IN  
3
F_AD2  
O
14/14  
PMR[23] = 0 and  
(PU  
22.5  
(PMR[27] = 1 or  
FPCI_MON = 1)  
E30  
E31  
TDO  
TCK  
O
I
O
V
V
---  
---  
PCI  
IO  
IO  
3
ERR#  
I
IN ,  
T
V
IN  
D21  
PMR[23] = 0 and  
PCI  
(PU  
)
)
O
(PMR[27] = 0 and  
FPCI_MON = 0)  
22.5  
1/4  
F1  
F2  
F3  
TRDY#  
D13  
I/O  
(PU  
IN  
O
,
V
V
V
Cycle Multiplexed  
Cycle Multiplexed  
Cycle Multiplexed  
PCI  
PCI  
IO  
IO  
IO  
3
TFTD4  
O
O
1/4  
PMR[23] = 1 and  
22.5  
(PMR[27] = 0 and  
FPCI_MON = 0)  
I/O  
(PU  
IN  
O
,
PCI  
PCI  
)
)
)
)
)
22.5  
3
F_C/BE0#  
AFD#/DSTRB#  
TFTD2  
O
O
1/4  
PMR[23] = 0 and  
IRDY#  
D14  
I/O  
(PU  
IN  
O
,
(PMR[27] = 1 or  
FPCI_MON = 1)  
PCI  
PCI  
22.5  
3
O
O
V
I/O  
(PU  
IN  
O
,
D22  
14/14  
PMR[23] = 0 and  
PCI  
PCI  
(PMR[27] = 0 and  
FPCI_MON = 0)  
22.5  
C/BE2#  
D10  
I/O  
(PU  
IN  
O
,
PCI  
PCI  
3
O
O
1/4  
PMR[23] = 1 and  
22.5  
(PMR[27] = 0 and  
FPCI_MON = 0)  
I/O  
(PU  
IN  
O
,
PCI  
PCI  
22.5  
3
INTR_O  
O
O
14/14  
---  
PMR[23] = 0 and  
(PMR[27] = 1 or  
FPCI_MON = 1)  
F4  
AD17  
I/O  
IN  
O
,
V
V
Cycle Multiplexed  
PCI  
PCI  
IO  
IO  
D23  
V
PWR  
---  
---  
IO  
A17  
O
I
O
PCI  
D24  
D25  
NC  
---  
---  
---  
---  
---  
---  
---  
F28  
TMS  
IN  
---  
PCI  
(PU  
)
22.5  
V
GND  
SS  
32  
AMD Geode™ SC3200 Processor Data Book  
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Signal Definitions  
Ball  
32581C  
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)  
1
1
I/O  
Buffer Power  
Rail Configuration  
Ball  
No.  
I/O  
Buffer Power  
No.  
Signal Name  
(PU/PD) Type  
Signal Name  
(PU/PD) Type  
Rail Configuration  
4
F29  
TDI  
I
IN  
V
---  
J31  
GPIO39  
I/O  
(PU )  
22.5  
IN  
O
,
V
PCI  
IO  
PCI  
PCI  
IO  
PMR[14] = 0 and  
(PU  
)
)
4
22.5  
PMR[22] = 0  
F30  
GTEST  
I
IN  
V
---  
4
T
IO  
SERIRQ  
I/O  
I/O  
IN  
O
,
PCI  
PCI  
PMR[14] = 1 and  
(PD  
22.5  
4
PMR[22] = 1  
F31  
G1  
VPCKIN  
STOP#  
I
IN  
V
V
---  
T
IO  
IO  
K1  
AD11  
A11  
IN  
O
,
V
Cycle Multiplexed  
PCI  
PCI  
IO  
I/O  
IN  
O
,
Cycle Multiplexed  
PCI  
(PU  
)
)
22.5  
PCI  
O
O
PCI  
D15  
I/O  
IN  
O
,
PCI  
PCI  
K2  
K3  
K4  
V
V
PWR  
GND  
I/O  
---  
---  
---  
---  
---  
IO  
(PU  
22.5  
---  
SS  
G2  
V
V
V
V
V
V
GND  
PWR  
GND  
GND  
PWR  
GND  
I
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
SS  
AD14  
IN  
,
V
Cycle Multiplexed  
PCI  
IO  
G3  
---  
---  
---  
---  
---  
IO  
O
PCI  
G4  
SS  
SS  
IO  
A14  
O
O
PCI  
G28  
G29  
G30  
G31  
H1  
4
K28  
GPIO38/IRRX2  
I/O  
IN  
O
,
V
PCI  
PCI  
IO  
PMR[14] = 0 and  
(PU  
)
4
22.5  
PMR[22] = 0. The  
IRRX2 input is con-  
nected to the input  
path of GPIO38.  
There is no logic  
required to enable  
IRRX2, just a sim-  
ple connection.  
Hence, when  
GPIO38 is the  
selected function,  
IRRX2 is also  
selected.  
SS  
VPD7  
IN  
V
T
IO  
IO  
SERR#  
I/O  
IN  
,
V
V
V
V
PCI  
(PU  
)
)
)
)
)
OD  
22.5  
PCI  
H2  
H3  
H4  
PERR#  
LOCK#  
C/BE3#  
D11  
I/O  
IN  
O
,
---  
PCI  
PCI  
IO  
IO  
IO  
(PU  
22.5  
22.5  
22.5  
I/O  
(PU  
IN  
O
,
---  
PCI  
PCI  
4
LPCPD#  
O
O
PCI  
PMR[14] = 1 and  
I/O  
(PU  
IN  
O
,
Cycle Multiplexed  
PCI  
PCI  
4
PMR[22] = 1  
K29  
K30  
K31  
V
PWR  
GND  
I/O  
---  
---  
---  
---  
---  
---  
I/O  
IN  
O
,
IO  
PCI  
PCI  
(PU  
22.5  
V
SS  
H28  
H29  
H30  
H31  
J1  
VPD6  
VPD5  
VPD4  
VPD3  
AD13  
I
I
I
I
IN  
V
V
V
V
V
---  
T
T
T
T
IO  
IO  
IO  
IO  
IO  
4
GPIO37  
IN  
,
V
PCI  
IO  
PMR[14] = 0 and  
(PU  
)
4
O
22.5  
IN  
---  
PCI  
PMR[22] = 0  
4
IN  
IN  
---  
LFRAME#  
O
O
PCI  
PMR[14] = 1 and  
4
PMR[22] = 1  
---  
L1  
C/BE0#  
D8  
I/O  
(PU  
IN  
O
,
V
Cycle Multiplexed  
PCI  
PCI  
IO  
I/O  
IN  
O
,
Cycle Multiplexed  
PCI  
)
)
22.5  
PCI  
I/O  
(PU  
IN  
O
,
PCI  
PCI  
A13  
O
O
PCI  
22.5  
J2  
C/BE1#  
I/O  
IN  
O
,
V
Cycle Multiplexed  
PCI  
PCI  
IO  
L2  
AD9  
I/O  
IN  
O
,
V
V
V
V
Cycle Multiplexed  
Cycle Multiplexed  
Cycle Multiplexed  
PCI  
PCI  
IO  
IO  
IO  
IO  
(PU  
)
)
22.5  
D9  
I/O  
(PU  
IN  
O
,
PCI  
PCI  
A9  
O
O
PCI  
22.5  
L3  
AD10  
I/O  
IN  
O
,
PCI  
PCI  
J3  
J4  
AD15  
I/O  
IN  
O
,
V
V
Cycle Multiplexed  
Cycle Multiplexed  
PCI  
PCI  
IO  
IO  
A10  
O
O
PCI  
A15  
PAR  
O
O
PCI  
L4  
AD12  
I/O  
IN  
O
,
PCI  
PCI  
I/O  
IN  
O
,
PCI  
PCI  
(PU  
)
)
22.5  
A12  
O
O
PCI  
D12  
I/O  
(PU  
IN  
O
,
PCI  
PCI  
22.5  
4
L28  
GPIO36  
I/O  
IN  
O
,
PCI  
PCI  
PMR[14] = 0 and  
(PU  
)
4
22.5  
PMR[22] = 0  
J28  
J29  
J30  
VPD2  
VPD1  
VPD0  
I
I
I
IN  
V
V
V
---  
---  
---  
T
T
T
IO  
IO  
IO  
4
LDRQ#  
I
IN  
PCI  
PMR[14] = 1 and  
IN  
IN  
4
PMR[22] = 1  
AMD Geode™ SC3200 Processor Data Book  
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33  
32581C  
Signal Definitions  
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)  
1
1
Ball  
No.  
I/O  
Buffer Power  
Ball  
No.  
I/O  
Buffer Power  
Signal Name  
(PU/PD) Type  
Rail Configuration  
Signal Name  
(PU/PD) Type  
Rail Configuration  
4
L29  
L30  
L31  
GPIO35  
I/O  
(PU  
IN  
O
,
V
V
V
N29  
GPIO12  
I/O  
(PU  
IN  
O
,
V
PMR[19] = 0  
PCI  
PCI  
IO  
IO  
IO  
PMR[14] = 0 and  
AB  
8/8  
IO  
)
)
)
)
)
)
)
)
)
)
4
22.5  
22.5  
PMR[22] = 0  
AB2C  
I/O  
(PU  
IN  
OD  
,
AB  
PMR[19] = 1  
4
LAD3  
I/O  
(PU  
IN  
O
,
PCI  
PCI  
PMR[14] = 1 and  
22.5  
4
22.5  
8
PMR[22] = 1  
3
N30  
AB1D  
I/O  
(PU  
IN  
OD  
,
V
4
AB  
IO  
PMR[23] = 0  
GPIO34  
LAD2  
I/O  
(PU  
IN  
O
,
PCI  
PCI  
PMR[14] = 0 and  
22.5  
8
4
22.5  
PMR[22] = 0  
3
GPIO1  
IOCS1#  
AB1C  
I/O  
(PU  
IN ,  
O
T
PMR[23] = 1 and  
4
I/O  
(PU  
IN  
O
,
PCI  
PCI  
PMR[14] = 1 and  
22.5  
PMR[13] = 0  
3/5  
4
22.5  
PMR[22] = 1  
3
O
O
3/5  
PMR[23] = 1 and  
4
GPIO33  
LAD1  
I/O  
(PU  
IN  
O
,
PCI  
PCI  
PMR[14] = 0 and  
PMR[13] = 1  
4
22.5  
PMR[22] = 0  
3
N31  
I/O  
IN  
OD  
,
V
V
AB  
IO  
PMR[23] = 0  
4
I/O  
(PU  
IN  
O
,
(PU  
)
)
PCI  
PCI  
PMR[14] = 1 and  
22.5  
8
4
22.5  
PMR[22] = 1  
3
GPIO20  
DOCCS#  
AD4  
I/O  
(PU  
IN ,  
T
O
PMR[23] = 1 and  
M1  
M2  
V
GND  
I/O  
---  
IN  
---  
---  
SS  
22.5  
PMR[7] = 0  
3/5  
AD7  
,
V
Cycle Multiplexed  
3
O
O
PCI  
IO  
3/5  
PMR[23] = 1 and  
O
PCI  
PMR[7] = 1  
A7  
O
O
P1  
I/O  
IN  
,
Cycle Multiplexed  
PCI  
PCI  
IO  
O
PCI  
M3  
M4  
V
PWR  
I/O  
---  
IN  
---  
---  
IO  
A4  
O
O
O
PCI  
AD8  
,
V
Cycle Multiplexed  
PCI  
IO  
O
P2  
P3  
IDE_CS1#  
TFTDE  
AD1  
O
O
V
V
PMR[24] = 0  
PCI  
1/4  
1/4  
IO  
IO  
A8  
O
O
O
PMR[24] = 1  
PCI  
4
M28  
M29  
GPIO32  
I/O  
IN  
O
,
V
I/O  
IN  
,
Cycle Multiplexed  
PCI  
PCI  
IO  
PMR[14] = 0 and  
PCI  
(PU  
)
)
4
22.5  
O
PMR[22] = 0  
PCI  
4
A1  
O
O
LAD0  
I/O  
IN  
O
,
PCI  
PCI  
PCI  
PMR[14] = 1 and  
(PU  
4
22.5  
PMR[22] = 1  
P4  
V
V
V
V
V
V
V
V
V
PWR  
PWR  
PWR  
GND  
GND  
GND  
PWR  
PWR  
PWR  
O
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
CORE  
CORE  
CORE  
SS  
GPIO13  
AB2D  
I/O  
IN  
O
,
V
V
PMR[19] = 0  
PMR[19] = 1  
AB  
8/8  
IO  
IO  
P13  
P14  
P15  
P16  
P17  
P18  
P19  
P28  
P29  
---  
---  
---  
---  
---  
---  
---  
---  
(PU  
)
)
22.5  
I/O  
IN  
,
AB  
(PU  
OD  
22.5  
8
M30  
M31  
N1  
V
PWR  
GND  
I/O  
---  
---  
---  
---  
SS  
IO  
V
---  
---  
SS  
SS  
AD3  
IN  
O
,
V
Cycle Multiplexed  
CORE  
CORE  
CORE  
PCI  
IO  
IO  
IO  
PCI  
A3  
O
O
PCI  
N2  
N3  
AD6  
I/O  
IN  
O
,
V
V
Cycle Multiplexed  
Cycle Multiplexed  
PCI  
PCI  
SDATA_OUT  
TFT_PRSNT  
O
V
AC97  
STRP  
IO  
IO  
I
IN  
V
Strap (See Table 3-  
4 on page 44.)  
A6  
O
O
PCI  
(PD  
)
100  
AD5  
I/O  
IN  
O
,
PCI  
PCI  
P30  
SYNC  
O
O
V
---  
AC97  
IO  
CLKSEL3  
I
IN  
Strap (See Table 3-  
4 on page 44.)  
STRP  
A5  
O
O
PCI  
(PD  
)
100  
N4  
V
V
V
V
V
V
V
V
V
GND  
PWR  
PWR  
GND  
GND  
GND  
PWR  
PWR  
GND  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
SS  
P31  
R1  
AC97_CLK  
O
O
V
PMR[25] = 1  
2/5  
IO  
N13  
N14  
N15  
N16  
N17  
N18  
N19  
N28  
---  
---  
---  
---  
---  
---  
---  
---  
CORE  
CORE  
SS  
V
V
V
V
V
V
V
V
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
R2  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
R3  
SS  
R4  
SS  
R13  
R14  
R15  
R16  
CORE  
CORE  
SS  
34  
AMD Geode™ SC3200 Processor Data Book  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Signal Definitions  
Ball  
32581C  
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)  
1
1
I/O  
Buffer Power  
Rail Configuration  
Ball  
No.  
I/O  
Buffer Power  
Rail Configuration  
No.  
R17  
R18  
R19  
R28  
R29  
R30  
R31  
T1  
Signal Name  
(PU/PD) Type  
Signal Name  
SDATA_IN  
(PU/PD) Type  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
GND  
GND  
GND  
GND  
GND  
GND  
GND  
PWR  
PWR  
PWR  
PWR  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
PWR  
PWR  
PWR  
PWR  
I/O  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
U31  
I
IN  
V
FPCI_MON = 0  
FPCI_MON = 1  
PMR[24] = 0  
SS  
T
IO  
---  
F_GNT0#  
O
O
2/5  
SS  
---  
V1  
IDE_DATA15  
I/O  
IN  
,
TS1  
V
SS  
IO  
TS  
1/4  
---  
SS  
TFTD7  
O
O
PMR[24] = 1  
PMR[24] = 0  
1/4  
---  
SS  
V2  
V3  
IDE_DATA14  
I/O  
IN  
,
V
V
TS1  
IO  
IO  
---  
SS  
TS  
1/4  
---  
SS  
TFTD17  
O
O
PMR[24] = 1  
PMR[24] = 0  
1/4  
---  
CORE  
CORE  
CORE  
CORE  
SS  
IDE_DATA13  
I/O  
IN  
,
TS1  
TS  
T2  
---  
1/4  
TFTD15  
O
O
PMR[24] = 1  
T3  
---  
1/4  
V4  
V
GND  
PWR  
PWR  
GND  
GND  
GND  
PWR  
PWR  
GND  
O
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
T4  
---  
SS  
V13  
V14  
V15  
V16  
V17  
V18  
V19  
V28  
V29  
V30  
V
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
T13  
T14  
T15  
T16  
T17  
T18  
T19  
T28  
T29  
T30  
T31  
U1  
---  
CORE  
V
---  
CORE  
SS  
V
---  
SS  
SS  
V
---  
SS  
SS  
V
---  
SS  
SS  
V
---  
CORE  
SS  
V
---  
CORE  
SS  
V
---  
SS  
CORE  
CORE  
CORE  
CORE  
SDCLK3  
GXCLK  
O
V
---  
2/5  
2/5  
IO  
IO  
3
O
O
V
---  
PMR[23] = 0 and  
PMR[29] = 0  
---  
3
FP_VDD_ON  
TEST3  
O
O
O
O
1/4  
2/5  
PMR[23] = 1  
AD0  
IN  
,
V
Cycle Multiplexed  
PCI  
IO  
3
O
PMR[23] = 0 and  
PCI  
PMR[29] = 1  
A0  
O
O
O
PCI  
V31  
GPIO16  
IN ,  
T
V
PMR[0] = 0 and  
FPCI_MON = 0  
IO  
U2  
U3  
IDE_ADDR2  
TFTD4  
AD2  
O
O
V
V
PMR[24] = 0  
)
1/4  
1/4  
IO  
IO  
O
2/5  
O
PMR[24] = 1  
PC_BEEP  
O
PMR[0] = 1 = 0 and  
FPCI_MON = 0  
2/5  
I/O  
IN  
O
,
Cycle Multiplexed  
PCI  
F_DEVSEL#  
O
FPCI_MON = 1  
PCI  
2/5  
A2  
O
O
W1  
W2  
W3  
V
PWR  
GND  
I/O  
---  
---  
IN  
---  
---  
---  
PCI  
IO  
U4  
V
PWR  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
PWR  
O
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
V
---  
CORE  
SS  
U13  
U14  
U15  
U16  
U17  
U18  
U19  
U28  
U29  
V
---  
---  
---  
---  
---  
---  
---  
---  
---  
IDE_DATA12  
,
V
PMR[24] = 0  
SS  
TS1  
IO  
TS  
1/4  
V
V
V
V
V
V
V
---  
SS  
TFTD13  
O
O
PMR[24] = 1  
PMR[24] = 0  
1/4  
---  
SS  
W4  
IDE_DATA11  
I/O  
IN  
,
V
TS1  
IO  
---  
SS  
TS  
1/4  
---  
SS  
GPIO41  
I/O  
IN  
,
PMR[24] = 1  
TS1  
O
---  
1/4  
SS  
W13  
W14  
W15  
W16  
W17  
W18  
W19  
V
PWR  
PWR  
GND  
GND  
GND  
PWR  
PWR  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
CORE  
SS  
V
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
CORE  
CORE  
V
AC97_RST#  
F_STOP#  
BIT_CLK  
O
V
FPCI_MON = 0  
FPCI_MON = 1  
FPCI_MON = 0  
FPCI_MON = 1  
SS  
2/5  
2/5  
IO  
V
O
O
O
SS  
V
U30  
I
IN  
V
SS  
T
IO  
V
F_TRDY#  
O
CORE  
1/4  
V
CORE  
AMD Geode™ SC3200 Processor Data Book  
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35  
32581C  
Signal Definitions  
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)  
1
1
Ball  
No.  
I/O  
Buffer Power  
Rail Configuration  
Ball  
No.  
I/O  
Buffer Power  
Signal Name  
(PU/PD) Type  
Signal Name  
(PU/PD) Type  
Rail Configuration  
5
5
MD57  
I/O  
IN ,  
V
---  
MD24  
I/O  
IN ,  
TS  
2/5  
V
IO  
---  
W28  
T
IO  
AB28  
T
TS  
2/5  
W29  
W30  
W31  
Y1  
SDCLK1  
O
O
V
---  
AB29  
AB30  
AB31  
AC1  
V
V
PWR  
GND  
O
---  
---  
---  
---  
---  
2/5  
IO  
IO  
V
V
GND  
PWR  
I/O  
---  
---  
IN  
---  
---  
---  
---  
SS  
IO  
SS  
---  
DQM7  
O
V
---  
2/5  
IO  
IO  
IDE_DATA10  
IDE_DATA9  
IDE_DATA8  
GPIO40  
,
V
PMR[24] = 0  
IDE_DATA1  
I/O  
IN ,  
TS1  
V
V
V
V
PMR[24] = 0  
TS1  
IO  
IO  
IO  
TS  
TS  
1/4  
1/4  
Y2  
Y3  
I/O  
I/O  
I/O  
IN  
,
V
V
PMR[24] = 0  
PMR[24] = 0  
PMR[24] = 1  
TFTD16  
O
O
PMR[24] = 1  
PMR[24] = 0  
TS1  
1/4  
TS  
1/4  
AC2  
AC3  
AC4  
IDE_DATA2  
I/O  
IN  
,
TS1  
IO  
IO  
IO  
IN  
,
TS  
TS1  
1/4  
TS  
1/4  
TFTD14  
O
O
PMR[24] = 1  
PMR[24] = 0  
1/4  
IN  
,
TS1  
IDE_DATA0  
I/O  
IN  
,
TS1  
O
1/4  
1/4  
1/4  
TS  
1/4  
Y4  
IDE_IOR0#  
TFTD10  
MD58  
O
O
O
V
PMR[24] = 0  
PMR[24] = 1  
---  
IO  
TFTD6  
O
I
O
PMR[24] = 1  
PMR[24] = 0  
PMR[24] = 1  
---  
1/4  
O
IDE_DREQ0  
TFTD8  
IN  
TS1  
5
I/O  
IN ,  
TS  
V
V
V
V
V
Y28  
Y29  
Y30  
Y31  
T
IO  
IO  
IO  
IO  
IO  
O
O
1/4  
2/5  
5
5
5
MD25  
I/O  
IN ,  
V
V
V
AC28  
AC29  
AC30  
T
IO  
IO  
IO  
5
MD59  
MD60  
MD56  
I/O  
I/O  
I/O  
IN ,  
TS  
---  
---  
---  
T
TS  
2/5  
2/5  
MD26  
MD27  
I/O  
I/O  
IN ,  
---  
---  
T
5
5
IN ,  
TS  
T
TS  
2/5  
2/5  
IN ,  
T
IN ,  
TS  
T
TS  
2/5  
2/5  
AC31  
AD1  
DQM3  
O
I
O
V
V
---  
2/5  
IO  
IO  
AA1  
AA2  
IDE_RST#  
TFTDCK  
O
O
O
O
PMR[24] = 0  
PMR[24] = 1  
PMR[24] = 0  
1/4  
1/4  
IDE_IORDY0  
TFTD11  
IN  
PMR[24] = 0  
PMR[24] = 1  
PMR[24] = 0  
PMR[24] = 1  
PMR[24] = 0  
PMR[24] = 1  
PMR[24] = 0  
PMR[24] = 1  
---  
TS1  
O
O
O
O
O
O
O
I/O  
O
O
O
O
O
O
O
1/4  
1/4  
1/4  
1/4  
1/4  
1/4  
1/4  
IDE_DATA7  
I/O  
IN  
,
V
V
V
TS1  
IO  
IO  
IO  
TS  
AD2  
AD3  
AD4  
IDE_IOW0#  
TFTD9  
V
V
V
1/4  
IO  
IO  
IO  
INTD#  
I
IN  
PMR[24] = 1  
PMR[24] = 0  
TS  
AA3  
AA4  
IDE_DATA6  
I/O  
IN  
,
TS1  
IDE_ADDR0  
TFTD3  
TS  
1/4  
IRQ9  
I
IN  
PMR[24] = 1  
PMR[24] = 0  
TS1  
IDE_DACK0#  
TFTD0  
IDE_DATA5  
I/O  
IN  
,
TS1  
TS  
1/4  
1/4  
2/5  
5
MD52  
IN ,  
V
V
V
V
V
AD28  
AD29  
AD30  
T
IO  
IO  
IO  
IO  
IO  
CLK27M  
SDCLK2  
MD61  
O
O
O
O
PMR[24] = 1  
TS  
2/5  
AA28  
AA29  
V
V
---  
---  
IO  
IO  
5
5
5
MD29  
MD30  
MD31  
I/O  
I/O  
I/O  
IN ,  
---  
---  
---  
T
5
5
5
I/O  
IN ,  
TS  
TS  
T
2/5  
2/5  
IN ,  
T
MD62  
I/O  
I/O  
I/O  
IN ,  
TS  
V
V
V
---  
TS  
AA30  
T
IO  
IO  
IO  
2/5  
2/5  
IN ,  
AD31  
AE1  
T
MD63  
IN ,  
TS  
---  
TS  
AA31  
AB1  
T
2/5  
2/5  
IDE_ADDR1  
TFTD2  
O
O
O
PMR[24] = 0  
1/4  
1/4  
IDE_DATA4  
IN  
,
PMR[24] = 0  
TS1  
O
PMR[24] = 1  
TS  
1/4  
AE2  
V
V
V
V
V
V
GND  
PWR  
GND  
GND  
PWR  
GND  
---  
---  
---  
---  
---  
---  
---  
---  
SS  
IO  
FP_VDD_ON  
O
O
PMR[24] = 1  
1/4  
AE3  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
AB2  
AB3  
AB4  
V
V
GND  
PWR  
I/O  
---  
---  
IN  
---  
---  
---  
SS  
AE4  
SS  
SS  
IO  
---  
IO  
AE28  
AE29  
AE30  
IDE_DATA3  
,
V
PMR[24] = 0  
TS1  
IO  
TS  
1/4  
TFTD12  
O
O
PMR[24] = 1  
1/4  
SS  
36  
AMD Geode™ SC3200 Processor Data Book  
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Signal Definitions  
Ball  
32581C  
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)  
1
1
I/O  
Buffer Power  
Rail Configuration  
Ball  
No.  
I/O  
Buffer Power  
Rail Configuration  
No.  
Signal Name  
(PU/PD) Type  
Signal Name  
(PU/PD) Type  
5
MD28  
I/O  
IN ,  
V
---  
AH12  
AH13  
AH14  
AH15  
WEA#  
O
GND  
PWR  
O
O
V
IO  
---  
---  
---  
---  
---  
AE31  
T
IO  
2/5  
TS  
2/5  
V
V
---  
---  
---  
---  
SS  
IO  
AF1  
AF2  
AF3  
IRQ14  
I
IN  
V
PMR[24] = 0  
PMR[24] = 1  
PMR[24] = 0  
PMR[24] = 1  
---  
TS1  
IO  
TFTD1  
O
O
O
O
I
O
O
O
O
1/4  
1/4  
1/4  
8/8  
MA1  
O
V
2/5  
IO  
IO  
IDE_CS0#  
TFTD5  
V
V
IO  
IO  
5
5
MD34  
I/O  
IN ,  
TS  
V
AH16  
AH17  
T
2/5  
SOUT1  
CLKSEL1  
MD37  
I/O  
IN ,  
TS  
V
---  
T
IO  
2/5  
IN  
Strap (See Table 3-  
4 on page 44.)  
STRP  
(PD  
)
AH18  
AH19  
V
PWR  
GND  
I/O  
---  
---  
---  
---  
---  
---  
---  
100  
IO  
AF4  
OVER_CUR#  
MD50  
I
IN  
V
V
---  
---  
V
TS  
IO  
IO  
SS  
5
5
5
5
I/O  
IN ,  
5
MD41  
IN ,  
T
TS  
V
AF28  
AF29  
AF30  
T
AH20  
IO  
TS  
2/5  
2/5  
MD49  
I/O  
I/O  
I/O  
I/O  
IN ,  
V
V
V
V
---  
AH21  
AH22  
AH23  
MA9  
O
O
O
O
O
V
V
V
V
---  
---  
---  
---  
T
IO  
IO  
IO  
IO  
2/5  
2/5  
2/5  
IO  
IO  
IO  
IO  
TS  
2/5  
MA8  
MD54  
IN ,  
---  
T
DQM1  
MD13  
O
TS  
2/5  
5
I/O  
IN ,  
TS  
AH24  
T
MD53  
IN ,  
---  
AF31  
AG1  
T
2/5  
TS  
2/5  
AH25  
AH26  
AH27  
V
GND  
O
---  
---  
---  
---  
---  
---  
SS  
GPIO18  
DTR1#/BOUT1  
IN  
O
,
PMR[16] = 0  
PMR[16] =1  
TS  
(PU  
)
22.5  
8/8  
MA11  
CS1#  
MD18  
O
V
V
V
2/5  
2/5  
IO  
IO  
IO  
O
O
8/8  
O
O
(PU  
)
22.5  
5
5
5
5
I/O  
IN ,  
TS  
AH28  
AH29  
AH30  
T
AG2  
AG3  
AG4  
SIN1  
I
I
IN  
V
V
V
---  
TS  
IO  
IO  
IO  
2/5  
X27I  
WIRE  
---  
MD48  
MD20  
MD51  
I/O  
I/O  
I/O  
IN ,  
TS  
2/5  
V
V
V
V
---  
---  
---  
T
IO  
IO  
IO  
IO  
TEST1  
PLL6B  
O
I/O  
O
PMR[29] = 1  
PMR[29] = 0  
2/5  
IN ,  
TS  
IN  
,
T
TS  
TS  
2/5  
2/5  
IN ,  
TS  
5
5
MD21  
I/O  
IN ,  
V
---  
T
AH31  
AJ1  
AG28  
T
IO  
TS  
2/5  
2/5  
TEST2  
PLL5B  
O
O
2/5  
PMR[29] = 1  
PMR[29] = 0  
AG29  
AG30  
DQM6  
DQM2  
MD55  
O
O
O
O
V
V
V
---  
---  
---  
2/5  
2/5  
IO  
IO  
IO  
I/O  
IN ,  
TS  
T
2/5  
I/O  
IN ,  
AG31  
T
AJ2  
AJ3  
AJ4  
X32I  
I
O
WIRE  
WIRE  
---  
V
V
---  
---  
---  
---  
---  
TS  
BAT  
BAT  
2/5  
X32O  
AH1  
AH2  
AH3  
POWER_EN  
X27O  
O
O
O
V
V
V
---  
1/4  
IO  
IO  
IO  
V
PLL3  
PWR  
O
---  
WIRE  
---  
5, 2  
ONCTL#  
GPWIO2  
OD  
V
TEST0  
O
O
PMR[29] = 1  
PMR[29] = 0  
14  
SB  
SB  
AJ5  
AJ6  
2/5  
I/O  
IN  
TS  
,
V
PLL2B  
I/O  
IN ,  
T
TS  
2/5  
TS  
(PU  
)
100  
PWR  
I/O  
2/14  
AJ7  
AJ8  
V
---  
---  
---  
AH4  
AH5  
V
PWR  
I
---  
---  
---  
---  
IO  
IO  
GPIO11  
IN  
O
,
V
PMR[18] = 0 and  
PMR[8] = 0  
PWRBTN#  
IN  
V
TS  
8/8  
IO  
BTN  
SB  
(PU  
)
(PU  
)
22.5  
100  
AH6  
GPWIO0  
I/O  
(PU  
IN  
TS  
,
V
---  
RI2#  
I
IN  
PMR[18] = 1 and  
PMR[8] = 0  
TS  
SB  
TS  
)
(PU  
)
)
100  
22.5  
2/14  
IRQ15  
MD0  
I
IN  
PMR[18] = 0 and  
PMR[8] = 1  
AH7  
AH8  
AH9  
V
GND  
O
---  
---  
---  
---  
---  
---  
TS1  
SS  
(PU  
22.5  
CLK32  
POR#  
MD3  
O
V
SB  
2/5  
5
I/O  
IN ,  
TS  
2/5  
V
---  
AJ9  
T
IO  
IO  
I
IN  
V
V
TS  
IO  
IO  
5
5
I/O  
IN ,  
TS  
AH10  
AH11  
T
AJ10  
AJ11  
V
PWR  
I/O  
---  
IN ,  
---  
---  
---  
IO  
2/5  
5
MD6  
V
T
MD5  
I/O  
IN ,  
TS  
V
---  
T
IO  
TS  
2/5  
2/5  
AMD Geode™ SC3200 Processor Data Book  
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37  
32581C  
Signal Definitions  
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)  
1
1
Ball  
No.  
I/O  
Buffer Power  
Rail Configuration  
Ball  
No.  
I/O  
Buffer Power  
Signal Name  
CASA#  
BA0  
(PU/PD) Type  
Signal Name  
(PU/PD) Type  
Rail Configuration  
AJ12  
AJ13  
AJ14  
O
O
O
O
O
V
V
V
V
---  
---  
---  
---  
AK15  
AK16  
MA2  
O
O
V
---  
---  
---  
2/5  
2/5  
2/5  
IO  
IO  
IO  
IO  
2/5  
IO  
V
PWR  
I/O  
---  
IO  
5
5
MA10  
O
MD35  
IN ,  
V
AK17  
AK18  
T
IO  
TS  
2/5  
5
5
5
5
5
5
MD32  
I/O  
IN ,  
AJ15  
AJ16  
AJ17  
AJ18  
AJ19  
AJ20  
T
TS  
MD46  
I/O  
IN ,  
V
---  
2/5  
T
IO  
TS  
2/5  
MD33  
MD36  
MD47  
MD45  
MD42  
SDCLK0  
I/O  
I/O  
I/O  
I/O  
I/O  
IN ,  
V
V
V
V
V
V
---  
---  
---  
---  
---  
T
IO  
IO  
IO  
IO  
IO  
IO  
TS  
AK19  
AK20  
V
PWR  
I/O  
---  
IN ,  
---  
---  
---  
2/5  
IO  
5
IN ,  
MD43  
V
T
T
IO  
TS  
TS  
2/5  
2/5  
IN ,  
AK21  
AK22  
AK23  
DQM5  
O
GND  
O
O
V
---  
---  
---  
---  
T
2/5  
IO  
TS  
2/5  
V
---  
---  
SS  
IN ,  
T
MA5  
O
V
V
2/5  
IO  
IO  
TS  
2/5  
5
MD15  
I/O  
IN ,  
AK24  
T
IN ,  
T
TS  
2/5  
TS  
2/5  
AK25  
AK26  
V
GND  
I/O  
---  
IN ,  
---  
---  
---  
SS  
AJ21  
AJ22  
AJ23  
AJ24  
AJ25  
O
PWR  
O
O
---  
---  
---  
---  
---  
---  
2/5  
5
5
MD14  
V
T
IO  
V
---  
---  
IO  
TS  
2/5  
MA6  
MA3  
O
O
V
V
2/5  
2/5  
IO  
IO  
MD12  
I/O  
IN ,  
V
---  
AK27  
T
IO  
O
TS  
2/5  
V
PWR  
I/O  
---  
IN ,  
---  
AK28  
AK29  
SDCLK_OUT  
MD16  
O
O
V
V
---  
---  
IO  
2/5  
IO  
IO  
5
5
5
MD11  
V
I/O  
IN ,  
AJ26  
T
IO  
T
TS  
TS  
2/5  
2/5  
AJ27  
AJ28  
SDCLK_IN  
MD19  
I
IN  
V
V
---  
---  
AK30  
AK31  
AL1  
AL2  
AL3  
AL4  
AL5  
AL6  
V
V
V
V
V
GND  
PWR  
GND  
PWR  
PWR  
O
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
T
IO  
IO  
SS  
IO  
I/O  
IN ,  
---  
---  
---  
---  
T
TS  
2/5  
SS  
IO  
AJ29  
AJ30  
V
PWR  
I/O  
---  
---  
---  
---  
IO  
5
5
MD22  
IN ,  
V
T
IO  
BAT  
TS  
2/5  
LED#  
OD  
V
SB  
14  
MD17  
I/O  
IN ,  
V
---  
AJ31  
T
IO  
TS  
V
PWR  
PWR  
O
---  
---  
---  
---  
2/5  
SB  
AK1  
AK2  
AK3  
AK4  
AK5  
V
PWR  
GND  
GND  
I
---  
---  
---  
---  
---  
---  
---  
---  
---  
V
IO  
SBL  
5, 2  
V
---  
---  
PWRCNT2  
SDATA_IN2  
OD  
V
SS  
AL7  
AL8  
14  
SB  
SB  
AV  
I
IN  
V
F3BAR0+Memory  
Offset 08h[21] = 1  
SSPLL3  
TS  
THRM#  
IN  
V
TS  
SB  
SB  
5
MD2  
MD4  
I/O  
I/O  
IN ,  
V
V
---  
AL9  
T
IO  
IO  
GPWIO1  
I/O  
IN  
,
V
Ts  
TS  
2/5  
(PU  
)
TS  
100  
2/14  
5
IN ,  
---  
AL10  
T
5, 2  
PWRCNT1  
O
OD  
V
---  
AK6  
AK7  
14  
SB  
TS  
2/5  
V
GND  
---  
---  
---  
SS  
AL11  
AL12  
AL13  
AL14  
AL15  
AL16  
DQM0  
CS0#  
O
O
O
O
V
V
---  
---  
---  
---  
---  
---  
---  
2/5  
2/5  
IO  
IO  
AK8  
IRRX1  
SIN3  
MD1  
I
I
IN  
V
PMR[6] = 0  
PMR[6] =1  
---  
TS  
TS  
SB  
IN  
V
V
IO  
IO  
V
GND  
O
---  
---  
SS  
5
I/O  
IN ,  
AK9  
T
MA0  
O
O
V
V
2/5  
2/5  
IO  
IO  
TS  
2/5  
DQM4  
O
AK10  
AK11  
V
GND  
I/O  
---  
---  
---  
---  
SS  
V
GND  
I/O  
---  
IN ,  
---  
SS  
5
MD7  
IN ,  
V
T
IO  
5
5
MD38  
V
TS  
AL17  
T
IO  
2/5  
TS  
2/5  
AK12  
AK13  
AK14  
RASA#  
O
PWR  
O
O
V
---  
---  
---  
2/5  
IO  
MD39  
I/O  
IN ,  
V
---  
---  
AL18  
AL19  
T
IO  
V
---  
---  
IO  
TS  
2/5  
BA1  
O
V
2/5  
IO  
V
GND  
---  
---  
SS  
38  
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Signal Definitions  
Ball  
32581C  
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)  
1
1
I/O  
Buffer Power  
Rail Configuration  
Ball  
No.  
I/O  
Buffer Power  
Rail Configuration  
No.  
Signal Name  
(PU/PD) Type  
Signal Name  
(PU/PD) Type  
5
5
MD44  
I/O  
I/O  
IN ,  
V
---  
AL30  
AL31  
V
V
PWR  
GND  
---  
---  
---  
---  
---  
---  
AL20  
T
IO  
IO  
TS  
2/5  
SS  
MD40  
IN ,  
V
---  
AL21  
T
IO  
1.  
2.  
For Buffer Type definitions, refer to Table 9-10 "Buffer Types" on page  
357.  
Is 5V tolerant (ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#,  
PD[7:0], PE, SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#,  
PWRCNT[2:1]).  
The TFT_PRSNT strap determines the power-on reset (POR) state of  
PMR[23].  
The LPC_ROM strap determines the power-on reset (POR) state of  
PMR[14] and PMR[22].  
Is back-drive protected (MD[63:0], DPOS_PORT1, DNEG_PORT1,  
DPOS_PORT2, DNEG_PORT2, DPOS_PORT3, DNEG_PORT3,  
ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], PE,  
SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]).  
TS  
2/5  
AL22  
AL23  
AL24  
CKEA  
MA7  
MA4  
MD8  
O
O
O
O
O
V
V
V
V
---  
---  
---  
---  
2/5  
2/5  
2/5  
IO  
IO  
IO  
IO  
3.  
4.  
5.  
O
5
5
5
I/O  
IN ,  
AL25  
AL26  
AL27  
T
TS  
2/5  
MD10  
MD9  
I/O  
I/O  
IN ,  
V
V
---  
---  
T
IO  
IO  
TS  
2/5  
IN ,  
T
TS  
2/5  
AL28  
AL29  
MA12  
MD23  
O
O
V
V
---  
---  
2/5  
IO  
IO  
5
I/O  
IN ,  
TS  
T
2/5  
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39  
32581C  
Signal Definitions  
Table 3-3. BGU481 Ball Assignment - Sorted Alphabetically by Signal Name  
Signal Name  
Ball No.  
Signal Name  
Ball No.  
Signal Name  
Ball No.  
A0  
U1  
P3  
U3  
N1  
P1  
N3  
N2  
M2  
M4  
L2  
AD18  
E3  
E2  
D3  
D1  
D2  
B6  
C2  
C4  
C1  
D4  
B4  
B3  
A3  
D5  
D22  
D27  
D8  
L1  
J2  
A1  
AD19  
D9  
A2  
AD20  
D10  
F3  
A3  
AD21  
D11  
H4  
A4  
AD22  
D12  
J4  
A5  
AD23  
D13  
F1  
A6  
AD24  
D14  
F2  
A7  
AD25  
D15  
G1  
A8  
AD26  
DCD2#  
C28  
E4  
A9  
AD27  
DEVSEL#  
DID0  
A10  
L3  
AD28  
C5  
A11  
K1  
L4  
AD29  
DID1  
C6  
A12  
AD30  
DNEG_PORT1  
DNEG_PORT2  
DNEG_PORT3  
DOCCS#  
DOCR#  
DOCW#  
DPOS_PORT1  
DPOS_PORT2  
DPOS_PORT3  
DQM0  
A29  
B28  
A27  
A9, N31  
D9  
A13  
J1  
AD31  
A14  
K4  
J3  
AFD#/DSTRB#  
AVCCUSB  
A15  
A16  
E1  
F4  
AVSSPLL2  
AVSSPLL3  
AVSSUSB  
C16  
AK3  
C27  
A17  
A8  
A18  
E3  
E2  
D3  
D1  
D2  
B6  
N31  
N30  
N29  
M29  
P31  
U29  
B18  
U1  
P3  
U3  
N1  
P1  
N3  
N2  
M2  
M4  
L2  
A28  
B27  
A26  
AL11  
AH23  
AG30  
AC31  
AL15  
AK21  
AG29  
AB31  
B29  
AG1  
D28  
D21  
C21  
A21  
D20  
C20  
C18  
C19  
A20  
A18  
D21  
B17  
D17  
C17  
V31  
A22  
U31  
B20  
A19  
BA0  
AJ13  
AK14  
E4  
A20  
BA1  
A21  
BHE#  
BIT_CLK  
BOOT16  
BUSY/WAIT#  
C/BE0#  
C/BE1#  
C/BE2#  
C/BE3#  
CASA#  
CKEA  
CLK27M  
CLK32  
CLKSEL0  
CLKSEL1  
CLKSEL2  
CLKSEL3  
CS0#  
A22  
DQM1  
U30  
C8  
A23  
DQM2  
AB1C  
AB1D  
AB2C  
AB2D  
AC97_CLK  
AC97_RST#  
ACK#  
AD0  
AD1  
AD2  
AD3  
AD4  
AD5  
AD6  
AD7  
AD8  
AD9  
AD10  
AD11  
AD12  
AD13  
AD14  
AD15  
AD16  
AD17  
DQM3  
B17  
L1  
DQM4  
DQM5  
J2  
DQM6  
F3  
DQM7  
H4  
DSR2#  
AJ12  
AL22  
AA4  
AH8  
B8  
DTR1#/BOUT1  
DTR2#/BOUT2  
ERR#  
F_AD0  
F_AD1  
AF3  
D29  
P30  
AL12  
AH27  
C31  
C2  
F_AD2  
F_AD3  
F_AD4  
F_AD5  
CS1#  
F_AD6  
CTS2#  
D0  
F_AD7  
L3  
F_C/BE0#  
F_C/BE1#  
F_C/BE2#  
F_C/BE3#  
F_DEVSEL#  
F_FRAME#  
F_GNT0#  
F_IRDY#  
D1  
C4  
K1  
L4  
D2  
C1  
D3  
D4  
J1  
D4  
B4  
K4  
J3  
D5  
B3  
D6  
A3  
E1  
F4  
D7  
D5  
40  
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Signal Definitions  
32581C  
Table 3-3. BGU481 Ball Assignment - Sorted Alphabetically by Signal Name (Continued)  
Signal Name  
Ball No.  
Signal Name  
Ball No.  
Signal Name  
Ball No.  
F_STOP#  
F_TRDY#  
FP_VDD_ON  
FPCI_MON  
FPCICLK  
FRAME#  
GNT0#  
U29  
U30  
V30, AB1  
A4  
IDE_DATA1  
IDE_DATA2  
IDE_DATA3  
IDE_DATA4  
IDE_DATA5  
IDE_DATA6  
IDE_DATA7  
IDE_DATA8  
IDE_DATA9  
IDE_DATA10  
IDE_DATA11  
IDE_DATA12  
IDE_DATA13  
IDE_DATA14  
IDE_DATA15  
IDE_DREQ0  
IDE_DREQ1  
IDE_IOR0#  
IDE_IOR1#  
IDE_IORDY0  
IDE_IORDY1  
IDE_IOW0#  
IDE_IOW1#  
IDE_RST#  
INIT#  
AC1  
AC2  
AB4  
AB1  
AA4  
AA3  
AA2  
Y3  
LOCK#  
LPC_ROM  
LPCPD#  
MA0  
H3  
D6  
K28  
AL14  
AH15  
AK15  
AJ24  
AL24  
AK23  
AJ23  
AL23  
AH22  
AH21  
AJ14  
AH26  
AL28  
AJ9  
B18  
D8  
MA1  
MA2  
C5  
MA3  
GNT1#  
C6  
MA4  
GPIO0  
D11  
D10, N30  
D28  
C30  
C31  
C28  
B29  
AJ8  
N29  
M29  
D9  
Y2  
MA5  
GPIO1  
Y1  
MA6  
GPIO6  
W4  
MA7  
GPIO7  
W3  
MA8  
GPIO8  
V3  
MA9  
GPIO9  
V2  
MA10  
MA11  
MA12  
MD0  
GPIO10  
V1  
GPIO11  
AC4  
C31  
Y4  
GPIO12  
GPIO13  
MD1  
AK9  
GPIO14  
D28  
AD1  
B29  
AD2  
C28  
AA1  
B21  
D26  
C26  
C9  
MD2  
AL9  
GPIO15  
A8  
MD3  
AH10  
AL10  
AH11  
AJ11  
AK11  
AL25  
AL27  
AL26  
AJ26  
AK27  
AH24  
AK26  
AK24  
AK29  
AJ31  
AH28  
AJ28  
AH30  
AG28  
AJ30  
AL29  
AB28  
AC28  
AC29  
AC30  
AE31  
AD29  
AD30  
AD31  
AJ15  
GPIO16  
V31  
A10  
AG1  
C9  
MD4  
GPIO17  
MD5  
GPIO18  
MD6  
GPIO19  
MD7  
GPIO20  
A9, N31  
M28  
L31  
MD8  
GPIO32  
INTA#  
MD9  
GPIO33  
INTB#  
MD10  
MD11  
MD12  
MD13  
MD14  
MD15  
MD16  
MD17  
MD18  
MD19  
MD20  
MD21  
MD22  
MD23  
MD24  
MD25  
MD26  
MD27  
MD28  
MD29  
MD30  
MD31  
MD32  
GPIO34  
L30  
INTC#  
GPIO35  
L29  
INTD#  
AA2  
D22  
C9  
GPIO36  
L28  
INTR_O  
GPIO37  
K31  
K28  
J31  
IOCHRDY  
IOCS0#  
GPIO38/IRRX2  
GPIO39  
A10  
D10  
N30  
D9  
IOCS1#  
GPIO40  
Y3  
IOCS1#  
GPIO41  
W4  
IOR#  
GPWIO0  
GPWIO1  
GPWIO2  
GTEST  
AH6  
AK5  
AJ6  
F30  
V30  
A11  
AD3  
AE1  
U2  
IOW#  
A8  
IRDY#  
F2  
IRQ9  
AA3  
AF1  
AJ8  
AK8  
C11  
M28  
L31  
L30  
L29  
L28  
AL4  
K31  
IRQ14  
GXCLK  
IRQ15  
HSYNC  
IRRX1  
IDE_ADDR0  
IDE_ADDR1  
IDE_ADDR2  
IDE_CS0#  
IDE_CS1#  
IDE_DACK0#  
IDE_DACK1#  
IDE_DATA0  
IRTX  
LAD0  
LAD1  
AF2  
P2  
LAD2  
LAD3  
AD4  
C30  
AC3  
LDRQ#  
LED#  
LFRAME#  
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41  
32581C  
Signal Definitions  
Table 3-3. BGU481 Ball Assignment - Sorted Alphabetically by Signal Name (Continued)  
Signal Name  
Ball No.  
Signal Name  
Ball No.  
Signal Name  
Ball No.  
MD33  
MD34  
MD35  
MD36  
MD37  
MD38  
MD39  
MD40  
MD41  
MD42  
MD43  
MD44  
MD45  
MD46  
MD47  
MD48  
MD49  
MD50  
MD51  
MD52  
MD53  
MD54  
MD55  
MD56  
MD57  
MD58  
MD59  
MD60  
MD61  
MD62  
MD63  
NC (Total of 13)  
AJ16  
AH16  
AK17  
AJ17  
AH17  
AL17  
AL18  
AL21  
AH20  
AJ20  
AK20  
AL20  
AJ19  
AK18  
AJ18  
AH29  
AF29  
AF28  
AH31  
AD28  
AF31  
AF30  
AG31  
Y31  
PD4  
C18  
C19  
A20  
A18  
D17  
H2  
STB#/WRITE#  
STOP#  
SYNC  
A22  
G1  
PD5  
PD6  
P30  
PD7  
TCK  
E31  
PE  
TDI  
F29  
PERR#  
PLL2B  
TDN  
D31  
AH3  
AJ1  
AG4  
AH9  
AH1  
AH5  
AK6  
AL7  
AK12  
B8  
TDO  
E30  
PLL5B  
TDP  
D30  
PLL6B  
TEST0  
TEST1  
TEST2  
TEST3  
TFT_PRSNT  
TFTD0  
TFTD1  
TFTD2  
TFTD3  
TFTD4  
TFTD5  
TFTD6  
TFTD7  
TFTD8  
TFTD9  
TFTD10  
TFTD11  
TFTD12  
TFTD13  
TFTD14  
TFTD15  
TFTD16  
TFTD17  
TFTDCK  
TFTDE  
THRM#  
TMS  
AH3  
POR#  
AG4  
POWER_EN  
PWRBTN#  
PWRCNT1  
PWRCNT2  
RASA#  
AJ1  
V30  
P29  
A9, AD4  
A20, AF1  
D22, AE1  
B17, AD3  
D21, U2  
B21, AF2  
C21, AC3  
A21, V1  
D20, AC4  
C20, AD2  
C18, Y4  
C19, AD1  
D10, AB4  
A18, W3  
D17, AC2  
C17, V3  
B20, AC1  
A22, V2  
A10, AA1  
B18, P2  
AK4  
RD#  
REQ0#  
B5  
REQ1#  
A5  
RI2#  
AJ8  
C8  
ROMCS#  
RTS2#  
C30  
U31  
AL8  
P29  
AJ27  
AK28  
AJ21  
W29  
AA28  
V29  
C30  
B29  
C28  
E28  
C31  
D28  
J31  
SDATA_IN  
SDATA_IN2  
SDATA_OUT  
SDCLK_IN  
SDCLK_OUT  
SDCLK0  
SDCLK1  
SDCLK2  
SDCLK3  
SDTEST0  
SDTEST1  
SDTEST2  
SDTEST3  
SDTEST4  
SDTEST5  
SERIRQ  
SERR#  
SIN1  
W28  
Y28  
Y29  
Y30  
AA29  
AA30  
AA31  
A14, A15, A23,  
A24, A25, B12,  
B15, B23, B26,  
C23, C24, D16,  
D24  
F28  
TRDE#  
TRDY#  
TRST#  
VBAT  
D11  
ONCTL#  
OVER_CUR#  
PAR  
AJ5  
AF4  
J4  
F1  
H1  
E29  
AG2  
E28  
AK8  
C17  
B20  
B21  
AF3  
D29  
C11  
AL3  
PC_BEEP  
PCICLK  
PCICLK0  
PCICLK1  
PCIRST#  
PD0  
V31  
A7  
SIN2  
V
CORE (Total of 29) D12, N13, N14,  
N18, N19, P4,  
SIN3  
A4  
P13, P14, P18,  
P19, P28, T1, T2,  
T3, T4, T28, T29,  
T30, T31, U4,  
U28, V13, V14,  
V18, V19, W13,  
W14, W18, W19  
SLCT  
D6  
SLIN#/ASTRB#  
SMI_O  
A6  
C21  
A21  
D20  
C20  
SOUT1  
SOUT2  
SOUT3  
PD1  
PD2  
PD3  
42  
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Signal Definitions  
32581C  
Table 3-3. BGU481 Ball Assignment - Sorted Alphabetically by Signal Name (Continued)  
Signal Name  
IO (Total of 46)  
Ball No.  
Signal Name  
Ball No.  
Signal Name  
Ball No.  
V
A2, A12, A30, B2,  
B13, B16, B19,  
B31, C3, C7,  
C10, C13, C22,  
C25, C29, D14,  
D15, D18, D23,  
G3, G29, K2,  
K29, M3, M30,  
W1, W31, AB3,  
AB29, AE3,  
VSS (Total of 96)  
A1, A13, A16,  
A19, A31, B1, B7,  
B10, B14, B22,  
B24, B25, B30,  
C12, C14, C15,  
D7, D13, D19,  
D25, G2, G4,  
G28, G30, K3,  
K30, M1, M31,  
N4, N15, N16,  
N17, N28, P15,  
P16, P17, R1, R2,  
R3, R4, R13,  
R14, R15, R16,  
R17, R18, R19,  
R28, R29, R30,  
R31, T13, T14,  
T15, T16, T17,  
T18, T19, U13,  
U14, U15, U16,  
U17, U18, U19,  
V4, V15, V16,  
V17, V28, W2,  
W15, W16, W17,  
W30, AB2, AB30,  
AE2, AE4, AE28,  
AE30, AH7,  
WEA#  
WR#  
X27I  
AH12  
B9  
AG3  
AH2  
AJ2  
AJ3  
X27O  
X32I  
X32O  
AE29, AH4,  
AH14, AH18,  
AJ7, AJ10, AJ22,  
AJ25, AJ29, AK1,  
AK13, AK16,  
AK19, AK31,  
AL2, AL30  
VPCKIN  
VPD0  
VPD1  
VPD2  
VPD3  
VPD4  
VPD5  
VPD6  
VPD7  
VPLL2  
F31  
J30  
J29  
J28  
H31  
H30  
H29  
H28  
G31  
A17  
AH13, AH19,  
AH25, AK2, AK7,  
AK10, AK22,  
AK25, AK30,  
AL1, AL13, AL16,  
AL19, AL31  
VPLL3  
VSB  
AJ4  
AL5  
AL6  
VSYNC  
B11  
VSBL  
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32581C  
Signal Definitions  
3.2  
Strap Options  
Several balls are read at power-up that set up the state of  
the SC3200. These balls are typically multiplexed with  
other functions that are outputs after the power-up  
sequence is complete. The SC3200 must read the state of  
the balls at power-up and the internal PU or PD resistors  
do not guarantee the correct state will be read. Therefore, it  
is required that an external PU or PD resistor with a value  
of 1.5 KΩ be placed on the balls listed in Table 3-4. The  
value of the resistor is important to ensure that the proper  
state is read during the power-up sequence. If the ball is  
not read correctly at power-up, the SC3200 may default to  
a state that causes it to function improperly, possibly result-  
ing in application failure.  
Table 3-4. Strap Options  
Nominal  
Internal  
External PU/PD Strap Settings  
Strap  
Option  
Muxed With  
RD#  
Ball No. PU or PD Strap = 0 (PD) Strap = 1 (PU) Register References  
CLKSEL0  
CLKSEL1  
CLKSEL2  
CLKSEL3  
B8  
PD100  
PD100  
PD100  
PD100  
See Table 4-7 on page 83 for  
CLKSEL strap options.  
GCB+I/O Offset 1Eh[9:8] (aka CCFC regis-  
ter bits [9:8]) (RO): Value programmed at  
reset by  
SOUT1  
SOUT2  
SYNC  
AF3  
D29  
P30  
CLKSEL[1:0].  
GCB+I/O Offset 10h[3:0] (aka MCCM regis-  
ter bits [3:0]) (RO): Value programmed at  
reset by  
CLKSEL[3:0].  
GCB+I/O Offset 1Eh[3:0] (aka CCFC regis-  
ter bits [3:0]) (R/W, but write not recom-  
mended): Value programmed at reset by  
CLKSEL[3:0].  
Note: Values for GCB+I/O Offset 10h[3:0]  
and 1Eh[3:0] are not the same.  
BOOT16  
ROMCS#  
C8  
PD100  
Enable boot  
from 8-bit ROM from 16-bit  
ROM  
Enable boot  
GCB+I/O Offset 34h[3] (aka MCR register  
bit 3) (RO): Reads back strap setting.  
GCB+I/O Offset 34h[14] (R/W): Used to  
allow the ROMCS# width to be changed  
under program control.  
TFT_PRSNT SDATA_OUT  
P29  
D6  
PD100  
PD100  
PD100  
TFT not muxed TFT muxed  
GCB+I/O Offset 30h[23] (aka PMR register  
bit 23) (R/W): Reads back strap setting.  
onto Parallel  
Port  
onto Parallel  
Port  
LPC_ROM  
FPCI_MON  
PCICLK1  
PCICLK0  
Disable boot  
from ROM on  
LPC bus  
Enable boot  
from ROM on  
LPC bus  
F0BAR1+I/O Offset 10h[15] (R/W): Reads  
back strap setting and allows LPC ROM to  
be changed under program control.  
A4  
Disable Fast-  
PCI, INTR_O,  
and SMI_O  
Enable Fast-  
PCI, INTR_O,  
and SMI_O  
GCB+I/O Offset 34h[30] (aka MCR register  
bit 30) (RO): Reads back strap setting.  
Note:  
For normal operation, strap this  
monitoring sig- monitoring sig-  
signal low using a 1.5 KΩ resistor.  
nals.  
nals. (Useful  
during debug.)  
DID0  
DID1  
GNT0#  
GNT1#  
C5  
C6  
PD100  
PD100  
Defines the system-level chip ID. GCB+I/O Offset 34h[31,29] (aka MCR regis-  
ter bits 31 and 29) (RO): Reads back strap  
setting.  
Note:  
GNT0# must have a PU resistor of  
1.5 KΩ and GNT1# must have a  
PU resistor of 1.5 KΩ.  
Note: Accuracy of internal PU/PD resistors: 80K to 250K.  
Location of the GCB (General Configuration Block) cannot be determined by software. See the AMD Geode™ SC3200 Specifi-  
cation Update document.  
44  
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Signal Definitions  
32581C  
3.3  
Multiplexing Configuration  
The tables that follow list multiplexing options and their  
configurations. Certain multiplexing options may be chosen  
per signal; others are available only for a group of signals.  
system reset, the pull-up is present. This pull-up resistor  
can be disabled by writing Core Logic registers. The config-  
uration is without regard to the selected ball function. The  
above applies to all pins multiplexed with GPIO, except  
GPIO12, GPIO13, and GPIO16.  
Where ever a GPIO pin is multiplexed with another func-  
tion, there is an optional pull-up resistor on this pin; after  
Table 3-5. Two-Signal/Group Multiplexing  
Default  
Alternate  
Configuration  
Ball No.  
Signal  
Configuration  
Signal  
IDE  
TFT, PCI, GPIO, System  
AD3  
AE1  
U2  
IDE_ADDR0  
IDE_ADDR1  
IDE_ADDR2  
IDE_DATA0  
IDE_DATA1  
IDE_DATA2  
IDE_DATA3  
IDE_DATA4  
IDE_DATA5  
IDE_DATA6  
IDE_DATA7  
IDE_DATA8  
IDE_DATA9  
IDE_DATA10  
IDE_DATA11  
IDE_DATA12  
IDE_DATA13  
IDE_DATA14  
IDE_DATA15  
IDE_IOR0#  
IDE_IORDY0  
IDE_DREQ0  
IDE_IOW0#  
IDE_CS0#  
PMR[24] = 0  
TFTD3  
PMR[24] = 1  
TFTD2  
TFTD4  
AC3  
AC1  
AC2  
AB4  
AB1  
AA4  
AA3  
AA2  
Y3  
TFTD6  
TFTD16  
TFTD14  
TFTD12  
FP_VDD_ON  
CLK27M  
IRQ9  
INTD#  
GPIO40  
DDC_SDA  
DDC_SCL  
GPIO41  
TFTD13  
TFTD15  
TFTD17  
TFTD7  
Y2  
Y1  
W4  
W3  
V3  
V2  
V1  
Y4  
TFTD10  
TFTD11  
TFTD8  
AD1  
AC4  
AD2  
AF2  
P2  
TFTD9  
TFTD5  
IDE_CS1#  
TFTDE  
TFTD0  
AD4  
AA1  
AF1  
IDE_DACK0#  
IDE_RST#  
TFTDCK  
TFTD1  
IRQ14  
Sub-ISA  
GPIO  
D11  
TRDE#  
PMR[12] = 0  
GPIO0  
PMR[12] = 1  
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32581C  
Signal Definitions  
Table 3-5. Two-Signal/Group Multiplexing (Continued)  
Default  
Alternate  
Configuration  
Ball No.  
Signal  
Configuration  
Signal  
GPIO  
ACCESS.bus  
N29  
M29  
GPIO12  
PMR[19] = 0  
AB2C  
AB2D  
PMR[19] = 1  
GPIO13  
GPIO  
UART  
AG1  
GPIO18  
PMR[16] = 0  
Infrared  
DTR1#/BOUT1  
PMR[16] = 1  
UART  
C11  
AK8  
IRTX  
PMR[6] = 0  
SOUT3  
SIN3  
PMR[6] = 1  
IRRX1  
GPIO  
LPC  
M28  
L31  
L30  
L29  
L28  
K31  
K28  
J31  
GPIO32  
PMR[14] = 0 and PMR[22] = LAD0  
PMR[14] = 1 and PMR[22] =  
1
0
GPIO33  
LAD1  
GPIO34  
LAD2  
LAD3  
GPIO35  
GPIO36  
LDRQ#  
GPIO37  
LFRAME#  
LPCPD#  
SERIRQ  
GPIO38/IRRX2  
GPIO39  
UART  
Internal Test  
E28  
SIN2  
PMR[28] = 0  
AC97  
SDTEST3  
PMR[28] = 1  
FPCI Monitoring  
FPCI_MON = 1  
U29  
U31  
U30  
AC97_RST#  
SDATA_IN  
BIT_CLK  
FPCI_MON = 0  
F_STOP#  
F_GNT0#  
F_TRDY#  
Internal Test  
PMR[29] = 0  
Internal Test  
AG4  
AJ1  
AH3  
PLL6B  
PLL5B  
PLL2B  
TEST1  
TEST2  
TEST0  
PMR[29] = 1  
Table 3-6. Three-Signal/Group Multiplexing  
Default  
Configuration  
Alternate1  
Alternate2  
Ball No.  
Signal  
Signal  
Configuration  
Sub-ISA1  
Signal  
Configuration  
Sub-ISA  
GPIO  
PMR[21] = 1 and  
D9  
A8  
IOR#  
IOW#  
PMR[21] = 0 and  
PMR[2] = 0  
DOCR#  
DOCW#  
PMR[21] = 0 and  
PMR[2] = 1  
GPIO14  
GPIO15  
PMR[2] = 1  
GPIO  
AC97  
FPCI Monitoring  
46  
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Signal Definitions  
32581C  
Table 3-6. Three-Signal/Group Multiplexing (Continued)  
Default  
Configuration  
Alternate1  
Configuration  
Alternate2  
Configuration  
FPCI_MON = 1  
Ball No.  
Signal  
Signal  
Signal  
V31  
GPIO16  
PMR[0] = 0 and  
FPCI_MON = 0  
PC_BEEP  
PMR[0] = 1 = 0 and  
FPCI_MON = 0  
F_DEVSEL  
GPIO  
PCI2  
Sub-ISA  
C9  
GPIO19  
PMR[9] = 0 and  
PMR[4] = 0  
INTC#  
PMR[9] = 0 and  
PMR[4] = 1  
IOCHRDY  
PMR[9] = 1 and  
PMR[4] = 1  
Parallel Port  
TFT3  
FPCI Monitoring  
B18  
D22  
B17  
D21  
B21  
C21  
A21  
D20  
C20  
C18  
C19  
A20  
A18  
D17  
C17  
B20  
ACK#  
PMR[23] = 0 and  
(PMR[27] = 0 and  
FPCI_MON = 0)  
TFTDE  
TFTD2  
TFTD3  
TFTD4  
TFTD5  
TFTD6  
TFTD7  
TFTD8  
TFTD9  
TFTD10  
TFTD11  
TFTD1  
TFTD13  
TFTD14  
TFTD15  
TFTD16  
PMR[23] = 1 and  
(PMR[27] = 0 and  
FPCI_MON = 0)  
FPCI_CLK  
INTR_O  
F_C/BE1#  
F_C/BE0#  
SMI_O  
PMR[23] = 0 and  
(PMR[27] = 1 or  
FPCI_MON = 1)  
AFD#/DSTRB#  
BUSY/WAIT#  
ERR#  
INIT#  
PD0  
F_AD0  
PD1  
F_AD1  
PD2  
F_AD2  
PD3  
F_AD3  
PD4  
F_AD4  
PD5  
F_AD5  
PD6  
F_AD6  
PD7  
F_AD7  
PE  
F_C/BE2#  
F_C/BE3#  
F_IRDY  
SLCT  
SLIN#  
/ASTRB#  
A22  
STB#/WRITE#  
TFTD17  
F_FRAME#  
GPIO  
Sub-ISA  
TFT3  
A10  
A9  
GPIO17  
GPIO20  
GPIO1  
PMR[23] = 0 and  
PMR[5] = 0  
IOCS0#  
DOCCS#  
IOCS1#  
PMR[23] = 0 and  
PMR[5] = 1  
TFTDCK  
TFTD0  
PMR[23] = 1  
PMR[23] = 1  
PMR[23] = 1  
PMR[23] = 0 and  
PMR[7] = 0  
PMR[23] = 0 and  
PMR[7] = 1  
D10  
PMR[23] = 0 and  
PMR[13] = 0  
PMR[23] = 0 and  
PMR[13] = 1  
TFTD12  
AB1  
GPIO  
Sub-ISA  
N31  
N30  
AB1C  
AB1D  
PMR[23] = 0  
GPIO20  
GPIO1  
PMR[23] = 1 and  
PMR[7] = 0  
DOCCS#  
IOCS1#  
PMR[23] = 1 and  
PMR[7] = 1  
PMR[23] = 0  
PMR[23] = 1 and  
PMR[13] = 0  
PMR[23] = 1 and  
PMR[13] = 1  
GPIO  
UART2  
IDE2  
AJ8  
GPIO11  
PMR[18] = 0 and  
PMR[8] = 0  
RI2#  
PMR[18] = 1 and  
PMR[8] = 0  
IRQ15  
PMR[18] = 0 and  
PMR[8] = 1  
Internal Test  
Internal Test  
TFT  
PMR[23] = 1  
V30  
GXCLK  
PMR[23] = 0 and  
PMR[29] = 0  
TEST3  
PMR[23] = 0 and  
PMR[29] = 1  
FP_VDD_ON  
1. The combination of PMR[21] = 1 and PMR[2] = 0 is undefined and should not be used.  
2. The combination of PMR[9] = 1 and PMR[4] = 0 is undefined and should not be used.  
3. These TFT outputs are reset to 0 by POR# if the TFT_PRSNT strap is pulled high or PMR[10] = 0. This relates to signals TFTD[17:0],  
TFTDE, TFTDCK.  
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32581C  
Signal Definitions  
Alternate3  
Table 3-7. Four-Signal/Group Multiplexing  
Default  
Configuration  
Alternate1  
Signal Configuration  
Alternate2  
Signal Configuration  
Ball  
No.  
Signal  
Signal  
Configuration  
GPIO  
UART2  
PMR[17] = 1  
IDE2  
PMR[17] = 0  
Internal Test  
C30 GPIO7  
C31 GPIO8  
PMR[17] = 0  
and  
PMR[8] = 0  
RTS2#  
CTS2#  
IDE_DACK1#  
IDE_DREQ1  
SDTEST0  
SDTEST4  
PMR[17] = 1  
and  
PMR[8] = 1  
and  
PMR[8] = 0  
and  
PMR[8] = 1  
D28 GPIO6  
C28 GPIO9  
B29 GPIO10  
PMR[18] = 0  
and  
PMR[8] = 0  
DTR2#/BOUT2 PMR[18] = 1  
IDE_IOR1#  
IDE_IOW1#  
IDE_IORDY1  
PMR[18] = 0  
and  
PMR[8] = 1  
SDTEST5  
SDTEST2  
SDTEST1  
PMR[18] = 1  
and  
PMR[8] = 1  
and  
PMR[8] = 0  
DCD2#  
DSR2#  
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Signal Definitions  
32581C  
3.4  
Signal Descriptions  
Information in the tables that follow may have duplicate information in multiple tables. Multiple references all contain identi-  
cal information.  
3.4.1  
System Interface  
Signal Name  
Ball No.  
Type Description  
I Fast-PCI Clock Selects. These strap signals are used to  
Mux  
CLKSEL1  
CLKSEL0  
AF3  
B8  
SOUT1  
RD#  
set the internal Fast-PCI clock.  
00 = 33.3 MHz  
01 = 48 MHz  
10 = 66.7 MHz  
11 = 33.3 MHz  
During system reset, an internal pull-down resistor of 100  
KΩ exists on these balls. An external pull-up or pull-down  
resistor of 1.5 KΩ must be used.  
CLKSEL3  
CLKSEL2  
P30  
D29  
I
Maximum Core Clock Multiplier. These strap signals  
are used to set the maximum allowed multiplier value for  
the core clock.  
SYNC  
SOUT2  
During system reset, an internal pull-down resistor of 100  
KΩ exists on these balls. An external pull-up or pull-down  
resistor of 1.5 KΩ must be used.  
BOOT16  
C8  
D6  
I
I
Boot ROM is 16 Bits Wide. This strap signal enables  
the optional 16-bit wide Sub-ISA bus.  
ROMCS#  
PCICLK1  
During system reset, an internal pull-down resistor of 100  
KΩ exists on these balls. An external pull-up or pull-down  
resistor of 1.5 KΩ must be used.  
LPC_ROM  
LPC_ROM. This strap signal forces selecting of the LPC  
bus and sets bit F0BAR1+I/O Offset 10h[15], LPC ROM  
Addressing Enable. It enables the SC3200 to boot from a  
ROM connected to the LPC bus.  
During system reset, an internal pull-down resistor of 100  
KΩ exists on these balls. An external pull-up or pull-down  
resistor of 1.5 KΩ must be used.  
TFT_PRSNT  
FPCI_MON  
P29  
A4  
I
I
TFT Present. A strap used to select multiplexing of TFT  
signals at power-up. Enables using TFT instead of Paral-  
lel Port, ACB1, and GPIO17.  
SDATA_OUT  
PCICLK0  
During system reset, an internal pull-down resistor of 100  
KΩ exists on these balls. An external pull-up or pull-down  
resistor of 1.5 KΩ must be used.  
Fast-PCI Monitoring. The strap on this ball forces selec-  
tion of Fast-PCI monitoring signals. For normal operation,  
strap this signal low using a 1.5 KΩ resistor. The value of  
this strap can be read on the MCR[30].  
DID1  
DID0  
C6  
C5  
I
I
Device ID. Together, the straps on these signals define  
the system-level chip ID.  
GNT1#  
GNT0#  
The value of DID1 can be read in the MCR[29]. The  
value of DID0 can be read in the MCR[31].  
DID0 and DID1 must have a pull-up resistor of 1.5 KΩ.  
POR#  
AH9  
I
Power On Reset. POR# is the system reset signal gen-  
erated from the power supply to indicate that the system  
should be reset.  
---  
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32581C  
Signal Definitions  
Mux  
3.4.1  
System Interface (Continued)  
Signal Name  
Ball No.  
Type Description  
X32I  
AJ2  
AJ3  
I/O  
Crystal Connections. Connected directly to a 32.768  
---  
---  
KHz crystal. This clock input is required even if the inter-  
nal RTC is not being used. Some of the internal clocks  
are derived from this clock. If an external clock is used, it  
should be connected to X32I, using a voltage level of 0  
X32O  
volts to V  
+10% maximum. X32O should remain  
CORE  
unconnected.  
X27I  
AG3  
AH2  
I/O  
Crystal Connections. Connected directly to a  
---  
---  
27.000 MHz crystal. Some of the internal clocks are  
derived from this clock. If an external clock is used, it  
should be connected to X27I, using a voltage level of 0  
X27O  
volts to V and X27O should be remain unconnected.  
IO  
CLK27M  
PCIRST#  
AA4  
A6  
O
O
27 MHz Output Clock. Output of crystal oscillator.  
IDE_DATA5  
---  
PCI and System Reset. PCIRST# is the reset signal for  
the PCI bus and system. It is asserted for approximately  
100 µs after POR# is negated.  
3.4.2  
Memory Interface Signals  
Signal Name  
Ball No.  
Type Description  
Mux  
MD[63:0]  
See  
Table 3-3  
on page  
40.  
I/O  
Memory Data Bus. The data bus lines driven to/from  
system memory.  
---  
MA[12:0]  
See  
Table 3-3  
on page  
40.  
O
Memory Address Bus. The multiplexed row/column  
address lines driven to the system memory. Supports  
256-Mbit SDRAM.  
---  
BA1  
AK14  
AJ13  
AH27  
AL12  
O
O
Bank Address Bits. These bits are used to select the  
component bank within the SDRAM.  
---  
---  
---  
---  
BA0  
CS1#  
CS0#  
Chip Selects. These bits are used to select the module  
bank within system memory. Each chip select corre-  
sponds to a specific module bank. If CS# is high, the  
bank(s) do not respond to RAS#, CAS#, and WE# until  
the bank is selected again.  
RASA#  
CASA#  
WEA#  
AK12  
AJ12  
AH12  
O
O
O
Row Address Strobe. RAS#, CAS#, WE# and CKE are  
encoded to support the different SDRAM commands.  
RASA# is used with CS[1:0]#.  
---  
---  
---  
Column Address Strobe. RAS#, CAS#, WE# and CKE  
are encoded to support the different SDRAM commands.  
CASA# is used with CS[1:0]#.  
Write Enable. RAS#, CAS#, WE# and CKE are encoded  
to support the different SDRAM commands. WEA# is  
used with CS[1:0]#.  
50  
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Signal Definitions  
32581C  
3.4.2  
Memory Interface Signals (Continued)  
Signal Name  
Ball No.  
Type Description  
Mux  
DQM7  
DQM6  
DQM5  
DQM4  
DQM3  
DQM2  
DQM1  
DQM0  
CKEA  
AB31  
AG29  
AK21  
AL15  
AC31  
AG30  
AH23  
AL11  
AL22  
O
Data Mask Control Bits. During memory read cycles,  
---  
---  
---  
---  
---  
---  
---  
---  
---  
these outputs control whether SDRAM output buffers are  
driven on the MD bus or not. All DQM signals are  
asserted during read cycles.  
During memory write cycles, these outputs control  
whether or not MD data is written into SDRAM.  
DQM[7:0] connect directly to the [DQM7:0] pins of each  
DIMM connector.  
O
Clock Enable. These signals are used to enter Suspend/  
power-down mode. CKEA is used with CS[1:0]#.  
If CKE goes low when no read or write cycle is in  
progress, the SDRAM enters power-down mode. To  
ensure that SDRAM data remains valid, the self-refresh  
command is executed. To exit this mode, and return to  
normal operation, drive CKE high.  
These signals should have an external pull-down resistor  
of 33 KΩ.  
SDCLK3  
SDCLK2  
SDCLK1  
SDCLK0  
SDCLK_IN  
V29  
AA28  
W29  
AJ21  
AJ27  
O
SDRAM Clocks. SDRAM uses these clocks to sample  
all control, address, and data lines. To ensure that the  
Suspend mode functions correctly, SDCLK3 and  
SDCLK1 should be used with CS1#. SDCLK2 and  
SDCLK0 should be used together with CS0#.  
---  
---  
---  
---  
---  
I
SDRAM Clock Input. The SC3200 samples the memory  
read data on this clock. Works in conjunction with the  
SDCLK_OUT signal.  
SDCLK_OUT  
AK28  
O
SDRAM Clock Output. This output is routed back to  
SDCLK_IN. The board designer should vary the length of  
the board trace to control skew between SDCLK_IN and  
SDCLK.  
---  
3.4.3  
Video Port Interface Signals  
Signal Name  
Ball No.  
Type  
I
Description  
Mux  
VPD7  
VPD6  
VPD5  
VPD4  
VPD3  
VPD2  
VPD1  
VPD0  
VPCKIN  
G31  
H28  
H29  
H30  
H31  
J28  
J29  
J30  
F31  
Video Port Data. The data is input from the CCIR-  
656 video decoder.  
---  
---  
---  
---  
---  
---  
---  
---  
---  
I
Video Port Clock Input. The clock input from the  
video decoder.  
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32581C  
Signal Definitions  
3.4.4  
TFT Interface Signals  
Signal Name  
Ball No.  
Type Description  
Mux  
HSYNC  
VSYNC  
TFTDCK  
A11  
B11  
AA1  
A10  
P2  
O
O
O
Horizontal Sync  
---  
Vertical Sync  
TFT Clock.  
---  
IDE_RST#  
GPIO17+ IOCS0#  
IDE_CS1#  
TFTDE  
O
O
O
TFT Data Enable.  
B18  
AB1  
V30  
ACK#+FPCICLK  
IDE_DATA4  
GXCLK+TEST3  
FP_VDD_ON  
TFTD[17:0]  
TFT Power Control. Used to enable power to the flat  
panel display, with power sequence timing.  
See  
Table 3-3  
on page  
40.  
Digital RGB Data to TFT.  
The TFT interface is  
muxed with the IDE  
interface or the Par-  
allel Port. See Table  
3-5 on page 45 and  
Table 3-6 on page  
46 for details.  
TFTD[5:0] - Connect to the BLUE TFT inputs.  
TFTD[11:6] - Connect to GREEN TFT inputs.  
TFTD[17:12] - Connect to RED TFT inputs.  
3.4.5  
ACCESS.bus Interface Signals  
Signal Name  
Ball No.  
Type Description  
Mux  
AB1C  
N31  
I/O  
I/O  
I/O  
I/O  
ACCESS.bus 1 Serial Clock. This is the serial clock for  
the interface.  
GPIO20+DOCCS#  
Note: If selected as AB1C function but not used, tie  
AB1C high.  
AB1D  
AB2C  
AB2D  
N30  
N29  
M29  
ACCESS.bus 1 Serial Data. This is the bidirectional  
serial data signal for the interface.  
GPIO1+IOCS1#  
GPIO12  
Note: If AB1D function is selected but not used, tie  
AB1D high.  
ACCESS.bus 2 Serial Clock. This is the serial clock for  
the interface.  
Note: If AB2C function is selected but not used, tie  
AB2C high.  
ACCESS.bus 2 Serial Data. This is the bidirectional  
GPIO13  
serial data signal for the interface.  
Note: If AB2D function is selected but not used, tie  
AB2D high.  
52  
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Signal Definitions  
32581C  
3.4.6  
PCI Bus Interface Signals  
Signal Name  
PCICLK  
BalL No. Type Description  
Mux  
A7  
I
PCI Clock. PCICLK provides timing for all transactions  
on the PCI bus. All other PCI signals are sampled on the  
rising edge of PCICLK, and all timing parameters are  
defined with respect to this edge.  
---  
PCICLK0  
PCICLK1  
A4  
D6  
O
O
PCI Clock Outputs. PCICLK0 and PCICLK1 provide  
clock drives for the system at 33 MHz. These clocks are  
asynchronous to PCI signals. There is low skew between  
all outputs. One of these clock signals should be con-  
nected to the PCICLK input. All PCI clock users in the  
system (including PCICLK) should receive the clock with  
as low a skew as possible.  
FPCI_MON (Strap)  
LPC_ROM (Strap)  
AD[31:24]  
AD[23:0]  
See  
Table 3-3  
on page  
40.  
I/O  
Multiplexed Address and Data. A bus transaction con-  
sists of an address phase in the cycle in which FRAME#  
is asserted followed by one or more data phases. During  
the address phase, AD[31:0] contain a physical 32-bit  
address. For I/O, this is a byte address. For configuration  
and memory, it is a DWORD address. During data  
phases, AD[7:0] contain the least significant byte (LSB)  
and AD[31:24] contain the most significant byte (MSB).  
D[7:0]  
A[23:0]  
C/BE3#  
C/BE2#  
C/BE1#  
C/BE0#  
H4  
F3  
J2  
L1  
I/O  
Multiplexed Command and Byte Enables. During the  
address phase of a transaction when FRAME# is active,  
C/BE[3:0]# define the bus command. During the data  
phase, C/BE[3:0]# are used as byte enables. The byte  
enables are valid for the entire data phase and determine  
which byte lanes carry meaningful data. C/BE0# applies  
to byte 0 (LSB) and C/BE3# applies to byte 3 (MSB).  
D11  
D10  
D9  
D8  
INTA#  
INTB#  
INTC#  
INTD#  
D26  
C26  
C9  
I
PCI Interrupts. The SC3200 provides inputs for the  
optional “level-sensitive” PCI interrupts (also known in  
industry terms as PIRQx#). These interrupts can be  
mapped to IRQs of the internal 8259A interrupt control-  
lers using PCI Interrupt Steering Registers 1 and 2  
(F0 Index 5Ch and 5Dh).  
---  
---  
GPIO19+IOCHRDY  
IDE_DATA7  
AA2  
Note: If selected as INTC# or INTD# function(s) but not  
used, tie INTC# and INTD# high.  
PAR  
J4  
I/O  
Parity. Parity generation is required by all PCI agents.  
The master drives PAR for address- and write-data  
phases. The target drives PAR for read-data phases. Par-  
ity is even across AD[31:0] and C/BE[3:0]#.  
D12  
For address phases, PAR is stable and valid one PCI  
clock after the address phase. It has the same timing as  
AD[31:0] but is delayed by one PCI clock.  
For data phases, PAR is stable and valid one PCI clock  
after either IRDY# is asserted on a write transaction or  
after TRDY# is asserted on a read transaction.  
Once PAR is valid, it remains valid until one PCI clock  
after the completion of the data phase. (Also see  
PERR#.)  
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32581C  
Signal Definitions  
3.4.6  
PCI Bus Interface Signals (Continued)  
Signal Name  
BalL No. Type Description  
Mux  
FRAME#  
D8  
I/O  
Frame Cycle. Frame is driven by the current master to  
indicate the beginning and duration of an access.  
FRAME# is asserted to indicate the beginning of a bus  
transaction. While FRAME# is asserted, data transfers  
continue. FRAME# is de-asserted when the transaction  
is in the final data phase.  
---  
This signal is internally connected to a pull-up resistor.  
IRDY#  
TRDY#  
STOP#  
F2  
I/O  
Initiator Ready. IRDY# is asserted to indicate that the  
bus master is able to complete the current data phase of  
the transaction. IRDY# is used in conjunction with  
TRDY#. A data phase is completed on any PCI clock in  
which both IRDY# and TRDY# are sampled as asserted.  
During a write, IRDY# indicates that valid data is present  
on AD[31:0]. During a read, it indicates that the master is  
prepared to accept data. Wait cycles are inserted until  
both IRDY# and TRDY# are asserted together.  
D14  
D13  
D15  
This signal is internally connected to a pull-up resistor.  
F1  
I/O  
Target Ready. TRDY# is asserted to indicate that the tar-  
get agent is able to complete the current data phase of  
the transaction. TRDY# is used in conjunction with  
IRDY#. A data phase is complete on any PCI clock in  
which both TRDY# and IRDY# are sampled as asserted.  
During a read, TRDY# indicates that valid data is present  
on AD[31:0]. During a write, it indicates that the target is  
prepared to accept data. Wait cycles are inserted until  
both IRDY# and TRDY# are asserted together.  
This signal is internally connected to a pull-up resistor.  
G1  
I/O  
Target Stop. STOP# is asserted to indicate that the cur-  
rent target is requesting that the master stop the current  
transaction. This signal is used with DEVSEL# to indicate  
retry, disconnect, or target abort. If STOP# is sampled  
active by the master, FRAME# is de-asserted and the  
cycle is stopped within three PCI clock cycles. As an  
input, STOP# can be asserted in the following cases:  
1) If a PCI master tries to access memory that has  
been locked by another master. This condition is  
detected if FRAME# and LOCK# are asserted dur-  
ing an address phase.  
2) If the PCI write buffers are full or if a previously buff-  
ered cycle has not completed.  
3) On read cycles that cross cache line boundaries.  
This is conditional based upon the programming of  
GX1 module’s PCI Configuration Register, Index  
41h[1].  
This signal is internally connected to a pull-up resistor.  
54  
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Signal Definitions  
32581C  
3.4.6  
PCI Bus Interface Signals (Continued)  
Signal Name  
LOCK#  
BalL No. Type Description  
Mux  
H3  
I/O  
Lock Operation. LOCK# indicates an atomic operation  
that may require multiple transactions to complete. When  
LOCK# is asserted, non-exclusive transactions may pro-  
ceed to an address that is not currently locked (at least  
16 bytes must be locked). A grant to start a transaction  
on PCI does not guarantee control of LOCK#. Control of  
LOCK# is obtained under its own protocol in conjunction  
with GNT#.  
---  
It is possible for different agents to use PCI while a single  
master retains ownership of LOCK#. The arbiter can  
implement a complete system lock. In this mode, if  
LOCK# is active, no other master can gain access to the  
system until the LOCK# is de-asserted.  
This signal is internally connected to a pull-up resistor.  
DEVSEL#  
E4  
I/O  
Device Select. DEVSEL# indicates that the driving  
device has decoded its address as the target of the cur-  
rent access. As an input, DEVSEL# indicates whether  
any device on the bus has been selected. DEVSEL# is  
also driven by any agent that has the ability to accept  
cycles on a subtractive decode basis. As a master, if no  
DEVSEL# is detected within and up to the subtractive  
decode clock, a master abort cycle is initiated (except for  
special cycles which do not expect a DEVSEL#  
returned).  
BHE#  
This signal is internally connected to a pull-up resistor.  
PERR#  
H2  
I/O  
Parity Error. PERR# is used for reporting data parity  
errors during all PCI transactions except a Special Cycle.  
The PERR# line is driven two PCI clocks after the data in  
which the error was detected. This is one PCI clock after  
the PAR that is attached to the data. The minimum dura-  
tion of PERR# is one PCI clock for each data phase in  
which a data parity error is detected. PERR# must be  
driven high for one PCI clock before being placed in TRI-  
STATE. A target asserts PERR# on write cycles if it has  
claimed the cycle with DEVSEL#. The master asserts  
PERR# on read cycles.  
---  
This signal is internally connected to a pull-up resistor.  
SERR#  
H1  
I/O  
System Error. SERR# can be asserted by any agent for  
reporting errors other than PCI parity. When the PFS bit  
is enabled in the GX1 module’s PCI Control Function 2  
register (Index 41h[5]), SERR# is asserted upon asser-  
tion of PERR#.  
---  
This signal is internally connected to a pull-up resistor.  
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32581C  
Signal Definitions  
Mux  
3.4.6  
PCI Bus Interface Signals (Continued)  
Signal Name  
BalL No. Type Description  
REQ1#  
REQ0#  
A5  
B5  
I
Request Lines. REQ[1:0]# indicate to the arbiter that an  
agent requires the bus. Each master has its own REQ#  
line. REQ# priorities (in order) are:  
---  
---  
1) VIP  
2) IDE Channel 0  
3) IDE Channel 1  
4) Audio  
5) USB  
6) External REQ0#  
7) External REQ1#.  
Each REQ# is internally connected to a pull-up resistor.  
GNT1#  
GNT0#  
C6  
C5  
O
Grant Lines. GNT[1:0]# indicate to the requesting mas-  
ter that it has been granted access to the bus. Each mas-  
ter has its own GNT# line. GNT# can be retracted at any  
time a higher REQ# is received or if the master does not  
begin a cycle within a minimum period of time (16 PCI  
clocks).  
DID1 (Strap)  
DID0 (Strap)  
Each of these signals is internally connected to a pull-up  
resistor.  
GNT0# must have a pull-up resistor of 1.5 KΩ and  
GNT1# must have a pull-up resistor of 1.5 KΩ.  
56  
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Signal Definitions  
32581C  
3.4.7  
Sub-ISA Interface Signals  
Signal Name  
A[23:0]  
Ball No.  
Type  
Description  
Mux  
See Table  
3-3 on  
O
Address Lines  
AD[23:0]  
page 40.  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
See Table  
3-3 on  
page 40.  
I/O  
Data Bus  
STOP#  
IRDY#  
TRDY#  
PAR  
C/BE3#  
C/BE2#  
C/BE1#  
C/BE0#  
AD[31:24]  
DEVSEL#  
D8  
D[7:0]  
BHE#  
E4  
O
O
Byte High Enable. With A0, defines byte  
accessed for 16 bit wide bus cycles.  
IOCS1#  
D10  
N30  
A10  
C30  
A9  
I/O Chip Selects  
GPIO1+TFTD12  
AB1D+GPIO1  
GPIO17+TFTDCK  
BOOT16 (Strap)  
GPIO20+TFTD0  
AB1C+GPIO20  
GPIO0  
IOCS0#  
ROMCS#  
DOCCS#  
O
O
ROM or Flash ROM Chip Select  
DiskOnChip or NAND Flash Chip Select  
N31  
D11  
TRDE#  
O
Transceiver Data Enable Control. Active low for  
Sub-ISA data transfers. The signal timing is as fol-  
lows:  
• In a read cycle, TRDE# has the same timing as  
RD#.  
• In a write cycle, TRDE# is asserted (to active  
low) at the time WR# is asserted. It continues  
being asserted for one PCI clock cycle after  
WR# has been negated, then it is negated.  
RD#  
B8  
B9  
D9  
A8  
D9  
O
O
O
O
O
Memory or I/O Read. Active on any read cycle.  
Memory or I/O Write. Active on any write cycle.  
I/O Read. Active on any I/O read cycle.  
CLKSEL0 (Strap)  
---  
WR#  
IOR#  
IOW#  
DOCR#  
DOCR#+GPIO14  
DOCW#+GPIO15  
IOR#+GPIO14  
I/O Write. Active on any I/O write cycle.  
DiskOnChip or NAND Flash Read. Active on any  
memory read cycle to DiskOnChip.  
DOCW#  
IRQ9  
A8  
O
I
DiskOnChip or NAND Flash Write. Active on  
any memory write cycle to DiskOnChip.  
IOW#+GPIO15  
IDE_DATA6  
AA3  
Interrupt 9 Request Input. Active high.  
Note: If IRQ9 function is selected but not used,  
tie IRQ9 low.  
IOCHRDY  
C9  
I
I/O Channel Ready  
GPIO19+INTC#  
Note: If IOCHRDY function is selected but not  
used, tie IOCHRDY high.  
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32581C  
Signal Definitions  
3.4.8  
Low Pin Count (LPC) Bus Interface Signals  
Signal Name  
Ball No.  
Type  
Description  
Mux  
LAD3  
LAD2  
LAD1  
LAD0  
LDRQ#  
L29  
L30  
L31  
M28  
L28  
I/O  
LPC Address-Data. Multiplexed command,  
address, bidirectional data, and cycle status.  
GPIO35  
GPIO34  
GPIO33  
GPIO32  
GPIO36  
I
LPC DMA Request. Encoded DMA request for  
LPC interface.  
Note: If LDRQ# function is selected but not  
used, tie LDRQ# high.  
LFRAME#  
K31  
O
LPC Frame. A low pulse indicates the beginning  
of a new LPC cycle or termination of a broken  
cycle.  
GPIO37  
LPCPD#  
SERIRQ  
K28  
J31  
O
LPC Power-Down. Signals the LPC device to pre-  
pare for power shut-down on the LPC interface.  
GPIO38/IRRX2  
GPIO39  
I/O  
Serial IRQ. The interrupt requests are serialized  
over a single signal, where each IRQ level is deliv-  
ered during a designated time slot.  
Note: If SERIRQ function is selected but not  
used, tie SERIRQ high.  
3.4.9  
IDE Interface Signals  
Signal Name  
IDE_RST#  
Ball No.  
Type Description  
Mux  
AA1  
O
IDE Reset. This signal resets all the devices that are  
TFTDCK  
attached to the IDE interface.  
IDE_ADDR2  
IDE_ADDR1  
IDE_ADDR0  
IDE_DATA[15:0]  
U2  
O
IDE Address Bits. These address bits are used to  
access a register or data port in a device on the IDE bus.  
TFTD4  
TFTD2  
TFTD3  
AE1  
AD3  
See  
Table 3-3  
on page  
40.  
I/O  
IDE Data Lines. IDE_DATA[15:0] transfers data to/from  
the IDE devices.  
The IDE interface is  
muxed with the TFT  
interface. See Table  
3-5 on page 45 for  
details.  
IDE_IOR0#  
IDE_IOR1#  
Y4  
O
O
IDE I/O Read Channels 0 and 1. IDE_IOR0# is the read  
signal for Channel 0 and IDE_IOR1# is the read signal  
for Channel 1. Each signal is asserted at read accesses  
to the corresponding IDE port addresses.  
TFTD10  
D28  
GPIO6+DTR2#/  
BOUT2+SDTEST5#  
IDE_IOW0#  
IDE_IOW1#  
AD2  
C28  
O
O
IDE I/O Write Channels 0 and 1. IDE_IOW0# is the  
write signal for Channel 0. IDE_IOW1# is the write signal  
for Channel 1. Each signal is asserted at write accesses  
to corresponding IDE port addresses.  
TFTD9  
GPIO9+DCD2#+  
SDTEST2  
IDE_CS0#  
IDE_CS1#  
AF2  
P2  
O
O
IDE Chip Selects 0 and 1. These signals are used to  
select the command block registers in an IDE device.  
TFTD5  
TFTDE  
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Signal Definitions  
32581C  
3.4.9  
IDE Interface Signals (Continued)  
Signal Name  
Ball No.  
Type Description  
Mux  
IDE_IORDY0  
IDE_IORDY1  
AD1  
B29  
I
I
I/O Ready Channels 0 and 1. When de-asserted, these  
signals extend the transfer cycle of any host register  
access if the required device is not ready to respond to  
the data transfer request.  
TFTD11  
GPIO10+DSR2#+  
SDTEST1  
Note: If selected as IDE_IORDY0 or IDE_IORDY1  
function(s) but not used, then signal(s) should be  
tied high.  
IDE_DREQ0  
IDE_DREQ1  
AC4  
C31  
I
I
DMA Request Channels 0 and 1. The IDE_DREQ sig-  
nals are used to request a DMA transfer from the  
SC3200. The direction of transfer is determined by the  
IDE_IOR/IOW signals.  
TFTD8  
GPIO8+CTS2#  
+SDTEST5  
Note: If selected as IDE_DREQ0/ IDE_DREQ1 func-  
tion but not used, tie IDE_DREQ0/IDE_DREQ1  
low.  
IDE_DACK0#  
IDE_DACK1#  
AD4  
C30  
O
O
DMA Acknowledge Channels 0 and 1. The  
IDE_DACK# signals acknowledge the DREQ request to  
initiate DMA transfers.  
TFTD0  
GPIO7+RTS2#  
+SDTEST0  
IRQ14  
IRQ15  
AF1  
AJ8  
I
I
Interrupt Request Channels 0 and 1. These input sig-  
nals are edge-sensitive interrupts that indicate when the  
IDE device is requesting a CPU interrupt service.  
TFTD1  
GPIO11+RI2#  
Note: If selected as IRQ14/IRQ15 function but not  
used, tie IRQ14/IRQ15 low.  
3.4.10 Universal Serial Bus (USB) Interface Signals  
Signal Name  
Ball No.  
Type Description  
Mux  
POWER_EN  
AH1  
O
Power Enable. This signal enables the power to a self-  
---  
powered USB hub.  
OVER_CUR#  
AF4  
I
Overcurrent. This signal indicates that the USB hub has  
---  
detected an overcurrent on the USB.  
1
DPOS_PORT1  
DNEG_PORT1  
DPOS_PORT2  
DNEG_PORT2  
DPOS_PORT3  
DNEG_PORT3  
A28  
A29  
B27  
B28  
A26  
A27  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
---  
---  
---  
---  
---  
---  
USB Port 1 Data Positive for Port 1.  
1
USB Port 1 Data Negative for port 1.  
1
USB Port 2 Data Positive for Port 2.  
1
USB Port 2 Data Negative for Port 2.  
1
USB Port 3 Data Positive for Port 3.  
1
USB Port 3 Data Negative for Port 3.  
1. A 15K ohm pull-down resistor is required on all ports (even if unused).  
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32581C  
Signal Definitions  
Mux  
3.4.11 Serial Ports (UARTs) Interface Signals  
Signal Name  
Ball No.  
Type Description  
SIN1  
SIN2  
SIN3  
AG2  
E28  
AK8  
I
Serial Inputs. Receive composite serial data from the  
communications link (peripheral device, modem or other  
data transfer device).  
---  
SDTEST3  
IRRX1  
Note: If selected as SIN2 or SIN3 function(s) but not  
used, then signal(s) should be tied high.  
SOUT1  
SOUT2  
SOUT3  
RTS2#  
AF3  
D29  
C11  
C30  
O
O
Serial Outputs. Send composite serial data to the com-  
munications link (peripheral device, modem or other data  
transfer device). These signals are set active high after a  
system reset.  
CLKSEL1 (Strap)  
CLKSEL2 (Strap)  
IRTX  
Request to Send. When low, indicates to the modem or  
other data transfer device that the corresponding UART  
is ready to exchange data. A system reset sets these sig-  
nals to inactive high, and loopback operation holds them  
inactive.  
GPIO7+  
IDE_DACK1#  
CTS2#  
C31  
I
Clear to Send. When low, indicates that the modem or  
GPIO8+  
other data transfer device is ready to exchange data.  
IDE_DREQ1  
Note: If selected as CTS2# function but not used, tie  
CTS2# low.  
DTR1#/BOUT1  
DTR2#/BOUT2  
AG1  
D28  
O
Data Terminal Ready Outputs. When low, indicate to  
the modem or other data transfer device that the UART is  
ready to establish a communications link. After a system  
reset, these balls provide the DTR# function and set  
these signals to inactive high. Loopback operation drive  
them inactive.  
GPIO18  
GPIO6+IDE_IOR1#  
Baud Outputs. Provide the associated serial channel  
baud rate generator output signal if test mode is selected  
(i.e., bit 7 of the EXCR1 Register is set).  
RI2#  
AJ8  
I
Ring Indicator. When low, indicates to the modem that a  
telephone ring signal has been received by the modem.  
They are monitored during power-off for wakeup event  
detection.  
GPIO11+IRQ15  
Note: If selected as RI2# function but not used, tie  
RI2# high.  
DCD2#  
DSR2#  
C28  
B29  
I
I
Data Carrier Detected. When low, indicates that the  
data transfer device (e.g., modem) is ready to establish a  
communications link.  
GPIO9+IDE_IOW1#  
+SDTEST2  
Note: If selected as DCD2# function but not used, tie  
DCD2# high.  
Data Set Ready. When low, indicates that the data trans-  
fer device (e.g., modem) is ready to establish a communi-  
cations link.  
GPIO10+  
IDE_IORDY1  
Note: If selected as DSR2# function but not used, tie  
DSR2# low.  
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Signal Definitions  
32581C  
3.4.12 Parallel Port Interface Signals  
Signal Name  
Ball No.  
Type Description  
Mux  
ACK#  
B18  
I
Acknowledge. Pulsed low by the printer to indicate that it  
TFTDE+FPCICLK  
has received data from the Parallel Port.  
AFD#/DSTRB#  
D22  
O
Automatic Feed. When low, instructs the printer to auto-  
matically feed a line after printing each line. This signal is  
in TRI-STATE after a 0 is loaded into the corresponding  
control register bit. An external 4.7 KΩ pull-up resistor  
should be attached to this ball.  
TFTD2+INTR_O  
Data Strobe (EPP). Active low, used in EPP mode to  
denote a data cycle. When the cycle is aborted, DSTRB#  
becomes inactive (high).  
BUSY/WAIT#  
B17  
I
Busy. Set high by the printer when it cannot accept  
TFTD3+F_C/BE1#  
another character.  
Wait. In EPP mode, the Parallel Port device uses this  
active low signal to extend its access cycle.  
ERR#  
INIT#  
D21  
B21  
I
Error. Set active low by the printer when it detects an  
error.  
TFTD4+F_C/BE0#  
TFTD5+SMI_O  
O
Initialize. When low, initializes the printer. This signal is  
in TRI-STATE after a 1 is loaded into the corresponding  
control register bit. Use an external 4.7 KΩ pull-up resis-  
tor.  
PD7  
PD6  
PD5  
PD4  
PD3  
PD2  
PD1  
PD0  
PE  
A18  
A20  
C19  
C18  
C20  
D20  
A21  
C21  
D17  
I/O  
Parallel Port Data. Transfer data to and from the periph-  
eral data bus and the appropriate Parallel Port data regis-  
ter. These signals have a high current drive capability.  
TFTD13+F_AD7  
TFTD1+F_AD6  
TFTD11+F_AD5  
TFTD10+F_AD4  
TFTD9+F_AD3  
TFTD8+F_AD2  
TFTD7+F_AD1  
TFTD6+F_AD0  
TFTD14+F_C/BE2#  
I
Paper End. Set high by the printer when it is out of  
paper.  
This ball has an internal weak pull-up or pull-down resis-  
tor that is programmed by software.  
SLCT  
C17  
B20  
I
Select. Set active high by the printer when the printer is  
selected.  
TFTD15+F_C/BE3#  
SLIN#/ASTRB#  
O
Select Input. When low, selects the printer. This signal  
is in TRI-STATE after a 0 is loaded into the corresponding  
control register bit. Uses an external 4.7 KΩ pull-up resis-  
tor.  
TFTD16+  
F_IRDY#  
Address Strobe (EPP). Active low, used in EPP mode to  
denote an address or data cycle. When the cycle is  
aborted, ASTRB# becomes inactive (high).  
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32581C  
Signal Definitions  
Mux  
3.4.12 Parallel Port Interface Signals (Continued)  
Signal Name  
Ball No.  
Type Description  
STB#/WRITE#  
A22  
O
Data Strobe. When low, indicates to the printer that valid  
TFTD17+  
data is available at the printer port. This signal is in TRI-  
STATE after a 0 is loaded into the corresponding control  
register bit. An external 4.7 KΩ pull-up resistor should be  
employed.  
F_FRAME#  
Write Strobe. Active low, used in EPP mode to denote  
an address or data cycle. When the cycle is aborted,  
WRITE# becomes inactive (high).  
3.4.13 Fast Infrared (IR) Port Interface Signals  
Signal Name  
Ball No.  
Type Description  
Mux  
IRRX1  
AK8  
I
IR Receive. Primary input to receive serial data from the  
SIN3  
IR transceiver. Monitored during power-off for wakeup  
event detection.  
Note: If selected as IRRX1 function but not used, tie  
IRRX1 high.  
IRRX2/GPIO38  
K28  
C11  
I
IR Receive 2. Auxiliary IR receiver input to support a  
second transceiver. This input signal can be used when  
GPIO38 is selected using PMR[14], and when  
AUX_IRRX bit in register IRCR2 of the IR module in  
internal SuperI/O is set.  
LPCPD#  
SOUT3  
IRTX  
O
IR Transmit. IR serial output data.  
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Signal Definitions  
32581C  
3.4.14 AC97 Audio Interface Signals  
Signal Name  
Ball No.  
Type Description  
Mux  
BIT_CLK  
U30  
I
Audio Bit Clock. The serial bit clock from the codec.  
F_TRDY#  
Note: If selected as BIT_CLK function but not used, tie  
BIT_CLK low.  
SDATA_OUT  
SDATA_IN  
P29  
U31  
O
I
Serial Data Output. This output transmits audio serial  
data to the codec.  
TFT_PRSNT (Strap)  
F_GNT0#  
Serial Data Input. This input receives serial data from  
the primary codec.  
Note: If selected as SDATA_IN function but not used,  
tie SDATA_IN low.  
SDATA_IN2  
SYNC  
AL8  
P30  
I
Serial Data Input 2. This input receives serial data from  
the secondary codec. This signal has wakeup capability.  
---  
O
Serial Bus Synchronization. This bit is asserted to syn-  
chronize the transfer of data between the SC3200 and  
the AC97 codec.  
CLKSEL3 (Strap)  
AC97_CLK  
P31  
U29  
O
O
Codec Clock. It is twice the frequency of the Audio Bit  
Clock.  
---  
AC97_RST#  
Codec Reset. S3 to S5 wakeup is not supported  
F_STOP#  
because AC97_RST# is powered by V . If wakeup from  
IO  
states S3 to S5 are needed, a circuit in the system board  
should be used to reset the AC97 codec.  
PC_BEEP  
V31  
O
PC Beep. Legacy PC/AT speaker output.  
GPIO16+  
F_DEVSEL#  
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32581C  
Signal Definitions  
3.4.15 Power Management Interface Signals  
Signal Name  
Ball No.  
Type Description  
Mux  
CLK32  
AH8  
AH6  
AK5  
AJ6  
AL4  
O
32.768 KHz Output Clock  
---  
---  
---  
---  
---  
GPWIO0  
GPWIO1  
GPWIO2  
LED#  
I/O  
General Purpose Wakeup I/Os. These signals each  
have an internal pull-up of 100 KΩ.  
O
O
I
LED Control. Drives an externally connected LED (on,  
off or a 1 Hz blink). Sleeping / Working indicator. This sig-  
nal is an open-drain output.  
ONCTL#  
AJ5  
On / Off Control. This signal indicates to the main power  
supply that power should be turned on. This signal is an  
open-drain output.  
---  
---  
PWRBTN#  
AH5  
Power Button. Input used by the power management  
logic to monitor external system events, most typically a  
system on/off button or switch.  
The signal has an internal pull-up of 100 KΩ, a Schmitt-  
trigger input buffer and debounce protection of at least 16  
ms.  
ACPI is non-functional and all ACPI outputs are unde-  
fined when the power-up sequence does not include  
using the power button. SUSP# is an internal signal gen-  
erated from the ACPI block. Without an ACPI reset,  
SUSP# can be permanently asserted. If the USE_SUSP  
bit in CCR2 of GX1 module is enabled (Index C2h[7] = 1),  
the CPU will stop.  
If ACPI functionality is desired, or the situation described  
above avoided, the power button must be toggled. This  
can be done externally or internally. GPIO63 is internally  
connected to PWRBTN#. To toggle the power button with  
software, GPIO63 must be programmed as an output  
using the normal GPIO programming protocol (see Sec-  
tion 6.4.1.1 "GPIO Support Registers" on page 222).  
GPIO63 must be pulsed low for at least 16 ms and not  
more than 4 sec.  
Asserting POR# has no effect on ACPI. If POR# is  
asserted and ACPI was active prior to POR#, then ACPI  
will remain active after POR#. Therefore, BIOS must  
ensure that ACPI is inactive before GPIO63 is pulsed  
low.  
PWRCNT1  
PWRCNT2  
AK6  
AL7  
O
O
Suspend Power Plane Control 1 and 2. Control signal  
asserted during power management Suspend states.  
These signals are open-drain outputs.  
---  
---  
THRM#  
AK4  
I
Thermal Event. Active low signal generated by external  
hardware indicating that the system temperature is too  
high.  
---  
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Signal Definitions  
32581C  
3.4.16 GPIO Interface Signals  
Signal Name  
Ball No.  
Type Description  
Mux  
GPIO0  
GPIO1  
D11  
D10  
N30  
D28  
I/O  
GPIO Port 0. Each signal is configured independently as  
an input or I/O, with or without static pull-up, and with  
either open-drain or totem-pole output type.  
TRDE#  
IOCS1#+TFTD12  
AB1D+IOCS1#  
A debouncer and an interrupt can be enabled or masked  
for each of signals GPIO[00:01] and [06:15] indepen-  
dently.  
GPIO6  
DTR2#/BOUT2+  
IDE_IOR1#+  
SDTEST5  
Note: GPIO12, GPIO13, GPIO16 inputs: If GPIOx func-  
tion is selected but not used, tie GPIOx low.  
GPIO7  
GPIO8  
GPIO9  
GPIO10  
C30  
C31  
C28  
B29  
RTS2#+IDE_DACK1#  
+SDTEST0  
CTS2#+IDE_DREQ1  
+SDTEST4  
DCD2#+IDE_IOW1#+  
SDTEST2  
DSR2#+IDE_IORDY1  
+SDTEST1  
GPIO11  
GPIO12  
GPIO13  
GPIO14  
GPIO15  
GPIO16  
AJ8  
N29  
M29  
D9  
RI2#+IRQ15  
AB2C  
AB2D  
IOR#+DOCR#  
IOW#+DOCW#  
A8  
V31  
PC_BEEP+  
F_DEVSEL#  
GPIO17  
GPIO18  
GPIO19  
GPIO20  
A10  
AG1  
C9  
IOCS0#+TFTDCK  
DTR1#/BOUT1  
INTC#+IOCHRDY  
DOCCS#+TFTD0  
AB1C+DOCCS#  
LAD0  
A9  
N31  
M28  
L31  
L30  
L29  
L28  
K31  
K28  
J31  
Y3  
GPIO32  
GPIO33  
GPIO34  
GPIO35  
GPIO36  
GPIO37  
GPIO38/IRRX2  
GPIO39  
GPIO40  
GPIO41  
I/O  
GPIO Port 1. Each signal is configured independently as  
an input or I/O, with or without static pull-up, and with  
either open-drain or totem-pole output type.  
LAD1  
LAD2  
A debouncer and an interrupt can be enabled or masked  
for each of signals GPIO[32:41] independently.  
LAD3  
LDRQ#  
LFRAME#  
LPCPD#  
SERIRQ  
IDE_DATA8  
IDE_DATA11  
W4  
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32581C  
Signal Definitions  
3.4.17 Debug Monitoring Interface Signals  
Signal Name  
Ball No.  
Type Description  
Mux  
FPCICLK  
F_AD7  
B18  
A18  
A20  
C19  
C18  
C20  
D20  
A21  
C21  
C17  
D17  
B17  
O
O
O
O
O
O
O
O
O
O
O
O
Fast-PCI Bus Monitoring Signals. When enabled, this  
ACK#+TFTDE  
PD7+TFTD13  
PD6+TFTD1  
PD5+TFTD11  
PD4+TFTD10  
PD3+TFTD9  
PD2+TFTD8  
PD1+TFTD7  
PD0+TFTD6  
SLCT+TFTD15  
PE+TFTD14  
group of signals provides for monitoring of the internal  
Fast-PCI bus for debug purposes. To enable, pull up  
FPCI_MON (ball A4).  
F_AD6  
F_AD5  
F_AD4  
F_AD3  
F_AD2  
F_AD1  
F_AD0  
F_C/BE3#  
F_C/BE2#  
F_C/BE1#  
BUSY/WAIT#+  
TFTD3  
F_C/BE0#  
D21  
A22  
O
O
ERR#+TFTD4+  
F_FRAME#  
STB#/WRITE#+  
TFTD17  
F_IRDY#  
B20  
O
SLIN#/ASTRB#+  
TFTD16  
F_STOP#  
U29  
V31  
O
O
AC97_RST#  
F_DEVSEL#  
GPIO16+  
PC_BEEP  
F_GNT0#  
F_TRDY#  
INTR_O  
U31  
U30  
D22  
O
O
O
SDATA_IN  
BIT_CLK  
CPU Core Interrupt. When enabled, this signal provides  
for monitoring of the internal GX1 core INTR signal for  
debug purposes. To enable, pull up FPCI_MON (ball A4).  
AFD#/DSTRB#+  
TFTD2  
SMI_O  
B21  
O
System Management Interrupt. This is the input to the  
GX1 core. When enabled, this signal provides for moni-  
toring of the internal GX1 core SMI# signal for debug pur-  
poses. To enable, pull up FPCI_MON (ball A4).  
INIT#+TFTD5+  
3.4.18 JTAG Interface Signals  
Signal Name  
Ball No.  
Type Description  
Mux  
TCK  
E31  
I
JTAG Test Clock. This signal has an internal weak pull-  
---  
up resistor.  
TDI  
F29  
I
JTAG Test Data Input. This signal has an internal weak  
---  
pull-up resistor.  
TDO  
TMS  
E30  
F28  
O
I
JTAG Test Data Output  
---  
---  
JTAG Test Mode Select. This signal has an internal  
weak pull-up resistor.  
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Signal Definitions  
32581C  
3.4.18 JTAG Interface Signals (Continued)  
Signal Name  
Ball No.  
Type Description  
Mux  
TRST#  
E29  
I
JTAG Test Reset. This signal has an internal weak pull-  
---  
up resistor.  
For normal JTAG operation, this signal should be active  
at power-up.  
If the JTAG interface is not being used, this signal can be  
tied low.  
3.4.19 Test and Measurement Interface Signals  
Signal Name  
Ball No.  
Type  
Description  
Mux  
GXCLK  
V30  
O
GX Clock. This signal is for internal testing only. For nor-  
mal operation either program as FP_VDD_ON or leave  
unconnected.  
FP_VDD_ON+  
TEST3  
TEST3  
V30  
O
Internal Test Signal. This signal is used for internal test-  
ing only. For normal operation leave unconnected, unless  
programmed as FP_VDD_ON.  
FP_VDD_ON+  
GXCLK  
TEST2  
TEST1  
TEST0  
GTEST  
AJ1  
AG4  
AH3  
F30  
O
O
O
I
Internal Test Signals. These signals are used for internal  
testing only. For normal operation, leave unconnected  
unless programmed as one of their muxed options.  
PLL5B  
PLL6B  
PLL2B  
---  
Global Test. This signal is used for internal testing only.  
For normal operation this signal should be pulled down  
with 1.5 KΩ.  
PLL6B  
AG4  
AJ1  
AH3  
D28  
I/O  
I/O  
I/O  
O
PLL6, PLL5 and PLL2 Bypass. These signals are used  
for internal testing only. For normal operation leave  
unconnected.  
TEST1  
TEST2  
TEST0  
PLL5B  
PLL2B  
SDTEST5  
Memory Internal Test Signals. These signals are used  
for internal testing only. For normal operation, these sig-  
nals should be programmed as one of their muxed  
options.  
GPIO6+  
DTR2#/BOUT2+  
IDE_IOR1#  
SDTEST4  
C31  
O
GPIO8+CTS2#+  
IDE_DREQ1  
SDTEST3  
SDTEST2  
E28  
C28  
O
O
SIN2  
GPIO9+DCD2#+  
IDE_IOW1#  
SDTEST1  
SDTEST0  
B29  
C30  
O
O
GPIO10+DSR2#  
+IDE_IORDY1  
GPIO7+RTS2#+  
IDE_DACK1#  
TDP  
TDN  
D30  
D31  
I/O  
I/O  
Thermal Diode Positive / Negative. These signals are  
for internal testing only. For normal operation leave  
unconnected.  
---  
---  
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32581C  
Signal Definitions  
1
3.4.20 Power, Ground and No Connections  
Signal Name  
Ball No.  
C16  
Type Description  
AV  
AV  
GND Analog PLL2 Ground Connection.  
GND Analog PLL3 Ground Connection.  
SSPLL2  
SSPLL3  
AK3  
V
A17  
PWR 3.3V PLL2 Analog Power Connection. Low noise power for PLL2 and  
PLL2  
PLL5.  
V
AJ4  
PWR 3.3V PLL3 Analog Power Connection. Low noise power for PLL3,  
PLL3  
PLL4, and PLL6.  
AV  
AV  
D27  
C27  
AL3  
PWR 3.3V Analog USB Power Connection. Low noise power.  
GND Analog USB Ground Connection.  
CCUSB  
SSUSB  
V
PWR Battery. Provides battery back-up to the RTC and ACPI registers, when  
BAT  
V
is lower than the minimum value (see Table 9-3 on page 352). The  
SB  
ball is connected to the internal logic through a series resistor for UL pro-  
tection. If battery backup is not desired, connect V to V  
.
SS  
BAT  
V
V
AL5  
AL6  
PWR 3.3V Standby Power Supply. Provides power to the Real-Time Clock  
SB  
(RTC) and ACPI circuitry while the main power supply is turned off.  
PWR 1.8V Standby Power Supply. Provides power to the internal logic while  
the main power supply is turned off. This signal requires a 0.1 μF bypass  
SBL  
capacitor to V . This supply must be present when V is present.  
SS  
SB  
V
V
V
See Table 3-3  
on page 40.  
(Total of 29)  
PWR 1.8V Core Processor Power Connections.  
CORE  
IO  
See Table 3-3  
on page 40.  
(Total of 46)  
PWR 3.3V I/O Power Connections.  
GND Ground Connections.  
See Table 3-3  
on page 40.  
(Total of 96)  
SS  
NC  
See Table 3-3  
on page 40.  
(Total of 13)  
---  
No Connections. These lines should be left disconnected. Connecting a  
pull-up/-down resistor or to an active signal could cause unexpected  
results and possible malfunctions.  
1. All power sources except V  
must be connected, even if the function is not used.  
BAT  
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General Configuration Block  
32581C  
4.0General Configuration Block  
4
The General Configuration block includes registers for:  
• Pin Multiplexing and Miscellaneous Configuration  
• WATCHDOG Timer  
not have a register block in PCI configuration space (i.e.,  
they do not appear to software as PCI registers).  
After system reset, the Base Address register is located at  
I/O address 02EAh. This address can be used only once.  
Before accessing any PCI registers, the BOOT code must  
program this 16-bit register to the I/O base address for the  
General Configuration block registers. All subsequent  
writes to this address, are ignored until system reset.  
• High-Resolution Timer  
• Clock Generators  
A selectable interrupt is shared by all these functions.  
Note: Location of the General Configuration Block can-  
not be determined by software. See the  
AMD Geode™ SC3200 Specification Update doc-  
ument.  
4.1  
Configuration Block Addresses  
Registers of the General Configuration block are I/O  
mapped in a 64-byte address range. These registers are  
physically connected to the internal Fast-PCI bus, but do  
Reserved bits in the General Configuration block should  
read as written unless otherwise specified.  
Table 4-1. General Configuration Block Register Summary  
Offset  
Width (Bits)  
Type  
R/W  
Name  
WDTO. WATCHDOG Timeout  
Reset Value  
Reference  
00h-01h  
02h-03h  
04h  
16  
16  
8
0000h  
Page 78  
Page 78  
Page 79  
---  
R/W  
R/WC  
---  
WDCNFG. WATCHDOG Configuration  
WDSTS. WATCHDOG Status  
RSVD. Reserved  
0000h  
00h  
05h-07h  
08h-0Bh  
0Ch  
---  
32  
8
---  
RO  
R/W  
R/W  
---  
TMVALUE. TIMER Value  
TMSTS. TIMER Status  
xxxxxxxxh  
Page 80  
Page 80  
Page 80  
---  
00h  
0Dh  
8
TMCNFG. TIMER Configuration  
RSVD. Reserved  
00h  
0Eh-0Fh  
10h  
---  
8
---  
RO  
---  
MCCM. Maximum Core Clock Multiplier  
RSVD. Reserved  
Strapped Value  
Page 85  
---  
11h  
---  
8
---  
12h  
R/W  
---  
PPCR. PLL Power Control  
RSVD. Reserved  
2Fh  
Page 85  
---  
13h-17h  
18h-1Bh  
1Ch-1Dh  
1Eh-1Fh  
20h-2Fh  
30h-33h  
34h-37h  
38h  
---  
32  
---  
16  
---  
32  
32  
8
---  
R/W  
---  
PLL3C. PLL3 Configuration  
RSVD. Reserved  
E1040005h  
Page 85  
---  
---  
Strapped Value  
---  
R/W  
---  
CCFC. Core Clock Frequency Control  
RSVD. Reserved  
Page 86  
---  
R/W  
R/W  
R/W  
---  
PMR. Pin Multiplexing Register  
MCR. Miscellaneous Configuration Register  
INTSEL. Interrupt Selection  
RSVD. Reserved  
00000000h  
00000001h  
00h  
Page 70  
Page 74  
Page 76  
---  
39h-3Bh  
3Ch  
---  
8
---  
RO  
RO  
RO  
ID. Device ID  
xxh  
Page 76  
Page 76  
Page 76  
3Dh  
8
REV. Revision  
xxh  
3Eh-3Fh  
16  
CBA. Configuration Base Address  
xxxxh  
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32581C  
General Configuration Block  
4.2  
Multiplexing, Interrupt Selection, and Base Address Registers  
The registers described inTable 4-2 are used to determine  
general configuration for the SC3200. These registers also  
indicate which multiplexed signals are issued via balls from  
which more than one signal may be output. For more infor-  
mation about multiplexed signals and the appropriate con-  
figurations, see Section 3.1 "Ball Assignments" on page 27.  
Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers  
Bit  
Description  
Offset 30h-33h  
Pin Multiplexing Register - PMR (R/W)  
Reset Value: 00000000h  
This register configures pins with multiple functions. See Section 3.1 on page 27 for more information about multiplexing information.  
31:30  
29  
Reserved: Always write 0.  
Test Signals. Selects ball functions.  
Ball #  
0: Internal Test Signals  
1: Internal Test Signals  
Name  
Add’l Dependencies  
Name  
Add’l Dependencies  
D28 / AH3  
C28 / AG4  
B29 / AJ1  
AL16 / V30  
PLL2B  
PLL6B  
PLL5B  
GXCLK  
None  
TEST0  
TEST1  
TEST2  
TEST3  
None  
None  
None  
None  
None  
See PMR[23]  
PMR[23] = 0  
28  
27  
Test Signals. Selects ball function.  
Ball #  
0: AC97 Signal  
Name  
1: Internal Test Signal  
Add’l Dependencies  
Name  
Add’l Dependencies  
AJ4 / E28  
SIN2  
None  
SDTEST3  
See Note.  
Note: If this bit is set, PMR[8] and PMR[18] must be set by software.  
FPCI_MON (Fast-PCI Monitoring). Selects Fast-PCI monitoring output signals instead of Parallel Port signals.  
Fast-PCI monitoring output signals can be enabled in two ways: by setting this bit to 1 or by strapping FPCI_MON (ball A4)  
high. (The strapped value can be read back at MCR[30].) Listed below is how these two options work together and the sig-  
nals that are enabled (enabling overrides add’l dependencies except FPCI_MON = 1). Note that the FPCI monitoring signals  
that are muxed with Audio signals are not enabled via this bit. They are only enabled using the strap option.  
PMR[27] FPCI_MON  
0
0
1
1
0
1
0
1
Disable all Fast-PCI monitoring signals  
Enable all Fast-PCI monitoring signals  
Enable Fast-PCI monitoring signals muxed with Parallel Port signals only  
Enable all Fast-PCI monitoring signals  
Ball #  
FPCI_MON  
Other Signal  
Add’l Dependencies  
U3 / B18  
U1 / A18  
V3 / A20  
V2 / C19  
V1 / C18  
W2 / C20  
W3 / D20  
Y1 / A21  
AA1 / C21  
T4 / C17  
T3 / D17  
T1 / B17  
AA3 / D21  
AB1 / A22  
W1 / B20  
AB2 / D22  
Y3 / B21  
FPCICLK  
F_AD7  
F_AD6  
F_AD5  
F_AD4  
F_AD3  
F_AD2  
F_AD1  
F_AD0  
F_C/BE3#  
F_C/BE2#  
F_C/BE1#  
F_C/BE0#  
F_FRAME#  
F_IRDY#  
INTR_O  
SMI_O  
ACK#+TFTDE  
PD7+TFTD13  
PD6+TFTD1  
PD5+TFT11  
PD4+TFTD10  
PD3+TFTD9  
PD2+TFTD8  
PD1+TFTD7  
PD0_TFTD5  
See PMR[23]  
See PMR[23]  
See PMR[23]  
See PMR[23]  
See PMR[23]  
See PMR[23]  
See PMR[23]  
See PMR[23]  
See PMR[23]  
See PMR[23]  
See PMR[23]  
See PMR[23]  
See PMR[23]  
See PMR[23]  
See PMR[23]  
See PMR[23]  
See PMR[23]  
SLCT+TFTD15  
PE+TFTD14  
BUSY/WAIT#+TFTD3  
ERR#+TFTD4  
STB#/WRITE#+TFTD7  
SLIN#/ASTRB#+TFTD16  
AFD#/DSTRB#+TFTD2  
INIT#+TFTD5  
AL15 / V31  
AJ15 / U29  
AK14 / U31  
AL14 / U30  
F_DEVSEL#  
F_STOP#  
F_GNT0#  
F_TRDY#  
GPIO16+PC_BEEP  
AC97_RST#  
SDATA_IN  
FPCI_MON = 1 and see PMR[0]  
FPCI_MON = 1  
FPCI_MON = 1  
BIT_CLK  
FPCI_MON = 1  
26  
Reserved. Always write 0.  
70  
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General Configuration Block  
32581C  
Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)  
Bit  
Description  
25  
AC97CKEN (Enable AC97_CLK Output). This bit enables the output drive of AC97_CLK (ball P31).  
0: AC97_CLK output is HiZ.  
1: AC97_CLK output is enabled.  
24  
TFTIDE (TFT/IDE). Determines whether certain balls are used for TFT signals or for IDE signals. Note that there are no  
additional dependencies.  
Ball #  
0: IDE Signals  
Name  
1: GPIO and TFT Signals  
Name  
A26 / AD3  
C26 / AE1  
C17 / U2  
B24 / AC3  
A24 / AC1  
D23 / AC2  
C23 / AB4  
B23 / AB1  
A23 / AA4  
C22 / AA3  
B22 / AA2  
A21 / Y3  
C20 / Y2  
A20 / Y1  
C19 / W4  
B19 / W3  
A19 / V3  
IDE_ADDR0  
IDE_ADDR1  
IDE_ADDR2  
IDE_DATA0  
IDE_DATA1  
IDE_DATA2  
IDE_DATA3  
IDE_DATA4  
IDE_DATA5  
IDE_DATA6  
IDE_DATA7  
IDE_DATA8  
IDE_DATA9  
IDE_DATA10  
IDE_DATA11  
IDE_DATA12  
IDE_DATA13  
IDE_DATA14  
IDE_DATA15  
IDE_CS0#  
TFTD3  
TFTD2  
TFTD4  
TFTD6  
TFTD16  
TFTD14  
TFTD12  
FP_VDD_ON  
CLK27M  
IRQ9  
INTD#  
GPIO40  
DDC_SDA  
DDC_SCL  
GPIO41  
TFTD13  
TFTD15  
TFTD17  
TFTD7  
C18 / V2  
B18 / V1  
A27 / AF2  
C16 / P2  
TFTD5  
TFTDE  
IDE_CS1#  
C21 / Y4  
IDE_IOR0#  
IDE_IOW0#  
IDE_DREQ0  
IDE_DACK0#  
IDE_RST#  
IDE_IORDY0  
IRQ14  
TFTD10  
TFTD9  
TFTD8  
D24 / AD2  
C24 / AC4  
C25 / AD4  
A22 / AA1  
A25 / AD1  
D25 / AF1  
TFTD0  
TFTDCK  
TFTD11  
TFTD1  
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71  
32581C  
General Configuration Block  
Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)  
Bit  
Description  
23  
TFTPP (TFT/Parallel Port). Determines whether certain balls are used for TFT or PP/ACB1/FPCI. This bit is set to 1 at  
power-on if the TFT_PRSNT strap (ball P29) is pulled high.  
Ball #  
0: PP/ACB1/FPCI  
Name  
1: TFT  
Name  
Add’l Dependencies  
Add’l Dependencies  
H2 / D10  
H3 / A9  
GPIO1  
IOCS1#  
PMR[13] = 0  
PMR[13] = 1  
TFTD12  
TFTD0  
TFTDCK  
TFTD3  
TFTD14  
TFTD15  
TFTD13  
TFTDE  
TFTD10  
TFTD11  
TFTD1  
TFTD16  
TFTD9  
TFTD8  
TFTD7  
TFTD5  
TFTD6  
TFTD4  
TFTD17  
TFTD2  
None  
GPIO20  
DOCCS#  
PMR[7] = 0  
PMR[7] = 1  
None  
J4 / A10  
GPIO17  
IOCS0#  
PMR[5] = 0  
PMR[5] = 1  
None  
T1 / B17  
T3 / D17  
T4 / C17  
U1 / A18  
U3 / B18  
V1 / C18  
V2 / C19  
V3 / A20  
W1 / B20  
W2 / C20  
W3 / D20  
Y1 / A21  
Y3 / B21  
AA1 / C21  
AA3 / D21  
AB1 / A22  
AB2 / D22  
AJ13 / N31  
AL12 / N30  
AL16 / V30  
BUSY/WAIT#  
F_C/BE1#  
Note 1  
Note 2  
None  
PE  
F_C/BE2#  
Note 1  
Note 2  
Note 1  
Note 1  
Note 1  
Note 1  
Note 1  
Note 1  
Note 1  
Note 1  
Note 1  
Note 1  
Note 1  
Note 1  
Note 1  
Note 1  
None  
SLCT  
F_C/BE3#  
Note 1  
Note 2  
PD7  
F_AD7  
Note 1  
Note 2  
ACK#  
FPCICLK  
Note 1  
Note 2  
PD4  
F_AD4  
Note 1  
Note 2  
PD5  
F_AD5  
Note 1  
Note 2  
PD6  
F_AD6  
Note 1  
Note 2  
SLIN#/ASTRB#  
F_IRDY#  
Note 1  
Note 2  
PD3  
F_AD3  
Note 1  
Note 2  
PD2  
F_AD2  
Note 1  
Note 2  
PD1  
F_AD1  
Note 1  
Note 2  
INIT#  
SMI_O  
Note 1  
Note 2  
PD0  
F_AD0  
Note 1  
Note 2  
ERR#  
F_C/BE0#  
Note 1  
Note 2  
STB#/WRITE#  
F_FRAME#  
Note 1  
Note 2  
AFD#/DSTRB#  
INTR_O  
Note 1  
Note 2  
Note 1  
AB1C  
None  
GPIO20  
DOCCS#  
PMR[7] = 0  
PMR[7] = 1  
AB1D  
None  
GPIO1  
IOCS1#  
PMR[13] = 0  
PMR[13] = 1  
GXCLK  
TEST3  
PMR[29] = 0  
PMR[29] = 1  
FP_VDD_ON  
None  
Note: 1. PMR[27] = 0 and FPCI_MON = 0  
2. PMR[27] = 1 or FPCI_MON = 1  
3. ACCESS.bus interface 1 is not available if PMR[23] = 1.  
4. If FPCI_MON strap is enabled, the TFT_PRSNT strap should pulled low.  
22  
RSVD (Reserved). Must be set equal to PMR[14] (LPCSEL). The LPC_ROM strap (ball D6) determines the power-on reset  
(POR) state of PMR[14] and PMR[22].  
72  
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General Configuration Block  
32581C  
Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)  
Bit  
Description  
21  
IOCSEL (Select I/O Commands). Selects ball functions.  
Ball #  
0: I/O Command Signals  
1: GPIO Signals  
Name  
Name  
Add’l Dependencies  
Add’l Dependencies  
F1 / D9  
G3 / A8  
IOR#  
DOCR#  
PMR[2] = 0  
PMR[2] = 1  
GPIO14  
Undefined  
PMR[2] = 1  
PMR[2] = 0  
IOW#  
DOCW#  
PMR[2] = 0  
PMR[2] = 1  
GPIO15  
Undefined  
PMR[2] = 1  
PMR[2] = 0  
20  
19  
Reserved. Must be set to 0.  
AB2SEL (Select ACCESS.bus 2). Selects ball functions.  
Ball #  
0: GPIO Signals  
Name  
1: ACCESS.bus 2 Signals  
Add’l Dependencies  
Name  
AB2C  
AB2D  
Add’l Dependencies  
AJ12 / N29  
AL11 / M29  
GPIO12  
GPIO13  
None  
None  
None  
None  
18  
SP2SEL (Select SP2 Additional Pins). Selects ball functions.  
Ball #  
0: GPIO, IDE Signals  
1: Serial Port Signals  
Name  
Add’l Dependencies  
Name  
Add’l Dependencies  
AH3 / D28  
AG4 / C28  
AJ1 / B29  
H30 / AJ8  
GPIO6  
IDE_IOR1#  
PMR[8] = 0  
PMR[8] = 1  
DTR2#/BOUT2  
SDTEST5  
PMR[8] = 0  
PMR[8] = 1  
GPIO9  
IDE_IOW1#  
PMR[8] = 0  
PMR[8] = 1  
DCD2#  
SDTEST2  
PMR[8] = 0  
PMR[8] = 1  
GPIO10  
IDE_IORDY1  
PMR[8] = 0  
PMR[8] = 1  
DSR2#  
SDTEST1  
PMR[8] = 0  
PMR[8] = 1  
GPIO11  
IRQ15  
PMR[8] = 0  
PMR[8] = 1  
RI2#  
Undefined  
PMR[8] = 0  
PMR[8] = 1  
17  
16  
SP2CRSEL (Select SP2 Flow Control). Selects ball functions.  
Ball #  
0: GPIO, IDE Signals  
1: Serial Port Signals  
Name  
Add’l Dependencies  
Name  
Add’l Dependencies  
AH4 / C30  
AJ2 / C31  
GPIO7  
IDE_DACK1#  
PMR[8] = 0  
PMR[8] = 1  
RTS2#  
SDTEST0  
PMR[8] = 0  
PMR[8] = 1  
GPIO8  
IDE_DREQ1  
PMR[8] = 0  
PMR[8] = 1  
CTS2#  
SDTEST4  
PMR[8] = 0  
PMR[8] = 1  
SP1SEL (Select SP1 Additional Pin). Selects ball function.  
Ball #  
0: GPIO Signal  
Name  
1: Serial Port Signal  
Name  
Add’l Dependencies  
Add’l Dependencies  
A28 / AG1  
GPIO18  
None  
DTR1#/BOUT1  
None  
15  
14  
RSVD (Reserved). Write to 0.  
LPCSEL (Select LPC Bus). Selects ball functions. The LPC_ROM strap (ball D6) determines the power-on reset (POR)  
state of PMR[14] and PMR[22].  
Ball #  
0: GPIO Signals  
Name  
1: LPC Signals  
Name  
Add’l Dependencies  
PMR[22] = 0  
PMR[22] = 0  
PMR[22] = 0  
PMR[22] = 0  
PMR[22] = 0  
PMR[22] = 0  
PMR[22] = 0  
PMR[22] = 0  
Add’l Dependencies  
PMR[22] = 1  
PMR[22] = 1  
PMR[22] = 1  
PMR[22] = 1  
PMR[22] = 1  
PMR[22] = 1  
PMR[22] = 1  
PMR[22] = 1  
AJ11 / M28  
AL10 / L31  
AK10 / L30  
AJ10 / L29  
AL9 / L28  
AK9 / K31  
AJ9 / K28  
AL8 / J31  
GPIO32  
LAD0  
GPIO33  
LAD1  
GPIO34  
LAD2  
GPIO35  
LAD3  
GPIO36  
LDRQ#  
LFRAME#  
LPCPD#  
SERIRQ  
GPIO37  
GPIO38/IRRX2  
GPIO39  
13  
IOCS1SEL (Select IOCS1). Selects ball functions for IOCS1# or GPIO1. Works in conjunction with PMR[23], see PMR[23]  
for definition.  
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73  
32581C  
General Configuration Block  
Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)  
Bit  
Description  
12  
TRDESEL (Select TRDE#). Selects ball function.  
Ball #  
0: Sub-ISA Signal  
Name  
1: GPIO Signal  
Name  
Add’l Dependencies  
Add’l Dependencies  
H1 / D11  
TRDE#  
None  
GPIO0  
None  
11  
10  
EIDE (Enable IDE Outputs). This bit enables IDE output signals.  
0: IDE signals are HiZ. Other signals multiplexed on the same balls are HiZ until this bit is set. (without regard to bit 24 of  
this register). This bit does not control IDE channel 1 control signals selected by bit 8 of this register.  
1:  
Signals are enabled.  
ETFT (Enable TFT Outputs). This bit enables TFT output signals, that are multiplexed with the Parallel Port and controlled  
by PMR[23].  
0: Signals TFTD[17:0], TFTDE and TFTDCK are set to 0.  
1: Signals TFTD[17:0], TFTDE and TFTDCK are enabled.  
Note: TFTDCK that is multiplexed on IDE_RST# (ball AA1) is also enabled by this bit.  
IOCHRDY (Select IOCHRDY). Selects ball function.  
9
Ball #  
0: PCI, GPIO Signal  
Name  
1: Sub-ISA Signal  
Name  
Add’l Dependencies  
Add’l Dependencies  
H4 / C9  
GPIO19  
INTC#  
PMR[4] = 0  
PMR[4] = 1  
IOCHRDY  
Undefined  
PMR[4] = 1  
PMR[4] = 0  
8
7
6
IDE1SEL (Select IDE Channel 1). Selects IDE Channel 1 or GPIO ball functions. Works in conjunction with PMR[18] and  
PMR[17], see PMR[18] and PMR[17] for definitions.  
DOCCSSEL (Select DOCCS#). Selects DOCCS# or GPIO20 ball functions. Works in conjunction with PMR[23], see  
PMR[23] for definition.  
SP3SEL (Select UART3). Selects ball functions.  
Ball #  
0: IR Signals  
Name  
1: Serial Port Signals  
Add’l Dependencies  
Name  
Add’l Dependencies  
J28 / AK8  
J3 / C11  
IRRX1  
IRTX  
None  
None  
SIN3  
None  
None  
SOUT3  
5
4
3
2
IOCS0SEL (Select IOCS0#). Selects ball function. Works in conjunction with PMR[23], see PMR[23] for definition.  
INTCSEL (Select INTC#). Selects ball function. Works in conjunction with PMR[9], see PMR[9] for definition.  
Reserved. Write as read.  
DOCWRSEL (Select DiskOnChip and NAND Flash Command Lines). Selects ball functions. Works in conjunction with  
PMR[21], see PMR[21] for definition.  
1
0
Reserved. Write as read.  
PCBEEPSEL (Select PC_BEEP). Selects ball function.  
Ball #  
0: GPIO Signal  
Name  
1: Audio Signal  
Name  
Add’l Dependencies  
Add’l Dependencies  
AL15 / V31  
GPIO16  
F_DEVSEL#  
FPCI_MON = 0  
FPCI_MON = 1  
PC_BEEP  
F_DEVSEL#  
FPCI_MON] = 0  
FPCI_MON = 1  
Offset 34h-37h  
Miscellaneous Configuration Register - MCR (R/W)  
Reset Value: 0000001h  
Power-on reset value: The BOOT16 strap pin selects "Enable 16-Bit Wide Boot Memory".  
31  
30  
DID0 (Ball C5) Strap Status. (Read Only) Represents the value of the strap that is latched after power-on reset. Read in  
conjunction with bit 29.  
FPCI_MON (Ball A4) Strap Status. (Read Only) Represents the value of the strap that is latched after power-on reset.  
Indicates if Fast-PCI monitoring output signals (instead of Parallel Port and some audio signals) are enabled. The state of  
this bit along with PMR[27] control the Fast-PCI monitoring function. See PMR[27] definition.  
29  
DID1 (Ball C6) Strap Status. (Read Only) Represents the value of the strap that is latched after power-on reset. Read in  
conjunction with bit 31.  
28:20  
19:18  
17  
Reserved.  
Reserved. Write as 0.  
HSYNC Timing. HSYNC timing control for TFT.  
0: Reserved.  
1: HSYNC timing suited for TFT.  
74  
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General Configuration Block  
32581C  
Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)  
Bit  
Description  
16  
Delay HSYNC. HSYNC delay by two TFT clock cycles.  
0: There is no delay on HSYNC.  
1: HYSNC is delayed twice by rising edge of TFT clock. Enables delay between VSYNC and HSYNC suited for TFT dis-  
play.  
15  
14  
Reserved. Write as read.  
IBUS16 (Invert BUS16). This bit inverts the meaning of MCR[3] (bit 3 of this register).  
0: BUS16 is as described for MCR[3].  
1: BUS16 meaning is inverted: if MCR[3] = 0, ROMCS# access is 16 bits wide; if MCR[3] = 1, ROMCS# access is 8 bits  
wide.  
13  
12  
Reserved. Must be set to 0.  
IO1ZWS (Enable ZWS# for IOCS1# Access). This bit enables internal activation of ZWS# (Zero Wait States) control for  
IOCS1# access.  
0: ZWS# is not active for IOCS1# access.  
1: ZWS# is active for IOCS1# access.  
11  
10  
9
IO0ZWS (Enable ZWS# for IOCS0# Access). This bit enables internal activation of ZWS# (Zero Wait States) control for  
IOCS0# access.  
0: ZWS# is not active for IOCS0# access.  
1: ZWS# is active for IOCS0# access.  
DOCZWS (Enable ZWS# for DOCCS# Access). This bit enables internal activation of ZWS# (Zero Wait States) control for  
DOCCS# access.  
0: ZWS# is not active for DOCCS# access.  
1: ZWS# is active for DOCCS# access.  
ROMZWS (Enable ZWS# for ROMCS# Access). This bit enables internal activation of ZWS# (Zero Wait States) control for  
ROMCS# access.  
0: ZWS# is not active for ROMCS# access.  
1: ZWS# is active for ROMCS# access.  
8
7
6
IO1_16 (Enable 16-Bit Wide IOCS1# Access). This bit enables the16-line access to IOCS1# in the Sub-ISA interface.  
0: 8-bit wide IOCS1# access is used.  
1: 16-bit wide IOCS1# access is used.  
IO0_16 (Enable 16-Bit Wide IOCS0# Access). This bit enables the 16-line access to IOCS0# in the Sub-ISA interface.  
0: 8-bit wide IOCS0# access is used.  
1: 16-bit wide IOCS0# access is used.  
DOC16 (Enable 16-Bit Wide DOCCS# Access). This bit enables the 16-line access to DOCCS# in the Sub-ISA interface.  
0: 8-bit wide DOCCS# access is used.  
1: 16-bit wide DOCCS# access is used.  
5
4
Reserved. Write as read.  
IRTXEN (Infrared Transmitter Enable). This bit enables drive of Infrared transmitter output.  
0: IRTX+SOUT3 line (ball C11) is HiZ.  
1: IRTX+SOUT3 line (ball C11) is enabled.  
3
BUS16 (16-Bit Wide Boot Memory). (Read Only) This bit reports the status of the BOOT16 strap (ball C8). If the BOOT16  
strap is pulled high, at reset 16-bit access to ROM in the Sub-ISA interface is enabled. MCR[14] = 1 inverts the meaning of  
this register.  
0: 8-bit wide ROM.  
1: 16-bit wide ROM.  
2:1  
Reserved. Write as read.  
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75  
32581C  
General Configuration Block  
Table 4-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)  
Bit  
Description  
0
SDBE0 (Slave Disconnect Boundary Enable). Works in conjunction with the GX1 module’s PCI Control Function 2 Regis-  
ter (Index 41h), bit 1 (SDBE1). Sets boundaries for when the GX1 module is a PCI slave.  
SDBE[1:0]  
00: Read and Write disconnect on boundaries set by bits [3:2] of the GX1 module’s PCI Control Function 2 register (Index  
41h).  
01: Write disconnects on boundaries set by bits [3:2] of the GX1 module’s PCI Control Function 2 register. Read discon-  
nects on cache line boundary of 16 bytes.  
1x: Read and Write disconnect on cache line boundary of 16 bytes.  
This bit is reset to 1.  
All PCI bus masters (including SC3200’s on-chip PCI bus masters, e.g., the USB Controller) must be disabled while modify-  
ing this bit. When accessing this register while any PCI bus master is enabled, use read-modify-write to ensure these bit  
contents are unchanged.  
Offset 38h  
Interrupt Selection Register - INTSEL (R/W)  
Reset Value: 00h  
This register selects the IRQ signal of the combined WATCHDOG and High-Resolution timer interrupt. This interrupt is shareable with  
other interrupt sources.  
7:4  
3:0  
Reserved. Write as read.  
CBIRQ. Configuration Block Interrupt.  
0000: Disable  
0001: IRQ1  
0100: IRQ4  
1000: IRQ8#  
1001: IRQ9  
1010: IRQ10  
1011: IRQ11  
1100: IRQ12  
1101: Reserved  
1110: IRQ14  
1111: IRQ15  
0101: IRQ5  
0110: IRQ6  
0111: IRQ7  
0010: Reserved  
0011: IRQ3  
Offset 39h-3Bh  
Offset 3Ch  
Reserved - RSVD  
Device Identification Number Register - ID (RO)  
Reset Value: xxh  
This register identifies the device. SC3200 = 04h.  
Offset 3Dh  
Revision Register - REV (RO)  
Reset Value: xxh  
Reset Value: xxh  
This register identifies the device revision. See the AMD Geode™ SC3200 Specification Update document for value.  
Offset 3Eh-3Fh Configuration Base Address Register - CBA (RO)  
This register sets the base address of the Configuration block.  
15:6  
5:0  
Configuration Base Address. These bits are the high bits of the Configuration Base Address.  
Configuration Base Address. These bits are the low bits of the Configuration Base Address. These bits are set to 0.  
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General Configuration Block  
32581C  
4.3  
WATCHDOG  
The SC3200 includes a WATCHDOG function to serve as a  
fail-safe mechanism in case the system becomes hung.  
When triggered, the WATCHDOG mechanism returns the  
system to a known state by generating an interrupt, an  
SMI, or a system reset (depending on configuration).  
• The GX1 module’s internal SUSPA# signal is 1.  
or  
• The GX1 module’s internal SUSPA# signal is 0 and the  
WD32KPD bit (Offset 02h[8]) is 0.  
The 32 KHz input clock is disabled, when:  
4.3.1  
Functional Description  
• The GX1 module’s internal SUSPA# signal is 0 and the  
WATCHDOG is enabled when the WATCHDOG Timeout  
(WDTO) register (Offset 00h) is set to a non-zero value.  
The WATCHDOG timer starts with this value and counts  
down until either the count reaches 0, or a trigger event  
restarts the count (with the WDTO register value).  
WD32KPD bit is 1.  
For more information about signal SUSPA#, refer to the  
AMD Geode™ GX1 Processor Data Book.  
When the WATCHDOG timer reaches 0:  
The WATCHDOG timer is restarted in any of the following  
cases:  
• If the WDOVF bit in the WDSTS register (Offset 04h[0])  
is 0, an interrupt, an SMI or a system reset is generated,  
depending on the value of the WDTYPE1 field in the  
WDCNFG register (Offset 02h[5:4]).  
• The WDTO register is set with a non-zero value.  
• The WATCHDOG timer reaches 0 and the WATCHDOG  
Overflow bit, WDOVF (Offset 04h[0]), is 0.  
• If the WDOVF bit in the WDSTS register is already 1  
when the WATCHDOG timer reaches 0, an interrupt, an  
SMI or a system reset is generated according to the  
WDTYPE2 field (Offset 02h[7:6]), and the timer is  
disabled. The WATCHDOG timer is re-enabled when a  
non-zero value is written to the WDTO register (Offset  
00h).  
The WATCHDOG function is disabled in any of the follow-  
ing cases:  
• System reset occurs.  
• The WDTO register is set to 0.  
• The WDOVF bit is already 1 when the timer reaches 0.  
The interrupt or SMI is de-asserted when the WDOVF bit is  
set to 0. The reset generated by the WATCHDOG function  
is used to trigger a system reset via the Core Logic mod-  
ule. The value of the WDOVF bit, the WDTYPE1 field, and  
the WDTYPE2 field are not affected by a system reset  
(except when generated by power-on reset).  
4.3.1.1 WATCHDOG Timer  
The WATCHDOG timer is a 16-bit down counter. Its input  
clock is a 32 KHz clock divided by a predefined value (see  
WDPRES field, Offset 02h[3:0]). The 32 KHz input clock is  
enabled when either:  
The SC3200 also allows no action to be taken when the  
timer reaches 0 (according to WDTYPE1 field and  
WDTYPE2 field). In this case only the WDOVF bit is set to  
1.  
Internal Fast-PCI Bus  
WATCHDOG  
WDTO  
SUSPA#  
32 KHz  
POR#  
WDPRES  
Timer  
WDOVF  
WDTYPE1 or  
WDTYPE2  
Reset IRQ SMI  
Figure 4-1. WATCHDOG Block Diagram  
AMD Geode™ SC3200 Processor Data Book  
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77  
     
32581C  
General Configuration Block  
WATCHDOG Interrupt  
4.3.2  
WATCHDOG Registers  
The WATCHDOG interrupt (if configured and enabled) is  
routed to an IRQ signal. The IRQ signal is programmable  
via the INTSEL register (Offset 38h, described in Table 4-2  
"Multiplexing, Interrupt Selection, and Base Address Regis-  
ters" on page 70). The WATCHDOG interrupt is a share-  
able, active low, level interrupt.  
Table 4-3 describes the WATCHDOG registers.  
4.3.2.1 Usage Hints  
• SMM code should set bit 8 of the WDCNFG register to 1  
when entering ACPI C3 state, if the WATCHDOG timer  
is to be suspended. If this is not done, the WATCHDOG  
timer is functional during C3 state.  
WATCHDOG SMI  
The WATCHDOG SMI is recognized by the Core Logic  
module as internal input signal EXT_SMI0#. To use the  
WATCHDOG SMI, Core Logic registers must be configured  
appropriately.  
• SMM code should set bit 8 of the WDCNFG register to  
1, when entering ACPI S1 and S2 states if the  
WATCHDOG timer is to be suspended. If this is not  
done, the WATCHDOG timer is functional during S1 and  
S2 states.  
Table 4-3. WATCHDOG Registers  
Bit  
Description  
Offset 00h-01h  
WATCHDOG Timeout Register - WDTO (R/W)  
Reset Value: 0000h  
Reset Value: 0000h  
This register specifies the programmed WATCHDOG timeout period.  
15:0 Programmed timeout period.  
Offset 02h-03h WATCHDOG Configuration Register - WDCNFG (R/W)  
This register selects the signal to be generated when the timer reaches 0, whether or not to disable the 32 KHz input clock during low  
power states, and the prescaler value of the clock input.  
15:9  
8
Reserved. Write as read.  
WD32KPD (WATCHDOG 32 KHz Power Down).  
0: 32 KHz clock is enabled.  
1: 32 KHz clock is disabled, when the GX1 module asserts its internal SUSPA# signal.  
This bit is cleared to 0, when POR# is asserted or when the GX1 module de-asserts its internal SUSPA# signal (i.e., on  
SUSPA# rising edge). See Section 4.3.2.1 "Usage Hints" on page 78.  
7:6  
5:4  
3:0  
WDTYPE2 (WATCHDOG Event Type 2).  
00: No action  
01: Interrupt  
10: SMI  
11: System reset  
This field is reset to 0 when POR# is asserted. Other system resets do not affect this field.  
WDTYPE1 (WATCHDOG Event Type 1).  
00: No action  
01: Interrupt  
10: SMI  
11: System reset  
This field is reset to 0 when POR# is asserted. Other system resets do not affect this field.  
WDPRES (WATCHDOG Timer Prescaler). Divide 32 KHz by:  
0000: 1  
0001: 2  
0010: 4  
0011: 8  
0100: 16  
0101: 32  
0110: 64  
0111: 128  
1000: 256  
1001: 512  
1010: 1024  
1011: 2048  
1100: 4096  
1101: 8192  
1110: Reserved  
1111: Reserved  
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General Configuration Block  
32581C  
Table 4-3. WATCHDOG Registers (Continued)  
Bit  
Description  
Offset 04h  
WATCHDOG Status Register - WDSTS (R/WC)  
Reset Value: 00h  
This register contains WATCHDOG status information.  
7:4  
3
Reserved. Write as read.  
WDRST (WATCHDOG Reset Asserted). (Read Only) This bit is set to 1 when WATCHDOG Reset is asserted. It is set to  
0 when POR# is asserted, or when the WDOVF bit is set to 0.  
2
1
0
WDSMI (WATCHDOG SMI Asserted). (Read Only) This bit is set to 1 when WATCHDOG SMI is asserted. It is set to 0  
when POR# is asserted, or when the WDOVF bit is set to 0.  
WDINT (WATCHDOG Interrupt Asserted. (Read Only) This bit is set to 1 when the WATCHDOG Interrupt is asserted. It  
is set to 0 when POR# is asserted, or when the WDOVF bit is set to 0.  
WDOVF (WATCHDOG Overflow). This bit is set to 1 when the WATCHDOG Timer reaches 0. It is set to 0 when POR# is  
asserted, or when a 1 is written to this bit by software. Other system reset sources do not affect this bit.  
Offset 05h-07h  
Reserved - RSVD  
4.4  
High-Resolution Timer  
The SC3200 provides an accurate time value that can be  
used as a time stamp by system software. This time is  
called the High-Resolution Timer. The length of the timer  
value can be extended via software. It is normally enabled  
while the system is in the C0 and C1 states. Optionally,  
software can be programmed to enable use of the High-  
Resolution Timer during C3 state and/or S1 state as well.  
In all other power states the High-Resolution Timer is dis-  
abled.  
The input clock (derived from the 27 MHz crystal oscillator)  
is enabled when:  
• The GX1 module’s internal SUSPA# signal is 1.  
or  
• The GX1 module’s internal SUSPA# signal is 0 and bit  
TM27MPD (Offset 0Dh[2]) is 0.  
The input clock is disabled, when the GX1 module’s inter-  
nal SUSPA# signal is 0 and the TM27MPD bit is 1.  
4.4.1  
Functional Description  
For more information about signal SUSPA# see Section  
4.4.2.1 "Usage Hints" on page 79 and the AMD Geode™  
GX1 Processor Data Book.  
The High-Resolution Timer is a 32-bit free-running count-  
up timer that uses the oscillator clock or the oscillator clock  
divided by 27. Bit TMCLKSEL of the TMCNFG register  
(Offset 0Dh[1]) can be set via software to determine which  
clock should be used for the High-Resolution Timer.  
The High-Resolution Timer function resides on the internal  
Fast-PCI bus and its registers are in General Configuration  
Block address space. Only one complete register should  
be accessed at-a-time (e.g., DWORD access should be  
used for DWORD wide registers and byte access should be  
used for byte-wide registers).  
When the most significant bit (bit 31) of the timer changes  
from 1 to 0, bit TMSTS of the TMSTS register (Offset  
0Ch[0]) is set to 1. When both bit TMSTS and bit TMEN  
(Offset 0Dh[0]) are 1, an interrupt is asserted. Otherwise,  
the interrupt is de-asserted. This interrupt enables software  
emulation of a larger timer.  
4.4.2  
High-Resolution Timer Registers  
Table 4-4 on page 80 describes the registers for the High-  
Resolution Timer (TIMER).  
The High-Resolution Timer interrupt is routed to an IRQ  
signal. The IRQ signal is programmable via the INTSEL  
register (Offset 38h). For more information about this regis-  
ter, see section Section 4.2 "Multiplexing, Interrupt Selec-  
tion, and Base Address Registers" on page 70.  
4.4.2.1 Usage Hints  
• SMM code should set bit 2 of the TMCNFG register to 1  
when entering ACPI C3 state if the High-Resolution  
Timer should be disabled. If this is not done, the High-  
Resolution Timer is functional during C3 state.  
System software uses the read-only TMVALUE register  
(Offset 08h[31:0]) to read the current value of the timer.  
The TMVALUE register has no default value.  
• SMM code should set bit 2 of the TMCNFG register to 1  
when entering ACPI S1 state if the High-Resolution  
Timer should be disabled. If this is not done, the High-  
Resolution Timer is functional during S1 state.  
AMD Geode™ SC3200 Processor Data Book  
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32581C  
General Configuration Block  
Table 4-4. High-Resolution Timer Registers  
Bit  
Description  
Offset 08h-0Bh  
TIMER Value Register - TMVALUE (RO)  
Reset Value: xxxxxxxxh  
Reset Value: 00h  
This register contains the current value of the High-Resolution Timer.  
31:0  
Current Timer Value.  
Offset 0Ch  
TIMER Status Register - TMSTS (R/W)  
This register supplies the High-Resolution Timer status information.  
7:1  
0
Reserved.  
TMSTS (TIMER Status). This bit is set to 1 when the most significant bit (bit 31) of the timer changes from 1 to 0. It is  
cleared to 0 upon system reset or when 1 is written by software to this bit.  
Offset 0Dh  
TIMER Configuration Register - TMCNFG (R/W)  
Reset Value: 00h  
This register enables the High-Resolution Timer interrupt; selects the Timer clock; and disables the 27 MHz internal clock during low  
power states.  
7:3  
2
Reserved.  
TM27MPD (TIMER 27 MHz Power Down). This bit is cleared to 0 when POR# is asserted or when the GX1 module de-  
asserts its internal SUSPA# signal (i.e., on SUSPA# rising edge). See Section 4.4.2.1 "Usage Hints" on page 79.  
0: 27 MHz input clock is enabled.  
1: 27 MHz input clock is disabled when the GX1 module asserts its internal SUSPA# signal.  
TMCLKSEL (TIMER Clock Select).  
1
0
0: Count-up timer uses the oscillator clock divided by 27.  
1: Count-up timer uses the oscillator clock, 27 MHz clock.  
TMEN (TIMER Interrupt Enable).  
0: High-Resolution Timer interrupt is disabled.  
1: High-Resolution Timer interrupt is enabled.  
Offset 0Eh-0Fh  
Reserved - RSVD  
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General Configuration Block  
32581C  
4.5  
Clock Generators and PLLs  
This section describes the registers for the clocks required  
by the GX1 module, Core Logic module, and the Video  
Processor, and how these clocks are generated. See Fig-  
ure 4-2 for a clock generation diagram.  
The clock generators are based on 32.768 KHz and 27.000  
MHz crystal oscillators. The 32.768 KHz crystal oscillator is  
described in Section 5.5.2 "RTC Clock Generation" on  
page 103 (functional description of the RTC).  
Real-Time Clock (RTC)  
32.768 KHz  
32.768 KHz  
USB Clock (48 MHz)  
and I/O Block Clock  
Crystal  
Oscillator  
PLL4  
48 MHz  
Shutdown  
DISABLE  
AC97_CLK  
(24.576 MHz)  
To PAD  
PLL3  
24.576 MHz  
Shutdown  
Shutdown  
27 MHz  
Crystal  
High-Resolution Timer Clock  
Oscillator  
ACPI Clock (14.318 MHz)  
Divide  
PLL6  
57.273 MHz  
by 4  
CLK27M Ball  
Shutdown  
Dot Clock  
CLK  
PLL2  
Shutdown  
DISABLE  
25-135 MHz  
48 MHz  
Internal Fast-PCI Clock  
66 MHz  
PLL5  
66.67 MHz  
Shutdown  
(ACPI)  
33 MHz  
External PCI Clock  
(33.3 MHz)  
Divide  
by 2  
DISABLE  
Core Clock  
ADL  
100-333 MHz  
Shutdown  
(ACPI)  
SDRAM Clock  
Divider  
Note:  
V
powers PLL2 and PLL5. V  
powers PLL3, PLL4, and PLL6.  
PLL2  
PLL3  
Figure 4-2. Clock Generation Block Diagram  
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81  
     
32581C  
General Configuration Block  
4.5.1  
27 MHz Crystal Oscillator  
The internal oscillator employs an external crystal con-  
nected to the on-chip amplifier. The on-chip amplifier is  
accessible on the X27I input and X27O output signals. See  
Figure 4-3 for the recommended external circuit and Table  
4-5 for a list of the circuit components.  
To other  
modules  
Internal  
External  
X27O  
X27I  
Choose C and C capacitors to match the crystal’s load  
1
2
R
1
capacitance. The load capacitance C “seen” by crystal Y  
R
2
L
is comprised of C in series with C and in parallel with the  
1
2
parasitic capacitance of the circuit. The parasitic capaci-  
tance is caused by the chip package, board layout and  
socket (if any), and can vary from 0 to 10 pF. The rule of  
thumb in choosing these capacitors is:  
C
C
2
Y
1
Figure 4-3. Recommended Oscillator External  
Circuitry  
C = (C * C ) / (C + C ) + C  
L
1
2
1
2
PARASITIC  
Example 1:  
Crystal C = 10 pF, C  
= 8.2 pF  
= 8 pF  
L
PARASITIC  
C = 3.6 pF, C = 3.6 pF  
1
2
Example 2:  
Crystal C = 20 pF, C  
L
PARASITIC  
C = 24 pF, C = 24 pF  
1
2
Table 4-5. Crystal Oscillator Circuit Components  
Component  
Parameters  
Values  
Tolerance  
Crystal  
Resonance Frequency  
Type  
27.00 MHz Parallel mode  
50 PPM or better  
AT-cut or BT-cut  
40 Ω  
Serial Resistance  
Shunt Capacitance  
Max  
Max  
7 pF  
Load Capacitance, C  
10-20 pF  
L
Temperature Coefficient  
Resistance  
User-defined  
Resistor R  
Resistor R  
20 MΩ  
5%  
5%  
1
1
Resistance  
Capacitance  
Capacitance  
100 Ω  
2
1
1
3-24 pF  
3-24 pF  
5%  
5%  
Capacitor C  
Capacitor C  
1
2
1. The value of these components is recommended. It should be tuned according to crystal and board parameters.  
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General Configuration Block  
32581C  
4.5.2  
GX1 Module Core Clock  
Table 4-6. Core Clock Frequency  
Internal Fast-PCI Clock Freq. (MHz)  
The core clock is generated by an Analog Delay Loop  
(ADL) clock generator from the internal Fast-PCI clock. The  
clock can be any whole-number multiple of the input clock  
between 4 and 10. Possible values are listed in Table 4-6.  
ADL  
Multiplier  
Value  
33.33  
48  
66.67  
At power-on reset, the core clock multiplier value is set  
according to the value of four strapped balls - CLKSEL[3:0]  
(balls P30, D29, AF3, B8). These balls also select the clock  
which is used as input to the multiplier, as shown in Table  
4-7.  
4
5
133.3  
166.7  
200  
192  
240  
288  
---  
266.7  
---  
6
---  
7
233.3  
266.7  
---  
---  
8
---  
---  
4.5.3  
Internal Fast-PCI Clock  
The internal Fast-PCI clock can be configured to 33, 48, or  
66 MHz via strap options on the CLKSEL1 and CLKSEL0  
balls. These can be read in the internal Fast-PCI Clock field  
in the CCFC register (GCB+I/O Offset 1Eh[9:8]). (See  
Table 4-8 on page 85 details on the CCFC register.)  
9
---  
---  
10  
---  
---  
---  
Table 4-7. Strapped Core Clock Frequency  
Default ADL Multiplier  
Internal Fast-PCI Clock  
CLKSEL[3:0]  
Straps  
Freq. (MHz)  
(GCB+I/O Offset 1Eh[9:8])  
Multiplier Value  
(GCB+I/O Offset 1Eh[3:0])  
Maximum Core  
Clock Freq. (MHz)  
Multiply By  
0111  
1011  
1111  
0000  
0100  
1000  
1100  
0001  
0101  
1001  
1101  
0110  
1010  
33.33  
4
5
0100  
0101  
0110  
0111  
1000  
1001  
1010  
0100  
0101  
0110  
0111  
0100  
0101  
133  
167  
6
200  
7
233  
8
266  
9
Reserved  
Reserved  
192  
10  
4
48  
5
240  
6
288  
7
Reserved  
266  
66.67  
4
5
Reserved  
Note: Not all speeds are supported. For information on supported speeds, see Section A.1 "Order Information" on page  
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32581C  
General Configuration Block  
4.5.4  
SuperI/O Clocks  
4.5.6  
Video Processor Clocks  
The SuperI/O module requires a 48 MHz input for Fast  
infrared (FIR), UART, and other functions. This clock is sup-  
plied by PLL4 using a multiplier value of 576/(108x3) to  
generate 48 MHz.  
The Video processor requires the following clock sources:  
Dot  
The Dot clock is generated by PLL2. It is supplied to the  
Display Controller in the GX1 module (DCLK) that creates  
the pixel information, and is returned to the Graphics block  
(PCLK) with this information. PLL2 uses the 27 MHz clock  
to generate the Dot clock.  
4.5.5  
Core Logic Module Clocks  
The Core Logic module requires the following clock  
sources:  
Video  
Real-Time Clock (RTC)  
The Video clock source depends on the source of the video  
data.  
RTC requires a 32.768 KHz clock which is supplied directly  
from an internal low-power crystal oscillator. This oscillator  
uses battery power and has very low current consumption.  
• If the video data is coming from the GX1 module  
(Capture Video mode), the video clock is generated by  
the Display Controller.  
USB  
The USB requires a 48 MHz input which is supplied by  
PLL4. The required total frequency accuracy and slow jitter  
for USB is 500 PPM; edge to edge jitter is ±1.2%.  
• If the video data is coming directly from the VIP block  
(Direct Video mode), the Video Clock is generated by  
the VIP block.  
ACPI  
The ACPI logic block uses a 14.32 MHz clock supplied by  
PLL6. PLL6 creates this clock from the 32.768 KHz clock,  
with a multiplier value of 6992/4 to output a 57.278 MHz  
clock that is divided by 4.  
External PCI  
The PCI Interface uses a 33.3 MHz clock that is created by  
PLL5 and divided by 2. PLL5 uses the 27 MHz clock, to  
output a 66.67 MHz clock. PLL5 has a frequency accuracy  
of ± 0.1%.  
AC97  
The SC3200 generates the 24.576 MHz clock required by  
the audio codec. Therefore, no crystal need be included for  
the audio codec on the system board.  
PLL3 uses the crystal oscillator clock, to generate a 24.576  
MHz clock. This clock is driven on the AC97_CLK ball. The  
accuracy of the clock supplied by the SC3200 is 50 PPM.  
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General Configuration Block  
32581C  
4.5.7  
Clock Registers  
Table 4-8 describes the registers of the clock generator and PLL.  
Table 4-8. Clock Generator Configuration  
Bit  
Description  
Offset 10h  
Maximum Core Clock Multiplier Register - MCCM (RO)  
Reset Value: Strapped Value  
This register holds the maximum core clock multiplier value. The maximum clock frequency allowed by the core, is the Fast-PCI clock  
multiplied by this value.  
7:4  
3:0  
Reserved.  
MCM (Maximum Clock Multiplier). This 4-bit value is the maximum multiplier value allowed for the core clock generator. It  
is derived from strap pins CLKSEL[3:0] based on the multiplier value in Table 4-7 on page 83.  
Offset 11h  
Reserved - RSVD  
Offset 12h  
PLL Power Control Register - PPCR (R/W)  
Reset Value: 2Fh  
This register controls operation of the PLLs.  
7
6
Reserved.  
EXPCID (Disable External PCI Clock).  
0: External PCI clock is enabled.  
1: External PCI clock is disabled.  
5
GPD (Disable Graphic Pixel Reference Clock).  
0: PLL2 input clock is enabled.  
1: PLL2 input clock is disabled.  
Reserved.  
4
3
PLL3SD (Shut Down PLL3). AC97 codec clock.  
0: PLL3 is enabled.  
1: PLL3 is shutdown.  
2
1
0
FM1SD (Shut Down PLL4).  
0: PLL4 is enabled.  
1: PLL4 is shutdown, unless internal Fast-PCI clock is strapped to 48 MHz.  
C48MD (Disable SuperI/O and USB Clock).  
0: USB and SuperI/O clock is enabled.  
1: USB and SuperI/O clock is disabled.  
Reserved. Write as read.  
Offset 13h-17h  
Offset 18h-1Bh  
Reserved - RSVD  
PLL3 Configuration Register - PLL3C (R/W)  
Reset Value: E1040005h  
31:24  
MFFC (MFF Counter Value).  
Fvco = OSCCLK * MFBC / (MFFC * MOC)  
OSCCLK = 27 MHz  
23:19  
18:8  
Reserved. Write as read.  
MFBC (MFB Counter Value).  
Fvco  
= OSCCLK * MFBC / (MFFC * MOC)  
OSCCLK = 27 MHz  
Note: Bits 18, 9, and 8 cannot be changed. Bit 18 is always a 1; bits 9 and 8 are always 0.  
7
6
Reserved. Write as read.  
Reserved. Must be set to 0.  
MOC (MO Counter Value).  
5:0  
Fvco  
= OSCCLK * MFBC / (MFFC * MOC)  
OSCCLK = 27 MHz  
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32581C  
General Configuration Block  
Reset Value: Strapped Value  
Table 4-8. Clock Generator Configuration (Continued)  
Bit  
Description  
Offset 1Eh-1Fh  
Core Clock Frequency Control Register - CCFC (R/W)  
This register controls the configuration of the core clock multiplier and the reference clocks.  
15:14  
13  
Reserved.  
Reserved. Must be set to 0.  
Reserved. Must be set to 0.  
Reserved.  
12  
11:10  
9:8  
FPCICK (Internal Fast-PCI Clock). (Read Only) Reflects the internal Fast-PCI clock and is the input to the GX1 module  
that is used to generate the core clock. These bits reflect the value of strap pins CLKSEL[1:0].  
00: 33.3 MHz  
01: 48 MHz  
10: 66.7 MHz  
11: 33.3 MHz  
Reserved.  
7:4  
3:0  
MVAL (Multiplier Value). This 4-bit value controls the multiplier in ADL. The value is set according to the Maximum Clock  
Multiplier bits of the MCCM register (Offset 10h). The multiplier value should never be written with a multiplier which is differ-  
ent from the multiplier indicated in the MCCM register.  
0100: Multiply by 4  
0101: Multiply by 5  
0110: Multiply by 6  
0111: Multiply by 7  
1000: Multiply by 8  
1001: Multiply by 9  
1010: Multiply by 10  
Other: Reserved  
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5.0SuperI/O Module  
5
The SuperI/O (SIO) module is a PC98 and ACPI compliant  
SIO that offers a single-cell solution to the most commonly  
used ISA peripherals.  
Outstanding Features  
• Full compatibility with ACPI Revision 1.0 requirements.  
• System Wakeup Control powered by V , generates  
SB  
The SIO module incorporates: two Serial Ports, an Infrared  
Communication Port that supports FIR, MIR, HP-SIR,  
Sharp-IR, and Consumer Electronics-IR, a full IEEE 1284  
Parallel Port, two ACCESS.bus Interface (ACB) ports, Sys-  
tem Wakeup Control (SWC), and a Real-Time Clock (RTC)  
that provides RTC timekeeping.  
power-up request and a PME (power management  
event) in response to SDATA_IN2 (an audio codec),  
IRRX1 (a pre-programmed CEIR), or a RI2# (serial port  
ring indicate) event.  
• Advanced RTC, Y2K compliant.  
Serial  
Interface  
Serial  
Interface  
Infrared/Serial  
ISA  
Interface  
V
V
SB  
BAT  
Interface  
IR Comunication  
Port/Serial Port 3  
Serial Port 1  
Serial Port 2  
Real-Time Clock  
Host Interface  
System Wakeup  
IEEE 1284  
Parallel Port  
ACCESS.bus 1  
ACCESS.bus 2  
Control  
Wakeup PWUREQ  
Events  
AB1C  
AB1D  
AB2C  
AB2D  
Parallel Port  
Interface  
Figure 5-1. SIO Block Diagram  
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5.1  
Features  
PC98 and ACPI Compliant  
System Wakeup Control (SWC)  
• PnP Configuration Register structure  
• Power-up request upon detection of RI2#, CEIR, or  
SDATA_IN2 activity:  
• Flexible resource allocation for all logical devices:  
— Relocatable base address  
— Optional routing of power-up request on IRQ line  
— 9 Parallel IRQ routing options  
• Pre-programmed CEIR address in a pre-selected  
— 3 optional 8-bit DMA channels (where applicable)  
standard (any NEC, RCA or RC-5)  
• Powered by V  
SB  
Parallel Port  
• Battery-backed wakeup setup  
• Power-fail recovery support  
• Software or hardware control  
• Enhanced Parallel Port (EPP) compatible with version  
EPP 1.9 and IEEE 1284 compliant  
Real-Time Clock  
• EPP support for version EPP 1.7 of the Xircom specifi-  
• A modifiable address that is referenced by a 16-bit  
cation  
programmable register  
• EPP support as mode 4 of the Extended Capabilities  
• DS1287, MC146818 and PC87911 compatibility  
Port (ECP)  
• 242 bytes of battery backed up CMOS RAM in two  
• IEEE 1284 compliant ECP, including level 2  
banks  
• Selection of internal pull-up or pull-down resistor for  
• Selective lock mechanisms for the CMOS RAM  
Paper End (PE) pin  
• Battery backed up century calendar in days, day of the  
week, date of month, months, years and century, with  
automatic leap-year adjustment  
• PCI bus utilization reduction by supporting a demand  
DMA mode mechanism and a DMA fairness mechanism  
• Protection circuit that prevents damage to the parallel  
port when a printer connected to it powers up or is oper-  
ated at high voltages, even if the device is in power-  
down  
• Battery backed-up time of day in seconds, minutes and  
hours that allows a 12 or 24 hour format and adjust-  
ments for daylight savings time  
• BCD or binary format for time keeping  
• Output buffers that can sink and source 14 mA  
• Three different maskable interrupt flags:  
— Periodic interrupts - At intervals from 122 ms to 500  
ms  
Serial Port 1  
• 16550A compatible (SIN1, SOUT1, DTR1#/BOUT1  
— Time-of-Month alarm - At intervals from once per  
second to once per month  
signals only)  
— Update Ended Interrupt - Once per second upon  
completion of update  
Serial Port 2  
• 16550A compatible  
• Separate battery pin, 3.0V operation that includes an  
internal UL protection resistor  
Serial Port 3 / Infrared (IR) Communication Port  
• 7 µA typical power consumption during power down  
• Double-buffer time registers  
• Serial Port 3  
— SIN and SOUT signals only  
— Data rate of up to 1.5-Mbps  
• Y2K Compliant  
— Software compatible with the 16550A and the 16450  
— Shadow register support for write-only bit monitoring  
— DMA support  
Clock Sources  
• 48 MHz clock input  
• IR Communication Port  
— IrDA 1.1 and 1.0 compatible  
• On-chip low frequency clock generator for wakeup  
— Data rate of up to 115.2 Kbps (HP-SIR)  
— Data rate of 1.152 Mbps (MIR)  
— Data rate of 4.0 Mbps (FIR)  
• 32.768 KHz crystal with an internal frequency multiplier  
to generate all required internal frequencies  
— Selectable internal or external modulation/demodula-  
tion (ASK-IR and DASK-IR options of SHARP-IR)  
— Consumer-IR (TV-Remote) mode  
— Consumer Remote Control supports RC-5, RC-6,  
NEC, RCA and RECS 80  
— DMA support  
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5.2  
Module Architecture  
The SIO module comprises a collection of generic func-  
tional blocks. Each functional block is described in detail  
later in this chapter. The beginning of this chapter  
describes the SIO structure and provides all device specific  
information, including special implementation of generic  
blocks, system interface and device configuration.  
The central configuration register set supports ACPI com-  
pliant PnP configuration. The configuration registers are  
structured as a subset of the Plug and Play Standard Reg-  
isters, defined in Appendix A of the Plug and Play ISA  
Specification Version 1.0a by Intel and Microsoft®. All sys-  
tem resources assigned to the functional blocks (I/O  
address space, DMA channels and IRQ lines) are config-  
ured in, and managed by, the central configuration register  
set. In addition, some function-specific parameters are con-  
figurable through this unit and distributed to the functional  
blocks through special control signals.  
The SIO module is based on eight logical devices, the host  
interface, and a central configuration register set, all built  
around a central, internal 8-bit bus.  
The host interface serves as a bridge between the external  
ISA interface and the internal bus. It supports 8-bit I/O  
read, 8-bit I/O write and 8-bit DMA transactions, as defined  
in Personal Computer Bus Standard P996.  
The source of the device internal clocks is the 48 MHz  
clock signal or through the 32.768 KHz crystal with an  
internal frequency multiplier. RTC operates on a 32 KHz  
clock.  
ACK#  
AFD#/DSTRB#  
BUSY/WAIT#  
ERR#  
SIN1  
Infrared  
Communication  
Port/Serial Port 3  
Serial  
Port 1  
SOUT1  
Parallel  
Port  
INIT#  
PD[7:0]  
DTR#/BOUT1  
PE  
SLCT  
SLIN#/ASTRB#  
STB#/WRITE#  
SIN2  
SOUT2  
RTS2#  
DTR2#/BOUT2  
CTS2  
RI2#  
DCD2#  
DSR2#  
Serial  
Port 2  
Configuration  
and Control  
Registers  
AB1C  
AB1D  
ACCESS.  
bus 1  
TC  
AB2C  
AB2D  
DACK0-3  
DRQ0-3  
IRQ1-12,14-15  
IOCHRDY  
ZWS#  
IOWR#  
IORD#  
ACCESS.  
bus 2  
Internal  
Host  
Interface  
Internal  
Signals  
System  
Wakeup  
Real-Time Clock (RTC)  
AEN  
Internal  
Signal  
Internal Signals  
Figure 5-2. Detailed SIO Block Diagram  
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5.3  
Configuration Structure / Access  
This section describes the structure of the configuration  
register file, and the method of accessing the configuration  
registers.  
Table 5-2. LDN Assignments  
LDN Functional Block  
Reference  
00h  
01h  
02h  
Real-Time Clock (RTC)  
Page 96  
Page 98  
Page 99  
5.3.1  
Index-Data Register Pair  
System Wakeup Control (SWC)  
The SIO configuration access is performed via an Index-  
Data register pair, using only two system I/O byte locations.  
The base address of this register pair is determined  
according to the state of the IO_SIOCFG_IN bit field of the  
Core Logic module (F5BAR0+I/O Offset 00h[26:25]). Table  
5-1 shows the selected base addresses as a function of the  
IO_SIOCFG_IN bit field.  
Infrared Communication Port  
(IRCP) or Serial Port 3 (SP3)  
03h  
05h  
06h  
07h  
08h  
Serial Port 1 (SP1)  
ACCESS.bus 1 (ACB1)  
ACCESS.bus 2 (ACB2)  
Parallel Port (PP)  
Page 100  
Page 101  
Page 102  
Page 100  
Table 5-1. SIO Configuration Options  
I/O Address  
Serial Port 2 (SP2)  
Figure 5-3 shows the structure of the standard PnP config-  
uration register file. The SIO Control And Configuration  
registers are not banked and are accessed by the Index-  
Data register pair only (as described above). However, the  
Logical Device Control and Configuration registers are  
duplicated over eight banks for eight logical devices. There-  
fore, accessing a specific register in a specific bank is per-  
formed by two-dimensional indexing, where the LDN  
register selects the bank (or logical device), and the Index  
register selects the register within the bank. Accessing the  
Data register while the Index register holds a value of 30h  
or higher results in a physical access to the Logical Device  
Configuration registers currently pointed to by the Index  
register, within the logical device bank currently selected by  
the LDN register.  
IO_SIOCFG_IN  
Settings  
Index  
Register Register  
Data  
Description  
00  
01  
-
-
-
-
SIO disabled  
Configuration  
access disabled  
10  
11  
002Eh  
015Ch  
002Fh  
Base address 1  
selected  
015Dh Base address 2  
selected  
The Index Register is an 8-bit R/W register located at the  
selected base address (Base+0). It is used as a pointer to  
the configuration register file, and holds the index of the  
configuration register that is currently accessible via the  
Data Register. Reading the Index Register returns the last  
value written to it (or the default of 00h after reset).  
07h  
Logical Device Number Register  
20h  
2Fh  
SIO Configuration Registers  
The Data Register is an 8-bit virtual register, used as a  
data path to any configuration register. Accessing the data  
register results with physically accessing the configuration  
register that is currently pointed by the Index Register.  
Logical Device Control Register  
30h  
60h  
63h  
5.3.2  
Banked Logical Device Registers  
Standard Logical Device  
70h  
71h  
74h  
75h  
Each functional block is associated with a Logical Device  
Number (LDN). The configuration registers are grouped  
into banks, where each bank holds the standard configura-  
tion registers of the corresponding logical device. Table 5-2  
shows the LDNs of the device functional blocks.  
Standard Registers  
Bank  
Select  
Special (Vendor-defined)  
Logical Device  
Configuration Registers  
F0h  
FEh  
Banks  
(One per Logical Device)  
Figure 5-3. Structure of the Standard  
Configuration Register File  
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Write accesses to unimplemented registers (i.e., accessing  
the Data register while the Index register points to a non-  
existing register or the LDN is 07h or higher than 08h), are  
ignored and a read returns 00h on all addresses except for  
74h and 75h (DMA configuration registers) which returns  
04h (indicating no DMA channel is active). The configura-  
tion registers are accessible immediately after reset.  
The SIO module wakes up with the default setup, as fol-  
lows:  
• When a hardware reset occurs:  
— The configuration base address is 2Eh, 15Ch or  
None, according to the IO_SIOCFG_IN bit values, as  
shown in Table 5-1 on page 90.  
— All Logical devices are disabled, with the exception of  
the RTC and the SWC, which remains functional but  
whose registers cannot be accessed.  
5.3.3  
Default Configuration Setup  
The device has four reset types:  
• When either a hardware or a software reset occurs:  
— The legacy devices are assigned with their legacy  
system resource allocation.  
Software Reset  
This reset is generated by bit 1 of the SIOCF1 register,  
which resets all logical devices. A software reset also  
resets most bits in the SIO Configuration and Control regis-  
ters (see Section 5.4.1 on page 95 for the bits not affected).  
This reset does not affect register bits that are locked for  
write access.  
— The AMD proprietary functions are not assigned with  
any default resources and the default values of their  
base addresses are all 00h.  
5.3.4  
Address Decoding  
Hardware Reset  
A full 16-bit address decoding is applied when accessing  
the configuration I/O space, as well as the registers of the  
functional blocks. However, the number of configurable bits in  
the base address registers vary for each device.  
This reset is activated by the system reset signal. This  
resets all logical devices, with the exception of the RTC and  
the SWC, and all SIO Configuration and Control registers,  
with the exception of the SIOCF2 register. It also resets all  
SuperI/O control and configuration registers, except for  
those that are battery-backed.  
The lower 1, 2, 3 or 4 address bits are decoded within the  
functional block to determine the offset of the accessed  
register, within the device’s I/O range of 2, 4, 8 or 16 bytes,  
respectively. The rest of the bits are matched with the base  
address register to decode the entire I/O range allocated to  
the device. Therefore the lower bits of the base address  
register are forced to 0 (RO), and the base address is  
forced to be 2, 4, 8 or 16 byte aligned, according to the size  
of the I/O range.  
V
Power-Up Reset  
PP  
This reset is activated when either V or V  
on after both have been off. V  
which is a combination of V and V . V is taken from  
is powered  
is an internal voltage  
SB  
BAT  
PP  
SB  
BAT PP  
V
if V is greater than the minimum (Min) value defined  
SB  
SB  
in Section 9.1.4 "Operating Conditions" on page 352; oth-  
erwise, V is used as the V source. This reset resets  
BAT  
PP  
The base address of the RTC, Serial Port 1, Serial Port 2,  
and the Infrared Communication Port are limited to the I/O  
address range of 00h to 7Fxh only (bits [15:11] are forced  
to 0). The Parallel Port base address is limited to the I/O  
address range of 00h to 3F8h. The addresses of the non-  
legacy devices are configurable within the full 16-bit  
address range (up to FFFxh).  
all registers whose values are retained by V  
PP.  
V
Power-Up Reset  
SB  
This is an internally generated reset that resets the SWC,  
excluding those SWC registers whose values are retained  
by V . This reset is activated after V is powered up.  
PP  
SB  
In some special cases, other address bits are used for  
internal decoding (such as 10 in the Parallel Port). For  
more details, please see the detailed description of the  
base address register for each specific logical device.  
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5.4  
Standard Configuration Registers  
As illustrated in Figure 5-4, the Standard Configuration reg-  
isters are broadly divided into two categories: SIO Control  
and Configuration registers and Logical Device Control and  
Configuration registers (one per logical device, some are  
optional).  
(except for the RTC and the SWC). Activation of the block  
enables access to the block’s registers, and attaches its  
system resources, which are unused as long as the block is  
not activated. Activation of the block may also result in  
other effects (e.g., clock enable and active signaling), for  
certain functions.  
SIO Control and Configuration Registers  
Standard Logical Device Configuration Registers  
(Index 60h-75h): These registers are used to manage the  
resource allocation to the functional blocks. The I/O port  
base address descriptor 0 is a pair of registers at Index  
60h-61h, holding the (first or only) 16-bit base address for  
the register set of the functional block. An optional second  
base-address (descriptor 1) at Index 62h-63h is used for  
devices with more than one continuous register set. Inter-  
rupt Number Select (Index 70h) and Interrupt Type Select  
(Index 71h) allocate an IRQ line to the block and control its  
type. DMA Channel Select 0 (Index 74h) allocates a DMA  
channel to the block, where applicable. DMA Channel  
Select 1 (Index 75h) allocates a second DMA channel,  
where applicable.  
The only PnP control register in the SIO module is the Log-  
ical Device Number register at Index 07h. All other stan-  
dard PnP control registers are associated with PnP  
protocol for ISA add-in cards, and are not supported by the  
SIO module.  
The SIO Configuration registers at Index 20h-27h are  
mainly used for part identification. (See Section 5.4.1 "SIO  
Control and Configuration Registers" on page 95 for further  
details.)  
Logical Device Control and Configuration Registers  
A subset of these registers is implemented for each logical  
device. (See Table 5-2 on page 90 for LDN assignment and  
Section 5.4.2 "Logical Device Control and Configuration"  
on page 96 for register details.)  
Special Logical Device Configuration Registers (F0h-  
F3h): The vendor-defined registers, starting at Index F0h  
are used to control function-specific parameters such as  
operation modes, power saving modes, pin TRI-STATE,  
clock rate selection, and non-standard extensions to  
generic functions.  
Logical Device Control Register (Index 30h): The only  
implemented Logical Device Control register is the Activate  
register at Index 30. Bit 0 of the Activate register and bit 0  
of the SIO Configuration 1 register (Global Device Enable  
bit) control the activation of the associated function block  
Index  
Register Name  
Logical Device Number  
07h  
20h  
21h  
22h  
27h  
2Eh  
30h  
60h  
61h  
62h  
63h  
70h  
71h  
74h  
75h  
F0h  
F1h  
F2h  
F3h  
SIO ID  
SIO Configuration 1  
SIO Control and  
Configuration Registers  
SIO Configuration 2  
SIO Revision ID  
Reserved exclusively for AMD use  
Logical Device Control (Activate)  
I/O Port Base Address Descriptor 0 Bits [15:8]  
I/O Port Base Address Descriptor 0 Bits [7:0]  
I/O Port Base Address Descriptor 1 Bits [15:8]  
I/O Port Base Address Descriptor 1 Bits [7:0]  
Interrupt Number Select  
Logical Device Control and  
Configuration Registers -  
one per logical device  
(some are optional)  
Interrupt Type Select  
DMA Channel Select 0  
DMA Channel Select 1  
Device Specific Logical Device Configuration 1  
Device Specific Logical Device Configuration 2  
Device Specific Logical Device Configuration 3  
Device Specific Logical Device Configuration 4  
Figure 5-4. Standard Configuration Registers Map  
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Table 5-3 provides the bit definitions for the Standard Con-  
figuration registers.  
write to prevent the values of reserved bits from being  
changed during write.  
• All reserved bits return 0 on reads, except where noted  
otherwise. They must not be modified as such modifica-  
tion may cause unpredictable results. Use read-modify-  
• Write only registers should not use read-modify-write  
during updates.  
Table 5-3. Standard Configuration Registers  
Bit  
Description  
Index 07h  
Logical Device Number (R/W)  
This register selects the current logical device. See Table 5-2 for valid numbers. All other values are reserved.  
7:0 Logical Device number.  
Index 20h-2Fh  
SIO configuration and ID registers. See Section 5.4.1 "SIO Control and Configuration Registers" on page 95 for register/bit details.  
SIO Configuration (R/W)  
Index 30h  
Activate (R/W)  
7:1  
0
Reserved.  
Logical Device Activation Control.  
0: Disable  
1: Enable  
Index 60h  
7:0  
I/O Port Base Address Bits [15:8] Descriptor 0 (R/W)  
Descriptor 0 A[15:8]. Selects I/O lower limit address bits [15:8] for I/O Descriptor 0.  
I/O Port Base Address Bits [7:0] Descriptor 0 (R/W)  
Index 61h  
7:0  
Descriptor 0 A[7:0]. Selects I/O lower limit address bits [7:0] for I/O Descriptor 0.  
I/O Port Base Address Bits [15:8] Descriptor 1 (R/W)  
Descriptor 1 A[15:8]. Selects I/O lower limit address bits [15:8] for I/O Descriptor 1.  
I/O Port Base Address Bits [7:0] Descriptor 1 (R/W)  
Index 62h  
7:0  
Index 63h  
7:0  
Descriptor 1 A[7:0]. Selects I/O lower limit address bits [7:0] for I/O Descriptor 1.  
Interrupt Number (R/W)  
Index 70h  
7:4  
3:0  
Reserved.  
Interrupt Number. These bits select the interrupt number. A value of 1 selects IRQ1, a value of 2 selects IRQ2, etc. (up to  
IRQ12).  
Note: IRQ0 is not a valid interrupt selection.  
Index 71h  
Interrupt Request Type Select (R/W)  
Selects the type and level of the interrupt request number selected in the previous register.  
7:2  
1
Reserved.  
Interrupt Level Requested. Level of interrupt request selected in previous register.  
0: Low polarity.  
1: High polarity.  
This bit must be set to 1 (high polarity), except for IRQ8#, that must be low polarity.  
0
Interrupt Type Requested. Type of interrupt request selected in previous register.  
0: Edge.  
1: Level.  
Index 74h  
DMA Channel Select 0 (R/W)  
Selects selected DMA channel for DMA 0 of the logical device (0 - the first DMA channel in case of using more than one DMA channel).  
7:3  
2:0  
Reserved.  
DMA 0 Channel Select. This bit field selects the DMA channel for DMA 0.  
The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc.  
A value of 4 indicates that no DMA channel is active.  
Values 5-7 are reserved.  
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Table 5-3. Standard Configuration Registers (Continued)  
Bit  
Description  
Index 75h  
DMA Channel Select 1 (R/W)  
Indicates selected DMA channel for DMA 1 of the logical device (1 - the second DMA channel in case of using more than one DMA  
channel).  
7:3  
2:0  
Reserved.  
DMA 1 Channel Select: This bit field selects the DMA channel for DMA 1.  
The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc.  
A value of 4 indicates that no DMA channel is active.  
Values 5-7 are reserved.  
Index F0h-FEh  
Logical Device Configuration (R/W)  
Special (vendor-defined) configuration options.  
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5.4.1  
SIO Control and Configuration Registers  
Table 5-4 lists the SIO Control and Configuration registers and Table 5-5 provides their bit formats.  
Table 5-4. SIO Control and Configuration Register Map  
Index  
20h  
Type  
RO  
Name  
Power Rail  
Reset Value  
SID. SIO ID  
V
V
F5h  
01h  
02h  
01h  
---  
CORE  
CORE  
21h  
R/W  
R/W  
RO  
SIOCF1. SIO Configuration 1  
SIOCF2. SIO Configuration 2  
SRID. SIO Revision ID  
RSVD. Reserved exclusively for AMD use.  
22h  
V
PP  
27h  
V
CORE  
2Eh  
---  
---  
Table 5-5. SIO Control and Configuration Registers  
Bit  
Description  
Index 20h  
7:0  
SIO ID Register - SID (RO)  
Reset Value: F5h  
Reset Value: 01h  
Chip ID. Contains the identity number of the module. The SIO module is identified by the value F5h.  
Index 21h  
7:6  
SIO Configuration 1 Register - SIOCF1 (RW)  
General Purpose Scratch. When bit 5 is set to 1, these bits are RO. After reset, these bits can be read or write. Once  
changed to RO, the bits can be changed back to R/W only by a hardware reset.  
5
Lock Scratch. This bit controls bits 7 and 6 of this register. Once this bit is set to 1 by software, it can be cleared to 0 only  
by a hardware reset.  
0: Bits 7 and 6 of this register are R/W bits. (Default)  
1: Bits 7 and 6 of this register are RO bits.  
4:2  
1
Reserved.  
SW Reset. Read always returns 0.  
0: Ignored. (Default)  
1: Resets all devices that are reset by MR (with the exception of the lock bits) and the registers of the SWC.  
0
Global Device Enable. This bit controls the function enable of all the logical devices in the SIO module, except the SWC  
and the RTC. It allows them to be disabled simultaneously by writing to a single bit.  
0: All logical devices in the SIO module are disabled, except the SWC and the RTC.  
1: Each logical device is enabled according to its Activate register at Index 30h. (Default)  
Index 22h  
SIO Configuration 2 Register - SIOCF2 (R/W)  
Reset Value: 02h  
Note: This register is reset only when VPP is first applied.  
7
6:4  
3:2  
1
Reserved.  
General Purpose Scratch. Battery-backed.  
Reserved.  
Reserved.  
0
Reserved. (RO)  
Index 27h  
SIO Revision ID Register - SRID (RO)  
Reset Value: 01h  
7:0  
SIO Revision ID. (RO) This RO register contains the identity number of the chip revision. SRID is incremented on each revi-  
sion.  
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5.4.2.1 LDN 00h - Real-Time Clock  
5.4.2  
Logical Device Control and  
Configuration  
Table 5-6 lists the registers which are relevant to configura-  
tion of the Real-Time Clock (RTC). Only the last registers  
(F0h-F3h) are described here (Table 5-7). See Table 5-3  
"Standard Configuration Registers" on page 93 for descrip-  
tions of the other registers.  
As described in Section 5.3.2 "Banked Logical Device Reg-  
isters" on page 90, each functional block is associated with  
a Logical Device Number (LDN). This section provides the  
register descriptions for each LDN.  
The register descriptions in this subsection use the follow-  
ing abbreviations for Type:  
• R/W  
• R  
= Read/Write  
= Read from a specific address returns the  
value of a specific register. Write to the  
same address is to a different register.  
= Write  
• W  
• RO  
= Read Only  
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit  
clears it to 0. Writing 0 has no effect.  
Table 5-6. Relevant RTC Configuration Registers  
Reset  
Value  
Index  
Type  
Configuration Register or Action  
1
30h  
R/W  
00h  
Activate. When bit 0 is cleared, the registers of this logical device are not accessible.  
Standard Base Address MSB register. Bits [7:3] (for A[15:11]) are RO, 00000b.  
Standard Base Address LSB register. Bit 0 (for A0) is RO, 0b.  
Extended Base Address MSB register. Bits [7:3] (for A[15:11]) are RO, 00000b.  
Extended Base Address LSB register. Bit 0 (for A0) is RO, 0b.  
Interrupt Number.  
60h  
61h  
62h  
63h  
70h  
71h  
74h  
75h  
F0h  
F1h  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
RO  
00h  
70h  
00h  
72h  
08h  
00h  
04h  
04h  
00h  
00h  
Interrupt Type. Bit 1 is R/W; other bits are RO.  
Report no DMA assignment.  
RO  
Report no DMA assignment.  
R/W  
R/W  
RAM Lock register (RLR).  
Date of Month Alarm Offset register (DOMAO). Sets index of Date of Month Alarm  
register in the standard base address.  
F2h  
F3h  
R/W  
R/W  
Month Alarm Offset register (MONAO). Sets index of Month Alarm register in the  
standard base address.  
00h  
00h  
Century Offset register (CENO). Sets index of Century register in the standard base  
address.  
1. The logical device registers are maintained, and all RTC mechanisms are functional.  
96  
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Table 5-7. RTC Configuration Registers  
Bit  
Description  
Index F0h  
RAM Lock Register - RLR (R/W)  
When any non-reserved bit in this register is set to 1, it can be cleared only by hardware reset.  
7
6
5
4
3
Block Standard RAM.  
0: No effect on Standard RAM access. (Default)  
1: Read and write to locations 38h-3Fh of the Standard RAM are blocked, writes ignored, and reads return FFh.  
Block RAM Write.  
0: No effect on RAM access. (Default)  
1: Writes to RAM (Standard and Extended) are ignored.  
Block Extended RAM Write. This bit controls writes to bytes 00h-1Fh of the Extended RAM.  
0: No effect on the Extended RAM access. (Default)  
1: Writes to bytes 00h-1Fh of the Extended RAM are ignored.  
Block Extended RAM Read. This bit controls read from bytes 00h-1Fh of the Extended RAM.  
0: No effect on Extended RAM access. (Default)  
1: Reads to bytes 00h-1Fh of the Extended RAM are ignored.  
Block Extended RAM. This bit controls access to the Extended RAM 128 bytes.  
0: No effect on Extended RAM access. (Default)  
1: Read and write to the Extended RAM are blocked: writes are ignored and reads return FFh.  
Reserved.  
2:0  
Index F1h  
Date Of Month Alarm Register Offset Register - DOMAO (R/W)  
7
Reserved.  
6:0  
Date of Month Alarm Register Offset Value.  
Index F2h  
Month Alarm Register Offset Register - MANAO (R/W)  
7
Reserved.  
6:0  
Month Alarm Register Offset Value.  
Index F3h  
Century Register Offset Register - CENO (R/W)  
7
Reserved.  
6:0  
Century Register Offset Value.  
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5.4.2.2 LDN 01h - System Wakeup Control  
described earlier in Table 5-3 "Standard Configuration Reg-  
isters" on page 93.  
Table 5-8 lists registers that are relevant to the configura-  
tion of System Wakeup Control (SWC). These registers are  
Table 5-8. Relevant SWC Registers  
Reset  
Value  
Index  
Type  
Configuration Register or Action  
1
30h  
R/W  
00h  
Activate. When bit 0 is cleared, the registers of this logical device are not accessible.  
Base Address MSB register.  
60h  
61h  
70h  
71h  
74h  
75h  
R/W  
R/W  
R/W  
R/W  
RO  
00h  
00h  
00h  
03h  
04h  
04h  
Base Address LSB register. Bits [3:0] (for A[3:0]) are RO, 0000b.  
Interrupt Number. (For routing the internal PWUREQ signal.)  
Interrupt Type. Bit 1 is R/W. Other bits are RO.  
Report no DMA assignment.  
RO  
Report no DMA assignment.  
1. The logical device registers are maintained, and all wakeup detection mechanisms are functional.  
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5.4.2.3 LDN 02h - Infrared Communication Port or  
Serial Port 3  
Only the last register (F0h) is described here (Table 5-10).  
See Table 5-3 "Standard Configuration Registers" on page  
93 for descriptions of the other registers listed.  
Table 5-9 lists the configuration registers which affect the  
Infrared Communication Port or Serial Port 3 (IRCP/SP3).  
Table 5-9. Relevant IRCP/SP3 Registers  
Reset  
Value  
Index  
Type  
Configuration Register or Action  
30h  
60h  
61h  
70h  
71h  
74h  
75h  
F0h  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Activate. See also bit 0 of the SIOCF1 register.  
Base Address MSB register. Bits [7:3] (for A[15:11]) are RO, 00000b.  
Base Address LSB register. Bit [2:0] (for A[2:0]) are RO, 000b.  
Interrupt Number.  
00h  
03h  
E8h  
00h  
03h  
04h  
04h  
02h  
Interrupt Type. Bit 1 is R/W; other bits are RO.  
DMA Channel Select 0 (RX_DMA).  
DMA Channel Select 1 (TX_DMA).  
Infrared Communication Port/Serial Port 3 Configuration register.  
Table 5-10. IRCP/SP3 Configuration Register  
Bit  
Description  
Index F0h  
Infrared Communication Port/Serial Port 3 Configuration Register (R/W)  
Reset Value: 02h  
7
Bank Select Enable. Enables bank switching.  
0: All attempts to access the extended registers are ignored. (Default)  
1: Enables bank switching.  
6:3  
2
Reserved.  
Busy Indicator. (RO) This bit can be used by power management software to decide when to power-down the device.  
0: No transfer in progress. (Default)  
1: Transfer in progress.  
1
0
Power Mode Control. When the logical device is active in:  
0: Low power mode - Clock disabled. The output signals are set to their default states. Registers are maintained. (Unlike  
Active bit in Index 30h that also prevents access to device registers.)  
1: Normal power mode - Clock enabled. The device is functional when the logical device is active. (Default)  
TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE. One excep-  
tion is the IRTX/SOUT3 pin, which is driven to 0 when the Infrared Communication Port or Serial Port 3 is inactive and is not  
affected by this bit.  
0: Disabled. (Default)  
1: Enabled (when the device is inactive).  
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5.4.2.4 LDN 03h and 08h - Serial Ports 1 and 2  
affect Serial Ports 1 and 2. Only the last register (F0h) is  
described here (Table 5-12). See Table 5-3 "Standard Con-  
figuration Registers" on page 93 for descriptions of the oth-  
ers.  
Serial Ports 1 and 2 are identical, except for their reset val-  
ues.  
Serial Port 1 is designated as LDN 03h and Serial Port 2 as  
LDN 08h. Table 5-11 lists the configuration registers which  
Table 5-11. Relevant Serial Ports 1 and 2 Registers  
Reset Value  
Index  
Type  
Configuration Register or Action  
Port 1  
Port 2  
30h  
60h  
61h  
70h  
71h  
74h  
75h  
F0h  
R/W  
R/W  
R/W  
R/W  
R/W  
RO  
Activate. See also bit 0 of the SIOCF1 register.  
Base Address MSB register. Bits [7:3] (for A[15:11]) are RO, 00000b.  
Base Address LSB register. Bit [2:0] (for A[2:0]) are RO, 000b.  
Interrupt Number.  
00h  
03h  
F8h  
04h  
03h  
04h  
04h  
02h  
00h  
02h  
F8h  
03h  
03h  
04h  
04h  
02h  
Interrupt Type. Bit 1 is R/W; other bits are RO.  
Report no DMA assignment.  
RO  
Report no DMA assignment.  
R/W  
Serial Ports 1 and 2 Configuration register.  
Table 5-12. Serial Ports 1 and 2 Configuration Register  
Bit  
Description  
Index F0h  
Serial Ports 1 and 2 Configuration Register (R/W)  
Reset Value: 02h  
7
Bank Select Enable. Enables bank switching for Serial Ports 1 and 2.  
0: Disabled. (Default)  
1: Enabled.  
6:3  
2
Reserved.  
Busy Indicator. (RO) This bit can be used by power management software to decide when to power-down Serial Ports 1  
and 2 logical devices.  
0: No transfer in progress. (Default)  
1: Transfer in progress.  
1
0
Power Mode Control. When the logical device is active in:  
0: Low power mode - Serial Ports 1 and 2 Clock disabled. The output signals are set to their default states. Registers are  
maintained. (Unlike Active bit in Index 30h that also prevents access to Serial Ports 1 or 2 registers.)  
1: Normal power mode - Serial Ports 1 and 2 clock enabled. Serial Ports 1 and 2 are functional when the respective logical  
devices are active. (Default)  
TRI-STATE Control. This bit controls the TRI-STATE status of the device output pins when it is inactive (disabled).  
0: Disabled. (Default)  
1: Enabled when device inactive.  
100  
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5.4.2.5 LDN 05h and 06h - ACCESS.bus Ports 1 and 2  
ACB1 is designated as LDN 05h and ACB2 as LDN 06h.  
Table 5-13 lists the configuration registers which affect the  
ACCESS.bus ports. Only the last register (F0h) is  
described here (Table 5-14). See Table 5-3 "Standard Con-  
figuration Registers" on page 93 for descriptions of the oth-  
ers.  
ACCESS.bus ports 1 and 2 (ACB1 and ACB2) are identi-  
cal. Each ACB is a two-wire synchronous serial interface  
compatible with the ACCESS.bus physical layer. ACB1 and  
ACB2 use a 24 MHz internal clock. Six runtime registers for  
each ACCESS.bus are described in Section 5.7  
"ACCESS.bus Interface" on page 119.  
Table 5-13. Relevant ACB1 and ACB2 Registers  
Reset  
Value  
Index  
Type  
Configuration Register or Action  
30h  
60h  
61h  
70h  
71h  
74h  
75h  
F0h  
R/W  
R/W  
R/W  
R/W  
R/W  
RO  
Activate. See also bit 0 of the SIOCF1 register  
Base Address MSB register.  
00h  
00h  
00h  
00h  
03h  
04h  
04h  
00h  
Base Address LSB register. Bits [2:0] (for A[2:0]) are RO, 000b.  
Interrupt Number.  
Interrupt Type. Bit 1 is R/W. Other bits are RO.  
Report no DMA assignment.  
RO  
Report no DMA assignment.  
R/W  
ACB1 and ACB2 Configuration register.  
Table 5-14. ACB1 and ACB2 Configuration Register  
Bit  
Description  
Index F0h  
ACB1 and ACB2 Configuration Register (R/W)  
This register is reset by hardware to 00h.  
7:3  
2
Reserved.  
Internal Pull-Up Enable.  
0: No internal pull-up resistors on AB1C/AB2C and AB1D/AB2D. (Default)  
1: Internal pull-up resistors on AB1C/AB2C and AB1D/AB2D.  
1:0  
Reserved.  
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5.4.2.6 LDN 07h - Parallel Port  
• A group of four registers, used only in the Extended ECP  
mode, accessed by a second level offset.  
The Parallel Port supports all IEEE 1284 standard commu-  
nication modes: Compatibility (known also as Standard or  
SPP), Bidirectional (known also as PS/2), FIFO, EPP  
(known also as Mode 4) and ECP (with an optional  
Extended ECP mode).  
The desired mode is selected by the ECR runtime register  
(Offset 402h). The selected mode determines which runt-  
ime registers are used and which address bits are used for  
the base address. (See Section 5.8.1 on page 127 for fur-  
ther details regarding the runtime registers.)  
The Parallel Port includes two groups of runtime registers,  
as follows:  
Table 5-15 lists the configuration registers which affect the  
Parallel Port. Only the last register (F0h) is described here  
(Table 5-16). See Table 5-3 "Standard Configuration Regis-  
ters" on page 93 for descriptions of the others.  
• A group of 21 registers at first level offset, sharing 14  
entries. Three of these registers (at Offset 403h, 404h,  
and 405h) are used only in the Extended ECP mode.  
Table 5-15. Relevant Parallel Port Registers  
Reset  
Value  
Index  
Type  
Configuration Register or Action  
30h  
60h  
R/W  
R/W  
Activate. See also bit 0 of the SIOCF1 register.  
00h  
02h  
Base Address MSB register. Bits [7:3] (for A[15:11]) are RO, 00000b. Bit 2 (for A10)  
should be 0b.  
61h  
R/W  
Base Address LSB register. Bits 1 and 0 (A1 and A0) are RO, 00b. For ECP Mode 4  
78h  
(EPP) or when using the Extended registers, bit 2 (A2) should also be 0b.  
70h  
71h  
R/W  
R/W  
Interrupt Number.  
Interrupt Type.  
Bits [7:2] are RO.  
Bit 1 is R/W.  
07h  
02h  
Bit 0 is RO. It reflects the interrupt type dictated by the Parallel Port operation mode.  
This bit is set to 1 (level interrupt) in Extended Mode and cleared (edge interrupt) in all  
other modes.  
74h  
75h  
F0h  
R/W  
RO  
DMA Channel Select.  
04h  
04h  
F2h  
Report no second DMA assignment.  
Parallel Port Configuration register. (See Table 5-16.)  
R/W  
Table 5-16. Parallel Port Configuration Register  
Bit  
Description  
Index F0h  
Parallel Port Configuration Register (R/W)  
Reset Value: F2h  
This register is reset by hardware to F2h.  
7:5  
4
Reserved. Must be 11.  
Extended Register Access.  
0: Registers at base (address)+403h, base+404h and base+405h are not accessible (reads and writes are ignored).  
1: Registers at base (address)+403h, base+404h and base+405h are accessible. This option supports run-time configura-  
tion within the Parallel Port address space.  
3:2  
1
Reserved.  
Power Mode Control. When the logical device is active:  
0: Parallel port clock disabled. ECP modes and EPP timeout are not functional when the logical device is active. Registers  
are maintained.  
1: Parallel port clock enabled. All operation modes are functional when the logical device is active. (Default)  
0
TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.  
0: Disable. (Default)  
1: Enable.  
102  
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5.5  
Real-Time Clock (RTC)  
The RTC provides timekeeping and calendar management  
capabilities. The RTC uses a 32.768 KHz signal as the  
basic clock for timekeeping. It also includes 242 bytes of  
battery-backed RAM for general-purpose use.  
These locations may be reassigned, in compliance with  
Plug and Play requirements.  
5.5.2  
RTC Clock Generation  
The RTC provides the following functions:  
• Accurate timekeeping and calendar management  
• Alarm at a predetermined time and/or date  
• Three programmable interrupt sources  
The RTC uses a 32.768 KHz clock signal as the basic  
clock for timekeeping. The 32.768 KHz clock can be sup-  
plied by the internal oscillator circuit, or by an external  
oscillator (see Section 5.5.2.2 "External Oscillator" on page  
104).  
5.5.2.1 Internal Oscillator  
• Valid timekeeping during power-down, by utilizing  
external battery backup  
The internal oscillator employs an external crystal con-  
nected to the on-chip amplifier. The on-chip amplifier is  
accessible on the X32I input and X32O output. See Figure  
5-5 for the recommended external circuit and Table 5-17 for  
a listing of the circuit components. The oscillator may be  
disabled in certain conditions. See Section 5.5.2.8 "Oscilla-  
tor Activity" on page 107 for more details.  
• 242 bytes of battery-backed RAM  
• RAM lock schemes to protect its content  
• Internal oscillator circuit (the crystal itself is off-chip), or  
external clock supply for the 32.768 KHz clock  
• A century counter  
• PnP support:  
— Relocatable Index and Data registers  
— Module access enable/disable option  
— Host interrupt enable/disable option  
To other  
modules  
V
BAT  
Internal  
External  
C
F
• Additional low-power features such as:  
X32I  
X32O  
— Automatic switching from battery to V  
— Internal power monitoring on the VRT bit  
— Oscillator disabling to save battery during storage  
SB  
R
1
R
2
• Software compatible with the DS1287 and MC146818  
B
1
C
C
Y
1
2
Battery  
C = 0.1 μF  
F
5.5.1  
Bus Interface  
The RTC function is initially mapped to the default SuperI/O  
locations at Indexes 70h to 73h (two Index/Data pairs).  
Figure 5-5. Recommended Oscillator External  
Circuitry  
Table 5-17. Crystal Oscillator Circuit Components  
Component  
Parameters  
Values  
Tolerance  
Crystal  
Resonance Frequency  
Type  
32.768 KHz Parallel mode  
User-defined  
N-cut or XY-bar  
40 KΩ  
Serial Resistance  
Quality Factor, Q  
Shunt Capacitance  
Load Capacitance, CL  
Max  
Min  
35000  
2 pF  
Max  
9-13 pF  
Temperature Coefficient  
Resistance  
User-defined  
Resistor R1  
Resistor R2  
Capacitor C1  
Capacitor C2  
20 MΩ  
5%  
5%  
5%  
5%  
Resistance  
Capacitance  
Capacitance  
120 KΩ  
3 to 10 pF (Note)  
3 to 10 pF (Note)  
Note: When voltage is applied to the oscillator it may not start to oscillate immediately due to the balanced external circuit. In general  
this is not a problem because the oscillator runs all the time (whether system is on or off). In systems where this is not the case, C1 and  
C2 should be different by 50% to assure an unbalanced circuit.  
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External Elements  
Choose C and C capacitors (see Figure 5-5 on page  
The divider chain can be activated by setting normal opera-  
tional mode (bits [6:4] of CRA = 01x or 100). The first  
update occurs 500 ms after divider chain activation.  
1
2
103) to match the crystal’s load capacitance. The load  
capacitance C “seen” by crystal Y is comprised of C in  
L
1
Bits [3:0] of CRA select one the of fifteen taps from the  
divider chain to be used as a periodic interrupt. The peri-  
odic flag becomes active after half of the programmed  
period has elapsed, following divider chain activation.  
series with C and in parallel with the parasitic capacitance  
2
of the circuit. The parasitic capacitance is caused by the  
chip package, board layout and socket (if any), and can  
vary from 0 to 10 pF. The rule of thumb in choosing these  
capacitors is:  
See Table 5-20 on page 109 for more details.  
C = (C * C ) / (C + C ) + C  
L
1
2
1
2
PARASITIC  
Example:  
V
BAT  
To other  
modules  
Crystal C = 10 pF, C  
= 8.2 pF  
L
PARASITIC  
C = 3.6 pF, C = 3.6 pF  
1
2
Internal  
C
F
External  
Oscillator Startup  
The oscillator starts to generate 32.768 KHz pulses to the  
RTC after about 100 ms from when V is higher than  
X32O  
NC  
CLKIN  
(X32I)  
BAT  
R
R
2
1
V
(2.4V) or V is higher than V  
(3.0V). The  
BATMIN  
SB  
SBMIN  
oscillation amplitude on the X32O pin stabilizes to its final  
value (approximately 0.4V peak-to-peak around 0.7V DC)  
in about 1 s.  
3.3V square wave  
OUT  
POWER  
R = 30 KΩ  
1
32.768 KHz  
Clock Generator  
C
can be trimmed to achieve precisely 32.768 KHz. To  
1
C
F
B
1
R = 30 KΩ  
2
achieve a high time accuracy, use crystal and capacitors  
with low tolerance and temperature coefficients.  
Battery  
C = 0.1 μF  
F
5.5.2.2 External Oscillator  
Figure 5-6. External Oscillator Connections  
32.768 KHz can be applied from an external clock source,  
as shown in Figure 5-6.  
Connections  
Divider Chain  
3
2
Connect the clock to the X32I ball, leaving the oscillator  
output, X32O, unconnected.  
1
2
2
2
13 14 15  
1 Hz  
2
2
2
Signal Parameters  
Reset  
The signal levels should conform to the voltage level  
requirements for X32I, of square or sine wave of 0.0V to  
DV2 DV1 DV0  
V
amplitude. The signal should have a duty cycle of  
CORE  
4
6
5
approximately 50%. It should be sourced from a battery-  
backed source in order to oscillate during power-down.  
This assures that the RTC delivers updated time/calendar  
information.  
CRA Register  
32.768 KHz  
Oscillator  
Enable  
To other  
modules  
5.5.2.3 Timing Generation  
The timing generation function divides the 32.768 KHz  
clock by 2 to derive a 1 Hz signal, which serves as the  
X32I  
X32O  
15  
input for the seconds counter. This is performed by a  
divider chain composed of 15 divide-by-two latches, as  
shown in Figure 5-7.  
Figure 5-7. Divider Chain Control  
Bits [6:4] (DV[2:0]) of the CRA Register control the follow-  
ing functions:  
• Normal operation of the divider chain (counting).  
• Divider chain reset to 0.  
• Oscillator activity when only V  
power is present  
BAT  
(backup state).  
104  
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5.5.2.4 Timekeeping  
Data Format  
Method 2  
1) Access the RTC registers after detection of an Update  
Ended interrupt. This implies that an update has just  
been completed and 999 ms remain until the next  
update.  
Time is kept in BCD or binary format, as determined by bit  
2 (DM) of Control Register B (CRB), and in either 12 or 24-  
hour format, as determined by bit 1 of this register.  
2) To detect an Update Ended interrupt, you may either:  
Note: When changing the above formats, re-initialize all  
— Poll bit 4 of CRC.  
— Use the following interrupt routine:  
– Set bit 4 of CRB.  
the time registers.  
Daylight Saving  
– Wait for an interrupt from interrupt pin.  
– Clear the IRQF flag of CRC before exiting the  
interrupt routine.  
Daylight saving time exceptions are handled automatically,  
as described in Table 5-20 on page 109.  
Leap Years  
Method 3  
Leap year exceptions are handled automatically by the  
internal calendar function. Every four years, February is  
extended to 29 days.  
Poll bit 7 of CRA. The update occurs 244 μs after this bit  
goes high. Therefore, if a 0 is read, the time registers  
remain stable for at least 244 μs.  
Updating  
Method 4  
The time and calendar registers are updated once per sec-  
ond regardless of bit 7 (SET) of CRB. Since the time and  
calendar registers are updated serially, unpredictable  
results may occur if they are accessed during the update.  
Therefore, you must ensure that reading or writing to the  
time storage locations does not coincide with a system  
update of these locations. There are several methods to  
avoid this contention.  
Use a periodic interrupt routine to determine if an update  
cycle is in progress, as follows:  
1) Set the periodic interrupt to the desired period.  
2) Set bit 6 of CRB to enable the interrupt from periodic  
interrupt.  
3) Wait for the periodic interrupt appearance. This indi-  
cates that the period represented by the following  
expression remains until another update occurs:  
[(Period of periodic interrupt / 2) + 244 μs]  
Method 1  
1) Set bit 7 of CRB to 1. This takes a “snapshot” of the  
internal time registers and loads them into the user  
copy registers. The user copy registers are seen when  
accessing the RTC from outside, and are part of the  
double buffering mechanism. You may keep this bit set  
for up to 1 second, since the time/calendar chain con-  
tinue to be updated once per second.  
5.5.2.5 Alarms  
The timekeeping function can be set to generate an alarm  
when the current time reaches a stored alarm time. After  
each RTC time update (every 1 second), the seconds, min-  
utes, hours, date of month and month counters are com-  
pared with their corresponding registers in the alarm  
settings. If equal, bit 5 of CRC is set. If the Alarm Interrupt  
Enable bit was previously set (CRB bit 5), interrupt request  
pin is also active.  
2) Read or write the required registers (since bit 1 is set,  
you are accessing the user copy registers). If you per-  
form a read operation, the information you read is cor-  
rect from the time when bit 1 was set. If you perform a  
write operation, you write only to the user copy regis-  
ters.  
Any alarm register may be set to “Unconditional Match” by  
setting bits [7:6] to 11. This combination, not used by any  
BCD or binary time codes, results in a periodic alarm. The  
rate of this periodic alarm is determined by the registers  
that were set to “Unconditional Match”.  
3) Reset bit 1 to 0. During the transition, the user copy  
registers update the internal registers, using the dou-  
ble buffering mechanism to ensure that the update is  
performed between two time updates. This mecha-  
nism enables new time parameters to be loaded in the  
RTC.  
For example, if all but the seconds and minutes alarm reg-  
isters are set to “Unconditional Match”, an interrupt is gen-  
erated every hour at the specified minute and second. If all  
but the seconds, minutes and hours alarm registers are set  
to “Unconditional Match”, an interrupt is generated every  
day at the specified hour, minute and second.  
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5.5.2.6 Power Supply  
The RTC is supplied from one of two power supplies, V  
SB  
or V , according to their levels. An internal voltage com-  
parator delivers the control signals to a pair of switches.  
The device is supplied from two supply voltages, as shown  
in Figure 5-8:  
BAT  
Battery backup voltage V  
maintains the correct time and  
BAT  
• System standby power supply voltage, V  
SB  
saves the CMOS memory when the V voltage is absent,  
SB  
due to power failure or disconnection of the external AC/DC  
• Backup voltage, from low capacity Lithium battery  
input power supply or V main battery.  
SB  
A standby voltage, V , from the external AC/DC power  
SB  
To assure that the module uses power from V and not  
SB  
supply powers the RTC under normal conditions.  
from V , the V voltage should be maintained above its  
BAT  
SB  
Figure 5-9 represents a typical battery configuration. No  
external diode is required to meet the UL standard, due to  
minimum, as detailed in Section 9.0 "Electrical Specifica-  
tions" on page 351.  
the internal switch and internal serial resistor R  
.
UL  
The actual voltage point where the module switches from  
V
to V is lower than the minimum workable battery  
BAT  
SB  
voltage, but high enough to guarantee the correct function-  
ality of the oscillator and the CMOS RAM.  
External AC Power  
ACPI Controller  
Figure 5-10 shows typical battery current consumption dur-  
ing battery-backed operation, and Figure 5-11 during nor-  
mal operation.  
Power  
Supply  
VDIGITAL  
VDIGITAL Sense  
VDIGITAL  
ONCTL#  
VSB  
I
(μA)  
ONCTL#  
VSB  
PC0  
VSB  
BAT  
VSB  
RTC  
10.0  
7.5  
VBAT  
5.0  
VBAT  
VBAT  
Backup  
Battery  
2.5  
V
(V)  
BAT  
2.4 3.0 3.6  
Figure 5-8. Power Supply Connections  
Figure 5-10. Typical Battery Current: Battery  
Backed Power Mode @ T = 25°C  
C
V
V
SB  
V
0.1 μF  
SB  
RTC  
C
C
F
I
(μA)  
V
BAT  
SBL  
SBL  
V
PP  
V
REF  
F
0.1 μF  
V
BAT  
BT  
1
0.75  
0.50  
0.25  
R
C
0.1 μF  
UL  
F
V
SB  
(V)  
Note: Place a 0.1 μF capacitor on each V , V  
SB  
SBL  
3.0 3.3 3.6  
power supply pin as close as possible to the  
pin, and also on V  
Note: Battery voltage in this test is 3.0V.  
.
BAT  
Figure 5-11. Typical Battery Current: Normal  
Operation Mode  
Figure 5-9. Typical Battery Configuration  
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5.5.2.7 System Power States  
Power-Up Detection  
When system power is restored after a power failure or  
The system power state may be No Power, Power On,  
Power Off or Power Failure. Table 5-18 indicates the power-  
source combinations for each state. No other power-source  
combinations are valid.  
power off state (V = 0), the lockout condition continues  
SB  
for a delay of 62 ms (minimum) to 125 ms (maximum) after  
the RTC switches from battery to system power.  
In addition, the power sources and distribution for the entire  
system are illustrated in Figure 5-8 on page 106.  
The lockout condition is switched off immediately in the fol-  
lowing situations:  
• If the Divider Chain Control bits, DV[2:0], (CRA bits [6:4])  
specify a normal operation mode (01x or 100), all input  
signals are enabled immediately upon detection of  
Table 5-18. System Power States  
V
V
V
BAT  
Power State  
system voltage above V  
.
DIGITAL  
SB  
SBON  
• When battery voltage is below V  
and HMR is 1,  
−
−
−
+
−
−
+
+
−
No Power  
BATDCT  
all input signals are enabled immediately upon detection  
of system voltage above V . This also initializes  
+
Power Failure  
Power Off  
Power On  
SBON  
+ or -  
+ or -  
registers at offsets 00h through 0Dh.  
• If bit 7 (VRT) of CRD is 0, all input signals are enabled  
immediately upon detection of system voltage above  
V
.
SBON  
No Power  
5.5.2.8 Oscillator Activity  
This state exists when no external or battery power is con-  
nected to the device. This condition does not occur once a  
backup battery has been connected, except in the case of  
a malfunction.  
The RTC oscillator is active if:  
• V power supply is higher than V  
, independent of  
SB  
SBON  
the battery voltage, V  
BAT  
Power On  
-or-  
This is the normal state when the system is active. This  
state may be initiated by various events in addition to the  
normal physical switching on of the system. In this state,  
the system power supply is powered by external AC power  
• V  
power supply is higher than V  
is present or not.  
, regardless if  
BATMIN  
BAT  
V
SB  
The RTC oscillator is disabled if:  
• During power-down (V only), the battery voltage  
and produces V  
and V . The system and the part  
DIGITAL  
SB  
BAT  
are powered by V  
with the exception of the RTC log-  
DIGITAL,  
drops below V  
may be disabled and its functionality cannot be guaran-  
teed.  
. When this occurs, the oscillator  
BATMIN  
ical device, which is powered by V  
SB.  
Power Off (Suspended)  
This is the normal state when the system has been  
switched off and is not required to be active, but is still con-  
nected to a live external AC input power source. This state  
may be initiated directly or by software. The system is pow-  
ered down. The RTC logical device remains active, pow-  
-or-  
• Software wrote 00x to DV[2:0] bits of the CRA Register  
and V is removed. This disables the oscillator and  
decreases the power consumption from the battery  
connected to V . When disabling the oscillator, the  
CMOS RAM is not affected as long as the battery is  
present at a correct voltage level.  
SB  
BAT  
ered by V  
.
SB  
Power Failure  
This state occurs when the external power source to the  
system stops supplying power, due to disconnection or  
power failure on the external AC input power source. The  
RTC continues to maintain timekeeping and RAM data  
If the RTC oscillator becomes inactive, the following fea-  
tures are dysfunctional/disabled:  
• Timekeeping.  
• Periodic interrupt.  
• Alarm.  
under battery power (V ), unless the oscillator stop bit  
BAT  
was set in the RTC. In this case, the oscillator stops func-  
tioning if the system goes to battery power, and timekeep-  
ing data becomes invalid.  
System Bus Lockout  
During power on or power off, spurious bus transactions  
from the host may occur. To protect the RTC internal regis-  
ters from corruption, all inputs are automatically locked out.  
The lockout condition is asserted when V is lower than  
SB  
V
.
SBON  
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5.5.2.9 Interrupt Handling  
5.5.2.10 Battery-Backed RAMs and Registers  
The RTC has a single Interrupt Request line which handles  
the following three interrupt conditions:  
The RTC has two battery-backed RAMs and 17 registers,  
used by the logical units themselves. Battery-backup power  
enables information retention during system power down.  
• Periodic interrupt.  
• Alarm interrupt.  
The RAMs are:  
• Standard RAM  
• Extended RAM  
• Update end interrupt.  
The interrupts are generated if the respective enable bits in  
the CRB register are set prior to an interrupt event occur-  
rence. Reading the CRC register clears all interrupt flags.  
Thus, when multiple interrupts are enabled, the interrupt  
service routine should first read and store the CRC regis-  
ter, and then deal with all pending interrupts by referring to  
this stored status.  
The memory maps and register content of the RAMs is  
provided in Section 5.5.4 "RTC General-Purpose RAM  
Map" on page 113.  
The first 14 bytes and 3 programmable bytes of the Stan-  
dard RAM are overlaid by time, alarm data and control reg-  
isters. The remaining 111 bytes are general-purpose  
memory.  
If an interrupt is not serviced before a second occurrence  
of the same interrupt condition, the second interrupt event  
is lost. Figure 5-12 illustrates the interrupt timing in the  
RTC.  
Registers with reserved bits should be written using the  
read-modify-write method.  
All register locations within the device are accessed by the  
RTC Index and Data registers (at base address and base  
address+1). The Index register points to the register loca-  
tion being accessed, and the Data register contains the  
data to be transferred to or from the location. An additional  
128 bytes of battery-backed RAM (also called Extended  
RAM) may be accessed via a second pair of Index and  
Data registers.  
Bit 7  
of CRA  
A
244 μs  
Bit 4  
of CRC  
P
P/2  
P/2  
Bit 6  
Access to the two RAMs may be locked. For details see  
Table 5-7 on page 97.  
of CRC  
B
C
30.5 μs  
Bit 5  
of CRC  
Flags (and IRQ) are reset at the conclusion of CRC read or by  
reset.  
A = Update In Progress bit high before update occurs = 244 μs  
B = Periodic interrupt to update = Period (periodic int) / 2 +  
244 μs  
C =Update to Alarm Interrupt = 30.5 μs  
P = Period is programmed by RS[3:0] of CRA  
Figure 5-12. Interrupt/Status Timing  
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5.5.3  
RTC Registers  
dures, read about bit 7 (VRT) of the CRD Register.  
The RTC registers can be accessed (see Section 5.4.2.1  
"LDN 00h - Real-Time Clock" on page 96) at any time dur-  
ing normal operation mode (i.e.,when V is within the rec-  
ommended operation range). This access is disabled  
during battery-backed operation. The write operation to  
these registers is also disabled if bit 7 of the CRD Register  
is 0.  
This section describes the RTC Timing and Control Regis-  
ters that control basic RTC functionality.  
SB  
Table 5-19. RTC Register Map  
Reset  
Type  
Index  
00h  
01h  
02h  
03h  
04h  
05h  
06h  
07h  
08h  
09h  
Type  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Name  
SEC. Seconds Register  
SECA. Seconds Alarm Register  
MIN. Minutes Register  
MINA. Minutes Alarm Register  
HOR. Hours Register  
V
V
V
V
V
V
V
V
V
V
PUR  
PP  
PP  
PP  
PP  
PP  
PP  
PP  
PP  
PP  
PP  
PUR  
PUR  
PUR  
PUR  
PUR  
PUR  
PUR  
PUR  
PUR  
HORA. Hours Alarm Register  
DOW. Day Of Week Register  
DOM. Date Of Month Register  
MON. Month Register  
YER. Year Register  
0Ah  
0Bh  
0Ch  
0Dh  
R/W  
R/W  
RO  
CRA. RTC Control Register A  
CRB. RTC Control Register B  
CRC. RTC Control Register C  
CRD. RTC Control Register D  
Bit specific  
Bit specific  
Bit specific  
RO  
V
V
V
V
PUR  
PUR  
PUR  
PUR  
PP  
PP  
PP  
PP  
1
1
1
R/W  
R/W  
R/W  
DOMA. Date of Month Alarm Register  
MONA. Month Alarm Register  
CEN. Century Register  
Programmable  
Programmable  
Programmable  
1. Overlaid on RAM bytes in range 0Eh-7Fh. See Section 5.4.2.1 "LDN 00h - Real-Time Clock" on page 96.  
Table 5-20. RTC Registers  
Bit  
Description  
Index 00h  
Seconds Register - SEC (R/W)  
Reset Type: VPP PUR  
Reset Type: VPP PUR  
7:0  
Seconds Data. Values may be 00 to 59 in BCD format or 00 to 3B in binary format.  
Index 01h  
Seconds Alarm Register - SECA (R/W)  
7:0  
Seconds Alarm Data. Values may be 00 to 59 in BCD format or 00 to 3B in binary format.  
When bits 7 and 6 are both set to one (“11”), unconditional match is selected.  
Minutes Register - MIN (R/W)  
Index 02h  
Reset Type: VPP PUR  
7:0  
Minutes Data. Values can be 00 to 59 in BCD format, or 00 to 3B in binary format.  
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Table 5-20. RTC Registers (Continued)  
Bit  
Index 03h  
7:0  
Description  
Minutes Alarm Register - MINA (R/W)  
Reset Type: VPP PUR  
Minutes Alarm Data. Values can be 00 to 59 in BCD format, or 00 to 3B in binary format.  
When bits 7 and 6 are both set to 1, unconditional match is selected. See Section 5.5.2.5 "Alarms" on page 105 for more  
information about “unconditional” matches.  
Index 04h  
Hours Register - HOR (R/W)  
Reset Type: VPP PUR  
7:0  
Hours Data. For 12-hour mode, values can be 01 to 12 (AM) and 81 to 92 (PM) in BCD format, or 01 to 0C (AM) and 81 to  
8C (PM) in binary format. For 24-hour mode, values can be 0- to 23 in BCD format or 00 to 17 in binary format.  
Index 05h  
Hours Alarm Register - HORA (R/W)  
Reset Type: VPP PUR  
7:0  
Hours Alarm Data. For 12-hour mode, values may be 01 to 12 (AM) and 81 to 92 (PM) in BCD format or 01 to 0C (AM) and  
81 to 8C (PM) in Binary format. For 24-hour mode, values may be 0- to 23 in BCD format or 00 to 17 in Binary format.  
When bits 7 and 6 are both set to one (“11”), unconditional match is selected.  
Index 06h  
Day of Week Register - DOW (R/W)  
Reset Type: VPP PUR  
Reset Type: VPP PUR  
Reset Type: VPP PUR  
7:0  
Day Of Week Data. Values may be 01 to 07 in BCD format or 01 to 07 in binary format.  
Index 07h  
Date of Month Register - DOM (R/W)  
7:0  
Date Of Month Data. Values may be 01 to 31 in BCD format or 01 to 1F in binary format.  
Index 08h  
Month Register - MON (R/W)  
Width: Byte  
7-0  
Month Data. Values may be 01 to 12 in BCD format or 01 to 0C in binary format.  
Index 09h  
Year Register - YER (R/W)  
Reset Type: VPP PUR  
7:0  
Year Data. Values may be 00 to 99 in BCD format or 00 to 63 in binary format.  
Index 0Ah  
RTC Control Register A - CRA (R/W)  
Reset Type: Bit Specific  
This register controls test selection, among other functions. This register cannot be written before reading bit 7 of CRD.  
7
Update in Progress. (RO) This bit is not affected by reset. This bit reads 0 when bit 7 of the CRB Register is 1.  
0: Timing registers not updated within 244 μs.  
1: Timing registers updated within 244 μs.  
6:4  
3:0  
Divider Chain Control. These bits control the configuration of the divider chain for timing generation and register bank  
selection. See Table 5-21 on page 112. They are cleared to 000 as long as bit 7 of CRD is 0.  
Periodic Interrupt Rate Select. These bits select one of fifteen output taps from the clock divider chain to control the rate of  
the periodic interrupt. See Table 5-22 on page 112 and Figure 5-7 on page 104. They are cleared to 000 as long as bit 7 of  
CRD is 0.  
Index 0Bh  
RTC Control Register B - CRB (R/W)  
Set Mode. This bit is reset at VPP power-up reset only.  
0: Timing updates occur normally.  
Reset Type: Bit Specific  
7
1: User copy of time is “frozen”, allowing the time registers to be accessed whether or not an update occurs.  
6
5
4
Periodic Interrupt. Bits [3:0] of the CRA Register determine the rate at which this interrupt is generated. It is cleared to 0 on  
RTC reset (i.e., hardware or software reset) or when RTC is disable.  
0: Disable.  
1: Enable.  
Alarm Interrupt. This interrupt is generated immediately after a time update in which the seconds, minutes, hours, date and  
month time equal their respective alarm counterparts. It is cleared to 0 as long as bit 7 of the CRD Register is reads 0.  
0: Disable.  
1: Enable.  
Update Ended Interrupt. This interrupt is generated when an update occurs. It is cleared to 0 on RTC reset (i.e., hardware  
or software reset) or when the RTC is disable.  
0: Disable.  
1: Enable.  
110  
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Table 5-20. RTC Registers (Continued)  
Bit  
Description  
3
Reserved. This bit is defined as “Square Wave Enable” by the MC146818 and is not supported by the RTC. This bit is  
always read as 0.  
2
1
0
Data Mode. This bit is reset at VPP power-up reset only.  
0: Enable BCD format.  
1: Enable Binary format.  
Hour Mode. This bit is reset at VPP power-up reset only.  
0: Enable 12-hour format.  
1: Enable 24-hour format.  
Daylight Saving. This bit is reset at VPP power-up reset only.  
0: Disable.  
1: Enable:  
- In the spring, time advances from1:59:59 AM to 3:00:00 AM on the first Sunday in April.  
- In the fall, time returns from 1:59:59 AM to 1:00:00 AM on the last Sunday in October.  
Index 0Ch  
RTC Control Register C - CRC (RO)  
Reset Type: Bit Specific  
7
IRQ Flag. Mirrors the value on the interrupt output signal. When interrupt is active, IRQF is 1. To clear this bit (and deacti-  
vate the interrupt pin), read the CRC Register as the flag bits UF, AF and PF are cleared after reading this register.  
0: IRQ inactive.  
1: Logic equation is true: ((UIE and UF) or (AIE and AF) or (PIE and PF)).  
6
5
4
Periodic Interrupt Flag. Cleared to 0 on RTC reset (i.e., hardware or software reset) or the RTC disabled. In addition, this  
bit is cleared to 0 when this register is read.  
0: No transition occurred on the selected tap since the last read.  
1: Transition occurred on the selected tap of the divider chain.  
Alarm Interrupt Flag. Cleared to 0 as long as bit 7 of the CRD Register is reads 0. In addition, this bit is cleared to 0 when  
this register is read.  
0: No alarm detected since the last read.  
1: Alarm condition detected.  
Update Ended Interrupt Flag. Cleared to 0 on RTC reset (i.e., hardware or software reset) or the RTC disabled. In addi-  
tion, this bit is cleared to 0 when this register is read.  
0: No update occurred since the last read.  
1: Time registers updated.  
Reserved.  
3:0  
Index 0Dh  
RTC Control Register D - CRD (RO)  
Reset Type: VPP PUR  
7
Valid RAM and Time. This bit senses the voltage that feeds the RTC (VSB or VBAT) and indicates whether or not it was  
too low since the last time this bit was read. If it was too low, the RTC contents (time/calendar registers and CMOS RAM) is  
not valid.  
0: The voltage that feeds the RTC was too low.  
1: RTC contents (time/calendar registers and CMOS RAM) are valid.  
Reserved.  
6:0  
Index Programmable  
Date of Month Alarm Register - DOMA (R/W)  
Reset Type: VPP PUR  
Reset Type: VPP PUR  
Reset Type: VPP PUR  
7:0  
Date of Month Alarm Data. Values may be 01 to 31 in BCD format or 01 to 1F in Binary format.  
When bits 7 and 6 are both set to one (“11”), unconditional match is selected. (Default)  
Index Programmable  
Month Alarm Register - MONA (R/W)  
7:0  
Month Alarm Data. Values may be 01 to 12 in BCD format or 01 to 0C in Binary format.  
When bits 7 and 6 are both set to one (“11”), unconditional match is selected. (Default)  
Index Programmable  
Century Register - CEN (R/W)  
7:0 Century Data. Values may be 00 to 99 in BCD format or 00 to 63 in Binary format.  
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Table 5-21. Divider Chain Control / Test Selection  
Table 5-22. Periodic Interrupt Rate Encoding  
DV2  
DV1  
DV0  
Rate Select  
3 2 1 0  
Periodic Interrupt  
Rate (ms)  
Divider  
Chain Output  
CRA6  
CRA5 CRA4 Configuration  
0 0 0 0  
0 0 0 1  
0 0 1 0  
0 0 1 1  
0 1 0 0  
0 1 0 1  
0 1 1 0  
0 1 1 1  
1 0 0 0  
1 0 0 1  
1 0 1 0  
1 0 1 1  
1 1 0 0  
1 1 0 1  
1 1 1 0  
1 1 1 1  
No interrupts  
3.906250  
7.812500  
0.122070  
0.244141  
0.488281  
0.976562  
1.953125  
3.906250  
7.812500  
15.625000  
31.250000  
62.500000  
125.000000  
250.000000  
500.000000  
0
0
0
1
1
0
1
1
0
1
X
0
Oscillator Disabled  
Normal Operation  
Test  
7
8
1
2
X
X
3
Divider Chain Reset  
4
5
6
7
8
9
10  
11  
12  
13  
14  
Table 5-23. BCD and Binary Formats  
BCD Format  
Parameter  
Binary Format  
Seconds  
Minutes  
Hours  
00 to 59  
00 to 3B  
00 to 3B  
00 to 59  
12-hour mode:  
01 to 12 (AM)  
81 to 92 (PM)  
00 to 23  
12-hour mode:  
01 to 0C (AM)  
81 to 8C (PM)  
00 to 17  
24-hour mode:  
24-hour mode:  
01 to 07  
Day  
01 to 07 (Sunday = 01)  
01 to 31  
Date  
01 to 1F  
Month  
Year  
01 to 12 (January = 01)  
00 to 99  
01 to 0C  
00 to 63  
Century  
00 to 99  
00 to 63  
112  
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5.5.3.1 Usage Hints  
5.5.4  
RTC General-Purpose RAM Map  
1) Read bit 7 of CRD at each system power-up to vali-  
date the contents of the RTC registers and the CMOS  
RAM. When this bit is 0, the contents of these regis-  
ters and the CMOS RAM are questionable. This bit is  
reset when the backup battery voltage is too low. The  
voltage level at which this bit is reset is below the mini-  
mum recommended battery voltage, 2.4V. Although  
the RTC oscillator may function properly and the regis-  
ter contents may be correct at lower than 2.4V, this bit  
is reset since correct functionality cannot be guaran-  
teed. System BIOS may use a checksum method to  
revalidate the contents of the CMOS-RAM. The check-  
sum byte should be stored in the same CMOS RAM.  
Table 5-24. Standard RAM Map  
Index  
0Eh - 7Fh  
Description  
Battery-backed general-purpose 111-  
byte RAM.  
Table 5-25. Extended RAM Map  
Description  
Index  
00h - 7Fh  
Battery-backed general-purpose 128-  
byte RAM.  
2) Change the backup battery while normal operating  
power is present, and not in backup mode, to maintain  
valid time and register information. If a low leakage  
capacitor is connected to V , the battery may be  
BAT  
changed in backup mode.  
3) A rechargeable NiCd battery may be used instead of a  
non-rechargeable Lithium battery. This is a preferred  
solution for portable systems, where small size com-  
ponents is essential.  
4) A supercap capacitor may be used instead of the nor-  
mal Lithium battery. In a portable system usually the  
V
voltage is always present since the power man-  
SB  
agement stops the system before its voltage falls to  
low. The supercap capacitor in the range of 0.047-  
0.47 F should supply the power during the battery  
replacement.  
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5.6  
System Wakeup Control (SWC)  
The SWC wakes up the system by sending a power-up  
request to the ACPI controller in response to the following  
maskable system events:  
5.6.1.2 CEIR Address  
A CEIR transmission received on IRRX1 in a pre-selected  
standard (NEC, RCA or RC-5) is matched against a pro-  
grammable CEIR address. Detection of matching can be  
used as a wakeup event. The CEIR address detection  
operates independently of the serial port with the IR (which  
is powered down with the rest of the system).  
• Modem ring (RI2#)  
• Audio Codec event (SDATA_IN2)  
• Programmable Consumer Electronics IR (CEIR)  
address  
Whenever an IR signal is detected, the receiver immedi-  
ately enters the Active state. When this happens, the  
receiver keeps sampling the IR input signal and generates  
a bit string where a logic 1 indicates an idle condition and a  
logic 0 indicates the presence of IR energy. The received  
bit string is de-serialized and assembled into 8-bit charac-  
ters.  
Each system event that is monitored by the SWC is fed into  
a dedicated detector that decides when the event is active,  
according to predetermined (either fixed or programmable)  
criteria. A set of dedicated registers is used to determine  
the wakeup criteria, including the CEIR address.  
A Wakeup Events Status Register (WKSR) and a Wakeup  
Events Control Register (WKCR) hold a Status bit and  
Enable bit, respectively, for each possible wakeup event.  
The expected CEIR protocol of the received signal should  
be configured through bits [5:4] of the CEIR Wakeup Con-  
trol register (IRWCR) (see Table 5-30 on page 117).  
Upon detection of an active event, the corresponding Sta-  
tus bit is set to 1. If the event is enabled (the corresponding  
Enable bit is set to 1), a power-up request is issued to the  
ACPI controller. In addition, detection of an active wakeup  
event may be also routed to an arbitrary IRQ.  
The CEIR Wakeup Address register (IRWAD) holds the  
unique address to be compared with the address contained  
in the incoming CEIR message. If CEIR is enabled  
(IRWCR[0] = 1) and an address match occurs, then the  
CEIR Event Status bit of WKSR is set to 1.  
Disabling an event prevents it from issuing power-up  
requests, but does not affect the Status bits. A power-up  
reset is issued to the ACPI controller when both the Status  
and Enable bits are set to 1 for at least one event type.  
The CEIR Address Shift register (ADSR) holds the  
received address which is compared with the address con-  
tained in the IRWAD. The comparison is affected also by  
the CEIR Wakeup Address Mask register (IRWAM) in  
which each bit determines whether to ignore the corre-  
sponding bit in the IRWAD.  
SWC logic is powered by V . The SWC control and con-  
SB  
figuration registers are battery backed, powered by V  
.
PP  
The setup of the wakeup events, including programmable  
If CEIR routing to interrupt request is enabled, the assigned  
SWC interrupt request can be used to indicate that a com-  
plete address has been received. To get this interrupt when  
the address is completely received, IRWAM should be writ-  
ten with FFh. Once the interrupt is received, the value of  
the address can be read from ADSR.  
sequences, is retained throughout power failures (no V  
)
SB  
as long as the battery is connected. V is taken from V  
PP  
SB  
if V > 2.0; otherwise, V  
is used as the V source.  
SB  
BAT  
PP  
Hardware reset does not affect the SWC registers. They  
are reset only by a SIO software reset or power-up of V  
.
PP  
Another parameter that is used to determine whether a  
CEIR signal is to be considered valid is the bit cell time  
width. There are four time ranges for the different protocols  
and carrier frequencies. Four pairs of registers (IRWTRxL  
and IRWTRxH) define the low and high limits of each time  
range. Table 5-26 lists the recommended time ranges limits  
for the different protocols and their applicable ranges. The  
values are represented in hexadecimal code where the  
units are of 0.1 ms.  
5.6.1  
Event Detection  
5.6.1.1 Audio Codec Event  
A low-to-high transition on SDATA_IN2 indicates the detec-  
tion of an Audio Codec event and can be used as a wakeup  
event.  
Table 5-26. Time Range Limits for CEIR Protocols  
RC-5 NEC  
RCA  
Time  
Range  
Low Limit  
High Limit  
Low Limit  
High Limit  
Low Limit  
High Limit  
0
1
2
3
10h  
14h  
09h  
14h  
50h  
28h  
0Dh  
19h  
64h  
32h  
0Ch  
16h  
B4h  
23h  
12h  
1Ch  
DCh  
2Dh  
07h  
0Bh  
-
-
-
-
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• Bank 0 holds reserved registers.  
5.6.2  
SWC Registers  
The SWC registers are organized in two banks. The offsets  
are related to a base address that is determined by the  
SWC Base Address Register in the logical device configu-  
ration. The lower three registers are common to the two  
banks while the upper registers (03h-0Fh) are divided as  
follows:  
• Bank 1 holds the CEIR Control Registers.  
The active bank is selected through the Configuration Bank  
Select field (bits [1:0]) in the Wakeup Configuration Regis-  
ter (WKCFG). See Table 5-29 on page 116.  
The tables that follow provide register maps and bit defini-  
tions for Banks 0 and 1.  
Table 5-27. Banks 0 and 1 - Common Control and Status Register Map  
Reset  
Value  
Offset  
Type  
Name  
00h  
01h  
02h  
R/W1C  
R/W  
WKSR. Wakeup Events Status Register  
WKCR. Wakeup Events Control Register  
WKCFG. Wakeup Configuration Register  
00h  
03h  
00h  
R/W  
Table 5-28. Bank 1 - CEIR Wakeup Configuration and Control Register Map  
Reset  
Value  
Offset  
Type  
Name  
03h  
04h  
05h  
06h  
07h  
08h  
09h  
0Ah  
0Bh  
0Ch  
0Dh  
0Eh  
0Fh  
R/W  
---  
IRWCR. CEIR Wakeup Control Register  
00h  
---  
RSVD. Reserved  
R/W  
R/W  
RO  
IRWAD. CEIR Wakeup Address Register  
00h  
E0h  
00h  
10h  
14h  
07h  
0Bh  
50h  
64h  
28h  
32h  
IRWAM. CEIR Wakeup Address Mask Register  
ADSR. CEIR Address Shift Register  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
IRWTR0L. CEIR Wakeup, Range 0, Low Limit Register  
IRWTR0H. CEIR Wakeup, Range 0, High Limit Register  
IRWTR1L. CEIR Wakeup, Range 1, Low Limit Register  
IRWTR1H. CEIR Wakeup, Range 1, High Limit Register  
IRWTR2L. CEIR Wakeup, Range 2, Low Limit Register  
IRWTR2H. CEIR Wakeup, Range 2, High Limit Register  
IRWTR3L. CEIR Wakeup, Range 3, Low Limit Register  
IRWTR3H. CEIR Wakeup, Range 3, High Limit Register  
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Table 5-29. Banks 0 and 1 - Common Control and Status Registers  
Bit  
Description  
Offset 00h  
Wakeup Events Status Register - WKSR (R/W1C)  
Reset Value: 00h  
This register is set to 00h on power-up of VPP or software reset. It indicates which wakeup event and/or PME occurred. (See Section  
6.2.9.4 "Power Management Events" on page 158.)  
7
6
5
Reserved.  
Reserved. Must be set to 0.  
IRRX1 (CEIR) Event Status. This sticky bit shows the status of the CEIR event detection.  
0: Event not detected. (Default)  
1: Event detected.  
4:2  
1
Reserved.  
RI2# Event Status. This sticky bit shows the status of RI2# event detection.  
0: Event not detected. (Default)  
1: Event detected.  
0
SDATA_IN2 Event Status. This sticky bit shows the status of Audio Codec event detection.  
0: Event not detected. (Default)  
1: Event detected.  
Offset 01h  
Wakeup Events Control Register - WKCR (R/W)  
Reset Value: 03h  
This register is set to 03h on power-up of VPP or software reset. Detected wakeup events that are enabled issue a power-up request the  
ACPI controller and/or a PME to the Core Logic module. (See Section 6.2.9.4 "Power Management Events" on page 158.)  
7
6
5
Reserved.  
Reserved. Must be set to 0.  
IRRX1 (CEIR) Event Enable.  
0: Disable. (Default)  
1: Enable.  
4:2  
1
Reserved.  
RI2# Event Enable.  
0: Disable.  
1: Enable. (Default)  
SDATA_IN2 Event Enable.  
0: Disable.  
0
1: Enable. (Default)  
Offset 02h  
Wakeup Configuration Register - WKCFG (R/W)  
Reset Value: 00h  
This register is set to 00h on power-up of VPP or software reset. It enables access to CEIR registers.  
7:5  
4
Reserved.  
Reserved. Must be set to 0.  
Reserved. Must be set to 0.  
Reserved.  
3
2
1:0  
Configuration Bank Select Bits.  
00: Only shared registers are accessible.  
01: Shared registers and Bank 1 (CEIR) registers are accessible.  
10: Bank selected.  
11: Reserved.  
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Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers  
Bit  
Description  
Bank 1, Offset 03h  
CEIR Wakeup Control Register - IRWCR (R/W)  
Reset Value: 00h  
This register is set to 00h on power-up of VPP or software reset.  
7:6  
5:4  
Reserved.  
CEIR Protocol Select.  
00: RC5  
01: NEC/RCA  
1x: Reserved  
Reserved.  
3
2
Invert IRRX Input.  
0: Not inverted. (Default)  
1: Inverted.  
1
0
Reserved.  
CEIR Enable.  
0: Disable. (Default)  
1: Enable.  
Bank 1, Offset 04h  
Bank 1, Offset 05h  
Reserved  
CEIR Wakeup Address Register - IRWAD (R/W)  
Reset Value: 00h  
This register defines the station address to be compared with the address contained in the incoming CEIR message. If CEIR is enabled  
(bit 0 of the IRWCR register is 1) and an address match occurs, then bit 5 of the WKSR register is set to 1.  
This register is set to 00h on power-up of VPP or software reset.  
7:0  
CEIR Wakeup Address  
Bank 1, Offset 06h  
CEIR Wakeup Mask Register - IRWAM (R/W)  
Reset Value: E0h  
Each bit in this register determines whether the corresponding bit in the IRWAD register takes part in the address comparison. Bits 5, 6,  
and 7 must be set to 1 if the RC-5 protocol is selected.  
This register is set to E0h on power-up of VPP or software reset.  
7:0  
CEIR Wakeup Address Mask.  
•
•
If the corresponding bit is 0, the address bit is not masked (enabled for compare).  
If the corresponding bit is 1, the address bit is masked (ignored during compare).  
Bank 1, Offset 07h  
CEIR Address Shift Register - ADSR (RO)  
Reset Value: 00h  
This register holds the received address to be compared with the address contained in the IRWAD register.  
This register is set to 00h on power-up of VPP or software reset.  
7:0  
CEIR Address.  
CEIR Wakeup Range 0 Registers  
These two registers (IRWTR0L and IRWTR0H) define the low and high limits of time range 0 (see Table 5-26 on page 114). The values  
are represented in units of 0.1 ms.  
•
RC-5 protocol: The bit cell width must fall within this range for the cell to be considered valid. The nominal cell width is 1.778 ms for a  
36 KHz carrier. IRWTR0L and IRWTR0H should be set to 10h and 14h, respectively. (Default)  
•
NEC protocol: The time distance between two consecutive CEIR pulses that encodes a bit value of 0 must fall within this range. The  
nominal distance for a 0 is 1.125 ms for a 38 KHz carrier. IRWTR0L and IRWTR0H should be set to 09h and 0Dh, respectively.  
Bank 1, Offset 08h  
IRWTR0L Register (R/W)  
Reset Value: 10h  
This register is set to 10h on power-up of VPP or software reset.  
7:5  
4:0  
Reserved.  
CEIR Pulse Change, Range 0, Low Limit.  
Bank 1, Offset 09h  
IRWTR0H Register (R/W)  
Reset Value: 14h  
This register is set to 14h on power-up of VPP or software reset.  
7:5  
4:0  
Reserved.  
CEIR Pulse Change, Range 0, High Limit.  
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Table 5-30. Bank 1 - CEIR Wakeup Configuration and Control Registers (Continued)  
Bit  
Description  
CEIR Wakeup Range 1 Registers  
These two registers (IRWTR1L and IRWTR1H) define the low and high limits of time range 1 (see Table 5-26 on page 114). The values  
are represented in units of 0.1 ms.  
•
RC-5 protocol: The pulse width defining a half-bit cell must fall within this range in order for the cell to be considered valid. The  
nominal pulse width is 0.889 for a 38 KHz carrier. IRWTR1L and IRWTR1H should be set to 07h and 0Bh, respectively. (Default)  
•
NEC protocol: The time between two consecutive CEIR pulses that encodes a bit value of 1 must fall within this range. The nominal  
time for a 1 is 2.25 ms for a 36 KHz carrier. IRWTR1L and IRWTR1H should be set to 14h and 19h, respectively.  
Bank 1, Offset 0Ah  
IRWTR1L Register (R/W)  
Reset Value: 07h  
This register is set to 07h on power-up of VPP or software reset.  
7:5  
4:0  
Reserved.  
CEIR Pulse Change, Range 1, Low Limit.  
Bank 1, Offset 0Bh  
IRWTR1H Register (R/W)  
Reset Value: 0Bh  
This register is set to 0Bh on power-up of VPP or software reset.  
7:5  
4:0  
Reserved.  
CEIR Pulse Change, Range 1, High Limit.  
CEIR Wakeup Range 2 Registers  
These two registers (IRWTR2L and IRWTR2H) define the low and high limits of time range 2 (see Table 5-26 on page 114). The values  
are represented in units of 0.1 ms.  
•
•
RC-5 protocol: These registers are not used when the RC-5 protocol is selected.  
NEC protocol: The header pulse width must fall within this range in order for the header to be considered valid. The nominal value is  
9 ms for a 38 KHz carrier. IRWTR2L and IRWTR2H should be set to 50h and 64h, respectively. (Default)  
Bank 1, Offset 0Ch  
IRWTR2L Register (R/W)  
Reset Value: 50h  
This register is set to 50h on power-up of VPP or software reset.  
7:0 CEIR Pulse Change, Range 2, Low Limit.  
Bank 1, Offset 0Dh IRWTR2H Register (R/W)  
This register is set to 64h on power-up of VPP or software reset.  
7:0 CEIR Pulse Change, Range 2, High Limit.  
CEIR Wakeup Range 3 Registers  
Reset Value: 64h  
These two registers (IRWTR3L and IRWTR3H) define the low and high limits of time range 3 (see Table 5-26 on page 114). The values  
are represented in units of 0.1 ms.  
•
•
RC-5 protocol: These registers are not used when the RC-5 protocol is selected.  
NEC protocol: The post header gap width must fall within this range in order for the gap to be considered valid. The nominal value is  
4.5 ms for a 36 KHz carrier. IRWTR3L and IRWTR3H should be set to 28h and 32h, respectively. (Default)  
Bank 1, Offset 0Eh  
IRWTR3L Register (R/W)  
Reset Value: 28h  
This register is set to 28h on power-up of VPP or software reset.  
7:0 CEIR Pulse Change, Range 3, Low Limit.  
Bank 1, Offset 0Fh IRWTR3H Register (R/W)  
This register is set to 32h on power-up of VPP or software reset.  
7:0 CEIR Pulse Change, Range 3, High Limit.  
Reset Value: 32h  
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5.7  
ACCESS.bus Interface  
The SC3200 has two ACCESS.bus (ACB) controllers. ACB  
is a two-wire synchronous serial interface compatible with  
the ACCESS.bus physical layer, Intel's SMBus, and Philips’  
During each clock cycle, the slave can stall the master  
while it handles the previous data or prepares new data.  
This can be done for each bit transferred, or on a byte  
boundary, by the slave holding ABC low to extend the  
clock-low period. Typically, slaves extend the first clock  
cycle of a transfer if a byte read has not yet been stored, or  
if the next byte to be transmitted is not yet ready. Some  
microcontrollers, with limited hardware support for  
ACCESS.bus, extend the access after each bit, thus allow-  
ing the software to handle this bit.  
2
I C™. The ACB can be configured as a bus master or  
slave, and can maintain bidirectional communication with  
both multiple master and slave devices. As a slave device,  
the ACB may issue a request to become the bus master.  
The ACB allows easy interfacing to a wide range of low-  
cost memories and I/O devices, including: EEPROMs,  
SRAMs, timers, ADC, DAC, clock chips and peripheral driv-  
ers.  
The ACCESS.bus protocol uses a two-wire interface for  
bidirectional communication between the ICs connected to  
the bus. The two interface lines are the Serial Data Line  
(AB1D and AB2D) and the Serial Clock Line (AB1C and  
AB2C). (Here after referred to as ABD and ABC unless oth-  
erwise specified.) These lines should be connected to a  
positive supply via an internal or external pull-up resistor,  
and remain high even when the bus is idle.  
ABD  
ABC  
Data Line  
Stable:  
Data Valid Allowed  
Change  
of Data  
Each IC has a unique address and can operate as a trans-  
mitter or a receiver (though some peripherals are only  
receivers).  
Figure 5-13. Bit Transfer  
5.7.2  
Start and Stop Conditions  
During data transactions, the master device initiates the  
transaction, generates the clock signal and terminates the  
transaction. For example, when the ACB initiates a data  
transaction with an attached ACCESS.bus compliant  
peripheral, the ACB becomes the master. When the periph-  
eral responds and transmits data to the ACB, their master/  
slave (data transaction initiator and clock generator) rela-  
tionship is unchanged, even though their transmitter/  
receiver functions are reversed.  
The ACCESS.bus master generates Start and Stop Condi-  
tions (control codes). After a Start Condition is generated,  
the bus is considered busy and retains this status for a cer-  
tain time after a Stop Condition is generated. A high-to-low  
transition of the data line (ABD) while the clock (ABC) is  
high indicates a Start Condition. A low-to-high transition of  
the ABD line while the ABC is high indicates a Stop Condi-  
tion (Figure 5-14).  
In addition to the first Start Condition, a repeated Start  
Condition can be generated in the middle of a transaction.  
This allows another device to be accessed, or a change in  
the direction of data transfer.  
This section describes the general ACB functional block. A  
device may include a different implementation. For device  
specific implementation, see Section 5.4.2.5 "LDN 05h and  
06h - ACCESS.bus Ports 1 and 2" on page 101.  
5.7.1  
Data Transactions  
One data bit is transferred during each clock pulse. Data is  
sampled during the high state of the serial clock (ABC).  
Consequently, throughout the clock’s high period, the data  
should remain stable (see Figure 5-13). Any changes on  
the ABD line during the high state of the ABC and in the  
middle of a transaction aborts the current transaction. New  
data should be sent during the low ABC state. This protocol  
permits a single data line to transfer both command/control  
information and data, using the synchronous serial clock.  
ABD  
ABC  
S
P
Start  
Stop  
Condition  
Condition  
Figure 5-14. Start and Stop Conditions  
Each data transaction is composed of a Start Condition, a  
number of byte transfers (set by the software) and a Stop  
Condition to terminate the transaction. Each byte is trans-  
ferred with the most significant bit first, and after each byte  
(8 bits), an Acknowledge signal must follow. The following  
sections provide further details of this process.  
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the ABD line (permits it to go high) to allow the receiver to  
send the ACK signal. The receiver must pull down the ABD  
line during the ACK clock pulse, signalling that it has cor-  
rectly received the last data byte and is ready to receive the  
next byte. Figure 5-16 illustrates the ACK cycle.  
5.7.3  
Acknowledge (ACK) Cycle  
The ACK cycle consists of two signals: the ACK clock pulse  
sent by the master with each byte transferred, and the ACK  
signal sent by the receiving device (see Figure 5-15).  
The master generates the ACK clock pulse on the ninth  
clock pulse of the byte transfer. The transmitter releases  
Acknowledge  
Signal From Receiver  
ABD  
MSB  
ABC  
3 - 6  
8
9
ACK  
1
2
7
9
ACK  
1
2
3 - 8  
P
S
Start  
Condition  
Stop  
Condition  
Clock Line Held  
Low by Receiver  
While Interrupt  
is Serviced  
Byte Complete  
Interrupt Within  
Receiver  
Figure 5-15. ACCESS.bus Data Transaction  
Data Output  
by Transmitter  
Transmitter Stays Off Bus  
During Acknowledge Clock  
Data Output  
by Receiver  
Acknowledge  
Signal From Receiver  
ABC  
3 - 6  
8
1
2
7
9
S
Start  
Condition  
Figure 5-16. ACCESS.bus Acknowledge Cycle  
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5.7.4  
Acknowledge After Every Byte Rule  
5.7.6  
Arbitration on the Bus  
According to this rule, the master generates an acknowl-  
edge clock pulse after each byte transfer, and the receiver  
sends an acknowledge signal after every byte received.  
There are two exceptions to this rule:  
Multiple master devices on the bus require arbitration  
between their conflicting bus access demands. Control of  
the bus is initially determined according to address bits and  
clock cycle. If the masters are trying to address the same  
slave, data comparisons determine the outcome of this  
arbitration. In master mode, the device immediately aborts  
a transaction if the value sampled on the ABD line differs  
from the value driven by the device. (An exception to this  
rule is ABD while receiving data. The lines may be driven  
low by the slave without causing an abort.)  
• When the master is the receiver, it must indicate to the  
transmitter the end of data by not acknowledging (nega-  
tive acknowledge) the last byte clocked out of the slave.  
This negative acknowledge still includes the acknowl-  
edge clock pulse (generated by the master), but the  
ABD line is not pulled down.  
The ABC signal is monitored for clock synchronization and  
to allow the slave to stall the bus. The actual clock period is  
set by the master with the longest clock period, or by the  
slave stall period. The clock high period is determined by  
the master with the shortest clock high period.  
• When the receiver is full, otherwise occupied, or a  
problem has occurred, it sends a negative acknowledge  
to indicate that it cannot accept additional data bytes.  
5.7.5  
Addressing Transfer Formats  
When an abort occurs during the address transmission, a  
master that identifies the conflict should give up the bus,  
switch to slave mode and continue to sample ABD to check  
if it is being addressed by the winning master on the bus.  
Each device on the bus has a unique address. Before any  
data is transmitted, the master transmits the address of the  
slave being addressed. The slave device should send an  
acknowledge signal on the ABD line, once it recognizes its  
address.  
5.7.7  
Master Mode  
The address consists of the first 7 bits after a Start Condi-  
tion. The direction of the data transfer (R/W#) depends on  
the bit sent after the address, the eighth bit. A low-to-high  
transition during a ABC high period indicates the Stop Con-  
dition, and ends the transaction of ABD (see Figure 5-17).  
Requesting Bus Mastership  
An ACCESS.bus transaction starts with a master device  
requesting bus mastership. It asserts a Start Condition, fol-  
lowed by the address of the device it wants to access. If  
this transaction is successfully completed, the software  
may assume that the device has become the bus master.  
When the address is sent, each device in the system com-  
pares this address with its own. If there is a match, the  
device considers itself addressed and sends an acknowl-  
edge signal. Depending on the state of the R/W# bit (1 =  
Read, 0 = Write), the device acts either as a transmitter or  
a receiver.  
For the device to become the bus master, the software  
should perform the following steps:  
1) Configure ACBCTL1[2] to the desired operation mode.  
(Polling or Interrupt) and set the ACBCTL1[0]. This  
causes the ACB to issue a Start Condition on the  
ACCESS.bus when the ACCESS.bus becomes free  
(ACBCST[1] is cleared, or other conditions that can  
delay start). It then stalls the bus by holding ABC low.  
2
The I C bus protocol allows a general call address to be  
sent to all slaves connected to the bus. The first byte sent  
specifies the general call address (00h) and the second  
byte specifies the meaning of the general call (for example,  
write slave address by software only). Those slaves that  
require data acknowledge the call, and become slave  
receivers; other slaves ignore the call.  
2) If a bus conflict is detected (i.e., another device pulls  
down the ABC signal), the ACBST[5] is set.  
3) If there is no bus conflict, ACBST[1] and ACBST[6] are  
set.  
4) If the ACBCTL1[2] is set and either ACBST[5] or  
ACBST[6] is set, an interrupt is issued.  
ABD  
ABC  
9
9
9
8
8
8
1 - 7  
1 - 7  
Data  
1 - 7  
Data  
P
S
Start  
Condition  
Stop  
Condition  
Address  
ACK  
R/W  
ACK  
ACK  
Figure 5-17. A Complete ACCESS.bus Data Transaction  
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SuperI/O Module  
Sending the Address Byte  
Master Receive  
When the device is the active master of the ACCESS.bus  
(ACBST[1] is set), it can send the address on the bus.  
After becoming the bus master, the device can start receiv-  
ing data on the ACCESS.bus.  
The address sent should not be the device’s own address,  
as defined by ACBADDR[6:0] if ACBADDR[7] is set, nor  
should it be the global call address if ACBST[3] is set.  
To receive a byte in an interrupt or polling operation, the  
software should:  
1) Check that ACBST[6] is set and that ACBST[5] is  
cleared. If ACBCTL1[7] is set, also check that the  
ACBST[3] is cleared (and clear it if required).  
To send the address byte, use the following sequence:  
1) For a receive transaction where the software wants  
only one byte of data, it should set ACBCTL1[4]. If only  
an address needs to be sent or if the device requires  
stall for some other reason, set ACBCTL1[7].  
2) Set ACBCTL1[4] to 1, if the next byte is the last byte  
that should be read. This causes a negative acknowl-  
edge to be sent.  
2) Write the address byte (7-bit target device address)  
and the direction bit to the ACBSDA register. This  
causes the ACB to generate a transaction. At the end  
of this transaction, the acknowledge bit received is  
copied to ACBST[4]. During the transaction, the ABD  
and ABC lines are continuously checked for conflict  
with other devices. If a conflict is detected, the transac-  
tion is aborted, ACBST[5] is set and ACBST[1] is  
cleared.  
3) Read the data byte from the ACBSDA.  
Before receiving the last byte of data, set ACBCTL1[4].  
5.7.7.1 Master Stop  
To end a transaction, set the ACBCTL1[1] before clearing  
the current stall flag (i.e., ACBST[6], ACBST[4], or  
ACBST[3]). This causes the ACB to send a Stop Condition  
immediately, and to clear ACBCTL1[1]. A Stop Condition  
may be issued only when the device is the active bus mas-  
ter (i.e., ACBST[1] is set).  
3) If ACBCTL1[7] is set and the transaction was success-  
fully completed (i.e., both ACBST[5] and ACBST[4] are  
cleared), ACBST[3] is set. In this case, the ACB stalls  
any further ACCESS.bus operations (i.e., holds ABC  
low). If ACBCTL1[2] is set, it also sends an interrupt  
request to the host.  
Master Bus Stall  
The ACB can stall the ACCESS.bus between transfers  
while waiting for the host response. The ACCESS.bus is  
stalled by holding the AB1C signal low after the acknowl-  
edge cycle. Note that this is interpreted as the beginning of  
the following bus operation. The user must make sure that  
the next operation is prepared before the flag that causes  
the bus stall is cleared.  
4) If the requested direction is transmit and the start  
transaction was completed successfully (i.e., neither  
ACBST[5] nor ACBST[4] is set, and no other master  
has accessed the device), ACBST[6] is set to indicate  
that the ACB awaits attention.  
The flags that can cause a bus stall in master mode are:  
5) If the requested direction is receive, the start transac-  
tion was completed successfully and ACBCTL1[7] is  
cleared, the ACB starts receiving the first byte auto-  
matically.  
• Negative acknowledge after sending a byte (ACBST[4] =  
1).  
• ACBST[6] bit is set.  
• ACBCTL1[7] = 1, after a successful start (ACBST[3] =  
6) Check that both ACBST[5] and ACBST[4] are cleared.  
If ACBCTL1[2] is set, an interrupt is generated when  
ACBST[5] or ACBST[4] is set.  
1).  
Repeated Start  
A repeated start is performed when the device is already  
the bus master (ACBST[1] is set). In this case, the  
ACCESS.bus is stalled and the ACB awaits host handling  
due to: negative acknowledge (ACBST[4] = 1), empty  
buffer (ACBST[6] = 1) and/or a stall after start (ACBST[3]  
1).  
Master Transmit  
After becoming the bus master, the device can start trans-  
mitting data on the ACCESS.bus.  
To transmit a byte in an interrupt or polling controlled oper-  
ation, the software should:  
1) Check that both ACBST[5] and ACBST[4] are cleared,  
and that ACBST[6] is set. If ACBCTL1[7] is set, also  
check that ACBST[3] is cleared (and clear it if  
required).  
For a repeated start:  
1) Set \ACBCTL1[0] to 1.  
2) In master receive mode, read the last data item from  
ACBSDA.  
2) Write the data byte to be transmitted to the ACBSDA.  
3) Follow the address send sequence, as described pre-  
viously in "Sending the Address Byte". If the ACB was  
awaiting handling due to ACBST[3] = 1, clear it only  
after writing the requested address and direction to  
ACBSDA.  
When either ACBST[5] or ACBST[4] is set, an interrupt is  
generated. When the slave responds with a negative  
acknowledge, ACBST[4] Register is set and ACBST[6]  
remains cleared. In this case, if ACBCTL1[2] Register is  
set, an interrupt is issued.  
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Master Error Detection  
3) If ACBCTL1[2] is set, an interrupt is generated if both  
ACBCTL1[2] and ACBCTL16 are set.  
The ACB detects illegal Start or Stop Conditions (i.e., a  
Start or Stop Condition within the data transfer, or the  
acknowledge cycle) and a conflict on the data lines of the  
ACCESS.bus. If an illegal condition is detected, ACBST[5]  
is set, and master mode is exited (ACBST[1] is cleared).  
4) The software then reads ACBST[0] to identify the  
direction requested by the master device. It clears  
ACBST[2] so future byte transfers are identified as  
data bytes.  
Bus Idle Error Recovery  
Slave Receive and Transmit  
When a request to become the active bus master or a  
restart operation fails, ACBST[5] is set to indicate the error.  
In some cases, both the device and the other device may  
identify the failure and leave the bus idle. In this case, the  
start sequence may be incomplete and the ACCESS.bus  
may remain deadlocked.  
Slave receive and transmit are performed after a match is  
detected and the data transfer direction is identified. After a  
byte transfer, the ACB extends the acknowledge clock until  
the software reads or writes ACBSDA. The receive and  
transmit sequences are identical to those used in the mas-  
ter routine.  
To recover from deadlock, use the following sequence:  
1) Clear ACBST[5] and ACBCST[1].  
Slave Bus Stall  
When operating as  
a
slave, the device stalls the  
ACCESS.bus by extending the first clock cycle of a trans-  
action in the following cases:  
2) Wait for a timeout period to check that there is no other  
active master on the bus (i.e., ACBCST[1] remains  
cleared).  
• ACBST[6] is set.  
3) Disable, and re-enable the ACB to put it in the non-  
addressed slave mode. This completely resets the  
functional block.  
• ACBST[2] and ACBCTL1[6] are set.  
Slave Error Detection  
The ACB detects illegal Start and Stop Conditions on the  
ACCESS.bus (i.e., a Start or Stop Condition within the data  
transfer or the acknowledge cycle). When this occurs,  
ACBST[5] is set and ACBCST[3:2] are cleared, setting the  
ACB as an unaddressed slave.  
At this point, some of the slaves may not identify the bus  
error. To recover, the ACB becomes the bus master: it  
asserts a Start Condition, sends an address byte, then  
asserts a Stop Condition which synchronizes all the slaves.  
5.7.8  
Slave Mode  
5.7.9  
Configuration  
A slave device waits in idle mode for a master to initiate a  
bus transaction. Whenever the ACB is enabled and it is not  
acting as a master (i.e., ACBST[1] is cleared), it acts as a  
slave device.  
ABD and ABC Signals  
The ABD and ABC are open-drain signals. The device per-  
mits the user to define whether to enable or disable the  
internal pull-up of each of these signals.  
Once a Start Condition on the bus is detected, the device  
checks whether the address sent by the current master  
matches either:  
ACB Clock Frequency  
The ACB permits the user to set the clock frequency for the  
ACCESS.bus clock. The clock is set by the ACBCTL2[7:1],  
which determines the ABC clock period used by the device.  
This clock low period may be extended by stall periods initi-  
ated by the ACB or by another ACCESS.bus device. In  
case of a conflict with another bus master, a shorter clock  
high period may be forced by the other bus master until the  
conflict is resolved.  
• The ACBADDR[6:0] value if ACBADDR[7] = 1.  
or  
• The general call address if ACBCTL1[5] 1.  
This match is checked even when ACBST[1] is set. If a bus  
conflict (on ABD or ABC) is detected, ACBST[5] is set,  
ACBST[1] is cleared and the device continues to search  
the received message for a match.  
If an address match or a global match is detected:  
1) The device asserts its ABD pin during the acknowl-  
edge cycle.  
2) ACBCST[2] and ACBST[2] are set. If ACBST[0] = 1  
(i.e., slave transmit mode) ACBST[6] is set to indicate  
that the buffer is empty.  
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as LDN 05h and ACCESS.bus Port 2 as LDN 06h. In addi-  
tion to the registers listed here, there are additional config-  
uration registers listed in Section 5.4.2.5 "LDN 05h and 06h  
- ACCESS.bus Ports 1 and 2" on page 101.  
5.7.10 ACB Registers  
Each functional block is associated with a Logical Device  
Number (LDN) (see Section 5.3.2 "Banked Logical Device  
Registers" on page 90). ACCESS.Bus Port 1 is assigned  
Table 5-31. ACB Register Map  
Reset  
Value  
Offset  
Type  
Name  
00h  
01h  
02h  
03h  
04h  
05h  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
ACBSDA. ACB Serial Data  
ACBST. ACB Status  
xxh  
00h  
00h  
00h  
xxh  
00h  
ACBCST. ACB Control Status  
ACBCTL1. ACB Control 1  
ACBADDR. ACB Own Address  
ACBCTL2. ACB Control 2  
Table 5-32. ACB Registers  
Bit  
Description  
Offset 00h  
ACB Serial Data Register - ACBSDA (R/W)  
Reset Value: xxh  
7:0  
ACB Serial Data. This shift register is used to transmit and receive data. The most significant bit is transmitted (received)  
first, and the least significant bit is transmitted last. Reading or writing to ACBSDA is allowed only when ACBST[6] is set, or  
for repeated starts after setting the ACBCTL1[0]. An attempt to access the register in other cases may produce unpredict-  
able results.  
Offset 01h  
ACB Status Register - ACBST (R/W)  
Reset Value: 00h  
This is a read register with a special clear. Some of its bits may be cleared by software, as described below. This register maintains the  
current ACB status. On reset, and when the ACB is disabled, ACBST is cleared (00h).  
7
6
SLVSTP (Slave Stop). (R/W1C) Writing 0 to SLVSTP is ignored.  
0: Writing 1 or ACB disabled.  
1: Stop Condition detected after a slave transfer in which ACBCST[2] or ACBCST[3] was set.  
SDAST (SDA Status). (RO)  
0: Reading from ACBSDA during a receive, or when writing to it during a transmit. When ACBCTL1[0] is set, reading ACB-  
SDA does not clear SDAST. This enables ACB to send a repeated start in master receive mode.  
1: SDA Data Register awaiting data (transmit - master or slave) or holds data that should be read (receive - master or  
slave).  
5
BER (Bus Error). (R/W1C) Writing 0 to this bit is ignored.  
0: Writing 1 or ACB disabled.  
1: Start or Stop Condition detected during data transfer (i.e., Start or Stop Condition during the transfer of bits [8:2] and  
acknowledge cycle), or when an arbitration problem detected.  
4
3
NEGACK (Negative Acknowledge). (R/W1C) Writing 0 to this bit is ignored.  
0: Writing 1 or ACB disabled.  
1: Transmission not acknowledged on the ninth clock (In this case, SDAST (bit 6) is not set).  
STASTR (Stall After Start). (R/W1C) Writing 0 to this bit is ignored.  
0: Writing 1 or ACB disabled.  
1: Address sent successfully (i.e., a Start Condition sent without a bus error, or Negative Acknowledge), if ACBCTL1[7] is  
set. This bit is ignored in slave mode. When STASTR is set, it stalls the ACCESS.bus by pulling down the ABC line, and  
suspends any further action on the bus (e.g., receive of first byte in master receive mode). In addition, if ACBCTL1[1] is  
set, it also causes the ACB to send an interrupt.  
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Table 5-32. ACB Registers (Continued)  
Bit  
Description  
2
NMATCH (New Match). (R/W1C) Writing 0 to this bit is ignored. If ACBCTL1[2] is set, an interrupt is sent when this bit is  
set.  
0: Software writes 1 to this bit.  
1: Address byte follows a Start Condition or a repeated start, causing a match or a global-call match.  
MASTER. (RO)  
1
0
0: Arbitration loss (BER, bit 5, is set) or recognition of a Stop Condition.  
1: Bus master request succeeded and master mode active.  
XMIT (Transmit). (RO) Direction bit.  
0: Master/slave transmit mode not active.  
1: Master/slave transmit mode active.  
Offset 02h  
ACB Control Status Register - ACBCST (R/W)  
Reset Value: 00h  
This register configures and controls the ACB functional block. It maintains the current ACB status and controls several ACB functions.  
On reset and when the ACB is disabled, the non-reserved bits of ACBCST are cleared.  
7:6  
5
Reserved.  
TGABC (Toggle ABC Line). (R/W) Enables toggling the ABC line during error recovery.  
0: Clock toggle completed.  
1: When the ABD line is low, writing 1 to this bit toggles the ABC line for one cycle. Writing 1 to TGABC while ABD is high  
is ignored.  
4
3
TSDA (Test ABD Line). (RO) Reads the current value of the ABD line. It can be used while recovering from an error condi-  
tion in which the ABD line is constantly pulled low by an out-of-sync slave. Data written to this bit is ignored.  
GCMTCH (Global Call Match). (RO)  
0: Start Condition or repeated Start and a Stop Condition (including illegal Start or Stop Condition).  
1: In slave mode, ACBCTL1.GCMEN is set and the address byte (the first byte transferred after a Start Condition) is 00h.  
MATCH (Address Match). (RO)  
2
0: Start Condition or repeated Start and a Stop Condition (including illegal Start or Stop Condition).  
1: ACBADDR[7] is set and the first 7 bits of the address byte (the first byte transferred after a Start Condition) match the 7-  
bit address in ACBADDR.  
1
0
BB (Bus Busy). (R/W1C)  
0: Writing 1, ACB disabled, or Stop Condition detected.  
1: Bus active (a low level on either ABD or ABC), or Start Condition.  
BUSY. (RO) This bit should always be written 0. This bit indicates the period between detecting a Start Condition and com-  
pleting receipt of the address byte. After this, the ACB is either free or enters slave mode.  
0: Completion of any state below or ACB disabled.  
1: ACB is in one of the following states:  
-Generating a Start Condition  
-Master mode (ACBST[1] is set)  
-Slave mode (ACBCST[2] or ACBCST[3] set).  
Offset 03h  
ACB Control Register 1 - ACBCTL1 (R/W)  
STASTRE (Stall After Start Enable).  
Reset Value: 00h  
7
0: When cleared, ACBST[3] can not be set. However, if ACBST[3] is set, clearing STASTRE does not clear ACBST[3].  
1: Stall after start mechanism enabled, and ACB stalls the bus after the address byte.  
6
5
NMINTE (New Match Interrupt Enable).  
0: No interrupt issued on a new match.  
1: Interrupt issued on a new match only if ACBCTL1[2] set.  
GCMEN (Global Call Match Enable).  
0: Global call match disabled.  
1: Global call match enabled.  
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Table 5-32. ACB Registers (Continued)  
Bit  
Description  
4
ACK (Acknowledge). This bit is ignored in transmit mode. When the device acts as a receiver (slave or master), this bit  
holds the stop transmitting instruction that is transmitted during the next acknowledge cycle.  
0: Cleared after acknowledge cycle.  
1: Negative acknowledge issued on next received byte.  
Reserved.  
3
2
INTEN (Interrupt Enable).  
0: ACB interrupt disabled.  
1: ACB interrupt enabled. An interrupt is generated in response to one of the following events:  
-Detection of an address match (ACBST[2] = 1) and ACBCTL1[6] = 1.  
-Receipt of Bus Error (ACBST[5] = 1).  
-Receipt of Negative Acknowledge after sending a byte (ACBST[4] = 1).  
-Acknowledge of each transaction (same as the hardware set of the ACBST[6]).  
-In master mode if ACBCTL1[7] = 1, after a successful start (ACBST[3] = 1).  
-Detection of a Stop Condition while in slave mode (ACBST[7] = 1).  
1
0
STOP (Stop).  
0: Automatically cleared after Stop issued.  
1: Setting this bit in master mode generates a Stop Condition to complete or abort current message transfer.  
START (Start). Set this bit only when in master mode or when requesting master mode.  
0: Cleared after Start Condition sent or Bus Error (ACBST[5] = 1) detected.  
1: Single or repeated Start Condition generated on the ACCESS.bus. If the device is not the active master of the bus  
(ACBST[1] = 0), setting START generates a Start Condition when the ACCESS.bus becomes free (ACBCST[1] = 0). An  
address transmission sequence should then be performed.  
If the device is the active master of the bus (ACBST[1] = 1), setting START and then writing to ACBSDA generates a  
Start Condition. If a transmission is already in progress, a repeated Start Condition is generated. This condition can be  
used to switch the direction of the data flow between the master and the slave, or to choose another slave device without  
separating them with a Stop Condition.  
Offset 04h  
ACB Own Address Register - ACBADDR (R/W)  
SAEN (Slave Address Enable).  
Reset Value: xxh  
7
0: ACB does not check for an address match with ACBADDR[6:0].  
1: ACBADDR[6:0] holds a valid address and enables the match of ADDR to an incoming address byte.  
6:0  
ADDR (Address). These bits hold the 7-bit device address of the SC3200. When in slave mode, the first 7 bits received  
after a Start Condition are compared with this field (first bit received is compared with bit 6, and the last bit with bit 0). If the  
address field matches the received data and ACBADDR[7] is 1, a match is declared.  
Offset 05h  
ACB Control Register 2 - ACBCTL2 (R/W)  
Reset Value: 00h  
This register enables/disables the functional block and determines the ACB clock rate.  
7:1  
ABCFRQ (ABC Frequency). This field defines the ABC period (low and high time) when the device serves as a bus mas-  
ter. The clock low and high times are defined as follows:  
tABCl = tABCh = 2*ABCFRQ*tCLK  
where tCLK is the module input clock cycle, as defined in the Section 5.2 "Module Architecture" on page 89.  
ABCFRQ can be programmed to values in the range of 0001000b through 1111111b. Using any other value has unpredict-  
able results.  
0
EN (Enable).  
0: ACB is disabled, ACBCTL1, ACBST and ACBCST registers are cleared, and clocks are halted.  
1: ACB is enabled.  
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5.8  
Legacy Functional Blocks  
This section briefly describes the following blocks that pro-  
vide legacy device functions:  
5.8.1  
Parallel Port  
The Parallel Port supports all IEEE1284 standard commu-  
nication modes: Compatibility (known also as Standard or  
SPP), Bidirectional (known also as PS/2), FIFO, EPP  
(known also as Mode 4) and ECP (with an optional  
Extended ECP mode).  
• Parallel Port. (Similar to Parallel Port in the National  
Semiconductor PC87338.)  
• Serial Port 1 and Serial Port 2 (SP1 and SP2), UART  
functionality for both SP1 and SP2. (Similar to SCC1 in  
the National Semiconductor PC87338.)  
5.8.1.1 Parallel Port Register and Bit Maps  
The Parallel Port register maps (Table 5-33 and Table 5-34)  
are grouped according to first and second level offsets.  
EPP and second level offset registers are available only  
when the base address is 8-byte aligned.  
• Infrared Communications Port / Serial Port 3 function-  
ality. (Similar to SCC2 in the National Semiconductor  
PC87338.)  
The description of each Legacy block includes a general  
description, register maps, and bit maps.  
Parallel Port functional block bit maps are shown in Table 5-  
35 and Table 5-36.  
Table 5-33. Parallel Port Register Map for First Level Offset  
First Level Offset  
Type  
Name  
Modes (ECR Bits) 7 6 5  
000h  
000h  
001h  
002h  
003h  
004h  
005h  
006h  
007h  
400h  
400h  
400h  
400h  
401h  
402h  
403h  
404h  
405h  
R/W  
W
DATAR. PP Data  
000 or 001  
011  
AFIFO. ECP Address FIFO  
DSR. Status  
RO  
All Modes  
All Modes  
100  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
W
DCR. Control  
ADDR. EPP Address  
DATA0. EPP Data Port 0  
DATA1. EPP Data Port 1  
DATA2. EPP Data Port 2  
DATA3. EPP Data Port 3  
CFIFO. PP Data FIFO  
DFIFO. ECP Data FIFO  
TFIFO. Test FIFO  
100  
100  
100  
100  
010  
R/W  
R/W  
RO  
011  
110  
CNFGA. Configuration A  
CNFGB. Configuration B  
ECR. Extended Control  
EIR. Extended Index  
EDR. Extended Data  
EAR. Extended Auxiliary Status  
111  
RO  
111  
R/W  
R/W  
R/W  
R/W  
All Modes  
All Modes  
All Modes  
All Modes  
Table 5-34. Parallel Port Register Map for Second Level Offset  
Second Level Offset  
Type  
Name  
00h  
02h  
04h  
05h  
R/W  
R/W  
R/W  
R/W  
Control0. Control Register 0  
Control2. Control Register 2  
Control4. Control Register 4  
PP Confg0. Parallel Port Configuration Register 0  
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32581C  
SuperI/O Module  
Table 5-35. Parallel Port Bit Map for First Level Offset  
Bits  
Offset  
Name  
7
6
5
4
3
2
1
0
000h  
DATAR  
AFIFO  
DSR  
Data Bits  
Address Bits  
001h  
002h  
Printer  
Status  
ACK#  
Status  
PE  
Status  
SLCT  
Status  
ERR#  
Status  
RSVD  
EPP  
Timeout  
Status  
DCR  
RSVD  
Direction  
Control  
Interrupt  
Enable  
PP Input  
Control  
Printer Ini- Automatic  
Data  
tialization  
Control  
Line Feed  
Control  
Strobe  
Control  
003h  
004h  
005h  
006h  
007h  
400h  
400h  
400h  
400h  
ADDR  
DATA0  
DATA1  
DATA2  
DATA3  
CFIFO  
DFIFO  
TFIFO  
CNFGA  
EPP Device or Register Selection Address Bits  
EPP Device or R/W Data  
EPP Device or R/W Data  
EPP Device or R/W Data  
EPP Device or R/W Data  
Data Bits  
Data Bits  
Data Bits  
RSVD  
Bit 7 of PP  
Confg0  
RSVD  
401h  
402h  
CNFGB  
ECR  
RSVD  
Interrupt  
Request  
Value  
Interrupt Select  
RSVD  
DMA Channel Select  
ECP Mode Control  
ECP Inter- ECP DMA ECP Inter-  
rupt Mask  
FIFO  
Full  
FIFO  
Empty  
Enable  
rupt Ser-  
vice  
403h  
404h  
405h  
EIR  
EDR  
EAR  
RSVD  
Second Level Offset  
Data Bits  
RSVD  
FIFO Tag  
Table 5-36. Parallel Port Bit Map for Second Level Offset  
Bits  
Offset  
Name  
7
6
5
4
3
2
1
0
00h  
Control0  
RSVD  
DCR Reg- Freeze Bit  
ister Live  
RSVD  
EPP Time-  
out Inter-  
rupt Mask  
02h  
Control2  
SPP Com-  
patibility  
Channel  
Address  
Enable  
RSVD  
Revision  
1.7 or 1.9  
Select  
RSVD  
04h  
05h  
Control4  
RSVD  
PP DMA Request Inactive Time  
RSVD  
PP DMA Request Active Time  
PP Confg0  
Bit 3 of  
CNFGA  
Demand  
DMA  
ECP IRQ Channel Number  
PE Inter-  
ECP DMA Channel  
Number  
nal PU or  
PD  
Enable  
128  
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5.8.2  
UART Functionality (SP1 and SP2)  
Both SP1 and SP2 provide UART functionality. The generic  
SP1 and SP2 support serial data communication with  
remote peripheral device or modem using a wired inter-  
face. The functional blocks can function as a standard  
16450, 16550, or as an Extended UART.  
Bank 3  
Bank 2  
Bank 1  
Common  
Register  
Throughout  
All Banks  
Bank 0  
5.8.2.1 UART Mode Register Bank Overview  
Offset 07h  
Offset 06h  
Offset 05h  
Offset 04h  
Four register banks, each containing eight registers, control  
UART operation. All registers use the same 8-byte address  
space to indicate offsets 00h through 07h. The BSR regis-  
ter selects the active bank and is common to all banks. See  
Figure 5-18.  
5.8.2.2 SP1 and SP2 Register and Bit Maps for UART  
Functionality  
LCR/BSR  
Offset 02h  
The tables in this subsection provide register and bit maps  
for Banks 0 through 3.  
Offset 01h  
Offset 00h  
16550 Banks  
Figure 5-18. UART Mode Register Bank  
Architecture  
Table 5-37. Bank 0 Register Map  
Name  
Offset  
Type  
00h  
RO  
W
RXD. Receiver Data Port  
TXD. Transmitter Data Port  
IER. Interrupt Enable  
01h  
02h  
R/W  
RO  
R/W  
W
EIR. Event Identification (Read Cycles)  
FCR. FIFO Control (Write Cycles)  
1
03h  
LCR . Line Control  
1
R/W  
BSR .Bank Select  
04h  
05h  
06h  
07h  
R/W  
R/W  
R/W  
R/W  
R/W  
MCR. Modem/Mode Control  
LSR. Link Status  
MSR. Modem Status  
SPR. Scratchpad  
ASCR. Auxiliary Status and Control  
1. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-38.  
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Table 5-38. Bank Selection Encoding  
BSR Bits  
7
6
5
4
3
2
1
0
Bank Selected  
0
1
1
1
1
1
x
0
1
1
1
1
x
x
x
x
1
1
x
x
x
x
0
0
x
x
x
x
0
0
x
x
x
x
0
1
x
x
1
x
0
0
x
x
x
1
0
0
0
1
1
1
2
3
Table 5-39. Bank 1 Register Map  
Name  
Offset  
Type  
00h  
01h  
02h  
03h  
R/W  
R/W  
---  
LBGD(L). Legacy Baud Generator Divisor Port (Low Byte)  
LBGD(H). Legacy Baud Generator Divisor Port (High Byte)  
RSVD. Reserved  
1
W
LCR . Line Control  
1
R/W  
---  
BSR . Bank Select  
04h-07h  
RSVD. Reserved  
1. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-38 on page 130.  
Table 5-40. Bank 2 Register Map  
Offset  
Type  
Name  
00h  
01h  
02h  
03h  
04h  
05h  
06h  
07h  
R/W  
R/W  
R/W  
R/W  
R/W  
---  
BGD(L). Baud Generator Divisor Port (Low Byte)  
BGD(H). Baud Generator Divisor Port (High Byte)  
EXCR1. Extended Control1  
BSR. Bank Select  
EXCR2. Extended Control 2  
RSVD. Reserved  
RO  
RXFLV. RX_FIFO Level  
RO  
TXFLV. TX_FIFO Level  
Table 5-41. Bank 3 Register Map  
Name  
Offset  
Type  
00h  
01h  
RO  
RO  
RO  
R/W  
---  
MRID. Module and Revision ID  
SH_LCR. Shadow of LCR  
SH_FCR. Shadow of FIFO Control  
BSR. Bank Select  
02h  
03h  
04h-07h  
RSVD. Reserved  
130  
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Table 5-42. Bank 0 Bit Map  
Bits  
Offset  
Name  
7
6
5
4
3
2
1
0
00h  
RXD  
TXD  
RXD[7:0] (Receiver Data Bits)  
TXD[7:0] (Transmitter Data Bits)  
MS_IE  
IER1  
IER2  
01h  
02h  
RSVD  
TXEMP_IE  
LS_IE  
TXLDL_IE RXHDL_IE  
TXLDL_IE RXHDL_IE  
RSVD3/  
RSVD  
MS_IE  
LS_IE  
DMA_IE4  
EIR1  
EIR2  
FEN[1:0]  
RSVD  
RSVD  
RXFT  
IPR1  
IPR0  
IPF  
RSVD 3/  
TXEMP_EV  
MS_EV  
LS_EV or  
TXLDL_EV RXHDL_EV  
TXHLT_EV  
DMA_EV 4  
FCR  
RXFTH[1:0]  
TXFTH[1:0]  
RSVD  
PEN  
TXSR  
STB  
RXSR  
FIFO_EN  
5
03h  
04h  
BKSE  
BKSE  
SBRK  
STKP  
EPS  
WLS[1:0]  
LCR  
BSR5  
MCR1  
BSR[6:0] (Bank Select)  
RSVD  
LOOP  
ISEN or  
DCDLP  
RILP  
RTS  
RTS  
DTR  
DTR  
MCR2  
LSR  
RSVD  
TX_DFR  
RSVD  
05h  
06h  
07h  
ER_INF  
DCD  
TXEMP  
RI  
TXRDY  
DSR  
BRK  
CTS  
FE  
PE  
OE  
RXDA  
DCTS  
MSR  
DDCD  
TERI  
DDSR  
SPR1  
Scratch Data  
ASCR2  
TXUR4  
RXACT4  
RXWDG4  
S_OET4  
RSVD  
RSVD  
RSVD  
RXF_TOUT  
1. Non-Extended Mode.  
2. Extended Mode.  
3. In SP1 only.  
4. In SP2 only.  
5. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-38 on page 130.  
Table 5-43. Bank 1 Bit Map  
Register  
Name  
Bits  
Offset  
7
6
5
4
3
2
1
0
00h  
01h  
02h  
03h  
LBGD(L)  
LBGD(H)  
RSVD  
LBGD[7:0] (Low Byte)  
LBGD[15:8] (High Byte)  
Reserved  
1
BKSE  
BKSE  
SBRK  
STKP  
EPS  
PEN  
STB  
WLS[1:0]  
LCR  
BSR1  
BSR[6:0] (Bank Select)  
Reserved  
04h-07h  
RSVD  
1. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-38 on page 130.  
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Table 5-44. Bank 2 Bit Map  
Register  
Name  
Bits  
Offset  
7
6
5
4
3
2
1
0
00h  
01h  
02h  
03h  
04h  
05h  
06h  
07h  
BGD(L)  
BGD(H)  
EXCR1  
BSR  
BGD[7:0] (Low Byte)  
BGD [15:8] (High Byte)