Cat.No. W303–E1–4
Programmable Controllers
C200HX/C200HG/C200HE
OPERATION MANUAL
C200HX/C200HG/C200HE
Programmable Controllers
Operation Manual
Revised June 2000
Notice:
OMRON products are manufactured for use according to proper procedures by a qualified operator
and only for the purposes described in this manual.
The following conventions are used to indicate and classify precautions in this manual. Always heed
the information provided with them. Failure to heed precautions can result in injury to people or dam-
age to property.
DANGER
Indicates an imminently hazardous situation which, if not avoided, will result in death or
serious injury.
!
!
!
WARNING
Caution
Indicates a potentially hazardous situation which, if not avoided, could result in death or
serious injury.
Indicates a potentially hazardous situation which, if not avoided, may result in minor or
moderate injury, or property damage.
OMRON Product References
All OMRON products are capitalized in this manual. The word “Unit” is also capitalized when it refers
to an OMRON product, regardless of whether or not it appears in the proper name of the product.
The abbreviation “Ch,” which appears in some displays and on some OMRON products, often means
“word” and is abbreviated “Wd” in documentation in this sense.
The abbreviation “PC” means Programmable Controller and is not used as an abbreviation for any-
thing else.
Visual Aids
The following headings appear in the left column of the manual to help you locate different types of
information.
Note Indicates information of particular interest for efficient and convenient operation
of the product.
1, 2, 3... 1. Indicates lists of one sort or another, such as procedures, checklists, etc.
OMRON, 1996
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any
form, or by any means, mechanical, electronic, photocopying, recording, or otherwise, without the prior written permis-
sion of OMRON.
No patent liability is assumed with respect to the use of the information contained herein. Moreover, because OMRON is
constantly striving to improve its high-quality products, the information contained in this manual is subject to change
without notice. Every precaution has been taken in the preparation of this manual. Nevertheless, OMRON assumes no
responsibility for errors or omissions. Neither is any liability assumed for damages resulting from the use of the informa-
tion contained in this publication.
v
TABLE OF CONTENTS
PRECAUTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 General Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Safety Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Operating Environment Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Application Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Conformance to EC Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xiii
xiv
xiv
xiv
xv
xv
xvii
SECTION 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1-1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2 The Origins of PC Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-3 PC Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-4 OMRON Product Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-5 Overview of PC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-6 Peripheral Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-7 Available Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8 C200HX/HG/HE Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2
3
4
4
5
6
7
SECTION 2
Hardware Considerations . . . . . . . . . . . . . . . . . . . . . . . . .
11
2-1 CPU Unit Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2 PC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3 CPU Unit Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-4 Memory Cassettes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-5 CPU Unit DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-6 Operating without a Backup Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
15
15
16
20
21
SECTION 3
Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
3-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2 Data Area Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3 IR (Internal Relay) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4 SR (Special Relay) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5 AR (Auxiliary Relay) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6 DM (Data Memory) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7 HR (Holding Relay) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-8 TC (Timer/Counter) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-9 LR (Link Relay) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-10 UM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-11 TR (Temporary Relay) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-12 EM (Extended Data Memory) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
25
29
33
48
56
68
68
69
70
71
71
SECTION 4
Writing and Inputting the Program . . . . . . . . . . . . . . . . .
73
4-1 Basic Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2 Instruction Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3 Program Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4 Basic Ladder Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5 The Programming Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6 Preparation for Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7 Inputting, Modifying, and Checking the Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
74
75
75
88
91
104
vii
TABLE OF CONTENTS
4-8 Controlling Bit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-9 Work Bits (Internal Relays) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-10 Programming Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-11 Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-12 Special I/O Unit Interface Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-13 Analog Timer Unit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
120
122
124
126
126
130
SECTION 5
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5-1 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-2 Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-3 Data Areas, Definer Values, and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-4 Differentiated Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-5 Expansion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-6 Coding Right-hand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-7 Instruction Set Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-8 Ladder Diagram Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-9 Bit Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-10 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) . . . . . . . . . . . . . . . . . . .
5-11 JUMP and JUMP END – JMP(04) and JME(05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-12 END – END(01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-13 NO OPERATION – NOP(00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14 Timer and Counter Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15 Data Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16 Data Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17 Data Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18 Data Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19 BCD Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20 Binary Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-21 Special Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-22 Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-23 Subroutines and Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-24 Step Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25 Special Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-26 Network Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-27 Serial Communications Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-28 Advanced I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-29 Special I/O Unit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
138
138
138
140
141
142
145
149
150
155
157
158
158
158
171
180
192
204
228
243
257
275
279
291
300
318
329
336
350
SECTION 6
Program Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . 359
6-1 Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-2 Calculating Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-3 Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-4 I/O Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
360
364
367
376
SECTION 7
Program Monitoring and Execution . . . . . . . . . . . . . . . . 389
7-1 Monitoring Operation and Modifying Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2 Programming Console Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
390
390
viii
TABLE OF CONTENTS
SECTION 8
Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
8-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-2 Host Link Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-3 RS-232C Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-4 One-to-one PC Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-5 NT Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-6 The Protocol Macro Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
418
419
426
430
432
433
SECTION 9
Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
9-1 Alarm Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-2 Programmed Alarms and Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-3 Reading and Clearing Errors and Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-4 Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-6 Host Link Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
444
444
444
445
449
450
SECTION 10
Host Link Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
10-1 Host Link Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-2 Host Link End Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3 Host Link Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
454
455
458
Appendices
A Standard Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B Programming Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C Error and Arithmetic Flag Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D Word Assignment Recording Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E Program Coding Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
F Data Conversion Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
G Extended ASCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
501
517
523
527
533
535
537
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
ix
About this Manual:
This manual describes the operation of the C200HX/HG/HE Programmable Controllers, and it includes
the sections described below. Installation information is provided in the C200HX/HG/HE Programmable
Controller Installation Guide. A table of other manuals that can be used in conjunction with this manual is
provided in Section 1 Introduction. Provided in Section 2 Hardware Considerations is a description of the
differences between the C200HS CPU Units and the new CPU Units described in this manual.
Please read this manual completely and be sure you understand the information provided before attempt-
ing to operate the C200HX/HG/HE. Be sure to read the precautions in the following section.
Section 1 Introduction explains the background and some of the basic terms used in ladder-diagram
programming. It also provides an overview of the process of programming and operating a PC and ex-
plains basic terminology used with OMRON PCs. Descriptions of Peripheral Devices used with the
C200HX/HG/HE PCs and a table of other manuals available to use with this manual for special PC ap-
plications are also provided.
Section 2 Hardware Considerations explains basic aspects of the overall PC configuration, describes
the indicators that are referred to in other sections of this manual, and explains how to use the Memory
Cassette to manage UM and IOM data.
Section 3 Memory Areas takes a look at the way memory is divided and allocated and explains the in-
formation provided there to aid in programming. It explains how I/O is managed in memory and how bits in
memory correspond to specific I/O points. It also provides information on System DM, a special area in
C200HX/HG/HE PCs that provides the user with flexible control of PC operating parameters.
Section 4 Writing and Entering Programs explains the basics of ladder-diagram programming, looking
at the elements that make up the parts of a ladder-diagram program and explaining how execution of this
program is controlled. It also explains how to convert ladder diagrams into mnemonic code so that the
programs can be entered using a Programming Console.
Section 5 Instruction Set describes all of the instructions used in programming.
Section 6 Program Execution Timing explains the cycling process used to execute the program and
tells how to coordinate inputs and outputs so that they occur at the proper times.
Section 7 Program Debugging and Execution explains the Programming Console procedures used to
input and debug the program and to monitor and control operation.
Section 8 Communications provides an overview of the communications features provided by the
C200HS.
Section 9 Troubleshooting provides information on error indications and other means of reducing
down-time. Information in this section is also useful when debugging programs.
Section 10 Host Link Commands explains the host link commands that can be used for host link com-
munications via the C200HX/HG/HE ports.
The Appendices provide tables of standard OMRON products available for the C200HX/HG/HE PCs,
reference tables of instructions, a coding sheet to help in programming and parameter input, and other
information helpful in PC operation.
!
WARNING Failure to read and understand the information provided in this manual may result in
personal injury or death, damage to the product, or product failure. Please read each
section in its entirety and be sure you understand the information provided in the section
and related sections before attempting any of the procedures or operations given.
xi
PRECAUTIONS
This section provides general precautions for using the Programmable Controller (PC) and related devices.
The information contained in this section is important for the safe and reliable application of the PC. You must read
this section and understand the information contained before attempting to set up or operate a PC system.
1 Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 General Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Safety Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Operating Environment Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Application Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Conformance to EC Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xiv
xiv
xiv
xv
xv
xvii
xiii
Safety Precautions
3
1
Intended Audience
This manual is intended for the following personnel, who must also have knowl-
edge of electrical systems (an electrical engineer or the equivalent).
• Personnel in charge of installing FA systems.
• Personnel in charge of designing FA systems.
• Personnel in charge of managing FA systems and facilities.
2
General Precautions
The user must operate the product according to the performance specifications
described in the operation manuals.
Before using the product under conditions which are not described in the manual
or applying the product to nuclear control systems, railroad systems, aviation
systems, vehicles, combustion systems, medical equipment, amusement ma-
chines, safety equipment, and other systems, machines, and equipment that
may have a serious influence on lives and property if used improperly, consult
your OMRON representative.
Make sure that the ratings and performance characteristics of the product are
sufficient for the systems, machines, and equipment, and be sure to provide the
systems, machines, and equipment with double safety mechanisms.
This manual provides information for programming and operating OMRON PCs.
Be sure to read this manual before attempting to use the software and keep this
manual close at hand for reference during operation.
WARNING It is extremely important that a PC and all PC Units be used for the specified
purpose and under the specified conditions, especially in applications that can
directly or indirectly affect human life. You must consult with your OMRON
representative before applying a PC System to the above mentioned
applications.
!
3
Safety Precautions
WARNING Do not attempt to take any Unit apart while the power is being supplied. Doing so
!
!
!
may result in electric shock.
WARNING Do not touch any of the terminals or terminal blocks while the power is being
supplied. Doing so may result in electric shock.
WARNING Provide safety measures in external circuits (i.e., not in the Programmable
Controller), including the following items, to ensure safety in the system if an
abnormality occurs due to malfunction of the PC or another external factor
affecting the PC operation. Not doing so may result in serious accidents.
• Emergency stop circuits, interlock circuits, limit circuits, and similar safety
measures must be provided in external control circuits.
• The PC will turn OFF all outputs when its self-diagnosis function detects any
error or when a severe failure alarm (FALS) instruction is executed. As a coun-
termeasure for such errors, external safety measures must be provided to en-
sure safety in the system.
• The PC outputs may remain ON or OFF due to deposition or burning of the
output relays or destruction of the output transistors. As a countermeasure for
xiv
Application Precautions
5
such problems, external safety measures must be provided to ensure safety in
the system.
• When the 24-VDC output (service power supply to the PC) is overloaded or
short-circuited, the voltage may drop and result in the outputs being turned
OFF. As a countermeasure for such problems, external safety measures must
be provided to ensure safety in the system.
Caution Execute online edit only after confirming that no adverse effects will be caused
!
!
by extending the cycle time. Otherwise, the input signals may not be readable.
Caution Confirm safety at the destination node before transferring a program to another
node or changing contents of the I/O memory area. Doing either of these without
confirming safety may result in injury.
Caution Tighten the screws on the terminal block of the AC Power Supply Unit to the
torque specified in the operation manual. The loose screws may result in burning
or malfunction.
!
4
Operating Environment Precautions
Do not operate the control system in the following places.
• Where the PC is exposed to direct sunlight.
• Where the ambient temperature is below 0°C or over 55°C.
• Where the PC may be affected by condensation due to radical temperature
changes.
• Where the ambient humidity is below 10% or over 90%.
• Where there is any corrosive or inflammable gas.
• Where there is excessive dust, saline air, or metal powder.
• Where the PC is affected by vibration or shock.
• Where any water, oil, or chemical may splash on the PC.
Caution The operating environment of the PC System can have a large effect on the lon-
gevity and reliability of the system. Improper operating environments can lead to
malfunction, failure, and other unforeseeable problems with the PC System. Be
sure that the operating environment is within the specified conditions at installa-
tion and remains within the specified conditions during the life of the system.
!
5
Application Precautions
Observe the following precautions when using the PC.
WARNING Failure to abide by the following precautions could lead to serious or possibly
!
fatal injury. Always heed these precautions.
• Always ground the system to 100 Ω or less when installing the system to pro-
tect against electrical shock.
• Always turn OFF the power supply to the PC before attempting any of the fol-
lowing. Performing any of the following with the power supply turned ON may
lead to electrical shock:
• Mounting or removing any Units (e.g., I/O Units, CPU Unit, etc.) or memory
cassettes.
• Assembling any devices or racks.
xv
Application Precautions
5
• Connecting or disconnecting any cables or wiring.
Caution Failure to abide by the following precautions could lead to faulty operation of the
PC or the system or could damage the PC or PC Units. Always heed these pre-
cautions.
!
• Use the Units only with the power supplies and voltages specified in the opera-
tion manuals. Other power supplies and voltages may damage the Units.
• Take measures to stabilize the power supply to conform to the rated supply if it
is not stable.
• Provide circuit breakers and other safety measures to provide protection
against shorts in external wiring.
• Do not apply voltages exceeding the rated input voltage to Input Units.
• Do not apply voltages exceeding the maximum switching capacity to Output
Units.
• Always disconnect the functional ground terminal when performing withstand
voltage tests.
• Carefully follow all of the installation instructions provided in the manuals, in-
cluding the Installation Guide.
• Provide proper shielding when installing in the following locations:
• Locations subject to static electricity or other sources of noise.
• Locations subject to strong electromagnetic fields.
• Locations subject to possible exposure to radiation.
• Locations near to power supply lines.
• Be sure to tighten Backplane screws, terminal screws, and cable connector
screws securely.
• Do not attempt to take any Units apart, to repair any Units, or to modify any
Units in any way.
Caution The following precautions are necessary to ensure the general safety of the sys-
!
tem. Always heed these precautions.
• Provide double safety mechanisms to handle incorrect signals that can be
generated by broken signal lines or momentary power interruptions.
• Provide external interlock circuits, limit circuits, and other safety circuits in
addition to any provided within the PC to ensure safety.
• Always test the operation of the user program sufficiently before starting actual
system operation.
• Always confirm that there will be no adverse affects on the system before
changing the PC’s operating mode.
• Always confirm that there will be no adverse affects on the system before
force-setting/resetting any bits in PC memory.
• Always confirm that there will be no adverse affects on the system before
changing any set values or present values in PC memory.
• Whenever the CPU Unit has been replaced, be sure that all required memory
data, such as that in the HR and DM areas, has been transferred to the new
CPU Unit before starting operation.
• Never pull on or place objects on cables or cords, or wires may be broken.
xvi
Conformance to EC Directives
6
6
Conformance to EC Directives
Observe the following precautions when installing the C200HX/HG/HE PCs that
conform to the EC Directives.
Provide reinforced insulation or double insulation for the DC power source con-
nected to the DC I/O Unit and for the Power Supply Unit.
Use a separate power source for the DC I/O Unit from the external power supply
for the Relay Output Unit.
xvii
SECTION 1
Introduction
This section gives a brief overview of the history of Programmable Controllers and explains terms commonly used in ladder-
diagram programming. It also provides an overview of the process of programming and operating a PC and explains basic
terminology used with OMRON PCs. Descriptions of peripheral devices used with the C200HX/HG/HE PCs, a table of other
manuals available to use with this manual for special PC applications, and a description of the new features of the C200HX/
HG/HE PCs are also provided.
1-1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2 The Origins of PC Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-3 PC Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-4 OMRON Product Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-5 Overview of PC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-6 Peripheral Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-7 Available Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8 C200HX/HG/HE Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-1 C200HS and C200HX/HG/HE Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-8-2 Program Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2
3
4
4
5
6
7
7
8
1
The Origins of PC Logic
Section 1-2
1-1 Overview
A PC (Programmable Controller) is basically a CPU (Central Processing Unit)
containing a program and connected to input and output (I/O) devices. The pro-
gram controls the PC so that when an input signal from an input device turns ON,
the appropriate response is made. The response normally involves turning ON
an output signal to some sort of output device. The input devices could be photo-
electric sensors, pushbuttons on control panels, limit switches, or any other de-
vice that can produce a signal that can be input into the PC. The output devices
could be solenoids, switches activating indicator lamps, relays turning on mo-
tors, or any other devices that can be activated by signals output from the PC.
For example, a sensor detecting a passing product turns ON an input to the PC.
The PC responds by turning ON an output that activates a pusher that pushes
the product onto another conveyor for further processing. Another sensor, posi-
tioned higher than the first, turns ON a different input to indicate that the product
is too tall. The PC responds by turning on another pusher positioned before the
pusher mentioned above to push the too-tall product into a rejection box.
Although this example involves only two inputs and two outputs, it is typical of the
type of control operation that PCs can achieve. Actually even this example is
much more complex than it may at first appear because of the timing that would
be required, i.e., “How does the PC know when to activate each pusher?” Much
more complicated operations, however, are also possible. The problem is how
to get the desired control signals from available inputs at appropriate times.
To achieve proper control, the C200HX/HG/HE PCs use a form of PC logic
called ladder-diagram programming. This manual is written to explain ladder-
diagram programming and to prepare the reader to program and operate the
PC.
1-2 The Origins of PC Logic
PCs historically originate in relay-based control systems. And although the inte-
grated circuits and internal logic of the PC have taken the place of the discrete
relays, timers, counters, and other such devices, actual PC operation proceeds
as if those discrete devices were still in place. PC control, however, also pro-
vides computer capabilities and accuracy to achieve a great deal more flexibility
and reliability than is possible with relays.
The symbols and other control concepts used to describe PC operation also
come from relay-based control and form the basis of the ladder-diagram pro-
gramming method. Most of the terms used to describe these symbols and con-
cepts, however, have come in from computer terminology.
Relay vs. PC Terminology
The terminology used throughout this manual is somewhat different from relay
terminology, but the concepts are the same.
The following table shows the relationship between relay terms and the PC
terms used for OMRON PCs.
Relay term
contact
PC equivalent
input or condition
coil
output or work bit
NO relay
NC relay
normally open condition
normally closed condition
2
PC Terminology
Section 1-3
Actually there is not a total equivalence between these terms. The term condi-
tion is only used to describe ladder diagram programs in general and is specifi-
cally equivalent to one of a certain set of basic instructions. The terms input and
output are not used in programming per se, except in reference to I/O bits that
are assigned to input and output signals coming into and leaving the PC. Nor-
mally open conditions and normally closed conditions are explained in 4-4 Basic
Ladder Diagrams.
1-3 PC Terminology
Although also provided in the Glossary at the back of this manual, the following
terms are crucial to understanding PC operation and are thus explained here.
PC
Because the C200HX/HG/HE PCs are Rack PCs, there is no one product that is
a C200HX/HG/HE PC. That is why we talk about the configuration of the PC,
because a PC is a configuration of smaller Units.
To have a functional PC, you would need to have a CPU Rack with at least one
Unit mounted to it that provides I/O points. When we refer to the PC, however, we
are generally talking about the CPU Unit and all of the Units directly controlled by
it through the program. This does not include the I/O devices connected to PC
inputs and outputs.
If you are not familiar with the terms used above to describe a PC, refer to Sec-
tion 2 Hardware Considerations for explanations.
Inputs and Outputs
A device connected to the PC that sends a signal to the PC is called an input
device; the signal it sends is called an input signal. A signal enters the PC
through terminals or through pins on a connector on a Unit. The place where a
signal enters the PC is called an input point. This input point is allocated a loca-
tion in memory that reflects its status, i.e., either ON or OFF. This memory loca-
tion is called an input bit. The CPU Unit, in its normal processing cycle, monitors
the status of all input points and turns ON or OFF corresponding input bits ac-
cordingly.
There are also output bits in memory that are allocated to output points on
Units through which output signals are sent to output devices, i.e., an output
bit is turned ON to send a signal to an output device through an output point. The
CPU Unit periodically turns output points ON or OFF according to the status of
the output bits.
These terms are used when describing different aspects of PC operation. When
programming, one is concerned with what information is held in memory, and so
I/O bits are referred to. When talking about the Units that connect the PC to the
controlled system and the places on these Units where signals enter and leave
the PC, I/O points are referred to. When wiring these I/O points, the physical
counterparts of the I/O points, either terminals or connector pins, are referred to.
When talking about the signals that enter or leave the PC, one refers to input
signals and output signals, or sometimes just inputs and outputs. It all depends
on what aspect of PC operation is being talked about.
Controlled System and
Control System
The Control System includes the PC and all I/O devices it uses to control an ex-
ternal system. A sensor that provides information to achieve control is an input
device that is clearly part of the Control System. The controlled system is the
external system that is being controlled by the PC program through these I/O
devices. I/O devices can sometimes be considered part of the controlled sys-
tem, e.g., a motor used to drive a conveyor belt.
3
Overview of PC Operation
Section 1-5
1-4 OMRON Product Terminology
OMRON products are divided into several functional groups that have generic
names. Appendix A Standard Models list products according to these groups.
The term Unit is used to refer to all of the OMRON PC products. Although a Unit
is any one of the building blocks that goes together to form a C200HX/HG/HE
PC, its meaning is generally, but not always, limited in context to refer to the Units
that are mounted to a Rack. Most, but not all, of these products have names that
end with the word Unit.
The largest group of OMRON products is the I/O Units. These include all of the
Rack-mounting Units that provide non-dedicated input or output points for gen-
eral use. I/O Units come with a variety of point connections and specifications.
High-density I/O Units are designed to provide high-density I/O capability and
include Group 2 High-density I/O Units and Special I/O High-density I/O Units.
Special I/O Units are dedicated Units that are designed to meet specific needs.
These include some of the High-density I/O Units, Position Control Units, High-
speed Counter Units, and Analog I/O Units.
Link Units are used to create Link Systems that link more than one PC or link a
single PC to remote I/O points. Link Units include Remote I/O Units, PC Link
Units, Host Link Units, SYSMAC NET Link Units, and SYSMAC LINK Units.
SYSMAC NET Link and SYSMAC LINK Units can be used with the CPU11-E
only.
Other product groups include Programming Devices, Peripheral Devices,
and DIN Rail Products.
1-5 Overview of PC Operation
The following are the basic steps involved in programming and operating a
C200HX/HG/HE PC. Assuming you have already purchased one or more of
these PCs, you must have a reasonable idea of the required information for
steps one and two, which are discussed briefly below. This manual is written to
explain steps three through six, eight, and nine. The relevant sections of this
manual that provide more information are listed with each of these steps.
1, 2, 3...
1. Determine what the controlled system must do, in what order, and at what
times.
2. Determine what Racks and what Units will be required. Refer to the
C200HX/HG/HE PC Installation Guide. If a Link System is required, refer to
the appropriate System Manual.
3. On paper, assign all input and output devices to I/O points on Units and de-
termine which I/O bits will be allocated to each. If the PC includes Special I/O
Units or Link Systems, refer to the individual Operation Manuals or System
Manuals for details on I/O bit allocation. (Section 3 Memory Areas)
4. Using relay ladder symbols, write a program that represents the sequence
of required operations and their inter-relationships. Be sure to also program
appropriate responses for all possible emergency situations. (Section 4
Writing and Inputting the Program, Section 5 Instruction Set, Section 6 Pro-
gram Execution Timing)
5. Input the program and all required operating parameters into the PC. (Sec-
tion 4-7 Inputting, Modifying, and Checking the Program.)
6. Debug the program, first to eliminate any syntax errors, and then to find
execution errors. (Section 4-7 Inputting, Modifying, and Checking the Pro-
gram, Section 7 Program Monitoring and Execution, and Section 9 Trouble-
shooting)
4
Peripheral Devices
Section 1-6
7. Wire the PC to the controlled system. This step can actually be started as
soon as step 3 has been completed. Refer to the C200HX/HG/HE PC Instal-
lation Guide and to Operation Manuals and System Manuals for details on
individual Units.
8. Test the program in an actual control situation and carry out fine tuning as
required. (Section 7 Program Monitoring and Execution and Section 9 Trou-
bleshooting)
9. Record two copies of the finished program on masters and store them safely
in different locations. (Section 4-7 Inputting, Modifying, and Checking the
Program)
Control System Design
Designing the Control System is the first step in automating any process. A PC
can be programmed and operated only after the overall Control System is fully
understood. Designing the Control System requires, first of all, a thorough un-
derstanding of the system that is to be controlled. The first step in designing a
Control System is thus determining the requirements of the controlled system.
Input/Output Requirements The first thing that must be assessed is the number of input and output points
that the controlled system will require. This is done by identifying each device
that is to send an input signal to the PC or which is to receive an output signal
from the PC. Keep in mind that the number of I/O points available depends on
the configuration of the PC. Refer to 3-3 IR Area for details on I/O capacity and
the allocation of I/O bits to I/O points.
Sequence, Timing, and
Relationships
Next, determine the sequence in which control operations are to occur and the
relative timing of the operations. Identify the physical relationships between the
I/O devices as well as the kinds of responses that should occur between them.
For instance, a photoelectric switch might be functionally tied to a motor by way
of a counter within the PC. When the PC receives an input from a start switch, it
could start the motor. The PC could then stop the motor when the counter has
received a specified number of input signals from the photoelectric switch.
Each of the related tasks must be similarly determined, from the beginning of the
control operation to the end.
Unit Requirements
The actual Units that will be mounted or connected to PC Racks must be deter-
mined according to the requirements of the I/O devices. Actual hardware specifi-
cations, such as voltage and current levels, as well as functional considerations,
such as those that require Special I/O Units or Link Systems will need to be con-
sidered. In many cases, Special I/O Units, Intelligent I/O Units, or Link Systems
can greatly reduce the programming burden. Details on these Units and Link
Systems are available in appropriate Operation Manuals and System Manuals.
Once the entire Control System has been designed, the task of programming,
debugging, and operation as described in the remaining sections of this manual
can begin.
1-6 Peripheral Devices
The following peripheral devices can be used in programming, either to input/
debug/monitor the PC program or to interface the PC to external devices to out-
put the program or memory area data. Model numbers for all devices listed be-
low are provided in Appendix A Standard Models. OMRON product names have
been placed in bold when introduced in the following descriptions.
Programming Console
A Programming Console is the simplest form of programming device for OM-
RON PCs. All Programming Consoles are connected directly to the CPU Unit
without requiring a separate interface.
SYSMAC Support Software: SSS is designed to run on IBM PC/AT or compatibles and allows you to perform
SSS
all the operations of the Programming Console as well as many additional ones.
5
Available Manuals
Section 1-7
PC programs can be written on-screen in ladder-diagram form as well as in mne-
monic form. As the program is written, it is displayed on a display, making con-
firmation and modification quick and easy. Syntax checks may also be per-
formed on the programs before they are downloaded to the PC.
The SSS comes on 3.5” disks.
A computer running the SSS is connected to the C200HX/HG/HE PC via the Pe-
ripheral Port on the CPU Unit using the CQM1-CIF02 or CV500-CIF01 cable.
1-7 Available Manuals
The following table lists other manuals that may be required to program and/or
operate the C200HX/HG/HE PCs. Operation Manuals and/or Operation Guides
are also provided with individual Units and are required for wiring and other
specifications.
Name
GPC Operation Manual
Cat. No.
W84
Contents
Programming procedures for the GPC
(Graphics Programming Console)
FIT Operation Manual
W150
Programming procedures for using the FIT
(Factory Intelligent Terminal)
SYSMAC Support Software Operation Manuals
Data Access Console Operation Guide
W247/W248
W173
Programming procedures for using the SSS
Data area monitoring and data modification
procedures for the Data Access Console
Printer Interface Unit Operation Guide
PROM Writer Operation Guide
W107
W155
W119
W120
Procedures for interfacing a PC to a printer
Procedures for writing programs to EPROM chips
Procedures for interfacing PCs to floppy disk drives
Floppy Disk Interface Unit Operation Guide
Wired Remote I/O System Manual
(SYSMAC BUS)
Information on building a Wired Remote I/O System
to enable remote I/O capability
Optical Remote I/O System Manual
(SYSMAC BUS)
W136
W135
W143
W114
Information on building an Optical Remote I/O
System to enable remote I/O capability
PC Link System Manual
Information on building a PC Link System to
automatically transfer data between PCs
Host Link System Manual
(SYSMAC WAY)
Information on building a Host Link System to
manage PCs from a ‘host’ computer
SYSMAC NET Link Unit Operation Manual
Information on building a SYSMAC NET Link
System and thus create an optical LAN integrating
PCs with computers and other peripheral devices
SYSMAC LINK System Manual
W174
Information on building a SYSMAC LINK System to
enable automatic data transfer, programming, and
programmed data transfer between the PCs in the
System
High-speed Counter Unit Operation Manual
Position Control Unit Operation Manuals
W141
Information on High-speed Counter Unit
NC111: W137 Information on Position Control Unit
NC112: W128
NC211: W166
Analog I/O Units Operation Guide
W127
Information on the C200H-AD001, C200H-DA001
Analog I/O Units
Analog Input Unit Operation Manual
Temperature Sensor Unit Operation Guide
ASCII Unit Operation Manual
W229
W124
W165
W153
W172
W208
W210
Information on the C200H-AD002 Analog Input Unit
Information on Temperature Sensor Unit
Information on ASCII Unit
ID Sensor Unit Operation Guide
Information on ID Sensor Unit
Information on Voice Unit
Voice Unit Operation Manual
Fuzzy Logic Unit Operation Manual
Fuzzy Support Software Operation Manual
Information on Fuzzy Logic Unit
Information on the Fuzzy Support Software which
supports the Fuzzy Logic Units
Temperature Control Unit Operation Manual
W225
W240
Information on Temperature Control Unit
Heat/Cool Temperature Control Unit Operation
Manual
Information on Heating and Cooling Temperature
Control Unit
6
C200HX/HG/HE Features
Section 1-8
Name
Cat. No.
W241
W224
Contents
Information on PID Control Unit
Information on Cam Positioner Unit
PID Control Unit Operation Manual
Cam Positioner Unit Operation Manual
1-8 C200HX/HG/HE Features
The C200HX/HG/HE CPU Units have a number of new features, but C200H and
C200HS programs can be used in the new CPU Units.
1-8-1 C200HS and C200HX/HG/HE Capabilities
The following table shows the new capabilities of the C200HX/HG/HE PCs and
compares them with those of the C200HS.
Function
Capability
C200HX/HG/HE
C200HS
15.2K words
Memory
User memory (UM)
C200HE-CPU11-E: 3.2K words
C200HE-CPUj 2-E: 7.2K words
C200HG-CPUj 3-E: 15.2K words
C200HX-CPUj 4-E: 31.2K words
Normal DM
6,144 words (DM 0000 to DM 6143)
6,144 words
(DM 0000 to DM 6143)
(The C200HE-CPU11-E doesn’t have
DM 4096 to DM 5999.)
Fixed DM
512 words (DM 6144 to DM 6655)
0 to 3,000 words (DM 7000 to DM 9999)
6,144 words (EM 0000 to EM 6143)
512 words
(DM 6144 to DM 6655)
Expansion DM
0 to 3,000 words
(DM 7000 to DM 9999)
Extended Data Memory
(EM)
None
C200HE: None
C200HG: 6,144 words × 1 bank
C200HX: 6,144 words × 3 banks
I/O allocation
Expansion Racks
3 Racks
2 Racks
(2 Racks in the C200HE-CPU j -E or
j
C200HX/HG-CPU3j -E/4j -E)
Group-2 Multipoint I/O
Units
Unit numbers 0 to 9, A to F
Unit numbers 0 to 9
(Incompatible with the C200HE-CPU11-E.)
(Unit numbers 0 to 9 with the
C200HE-CPUj 2-E,
C200HX/HG-CPU3j -E/4j -E.)
Special I/O Units
Unit numbers 0 to 9, A to F
Unit numbers 0 to 9
(Unit numbers 0 to 9 with the
C200HE-CPU j -E or
j
C200HX/HG-CPU3j -E/4j -E.)
Execution time
Basic instructions (LD)
MOV(21)
0.104 µs (C200HX)
0.156 µs (C200HG)
0.313 µs (C200HE)
0.417 µs (C200HX)
0.625 µs (C200HG)
1.250 µs (C200HE)
0.375 µs
19.00 µs
ADD(30)
16.65 µs (C200HX/HG)
40.10 µs
---
31.45 µs (C200HE)
Other instructions
C200HX/HG:
C200HE:
1/3 to 2/3 of C200HS time
3/4 to 4/5 of C200HS time
Common processes
(END(01) processing)
0.7 ms (C200HX/HG)
2.1 ms (C200HE)
0.7 ms
---
I/O refresh time
Same as the C200HS, although part of
Special I/O refreshing takes 1/2 to 2/3 the
C200HS time.
7
C200HX/HG/HE Features
Section 1-8
Function
Capability
C200HX/HG/HE
Available in the
C200HX/HG/HE-CPU4j -E/6j -E
C200HS
CPU Unit
functions
RS-232C port
Available in the
C200HS-CPU2j -E
/3j -E
Clock function
Available in all except the C200HE-CPU11-E Available in all models
SYSMAC NET Link and
Communications Boards can be installed in
Available in the
SYSMAC LINK functions all PCs except the C200HE-CPU11-E.
(Board model numbers:
C200HS-CPU3j -E
C200HW-COM01/04-E)
Communications ---
Boards
Communications Boards can be installed in
all PCs except the C200HE-CPU11-E. These
Boards can provide the following functions:
---
SYSMAC NET Link and SYSMAC LINK,
Communications Ports (Ports 1 and 2), and
Protocol Macro functions
Special I/O Units ---
The IORD(––) and IOWR(––) instructions
allow data to be transferred to and from
Special I/O Units.
---
Interrupts
Interrupt Input Units
2 Units (16 inputs)
Can be set.
1 Unit (8 inputs)
---
Communications Board
interrupts
Response characteristics Same as the C200HS, although a 1-ms
response is possible in the C200HW-SLK
Normal mode: 10 ms
High-speed mode: 1 ms
j
j
(Always 10 ms when a
SYSMAC NET Link or
SYSMAC LINK is used.)
PTs
---
NT Link (1:1) or NT Link (1:N)
NT Link (1:1)
(Up to 8 PTs can be connected from the
RS-232C port through an RS-422/485 Link
Adapter. When the C200HE-CPU j -E with
j
a Communications Board is used, only 3 PTs
can be connected)
SYSMAC LINK
Service time
3.5 ms max. (1 operating level)
10.8 ms max.
(1 operating level)
Remote programming
Effect on response time
Possible from the Peripheral Port or RS-232C Possible from the
Ports (including Communications Boards).
Peripheral Port.
None
10 ms in any mode
1-8-2 Program Compatibility
C200HS programs and Memory Cassettes can be used as is in the C200HX/
HG/HE and programs developed for the C200H can be transferred for use in the
C200HX/HG/HE very easily.
Detailed procedures for the individual steps involved in transferring programs
can be found in the SSS Operation Manuals. You will also require a
CQM1-CIF02 Connecting Cable to connect the computer running SSS to the
C200HS.
Precautions
Observe the following precautions when transferring C200H programs to the
C200HX/HG/HE.
• If a C200H program including the SET SYSTEM instruction (SYS(49)) is trans-
ferred to the C200HX/HG/HE, the operating parameters set by this instruction
will be transferred to the C200HX/HG/HE’s PC Setup area (DM 6600, DM
6601, and DM 6655) and overwrite any current settings. Be sure to confirm
that the settings in these words are correct before using the PC after program
transfer.
8
C200HX/HG/HE Features
Section 1-8
• If the C200H program accesses the C200H’s error log in DM 0969 to DM 0999,
the addresses of the words being accessed must be changed to DM 6000 to
DM 6030, which is the error log area for the C200HX/HG/HE.
• Any programs that rely on the execution cycle time (i.e., on the time required to
execute any one part of all of the program) must be adjusted when used on the
C200HX/HG/HE, which provides a much faster cycle time.
Using Internal Memory
The following procedure outlines the steps to transfer C200H programs to the
user memory inside the C200HX/HG/HE.
1, 2, 3...
1. Transfer the program and any other required data to the SSS work area.
This data can be transferred from a C200H CPU Unit, from floppy disk, or
from a C200HS Memory Unit.
To transfer from a C200H CPU Unit, set the PC for the SSS to the C200H,
connect the SSS to the C200H, go online, and transfer the program and any
other required data to the SSS work area. You will probably want to transfer
DM data and the I/O table, if you have created an I/O table for the C200H.
or To transfer from floppy disk, set the PC for the SSS to the C200H in the
offline mode and load the program and any other require data to the SSS
work area. You will probably want to load DM data and the I/O table, if you
have created an I/O table for the C200H.
or To transfer from a C200H-MP831, set the PC for the SSS to the C200H in the
offline mode and read data from the Memory Unit into the SSS work area.
2. Go offline if the SSS is not already offline.
3. Change the PC setting for the SSS to the C200HX/HG/HE.
4. If you want to transfer I/O comments together with the program to the
C200HX/HG/HE, allocate UM area for I/O comments.
5. Connect the SSS to the C200HX/HG/HE and go online.
6. Make sure that pin 1 on the C200HX/HG/HE’s CPU Unit is OFF to enable
writing to the UM area.
7. Transfer the program and and any other required data to the C200HX/HG/
HE. You will probably want to transfer DM data and the I/O table, if you have
created an I/O table for the C200H.
8. Turn OFF the C200HX/HG/HE and then back ON to reset it.
9. Test program execution before attempting actual operation.
Using Memory Cassettes
The following procedure outlines the steps to transfer C200H programs to the
C200HX/HG/HE via EEPROM or EPROM Memory Cassettes. This will allow
you to read the program data from the Memory Cassette automatically at
C200HX/HG/HE startup. The first four steps of this procedure is the same as
those used for transferring directly to the C200HX/HG/HE’s internal memory
(UM area).
1, 2, 3...
1. Transfer the program and any other required data to the SSS work area.
This data can be transferred from a C200H CPU Unit, from floppy disk, or
from a Memory Unit.
To transfer from a C200H CPU Unit, set the PC for the SSS to the C200H,
connect the SSS to the C200H, go online, and transfer the program and any
other required data to the SSS work area. You will probably want to transfer
DM data and the I/O table, if you have created an I/O table for the C200H.
or To transfer from floppy disk, set the PC for the SSS to the C200H in the
offline mode and load the program and any other required data to the SSS
work area. You will probably want to load DM data and the I/O table, if you
have created an I/O table for the C200H.
or To transfer from a C200H-MP831, set the PC for the SSS to the C200H in the
offline mode and read data from the Memory Unit into the SSS work area.
9
C200HX/HG/HE Features
Section 1-8
2. Go offline if the SSS is not already offline.
3. Change the PC setting for the SSS to the C200HX/HG/HE.
4. If you want to transfer I/O comments together with the program to the
C200HX/HG/HE, allocate UM area for I/O comments.
5. Allocate expansion DM words DM 7000 to DM 7999 in the UM area using the
UM allocation operation from the SSS.
6. Copy DM 1000 through DM 1999 to DM 7000 through DM 7999.
7. Write “0100” to DM 6602 to automatically transfer the contents of DM 7000
through DM 7999 to DM 1000 through DM 1999 at startup.
8. To transfer to an EEPROM Memory Cassette, use the following procedure.
a) Connect the SSS to the C200HX/HG/HE and go online.
b) Make sure that pin 1 on the C200HX/HG/HE’s CPU Unit is OFF to enable
writing to the UM area.
c) Transfer the program and any other require data to the C200HX/HG/HE.
You will probably want to transfer DM data and the I/O table, if you have
created an I/O table for the C200H. Make sure you specify transfer of the
Expansion DM Area and, if desired, the I/O Comment Area.
d) Turn ON SR 27000 from the SSS to transfer UM data to the Memory Cas-
sette and continue from step 9.
or To transfer to an EPROM Memory Cassette, use the following procedure.
a) Connect a PROM Writer to the SSS and write the data to the EPROM
chip using the SSS EPROM writing operation.
b) Set the ROM type selector on the Memory Cassette to the correct capac-
ity.
c) Mount the ROM chip to the Memory Cassette.
d) Mount a EPROM Memory Cassette to the C200HX/HG/HE.
9. Turn ON pin 2 on the C200HX/HG/HE’s DIP switch to enable automatic
transfer of Memory Cassette data to the CPU Unit at startup.
10. Turn OFF the C200HX/HG/HE and then back ON to reset it and transfer
data from the Memory Cassette to the CPU Unit.
11. Test program execution before attempting actual operation.
10
SECTION 2
Hardware Considerations
This section provides information on hardware aspects of the C200HX/HG/HE that are relevant to programming and software
operation. These include CPU Unit Components, the basic PC configuration, CPU Unit capabilities, and Memory Cassettes.
This information is covered in detail in the C200HX/HG/HE Installation Guide.
2-1 CPU Unit Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1-1 CPU Unit Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1-2 Peripheral Device Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2 PC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3 CPU Unit Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-4 Memory Cassettes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-4-1 Hardware and Software Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-4-2 Writing/Reading UM Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-4-3 Writing/Reading IOM Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-5 CPU Unit DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-6 Operating without a Backup Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
13
13
15
15
16
17
17
18
20
21
11
CPU Unit Components
Section 2-1
2-1 CPU Unit Components
The following diagram shows the main CPU Unit components.
Indicators
Memory Cassette
DIP switch
Communications Board
Peripheral port
RS-232C port
(The C200HW-COM06-E
is mounted to this CPU
Unit.)
Memory Cassette
The CPU Unit has a compartment to connect the Memory Cassette to the CPU
Unit. The Memory Cassette works as a RAM together with the built-in RAM of the
CPU Unit.
Peripheral Port
A peripheral device can be connected to the peripheral port.
The CPU Unit has a built-in RS-232C port.
RS-232C Port
Communications Board
The CPU Unit has a compartment to connect the Communications Board to the
CPU Unit.
DIP Switch
The PC operates according to the DIP switch settings of the CPU Unit. The DIP
switch of the CPU Unit for the C200HX/HG/HE has six pins. For the function of
each of the pins, refer to the following table. (All six pins are OFF when the PC is
shipped.)
O N
OFF⇔ ON
Pin Setting
Function
1
ON
Data cannot be written to the UM area.
OFF
ON
Data can be written to the UM area.
2
3
4
5
Memory Cassette data is read automatically at startup.
Memory Cassette data is not read automatically at startup.
Programming Console displays messages in English.
Programming Console displays messages in Japanese.
The expansion instructions can be set.
OFF
ON
OFF
ON
OFF
ON
The expansion instructions cannot be set (default setting).
Sets the following conditions for the communications port (including
when a CQM1-CIF02 is connected to the Peripheral Port):
1 start bit, 7 data bits, even parity, 2 stop bit, 9,600 bps baud rate
Cancels the above settings.
OFF
ON
6
Programming Console is in expansion terminal mode (AR 0712 is
turned ON).
OFF
Programming Console is in normal mode (AR 0712 is turned OFF).
12
CPU Unit Components
Section 2-1
2-1-1 CPU Unit Indicators
CPU Unit indicators provide visual information on the general operation of the
PC. Although not substitutes for proper error programming using the flags and
other error indicators provided in the data areas of memory, these indicators pro-
vide ready confirmation of proper operation.
Indicator
RUN (green)
ERR (red)
Meaning
Lit when the PC is operating normally.
Flashes if the PC detects any non-fatal error in operation. The PC
will continue operating.
Lit if the PC detects any fatal error in operation. The PC will stop
operating. After the PC stops operating, the RUN indicator will be
OFF and all output signals of the Output Units will be interrupted
(turned OFF).
INH (orange)
Lit when the Load OFF flag (AR bit) is ON, in which case all
output signals of the Output Units will be interrupted (turned
OFF).
COMM
(orange)
Flashes when the CPU Unit is communicating with the device
connected to the peripheral port or RS-232C port.
2-1-2 Peripheral Device Connection
A Programming Console or IBM PC/AT running SSS can be used to program
and monitor the C200HX/HG/HE PCs.
Programming Console
A C200H-PR027-E or CQM1-PRO01-E Programming Console can be con-
nected as shown in the diagram. The C200H-PR027-E is connected via the
C200H-CN222 or C200H-CN422 Programming Console Connecting Cable,
which must be purchased separately. A Connecting Cable is provided with the
CQM1-PRO01-E.
Data Access Console
A C200H-DAC01 Data Access Console can be connected via the C200H-
CN222 or C200H-CN422 Programming Console Connecting Cable, which must
be purchased separately. The following operations are not available when the
C200H-DAC01 is used with the C200HX/HG/HE:
Set value read and change
Error message display
13
CPU Unit Components
Section 2-1
IBM PC/AT with SSS
An IBM PC/AT or compatible computer with SYSMAC Support Software can be
connected as shown in the diagram.
C200H-LK201-V1
C200HX/HG/HE
Mounted
directly
Host Link Unit
RS-232C
port
Peripheral
port
Connecting
Cables
C200H-CN222/422
(2 m/4 m)
XW2Z-200S/500S
(See note)
CQM1-CIF02
Programming Console
Connecting Cable
Connecting Cable
Connecting Cable
C500-ZL3AT1-E
Peripheral
Device
Support
Software
IBM PC/AT or Compatible
SYSMAC Support Software
Programming Console
Programming Console for
C200H
Data Access Console for
C200H
C200H-PRO27-E
C200H-DAC01
CQM1-PRO01-E
Note The connector of the XW2Z-200S/500S Connecting Cable is a male 25-pin ter-
minal. An adapter is required for the 9-pin male D-sub terminal on the IBM PC/AT
or compatible side.
14
CPU Unit Capabilities
Section 2-3
2-2 PC Configuration
The basic PC configuration consists of two types of Rack: a CPU Rack and Ex-
pansion I/O Racks. The Expansion I/O Racks are not a required part of the basic
system. They are used to increase the number of I/O points. An illustration of
these Racks is provided in 3-3 IR Area. A third type of Rack, called a Slave Rack,
can be used when the PC is provided with a Remote I/O System.
CPU Racks
A C200HX/HG/HE CPU Rack consists of three components: (1) The CPU Back-
plane, to which the CPU Unit and other Units are mounted. (2) The CPU Unit,
which executes the program and controls the PC. (3) Other Units, such as I/O
Units, Special I/O Units, and Link Units, which provide the physical I/O terminals
corresponding to I/O points.
A C200HX/HG/HE CPU Rack can be used alone or it can be connected to other
Racks to provide additional I/O points. The CPU Rack provides three, five, eight,
or ten slots to which these other Units can be mounted depending on the back-
plane used.
Expansion I/O Racks
An Expansion I/O Rack can be thought of as an extension of the PC because it
provides additional slots to which other Units can be mounted. It is built onto an
Expansion I/O Backplane to which a Power Supply and up to ten other Units are
mounted.
An Expansion I/O Rack is always connected to the CPU Unit via the connectors
on the Backplanes, allowing communication between the two Racks. Up to three
Expansion I/O Racks (two with the C200HE PCs) can be connected in series to
the CPU Rack.
Unit Mounting Position
Only I/O Units and Special I/O Units can be mounted to Slave Racks. All I/O
Units, Special I/O Units, Group-2 High-density I/O Units, Remote I/O Master
Units, PC and Host Link Units, can be mounted to any slot on all other Racks.
Interrupt Input Units must be mounted to Backplanes with the “-V2” suffix on the
model number.
Refer to the C200HX/HG/HE Installation Guide for details about which slots can
be used for which Units and other details about PC configuration. The way in
which I/O points on Units are allocated in memory is described in 3-3 IR Area.
2-3 CPU Unit Capabilities
The following table shows the capabilities of the C200HX/HG/HE CPU Units.
The CPU4j-E and CPU6j-E CPU Units are equipped with RS-232C ports.
Item
C200HE-
C200HG-
C200HX-
CPU11-E CPU32-E/ CPU33-E/ CPU53-E/ CPU34-E/ CPU54-E/
42-E
43-E
63-E
44-E
64-E
Program capacity
DM capacity
3.2K words 7.2K words 15.2K words
31.2K words
6K words
4K words
None
6K words
10 Units
6K words
EM capacity
6K words × 1 bank
6K words × 3 banks
0.1 µs min.
Basic instruction execution time
0.3 µs min.
2 Racks
0.15 µs min.
2 Racks
Max. number of Expansion I/O Racks
3 Racks
2 Racks
3 Racks
16 Units
Max. number of Group-2 High-density I/O None
Units
10 Units
16 Units
10 Units
Max. number of Special I/O Units
Clock function
10 Units
10 Units
Yes
16 Units
10 Units
Yes
16 Units
No
No
Yes
Yes
Communications Board Slot
Yes
Yes
15
Memory Cassettes
Section 2-4
2-4 Memory Cassettes
The C200HX/HG/HE comes equipped with a built-in RAM for the user’s pro-
gram, so a normal program be created even without installing a Memory Cas-
sette. An optional Memory Cassette can be used to store the program, PC Set-
up, I/O comments, DM area and other data area contents. Refer to the C200HX/
HG/HE Installation Guide for details on installing Memory Cassettes.
Memory Cassette Functions The Memory Cassette can be used to store and retrieve UM and IOM data; UM
stored in the Memory Cassette can also be compared to the UM in the PC.
1, 2, 3...
1. The contents of UM (user memory) can be stored in the Memory Cassette
for later retrieval or verification. If pin 2 of the CPU Unit DIP switch is set to
ON, the contents of the Memory Cassette are automatically retrieved when
the PC is turned ON.
The UM area contains the ladder program, fixed DM (such as the PC Setup),
expansion DM, I/O comments, the I/O table, and the UM area allocation in-
formation.
2. The contents of the PC’s I/O memory (IOM) can be stored in the Memory
Cassette for later retrieval.
IOM includes the IR area, SR area, LR area, HR area, AR area, timer and
counter PVs, DM 0000 through DM 6143, and EM 0000 through EM 6143.
UM and IOM data is completely compatible between the C200HX/HG/HE and
the C200HS data, except the portion of the C200HX/HG/HE data areas that ex-
ceed the capacity of the C200HS and the new instructions (BXF2(––),
IEMS(––), IORD(––), IOWR(––), PMCR(––), STUP(––), and XFR2(––)) that
aren’t supported by the C200HS CPU Unit. Data area addresses and instruc-
tions that aren’t supported by the C200HS can’t be used in the C200HS. IOM
data can’t be retrieved to the PC’s RAM unless the size of the IOM in the Memory
Cassette matches the size of the IOM in the PC.
Compatible Memory
Cassettes
There are two types of Memory Cassette available: EEPROM and EPROM. The
following table shows the Memory Cassettes which can be used with the
C200HX/HG/HE PCs.
Memory
Capacity
Model number
Comments
EEPROM
The EEPROM Memory Cassette
can be used to write and read UM
and I/O data to the CPU Unit. It does
not require any backup power sup-
ply and will retain its data even after
it is removed from the CPU Unit.
4K words
C200HW-ME04K
8K words
C200HW-ME08K
16K words C200HW-ME16K
32K words C200HW-ME32K
EPROM
16K or 32K C200HS-MP16K The EPROM chip is not included
words
with the Memory Cassette; it must
be purchased separately.
27256 equivalent (ROM-JD-B): 16K
27512 equivalent (ROM-KD-B): 32K
Note 1. Data stored in EEPROM won’t be reliable after the contents have been over-
written 50,000 times.
2. Use a standard PROM writer to write a program to the EPROM Memory
Cassette. Connect an EPROM to the EPROM Memory Cassette before
installing the EPROM Memory Cassette to the CPU Unit. The EPROM
Memory Cassette will lose its data if it is removed from the CPU Unit.
16
Memory Cassettes
Section 2-4
2-4-1 Hardware and Software Settings
The hardware and software settings related to Memory Cassette operations are
described below.
Switch Settings
Switch 1 on the Memory Cassette is turned OFF when the Memory Cassette is
shipped. Check the setting on switch 1 before installation.
Memory Switch 1
Function
Cassette
setting
EEPROM
ON
The data in the Memory Cassette is write-protected.
The data in the Memory Cassette can be overwritten.
OFF
ON
EPROM
27512-equivalent ROM-KD-B EPROM
(32K words, 150 ns access time)
OFF
27256-equivalent ROM-JD-B EPROM
(16K words, 150 ns access time)
SR Area Flags and Control
Bits
SR 269 through SR 273 contain flags and control bits related to Memory Cas-
sette contents and operation. Refer to 3-4 SR (Special Relay) Area for details.
2-4-2 Writing/Reading UM Data
Use the following procedures to transfer UM data to or from a Memory Cassette.
(A PROM writer is required to write data to an EPROM Memory Cassette. Refer
to the SYSMAC Support Software Operation Manual for details.)
Note UM contains the ladder program, fixed DM (such as the PC Setup), expansion
DM, I/O comments, the I/O table, and the UM area allocation information.
Writing UM Data to a
Memory Cassette
Use the following procedure to write UM data to an EEPROM Memory Cassette.
1, 2, 3...
1. Before turning ON the C200HX/HG/HE’s power supply, make sure that
switch 1 on the Memory Cassette is set to OFF.
2. Turn ON the C200HX/HG/HE and write the ladder program or read an exist-
ing program from a data disk.
3. Switch the C200HX/HG/HE to PROGRAM mode.
4. Use a host computer running SSS or a Programming Console to turn ON
SR 27000 (the Save UM to Cassette Bit). The data will be written from the
PC to the Memory Cassette. SR 27000 will be turned OFF automatically af-
ter the data transfer has been completed.
5. If you want to write-protect the data on the Memory Cassette, turn OFF the
PC and set switch 1 of the Memory Cassette to ON. If this switch is ON, data
in the Memory Cassette will be retained even if SR 27000 is turned ON.
Reading UM Data from a
Memory Cassette
There are two ways to read UM data from a Memory Cassette: automatic trans-
fer at startup or a one-time transfer using a Peripheral Device.
(There is no function that automatically writes data to the Memory Cassette.)
Automatic Transfer at Startup:
1, 2, 3...
1. Turn ON pin 2 of the CPU Unit’s DIP switch.
2. Install the Memory Cassette containing the data into the C200HX/HG/HE.
3. Turn ON the C200HX/HG/HE’s power supply. The contents of the Memory
Cassette will be transferred to the CPU Unit automatically. A memory error
will occur if the data couldn’t be transferred.
One-time Transfer using a Peripheral Device:
1, 2, 3...
1. Install the Memory Cassette containing the data into the C200HX/HG/HE.
2. Turn ON the C200HX/HG/HE and switch it to PROGRAM mode.
3. Use a host computer running SSS or a Programming Console to turn ON
SR 27001 (the Load UM from Cassette Bit). The data will be read from the
Memory Cassette to the PC. SR 27001 will be turned OFF automatically af-
ter the data transfer has been completed.
17
Memory Cassettes
Section 2-4
Comparing UM Data on a
Memory Cassette
Use the following procedure to the UM data on an Memory Cassette to the UM
data in the PC.
1, 2, 3...
1. Switch the C200HX/HG/HE to PROGRAM mode.
2. Use a host computer running SSS or a Programming Console to turn ON
SR 27002 (the Compare UM to Cassette Bit). The data will be compared be-
tween the PC and the Memory Cassette. SR 27002 will be turned OFF auto-
matically after the data comparison has been completed.
3. Use a host computer running SSS or a Programming Console to check the
status of SR 27003 (the Comparison Results Flag).
Note If data verification is executed in a mode other than the PROGRAM mode, an
operation continuance error (FAL90) will occur and 27002 will turn ON (1). Al-
though 27003 will also turn ON, comparison will not be performed. If data com-
parison is executed without mounting the Memory Cassette, 27003 will turn ON
(1).
2-4-3 Writing/Reading IOM Data
Use the following procedures to transfer IOM data to or from a Memory Cas-
sette. (A PROM writer is required to write data to an EPROM Memory Cassette.
Refer to the SYSMAC Support Software Operation Manual for details.)
IOM includes the IR area, SR area, LR area, HR area, AR area, timer and count-
er PVs, DM 0000 through DM 6143, and EM 0000 through EM 6143.
The capacity of the Memory Cassette must match the memory capacity of the
CPU Unit when IOM data is transferred to or from a Memory Cassette. The
memory requirements are as follows:
Writing IOM: CPU Unit’s capacity ≤ Memory Cassette’s capacity
Reading IOM: CPU Unit’s capacity = Amount of IOM data in Memory Cas-
sette
Note In C200HS PCs, the data transfer will be performed even if the memory capaci-
ties don’t match, an error which can easily go unnoticed.
The following table shows the Memory Cassette capacity required to store 1 or
more banks of EM.
Memory Cassette capacity
Number of EM banks
4K words
None (A 4K-word Memory Cassette can’t be used to
store other IOM data, either.)
8K words
16K words
32K words
None
1 bank (Only EM bank 0 can be stored.)
3 banks (EM banks 0 through 2 can be stored.)
Bits 08 through 15 of SR 273 indicate the EM bank number of the IOM data
stored in the Memory Cassette.
Content of
Meaning
SR 27308 to SR 27315
00
There is no Memory Cassette installed, no IOM data in
the Memory Cassette, or no EM data in the Memory Cas-
sette.
01
04
The Memory Cassette contains IOM data that includes
EM bank 0 only.
The Memory Cassette contains IOM data that includes
EM banks 0 through 2.
Writing IOM Data to a
Memory Cassette
Use the following procedure to write IOM data to an EEPROM Memory Cas-
sette.
1, 2, 3...
1. Before turning ON the C200HX/HG/HE’s power supply, make sure that
switch 1 on the Memory Cassette is set to OFF.
18
Memory Cassettes
Section 2-4
2. Turn ON the C200HX/HG/HE and switch it to PROGRAM mode.
3. Use a host computer running SSS or a Programming Console to turn ON
SR 27300 (the Save IOM to Cassette Bit). The data will be written from the
PC to the Memory Cassette. SR 27300 will be turned OFF automatically af-
ter the data transfer has been completed.
4. If you want to write-protect the data on the Memory Cassette, turn OFF the
PC and set switch 1 of the Memory Cassette to ON. If this switch is ON, data
in the Memory Cassette will be retained even if SR 27300 is turned ON.
Reading IOM Data from a
Memory Cassette
Use the following procedure to read IOM data from a Memory Cassette. The
contents of the error history (DM 6000 through DM 6030) can’t be read from the
Memory Cassette.
Note There is no function that automatically reads IOM data from the Memory Cas-
sette.
1, 2, 3...
1. Install the Memory Cassette containing the data into the C200HX/HG/HE.
2. Turn ON the C200HX/HG/HE and switch it to PROGRAM mode.
3. Use a host computer running SSS or a Programming Console to turn ON
SR 27301 (the Load IOM from Cassette Bit). The data will be read from the
Memory Cassette to the PC. SR 27301 will be turned OFF automatically af-
ter the data transfer has been completed.
19
CPU Unit DIP Switch
Section 2-5
2-5 CPU Unit DIP Switch
The 6 pins on the DIP switch control 6 of the CPU Unit’s operating parameters.
Pin
Item
Memory protect
Setting
ON
Function
1
1
The UM area cannot be overwritten from a Peripheral Device.
1
OFF
ON
The UM area can be overwritten from a Peripheral Device.
2
3
Automatic transfer of Memory
Cassette contents
The contents of the Memory Cassette will be automatically
transferred to the internal RAM at start-up.
OFF
ON
The contents will not be automatically transferred.
Message language
Programming Console messages will be displayed in English.
OFF
Programming Console messages will be displayed in the language
stored in system ROM. (Messages will be displayed in Japanese with
the Japanese version of system ROM.)
4
5
Expansion instruction setting
Communications parameters
ON
Expansion instructions will be set by user. Normally ON when using a
host computer for programming/monitoring.
OFF
ON
Expansion instructions will be set to defaults.
Standard communications parameters (see note 1) will be set for the
following serial communications ports.
• Built-in RS-232C port
• Peripheral port (only when a CQM1-CIF01/-CIF02 Cable is con-
nected. Does not apply to Programming Console.)
Note
1. Standard communications parameters are as follows:
Serial communications mode: Host Link or peripheral bus;
start bits: 1; data length: 7 bits; parity: even; stop bits: 2;
baud rate: 9,600 bps
2. The CX-Programmer running on a personal computer can
be connected to the peripheral port via the peripheral bus
using the above standard communications parameters.
OFF
The communications parameters for the following serial
communications ports will be set in PC Setup as follows:
• Built-in RS-232C port: DM 6645 and DM 6646
• Peripheral port: DM 6650 and DM 6651
Note When the CX-Programmer is connected to the peripheral port
with the peripheral bus, either set bits 00 to 03 of DM 6650 in the
Fixed DM Area to 0 Hex (for standard parameters), or set bits 12
to 15 of DM 6650 to 0 Hex and bits 00 to 03 of DM 6650 to 1 Hex
(for Host Link or peripheral bus ) separately.
6
Expansion TERMINAL mode
setting when AR 0712 is ON
ON
Expansion TERMINAL mode (Programming Console); AR 0712 ON.
Normal mode (Programming Console); AR 0712: OFF
OFF
Note 1. The UM area contains the ladder program, fixed DM (including the PC Set-
up), expansion DM, I/O comments, the I/O table, and the UM area allocation
information.
2. All six pins are set to OFF when the PC is shipped.
20
Operating without a Backup Battery
Section 2-6
2-6 Operating without a Backup Battery
An EEPROM or EPROM Memory Cassette can be used together with various
memory settings to enable operation without a backup battery. The following
conditions must be met.
1, 2, 3...
1. The user program must be written to an EPROM or EEPROM Memory Cas-
sette.
2. The clock cannot be used. (A battery is required to run the internal clock.)
3. The PC Setup must be set to not detect low battery voltage.
4. The system must be designed to run properly even if DM area data is lost.
5. The Output OFF Bit (SR 25215) must be programmed to remain OFF. (The
status of this bit will be unstable without a battery.)
25314 (Always OFF Flag)
25215
6. The Forced Status Hold Bit (SR 25211) and Data Retention Control Bit
(SR 25212) must be set to be cleared in the PC Setup. (The status of these
bits will be unstable without a battery.)
7. The DIP switch on the CPU Unit must be set so that pin 1 is OFF and pin 2 is
ON.
If these conditions can be met, use the following procedures to operate without a
backup battery.
EEPROM Memory Cassette
1, 2, 3...
1. Allocate UM area using the SYSMAC Support Software (SSS) if you want to
use Expansion DM for Special I/O Units or if you want to store I/O comments
in the PC.
2. Write and transfer the user program, including a line using the Always OFF
Flag (SR 25314) to ensure that the Output OFF Bit (SR 25215) remains
OFF.
25314 (Always OFF Flag)
25215
3. Set the following in the PC Setup
DM 6601 = 0000 (To reset Forced Status Hold Bit (SR 25211) and I/O Status
Hold Bit (SR 25212) at startup)
DM 6655 bits 12 to 15 = 1, bits 4 to 7 = 0 (To not detect low battery voltage)
DM 6600 and DM 6602 to DM 6654 = As required by the application.
4. Set Fixed DM (including the Communications Board settings in DM 6144 to
DM 6599) and Expansion DM as required by the application.
5. Check operation.
6. Mount the Memory Cassette in the CPU Unit.
7. Switch to PROGRAM mode.
8. Turn ON SR 27000 to transfer the program, Fixed DM, and the PC Setup to
the Memory Cassette. (This bit will automatically reset itself if turned ON
from a Programming Console. It will need to be turned OFF by clearing
forced status if it is set from the SSS.)
9. Turn ON the write protect switch on the Memory Cassette.
10. Turn OFF pin 1 and turn ON pin 2 on the DIP switch on the CPU Unit to auto-
matically transfer the program, Fixed DM, and the PC Setup from the
Memory Cassette when power is turned ON.
21
Operating without a Backup Battery
Section 2-6
EPROM Memory Cassette
1, 2, 3...
1. Allocate UM area using the SYSMAC Support Software (SSS) if you want to
use Expansion DM for Special I/O Units or if you want to store I/O comments
in the PC.
2. Write and transfer the user program, including a line using the Always OFF
Flag (SR 25314) to ensure that the Output OFF Bit (SR 25215) remains
OFF.
25314 (Always OFF Flag)
25215
3. Set the following in the PC Setup
DM 6601 = 0000 (To reset Forced Status Hold Bit (SR 25211) and I/O Status
Hold Bit (SR 25212) at startup)
DM 6655 bits 12 to 15 = 1, bits 4 to 7 = 0 (To not detect low battery voltage)
DM 6600 and DM 6602 to DM 6654 = As required by the application.
4. Set Fixed DM (including the Communications Board settings in DM 6144 to
DM 6599) and Expansion DM as required by the application.
5. Check operation.
6. Transfer the program, Fixed DM, and the PC Setup to the SSS.
7. Write the program, Fixed DM, and the PC Setup to ROM using the SSS and
a PROM writer.
8. Mount the ROM onto the Memory Cassette.
9. Mount the Memory Cassette in the CPU Unit.
10. Turn OFF pin 1 and turn ON pin 2 on the DIP switch on the CPU Unit to auto-
matically transfer the program, Fixed DM, and the PC Setup from the
Memory Cassette when power is turned ON.
22
SECTION 3
Memory Areas
Various types of data are required to achieve effective and correct control. To facilitate managing this data, the PC is provided
with various memory areas for data, each of which performs a different function. The areas generally accessible by the user
for use in programming are classified as data areas. The other memory area is the UM Area, where the user’s program is
actually stored. This section describes these areas individually and provides information that will be necessary to use them. As
a matter of convention, the TR area is described in this section, even though it is not strictly a memory area.
3-1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
25
3-1-1
3-1-2
Data Area Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IR/SR Area Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2
3-3
3-4
Data Area Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IR (Internal Relay) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SR (Special Relay) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
29
33
38
39
40
41
42
42
42
42
43
43
43
43
44
44
44
44
44
45
45
46
46
47
47
47
48
48
48
48
48
48
3-4-1
SYSMAC NET/SYSMAC LINK System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Remote I/O Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link System Flags and Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Forced Status Hold Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Status Hold Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output OFF Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FAL (Failure Alarm) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Battery Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cycle Time Error Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Verification Error Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
First Cycle Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Pulse Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Step Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Group-2 Error Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Unit Error Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Execution Error Flag, ER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arithmetic Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Subroutine Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RS-232C Port Communications Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Port Communications Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Cassette Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transfer Error Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ladder Diagram Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Save Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transfer Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PC Setup Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock and Keyboard Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Group-2 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special I/O Unit Restart Bits and Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4-2
3-4-3
3-4-4
3-4-5
3-4-6
3-4-7
3-4-8
3-4-9
3-4-10
3-4-11
3-4-12
3-4-13
3-4-14
3-4-15
3-4-16
3-4-17
3-4-18
3-4-19
3-4-20
3-4-21
3-4-22
3-4-23
3-4-24
3-4-25
3-4-26
3-4-27
3-4-28
3-4-29
3-4-30
3-5
AR (Auxiliary Relay) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
50
51
51
51
52
52
52
53
53
54
54
54
55
55
55
55
55
55
3-5-1
Restarting Special I/O Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Rack Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Group-2 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optical I/O Unit and I/O Terminal Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSMAC LINK System Data Link Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error History Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Node Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSMAC LINK/SYSMAC NET Link System Service Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calendar/Clock Area and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TERMINAL Mode Key Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power OFF Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSMAC LINK – Peripheral Device Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cycle Time Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Unit Mounted Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Unit-mounting Device Mounted Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FPD Trigger Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Tracing Flags and Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cycle Time Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5-2
3-5-3
3-5-4
3-5-5
3-5-6
3-5-7
3-5-8
3-5-9
3-5-10
3-5-11
3-5-12
3-5-13
3-5-14
3-5-15
3-5-16
3-5-17
3-5-18
3-6
DM (Data Memory) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
57
58
58
60
65
67
3-6-1
3-6-2
3-6-3
3-6-4
3-6-5
3-6-6
Expansion DM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special I/O Unit Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error History Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PC Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Communications Board Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special I/O Unit Area Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7
3-8
3-9
HR (Holding Relay) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TC (Timer/Counter) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LR (Link Relay) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
68
69
70
71
71
71
72
3-10 UM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-11 TR (Temporary Relay) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-12 EM (Extended Data Memory) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-12-1
3-12-2
Using the EM Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Current EM Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
Introduction
Section 3-1
3-1 Introduction
3-1-1 Data Area Overview
Details, including the name, size, and range of each area are summarized in the
following table. Data and memory areas are normally referred to by their acro-
nyms, e.g., the IR Area, the SR Area, etc.
Area
Size
3,776 bits
Range
Comments
Internal Relay Area 1
IR 000 to IR 235
Refer to 3-1-2 IR/SR Area Overview and 3-3 IR
(Internal Relay) Area for more details.
Refer to 3-1-2 IR/SR Area Overview and 3-4 SR
(Special Relay) Area for more details.
Special Relay Area 1
Special Relay Area 2
Internal Relay Area 2
312 bits
704 bits
3,392 bits
SR 236 to SR 255
SR 256 to SR 299
IR 300 to IR 511
Refer to 3-1-2 IR/SR Area Overview and 3-3 IR
(Internal Relay) Area for more details.
Temporary Relay Area
8 bits
TR 00 to TR 07
Used to temporarily store and retrieve execution
conditions when programming certain types of
branching ladder diagrams.
Holding Relay Area
Auxiliary Relay Area
Link Relay Area
1,600 bits
448 buts
1,024 bits
HR 00 to HR 99
AR 00 to AR 27
LR 00 to LR 63
Used to store data and to retain the data values
when the power to the PC is turned OFF.
Contains flags and bits for special functions. Re-
tains status during power failure.
Used for data links in the PC Link System.
(These bits can be used as work words or work
bits when not used in the PC Link System.)
Timer/Counter Area
Data Memory Area
512 counters/
timers
TC 000 to TC 511
Used to define timers and counters, and to
access completion flags, PV, and SV.
TIM 000 through TIM 015 are refreshed via
interrupt processing as high-speed timers.
6,144 words
DM 0000 to DM 6143 Read/Write
DM 6031 is used for indirect DM addressing and
EM bank information and should not be written
by the user.
1,000 words DM 0000 to DM 0999 Normal DM.
2,600 words DM 1000 to DM 2599 Special I/O Unit Area
3,400 words DM 2600 to DM 5999 Normal DM.
31 words
DM 6000 to DM 6030 History Log
(44 words)
DM 6100 to DM 6143 Link test area (reserved)
DM 6144 to DM 6599 Fixed DM Area (read only)
DM 6600 to DM 6655 PC Setup
Fixed DM Area
512 words
56 words
Extended Data Memory 6,144 words
Area
EM 0000 to EM 6143 The amount of EM area memory depends on the
PC model being used. PCs are available with no
EM, one 6,144-word bank, or three 6,144-word
banks.
Like DM, the EM memory can be accessed in
word units only and EM area data is retained
when the power to the PC is turned OFF.
Work Bits and Words
When some bits and words in certain data areas are not being used for their in-
tended purpose, they can be used in programming as required to control other
bits. Words and bits available for use in this fashion are called work words and
work bits. Most, but not all, unused bits can be used as work bits. Those that can
be used are described area-by-area in the remainder of this section. Actual ap-
plication of work bits and work words is described in Section 4 Writing and Input-
ting the Program.
Flags and Control Bits
Some data areas contain flags and/or control bits. Flags are bits that are auto-
matically turned ON and OFF to indicate particular operation status. Although
24
Data Area Structure
Section 3-2
some flags can be turned ON and OFF by the user, most flags are read only; they
cannot be controlled directly.
Control bits are bits turned ON and OFF by the user to control specific aspects of
operation. Any bit given a name using the word bit rather than the word flag is a
control bit, e.g., Restart bits are control bits.
3-1-2 IR/SR Area Overview
When designating a data area, the acronym for the area is always required for
any area except the IR and SR areas. Although the acronyms for the IR and SR
areas are given for clarity in text explanations, they are not required, and not en-
tered, when programming.
The IR and SR areas are divided into two 256-word sections; the boundary be-
tween these sections is located in the SR area between SR 255 and SR 256.
When the SR area is used as an operand in an instruction, the operand cannot
cross over this boundary. Also, basic instructions that access bits in the second
section (SR 25600 through IR 51115) have somewhat longer execution times.
Area
I/O Area 1
Range
Comments
IR Area 1
IR 000 to IR 029
I/O words are allocated to the CPU Rack and
Expansion I/O Racks by slot position.
Group-2 High-density I/O Unit IR 030 to IR 049
and B7A Interface Unit Area
Allocated to Group-2 High-density I/O Units and to
B7A Interface Units 0 to 9.
SYSMAC BUS and
CompoBus/D Output Area
IR 050 to IR 099
Allocated to CompoBus/D outputs and Remote
I/O Slave Racks 0 to 4.
Special I/O Unit Area 1
IR 100 to IR 199
IR 200 to IR 231
Allocated to Special I/O Units 0 to 9.
Optical I/O Unit and I/O
Terminal Area
Allocated to Optical I/O Units and I/O Terminals.
Work Area
IR 232 to IR 235
For use as work bits in the program.
SR Area 1
SR Area 2
SR 23600 to SR 25507 Contains system clocks, flags, control bits, and
status information.
SR 256 to SR 299
Contains flags, control bits, and status informa-
tion. SR 290 to SR 297 are used as I/O words by
MCRO(99).
IR Area 2
I/O Area 2
Work Area
IR 300 to IR 309
IR 310 to IR 329
These I/O words are allocated to a third
Expansion I/O Rack by slot position.
For use as work bits in the program.
Group-2 High-density I/O Unit IR 330 to IR 341
Area 2
Allocated to Group-2 High-density I/O Units.
Work Area
IR 342 to IR 349
IR 350 to IR 399
IR 400 to IR 459
IR 460 to IR 511
For use as work bits in the program.
Allocated to CompoBus/D inputs.
Allocated to Special I/O Units A to F.
For use as work bits in the program.
CompoBus/D Input Area
Special I/O Unit Area 2
Work Area
Note 1. Refer to 3-3 IR (Internal Relay) Area for more details on the IR area.
Refer to 3-4 SR (Special Relay) Area for more details on the SR area.
2. Bits in IR Area 1 and IR Area 2 can can be used in programming as work bits
when not used for their allocated purpose.
3-2 Data Area Structure
When designating a data area, the acronym for the area is always required for
any but the IR and SR areas. Although the acronyms for the IR and SR areas are
often given for clarity in text explanations, they are not required, and not entered,
when programming. Any data area designation without an acronym is assumed
to be in either the IR or SR area. Because IR and SR addresses run consecutive-
ly, the word or bit addresses are sufficient to differentiate these two areas.
25
Data Area Structure
Section 3-2
An actual data location within any data area but the TC area is designated by its
address. The address designates the bit or word within the area where the de-
sired data is located. The TC area consists of TC numbers, each of which is used
for a specific timer or counter defined in the program. Refer to 3-8 TC Area for
more details on TC numbers and to 5-14 Timer and Counter Instructions for in-
formation on their application.
The rest of the data areas (i.e., the IR, SR, HR, DM, AR, and LR areas) consist of
words, each of which consists of 16 bits numbered 00 through 15 from right to
left. IR words 000 and 001 are shown below with bit numbers. Here, the content
of each word is shown as all zeros. Bit 00 is called the rightmost bit; bit 15, the
leftmost bit.
The term least significant bit is often used for rightmost bit; the term most signifi-
cant bit, for leftmost bit. These terms are not used in this manual because a
single data word is often split into two or more parts, with each part used for dif-
ferent parameters or operands. When this is done, the rightmost bits of a word
may actually become the most significant bits, i.e., the leftmost bits in another
word,when combined with other bits to form a new word.
Bit number
IR word 000
IR word 001
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The DM area is accessible by word only; you cannot designate an individual bit
within a DM word. Data in the IR, SR, HR, AR, and LR areas is accessible either
by word or by bit, depending on the instruction in which the data is being used.
To designate one of these areas by word, all that is necessary is the acronym (if
required) and the two-, three-, or four-digit word address. To designate an area
by bit, the word address is combined with the bit number as a single four- or five-
digit address. The following table show examples of this. The two rightmost dig-
its of a bit designation must indicate a bit between 00 and 15, i.e., the rightmost
digit must be 5 or less the next digit to the left, either 0 or 1.
The same TC number can be used to designate either the present value (PV) of
the timer or counter, or a bit that functions as the Completion Flag for the timer or
counter. This is explained in more detail in 3-8 TC Area.
Area
Word designation
Bit designation
00015 (leftmost bit in word 000)
25200 (rightmost bit in word 252)
Not possible
IR
000
252
SR
DM
TC
LR
DM 1250
TC 215 (designates PV)
LR 12
TC 215 (designates completion flag)
LR 1200
Data Structure
Word data input as decimal values is stored in binary-coded decimal (BCD);
word data entered as hexadecimal is stored in binary form. Each four bits of a
word represents one digit, either a hexadecimal or decimal digit, numerically
equivalent to the value of the binary bits. One word of data thus contains four
digits, which are numbered from right to left. These digit numbers and the corre-
sponding bit numbers for one word are shown below.
Digit number
3
2
1
0
Bit number
Contents
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
When referring to the entire word, the digit numbered 0 is called the rightmost
digit; the one numbered 3, the leftmost digit.
26
Data Area Structure
Section 3-2
When inputting data into data areas, it must be input in the proper form for the
intended purpose. This is no problem when designating individual bits, which
are merely turned ON (equivalent to a binary value of 1) or OFF (a binary value of
0). When inputting word data, however, it is important to input it either as decimal
or as hexadecimal, depending on what is called for by the instruction it is to be
used for. Section 5 Instruction Set specifies when a particular form of data is re-
quired for an instruction.
Converting Different Forms Binary and hexadecimal can be easily converted back and forth because each
of Data
four bits of a binary number is numerically equivalent to one digit of a hexadeci-
mal number. The binary number 0101111101011111 is converted to hexadeci-
mal by considering each set of four bits in order from the right. Binary 1111 is
hexadecimal F; binary 0101 is hexadecimal 5. The hexadecimal equivalent
3
2
would thus be 5F5F, or 24,415 in decimal (16 x 5 + 16 x 15 + 16 x 5 + 15).
Decimal and BCD are easily converted back and forth. In this case, each BCD
digit (i.e., each group of four BCD bits) is numerically equivalent of the corre-
sponding decimal digit. The BCD bits 0101011101010111 are converted to deci-
mal by considering each four bits from the right. Binary 0101 is decimal 5; binary
0111 is decimal 7. The decimal equivalent would thus be 5,757. Note that this is
not the same numeric value as the hexadecimal equivalent of
0101011101010111, which would be 5,757 hexadecimal, or 22,359 in decimal
3
2
(16 x 5 + 16 x 7 + 16 x 5 + 7).
Because the numeric equivalent of each four BCD binary bits must be numeri-
cally equivalent to a decimal value, any four bit combination numerically greater
than 9 cannot be used, e.g., 1011 is not allowed because it is numerically equiva-
lent to 11, which cannot be expressed as a single digit in decimal notation. The
binary bits 1011 are of course allowed in hexadecimal are a equivalent to the
hexadecimal digit C.
There are instructions provided to convert data either direction between BCD
and hexadecimal. Refer to 5-18 Data Conversion for details. Tables of binary
equivalents to hexadecimal and BCD digits are provided in the appendices for
reference.
Decimal Points
Decimal points are used in timers only. The least significant digit represents
tenths of a second. All arithmetic instructions operate on integers only.
Signed and Unsigned Binary Data
This section explains signed and unsigned binary data formats. Many instruc-
tions can use either signed or unsigned data and a few (CPS(––), CPSL(––),
DBS(––), DBSL(––), MBS(––), and MBSL(––)) use signed data exclusively.
Unsigned binary
Unsigned binary is the standard format used in OMRON PCs. Data in this manu-
al are unsigned unless otherwise stated. Unsigned binary values are always
positive and range from 0 ($0000) to 65,535 ($FFFF). Eight-digit values range
from 0 ($0000 0000) to 4,294,967,295 ($FFFF FFFF).
3
2
1
0
Digit value
16
16
16
16
Bit number
Contents
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
27
Data Area Structure
Section 3-2
Signed Binary
Signed binary data can have either a positive and negative value. The sign is
indicated by the status of bit 15. If bit 15 is OFF, the number is positive and if bit 15
is ON, the number is negative. Positive signed binary values range from 0
($0000) to 32,767 ($7FFF), and negative signed binary values range from
–32,768 ($8000) to –1 ($FFFF).
Sign indicator
Digit value
3
2
1
0
16
16
16
16
Bit number
Contents
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Eight-digit positive values range from 0 ($0000 0000) to 2,147,483,647 ($7FFF
FFFF), and eight-digit negative values range from –2,147,483,648 ($8000
0000) to –1 ($FFFF FFFF).
The following table shows the corresponding decimal, 16-bit hexadecimal, and
32-bit hexadecimal values.
Decimal
2147483647
16-bit Hex
---
32-bit Hex
7FFFFFFF
2147483646
---
7FFFFFFE
.
.
.
.
.
.
.
.
.
---
32768
32767
00008000
00007FFF
7FFF
32766
7FFE
00007FFE
.
.
.
.
.
.
.
.
.
2
1
0
0002
0001
0000
FFFF
00000002
00000001
00000000
FFFFFFFF
–1
–2
FFFE
FFFFFFFE
.
.
.
.
.
.
.
.
.
–32767
–32768
–32769
8001
8000
FFFF8001
FFFF8000
FFFF7FFF
---
.
.
.
.
.
.
.
.
.
–2147483647
–2147483648
---
---
80000001
80000000
Converting Decimal to
Signed Binary
Positive signed binary data is identical to unsigned binary data (up to 32,767)
and can be converted using BIN(100). The following procedure converts nega-
tive decimal values between –32,768 and –1 to signed binary. In this example
–12345 is converted to CFC7.
28
IR (Internal Relay) Area
Section 3-3
1. First take the absolute value (12345) and convert to unsigned binary:
Bit number
Contents
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
1
2. Next take the complement:
Bit number
Contents
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
1
1
0
0
1
1
1
1
1
1
0
0
0
1
1
0
3. Finally add one:
Bit number
Contents
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
1
1
0
0
1
1
1
1
1
1
0
0
0
1
1
1
Reverse the procedure to convert negative signed binary data to decimal.
3-3 IR (Internal Relay) Area
The IR area is used both as data to control I/O points, and as work bits to manipu-
late and store data internally. It is accessible both by bit and by word. In the
C200HX/HG/HE PC, the IR area is comprised of words IR 000 to IR 235 (IR
area 1) and IR 300 to IR 511 (IR area 2). Basic instructions have somewhat long-
er execution times when they access IR area 2 rather than IR area 1.
Words in the IR area that are used to control I/O points are called I/O words. Bits
in I/O words are called I/O bits. Bits in the IR area which are not assigned as I/O
bits can be used as work bits. IR area work bits are reset when power is inter-
rupted or PC operation is stopped.
Area
Range
IR Area 1
I/O Area 1
IR 000 to IR 029
IR 030 to IR 049
Group-2 High-density I/O Unit Area 1
and B7A Interface Unit Area
SYSMAC BUS and CompoBus/D Output
Area
IR 050 to IR 099
Special I/O Unit Area 1
Optical I/O Unit and I/O Terminal Area
Work Area
IR 100 to IR 199
IR 200 to IR 231
IR 232 to IR 235
IR 300 to IR 309
IR 310 to IR 329
IR 330 to IR 341
IR 342 to IR 349
IR 350 to IR 399
IR 400 to IR 459
IR 460 to IR 511
IR Area 2
I/O Area 2
Work Area
Group-2 High-density I/O Unit Area 2
Work Area
CompoBus/D Input Area
Special I/O Unit Area 2
Work Area
I/O Words
If a Unit brings inputs into the PC, the bit assigned to it is an input bit; if the Unit
sends an output from the PC, the bit is an output bit. To turn ON an output, the
output bit assigned to it must be turned ON. When an input turns ON, the input bit
assigned to it also turns ON. These facts can be used in the program to access
input status and control output status through I/O bits.
Input Bit Usage
Input bits can be used to directly input external signals to the PC and can be used
in any order in programming. Each input bit can also be used in as many instruc-
tions as required to achieve effective and proper control. They cannot be used in
29
IR (Internal Relay) Area
Section 3-3
instructions that control bit status, e.g., the OUTPUT, DIFFERENTIATION UP,
and KEEP instructions.
Output Bit Usage
Output bits are used to output program execution results and can be used in any
order in programming. Because outputs are refreshed only once during each
cycle (i.e., once each time the program is executed), any output bit can be used
in only one instruction that controls its status, including OUT, KEEP(11),
DIFU(13), DIFD(14) and SFT(10). If an output bit is used in more than one such
instruction, only the status determined by the last instruction will actually be out-
put from the PC.
See5-15-1 Shift Register – SFT(10) for an example that uses an output bit in two
‘bit-control’ instructions.
Word Allocation for Racks
I/O words are allocated to the CPU Rack and Expansion I/O Racks by slot posi-
tion. One I/O word is allocated to each slot, as shown in the following table. Since
each slot is allocated only one I/O word, a 3-slot rack uses only the first 3 words,
a 5-slot rack uses only the first 5 words, and an 8-slot rack uses only the first 8
words. Words that are allocated to unused or nonexistent slots are available as
work words.
← Left side of rack
Right side of a 10-slot rack →
Rack
Slot 1
IR 000
IR 010
IR 020
IR 300
Slot 2
IR 001
IR 011
IR 021
IR 301
Slot 3
IR 002
IR 012
IR 022
IR 302
Slot 4
IR 003
IR 013
IR 023
IR 303
Slot 5
IR 004
IR 014
IR 024
IR 304
Slot 6
IR 005
IR 015
IR 025
IR 305
Slot 7
IR 006
IR 016
IR 026
IR 306
Slot 8
IR 007
IR 017
IR 027
IR 307
Slot 9
IR 008
IR 018
IR 028
IR 308
Slot 10
IR 009
IR 019
IR 029
IR 309
CPU
st
1
2
3
Expansion
Expansion
Expansion
nd
rd
Unused Words
Any words allocated to a Unit that does not use them can be used in program-
ming as work words and bits. Units that do not used the words assigned to the
slot they are mounted to include Link Units (e.g., Host Link Units, PC Link Units,
SYSMAC NET Link Units, etc.), Remote I/O Master Units, Special I/O Units,
Group-2 High-density I/O Units, B7A Interface Units, and Auxiliary Power Sup-
ply Units.
Allocation for Special I/O
Units and Slave Racks
In most C200HX/HG/HE PCs, up to sixteen Special I/O Units may be mounted in
any slot of the CPU Rack or Expansion I/O Racks. (A limited number of Special
I/O Units can be installed in Remote I/O Slave Racks, too.) Each Special I/O Unit
is allocated ten words based on its unit number (0 to F).
Up to ten Special I/O Units may be mounted in the C200HE-CPU j-E and
j
C200HG/HX-CPU3j-E/4j-E PCs. Each Unit is allocated ten words based on
its unit number (0 to 9).
Unit number
I/O words
PC Restrictions
None
0
IR 100 to IR 109
IR 110 to IR 119
IR 120 to IR 129
IR 130 to IR 139
IR 140 to IR 149
IR 150 to IR 159
IR 160 to IR 169
IR 170 to IR 179
IR 180 to IR 189
IR 190 to IR 199
1
2
3
4
5
6
7
8
9
30
IR (Internal Relay) Area
Section 3-3
Unit number
I/O words
PC Restrictions
A
IR 400 to IR 409 Not available in C200HE-CPU
j
j
-
E
a
n
d
C200HG/HX-CPU3j -E/4j -E PCs.
B
C
D
E
F
IR 410 to IR 419
IR 420 to IR 429
IR 430 to IR 439
IR 440 to IR 449
IR 450 to IR 459
Note I/O words that aren’t allocated to Special I/O Units can be used as work words.
Up to five Slave Racks may be used, whether one or two Masters are used. IR
area words are allocated to Slave Racks by the unit number on the Unit, as
shown in the following tables.
Unit number
I/O words
0
1
2
3
4
IR 050 to IR 059
IR 060 to IR 069
IR 070 to IR 079
IR 080 to IR 089
IR 090 to IR 099
The C500-RT001/002-(P)V1 Remote I/O Slave Rack may be used, but it re-
quires 20 I/O words, not 10, and therefore occupies the I/O words allocated to 2
C200H Slave Racks, both the words allocated to the unit number set on the rack
and the words allocated to the following unit number. When using a C200HX/
HG/HE CPU Unit, do not set the unit number on a C500 Slave Rack to 4, be-
cause there is no unit number 5. With the C500 Slave Rack, I/O words are allo-
cated only to installed Units, from left to right, and not to slots as in the C200HX/
HG/HE Racks.
Allocation for Optical I/O
Units and I/O Terminals
I/O words between IR 200 and IR 231 are allocated to Optical I/O Units and I/O
Terminals by unit number. The I/O word allocated to each Unit is IR 200+n,
where n is the unit number set on the Unit.
Allocation for Remote I/O
Master and Link Units
Remote Master I/O Units and Host Link Units do not use I/O words, and the PC
Link Units use the LR area, so words allocated to the slots in which these Units
are mounted are available as work words.
Bit Allocation for I/O Units
An I/O Unit may require anywhere from 8 to 16 bits, depending on the model.
With most I/O Units, any bits not used for input or output are available as work
bits. Transistor Output Units C200H-OD213 and C200H-OD411, as well as Triac
Output Unit C200H-OA221, however, uses bit 08 for the Blown Fuse Flag. Tran-
sistor Output Unit C200H-OD214 uses bits 08 to 11 for the Alarm Flag. Bits 08 to
15 of any word allocated to these Units, therefore, cannot be used as work bits.
Bit Allocation for Interrupt
Input Units
The Interrupt Input Unit uses the 8 bits of the first I/O word allocated to its slot in
the CPU Rack. (An Interrupt Input Unit will operate as a normal Input Unit when
installed in an Expansion I/O Rack.) The other 24 bits allocated to its slot in the
CPU Rack can be used as work bits.
31
IR (Internal Relay) Area
Section 3-3
Allocation for Group-2
High-density I/O Units and
B7 Interface Units
Group-2 High-density I/O Units and B7A Interface Units are allocated words be-
tween IR 030 and IR 049 according to I/O number settings made on them and do
not use the words allocated to the slots in which they are mounted. For 32-point
Units, each Unit is allocated two words; for 64-point Units, each Unit is allocated
four words. The words allocated for each I/O number are in the following tables.
Any words or parts of words not used for I/O can be used as work words or bits in
programming.
32-point Units
64-point Units
I/O number
Words
I/O number
Words
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IR 30 to IR 31
IR 32 to IR 33
IR 34 to IR 35
IR 36 to IR 37
IR 38 to IR 39
IR 40 to IR 41
IR 42 to IR 43
IR 44 to IR 45
IR 46 to IR 47
IR 48 to IR 49
IR 330 to IR 331
IR 332 to IR 333
IR 334 to IR 335
IR 336 to IR 337
IR 338 to IR 339
IR 340 to IR 341
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IR 30 to IR 33
IR 32 to IR 35
IR 34 to IR 37
IR 36 to IR 39
IR 38 to IR 41
IR 40 to IR 43
IR 42 to IR 45
IR 44 to IR 47
IR 46 to IR 49
Cannot be used.
IR 330 to IR 333
IR 332 to IR 335
IR 334 to IR 337
IR 336 to IR 339
IR 338 to IR 341
Cannot be used.
When setting I/O numbers on the High-density I/O Units and B7A Interface
Units, be sure that the settings will not cause the same words to be allocated to
more than one Unit. For example, if I/O number 0 is allocated to a 64-point Unit,
I/O number 1 cannot be used for any Unit in the system.
Group-2 High-density I/O Units and B7A Interface Units are not considered Spe-
cial I/O Units and do not affect the limit to the number of Special I/O Units allowed
in the System, regardless of the number used.
The words allocated to Group-2 High-density I/O Units correspond to the con-
nectors on the Units as shown in the following table.
Unit
32-point Units
Word
Connector/row
Row A
m
m + 1
m
Row B
64-point Units
CN1, row A
CN1, row B
CN2, row A
CN2, row B
m + 1
m + 2
m + 3
Note 1. Group-2 High-density I/O Units and B7A Interface Units cannot be mounted
to Slave Racks.
2. Refer to the Installation Guide for limitations on the number of Special I/O
Units that can be mounted to Slave Racks.
32
SR (Special Relay) Area
Section 3-4
3-4 SR (Special Relay) Area
The SR area contains flags and control bits used for monitoring PC operation,
accessing clock pulses, and signalling errors. SR area word addresses range
from 236 through 299; bit addresses, from 23600 through 29915.
The SR areas is divided into two sections. The first section ends at SR 255 and
the second section begins at SR 256. When an SR area word is used as an oper-
and in an instruction, the operand mustn’t cross over this boundary. Basic
instructions that access bits in the SR Area 2 have longer execution times.
Area
SR Area 1
SR Area 2
Range
SR 23600 to SR 25507
SR 25600 to SR 29915
The following table lists the functions of SR area flags and control bits. Most of
these bits are described in more detail following the table. Descriptions are in
order by bit number except that Link System bits are grouped together.
Unless otherwise stated, flags are OFF until the specified condition arises, when
they are turned ON. Restart bits are usually OFF, but when the user turns one
ON then OFF, the specified Link Unit will be restarted. Other control bits are OFF
until set by the user.
Not all SR words and bits are writeable by the user. Be sure to check the function
of a bit or word before attempting to use it in programming.
Word(s)
236
Bit(s)
Function
00 to 07 Node loop status output area for operating level 0 of SYSMAC NET Link System
08 to 15 Node loop status output area for operating level 1 of SYSMAC NET Link System
00 to 07 Completion code output area for operating level 0 following execution of
237
SEND(90)/RECV(98) for SYSMAC LINK/SYSMAC NET Link System or CMCR(––) for a PC
Card
08 to 15 Completion code output area for operating level 1 following execution of
SEND(90)/RECV(98) for SYSMAC LINK/SYSMAC NET Link System or CMCR(––) for a PC
Card
238 and 241
242 and 245
00 to 15 Data link status output area for operating level 0 of SYSMAC LINK or SYSMAC NET Link
System
00 to 15 Data link status output area for operating level 1 of SYSMAC LINK or SYSMAC NET Link
System
246
00 to 15 Not used
00 to 07 PC Link Unit Run Flags for Units 16 through 31 or data link status for operating level 1
08 to 15 PC Link Unit Error Flags for Units 16 through 31 or data link status for operating level 1
247 and 248
00 to 07 PC Link Unit Run Flags for Units 00 through 15 or data link status for operating level 0
08 to 15 PC Link Unit Error Flags for Units 00 through 15 or data link status for operating level 0
249 and 250
00
Remote I/O Error Read Bit
251
01 to 02 Not used
Writeable
03
Remote I/O Error Flag
04 to 06 Slave Rack number and unit number of Remote I/O Unit, Optical I/O Unit, or I/O Terminal
with error
07
Not used
08 to 15 Master’s unit number and word allocated to Remote I/O Unit, Optical I/O Unit, or I/O Terminal
with error (Hexadecimal)
33
SR (Special Relay) Area
Section 3-4
Word(s)
252
Bit(s)
00
Function
SEND(90)/RECV(98) Error Flag for operating level 0 of SYSMAC LINK or SYSMAC NET
Link System or CMCR(––) Error Flag for PC Card
01
SEND(90)/RECV(98) Enable Flag for operating level 0 of SYSMAC LINK or SYSMAC NET
Link System or CMCR(––) Enable Flag for PC Card
02
03
Operating Level 0 Data Link Operating Flag
SEND(90)/RECV(98) Error Flag for operating level 1 of SYSMAC LINK or SYSMAC NET
Link System or CMCR(––) Error Flag for PC Card
04
SEND(90)/RECV(98) Enable Flag for operating level 1 of SYSMAC LINK or SYSMAC NET
Link System or CMCR(––) Enable Flag for PC Card
05
06
07
08
09
10
11
12
13
14
15
Operating Level 1 Data Link Operating Flag
Rack-mounting Host Link Unit Level 1 Communications Error Flag
Rack-mounting Host Link Unit Level 1 Restart Bit
Peripheral Port Restart Bit
RS-232C Port Restart Bit
PC Setup Clear Bit
Forced Status Hold Bit
Data Retention Control Bit
Rack-mounting Host Link Unit Level 0 Restart Bit
Not used.
Output OFF Bit
00 to 07 FAL number output area (see error information provided elsewhere)
253
08
09
10
11
12
13
14
15
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
Low Battery Flag
Cycle Time Error Flag
I/O Verification Error Flag
Rack-mounting Host Link Unit Level 0 Communications Error Flag
Remote I/O Error Flag
Always ON Flag
Always OFF Flag
First Cycle Flag
1-minute clock pulse bit
254
0.02-second clock pulse bit
Negative (N) Flag
MTR Execution Flag
Overflow Flag (for signed binary calculations)
Underflow Flag (for signed binary calculations)
Differential Monitor End Flag
Step Flag
HKY Execution Flag
7SEG Execution Flag
DSW Execution Flag
Interrupt Input Unit Error Flag
Reserved by system (not accessible by user)
Interrupt Program Error Flag
Group-2 Error Flag
Special Unit Error Flag (includes Special I/O, PC Link, Host Link, Remote I/O Master Units)
34
SR (Special Relay) Area
Section 3-4
Word(s)
255
Bit(s)
00
Function
0.1-second clock pulse bit
0.2-second clock pulse bit
1.0-second clock pulse bit
Instruction Execution Error (ER) Flag
Carry (CY) Flag
01
02
03
04
05
06
07
These flags are turned OFF when the END(01)
instruction is executed, so their status can’t be
monitored from a Programming Console.
Greater Than (GR) Flag
Equals (EQ) Flag
Refer to Appendix C for a table showing which
instructions affect these flags.
Less Than (LE) Flag
08 to 15 Reserved by system (used for TR bits)
00 to 15 Reserved by system
256 to 261
262
00 to 15 Longest interrupt subroutine (action) execution time (0.1-ms units)
263
00 to 15 Number of interrupt subroutine (action) with longest execution time. (8000 to 8255)
(Bit 15 is the Interrupt Flag)
00 to 03 RS-232C Port Error Code
264
0: No error
1: Parity error
2: Framing error
3: Overrun error
04
05
06
07
RS-232C Port Communications Error
RS-232C Port Send Ready Flag
RS-232C Port Reception Completed Flag
RS-232C Port Reception Overflow Flag
08 to 11 Peripheral Port Error Code in General I/O Mode
0: No error
1: Parity error
2: Framing error
3: Overrun error
12
13
14
15
Peripheral Port Communications Error in General I/O Mode
Peripheral Port Send Ready Flag in in General I/O Mode
Peripheral Port Reception Completed Flag in General I/O Mode
Peripheral Port Reception Overflow Flag in General I/O Mode
265
00 to 15 NT Link (1:N) Mode
Bits 00 to 07: Communicating with PT Flags for Units 0 to 7
Bits 08 to 15: Registering PT Priority Flags for Units 0 to 7
RS-232C Mode
Bits 00 to 15: RS-232C Port Reception Counter
00 to 15 Peripheral Reception Counter in RS-232C Mode
00 to 04 Reserved by system (not accessible by user)
266
267
05
06 to 12 Reserved by system (not accessible by user)
13 Host Link Level 1 Send Ready Flag
Host Link Level 0 Send Ready Flag
14 to 15 Reserved by system (not accessible by user)
268
269
00 to 15 Communications Board Error Information
00 to 07 Memory Cassette Contents 00: Nothing; 01: UM; 02: IOM; 03: HIS
08 to 10 Memory Cassette Capacity
0: 0 KW (no cassette); 2: 4 or 8 KW; 3: 16 KW; 4: 32 KW
11 to 13 Reserved by system (not accessible by user)
14
15
EEPROM Memory Cassette Protected or EPROM Memory Cassette Mounted Flag
Memory Cassette Flag
35
SR (Special Relay) Area
Section 3-4
Word(s)
270
Bit(s)
00
Function
Save UM to Cassette Bit
Data transferred when the Bit is turned ON in
PROGRAM mode. Bit will automatically turn OFF.
A non-fatal error will occur if these bits are turned
ON in RUN or MONITOR modes.
01
Load UM from Cassette Bit
02
03
Compare UM to Cassette Bit
Comparison Results
0: Contents identical; 1: Contents differ or comparison not possible
04 to 10 Reserved by system (not accessible by user)
11
12
Transfer Error Flag: Transferring
SYSMAC NET data link table on UM
during active data link.
Data will not be transferred from UM to the Memory
Cassette if an error occurs (except for Board
Checksum Error). Detailed information on checksum
errors occurring in the Memory Cassette will not be
output to SR 272 because the information is not
needed. Repeat the transmission if SR 27015 is ON.
Transfer Error Flag: Not PROGRAM
mode
13
14
Transfer Error Flag: Read Only
Transfer Error Flag: Insufficient
Capacity or No UM
15
Transfer Error Flag: Board Checksum
Error
00 to 07 Ladder program size stored in Memory Cassette
271
272
Ladder-only File: 04: 4 KW; 08: 8 KW; 12: 12 KW; ... (32: 32 KW)
00: No ladder program or a file other than a ladder program has been stored.
08 to 15 Ladder program size and type in CPU Unit (Specifications are the same as for bits 00 to 07.)
00 to 10 Reserved by system (not accessible by user)
11
12
13
14
15
00
Memory Error Flag: PC Setup Checksum Error
Memory Error Flag: Ladder Checksum Error
Memory Error Flag: Instruction Change Vector Area Checksum Error
Memory Error Flag: Memory Cassette Online Disconnection
Memory Error Flag: Autoboot Error
Save IOM to Cassette Bit
Load IOM from Cassette Bit
Set this bit to 0.
273
Data transferred to Memory Cassette when Bit is
turned ON in PROGRAM mode. Bit will automatically
turn OFF. An error will be produced if turned ON in
any other mode.
01
02
03 to 07 Reserved by system (not accessible by user)
08 to 11 Contains the EM bank number when the Memory Cassette contains IOM data.
12
Transfer Error Flag: Not PROGRAM
mode
Data will not be transferred from IOM to the Memory
Cassette if an error occurs (except for Read Only
Error).
13
14
Transfer Error Flag: Read Only
Transfer Error Flag: Insufficient
Capacity or No IOM
15
Always 0.
36
SR (Special Relay) Area
Section 3-4
Word(s)
274
Bit(s)
00
Function
Special I/O Unit #0 Restart Flag
Special I/O Unit #1 Restart Flag
Special I/O Unit #2 Restart Flag
Special I/O Unit #3 Restart Flag
Special I/O Unit #4 Restart Flag
Special I/O Unit #5 Restart Flag
Special I/O Unit #6 Restart Flag
Special I/O Unit #7 Restart Flag
Special I/O Unit #8 Restart Flag
Special I/O Unit #9 Restart Flag
Special I/O Unit #A Restart Flag
Special I/O Unit #B Restart Flag
Special I/O Unit #C Restart Flag
Special I/O Unit #D Restart Flag
Special I/O Unit #E Restart Flag
Special I/O Unit #F Restart Flag
These flags will turn ON during restart processing.
These flags will not turn ON for Units on Slave
Racks.
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
00
01
02
03
04
05
PC Setup Error (DM 6600 to DM 6605)
PC Setup Error (DM 6613 to DM 6623)
PC Setup Error (DM 6645 to DM 6655)
275
Reserved by system (not accessible by user)
Changing RS-232C Setup Flag
Reserved by system (not accessible by user)
06 to 07 Reserved by system (not accessible by user)
08 to 15 Reserved by system (not accessible by user)
00 to 07 Minutes (00 to 59)
08 to 15 Hours (00 to 23)
276
Indicates the current time in BCD.
277 to 279
280
00 to 15 Used for keyboard mapping. See page 412.
00 to 15 Group-2 High-density I/O Unit Error Flags for Units 0 to F
(AR 0205 to AR 0214 also function as Error Flags for Units 0 to 9.)
281
00 to 15 Special I/O Unit Restart Bits for Units 0 to F
(Units 0 to 9 can also be restarted with Special I/O Unit Restart Bits AR 0100 to AR 0109.)
• To restart a Special I/O Unit, either use for force-set/reset operation to turn the Restart Bit ON
and OFF, or turn OFF the power and then turn it ON again.
• Follow the same procedure as above for starting PC Link Units.
282
00 to 15 Special I/O Unit Error Flags for Units 0 to F
(AR 0000 to AR 0009 also function as Error Flags for Units 0 to 9.)
283 to 286
287 to 288
289
00 to 15 Communications Board monitoring area
00 to 15 Communications Board interrupt data area
00 to 07 Communications Board general monitoring area
08
Communications Board Port A Instruction Execution Flag
09 to 10 Used by Communications Board Port A instructions
11
12
Communications Board Port A Instruction Abort Bit
Communications Board Port B Instruction Execution Flag
13 to 14 Used by Communications Board Port B instructions
15 Communications Board Port B Instruction Abort Bit
290 to 293
294 to 297
298 to 299
00 to 15 Macro Area inputs.
00 to 15 Macro Area outputs.
00 to 15 Reserved by system (not accessible by user)
37
SR (Special Relay) Area
Section 3-4
3-4-1 SYSMAC NET/SYSMAC LINK System
Loop Status
SR 236 provides the local node loop status for SYSMAC NET Systems, as
shown below.
---
Level 0
Level 1
Bit in SR 236
07 06
15 14
05
13
04
12
03
11
02
10
01
09
00
08
Status/
1
1
Central Power Supply
1
Loop Status
Reception Status
1
Meaning
0: Connected
1: Not connected
11: Normal loop
0: Reception enabled
1: Reception disabled
10: Downstream backloop
01: Upstream backloop
00: Loop error
Completion Codes
SR 23700 to SR23707 provide the SEND/RECV completion code for operating
level 0 and SR 23708 to SR 23215 provide the SEND/RECV completion code for
operating level 1. The completion codes are as given in the following tables.
SYSMAC LINK
Code
00
Item
Normal end
Meaning
Processing ended normally.
01
02
03
04
Parameter error
Parameters for network communication instruction is
not within acceptable ranges.
Unable to send
Unit reset during command processing or local node
in not in network.
Destination not in
network
Destination node is not in network.
Busy error
The destination node is processing data and cannot
receive the command.
05
06
Response timeout The response monitoring time was exceeded.
Response error
There was an error in the response received from
the destination node.
07
Communications
controller error
An error occurred in the communications controller.
08
09
Setting error
PC error
There is an error in the node address settings.
An error occurred in the CPU Unit of the destination
node.
SYSMAC NET
Code
Item
Meaning
00
01
Normal end
Processing ended normally.
Parameter error
Parameters for network communication instruction is
not within acceptable ranges.
02
03
04
Routing error
Busy error
There is a mistake in the routing tables for
connection to a remote network.
The destination node is processing data and cannot
receive the command.
Send error (token
lost)
The token was not received from the Line Server.
05
06
Loop error
An error occurred in the communications loop.
No response
The destination node does not exist or the response
monitoring time was exceeded.
07
Response error
There is an error in the response format.
38
SR (Special Relay) Area
Section 3-4
Data Link Status Flags
SR 238 to SR 245 contain the data link status for SYSMAC LINK/SYSMAC NET
Systems. The data structure depends on the system used to create the data link.
SYSMAC LINK
Bit
Operating
level 0
Operating
level 1
12 to 15
Node 4
11 to 08
Node 3
04 to 07
Node 2
00 to 03
Node 1
SR 238
SR 239
SR 240
SR 241
SR 242
SR 243
SR 244
SR 245
Node 8
Node 7
Node 6
Node 5
Node 9
Node 13
Node 12
Node 16
Node 11
Node 15
Node 10
Node 14
Leftmost bit
Rightmost bit
1: Data link
operating
1: Communica-
tions error
1: PC CPU Unit
error
1: PC RUN status
SYSMAC NET
Bit (Node numbers below)
10 09 08 07 06 05
Operating Operating
level 0
level 1
15
14
13
12
11
04
03
02
01
00
SR 238
SR 239
SR 240
SR 241
SR 242
SR 243
SR 244
SR 245
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
16
24
32
15
23
31
14
22
30
13
21
29
12
20
28
11
19
27
10
18
26
9
16
24
32
15
23
31
14
22
30
13
21
29
12
20
28
11
19
27
10
18
26
9
17
25
17
25
1: PC CPU Unit error
1: PC RUN status
3-4-2 Remote I/O Systems
SR 25312 turns ON to indicate an error has occurred in Remote I/O Systems.
The ALM/ERR indicator will flash, but PC operation will continue. SR 251 con-
tains information on the source and type of error and AR 0014 and AR 0015 con-
tain information on the SYSMAC LINK status. The function of each bit is de-
scribed below. Refer to Optical and Wired Remote I/O System Manuals for de-
tails.
SR 25100 – Error Check Bit
If there are errors in more than one Remote I/O Unit, word SR 251 will contain
error information for only the first one. Data for the remaining Units will be stored
in memory and can be accessed by turning the Error Check bit ON and OFF. Be
sure to record data for the first error, which will be cleared when data for the next
error is displayed.
SR 25101 and SR 25102
SR 25103
Not used.
Remote I/O Error Flag: Bit 03 turns ON when an error has occurred in a Remote
I/O Unit.
0
1
2
SR 25104 through SR 25115 The content of bits 04 to 06 is a 3-digit binary number (04: 2 , 05: 2 , 06: 2 ) and
0
the content of bits 08 to 15 is a 2-digit hexadecimal number (08 to 11: 16 , 12 to
1
15: 16 ).
If the content of bits 12 through 15 is B, an error has occurred in a Remote I/O
Master or Slave Unit, and the content of bits 08 through 11 will indicate the unit
number, either 0 or 1, of the Master involved. In this case, bits 04 to 06 contain
the unit number of the Slave Rack involved.
If the content of bits 12 through 15 is a number from 0 to 31, an error has oc-
curred in an Optical I/O Unit or I/O Terminal. The number is the unit number of the
Optical I/O Unit or I/O Terminal involved, and bit 04 will be ON if the Unit is as-
signed leftmost word bits (08 through 15), and OFF if it is assigned rightmost
word bits (00 through 07).
39
SR (Special Relay) Area
Section 3-4
3-4-3 Link System Flags and Control Bits
Use of the following SR bits depends on the configuration of any Link Systems to
which your PC belongs. These flags and control bits are used when Link Units,
such as PC Link Units, Remote I/O Units, or Host Link Units, are mounted to the
PC Racks or to the CPU Unit. For additional information, consult the System
Manual for the particular Units involved.
The following bits can be employed as work bits when the PC does not belong to
the Link System associated with them.
Host Link Systems
Both Error flags and Restart bits are provided for Host Link Systems. Error flags
turn ON to indicate errors in Host Link Units. Restart bits are turned ON and then
OFF to restart a Host Link Unit. SR bits used with Host Link Systems are summa-
rized in the following table. Rack-mounting Host Link Unit Restart bits are
not effective for the Multilevel Rack-mounting Host Link Units. Refer to the
Host Link System Manual for details.
Bit
Flag
25206
25207
25213
25311
Rack-mounting Host Link Unit Level 1 Error Flag
Rack-mounting Host Link Unit Level 1 Restart Bit
Rack-mounting Host Link Unit Level 0 Restart Bit
Rack-mounting Host Link Unit Level 0 Error Flag
PC Link Systems
PC Link Unit Error and Run
Flags
When the PC belongs to a PC Link System, words 247 through 250 are used to
monitor the operating status of all PC Link Units connected to the PC Link Sys-
tem. This includes a maximum of 32 PC Link Units. If the PC is in a Multilevel PC
Link System, half of the PC Link Units will be in a PC Link Subsystem in operating
level 0; the other half, in a Subsystem in operating level 1. The actual bit assign-
ments depend on whether the PC is in a Single-level PC Link System or a Multi-
level PC Link System. Refer to the PC Link System Manual for details. Error and
Run Flag bit assignments are described below.
Bits 00 through 07 of each word are the Run flags, which are ON when the PC
Link Unit is in RUN mode. Bits 08 through 15 are the Error flags, which are ON
when an error has occurred in the PC Link Unit. The following table shows bit
assignments for Single-level and Multi-level PC Link Systems.
Single-level PC Link
Systems
Flag type
Bit no.
00
SR 247
Unit #24
Unit #25
Unit #26
Unit #27
Unit #28
Unit #29
Unit #30
Unit #31
Unit #24
Unit #25
Unit #26
Unit #27
Unit #28
Unit #29
Unit #30
Unit #31
SR 248
Unit #16
Unit #17
Unit #18
Unit #19
Unit #20
Unit #21
Unit #22
Unit #23
Unit #16
Unit #17
Unit #18
Unit #19
Unit #20
Unit #21
Unit #22
Unit #23
SR 249
Unit #8
SR 250
Unit #0
Run flags
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
Unit #9
Unit #1
Unit #2
Unit #3
Unit #4
Unit #5
Unit #6
Unit #7
Unit #0
Unit #1
Unit #2
Unit #3
Unit #4
Unit #5
Unit #6
Unit #7
Unit #10
Unit #11
Unit #12
Unit #13
Unit #14
Unit #15
Unit #8
Error flags
Unit #9
Unit #10
Unit #11
Unit #12
Unit #13
Unit #14
Unit #15
40
SR (Special Relay) Area
Section 3-4
Multilevel PC Link Systems
Flag type
Bit no.
SR 247
Unit #8,
level 1
SR 248
Unit #0,
level 1
SR 249
Unit #8,
level 0
SR 250
Run flags
00
01
02
03
04
05
06
07
Unit #0,
level 0
Unit #9,
level 1
Unit #1,
level 1
Unit #9,
level 0
Unit #1,
level 0
Unit #10,
level 1
Unit #2,
level 1
Unit #10,
level 0
Unit #2,
level 0
Unit #11,
level 1
Unit #3,
level 1
Unit #11,
level 0
Unit #3,
level 0
Unit #12,
level 1
Unit #4,
level 1
Unit #12,
level 0
Unit #4,
level 0
Unit #13,
level 1
Unit #5,
level 1
Unit #13,
level 0
Unit #5,
level 0
Unit #14,
level 1
Unit #6,
level 1
Unit #14,
level 0
Unit #6,
level 0
Unit #15,
level 1
Unit #7,
level 1
Unit #15,
level 0
Unit #7,
level 0
Error flags 08
Unit #8,
level 1
Unit #0,
level 1
Unit #8,
level 0
Unit #0,
level 0
09
10
11
12
13
14
15
Unit #9,
level 1
Unit #1,
level 1
Unit #9,
level 0
Unit #1,
level 0
Unit #10,
level 1
Unit #2,
level 1
Unit #10,
level 0
Unit #2,
level 0
Unit #11,
level 1
Unit #3,
level 1
Unit #11,
level 0
Unit #3,
level 0
Unit #12,
level 1
Unit #4,
level 1
Unit #12,
level 0
Unit #4,
level 0
Unit #13,
level 1
Unit #5,
level 1
Unit #13,
level 0
Unit #5,
level 0
Unit #14,
level 1
Unit #6,
level 1
Unit #14,
level 0
Unit #6,
level 0
Unit #15,
level 1
Unit #7,
level 1
Unit #15,
level 0
Unit #7,
level 0
Application Example
If the PC is in a Multilevel PC Link System and the content of word 248 is 02FF,
then PC Link Units #0 through #7 of in the PC Link Subsystem assigned operat-
ing level 1 would be in RUN mode, and PC Link Unit #1 in the same Subsystem
would have an error. The hexadecimal digits and corresponding binary bits of
word 248 would be as shown below.
Bit no.
Binary
Hex
15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00
0 0 0 0
0
0 0 1 0
2
1 1 1 1
F
1 1 1 1
F
3-4-4 Forced Status Hold Bit
SR 25211 determines whether or not the status of bits that have been force-set
or force-reset is maintained when switching between PROGRAM and MON-
ITOR mode to start or stop operation. If SR 25211 is ON, bit status will be main-
tained; if SR 25211 is OFF, all bits will return to default status when operation is
started or stopped. The Forced Status Hold Bit is only effective when enabled in
the PC Setup.
The status of SR 25211 in not affected by a power interruption unless the I/O
table is registered; in that case, SR 25211 will go OFF.
SR 25211 is not effective when switching to RUN mode.
SR 25211 should be manipulated from a Peripheral Device, e.g., a Program-
ming Console or SSS.
41
SR (Special Relay) Area
Section 3-4
Maintaining Status during
Startup
The status of SR 25211 and thus the status of force-set and force-reset bits can
be maintained when power is turned OFF and ON by enabling the Forced Status
Hold Bit in the PC Setup. If the Forced Status Hold Bit is enabled, the status of
SR 25211 will be preserved when power is turned OFF and ON. If this is done
and SR 25211 is ON, then the status of force-set and force-reset bits will also be
preserved, as shown in the following table.
Status before shutdown
SR 25211
Status at next startup
SR 25211 Force-set/reset bits
ON
OFF
ON
Status maintained
Reset
OFF
Note Refer to 3-6-4 PC Setup for details on enabling the Forced Status Hold Bit.
3-4-5 I/O Status Hold Bit
SR 25212 determines whether or not the status of IR and LR area bits is main-
tained when operation is started or stopped. If SR 25212 is ON, bit status will be
maintained; if SR 25212 is OFF, all IR and LR area bits will be reset. The I/O Sta-
tus Hold Bit is effective only if enabled in the PC Setup.
The status of SR 25212 in not affected by a power interruption unless the I/O
table is registered; in that case, SR 25212 will go OFF.
SR 25212 should be manipulated from a Peripheral Device, e.g., a Program-
ming Console or SSS.
Maintaining Status during
Startup
The status of SR 25212 and thus the status of IR and LR area bits can be main-
tained when power is turned OFF and ON by enabling the I/O Status Hold Bit in
the PC Setup. If the I/O Status Hold Bit is enabled, the status of SR 25212 will be
preserved when power is turned OFF and ON. If this is done and SR 25212 is
ON, then the status of IR and LR area bits will also be preserved, as shown in the
following table.
Status before shutdown
SR 25212
Status at next startup
SR 25212 IR and LR bits
ON
OFF
ON
Status maintained
Reset
OFF
Note Refer to 3-6-4 PC Setup for details on enabling the I/O Status Hold Bit.
3-4-6 Output OFF Bit
SR bit 25215 is turned ON to turn OFF all outputs from the PC. The OUT INHIBIT
indicator on the front panel of the CPU Unit will light. When the Output OFF Bit is
OFF, all output bits will be refreshed in the usual way.
The status of the Output OFF Bit is maintained for power interruptions or when
PC operation is stopped, unless the I/O table has been registered, or the I/O
table has been registered and either the Forced Status Hold Bit or the I/O Status
Hold Bit has not been enabled in the PC Setup.
3-4-7 FAL (Failure Alarm) Area
A 2-digit BCD FAL code is output to bits 25300 to 25307 when the FAL or FALS
instruction is executed. These codes are user defined for use in error diagnosis,
although the PC also outputs FAL codes to these bits, such as one caused by
battery voltage drop.
This area can be reset by executing the FAL instruction with an operand of 00 or
by performing a Failure Read Operation from the Programming Console.
3-4-8 Low Battery Flag
SR bit 25308 turns ON if the voltage of the CPU Unit’s backup battery drops. The
ALM/ERR indicator on the front of the CPU Unit will also flash.
42
SR (Special Relay) Area
Section 3-4
This bit can be programmed to activate an external warning for a low battery volt-
age.
The operation of the battery alarm can be disabled in the PC Setup if desired.
Refer to 3-6-4 PC Setup for details.
3-4-9 Cycle Time Error Flag
SR bit 25309 turns ON if the cycle time exceeds 100 ms. The ALM/ERR indicator
on the front of the CPU Unit will also flash. Program execution will not stop, how-
ever, unless the maximum time limit set for the watchdog timer is exceeded. Tim-
ing may become inaccurate after the cycle time exceeds 100 ms.
3-4-10 I/O Verification Error Flag
SR bit 25310 turns ON when the Units mounted in the system disagree with the
I/O table registered in the CPU Unit. The ALM/ERR indicator on the front of the
CPU Unit will also flash, but PC operation will continue.
To ensure proper operation, PC operation should be stopped, Units checked,
and the I/O table corrected whenever this flag goes ON.
3-4-11 First Cycle Flag
SR bit 25315 turns ON when PC operation begins and then turns OFF after one
cycle of the program. The First Cycle Flag is useful in initializing counter values
and other operations. An example of this is provided in 5-14 Timer and Counter
Instructions.
3-4-12 Clock Pulse Bits
Five clock pulses are available to control program timing. Each clock pulse bit is
ON for the first half of the rated pulse time, then OFF for the second half. In other
words, each clock pulse has a duty factor of 50%.
These clock pulse bits are often used with counter instructions to create timers.
Refer to 5-14 Timer and Counter Instructions for an example of this.
Pulse width
Bit
1 min
0.02 s
25401
0.1 s
0.2 s
1.0 s
25400
25500
25501
25502
Bit 25400
1-min clock pulse
Bit 25401
0.02-s clock pulse
30 s
.05 s
0.5 s
30 s
.01 s
.01 s
.02 s
1 min.
Bit 25500
0.1-s clock pulse
Bit 25501
0.2-s clock pulse
.05 s
0.1 s
0.1 s
0.1 s
0.2 s
Bit 25502
1.0-s clock pulse
Note:
Because the 0.1-second and
0.02-second clock pulse bits have
ON times of 50 and 10 ms, respec-
tively, the CPU Unit may not be
able to accurately read the pulses
if program execution time is too
long.
0.5 s
1.0 s
43
SR (Special Relay) Area
Section 3-4
3-4-13 Step Flag
SR bit 25407 turns ON for one cycle when step execution is started with the
STEP(08) instruction.
3-4-14 Group-2 Error Flag
SR bit 25414 turns ON for any of the following errors for Group-2 High-density
I/O Units and B7A Interface Units: the same I/O number set twice, the same
words allocated to more than one Unit, refresh errors. If one of these errors oc-
curs, the Unit will stop operation and the ALARM indicator will flash, but the over-
all PC will continue operation.
When the Group-2 Error Flag is ON, the number of the Unit with the error will be
provided in AR 0205 to AR 0214. If the Unit cannot be started properly even
though the I/O number is set correctly and the Unit is installed properly, a fuse
may be blown or the Unit may contain a hardware failure. If this should occur,
replace the Unit with a spare and try to start the system again.
There is also an error flag for High-density I/O Units and B7A Interface Units in
the AR area, AR 0215.
3-4-15 Special Unit Error Flag
SR bit 25415 turns ON to indicate errors in the following Units: Special I/O, PC
Link, Host Link, and Remote I/O Master Units. SR bit 25415 will turn ON for any
of the following errors.
• When more than one Special I/O Unit is set to the same unit number.
• When an error occurs in refreshing data between a Special I/O Unit and the
PC’s CPU Unit.
• When an error occurs between a Host Link Unit and the PC’s CPU Unit.
• When an error occurs in a Remote I/O Master Unit.
Although the PC will continue operation if SR 25415 turns ON, the Units causing
the error will stop operation and the ALM indicator will flash. Check the status of
AR 0000 to AR 0015 to obtain the unit numbers of the Units for which the error
occurred and investigate the cause of the error.
Unit operation can be restarted by using the Restart Bits (AR 0100 to AR 0115,
SR 25207, and SR 25213), but will not be effective if the same unit number is set
for more than one Special I/O Unit. Turn OFF the power supply, correct the unit
number settings, and turn ON the power supply again to restart.
SR 25415 will not turn OFF even if AR 0100 to AR 0115 (Restart Bits) are turned
ON. It can be turned OFF by reading errors from a Programming Device or by
executing FAL(06) 00 from the ladder program.
3-4-16 Instruction Execution Error Flag, ER
SR bit 25503 turns ON if an attempt is made to execute an instruction with incor-
rect operand data. Common causes of an instruction error are non-BCD oper-
and data when BCD data is required, or an indirectly addressed DM word that is
non-existent. When the ER Flag is ON, the current instruction will not be
executed.
3-4-17 Arithmetic Flags
The following flags are used in data shifting, arithmetic calculation, and compari-
son instructions. They are generally referred to only by their two-letter abbrevi-
ations.
Note These flags are all reset when the END(01) instruction is executed, and there-
fore cannot be monitored from a programming device.
Refer to 5-15 Data Shifting, 5-17 Data Comparison, 5-19 BCD Calculations, and
5-20 Binary Calculations for details.
44
SR (Special Relay) Area
Section 3-4
Negative Flag, N
SR bit 25402 turns ON when the result of a calculation is negative.
Overflow Flag, OF
SR bit 25404 turns ON when the result of a binary addition or subtraction ex-
ceeds 7FFF or 7FFFFFFF.
Underflow Flag, UF
Carry Flag, CY
SR bit 25405 turns ON when the result of a signed binary addition or subtraction
exceeds 8000 or 80000000.
SR bit 25504 turns ON when there is a carry in the result of an arithmetic opera-
tion or when a rotate or shift instruction moves a “1” into CY. The content of CY is
also used in some arithmetic operations, e.g., it is added or subtracted along
with other operands. This flag can be set and cleared from the program using the
Set Carry and Clear Carry instructions.
Greater Than Flag, GR
Equal Flag, EQ
SR bit 25505 turns ON when the result of a comparison shows the first of two
operands to be greater than the second.
SR bit 25506 turns ON when the result of a comparison shows two operands to
be equal or when the result of an arithmetic operation is zero.
Less Than Flag, LE
SR bit 25507 turns ON when the result of a comparison shows the first of two
operands to be less than the second.
Note The four arithmetic flags are turned OFF when END(01) is executed.
3-4-18 Interrupt Subroutine Areas
The following areas are used in subroutine interrupt processing.
Interrupt Subroutine
Maximum Processing Time
Area
SR bits 26200 to 26215 are used to set the maximum processing time of the in-
terrupt subroutine. Processing times are determined to within 0.1 ms incre-
ments.
Maximum Processing Time
Interrupt Subroutine
Number Area
SR bits 26300 to 26315 contain the maximum processing time interrupt subrou-
tine number. Bit 15 will be ON if there is an interruption.
3-4-19 RS-232C Port Communications Areas
RS-232C Port Error Code
SR bits 26400 to 26403 set when there is a RS-232C port error.
Error code
Error type
Error conditions
Valid modes
All modes
0
1
No error
---
Parity error
When data received differs from
positive/negative parity setting.
All modes
2
3
4
Framing error
Overrun error
Timeout error
When step bit cannot be detected.
When data is not properly received.
All modes
All modes
When a timeout occurs for two PCs linked
one-to-one.
1:1 PC Link slave or 1:1
PC Link master
RS-232C Port
SR bit 26404 turns ON when there is a RS-232C port communication error.
SR bit 26405 turns ON when the PC is ready to transmit data.
Communication Error Bit
RS-232C Port Send Ready
Flag
RS-232C Port Reception
Completed Flag
SR bit 26406 turns ON when the PC has completed reading data from a
RS-232C device.
RS-232C Port Reception
Overflow Flag
SR bit 26407 turns ON when data overflow occurs following the reception of
data.
RS-232C Reception Counter SR 26500 to SR 26515 contains the number of RS-232C port receptions in Gen-
eral I/O Mode.
45
SR (Special Relay) Area
Section 3-4
Host Link Level 0 Send
Ready Flag
SR bit 26705 turns ON when the PC is ready to transmit to the Host Link Unit.
SR bit 26713 turns ON when the PC is ready to transmit to the Host Link.
Host Link Level 1 Send
Ready Flag
3-4-20 Peripheral Port Communications Areas
Peripheral Port Error Code
SR bits 26408 to 26411 are set when there is a peripheral port error in the Gener-
al I/O Mode.
Error code
Error type
Error conditions
Valid modes
All modes
0
1
No error
---
Parity error
When data received differs from
positive/negative parity setting.
All modes
2
3
4
Framing error
Overrun error
Timeout error
When step bit cannot be detected.
When data is not properly received.
All modes
All modes
When a timeout occurs for two PCs linked
one-to-one.
1:1 PC Link slave or 1:1
PC Link master
Peripheral Port
Communication Error Bit
SR bit 26412 turns ON when there is a peripheral port communication error (ef-
fective in General I/O Mode).
Peripheral Port Send Ready SR bit 26413 turns ON when the PC is ready to transmit data in General I/O
Flag
Mode.
Peripheral Port Reception
Completed Flag
SR bit 26414 turns ON when the PC has completed reading data from a periph-
eral device. Effective in General I/O Mode.
Peripheral Port Reception
Overflow Flag
SR bit 26415 turns ON when data overflow occurs following the reception of
data. Effective in General I/O Mode.
Peripheral Reception
Counter
SR 26600 to SR 26615 contains the number of peripheral port receptions in
General I/O Mode (BCD).
Host Link Level 0 Send
Ready Flag
SR bit 26705 turns ON when the PC is ready to transmit to the Host Link Unit.
Host Link Level 1 Receive
Ready Flag
SR bit 26713 turns ON when the PC is ready to receive data from the Host Link.
3-4-21 Memory Cassette Areas
Memory Cassette Contents
SR 26900 to SR 26907 indicate the type of memory used for the Memory Cas-
sette.
Memory Type
Code
Nothing
UM
00
01
02
03
IOM
HIS
Memory Cassette Capacity
SR 26908 to SR 26910 indicate the memory capacity of the Memory Cassette.
Capacity
0 KW (no board mounted)
4 KW/8 KW
Code
0
2
3
4
16 KW
32 KW
EEPROM/EPROM Memory
Cassette Mounted Flag
SR bit 26914 turns ON when EEPROM Memory Cassette is protected or
EPROM Memory Cassette is mounted.
46
SR (Special Relay) Area
Section 3-4
Memory Cassette Flag
SR bit 26915 turns ON when a Memory Cassette is mounted.
Save UM to Cassette Flag
SR bit 27000 turns ON when UM data is read to a Memory Cassette in Program
Mode. Bit will automatically turn OFF. An error will be produced if turned ON in
any other mode.
Load UM from Cassette
Flag
SR bit 27001 turns ON when data is loaded into UM from a Memory Cassette in
Program Mode. Bit will automatically turn OFF. An error will be produced if
turned ON in any other mode.
Collation (Between DM and
Memory Cassette)
SR bit 27002 turns ON when data has been compared between DM and a
Memory Cassette. SR bit 27003 is turned OFF if the data in the Memory Cas-
sette matches and it is turned ON if the data does not match.
3-4-22 Data Transfer Error Bits
Data will not be transferred from UM to the Memory Cassette if an error occurs
(except for Board Checksum Error). Detailed information on checksum errors
occurring in the Memory Cassette will not be output to SR 272 because the in-
formation is not needed. Repeat the transmission if SR 27015 is ON.
Transfer Error Flag:
Active Data Link
SR bit 27011 turns ON when an attempt is made to transfer the UM used for the
SYSMAC NET data link table while the data link is active.
Transfer Error Flag:
Not PROGRAM Mode
SR bit 27012 turns ON when the PC is not in Program Mode and data transfer is
attempted.
Transfer Error Flag:
Read Only
SR bit 27013 turns ON when the PC is in Read-only Mode and data transfer is
attempted.
Transfer Error Flag:
Insufficient Capacity or No
UM
SR bit 27014 turns ON when data transfer is attempted and available UM is in-
sufficient.
Transfer Error Flag: Board
Checksum Error
SR bit 27015 turns ON when data transfer is attempted and a Board Checksum
error occurs.
3-4-23 Ladder Diagram Memory Areas
Memory Cassette Ladder
Diagram Size Area
SR 27100 to SR 27107 indicate the amount of ladder program stored in a
Memory Cassette. Ladder-only Files:
04: 4 KW; 08: 8 KW; 12: 12 KW; ... (32: 32 KW)
00:Memory Cassette contents not UM or there is no file.
CPU Unit Ladder Diagram
Size and Type
SR 27108 to SR 27115 indicate the CPU Unit’s ladder program size and type.
Specifications are the same as for bits 00 to 07.
3-4-24 Memory Error Flags
Memory Error Flag: PC
Setup Error
SR bit 27211 turns ON when a PC Setup Checksum error occurs.
Memory Error Flag: Ladder
Checksum Error
SR bit 27212 turns ON when a Ladder Checksum error occurs.
Memory Error Flag:
Instruction Change Error
SR bit 27213 turns ON when an instruction change vector area error occurs.
Memory Error Flag: Memory SR bit 27214 turns ON when a Memory Cassette is connected or disconnected
Cassette Disconnect Error
during operations.
47
AR (Auxiliary Relay) Area
Section 3-5
Memory Error Flag:
Autoboot Error
SR bit 27215 turns ON when an autoboot error occurs.
3-4-25 Data Save Flags
Data transferred to Memory Cassette when Bit is turned ON in PROGRAM
mode. Bit will automatically turn OFF. An error will be produced if turned ON in
any other mode.
Save IOM to Cassette Bit
SR bit 27300 turns ON when IOM is saved to a Memory Cassette.
Load IOM from Cassette Bit SR bit 27301 turns ON when loading to IOM from a Memory Cassette.
3-4-26 Transfer Error Flags
Data will not be transferred from IOM to the Memory Cassette if an error occurs
(except for Read Only Error).
Transfer Error Flag: Not
PROGRAM mode
SR bit 27312 turns ON when attempting to transfer data in other than Program
Mode.
Transfer Error Flag
Transfer Error Flag
SR bit 27313 turns ON when attempting to transfer data in Read-only Mode.
SR bit 27314 turns ON when attempting to transfer data and IOM capacity is in-
sufficient.
3-4-27 PC Setup Error Flags
PC Setup Startup Error
SR bit 27500 turns ON when a PC Setup Startup error occurs (DM6600 to
DM6605).
PC Setup RUN Error
SR bit 27501 turns ON when a PC Setup Run error occurs (DM6613 to
DM6623).
PC Setup
Communications/Error
Setting/Misc. Error
SR bit 27502 turns ON when a PC Setup Communications, Error setting or Mis-
cellaneous error occurs (DM 6635 to DM 6655).
3-4-28 Clock and Keyboard Mapping
Clock (SR 276)
SR 276 contains the current time. SR bits 27600 to 27607 contain the minutes
(00 to 59) and SR bits 27608 to 27615 contain the hours (0 to 23).
Keyboard Mapping (SR 277) SR 277 through SR 279 are used for keyboard mapping.
3-4-29 Group-2 Error Flags
SR bits 28000 to SR 28015 are used as Error Flags for Group-2 High-density I/O
Units with unit numbers 0 to F. The corresponding Error Flag is turned ON when
an error occurs in that Unit. Ten bits in the AR area (AR 0205 to AR 0214) are also
used as Error Flags for Units 0 to 9.
3-4-30 Special I/O Unit Restart Bits and Error Flags
SR bits 28100 to SR 28115 are used as Restart Bits for Special I/O Units with unit
numbers 0 to F. Turn the corresponding bit ON and OFF to restart a Special I/O
Unit. Ten bits in the AR area (AR 0100 to AR 0109) are also used as Restart Bits
for Units 0 to 9.
SR bits 28200 to SR 28215 are used as Error Flags for Special I/O Units with unit
numbers 0 to F. The corresponding Error Flag is turned ON when an error occurs
in that Unit. Ten bits in the AR area (AR 0000 to AR 0009) are also used as Error
Flags for Units 0 to 9.
3-5 AR (Auxiliary Relay) Area
AR word addresses extend from AR 00 to AR 27; AR bit addresses extend from
AR 0000 to AR 2715. Most AR area words and bits are dedicated to specific
48
AR (Auxiliary Relay) Area
Section 3-5
uses, such as transmission counters, flags, and control bits, and words AR 00
through AR 07 and AR 23 through AR 27 cannot be used for any other purpose.
Words and bits from AR 08 to AR 17 are available as work words and work bits if
not used for the following assigned purposes.
Word
AR 08 to AR 15
AR 16, AR 17
Use
SYSMAC LINK Units
SYSMAC LINK and SYSMAC NET Link Units
The AR area retains status during power interruptions, when switching from
MONITOR or RUN mode to PROGRAM mode, or when PC operation is
stopped. Bit allocations are shown in the following table and described in the fol-
lowing pages in order of bit number.
AR Area Flags and Control Bits
Word(s)
Bit(s)
Function
00
00 to 09
Error Flags for Special I/O Units 0 to 9 and PC Link Units 0 to 9
(The function of these flags is duplicated in SR 28200 through SR 28209.)
10
Error Flag for operating level 1 of SYSMAC LINK or SYSMAC NET Link System
Error Flag for operating level 0 of SYSMAC LINK or SYSMAC NET Link System
Host Computer to Rack-mounting Host Link Unit Level 1 Error Flag
Host Computer to Rack-mounting Host Link Unit Level 0 Error Flag
Remote I/O Master Unit 1 Error Flag
11
12
13
14
15
Remote I/O Master Unit 0 Error Flag
01
00 to 09
Restart Bits for Special I/O Units 0 to 9 and PC Link Units 0 to 9
(The operation of these bits is duplicated in SR 28100 through SR 28109.)
10
Restart Bit for operating level 1 of SYSMAC LINK or SYSMAC NET Link System
Restart Bit for operating level 0 of SYSMAC LINK or SYSMAC NET Link System
Not used.
11
12, 13
14
Remote I/O Master Unit 1 Restart Bit.
15
Remote I/O Master Unit 0 Restart Bit.
02
00 to 04
05 to 14
15
Slave Rack Error Flags (#0 to #4)
Group-2 Error Flags (Bits 05 through 14 correspond to Units 0 to 9.)
Group-2 Error Flag
03
04
05
06
07
00 to 15
00 to 15
00 to 15
00 to 15
00 to 03
04 to 07
08
Error Flags for Optical I/O Units and I/O Terminals 0 to 7
Error Flags for Optical I/O Units and I/O Terminals 8 to 15
Error Flags for Optical I/O Units and I/O Terminals 16 to 23
Error Flags for Optical I/O Units and I/O Terminals 24 to 31
Data Link setting for operating level 0 of SYSMAC LINK System
Data Link setting for operating level 1 of SYSMAC LINK System
TERMINAL Mode Input Cancel Bit
09
Expansion TERMINAL Mode ON/OFF Bit
10 to 11
12
Not used.
Same as status of pin 6 on CPU Unit’s DIP switch
Error History Overwrite Bit
13
14
Error History Reset Bit
15
Error History Enable Bit
08 to 11
12 to 15
16
00 to 15
00 to 15
00 to 15
00 to 15
00 to 07
08 to 15
Active Node Flags for SYSMAC LINK System nodes of operating level 0
Active Node Flags for SYSMAC LINK System nodes of operating level 1
SYSMAC LINK/SYSMAC NET Link System operating level 0 service time per cycle
SYSMAC LINK/SYSMAC NET Link System operating level 1 service time per cycle
Seconds: 00 to 59
17
18
Minutes: 00 to 59
49
AR (Auxiliary Relay) Area
Section 3-5
Word(s)
Bit(s)
00 to 07
08 to 15
00 to 07
08 to 15
00 to 07
Function
19
20
21
Hours: 00 to 23 (24-hour system)
Day of Month: 01 to 31 (adjusted by month and for leap year)
Month: 1 to 12
Year: 00 to 99 (Rightmost two digits of year)
Day of Week: 00 to 06 (00: Sunday; 01: Monday; 02: Tuesday; 03: Wednesday; 04:
Thursday; 05: Friday; 06: Saturday)
08 to 12
13
Not used.
30-second Compensation Bit
14
Clock Stop Bit
15
Clock Set Bit
22
23
24
00 to 15
00 to 15
00
Keyboard Mapping
Power Off Counter (BCD)
SYSMAC LINK – RS-232C Peripheral Device Flag
SYSMAC LINK – Port A Peripheral Device Flag
SYSMAC LINK – Port B Peripheral Device Flag
SYSMAC LINK – Peripheral Device Initialization BIt
Not used.
01
02
03
04
05
Cycle Time Flag
06
SYSMAC LINK System Network Parameter Flag for operating level 1
SYSMAC LINK System Network Parameter Flag for operating level 0
SYSMAC LINK/SYSMAC NET Link Unit Level 1 Mounted Flag
SYSMAC LINK/SYSMAC NET Link Unit Level 0 Mounted Flag
Not used.
07
08
09
10
11
PC Link Unit Level 1 Mounted Flag
PC Link Unit Level 0 / Single Level Mounted Flag
Rack-mounting Host Link Unit Level 1 Mounted Flag
Rack-mounting Host Link Unit Level 0 Mounted Flag
CPU Unit-mounting Device Mounted Flag
12
13
14
15
25
00 to 07
Password for access to the Online Edit Disable Bit
(The Online Edit Disable Bit is valid when this byte contains 5A.)
08
FPD(––) Trigger Bit
09
Online Edit Disable Bit
Online Edit Standby Flag
Not used.
10
11
12
Trace End Flag
13
Tracing Flag
14
Trace Trigger Bit (writeable)
Trace Start Bit (writeable)
Maximum Cycle Time (0.1 ms)
Present Cycle Time (0.1 ms)
15
26
27
00 to 15
00 to 15
3-5-1 Restarting Special I/O Units
AR bits 0100 to AR 0109 correspond to the unit numbers of Special I/O Units 0 to
9. To restart Special I/O Units (including PC Link Units) turn the corresponding
bit ON and OFF (or turn power ON and OFF). Do not access data refreshed for
Special I/O Units during restart processing (see SR 27400 to SR 27409 on page
37).
Note Bits SR 28100 to SR 28115 also act as Restart Bits for Special I/O Units 0 to F.
50
AR (Auxiliary Relay) Area
Section 3-5
3-5-2 Slave Rack Error Flags
AR bits 0200 to AR 0204 correspond to the unit numbers of Remote I/O Slave
Units #0 to #4. These flags will turn ON if the same number is allocated to more
then one Slave or if a transmission error occurs when starting the System. Refer
to SR 251 for errors that occur after the System has started normally.
3-5-3 Group-2 Error Flags
Bits AR 0205 to AR 0215 correspond to Group-2 High-density I/O Units and B7A
Interface Units 0 to 9 (I/O numbers) and will turn ON when the same number is
set for more than one Unit, when the same word is allocated to more than one
Unit, when I/O number 9 is set for a 64-point Unit, or when the fuse burns out in a
Transistor High-density I/O Unit. AR bit 0215 will turn ON when a Unit is not rec-
ognized as a Group-2 High-density I/O Unit.
Note Bits SR 28000 to SR 28015 also act as Error Flags for Group-2 High-density I/O
Units with unit numbers 0 to F.
3-5-4 Optical I/O Unit and I/O Terminal Error Flags
AR 03 through AR 06 contain the Error Flags for Optical I/O Units and I/O Termi-
nals. An error indicates a duplication of a unit number. Up to 64 Optical I/O Units
and I/O Terminals can be connected to the PC. Units are distinguished by unit
number, 0 through 31, and a letter, L or H. Bits are allocated as shown in the fol-
lowing table.
Optical I/O Unit and I/O
Terminal Error Flags
Bits
00
AR03
AR04
AR05
AR06
allocation allocation allocation allocation
0 L
0 H
1 L
1 H
2 L
2 H
3 L
3 H
4 L
4 H
5 L
5 H
6 L
6 H
7 L
7 H
8 L
16 L
16 H
17 L
17 H
18 L
18 H
19 L
19 H
20 L
20 H
21 L
21 H
22 L
22 H
23 L
23 H
24 L
24 H
25 L
25 H
26 L
26 H
27 L
27 H
28 L
28 H
29 L
29 H
30 L
30 H
31 L
31 H
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
8 H
9 L
9 H
10 L
10 H
11 L
11 H
12 L
12 H
13 L
13 H
14 L
14 H
15 L
15 H
51
AR (Auxiliary Relay) Area
Section 3-5
3-5-5 SYSMAC LINK System Data Link Settings
AR 0700 to AR 0703 and AR 0704 to AR 0707 are used to designate word alloca-
tions for operating levels 0 and 1 of the SYSMAC LINK System. Allocation can
be set to occur either according to settings from the SSS or automatically in the
LR and/or DM areas. If automatic allocation is designated, the number of words
to be allocated to each node is also designated. These settings are shown be-
low.
External/Automatic
Allocation
Operating level 0
AR 0700 AR 0701
Operating level 1
AR 0704 AR 0705
Setting
0
0
0
0
Words set externally (SSS)
1
0
1
0
1
1
1
0
1
0
1
1
Automatic
allocation
LR area only
DM area only
LR and DM
areas
Words per Node
The following setting is necessary if automatic allocation is designated above.
Operating level 0
Operating level 1
Words per node
DM area
Max. no.
of nodes
AR 0702 AR 0703 AR 0706 AR 0707 LR area
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
4
8
16
8
16
32
64
8
4
2
16
32
The above settings are read every cycle while the SYSMAC LINK System is in
operation.
3-5-6 Error History Bits
AR 0713 (Error History Overwrite Bit) is turned ON or OFF by the user to control
overwriting of records in the Error History Area in the DM area. Turn ON AR 0713
to overwrite the oldest error record each time an error occurs after 10 have been
recorded. Turn OFF AR 0713 to store only the first 10 records that occur each
time after the history area is cleared.
AR 0714 (Error History Reset Bit) is turned ON and then OFF by the user to reset
the Error Record Pointer (DM 6000) and thus restart recording error records at
the beginning of the history area.
AR 0715 (Error History Enable Bit) is turned ON by the user to enable error histo-
ry storage and turned OFF to disable error history storage.
Refer to 3-6 DM Area for details on the Error History Area.
Error history bits are refreshed each cycle.
3-5-7 Active Node Flags
AR 08 through AR 11 and AR 12 through AR 15 provide flags that indicate which
nodes are active in the SYSMAC LINK System at the current time. These flags
are refreshed every cycle while the SYSMAC LINK System is operating.
The body of the following table show the node number assigned to each bit. If the
bit is ON, the node is currently active.
Level 0
AR 08
Level 1
Bit (body of table shows node numbers)
00
01
02
03
04
05
06
07
08
09
10
10
11
11
12
12
13
13
14
14
15
15
16
AR 12
AR 13
AR 14
AR 15
1
2
3
4
5
6
7
8
9
AR 09
AR 10
AR 11
17
33
49
18
34
50
19
35
51
20
36
52
21
37
53
22
38
54
23
39
55
24
40
56
25
41
57
26
42
58
27
43
59
28
44
60
29
45
61
30
46
62
31
47
*
32
48
**
*Communication Controller Error Flag
**EEPROM Error Flag
52
AR (Auxiliary Relay) Area
Section 3-5
3-5-8 SYSMAC LINK/SYSMAC NET Link System Service Time
AR 16 provides the time allocated to servicing operating level 0 of the SYSMAC
LINK System and/or SYSMAC NET Link System during each cycle when a SYS-
MAC LINK Unit and/or SYSMAC NET Link Unit is mounted to a Rack.
AR 17 provides the time allocated to servicing operating level 1 of the SYSMAC
LINK System and/or SYSMAC NET Link System during each cycle when a SYS-
MAC LINK Unit and/or SYSMAC NET Link Unit is mounted to a Rack.
These times are recorded in 4-digit BCD to tenths of a millisecond (000.0 ms to
999.9 ms) and are refreshed every cycle.
Bits
15 to 12 11 to 08 07 to 04 03 to 00
2
1
0
–1
10
10
10
10
3-5-9 Calendar/Clock Area and Bits
Calendar/Clock Area
A clock is built into the C200HX/HG/HE CPU Units. If AR 2114 (Clock Stop Bit) is
OFF, then the date, day, and time will be available in BCD in AR 18 to AR 20 and
AR 2100 to AR 2108 as shown below. This area can also be controlled with AR
2113 (30-second Compensation Bit) and AR 2115 (Clock Set Bit).
Calendar/Clock Bits
Bits
Contents
Possible values
AR 1800 to AR 1807 Seconds
AR 1808 to AR 1815 Minutes
AR 1900 to AR 1907 Hours
AR 1908 to AR 1915 Day of month
AR 2000 to AR 2007 Month
AR 2008 to AR 2015 Year
AR 2100 to AR 2107 Day of week
00 to 59
00 to 59
00 to 23 (24-hour system)
01 to 31 (adjusted by month and for leap year)
1 to 12
00 to 99 (Rightmost two digits of year)
00 to 06 (00: Sunday; 01: Monday; 02: Tuesday; 03: Wednesday; 04:
Thursday; 05: Friday; 06: Saturday)
30-second Compensation Bit AR 2113 is turned ON to round the seconds of the Calendar/clock Area to zero,
i.e., if the seconds is 29 or less, it is merely set to 00; if the seconds is 30 or great-
er, the minutes is incremented by 1 and the seconds is set to 00.
Clock Stop Bit
AR 2114 is turned OFF to enable the operation of the Calendar/clock Area and
ON to stop the operation.
Clock Set Bit
AR 2115 is used to set the Calendar/clock Area as described below. This data
must be in BCD and must be set within the limits for the Calendar/clock Area
given above.
1, 2, 3...
1. Turn ON AR 2114 (Stop Bit).
2. Set the desired date, day, and time, being careful not to turn OFF AR 2114
(Clock Stop Bit) when setting the day of the week (they’re in the same word).
(On the Programming Console, the Bit/Digit Monitor and Force Set/Reset
Operations are the easiest ways to set this data.)
3. Turn ON AR 2115 (Clock Set Bit). The Calendar/clock will automatically start
operating with the designated settings and AR 2114 and AR 2115 will both
be turned OFF.
The Calendar/clock Area and Bits are refreshed each cycle while operational.
Note The accuracy of the clock is as follows:
Temperature
55°C
25°C
Accuracy/month
–3 to 0 minutes
±1 minute
0°C
–2 to 0 minutes
53
AR (Auxiliary Relay) Area
Section 3-5
3-5-10 TERMINAL Mode Key Bits
If the Programming Console is mounted to the PC and is in TERMINAL mode,
any inputs on keys 0 through 9 (including characters A through F, i.e., keys 0
through 5 with SHIFT) will turn on a corresponding bit in AR 22. TERMINAL
mode is entered by a Programming Console operation.
The bits in AR 22 correspond to Programming Console inputs as follows:
Bit
AR 2200
AR 2201
AR 2202
AR 2203
AR 2204
AR 2205
AR 2206
AR 2207
AR 2208
AR 2209
AR 2210
AR 2211
AR 2212
AR 2213
AR 2214
AR 2215
Programming Console input
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Refer to Section 7 Program Monitoring and Execution for details on the TERMI-
NAL mode.
3-5-11 Power OFF Counter
AR 23 provides in 4-digit BCD the number of times that the PC power has been
turned OFF. This counter can be reset as necessary using the PV Change 1 op-
eration from the Programming Console. (Refer to 7-2-4 Hexadecimal/BCD Data
Modification for details.) The Power OFF Counter is refreshed every time power
is turned ON.
3-5-12 SYSMAC LINK – Peripheral Device Flags
A Peripheral Device can be used through the SYSMAC LINK System from only
one port at a time. When changing the port from which the Peripheral Device is
being used, turn ON the SYSMAC LINK – Peripheral Device Initialization Bit
(AR 2403).
Bit
Function
AR 2400 SYSMAC LINK – RS-232C Peripheral Device Flag
(This flag is turned ON when a Peripheral Device is being used through
the SYSMAC LINK System from the RS-232C port.)
AR 2401 SYSMAC LINK – Port A Peripheral Device Flag
(This flag is turned ON when a Peripheral Device is being used through
the SYSMAC LINK System from Communications Board port A.)
AR 2402 SYSMAC LINK – Port B Peripheral Device Flag
(This flag is turned ON when a Peripheral Device is being used through
the SYSMAC LINK System form Communications Board port B.)
AR 2403 SYSMAC LINK – Peripheral Device Initialization Bit
(Turn this bit ON to initialize the usage of a Peripheral Device through the
SYSMAC LINK System.)
54
AR (Auxiliary Relay) Area
Section 3-5
3-5-13 Cycle Time Flag
AR 2405 turns ON when the cycle time set with SCAN(18) is shorter than the
actual cycle time.
AR 2405 is refreshed every cycle while the PC is in RUN or MONITOR mode.
3-5-14 Link Unit Mounted Flags
The following flags indicate when the specified Link Units are mounted to the
Racks. (Refer to 3-5-15 CPU Unit-mounting Device Mounted Flag for CPU Unit-
mounting Host Link Units.) These flags are refreshed every cycle.
Name
Bit
Link Unit
SYSMAC LINK/SYSMAC NET Link Unit AR 2408
Level 1 Mounted Flag
SYSMAC LINK/SYSMAC NET Link Unit in operating level 1
SYSMAC LINK/SYSMAC NET Link Unit AR 2409
Level 0 Mounted Flag
SYSMAC LINK/SYSMAC NET Link Unit in operating level 0
Rack-mounting Host Link Unit Level 1
Rack-mounting Host Link Unit Level 0
AR 2413
AR 2414
Rack-mounting Host Link Unit in operating level 1
Rack-mounting Host Link Unit in operating level 0
3-5-15 CPU Unit-mounting Device Mounted Flag
AR 2415 turns ON when any device is mounted directly to the CPU Unit. This
includes CPU Unit-mounting Host Link Units, Programming Consoles, and In-
terface Units. This flag is refreshed every cycle.
3-5-16 FPD Trigger Bit
AR 2508 is used to adjust the monitoring time of FPD(––) automatically. Refer to
5-25-12 FAILURE POINT DETECT – FPD(––) for details.
3-5-17 Data Tracing Flags and Control Bits
The following control bits and flags are used during data tracing with TRSM(45).
The Tracing Flag will be ON during tracing operations. The Trace Completed
Flag will turn ON when enough data has been traced to fill Trace Memory.
Bit
AR 2512
AR 2513
AR 2514
AR 2515
Name
Trace Completed Flag
Tracing Flag
Trace Trigger Bit (writeable)
Sampling Start Bit (writeable)
Note Refer to 5-25-3 TRACE MEMORY SAMPLING – TRSM(45) for details.
3-5-18 Cycle Time Indicators
AR 26 contains the maximum cycle time that has occurred since program execu-
tion was begun. AR 27 contains the present cycle time.
Both times are to tenths of a millisecond in 4-digit BCD (000.0 ms to 999.9 ms),
and are refreshed every cycle.
55
DM (Data Memory) Area
Section 3-6
3-6 DM (Data Memory) Area
The DM area is divided into various parts as described in the following table. A
portion of UM (up to 3,000 words in 1,000-word increments) can be allocated as
Expansion DM.
Addresses
User
read/write
Usage
DM 0000 to DM 0999
DM 1000 to DM 2599
Read/Write Normal DM.
1
Special I/O Unit Area
DM 2600 to DM 5999
DM 6000 to DM 6030
DM 6100 to DM 6143
DM 6144 to DM 6599
DM 6600 to DM 6655
DM 7000 to DM 9999
Normal DM.
History Log
Reserved
Read only
System Settings
PC Setup
2
Expansion DM
Note 1. The PC Setup can be set to use DM 7000 through DM 8599 as the Special
I/O Area instead of DM 1000 to DM 2599. Refer to 3-6-4 PC Setup for de-
tails.
When Special I/O Units are used, 100 words are occupied by each Unit, as
follows:
Unit #0:
Unit #1:
(...)
DM 1000 to DM 1099
DM 1100 to DM 1199
Unit #9:
Unit #A:
(...)
DM 1900 to DM 1999
DM 2000 to DM 2099
Unit #F:
DM 2500 to DM 2599
2. The UM Area Allocation Programming Console operation can be used to al-
locate up to 3000 words of UM as Expansion DM.
Although composed of 16-bit words like any other data area, data in the DM area
cannot be specified by bit for use in instructions with bit operands. DM 0000 to
DM 6143 can be written to by the program, but DM 6144 to DM 6655 can be over-
written only from a Peripheral Device, such as a Programming Console or com-
puter with SSS.
The DM area retains status during power interruptions.
DM 6031 cannot be used in user applications because it is used by the system to
store EM bank number information and indirect DM addresses.
Indirect Addressing
Normally, when the content of a data area word is specified for an instruction, the
instruction is performed directly on the content of that word. For example, sup-
pose MOV(21) is performed with DM 0100 as the first operand and LR 20 as the
second operand. When this instruction is executed, the content of DM 0100 is
moved to LR 20.
Note Expansion DM cannot be used for indirect addressing.
It is possible, however, to use indirect DM addresses as the operands for many
instructions. To indicate an indirect DM address, ꢀDM is input with the address of
the operand. With an indirect address, with content of this operand does not con-
tain the actual data to be used. Instead, its contents is assumed to hold the ad-
dress of another DM word, the content of which will actually be used in the
instruction. If ꢀDM 0100 was used in our example above and the content of DM
0100 is 0324, then ꢀDM 0100 actually means that the content of DM 0324 is to
56
DM (Data Memory) Area
Section 3-6
be used as the operand in the instruction, and the content of DM 0324 will be
moved to LR 00.
Word
Content
4C59
0324
MOV(21)
ꢀDM 0100
LR 00
DM 0099
DM 0100
DM 0101
Indirect
address
Indicates
DM 0324
F35A
DM 0324
DM 0325
DM 0326
5555
2506
D541
5555 moved
to LR 00.
3-6-1 Expansion DM Area
The expansion DM area is designed to provide memory space for storing oper-
ating parameters and other operating data for Link Units and Special I/O Units.
Up to 3,000 words of UM can be allocated as Expansion DM (in 1K-word incre-
ments) using the UM ALLOCATION operation in the Programming Console or
SSS. Expansion DM area addresses run from DM 7000 to DM 9999.
The data in the expansion DM area can be transferred to the Special I/O Unit
Default Area (DM 1000 to DM 1999) when starting the PC or via programming
instruction to easily change operating parameters, enabling rapid switching be-
tween control processes. The expansion DM area can also be used to store pa-
rameters for other devices connected in the PC system, e.g., Programmable
Terminal character string or numeral tables.
The expansion DM area is used to store operating parameters and cannot be
used in programming like the normal DM area. Expansion DM can only be over-
written from a Peripheral Device, retains status during power interruptions, and
cannot be used for indirect addressing.
The UM area can be allocated as expansion DM area in increments of 1K words.
Once expansion DM area has been created, it is saved and transferred as part of
the program, i.e., no special procedures are required when saving or transfer-
ring the program.
UM ALLOCATION Operation The procedure for the Programming Console’s UM ALLOCATION operation is
shown below. Refer to 4-6-3 Clearing Memory for details on the DATA CLEAR
and UM ALLOCATION instructions.
1, 2, 3...
1. Clear memory.
CLR
NOT
SET
RESET
EXT
MONTR
Note UM allocation is not possible unless memory is cleared first.
2. The expansion DM area can be set to 0, 1, 2, or 3 K words. The following key
sequence creates a 2-KW expansion DM area (DM 7000 to DM 8999).
CLR
FUN
VER
CHG
2
SET
9
7
1
3
WRITE
Press the 0 Key to eliminate the expansion DM area (0 KW).
or Press the 1 Key to allocate DM 7000 to DM 7999 (1 KW).
or Press the 2 Key to allocate DM 7000 to DM 8999 (2 KW).
or Press the 3 Key to allocate DM 7000 to DM 9999 (3 KW).
57
DM (Data Memory) Area
Section 3-6
3-6-2 Special I/O Unit Data
Special I/O Units are allocated 1000 or 1600 words in the DM Area depending on
the value set in word DM 6602 of the PC Setup. The DM 6602 setting determines
whether the Special I/O Unit Data area is setup for 10 or 16 Units and whether
the data is stored in read/write DM (DM 1000 to DM 2599) or read-only DM
(DM 7000 to DM 8599). Refer to Appendix E for details.
Unit
Addresses
0
1
2
3
4
5
6
7
8
9
DM 1000 to DM 1099 or DM 7000 to DM 7099
DM 1100 to DM 1199 or DM 7100 to DM 7199
DM 1200 to DM 1299 or DM 7200 to DM 7299
DM 1300 to DM 1399 or DM 7300 to DM 7399
DM 1400 to DM 1499 or DM 7400 to DM 7499
DM 1500 to DM 1599 or DM 7500 to DM 7599
DM 1600 to DM 1699 or DM 7600 to DM 7699
DM 1700 to DM 1799 or DM 7700 to DM 7799
DM 1800 to DM 1899 or DM 7800 to DM 7899
DM 1900 to DM 1999 or DM 7900 to DM 7999
DM 2000 to DM 2099 or DM 8000 to DM 8099
DM 2100 to DM 2199 or DM 8100 to DM 8199
DM 2200 to DM 2299 or DM 8200 to DM 8299
DM 2300 to DM 2399 or DM 8300 to DM 8399
DM 2400 to DM 2499 or DM 8400 to DM 8499
DM 2500 to DM 2599 or DM 8500 to DM 8599
A
B
C
D
E
F
Note These DM words can be used for other purposes when not allocated to Special
I/O Units.
3-6-3 Error History Area
DM 6000 to DM 6030 are used to store up to 10 records that show the nature,
time, and date of errors that have occurred in the PC.
The Error History Area will store system-generated or FAL(06)/FALS(07)-gener-
ated error codes whenever AR 0715 (Error History Enable Bit) is ON. Refer to
Section 9 Troubleshooting for details on error codes.
Area Structure
Error records occupy three words each stored between DM 6001 and DM 6030.
The last record that was stored can be obtained via the content of DM 6000 (Er-
ror Record Pointer). The record number, DM words, and pointer value for each of
the ten records are as follows:
Record
None
Addresses
Pointer value
N.A.
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
000A
1
2
3
4
5
6
7
8
9
10
DM 6001 to DM 6003
DM 6004 to DM 6006
DM 6007 to DM 6009
DM 6010 to DM 6012
DM 6013 to DM 6015
DM 6016 to DM 6018
DM 6019 to DM 6021
DM 6022 to DM 6024
DM 6025 to DM 6027
DM 6028 to DM 6030
58
DM (Data Memory) Area
Section 3-6
Although each of them contains a different record, the structure of each record is
the same: the first word contains the error code; the second and third words, the
day and time. The error code will be either one generated by the system or by
FAL(06)/FALS(07); the time and date will be the date and time from AR 18 and
AR 19 (Calender/date Area). Also recorded with the error code is an indication of
whether the error is fatal (08) or non-fatal (00). This structure is shown below.
Word
Bit
Content
Error code
First
00 to 07
08 to 15
00 to 07
08 to 15
00 to 07
08 to 15
00 (non-fatal) or 80 (fatal)
Seconds
Second
Third
Minutes
Hours
Day of month
The following table lists the possible error codes and corresponding errors.
Error severity
Error code
Error
Fatal errors
00
Power interruption
01 to 99 or 9F
System error (FALS)
I/O bus error
C0 to C3
E0
Input-output I/O table error
Too many Units
E1
F0
No END(01) instruction
Memory error
F1
Non-fatal errors 01 to 99
System error (FAL)
Interrupt Input error
Interrupt program error
Group 2 High-density I/O error
PC Setup error
8A
8B
9A
9B
9C
Communications Board error
UM Memory Cassette transfer error
Remote I/O error
9D
B0 to B1
D0
Special I/O error
E7
I/O table verification error
Battery error
F7
F8
Cycle time overrun
Operation
When the first error code is generated with AR 0715 (Error History Enable Bit)
turned ON, the relevant data will be placed in the error record after the one indi-
cated by the History Record Pointer (initially this will be record 1) and the Pointer
will be incremented. Any other error codes generated thereafter will be placed in
consecutive records until the last one is used. Processing of further error records
is based on the status of AR 0713 (Error History Overwrite Bit).
If AR 0713 is ON and the Pointer contains 000A, the next error will be written into
record 10, the contents of record 10 will be moved to record 9, and so on until the
contents of record 1 is moved off the end and lost, i.e., the area functions like a
shift register. The Record Pointer will remain set to 000A.
If AR 0713 is OFF and the Pointer reaches 000A, the contents of the Error Histo-
ry Error will remain as it is and any error codes generate thereafter will not be
recorded until AR 0713 is turned OFF or until the Error History Area is reset.
59
DM (Data Memory) Area
Section 3-6
The Error History Area can be reset by turning ON and then OFF
AR 0714 (Error History Reset Bit). When this is done, the Record Pointer will be
reset to 0000, the Error History Area will be reset (i.e., cleared), and any further
error codes will be recorded from the beginning of the Error History Area.
AR 0715 (Error History Enable Bit) must be ON to reset the Error History Area.
3-6-4 PC Setup
The PC Setup (DM 6600 through DM 6655) contains settings that determine PC
operation. Data in the PC Setup can be changed with a Programming Console or
SSS if UM is not write-protected by pin 1 of the CPU Unit’s DIP switch. Refer to
page 20 for details on changing DIP switch pin settings.
The data in DM 6600 through DM 6634 can be set or changed only when the PC
is in PROGRAM mode. The data in DM 6635 through DM 6655 can be set or
changed when the PC is in PROGRAM or MONITOR mode. The following words
can be changed from the SYSMAC Support Software’s PC Setup menu. (The
PC must be in PROGRAM mode.)
1, 2, 3...
1. Startup mode (DM 6600)
2. Startup mode designation (DM 6601)
3. Cycle monitor time (DM 6618)
4. Cycle time setting (DM 6619)
5. RS-232C Port Settings (DM 6645 through DM 6649)
The PC can be operated with the default PC Setup, which requires changing
only when customizing the PC’s operating environment to application needs.
The PC Setup parameters are described in the following table.
If there is an error in the settings in DM 6600 to DM 6655, a non-fatal error (error
code 9B) will occur when the data is read by the PC and one of the flags from
SR 27500 to SR 27502 will turn ON to indicate the location of the error. If there is
an error in the settings in DM 6550 to DM 6559, a non-fatal error (error code 9C)
will occur.
Word(s)
Startup Processing (DM 6600 to DM 6612)
The following settings are accessed only once when the PC is turned ON.
Bit(s)
Function
Default
DM 6600
00 to 07 Startup mode (effective when bits 08 to 15 are set to 02).
00: PROGRAM; 01: MONITOR 02: RUN
PROGRAM
08 to 15 Startup mode designation
00: Programming Console switch
Programming
Console switch
01: Continue operating mode last used before power was turned off
02: Setting in 00 to 07
DM 6601
00 to 07 Reserved
---
08 to 11 IOM Hold Bit (SR 25212) Status
0: Reset; 1: Maintain
Reset
12 to 15 Forced Status Hold Bit (SR 25211) Status
0: Reset; 1: Maintain
60
DM (Data Memory) Area
Section 3-6
Word(s)
Bit(s)
Function
Default
DM 6602
00 to 07 Not used.
---
08 to 15 00: C200H-compatible RAM Mode (Default)
Use DM 1000 through DM 2599 for the initial data area for the Special
DM 1000 to
DM 2599
I/O Unit Area.
• Data in the Special I/O Unit Area can be read/written.
• The data cannot be converted to ROM.
01: C200H-compatible ROM Mode 1
Transfer the contents of DM 7000 through DM 7999 to DM 1000
through DM 1999 at startup and use DM 1000 through DM 1999.
• The UM Area Allocation operation must be performed beforehand.
• The data is compatible with C200H applications that use EEPROM/
EPROM.
• ROM conversion is possible indirectly by writing DM 7000 through DM
7999 to ROM.
02: DM Linear Mode 1
Use DM 7000 through DM 7999 for the initial data area for Special I/O
Unit Area.
• The UM Area Allocation operation must be performed beforehand.
• DM 1000 through DM 1999 can be used as regular DM.
• DM 7000 through DM 7999 can be converted to ROM.
11: C200H-compatible ROM Mode 2
Transfer the contents of DM 7000 through DM 8599 to DM 1000
through DM 2599 at startup and use DM 1000 through DM 2599.
• The UM Area Allocation operation must be performed beforehand.
• ROM conversion is possible indirectly by converting DM 7000 through
DM 8599 to ROM.
12: DM Linear Mode 2
Use DM 7000 through DM 8599 for the Special I/O Unit Area.
• The UM Area Allocation operation must be performed beforehand.
• DM 1000 through DM 2599 can be used as regular DM.
• DM 7000 through DM 8599 can be converted to ROM.
See also 3-6-6 Special I/O Unit Area Settings.
DM 6603 to 00 to 15 Not used.
DM 6604
---
DM 6605
00 to 07 Momentary power interruption time (0 to 10 ms)
Set the momentary power interruption time from 00 to 10 in BCD.
08 to 15 Not used.
0 ms
---
---
DM 6606 to 00 to 15 Not used.
DM 6612
Communications and Cycle Time Settings (DM 6613 to DM 6619)
The following settings are accessed only once when program execution begins.
DM 6613
00 to 07 Servicing time for Communications Board port B
(effective when bits 08 to 15 are set to 01)
No setting
(0000)
00 to 99 (BCD): Percentage of cycle time used to service port B.
Minimum: 0.26 ms; maximum 58.254 ms
08 to 15 Communications Board port B servicing setting enable
00: Do not set service time (Fixed at 5%, 0.26 ms min.)
01: Use time in 00 to 07.
Service time is 10 ms when operation is stopped, regardless of this setting.
61
DM (Data Memory) Area
Section 3-6
Word(s)
Bit(s)
Function
Default
DM 6614
00 to 07 Servicing time for Communications Board port A
(effective when bits 08 to 15 are set to 01)
No setting
(0000)
00 to 99 (BCD): Percentage of cycle time used to service port A.
Minimum: 0.26 ms; maximum 58.254 ms
08 to 15 Communications Board port A servicing setting enable
00: Do not set service time (Fixed at 5%, 0.26 ms min.)
01: Use time in 00 to 07.
Service time is 10 ms when operation is stopped, regardless of this setting.
DM 6615
DM 6616
00 to 15 Reserved
---
00 to 07 Servicing time for RS-232C port (effective when bits 08 to 15 are set to 01)
00 to 99 (BCD): Percentage of cycle time used to service RS-232C port.
No setting
(0000)
Minimum: 0.228 ms; maximum 58.254 ms
08 to 15 (RS-232C port servicing setting enable)
00: Do not set service time (Fixed at 5%, 0.228 ms min.)
01: Use time in 00 to 07.
Service time is 10 ms when operation is stopped, regardless of this setting.
DM 6617
00 to 07 Servicing time for peripheral port (effective when bits 08 to 15 are set to 01) No setting
00 to 99 (BCD): Percentage of cycle time used to service peripheral.
(0000)
Minimum: 0.26 ms; maximum 58.254 ms
08 to 15 Peripheral port servicing setting enable
00: Do not set service time (Fixed at 5%, 0.26 ms min.)
01: Use time in 00 to 07.
Service time is 10 ms when operation is stopped, regardless of this setting.
DM 6618
DM 6619
00 to 07 Cycle monitor time (effective when bits 08 to 15 are set to 01, 02, or 03)
00
00 to 99 (BCD) × setting unit (see 08 to 15)
08 to 15 Cycle monitor enable (Setting in 00 to 07 × setting unit; 99 s max.)
00: 120 ms (setting in bits 00 to 07 disabled)
01: Setting unit: 10 ms
00: 120 ms
02: Setting unit: 100 ms
03: Setting unit: 1 s
00 to 15 Cycle time
Variable
Enable
0000: Variable (no minimum)
0001 to 9999 (BCD): Minimum time in ms
Interrupt/Refresh Processing (DM 6620 to DM 6623)
The following settings are accessed only once when program execution begins.
DM 6620
00 to 09 Special I/O Unit cyclic refresh (Bit number corresponds to unit number, PC
Link Units included)
0: Enable cyclic refresh and I/O REFRESH (IORF(97)) from main program
1: Disable (refresh only for I/O REFRESH from interrupt programs)
A setting of 01 (Disable) is valid only when the interrupt response is set to
high-speed response mode. It is not valid for normal interrupt response or for
Special I/O Units mounted in Slave Racks.
10 to 11 Reserved
---
12 to 15 Interrupt response
Normal
0: Normal (C200H compatible)
Interrupts cannot be received when Host Link servicing, execution of a
single instruction, Remote I/O processing, or Special I/O processing is
being performed. The interrupt subroutine will be executed after the
processing is completed.
1: High-speed Response (C200HS or C200HX/HG/HE)
Interrupts will be received when Host Link servicing, execution of a
single instruction, Remote I/O processing, or Special I/O processing is
being performed. If there is an interrupt input, the current processing will
be interrupted and the interrupt subroutine will be executed.
62
DM (Data Memory) Area
Section 3-6
Word(s)
Bit(s)
Function
Default
DM 6621
00 to 07 Reserved
---
08 to 15 Special I/O Unit refresh (PC Link Units included)
00: Enable refresh for all Special I/O Units
Enable
01: Disable refresh for all Special I/O Units (but, not valid on Slave Racks)
A setting of 1 (Disable) is not valid for Special I/O Units mounted in Slave
Racks.
DM 6622
DM 6623
00 to 07 Scheduled interrupt time unit
10 ms
(0000)
00: 10 ms
01: 1 ms
08 to 15 Scheduled interrupt time unit enable
00: Disable (10 ms)
01: Enable setting in 00 to 07
00 to 15 Special I/O Unit cyclic refresh (PC Link Units included)
(Bit numbers 00 to 15 correspond to unit numbers 0 to F.)
Enable
0: Enable cyclic refresh and I/O REFRESH (IORF(97)) from main program
1: Disable (refresh only for I/O REFRESH from interrupt programs)
A setting of 01 (Disable) is valid only when the interrupt response is set to
high-speed response mode. It is not valid for normal interrupt response or for
Special I/O Units mounted in Slave Racks.
DM 6624 to 00 to 15 Reserved
DM 6644
---
RS-232C Port Settings (DM 6645 to DM 6649)
The following settings are accessed continually while the PC is ON.
DM 6645
00 to 03 Port settings
0: Standard (Host Link or peripheral bus serial communications mode, 1
Standard
start bit, 7-bit data, even parity, 2 stop bits, 9,600 bps)
1: Settings in DM 6646
04 to 07 CTS control setting
Disable
0: Disable CTS control
1: Enable CTS control
08 to 11 Words linked for 1:1 PC Link
LR 00 to LR 63
0: LR 00 to LR 63; 1: LR 00 to LR 31; 2: LR 00 to LR 15
Maximum PT node number for 1:N NT Link
1 to 7 BCD (1 to 3 with a C200HE-CPU j -E PC)
12 to 15 Serial communications mode
j
Host Link
1.2 K
0: Host Link; 1: RS-232C; 2: 1:1 PC Link slave; 3: 1:1 PC Link master;
4: 1:1 NT Link; 5: 1:N NT Link
DM 6646
00 to 07 Baud rate
00: 1.2K, 01: 2.4K, 02: 4.8K, 03: 9.6K, 04: 19.2K
08 to 15 Frame format
Start
1 bit
1 start bit, 7-bit
data, 1 stop bit,
even parity
Length
7 bits
7 bits
7 bits
7 bits
7 bits
7 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
Stop
1 bit
1 bit
1 bit
2 bit
2 bit
2 bit
1 bit
1 bit
1 bit
2 bit
2 bit
2 bit
Parity
Even
Odd
None
Even
Odd
None
Even
Odd
None
Even
Odd
00:
01:
02:
03:
04:
05:
06:
07:
08:
09:
10:
11:
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
None
DM 6647
00 to 15 Transmission delay
0000 to 9999: BCD in 10-ms units.
0 ms
63
DM (Data Memory) Area
Section 3-6
Word(s)
Bit(s)
Function
Default
DM 6648
00 to 07 Node number (Host Link)
00 to 31 (BCD)
0
08 to 11 Start code enable (RS-232C)
0: Disable; 1: Set
Disabled
Disabled
12 to 15 End code enable (RS-232C)
0: Disable (number of bytes received)
1: Set (specified end code)
2: CR, LF
DM 6649
00 to 07 Start code (RS-232C)
Not used
(0000)
00 to FF (binary)
08 to 15 12 to 15 of DM 6648 set to 0:
Number of bytes received
00: Default setting (256 bytes)
01 to FF: 1 to 255 bytes
12 to 15 of DM 6648 set to 1:
End code (RS-232C)
00 to FF (binary)
Peripheral Port Settings (DM 6650 to DM 6654)
The following settings are accessed continually while the PC is ON.
Note To use the peripheral port set to Host Link mode after using it in peripheral bus mode, turn OFF the power once and
turn ON again or disconnect and reconnect the cable.
DM 6650
00 to 03 Port settings
0: Standard (Host Link or peripheral bus serial communications mode, 1
Standard
start bit, 7-bit data, even parity, 2 stop bits, 9,600 bps)
1: Settings in DM 6651
04 to 11 Reserved
---
12 to 15 Serial communications mode
0: Host Link; 1: No-protocol
Host Link
DM 6651
00 to 07 Baud rate
1.2 K
00: 1.2K, 01: 2.4K, 02: 4.8K, 03: 9.6K, 04: 19.2K
08 to 15 Frame format
Start
1 start bit, 7-bit
data, 1 stop bit,
even parity
Length
7 bits
7 bits
7 bits
7 bits
7 bits
7 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
Stop
1 bit
1 bit
1 bit
2 bit
2 bit
2 bit
1 bit
1 bit
1 bit
2 bit
2 bit
2 bit
Parity
Even
Odd
None
Even
Odd
None
Even
Odd
None
Even
Odd
00:
01:
02:
03:
04:
05:
06:
07:
08:
09:
10:
11:
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
None
DM 6652
DM 6653
00 to 15 Transmission delay (Host Link)
0000 to 9999: in 10-ms units.
0 ms
0
00 to 07 Node number (Host Link)
00 to 31 (BCD)
08 to 11 Start code enable (RS-232C)
0: Disable; 1: Set
Disable
Disable
12 to 15 End code enable (RS-232C)
0: Disable (number of bytes received)
1: Set (specified end code)
2: CR, LF
64
DM (Data Memory) Area
Section 3-6
Word(s)
Bit(s)
Function
Default
DM 6654
00 to 07 Start code (RS-232C)
00 to FF (binary)
0000
08 to 15 12 to 15 of DM 6653 set to 0:
Number of bytes received
00: Default setting (256 bytes)
01 to FF: 1 to 255 bytes
12 to 15 of DM 6653 set to 1:
End code (RS-232C)
00 to FF (binary)
Error Settings (DM 6655)
The following settings are accessed continually while the PC is ON.
DM 6655
00 to 03 Interrupt programming error enable
0: Detect interrupt programming errors
1: Do not detect
Detect
04 to 07 Reserved
---
08 to 11 Cycle time monitor enable
0: Detect long cycles as non-fatal errors
1: Do not detect long cycles
Detect
12 to 15 Low battery error enable
Detect
0: Detect low battery voltage as non-fatal error
1: Do not detect low battery voltage
3-6-5 Communications Board Settings
DM 6550 through DM 6554 contain the communications settings for Commu-
nications Board port B and DM 6555 through DM 6559 contain the communica-
tions settings for Communications Board port A.
Word(s)
Bit(s)
Function
Default
Communications Board Port B Settings (DM 6550 to DM 6554)
The following settings are accessed continually while the PC is ON.
DM 6550
00 to 03 Port settings
0: Standard (1 start bit, 7-bit data, even parity, 2 stop bits, 9,600 bps)
Standard
1: Settings in DM 6551
04 to 07 CTS control setting
0: Disable CTS control
Disable
1: Enable CTS control
08 to 11 Words linked for 1:1 PC Link (Cannot be changed once set in the 1:1 PC
Link Master.)
LR 00 to LR 63
0: LR 00 to LR 63; 1: LR 00 to LR 31; 2: LR 00 to LR 15
Maximum PT node number for 1:N NT Link
1 to 7 BCD (1 to 3 with a C200HE-CPU
j
j
-
E
P
C
)
12 to 15 Communications mode
Host Link
0: Host Link; 1: RS-232C; 2: 1:1 PC Link slave; 3: 1:1 PC Link master;
4: 1:1 NT Link; 5: 1:N NT Link; 6: Protocol Macro
65
DM (Data Memory) Area
Section 3-6
Word(s)
Bit(s)
Function
Default
DM 6551
00 to 07 Baud rate
1.2 K
00: 1.2K, 01: 2.4K, 02: 4.8K, 03: 9.6K, 04: 19.2K
08 to 15 Frame format
Start
1 bit
1 start bit, 7-bit
data, 1 stop bit,
even parity
Length
7 bits
7 bits
7 bits
7 bits
7 bits
7 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
Stop
1 bit
1 bit
1 bit
2 bit
2 bit
2 bit
1 bit
1 bit
1 bit
2 bit
2 bit
2 bit
Parity
Even
Odd
None
Even
Odd
None
Even
Odd
None
Even
Odd
00:
01:
02:
03:
04:
05:
06:
07:
08:
09:
10:
11:
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
None
DM 6552
DM 6553
00 to 15 Transmission delay
0000 to 9999: BCD in 10-ms units.
00 to 07 Node number (Host Link)
0 ms
0
00 to 31 (BCD)
08 to 11 Start code enable (RS-232C)
0: Disable; 1: Set
Disabled
Disabled
12 to 15 End code enable (RS-232C)
0: Disable (number of bytes received)
1: Set (specified end code)
2: CR, LF
DM 6554
00 to 07 Start code (RS-232C)
00 to FF (binary)
0000
08 to 15 12 to 15 of DM 6553 set to 0:
Number of bytes received
00: Default setting (256 bytes)
01 to FF: 1 to 255 bytes
12 to 15 of DM 6553 set to 1:
End code (RS-232C)
00 to FF (binary)
Communications Board Port A Settings (DM 6555 to DM 6559)
The following settings are read continually while the PC is ON.
DM 6555
00 to 03 Port settings
Standard
Disable
0: Standard (1 start bit, 7-bit data, even parity, 2 stop bits, 9,600 bps)
1: Settings in DM 6556
04 to 07 CTS control setting
0: Disable CTS control
1: Enable CTS control
08 to 11 Words linked for 1:1 PC Link (Can’t be changed once set in the 1:1 PC Link LR 00 to LR 63
Master.)
0: LR 00 to LR 63; 1: LR 00 to LR 31; 2: LR 00 to LR 15
Maximum PT node number for 1:N NT Link
1 to 7 BCD (1 to 3 with a C200HE-CPU
j
j
-
E
P
C
)
12 to 15 Communications mode
Host Link
0: Host Link; 1: RS-232C; 2: 1-to-1 link slave; 3: 1-to-1 link master;
4: NT Link (1:1); 5: NT Link (1:N); 6: Protocol Macro
66
DM (Data Memory) Area
Section 3-6
Word(s)
Bit(s)
Function
Default
DM 6556
00 to 07 Baud rate
1.2 K
00: 1.2K, 01: 2.4K, 02: 4.8K, 03: 9.6K, 04: 19.2K
08 to 15 Frame format
Start
1 bit
1 start bit, 7-bit
data, 1 stop bit,
even parity
Length
7 bits
7 bits
7 bits
7 bits
7 bits
7 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
Stop
1 bit
1 bit
1 bit
2 bit
2 bit
2 bit
1 bit
1 bit
1 bit
2 bit
2 bit
2 bit
Parity
Even
Odd
None
Even
Odd
None
Even
Odd
None
Even
Odd
00:
01:
02:
03:
04:
05:
06:
07:
08:
09:
10:
11:
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
None
DM 6557
DM 6558
00 to 15 Transmission delay
0000 to 9999: BCD in 10-ms units.
00 to 07 Node number (Host Link)
0 ms
0
00 to 31 (BCD)
08 to 11 Start code enable (RS-232C)
0: Disable; 1: Set
Disabled
Disabled
12 to 15 End code enable (RS-232C)
0: Disable (number of bytes received)
1: Set (specified end code)
2: CR, LF
DM 6559
00 to 07 Start code (RS-232C)
00 to FF (binary)
0000
08 to 15 12 to 15 of DM 6558 set to 0:
Number of bytes received
00: Default setting (256 bytes)
01 to FF: 1 to 255 bytes
12 to 15 of DM 6558 set to 1:
End code (RS-232C)
00 to FF (binary)
3-6-6 Special I/O Unit Area Settings
The setting in bits 08 through 15 of DM 6602 determines the size and location of
the Special I/O Unit Area, as shown in the following table.
Setting
Mode
Function
00
C200H-compatible DM 1000 through DM 2599 are used for the Special I/O Unit Area.
RAM Mode
• Data in the Special I/O Unit Area can be read/written.
• The data cannot be converted to ROM.
01
02
C200H-compatible The contents of DM 7000 through DM 7999 are transferred to DM 1000 through DM 1999
ROM Mode 1
at startup and DM 1000 through DM 1999 are used for the Special I/O Unit Area.
• The UM Area Allocation operation must be performed beforehand.
• The data is compatible with C200H applications that use EEPROM/EPROM.
• ROM conversion is possible indirectly by converting DM 7000 through DM 7999 to ROM.
DM Linear Mode 1 DM 7000 through DM 7999 are used for the Special I/O Unit Area.
• The UM Area Allocation operation must be performed beforehand.
• DM 1000 through DM 1999 can be used as regular DM.
• DM 7000 through DM 7999 can be converted to ROM.
67
TC (Timer/Counter) Area
Section 3-8
Setting
Mode
Function
11
C200H-compatible The contents of DM 7000 through DM 8599 are transferred to DM 1000 through DM 2599
ROM Mode 2
at startup and DM 1000 through DM 2599 are used for the Special I/O Unit Area.
• The UM Area Allocation operation must be performed beforehand.
• ROM conversion is possible indirectly by converting DM 7000 through DM 8599 to ROM.
12
DM Linear Mode 2 DM 7000 through DM 8599 are used for the Special I/O Unit Area.
• The UM Area Allocation operation must be performed beforehand.
• DM 1000 through DM 2599 can be used as regular DM.
• DM 7000 through DM 8599 can be converted to ROM.
DM 7000 through DM 9999 cannot be read or overwritten directly from the pro-
gram. To read this data from the program, the data must be copied to another
data area or regular DM using the EXPANSION DM READ – XDMR(––) instruc-
tion.
When C200H-compatible ROM Mode or DM Linear Mode is set, the UM Area
Allocation operation must be performed in advance to allocate part of the ladder
program area for use as expansion DM. A system error (FAL 9B) will occur if
memory isn’t allocated as expansion DM. Refer to 7-2-15 UM Area Allocation for
details on the UM Area Allocation operation.
When DM Linear Mode is set, the Special I/O Unit’s data area will begin from
DM 7000 instead of DM 1000 so add 6000 to the DM addresses where they ap-
pear in the Special I/O Unit’s Operation Manual.
When the Special I/O Unit Area setting is 01, 02, 11, or 12 and expansion DM
beyond DM 8000 hasn’t been allocated, a Special I/O Unit error will occur for a
Unit with unit number A through F when the Unit accesses its allocated area.
3-7 HR (Holding Relay) Area
The HR area is used to store/manipulate various kinds of data and can be ac-
cessed either by word or by bit. Word addresses range from HR 00 through HR
99; bit addresses, from HR 0000 through HR 9915. HR bits can be used in any
order required and can be programmed as often as required.
The HR area retains status when the system operating mode is changed, when
power is interrupted, or when PC operation is stopped.
HR area bits and words can be used to preserve data whenever PC operation is
stopped. HR bits also have various special applications, such as creating latch-
ing relays with the Keep instruction and forming self-holding outputs. These are
discussed in Section 4 Writing and Inputting the Program and Section 5 Instruc-
tion Set.
Note The required number of words is allocated between HR 00 and HR 42 for routing
tables and to monitor timers when using SYSMAC NET Systems.
3-8 TC (Timer/Counter) Area
The TC area is used to create and program timers and counters and holds the
Completion flags, set values (SV), and present values (PV) for all timers and
counters. All of these are accessed through TC numbers ranging from TC 000
through TC 511. Each TC number is defined as either a timer or counter using
one of the following instructions: TIM, TIMH, CNT, CNTR(12), and TTIM(87). No
prefix is required when using a TC number in a timer or counter instruction.
Once a TC number has been defined using one of these instructions, it cannot
be redefined elsewhere in the program either using the same or a different
instruction. If the same TC number is defined in more than one of these instruc-
tions or in the same instruction twice, an error will be generated during the pro-
gram check. There are no restrictions on the order in which TC numbers can be
used.
68
LR Area
Section 3-9
Once defined, a TC number can be designated as an operand in one or more of
certain set of instructions other than those listed above. When defined as a timer,
a TC number designated as an operand takes a TIM prefix. The TIM prefix is
used regardless of the timer instruction that was used to define the timer. Once
defined as a counter, the TC number designated as an operand takes a CNT
prefix. The CNT is also used regardless of the counter instruction that was used
to define the counter.
TC numbers can be designated for operands that require bit data or for operands
that require word data. When designated as an operand that requires bit data,
the TC number accesses the completion flag of the timer or counter. When des-
ignated as an operand that requires word data, the TC number accesses a
memory location that holds the PV of the timer or counter.
TC numbers are also used to access the SV of timers and counters from a Pro-
gramming Device. The procedures for doing so using the Programming Console
are provided in 7-1 Monitoring Operation and Modifying Data.
The TC area retains the SVs of both timers and counters during power interrup-
tions. The PVs of timers are reset when PC operation is begun and when reset in
interlocked program sections, but the PVs of counters are retained. Refer to
5-10 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) for details on
timer and counter operation in interlocked program sections. The PVs of count-
ers are not reset at these times.
Note that in programming “TIM 000” is used to designate three things: the Timer
instruction defined with TC number 000, the completion flag for this timer, and
the PV of this timer. The meaning in context should be clear, i.e., the first is al-
ways an instruction, the second is always a bit, and the third is always a word.
The same is true of all other TC numbers prefixed with TIM or CNT.
3-9 LR (Link Relay) Area
The LR area is used as a common data area to transfer information between
PCs. This data transfer is achieved through a PC Link System.
Certain words will be allocated as the write words of each PC. These words are
written by the PC and automatically transferred to the same LR words in the oth-
er PCs in the System. The write words of the other PCs are transferred in as read
words so that each PC can access the data written by the other PCs in the PC
Link System. Only the write words allocated to the particular PC will be available
for writing; all other words may be read only. Refer to the PC Link System Manual
for details.
The LR area is accessible either by bit or by word. LR area word addresses
range from LR 00 to LR 63; LR area bit addresses, from LR 0000 to LR 6315. Any
part of the LR area that is not used by the PC Link System can be used as work
words or for SYSMAC NET Link or SYSMAC LINK Systems.
LR area data is not retained when the power is interrupted, when the PC is
changed to PROGRAM mode, or when it is reset in an interlocked program sec-
tion. Refer to 5-10 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03)
for details on interlocks.
69
UM Area
Section 3-10
3-10 UM Area
With the C200HX/HG/HE PCs, the UM area contains the ladder program. Part of
the UM area can be allocated for use as expansion DM or the I/O comment area.
The usable size of the UM area ranges from 3.2 KW in the C200HE-CPU11-E to
31.2 KW in the C200HX-CPUj4-E.
A Programming Console or SYSMAC Support Software (SSS) can be used to
allocate expansion DM, but the I/O comment area can be allocated with SSS
only. The structure of the DM and UM areas is shown in the following illustration.
DM 0000
DM 6144
DM 6600 DM 6655
DM 7000
DM 9999
Expansion
DM Area
(0 to 3 KW)
PC Setup Reserved
I/O Comment
Area
Ladder program
Variable size
UM Area (32 KW max.)
ROM-convertible Area
Special I/O Unit Default Area
DM 1000 to DM 1999
Fixed DM Area
Normal DM Area
Note Refer to the SYSMAC Support Software (SSS) Manual for details on using SSS
to allocate UM for expansion DM or I/O comments. Refer to 7-2-15 UM Area Al-
location for details on using the Programming Console to allocate UM for expan-
sion DM.
Area
Function
Normal DM
This area can be used freely for calculations and programming
instructions. DM can be accessed in word units only.
DM 1000 through DM 2599 are assigned to Special I/O Units
when Special I/O Units are being used, but can be used as
normal DM when the Special I/O Unit Area has been set to
DM 7000 through DM 8599 in the PC Setup (DM 6602).
PC Setup
Reserved
The PC Setup contains various settings that control PC operation.
This area is reserved for system use. It cannot be accessed by
the user.
Expansion DM This area contains initialing data such as Special I/O Unit data,
numerical or character string tables for PTs, and calculation data.
Data can’t be read directly from the expansion DM area as it can
from normal DM.
Expansion DM can be overwritten by performing the
Hexadecimal/BCD Data Modification operation from a
Programming Console or by transferring edited DM data from
SYSMAC Support Software.
I/O comment
This area is used to store I/O comments, which can be saved
together with the program. The I/O comments will be
automatically uploaded with the program and automatically
allocated to that monitoring can be perform with I/O comments.
Ladder program This area is used to store the ladder program created by the user.
UM area words allocated to expansion DM and/or the I/O
Comment Area are taken from the ladder program area.
Note 1. The ladder program area is reduced proportionately when UM area words
are allocated to expansion DM and/or the I/O Comment Area. Make sure
that there is enough excess capacity in the ladder program area before allo-
cating memory to expansion DM and/or the I/O Comment Area.
2. The default setting for the UM area doesn’t have any memory allocated to
expansion DM or the I/O Comment Area. This memory must be allocated by
the user as required.
70
EM (Extended Data Memory) Area
Section 3-12
3-11 TR (Temporary Relay) Area
The TR area provides eight bits that are used only with the LD and OUT instruc-
tions to enable certain types of branching ladder diagram programming. The use
of TR bits is described in Section 4 Writing and Inputting the Program.
TR addresses range from TR 0 though TR 7. Each of these bits can be used as
many times as required and in any order required as long as the same LR bit is
not used twice in the same instruction block.
3-12 EM (Extended Data Memory) Area
In addition to the high-capacity DM area, C200HG and C200HX PCs are
equipped with an EM area that can store up to 18K-words of data. The EM area
is divided into banks which contain 6,144 words each (EM 0000 through
EM 6143). The C200HG PCs have one bank (bank 0) and the C200HX PCs
have three banks (banks 0, 1, and 2). The effective bank is called the current
bank.
3-12-1 Using the EM Area
The EM area can’t be accessed directly by most instructions, but the PCs are
provided with the EMBC(––), XFR2(––), BXF2(––), and IEMS(––) instructions
to manage EM area data.
Instruction
EMBC(––)
XFR2(––)
Function
Changes the current bank to the specified bank number.
Transfers data within the current EM bank or between the current
EM bank and one of the regular data areas.
BXF2(––)
Transfers data between the specified EM bank and another EM
bank or a regular data area.
IEMS(––)
Switches the destination of indirect addressing (ꢀDM) to the
specified EM bank. Can also switch the destination back to DM.
Example 1
The following example uses EMBC(––) to set the current bank to bank 1 and
XFR2(––) to transfer the contents of EM 2000 through EM 2999 to DM 0000
through DM 0999. After execution of a program section, the contents of
DM 0000 through DM 0999 are transferred back to EM 2000 through EM 2999.
EMBC
#0001
XFR2
#1000
#2000
D0000
Data processing performed with
data in DM 0000 through DM 0999.
XFR2
#1000
D0000
#2000
Note If BXF2(––) were used to perform the data transfers, any EM bank could be spe-
cified and EMBC(––) would not be required to select EM bank 1.
Example 2
The following example uses IEMS(––) to change the destination for indirect ad-
dressing (ꢀDM) to EM bank 1. After this instruction is executed, ꢀDM operands
71
EM (Extended Data Memory) Area
Section 3-12
access words in EM bank 1 and not the DM area. In this case, the second oper-
and in the MOV(21) instruction transfers #1234 to a word in the EM bank. (For
example, #1234 will be moved to EM 0100 if DM 0000 contains 0100.)
Later in the program, the destination for indirect addressing (ꢀDM) is switched
back to the DM area by executing IEMS(––) with an operand of 000.
IEMS
#E0B1
MOV
#1234
∗D0000
IEMS
000
Note 1. Be sure to return the indirect addressing destination to its default (the DM
area) when necessary. The destination will be returned to the DM area auto-
matically at the beginning of the next cycle.
2. The destination for indirect addressing reverts to the DM area at the start of
interrupt subroutines, but can be changed within a subroutine. The destina-
tion is returned to its original setting when control is returned to the main pro-
gram.
3-12-2 The Current EM Bank
The current EM bank is set to bank 0 when the PC is turned on, and the current
EM bank can be changed by EMBC(––) or IEMS(––). Unlike the destination for
indirect addressing, the current bank number is not initialized at the start of a
cycle or the start of an interrupt subroutine.
After the PC has been turned ON, the switched bank status will be resumed after
the PC mode is changed or execution of an interrupt subroutine is completed.
72
SECTION 4
Writing and Inputting the Program
This section explains the basic steps and concepts involved in writing a basic ladder diagram program, inputting the program
into memory, and executing it. It introduces the instructions that are used to build the basic structure of the ladder diagram and
control its execution. The entire set of instructions used in programming is described in Section 5 Instruction Set.
4-1 Basic Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2 Instruction Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-3 Program Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4 Basic Ladder Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-1 Basic Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-2 Mnemonic Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-3 Ladder Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-4 OUTPUT and OUTPUT NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-5 The END Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-6 Logic Block Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-4-7 Coding Multiple Right-hand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5 The Programming Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5-1 The Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5-2 PC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-5-3 The Display Message Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6 Preparation for Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-1 Entering the Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-2 Buzzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-3 Clearing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-4 Registering the I/O Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-5 Clearing Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-6 Verifying the I/O Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-7 Reading the I/O Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-8 Clearing the I/O Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-6-9 SYSMAC NET Link Table Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7 Inputting, Modifying, and Checking the Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-1 Setting and Reading from Program Memory Address . . . . . . . . . . . . . . . . . . . . .
4-7-2 Entering and Editing Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-3 Checking the Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-4 Displaying the Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-5 Program Searches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-6 Inserting and Deleting Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-7 Branching Instruction Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-7-8 Jumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8 Controlling Bit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8-1 DIFFERENTIATE UP and DIFFERENTIATE DOWN . . . . . . . . . . . . . . . . . . . .
4-8-2 KEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-8-3 Self-maintaining Bits (Seal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-9 Work Bits (Internal Relays) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-10 Programming Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-11 Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-12 Special I/O Unit Interface Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-12-1 Restarting Special I/O Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-12-2 Special I/O Unit Error Processing Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-12-3 Changing the Special I/O Unit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-12-4 Special I/O Unit I/O Refreshing Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-12-5 Reducing the Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-13 Analog Timer Unit Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-13-1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-13-2 Bit Allocation and DIP Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-13-3 Example Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
74
75
75
76
76
77
80
80
81
88
88
88
91
91
91
92
92
93
96
97
97
99
101
102
104
104
105
108
110
111
112
115
119
120
121
121
121
122
124
126
126
126
127
127
128
129
130
130
131
132
73
Instruction Terminology
Section 4-2
4-1 Basic Procedure
There are several basic steps involved in writing a program. Sheets that can be
copied to aid in programming are provided in Appendix F Word Assignment Re-
cording Sheets and Appendix G Program Coding Sheet.
1, 2, 3...
1. Obtain a list of all I/O devices and the I/O points that have been assigned to
them and prepare a table that shows the I/O bit allocated to each I/O device.
2. If the PC has any Units that are allocated words in data areas other than the
IR area or are allocated IR words in which the function of each bit is specified
by the Unit, prepare similar tables to show what words are used for which
Units and what function is served by each bit within the words. These Units
include Special I/O Units and Link Units.
3. Determine what words are available for work bits and prepare a table in
which you can allocate these as you use them.
4. Also prepare tables of TC numbers and jump numbers so that you can allo-
cate these as you use them. Remember, the function of a TC number can be
defined only once within the program; jump numbers 01 through 99 can be
used only once each. (TC numbers are described in 5-14 Timer and Counter
Instructions; jump numbers are described later in this section.)
5. Draw the ladder diagram.
6. Input the program into the CPU Unit. When using the Programming Con-
sole, this will involve converting the program to mnemonic form.
7. Check the program for syntax errors and correct these.
8. Execute the program to check for execution errors and correct these.
9. After the entire Control System has been installed and is ready for use,
execute the program and fine tune it if required.
10. Make a backup copy of the program.
The basics of ladder-diagram programming and conversion to mnemonic code
are described in 4-4 Basic Ladder Diagrams. Preparing for and inputting the pro-
gram via the Programming Console are described in 4-5 The Programming
Console through 4-7 Inputting, Modifying, and Checking the Program. The rest
of Section 4 covers more advanced programming, programming precautions,
and program execution. All special application instructions are covered in Sec-
tion 5 Instruction Set. Debugging is described in Section 7 Program Monitoring
and Execution. Section 9 Troubleshooting also provides information required for
debugging.
4-2 Instruction Terminology
There are basically two types of instructions used in ladder-diagram program-
ming: instructions that correspond to the conditions on the ladder diagram and
are used in instruction form only when converting a program to mnemonic code
and instructions that are used on the right side of the ladder diagram and are
executed according to the conditions on the instruction lines leading to them.
Most instructions have at least one or more operands associated with them. Op-
erands indicate or provide the data on which an instruction is to be performed.
These are sometimes input as the actual numeric values, but are usually the ad-
dresses of data area words or bits that contain the data to be used. For instance,
a MOVE instruction that has IR 000 designated as the source operand will move
the contents of IR 000 to some other location. The other location is also desig-
nated as an operand. A bit whose address is designated as an operand is called
an operand bit; a word whose address is designated as an operand is called an
operand word. If the actual value is entered as a constant, it is preceded by # to
indicate that it is not an address.
Other terms used in describing instructions are introduced in Section 5 Instruc-
tion Set.
74
Basic Ladder Diagrams
Section 4-4
4-3 Program Capacity
The maximum user program size varies with the amount of UM allocated to ex-
pansion DM and the I/O Comment Area. Approximately 10.1 KW are available
for the ladder program when 3 KW are allocated to expansion DM and 2 KW are
allocated to I/O comments as shown below. Refer to the 3-10 UM Area for further
information on UM allocation.
DM
6144
DM
6600
DM
6655
DM
7000
DM
9999
PC
Setup
Reserved
Expansion
DM Area
I/O Comment
Area
Ladder program
Variable size
Ladder Program Area (15.1 KW)
Fixed DM Area
4-4 Basic Ladder Diagrams
A ladder diagram consists of one line running down the left side with lines
branching off to the right. The line on the left is called the bus bar; the branching
lines, instruction lines or rungs. Along the instruction lines are placed conditions
that lead to other instructions on the right side. The logical combinations of these
conditions determine when and how the instructions at the right are executed. A
ladder diagram is shown below.
00000 06315
25208
HR 0109 LR 2503
24400
24401
Instruction
00001
00501
00502
00503 00504
00100 00002
00010
00003 HR 0050
00007 TIM 001 LR 0515
21001 21002
00403
00405
Instruction
00011
21005 21007
As shown in the diagram above, instruction lines can branch apart and they can
join back together. The vertical pairs of lines are called conditions. Conditions
without diagonal lines through them are called normally open conditions and
correspond to a LOAD, AND, or OR instruction. The conditions with diagonal
lines through them are called normally closed conditions and correspond to a
LOAD NOT, AND NOT, or OR NOT instruction. The number above each condi-
tion indicates the operand bit for the instruction. It is the status of the bit
associated with each condition that determines the execution condition for fol-
lowing instructions. The way the operation of each of the instructions corre-
sponds to a condition is described below. Before we consider these, however,
there are some basic terms that must be explained.
Note When displaying ladder diagrams with SSS, a second bus bar will be shown on
the right side of the ladder diagram and will be connected to all instructions on
the right side. This does not change the ladder-diagram program in any function-
al sense. No conditions can be placed between the instructions on the right side
and the right bus bar, i.e., all instructions on the right must be connected directly
to the right bus bar. Refer to the SSS Operation Manual: C Series for details.
75
Basic Ladder Diagrams
Section 4-4
4-4-1 Basic Terms
Normally Open and
Normally Closed
Conditions
Each condition in a ladder diagram is either ON or OFF depending on the status
of the operand bit that has been assigned to it. A normally open condition is ON if
the operand bit is ON; OFF if the operand bit is OFF. A normally closed condition
is ON if the operand bit is OFF; OFF if the operand bit is ON. Generally speaking,
you use a normally open condition when you want something to happen when a
bit is ON, and a normally closed condition when you want something to happen
when a bit is OFF.
00000
Instruction is executed
Instruction
when IR bit 00000 is ON.
Normally open
condition
00000
Instruction is executed
Instruction
when IR bit 00000 is OFF.
Normally closed
condition
Execution Conditions
Operand Bits
In ladder diagram programming, the logical combination of ON and OFF condi-
tions before an instruction determines the compound condition under which the
instruction is executed. This condition, which is either ON or OFF, is called the
execution condition for the instruction. All instructions other than LOAD instruc-
tions have execution conditions.
The operands designated for any of the ladder instructions can be any bit in the
IR, SR, HR, AR, LR, or TC areas. This means that the conditions in a ladder dia-
gram can be determined by I/O bits, flags, work bits, timers/counters, etc. LOAD
and OUTPUT instructions can also use TR area bits, but they do so only in spe-
cial applications. Refer to 4-7-7 Branching Instruction Lines for details.
Logic Blocks
The way that conditions correspond to what instructions is determined by the
relationship between the conditions within the instruction lines that connect
them. Any group of conditions that go together to create a logic result is called a
logic block. Although ladder diagrams can be written without actually analyzing
individual logic blocks, understanding logic blocks is necessary for efficient pro-
gramming and is essential when programs are to be input in mnemonic code.
4-4-2 Mnemonic Code
The ladder diagram cannot be directly input into the PC via a Programming Con-
sole; SSS is required. To input from a Programming Console, it is necessary to
convert the ladder diagram to mnemonic code. The mnemonic code provides
exactly the same information as the ladder diagram, but in a form that can be
typed directly into the PC. Actually you can program directly in mnemonic code,
although it in not recommended for beginners or for complex programs. Also,
regardless of the Programming Device used, the program is stored in memory in
mnemonic form, making it important to understand mnemonic code.
Because of the importance of the Programming Console as a peripheral device
and because of the importance of mnemonic code in complete understanding of
a program, we will introduce and describe the mnemonic code along with the
ladder diagram. Remember, you will not need to use the mnemonic code if you
are inputting via SSS (although you can use it with SSS too, if you prefer).
Program Memory Structure
The program is input into addresses in Program Memory. Addresses in Program
Memory are slightly different to those in other memory areas because each ad-
dress does not necessarily hold the same amount of data. Rather, each address
holds one instruction and all of the definers and operands (described in more
detail later) required for that instruction. Because some instructions require no
operands, while others require up to three operands, Program Memory address-
es can be from one to four words long.
76
Basic Ladder Diagrams
Section 4-4
Program Memory addresses start at 00000 and run until the capacity of Program
Memory has been exhausted. The first word at each address defines the instruc-
tion. Any definers used by the instruction are also contained in the first word.
Also, if an instruction requires only a single bit operand (with no definer), the bit
operand is also programmed on the same line as the instruction. The rest of the
words required by an instruction contain the operands that specify what data is
to be used. When converting to mnemonic code, all but ladder diagram instruc-
tions are written in the same form, one word to a line, just as they appear in the
ladder diagram symbols. An example of mnemonic code is shown below. The
instructions used in it are described later in the manual.
Address Instruction
Operands
HR 0001
00000
00001
00002
00003
00004
00005
00006
LD
AND
00001
00002
00100
00101
00102
OR
LD NOT
AND
AND LD
MOV(21)
000
DM
0000
00007
CMP(20)
DM
HR
0000
00
00008
00009
00010
LD
25505
00501
OUT
MOV(21)
DM
DM
0000
0500
00011
00012
00013
DIFU(13)
AND
00502
00005
00503
OUT
The address and instruction columns of the mnemonic code table are filled in for
the instruction word only. For all other lines, the left two columns are left blank. If
the instruction requires no definer or bit operand, the operand column is left
blank for first line. It is a good idea to cross through any blank data column
spaces (for all instruction words that do not require data) so that the data column
can be quickly scanned to see if any addresses have been left out.
When programming, addresses are automatically displayed and do not have to
be input unless for some reason a different location is desired for the instruction.
When converting to mnemonic code, it is best to start at Program Memory ad-
dress 00000 unless there is a specific reason for starting elsewhere.
4-4-3 Ladder Instructions
The ladder instructions are those instructions that correspond to the conditions
on the ladder diagram. Ladder instructions, either independently or in combina-
tion with the logic block instructions described next, form the execution condi-
tions upon which the execution of all other instructions are based.
77
Basic Ladder Diagrams
Section 4-4
LOAD and LOAD NOT
The first condition that starts any logic block within a ladder diagram corre-
sponds to a LOAD or LOAD NOT instruction. Each of these instruction requires
one line of mnemonic code. “Instruction” is used as a dummy instruction in the
following examples and could be any of the right-hand instructions described lat-
er in this manual.
00000
Address Instruction
Operands
00000
A LOAD instruction.
00000
00001
00002
00003
LD
Instruction
LD NOT
Instruction
00000
00000
A LOAD NOT instruction.
When this is the only condition on the instruction line, the execution condition for
the instruction at the right is ON when the condition is ON. For the LOAD instruc-
tion (i.e., a normally open condition), the execution condition will be ON when IR
00000 is ON; for the LOAD NOT instruction (i.e., a normally closed condition), it
will be ON when 00000 is OFF.
AND and AND NOT
When two or more conditions lie in series on the same instruction line, the first
one corresponds to a LOAD or LOAD NOT instruction; and the rest of the condi-
tions correspond to AND or AND NOT instructions. The following example
shows three conditions which correspond in order from the left to a LOAD, an
AND NOT, and an AND instruction. Again, each of these instructions requires
one line of mnemonic code.
00000
00100
LR 0000
Instruction
Address Instruction
Operands
00000
00001
00002
00003
LD
00000
AND NOT
AND
00100
0000
LR
Instruction
The instruction will have an ON execution condition only when all three condi-
tions are ON, i.e., when IR 00000 is ON, IR 00100 is OFF, and LR 0000 is ON.
AND instructions in series can be considered individually, with each taking the
logical AND of the execution condition (i.e., the total of all conditions up to that
point) and the status of the AND instruction’s operand bit. If both of these are ON,
an ON execution condition will be produced for the next instruction. If either is
OFF, the result will also be OFF. The execution condition for the first AND
instruction in a series is the first condition on the instruction line.
Each AND NOT instruction in series takes the logical AND of its execution condi-
tion and the inverse of its operand bit.
78
Basic Ladder Diagrams
Section 4-4
OR and OR NOT
When two or more conditions lie on separate instruction lines which run in paral-
lel and then join together, the first condition corresponds to a LOAD or LOAD
NOT instruction; the other conditions correspond to OR or OR NOT instructions.
The following example shows three conditions which correspond (in order from
the top) to a LOAD NOT, an OR NOT, and an OR instruction. Again, each of
these instructions requires one line of mnemonic code.
00000
Instruction
00100
LR 0000
Address Instruction
Operands
00000
00000
00001
00002
00003
LD NOT
OR NOT
OR
00100
0000
LR
Instruction
The instruction will have an ON execution condition when any one of the three
conditions is ON, i.e., when IR 00000 is OFF, when IR 00100 is OFF, or when LR
0000 is ON.
OR and OR NOT instructions can be considered individually, each taking the
logical OR between its execution condition and the status of the OR instruction’s
operand bit. If either one of these were ON, an ON execution condition will be
produced for the next instruction.
Combining AND and OR
Instructions
When AND and OR instructions are combined in more complicated diagrams,
they can sometimes be considered individually, with each instruction performing
a logic operation on the execution condition and the status of the operand bit.
The following is one example. Study this example until you are convinced that
the mnemonic code follows the same logic flow as the ladder diagram.
00000
00001
00002
00003
Instruction
00200
Address Instruction
Operands
00000
00000
00001
00002
00003
00004
00005
LD
AND
00001
00200
00002
00003
OR
AND
AND NOT
Instruction
Here, an AND is taken between the status of IR 00000 and that of IR 00001 to
determine the execution condition for an OR with the status of IR 00200. The
result of this operation determines the execution condition for an AND with the
status of IR 00002, which in turn determines the execution condition for an AND
with the inverse (i.e., and AND NOT) of the status of IR 00003.
In more complicated diagrams, however, it is necessary to consider logic blocks
before an execution condition can be determined for the final instruction, and
that’s where AND LOAD and OR LOAD instructions are used. Before we consid-
er more complicated diagrams, however, we’ll look at the instructions required to
complete a simple “input-output” program.
79
Basic Ladder Diagrams
Section 4-4
4-4-4 OUTPUT and OUTPUT NOT
The simplest way to output the results of combining execution conditions is to
output it directly with the OUTPUT and OUTPUT NOT. These instructions are
used to control the status of the designated operand bit according to the execu-
tion condition. With the OUTPUT instruction, the operand bit will be turned ON
as long as the execution condition is ON and will be turned OFF as long as the
execution condition is OFF. With the OUTPUT NOT instruction, the operand bit
will be turned ON as long as the execution condition is OFF and turned OFF as
long as the execution condition is ON. These appear as shown below. In mne-
monic code, each of these instructions requires one line.
00000
00001
Address Instruction
Operands
00000
00200
00200
00201
00000
00001
LD
OUT
Address Instruction
Operands
00000
00001
LD
00001
00201
OUT NOT
In the above examples, IR 00200 will be ON as long as IR 00000 is ON and IR
00201 will be OFF as long as IR 00001 is ON. Here, IR 00000 and IR 00001 will
be input bits and IR 00200 and IR 00201 output bits assigned to the Units con-
trolled by the PC, i.e., the signals coming in through the input points assigned IR
00000 and IR 00001 are controlling the output points assigned IR 00200 and IR
00201, respectively.
The length of time that a bit is ON or OFF can be controlled by combining the
OUTPUT or OUTPUT NOT instruction with TIMER instructions. Refer to Exam-
ples under 5-14-1 TIMER – TIM for details.
4-4-5 The END Instruction
The last instruction required to complete a simple program is the END instruc-
tion. When the CPU Unit cycles the program, it executes all instruction up to the
first END instruction before returning to the beginning of the program and begin-
ning execution again. Although an END instruction can be placed at any point in
a program, which is sometimes done when debugging, no instructions past the
first END instruction will be executed until it is removed. The number following
the END instruction in the mnemonic code is its function code, which is used
when inputted most instruction into the PC. These are described later. The END
instruction requires no operands and no conditions can be placed on the same
instruction line with it.
00000
00001
Instruction
END(01)
Program execution
ends here.
Address Instruction
Operands
00000
00000
00001
00002
00003
LD
AND NOT
Instruction
END(01)
00001
---
If there is no END instruction anywhere in the program, the program will not be
executed at all.
80
Basic Ladder Diagrams
Section 4-4
Now you have all of the instructions required to write simple input-output pro-
grams. Before we finish with ladder diagram basic and go onto inputting the pro-
gram into the PC, let’s look at logic block instruction (AND LOAD and OR LOAD),
which are sometimes necessary even with simple diagrams.
4-4-6 Logic Block Instructions
Logic block instructions do not correspond to specific conditions on the ladder
diagram; rather, they describe relationships between logic blocks. The AND
LOAD instruction logically ANDs the execution conditions produced by two logic
blocks. The OR LOAD instruction logically ORs the execution conditions pro-
duced by two logic blocks.
AND LOAD
Although simple in appearance, the diagram below requires an AND LOAD
instruction.
00000
00001
00002
00003
Instruction
Address Instruction
Operands
00000
00000
00001
00002
00003
00004
00005
LD
OR
00001
00002
00003
---
LD
OR NOT
AND LD
Instruction
The two logic blocks are indicated by dotted lines. Studying this example shows
that an ON execution condition will be produced when: either of the conditions in
the left logic block is ON (i.e., when either IR 00000 or IR 00001 is ON), and
when either of the conditions in the right logic block is ON (i.e., when either IR
00002 is ON or IR 00003 is OFF).
The above ladder diagram cannot, however, be converted to mnemonic code
using AND and OR instructions alone. If an AND between IR 00002 and the re-
sults of an OR between IR 00000 and IR 00001 is attempted, the OR NOT be-
tween IR 00002 and IR 00003 is lost and the OR NOT ends up being an OR NOT
between just IR 00003 and the result of an AND between IR 00002 and the first
OR. What we need is a way to do the OR (NOT)’s independently and then com-
bine the results.
To do this, we can use the LOAD or LOAD NOT instruction in the middle of an
instruction line. When LOAD or LOAD NOT is executed in this way, the current
execution condition is saved in a special buffer and the logic process is re-
started. To combine the results of the current execution condition with that of a
previous “unused” execution condition, an AND LOAD or an OR LOAD instruc-
tion is used. Here “LOAD” refers to loading the last unused execution condition.
An unused execution condition is produced by using the LOAD or LOAD NOT
instruction for any but the first condition on an instruction line.
81
Basic Ladder Diagrams
Section 4-4
Analyzing the above ladder diagram in terms of mnemonic instructions, the
condition for IR 00000 is a LOAD instruction and the condition below it is an OR
instruction between the status of IR 00000 and that of IR 00001. The condition at
IR 00002 is another LOAD instruction and the condition below is an OR NOT
instruction, i.e., an OR between the status of IR 00002 and the inverse of the
status of IR 00003. To arrive at the execution condition for the instruction at the
right, the logical AND of the execution conditions resulting from these two blocks
will have to be taken. AND LOAD does this. The mnemonic code for the ladder
diagram is shown below. The AND LOAD instruction requires no operands of its
own, because it operates on previously determined execution conditions. Here
too, dashes are used to indicate that no operands needs designated or input.
OR LOAD
The following diagram requires an OR LOAD instruction between the top logic
block and the bottom logic block. An ON execution condition will be produced for
the instruction at the right either when IR 00000 is ON and IR 00001 is OFF, or
when IR 00002 and IR 00003 are both ON. The operation of the OR LOAD
instruction and its mnemonic code are exactly the same as that for an AND
LOAD instruction, except that the current execution condition is ORed with the
last unused execution condition.
00000
00002
00001
00003
Instruction
Address Instruction
Operands
00000
00000
00001
00002
00003
00004
00005
LD
AND NOT
LD
00001
00002
00003
---
AND
OR LD
Instruction
Naturally, some diagrams will require both AND LOAD and OR LOAD instruc-
tions.
Logic Block Instructions in
Series
To code diagrams with logic block instructions in series, the diagram must be
divided into logic blocks. Each block is coded using a LOAD instruction to code
the first condition, and then AND LOAD or OR LOAD is used to logically combine
the blocks. With both AND LOAD and OR LOAD there are two ways to achieve
this. One is to code the logic block instruction after the first two blocks and then
after each additional block. The other is to code all of the blocks to be combined,
starting each block with LOAD or LOAD NOT, and then to code the logic block
instructions which combine them. In this case, the instructions for the last pair of
blocks should be combined first, and then each preceding block should be com-
bined, working progressively back to the first block. Although either of these
methods will produce exactly the same result, the second method, that of coding
all logic block instructions together, can be used only if eight or fewer blocks are
being combined, i.e., if seven or fewer logic block instructions are required.
82
Basic Ladder Diagrams
Section 4-4
The following diagram requires AND LOAD to be converted to mnemonic code
because three pairs of parallel conditions lie in series. The two options for coding
the programs are also shown.
00000
00002
00004
00500
00001
00003
00005
Address Instruction
Operands
Address Instruction
Operands
00000
00001
00002
00003
00004
00005
00006
00007
00008
LD
00000
00000
00001
00002
00003
00004
00005
00006
00007
00008
LD
00000
OR NOT
LD NOT
OR
00001
00002
00003
—
OR NOT
LD NOT
OR
00001
00002
00003
00004
00005
—
AND LD
LD
LD
00004
00005
—
OR
OR
AND LD
AND LD
OUT
AND LD
OUT
—
00500
00500
Again, with the method on the right, a maximum of eight blocks can be com-
bined. There is no limit to the number of blocks that can be combined with the
first method.
The following diagram requires OR LOAD instructions to be converted to mne-
monic code because three pairs of series conditions lie in parallel to each other.
00000 00001
00501
00002 00003
00040 00005
The first of each pair of conditions is converted to LOAD with the assigned bit
operand and then ANDed with the other condition. The first two blocks can be
coded first, followed by OR LOAD, the last block, and another OR LOAD; or the
three blocks can be coded first followed by two OR LOADs. The mnemonic
codes for both methods are shown below.
Address Instruction
Operands
00000
Address Instruction
Operands
00000
00000
00001
00002
00003
00004
00005
00006
00007
00008
LD
00000
00001
00002
00003
00004
00005
00006
00007
00008
LD
AND NOT
LD NOT
AND NOT
OR LD
LD
00001
00002
00003
—
AND NOT
LD NOT
AND NOT
LD
00001
00002
00003
00004
00005
—
00004
00005
—
AND
AND
OR LD
OR LD
OUT
OR LD
OUT
—
00501
00501
Again, with the method on the right, a maximum of eight blocks can be com-
bined. There is no limit to the number of blocks that can be combined with the
first method.
83
Basic Ladder Diagrams
Section 4-4
Combining AND LOAD and
OR LOAD
Both of the coding methods described above can also be used when using AND
LOAD and OR LOAD, as long as the number of blocks being combined does not
exceed eight.
The following diagram contains only two logic blocks as shown. It is not neces-
sary to further separate block b components, because it can be coded directly
using only AND and OR.
00000 00001
00002 00003
00201
00501
00004
Block
a
Block
b
Address Instruction
Operands
00000
00000
00001
00002
00003
00004
00005
00006
00007
LD
AND NOT
LD
00001
00002
00003
00201
00004
—
AND
OR
OR
AND LD
OUT
00501
Although the following diagram is similar to the one above, block b in the diagram
below cannot be coded without separating it into two blocks combined with OR
LOAD. In this example, the three blocks have been coded first and then OR
LOAD has been used to combine the last two blocks, followed by AND LOAD to
combine the execution condition produced by the OR LOAD with the execution
condition of block a.
When coding the logic block instructions together at the end of the logic blocks
they are combining, they must, as shown below, be coded in reverse order, i.e.,
the logic block instruction for the last two blocks is coded first, followed by the
one to combine the execution condition resulting from the first logic block
instruction and the execution condition of the logic block third from the end, and
on back to the first logic block that is being combined.
Block
b1
Address Instruction
Operands
00000
00000 00001
00002 00003
00000
00001
00002
00003
00004
00005
00006
00007
00008
LD NOT
AND
00502
00001
00002
00003
00004
00202
—
LD
00004 00202
AND NOT
LD NOT
AND
Block
b2
OR LD
AND LD
OUT
—
Block
a
Block
b
00502
84
Basic Ladder Diagrams
Section 4-4
Complicated Diagrams
When determining what logic block instructions will be required to code a dia-
gram, it is sometimes necessary to break the diagram into large blocks and then
continue breaking the large blocks down until logic blocks that can be coded
without logic block instructions have been formed. These blocks are then coded,
combining the small blocks first, and then combining the larger blocks. Either
AND LOAD or OR LOAD is used to combine the blocks, i.e., AND LOAD or OR
LOAD always combines the last two execution conditions that existed, regard-
less of whether the execution conditions resulted from a single condition, from
logic blocks, or from previous logic block instructions.
When working with complicated diagrams, blocks will ultimately be coded start-
ing at the top left and moving down before moving across. This will generally
mean that, when there might be a choice, OR LOAD will be coded before AND
LOAD.
The following diagram must be broken down into two blocks and each of these
then broken into two blocks before it can be coded. As shown below, blocks a
and b require an AND LOAD. Before AND LOAD can be used, however, OR
LOAD must be used to combine the top and bottom blocks on both sides, i.e., to
combine a1 and a2; b1 and b2.
Block
a1
Block
b1
Address Instruction
Operands
00000
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
LD
00000 00001
00004 00005
00503
AND NOT
LD NOT
AND
00001
00002
00003
—
00002 00003
00006 00007
OR LD
LD
Blocks a1 and a2
Block
a2
Block
b2
00004
00005
00006
00007
—
AND
LD
Block
a
Block
b
AND
Blocks b1 and b2
Blocks a and b
OR LD
AND LD
OUT
—
00503
The following type of diagram can be coded easily if each block is coded in order:
first top to bottom and then left to right. In the following diagram, blocks a and b
would be combined using AND LOAD as shown above, and then block c would be
coded and a second AND LOAD would be used to combined it with the execution
condition from the first AND LOAD. Then block d would be coded, a third AND
LOAD would be used to combine the execution condition from block d with the
execution condition from the second AND LOAD, and so on through to block n.
00500
Block
a
Block
b
Block
c
Block
n
85
Basic Ladder Diagrams
Section 4-4
The following diagram requires an OR LOAD followed by an AND LOAD to code
the top of the three blocks, and then two more OR LOADs to complete the mne-
monic code.
00000
00001
Address Instruction
Operands
00000
LR 0000
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
LD
00002
00003
LD
00001
00002
00003
––
LD
00004
00005
00007
AND NOT
OR LD
AND LD
LD NOT
AND
00006
––
00004
00005
––
OR LD
LD NOT
AND
00006
00007
––
OR LD
OUT
LR
0000
Although the program will execute as written, this diagram could be drawn as
shown below to eliminate the need for the first OR LOAD and the AND LOAD,
simplifying the program and saving memory space.
Address Instruction
Operands
00002
00002
00001
00003
00000
LR 0000
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
LD
AND NOT
OR
00003
00001
00000
00004
00005
––
00004
00006
00005
00007
AND
LD NOT
AND
OR LD
LD NOT
AND
00006
00007
––
OR LD
OUT
LR
0000
The following diagram requires five blocks, which here are coded in order before
using OR LOAD and AND LOAD to combine them starting from the last two
blocks and working backward. The OR LOAD at program address 00008 com-
bines blocks blocks d and e, the following AND LOAD combines the resulting
execution condition with that of block c, etc.
Address Instruction
Operands
00000
00000
00001
00002
LR 0000
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
LD
Block b
LD
00001
00002
00003
00004
00005
00006
00007
––
Block a
AND
LD
Block c
00003 00004
Block d
00005
AND
LD
LD
AND
OR LD
AND LD
OR LD
AND LD
OUT
00006
00007
Blocks d and e
––
Block c with result of above
Block e
––
Block b with result of above
Block a with result of above
––
LR
0000
86
Basic Ladder Diagrams
Section 4-4
Again, this diagram can be redrawn as follows to simplify program structure and
coding and to save memory space.
Address Instruction
Operands
00006
00006
00005
00007
00001
00003
00004
00000
LR 0000
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
LD
AND
OR
00007
00005
00003
00004
00001
00002
––
00002
AND
AND
LD
AND
OR LD
AND
OUT
00000
0000
LR
The next and final example may at first appear very complicated but can be
coded using only two logic block instructions. The diagram appears as follows:
Block a
00000
01000
00500
00001
01001
00002
00003
00004
00006
00005
00500
Block b
Block c
The first logic block instruction is used to combine the execution conditions re-
sulting from blocks a and b, and the second one is to combine the execution
condition of block c with the execution condition resulting from the normally
closed condition assigned IR 00003. The rest of the diagram can be coded with
OR, AND, and AND NOT instructions. The logical flow for this and the resulting
code are shown below.
Block a
Block b
00000
00001
01000
01001
LD
AND
00000
00001
LD
AND
01000
01001
Address Instruction
Operands
00000
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
LD
OR LD
AND
LD
00001
01000
01001
––
Block c
00004
00005
00500
AND
OR LD
OR
LD
00004
00005
OR
00500
00003
00500
00002
00003
00004
00005
00006
––
AND
AND
AND NOT
LD
00002
00006
LD
AND
AND NOT 00003
00002
00006
AND
OR
AND LD
OUT
AND LD
00500
00500
87
The Programming Console
Section 4-5
4-4-7 Coding Multiple Right-hand Instructions
If there is more than one right-hand instruction executed with the same execu-
tion condition, they are coded consecutively following the last condition on the
instruction line. In the following example, the last instruction line contains one
more condition that corresponds to an AND with IR 00004.
00000
00001
00003
Address Instruction
Operands
00000
HR
0001
00000
00001
00002
00003
00004
00005
00006
00007
00008
LD
OR
00001
00002
0000
00500
00506
OR
OR
HR
HR
00002
00004
AND
OUT
OUT
AND
OUT
00003
0001
HR 0000
00500
00004
00506
4-5 The Programming Console
This and the next section describe the Programming Console and the opera-
tions necessary to prepare for program input. 4-7 Inputting, Modifying, and
Checking the Program describes actual procedures for inputting the program
into memory.
Although the Programming Console can be used to write ladder programs, it is
primarily used to support SSS operations and is very useful for on-site editing
and maintenance. The main Programming Console functions are listed below.
1, 2, 3...
1. Displaying operating messages and the results of diagnostic checks.
2. Writing and reading ladder programs, inserting and deleting instructions,
searching for data or instructions, and monitoring I/O bit status.
3. Monitoring I/O status, force-setting/resetting bits.
4. The Programming Console can be connected to or disconnected from the
PC with the power on.
5. The Programming Console can be used with C-series PCs.
6. Supports TERMINAL mode, which allows the display of a 32-character
message, as well as operation of the keyboard mapping function. Refer to
5-25-6 TERMINAL MODE – TERM(––) for details.
Note The Programming Console does not support all of the SSS operations, only
those required for on-site editing and maintenance.
4-5-1 The Keyboard
The keyboard of the Programming Console is functionally divided by key color
into the following four areas:
White: Numeric Keys
The ten white keys are used to input numeric program data such as program
addresses, data area addresses, and operand values. The numeric keys are
also used in combination with the function key (FUN) to enter instructions with
function codes. The numeral keys 0 to 5 are also pressed after the SHIFT key to
input hexadecimal numerals A to F.
Red: CLR Key
The CLR key clears the display and cancels current Programming Console op-
erations. It is also used when you key in the password at the beginning of pro-
gramming operations. Any Programming Console operation can be cancelled
by pressing the CLR key, although the CLR key may have to be pressed two or
three times to cancel the operation and clear the display.
88
The Programming Console
Section 4-5
Yellow: Operation Keys
The yellow keys are used for writing and correcting programs. Detailed explana-
tions of their functions are given later in this section.
Gray: Instruction and Data
Area Keys
Except for the SHIFT key on the upper right, the gray keys are used to input
instructions and designate data area prefixes when inputting or changing a pro-
gram. The SHIFT key is similar to the shift key of a typewriter, and is used to alter
the function of the next key pressed. (It is not necessary to hold the SHIFT key
down; just press it once and then press the key to be used with it.)
89
The Programming Console
Section 4-5
The gray keys other than the SHIFT key have either the mnemonic name of the
instruction or the abbreviation of the data area written on them. The functions of
these keys are described below.
Pressed before the function code when inputting an instruction
via its function code.
Pressed to enter SFT (the Shift Register instruction).
Input either after a function code to designate the differentiated
form of an instruction or after a ladder instruction to designate
an inverse condition.
Pressed to enter AND (the AND instruction) or used with NOT
to enter AND NOT.
Pressed to enter OR (the OR instruction) or used with NOT to
enter OR NOT.
Pressed to enter CNT (the Counter instruction) or to designate
a TC number that has already been defined as a counter.
Pressed to enter LD (the Load instruction) or used with NOT to
enter LD NOT. Also pressed to indicate an input bit.
Pressed to enter OUT (the Output instruction) or used with
NOT to enter OUT NOT. Also pressed to indicate an output bit.
Pressed to enter TIM (the Timer instruction) or to designate a
TC number that has already been defined as a timer.
Pressed before designating an address in the TR area.
Pressed before designating an address in the LR area.
Pressed before designating an address in the HR area.
Pressed before designating an address in the AR area.
Pressed before designating an address in the DM area.
Pressed before designating an address in the EM area.
Pressed before designating an indirect DM address.
Pressed before designating a word address.
Pressed before designating an operand as a constant.
Pressed before designating a bit address.
Pressed to select either the upper or lower function for keys
that have two functions. Pressing this key once selects the
upper function, and pressing it again selects the lower function.
Selects expanded functions when used in combination with
other keys. Pressed before the numeric keys 0 to 5 to input the
hexadecimal numerals A to F.
90
Preparation for Operation
Section 4-6
4-5-2 PC Modes
The Programming Console is equipped with a switch to control the PC mode. To
select one of the three operating modes—RUN, MONITOR, or PROGRAM—
use the mode switch. The mode that you select will determine PC operation as
well as the procedures that are possible from the Programming Console.
RUN mode is the mode used for normal program execution. When the switch is
set to RUN and the START input on the CPU Power Supply Unit is ON, the CPU
Unit will begin executing the program according to the program written in its Pro-
gram Memory. Although monitoring PC operation from the Programming Con-
sole is possible in RUN mode, no data in any of the memory areas can be input or
changed.
MONITOR mode allows you to visually monitor in-progress program execution
while controlling I/O status, changing PV (present values) or SV (set values),
etc. In MONITOR mode, I/O processing is handled in the same way as in RUN
mode. MONITOR mode is generally used for trial system operation and final pro-
gram adjustments.
In PROGRAM mode, the PC does not execute the program. PROGRAM mode
is for creating and changing programs, clearing memory areas, and registering
and changing the I/O table. A special Debug operation is also available within
PROGRAM mode that enables checking a program for correct execution before
trial operation of the system.
Caution Do not leave the Programming Console connected to the PC by an extension
cable when in RUN mode. Noise picked up by the extension cable can enter the
PC, affecting the program and thus the controlled system.
!
4-5-3 The Display Message Switch
Pin 3 of the CPU Unit’s DIP switch determines whether Japanese or English lan-
guage messages will be displayed on the Programming Console. It is factory set
to ON, which causes English language messages to be displayed.
4-6 Preparation for Operation
This section describes the procedures required to begin Programming Console
operation. These include password entry, clearing memory, error message
clearing, and I/O table operations. I/O table operations are also necessary at
other times, e.g., when changes are to be made in Units used in the PC configu-
ration.
Caution Always confirm that the Programming Console is in PROGRAM mode when
turning on the PC with a Programming Console connected unless another mode
is desired for a specific purpose. If the Programming Console is in RUN mode
when PC power is turned on, any program in Program Memory will be executed,
possibly causing a PC-controlled system to begin operation.
!
The following sequence of operations must be performed before beginning ini-
tial program input.
1, 2, 3...
1. Insert the mode key into the Programming Console.
2. Set the mode switch to PROGRAM mode. (The mode key cannot be re-
moved while set to PROGRAM mode.)
3. Turn ON PC power.
Note When I/O Units are installed, turn on those Units also. The Program-
ming Console will not operate if these Units are not turned ON.
91
Preparation for Operation
Section 4-6
4. Confirm that the CPU Unit’s POWER LED is lit and the following display ap-
pears on the Programming Console screen. (If the PC mode is not dis-
played, turn OFF and restart the power supply. If the ALM/ERR LED is lit or
flashing or an error message is displayed, clear the error that has occurred.)
<PROGRAM>
PASSWORD!
5. Enter the password. See 4-6-1 Entering the Password for details.
6. Clear memory. Skip this step if the program does not need to be cleared.
See 4-6-3 Clearing Memory for details.
4-6-1 Entering the Password
To gain access to the PC’s programming functions, you must first enter the pass-
word. The password prevents unauthorized access to the program.
The PC prompts you for a password when PC power is turned ON or, if PC power
is already ON, after the Programming Console has been connected to the PC.
To gain access to the system when the “Password!” message appears, press
CLR and then MONTR. Then press CLR to clear the display.
If the Programming Console is connected to the PC when PC power is already
ON, the first display below will indicate the mode the PC was in before the Pro-
gramming Console was connected. Ensure that the PC is in PROGRAM mode
before you enter the password. When the password is entered, the PC will
shift to the mode set on the mode switch, causing PC operation to begin if the
mode is set to RUN or MONITOR. The mode can be changed to RUN or MON-
ITOR with the mode switch after entering the password.
<PROGRAM>
PASSWORD!
<PROGRAM>
BZ
Indicates the mode set by the mode selector switch.
4-6-2 Buzzer
Immediately after the password is input or anytime immediately after the mode
has been changed, SHIFT and then the 1 key can be pressed to turn ON and
OFF the buzzer that sounds when Programming Console keys are pressed. If
BZ is displayed in the upper right corner, the buzzer is operative. If BZ is not dis-
played, the buzzer is not operative.
This buzzer also will also sound whenever an error occurs during PC operation.
Buzzer operation for errors is not affected by the above setting.
92
Preparation for Operation
Section 4-6
4-6-3 Clearing Memory
Using the Memory Clear operation it is possible to clear all or part of the UM area
(RAM or EEPROM), and the IR, HR, AR, DM, EM and TC areas. Unless other-
wise specified, the clear operation will clear all of the above memory areas. The
UM area will not be cleared if the write-protect switch (pin 1 of the CPU Unit’s DIP
switch) is set to ON.
Before beginning to programming for the first time or when installing a new pro-
gram, all areas should normally be cleared. Before clearing memory, check to
see if a program is already loaded that you need. If you need the program, clear
only the memory areas that you do not need, and be sure to check the existing
program with the program check key sequence before using it. The check se-
quence is provided later in this section. Further debugging methods are pro-
vided in Section 7 Program Monitoring and Execution. To clear all memory areas
press CLR until all zeros are displayed, and then input the keystrokes given in
the top line of the following key sequence. The branch lines shown in the se-
quence are used only when performing a partial memory clear, which is de-
scribed below.
Memory can be cleared in PROGRAM mode only. The following table shows
which memory areas will be cleared for the 3 memory clearing operations (all
clear, partial clear, memory clear).
Memory Area
I/O words
All clear
Cleared
Partial clear
Memory clear
Cleared
Cleared
Cleared
Cleared
Cleared
---
Cleared
---
Work words
Cleared
Cleared
Cleared
Cleared
Cleared
Cleared
Cleared
HR, AR, TC, DM, fixed DM
Expansion DM
EM
Cleared
---
Cleared
---
I/O comments
Ladder program
UM Allocation information
Cleared
---
Cleared
---
Note 1. The error history area (DM 6000 to DM 6030) will not be cleared when the
DM area is cleared.
2. When the PC Setup area (DM 6600 to DM 6655 in fixed DM) is cleared, the
settings will be returned to their factory-set defaults.
3. When the All Clear operation is executed, the ladder program area will be
allocated entirely to the ladder program. (The expansion DM and I/O com-
ment areas will be set to 0 KW.) Also , all EM banks will be cleared.
All Clear
The key sequence for all clear is shown below.
93
Preparation for Operation
Section 4-6
The following procedure is used to clear memory completely.
MEMORY ERR
Continue pressing
I/O VER ERR
the CLR key once for
each error message
until “00000” appears
on the display
00000
00000
00000MEMORY CLR?
HR CNT DM EM~
All clear
00000MEM ALLCLR?
00000MEM ALLCLR
END
Partial Clear
It is possible to retain the data in specified areas or part of the ladder program. To
retain the data in the HR and AR, TC, DM, and/or EM areas, press the appropri-
ate key after entering REC/RESET. HR is pressed to designate both the HR and
AR areas. In other words, specifying that HR is to be retained will ensure that AR
is retained also. If not specified for retention, both areas will be cleared. CNT is
used for the entire TC area. Press Shift + DM to specify the EM area. The display
will show those areas that will be cleared.
It is possible to retain some EM banks and clear others. See the explanation un-
der the heading “Clearing Selected EM Banks” on page 95.
It is also possible to retain a portion of the ladder program from the beginning to a
specified address. After designating the data areas to be retained, specify the
first program address to be cleared. For example, to leave addresses 00000 to
00122 untouched, but to clear addresses from 00123 to the end of Program
Memory, input 00123.
The key sequence for a partial memory clear is shown below.
Program Memory cleared
from designated address.
Both AR and HR areas
TC area
Retained if pressed
DM area
EM area
94
Preparation for Operation
Section 4-6
To leave the TC area uncleared and retain Program Memory addresses 00000
through 00122, input as follows:
00000
00000
00000
00000MEMORY CLR?
HR CNT DM EM~
00000MEMORY CLR?
HR
DM EM~
00123MEMORY CLR?
HR DM EM~
00000MEMORY CLR
END HR DM EM
Clearing Selected EM Banks When a partial memory clear operation is being performed, specific banks can
be selected for clearing rather than selecting the entire EM area. In the following
example, EM banks 0 and 2 are selected for clearing.
The Programming Console will display the following screens:
00000
00000
00000
00000MEMORY CLR?
HR CNT DM EM
00000 EM CLR ?
012
00000 EM CLR ?
0 2
00000 EM CLR END
0 2
95
Preparation for Operation
Section 4-6
Memory Clear
The memory clear operation clears all memory areas except the I/O comments
and UM Allocation information.
The Programming Console will display the following screens:
00000
00000
00000
00000MEMORY CLR?
HR CNT DM EM~
00000MEMORY CLR
END
Note When the write-protect switch (pin 1 of the CPU Unit’s DIP switch) is set to ON
the UM area (from DM 6144 through the ladder program) will not be cleared.
Other data areas, such as HR, AR, CNT, and DM from DM 0000 to DM 6143 will
be cleared.
4-6-4 Registering the I/O Table
The I/O Table Registration operation records the types of I/O Units controlled by
the PC and the Rack locations of the I/O Units. It also clears all I/O bits.
It is not absolutely necessary to register the I/O table with the C200HX/HG/HE.
When the I/O table has not been registered, the PC will operate according to the
I/O Units mounted when power is applied. The I/O verification/setting error will
not occur.
It is necessary to register the I/O table if I/O Units are changed, otherwise an I/O
verification error message, “I/O VER ERR” or “I/O SET ERROR”, will appear
when starting programming operations.
I/O Table Registration can be performed only in PROGRAM mode with the write-
protection switch (pin 1 of the CPU Unit’s DIP switch) set to OFF
(OFF=“WRITE”).
Key Sequence
96
Preparation for Operation
Section 4-6
Initial I/O Table Registration
00000
00000
FUN (??)
00000IOTBL ?
?Ć?U=
Register I/O table
00000IOTBL WRIT
????
00000IOTBL WRIT
9713
00000IOTBL WRIT
OK
4-6-5 Clearing Error Messages
After the I/O table has been registered, any error messages recorded in memory
should be cleared. It is assumed here that the causes of any of the errors for
which error messages appear have already been taken care of. If the beeper
sounds when an attempt is made to clear an error message, eliminate the cause
of the error, and then clear the error message (refer to Section 9 Troubleshoot-
ing).
To display any recorded error messages, press CLR, FUN, and then MONTR.
The first message will appear. Pressing MONTR again will clear the present
message and display the next error message. Continue pressing MONTR until
all messages have been cleared.
Although error messages for fatal errors can be accessed in any mode, they can
be cleared only in PROGRAM mode.
Key Sequence
4-6-6 Verifying the I/O Table
The I/O Table Verification operation is used to check the I/O table registered in
memory to see if it matches the actual sequence of I/O Units mounted. The first
inconsistency discovered will be displayed as shown below. Every subsequent
pressing of VER displays the next inconsistency.
Note This operation can be executed only when the I/O table has been registered.
Key Sequence
97
Preparation for Operation
Section 4-6
Example
00000
00000
FUN (??)
00000IOTBL ?
?Ć?U=
00000IOTBL CHK
OK
(No errors)
00000IOTBL CHK
0Ć1U=O*** I***
(A verification error occurred)
Actual I/O words
Registered I/O table words
I/O slot number
Rack number
Meaning of Displays
The following display indicates a C500, C1000H, or C2000H and C200H,
C200HS, or C200HX/HG/HE have the same unit number on a Remote I/O Slave
Rack.
00000I/OTBL CHK
*Ć*U=ĆĆĆĆ
The following display indicates a duplication in Optical I/O Unit unit numbers.
00000I/OTBL CHK
2**HU=R*ĆI R*ĆW
Indicates duplication
98
Preparation for Operation
Section 4-6
4-6-7 Reading the I/O Table
The I/O Table Read operation is used to access the I/O table that is currently
registered in the CPU Unit memory. This operation can be performed in any PC
mode.
Key Sequence
[0 to 3]
[0 to 9]
Rack
number
Unit
number
Press the EXT key to select Remote
I/O Slave Racks or Optical I/O Units.
Example
00000
00000
FUN (??)
00000IOTBL ?
?Ć?U=
(Main Rack)
(Slave Rack Units)
00000IOTBL ?
R??Ć?U=
(Optical I/O Unit)
00000IOTBL ?
2??LU=
00000IOTBL ?
?Ć?U=
(Main Rack)
00000IOTBL ?
0Ć?U=
00000IOTBL ?
0Ć5U=
00000IOTBL READ
0Ć5U=i*** 005
00000IOTBL READ
0Ć4U=o*** 004
00000IOTBL READ
0Ć5U=i*** 005
99
Preparation for Operation
Section 4-6
Meaning of Displays
I/O Unit Designations for Displays
(see I/O Units Mounted in Remote Slave Racks, page 101)
C500, 1000H/C2000H I/O Units
No. of points
Input Unit
Output Unit
O * * *
16
32
64
I * * *
I I * * O O * *
I I I I O O O O
C200H, C200HS I/O Units
No. of points
Input Unit
Output Unit
o * * *
8
i(*)* *
i i * *
16
o o * *
Note: (∗) is i for non-fatal errors or F_
I/O Units
00000IOTBL READ
*Ć*U=**** ***
I/O word number
I/O type: i: (input), o: (output)
Unit number (0 to 9)
Rack number (0 to 3)
Interrupt Input Units
00000IOTBL READ
*Ć*U=****
INT0 or INT1:
Mounted to CPU Unit or Expansion I/O
Rack.
Special I/O Units
00000IOTBL READ
*Ć*U=$***
Blank:
W:
Unit 1 exclusively
Unit 2 exclusively
C: High-speed Counter
N: Position Control Unit
A: Other
Special I/O
Unit type:
Unit number (0 to F)
Indicates Special I/O Unit
Remote I/O Master Units
00000IOTBL READ
*Ć*U=RMT*
Remote I/O
Master no. (0 or 1)
100
Preparation for Operation
Section 4-6
Remote I/O Slave Racks
00000IOTBL READ
R**Ć*U=**** ***
I/O word number
I/O type: I, O
i, o (see tables on previous page)
Unit number (0 to 9)
Remote I/O Slave Unit number (0 to 4)
Remote I/O Master Unit number (0 or 1)
Indicates a Remote I/O Rack
Group-2 HIgh-density I/O
Units
00000IOTBL READ
*Ć*U=#***
2:
4:
2 words (32 points)
4 words (64 points)
I:
O:
Input Unit
Output Unit
Unit number (0 to F)
Indicates Group-2 HIgh-density I/O Unit
Optical I/O Units and
Remote Terminals
00000IOTBL READ
2**HU=R*Ć*
I/O type: I (input), O (output), or
W (input/output)
Remote I/O Master Unit number (0 to 1)
Word (H: leftmost 8 bits; L: rightmost 8 bits)
I/O word number (200 to 231)
4-6-8 Clearing the I/O Table
The I/O Table Clear operation is used to delete the contents of the I/O table that
is currently registered in the CPU Unit memory. The PC will be set for operation
based on the I/O Units mounted when the I/O Table Clear operation is per-
formed.
The I/O Table Clear operation will reset all Special I/O Units and Link Units
mounted at the time. Do not perform the I/O Table Clear operation when a Host
Link Unit, PC Link Unit, Remote I/O Master Unit, High-speed Counter Unit, Posi-
tion Control Unit, or other Special I/O Unit is in operation.
Note This operation can be performed only in PROGRAM mode with the write-protec-
tion switch (pin 1 of the CPU Unit’s DIP switch) set to OFF (OFF=“WRITE”).
101
Preparation for Operation
Section 4-6
Key Sequence
Example
00000
00000
FUN (??)
00000IOTBL
?Ć?U=
00000IOTBL WRIT
????
00000IOTBL CANC
????
00000IOTBL CANC
9713
00000IOTBL CANC
OK
4-6-9 SYSMAC NET Link Table Transfer
The SYSMAC NET Link Table Transfer operation transfers a copy of the SYS-
MAC NET Link Data Link table to the UM Area program memory. This allows the
user program and SYSMAC NET Link table to be written into EPROM together.
The data link table must be created with the SYSMAC Support Software and
transferred to the PC before copying the table to program memory.
The data link table is stored in RAM when it is transferred to the PC from the
SYSMAC Support Software, so the table will be lost if the CPU Unit’s backup
battery dies. To prevent this loss, we recommend converting the program (with
the data link table) to EPROM or storing the program in an EEPROM Memory
Cassette.
Note When power is applied to a PC which has a copy of a SYSMAC NET Link table
stored in its program memory, the SYSMAC NET Link table of the CPU Unit will
be overwritten. Changes made in the SYSMAC NET Link table do not affect the
copy of the SYSMAC NET Link table in program memory; SYSMAC NET Link
Table Transfer must be repeated to change the copy in program memory.
The SYSMAC NET Link Table Transfer operation will not work if:
• The Memory Unit is not RAM or EEPROM, or the write protect switch is not set
to write.
• There isn’t an END(01) instruction.
• The contents of program memory exceeds 14.7 KW. The program capacity is
reduced when memory is allocated to expansion DM or the I/O comment area.
About 0.5 KW of program memory beyond the END(01) instruction are needed
to store the data link table.
SYSMAC NET Link table transfer can only be done in PROGRAM mode.
102
Preparation for Operation
Section 4-6
Key Sequence
Example
00000
00000
FUN(??)
00000LINK TBL~UM
(SYSMACĆNET)????
00000LINK TBL~UM
(SYSMACĆNET)9713
00000LINK TBL~UM
OK
The following indicates that the
I/O table cannot be transferred.
00000LINK TBL~UM
DISABLED
103
Inputting, Modifying, and Checking the Program
Section 4-7
4-7 Inputting, Modifying, and Checking the Program
Once a program is written in mnemonic code, it can be input directly into the PC
from a Programming Console. Mnemonic code is keyed into Program Memory
addresses from the Programming Console. Checking the program involves a
syntax check to see that the program has been written according to syntax rules.
Once syntax errors are corrected, a trial execution can begin and, finally, correc-
tion under actual operating conditions can be made.
The operations required to input a program are explained below. Operations to
modify programs that already exist in memory are also provided in this section,
as well as the procedure to obtain the current cycle time.
Before starting to input a program, check to see whether there is a program
already loaded. If there is a program loaded that you do not need, clear it first
using the program memory clear key sequence, then input the new program. If
you need the previous program, be sure to check it with the program check key
sequence and correct it as required. Further debugging methods are provided in
Section 7 Program Monitoring and Execution.
4-7-1 Setting and Reading from Program Memory Address
When inputting a program for the first time, it is generally written to Program
Memory starting from address 00000. Because this address appears when the
display is cleared, it is not necessary to specify it.
When inputting a program starting from other than 00000 or to read or modify a
program that already exists in memory, the desired address must be designated.
To designate an address, press CLR and then input the desired address. Lead-
ing zeros of the address need not be input, i.e., when specifying an address such
as 00053 you need to enter only 53. The contents of the designated address will
not be displayed until the down key is pressed.
Once the down key has been pressed to display the contents of the designated
address, the up and down keys can be used to scroll through Program Memory.
Each time one of these keys is pressed, the next or previous word in Program
Memory will be displayed.
If Program Memory is read in RUN or MONITOR mode, the ON/OFF status of
any displayed bit will also be shown.
Key Sequence
104
Inputting, Modifying, and Checking the Program
Section 4-7
Example
If the following mnemonic code has already been input into Program Memory,
the key inputs below would produce the displays shown.
Address Instruction
Operands
00000
00000
00200
00200
00201
00202
LD
AND
TIM
00001
000
#
0123
00100
00203
LD
00200READ
LD
OFF
00000
00201READ
AND
ON
00001
00202READ
TIM
OFF
000
00202
TIM
#0123
ON
00203READ
LD 00100
4-7-2 Entering and Editing Programs
Programs can be entered and edited only in PROGRAM mode with the write-
protect switch (pin 1 of the CPU Unit’s DIP switch) set to OFF (OFF=“WRITE”).
The same procedure is used to either input a program for the first time or to edit a
program that already exists. In either case, the current contents of Program
Memory is overwritten, i.e., if there is no previous program, the NOP(00) instruc-
tion, which will be written at every address, will be overwritten.
To enter a program, input the mnemonic code that was produced from the ladder
diagram step-by-step, ensuring that the correct address is set before starting.
Once the correct address is displayed, enter the first instruction word and press
WRITE. Next, enter the required operands, pressing WRITE after each, i.e.,
WRITE is pressed at the end of each line of the mnemonic code. When WRITE is
pressed at the end of each line, the designated instruction or operand is entered
and the next display will appear. If the instruction requires two or more words, the
next display will indicate the next operand required and provide a default value
for it. If the instruction requires only one word, the next address will be displayed.
Continue inputting each line of the mnemonic code until the entire program has
been entered.
When inputting numeric values for operands, it is not necessary to input leading
zeros. Leading zeros are required only when inputting function codes (see
below). When designating operands, be sure to designate the data area for all
but IR and SR addresses by pressing the corresponding data area key, and to
designate each constant by pressing CONT/#. CONT/# is not required for
counter or timer SVs (see below). The AR area is designated by pressing SHIFT
and then HR. TC numbers as bit operands (i.e., completion flags) are desig-
nated by pressing either TIM or CNT before the address, depending on whether
the TC number has been used to define a timer or a counter. To designate an
indirect DM address, press CH/∗ before the address (pressing DM is not neces-
sary for an indirect DM address).
105
Inputting, Modifying, and Checking the Program
Section 4-7
Inputting SV for Counters
and Timers
The SV (set value) for a timer or counter is generally entered as a constant,
although inputting the address of a word that holds the SV is also possible. When
inputting an SV as a constant, CONT/# is not required; just input the numeric
value and press WRITE. To designate a word, press CLR and then input the
word address as described above.
Designating Instructions
The most basic instructions are input using the Programming Console keys pro-
vided for them. All other instructions are entered using function codes. These
function codes are always written after the instruction’s mnemonic. If no function
code is given, there should be a Programming Console key for that instruction.
To designate the differentiated form of an instruction, press NOT after the func-
tion code.
To input an instruction using a function code, set the address, press FUN, input
the function code including any leading zeros, press NOT if the differentiated
form of the instruction is desired, input any bit operands or definers required for
the instruction, and then press WRITE.
Caution Enter function codes with care and be sure to press SHIFT when required.
!
Key Sequence
[Address displayed]
[Instruction word]
[Operand]
106
Inputting, Modifying, and Checking the Program
Section 4-7
Example
The following program can be entered using the key inputs shown below. Dis-
plays will appear as indicated.
Address Instruction
Operands
00002
00000
00200
00200
00201
LD
TIM
000
0123
000
#
#
00202
TIMH(15)
0500
00200
LD
00002
00201READ
NOP (00)
00201
TIM
000
00201 TIM DATA
#0000
00201 TIM
#0123
00202READ
NOP (00)
00202
FUN (??)
00202
TIMH (15)
000
00202 TIMH DATA
#0000
00202 TIMH
#0500
00203READ
NOP (00)
107
Inputting, Modifying, and Checking the Program
Section 4-7
Error Messages
The following error messages may appear when inputting a program. Correct
the error as indicated and continue with the input operation. The asterisks in the
displays shown below will be replaced with numeric data, normally an address,
in the actual display.
Message
Cause and correction
****REPL ROM
An attempt was made to write to write-protected RAM or EEPROM. Ensure that the
write-protect switch is set to OFF.
****PROG OVER
****ADDR OVER
The instruction at the last address in memory is not NOP(00). Erase all unnecessary
instructions at the end of the program.
An address was set that is larger than the highest memory address in the UM area.
Input a smaller address
****SETDATA ERR Data has been input in the wrong format or beyond defined limits, e.g., a hexadecimal
value has been input for BCD. Re-enter the data. This error will generate a FALS 00
error.
****I/O NO. ERR A data area address has been designated that exceeds the limit of the data area, e.g.,
an address is too large. Confirm the requirements for the instruction and re-enter the
address.
4-7-3 Checking the Program
Once a program has been entered, the syntax should be checked to verify that
no programming rules have been violated. This check should also be performed
if the program has been changed in any way that might create a syntax error.
To check the program, input the key sequence shown below. The numbers indi-
cate the desired check level (see below). When the check level is entered, the
program check will start. If an error is discovered, the check will stop and a dis-
play indicating the error will appear. Press SRCH to continue the check. If an
error is not found, the program will be checked through to the first END(01), with
a display indicating when each 64 instructions have been checked (e.g., display
#1 of the example after the following table).
CLR can be pressed to cancel the check after it has been started, and a display
like display #2, in the example, will appear. When the check has reached the first
END, a display like display #3 will appear.
A syntax check can be performed on a program only in PROGRAM mode.
Key Sequence
To check
up to END(01)
To abort
(0, 1, 2, Check levels)
Check Levels and Error
Messages
Three levels of program checking are available. The desired level must be des-
ignated to indicate the type of errors that are to be detected. The following table
provides the error types, displays, and explanations of all syntax errors. Check
level 0 checks for type A, B, and C errors; check level 1, for type A and B errors;
and check level 2, for type A errors only.
The address where the error was generated will also be displayed.
108
Inputting, Modifying, and Checking the Program
Section 4-7
Many of the following errors are for instructions that have not yet been described
yet. Refer to 4-8 Controlling Bit Status or to Section 5 Instruction Set for details
on these.
Type
Message
Meaning and appropriate response
Type A ?????
The program has been lost. Re-enter the program.
NO END INSTR
There is no END(01) in the program. Write END(01) at the final address in the
program.
CIRCUIT ERR
The number of logic blocks and logic block instructions does not agree, i.e., either
LD or LD NOT has been used to start a logic block whose execution condition has
not been used by another instruction, or a logic block instruction has been used
that does not have the required number of logic blocks. Check your program.
LOCN ERR
DUPL
An instruction is in the wrong place in the program. Check instruction requirements
and correct the program.
The same jump number or subroutine number has been used twice. Correct the
program so that the same number is only used once for each. (Jump number 00
may be used as often as required.)
SBN UNDEFD
JME UNDEFD
OPERAND ERR
STEP ERR
SBS(91) has been programmed for a subroutine number that does not exist.
Correct the subroutine number or program the required subroutine.
A JME(04) is missing for a JMP(05). Correct the jump number or insert the proper
JME(04).
A constant entered for the instruction is not within defined values. Change the
constant so that it lies within the proper range.
STEP(08) with a section number and STEP(08) without a section number have
been used correctly. Check STEP(08) programming requirements and correct the
program.
Type B IL-ILC ERR
JMP-JME ERR
IL(02) and ILC(03) are not used in pairs. Correct the program so that each IL(02)
has a unique ILC(03). Although this error message will appear if more than one
IL(02) is used with the same ILC(03), the program will executed as written. Make
sure your program is written as desired before proceeding.
JMP(04) 00 and JME(05) 00 are not used in pairs. Although this error message will
appear if more than one JMP(04) 00 is used with the same JME(05) 00, the
program will be executed as written. Make sure your program is written as desired
before proceeding.
SBN-RET ERR
If the displayed address is that of SBN(92), two different subroutines have been
defined with the same subroutine number. Change one of the subroutine numbers
or delete one of the subroutines. If the displayed address is that of RET(93),
RET(93) has not been used properly. Check requirements for RET(93) and correct
the program.
Type C JMP UNDEFD
SBS UNDEFD
JME(05) has been used with no JMP(04) with the same jump number. Add a
JMP(04) with the same number or delete the JME(05) that is not being used.
A subroutine exists that is not called by SBS(91). Program a subroutine call in the
proper place, or delete the subroutine if it is not required.
COIL DUPL
The same bit is being controlled (i.e., turned ON and/or OFF) by more than one
instruction (e.g., OUT, OUT NOT, DIFU(13), DIFD(14), KEEP(11), SFT(10)).
Although this is allowed for certain instructions, check instruction requirements to
confirm that the program is correct or rewrite the program so that each bit is
controlled by only one instruction.
109
Inputting, Modifying, and Checking the Program
Section 4-7
Example
The following example shows some of the displays that can appear as a result of
a program check.
00000
00000PROG CHK
CHKLVL
(0Ć2)?
00064PROG CHK
Display #1
Display #2
Halts program check
00699CHK ABORTD
Check continues until END(01)
02000PROG CHK
END (01)(02.7KW)
Display #3
When errors are found
00178CIRCUIT ERR
OUT
00200
00200ILĆILC ERR
ILC (03)
02000NO END INST
END
4-7-4 Displaying the Cycle Time
Once the program has been cleared of syntax errors, the cycle time should be
checked. This is possible only in RUN or MONITOR mode while the program is
being executed. See Section 6 Program Execution Timing for details on the
cycle time.
To display the current average cycle time, press CLR then MONTR. The time
displayed by this operation is a typical cycle time. The differences in displayed
values depend on the execution conditions that exist when MONTR is pressed.
Example
00000
00000SCAN TIME
054.1MS
00000SCAN TIME
053.9MS
110
Inputting, Modifying, and Checking the Program
Section 4-7
4-7-5 Program Searches
The program can be searched for occurrences of any designated instruction or
data area address used in an instruction. Searches can be performed from any
currently displayed address or from a cleared display.
To designate a bit address, press SHIFT, press CONT/#, then input the address,
including any data area designation required, and press SRCH. To designate an
instruction, input the instruction just as when inputting the program and press
SRCH. Once an occurrence of an instruction or bit address has been found, any
additional occurrences of the same instruction or bit can be found by pressing
SRCH again. SRCH’G will be displayed while a search is in progress.
When the first word of a multiword instruction is displayed for a search operation,
the other words of the instruction can be displayed by pressing the down key
before continuing the search.
If Program Memory is read in RUN or MONITOR mode, the ON/OFF status of
any bit displayed will also be shown.
Key Sequence
111
Inputting, Modifying, and Checking the Program
Section 4-7
Example:
Instruction Search
00000
00000
LD
00000
00200SRCH
LD
00000
00000
00202SRCH
LD
02000SRCH
END (01)(02.7KW)
00000
00100
00100
TIM
001
001
00203SRCH
TIM
00203 TIM DATA
#0123
Example:
Bit Search
00000
00000CNT
CONT
00005
00200CONT SRCH
LD
00005
00203CONT SRCH
AND
00005
02000
END (01)(02.7K)
4-7-6 Inserting and Deleting Instructions
In PROGRAM mode, any instruction that is currently displayed can be deleted or
another instruction can be inserted before it. These operations are possible only
in PROGRAM mode with the write-protect switch (pin 1 of the CPU Unit’s DIP
switch) set to OFF (OFF=“WRITE”).
To insert an instruction, display the instruction before which you want the new
instruction to be placed, input the instruction word in the same way as when
inputting a program initially, and then press INS and the down key. If other words
are required for the instruction, input these in the same way as when inputting
the program initially.
112
Inputting, Modifying, and Checking the Program
Section 4-7
To delete an instruction, display the instruction word of the instruction to be
deleted and then press DEL and the up key. All the words for the designated
instruction will be deleted.
Caution Be careful not to inadvertently delete instructions; there is no way to recover
!
them without re-inputting them completely.
Key Sequences
When an instruction is inserted or deleted, all addresses in Program Memory
following the operation are adjusted automatically so that there are no blank
addresses or no unaddressed instructions.
Example
The following mnemonic code shows the changes that are achieved in a pro-
gram through the key sequences and displays shown below.
Original Program
Address Instruction
Operands
00100
00000
00001
00002
00003
00004
00005
00006
00007
00008
LD
AND
00101
00201
00102
––
LD
AND NOT
OR LD
AND
00103
00104
00201
––
AND NOT
OUT
END(01)
Before Deletion:
Before Insertion:
00104
00100
00101
00103
00105
00100
00201
00101
00102
00103
00104
Delete
00201
00201
00201
00102
00105
END(01)
END(01)
The following key inputs and displays show the procedure for achieving the pro-
gram changes shown above.
113
Inputting, Modifying, and Checking the Program
Section 4-7
Inserting an Instruction
00000
Find the address
prior to the inser-
tion point
00000
OUT
00000
00201
00201
00104
00000
00105
00000
OUT
Program After Insertion
Address Instruction
Operands
00207SRCH
OUT
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
LD
00100
00101
00201
00102
––
AND
LD
00206READ
AND NOT
AND NOT
OR LD
AND
00103
00105
00104
00201
––
00206
AND
AND
AND NOT
OUT
00206
AND
END(01)
00206INSERT?
AND
00105
Insert the
instruction
00207INSERT END
AND NOT
00104
00206READ
AND
00105
Deleting an Instruction
00000
Find the instruction
that requires deletion.
00000
OUT
00000
00201
00201
00104
Program After Deletion
Address Instruction
00000
OUT
Operands
00000
00001
00002
00003
00004
00005
00006
00007
00008
LD
00100
00101
00201
00102
––
AND NOT
LD
00208SRCH
OUT
AND NOT
OR LD
AND
00207READ
AND NOT
00103
00105
00201
––
AND
OUT
00207 DELETE?
END(01)
AND NOT
00104
00207DELETE END
OUT
00201
Confirm that this is the
instruction to be deleted.
00206READ
AND
00105
114
Inputting, Modifying, and Checking the Program
Section 4-7
4-7-7 Branching Instruction Lines
When an instruction line branches into two or more lines, it is sometimes neces-
sary to use either interlocks or TR bits to maintain the execution condition that
existed at a branching point. This is because instruction lines are executed
across to a right-hand instruction before returning to the branching point to
execute instructions on a branch line. If a condition exists on any of the instruc-
tion lines after the branching point, the execution condition could change during
this time making proper execution impossible. The following diagrams illustrate
this. In both diagrams, instruction 1 is executed before returning to the branching
point and moving on to the branch line leading to instruction 2.
Branching
point
Address Instruction
Operands
00000
00000
Instruction 1
Instruction 2
00000
00001
00002
00003
LD
00002
Instruction 1
AND
00002
Instruction 2
Diagram A: Correct Operation
Branching
point
00000
00001
00002
Instruction 1
Instruction 2
Address Instruction
Operands
00000
00001
00002
00003
00004
LD
00000
00001
AND
Instruction 1
AND
Diagram B: Incorrect Operation
00002
Instruction 2
If, as shown in diagram A, the execution condition that existed at the branching
point cannot be changed before returning to the branch line (instructions at the
far right do not change the execution condition), then the branch line will be
executed correctly and no special programming measure is required.
If, as shown in diagram B, a condition exists between the branching point and the
last instruction on the top instruction line, the execution condition at the branch-
ing point and the execution condition after completing the top instruction line will
sometimes be different, making it impossible to ensure correct execution of the
branch line.
There are two means of programming branching programs to preserve the
execution condition. One is to use TR bits; the other, to use interlocks
(IL(02)/IL(03)).
TR Bits
The TR area provides eight bits, TR 0 through TR 7, that can be used to tempo-
rarily preserve execution conditions. If a TR bit is placed at a branching point, the
current execution condition will be stored at the designated TR bit. When return-
ing to the branching point, the TR bit restores the execution status that was
saved when the branching point was first reached in program execution.
115
Inputting, Modifying, and Checking the Program
Section 4-7
The previous diagram B can be written as shown below to ensure correct execu-
tion. In mnemonic code, the execution condition is stored at the branching point
using the TR bit as the operand of the OUTPUT instruction. This execution
condition is then restored after executing the right-hand instruction by using the
same TR bit as the operand of a LOAD instruction
TR 0
Address Instruction
Operands
00000
00000
00001
00002
00000
00001
00002
00003
00004
00005
00006
LD
Instruction 1
Instruction 2
OUT
TR
0
AND
00001
Instruction 1
LD
Diagram B: Corrected Using a TR bit
TR
0
AND
00002
Instruction 2
In terms of actual instructions the above diagram would be as follows: The status
of IR 00000 is loaded (a LOAD instruction) to establish the initial execution
condition. This execution condition is then output using an OUTPUT instruction
to TR 0 to store the execution condition at the branching point. The execution
condition is then ANDed with the status of IR 00001 and instruction 1 is executed
accordingly. The execution condition that was stored at the branching point is
then re-loaded (a LOAD instruction with TR 0 as the operand), this is ANDed with
the status of IR 00002, and instruction 2 is executed accordingly.
The following example shows an application using two TR bits.
Address Instruction
Operands
00000
TR 0
TR 1
00000
00001
00002
00003
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
LD
Instruction 1
Instruction 2
Instruction 3
Instruction 4
OUT
TR
0
00001
1
AND
OUT
TR
00004
00005
AND
00002
Instruction 1
LD
TR
TR
TR
1
AND
00003
Instruction 2
LD
0
AND
00004
Instruction 3
LD
0
AND NOT
Instruction 4
00005
In this example, TR 0 and TR 1 are used to store the execution conditions at the
branching points. After executing instruction 1, the execution condition stored in
TR 1 is loaded for an AND with the status IR 00003. The execution condition
stored in TR 0 is loaded twice, the first time for an AND with the status of IR
00004 and the second time for an AND with the inverse of the status of IR 00005.
TR bits can be used as many times as required as long as the same TR bit is not
used more than once in the same instruction block. Here, a new instruction block
is begun each time execution returns to the bus bar. If, in a single instruction
block, it is necessary to have more than eight branching points that require the
execution condition be saved, interlocks (which are described next) must be
used.
116
Inputting, Modifying, and Checking the Program
Section 4-7
When drawing a ladder diagram, be careful not to use TR bits unless necessary.
Often the number of instructions required for a program can be reduced and
ease of understanding a program increased by redrawing a diagram that would
otherwise required TR bits. In both of the following pairs of diagrams, the bottom
versions require fewer instructions and do not require TR bits. In the first exam-
ple, this is achieved by reorganizing the parts of the instruction block: the bottom
one, by separating the second OUTPUT instruction and using another LOAD
instruction to create the proper execution condition for it.
Note Although simplifying programs is always a concern, the order of execution of
instructions is sometimes important. For example, a MOVE instruction may be
required before the execution of a BINARY ADD instruction to place the proper
data in the required operand word. Be sure that you have considered execution
order before reorganizing a program to simplify it.
TR 0
00000
00001
Instruction 1
Instruction 2
00000
Instruction 2
Instruction 1
00001
00000
00001
00003
Instruction 1
Instruction 2
Instruction 1
Instruction 2
TR 0
00002
00004
00001
00000
00002
00003
00001
00004
Note TR bits are only used when programming using mnemonic code. They are not
necessary when inputting ladder diagrams directly. The above limitations on the
number of branching points requiring TR bits, and considerations on methods to
reduce the number of programming instructions, still hold.
Interlocks
The problem of storing execution conditions at branching points can also be
handled by using the INTERLOCK (IL(02)) and INTERLOCK CLEAR (ILC(03))
instructions to eliminate the branching point completely while allowing a specific
execution condition to control a group of instructions. The INTERLOCK and
INTERLOCK CLEAR instructions are always used together.
117
Inputting, Modifying, and Checking the Program
Section 4-7
When an INTERLOCK instruction is placed before a section of a ladder pro-
gram, the execution condition for the INTERLOCK instruction will control the
execution of all instruction up to the next INTERLOCK CLEAR instruction. If the
execution condition for the INTERLOCK instruction is OFF, all right-hand
instructions through the next INTERLOCK CLEAR instruction will be executed
with OFF execution conditions to reset the entire section of the ladder diagram.
The effect that this has on particular instructions is described in 5-10 INTER-
LOCK and INTERLOCK CLEAR – IL(02) and ILC(03).
Diagram B can also be corrected with an interlock. Here, the conditions leading
up to the branching point are placed on an instruction line for the INTERLOCK
instruction, all of lines leading from the branching point are written as separate
instruction lines, and another instruction line is added for the INTERLOCK
CLEAR instruction. No conditions are allowed on the instruction line for INTER-
LOCK CLEAR. Note that neither INTERLOCK nor INTERLOCK CLEAR
requires an operand.
00000
IL(02)
Address Instruction
Operands
00000
00000
00001
00002
00003
00004
00005
00006
LD
00001
00002
Instruction 1
Instruction 2
IL(02)
---
LD
00001
Instruction 1
LD
00002
---
ILC(03)
Instruction 2
ILC(03)
If IR 00000 is ON in the revised version of diagram B, above, the status of IR
00001 and that of IR 00002 would determine the execution conditions for
instructions 1 and 2, respectively. Because IR 00000 is ON, this would produce
the same results as ANDing the status of each of these bits. If IR 00000 is OFF,
the INTERLOCK instruction would produce an OFF execution condition for
instructions 1 and 2 and then execution would continue with the instruction line
following the INTERLOCK CLEAR instruction.
As shown in the following diagram, more than one INTERLOCK instruction can
be used within one instruction block; each is effective through the next INTER-
LOCK CLEAR instruction.
00000
00001
00002
IL(02)
Address Instruction
Operands
00000
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
LD
Instruction 1
IL(02)
IL(02)
---
LD
00001
Instruction 1
LD
00002
---
00003
00005
00006
00004
IL(02)
Instruction 2
Instruction 3
Instruction 4
LD
00003
00004
AND NOT
Instruction 2
LD
00005
00006
---
Instruction 3
LD
ILC(03)
Instruction 4
ILC(03)
118
Inputting, Modifying, and Checking the Program
Section 4-7
If IR 00000 in the above diagram is OFF (i.e., if the execution condition for the
first INTERLOCK instruction is OFF), instructions 1 through 4 would be
executed with OFF execution conditions and execution would move to the
instruction following the INTERLOCK CLEAR instruction. If IR 00000 is ON, the
status of IR 00001 would be loaded as the execution condition for instruction 1
and then the status of IR 00002 would be loaded to form the execution condition
for the second INTERLOCK instruction. If IR 00002 is OFF, instructions 2
through 4 will be executed with OFF execution conditions. If IR 00002 is ON, IR
00003, IR 00005, and IR 00006 will determine the first execution condition in
new instruction lines.
4-7-8 Jumps
A specific section of a program can be skipped according to a designated execu-
tion condition. Although this is similar to what happens when the execution
condition for an INTERLOCK instruction is OFF, with jumps, the operands for all
instructions maintain status. Jumps can therefore be used to control devices
that require a sustained output, e.g., pneumatics and hydraulics, whereas inter-
locks can be used to control devices that do not required a sustained output,
e.g., electronic instruments.
Jumps are created using the JUMP (JMP(04)) and JUMP END (JME(05))
instructions. If the execution condition for a JUMP instruction is ON, the program
is executed normally as if the jump did not exist. If the execution condition for the
JUMP instruction is OFF, program execution moves immediately to a JUMP
END instruction without changing the status of anything between the JUMP and
JUMP END instruction.
All JUMP and JUMP END instructions are assigned jump numbers ranging
between 00 and 99. There are two types of jumps. The jump number used deter-
mines the type of jump.
A jump can be defined using jump numbers 01 through 99 only once, i.e., each of
these numbers can be used once in a JUMP instruction and once in a JUMP
END instruction. When a JUMP instruction assigned one of these numbers is
executed, execution moves immediately to the JUMP END instruction that has
the same number as if all of the instruction between them did not exist. Diagram
B from the TR bit and interlock example could be redrawn as shown below using
a jump. Although 01 has been used as the jump number, any number between
01 and 99 could be used as long as it has not already been used in a different part
of the program. JUMP and JUMP END require no other operand and JUMP END
never has conditions on the instruction line leading to it.
00000
00001
00002
JMP(04) 01
Instruction 1
Instruction 2
Address Instruction
Operands
00000
00000
00001
00002
00003
00004
00005
00006
LD
JMP(04)
LD
01
00001
Instruction 1
LD
00002
015
JME(05) 01
Instruction 2
JME(05)
Diagram B: Corrected with a Jump
This version of diagram B would have a shorter execution time when 00000 was
OFF than any of the other versions.
119
Controlling Bit Status
Section 4-8
The other type of jump is created with a jump number of 00. As many jumps as
desired can be created using jump number 00 and JUMP instructions using 00
can be used consecutively without a JUMP END using 00 between them. It is
even possible for all JUMP 00 instructions to move program execution to the
same JUMP END 00, i.e., only one JUMP END 00 instruction is required for all
JUMP 00 instruction in the program. When 00 is used as the jump number for a
JUMP instruction, program execution moves to the instruction following the next
JUMP END instruction with a jump number of 00. Although, as in all jumps, no
status is changed and no instructions are executed between the JUMP 00 and
JUMP END 00 instructions, the program must search for the next JUMP END 00
instruction, producing a slightly longer execution time.
Execution of programs containing multiple JUMP 00 instructions for one JUMP
END 00 instruction is similar to that of interlocked sections. The following dia-
gram is the same as that used for the interlock example above, except redrawn
with jumps. The execution of this diagram would differ from that of the diagram
described above (e.g., in the previous diagram interlocks would reset certain
parts of the interlocked section, however, jumps do not affect the status of any bit
between the JUMP and JUMP END instructions).
00000
00001
00002
JMP(04) 00
Address Instruction
Operands
00000
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
LD
JMP(04)
LD
00
Instruction 1
JMP(04) 00
00001
Instruction 1
LD
00002
00
00003
00005
00006
00004
JMP(04)
LD
Instruction 2
Instruction 3
Instruction 4
00003
00004
AND NOT
Instruction 2
LD
00005
00006
00
Instruction 3
LD
JME(05) 00
Instruction 4
JME(05)
4-8 Controlling Bit Status
There are five instructions that can be used generally to control individual bit sta-
tus. These are the OUTPUT, OUTPUT NOT, DIFFERENTIATE UP, DIFFER-
ENTIATE DOWN, and KEEP instructions. All of these instructions appear as the
last instruction in an instruction line and take a bit address for an operand.
Although details are provided in 5-9 Bit Control Instructions, these instructions
(except for OUTPUT and OUTPUT NOT, which have already been introduced)
are described here because of their importance in most programs. Although
these instructions are used to turn ON and OFF output bits in the IR area (i.e., to
send or stop output signals to external devices), they are also used to control the
status of other bits in the IR area or in other data areas.
120
Controlling Bit Status
Section 4-8
4-8-1 DIFFERENTIATE UP and DIFFERENTIATE DOWN
DIFFERENTIATE UP and DIFFERENTIATE DOWN instructions are used to
turn the operand bit ON for one cycle at a time. The DIFFERENTIATE UP
instruction turns ON the operand bit for one cycle after the execution condition
for it goes from OFF to ON; the DIFFERENTIATE DOWN instruction turns ON
the operand bit for one cycle after the execution condition for it goes from ON to
OFF. Both of these instructions require only one line of mnemonic code.
00000
00001
Address Instruction
Operands
00000
00200
DIFU(13) 00200
DIFD(14) 00201
00000
00001
LD
DIFU(13)
Address Instruction
Operands
00000
00001
LD
00001
00201
DIFD(14)
Here, IR 00200 will be turned ON for one cycle after IR 00000 goes ON. The next
time DIFU(13) 00200 is executed, IR 00200 will be turned OFF, regardless of the
status of IR 00000. With the DIFFERENTIATE DOWN instruction, IR 00201 will
be turned ON for one cycle after IR 00001 goes OFF (IR 00201 will be kept OFF
until then), and will be turned OFF the next time DIFD(14) 00201 is executed.
4-8-2 KEEP
The KEEP instruction is used to maintain the status of the operand bit based on
two execution conditions. To do this, the KEEP instruction is connected to two
instruction lines. When the execution condition at the end of the first instruction
line is ON, the operand bit of the KEEP instruction is turned ON. When the
execution condition at the end of the second instruction line is ON, the operand
bit of the KEEP instruction is turned OFF. The operand bit for the KEEP instruc-
tion will maintain its ON or OFF status even if it is located in an interlocked sec-
tion of the diagram.
In the following example, HR 0000 will be turned ON when IR 00002 is ON and IR
00003 is OFF. HR 0000 will then remain ON until either IR 00004 or IR 00005
turns ON. With KEEP, as with all instructions requiring more than one instruction
line, the instruction lines are coded first before the instruction that they control.
00002
00003
Address Instruction
Operands
00002
00000
00001
00002
00003
00004
LD
S: set input
KEEP(11)
HR 0000
AND NOT
LD
00003
00004
00005
0000
00004
00005
OR
R: reset input
KEEP(11)
HR
4-8-3 Self-maintaining Bits (Seal)
Although the KEEP instruction can be used to create self-maintaining bits, it is
sometimes necessary to create self-maintaining bits in another way so that they
can be turned OFF when in an interlocked section of a program.
121
Work Bits (Internal Relays)
Section 4-9
To create a self-maintaining bit, the operand bit of an OUTPUT instruction is
used as a condition for the same OUTPUT instruction in an OR setup so that the
operand bit of the OUTPUT instruction will remain ON or OFF until changes
occur in other bits. At least one other condition is used just before the OUTPUT
instruction to function as a reset. Without this reset, there would be no way to
control the operand bit of the OUTPUT instruction.
The above diagram for the KEEP instruction can be rewritten as shown below.
The only difference in these diagrams would be their operation in an interlocked
program section when the execution condition for the INTERLOCK instruction
was ON. Here, just as in the same diagram using the KEEP instruction, two reset
bits are used, i.e., HR 0000 can be turned OFF by turning ON either IR 00004 or
IR 00005.
00002
00003
00004
Address Instruction
Operands
00002
00005
HR 0000
00000
00001
00002
00003
00004
00005
LD
AND NOT
OR
00003
0000
HR
HR
HR 0000
AND NOT
AND NOT
OUT
00004
00005
0000
4-9 Work Bits (Internal Relays)
In programming, combining conditions to directly produce execution conditions
is often extremely difficult. These difficulties are easily overcome, however, by
using certain bits to trigger other instructions indirectly. Such programming is
achieved by using work bits. Sometimes entire words are required for these pur-
poses. These words are referred to as work words.
Work bits are not transferred to or from the PC. They are bits selected by the
programmer to facilitate programming as described above. I/O bits and other
dedicated bits cannot be used as works bits. All bits in the IR area that are not
allocated as I/O bits, and certain unused bits in the AR area, are available for use
as work bits. Be careful to keep an accurate record of how and where you use
work bits. This helps in program planning and writing, and also aids in debugging
operations.
Work Bit Applications
Examples given later in this subsection show two of the most common ways to
employ work bits. These should act as a guide to the almost limitless number of
ways in which the work bits can be used. Whenever difficulties arise in program-
ming a control action, consideration should be given to work bits and how they
might be used to simplify programming.
Work bits are often used with the OUTPUT, OUTPUT NOT, DIFFERENTIATE
UP, DIFFERENTIATE DOWN, and KEEP instructions. The work bit is used first
as the operand for one of these instructions so that later it can be used as a
condition that will determine how other instructions will be executed. Work bits
can also be used with other instructions, e.g., with the SHIFT REGISTER
instruction (SFT(10)). An example of the use of work words and bits with the
SHIFT REGISTER instruction is provided in 5-15-1 SHIFT REGISTER –
SFT(10).
Although they are not always specifically referred to as work bits, many of the
bits used in the examples in Section 5 Instruction Set use work bits. Understand-
ing the use of these bits is essential to effective programming.
122
Work Bits (Internal Relays)
Section 4-9
Reducing Complex
Conditions
Work bits can be used to simplify programming when a certain combination of
conditions is repeatedly used in combination with other conditions. In the follow-
ing example, IR 00000, IR 00001, IR 00002, and IR 00003 are combined in a
logic block that stores the resulting execution condition as the status of IR
24600. IR 24600 is then combined with various other conditions to determine
output conditions for IR 00100, IR 00101, and IR 00102, i.e., to turn the outputs
allocated to these bits ON or OFF.
Address Instruction
Operands
00000
00000
00002
00003
00001
24600
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
LD
AND NOT
OR
00001
00002
00003
24600
24600
00004
00005
00100
24600
00004
00005
00101
24600
00006
00007
00102
OR NOT
OUT
LD
AND
AND NOT
OUT
24600
24600
00004
00005
00005
00100
00101
LD
OR NOT
AND
OUT
LD NOT
OR
00004
24600
OR
OUT
00102
00006
00007
Differentiated Conditions
Work bits can also be used if differential treatment is necessary for some, but not
all, of the conditions required for execution of an instruction. In this example, IR
00100 must be left ON continuously as long as IR 00001 is ON and both IR
00002 and IR 00003 are OFF, or as long as IR 00004 is ON and IR 00005 is OFF.
It must be turned ON for only one cycle each time IR 00000 turns ON (unless one
of the preceding conditions is keeping it ON continuously).
123
Programming Precautions
Section 4-10
This action is easily programmed by using IR 22500 as a work bit as the operand
of the DIFFERENTIATE UP instruction (DIFU(13)). When IR 00000 turns ON, IR
22500 will be turned ON for one cycle and then be turned OFF the next cycle by
DIFU(13). Assuming the other conditions controlling IR 00100 are not keeping it
ON, the work bit IR 22500 will turn IR 00100 ON for one cycle only.
00000
Address Instruction
Operands
00000
DIFU(13) 22500
00100
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
LD
DIFU(13)
LD
22500
22500
00001
00002
00003
---
22500
00001
00002
00003
LD
AND NOT
AND NOT
OR LD
LD
00004
00005
00004
00005
---
AND NOT
OR LD
OUT
00100
4-10 Programming Precautions
The number of conditions that can be used in series or parallel is unlimited as
long as the memory capacity of the PC is not exceeded. Therefore, use as many
conditions as required to draw a clear diagram. Although very complicated dia-
grams can be drawn with instruction lines, there must not be any conditions on
lines running vertically between two other instruction lines. Diagram A shown
below, for example, is not possible, and should be drawn as diagram B. Mne-
monic code is provided for diagram B only; coding diagram A would be impossi-
ble.
00000
00002
00003
Instruction 1
Instruction 2
00004
00001
Diagram A
00001
00004
00004
00002
00003
Address Instruction
Operands
00001
Instruction 1
Instruction 2
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
LD
00000
00000
AND
00004
00000
00002
OR
AND
Instruction 1
LD
00001
00000
00004
00001
00003
AND
Diagram B
OR
AND NOT
Instruction 2
The number of times any particular bit can be assigned to conditions is not lim-
ited, so use them as many times as required to simplify your program. Often,
complicated programs are the result of attempts to reduce the number of times a
bit is used.
124
Programming Precautions
Section 4-10
Except for instructions for which conditions are not allowed (e.g., INTERLOCK
CLEAR and JUMP END, see below), every instruction line must also have at
least one condition on it to determine the execution condition for the instruction
at the right. Again, diagram A , below, must be drawn as diagram B. If an instruc-
tion must be continuously executed (e.g., if an output must always be kept ON
while the program is being executed), the Always ON Flag (SR 25313) in the SR
area can be used.
Instruction
Diagram A: Incorrect
25313
Address Instruction
Operands
25313
Instruction
00000
00001
LD
Instruction
Diagram B
There are a few exceptions to this rule, including the INTERLOCK CLEAR,
JUMP END, and step instructions. Each of these instructions is used as the
second of a pair of instructions and is controlled by the execution condition of the
first of the pair. Conditions should not be placed on the instruction lines leading to
these instructions. Refer to Section 5 Instruction Set for details.
When drawing ladder diagrams, it is important to keep in mind the number of
instructions that will be required to input it. In diagram A, below, an OR LOAD
instruction will be required to combine the top and bottom instruction lines. This
can be avoided by redrawing as shown in diagram B so that no AND LOAD or OR
LOAD instructions are required. Refer to 5-8-2 AND LOAD and OR LOAD for
more details and Section 7 Program Monitoring and Execution for further exam-
ples.
Address Instruction
Operands
00000
00000
00207
00000
00001
00002
00003
00004
LD
LD
00001
00207
---
00001 00207
AND
OR LD
OUT
00207
Diagram A
Address Instruction
Operands
00001 00207
00000
00207
00000
00001
00002
00003
LD
00001
00207
00000
00207
AND
OR
OUT
Diagram B
125
Special I/O Unit Interface Programs
Section 4-12
4-11 Program Execution
When program execution is started, the CPU Unit cycles the program from top to
bottom, checking all conditions and executing all instructions accordingly as it
moves down the bus bar. It is important that instructions be placed in the proper
order so that, for example, the desired data is moved to a word before that word
is used as the operand for an instruction. Remember that an instruction line is
completed to the terminal instruction at the right before executing an instruction
lines branching from the first instruction line to other terminal instructions at the
right.
Program execution is only one of the tasks carried out by the CPU Unit as part of
the cycle time. Refer to Section 6 Program Execution Timing for details.
4-12 Special I/O Unit Interface Programs
This section provides programming methods and precautions for Special I/O
Unit operation.
4-12-1 Restarting Special I/O Units
When a Special I/O Unit is restarted, execution of IORF(97) is disabled until Spe-
cial I/O Unit initialization is completed.
ON
SR 28100
OFF
(Unit #0 Restart Bit)
Special I/O Unit
Initialization
ON
SR 27400
OFF
(Unit #0 Restart Flag)
Execution of IORF(97)
for Unit #0
Enabled
Disabled
Enabled
While the Restart Flag (SR 27400) is ON, normal END refreshing is performed
and the Special I/O Unit is initialized. This processing occurs regardless of the
settings in DM 6620, DM 6621, and DM 6623, which relate to Special I/O Unit
refreshing. IORF(97) instructions in the program won’t be executed for the ini-
tializing Unit until initialization is completed.
Special I/O Unit data that was to be refreshed might be lost during initialization.
When writing a program to restart Special I/O Units, disable programming that
depends on data from the initializing Special I/O Unit, such as data used in cal-
culations, while its Restart Flag (SR 27400 to SR 27415) is ON. Normal program
operations can continue for Units that aren’t initializing.
The Restart Flag won’t turn ON for Special I/O Units mounted on Slave Racks.
The standard Special I/O Unit restart time is (20 × the cycle time).
126
Special I/O Unit Interface Programs
Section 4-12
4-12-2 Special I/O Unit Error Processing Program
Use a program like the one shown below to restart a Special I/O Unit in which an
error has occurred. This example program restarts Unit 1.
AR 0001
(Unit #0 Error Flag)
AR0001
DIFU(13) AR0101
Restart
SR 27401
(Unit #1 Restart Flag)
27401
Disables
calculations
JMP(04) 00
during Ini-
tialization.
Calculations using data from Special I/O Unit 1
JME(05) 00
4-12-3 Changing the Special I/O Unit Settings
In the C200HX/HG/HE, ladder instructions can be used to write data into the
Special I/O Unit Areas (DM 1000 to DM 2599) and change the Special I/O Unit
settings. Changing the settings is useful when different settings are required for
different production processes.
In this example there are two production processes that require different Special
I/O Unit settings. The settings for the first process are stored in DM 7000 through
DM 7999 and the settings for the second process are stored in DM 8000 through
DM 8999.
Programming Console
Operations
Steps 1 through 5 in the following procedure aren’t necessary when XFER(70) is
used to overwrite DM 1000 through DM 1999 directly from the program with the
contents of fixed DM (DM 6144 through DM 6599). In this case, just restart the
Unit from the program after overwriting DM 1000 through DM 1999.
1, 2, 3...
1. Clear the memory (all clear).
The UM Area Allocation operation can’t be performed unless the memory
has been cleared.
2. Perform the UM Area Allocation operation to allocate 2K words to the
expansion DM area (DM 7000 through DM 8999).
CLR
FUN
VER
CHG
B 1
D 3
PLAY
SET
WRITE
9
7
3. Perform the Hexadecimal/BCD Data Modification operation to set the Spe-
cial I/O Unit mode to “C200H-compatible ROM mode 1” by setting DM 6602
to #0100. This mode transfers the contents of DM 7000 through DM 7999 to
DM 1000 through DM 1999 at PC startup. This new PC Setup setting won’t
be effective until the PC is restarted by turning it off and then on again.
4. Set pin 4 of the CPU Unit’s DIP switch to ON. This setting enables the user to
assign expansion instruction function codes.
127
Special I/O Unit Interface Programs
Section 4-12
5. Perform the Expansion Instruction Function Code Assignment operation to
assign a function code to XDMR(––).
6. Input the program.
Example Program
(Special I/O Unit 2)
The following program changes the Special I/O Unit Area settings for Unit 2,
restarts the Unit, and disables calculations using data from Unit 2 while the Unit
is initializing.
Transfers
the contents
End of process 1.
40000
of DM 8200
through
DM 8299 to
@XDMR
#0100
DM 1200
#8200
through
DM 1299.
DM1200
Restarts
Unit 2.
DIFU(13) AR0102
Unit #2 Restart Flag
27402
Disables
calculations
JMP(04) 00
during Ini-
tialization.
Calculations using data from Special I/O Unit 2
JME(05) 00
4-12-4 Special I/O Unit I/O Refreshing Interval
When the interval between I/O refreshes is too short, the processing in the Spe-
cial I/O Unit can be delayed causing Special I/O Unit errors or otherwise interfer-
ing with proper Unit operation. In this case, use the following methods to restore
normal operation.
Short Interval between
END Refreshes
There are two ways to extend the interval between I/O refreshes. Either of these
methods can be used.
1, 2, 3...
1. Disable cyclic Special I/O Unit refreshing in the PC Setup (DM 6621) and
use IORF(97) to refresh the Special I/O Unit’s I/O only when necessary.
To disable cyclic refreshing for all Special I/O Units mounted to the CPU
Rack or Expansion I/O Racks, set DM 6621 to #0100.
2. Increase the PC’s cycle time by setting a minimum cycle time in the PC
Setup (DM 6619) or executing SCAN(18) in the program. (SCAN(18) is an
expansion instruction with default function code 18.)
Short Interval between
IORF(97) and END Refresh
Change the program to use either IORF(97) refreshing or END refreshing. It is
also possible to increase the PC’s cycle time by setting a minimum cycle time in
the PC Setup (DM 6619) or executing SCAN(18) in the program.
Short Interval between
IORF(97) Instructions
Change the program to increase the spacing between IORF(97) instructions or
use just one IORF(97) instruction.
128
Special I/O Unit Interface Programs
Section 4-12
4-12-5 Reducing the Cycle Time
When a Special I/O Unit is mounted in a C200HX/HG/HE PC, END refreshing is
performed automatically each cycle without making any special settings. When
several Special I/O Units are being used, the cycle time might become too long
because of the time required for this automatic I/O refreshing.
To reduce the time devoted to I/O refreshing, disable cyclic Special I/O Unit
refreshing in the PC Setup (DM 6621) and use IORF(97) to refresh the Special
I/O Units instead. I/O refreshing for all Special I/O Units mounted to the CPU
Rack or Expansion I/O Racks can be disabled in the PC Setup by setting DM
6621 to #0100.
The following example program reduces the Special I/O Unit refreshing time for
a PC with four Special I/O Units by refreshing just one Unit each cycle. The Units
are refreshed in order: Unit 0, Unit 1, Unit 2, Unit 3, Unit 0, and so on.
C200HX/HG/HE
129
Analog Timer Unit Programming
Section 4-13
The following program example is relevant for Special I/O Units mounted to the
CPU Rack or Expansion I/O Racks only, because END refreshing is always per-
formed on Special I/O Units mounted to Slave Racks regardless of the PC Setup
settings.
30000
30000
30000
30000
30001
30000
30001
30002
30003
30001
30001
30001
30001
30002
30002
30002
30002
30002
30003
30003
30003
30003
30003
30000
30001
30002
30003
30000
IORF(97)
IORF(97)
IORF(97)
IORF(97)
100
100
Refreshes Unit 0.
1 cycle
110
110
Refreshes Unit 1.
Refreshes Unit 2.
120
120
130
130
Refreshes Unit 3.
Note IR 30000 is used in an OUT instruction twice in this program. Although accept-
able in the above example, this type of duplication is not usually allowed unless
there is a specific reason and then only when proper operation can be ensured.
4-13 Analog Timer Unit Programming
An Analog Timer Unit’s timer SV can be changed easily without a Programming
Console. The Unit is equipped with an external variable resistor connector, so a
variable resistor can be installed in the control panel and connected to the Ana-
log Timer Unit to set or adjust the timer SV manually.
4-13-1 Operation
When the Timer Start Input is turned ON, the Timer Set Bits allocated to the Ana-
log Timer Unit (bits 00 to 03 of n) are turned ON, the analog timer begins to oper-
ate, and the timer set indicator (SET) on the Unit will light.
When the Unit’s timer SV (set internally or externally) elapses, the Unit’s Com-
pletion Flags (bits 08 to 11 of n) and the Time-up Output will be turned ON. Also,
the time-up indicator on the Unit (TIME UP) will light.
130
Analog Timer Unit Programming
Section 4-13
Refer to the Analog Timer Unit’s Operation Manual for details on switching
between internal and external timer SV settings, connecting a variable resistor,
and switch settings.
Timer Start Input
Timer Set
Bits
(Bits 00 to
03 of n)
Bits 08 to 11 of n
Time-up
Output
Completion Flags
Timer Start Input
Time-up Output
Timer interval
4-13-2 Bit Allocation and DIP Switch Settings
The following table shows the use of the word (n) allocated to the Analog Timer
Unit. This word address depends upon the slot in which the Unit is mounted.
Bit
I/O class
Function
Timer 0 Set Bit
Timer 1 Set Bit
Timer 2 Set Bit
Timer 3 Set Bit
Timer 0 Stop Bit
Timer 1 Stop Bit
Timer 2 Stop Bit
Timer 3 Stop Bit
Comments
00
01
02
03
04
05
06
07
08
09
10
11
Output
ON when timer is set.
OFF: Enable timer operation
ON: Stop timer operation
Input
Timer 0 Completion Flag ON when timer has timed out.
Timer 1 Completion Flag
Timer 2 Completion Flag
Timer 3 Completion Flag
12 to 15 ---
Not used.
---
Timer Range Setting
Set the timer range with the upper DIP switch on the front of the Unit. Each tim-
er’s range can be set independently.
Range
Timer 0
Timer 1
Timer 2
Timer 3
Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1
0.1 to 1 s
OFF
ON
OFF
OFF
ON
OFF
ON
OFF
OFF
ON
OFF
ON
OFF
OFF
ON
OFF
ON
OFF
OFF
ON
1 to 10 s
10 to 60 s
OFF
ON
OFF
ON
OFF
ON
OFF
ON
1 to 10 minutes
ON
ON
ON
ON
Selecting Internal/External
Timer SV Setting
Select internal or external setting with the lower DIP switch on the front of the
Unit.
Setting
Internal
External
Timer 0 (pin 4) Timer 1 (pin 3) Timer 2 (pin 2) Timer 3 (pin 1)
ON
ON
ON
ON
OFF
OFF
OFF
OFF
131
Analog Timer Unit Programming
Section 4-13
4-13-3 Example Program
Unit Configuration
The following table shows the word allocations for the Units in this example.
Item
Word
IR 002
IR word allocated to the Analog Timer Unit
IR word allocated to the Input Unit
IR word allocated to the Output Unit
IR 000
IR 005
The Analog Timer Unit’s SV settings and external variable resistor control con-
nections are shown below.
Timer
Set value
Range
Variable
resistor
setting
Variable resistor
control
0
1
2
3
0.6 s
0.1 to 1 s
60% clockwise Internal
30% clockwise Internal
20% clockwise External
3 s
1 to 10 s
20 s
10 to 60 s
8 minutes
1 to 10 minutes 80% clockwise External
132
Analog Timer Unit Programming
Section 4-13
Unit Settings and Wiring
The following diagram shows the switch settings and wiring connections
required to achieve the Unit configuration shown above.
The settings on these two variable resistor controls are valid
because timers 0 and 1 are set for internal SV settings.
Use the screwdriver included with the Unit to set the variable
resistor.
The settings on these two variable resistor controls are not
valid because timers 2 and 3 are set for external SV settings.
The timer range settings are as follows:
Timer 0:
Timer 1:
Timer 2:
Timer 3:
0.1 to 1 second 1 to 10 seconds 10 to 60 seconds 1 to 10 minutes
Pin 8
OFF
Pin 7 Pin 6
OFF ON
Pin 5
OFF
Pin 4
OFF
Pin 3 Pin 2
Pin 1
ON
ON
ON
The internal/external SV settings are as follows:
Timer 0
Timer 1
Timer 2
Timer 3
Pin 4
Pin 3
Pin 2
External
OFF
Pin 1
Internal
Internal
External
ON
ON
OFF
Do not connect anything to these connectors. Timers 0 and 1
are set for internal SV settings, so the variable resistor con-
trols at the top of the Unit are used to set their SVs.
External SV Settings (0 to 20 KΩ)
Connect variable resistor for timers 2 and 3 to these connec-
tors. Refer to the Analog Timer Unit’s Operation Manual for
details on these settings.
133
Analog Timer Unit Programming
Section 4-13
Ladder Program
The following diagram shows the example ladder program.
1, 2, 3...
1. Output IR 00500 will go ON about 0.6 s (T0) after input IR 00002 goes ON.
2. Output IR 00501 will go ON about 3 s (T1) after input IR 00003 goes ON.
3. Output IR 00502 will go ON about 20 s (T2) after input IR 00004 goes ON
and IR 00503 will go ON about 8 minutes (T3) after input IR 00004 goes ON.
4. Timers 2 and 3 are stopped by input IR 00005.
Timer Stop Bit
00005 Timer 0 Completion Flag
00206
T2
Timers 2 and 3 stop operating when the
emergency stop input goes ON.
00207
T3
Timer 0 Set Bit
00002
Timer 0 (00200) starts operating and the
Unit’s SET indicator lights when IR 00002
T0
00200
goes ON.
When the time set on the internal volume
control elapses, the Completion Flag (00208)
goes ON and the Unit’s TIME UP indicator
00208
00500
Timer 0 Completion Flag
lights. Output IR 00500 goes ON at the same
time.
Timer 1 Set Bit
00003
Timer 1 (00201) starts operating and the
Unit’s SET indicator lights when IR 00003
00201
T1
goes ON.
When the time set on the internal variable
00209
resistor control elapses, the Completion Flag
00501
(00209) goes ON and the Unit’s TIME UP
Timer 1 Completion Flag
indicator lights. Output IR 00501 goes ON at
Timer 2 Set Bit
the same time.
00004
00202
T2
Timer 2 (00202) and timer 3 (00203) start
operating and the Unit’s SET indicator lights
when IR 00004 goes ON.
00203
T3
When the time set on the external variable
resistor control elapses, the Completion Flag
(00210) goes ON and the Unit’s TIME UP
indicator lights. Output IR 00502 goes ON at
the same time.
00210
00502
Timer 2 Completion Flag
When the time set on the external variable
resistor control elapses, the Completion Flag
(00211) goes ON and the Unit’s TIME UP
indicator lights. Output IR 00503 goes ON at
the same time.
00211
00503
Timer 3 Completion Flag
134
SECTION 5
Instruction Set
The C200HX/HG/HE PCs have large programming instruction sets that allow for easy programming of complicated control
processes. This section explains instructions individually and provides the ladder diagram symbol, data areas, and flags used
with each.
The C200HX/HG/HS PCs can process more than 100 instructions that require function codes, but only 100 function codes (00
to 99) are available. Some instructions, called expansion instructions, do not have fixed function codes and must be assigned
function codes from the 18 function codes set aside for expansion instructions before they can be used.
The many instructions provided by the C200HX/HG/HE PCs are organized in the following subsections by instruction group.
These groups include Ladder Diagram Instructions, Bit Control Instructions, Timer and Counter Instructions, Data Shifting
Instructions, Data Movement Instructions, Data Comparison Instructions, Data Conversion Instructions, BCD Calculation
Instructions, Binary Calculation Instructions, Logic Instructions, Subroutines, Special Instructions, Network Instructions,
Serial Communications Instructions, Advanced I/O Instructions, and Special I/O Unit Instructions.
Some instructions, such as Timer and Counter instructions, are used to control execution of other instructions, e.g., a TIM
Completion Flag might be used to turn ON a bit when the time period set for the timer has expired. Although these other
instructions are often used to control output bits through the Output instruction, they can be used to control execution of other
instructions as well. The Output instructions used in examples in this manual can therefore generally be replaced by other
instructions to modify the program for specific applications other than controlling output bits directly.
5-1 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-2 Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-3 Data Areas, Definer Values, and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-4 Differentiated Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-5 Expansion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-6 Coding Right-hand Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-7 Instruction Set Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
138
138
138
140
141
142
145
145
145
149
149
150
150
150
151
153
154
155
157
158
158
158
159
164
165
166
169
171
171
173
175
175
176
176
177
177
178
178
180
180
180
5-7-1
5-7-2
Function Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alphabetic List by Mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-8 Ladder Diagram Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-8-1
5-8-2
LOAD, LOAD NOT, AND, AND NOT, OR, and OR NOT . . . . . . . . . . . . . . . . . . . . . . .
AND LOAD and OR LOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-9 Bit Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-9-1
5-9-2
5-9-3
5-9-4
OUTPUT and OUTPUT NOT – OUT and OUT NOT . . . . . . . . . . . . . . . . . . . . . . . . . . .
DIFFERENTIATE UP and DOWN – DIFU(13) and DIFD(14) . . . . . . . . . . . . . . . . . . . .
SET and RESET – SET and RSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
KEEP – KEEP(11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-10 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) . . . . . . . . . . . . . . . . . . . . . . . . . .
5-11 JUMP and JUMP END – JMP(04) and JME(05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-12 END – END(01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-13 NO OPERATION – NOP(00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14 Timer and Counter Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14-1 TIMER – TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14-2 HIGH-SPEED TIMER – TIMH(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14-3 TOTALIZING TIMER – TTIM(87) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14-4 COUNTER – CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14-5 REVERSIBLE COUNTER – CNTR(12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15 Data Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-1 SHIFT REGISTER – SFT(10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-2 REVERSIBLE SHIFT REGISTER – SFTR(84) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-3 ARITHMETIC SHIFT LEFT – ASL(25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-4 ARITHMETIC SHIFT RIGHT – ASR(26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-5 ROTATE LEFT – ROL(27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-6 ROTATE RIGHT – ROR(28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-7 ONE DIGIT SHIFT LEFT – SLD(74) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-8 ONE DIGIT SHIFT RIGHT – SRD(75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-9 WORD SHIFT – WSFT(16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15-10 ASYNCHRONOUS SHIFT REGISTER – ASFT(17) . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16 Data Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-1 MOVE – MOV(21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-2 MOVE NOT – MVN(22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5-16-3 BLOCK SET – BSET(71) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-4 BLOCK TRANSFER – XFER(70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-5 DATA EXCHANGE – XCHG(73) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-6 SINGLE WORD DISTRIBUTE – DIST(80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-7 DATA COLLECT – COLL(81) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-8 MOVE BIT – MOVB(82) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-9 MOVE DIGIT – MOVD(83) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-10 TRANSFER BITS – XFRB(62) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-11 EM BLOCK TRANSFER – XFR2(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-16-12 EM BANK TRANSFER – BXF2(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17 Data Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17-1 MULTI-WORD COMPARE – MCMP(19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17-2 COMPARE – CMP(20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17-3 DOUBLE COMPARE – CMPL(60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17-4 BLOCK COMPARE – BCMP(68) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17-5 TABLE COMPARE – TCMP(85) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17-6 AREA RANGE COMPARE – ZCP(88) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17-7 DOUBLE AREA RANGE COMPARE – ZCPL(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17-8 SIGNED BINARY COMPARE – CPS(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-17-9 DOUBLE SIGNED BINARY COMPARE – CPSL(––) . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18 Data Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-1 BCD-TO-BINARY – BIN(23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-2 DOUBLE BCD-TO-DOUBLE BINARY – BINL(58) . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-3 BINARY-TO-BCD – BCD(24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-4 DOUBLE BINARY-TO-DOUBLE BCD – BCDL(59) . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-5 HOURS-TO-SECONDS – SEC(65) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-6 SECONDS-TO-HOURS – HMS(66) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-7 4-TO-16/8-TO-256 DECODER – MLPX(76) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-8 16-TO-4/256-TO-8 ENCODER – DMPX(77) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-9 7-SEGMENT DECODER – SDEC(78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-10 ASCII CONVERT – ASC(86) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-11 ASCII-TO-HEXADECIMAL – HEX(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-12 SCALING – SCL(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-13 COLUMN TO LINE – LINE(63) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-14 LINE TO COLUMN – COLM(64) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-15 2’S COMPLEMENT – NEG(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-18-16 DOUBLE 2’S COMPLEMENT – NEGL(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19 BCD Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-1 INCREMENT – INC(38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-2 DECREMENT – DEC(39) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-3 SET CARRY – STC(40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-4 CLEAR CARRY – CLC(41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-5 BCD ADD – ADD(30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-6 DOUBLE BCD ADD – ADDL(54) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-7 BCD SUBTRACT – SUB(31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-8 DOUBLE BCD SUBTRACT – SUBL(55) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-9 BCD MULTIPLY – MUL(32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-10 DOUBLE BCD MULTIPLY – MULL(56) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-11 BCD DIVIDE – DIV(33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-12 DOUBLE BCD DIVIDE – DIVL(57) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-13 FLOATING POINT DIVIDE – FDIV(79) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-19-14 SQUARE ROOT – ROOT(72) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20 Binary Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20-1 BINARY ADD – ADB(50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20-2 BINARY SUBTRACT – SBB(51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20-3 BINARY MULTIPLY – MLB(52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20-4 BINARY DIVIDE – DVB(53) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20-5 DOUBLE BINARY ADD – ADBL(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20-6 DOUBLE BINARY SUBTRACT – SBBL(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20-7 SIGNED BINARY MULTIPLY – MBS(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20-8 DOUBLE SIGNED BINARY MULTIPLY – MBSL(––) . . . . . . . . . . . . . . . . . . . . . . . . .
5-20-9 SIGNED BINARY DIVIDE – DBS(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-20-10 DOUBLE SIGNED BINARY DIVIDE – DBSL(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5-21 Special Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-21-1 FIND MAXIMUM – MAX(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-21-2 FIND MINIMUM – MIN(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-21-3 AVERAGE VALUE – AVG(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-21-4 SUM – SUM(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-21-5 ARITHMETIC PROCESS – APR(69) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-21-6 PID CONTROL – PID(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-22 Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-22-1 COMPLEMENT – COM(29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-22-2 LOGICAL AND – ANDW(34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-22-3 LOGICAL OR – ORW(35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-22-4 EXCLUSIVE OR – XORW(36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-22-5 EXCLUSIVE NOR – XNRW(37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-23 Subroutines and Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-23-1 Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-23-2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-23-3 SUBROUTINE ENTER – SBS(91) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-23-4 SUBROUTINE DEFINE and RETURN – SBN(92)/RET(93) . . . . . . . . . . . . . . . . . . . . .
5-23-5 MACRO – MCRO(99) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-23-6 INTERRUPT CONTROL – INT(89) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-24 Step Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-24-1 STEP DEFINE and STEP START–STEP(08)/SNXT(09) . . . . . . . . . . . . . . . . . . . . . . . .
5-25 Special Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5-25-1 FAILURE ALARM – FAL(06) and
SEVERE FAILURE ALARM – FALS(07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5-25-2 CYCLE TIME – SCAN(18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-3 TRACE MEMORY SAMPLING – TRSM(45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-4 MESSAGE DISPLAY – MSG(46) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-5 LONG MESSAGE – LMSG(47) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-6 TERMINAL MODE – TERM(48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-7 WATCHDOG TIMER REFRESH – WDT(94) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-8 I/O REFRESH – IORF(97) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-9 GROUP-2 HIGH-DENSITY I/O REFRESH – MPRF(61) . . . . . . . . . . . . . . . . . . . . . . .
5-25-10 BIT COUNTER – BCNT(67) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-11 FRAME CHECKSUM – FCS(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-12 FAILURE POINT DETECTION – FPD(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-13 DATA SEARCH – SRCH(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-14 EXPANSION DM READ – XDMR(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-15 INDIRECT EM ADDRESSING – IEMS(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-25-16 SELECT EM BANK – EMBC(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-26 Network Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-26-1 NETWORK SEND – SEND(90) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-26-2 NETWORK RECEIVE – RECV(98) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-26-3 About Network Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-27 Serial Communications Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-27-1 RECEIVE – RXD(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-27-2 TRANSMIT – TXD(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-27-3 CHANGE RS-232C SETUP – STUP(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-27-4 PROTOCOL MACRO – PMCR(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-28 Advanced I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-28-1 7-SEGMENT DISPLAY OUTPUT – 7SEG(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-28-2 DIGITAL SWITCH INPUT – DSW(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-28-3 HEXADECIMAL KEY INPUT – HKY(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-28-4 TEN KEY INPUT – TKY(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-28-5 MATRIX INPUT – MTR(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-29 Special I/O Unit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-29-1 SPECIAL I/O UNIT READ – IORD(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-29-2 SPECIAL I/O UNIT WRITE – IOWR(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-29-3 PCMCIA CARD MACRO – CMCR(––) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
137
Data Areas, Definer Values, and Flags
Section 5-3
5-1 Notation
In the remainder of this manual, all instructions will be referred to by their mne-
monics. For example, the Output instruction will be called OUT; the AND Load
instruction, AND LD. If you’re not sure of the instruction a mnemonic is used for,
refer to Appendix B Programming Instructions.
If an instruction is assigned a function code, it will be given in parentheses after
the mnemonic. These function codes, which are 2-digit decimal numbers, are
used to input most instructions into the CPU Unit and are described briefly below
and in more detail in 4-7 Inputting, Modifying, and Checking the Program. A table
of instructions listed in order of function codes, is also provided in Appendix B.
An @ before a mnemonic indicates the differentiated version of that instruction.
Differentiated instructions are explained in Section 5-4.
5-2 Instruction Format
Most instructions have at least one or more operands associated with them. Op-
erands indicate or provide the data on which an instruction is to be performed.
These are sometimes input as the actual numeric values (i.e., as constants), but
are usually the addresses of data area words or bits that contain the data to be
used. A bit whose address is designated as an operand is called an operand bit;
a word whose address is designated as an operand is called an operand word. In
some instructions, the word address designated in an instruction indicates the
first of multiple words containing the desired data.
Each instruction requires one or more words in Program Memory. The first word
is the instruction word, which specifies the instruction and contains any definers
(described below) or operand bits required by the instruction. Other operands
required by the instruction are contained in following words, one operand per
word. Some instructions require up to four words.
A definer is an operand associated with an instruction and contained in the same
word as the instruction itself. These operands define the instruction rather than
telling what data it is to use. Examples of definers are TC numbers, which are
used in timer and counter instructions to create timers and counters, as well as
jump numbers (which define which Jump instruction is paired with which Jump
End instruction). Bit operands are also contained in the same word as the
instruction itself, although these are not considered definers.
5-3 Data Areas, Definer Values, and Flags
In this section, each instruction description includes its ladder diagram symbol,
the data areas that can be used by its operands, and the values that can be used
as definers. Details for the data areas are also specified by the operand names
and the type of data required for each operand (i.e., word or bit and, for words,
hexadecimal or BCD).
Not all addresses in the specified data areas are necessarily allowed for an oper-
and, e.g., if an operand requires two words, the last word in a data area cannot
be designated as the first word of the operand because all words for a single op-
erand must be within the same data area. Also, not all words in the SR and DM
areas are writeable as operands (see Section 3 Memory Areas for details.) Oth-
er specific limitations are given in a Limitations subsection. Refer to Section 3
Memory Areas for addressing conventions and the addresses of flags and con-
trol bits.
138
Data Areas, Definer Values, and Flags
Section 5-3
Caution The IR and SR areas are considered as separate data areas. If an operand has
access to one area, it doesn’t necessarily mean that the same operand will have
access to the other area. The border between the IR and SR areas can, howev-
er, be crossed for a single operand, i.e., the last bit in the IR area may be speci-
fied for an operand that requires more than one word as long as the SR area is
also allowed for that operand.
!
The Flags subsection lists flags that are affected by execution of an instruction.
These flags include the following SR area flags.
Abbreviation
ER
Name
Instruction Execution Error Flag
Carry Flag
Bit
25503
25504
25505
25506
25507
25402
25404
25405
CY
GR
EQ
LE
N
Greater Than Flag
Equals Flag
Less Than Flag
Negative Flag
OF
UF
Overflow Flag
Underflow Flag
ER is the flag most commonly used for monitoring an instruction’s execution.
When ER goes ON, it indicates that an error has occurred in attempting to
execute the current instruction. The Flags subsection of each instruction lists
possible reasons for ER being ON. ER will turn ON if operands are not entered
correctly. Instructions are not executed when ER is ON. A table of instructions
and the flags they affect is provided in Appendix C Error and Arithmetic Flag Op-
eration.
Indirect Addressing
When the DM area is specified for an operand, an indirect address can be used.
Indirect DM addressing is specified by placing an asterisk before the DM: ꢀDM.
When an indirect DM address is specified, the designated DM word will contain
the address of the DM word that contains the data that will be used as the operand
of the instruction. If, for example, ꢀDM 0001 was designated as the first operand
and LR 00 as the second operand of MOV(21), the contents of DM 0001 was
1111, and DM 1111 contained 5555, the value 5555 would be moved to LR 00.
Word
Content
4C59
1111
MOV(21)
ꢀDM 0001
LR 00
DM 0000
DM 0001
DM 0002
Indirect
address
Indicates
DM 1111.
F35A
DM 1111
DM 1113
DM 1114
5555
2506
D541
5555 moved
to LR 00.
When using indirect addressing, the address of the desired word must be in BCD
and it must specify a word within the DM area. In the above example, the content
of ꢀDM 0000 would have to be in BCD between 0000 and 6655.
The IEMS(––) instruction can be used to change the destination of ꢀDM from the
DM area to one of the banks in the EM area. Refer to 5-25-15 INDIRECT EM
ADDRESSING – IEMS(––) for details.
Designating Constants
Although data area addresses are most often given as operands, many oper-
ands and all definers are input as constants. The available value range for a giv-
en definer or operand depends on the particular instruction that uses it.
Constants must also be entered in the form required by the instruction, i.e., in
BCD or in hexadecimal.
139
Differentiated Instructions
Section 5-4
5-4 Differentiated Instructions
Most instructions are provided in both differentiated and non-differentiated
forms. Differentiated instructions are distinguished by an @ in front of the
instruction mnemonic.
A non-differentiated instruction is executed each time it is cycled as long as its
execution condition is ON. A differentiated instruction is executed only once af-
ter its execution condition goes from OFF to ON. If the execution condition has
not changed or has changed from ON to OFF since the last time the instruction
was cycled, the instruction will not be executed. The following two examples
show how this works with MOV(21) and @MOV(21), which are used to move the
data in the address designated by the first operand to the address designated by
the second operand.
00000
Address Instruction
Operands
00000
MOV(21)
HR 10
00000
00001
LD
MOV(21)
DM 0000
Diagram A
Diagram B
HR
DM
10
0000
00000
Address Instruction
Operands
@MOV(21)
HR 10
00000
00001
LD
00000
@MOV(21)
DM 0000
HR
DM
10
0000
In diagram A, the non-differentiated MOV(21) will move the content of HR 10 to
DM 0000 whenever it is cycled with 00000. If the cycle time is 80 ms and 00000
remains ON for 2.0 seconds, this move operation will be performed 25 times and
only the last value moved to DM 0000 will be preserved there.
In diagram B, the differentiated @MOV(21) will move the content of HR 10 to DM
0000 only once after 00000 goes ON. Even if 00000 remains ON for 2.0 seconds
with the same 80 ms cycle time, the move operation will be executed only once
during the first cycle in which 00000 has changed from OFF to ON. Because the
content of HR 10 could very well change during the 2 seconds while 00000 is
ON, the final content of DM 0000 after the 2 seconds could be different depend-
ing on whether MOV(21) or @MOV(21) was used.
All operands, ladder diagram symbols, and other specifications for instructions
are the same regardless of whether the differentiated or non-differentiated form
of an instruction is used. When inputting, the same function codes are also used,
but NOT is input after the function code to designate the differentiated form of an
instruction. Most, but not all, instructions have differentiated forms.
Refer to 5-10 INTERLOCK and INTERLOCK CLEAR – IL(02) and IL(03) for the
effects of interlocks on differentiated instructions.
The C200HX/HG/HE PCs also provide differentiation instructions: DIFU(13)
and DIFD(14). DIFU(13) operates the same as a differentiated instruction, but is
used to turn ON a bit for one cycle. DIFD(14) also turns ON a bit for one cycle, but
does it when the execution condition has changed from ON to OFF. Refer to
5-9-2 DIFFERENTIATE UP and DOWN - DIFU(13) and DIFD(14) for details.
Note Do not use SR 25313 and SR 25315 for differentiated instructions. These bits
never change status and will not trigger differentiated instructions.
140
Expansion Instructions
Section 5-5
5-5 Expansion Instructions
The C200HX/HG/HE PCs have more instructions that require function codes
(121) than function codes (100), so some instructions do not have fixed function
codes. These instructions, called expansion instructions, are listed in the follow-
ing table. Default function codes are given for the instructions that have them.
An expansion instruction can be assigned one of 18 function codes using the
Programming Console’s Expansion Instruction Function Code Assignments op-
eration. The 18 function codes are: 17, 18, 19, 47, 48, 60 to 69, 87, 88, and 89.
Refer to 7-2-14 Expansion Instruction Function Code Assignments for details on
assigning function codes.
Code
Mnemonic
(@)ASFT
(@)SCAN
Name
ASYNCHRONOUS SHIFT REGISTER
CYCLE TIME
Page
178
301
192
304
305
196
307
189
224
225
207
208
308
197
263
165
200
287
336
249
259
191
202
203
353
255
256
339
317
308
310
219
343
316
350
351
257
253
254
17
18
19
47
48
60
61
62
63
64
65
66
67
68
69
87
88
89
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
(@)MCMP MULTI-WORD COMPARE
(@)LMSG 32-CHARACTER MESSAGE
(@)TERM TERMINAL MODE
CMPL
DOUBLE COMPARE
(@)MPRF GROUP-2 HIGH-DENSITY I/O REFRESH
(@)XFRB
(@)LINE
TRANSFER BITS
COLUMN TO LINE
(@)COLM LINE TO COLUMN
(@)SEC
(@)HMS
(@)BCNT
HOURS TO SECONDS
SECONDS TO HOURS
BIT COUNTER
(@)BCMP BLOCK COMPARE
(@)APR
TTIM
ARITHMETIC PROCESS
TOTALIZING TIMER
ZCP
AREA RANGE COMPARE
INTERRUPT CONTROL
7-SEGMENT DISPLAY OUTPUT
DOUBLE BINARY ADD
(@)INT
7SEG
(@)ADBL
AVG
AVERAGE VALUE
(@)BXF2
CPS
EM BANK TRANSFER
SIGNED BINARY COMPARE
DOUBLE SIGNED BINARY COMPARE
PCMCIA CARD MACRO
SIGNED BINARY DIVIDE
DOUBLE SIGNED BINARY DIVIDE
DIGITAL SWITCH INPUT
SELECT EM BANK
CPSL
CMCR
(@)DBS
(@)DBSL
DSW
@EMBC
(@)FCS
FPD
FCS CALCULATE
FAILURE POINT DETECT
ASCII-TO-HEXADECIMAL
HEXADECIMAL KEY INPUT
INDIRECT EM ADDRESSING
SPECIAL I/O UNIT READ
SPECIAL I/O UNIT WRITE
FIND MAXIMUM
(@)HEX
HKY
(@)IEMS
(@)IORD
(@)IOWR
(@)MAX
(@)MBS
(@)MBSL
SIGNED BINARY MULTIPLY
DOUBLE SIGNED BINARY MULTIPLY
141
Coding Right-hand Instructions
Section 5-6
Code
Mnemonic
(@)MIN
MTR
Name
Page
258
348
226
227
266
335
329
251
222
314
333
261
346
331
315
190
201
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
FIND MINIMUM
MATRIX INPUT
2’S COMPLEMENT
(@)NEG
(@)NEGL
PID
DOUBLE 2’S COMPLEMENT
PID CONTROL
(@)PMCR PROTOCOL MACRO
(@)RXD
(@)SBBL
(@)SCL
RECEIVE
DOUBLE BINARY SUBTRACT
SCALING
(@)SRCH DATA SEARCH
(@)STUP
(@)SUM
(@)TKY
(@)TXD
CHANGE RS-232C SETUP
SUM CALCULATE
TEN KEY INPUT
TRANSMIT
(@)XDMR EXPANSION DM READ
(@)XFR2
ZCPL
EM BLOCK TRANSFER
DOUBLE AREA RANGE COMPARE
5-6 Coding Right-hand Instructions
Writing mnemonic code for ladder instructions is described in Section 4 Writing
and Inputting the Program. Converting the information in the ladder diagram
symbol for all other instructions follows the same pattern, as described below,
and is not specified for each instruction individually.
The first word of any instruction defines the instruction and provides any defin-
ers. If the instruction requires only a signal bit operand with no definer, the bit
operand is also placed on the same line as the mnemonic. All other operands are
placed on lines after the instruction line, one operand per line and in the same
order as they appear in the ladder symbol for the instruction.
The address and instruction columns of the mnemonic code table are filled in for
the instruction word only. For all other lines, the left two columns are left blank. If
the instruction requires no definer or bit operand, the data column is left blank for
first line. It is a good idea to cross through any blank data column spaces (for all
instruction words that do not require data) so that the data column can be quickly
scanned to see if any addresses have been left out.
If an IR or SR address is used in the data column, the left side of the column is left
blank. If any other data area is used, the data area abbreviation is placed on the
left side and the address is place on the right side. If a constant to be input, the
number symbol (#) is placed on the left side of the data column and the number
to be input is placed on the right side. Any numbers input as definers in the
instruction word do not require the number symbol on the right side. TC bits,
once defined as a timer or counter, take a TIM (timer) or CNT (counter) prefix.
When coding an instruction that has a function code, be sure to write in the func-
tion code, which will be necessary when inputting the instruction via the Pro-
gramming Console. Also be sure to designate the differentiated instruction with
the @ symbol.
142
Coding Right-hand Instructions
Section 5-6
The following diagram and corresponding mnemonic code illustrates the points
described above.
Address Instruction
Data
00000
00001
DIFU(13) 22500
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
LD
00000
00001
00002
22500
00100
00200
01001
01002
6300
––
00002
AND
OR
00100
00200
22500
DIFU(13)
LD
BCNT(67)
#0001
01001 01002 LR 6300
AND NOT
LD
004
HR 00
AND NOT
AND NOT
OR LD
AND
LR
00005
TIM 000
#0150
22500
––
BCNT(67)
TIM 000
#
0001
004
MOV(21)
HR 00
HR
00
LR 00
00012
00013
LD
00005
000
TIM
HR 0015
00500
#
0150
000
00014
00015
LD
TIM
MOV(21)
––
HR
LR
HR
00
00
00016
00017
LD
0015
00500
OUT NOT
143
Coding Right-hand Instructions
Section 5-6
Multiple Instruction Lines
If a right-hand instruction requires multiple instruction lines (such as KEEP(11)),
all of the lines for the instruction are entered before the right-hand instruction.
Each of the lines for the instruction is coded, starting with LD or LD NOT, to form
‘logic blocks’ that are combined by the right-hand instruction. An example of this
for SFT(10) is shown below.
Address Instruction
Data
00000
00100
00001
00200
I
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
LD
00000
00001
00002
00100
00200
01001
01002
6300
––
SFT(10)
HR 00
HR 00
00002
P
R
AND
22500
LD
LD
01001 01002 LR 6300
HR 0015
AND NOT
LD
00500
AND NOT
AND NOT
OR LD
AND
LR
22500
––
SFT(10)
HR
HR
HR
00
00
00011
00012
LD
0015
00500
OUT NOT
END(01)
When you have finished coding the program, make sure you have placed
END(01) at the last address.
144
Instruction Set Lists
Section 5-7
5-7 Instruction Set Lists
This section provides tables of the instructions available in the C200HX/HG/HE.
The first table can be used to find instructions by function code. The second table
can be used to find instruction by mnemonic. In both tables, the @ symbol indi-
cates instructions with differentiated variations.
Note Refer to 5-5 Expansion Instructions for a list of the expansion instructions.
5-7-1 Function Codes
The following table lists the instructions that have fixed function codes. Each
instruction is listed by mnemonic and by instruction name. Use the numbers in
the leftmost column as the left digit and the number in the column heading as the
right digit of the function code.
Right digit
Left
digit
0
1
2
3
4
5
6
7
8
9
NOP
NO
OPERATION
END
END
IL
ILC
INTERLOCK
CLEAR
JMP
JUMP
JME
JUMP END
(@) FAL
FALS
STEP
STEP
DEFINE
SNXT
STEP START
0
1
INTERLOCK
FAILURE
ALARM AND
RESET
SEVERE
FAILURE
ALARM
SFT
SHIFT
REGISTER
KEEP
KEEP
CNTR
REVERS-
IBLE
DIFU
DIFFER-
ENTIATE UP
DIFD
TIMH
(@) WSFT
WORD
SHIFT
(@) ASFT
(@) SCAN
CYCLE TIME
(@) MCMP
MULTI-
WORD
DIFFER-
ENTIATE
DOWN
HIGH-
SPEED
TIMER
ASYNCHRO-
NOUS SHIFT
REGISTER
COUNTER
COMPARE
CMP
COMPARE
(@) MOV
MOVE
(@) MVN
MOVE NOT
(@) BIN
BCD TO
BINARY
(@) BCD
BINARY TO
BCD
(@) ASL
SHIFT LEFT
(@) ASR
SHIFT
RIGHT
(@) ROL
ROTATE
LEFT
(@) ROR
ROTATE
RIGHT
(@) COM
COMPLE-
MENT
2
3
4
(@) ADD
BCD ADD
(@) SUB
BCD
SUBTRACT
(@) MUL
BCD
MULTIPLY
(@) DIV
BCD
DIVIDE
(@) ANDW
LOGICAL
AND
(@) ORW
LOGICAL OR EXCLUSIVE
OR
(@) XORW
(@) XNRW
EXCLUSIVE
NOR
(@) INC
INCREMENT
(@) DEC
DECRE-
MENT
(@) STC
SET CARRY
(@) CLC
CLEAR
CARRY
---
---
---
TRSM
(@) MSG
MESSAGE
DISPLAY
(@) LMSG
LONG MES-
SAGE
(@) TERM
TERMINAL
MODE
---
TRACE
MEMORY
SAMPLE
(@) ADB
BINARY ADD
(@) SBB
BINARY
SUBTRACT
(@) MLB
BINARY
MULTIPLY
(@) DVB
BINARY
DIVIDE
(@) ADDL
DOUBLE
BCD ADD
(@) SUBL
DOUBLE
BCD
(@) MULL
DOUBLE
BCD
(@) DIVL
DOUBLE
BCD
(@) BINL
DOUBLE
BCD-TO-
DOUBLE
BINARY
(@) BCDL
DOUBLE
BINARY-TO-
DOUBLE
BCD
5
6
SUBTRACT
MULTIPLY
DIVIDE
CMPL
DOUBLE
COMPARE
(@) MPRF
GROUP-2
HIGH-DENSI- BITS
TY I/O RE-
(@) XFRB
TRANSFER
(@) LINE
COLUMN TO
LINE
(@) COLM
LINE TO
COLUMN
(@) SEC
HOURS-TO-
SECONDS
(@) HMS
SECONDS-
TO-HOURS
(@) BCNT
BIT COUNT-
ER
(@) BCMP
BLOCK
COMPARE
(@) APR
ARITHMETIC
PROCESS
FRESH
(@) XFER
BLOCK
TRANSFER
(@) BSET
BLOCK SET
(@) ROOT
SQUARE
ROOT
(@) XCHG
DATA
EXCHANGE
(@) SLD
ONE DIGIT
SHIFT LEFT
(@) SRD
ONE DIGIT
SHIFT
(@) MLPX
4-TO-16/
8-TO-256
DECODER
(@) DMPX
16-TO-4/
256-TO-8
ENCODER
(@) SDEC
7-SEGMENT
DECODER
(@) FDIV
FLOATING
POINT
7
8
9
RIGHT
DIVIDE
(@) DIST
SINGLE
WORD
(@) COLL
DATA
COLLECT
(@) MOVB
MOVE BIT
(@) MOVD
MOVE DIGIT
(@) SFTR
REVERS-
IBLE SHIFT
REGISTER
(@) TCMP
TABLE
COMPARE
(@) ASC
ASCII
CONVERT
TTIM
TOTALIZING
COUNTER
ZCP
AREA
RANGE
COMPARE
(@) INT
INTERRUPT
CONTROL
DISTRIBUTE
(@) SEND
NETWORK
SEND
(@) SBS
SUBROU-
TINE
SBN
SUBROU-
TINE
RET
SUBROU-
TINE
(@) WDT
WATCHDOG
TIMER
---
---
(@) IORF
I/O
REFRESH
(@) RECV
NETWORK
RECEIVE
(@) MCRO
MACRO
ENTRY
DEFINE
RETURN
REFRESH
5-7-2 Alphabetic List by Mnemonic
Mnemonic
7SEG
Code
––
Words
Name
Page
4
7-SEGMENT DISPLAY OUTPUT
BINARY ADD
336
ADB (@)
ADBL (@)
ADD (@)
ADDL (@)
AND
50
4
4
4
4
1
1
1
4
4
4
243
249
229
230
149
150
149
276
263
218
––
DOUBLE BINARY ADD
BCD ADD
30
54
DOUBLE BCD ADD
AND
None
None
None
34
AND LD
AND LOAD
AND NOT
ANDW (@)
APR (@)
ASC (@)
AND NOT
LOGICAL AND
69
ARITHMETIC PROCESS
ASCII CONVERT
86
145
Instruction Set Lists
Section 5-7
Mnemonic
ASFT(@)
ASL (@)
ASR (@)
AVG (@)
BCD (@)
BCDL (@)
BCMP (@)
BCNT (@)
BIN (@)
BINL (@)
BSET (@)
BXF2 (@)
CLC (@)
CMCR (@)
CMP
Code
17
Words
Name
ASYNCHRONOUS SHIFT REGISTER
ARITHMETIC SHIFT LEFT
ARITHMETIC SHIFT RIGHT
AVERAGE VALUE
Page
178
175
175
259
205
206
197
308
204
205
181
190
229
353
193
196
166
169
185
225
275
202
203
255
256
228
151
151
183
236
237
212
339
248
317
158
300
300
308
238
310
219
343
208
316
155
155
228
287
4
25
26
––
24
59
68
67
23
58
71
––
41
––
20
60
None
12
81
64
29
––
––
––
––
39
14
13
80
33
57
77
––
53
––
01
06
07
––
79
––
––
––
66
––
02
03
38
89
2
2
4
3
3
4
4
3
3
4
4
1
4
3
4
2
3
4
4
2
4
4
4
4
2
2
2
4
4
4
4
4
4
2
1
2
2
4
4
4
4
4
4
2
1
1
2
4
BINARY TO BCD
DOUBLE BINARY-TO-DOUBLE BCD
BLOCK COMPARE
BIT COUNTER
BCD-TO-BINARY
DOUBLE BCD-TO-DOUBLE BINARY
BLOCK SET
EM BLOCK TRANSFER
CLEAR CARRY
PCMCIA CARD MACRO
COMPARE
CMPL
DOUBLE COMPARE
COUNTER
CNT
CNTR
REVERSIBLE COUNTER
DATA COLLECT
COLL (@)
COLM(@)
COM (@)
CPS
LINE TO COLUMN
COMPLEMENT
SIGNED BINARY COMPARE
DOUBLE SIGNED BINARY COMPARE
SIGNED BINARY DIVIDE
DOUBLE SIGNED BINARY DIVIDE
BCD DECREMENT
CPSL
DBS (@)
DBSL (@)
DEC (@)
DIFD
DIFFERENTIATE DOWN
DIFFERENTIATE UP
SINGLE WORD DISTRIBUTE
BCD DIVIDE
DIFU
DIST (@)
DIV (@)
DIVL (@)
DMPX (@)
DSW
DOUBLE BCD DIVIDE
16-TO-4/256-TO-8 ENCODER
DIGITAL SWITCH
DVB (@)
EMBC (@)
END
BINARY DIVIDE
SELECT EM BANK
END
FAL (@)
FALS
FAILURE ALARM AND RESET
SEVERE FAILURE ALARM
FCS CALCULATE
FCS (@)
FDIV (@)
FPD
FLOATING POINT DIVIDE
FAILURE POINT DETECT
ASCII-TO-HEXADECIMAL
HEXADECIMAL KEY INPUT
SECONDS TO HOURS
INDIRECT EM ADDRESSING
INTERLOCK
HEX (@)
HKY
HMS (@)
IEMS (@)
IL
ILC
INTERLOCK CLEAR
INCREMENT
INC (@)
INT (@)
INTERRUPT CONTROL
146
Instruction Set Lists
Section 5-7
Mnemonic
IORD (@)
IORF (@)
IOWR (@)
JME
Code
––
Words
Name
Page
350
306
351
157
157
154
149
149
224
304
257
253
254
192
285
258
248
209
180
187
188
307
303
348
235
236
180
226
227
158
149
150
149
277
150
150
266
335
323
284
176
241
176
153
329
245
251
284
283
4
SPECIAL I/O UNIT READ
I/O REFRESH
97
3
4
2
2
2
1
1
4
4
4
4
4
4
4
4
4
4
3
4
4
4
2
4
4
4
3
4
4
1
1
1
1
4
2
2
4
4
4
1
2
3
2
2
4
4
4
2
2
––
SPECIAL I/O UNIT WRITE
JUMP END
05
JMP
04
JUMP
KEEP
11
KEEP
LD
None
None
63
LOAD
LD NOT
LINE (@)
LMSG (@)
MAX (@)
MBS (@)
MBSL (@)
MCMP (@)
MCRO (@)
MIN (@)
MLB (@)
MLPX (@)
MOV (@)
MOVB (@)
MOVD (@)
MPRF (@)
MSG (@)
MTR
LOAD NOT
COLUMN TO LINE
32-CHARACTER MESSAGE
FIND MAXIMUM
SIGNED BINARY MULTIPLY
47
––
––
––
DOUBLE SIGNED BINARY MULTIPLY
MULTI-WORD COMPARE
MACRO
19
99
––
FIND MINIMUM
52
BINARY MULTIPLY
4-TO-16/8-TO-256 DECODER
MOVE
76
21
82
MOVE BIT
83
MOVE DIGIT
61
GROUP-2 HIGH-DENSITY I/O REFRESH
MESSAGE
46
––
MATRIX INPUT
MUL (@)
MULL (@)
MVN (@)
NEG
32
BCD MULTIPLY
56
DOUBLE BCD MULTIPLY
MOVE NOT
22
––
2’S COMPLEMENT
DOUBLE 2’S COMPLEMENT
NO OPERATION
OR
NEGL
––
NOP
00
OR
None
None
None
35
OR LD
OR LOAD
OR NOT
ORW (@)
OUT
OR NOT
LOGICAL OR
None
None
––
OUTPUT
OUT NOT
PID (@)
PMCR (@)
RECV (@)
RET
OUTPUT NOT
PID CONTROL
––
PROTOCOL MACRO
NETWORK RECEIVE
SUBROUTINE RETURN
ROTATE LEFT
98
93
ROL (@)
ROOT (@)
ROR (@)
RSET
27
72
SQUARE ROOT
ROTATE RIGHT
RESET
28
None
––
RXD(@)
SBB (@)
SBBL (@)
SBN
RECEIVE
51
BINARY SUBTRACT
DOUBLE BINARY SUBTRACT
SUBROUTINE DEFINE
SUBROUTINE ENTRY
––
92
SBS (@)
91
147
Instruction Set Lists
Section 5-7
Mnemonic
SCAN (@)
SCL (@)
SDEC (@)
SEC (@)
SEND (@)
SET
Code
18
Words
Name
Page
301
222
215
207
318
153
171
173
177
291
314
177
229
291
333
231
233
261
199
305
159
164
346
302
165
331
306
178
183
315
182
190
189
279
278
200
201
4
CYCLE TIME
––
78
65
90
None
10
84
74
09
––
75
40
08
––
31
55
––
85
48
None
15
––
45
87
––
94
16
73
––
70
––
62
37
36
88
––
4
4
4
4
2
3
4
3
2
4
3
1
2
2
4
4
4
4
4
2
3
4
1
4
4
2
3
3
4
4
4
4
4
4
4
4
SCALING
7-SEGMENT DECODER
HOURS TO SECONDS
NETWORK SEND
SET
SFT
SHIFT REGISTER
SFTR (@)
SLD (@)
SNXT
REVERSIBLE SHIFT REGISTER
ONE DIGIT SHIFT LEFT
STEP START
SRCH (@)
SRD (@)
STC (@)
STEP
DATA SEARCH
ONE DIGIT SHIFT RIGHT
SET CARRY
STEP DEFINE
STUP (@)
SUB (@)
SUBL (@)
SUM (@)
TCMP (@)
TERM (@)
TIM
CHANGE RS-232C SETUP
BCD SUBTRACT
DOUBLE BCD SUBTRACT
SUM CALCULATION
TABLE COMPARE
TERMINAL MODE
TIMER
TIMH
HIGH-SPEED TIMER
TEN KEY INPUT
TKY (@)
TRSM
TRACE MEMORY SAMPLE
TOTALIZING TIMER
TRANSMIT
TTIM
TXD (@)
WDT (@)
WSFT (@)
XCHG (@)
XDMR (@)
XFER (@)
XFR2 (@)
XFRB (@)
XNRW (@)
XORW (@)
ZCP
WATCHDOG TIMER REFRESH
WORD SHIFT
DATA EXCHANGE
EXPANSION DM READ
BLOCK TRANSFER
EM BLOCK TRANSFER
TRANSFER BITS
EXCLUSIVE NOR
EXCLUSIVE OR
AREA RANGE COMPARE
DOUBLE AREA RANGE COMPARE
ZCPL
148
Ladder Diagram Instructions
Section 5-8
5-8 Ladder Diagram Instructions
Ladder Diagram instructions include Ladder instructions and Logic Block
instructions and correspond to the conditions on the ladder diagram. Logic block
instructions are used to relate more complex parts.
5-8-1 LOAD, LOAD NOT, AND, AND NOT, OR, and OR NOT
Ladder Symbols
Operand Data Areas
B: Bit
B
LOAD – LD
IR, SR, AR, HR, TC, LR, TR
B: Bit
B
B
B
LOAD NOT – LD NOT
IR, SR, AR, HR, TC, LR
B: Bit
AND – AND
IR, SR, AR, HR, TC, LR
B: Bit
AND NOT – AND NOT
IR, SR, AR, HR, TC, LR
B: Bit
OR – OR
B
B
IR, SR, AR, HR, TC, LR
B: Bit
OR NOT – OR NOT
Limitations
IR, SR, AR, HR, TC, LR
There is no limit to the number of any of these instructions, or restrictions in the
order in which they must be used, as long as the memory capacity of the PC is
not exceeded.
Description
These six basic instructions correspond to the conditions on a ladder diagram.
As described in Section 4 Writing and Inputting the Program, the status of the
bits assigned to each instruction determines the execution conditions for all oth-
er instructions. Each of these instructions and each bit address can be used as
many times as required. Each can be used in as many of these instructions as
required.
The status of the bit operand (B) assigned to LD or LD NOT determines the first
execution condition. AND takes the logical AND between the execution condi-
tion and the status of its bit operand; AND NOT, the logical AND between the
execution condition and the inverse of the status of its bit operand. OR takes the
logical OR between the execution condition and the status of its bit operand; OR
NOT, the logical OR between the execution condition and the inverse of the sta-
tus of its bit operand. The ladder symbol for loading TR bits is different from that
shown above. Refer to 4-4-3 Ladder Instructions for details.
Flags
There are no flags affected by these instructions.
149
Bit Control Instructions
Section 5-9
5-8-2 AND LOAD and OR LOAD
AND LOAD – AND LD
00000
00001
00002
00003
Ladder Symbol
OR LOAD – OR LD
00000
00002
00001
Ladder Symbol
00003
Description
When instructions are combined into blocks that cannot be logically combined
using only OR and AND operations, AND LD and OR LD are used. Whereas
AND and OR operations logically combine a bit status and an execution condi-
tion, AND LD and OR LD logically combine two execution conditions, the current
one and the last unused one.
In order to draw ladder diagrams, it is not necessary to use AND LD and OR LD
instructions, nor are they necessary when inputting ladder diagrams directly, as
is possible from SSS. They are required, however, to convert the program to and
input it in mnemonic form. The procedures for these, limitations for different pro-
cedures, and examples are provided in 4-7 Inputting, Modifying, and Checking
the Program.
In order to reduce the number of programming instructions required, a basic un-
derstanding of logic block instructions is required. For an introduction to logic
blocks, refer to 4-4-6 Logic Block Instructions.
Flags
There are no flags affected by these instructions.
5-9 Bit Control Instructions
There are five instructions that can be used generally to control individual bit sta-
tus. These are OUT, OUT NOT, DIFU(13), DIFD(14), and KEEP(11). These
instructions are used to turn bits ON and OFF in different ways.
5-9-1 OUTPUT and OUTPUT NOT – OUT and OUT NOT
OUTPUT – OUT
Ladder Symbol
Ladder Symbol
Operand Data Areas
B: Bit
B
B
IR, SR, AR, HR, TC, LR, TR
OUTPUT NOT – OUT NOT
Operand Data Areas
B: Bit
IR, SR, AR, HR, TC, LR
Limitations
Description
Any output bit can generally be used in only one instruction that controls its sta-
tus. Refer to 3-3 IR Area for details.
OUT and OUT NOT are used to control the status of the designated bit according
to the execution condition.
150
Bit Control Instructions
Section 5-9
OUT turns ON the designated bit for an ON execution condition, and turns OFF
the designated bit for an OFF execution condition. With a TR bit, OUT appears at
a branching point rather than at the end of an instruction line. Refer to 4-7-7
Branching Instruction Lines for details.
OUT NOT turns ON the designated bit for a OFF execution condition, and turns
OFF the designated bit for an ON execution condition.
OUT and OUT NOT can be used to control execution by turning ON and OFF bits
that are assigned to conditions on the ladder diagram, thus determining execu-
tion conditions for other instructions. This is particularly helpful and allows a
complex set of conditions to be used to control the status of a single work bit, and
then that work bit can be used to control other instructions.
The length of time that a bit is ON or OFF can be controlled by combining the
OUT or OUT NOT with TIM. Refer to Examples under 5-14-1 TIMER – TIM for
details.
Flags
There are no flags affected by these instructions.
5-9-2 DIFFERENTIATE UP and DOWN – DIFU(13) and DIFD(14)
Ladder Symbols
Operand Data Areas
B: Bit
DIFU(13) B
IR, AR, HR, LR
B: Bit
DIFD(14) B
IR, AR, HR, LR
Limitations
Description
Any output bit can generally be used in only one instruction that controls its sta-
tus. Refer to 3-3 IR Area for details.
DIFU(13) and DIFD(14) are used to turn the designated bit ON for one cycle
only.
Whenever executed, DIFU(13) compares its current execution with the previous
execution condition. If the previous execution condition was OFF and the cur-
rent one is ON, DIFU(13) will turn ON the designated bit. If the previous execu-
tion condition was ON and the current execution condition is either ON or OFF,
DIFU(13) will either turn the designated bit OFF or leave it OFF (i.e., if the desig-
nated bit is already OFF). The designated bit will thus never be ON for longer
than one cycle, assuming it is executed each cycle (see Precautions, below).
Whenever executed, DIFD(14) compares its current execution with the previous
execution condition. If the previous execution condition was ON and the current
one is OFF, DIFD(14) will turn ON the designated bit. If the previous execution
condition was OFF and the current execution condition is either ON or OFF,
DIFD(14) will either turn the designated bit OFF or leave it OFF. The designated
bit will thus never be ON for longer than one cycle, assuming it is executed each
cycle (see Precautions, below).
These instructions are used when differentiated instructions (i.e., those prefixed
with an @) are not available and single-cycle execution of a particular instruction
is desired. They can also be used with non-differentiated forms of instructions
that have differentiated forms when their use will simplify programming. Exam-
ples of these are shown below.
Flags
There are no flags affected by these instructions.
151
Bit Control Instructions
Section 5-9
Precautions
DIFU(13) and DIFD(14) operation can be uncertain when the instructions are
programmed between IL and ILC, between JMP and JME, or in subroutines. Re-
fer to 5-10 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03), 5-11
JUMP and JUMP END – JMP(04) and JME(05), and 5-23 Subroutines and Inter-
rupt Control for details.
Example 1:
When There is No
Differentiated Instruction
In diagram A, below, whenever CMP(20) is executed with an ON execution
condition it will compare the contents of the two operand words (HR 10 and DM
0000) and set the arithmetic flags (GR, EQ, and LE) accordingly. If the execution
condition remains ON, flag status may be changed each cycle if the content of
one or both operands change. Diagram B, however, is an example of how
DIFU(13) can be used to ensure that CMP(20) is executed only once each time
the desired execution condition goes ON.
00000
Address Instruction
Operands
00000
CMP(20)
HR 10
00000
00001
LD
CMP(20)
DM 0000
Diagram A
HR
DM
10
0000
00000
22500
DIFU(13) 22500
Address Instruction
Operands
00000
00001
00002
00003
LD
00000
22500
22500
CMP(20)
HR 10
DIFU(13)
LD
DM 0000
Diagram B
CMP(20)
HR
DM
10
0000
Example 2:
Simplifying Programming
Although a differentiated form of MOV(21) is available, the following diagram
would be very complicated to draw using it because only one of the conditions
determining the execution condition for MOV(21) requires differentiated treat-
ment.
00000
Address Instruction
Operands
00000
DIFU(13) 22500
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
LD
DIFU(13)
LD
22500
22500
00001
00002
00003
---
22500
MOV(21)
HR 10
00001
00002
00003
LD
AND NOT
AND NOT
OR LD
LD
DM 0000
00004
00005
00004
00005
---
AND NOT
OR LD
MOV(21)
HR
DM
10
0000
152
Bit Control Instructions
Section 5-9
5-9-3 SET and RESET – SET and RSET
Ladder Symbols
Operand Data Areas
B: Bit
SET B
IR, SR, AR, HR, LR
B: Bit
RSET B
IR, SR, AR, HR, LR
Description
SET turns the operand bit ON when the execution condition is ON, and does not
affect the status of the operand bit when the execution condition is OFF. RSET
turns the operand bit OFF when the execution condition is ON, and does not af-
fect the status of the operand bit when the execution condition is OFF.
The operation of SET differs from that of OUT because the OUT instruction turns
the operand bit OFF when its execution condition is OFF. Likewise, RSET differs
from OUT NOT because OUT NOT turns the operand bit ON when its execution
condition is OFF.
Note The instructions SET and RESET are input as follows:
SET:
Operand
RESET:
Operand
Precautions
The status of operand bits for SET and RSET programmed between IL(02) and
ILC(03) or JMP(04) and JME(05) will not change when the interlock or jump
condition is met (i.e., when IL(02) or JMP(04) is executed with an OFF execution
condition).
Flags
There are no flags affected by these instructions.
Examples
The following examples demonstrate the difference between OUT and SET/
RSET. In the first example (Diagram A), IR 10000 will be turned ON or OFF
whenever IR 00000 goes ON or OFF.
In the second example (Diagram B), IR 10000 will be turned ON when IR 00001
goes ON and will remain ON (even if IR 00001 goes OFF) until IR 00002 goes
ON.
00000
Address Instruction
Operands
00000
10000
10000
00000
00001
LD
OUT
Diagram A
00001
00002
SET 10000
Address Instruction
Operands
00000
00001
00002
00003
LD
00001
10000
00002
10000
RSET 10000
SET
LD
Diagram B
RSET
153
Bit Control Instructions
Section 5-9
5-9-4 KEEP – KEEP(11)
Ladder Symbol
Operand Data Areas
S
R
KEEP(11)
B: Bit
B
IR, AR, HR, LR
Limitations
Description
Any output bit can generally be used in only one instruction that controls its sta-
tus. Refer to 3-3 IR Area for details.
KEEP(11) is used to maintain the status of the designated bit based on two
execution conditions. These execution conditions are labeled S and R. S is the
set input; R, the reset input. KEEP(11) operates like a latching relay that is set by
S and reset by R.
When S turns ON, the designated bit will go ON and stay ON until reset, regard-
less of whether S stays ON or goes OFF. When R turns ON, the designated bit
will go OFF and stay OFF until reset, regardless of whether R stays ON or goes
OFF. The relationship between execution conditions and KEEP(11) bit status is
shown below.
S execution condition
R execution condition
Status of B
KEEP(11) operates like the self-maintaining bit described in 4-8-3 Self-maintain-
ing Bits. The following two diagrams would function identically, though the one
using KEEP(11) requires one less instruction to program and would maintain
status even in an interlocked program section.
00002
00500
00003
Address Instruction
Operands
00002
00500
00000
00001
00002
00003
LD
OR
00500
00003
00500
AND NOT
OUT
00002
00003
Address Instruction
Operands
S
R
00000
00001
00002
LD
00002
00003
00500
KEEP(11)
00500
LD
KEEP(11)
Flags
There are no flags affected by this instruction.
Precautions
Exercise caution when using a KEEP reset line that is controlled by an external
normally closed device. Never use an input bit in an inverse condition on the re-
set (R) for KEEP(11) when the input device uses an AC power supply. The delay
in shutting down the PC’s DC power supply (relative to the AC power supply to
154
INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03)
Section 5-10
the input device) can cause the designated bit of KEEP(11) to be reset. This situ-
ation is shown below.
Input Unit
A
S
KEEP(11)
NEVER
B
A
R
Bits used in KEEP are not reset in interlocks. Refer to the 5-10 INTERLOCK –
and INTERLOCK CLEAR IL(02) and ILC(03) for details.
Example
If a HR bit or an AR bit is used, bit status will be retained even during a power
interruption. KEEP(11) can thus be used to program bits that will maintain status
after restarting the PC following a power interruption. An example of this that can
be used to produce a warning display following a system shutdown for an emer-
gency situation is shown below. Bits 00002, 00003, and 00004 would be turned
ON to indicate some type of error. Bit 00005 would be turned ON to reset the
warning display. HR 0000, which is turned ON when any one of the three bits
indicates an emergency situation, is used to turn ON the warning indicator
through 00500.
00002
00003
00004
S
Address Instruction
Operands
00002
00000
00001
00002
00003
00004
00005
00006
LD
KEEP(11)
HR 0000
OR
00003
00004
00005
0000
Indicates
emergency
situation
OR
LD
R
KEEP(11)
LD
HR
HR
0000
Reset input
00005
OUT
00500
HR 0000
Activates
warning
display
00500
KEEP(11) can also be combined with TIM to produce delays in turning bits ON
and OFF. Refer to 5-14-1 TIMER – TIM for details.
5-10 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03)
Ladder Symbol
IL(02)
Ladder Symbol
ILC(03)
Description
IL(02) is always used in conjunction with ILC(03) to create interlocks. Interlocks
are used to enable branching in the same way as can be achieved with TR bits,
but treatment of instructions between IL(02) and ILC(03) differs from that with
TR bits when the execution condition for IL(02) is OFF. If the execution condition
of IL(02) is ON, the program will be executed as written, with an ON execution
condition used to start each instruction line from the point where IL(02) is located
through the next ILC(03). Refer to 4-7-7 Branching Instruction Lines for basic
descriptions of both methods.
If the execution condition for IL(02) is OFF, the interlocked section between
IL(02) and ILC(03) will be treated as shown in the following table:
155
INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03)
Section 5-10
Instruction
OUT and OUT NOT
SET and RSET
Treatment
Designated bit turned OFF.
Bit status maintained.
Reset.
TIM and TIMH(15)
TTIM(87)
PV maintained.
CNT, CNTR(12)
KEEP(11)
PV maintained.
Bit status maintained.
DIFU(13) and DIFD(14)
Not executed (see the following
DIFU(13) and DIFD(14) in Interlocks).
All others
Not executed.
IL(02) and ILC(03) do not necessarily have to be used in pairs. IL(02) can be
used several times in a row, with each IL(02) creating an interlocked section
through the next ILC(03). ILC(03) cannot be used unless there is at least one
IL(02) between it and any previous ILC(03).
DIFU(13) and DIFD(14) in
Interlocks
Changes in the execution condition for a DIFU(13) or DIFD(14) are not recorded
if the DIFU(13) or DIFD(14) is in an interlocked section and the execution condi-
tion for the IL(02) is OFF. When DIFU(13) or DIFD(14) is execution in an inter-
locked section immediately after the execution condition for the IL(02) has gone
ON, the execution condition for the DIFU(13) or DIFD(14) will be compared to
the execution condition that existed before the interlock became effective (i.e.,
before the interlock condition for IL(02) went OFF). The ladder diagram and bit
status changes for this are shown below. The interlock is in effect while 00000 is
OFF. Notice that 01000 is not turned ON at the point labeled A even though
00001 has turned OFF and then back ON.
00000
00001
Address Instruction
Operands
00000
IL(02)
DIFU(13) 01000
ILC(03)
00000
00001
00002
00003
00004
LD
IL(02)
LD
00001
01000
DIFU(13)
ILC(03)
A
ON
OFF
00000
ON
00001
01000
OFF
ON
OFF
Precautions
There must be an ILC(03) following any one or more IL(02).
Although as many IL(02) instructions as are necessary can be used with one
ILC(03), ILC(03) instructions cannot be used consecutively without at least one
IL(02) in between, i.e., nesting is not possible. Whenever a ILC(03) is executed,
all interlocks between the active ILC(03) and the preceding ILC(03) are cleared.
When more than one IL(02) is used with a single ILC(03), an error message will
appear when the program check is performed, but execution will proceed nor-
mally.
Flags
There are no flags affected by these instructions.
156
JUMP and JUMP END – JMP(04) and JME(05)
Section 5-11
Example
The following diagram shows IL(02) being used twice with one ILC(03).
Address Instruction
Operands
00000
00001
IL(02)
00000
00001
00002
00003
LD
00000
IL(02)
LD
TIM 511
00001
511
#0015
001.5 s
TIM
00002
#
0015
IL(02)
00004
00005
00006
00007
00008
00009
LD
00002
00003
00100
00004
IL(02)
LD
CP
R
CNT
001
IR 010
00003
00004
00100
001
AND NOT
LD
CNT
00005
010
00502
00010
00011
00012
LD
00005
00502
OUT
ILC(03)
ILC(03)
When the execution condition for the first IL(02) is OFF, TIM 511 will be reset to
1.5 s, CNT 001 will not be changed, and 00502 will be turned OFF. When the
execution condition for the first IL(02) is ON and the execution condition for the
second IL(02) is OFF, TIM 511 will be executed according to the status of 00001,
CNT 001 will not be changed, and 00502 will be turned OFF. When the execution
conditions for both the IL(02) are ON, the program will execute as written.
5-11 JUMP and JUMP END – JMP(04) and JME(05)
Ladder Symbols
Definer Values
N: Jump number
JMP(04) N
# (00 to 99)
N: Jump number
JME(05) N
# (00 to 99)
Limitations
Description
Jump numbers 01 through 99 may be used only once in JMP(04) and once in
JME(05), i.e., each can be used to define one jump only. Jump number 00 can be
used as many times as desired.
JMP(04) is always used in conjunction with JME(05) to create jumps, i.e., to skip
from one point in a ladder diagram to another point. JMP(04) defines the point
from which the jump will be made; JME(05) defines the destination of the jump.
When the execution condition for JMP(04) in ON, no jump is made and the pro-
gram is executed consecutively as written. When the execution condition for
JMP(04) is OFF, a jump is made to the JME(05) with the same jump number and
the instruction following JME(05) is executed next.
If the jump number for JMP(04) is between 01 and 99, jumps, when made, will go
immediately to JME(05) with the same jump number without executing any
instructions in between. The status of timers, counters, bits used in OUT, bits
used in OUT NOT, and all other status bits controlled by the instructions between
JMP(04) and JMP(05) will not be changed. Each of these jump numbers can be
used to define only one jump. Because all of instructions between JMP(04) and
JME(05) are skipped, jump numbers 01 through 99 can be used to reduce cycle
time.
157
Timer and Counter Instructions
Section 5-14
If the jump number for JMP(04) is 00, the CPU Unit will look for the next JME(05)
with a jump number of 00. To do so, it must search through the program, causing
a longer cycle time (when the execution condition is OFF) than for other jumps.
The status of timers, counters, bits used in OUT, bits used in OUT NOT, and all
other status controlled by the instructions between JMP(04) 00 and JMP(05) 00
will not be changed. jump number 00 can be used as many times as desired. A
jump from JMP(04) 00 will always go to the next JME(05) 00 in the program. It is
thus possible to use JMP(04) 00 consecutively and match them all with the same
JME(05) 00. It makes no sense, however, to use JME(05) 00 consecutively, be-
cause all jumps made to them will end at the first JME(05) 00.
DIFU(13) and DIFD(14) in
Jumps
Although DIFU(13) and DIFD(14) are designed to turn ON the designated bit for
one cycle, they will not necessarily do so when written between JMP(04) and
JME (05). Once either DIFU(13) or DIFD(14) has turned ON a bit, it will remain
ON until the next time DIFU(13) or DIFD(14) is executed again. In normal pro-
gramming, this means the next cycle. In a jump, this means the next time the
jump from JMP(04) to JME(05) is not made, i.e., if a bit is turned ON by DIFU(13)
or DIFD(14) and then a jump is made in the next cycle so that DIFU(13) or
DIFD(14) are skipped, the designated bit will remain ON until the next time the
execution condition for the JMP(04) controlling the jump is ON.
Precautions
When JMP(04) and JME(05) are not used in pairs, an error message will appear
when the program check is performed. Although this message also appears if
JMP(04) 00 and JME(05) 00 are not used in pairs, the program will execute prop-
erly as written.
Flags
There are no flags affected by these instructions.
Examples
Examples of jump programs are provided in 4-7-8 Jumps.
5-12 END – END(01)
Ladder Symbol
END(01)
Description
END(01) is required as the last instruction in any program. If there are subrou-
tines, END(01) is placed after the last subroutine. No instruction written after
END(01) will be executed. END(01) can be placed anywhere in the program to
execute all instructions up to that point, as is sometimes done to debug a pro-
gram, but it must be removed to execute the remainder of the program.
If there is no END(01) in the program, no instructions will be executed and the
error message “NO END INST” will appear.
Flags
END(01) turns OFF the ER, CY, GR, EQ, and LE Flags.
5-13 NO OPERATION – NOP(00)
Description
NOP(00) is not generally required in programming and there is no ladder symbol
for it. When NOP(00) is found in a program, nothing is executed and the program
execution moves to the next instruction. When memory is cleared prior to pro-
gramming, NOP(00) is written at all addresses. NOP(00) can be input through
the 00 function code.
Flags
There are no flags affected by NOP(00).
5-14 Timer and Counter Instructions
TIM and TIMH are decrementing ON-delay timer instructions which require a TC
number and a set value (SV).
CNT is a decrementing counter instruction and CNTR is a reversible counter
instruction. Both require a TC number and a SV. Both are also connected to mul-
tiple instruction lines which serve as an input signal(s) and are reset.
158
Timer and Counter Instructions
Section 5-14
Any one TC number cannot be defined twice, i.e., once it has been used as the
definer in any of the timer or counter instructions, it cannot be used again. Once
defined, TC numbers can be used as many times as required as operands in
instructions other than timer and counter instructions.
TC numbers run from 000 through 511. No prefix is required when using a TC
number as a definer in a timer or counter instruction. Once defined as a timer, a
TC number can be prefixed with TIM for use as an operand in certain instruc-
tions. The TIM prefix is used regardless of the timer instruction that was used to
define the timer. Once defined as a counter, a TC number can be prefixed with
CNT for use as an operand in certain instructions. The CNT is also used regard-
less of the counter instruction that was used to define the counter.
TC numbers can be designated as operands that require either bit or word data.
When designated as an operand that requires bit data, the TC number accesses
a bit that functions as a ‘Completion Flag’ that indicates when the time/count has
expired, i.e., the bit, which is normally OFF, will turn ON when the designated SV
has expired. When designated as an operand that requires word data, the TC
number accesses a memory location that holds the present value (PV) of the
timer or counter. The PV of a timer or counter can thus be used as an operand in
CMP(20), or any other instruction for which the TC area is allowed. This is done
by designating the TC number used to define that timer or counter to access the
memory location that holds the PV.
Note that “TIM 000” is used to designate the TIMER instruction defined with TC
number 000, to designate the Completion Flag for this timer, and to designate
the PV of this timer. The meaning of the term in context should be clear, i.e., the
first is always an instruction, the second is always a bit operand, and the third is
always a word operand. The same is true of all other TC numbers prefixed with
TIM or CNT.
An SV can be input as a constant or as a word address in a data area. If an IR
area word assigned to an Input Unit is designated as the word address, the Input
Unit can be wired so that the SV can be set externally through thumbwheel
switches or similar devices. Timers and counters wired in this way can only be
set externally during RUN or MONITOR mode. All SVs, including those set ex-
ternally, must be in BCD.
5-14-1 TIMER – TIM
Definer Values
N: TC number
Ladder Symbol
# (000 through 511)
TIM N
SV
Operand Data Areas
SV: Set value (word, BCD)
IR, AR, DM, HR, LR, #
Limitations
Description
SV is between 000.0 and 999.9. The decimal point is not entered.
Each TC number can be used as the definer in only one TIMER or COUNTER
instruction.
TC 000 through TC 015 should not be used in TIM if they are required for
TIMH(15). Refer to 5-14-2 HIGH-SPEED TIMER – TIMH(15) for details.
A timer is activated when its execution condition goes ON and is reset (to SV)
when the execution condition goes OFF. Once activated, TIM measures in units
of 0.1 second from the SV.
159
Timer and Counter Instructions
Section 5-14
If the execution condition remains ON long enough for TIM to time down to zero,
the Completion Flag for the TC number used will turn ON and will remain ON
until TIM is reset (i.e., until its execution condition is goes OFF).
The following figure illustrates the relationship between the execution condition
for TIM and the Completion Flag assigned to it.
ON
Execution condition
OFF
ON
Completion Flag
OFF
SV
SV
Precautions
Interlocks and Power Interruptions
Timers in interlocked program sections are reset when the execution condition
for IL(02) is OFF. Power interruptions also reset timers. If a timer that is not reset
under these conditions is desired, SR area clock pulse bits can be counted to
produce timers using CNT. Refer to 5-14-4 COUNTER – CNT for details.
Program execution will continue even if a non-BCD SV is used, but timing will not
be accurate.
Jumps
Never program TIM between JMP(04) 00 and JME(05) 00 with an SV of #0000.
The Completion Flag will turn ON even when the execution condition for
JMP(04) 00 is ON (i.e., even when the program section with TIM is jumped). TIM
can be programmed successfully between JMP(04) and JME(05) as long as a
jump number between 01 and 99 is used.
Step Instructions
Never program TIM between STEP(08) and SNXT(09) with an SV of #0000. The
Completion Flag will turn ON even when the step containing TIM is reset.
The SV of the timers can be set in the range #0000 to #9999 (BCD). If the SV for a
timer is set to #0000 or #0001, it will operate in the following way. If the SV is set
to #0000, when the timer input goes from OFF to ON, the Completion Flag will
turn ON. If the SV is set to #0001, because the timer accuracy is 0 to –0.1 s, the
actual time will be a value between 0 and 0.1 s, and the Completion Flag may
turn ON as soon as the timer input goes from OFF to ON. With other values also,
allow for a timer accuracy of 0 to –0.1 s when setting the SV.
Flags
ER:
SV is not in BCD.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
Examples
All of the following examples use OUT in diagrams that would generally be used
to control output bits in the IR area. There is no reason, however, why these dia-
grams cannot be modified to control execution of other instructions.
Example 1:
Basic Application
The following example shows two timers, one set with a constant and one set via
input word 005. Here, 00200 will be turned ON after 00000 goes ON and stays
ON for at least 15 seconds. When 00000 goes OFF, the timer will be reset and
00200 will be turned OFF. When 00001 goes ON, TIM 001 is started from the SV
provided through IR word 005. Bit 00201 is also turned ON when 00001 goes
160
Timer and Counter Instructions
Section 5-14
ON. When the SV in 005 has expired, 00201 is turned OFF. This bit will also be
turned OFF when TIM 001 is reset, regardless of whether or not SV has expired.
00000
Address Instruction
Operands
00000
TIM 000
#0150
00000
00001
LD
015.0 s
TIM
000
0150
000
TIM 000
00001
#
00200
00002
00003
00004
00005
LD
TIM
OUT
LD
00200
00001
001
TIM 001
IR 005
IR 005
TIM
005
TIM 001
00006
00007
AND NOT
OUT
TIM
001
00201
00200
Example 2:
Extended Timers
There are two ways to achieve timers that operate for longer than 999.9 se-
conds. One method is to program consecutive timers, with the Completion Flag
of each timer used to activate the next timer. A simple example with two
900.0-second (15-minute) timers combined to functionally form a 30-minute tim-
er.
00000
Address Instruction
Operands
00000
TIM 001
#9000
00000
00001
LD
900.0 s
TIM
001
9000
001
TIM 001
#
TIM 002
00002
00003
LD
TIM
#9000 900.0 s
TIM
002
TIM 002
#
9000
002
00200
00004
00005
LD
TIM
OUT
00200
In this example, 00200 will be turned ON 30 minutes after 00000 goes ON.
TIM can also be combined with CNT or CNT can be used to count SR area clock
pulse bits to produce longer timers. An example is provided in 5-14-4 COUNTER
– CNT.
Example 3:
ON/OFF Delays
TIM can be combined with KEEP(11) to delay turning a bit ON and OFF in refer-
ence to a desired execution condition. KEEP(11) is described in 5-9-4 KEEP –
KEEP(11).
To create delays, the Completion Flags for two TIM are used to determine the
execution conditions for setting and reset the bit designated for KEEP(11). The
bit whose manipulation is to be delayed is used in KEEP(11). Turning ON and
OFF the bit designated for KEEP(11) is thus delayed by the SV for the two TIM.
The two SV could naturally be the same if desired.
In the following example, 00500 would be turned ON 5.0 seconds after 00000
goes ON and then turned OFF 3.0 seconds after 00000 goes OFF. It is neces-
sary to use both 00500 and 00000 to determine the execution condition for TIM
161
Timer and Counter Instructions
Section 5-14
002; 00000 in an inverse condition is necessary to reset TIM 002 when 00000
goes ON and 00500 is necessary to activate TIM 002 (when 00000 is OFF).
00000
Address Instruction
Operands
00000
TIM 001
#0050 005.0 s
00000
00001
LD
TIM
001
0050
00500
00000
002
00500 00000
TIM 001
#
TIM 002
#0030
00002
00003
00004
LD
003.0 s
AND NOT
TIM
S
R
KEEP(11)
00500
#
0030
001
00005
00006
00007
LD
TIM
TIM
00500
TIM 002
LD
002
KEEP(11)
00000
00500
5.0 s
3.0 s
Example 4:
One-Shot Bits
The length of time that a bit is kept ON or OFF can be controlled by combining
TIM with OUT or OUT NO. The following diagram demonstrates how this is pos-
sible. In this example, 00204 would remain ON for 1.5 seconds after 00000 goes
ON regardless of the time 00000 stays ON. This is achieved by using 01000 as a
self-maintaining bit activated by 00000 and turning ON 00204 through it. When
TIM 001 comes ON (i.e., when the SV of TIM 001 has expired), 00204 will be
turned OFF through TIM 001 (i.e., TIM 001 will turn ON which, as an inverse
condition, creates an OFF execution condition for OUT 00204).
01000
00000
01000
TIM 001
Address Instruction
Operands
01000
01000
00000
00001
00002
00003
00004
00005
LD
AND NOT
OR
TIM
001
00000
01000
01000
001
OUT
LD
TIM 001
TIM
#0015
001.5 s
#
0015
00006
00007
00008
LD
01000
001
01000 TIM 001
AND NOT
OUT
TIM
00204
00204
00000
00204
1.5 s
1.5 s
162
Timer and Counter Instructions
Section 5-14
The following one-shot timer may be used to save memory.
00000
00100
Address Instruction
Operands
TIM 001
#0015
00000
00001
00002
LD
00000
00100
001
001.5 s
OR
TIM
TIM 001
00100
#
0015
001
00003
00004
AND NOT
OUT
TIM
00100
Example 5:
Flicker Bits
Bits can be programmed to turn ON and OFF at regular intervals while a desig-
nated execution condition is ON by using TIM twice. One TIM functions to turn
ON and OFF a specified bit, i.e., the Completion Flag of this TIM turns the speci-
fied bit ON and OFF. The other TIM functions to control the operation of the first
TIM, i.e., when the first TIM’s Completion Flag goes ON, the second TIM is
started and when the second TIM’s Completion Flag goes ON, the first TIM is
started.
TIM 002
00000
Address Instruction
Operands
00000
TIM 001
#0010
00000
00001
00002
LD
1.0 s
1.5 s
AND
TIM
TIM
002
001
TIM 001
TIM 002
#0015
#
0010
001
00003
00004
LD
TIM
TIM
002
TIM 001
00205
#
0015
001
00005
00006
LD
TIM
OUT
00205
00000
00205
1.0 s
1.5 s 1.0 s 1.5 s
A simpler but less flexible method of creating a flicker bit is to AND one of the SR
area clock pulse bits with the execution condition that is to be ON when the flick-
er bit is operating. Although this method does not use TIM, it is included here for
comparison. This method is more limited because the ON and OFF times must
be the same and they depend on the clock pulse bits available in the SR area.
In the following example the 1-second clock pulse is used (25502) so that 00206
would be turned ON and OFF every second, i.e., it would be ON for 0.5 seconds
and OFF for 0.5 seconds. Precise timing and the initial status of 00206 would
depend on the status of the clock pulse when 00000 goes ON.
Address Instruction
Operands
00000
00000 25502
00000
00001
00002
LD
00206
AND
OUT
25502
00206
163
Timer and Counter Instructions
Section 5-14
5-14-2 HIGH-SPEED TIMER – TIMH(15)
Definer Values
N: TC number
Ladder Symbol
# (000 through 511,
although 000 through 015
preferred)
TIMH(15) N
SV
Operand Data Areas
SV: Set value (word, BCD)
IR, AR, DM, HR, LR, #
Limitations
SV is between 00.00 and 99.99. (Although 00.00 and 00.01 may be set, 00.00
will disable the timer, i.e., turn ON the Completion Flag immediately, and 00.01 is
not reliably cycled.) The decimal point is not entered.
Each TC number can be used as the definer in only one TIMER or COUNTER
instruction.
If the cycle time is greater than 10 ms, use TC 000 through TC 015. The PVs and
completion flags of timers 000 through 015 are refreshed every 10 ms, but the
PVs of timers 016 through TC 511 are refreshed each time that TIMH(15) is
executed in the program.
Description
Precautions
TIMH(15) operates in the same way as TIM except that TIMH measures in units
of 0.01 second.
The cycle time affects TIMH(15) accuracy if TC 016 through TC 511 are used. If
the cycle time is greater than 10 ms, use TC 000 through TC 015.
Refer to 5-14-1 TIMER – TIM for operational details and examples. Except for
the above, and all aspects of operation are the same.
Timers in interlocked program sections are reset when the execution condition
for IL(02) is OFF. Power interruptions also reset timers. If a timer that is not reset
under these conditions is desired, SR area clock pulse bits can be counted to
produce timers using CNT. Refer to 5-14-4 COUNTER – CNT for details.
Program execution will continue even if a non-BCD SV is used, but timing will not
be accurate.
The SV of the timers can be set in the range #0000 to #9999 (BCD). If the SV for a
timer is set to #0000 or #0001, it will operate in the following way. If the SV is set
to #0000, when the timer input goes from OFF to ON, the Completion Flag will
turn ON. There may be a time delay if TC 000 to TC 003 are used. If the SV is set
to #0001, because the timer accuracy is 0 to –0.1 s, the actual time will be a value
between 0 and 0.1 s, and the Completion Flag may turn ON as soon as the timer
input goes from OFF to ON. With other values also, allow for a timer accuracy of
0 to –0.1 s when setting the SV.
Flags
ER:
SV is not in BCD.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
164
Timer and Counter Instructions
Section 5-14
5-14-3 TOTALIZING TIMER – TTIM(87)
Definer Values
N: TC number
Ladder Symbol
# (000 through 511)
TTIM(87)
Operand Data Areas
N
SV: Set value (word, BCD)
IR, AR, DM, HR, LR
RB: Reset bit
SV
RB
IR, SR, AR, HR, LR
Limitations
Description
SV is between 0000 and 9999 (000.0 and 999.9 s) and must be in BCD. The dec-
imal point is not entered.
Each TC number can be used as the definer in only one TIMER or COUNTER
instruction.
TTIM(87) is used to create a timer that increments the PV every 0.1 s to time
between 0.1 and 999.9 s. TTIM(87) increments in units of 0.1 second from zero.
TTIM(87) accuracy is +0.0/–0.1 second. A TTIM(87) timer will time as long as its
execute condition is ON until it reaches the SV or until RB turns ON to reset the
timer. TTIM(87) timers will time only as long as they are executed every cycle,
i.e., they do not time, but maintain the current PV, in interlocked program sec-
tions or when they are jumped in the program.
The PVs and completion flags of timers 000 through 015 are refreshed every
10 ms, but the PVs of timers 016 through TC 511 are refreshed each time that
TTIM(87) is executed in the program.
Precautions
The PVs of totalizing timers in interlocked program sections are maintained
when the execution condition for IL(02) is OFF. Unlike timers and high-speed
timers, totalizing timers in jumped program sections do not continue timing, but
maintain the PV.
Power interruptions will reset timers.
Totalizing timers will not restart after timing out unless the PV is changed to a
value below the SV or the reset input is turned ON.
A delay of one cycle is sometimes required for a Completion Flag to be turned
ON after the timer times out.
The SV of the timers can be set in the range #0000 to #9999 (BCD). If the SV for a
timer is set to #0000 or #0001, it will operate in the following way. If the SV is set
to #0000, when the timer input goes from OFF to ON, the Completion Flag will
turn ON. If the SV is set to #0001, because the timer accuracy is 0 to –0.1 s, the
actual time will be a value between 0 and 0.1 s, and the Completion Flag may
turn ON as soon as the timer input goes from OFF to ON. With other values also,
allow for a timer accuracy of 0 to –0.1 s when setting the SV.
Flags
ER (SR 25503): Content of ꢀDM word is not BCD when set for BCD.
SV is not BCD.
165
Timer and Counter Instructions
Section 5-14
Example
The following figure illustrates the relationship between the execution conditions
for a totalizing timer with a set value of 2 s, its PV, and the Completion Flag.
00000
Address Instruction
Operands
00000
TTIM(87)
TIM 000
#0020
00000
00001
LD
TTIM(87)
TIM
#
000
0020
2100
LR 2100
LR
Timer input
(I: IR 00000)
Reset bit
(RB: LR 2100)
Completion Flag
(TIM 000)
Present value: 0020
0000
5-14-4 COUNTER – CNT
Definer Values
N: TC number
Ladder Symbol
# (000 through 511)
CP
R
CNT N
SV
Operand Data Areas
SV: Set value (word, BCD)
IR, AR, DM, HR, LR, #
Limitations
Description
Each TC number can be used as the definer in only one TIMER or COUNTER
instruction.
CNT is used to count down from SV when the execution condition on the count
pulse, CP, goes from OFF to ON, i.e., the present value (PV) will be decrem-
ented by one whenever CNT is executed with an ON execution condition for CP
and the execution condition was OFF for the last execution. If the execution
condition has not changed or has changed from ON to OFF, the PV of CNT will
not be changed. The Completion Flag for a counter is turned ON when the PV
reaches zero and will remain ON until the counter is reset.
CNT is reset with a reset input, R. When R goes from OFF to ON, the PV is reset
to SV. The PV will not be decremented while R is ON. Counting down from SV will
begin again when R goes OFF. The PV for CNT will not be reset in interlocked
program sections or by power interruptions.
166
Timer and Counter Instructions
Section 5-14
Changes in execution conditions, the Completion Flag, and the PV are illus-
trated below. PV line height is meant only to indicate changes in the PV.
ON
Execution condition
on count pulse (CP)
OFF
ON
Execution condition
on reset (R)
OFF
ON
Completion Flag
OFF
SV
SV
PV
0002
SV – 1
0001
SV – 2
0000
Precautions
Program execution will continue even if a non-BCD SV is used, but the SV will
not be correct.
Jumps
Never program CNT between JMP(04) 00 and JME(05) 00 with an SV of #0000.
The Completion Flag will turn ON even when the execution condition for
JMP(04) 00 is ON (i.e., even when the program section with CNT is jumped).
CNT can be programmed successfully between JMP(04) and JME(05) as long
as a jump number between 01 and 99 is used.
Step Instructions
Never program CNT between STEP(08) and SNXT(09) with an SV of #0000.
The Completion Flag will turn ON even when the step containing CNT is reset.
Flags
ER:
SV is not in BCD.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
Example 1:
Basic Application
In the following example, the PV will be decremented whenever both 00000 and
00001 are ON provided that 00002 is OFF and either 00000 or 00001 was OFF
the last time CNT 004 was executed. When 150 pulses have been counted down
(i.e., when PV reaches zero), 00205 will be turned ON.
00000
00002
00001
Address Instruction
Operands
00000
CP
R
CNT 004
#0150
00000
00001
00002
00003
LD
AND
LD
00001
00002
0004
0150
004
CNT 004
CNT
00205
#
00004
00005
LD
CNT
OUT
00205
Here, 00000 can be used to control when CNT is operative and 00001 can be
used as the bit whose OFF to ON changes are being counted.
167
Timer and Counter Instructions
Section 5-14
The previously-shown CNT can be modified to restart from SV each time power
is turned ON to the PC. This is done by using the First Cycle Flag in the SR area
(25315) to reset CNT as shown below.
00000
00001
Address Instruction
Operands
00000
CP
R
CNT 004
#0150
00000
00001
00002
00003
00004
LD
00002
25315
AND
LD
00001
00002
25315
004
OR
CNT
CNT 004
#
0150
004
00205
00005
00006
LD
CNT
OUT
00205
Example 2:
Extended Counter
Counters that can count past 9,999 can be programmed by using one CNT to
count the number of times another CNT has counted to zero from SV.
In the following example, 00000 is used to control when CNT 001 operates. CNT
001, when 00000 is ON, counts down the number of OFF to ON changes in
00001. CNT 001 is reset by its Completion Flag, i.e., it starts counting again as
soon as its PV reaches zero. CNT 002 counts the number of times the Comple-
tion Flag for CNT 001 goes ON. Bit 00002 serves as a reset for the entire ex-
tended counter, resetting both CNT 001 and CNT 002 when it is OFF. The
Completion Flag for CNT 002 is also used to reset CNT 001 to inhibit CNT 001
operation, once SV for CNT 002 has been reached, until the entire extended
counter is reset via 00002.
Because in this example the SV for CNT 001 is 100 and the SV for CNT 002 is
200, the Completion Flag for CNT 002 turns ON when 100 x 200 or 20,000 OFF
to ON changes have been counted in 00001. This would result in 00203 being
turned ON.
00000 00001
00002
CP
Address Instruction
Operands
00000
CNT 001
#0100
00000
00001
00002
00003
00004
00005
LD
AND
LD NOT
OR
00001
00002
001
R
CNT
CNT
CNT 001
CNT 002
CNT 001
00002
OR
002
CNT
001
#
0100
001
00006
00007
00008
LD
CNT
LD NOT
CNT
00002
002
CP
R
CNT 002
#0200
#
0200
002
00009
00010
LD
CNT
OUT
00203
CNT 002
00203
CNT can be used in sequence as many times as required to produce counters
capable of counting any desired values.
Example 3:
Extended Timers
CNT can be used to create extended timers in two ways: by combining TIM with
CNT and by counting SR area clock pulse bits.
In the following example, CNT 002 counts the number of times TIM 001 reaches
zero from its SV. The Completion Flag for TIM 001 is used to reset TIM 001 so
that it runs continuously and CNT 002 counts the number of times the Comple-
tion Flag for TIM 001 goes ON (CNT 002 would be executed once each time be-
168
Timer and Counter Instructions
Section 5-14
tween when the Completion Flag for TIM 001 goes ON and TIM 001 is reset by
its Completion Flag). TIM 001 is also reset by the Completion Flag for CNT 002
so that the extended timer would not start again until CNT 002 was reset by
00001, which serves as the reset for the entire extended timer.
Because in this example the SV for TIM 001 is 5.0 seconds and the SV for CNT
002 is 100, the Completion Flag for CNT 002 turns ON when 5 seconds x 100
times, i.e., 500 seconds (or 8 minutes and 20 seconds) have expired. This would
result in 00201 being turned ON.
00000 TIM 001 CNT 002
Address Instruction
Operands
00000
TIM 001
#0050
00000
00001
00002
00003
LD
005.0 s
AND NOT
AND NOT
TIM
TIM
001
002
TIM 001
00001
CP
R
CNT
CNT
002
001
#
0050
001
#0100
00004
00005
00006
LD
TIM
LD
00001
002
CNT 002
00201
CNT
#
0100
002
00007
00008
LD
CNT
OUT
00201
In the following example, CNT 001 counts the number of times the 1-second
clock pulse bit (25502) goes from OFF to ON. Here again, 00000 is used to con-
trol the times when CNT is operating.
Because in this example the SV for CNT 001 is 700, the Completion Flag for
CNT 002 turns ON when 1 second x 700 times, or 11 minutes and 40 seconds
have expired. This would result in 00202 being turned ON.
00000 25502
00001
CP
Address Instruction
Operands
00000
CNT
001
00000
00001
00002
00003
LD
AND
LD NOT
CNT
25502
00001
001
R
#0700
CNT 001
#
0700
001
0202
00004
00005
LD
CNT
OUT
00202
Note The shorter clock pulses will not necessarily produce accurate timers because
their short ON times might not be read accurately during longer cycles. In partic-
ular, the 0.02-second and 0.1-second clock pulses should not be used to create
timers with CNT instructions.
5-14-5 REVERSIBLE COUNTER – CNTR(12)
Definer Values
N: TC number
Ladder Symbol
# (000 through 511)
II
CNTR(12)
N
DI
R
Operand Data Areas
SV
SV: Set value (word, BCD)
IR, AR, DM, HR, LR, #
169
Timer and Counter Instructions
Section 5-14
Limitations
Description
Each TC number can be used as the definer in only one TIMER or COUNTER
instruction.
The CNTR(12) is a reversible, up/down circular counter, i.e., it is used to count
between zero and SV according to changes in two execution conditions, those in
the increment input (II) and those in the decrement input (DI).
The present value (PV) will be incremented by one whenever CNTR(12) is
executed with an ON execution condition for II and the last execution condition
for II was OFF. The present value (PV) will be decremented by one whenever
CNTR(12) is executed with an ON execution condition for DI and the last execu-
tion condition for DI was OFF. If OFF to ON changes have occurred in both II and
DI since the last execution, the PV will not be changed.
If the execution conditions have not changed or have changed from ON to OFF
for both II and DI, the PV of CNT will not be changed.
When decremented from 0000, the present value is set to SV and the Comple-
tion Flag is turned ON until the PV is decremented again. When incremented
past the SV, the PV is set to 0000 and the Completion Flag is turned ON until the
PV is incremented again.
CNTR(12) is reset with a reset input, R. When R goes from OFF to ON, the PV is
reset to zero. The PV will not be incremented or decremented while R is ON.
Counting will begin again when R goes OFF. The PV for CNTR(12) will not be
reset in interlocked program sections or by the effects of power interruptions.
Changes in II and DI execution conditions, the Completion Flag, and the PV are
illustrated below starting from part way through CNTR(12) operation (i.e., when
reset, counting begins from zero). PV line height is meant to indicate changes in
the PV only.
ON
Execution condition
on increment (II)
OFF
ON
Execution condition
on decrement (DI)
OFF
ON
Completion Flag
OFF
SV
SV
PV
SV – 1
SV – 1
0001
SV – 2
SV – 2
0000
0000
Precautions
Flags
Program execution will continue even if a non-BCD SV is used, but the SV will
not be correct.
ER:
SV is not in BCD.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
170
Data Shifting
Section 5-15
5-15 Data Shifting
All of the instructions described in this section are used to shift data, but in differ-
ing amounts and directions. The first shift instruction, SFT(10), shifts an execu-
tion condition into a shift register; the rest of the instructions shift data that is al-
ready in memory.
5-15-1 SHIFT REGISTER – SFT(10)
Ladder Symbol
Operand Data Areas
St: Starting word
IR, SR, AR, HR, LR
E: End word
I
SFT(10)
P
R
St
E
IR, SR, AR, HR, LR
Limitations
St must be less than or equal to E, and St and E must be in the same data area.
If a bit address in one of the words used in a shift register is also used in an
instruction that controls individual bit status (e.g., OUT, KEEP(11)), an error
(“COIL DUPL”) will be generated when program syntax is checked on the Pro-
gramming Console or another Programming Device. The program, however,
will be executed as written. See Example 2: Controlling Bits in Shift Registers for
a programming example that does this.
Description
SFT(10) is controlled by three execution conditions, I, P, and R. If SFT(10) is
executed and 1) execution condition P is ON and was OFF the last execution,
and 2) R is OFF, then execution condition I is shifted into the rightmost bit of a
shift register defined between St and E, i.e., if I is ON, a 1 is shifted into the regis-
ter; if I is OFF, a 0 is shifted in. When I is shifted into the register, all bits previously
in the register are shifted to the left and the leftmost bit of the register is lost.
E
St+1, St+2, ...
St
Lost
data
Execution
condition I
The execution condition on P functions like a differentiated instruction, i.e., I will
be shifted into the register only when P is ON and was OFF the last time SFT(10)
was executed. If execution condition P has not changed or has gone from ON to
OFF, the shift register will remain unaffected.
St designates the rightmost word of the shift register; E designates the leftmost.
The shift register includes both of these words and all words between them. The
same word may be designated for St and E to create a 16-bit (i.e., 1-word) shift
register.
When execution condition R goes ON, all bits in the shift register will be turned
OFF (i.e., set to 0) and the shift register will not operate until R goes OFF again.
Flags
There are no flags affected by SFT(10).
171
Data Shifting
Section 5-15
Example 1:
Basic Application
The following example uses the 1-second clock pulse bit (25502) so that the
execution condition produced by 00005 is shifted into a 3-word register between
IR 010 and IR 012 every second.
00005
25502
00006
Address Instruction
Operands
00005
I
SFT(10)
010
00000
00001
00002
00003
LD
P
R
LD
25502
00006
LD
012
SFT(10)
010
012
Example 2:
Controlling Bits in Shift
Registers
The following program is used to control the status of the 17th bit of a shift regis-
ter running from AR 00 through AR 01. When the 17th bit is to be set, 00004 is
turned ON. This causes the jump for JMP(04) 00 not to be made for that one
cycle, and AR 0100 (the 17th bit) will be turned ON. When 12800 is OFF (i.e., at
all times except during the first cycle after 00004 has changed from OFF to ON),
the jump is executed and the status of AR 0100 will not be changed.
00200 00201
00202
I
Address Instruction
Operands
00200
00000
00001
00002
00003
00004
LD
SFT(10)
AR 00
AND
LD
00201
00202
00203
P
R
LD
AR 01
00203
SFT(10)
AR
AR
00
01
00004
DIFU(13) 12800
JMP(04) 00
00005
00006
00007
00008
00009
00010
00011
LD
00004
12800
12800
00
DIFU(13)
LD
12800
JMP(04)
LD
12800
12800
0100
00
AR 0100
OUT
AR
JME(05)
JME(05) 00
When a bit that is part of a shift register is used in OUT (or any other instruction
that controls bit status), a syntax error will be generated during the program
check, but the program will executed properly (i.e., as written).
Example 3:
Control Action
The following program controls the conveyor line shown below so that faulty
products detected at the sensor are pushed down a shoot. To do this, the execu-
tion condition determined by inputs from the first sensor (00001) are stored in a
shift register: ON for good products; OFF for faulty ones. Conveyor speed has
been adjusted so that HR 0003 of the shift register can be used to activate a
pusher (00500) when a faulty product reaches it, i.e., when HR 0003 turns ON,
00500 is turned ON to activate the pusher.
172
Data Shifting
Section 5-15
The program is set up so that a rotary encoder (00000) controls execution of
SFT(10) through a DIFU(13), the rotary encoder is set up to turn ON and OFF
each time a product passes the first sensor. Another sensor (00002) is used to
detect faulty products in the shoot so that the pusher output and HR 0003 of the
shift register can be reset as required.
Sensor
(00001)
Pusher
(00500)
Sensor
(00002)
Rotary Encoder
(00000)
Chute
00001
00000
00003
Address Instruction
Operands
00001
I
SFT(10)
HR 00
HR 01
00000
00001
00002
00003
LD
P
R
LD
00000
00003
LD
SFT(10)
HR
HR
HR
00
01
HR 0003
00002
00004
00005
00006
00007
00008
LD
0003
00500
00002
00500
0003
00500
00500
OUT
LD
OUT NOT
OUT NOT
HR
HR 0003
5-15-2 REVERSIBLE SHIFT REGISTER – SFTR(84)
Operand Data Areas
C: Control word
IR, AR, DM, HR, LR
St: Starting word
Ladder Symbols
SFTR(84)
@SFTR(84)
C
St
E
C
St
E
IR, SR, AR, DM, HR, LR
E: End word
IR, SR, AR, DM, HR LR
Limitations
St and E must be in the same data area and St must be less than or equal to E.
173
Data Shifting
Section 5-15
Description
SFTR(84) is used to create a single- or multiple-word shift register that can shift
data to either the right or the left. To create a single-word register, designate the
same word for St and E. The control word provides the shift direction, the status
to be put into the register, the shift pulse, and the reset input. The control word is
allocated as follows:
15 14 13 12
Not used.
Shift direction
1 (ON): Left (LSB to MSB)
0 (OFF): Right (MSB to LSB)
Status to input into register
Shift pulse bit
Reset
The data in the shift register will be shifted one bit in the direction indicated by bit
12, shifting one bit out to CY and the status of bit 13 into the other end whenever
SFTR(84) is executed with an ON execution condition as long as the reset bit is
OFF and as long as bit 14 is ON. If SFTR(84) is executed with an OFF execution
condition or if SFTR(84) is executed with bit 14 OFF, the shift register will remain
unchanged. If SFTR(84) is executed with an ON execution condition and the re-
set bit (bit 15) is OFF, the entire shift register and CY will be set to zero.
Flags
ER:
CY:
St and E are not in the same data area or ST is greater than E.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
Receives the status of bit 00 of St or bit 15 of E, depending on the shift
direction.
Example
In the following example, IR 00005, IR 00006, IR 00007, and IR 00008 are used
to control the bits of C used in @SHIFT(84). The shift register is between LR 20
and LR 21, and it is controlled through IR 00009.
Address Instruction
Operands
00005
00005
05012
05013
Direction
00000
00001
00002
00003
00004
00005
00006
00007
00008
00009
LD
OUT
LD
05012
00006
05013
00007
05014
00008
05015
00009
00006
00007
OUT
LD
Status to input
Shift pulse
OUT
LD
05014
05015
OUT
LD
@SFT(10)
00008
00009
050
20
Reset
LR
LR
21
@SFTR(84)
050
LR 20
LR 21
174
Data Shifting
Section 5-15
5-15-3 ARITHMETIC SHIFT LEFT – ASL(25)
Ladder Symbols
Operand Data Areas
Wd: Shift word
ASL(25)
Wd
@ASL(25)
Wd
IR, SR, AR, DM, HR, LR
Description
When the execution condition is OFF, ASL(25) is not executed. When the execu-
tion condition is ON, ASL(25) shifts a 0 into bit 00 of Wd, shifts the bits of Wd one
bit to the left, and shifts the status of bit 15 into CY.
Bit
15
Bit
00
CY
1 0 0 1 1 1 0 0 0 1 0 1 0 0 1 1
0
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
CY:
EQ:
N:
Receives the status of bit 15.
ON when the content of Wd is zero; otherwise OFF.
ON when a 1 is shifted into bit 15 of Wd.
5-15-4 ARITHMETIC SHIFT RIGHT – ASR(26)
Ladder Symbols
Operand Data Areas
Wd: Shift word
ASR(26)
Wd
@ASR(26)
Wd
IR, SR, AR, DM, HR, LR
Description
When the execution condition is OFF, ASR(25) is not executed. When the
execution condition is ON, ASR(25) shifts a 0 into bit 15 of Wd, shifts the bits of
Wd one bit to the right, and shifts the status of bit 00 into CY.
Bit
15
Bit
00
CY
1 1 0 0 1 0 1 1 0 0 1 1 0 0 1 0
0
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
CY:
EQ:
Receives the data of bit 00.
ON when the content of Wd is zero; otherwise OFF.
175
Data Shifting
Section 5-15
5-15-5 ROTATE LEFT – ROL(27)
Ladder Symbols
Operand Data Areas
Wd: Rotate word
ROL(27)
Wd
@ROL(27)
Wd
IR, SR, AR, DM, HR, LR
Description
When the execution condition is OFF, ROL(27) is not executed. When the
execution condition is ON, ROL(27) shifts all Wd bits one bit to the left, shifting
CY into bit 00 of Wd and shifting bit 15 of Wd into CY.
Bit
15
Bit
00
CY
0
1 0 1 1 0 0 1 1 1 0 0 0 1 1 0 1
Precautions
Flags
Use STC(41) to set the status of CY or CLC(41) to clear the status of CY before
doing a rotate operation to ensure that CY contains the proper status before
execution ROL(27).
The status of CY is cleared at the end of each cycle (when END(01) is executed).
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
CY:
EQ:
N:
Receives the data of bit 15.
ON when the content of Wd is zero; otherwise OFF.
ON when a 1 is shifted into bit 15 of Wd.
5-15-6 ROTATE RIGHT – ROR(28)
Ladder Symbols
Operand Data Areas
Wd: Rotate word
ROR(28)
Wd
@ROR(28)
Wd
IR, SR, AR, DM, HR, LR
Description
When the execution condition is OFF, ROR(28) is not executed. When the
execution condition is ON, ROR(28) shifts all Wd bits one bit to the right, shifting
CY into bit 15 of Wd and shifting bit 00 of Wd into CY.
Bit
15
Bit
00
CY
0
0 1 0 1 0 1 0 0 0 1 1 1 0 0 0 1
Precautions
Flags
Use STC(41) to set the status of CY or CLC(41) to clear the status of CY before
doing a rotate operation to ensure that CY contains the proper status before
execution ROR(28).
The status of CY is cleared at the end of each cycle (when END(01) is executed).
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
CY:
EQ:
N:
ROR(28) receives the data of bit 00.
ON when the content of Wd is zero; otherwise OFF.
ON when a 1 is shifted into bit 15 of Wd.
176
Data Shifting
Section 5-15
5-15-7 ONE DIGIT SHIFT LEFT – SLD(74)
Ladder Symbols
Operand Data Areas
St: Starting word
SLD(74)
@SLD(74)
IR, SR, AR, DM, HR, LR
St
E
St
E
E: End word
IR, SR, AR, DM, HR, LR
Limitations
Description
St and E must be in the same data area, and St must be less than or equal to E.
When the execution condition is OFF, SLD(74) is not executed. When the execu-
tion condition is ON, SLD(74) shifts data between St and E (inclusive) by one
digit (four bits) to the left. 0 is written into the rightmost digit of the St, and the
content of the leftmost digit of E is lost.
E
St
...
8 F C 5
D 7 9 1
Lost data
0
Precautions
Flags
If a power failure occurs during a shift operation across more than 50 words, the
shift operation might not be completed.
ER:
The St and E words are in different areas, or St is greater than E.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
5-15-8 ONE DIGIT SHIFT RIGHT – SRD(75)
Ladder Symbols
Operand Data Areas
E: End word
SRD(75)
@SRD(75)
IR, SR, AR, DM, HR, LR
E
E
St: Starting word
St
St
IR, SR, AR, DM, HR, LR
Limitations
Description
St and E must be in the same data area, and St must be less than or equal to E.
When the execution condition is OFF, SRD(75) is not executed. When the
execution condition is ON, SRD(75) shifts data between St and E (inclusive) by
one digit (four bits) to the right. 0 is written into the leftmost digit of St and the
rightmost digit of E is lost.
St
E
...
3 4 5 2
F 8 C 1
Lost data
0
177
Data Shifting
Section 5-15
Precautions
If a power failure occurs during a shift operation across more than 50 words, the
shift operation might not be completed. Set the range between E and St to a
maximum of 50 words.
Flags
ER:
The St and E words are in different areas, or St is less than E.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
5-15-9 WORD SHIFT – WSFT(16)
Ladder Symbols
Operand Data Areas
St: Starting word
WSFT(16)
@WSFT(16)
IR, SR, AR, DM, HR, LR
St
E
St
E
E: End word
IR, SR, AR, DM, HR, LR
Limitations
Description
St and E must be in the same data area, and St must be less than or equal to E.
When the execution condition is OFF, WSFT(16) is not executed. When the
execution condition is ON, WSFT(16) shifts data between St and E in word units.
Zeros are written into St and the content of E is lost.
E
St + 1
St
F
0
4
C
2
2
3
1
4
5
2
9
1
0
0
0
2
0
9
0
Lost
0000
E
St + 1
St
3
5
0
2
Flags
ER:
The St and E words are in different areas, or St is greater than E.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
5-15-10 ASYNCHRONOUS SHIFT REGISTER – ASFT(17)
Operand Data Areas
C: Control word
Ladder Symbols
IR, SR, AR, DM, HR, LR
ASFT(17)
ASFT(17)
St: Starting word
C
St
E
C
St
E
IR, SR, AR, DM, HR, LR
E: End word
IR, SR, AR, DM, HR, LR
Limitations
St and E must be in the same data area, and St must be less than or equal to E.
178
Data Shifting
Section 5-15
Description
When the execution condition is OFF, ASFT(17) does nothing and the program
moves to the next instruction. When the execution condition is ON, ASFT(17) is
used to create and control a reversible asynchronous word shift register be-
tween St and E. This register only shifts words when the next word in the register
is zero, e.g., if no words in the register contain zero, nothing is shifted. Also, only
one word is shifted for each word in the register that contains zero. When the
contents of a word are shifted to the next word, the original word’s contents are
set to zero. In essence, when the register is shifted, each zero word in the regis-
ter trades places with the next word. (See Example below.)
The shift direction (i.e. whether the “next word” is the next higher or the next low-
er word) is designated in C. C is also used to reset the register. All of any portion
of the register can be reset by designating the desired portion with St and E.
Control Word
Bits 00 through 12 of C are not used. Bit 13 is the shift direction: turn bit 13 ON to
shift down (toward lower addressed words) and OFF to shift up (toward higher
addressed words). Bit 14 is the Shift Enable Bit: turn bit 14 ON to enable shift
register operation according to bit 13 and OFF to disable the register. Bit 15 is the
Reset bit: the register will be reset (set to zero) between St and E when
ASFT(17) is executed with bit 15 ON. Turn bit 15 OFF for normal operation.
Control word value
#4000
Function
Shifts upward (towards higher addressed words).
Shifts downward (towards lower addressed words).
Clears the contents of St through E to #0000.
#6000
#8000
Flags
ER:
The St and E words are in different areas, or St is greater than E.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
Example
The following example shows instruction ASFT(17) used to shift words in an
11-word shift register created between DM 0100 and DM 0110 with a control
word value of #6000 (bits 13 and 14 ON). The data changes that would occur for
the given register and control word contents are also shown.
00000
Address Instruction
Operands
00000
ASFT(17)
#6000
00100
00101
LD
ASFT(17)
DM 0100
DM 0110
#
6000
0100
0110
DM
DM
Before
execution
After 1
execution
After 7
executions
DM 0100
DM 0101
DM 0102
DM 0103
DM 0104
DM 0105
DM 0106
DM 0107
DM 0108
DM 0109
DM 0110
1234
0000
0000
2345
3456
0000
4567
5678
6789
0000
789A
1234
0000
2345
0000
3456
4567
0000
5678
6789
789A
0000
1234
2345
3456
4567
5678
6789
789A
0000
0000
0000
0000
179
Data Movement
Section 5-16
5-16 Data Movement
This section describes the instructions used for moving data between different
addresses in data areas. These movements can be programmed to be within
the same data area or between different data areas. Data movement is essential
for utilizing all of the data areas of the PC. Effective communications in Link Sys-
tems also requires data movement. All of these instructions change only the
content of the words to which data is being moved, i.e., the content of source
words is the same before and after execution of any of the data movement
instructions.
5-16-1 MOVE – MOV(21)
Ladder Symbols
Operand Data Areas
S: Source word
IR, SR, AR, DM, HR, TC, LR, #
D: Destination word
MOV(21)
@MOV(21)
S
D
S
D
IR, SR, AR, DM, HR, LR
Description
When the execution condition is OFF, MOV(21) is not executed. When the
execution condition is ON, MOV(21) copies the content of S to D.
Source word
Destination word
Bit status
not changed.
Precautions
Flags
TC numbers cannot be designated as D to change the PV of the timer or counter.
You can, however, easily change the PV of a timer or a counter by using
BSET(71).
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when all zeros are transferred to D.
ON when bit 15 of D is set to 1.
N:
5-16-2 MOVE NOT – MVN(22)
Ladder Symbols
Operand Data Areas
S: Source word
IR, SR, AR, DM, HR, TC, LR, #
D: Destination word
MVN(22)
@MVN(22)
S
D
S
D
IR, SR, AR, DM, HR, LR
Description
When the execution condition is OFF, MVN(22) is not executed. When the
execution condition is ON, MVN(22) transfers the inverted content of S (speci-
fied word or four-digit hexadecimal constant) to D, i.e., for each ON bit in S, the
corresponding bit in D is turned OFF, and for each OFF bit in S, the correspond-
ing bit in D is turned ON.
Source word
Destination word
Bit status
inverted.
180
Data Movement
Section 5-16
Precautions
TC numbers cannot be designated as D to change the PV of the timer or counter.
However, these can be easily changed using BSET(71).
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when all zeros are transferred to D.
ON when bit 15 of D is set to 1.
N:
5-16-3 BLOCK SET – BSET(71)
Operand Data Areas
S: Source data
IR, SR, AR, DM, HR, TC, LR, #
St: Starting word
Ladder Symbols
BSET(71)
@BSET(71)
S
St
E
S
St
E
IR, SR, AR, DM, HR, TC, LR
E: End Word
IR, SR, AR, DM, HR, TC, LR
Limitations
Description
St must be less than or equal to E, and St and E must be in the same data area.
When the execution condition is OFF, BSET(71) is not executed. When the
execution condition is ON, BSET(71) copies the content of S to all words from St
through E.
S
St
3 4 5 2
3 4 5 2
St+1
3 4 5 2
St+2
3 4 5 2
E
3 4 5 2
BSET(71) can be used to change timer/counter PV. (This cannot be done with
MOV(21) or MVN(22).) BSET(71) can also be used to clear sections of a data
area, i.e., the DM area, to prepare for executing other instructions.
Flags
ER:
St and E are not in the same data area or St is greater than E.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
181
Data Movement
Section 5-16
Example
The following example shows how to use BSET(71) to change the PV of a timer
depending on the status of IR 00003 and IR 00004. When IR 00003 is ON, TIM
010 will operate as a 50-second timer; when IR 00004 is ON, TIM 010 will oper-
ate as a 30-second timer.
00003
00004
Address Instruction
Operands
00003
@BSET(71)
#0500
00000
00001
00002
LD
AND NOT
@BSET(71)
00004
TIM 010
TIM 010
#
0500
010
00004
00003
TIM
TIM
@BSET(71)
#0300
010
00003
00004
00005
LD
00004
00003
TIM 010
TIM 010
AND NOT
@BSET(71)
#
0300
010
00003
00004
TIM
TIM
TIM 010
010
#9999
00006
00007
00008
LD
00003
00004
010
OR
TIM
#
9999
5-16-4 BLOCK TRANSFER – XFER(70)
Operand Data Areas
N: Number of words (BCD)
IR, SR, AR, DM, HR, TC, LR, #
S: Starting source word
Ladder Symbols
XFER(70)
@XFER(70)
N
S
D
N
S
D
IR, SR, AR, DM, HR, TC, LR
D: Starting destination word
IR, SR, AR, DM, HR, TC, LR
Limitations
Description
Both S and D may be in the same data area, but their respective block areas
must not overlap. S and S+N must be in the same data area, as must D and D+N.
N must be BCD between 0000 and 6144.
When the execution condition is OFF, XFER(70) is not executed. When the
execution condition is ON, XFER(70) copies the contents of S, S+1, ..., S+N to
D, D+1, ..., D+N.
S
D
3 4 5 2
3 4 5 2
S+1
D+1
3 4 5 1
3 4 5 1
S+2
D+2
3 4 2 2
3 4 2 2
S+N
D+N
6 4 5 2
6 4 5 2
182
Data Movement
Section 5-16
Flags
ER:
N is not BCD between 0000 and 2000.
S and S+N or D and D+N are not in the same data area.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
5-16-5 DATA EXCHANGE – XCHG(73)
Ladder Symbols
Operand Data Areas
E1: Exchange word 1
IR, SR, AR, DM, HR, TC, LR
E2: Exchange word 2
XCHG(73)
@XCHG(73)
E1
E2
E1
E2
IR, SR, AR, DM, HR, TC, LR
Description
When the execution condition is OFF, XCHG(73) is not executed. When the
execution condition is ON, XCHG(73) exchanges the content of E1 and E2.
E1
E2
If you want to exchange content of blocks whose size is greater than 1 word, use
work words as an intermediate buffer to hold one of the blocks using XFER(70)
three times.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
5-16-6 SINGLE WORD DISTRIBUTE – DIST(80)
Operand Data Areas
S: Source data
Ladder Symbols
IR, SR, AR, DM, HR, TC, LR, #
DBs: Destination base word
IR, SR, AR, DM, HR, TC, LR
C: Control word (BCD)
DIST(80)
@DIST(80)
S
DBs
C
S
DBs
C
IR, SR, AR, DM, HR, TC, LR, #
Limitations
Description
C must be a BCD. If C≤6655, DBs must be in the same data area as DBs+C. If
C≥9000, DBs must be in the same data area as DBs+C–9000.
Depending on the value of C, DIST(80) will operate as a data distribution instruc-
tion or stack instruction. If C is between 0000 and 6655, DIST(80) will operate as
a data distribution instruction and copy the content of S to DBs+C. If the leftmost
digit of C is 9, DIST(80) will operate as a stack instruction and create a stack with
the number of words specified in the rightmost 3 digits of C.
Precautions
Stack operation will be unreliable if the specified stack length is different from the
length specified in the last execution of DIST(80) or COLL(81).
Data Distribution Operation When the execution condition is OFF, DIST(80) is not executed. When the
(C=0000 to 6655)
execution condition is ON, DIST(80) copies the content of S to DBs+C, i.e.,C is
added to DBs to determine the destination word.
S
DBs + C
3 4 5 2
3 4 5 2
183
Data Movement
Section 5-16
Stack Operation
(C=9000 to 9999)
When the execution condition is OFF, DIST(80) is not executed. When the
execution condition is ON, DIST(80) operates a stack from DBs to
DBs+C–9000. DBs is the stack pointer, so S is copied to the word indicated by
DBs and DBs is incremented by 1. The Negative Flag also changes.
Digits of C:
3 2 1 0
Specifies the stack length (000 to 999).
A value of 9 indicates stack operation.
Data can be added to the stack until it is full. DIST(80) is normally used together
with COLL(81), which can be set to read from the stack on a FIFO or LIFO basis.
Refer to 5-16-7 DATA COLLECT – COLL(81) for details.
Example of Stack Operation In the following example, the content of C (LR 10) is 9010, and DIST(80) is used
to write the numerical data #00FF to the 10-word stack from HR 20 to HR 29.
During the first cycle when IR 00001 is ON, the data is written to DBs+1 (HR 21)
and the stack pointer is incremented by 1. In the second cycle the data is written
to DBs+2 (HR 22) and the stack pointer is incremented, and so on.
00001
Address Instruction
Operands
00001
DIST(80)
# 00FF
HR 20
00000
00001
LD
DIST(80)
#
00FF
20
LR 10
HR
LR
10
After one
execution
After two
executions
HR 20
HR 20
Stack pointer
0 0 0 1
0 0 0 2
HR 21
HR 21
Stack pointer
incremented
0 0 F F
0 0 F F
HR 22
HR 22
0 0 F F
Stack area
HR 29
HR 29
Flags
ER:
EQ:
The content of C is not BCD or 6655<C<9000.
When C≤6655, DBs and DBs+C are not in the same data area.
When C≥9000, DBs and DBs+C–9000 are not in the same data area.
Indirectly addressed DM word is non-existent. (Content of ∗DM word is
not BCD, or the DM area boundary has been exceeded.)
ON when the content of S is zero; otherwise OFF.
184
Data Movement
Section 5-16
5-16-7 DATA COLLECT – COLL(81)
Operand Data Areas
SBs: Source base word
IR, SR, AR, DM, HR, TC, LR
C: Offset data (BCD)
Ladder Symbols
COLL(81)
@COLL(81)
SBs
C
SBs
C
IR, SR, AR, DM, HR, TC, LR, #
D: Destination word
D
D
IR, SR, AR, DM, HR, TC, LR
Limitations
Description
C must be a BCD. If C≤6655, SBs must be in the same data area as SBs+C. If the
leftmost digit of C is 8 or 9, DBs must be in the same data area as SBs+N (N=the
3 rightmost digits of C).
Depending on the value of C, COLL(81) will operate as a data collection instruc-
tion, FIFO stack instruction, or LIFO stack instruction. If C is between 0000 and
6655, COLL(81) will operate as a data collection instruction and copy the con-
tent of SBs+C to D.
If the leftmost digit of C is 9 , COLL(81) will operate as a FIFO stack instruction. If
the leftmost digit of C is 8, COLL(81) will operate as a LIFO stack instruction.
Both stack operations use a stack beginning at SBs with a length specified in the
rightmost 3 digits of C.
Precautions
Stack operation will be unreliable if the specified stack length is different from the
length specified in the last execution of DIST(80) or COLL(81).
Data Collection Operation
(C=0000 to 6655)
When the execution condition is OFF, COLL(81) is not executed. When the
execution condition is ON, COLL(81) copies the content of SBs + C to D, i.e., C is
added to SBs to determine the source word.
SBs + C
D
3 4 5 2
3 4 5 2
FIFO Stack Operation
(C=9000 to 9999)
When the execution condition is OFF, COLL(81) is not executed. When the
execution condition is ON, COLL(81) copies the data from the oldest word re-
corded in the stack to D. The stack pointer, SBs, is then decremented by 1.
Digits of C:
3 2 1 0
Specifies the stack length (000 to 999).
A value of 9 indicates FIFO stack operation.
COLL(81) can be used together with DIST(80). Refer to 5-16-6 SINGLE WORD
DISTRIBUTE – DIST(80) for details.
Note FIFO stands for First-In-First-Out.
185
Data Movement
Section 5-16
Example
In the following example, the content of C (HR 00) is 9010, and COLL(81) is used
to copy the oldest entries from a10-word stack (IR 001 to IR 010) to LR 20.
00001
Address Instruction
Operands
00001
DIST(80)
001
00000
00001
LD
COLL(81)
HR 00
LR 20
001
00
HR
LR
20
Before
execution
After one
execution
After two
executions
Stack pointer
decremented
Stack pointer
decremented
IR 001
IR 001
IR 001
Stack pointer
0
1
A
0
0
2
0
0
0
1
0
0
0
0
IR 002
IR 002
C D
IR 002
2
3
4
A
B
IR 003
C D
IR 003
IR 010
IR 003
B
Stack area
IR 010
IR 010
Output
LR 20
Output
LR 20
A
B
C D
1
2
3
4
LIFO Stack Operation
(C=8000 to 8999)
When the execution condition is OFF, COLL(81) is not executed. When the
execution condition is ON, COLL(81) copies the data most recently recorded in
the stack to D. The stack pointer, SBs, is then decremented by 1.
Digits of C:
3 2 1 0
Specifies the stack length (000 to 999).
A value of 8 indicates LIFO stack operation.
Data can be added to the stack until it is full. DIST(80)’s stack operation can be
used together with COLL(81)’s read stack operation. COLL(81) can be set to
read on a FIFO or LIFO basis. Refer to 5-16-6 SINGLE WORD DISTRIBUTE
(80) for details.
Note LIFO stands for Last-In-First-Out.
186
Data Movement
Section 5-16
Example
In the following example, the content of C (HR 00) is 8010, and COLL(81) is used
to copy the most recent entries from a 10-word stack (IR 001 to IR 010) to LR 20.
00001
Address Instruction
Operands
00001
COLL(81)
001
00000
00001
LD
COLL(81)
HR 00
LR 20
001
00
HR
LR
20
Before
execution
After one
execution
After two
executions
Stack pointer
decremented
Stack pointer
decremented
IR 001
IR 001
IR 001
Stack pointer
0
1
A
0
0
2
0
1
0
0
1
4
0
0
0
0
IR 002
IR 002
IR 002
2
3
4
2
3
IR 003
C D
IR 003
IR 003
B
Stack area
IR 010
IR 010
IR 010
Output
LR 20
Output
LR 20
1
2
3
4
A
B
C D
Flags
ER:
The content of C is not BCD or 6655<C<8000.
When C≤6655, DBs and DBs+C are not in the same data area.
When C≥8000, the beginning and end of the stack are not in the same
data area or the value of the stack pointer exceeds the length of the
stack.
Indirectly addressed DM word is non-existent. (Content of ∗DM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the transferred data is zero; otherwise OFF.
5-16-8 MOVE BIT – MOVB(82)
Operand Data Areas
S: Source word
IR, SR, AR, DM, HR, LR, #
Bi: Bit designator (BCD)
IR, SR, AR, DM, HR, TC, LR, #
D: Destination word
Ladder Symbols
MOVB(82)
@MOVB(82)
S
Bi
D
S
Bi
D
IR, SR, AR, DM, HR, LR
Limitations
The rightmost two digits and the leftmost two digits of Bi must each be between
00 and 15.
187
Data Movement
Section 5-16
Description
When the execution condition is OFF, MOVB(82) is not executed. When the
execution condition is ON, MOVB(82) copies the specified bit of S to the speci-
fied bit in D. The bits in S and D are specified by Bi. The rightmost two digits of Bi
designate the source bit; the leftmost two bits designate the destination bit.
Bit
15
Bit
00
0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1
Bi
S
Bi
1
1
2
0
1
Bit
15
Bit
00
2
0
1
MSB
LSB
0 1 0 1 0 1 0 0 0 1 1 1 0 0 0 1
Source bit (00 to 15)
Bit
15
Bit
00
Destination bit (00 to 15)
0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 1
D
Flags
ER:
C is not BCD, or it is specifying a non-existent bit (i.e., bit specification
must be between 00 and 15).
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
N:
ON if the leftmost bit of the content of word D is 1, otherwise OFF.
5-16-9 MOVE DIGIT – MOVD(83)
Operand Data Areas
S: Source word
Ladder Symbols
IR, SR, AR, DM, HR, TC, LR, #
Di: Digit designator (BCD)
IR, SR, AR, DM, HR, TC, LR, #
D: Destination word
MOVD(83)
@MOVD(83)
S
Di
D
S
Di
D
IR, SR, AR, DM, HR, TC, LR
Limitations
Description
The rightmost three digits of Di must each be between 0 and 3.
When the execution condition is OFF, MOVD(83) is not executed. When the
execution condition is ON, MOVD(83) copies the content of the specified digit(s)
in S to the specified digit(s) in D. Up to four digits can be transferred at one time.
The first digit to be copied, the number of digits to be copied, and the first digit to
receive the copy are designated in Di as shown below. Digits from S will be co-
pied to consecutive digits in D starting from the designated first digit and contin-
ued for the designated number of digits. If the last digit is reached in either S or D,
further digits are used starting back at digit 0.
Digit number: 3 2 1 0
First digit in S (0 to 3)
Number of digits (0 to 3)
0: 1 digit
1: 2 digits
2: 3 digits
3: 4 digits
First digit in D (0 to 3)
Not used.
188
Data Movement
Section 5-16
Digit Designator
The following show examples of the data movements for various values of Di.
Di: 0010
Di: 0030
S
D
S
D
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
Di: 0031
Di: 0023
S
D
D
S
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
Flags
ER:
At least one of the rightmost three digits of Di is not between 0 and 3.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
5-16-10 TRANSFER BITS – XFRB(62)
Operand Data Areas
C: Control word
IR, SR, AR, DM, TC, HR, LR, #
S: First source word
Ladder Symbols
XFRB(62)
@XFRB(62)
C
S
D
C
S
D
IR, SR, AR, DM, HR, TC, LR
D: First destination word
IR, SR, AR, DM, HR, LR
Limitations
Description
The specified source bits must be in the same data area.
The specified destination bits must be in the same data area.
When the execution condition is OFF, XFRB(62) is not executed. When the
execution condition is ON, XFRB(62) copies the specified source bits to the spe-
cified destination bits. The two rightmost digits of C specify the starting bits in S
and D and the leftmost two digits indicate the number of bits that will be copied.
C
MSB
LSB
First bit of S (0 to F)
First bit of D (0 to F)
Number of bits (01 to FF)
Note Up to 255 (FF) bits can be copied at one time.
189
Data Movement
Section 5-16
Example
In the following example, XFRB(62) is used to transfer 5 bits from IR 020 to
LR 21 when IR 00001 is ON. The starting bit in IR 020 is 0, and the starting bit in
LR 21 is 4, so IR 02000 to IR 02004 are copied to LR 2104 to LR 2108.
00001
Address Instruction
Operands
00001
XFRB(62)
#0540
00000
00001
LD
XFRB(62)
IR 020
LR 21
#
0540
020
21
LR
Bit
15
Bit
00
0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 1
S (IR 020)
D (LR 21)
Bit
15
Bit
00
0 1 0 0 0 1 0 1 0 1 1 1 0 0 0 1
Flags
ER:
The specified source bits are not all in the same data area.
The specified destination bits are not all in the same data area.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
5-16-11 EM BLOCK TRANSFER – XFR2(––)
Operand Data Areas
N: Number of words (BCD)
IR, SR, AR, DM, HR, TC, LR, #
S: Starting source word
Ladder Symbols
XFR2(––)
@XFR2(––)
N
S
D
N
S
D
IR, SR, AR, DM, HR, TC, LR, #
D: Starting destination word
IR, SR, AR, DM, HR, TC, LR, #
Limitations
Description
S and S+N must be in the same data area, as must D and D+N.
N must be BCD.
When the execution condition is OFF, XFR2(––) is not executed. When the
execution condition is ON, XFR2(––) copies the contents of S, S+1, ..., S+N to D,
D+1, ..., D+N. If a constant is used for S or D, the constant specifies an address in
the current EM bank.
Flags
ER:
N is not BCD.
S and S+N or D and D+N are not in the same data area.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
190
Data Movement
Section 5-16
Example
The following example copies the contents of the 300 words from DM 0000
through DM 0299 to EM 2000 through EM 2299 in the current EM bank.
Address Instruction
Operands
00000
00000
XFR2(––)
#0300
00200
00201
LD
XFR2(––)
DM 0000
#2000
#
0300
0000
2000
DM
#
5-16-12 EM BANK TRANSFER – BXF2(––)
Operand Data Areas
C: FIrst control word
Ladder Symbols
IR, SR, AR, DM, HR, TC, LR, #
S: Starting source word
BXF2(––)
@BXF2(––)
C
S
D
C
S
D
IR, SR, AR, DM, HR, TC, LR, #
D: Starting destination word
IR, SR, AR, DM, HR, TC, LR, #
Limitations
Description
The value in C+1 must be BCD from 1 to 6144.
S and S+N must be in the same data area, as must D and D+N.
When the execution condition is OFF, BXF2(––) is not executed. When the
execution condition is ON, BXF2(––) copies the contents of S, S+1, ..., S+N to D,
D+1, ..., D+N. If a constant is used for S or D, the constant specifies an address in
the source or destination EM bank specified in C.
Control Words
C contains the source and destination bank numbers if data is being transferred
to or from EM. The bank numbers are ignored unless a constant is used for S or
D.
C+1 contains the number of words to transfer and must be BCD (1 to 6144).
Control word
Bits
0 to 7
Function
C
Specifies the source bank number (00 to 02).
Specifies the destination bank number (00 to 02).
Specifies the number of words to transfer (1 to 6144).
8 to 15
0 to 15
C+1
Flags
ER:
N is not BCD.
S and S+N or D and D+N are not in the same data area.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
191
Data Comparison
Section 5-17
Example
The following example copies the contents of the 300 words from DM 0000
through DM 0299 to EM 2000 through EM 2299 in the EM bank 01.
(EM bank 00 isn’t used as the source because S isn’t a constant.)
Address Instruction
Operands
00000
00000
BXF2(––)
DM 1000
DM 0000
#2000
00200
00201
LD
BXF2(––)
DM
DM
#
1000
0000
2000
C: DM 1000
C+1: DM 1001
0
1
0
0
0
3
0
0
Number of words (300)
Source bank number (00)
Destination bank number (01)
5-17 Data Comparison
5-17-1 MULTI-WORD COMPARE – MCMP(19)
Operand Data Areas
TB1: First word of table 1
IR, SR, AR, DM, HR, TC, LR
TB2: First word of table 2
IR, SR, AR, DM, HR, TC, LR
R: Result word
Ladder Symbols
MCMP(19)
@MCMP(19)
TB1
TB2
R
TB1
TB2
R
IR, AR, DM, HR, TC, LR
Limitations
Description
TB1 and TB1+15 must be in the same data area, as must TB2 and TB2+15.
When the execution condition is OFF, MCMP(19) is not executed. When the
execution condition is ON, MCMP(19) compares the content of TB1 to TB2,
TB1+1 to TB2+1, TB1+2 to TB2+2, ..., and TB1+15 to TB2+15. If the first pair is
equal, the first bit in R is turned OFF, etc., i.e., if the content of TB1 equals the
content of TB2, bit 00 is turned OFF, if the content of TB1+1 equals the content of
TB2+1, bit 01 is turned OFF, etc. The rest of the bits in R will be turned ON.
Flags
ER:
One of the tables (i.e., TB1 through TB1+15, or TB2 through TB2+15)
exceeds the data area.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
192
Data Comparison
Section 5-17
Example
The following example shows the comparisons made and the results provided
for MCMP(19). Here, the comparison is made during each cycle when 00000 is
ON.
00000
Address Instruction
Operands
00000
MCMP(19)
100
00000
00001
LD
MCMP(19)
DM 0200
DM 0300
100
0200
0300
DM
DM
TB1: IR 100
TB2: DM 0200
R: DM 0300
IR 100
0100
DM 0200
0100
0200
0210
0400
0500
0600
0210
0800
0900
1000
0210
1200
1300
1400
0210
1600
DM 030000
DM 030001
DM 030002
DM 030003
DM 030004
DM 030005
DM 030006
DM 030007
DM 030008
DM 030009
DM 030010
DM 030011
DM 030012
DM 030013
DM 030014
DM 030015
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
1
IR 101
IR 102
IR 103
IR 104
IR 105
IR 106
IR 107
IR 108
IR 109
IR 110
IR 111
IR 112
IR 113
IR 114
IR 115
0200
DM 0201
DM 0202
DM 0203
DM 0204
DM 0205
DM 0206
DM 0207
DM 0208
DM 0209
DM 0210
DM 0211
DM 0212
DM 0213
DM 0214
DM 0215
0210
ABCD
ABCD
ABCD
ABCD
0800
0900
1000
ABCD
ABCD
ABCD
1400
0210
1212
5-17-2 COMPARE – CMP(20)
Ladder Symbols
Operand Data Areas
Cp1: First compare word
IR, SR, AR, DM, HR, TC, LR, #
Cp2: Second compare word
IR, SR, AR, DM, HR, TC, LR, #
CMP(20)
Cp1
Cp2
Limitations
Description
When comparing a value to the PV of a timer or counter, the value must be in
BCD.
When the execution condition is OFF, CMP(20) is not executed. When the
execution condition is ON, CMP(20) compares Cp1 and Cp2 and outputs the
result to the GR, EQ, and LE flags in the SR area.
Precautions
Placing other instructions between CMP(20) and the operation which accesses
the EQ, LE, and GR flags may change the status of these flags. Be sure to ac-
cess them before the desired status is changed.
CMP(20) cannot be used to compare signed binary data. Use CPS(––) instead.
Refer to 5-17-8 SIGNED BINARY COMPARE – CPS(––) for details.
193
Data Comparison
Section 5-17
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
LE:
GR:
ON if Cp1 equals Cp2.
ON if Cp1 is less than Cp2.
ON if Cp1 is greater than Cp2.
Flag
Address
25505
C1 < C2
OFF
C1 = C2
OFF
C1 > C2
ON
GR
EQ
LE
25506
25507
OFF
ON
ON
OFF
OFF
OFF
Example 1:
Saving CMP(20) Results
The following example shows how to save the comparison result immediately. If
the content of HR 09 is greater than that of 010, 00200 is turned ON; if the two
contents are equal, 00201 is turned ON; if content of HR 09 is less than that of
010, 00202 is turned ON. In some applications, only one of the three OUTs would
be necessary, making the use of TR 0 unnecessary. With this type of program-
ming, 00200, 00201, and 00202 are changed only when CMP(20) is executed.
TR
0
00000
CMP(20)
HR 09
010
25505
00200
Greater Than
25506
25507
00201
00202
Equal
Less Than
Address Instruction
Operands
00000
Address Instruction
Operands
00000
00001
00002
LD
00005
00006
00007
00008
00009
00010
00011
OUT
LD
00200
0
OUT
TR
0
TR
TR
CMP(20)
AND
OUT
LD
25506
00201
0
010
09
HR
TR
00003
00004
LD
0
AND
OUT
25507
00202
AND
25505
Example 2:
Obtaining Indications
during Timer Operation
The following example uses TIM, CMP(20), and the LE flag (25507) to produce
outputs at particular times in the timer’s countdown. The timer is started by turn-
ing ON 00000. When 00000 is OFF, TIM 010 is reset and the second two
CMP(20)s are not executed (i.e., executed with OFF execution conditions). Out-
put 00200 is produced after 100 seconds; output 00201, after 200 seconds; out-
put 00202, after 300 seconds; and output 00204, after 500 seconds.
194
Data Comparison
Section 5-17
The branching structure of this diagram is important in order to ensure that
00200, 00201, and 00202 are controlled properly as the timer counts down. Be-
cause all of the comparisons here use to the timer’s PV as reference, the other
operand for each CMP(20) must be in 4-digit BCD.
00000
TIM 010
#5000
500.0 s
CMP(20)
TIM 010
#4000
25507
00200
Output at 100 s.
00200
CMP(20)
TIM 010
#3000
25507
00201
Output at 200 s.
00201
CMP(20)
TIM 010
#2000
25507
Output at 300 s.
00202
TIM 010
00204
Output at 500 s.
Address Instruction
Operands
00000
Address Instruction
Operands
25507
00000
00001
LD
00007
00008
00009
00010
AND
TIM
010
OUT
00201
00201
#
5000
LD
00002
CMP(20)
CMP(20)
TIM
#
010
4000
TIM
#
010
2000
00003
00004
00005
00006
AND
25507
00200
00200
00011
00012
00013
00014
AND
OUT
LD
25507
00202
010
OUT
LD
TIM
CMP(20)
OUT
00204
TIM
#
010
3000
195
Data Comparison
Section 5-17
5-17-3 DOUBLE COMPARE – CMPL(60)
Ladder Symbols
Operand Data Areas
Cp1: First word of first compare word pair
IR, SR, AR, DM, HR, TC, LR
CMPL(60)
Cp1
Cp2: First word of second compare word pair
IR, SR, AR, DM, HR, TC, LR
Cp2
000 (fixed)
Limitations
Description
Cp1 and Cp1+1 must be in the same data area, as must Cp2 and Cp2+1.
When the execution condition is OFF, CMPL(60) is not executed. When the
execution condition is ON, CMPL(60) joins the 4-digit hexadecimal content of
Cp1+1 with that of Cp1, and that of Cp2+1 with that of Cp2 to create two 8-digit
hexadecimal numbers, Cp+1,Cp1 and Cp2+1,Cp2. The two 8-digit numbers are
then compared and the result is output to the GR, EQ, and LE flags in the SR
area.
Precautions
Placing other instructions between CMPL(60) and the operation which ac-
cesses the EQ, LE, and GR flags may change the status of these flags. Be sure
to access them before the desired status is changed.
CMPL(60) cannot be used to compare signed binary data. Use CPSL(––)
instead. Refer to 5-17-9 DOUBLE SIGNED BINARY COMPARE – CPSL(––) for
details.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
GR:
EQ:
LE:
ON if Cp1+1,Cp1 is greater than Cp2+1,Cp2.
ON if Cp1+1,Cp1 equals Cp2+1,Cp2.
ON if Cp1+1,Cp1 is less than Cp2+1,Cp2.
196
Data Comparison
Section 5-17
Example:
Saving CMPL(60) Results
The following example shows how to save the comparison result immediately. If
the content of HR 10, HR 09 is greater than that of 011, 010, then 00200 is turned
ON; if the two contents are equal, 00201 is turned ON; if content of HR 10, HR 09
is less than that of 011, 010, then 00202 is turned ON. In some applications, only
one of the three OUTs would be necessary, making the use of TR 0 unnecessary.
With this type of programming, 00200, 00201, and 00202 are changed only
when CMPL(60) is executed.
TR
0
00000
CMPL(60)
HR 09
010
---
25505
25506
00200
00201
Greater Than
Equal
25507
00202
Less Than
Address Instruction
Operands
00000
Address Instruction
Operands
00000
00001
00002
LD
00004
00005
00006
00007
00008
00009
00010
OUT
LD
00200
0
OUT
TR
0
TR
TR
CMPL(60)
AND
OUT
LD
25506
00201
0
HR
09
010
AND
OUT
25507
00202
00003
AND
25505
5-17-4 BLOCK COMPARE – BCMP(68)
Operand Data Areas
CD: Compare data
IR, SR, AR, DM, HR, TC, LR, #
CB: First comparison block word
IR, DM, HR, TC, LR
Ladder Symbols
BCMP(68)
@BCMP(68)
CD
CB
R
CD
CB
R
R: Result word
IR, SR, AR, DM, HR, TC, LR
Limitations
Each lower limit word in the comparison block must be less than or equal to the
upper limit.
197
Data Comparison
Section 5-17
Description
When the execution condition is OFF, BCMP(68) is not executed. When the
execution condition is ON, BCMP(68) compares CD to the ranges defined by a
block consisting of of CB, CB+1, CB+2, ..., CB+31. Each range is defined by two
words, the first one providing the lower limit and the second word providing the
upper limit. If CD is found to be within any of these ranges (inclusive of the upper
and lower limits), the corresponding bit in R is set. The comparisons that are
made and the corresponding bit in R that is set for each true comparison are
shown below. The rest of the bits in R will be turned OFF.
CB ≤ CD ≤ CB+1
Bit 00
Bit 01
Bit 02
Bit 03
Bit 04
Bit 05
Bit 06
Bit 07
Bit 08
Bit 09
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
CB+2 ≤ CD ≤ CB+3
CB+4 ≤ CD ≤ CB+5
CB+6 ≤ CD ≤ CB+7
CB+8 ≤ CD ≤ CB+9
CB+10 ≤ CD ≤ CB+11
CB+12 ≤ CD ≤ CB+13
CB+14 ≤ CD ≤ CB+15
CB+16 ≤ CD ≤ CB+17
CB+18 ≤ CD ≤ CB+19
CB+20 ≤ CD ≤ CB+21
CB+22 ≤ CD ≤ CB+23
CB+24 ≤ CD ≤ CB+25
CB+26 ≤ CD ≤ CB+27
CB+28 ≤ CD ≤ CB+29
CB+30 ≤ CD ≤ CB+31
Normally the first word in the range is less than the second, but if the first word in
the range is greater than the second, the corresponding bit in R will be turned
OFF when CD is outside of the range defined by the two words, as shown in the
following diagram.
CB
CB + 1
0000
9999
9999
CB+1
CB
0000
Flags
ER:
The comparison block (i.e., CB through CB+31) exceeds the data area.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
198
Data Comparison
Section 5-17
Example
The following example shows the comparisons made and the results provided
for BCMP(68). Here, the comparison is made during each cycle when 00000 is
ON.
00000
Address Instruction
Operands
00000
BCMP(68)
001
00000
00001
LD
BCMP(68)
HR 10
HR 05
001
10
HR
HR
05
CD 001
Lower limits
Upper limits
R: HR 05
001
0210
HR 10
0000
HR 11
0100
0200
0300
0400
0500
0600
0700
0800
0900
1000
1100
1200
1300
1400
1500
1600
HR 0500
HR 0501
HR 0502
HR 0503
HR 0504
HR 0505
HR 0506
HR 0507
HR 0508
HR 0509
HR 0510
HR 0511
HR 0512
HR 0513
HR 0514
HR 0515
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
HR 12
HR 14
HR 16
HR 18
HR 20
HR 22
HR 24
HR 26
HR 28
HR 30
HR 32
HR 34
HR 36
HR 38
HR 40
0101
0201
0301
0401
0501
0601
0701
0801
0901
1001
1101
1201
1301
1401
1501
HR 13
HR 15
HR 17
HR 19
HR 21
HR 23
HR 25
HR 27
HR 29
HR 31
HR 33
HR 35
HR 37
HR 39
HR 41
Compare data in IR 001
(which contains 0210)
with the given ranges.
5-17-5 TABLE COMPARE – TCMP(85)
Operand Data Areas
CD: Compare data
Ladder Symbols
IR, SR, AR, DM, HR, TC, LR, #
TB: First comparison table word
IR, AR, DM, HR, TC, LR
R: Result word
TCMP(85)
@TCMP(85)
CD
TB
R
CD
TB
R
IR, SR, AR, DM, HR, TC, LR
Limitations
Description
TB and TB+15 must be in the same data area.
When the execution condition is OFF, TCMP(85) is not executed. When the
execution condition is ON, TCMP(85) compares CD to the content of TB, TB+1,
TB+2, ..., and TB+15. If CD is equal to the content of any of these words, the
corresponding bit in R is set, e.g., if the CD equals the content of TB, bit 00 is
turned ON, if it equals that of TB+1, bit 01 is turned ON, etc. The rest of the bits in
R will be turned OFF.
Flags
ER:
The comparison table (i.e., TB through TB+15) exceeds the data area.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON if none of the words in the comparison table match CD, i.e., all of the
bits in R are OFF.
199
Data Comparison
Section 5-17
Example
The following example shows the comparisons made and the results provided
for TCMP(85). Here, the comparison is made during each cycle when 00000 is
ON.
Address Instruction
Operands
00000
00000
TCMP(85)
001
00000
00001
LD
TCMP(85)
HR 10
HR 05
001
10
HR
HR
05
CD: 001
Upper limits
R: HR 05
001 0210
HR 10
HR 11
HR 12
HR 13
HR 14
HR 15
HR 16
HR 17
HR 18
HR 19
HR 20
HR 21
HR 22
HR 23
HR 24
HR 25
0100
HR 0500
HR 0501
HR 0502
HR 0503
HR 0504
HR 0505
HR 0506
HR 0507
HR 0508
HR 0509
HR 0510
HR 0511
HR 0512
HR 0513
HR 0514
HR 0515
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0200
0210
0400
0500
0600
0210
0800
0900
1000
0210
1200
1300
1400
0210
1600
Compare the data in IR 001
with the given ranges.
5-17-6 AREA RANGE COMPARE – ZCP(88)
Operand Data Areas
CD: Compare data
Ladder Symbols
IR, SR, AR, DM, HR, TC, LR, #
LL: Lower limit of range
ZCP(88)
CD
@ZCP(88)
CD
LL
IR, SR, AR, DM, HR, TC, LR, #
UL: Upper limit of range
LL
UL
UL
IR, SR, AR, DM, HR, TC, LR, #
Limitations
Description
LL must be less than or equal to UL.
When the execution condition is OFF, ZCP(88) is not executed. When the
execution condition is ON, ZCP(88) compares CD to the range defined by lower
limit LL and upper limit UL and outputs the result to the GR, EQ, and LE flags in
the SR area. The resulting flag status is shown in the following table.
Flag status
Comparison result
GR (SR 25505) EQ (SR 25506) LE (SR 25507)
CD < LL
0
0
1
0
1
0
1
0
0
LL ≤ CD ≤ UL
UL < CD
200
Data Comparison
Section 5-17
Precautions
Placing other instructions between ZCP(88) and the operation which accesses
the EQ, LE, and GR flags may change the status of these flags. Be sure to ac-
cess them before the desired status is changed.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
LL is greater than UL.
ON if LL ≤ CD ≤ UL
ON if CD < LL.
EQ:
LE:
GR:
ON if CD > UL.
Example:
Saving ZCP(88) Results
The following example shows how to save the comparison result immediately. If
IR 100 > AB1F, IR 00200 is turned ON; if #0010 ≤ IR 100 ≤ AB1F, IR 00201 is
turned ON; if IR 100 < 0010, IR 00202 is turned ON.
TR
0
00000
ZCP(88)
IR 100
#0010
#AB1F
25505
25506
Greater Than
00200
(above range)
Equal
00201
(within range)
25507
Less Than
00202
(below range)
Address Instruction
Operands
00000
Address Instruction
Operands
00200
00000
00001
00002
LD
00004
00005
00006
00007
00008
00009
00010
OUT
LD
OUT
TR
0
TR
0
25506
00201
0
ZCP(88)
AND
OUT
LD
IR
#
100
0010
TR
#
AB1F
25505
AND
OUT
25507
00202
00003
AND
5-17-7 DOUBLE AREA RANGE COMPARE – ZCPL(––)
Operand Data Areas
CD: Compare data
IR, SR, AR, DM, HR, LR
LL: Lower limit of range
IR, SR, AR, DM, HR, LR
UL: Upper limit of range
IR, SR, AR, DM, HR, LR
Ladder Symbols
ZCPL(––)
CD
LL
UL
Limitations
The 8-digit value in LL+1,LL must be less than or equal to UL+1,UL.
CD and CD+1 must be in the same data area, as must LL and LL+1, and UL and
UL+1.
201
Data Comparison
Section 5-17
Description
When the execution condition is OFF, ZCPL(––) is not executed. When the
execution condition is ON, ZCPL(––) compares the 8-digit value in CD, CD+1 to
the range defined by lower limit LL+1,LL and upper limit UL+1,UL and outputs
the result to the GR, EQ, and LE flags in the SR area. The resulting flag status is
shown in the following table.
Flag status
Comparison result
GR
(SR 25505)
EQ
(SR 25506)
LE
(SR 25507)
CD , CD+1< LL+1,LL
0
0
1
0
1
0
1
0
0
LL+1,LL ≤ CD, CD+1 ≤ UL+1,UL
UL+1,UL < CD, CD+1
Precautions
Flags
Placing other instructions between ZCPL(––) and the operation which accesses
the EQ, LE, and GR flags may change the status of these flags. Be sure to ac-
cess them before the desired status is changed.
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
LL+1,LL is greater than UL+1,UL.
ON if LL+1,LL ≤ CD, CD+1 ≤ UL+1,UL
ON if CD, CD+1 < LL+1,LL.
EQ:
LE:
GR:
ON if CD, CD+1 > UL+1,UL.
Example
Refer to 5-17-6 AREA RANGE COMPARE – ZCP(88) for an example. The only
difference between ZCP(88) and ZCPL(––) is the number of digits in the com-
parison data.
5-17-8 SIGNED BINARY COMPARE – CPS(––)
Operand Data Areas
Cp1: First compare word
IR, SR, AR, DM, HR, TC, LR, #
Cp2: Second compare word
IR, SR, AR, DM, HR, TC, LR, #
Third operand: Set to 000.
---
Ladder Symbols
CPS(––)
Cp1
Cp2
000
Description
When the execution condition is OFF, CPS(––) is not executed. When the
execution condition is ON, CPS(––) compares the 16-bit (4-digit) signed binary
contents in Cp1 and Cp2 and outputs the result to the GR, EQ, and LE flags in the
SR area.
Note 1. Refer to page 27 for details on 16-bit signed binary data.
2. Refer to 5-17-2 Compare – CMP(20) for details on saving comparison re-
sults.
Precautions
Placing other instructions between CPS(––) and the operation which accesses
the EQ, LE, and GR flags may change the status of these flags. Be sure to ac-
cess them before the desired status is changed.
202
Data Comparison
Section 5-17
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
LE:
GR:
ON if Cp1 equals Cp2.
ON if Cp1 is less than Cp2.
ON if Cp1 is greater than Cp2.
Flag status
Comparison result
GR (SR 25505) EQ (SR 25506) LE (SR 25507)
Cp1 < Cp2
Cp1 = Cp2
Cp1 > Cp2
0
0
1
0
1
0
1
0
0
5-17-9 DOUBLE SIGNED BINARY COMPARE – CPSL(––)
Operand Data Areas
Cp1: First compare word
IR, SR, AR, DM, HR, TC, LR
Cp2: Second compare word
IR, SR, AR, DM, HR, TC, LR
Third operand: Set to 000.
---
Ladder Symbols
CPSL(––)
Cp1
Cp2
000
Limitations
Description
Cp1 and Cp1+1 must be in the same data area, as must Cp2 and Cp2+1.
When the execution condition is OFF, CPSL(––) is not executed. When the
execution condition is ON, CPSL(––) compares the 32-bit (8-digit) signed binary
contents in Cp1+1, Cp1 and Cp2+1, Cp2 and outputs the result to the GR, EQ,
and LE flags in the SR area.
Note 1. Refer to page 27 for details on 32-bit signed binary data.
2. Refer to 5-17-2 Compare – CMP(20) for details on saving comparison re-
sults.
Precautions
Flags
Placing other instructions between CPSL(––) and the operation which accesses
the EQ, LE, and GR flags may change the status of these flags. Be sure to ac-
cess them before the desired status is changed.
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
LE:
GR:
ON if Cp1+1, Cp1 equals Cp2+1, Cp2.
ON if Cp1+1, Cp1 is less than Cp2+1, Cp2.
ON if Cp1+1, Cp1 is greater than Cp2+1, Cp2.
Flag status
Comparison result
GR (SR 25505) EQ (SR 25506) LE (SR 25507)
Cp1+1, Cp1 < Cp2+1, Cp2
Cp1+1, Cp1 = Cp2+1, Cp2
Cp1+1, Cp1 > Cp2+1, Cp2
0
0
1
0
1
0
1
0
0
203
Data Conversion
Section 5-18
5-18 Data Conversion
The conversion instructions convert word data that is in one format into another
format and output the converted data to specified result word(s). Conversions
are available to convert between binary (hexadecimal) and BCD, to 7-segment
display data, to ASCII, and between multiplexed and non-multiplexed data. All of
these instructions change only the content of the words to which converted data
is being moved, i.e., the content of source words is the same before and after
execution of any of the conversion instructions.
5-18-1 BCD-TO-BINARY – BIN(23)
Ladder Symbols
Operand Data Areas
S: Source word (BCD)
IR, SR, AR, DM, HR, TC, LR
R: Result word
BIN(23)
@BIN(23)
S
R
S
R
IR, SR, AR, DM, HR, LR
Description
When the execution condition is OFF, BIN(23) is not executed. When the execu-
tion condition is ON, BIN(23) converts the BCD content of S into the numerically
equivalent binary bits, and outputs the binary value to R. Only the content of R is
changed; the content of S is left unchanged.
S
BCD
R
Binary
BIN(23) can be used to convert BCD to binary so that displays on the Program-
ming Console or any other programming device will appear in hexadecimal rath-
er than decimal. It can also be used to convert to binary to perform binary arith-
metic operations rather than BCD arithmetic operations, e.g., when BCD and
binary values must be added.
Flags
ER:
The content of S is not BCD.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the result is zero.
25402 is always OFF.
N:
204
Data Conversion
Section 5-18
5-18-2 DOUBLE BCD-TO-DOUBLE BINARY – BINL(58)
Ladder Symbols
Operand Data Areas
S: First source word (BCD)
BINL(58)
@BINL(58)
IR, SR, AR, DM, HR, TC, LR
R: First result word
S
R
S
R
IR, SR, AR, DM, HR, LR
Description
When the execution condition is OFF, BINL(58) is not executed. When the
execution condition is ON, BINL(58) converts an eight-digit number in S and S+1
into 32-bit binary data, and outputs the converted data to R and R+1.
S + 1
S
BCD
R + 1
R
Binary
Flags
ER:
The contents of S and/or S+1 words are not BCD.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the result is zero.
25402 is always OFF.
N:
5-18-3 BINARY-TO-BCD – BCD(24)
Ladder Symbols
Operand Data Areas
S: Source word (binary)
IR, SR, AR, DM, HR, LR
R: Result word
BCD(24)
@BCD(24)
S
R
S
R
IR, SR, AR, DM, HR, LR
Description
BCD(24) converts the binary (hexadecimal) content of S into the numerically
equivalent BCD bits, and outputs the BCD bits to R. Only the content of R is
changed; the content of S is left unchanged.
Binary
S
R
BCD
BCD(24) can be used to convert binary to BCD so that displays on the Program-
ming Console or any other programming device will appear in decimal rather
than hexadecimal. It can also be used to convert to BCD to perform BCD arith-
metic operations rather than binary arithmetic operations, e.g., when BCD and
binary values must be added.
205
Data Conversion
Section 5-18
Note If the content of S exceeds 270F, the converted result would exceed 9999 and
BCD(24) will not be executed. When the instruction is not executed, the content
of R remains unchanged.
Signed Binary Data
BCD(24) cannot be used to convert signed binary data directly to BCD. To con-
vert signed binary data, first determine whether the data is positive or negative. If
it is positive, BCD(24) can be used to convert the data to BCD. If it is negative,
use the 2’s COMPLEMENT – NEG(––) instruction to convert the data to un-
signed binary before executing BCD(24). Refer to page 27 for details on signed
binary data.
Flags
ER:
S is greater than 270F.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the result is zero.
5-18-4 DOUBLE BINARY-TO-DOUBLE BCD – BCDL(59)
Ladder Symbols
Operand Data Areas
S: First source word (binary)
IR, SR, AR, DM, HR, LR
R: First result word
BCDL(59)
@BCDL(59)
S
R
S
R
IR, SR, AR, DM, HR, LR
Limitations
Description
If the content of S exceeds 05F5E0FF, the converted result would exceed
99999999 and BCDL(59) will not be executed. When the instruction is not
executed, the content of R and R+1 remain unchanged.
S and S+1 must be in the same data area as must R and R+1.
BCDL(59) converts the 32-bit binary content of S and S+1 into eight digits of
BCD data, and outputs the converted data to R and R+1.
S + 1
S
Binary
R + 1
R
BCD
Signed Binary Data
BCD(24) cannot be used to convert signed binary data directly to BCD. To con-
vert signed binary data, first determine whether the data is positive or negative. If
it is positive, BCD(24) can be used to convert the data to BCD. If it is negative,
use the DOUBLE 2’s COMPLEMENT – NEGL(––) instruction to convert the data
to unsigned binary before executing BCD(24). Refer to page 27 for details on
signed binary data.
Flags
ER:
Content of R and R+1 exceeds 99999999.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the result is zero.
206
Data Conversion
Section 5-18
5-18-5 HOURS-TO-SECONDS – SEC(65)
Operand Data Areas
S: Beginning source word (BCD)
IR, SR, AR, DM, HR, TC, LR
R: Beginning result word (BCD)
IR, SR, AR, DM, HR, TC, LR
000: Set to 000.
Ladder Symbols
SEC(65)
@SEC(65)
S
R
S
R
000
000
---
Limitations
Description
S and S+1 must be within the same data area. R and R+1 must be within the
same data area. S and S+1 must be BCD and must be in the proper hours/min-
utes/seconds format.
SEC(65) is used to convert time notation in hours/minutes/seconds to an equiv-
alent in just seconds.
For the source data, the seconds are designated in bits 00 through 07 and the
minutes are designated in bits 08 through 15 of S. The hours are designated in
S+1. The maximum is thus 9,999 hours, 59 minutes, and 59 seconds.
The result is output to R and R+1. The maximum obtainable value is 35,999,999
seconds.
Flags
ER:
S and S+1 or R and R+1 are not in the same data area.
S and/or S+1 do not contain BCD.
Number of seconds and/or minutes exceeds 59.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
Turns ON when the result is zero.
Example
When 00000 is OFF (i.e., when the execution condition is ON), the following
instruction would convert the hours, minutes, and seconds given in HR 12 and
HR 13 to seconds and store the results in DM 0100 and DM 0101 as shown.
00000
Address Instruction
Operands
00000
SEC(65)
00000
00001
LD NOT
SEC(65)
HR 12
DM 0100
000
HR
DM
12
0100
000
HR 12
3
2
2
8
0
1
7
5
2,815 hrs, 32 min, 07 s
HR 13
DM 0100
DM 0101
5
1
9
0
2
1
7
3
10,135,927 s
207
Data Conversion
Section 5-18
5-18-6 SECONDS-TO-HOURS – HMS(66)
Operand Data Areas
S: Beginning source word (BCD)
IR, SR, AR, DM, HR, TC, LR
R: Beginning result word (BCD)
IR, SR, AR, DM, HR, TC, LR
000: Set to 000.
Ladder Symbols
HMS(66)
@HMS(66)
S
R
S
R
000
000
---
Limitations
Description
S and S+1 must be within the same data area. R and R+1 must be within the
same data area. S and S+1 must be BCD and must be between 0 and
35,999,999 seconds.
HMS(66) is used to convert time notation in seconds to an equivalent in hours/
minutes/seconds.
The number of seconds designated in S and S+1 is converted to hours/minutes/
seconds and placed in R and R+1.
For the results, the seconds is placed in bits 00 through 07 and the minutes is
placed in bits 08 through 15 of R. The hours is placed in R+1. The maximum will
be 9,999 hours, 59 minutes, and 59 seconds.
Flags
ER:
S and S+1 or R and R+1 are not in the same data area.
S and/or S+1 do not contain BCD or exceed 36,000,000 seconds.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
Turns ON when the result is zero.
Example
When 00000 is OFF (i.e., when the execution condition is ON), the following
instruction would convert the seconds given in HR 12 and HR 13 to hours, min-
utes, and seconds and store the results in DM 0100 and DM 0101 as shown.
00000
Address Instruction
Operands
00000
HMS(66)
00000
00001
LD NOT
HMS(66)
HR 12
DM 0100
000
HR
DM
12
0100
000
HR 12
5
1
9
0
2
1
7
3
10,135,927 s
HR 13
DM 0100
DM 0101
3
2
2
8
0
1
7
5
2,815 hrs, 32 min, 07 s
208
Data Conversion
Section 5-18
5-18-7 4-TO-16/8-TO-256 DECODER – MLPX(76)
Operand Data Areas
S: Source word
IR, SR, AR, DM, HR, TC, LR
C: Control word
Ladder Symbols
MLPX(76)
@MLPX(76)
S
C
R
S
C
R
IR, SR, AR, DM, HR, TC, LR, #
R: First result word
IR, SR, AR, DM, HR, LR
Limitations
When the leftmost digit of C is 0, the rightmost two digits of C must each be be-
tween 0 and 3.
When the leftmost digit of C is 1, the rightmost two digits of C must each be be-
tween 0 and 1.
All result words must be in the same data area.
Description
Depending on the value of C, MLPX(76) operates as a 4-bit to 16-bit decoder or
an 8-bit to 256-bit decoder.
4-bit to 16-bit Decoder
MLPX(76) operates as a 4-bit to 16-bit decoder when the leftmost digit of C is 0.
The hexadecimal value of the digits in S are used to specify bits in up to 4 result
words. The specified bit in each result word is turned on, and the other 15 bits in
each word are turned off.
When the execution condition is OFF, MLPX(76) is not executed. When the
execution condition is ON, MLPX(76) converts up to four, four-bit hexadecimal
digits from S into decimal values from 0 to 15, each of which is used to indicate a
bit position. The bit whose number corresponds to each converted value is then
turned ON in a result word. If more than one digit is specified, then one bit will be
turned ON in each of consecutive words beginning with R. (See examples, be-
low.)
Control Word
The digits of C are set as shown below. Set the leftmost digit of C to 0 to specify
4-bit to 16-bit decoding.
Digit number: 3 2 1 0
Specifies the first digit to be converted (0 to 3)
Number of digits to be converted (0 to 3)
0: 1 digit
1: 2 digits
2: 3 digits
3: 4 digits
Not used. Set to 0.
A value of 0 specifies 4-bit to 16-bit decoding.
209
Data Conversion
Section 5-18
Some example C values and the digit-to-word conversions that they produce
are shown below.
C: 0010
C: 0030
S
S
R
R
0
1
2
3
0
1
2
3
R + 1
R + 1
R + 2
R + 3
C: 0031
C: 0023
S
S
R
R
0
1
2
3
0
1
2
3
R + 1
R + 2
R + 1
R + 2
R + 3
The following is an example of a one-digit decode operation from digit number 1
of S, i.e., here C would be 0001.
Source word
C
Bit C (i.e., bit number 12) turned ON.
First result word
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
The first digit and the number of digits to be converted are designated in C. If
more digits are designated than remain in S (counting from the designated first
digit), the remaining digits will be taken starting back at the beginning of S. The
final word required to store the converted result (R plus the number of digits to be
converted) must be in the same data area as R, e.g., if two digits are converted,
the last word address in a data area cannot be designated; if three digits are con-
verted, the last two words in a data area cannot be designated.
8-bit to 256-bit Decoder
Control Word
MLPX(76) operates as an 8-bit to 256-bit decoder when the leftmost digit of C is
set to 1. The hexadecimal value of the two bytes in S are used to specify a bit in
one or two groups of 16 consecutive result words (256 bits). The specified bit in
each group is turned on, and the other 255 bits in the group are turned off.
The digits of C are set as shown below. Set the leftmost digit of C to 1 to specify
8-bit to 256-bit decoding.
Digit number: 3 2 1 0
Specifies the first byte to be converted (0 or 1).
0: Rightmost byte
1: Leftmost byte
Number of bytes to be converted (0 or 1).
0: 1 byte
1: 2 bytes
Not used. Set to 0.
A value of 1 specifies 8-bit to 256-bit decoding.
210
Data Conversion
Section 5-18
The 4 possible C values and the conversions that they produce are shown be-
low. (In S, 0 indicates the rightmost byte and 1 indicates the leftmost byte.)
C: 1000
C: 1001
S
S
R to R+15
R+16 to R+31
R to R+15
R+16 to R+31
0
1
0
1
C: 1010
C: 1011
S
S
R to R+15
R to R+15
0
1
0
1
R+16 to R+31
R+16 to R+31
The following is an example of a one-byte decode operation from the rightmost
byte of S (C would be 1000 in this case).
Source word
Bit 2C (i.e., bit number 12 in
the third word) turned ON.
2
C
Bit
15
Bit
00
Bit
15
Bit Bit
00 15
Bit Bit
00 15
Bit
00
. . .
. . .
. . .
R+1
. . .
R
0 0 0
0 0 0
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
0 0 0
R+15
R+2
Flags
ER:
Undefined control word.
The result words are not all in the same data area.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
211
Data Conversion
Section 5-18
Example:
4-bit to 16-bit Decoding
The following program converts three digits of data from LR 20 to bit positions
and turns ON the corresponding bits in three consecutive words starting with
HR 10.
00000
Address Instruction
Operands
00000
MLPX(76)
DM 0020
#0021
00000
00001
LD
MLPX(76)
LR
#
20
0021
10
HR 10
HR
S: LR 20
R: HR 10
R+1: HR 11
R+2: HR 12
0
DM 00
DM 01
DM 02
DM 03
DM 04
DM 05
DM 06
DM 07
DM 08
DM 09
DM 10
DM 11
DM 12
DM 13
DM 14
DM 15
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
HR 1000
HR 1001
HR 1002
HR 1003
HR 1004
HR 1005
HR 1006
HR 1007
HR 1008
HR 1009
HR 1010
HR 1011
HR 1012
HR 1013
HR 1014
HR 1015
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
HR 1100
HR 1101
HR 1102
HR 1103
HR 1104
HR 1105
HR 1106
HR 1107
HR 1108
HR 1109
HR 1110
HR 1111
HR 1112
HR 1113
HR 1114
HR 1115
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
HR 1200
HR 1201
HR 1202
HR 1203
HR 1204
HR 1205
HR 1206
HR 1207
HR 1208
HR 1209
HR 1210
HR 1211
HR 1212
HR 1213
HR 1214
HR 1215
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
Not
Converted
1
1
1
1
0
1
1
0
0
0
0
0
15
6
1
2
3
0
5-18-8 16-TO-4/256-TO-8 ENCODER – DMPX(77)
Operand Data Areas
S: First source word
Ladder Symbols
IR, SR, AR, DM, HR, TC, LR
R: Result word
DMPX(77)
@DMPX(77)
S
R
C
S
R
C
IR, SR, AR, DM, HR, LR
C: Control Word
IR, SR, AR, DM, HR, TC, LR, #
Limitations
When the leftmost digit of C is 0, the rightmost two digits of C must each be be-
tween 0 and 3.
When the leftmost digit of C is 1, the rightmost two digits of C must each be be-
tween 0 and 1.
All source words must be in the same data area.
Description
Depending on the value of C, MLPX(76) operates as a 16-bit to 4-bit encoder or
an 256-bit to 8-bit encoder.
212
Data Conversion
Section 5-18
16-bit to 4-bit Encoder
DMPX(77) operates as a 16-bit to 4-bit encoder when the leftmost digit of C is 0.
When the execution condition is OFF, DMPX(77) is not executed. When the
execution condition is ON, DMPX(77) determines the position of the highest ON
bit in S, encodes it into single-digit hexadecimal value corresponding to the bit
number, then transfers the hexadecimal value to the specified digit in R. The dig-
its to receive the results are specified in C, which also specifies the number of
digits to be encoded.
Control Word
The digits of C are set as shown below. Set the leftmost digit of C to 0 to specify
16-bit to 4-bit encoding.
Digit number: 3 2 1 0
Specifies the first digit in R to receive converted data (0 to 3).
Number of words to be converted (0 to 3).
0: 1 word
1: 2 words
2: 3 words
3: 4 words
Not used. Set to 0.
A value of 0 specifies 16-bit to 4-bit encoding.
Some example C values and the word-to-digit conversions that they produce
are shown below.
C: 0011
C: 0030
R
R
S
0
1
2
3
0
1
2
3
S
S + 1
S + 1
S + 2
S + 3
C: 0013
C: 0032
R
R
0
S
S
0
1
2
3
1
2
3
S + 1
S + 2
S + 3
S + 1
The following is an example of a one-digit encode operation to digit number 1 of
R, i.e., here C would be 0001.
First source word
0
0
0
1
0
0
0
1
0
0
0
1
0
1
1
0
C transferred to indicate bit number 12 as
the highest ON bit.
Result word
C
Up to four digits from four consecutive source words starting with S may be en-
coded and the digits written to R in order from the designated first digit. If more
digits are designated than remain in R (counting from the designated first digit),
the remaining digits will be placed at digits starting back at the beginning of R.
The final word to be converted (S plus the number of digits to be converted) must
be in the same data area as SB.
213
Data Conversion
Section 5-18
256-bit to 8-bit Encoder
DMPX(77) operates as a 256-bit to 8-bit encoder when the leftmost digit of C is
set to 1.
When the execution condition is OFF, DMPX(77) is not executed. When the
execution condition is ON, DMPX(77) determines the position of the highest
(leftmost) ON bit in the group of 16 source words from S to S+15 or S+16 to
S+31, encodes it into a two-digit hexadecimal value corresponding to the loca-
tion of the bit among the 256 bits in the group, then transfers the hexadecimal
value to the specified byte in R. The byte to receive the result is specified in C,
which also specifies the number of bytes to be encoded.
Control Word
The digits of C are set as shown below. Set the leftmost digit of C to 1 to specify
256-bit to 8-bit decoding.
Digit number: 3 2 1 0
Specifies the first byte in R to receive converted data (0 or 1).
0: Rightmost byte
1: Leftmost byte
Number of bytes to be encoded (0 or 1).
0: 1 byte
1: 2 bytes
Not used. Set to 0.
A value of 1 specifies 256-bit to 8-bit encoding.
Three possible C values and the conversions that they produce are shown be-
low. (In R, 0 indicates the rightmost byte and 1 indicates the leftmost byte.)
C: 1000
C: 1010
C: 1011
R
R
R
S to S+15
S to S+15
S+16 to S+31
S to S+15
S+16 to S+31
0
1
0
1
0
1
S+16 to S+31
The following is an example of a one-byte encode operation to the rightmost byte
of R (C would be 1000 in this case).
Bit
15
Bit Bit
00 15
Bit
00
Bit
15
Bit
00
. . .
S+14
. . .
. . .
S
0 0 0 0 1 1 1 1 1 1 1 0 1 1 0 0 0 1 1
0 1 0
1 1 1
0 0 0
S+15
Result word
Bit FB (bit 251 of 0 to 255) is the highest ON bit of the
16-word group, so FB is written to the rightmost bit of R.
F
B
Flags
ER:
Undefined control word.
The source words are not all in the same data area.
Content of the source words is zero. (There isn’t an ON bit in the source
words.)
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
214
Data Conversion
Section 5-18
Example:
16-bit to 4-bit Encoding
When 00000 is ON, the following diagram encodes IR words 010 and 011 to the
first two digits of HR 20 and then encodes LR 10 and 11 to the last two digits of
HR 20. Although the status of each source word bit is not shown, it is assumed
that the bit with status 1 (ON) shown is the highest bit that is ON in the word.
00000
Address Instruction
Operands
00000
DMPX(77)
010
00000
00001
LD
DMPX(77)
HR 20
#0010
010
20
HR
#
0010
DMPX(77)
LR 10
00002
DMPX(77)
LR
HR
#
10
20
HR 20
#0012
0012
IR 010
IR 011
01100
:
01000
:
01011
01012
: :
1
0
:
01109
01110
: :
1
0
:
HR 20
Digit 0
Digit 1
Digit 2
Digit 3
01015
0
01115
0
B
9
1
8
LR 10
LR 11
LR 1100
:
LR 1000
LR 1001 1
LR 1002 0
LR 1108
LR 1109
: :
1
: :
: :
:
:
0
:
LR 1015 0
LR 1115
0
5-18-9 7-SEGMENT DECODER – SDEC(78)
Operand Data Areas
S: Source word (binary)
Ladder Symbols
IR, SR, AR, DM, HR, TC, LR
Di: Digit designator
SDEC(78)
@SDEC(78)
S
Di
D
S
Di
D
IR, SR, AR, DM, HR, TC, LR, #
D: First destination word
IR, SR, AR, DM, HR, LR
Limitations
Description
Di must be within the values given below
All destination words must be in the same data area.
When the execution condition is OFF, SDEC(78) is not executed. When the
execution condition is ON, SDEC(78) converts the designated digit(s) of S into
the equivalent 8-bit, 7-segment display code and places it into the destination
word(s) beginning with D.
215
Data Conversion
Section 5-18
Any or all of the digits in S may be converted in sequence from the designated
first digit. The first digit, the number of digits to be converted, and the half of D to
receive the first 7-segment display code (rightmost or leftmost 8 bits) are desig-
nated in Di. If multiple digits are designated, they will be placed in order starting
from the designated half of D, each requiring two digits. If more digits are desig-
nated than remain in S (counting from the designated first digit), further digits will
be used starting back at the beginning of S.
Digit Designator
The digits of Di are set as shown below.
Digit number: 3 2 1 0
Specifies the first digit to receive converted data (0 to 3).
Number of digits to be converted (0 to 3)
0: 1 digit
1: 2 digits
2: 3 digits
3: 4 digits
First half of D to be used.
0: Rightmost 8 bits (1st half)
1: Leftmost 8 bits (2nd half)
Not used; set to 0.
Some example Di values and the 4-bit binary to 7-segment display conversions
that they produce are shown below.
Di: 0011
Di: 0030
S digits
S digits
D
D
0
1
2
3
0
1
2
3
1st half
2nd half
1st half
2nd half
D+1
1st half
2nd half
Di: 0112
Di: 0130
S digits
D
S digits
0
D
0
1
2
3
1st half
2nd half
1st half
2nd half
1
2
3
D+1
D+1
1st half
2nd half
1st half
2nd half
D+2
1st half
2nd half
216
Data Conversion
Section 5-18
Example
The following example shows the data to produce an 8. The lower case letters
show which bits correspond to which segments of the 7-segment display. The
table underneath shows the original data and converted code for all hexadeci-
mal digits.
a
Di
S
D
Bit 00
or
bit 08
f
b
c
g
d
0
1
1
1
1
1
1
1
0
a
b
c
d
e
f
0
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0
1
0
0
0
0
0
1
0
1
1
1
1
0
1
1
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
e
1: Second digit
0
1
2
3
x10
x10
x10
x10
0
1
2
3
0
0
0
0
0
1
0
1
1
1
1
0
1
1
8
0: One digit
g
Bit 07
or
bit 15
0 or 1:
bits 00 through 07 or
08 through 15.
Not used.
Original data
Bits
Converted code (segments)
Display
Digit
–
g
f
e
d
c
b
a
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
0
1
0
0
1
1
1
1
1
0
0
1
1
1
1
0
0
1
0
0
1
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
0
1
0
1
1
Flags
ER:
Incorrect digit designator, or data area for destination exceeded
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
217
Data Conversion
Section 5-18
5-18-10 ASCII CONVERT – ASC(86)
Operand Data Areas
S: Source word
IR, SR, AR, DM, HR, TC, LR
Di: Digit designator
Ladder Symbols
ASC(86)
@ASC(86)
S
Di
D
S
Di
D
IR, SR, AR, DM, HR, TC, LR, #
D: First destination word
IR, SR, AR, DM, HR, LR
Limitations
Description
Di must be within the values given below
All destination words must be in the same data area.
When the execution condition is OFF, ASC(86) is not executed. When the
execution condition is ON, ASC(86) converts the designated digit(s) of S into the
equivalent 8-bit ASCII code and places it into the destination word(s) beginning
with D.
Any or all of the digits in S may be converted in order from the designated first
digit. The first digit, the number of digits to be converted, and the half of D to re-
ceive the first ASCII code (rightmost or leftmost 8 bits) are designated in Di. If
multiple digits are designated, they will be placed in order starting from the des-
ignated half of D, each requiring two digits. If more digits are designated than
remain in S (counting from the designated first digit), further digits will be used
starting back at the beginning of S.
Refer to Appendix I for a table of extended ASCII characters.
The digits of Di are set as shown below.
Digit number: 3 2 1 0
Digit Designator
Specifies the first digit to be converted (0 to 3).
Number of digits to be converted (0 to 3)
0: 1 digit
1: 2 digits
2: 3 digits
3: 4 digits
First half of D to be used.
0: Rightmost 8 bits (1st half)
1: Leftmost 8 bits (2nd half)
Parity
0: none,
1: even,
2: odd
218
Data Conversion
Section 5-18
Some examples of Di values and the 4-bit binary to 8-bit ASCII conversions that
they produce are shown below.
Di: 0011
Di: 0030
S
D
S
D
0
0
1
2
3
1st half
2nd half
1st half
2nd half
1
2
3
D+1
1st half
2nd half
Di: 0112
Di: 0130
S
D
S
0
1
2
3
D
0
1
2
3
1st half
2nd half
1st half
2nd half
D+1
D+1
1st half
2nd half
1st half
2nd half
D+2
1st half
2nd half
Parity
The leftmost bit of each ASCII character (2 digits) can be automatically adjusted
for either even or odd parity. If no parity is designated, the leftmost bit will always
be zero.
When even parity is designated, the leftmost bit will be adjusted so that the total
number of ON bits is even, e.g., when adjusted for even parity, ASCII “31”
(00110001) will be “B1” (10110001: parity bit turned ON to create an even num-
ber of ON bits); ASCII “36” (00110110) will be “36” (00110110: parity bit turned
OFF because the number of ON bits is already even). The status of the parity bit
does not affect the meaning of the ASCII code.
When odd parity is designated, the leftmost bit of each ASCII character will be
adjusted so that there is an odd number of ON bits.
Flags
ER:
Incorrect digit designator, or data area for destination exceeded.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
5-18-11 ASCII-TO-HEXADECIMAL – HEX(––)
Operand Data Areas
S: First source word
IR, SR, AR, DM, HR, TC, LR
Di: Digit designator
Ladder Symbols
HEX(––)
@HEX(––)
S
Di
D
S
Di
D
IR, SR, AR, DM, HR, TC, LR
D: Destination word
IR, SR, AR, DM, HR, LR
219
Data Conversion
Section 5-18
Limitations
Di must be within the values given below.
All source words must be in the same data area.
Bytes in the source words must contain the ASCII code equivalent of hexadeci-
mal values, i.e., 30 to 39 (0 to 9), 41 to 46 (A to F), or 61 to 66 (a to f).
Description
When the execution condition is OFF, HEX(––) is not executed. When the
execution condition is ON, HEX(––) converts the designated byte(s) of ASCII
code from the source word(s) into the hexadecimal equivalent and places it into
D.
Up to 4 ASCII codes may be converted beginning with the designated first byte
of S. The converted hexadecimal values are then placed in D in order from the
designated digit. The first byte (rightmost or leftmost 8 bits), the number of bytes
to be converted, and the digit of D to receive the first hexadecimal value are
designated in Di. If multiple bytes are designated, they will be converted in order
starting from the designated half of S and continuing to S+1 and S+2, if
necessary.
If more digits are designated than remain in D (counting from the designated first
digit), further digits will be used starting back at the beginning of D. Digits in D
that do not receive converted data will not be changed.
Digit Designator
The digits of Di are set as shown below.
Digit number: 3 2 1 0
Specifies the first digit of D to be used (0 to 3).
Number of bytes to be converted (0 to 3)
0: 1 byte (2-digit ASCII code)
1: 2 bytes
2: 3 bytes
3: 4 bytes
First byte of S to be used.
st
nd
0: Rightmost 8 bits (1 byte)
1: Leftmost 8 bits (2 byte)
Parity
0: none
1: even
2: odd
220
Data Conversion
Section 5-18
Some examples of Di values and the 8-bit ASCII to 4-bit hexadecimal conver-
sions that they produce are shown below.
Di: 0011
Di: 0030
S
D
S
D
st
st
0
1
2
3
0
1
2
3
1
2
byte
byte
1
2
byte
nd
nd
byte
S+1
st
1
2
byte
nd
byte
Di: 0023
Di: 0133
S
D
S
st
st
D
0
1
2
3
1
byte
1
2
byte
nd
nd
0
1
2
3
2
byte
S+1
byte
S+1
st
st
1
2
byte
byte
1
2
byte
nd
nd
byte
S+2
st
1
2
byte
nd
byte
ASCII Code Table
The following table shows the ASCII codes before conversion and the hexadeci-
mal values after conversion. Refer to Appendix I for a table of ASCII characters.
Original data
Converted data
Digit Bits
ASCII Code
Bit status (See note.)
30
31
32
33
34
35
36
37
38
39
41
42
43
44
45
46
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Note The leftmost bit of each ASCII code is adjusted for parity.
Parity
The leftmost bit of each ASCII character (2 digits) is automatically adjusted for
either even or odd parity.
With no parity, the leftmost bit should always be zero. With odd or even parity, the
leftmost bit of each ASCII character should be adjusted so that there is an odd or
even number of ON bits.
If the parity of the ASCII code in S does not agree with the parity specified in Di,
the ER Flag (SR 25503) will be turned ON and the instruction will not be
executed.
221
Data Conversion
Section 5-18
Flags
ER:
Incorrect digit designator, or data area for destination exceeded.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
nd
st
Example
In the following example, the 2 byte of LR 10 and the 1 byte of LR 11 are con-
verted to hexadecimal values and those values are written to the first and se-
cond bytes of IR 010.
00000
Address Instruction
Operands
00000
@HEX(––)
LR 10
00000
00001
LD
@HEX(––)
HR 10
LR
10
10
010
HR
010
HR 10 0 1 1 0
LR 12 3 5 3 4
LR 11 4 2 3 2
LR 10 3 1 3 0
Conversion to
hexadecimal
010 0 0 2 1
5-18-12 SCALING – SCL(––)
Ladder Symbols
Operand Data Areas
S: Source word
SCL(––)
@SCL(––)
IR, SR, AR, DM, HR, TC, LR, #
P1: First parameter word
IR, SR, AR, DM, HR, TC, LR
R: Result word
S
P1
R
S
P1
R
IR, SR, AR, DM, HR, LR
Limitations
Description
P1 and P1+2 must be BCD.
P1 through P1+3 must be in the same data area.
P1+1 and P1+3 must not be set to the same value.
SCL(––) is used to linearly convert a 4-digit hexadecimal value to a 4-digit BCD
value. Unlike BCD(24), which converts a 4-digit hexadecimal value to its 4-digit
BCD equivalent (S → S
), SCL(––) can convert the hexadecimal value ac-
cording to a specified linear relationship. The conversion line is defined by two
points specified in the parameter words P1 to P1+3.
hex
BCD
When the execution condition is OFF, SCL(––) is not executed. When the execu-
tion condition is ON, SCL(––) converts the 4-digit hexadecimal value in S to the
4-digit BCD value on the line defined by points (P1, P1+1) and (P1+2, P1+3) and
places the result in R. The result is rounded off to the nearest integer. If the result
is less than 0000, then 0000 is written to R, and if the result is greater than 9999,
then 9999 is written to R.
222
Data Conversion
Section 5-18
The following table shows the functions and ranges of the parameter words:
Parameter
P1
Function
BCD point #1 (A )
Range
Comments
0000 to 9999
0000 to FFFF
---
Y
P1+1
Hex. point #1 (A )
Do not set P1+1=P1+3.
---
X
P1+2
BCD point #2 (B ) 0000 to 9999
Y
P1+3
Hex. point #2 (B )
0000 to FFFF
Do not set P1+3=P1+1.
X
The following diagram shows the source word, S, converted to D according to
the line defined by points (A , A ) and (B , B ).
Y
X
Y
X
Value after conversion
(BCD)
B
Y
R
A
Y
Value before conversion
(Hexadecimal)
A
S
B
X
X
The results can be calculated by first converting all values to BCD and then using
the following formula.
Results = B – [(B – A )/(B – A ) X (B – S)]
Y
Y
Y
X
X
X
Flags
ER:
The value in P1+1 equals that in P1+3.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
P1 and P1+3 are not in the same data area, or other setting error.
ON when the result, R, is 0000.
EQ:
Example
When 00000 is turned ON in the following example, the BCD source data in DM
0100 (#0100) is converted to hexadecimal according to the parameters in DM
0150 to DM 0153. The result (#0512) is then written to DM 0200.
00000
Address Instruction
Operands
00000
@SCL(––)
DM 0100
DM 0150
00000
00001
LD
@SCL(––)
DM
DM
DM
0100
0150
0200
DM 0200
DM 0150 0010
DM 0100 0100
DM 0200 0512
DM 0151 0005
DM 0152 0050
DM 0153 0019
223
Data Conversion
Section 5-18
5-18-13 COLUMN TO LINE – LINE(63)
Operand Data Areas
S: First word of 16 word source set
IR, SR, AR, DM, HR, TC, LR
C: Column bit designator (BCD)
IR, SR, AR, DM, HR, TC, LR, #
D: Destination word
Ladder Symbols
LINE(63)
@LINE(63)
S
C
D
S
C
D
IR, SR, AR, DM, HR, TC, LR
Limitations
Description
S and S+15 must be in the same data area.
C must be between #0000 and #0015.
When the execution condition is OFF, LINE(63) is not executed. When the
execution condition is ON, LINE(63) copies bit column C from the 16-word set (S
to S+15) to the 16 bits of word D (00 to 15).
C
Bit
15
Bit
00
0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1
S
1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1
0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1
1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1
S+1
S+2
S+3
.
.
.
.
.
.
.
.
.
.
.
.
0 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0
Bit
15
Bit
00
S+15
. . .
0
0 1 1 1
D
Flags
ER:
EQ:
The column bit designator C is not BCD, or it is specifying a non-existent
bit (i.e., bit specification must be between 00 and 15).
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
ON when the content of D is zero; otherwise OFF.
Example
The following example shows how to use LINE(63) to move bit column 07 from
the set (IR 100 to IR 115) to DM 0100.
00000
Address Instruction
Operands
00000
LINE(63)
100
00000
00001
LD
LINE(63)
#0007
100
0007
0100
DM 0100
#
DM
224
Data Conversion
Section 5-18
5-18-14 LINE TO COLUMN – COLM(64)
Operand Data Areas
S: Source word
Ladder Symbols
IR, SR, AR, DM, HR, TC, LR
D: First word of the destination set
IR, AR, DM, HR, TC, LR
COLM(64)
@COLM(64)
S
D
C
S
D
C
C: Column bit designator (BCD)
IR, SR, AR, DM, HR, TC, LR, #
Limitations
Description
D and D+15 must be in the same data area.
C must be between #0000 and #0015.
When the execution condition is OFF, COLM(64) is not executed. When the
execution condition is ON, COLM(64) copies the 16 bits of word S (00 to 15) to
the column of bits, C, of the 16-word set (D to D+15).
Bit
15
Bit
00
.
.
.
.
.
.
.
0
0 1 1 1
S
C
Bit
15
Bit
00
0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1
1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1
0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1
1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1
D
D+1
D+2
D+3
.
.
.
.
.
.
.
.
.
.
.
.
0 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0
D+15
Flags
ER:
EQ:
The bit designator C is not BCD, or it is specifying a non-existent bit (i.e.,
bit specification must be between 00 and 15).
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
ON when the content of S is zero; otherwise OFF.
Example
The following example shows how to use COLM(64) to move the contents of
word DM 0100 (00 to 15) to bit column 15 of the set (DM 0200 to DM 0215).
00000
Address Instruction
Operands
00000
COLM(64)
DM 0100
DM 0200
#0015
00000
00001
LD
COLM(64)
DM
DM
#
0100
0200
0015
225
Data Conversion
Section 5-18
5-18-15 2’S COMPLEMENT – NEG(––)
Ladder Symbols
Operand Data Areas
S: Source word
IR, SR, AR, DM, HR, TC, LR, #
R: Result word
NEG(––)
S
R
IR, SR, AR, DM, HR, LR
Description
Converts the four-digit hexadecimal content of the source word (S) to its 2’s
complement and outputs the result to the result word (R). This operation is effec-
tively the same as subtracting S from 0000 and outputting the result to R.
If the content of S is 0000, the content of R will also be 0000 after execution, and
EQ (SR 25506) will be turned on.
If the content of S is 8000, the content of R will also be 8000 after execution, and
UF (SR 25405) will be turned on.
Note Refer to page 27 for details on 16-bit signed binary data.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
UF:
N:
ON when the content of S is 0000; otherwise OFF.
ON when the content of S is 8000; otherwise OFF.
ON when bit 15 of R is set to 1; otherwise OFF.
Example
The following example shows how to use NEG(––) to find the 2’s complement of
the hexadecimal value 001F and output the result to DM 0020.
00000
Address Instruction
Operands
00000
NEG(––)
#001F
DM 0020
---
00000
00001
LD
NEG(––)
#
001F
0020
DM
#0000
#001F
–
Output to DM 0020.
#FFE1
226
Data Conversion
Section 5-18
5-18-16 DOUBLE 2’S COMPLEMENT – NEGL(––)
Ladder Symbols
Operand Data Areas
S: First source word
IR, SR, AR, DM, HR, TC, LR
R: First result word
NEGL(––)
S
R
IR, SR, AR, DM, HR, LR
---
Limitations
Description
S and S+1 must be in the same data area, as must R and R+1.
Converts the eight-digit hexadecimal content of the source words (S and S+1) to
its 2’s complement and outputs the result to the result words (R and R+1). This
operation is effectively the same as subtracting the eight-digit content S and S+1
from $0000 0000 and outputting the result to R and R+1.
If the content of S is 0000 0000, the content of R will also be 0000 0000 after
execution and EQ (SR 25506) will be turned on.
If the content of S is 8000 0000, the content of R will also be 8000 0000 after
execution and UF (SR 25405) will be turned on.
Note Refer to page 27 for details on 32-bit signed binary data.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
UF:
N:
ON when the content of S+1, S is 0000 0000; otherwise OFF.
ON when the content of S+1, S is 8000 0000; otherwise OFF.
ON when bit 15 of R+1 is set to 1; otherwise OFF.
Example
The following example shows how to use NEGL(––) to find the 2’s complement
of the hexadecimal value in LR 21, LR 20 (001F FFFF) and output the result to
DM 0021, DM 0020.
00000
Address Instruction
Operands
00000
NEG(––)
LR20
00000
00001
LD
NEGL(––)
DM 0020
---
LR
20
DM
0020
0000
0000
S+1: LR 21
001F
S: LR 20
FFFF
–
R+1: DM 0021 R: DM 0020
FFE0 0001
227
BCD Calculations
Section 5-19
5-19 BCD Calculations
The BCD calculation instructions – INC(38), DEC(39), ADD(30), ADDL(54),
SUB(31), SUBL(55), MUL(32), MULL(56), DIV(33), DIVL(57), FDIV(79), and
ROOT(72) – all perform arithmetic operations on BCD data.
For INC(38) and DEC(39) the source and result words are the same. That is, the
content of the source word is overwritten with the instruction result. All other
instructions change only the content of the words in which results are placed,
i.e., the contents of source words are the same before and after execution of any
of the other BCD calculation instructions.
STC(40) and CLC(41), which set and clear the carry flag, are included in this
group because most of the BCD operations make use of the Carry Flag (CY) in
their results. Binary calculations and shift operations also use CY.
The addition and subtraction instructions include CY in the calculation as well as
in the result. Be sure to clear CY if its previous status is not required in the cal-
culation, and to use the result placed in CY, if required, before it is changed by
execution of any other instruction.
5-19-1 INCREMENT – INC(38)
Ladder Symbols
Operand Data Areas
Wd: Increment word (BCD)
INC(38)
Wd
@INC(38)
Wd
IR, SR, AR, DM, HR, LR
Description
Flags
When the execution condition is OFF, INC(38) is not executed. When the execu-
tion condition is ON, INC(38) increments Wd, without affecting Carry (CY).
ER:
Wd is not BCD
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the incremented result is 0.
5-19-2 DECREMENT – DEC(39)
Ladder Symbols
Operand Data Areas
Wd: Decrement word (BCD)
DEC(39)
Wd
@DEC(39)
Wd
IR, SR, AR, DM, HR, LR
Description
Flags
When the execution condition is OFF, DEC(39) is not executed. When the
execution condition is ON, DEC(39) decrements Wd, without affecting CY.
DEC(39) works the same way as INC(38) except that it decrements the value
instead of incrementing it.
ER:
Wd is not BCD
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the decremented result is 0.
228
BCD Calculations
Section 5-19
5-19-3 SET CARRY – STC(40)
Ladder Symbols
STC(40)
@STC(40)
When the execution condition is OFF, STC(40) is not executed. When the
execution condition is ON, STC(40) turns ON CY (SR 25504).
Note Refer to Appendix C Error and Arithmetic Flag Operation for a table listing the
instructions that affect CY.
5-19-4 CLEAR CARRY – CLC(41)
Ladder Symbols
CLC(41)
@CLC(41)
When the execution condition is OFF, CLC(41) is not executed. When the
execution condition is ON, CLC(41) turns OFF CY (SR 25504).
CLEAR CARRY is used to reset (turn OFF) CY (SR 25504) to “0.”
CY is automatically reset to “0” when END(01) is executed at the end of each
cycle.
Note Refer to Appendix C Error and Arithmetic Flag Operation for a table listing the
instructions that affect CY.
5-19-5 BCD ADD – ADD(30)
Operand Data Areas
Au: Augend word (BCD)
IR, SR, AR, DM, HR, TC, LR, #
Ad: Addend word (BCD)
IR, SR, AR, DM, HR, TC, LR, #
R: Result word
Ladder Symbols
ADD(30)
@ADD(30)
Au
Ad
R
Au
Ad
R
IR, SR, AR, DM, HR, LR
Description
When the execution condition is OFF, ADD(30) is not executed. When the
execution condition is ON, ADD(30) adds the contents of Au, Ad, and CY, and
places the result in R. CY will be set if the result is greater than 9999.
Au + Ad + CY
CY
R
Flags
ER:
Au and/or Ad is not BCD.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
CY:
ON when there is a carry in the result.
ON when the result is 0.
EQ:
229
BCD Calculations
Section 5-19
Example
If 00002 is ON, the program represented by the following diagram clears CY with
CLC(41), adds the content of LR 25 to a constant (6103), places the result in DM
0100, and then moves either all zeros or 0001 into DM 0101 depending on the
status of CY (25504). This ensures that any carry from the last digit is preserved
in R+1 so that the entire result can be later handled as eight-digit data.
Address Instruction
Operands
00002
TR 0
00000
00001
00002
00003
LR
00002
CLC(41)
OUT
TR
0
CLC(41)
ADD(30)
ADD(30)
LR 25
LR
#
25
6103
#6103
DM
0100
DM 0100
00004
00005
AND
25504
25504
25504
MOV(21)
MOV(21)
#0001
#
0001
0101
0
DM
TR
DM 0101
00006
00007
00008
LD
AND NOT
MOV(21)
25504
MOV(21)
#0000
#
0000
0101
DM 0101
DM
Although two ADD(30) can be used together to perform eight-digit BCD addition,
ADDL(54) is designed specifically for this purpose.
5-19-6 DOUBLE BCD ADD – ADDL(54)
Operand Data Areas
Au: First augend word (BCD)
IR, SR, AR, DM, HR, TC, LR
Ad: First addend word (BCD)
IR, SR, AR, DM, HR, TC, LR
R: First result word
Ladder Symbols
ADDL(54)
@ADDL(54)
Au
Ad
R
Au
Ad
R
IR, SR, AR, DM, HR, LR
Limitations
Description
Each of the following pairs must be in the same data area: Au and Au+1, Ad and
Ad+1, and R and R+1.
When the execution condition is OFF, ADDL(54) is not executed. When the
execution condition is ON, ADDL(54) adds the contents of CY to the 8-digit val-
ue in Au and Au+1 to the 8-digit value in Ad and Ad+1, and places the result in R
and R+1. CY will be set if the result is greater than 99999999.
Au + 1
Ad + 1
Au
Ad
CY
R
+
CY
R + 1
230
BCD Calculations
Section 5-19
Flags
ER:
Au and/or Ad is not BCD.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
CY:
ON when there is a carry in the result.
ON when the result is 0.
EQ:
Example
When 00000 is ON, the following program adds two 12-digit numbers, the first
contained in LR 20 through LR 22 and the second in DM 0012. The result is
placed in LR 10 through HR 13. In the second addition (using ADD(30)), any
carry from the first addition is included. The carry from the second addition is
placed in HR 13 by using @ADB(50) (see 5-20-1 BINARY ADD – ADB(50)) with
two all-zero constants to indirectly place the content of CY into HR 13.
00000
Address Instruction
Operands
00000
CLC(41)
00000
00001
00002
LD
@ADDL(54)
LR 20
CLC(41)
@ADDL(54)
DM 0010
HR 10
LR
20
0010
10
DM
HR
@ADD(30)
LR 22
00003
00004
@ADD(30)
@ADB(50)
LR
22
0012
12
DM 0012
HR 12
DM
HR
@ADB(50)
#0000
#
0000
0000
13
#
#0000
HR
HR 13
5-19-7 BCD SUBTRACT – SUB(31)
Operand Data Areas
Mi: Minuend word (BCD)
IR, SR, AR, DM, HR, TC, LR, #
Su: Subtrahend word (BCD)
IR, SR, AR, DM, HR, TC, LR, #
R: Result word
Ladder Symbols
SUB(31)
@SUB(31)
Mi
Su
R
Mi
Su
R
IR, SR, AR, DM, HR, LR
Description
When the execution condition is OFF, SUB(31) is not executed. When the
execution condition is ON, SUB(31) subtracts the contents of Su and CY from
Mi, and places the result in R. If the result is negative, CY is set and the 10’s com-
plement of the actual result is placed in R. To convert the 10’s complement to the
true result, subtract the content of R from zero (see example below).
Mi – Su – CY
CY
R
Note The 2’s COMPLEMENT – NEG(––) instruction can be used to convert binary
data only, it cannot be used with BCD data.
231
BCD Calculations
Section 5-19
Flags
ER:
Mi and/or Su is not BCD.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
CY:
ON when the result is negative, i.e., when Mi is less than Su plus CY.
ON when the result is 0.
EQ:
Caution Be sure to clear the carry flag with CLC(41) before executing SUB(31) if its pre-
vious status is not required, and check the status of CY after doing a subtraction
with SUB(31). If CY is ON as a result of executing SUB(31) (i.e., if the result is
negative), the result is output as the 10’s complement of the true answer. To con-
vert the output result to the true value, subtract the value in R from 0.
!
Example
When 00002 is ON, the following ladder program clears CY, subtracts the con-
tents of DM 0100 and CY from the content of 010 and places the result in HR 20.
If CY is set by executing SUB(31), the result in HR 20 is subtracted from zero
(note that CLC(41) is again required to obtain an accurate result), the result is
placed back in HR 20, and HR 2100 is turned ON to indicate a negative result.
If CY is not set by executing SUB(31), the result is positive, the second subtrac-
tion is not performed, and HR 2100 is not turned ON. HR 2100 is programmed as
a self-maintaining bit so that a change in the status of CY will not turn it OFF
when the program is recycled.
In this example, differentiated forms of SUB(31) are used so that the subtraction
operation is performed only once each time 00002 is turned ON. When another
subtraction operation is to be performed, 00002 will need to be turned OFF for at
least one cycle (resetting HR 2100) and then turned back ON.
TR 0
00002
Address Instruction
Operands
00002
CLC(41)
00000
00001
00002
00003
LD
OUT
TR
0
@SUB(31)
010
First
subtraction
CLC(41)
@SUB(31)
DM 0100
HR 20
010
0100
20
DM
HR
25504
CLC(41)
00004
00005
00006
AND
25504
CLC(41)
@SUB(31)
@SUB(31)
#0000
Second
subtraction
#
0000
20
HR
HR
TR
HR 20
20
HR 20
00007
00008
00009
00010
LD
0
25504
AND
OR
25504
2100
2100
HR 2100
HR
HR
OUT
HR 2100
Turned ON to indicate
negative result.
The first and second subtractions for this diagram are shown below using exam-
ple data for 010 and DM 0100.
232
BCD Calculations
Section 5-19
Note The actual SUB(31) operation involves subtracting Su and CY from 10,000 plus
Mi. For positive results the leftmost digit is truncated. For negative results the
10s complement is obtained. The procedure for establishing the correct answer
is given below.
First Subtraction
IR 010 1029
DM 0100
CY – 0
HR 20 7577 (1029 + (10000 – 3452))
CY (negative result)
– 3452
1
Second Subtraction
0000
HR 20 –7577
CY
HR 20 2423 (0000 + (10000 – 7577))
CY (negative result)
–0
1
In the above case, the program would turn ON HR 2100 to indicate that the value
held in HR 20 is negative.
5-19-8 DOUBLE BCD SUBTRACT – SUBL(55)
Operand Data Areas
Mi: First minuend word (BCD)
IR, SR, AR, DM, HR, TC, LR
Su: First subtrahend word (BCD)
IR, SR, AR, DM, HR, TC, LR
R: First result word
Ladder Symbols
SUBL(55)
@SUBL(55)
Mi
Su
R
Mi
Su
R
IR, SR, AR, DM, HR, LR
Limitations
Description
Each of the following pairs must be in the same data area: Mi and Mi+1, Su and
Su+1, and R and R+1.
When the execution condition is OFF, SUBL(55) is not executed. When the
execution condition is ON, SUBL(55) subtracts CY and the 8-digit contents of Su
and Su+1 from the 8-digit value in Mi and Mi+1, and places the result in R and
R+1. If the result is negative, CY is set and the 10’s complement of the actual
result is placed in R. To convert the 10’s complement to the true result, subtract
the content of R from zero. Since an 8-digit constant cannot be directly entered,
use the BSET(71) instruction (see 5-16-3 BLOCK SET – BSET(71)) to create an
8-digit constant.
Mi + 1
Su + 1
Mi
Su
CY
R
–
CY
R + 1
Note The DOUBLE 2’s COMPLEMENT – NEGL(––) instruction can be used to con-
vert binary data only, it cannot be used with BCD data.
233
BCD Calculations
Section 5-19
Flags
ER:
Mi, M+1,Su, and Su+1 are not BCD.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
CY:
ON when the result is negative, i.e., when Mi is less than Su.
ON when the result is 0.
EQ:
The following example works much like that for single-word subtraction. In this
example, however, BSET(71) is required to clear the content of DM 0000 and
DM 0001 so that a negative result can be subtracted from 0 (inputting an 8-digit
constant is not possible).
Example
TR 0
00003
CLC(41)
@SUBL(55)
First
subtraction
HR 20
120
DM 0100
25504
@BSET(71)
#0000
DM 0000
DM 0001
CLC(41)
@SUBL(55)
Second
subtraction
DM 0000
DM 0100
DM 0100
25504
HR 2100
HR 2100
Turned ON to indicate
negative result.
Address Instruction
Operands
00003
Address Instruction
Operands
00000
00001
00002
00003
LD
00006
00007
CLC(41)
OUT
TR
0
@SUBL(55)
CLC(41)
@SUBL(55)
DM
0000
0100
0100
0
DM
DM
TR
HR
DM
20
120
00008
00009
00010
00011
LD
0100
25504
AND
OR
25504
2100
2100
00004
00005
AND
HR
HR
@BSET(71)
OUT
#
0000
0000
0001
DM
DM
234
BCD Calculations
Section 5-19
5-19-9 BCD MULTIPLY – MUL(32)
Operand Data Areas
Md: Multiplicand (BCD)
IR, SR, AR, DM, HR, TC, LR, #
Mr: Multiplier (BCD)
Ladder Symbols
MUL(32)
@MUL(32)
Md
Mr
R
Md
Mr
R
IR, SR, AR, DM, HR, TC, LR, #
R: First result word
IR, SR, AR, DM, HR LR
Limitations
Description
R and R+1 must be in the same data area.
When the execution condition is OFF, MUL(32) is not executed. When the
execution condition is ON, MUL(32) multiplies Md by the content of Mr, and
places the result In R and R+1.
Md
X
Mr
R +1
R
Example
When IR 00000 is ON with the following program, the contents of IR 013 and DM
0005 are multiplied and the result is placed in HR 07 and HR 08. Example data
and calculations are shown below the program.
00000
Address Instruction
Operands
00000
MUL(32)
013
00000
00001
LD
MUL(32)
DM 0005
HR 07
013
00005
07
DM
HR
Md: IR 013
3
0
3
3
5
6
5
0
Mr: DM 0005
X
0
2
R+1: HR 08
R: HR 07
9
0
0
0
8
0
Flags
ER:
Md and/or Mr is not BCD.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the result is 0.
235
BCD Calculations
Section 5-19
5-19-10 DOUBLE BCD MULTIPLY – MULL(56)
Operand Data Areas
Md: First multiplicand word (BCD)
IR, SR, AR, DM, HR, TC, LR
Mr: First multiplier word (BCD)
IR, SR, AR, DM, HR, TC, LR
R: First result word
Ladder Symbols
MULL(56)
@MULL(56)
Md
Mr
R
Md
Mr
R
IR, SR, AR, DM, HR LR
Limitations
Description
Md and Md+1 must be in the same data area, as must Mr and Mr+1.
R through R+3 must be in the same data area.
When the execution condition is OFF, MULL(56) is not executed. When the
execution condition is ON, MULL(56) multiplies the eight-digit content of Md and
Md+1 by the content of Mr and Mr+1, and places the result in R to R+3.
Md + 1
Mr + 1
Md
Mr
x
R + 3
R + 2
R + 1
R
Flags
ER:
Md, Md+1,Mr, or Mr+1 is not BCD.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the result is 0.
5-19-11 BCD DIVIDE – DIV(33)
Operand Data Areas
Dd: Dividend word (BCD)
IR, SR, AR, DM, HR, TC, LR, #
Dr: Divisor word (BCD)
Ladder Symbol
DIV(33)
Dd
Dr
R
IR, SR, AR, DM, HR, TC, LR, #
R: First result word (BCD)
IR, SR, AR, DM, HR, LR
Limitations
Description
R and R+1 must be in the same data area.
When the execution condition is OFF, DIV(33) is not executed and the program
moves to the next instruction. When the execution condition is ON, Dd is divided
by Dr and the result is placed in R and R + 1: the quotient in R and the remainder
in R + 1.
Remainder
Quotient
R+1
R
Dr
Dd
236
BCD Calculations
Section 5-19
Flags
ER:
EQ:
Dd or Dr is not in BCD or when Dr is #0000.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
ON when the result is 0.
Example
When IR 00000 is ON with the following program, the content of IR 020 is divided
by the content of HR 09 and the result is placed in DM 0017 and DM 0018. Exam-
ple data and calculations are shown below the program.
00000
Address Instruction
Operands
00000
DIV(33)
020
00000
00001
LD
DIV(33)
HR 09
DM 0017
020
09
HR
DM
0017
Quotient
Remainder
R: DM 0017
R + 1: DM 0018
1
1
5
0
0
0
0
2
Dd: IR 020
Dd: HR 09
3
4
5
2
0
0
0
3
5-19-12 DOUBLE BCD DIVIDE – DIVL(57)
Operand Data Areas
Dd: First dividend word (BCD)
IR, SR, AR, DM, HR, TC, LR
Dr: First divisor word (BCD)
IR, SR, AR, DM, HR, TC, LR
R: First result word
Ladder Symbols
DIVL(57)
@DIVL(57)
Dd
Dr
R
Dd
Dr
R
IR, SR, AR, DM, HR, LR
Limitations
Description
Dd and Dd+1 must be in the same data area, as must Dr and Dr+1.
R through R+3 must be in the same data area.
When the execution condition is OFF, DIVL(57) is not executed. When the
execution condition is ON, DIVL(57) the eight-digit content of Dd and D+1 is di-
vided by the content of Dr and Dr+1 and the result is placed in R to R+3: the quo-
tient in R and R+1, the remainder in R+2 and R+3.
Remainder
R+2
Quotient
R+3
R+1
R
Dr+1
Dr
Dd+1
Dd
Flags
ER:
Dr and Dr+1 contain 0.
Dd, Dd+1, Dr, or Dr+1 is not BCD.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the result is 0.
237
BCD Calculations
Section 5-19
5-19-13 FLOATING POINT DIVIDE – FDIV(79)
Operand Data Areas
Dd: First dividend word (BCD)
IR, SR, AR, DM, HR, TC, LR
Dr: First divisor word (BCD)
IR, SR, AR, DM, HR, TC, LR
R: First result word
Ladder Symbols
FDIV(79)
@FDIV(79)
Dd
Dr
R
Dd
Dr
R
IR, SR, AR, DM, HR, LR
Limitations
Description
Dr and Dr+1 cannot contain zero. Dr and Dr+1 must be in the same data area, as
must Dd and Dd+1; R and R+1.
–7
The dividend and divisor must be between 0.0000001 x 10
and
7
–7
7
0.9999999 x 10 . The results must be between 0.1 x 10 and 0.9999999 x 10 .
When the execution condition is OFF, FDIV(79) is not executed. When the
execution condition is ON, FDIV(79) divides the floating-point value in Dd and
Dd+1 by that in Dr and Dr+1 and places the result in R and R+1.
Quotient
R+1
R
Dr+1
Dr
Dd+1
Dd
To represent the floating point values, the rightmost seven digits are used for the
mantissa and the leftmost digit is used for the exponent, as shown below. The
mantissa is expressed as a value less than one, i.e., to seven decimal places.
First word
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
1
0
1
0
0
0
0
1
0
0
0
1
0
0
0
1
exponent (0 to 7)
sign of exponent
mantissa (leftmost 3 digits)
0: +
1: –
Second word
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
mantissa (leftmost 4 digits)
–2
= 0.1111111 x 10
Flags
ER:
Dr and Dr+1 contain 0.
Dd, Dd+1, Dr, or Dr+1 is not BCD.
–7
7
The result is not between 0.1 x 10 and 0.999999 x 10 .
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the result is 0.
238
BCD Calculations
Section 5-19
Example
The following example shows how to divide two whole four-digit numbers (i.e.,
numbers without fractions) so that a floating-point value can be obtained.
First the original numbers must be placed in floating-point form. Because the
numbers are originally without decimal points, the exponent will be 4 (e.g., 3452
4
would equal 0.3452 x 10 ). All of the moves are to place the proper data into con-
secutive words for the final division, including the exponent and zeros. Data
movements for Dd and Dd+1 are shown at the right below. Movements for Dr
and Dr+1 are basically the same. The original values to be divided are in DM
0000 and DM 0001. The final division is also shown.
239
BCD Calculations
Section 5-19
00000
@MOV(21)
#0000
HR 01
HR 00
0
0
0
0
HR 00
@MOV(21)
#0000
0000
HR 02
@MOV(21)
#4000
HR 01
HR 00
4
0
0
0
0
0
0
0
HR 01
@MOV(21)
#4000
4000
HR 03
DM 0000
@MOVD(83)
DM 0000
#0021
3
4
5
2
HR 01
HR 00
HR 01
4
4
3
4
5
0
0
0
0
0
00000
@MOVD(83)
DM 0000
#0300
DM 0000
4
3
5
2
HR 00
HR 01
3
HR 00
0
4
5
2
0
@MOVD(83)
DM 0001
#0021
HR 03
@MOVD(83)
DM 0001
#0300
HR 01
HR 00
4
4
3
4
5
7
2
9
0
0
0
0
HR 02
HR 03
HR 02
0
0
0
0
÷
@FDIV(79)
HR 00
DM 0003
DM 0002
2
4
3
6
9
6
2
0
HR 02
2
DM 0002
0.4369620 x 10
Address Instruction
Operands
Address Instruction
Operands
00000
00001
LD
00000
00006
00007
00008
00009
@MOVD(83)
@MOVD(83)
@MOVD(83)
@FDIV(79)
@MOV(21)
DM
0000
0300
00
#
0000
00
#
HR
HR
00002
00003
00004
00005
@MOV(21)
@MOV(21)
@MOV(21)
@MOVD(83)
#
0000
02
DM
#
0001
0021
03
HR
HR
#
4000
01
HR
DM
#
0001
0300
02
#
4000
03
HR
HR
HR
HR
DM
00
02
DM
#
0000
0021
01
0002
HR
240
BCD Calculations
Section 5-19
5-19-14 SQUARE ROOT – ROOT(72)
Ladder Symbols
Operand Data Areas
Sq: First source word (BCD)
IR, SR, AR, DM, HR, TC, LR
R: Result word
ROOT(72)
@ROOT(72)
Sq
R
Sq
R
IR, SR, AR, DM, HR, LR,
Limitations
Description
Sq and Sq+1 must be in the same data area.
When the execution condition is OFF, ROOT(72) is not executed. When the
execution condition is ON, ROOT(72) computes the square root of the eight-dig-
it content of Sq and Sq+1 and places the result in R. The fractional portion is trun-
cated.
R
Sq+1
Sq
Flags
ER:
Sq or Sq+1 is not BCD.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the result is 0.
Example
The following example shows how to take the square root of a four-digit number
and then round the result.
First the words to be used are cleared to all zeros and then the value whose
square root is to be taken is moved to Sq+1. The result, which has twice the num-
ber of digits required for the answer (because the number of digits in the original
value was doubled), is placed in DM 0102, and the digits are split into two differ-
ent words, the leftmost two digits to IR 011 for the answer and the rightmost two
digits to DM 0103 so that the answer in IR 011 can be rounded up if required. The
last step is to compare the value in DM 0103 so that IR 011 can be incremented
using the Greater Than flag.
241
BCD Calculations
Section 5-19
In this example, √6017 = 77.56, and 77.56 is rounded off to 78.
00000
@BSET(71)
#0000
DM 0101
DM 0100
0
0
0
0
7
0
0
0
0
DM 0100
DM 0101
0000
010
0000
@MOV(21)
010
6
6
0
1
DM 0101
DM 0101
0
DM 0100
@ROOT(72)
DM 0100
1
7
0
0
0
0
60170000= 77.56932
DM 0102
@MOV(21)
#0000
DM 0103
0
IR 011
011
0
0
0
0
0
0
0
@MOV(21)
#0000
0000
0000
DM 0103
@MOVD(83)
DM 0102
#0012
DM 0102
7
7
5
6
011
IR 011
7
DM 0103
@MOVD(83)
DM 0102
#0210
0
0
7
5
6
0
0
DM 0103
@CMP(20)
DM 0103
#4900
5600 > 4900
25505
IR 011
7
@INC(38)
011
0
0
8
Address Instruction
Operands
Address Instruction
Operands
00000
00001
LD
00000
00006
00007
00008
@MOVD(83)
@MOVD(83)
@CMP(20)
@BSET(71)
DM
0102
0012
011
#
0000
0100
0101
#
DM
DM
00002
00003
00004
00005
@MOV(21)
@ROOT(72)
@MOV(21)
@MOV(21)
DM
#
0102
0210
0103
010
DM
0101
DM
DM
DM
0100
0102
DM
#
0103
4900
00009
00010
LD
25505
#
0000
011
@INC(38)
011
#
0000
0103
DM
242
Binary Calculations
Section 5-20
5-20 Binary Calculations
Binary calculation instructions — ADB(50), SBB(51), MLB(52), DVB(53),
ADBL(––), SBBL(––), MBS(––), MBSL(––), DBS(––), and DBSL(––) — perform
arithmetic operations on hexadecimal data.
Four of these instructions (ADB(50), SBB(51), ADBL(––), and SBBL(––)) can
act on both normal and signed data, two (MLB(52) and DVB(53)) act only on nor-
mal data, and four (MBS(––), MBSL(––), DBS(––), and DBSL(––)) act only on
signed binary data.
The addition and subtraction instructions include CY in the calculation as well as
in the result. Be sure to clear CY if its previous status is not required in the cal-
culation, and to use the result placed in CY, if required, before it is changed by the
execution of any other instruction. STC(40) and CLC(41) can be used to control
CY. Refer to 5-19 BCD Calculations.
Signed binary addition and subtraction instructions use the underflow and over-
flow flags (UF and OF) to indicate whether the result exceeds the acceptable
range for 16-bit or 32-bit signed binary data. Refer to page 27 for details on
signed binary data.
5-20-1 BINARY ADD – ADB(50)
Operand Data Areas
Au: Augend word (binary)
IR, SR, AR, DM, HR, TC, LR, #
Ad: Addend word (binary)
IR, SR, AR, DM, HR, TC, LR, #
R: Result word
Ladder Symbols
ADB(50)
@ADB(50)
Au
Ad
R
Au
Ad
R
IR, SR, AR, DM, HR, LR
Description
When the execution condition is OFF, ADB(50) is not executed. When the
execution condition is ON, ADB(50) adds the contents of Au, Ad, and CY, and
places the result in R. CY will be set if the result is greater than FFFF.
Au + Ad + CY
CY
R
ADB(50) can also be used to add signed binary data. The overflow and under-
flow flags (SR 25404 and SR 25405) indicate whether the result has exceeded
the lower or upper limits of the 16-bit signed binary data range. Refer to page 27
for details on signed binary data.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
CY:
EQ:
OF:
UF:
N:
ON when the result is greater than FFFF.
ON when the result is 0.
ON when the result exceeds +32,767 (7FFF).
ON when the result is below –32,768 (8000).
ON when bit 15 of the result is set to 1.
243
Binary Calculations
Section 5-20
Example 1:
Adding Normal Data
The following example shows a four-digit addition with CY used to place either
#0000 or #0001 into R+1 to ensure that any carry is preserved.
Address Instruction
Operands
00000
TR 0
00000
00000
00001
00002
00003
LD
CLC(41)
OUT
TR
0
CLC(41)
ADB(50)
ADB(50)
010
010
0100
10
DM 0100
HR 10
DM
HR
= R
25504
25504
00004
00005
AND NOT
MOV(21)
25504
MOV(21)
#0000
#
0000
11
HR 11
= R+1
= R+1
HR
TR
MOV(21)
#0001
00006
00007
00008
LD
0
AND
25504
MOV(21)
HR 11
#
00001
11
HR
In the case below, A6E2 + 80C5 = 127A7. The result is a 5-digit number, so CY
(SR 25504) = 1, and the content of R + 1 becomes #0001.
Au: IR 010
A
8
2
6
E
2
5
7
Ad: DM 0100
+
0
C
R+1: HR 11
R: HR 10
7
0
0
0
1
A
Note The UF and OF flags would also be turned ON during this addition, but they can
be ignored since they are relevant only in the addition of signed binary data.
Example 2:
Adding Signed Binary Data
In the following example, ADB(50) is used to add two 16-bit signed binary val-
ues. (The 2’s complement is used to express negative values.)
The effective range for 16-bit signed binary values is –32,768 (8000) to +32,768
(7FFF). The overflow flag (OF: SR 25404) is turned ON if the result exceeds
+32,767 (7FFF) and the underflow flag (UF: SR 25405) is turned ON if the result
falls below –32,768 (8000).
Address Instruction
Operands
00000
00000
CLC(41)
00000
00001
00002
LD
CLC(41)
ADB(50)
ADB(50)
LR 20
LR
20
0010
0020
DM 0010
DM 0020
DM
DM
244
Binary Calculations
Section 5-20
In the case below, 25,321 +(–13,253) = 12,068 (62E9 + CC3B = 2F24). Neither
OF nor UF are turned ON.
Au: LR 20
6
2
E
9
B
4
Ad: DM 0010
+
C
C
3
Ad: DM 0010
2
F
2
Note The status of the CY flag can be ignored when adding signed binary data since it
is relevant only in the addition of normal hexadecimal values.
5-20-2 BINARY SUBTRACT – SBB(51)
Operand Data Areas
Mi: Minuend word (binary)
IR, SR, AR, DM, HR, TC, LR, #
Su: Subtrahend word (binary)
IR, SR, AR, DM, HR, TC, LR, #
R: Result word
Ladder Symbols
SBB(51)
@SBB(51)
Mi
Su
R
Mi
Su
R
IR, SR, AR, DM, HR, LR
Description
When the execution condition is OFF, SBB(51) is not executed. When the
execution condition is ON, SBB(51) subtracts the contents of Su and CY from Mi
and places the result in R. If the result is negative, CY is set and the 2’s comple-
ment of the actual result is placed in R.
Mi – Su – CY
CY
R
SBB(51) can also be used to subtract signed binary data. The overflow and un-
derflow flags (SR 25404 and SR 25405) indicate whether the result has exceed-
ed the lower or upper limits of the 16-bit signed binary data range. Refer to page
27 for details on signed binary data.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
CY:
EQ:
OF:
UF:
N:
ON when the result is negative, i.e., when Mi is less than Su plus CY.
ON when the result is 0.
ON when the result exceeds +32,767 (7FFF).
ON when the result is below –32,768 (8000).
ON when bit 15 of the result is set to 1.
245
Binary Calculations
Section 5-20
Example 1: Normal Data
The following example shows a four-digit subtraction with CY used to place ei-
ther #0000 or #0001 into R+1 to ensure that any carry is preserved.
Address Instruction
Operands
00001
TR 1
00001
00000
00001
00002
00003
LD
CLC(41)
OUT
TR
1
CLC(41)
SBB(51)
SBB(51)
001
001
20
LR20
LR
HR 21
= R
HR
21
25504
25504
00004
00005
AND NOT
MOV(21)
25504
MOV(21)
#0000
#
0000
22
HR 22
= R+1
= R+1
HR
TR
MOV(21)
#0001
00006
00007
00008
LD
1
AND
25504
MOV(21)
HR 22
#
0001
22
NEG(––)
HR21
HR
00009
NEG(––)
HR 21
HR
HR
21
21
In the case below, the content of LR 20 (#7A03) and CY are subtracted from
IR 001 (#F8C5). The result is stored in HR 21 and the content of HR 22 (#0000)
indicates that the result is positive.
If the result had been negative, CY would have been set, #0001 would have
been placed in HR 22, and the result would have been converted to its 2’s com-
pliment.
Mi: IR 001
F
8
C
5
Su: LR 20
–
–
CY = 0
(from CLC(41))
7
0
A
0
3
0
0
0
R+1: HR 22
R: HR 21
0
0
0
0
7
E
C
2
Note The status of the UF and OF flags can be ignored since they are relevant only in
the subtraction of signed binary data.
246
Binary Calculations
Section 5-20
Example 2:
Signed Binary Data
In the following example, SBB(51) is used to subtract one 16-bit signed binary
value from another. (The 2’s complement is used to express negative values).
The effective range for 16-bit signed binary values is –32,768 (8000) to +32,767
(7FFF). The overflow flag (OF: SR 25404) is turned ON if the result exceeds
+32,767 (7FFF) and the underflow flag (UF: SR 25405) is turned ON if the result
falls below –32,768 (8000).
Address Instruction
Operands
00000
00000
CLC(41)
00000
00001
00002
LD
CLC(41)
SBB(51)
SBB(51)
LR 20
LR
20
0010
0020
DM 0010
DM 0020
DM
DM
In the case shown below, 30,020 – (–15,238) = 45,258 (7544 – C47A =
60CA).The OF flag would be turned ON to indicate that this result exceeds the
upper limit of the 16-bit signed binary data range. (In other words, the result is a
positive value that exceeds 32,767 (7FFF), not a negative number expressed as
signed binary data.)
Mi: LR 20
7
5
4
4
Su: DM 0010
C
4
7
A
–
R: DM 0020
B
0
C
A
In the case shown below, –30,000 – 3,000 = –33,000 (8AD0 – 0BB8 = 7F18).The
UF flag would be turned ON to indicate that this result is below the lower limit of
16-bit signed binary data range. (In other words, the result is a negative number
below –32,768 (8000), not a positive number expressed as signed binary data.)
Mi: LR 20
8
0
A
D
0
8
Su: DM 0010
B
B
–
R: DM 0020
7
F
1
8
The absolute value of the true result (80E8=33,000) can be obtained by taking
the 2’s complement of 7F18 using NEG(––).
Note The status of the CY flag can be ignored when adding signed binary data since it
is relevant only in the addition of normal hexadecimal values.
247
Binary Calculations
Section 5-20
5-20-3 BINARY MULTIPLY – MLB(52)
Operand Data Areas
Md: Multiplicand word (binary)
IR, SR, AR, DM, HR, TC, LR, #
Mr: Multiplier word (binary)
IR, SR, AR, DM, HR, TC, LR, #
R: First result word
Ladder Symbols
MLB(52)
@MLB(52)
Md
Mr
R
Md
Mr
R
IR, SR, AR, DM, HR LR
Limitations
Description
R and R+1 must be in the same data area.
When the execution condition is OFF, MLB(52) is not executed. When the
execution condition is ON, MLB(52) multiplies the content of Md by the contents
of Mr, places the rightmost four digits of the result in R, and places the leftmost
four digits in R+1.
Md
X
Mr
R +1
R
Precautions
Flags
MLB(52) cannot be used to multiply signed binary data. Use MBS(––) instead.
Refer to 5-20-7 SIGNED BINARY MULTIPLY – MBS(––) for details.
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the result is 0.
N:
ON when bit 15 of R+1 is set to 1.
5-20-4 BINARY DIVIDE – DVB(53)
Operand Data Areas
Dd: Dividend word (binary)
IR, SR, AR, DM, HR, TC, LR, #
Dr: Divisor word (binary)
IR, SR, AR, DM, HR, TC, LR, #
R: First result word
Ladder Symbols
DVB(53)
@DVB(53)
Dd
Dr
R
Dd
Dr
R
IR, SR, AR, DM, HR LR
Description
When the execution condition is OFF, DVB(53) is not executed. When the
execution condition is ON, DVB(53) divides the content of Dd by the content of
Dr and the result is placed in R and R+1: the quotient in R, the remainder in R+1.
Quotient
R
Remainder
R + 1
Dr
Dd
248
Binary Calculations
Section 5-20
Precautions
DVB(53) cannot be used to divide signed binary data. Use DBS(––) instead. Re-
fer to 5-20-9 SIGNED BINARY DIVIDE – DBS(––) for details.
Flags
ER:
Dr contains 0.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the result is 0.
N:
ON when bit 15 of R is set to 1.
Example
Address Instruction
Operands
00000
00000
DVB(53)
001
00000
00001
LD
DVB(53)
LR 20
HR 05
001
0020
05
LR
HR
Dd: IR 001
1
0
0
F
7
3
Dr: LR 20
0
ꢁ
0
R+1: HR 06
R: HR 05
0
0
0
2
0
5
A
7
Remainder (2)
Quotient (1447)
5-20-5 DOUBLE BINARY ADD – ADBL(––)
Operand Data Areas
Au: First augend word (binary)
IR, SR, AR, DM, HR, LR
Ad: First addend word (binary)
IR, SR, AR, DM, HR, LR
R: First result word
Ladder Symbols
ADBL(––)
@ADBL(––)
Au
Ad
R
Au
Ad
R
IR, SR, AR, DM, HR, LR
Limitations
Description
Au and Au+1 must be in the same data area, as must Ad and Ad+1, and R and
R+1.
When the execution condition is OFF, ADBL(––) is not executed. When the
execution condition is ON, ADBL(––)) adds the eight-digit contents of Au+1 and
Au, the eight-digit contents of Ad+1 and Ad, and CY, and places the result in R
and R+1. CY will be set if the result is greater than FFFF FFFF.
Au + 1
Ad + 1
Au
Ad
CY
R
+
CY
R + 1
249
Binary Calculations
Section 5-20
ADBL(––) can also be used to add signed binary data. The overflow and under-
flow flags (SR 25404 and SR 25405) indicate whether the result has exceeded
the lower or upper limits of the 32-bit signed binary data range. Refer to page 27
for details on signed binary data.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
CY:
EQ:
OF:
UF:
N:
ON when the result is greater than FFFF FFFF.
ON when the result is 0.
ON when the result exceeds +2,147,483,647 (7FFF FFFF).
ON when the result is below –2,147,483,648 (8000 0000).
ON when bit 15 of R is set to 1.
Example 1: Normal Data
The following example shows an eight-digit addition with CY (SR 25504) used to
represent the status of the 9 digit.
th
Address Instruction
Operands
00000
00000
CLC(41)
00000
00001
00002
LD
CLC(41)
ADBL(––)
ADBL(––)
000
000
0020
21
DM 0020
LR 21
DM
LR
14020187 + 00A3F8C5 = 14A5FA4C
Au : 000
Au + 1 : 001
1
4
0
2
0
1
8
7
Ad + 1 : DM 0021
Ad : DM 0020
F
8
C
5
0
0
A
3
0
CY (Cleared with CLC(41))
CY (No carry)
+
R + 1 : LR 22
R : LR 21
1
4
A
5
F
A
4
C
0
Note The status of the UF and OF flags can be ignored since they are relevant only in
the addition of signed binary data.
Example 2:
Signed Binary Data
In the following example, ADBL(––) is used to add two 32-bit signed binary val-
ues and output the 32-bit signed binary result to R and R+1. (The 2’s comple-
ment is used to express negative values).
The effective range for 32-bit signed binary values is –2,147,483,648
(8000 0000) to +2,147,483,647 (7FFF FFFF). The overflow flag (OF: SR 25404)
is turned ON if the result exceeds +2,147,483,647 (7FFF FFFF) and the under-
flow flag (UF: SR 25405) is turned ON if the result falls below –2,147,483,648
(8000 0000).
Address Instruction
Operands
00000
00000
CLC(41)
00000
00001
00002
LD
CLC(41)
ADBL(––)
ADBL(––)
LR 20
LR
20
0010
0020
DM 0010
DM 0020
DM
DM
250
Binary Calculations
Section 5-20
In the case below, 1,799,100,099 + (–282,751,929) = 1,516,348,100
(6B3C167D + EF258C47 = 5A61A2C4). Neither OF nor UF are turned ON.
Au : LR 20
Au + 1 : LR 21
6
B
3
C
1
6
7
D
Ad + 1 : DM 0011
Ad : DM 0010
8
C
4
7
E
F
2
5
0
CY (Cleared with CLC(41))
+
R + 1 : DM 0021
R : DM 0020
5
A
6
1
A
2
C
4
0
0
UF (SR 25405)
OF (SR 25404)
Note The status of the CY flag can be ignored when adding signed binary data since it
is relevant only in the addition of normal hexadecimal values.
5-20-6 DOUBLE BINARY SUBTRACT – SBBL(––)
Operand Data Areas
Mi: First minuend word (binary)
IR, SR, AR, DM, HR, TC, LR
Su: First subtrahend word (binary)
IR, SR, AR, DM, HR, TC, LR
R: First result word
Ladder Symbols
SBBL(––)
@SBBL(––)
Mi
Su
R
Mi
Su
R
IR, SR, AR, DM, HR, LR
Limitations
Description
Mi and Mi+1 must be in the same data area, as must Su and Su+1, and R and
R+1.
When the execution condition is OFF, SBBL(––) is not executed. When the
execution condition is ON, SBBL(––) subtracts CY and the eight-digit value in Su
and Su+1 from the eight-digit value in Mi and Mi+1, and places the result in R and
R+1. If the result is negative, CY is set and the 2’s complement of the actual re-
sult is placed in R+1 and R. Use the DOUBLE 2’s COMPLEMENT instructions to
convert the 2’s complement to the true result.
Mi + 1
Su + 1
Mi
Su
CY
R
–
CY
R + 1
SBBL(––) can also be used to subtract signed binary data. The overflow and un-
derflow flags (SR 25404 and SR 25405) indicate whether the result has exceed-
ed the lower or upper limits of the 32-bit signed binary data range. Refer to page
27 for details on signed binary data.
251
Binary Calculations
Section 5-20
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
CY:
EQ:
OF:
UF:
N:
ON when the result is negative, i.e., when Mi is less than Su plus CY.
ON when the result is 0.
ON when the result exceeds +2,147,483,647 (7FFF FFFF).
ON when the result is below –2,147,483,648 (8000 0000).
ON when bit 15 of R+1 is set to 1.
Example 1: Normal Data
In this example, the eight-digit number in IR 002 and IR 001 is subtracted from
the eight-digit number in DM 0021 and DM 0020, and the result is output to LR 22
and LR 21. If the result is negative, CY (SR 25504) is turned ON.
Address Instruction
Operands
00000
00000
CLC(41)
00000
00001
00002
LD
CLC(41)
SBBL(––)
SBBL(––)
001
001
0020
21
DM 0020
LR 21
DM
LR
14020187 + 00A3F8C5 = 14A5FA4C
Au : 001
Au + 1 : 002
1
4
0
2
0
1
8
7
Ad + 1 : DM 0021
Ad : DM 0020
F
8
C
5
0
0
A
3
0
CY (Cleared with CLC(41))
CY (No carry)
–
R + 1 : LR 22
R : LR 21
1
3
5
E
0
8
C
2
0
Note The status of the UF and OF flags can be ignored since they are relevant only in
the subtraction of signed binary data.
Example 2:
Signed Binary Data
In the following example, SBBL(––) is used to subtract one 32-bit signed binary
value from another and output the 32-bit signed binary result to R and R+1.
The effective range for 32-bit signed binary values is –2,147,483,648
(8000 0000) to +2,147,483,647 (7FFF FFFF). The overflow flag (OF: SR 25404)
is turned ON if the result exceeds +2,147,483,647 (7FFF FFFF) and the under-
flow flag (UF: SR 25405) is turned ON is the result falls below –2,147,483,648
(8000 0000).
Address Instruction
Operands
00000
00000
CLC(41)
00000
00001
00002
LD
CLC(41)
SBBL(––)
SBBL(––)
001
001
0020
21
DM 0020
LR 21
DM
LR
252
Binary Calculations
Section 5-20
In the case below, 1,799,100,099 – (–282,751,929) = 2,081,851,958
(6B3C 167D – {EF25 8C47 – 1 0000 0000} = 7C16 8A36). Neither OF nor UF
are turned ON.
Au : 000
Au + 1 : 001
6
B
3
C
1
6
7
D
Ad + 1 : DM 0021
Ad : DM 0020
8
C
4
7
E
F
2
5
–
–
0
CY (Cleared with CLC(41))
R + 1 : LR 22
R : LR 21
7
C
1
6
8
A
3
6
0
0
UF (SR 25405)
OF (SR 25404)
Note The status of the CY flag can be ignored when adding signed binary data since it
is relevant only in the addition of normal hexadecimal values.
5-20-7 SIGNED BINARY MULTIPLY – MBS(––)
Operand Data Areas
Md: Multiplicand word
IR, SR, AR, DM, HR, TC, LR, #
Mr: Multiplier word
Ladder Symbols
MBS(––)
@MBS(––)
Md
Mr
R
Md
Mr
R
IR, SR, AR, DM, HR, TC, LR, #
R: First result word
IR, SR, AR, DM, HR LR
Limitations
Description
R and R+1 must be in the same data area.
MBS(––) multiplies the signed binary content of two words and outputs the
8-digit signed binary result to R+1 and R. The rightmost four digits of the result
are placed in R, and the leftmost four digits are placed in R+1. Refer to page 27
for details on signed binary data.
Md
X
Mr
R +1
R
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the result is 0000 0000, otherwise OFF.
ON when bit 15 of R+1 is set to 1.
N:
253
Binary Calculations
Section 5-20
Example
In the following example, MBS(––) is used to multiply the signed binary contents
of IR 001 with the signed binary contents of DM 0020 and output the result to
LR 21 and LR 22.
Address Instruction
Operands
00000
00000
MBS(––)
001
00000
00001
LD
MBS(––)
DM 0020
LR 21
001
0020
21
DM
LR
Md: 001
1
F
5
B
1
3
(5,553)
Mr: DM 0020
X
C
1
(–1,005)
R+1: LR 22
R: LR 21
F
F
A
A
D
8
2
3
(–5,580,765)
5-20-8 DOUBLE SIGNED BINARY MULTIPLY – MBSL(––)
Operand Data Areas
Md: First multiplicand word
IR, SR, AR, DM, HR, TC, LR
Mr: First multiplier word
IR, SR, AR, DM, HR, TC, LR
R: First result word
Ladder Symbols
MBSL(––)
@MBSL(––)
Md
Mr
R
Md
Mr
R
IR, SR, AR, DM, HR LR
Limitations
Description
Md and Md+1 must be in the same data area, as must Mr and Mr+1, and R
through R+3.
MBSL(––) multiplies the 32-bit (8-digit) signed binary data in Md+1 and Md with
the 32-bit signed binary data in Mr+1 and Mr, and outputs the 16-digit signed
binary result to R+3 through R. Refer to page 27 for details on signed binary
data.
Md + 1
Mr + 1
Md
Mr
x
R + 3
R + 2
R + 1
R
Flags
ER:
EQ:
N:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
ON when the result is zero (content of R+3 through R all zeroes), other-
wise OFF.
ON when bit 15 of R+3 is set to 1.
254
Binary Calculations
Section 5-20
Example
In the following example, MBSL(––) is used to multiply the signed binary con-
tents of IR 101 and IR 100 with the signed binary contents of DM 0021 and
DM 0020 and output the result to LR 24 through LR 21.
Address Instruction
Operands
00000
00000
MBSL(––)
100
00000
00001
LD
MBSL(––)
DM 0020
LR 21
100
0020
21
DM
LR
Md+1: IR 101
Md: IR 100
0
0
0
8
7
9
3
8
2
(555,320)
Mr+1: DM 0021
F
Mr: DM 0020
F
F
0
A
8
1
X
(–1,005,550)
R+3: LR 24
R+2: LR 23
R+1: LR 22
R: LR 21
(–558,402,026,000)
F
F
F
F
F
F
7
D
F
C
A
5
4
5
F
0
5-20-9 SIGNED BINARY DIVIDE – DBS(––)
Operand Data Areas
Dd: Dividend word
Ladder Symbols
IR, SR, AR, DM, HR, TC, LR, #
Dr: Divisor word
DBS(––)
@DBS(––)
Dd
Dr
R
Dd
Dr
R
IR, SR, AR, DM, HR, TC, LR, #
R: First result word
IR, SR, AR, DM, HR LR
Limitations
Description
R and R+1 must be in the same data area.
DBS(––) divides the signed binary content of Dd by the signed binary content of
Dr, and outputs the 8-digit signed binary result to R+1 and R. The quotient is
placed in R, and the remainder is placed in R+1. Refer to page 27 for details on
signed binary data.
Quotient
R
Remainder
R + 1
Dr
Dd
Flags
ER:
Dr contains 0.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the content of R (the quotient) is 0000, otherwise OFF.
ON when bit 15 of R is set to 1.
N:
255
Binary Calculations
Section 5-20
Example
In the following example, DBS(––) is used to divide the signed binary contents of
IR 001 with the signed binary contents of DM 0020 and output the result to LR 21
and LR 22.
Address Instruction
Operands
00000
00000
DBS(––)
001
00000
00001
LD
DBS(––)
DM 0020
LR 21
001
0020
21
DM
LR
Dd: IR 001
D
0
D
D
A
A
(–8,742)
Dr: DM 0020
0
1
÷
(26)
R+1: LR 22
R: LR 21
F
F
F
A
F
E
B
0
(–336 and –6)
Remainder (–6)
Quotient (–336)
5-20-10DOUBLE SIGNED BINARY DIVIDE – DBSL(––)
Operand Data Areas
Dd: Dividend word (binary)
IR, SR, AR, DM, HR, TC, LR
Dr: Divisor word (binary)
IR, SR, AR, DM, HR, TC, LR
R: First result word
Ladder Symbols
DBSL(––)
@DBSL(––)
Dd
Dr
R
Dd
Dr
R
IR, SR, AR, DM, HR LR
Limitations
Description
Dd and Dd+1 must be in the same data area, as must Dr and Dr+1, and R
through R+3.
DBS(––) divides the 32-bit (8-digit) signed binary data in Dd+1 and Dd by the
32-bit signed binary data in Dr+1 and Dr, and outputs the 16-digit signed binary
result to R+3 through R. The quotient is placed in R+1 and R, and the remainder
is placed in R+3 and R+2. Refer to page 27 for details on signed binary data.
Remainder
R+2
Quotient
R+3
R+1
R
Dr+1
Dr
Dd+1
Dd
Flags
ER:
Dr+1 and Dr contain 0.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the content of R+1 and R (the quotient) is 0, otherwise OFF.
ON when bit 15 of R+1 is set to 1.
N:
256
Special Math Instructions
Section 5-21
Example
In the following example, DBSL(––) is used to divide the signed binary contents
of IR 002 and IR 001 with the signed binary contents of DM 0021 and DM 0020
and output the result to LR 24 through LR 21.
Address Instruction
Operands
00000
00000
DBSL(––)
001
00000
00001
LD
DBSL(––)
DM 0020
LR 21
001
0020
21
DM
LR
Dd+1: IR 002
Dd: IR 001
F
F
7
A
B
0
1
5
C
A
(–8,736,420)
Dr+1: DM 0021
0
Dr: DM 0020
ꢁ
0
0
0
0
1
(26)
R+3: LR 24
R+2: LR 23
R+1: LR 22
R: LR 21
F
F
F
F
F
F
F
C
F
F
F
A
D
F
7
0
(–336,016 and –4)
Remainder (–4)
Quotient (–336,016)
5-21 Special Math Instructions
5-21-1 FIND MAXIMUM – MAX(––)
Ladder Symbols
Operand Data Areas
C: Control data
MAX(––)
@MAX(––)
IR, SR, AR, DM, HR, LR, #
C
C
R : First word in range
1
R
R
1
1
IR, SR, AR, DM, HR, TC, LR
D: Destination word
D
D
IR, SR, AR, DM, HR, LR
Limitations
Description
N in C must be BCD between 001 to 999.
R and R +N–1 must be in the same data area.
1
1
When the execution condition is OFF, MAX(––) is not executed. When the
execution condition is ON, MAX(––) searches the range of memory from R to
1
R +N–1 for the address that contains the maximum value and outputs the maxi-
1
mum value to the destination word (D).
If bit 14 of C is ON, MAX(––) identifies the address of the word containing the
maximum value in D+1. The address is identified differently for the DM area:
1, 2, 3...
1. For an address in the DM area, the word address is written to D+1. For ex-
ample, if the address containing the maximum value is DM 0114, then #0114
is written in D+1.
2. For an address in another data area, the number of addresses from the be-
ginning of the search is written to D+1. For example, if the address contain-
ing the maximum value is IR 114 and the first word in the search range is
IR 014, then #0100 is written in D+1.
257
Special Math Instructions
Section 5-21
If bit 15 of C is ON and more than one address contains the same maximum val-
ue, the position of the lowest of the addresses will be output to D+1.
The number of words within the range (N) is contained in the 3 rightmost digits of
C, which must be BCD between 001 and 999.
When bit 15 of C is OFF, data within the range is treated as normal binary and
when it is ON the data is treated as signed binary.
C:
15 14 13 12 11
00
Number of words
in range (N)
Not used – set to zero.
Output address to D+1?
1 (ON): Yes.
0 (OFF): No.
Data type
1 (ON): Signed binary
0 (OFF): Normal binary
Caution If bit 14 of C is ON, values above #8000 are treated as negative numbers, so the
results will differ depending on the specified data type. Be sure that the correct
data type is specified.
!
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
The number of words specified in C is not BCD (000 to 999).
R and R +N–1 are not in the same data area.
1
1
EQ:
ON when the maximum value is #0000.
ON when bit 15 of D is set to 1.
N:
5-21-2 FIND MINIMUM – MIN(––)
Ladder Symbols
Operand Data Areas
C: Control data
MIN(––)
@MIN(––)
IR, SR, AR, DM, HR, LR, #
C
C
R : First word in range
1
R
R
1
1
IR, SR, AR, DM, HR, TC, LR
D: Destination word
D
D
IR, SR, AR, DM, HR, LR
Limitations
Description
N in C must be BCD between 001 to 999.
R and R +N–1 must be in the same data area.
1
1
When the execution condition is OFF, MIN(––) is not executed. When the execu-
tion condition is ON, MIN(––) searches the range of memory from R to R +N–1
1
1
for the address that contains the minimum value and outputs the minimum value
to the destination word (D).
If bit 14 of C is ON, MIN(––) identifies the address of the word containing the
minimum value in D+1. The address is identified differently for the DM area:
1, 2, 3...
1. For an address in the DM area, the word address is written to D+1. For ex-
ample, if the address containing the minimum value is DM 0114, then #0114
is written in D+1.
258
Special Math Instructions
Section 5-21
2. For an address in another data area, the number of addresses from the be-
ginning of the search is written to D+1. For example, if the address contain-
ing the minimum value is IR 114 and the first word in the search range is
IR 014, then #0100 is written in D+1.
If bit 14 of C is ON and more than one address contains the same minimum val-
ue, the position of the lowest of the addresses will be output to D+1.
The number of words within the range (N) is contained in the 3 rightmost digits of
C, which must be BCD between 001 and 999.
When bit 15 of C is OFF, data within the range is treated as unsigned binary and
when it is ON the data is treated as signed binary. Refer to page 27 for details on
signed binary data.
C:
15 14 13 12 11
00
Number of words
in range (N)
Not used – set to zero.
Output address to D+1?
1 (ON): Yes.
0 (OFF): No.
Data type
1 (ON): Signed binary
0 (OFF): Unsigned binary
Caution If bit 14 of C is ON, values above #8000 are treated as negative numbers, so the
results will differ depending on the specified data type. Be sure that the correct
data type is specified.
!
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
The number of words specified in C is not BCD (000 to 999).
R and R +N–1 are not in the same data area.
1
1
EQ:
ON when the minimum value is #0000.
ON when bit 15 of D is set to 1.
N:
5-21-3 AVERAGE VALUE – AVG(––)
Operand Data Areas
Ladder Symbols
S: Source word
AVG(––)
@AVG(––)
IR, SR, AR, DM, HR, TC, LR, #
N: Number of cycles
S
N
D
S
N
D
IR, SR, AR, DM, HR, TC, LR, #
D: First destination word
IR, SR, AR, DM, HR, LR
Limitations
Description
Data of S must be hexadecimal.
N must be BCD from #0001 to #0064.
D and D+N+1 must be in the same data area.
AVG(––) is used to calculate the average value of S over N cycles.
When the execution condition is OFF, AVG(––) is not executed.
259
Special Math Instructions
Section 5-21
For the first N–1 cycles when the execution condition is ON, AVG(––) writes the
value of S to D. Each time that AVG(––) is executed, the previous value of S is
stored in words D+2 to D+N+1. The first 2 digits of D+1 are incremented with
each execution and act as a pointer to indicate where the previous value is
stored. Bit 15 of D+1 remains OFF for the first N–1 cycles.
th
On the N cycle, the previous value of S is written to last word in the range D+2 to
D+N+1. The average value of the previous values stored in D+2 to D+N+1 is cal-
culated and written to D, bit 15 of D+1 is turned ON, and the previous value point-
er (the first 2 digits of D+1) is reset to zero. Each time that AVG(––) is executed,
the previous value of S overwrites the content of the word indicated by the point-
er and the new average value is calculated and written to D. The pointer will be
reset again after reaching N–1.
The following diagram shows the function of words D to D+N+1.
D
Average value (after N or more cycles)
Previous value pointer and cycle indicator
Previous value #1
D+1
D+2
D+3
Previous value #2
D+N+1
Previous value #N
The function of bits in D+1 are shown in the following diagram and explained in
more detail below.
D+1: 15 14
08 07
00
Not used. Set to zero.
Previous value pointer
(2-digit hexadecimal from 0 to N–1.)
Cycle indicator
0 (OFF): cycles since execution of AVG(––) < N.
1 (ON): cycles since execution of AVG(––) ≥ N.
Previous Value Pointer
Cycle Indicator
The previous value pointer indicates the location where the most recent value of
S was stored relative to D+2, i.e., a pointer value of 0 indicates D+2, a value of 1
indicates D+3, etc.
The cycle indicator is turned ON after AVG(––) has been executed N times. At
this point, D will contain the average value of the contents of words D+2 through
D+N+1. The average value is 4-digit hexadecimal and is rounded off to the near-
est integer value.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
One or more operands have been set incorrectly.
260
Special Math Instructions
Section 5-21
Example
In the following example, the content of IR 040 is set to #0000 and then increm-
ented by 1 each cycle. For the first two cycles, AVG(––) moves the content of
IR 040 to DM 1002 and DM 1003. The contents of DM 1001 will also change
(which can be used to confirm that the results of AVG(––) has changed). On the
third and later cycles AVG(––) calculates the average value of the contents of
DM 1002 to DM 1004 and writes that average value to DM 1000.
00001
@MOV(21)
Address Instruction
Operands
00001
#0000
040
00000
00001
LD
@MOV(21)
#
0000
040
AVG(––)
040
00002
AVG(––)
#0003
040
0003
1000
DM 1000
#
DM
00003
00004
CLC(41)
ADB(50)
CLC(41)
040
0001
040
ADB(50)
040
#
#0001
040
st
nd
rd
th
1
cycle
cycle
2
cycle
3
cycle
4
cycle
IR 40
0000
0001
0002
0003
st
nd
rd
th
1
2
cycle
3
cycle
4
cycle
DM 1000 0000
DM 1001 0001
DM 1002 0000
DM 1003 ---
0001
0002
0000
0001
---
0001
8000
0000
0001
0002
0002
8001
0003
0001
0002
Average
Pointer
3 previous values of IR 40
DM 1004 ---
5-21-4 SUM – SUM(––)
Operand Data Areas
C: Control data
Ladder Symbols
SUM(––)
@SUM(––)
IR, SR, AR, DM, HR, LR, #
C
C
R : First word in range
1
R
R
1
1
IR, SR, AR, DM, HR, TC, LR
D: First destination word
IR, SR, AR, DM, HR, LR
D
D
Limitations
The 3 rightmost digits of C must be BCD between 001 and 999.
If bit 14 of C is OFF (setting for BCD data), all data within the range R to R +N–1
1
1
must be BCD.
261
Special Math Instructions
Section 5-21
Description
When the execution condition is OFF, SUM(––) is not executed. When the
execution condition is ON, SUM(––) adds either the contents of words R to
1
R +N–1 or the bytes in words R to R +N/2–1 and outputs that value to the des-
1
1
1
tination words (D and D+1). The data can be summed as binary or BCD and will
be output in the same form. Binary data can be either signed or unsigned.
The function of bits in C are shown in the following diagram and explained in
more detail below.
C:
15 14 13 12 11
00
Number of items in range (N, BCD)
Number of words or number of bytes
001 to 999
Starting byte in R1 (when bit 13 is ON)
1 (ON): Rightmost
0 (OFF): Leftmost
Addition units
1 (ON): Bytes
0 (OFF): Words
Data type
1 (ON): Binary
0 (OFF): BCD
Data type (when bit 14 is ON)
1 (ON): Signed binary
0 (OFF): Unsigned binary
Number of Items in Range
Addition Units
The number of items within the range (N) is contained in the 3 rightmost digits of
C, which must be BCD between 001 and 999. This number will indicate the num-
ber of words or the number of bytes depending the items being summed.
Words will be added if bit 13 is OFF and bytes will be added if bit 13 is ON.
If bytes are specified, the range can begin with the leftmost or rightmost byte of
R . The leftmost byte of R will not be added if bit 12 is ON.
1
1
MSB LSB
R
1
3
5
7
2
4
6
8
1
R +1
1
R +2
1
R +3
1
The bytes will be added in this order when bit 12 is OFF: 1+2+3+4....
The bytes will be added in this order when bit 12 is ON: 2+3+4....
Data Type
Data within the range is treated as unsigned binary when bit 14 of C is ON and bit
15 is OFF, and it is treated as signed binary when both bits 14 and 15 are ON.
Refer to page 27 for details on signed binary data.
Data within the range is treated as BCD when bit 14 of C is OFF, regardless of the
status of bit 15.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
R and R +N–1 are not in the same data area.
1
1
The number of items in C is not BCD between 001 and 999.
The data being summed is not BCD when BCD was designated.
ON when the result is zero.
EQ:
N:
ON when bit 15 of D is set to 1.
262
Special Math Instructions
Section 5-21
Example
In the following example, the BCD contents of the 10 words from DM 0000 to
DM 0009 are added when IR 00001 is ON and the result is written to DM 0100
and DM 0101.
00001
Address Instruction
Operands
00001
@SUM(––)
#4010
00000
00001
LD
@SUM(––)
DM 0000
#
4010
0000
0100
DM 0100
DM
DM
DM 0000 3F2A
DM 0001 51C3
DM 0002 E02A
DM 0003 7C9F
DM 0004 2A20
DM 0005 A827
DM 0006 2A20
DM 0007 E02A
DM 0008 C755
DM 0009 94DC
DM 0100 2678
DM 0101 0005
5-21-5 ARITHMETIC PROCESS – APR(69)
Operand Data Areas
Ladder Symbols
C: Control word
APR(69)
@APR(69)
IR, SR, AR, DM, HR, TC, LR, #
S: Input data source word
IR, SR, AR, DM, HR, TC, LR
D: Result destination word
IR, SR, AR, DM, HR,TC, LR
C
S
D
C
S
D
Limitations
Description
For trigonometric functions S must be BCD from 0000 to 0900 (0°≤ ꢀ ≤ 90°).
When the execution condition is OFF, APR(69) is not executed. When the
execution condition is ON, the operation of APR(69) depends on the control
word C.
If C is #0000 or #0001, APR(69) computes sin(ꢀ ) or cos(ꢀ ). The BCD value of S
specifies ꢀ in tenths of degrees.
If C is an address, APR(69) computes f(x) of the function entered in advance be-
ginning at word C. The function is a series of line segments (which can approxi-
mate a curve) determined by the operator. The BCD or hexadecimal value of S
specifies x.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
For trigonometric functions, x > 0900. (x is the content of S.)
A constant other than #0000 or #0001 was designated for C.
The linear approximation data is not readable.
The result is 0000.
EQ:
N:
ON when bit 15 of D is set to 1.
263
Special Math Instructions
Section 5-21
Examples
Sine Function
The following example demonstrates the use of the APR(69) sine function to cal-
culate the sine of 30°. The sine function is specified when C is #0000.
Address Instruction
Operands
00000
00000
APR(69)
#0000
00000
00001
LD
APR(69)
DM 0000
DM 0100
#
0000
0000
0100
DM
DM
Input data, x
S: DM 0000
Result data
D: DM 0100
1
0
–1
–1
–2
–3
–4
0
0
10
3
10
0
10
0
10
5
10
0
10
0
10
0
Enter input data not
exceeding #0900 in BCD.
Result data has four significant
digits, fifth and higher digits are
ignored. The result for sin(90)
will be 0.9999, not 1.
Cosine Function
The following example demonstrates the use of the APR(69) cosine function to
calculate the cosine of 30°. The cosine function is specified when C is #0001.
Address Instruction
Operands
00000
00000
APR(69)
#0001
00000
00001
LD
APR(69)
DM 0010
DM 0110
#
0001
0010
0110
DM
DM
Input data, x
S: DM 0010
Result data
D: DM 0110
1
0
–1
–1
–2
–3
–4
0
0
10
3
10
0
10
0
10
8
10
6
10
6
10
0
Enter input data not
exceeding #0900 in BCD.
Result data has four significant
digits, fifth and higher digits are
ignored. The result for cos(0)
will be 0.9999, not 1.
Linear Approximation
APR(69) linear approximation is specified when C is a memory address. Word C
is the first word of the continuous block of memory containing the linear approxi-
mation data.
The content of word C specifies the number of line segments in the approxima-
tion, and whether the input and output are in BCD or BIN form. Bits 00 to 07 con-
tain the number of line segments less 1, m–1, as binary data. Bits 14 and 15 de-
termine, respectively, the output and input forms: 0 specifies BCD and 1 speci-
fies BIN.
C: 15 14
Not used.
07 06 05 04 03 02 01 00
Number of coordinates
minus one (m–1)
Output form
Input form
264
Special Math Instructions
Section 5-21
Enter the coordinates of the m+1 end-points, which define the m line segments,
as shown in the following table. Enter all coordinates in BIN form. Always enter
the coordinates from the lowest X value (X ) to the highest (X ). X is 0000, and
1
m
0
does not have to be entered.
Y
Word
C+1
Coordinate
Y
Y
m
X
m
Y
0
X
1
Y
1
X
2
Y
2
(max. X value)
C+2
4
C+3
Y
Y
3
1
C+4
C+5
C+6
Y
Y
2
0
↓
↓
C+(2m+1)
X
m
X
C+(2m+2)
Y
m
X
X
X
X
X
X
m
0
1
2
3
4
If bit 13 of C is set to 1, the graph will be reflected from left to right, as shown in the
following diagram.
Y
Y
X
X
X
X
X
X
0
0
m
m
The following example demonstrates the construction of a linear approximation
with 12 line segments. The block of data is continuous, as it must be, from DM
0000 to DM 0026 (C to C + (2 × 12 + 2)). The input data is taken from IR 010, and
the result is output to IR 011.
Address Instruction
Operands
00000
00000
APR(69)
DM 0000
010
00000
00001
LD
APR(69)
DM
0000
010
011
011
Bit
15
Bit
00
Content Coordinate
1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1
DM 0000 $C00B
DM 0001 $05F0
DM 0002 $0000
DM 0003 $0005
DM 0004 $0F00
DM 0005 $001A
DM 0006 $0402
X
Y
X
Y
X
Y
12
0
(Output and
input both BIN)
(m–1 = 11: 12 line
segments)
1
1
2
2
↓
↓
↓
X
Y
DM 0025 $05F0
12
12
DM 0026 $1F20
265
Special Math Instructions
Section 5-21
In this case, the input data word, IR 010, contains #0014, and f(0014) = #0726 is
output to R, IR 011.
Y
$1F20
$0F00
(x,y)
$0726
$0402
(0,0)
X
$0005
$0014
$001A
$05F0
5-21-6 PID CONTROL – PID(––)
Operand Data Areas
Ladder Symbol
S: Input word
PID(––)
IR, SR, AR, DM, HR, LR
C: First parameter word
IR, SR, DM, HR, LR
D: Output word
S
C
D
IR, SR, AR, DM, HR, LR
Limitations
Description
C and C+32 must be within the same data area.
Note Do not program PID(––) in the following situations. Doing so may produce unex-
pected behavior: In interrupt programs, in subroutines, between IL(02) and
ILC(03), between JMP(04) and JME(05), and in step programming (when using
STEP(08) and SNXT(09)).
PID(––) carries out PID control according to the designated parameters. It takes
the specified input range of binary data from the contents of input word S and
carries out the PID operation according to the parameters that are set. The re-
sults are then stored as the operation output amount in output word D.
PID parameter words range from C through C+32. The PID parameters are con-
figured as shown below.
Word
C
15 to 12
11 to 8
7 to 4
3 to 0
Set value (SV)
C+1
C+2
C+3
C+4
C+5
Proportional band (P)
Tik = Integral time T /sampling period γ (See note 1.)
Tdk = Derivative time Td/sampling period γ (See note 1.)
1
Sampling period γ
PID forward/
reverse designation
Time unit for Output range
2-PID parameter (α) (See note 2.)
C+6
0
Input range
sampling pe-
riod and inte-
gral/deriva-
tive times
C+7 to C+32 Work area (Cannot be accessed directly from program.)
266
Special Math Instructions
Section 5-21
Note 1. The actual integral and derivative times are calculated using the values set
in C+2 and C+3 and the time unit set in C+6.
2. Setting the 2-PID parameter (α) to 000 yields 0.65, the normal value.
3. The only CQM1 model that can use PID(––) is the CQM1-CPU4j-EV1.
Performance Specifications
Item
Specifications
PID calculation method
---
Target value filter-type, two degrees of freedom (forward/reverse
operation)
Number of PID control loops
Sampling period
---
t
No limit (1 loop per instruction)
0.01 to 102.3 s (See note.)
0.1 to 999.9%
PID constants
Proportional band
Integral constant
P
Tik
1 to 8191, 9999 (No integral operation for sampling period multiple or
9999.)
Derivative constant Tdk
0 to 8191 (No derivative operation for sampling period multiple.)
0 to 65,535 (Valid up to the maximum value of the input range.)
0 to 65,535 (Valid up to the maximum value of the input range.)
0 to 65,535 (Valid up to the maximum value of the output range.)
Set value
SV
PV
Measured value
Operation output amount
MV
Note For the C200HS and the CQM1-CPU4j-EV1, the sampling period is 0.1 to
102.3 s.
267
Special Math Instructions
Section 5-21
Parameter Settings
Item
Contents
Setting range
Set value (SV)
This is the target value of the process being
controlled.
Binary data (of the same number of bits as
specified for the input range)
Proportional band
Integral time (Tik)
This is the parameter for P control expressing the 0001 to 9999 (4 digits BCD);
proportional control range/total control range. (0.1% to 999.9%, in units of 0.1%)
This is a constant expressing the strength of the 0001 to 8191 (4 digits BCD);
integral operation. As this value increases, the
integral strength increases.
(9999 = No integral operation)
1× to 8191× when time unit = 0 or 1
0.1 to 819.1 s when time unit = 8
0.1 to 81.9 s when time unit = 9
The time unit parameter determines the setting
method.
Set to between 1 and 8191 times the
sampling period when a constant time is
used.
Derivative time
(Tdk)
This is a constant expressing the strength of the 0001 to 8191 (4 digits BCD);
derivative operation. As this value increases, the (0000 = No derivative operation)
derivative strength increases.
1× to 8191× when time unit = 0 or 1
0.1 to 819.1 s when time unit = 8
0.1 to 81.9 s when time unit = 9
The time unit parameter determines the setting
method.
Set to between 1 and 8191 times the
sampling period when a constant time is
used.
Sampling period
This sets the period for executing the PID
operation.
C200HX/HG/HE, CQM1-CPU4j -EV1:
0001 to 1023 (4 digits BCD);
(0.1 to 102.3 s, in units of 0.1 s)
C200HX/HG/HE only:
0001 to 9999 (4 digits BCD);
(0.01 to 99.99 s, in units of 0.01 s)
PID forward/reverse This is the parameter that determines the
designation direction of the proportional operation.
0: Reverse operation
1: Forward operation
(1 digit BCD)
2-PID parameter (α) This is the input filter coefficient. Normally use
0.65 (i.e., a setting of 000). The filter efficiency
000: α = 0.65
100 to 199: Rightmost two digits are α, i.e.,
0.00 to 0.99.
decreases as the coefficient approaches 0.
(3 digits BCD)
Input range
This is the number of input data bits.
0: 8 bits
1: 9 bits
2: 10 bits
3: 11 bits
4: 12 bits
5: 13 bits
6: 14 bits
7: 15 bits
8: 16 bits
(1 digit BCD)
Time unit for
Specifies the time unit for the sampling period
0, 1, 8, or 9 (1 digit BCD)
sampling period and and the method for setting the integral/derivative
0: Constant time, Unit: 100 ms
1: Constant time, Unit: 10 ms
8: Relative time, Unit: 100 ms
9: Relative time, Unit: 10 ms
integral/derivative
parameters.
times
Output range
This is the number of output data bits.
Same as the setting range for the input
range.
PID CONTROL Operation
Execution Condition OFF
All data that has been set is retained. Then the execution condition is OFF, the
operation amount can be written to the output word (D) to achieve manual con-
trol.
Rising Edge of the Execution Condition
The work area is initialized based on the PID parameters that have been set and
the PID control operation is begin. Sudden and radical changes in the operation
output amount are not made when starting operation to avoid adverse affect on
the controlled system (bumpless operation).
When PID parameters are changed, they first become valid when the execution
condition changes from OFF to ON.
268
Special Math Instructions
Section 5-21
Execution Condition ON
The PID operation is executed at the intervals based on the sampling period,
according to the PID parameters that have been set.
Sampling Period and PID Execution Timing
The sampling period is the time interval to retrieve the measurement data for
carrying out a PID operation. PID(––), however, is executed according to the
CPU Unit’s sampling time, so there may be cases where the sampling period is
exceeded. In such cases, the time interval until the next sampling is reduced.
PID Control Method
PID control operations are executed by means of PID control with feed-forward
control (two degrees of freedom).
When overshooting is prevented with simple PID control, stabilization of distur-
bances is slowed (1). If stabilization of disturbances is speeded up, on the other
hand, overshooting occurs and response toward the target value is slowed (2).
With feed-forward PID control, there is no overshooting, and response toward
the target value and stabilization of disturbances can both be speeded up (3).
Simple PID Control
Feed-forward PID control
(1)
(2)
As the target response is slowed,
the disturbance response worsens.
Target response
Disturbance response
As the disturbance response is
slowed, the target response worsens.
Overshoot
Control Operations
Proportional Operation (P)
Proportional operation is an operation in which a proportional band is estab-
lished with respect to the set value (SV), and within that band the operation
amount (the control output amount) is made proportional to the deviation. If the
present value (PV) is smaller than the proportional band, the operation amount
will be 100%. If within the proportional band the operation amount is made pro-
portional to the deviation and gradually decreased until the SV and PV match
(i.e., until the deviation is 0), the operation amount will return to the previous val-
ue (forward operation).
The proportional band is expressed as a percentage with respect to the total in-
put range. With proportional operation an offset (residual deviation) occurs, and
the offset is reduced by making the proportional band smaller. If it is made too
small, however, hunting will occur.
Adjusting the Proportional Band
Proportional Operation
(Reverse Operation)
Operation
amount
100%
Proportional band too narrow (hunting occurring)
Offset
SV
SV
0%
Proportional band just right
Proportional band too wide (large offset)
Proportional band
Integral Operation (I)
Combining integral operation with proportional operation reduces the offset ac-
269
Special Math Instructions
Section 5-21
cording to the time that has passed. The strength of the integral operation is indi-
cated by the integral time, which is the time required for the integral operation
amount to reach the same level as the proportional operation amount with re-
spect to the step deviation, as shown in the following illustration. The shorter the
integral time, the stronger the correction by the integral operation will be. If the
integral time is too short, the correction will be too strong and will cause hunting
to occur.
Integral Operation
Step response
Deviation
0
0
Operation
amount
PI Operation and Integral Time
Step response
Deviation
0
0
PI operation
I operation
P operation
Operation
amount
Ti: Integral time
Derivative Operation (D)
Proportional operation and integral operation both make corrections with re-
spect to the control results, so there is inevitably a response delay. Derivative
operation compensates for that drawback. In response to a sudden disturbance
it delivers a large operation amount and rapidly restores the original status. A
correction is executed with the operation amount made proportional to the in-
cline (derivative coefficient) caused by the deviation.
The strength of the derivative operation is indicated by the derivative time, which
is the time required for the derivative operation amount to reach the same level
as the proportional operation amount with respect to the step deviation, as
shown in the following illustration. The longer the derivative time, the stronger
the correction by the derivative operation will be.
Derivative Operation
Step response
Deviation
0
Operation
amount
0
0
PD Operation and Derivative Time
Ramp response
Deviation
PD operation
P operation
D operation
Operation
amount
0
Td: Derivative time
270
Special Math Instructions
Section 5-21
PID Operation
PID operation combines proportional operation (P), integral operation (I), and
derivative operation (D). It produces superior control results even for control ob-
jects with dead time. It employs proportional operation to provide smooth control
without hunting, integral operation to automatically correct any offset, and deriv-
ative operation to speed up the response to disturbances.
PID Operation Output Step Response
Step response
Deviation
0
PID operation
I operation
P operation
Operation
amount
0
0
D operation
PID Operation Output Ramp Response
Ramp response
Deviation
PID operation
I operation
P operation
D operation
Operation
amount
0
Direction of Operation
When using PID operation, select either of the following two control directions. In
either direction, the operation amount increases as the difference between the
SV and the PV increases.
• Forward operation: Control amount is increased when the SV is larger than the
PV.
Forward Operation
Operation
amount
100%
SV
0%
Low
High
Proportional band
• Reverse operation: Control amount is decreased when the SV is smaller than
the PV.
Reverse Operation
Operation
amount
100%
SV
0%
Low
High
Proportional band
Adjusting PID Parameters
The general relationship between PID parameters and control status is shown
below.
271
Special Math Instructions
Section 5-21
• When it is not a problem if a certain amount of time is required for stabilization
(settlement time), but it is important not to cause overshooting, then enlarge
the proportional band.
Control by measured PID
SV
When P is enlarged
• When overshooting is not a problem but it is desirable to quickly stabilize con-
trol, then narrow the proportional band. If the proportional band is narrowed too
much, however, then hunting may occur.
When P is narrowed
SV
Control by measured PID
• When there is broad hunting, or when operation is tied up by overshooting and
undershooting, it is probably because integral operation is too strong. The
hunting will be reduced if the integral time is increased or the proportional band
is enlarged.
Control by measured PID
(when loose hunting occurs)
SV
Enlarge I or P.
• If the period is short and hunting occurs, it may be that the control system re-
sponse is quick and the derivative operation is too strong. In that case, set the
derivative operation lower.
Control by measured PID
(when hunting occurs in a short period)
SV
Lower D.
Flags
ER:
CY:
Content of ꢀDM word is not BCD, or the DM area boundary has been
exceeded.
A PID parameter SV is out of range.
The PID operation was executed but the cycle time was two times the
sampling period. PID(––) will be executed for this error only even when
ER (SR25503) is ON.
The PID operation is being executed.
272
Special Math Instructions
Section 5-21
Example
This example shows a PID control program using PID(––).
CPU
Unit
AD001 DA001
#0
#1
Amplifier (See note below.)
Fan (Output word IR 111)
Temperature sensing element
(Output word IR 100)
Amplifier (See note below.)
Heater (Output word IR110)
Note Motors and heaters cannot be directly connected from a Analog Output Unit. An
amplifier (i.e., a current amplification circuit) is required.
Creating the Program
Follow the procedure outlined below in creating the program.
1, 2, 3...
1. Set the target value (binary 0000 to 0FFF) in DM 0000.
2. Input the PV of the temperature sensing element (binary 000 to 0FFF) in bits
0 to 11 of word 101.
3. Output the operation amount of the heater to bits 0 to 11 of word 110 by
means of the first PID(––) instruction in the following program.
4. Output the operation amount of the fan to bits 0 to 11 of word 111 by means of
the second PID(––) instruction in the following program.
5. Convert the PV of the temperature sensing element (binary 000 to FFF) to
temperature data (0000°C to 0200°C) by means of SCL(––), and output it to
DM 0200.
273
Special Math Instructions
Section 5-21
Program
00000
25315
@MOV(21)
#0F00
Target value
DM0000
@MOV(21)
DM0000
HR00
Parameter leading word for first
PID(––) instruction
@MOV(21)
DM0000
HR40
Parameter leading word for second
PID(––) instruction
PID(––)
101
PV of temperature sensing element
Heater operation amount
HR00
110
PID(––)
101
Fan operation amount
HR40
111
SCL
101
PV of temperature sensing element (binary)
Leading word of converted parameter
DM0100
DM0200
Present temperature of temperature sensing
element (°C)
END
274
Logic Instructions
Section 5-22
Note When using PID(––) or SCL(––), make the data settings in advance with a Pe-
ripheral Device such as the Programming Console or SSS.
Heater
Target value HR
Proportional band
HR 00
HR 01
(DM0000)
0080
0200
0100
0001
0000
Integral time/sampling period
Derivative time/sampling period
Sampling period
HR 02
HR 03
HR 04
HR 05
Forward/reverse designation/
PID parameters
I/O range and time unit settings
0404
HR 06
SCL Parameters
0000
Fan
HR 40
HR 41
(DM0000)
DM 0100
DM 0101
DM 0102
DM 0103
0060
0150
0100
0001
0001
0000
0200
0FFF
HR 42
HR 43
HR 44
HR 45
0404
HR 46
5-22 Logic Instructions
The logic instructions – COM(29), ANDW(34), ORW(35), XORW(36), and
XNRW(37) – perform logic operations on word data.
5-22-1 COMPLEMENT – COM(29)
Ladder Symbols
Operand Data Areas
Wd: Complement word
COM(29)
Wd
@COM(29)
Wd
IR, SR, AR, DM, HR, LR
Description
Example
When the execution condition is OFF, COM(29) is not executed. When the
execution condition is ON, COM(29) clears all ON bits and sets all OFF bits in
Wd.
COM(29) will alternate between complements of Wd each cycle while the
execution condition is ON; Use @COM(29) when necessary.
15
1
00
1
Original
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
15
0
00
0
Complement
275
Logic Instructions
Section 5-22
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the result is 0.
N:
ON when bit 15 of Wd is set to 1.
5-22-2 LOGICAL AND – ANDW(34)
Operand Data Areas
Ladder Symbols
I1: Input 1
IR, SR, AR, DM, HR, TC, LR, #
I2: Input 2
ANDW(34)
@ANDW(34)
I1
I2
R
I1
I2
R
IR, SR, AR, DM, HR, TC, LR, #
R: Result word
IR, SR, AR, DM, HR, LR
Description
Example
When the execution condition is OFF, ANDW(34) is not executed. When the
execution condition is ON, ANDW(34) logically AND’s the contents of I1 and I2
bit-by-bit and places the result in R.
15
1
00
1
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
I1
I2
15
0
00
1
15
0
00
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
R
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the result is 0.
N:
ON when bit 15 of R is set to 1.
276
Logic Instructions
Section 5-22
5-22-3 LOGICAL OR – ORW(35)
Operand Data Areas
I1: Input 1
IR, SR, AR, DM, HR, TC, LR, #
I2: Input 2
Ladder Symbols
ORW(35)
@ORW(35)
I1
I2
R
I1
I2
R
IR, SR, AR, DM, HR, TC, LR, #
R: Result word
IR, SR, AR, DM, HR, LR
Description
Example
When the execution condition is OFF, ORW(35) is not executed. When the
execution condition is ON, ORW(35) logically OR’s the contents of I1 and I2 bit-
by-bit and places the result in R.
15
1
00
1
I1
I2
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
15
0
00
1
15
1
00
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
R
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the result is 0.
N:
ON when bit 15 of R is set to 1.
277
Logic Instructions
Section 5-22
5-22-4 EXCLUSIVE OR – XORW(36)
Operand Data Areas
I1: Input 1
IR, SR, AR, DM, HR, TC, LR, #
I2: Input 2
Ladder Symbols
XORW(36)
@XORW(36)
I1
I2
R
I1
I2
R
IR, SR, AR, DM, HR, TC, LR, #
R: Result word
IR, SR, AR, DM, HR, LR
Description
Example
When the execution condition is OFF, XORW(36) is not executed. When the
execution condition is ON, XORW(36) exclusively OR’s the contents of I1 and I2
bit-by-bit and places the result in R.
15
1
00
1
I1
I2
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
15
0
00
1
15
1
00
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
R
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the result is 0.
N:
ON when bit 15 of R is set to 1.
278
Subroutines and Interrupt Control
Section 5-23
5-22-5 EXCLUSIVE NOR – XNRW(37)
Operand Data Areas
I1: Input 1
IR, SR, AR, DM, HR, TC, LR, #
I2: Input 2
Ladder Symbols
XNRW(37)
@XNRW(37)
I1
I2
R
I1
I2
R
IR, SR, AR, DM, HR, TC, LR, #
R: Result word
IR, SR, AR, DM, HR, LR
Description
When the execution condition is OFF, XNRW(37) is not executed. When the
execution condition is ON, XNRW(37) exclusively NOR’s the contents of I1 and
I2 bit-by-bit and places the result in R.
15
1
00
1
I1
I2
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
15
0
00
1
15
0
00
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
R
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
EQ:
ON when the result is 0.
N:
ON when bit 15 of R is set to 1.
5-23 Subroutines and Interrupt Control
5-23-1 Subroutines
Subroutines break large control tasks into smaller ones and enable you to reuse
a given set of instructions. When the main program calls a subroutine, control is
transferred to the subroutine and the subroutine instructions are executed. The
instructions within a subroutine are written in the same way as main program
code. When all the subroutine instructions have been executed, control returns
to the main program to the point just after the point from which the subroutine
was entered (unless otherwise specified in the subroutine).
Subroutines may also be activated by interrupts or the MCRO(99) instruction.
Interrupts
Like subroutine calls, interrupts cause a break in the flow of the main program
execution such that the flow can be resumed from that point after completion of
the subroutine. An interrupt is caused either by an external source, such as an
input signal from an Interrupt Input Unit, or a scheduled interrupt. In the case of
the scheduled interrupt, the interrupt signal is repeated at regular intervals.
Whereas subroutine calls are controlled from within the main program, subrou-
tines activated by interrupts are triggered when the interrupt signal is received.
In the case of the scheduled interrupt, the time interval between interrupts is set
by the user and is unrelated to the cycle timing of the PC. This capability is useful
for periodic supervisory or executive program execution.
279
Subroutines and Interrupt Control
Section 5-23
INT(89) is used to control the interrupt signals received from the Interrupt Input
Unit, and also to control the scheduling of the scheduled interrupt. INT(89) pro-
vides such functions as masking of interrupts (so that they are recorded but ig-
nored) and clearing of interrupts.
Refer to 5-23-2 Interrupts for more details on interrupts.
MCRO(99)
The MACRO instruction allows a single subroutine (programming pattern) to re-
place several subroutines that have identical structure but different operands.
Since a number of similar program sections can be managed with just one sub-
routine, the number of program steps can be greatly reduced. Refer to 5-23-5
MACRO – MCRO(99) for more details on this instruction.
5-23-2 Interrupts
The C200HX/HG/HE PCs support both input interrupts and scheduled inter-
rupts. Interrupts stop execution of the program to run a subroutine in must be
executed immediately (input interrupts from an Interrupt Input Unit) or subrou-
tines that must be executed periodically (scheduled interrupts).
There are two interrupt modes. In normal mode the CPU Unit waits until the cur-
rent process is completed before stopping the main program. In high-speed
mode the CPU Unit interrupts the current process. The normal mode is the de-
fault mode in C200HX/HG/HE PCs, but high-speed mode can be selected in the
PC Setup.
Normal Interrupt Mode
The following setting is used for normal interrupt mode.
DM 6620
0
0
0
0
In normal interrupt mode, the following processing will be completed once
started even if an interrupt occurs The interrupt will be processed as soon as the
current process is completed.
• Host Link servicing
• Remote I/O servicing
• Special I/O Unit servicing
• Individual instruction execution
Use this mode whenever using C200H interrupt subroutines without modifica-
tion or whenever possible considering the response time required for interrupts.
Note The C200HX/HG/HE is set to normal interrupt mode by default.
High-speed Interrupt Mode
The following setting is used for high-speed interrupt mode.
DM 6620
1
–
–
–
Interrupt mode
(1 = high-speed)
In high-speed interrupt mode, the following processing will be interrupted and
the interrupt subroutine executed as soon as an interrupt is generated.
• Host Link servicing
• Remote I/O servicing
• Special I/O Unit servicing
• Individual instruction execution
Use this mode whenever interrupt response time must be accurate to 1.0 ms.
Data will not necessarily be concurrent if the high-speed interrupt mode is used
because Host Link servicing, remote I/O servicing, Special I/O Unit servicing,
and individual instruction execution will not necessarily be completed when
280
Subroutines and Interrupt Control
Section 5-23
started. The program must be designed to allow for this when required by the
application. (See the section on data concurrence for further details.)
Input Interrupts
Input interrupts are executed when external inputs are received via an Interrupt
Input Unit. Up to two Interrupt Input Units can be mounted to the CPU Rack and
each Interrupt Input Unit provides 8 inputs numbered IN 0 through IN7.
Inputs IN0 through IN7 on the first Unit generate interrupts #00 to #07 and inputs
IN0 through IN7 on the second Unit generate interrupts #08 to #15. Generally
speaking, subroutines #00 to #15 are executed when interrupts #00 to #15 are
generated.
Scheduled Interrupts
Scheduled interrupts can be executed at intervals set either in increments of
10 ms or in increments or 1 ms. Interrupt #99 is used and subroutine #99 is
executed.
The unit used to set the scheduled interrupt interval is set in the PC Setup at
DM 6622.
Bit
15
00
DM 6622
Schedule Interrupt Setting Interval Setting Enable
00: Setting disabled (interval fixed at 10 ms)
01: Setting in bits 00 to 07 enabled
Schedule Interrupt Setting Interval Setting
00: 10 ms
01: 1 ms
Interrupt Priority
The specified subroutine will be executed when an interrupt is generated. If fur-
ther interrupts are generated during execution of an interrupt subroutine, they
will not be processed until execution of the current interrupt subroutine has been
completed. If more than one interrupt is generated or is awaiting execution at the
same time, the corresponding subroutines will be executed in the following order
of priority.
Input interrupt 1 > input interrupt 2 > ... > input interrupt 7 > scheduled interrupt
Special I/O in Interrupt
Subroutines
I/O for Special I/O Units can be refreshed from within interrupt subroutines by
using the I/O REFRESH (IORF) instruction. If the high-speed interrupt mode is
used, refreshing in the normal cycle (END refreshing and IORF refreshing in the
main program) must be disabled for the Special I/O Unit that is to be refreshed in
the interrupt subroutine. An interrupt programming error (system FAL error 8B)
will occur if the same special I/O is refreshed both within an interrupt program
and within the normal cycle, and the special I/O will not be refreshed within the
interrupt subroutine.
The PC Setup contains settings in DM 6620 that disable refreshing in the normal
cycle for specific Special I/O Units. This settings are as shown below.
DM6620
Bit 15
12
00
1
0
0
*
*
*
*
*
*
*
*
*
*
Interrupt mode
(1 = high-speed)
Unit #0
Unit #1
.
.
.
Unit #9
281
Subroutines and Interrupt Control
Section 5-23
Note Disabling special I/O refreshing in the normal cycle to refresh special I/O in an
interrupt subroutine is necessary only in the high-speed mode. Disabling normal
cycle refreshing of special I/O during normal interrupt mode will be ignored and
the special I/O will be refreshed both in the normal cycle and in the interrupt sub-
routine.
The execution time of interrupt subroutines must be kept to less than10 ms if the
high-speed interrupt mode is used and Special I/O Units, Host Link Units, or Re-
mote I/O Units are programmed. An interrupt programming error (system FAL
error 8B) will occur if the execution time is 10 ms or greater.
The execution time of interrupt subroutine with the longest execution time is out-
put to SR 262 and the number of the subroutine with the longest execution time
is output to SR 263.
Example: 12.3 ms for subroutine #80
Maximum interrupt subroutine execution time (in 0.1 ms)
No. of interrupt subroutine with maximum execution time
SR 262
SR 263
0
8
1
0
2
*
3
*
Note The above 10-ms limit does not apply when the normal interrupt mode is used or
when the above Units are not mounted.
Data Concurrence
Although data concurrence is not a problem for execution of normal arithmetic
instructions or comparison instructions, it can be a problem when executing
longer instructions that handle multiple words, such as block transfer instruc-
tions, when the high-speed interrupt mode is used and the same data is handled
both in the main program and in an interrupt subroutine.
Data may not be concurrent in two different situations: 1) if a data write operation
in the main program is interrupted and the same data is read in an interrupt sub-
routine and 2) if a data read operation in the main program is interrupted and the
same data is written in an interrupt subroutine.
If you must handle the same data both in the main program and in an interrupt
subroutine, use programming such as that shown below to be sure that data
concurrence is preserved, i.e., mask interrupts while read/writing data that is
also handled in an interrupt subroutine.
Masks all interrupts.
(@)INT(89)
100
000
000
Reading and writing common
data words
Unmasks all interrupts.
(@)INT(89)
200
000
000
Data concurrence can also be a problem if interrupts occur during data transfers
occurring in servicing for Special I/O Units, remote I/O, or Host Link Systems.
For any of these, data can be non-concurrent down to byte units.
Use one of the following methods to preserve data concurrence in the above sit-
uations. The second methods applies to Special I/O Units only.
• Mask interrupts in the main program while moving data transferred to/from
Units to different words and use these alternate words in the interrupt subrou-
tine.
282
Subroutines and Interrupt Control
Section 5-23
• Use the I/O REFRESH instruction in interrupt subroutines to refresh required
I/O from Special I/O Units and mask interrupts in the main program while read-
ing/writing Special I/O Unit words.
5-23-3 SUBROUTINE ENTER – SBS(91)
Ladder Symbol
Definer Data Areas
N: Subroutine number
SBS(91) N
000 to 255
Limitations
Description
Subroutine numbers 000 through 015 are used with input interrupts and subrou-
tine number 099 is used for the scheduled interrupt.
A subroutine can be executed by placing SBS(91) in the main program at the
point where the subroutine is desired. The subroutine number used in SBS(91)
indicates the desired subroutine. When SBS(91) is executed (i.e., when the
execution condition for it is ON), the instructions between the SBN(92) with the
same subroutine number and the first RET(93) after it are executed before
execution returns to the instruction following the SBS(91) that made the call.
Main program
SBS(91)
000
Main program
SBN(92)
000
Subroutine
RET(93)
END(01)
SBS(91) may be used as many times as desired in the program, i.e., the same
subroutine may be called from different places in the program).
SBS(91) may also be placed into a subroutine to shift program execution from
one subroutine to another, i.e., subroutines may be nested. When the second
subroutine has been completed (i.e., RET(93) has been reached), program
execution returns to the original subroutine which is then completed before re-
turning to the main program. There is no limit to the number of nesting levels,
unlike the C200HS PCs in which nesting is limited to 16 levels.
A subroutine cannot call itself (e.g., SBS(91) 000 cannot be programmed within
the subroutine defined with SBN(92) 000). The following diagram illustrates two
levels of nesting.
SBN(92) 010
SBS(91) 011
RET(93)
SBN(92) 011
SBS(91) 012
RET(93)
SBN(92) 012
SBS(91) 010
RET(93)
283
Subroutines and Interrupt Control
Section 5-23
The following diagram illustrates program execution flow for various execution
conditions for two SBS(91).
A
SBS(91)
B
000
001
OFF execution conditions for
subroutines 000 and 001
A
B
C
Main
program
SBS(91)
ON execution condition for
subroutine 000 only
A
D
B
C
C
ON execution condition for
subroutine 001 only
SBN(92)
D
000
001
A
B
E
C
RET(93)
SBN(92)
ON execution conditions for
subroutines 000 and 001
Subroutines
A
D
B
E
C
E
RET(93)
END(001)
Note A non-fatal error (error code 8B) will be generated if a subroutine’s execution
time exceeds 10 ms.
Flags
ER:
A subroutine does not exist for the specified subroutine number.
A subroutine has called itself.
An active subroutine has been called.
Caution SBS(91) will not be executed and the subroutine will not be called when ER is
!
ON.
5-23-4 SUBROUTINE DEFINE and RETURN – SBN(92)/RET(93)
Ladder Symbols
Definer Data Areas
N: Subroutine number
SBN(92) N
000 to 255
RET(93)
Limitations
Description
Each subroutine number can be used in SBN(92) once only.
SBN(92) is used to mark the beginning of a subroutine program; RET(93) is
used to mark the end. Each subroutine is identified with a subroutine number, N,
that is programmed as a definer for SBN(92). This same subroutine number is
used in any SBS(91) that calls the subroutine (see 5-23-3 SUBROUTINE EN-
TER – SBS(91)). No subroutine number is required with RET(93).
284
Subroutines and Interrupt Control
Section 5-23
All subroutines must be programmed at the end of the main program. When one
or more subroutines have been programmed, the main program will be
executed up to the first SBN(92) before returning to address 00000 for the next
cycle. Subroutines will not be executed unless called by SBS(91).
END(01) must be placed at the end of the last subroutine program, i.e., after the
last RET(93). It is not required at any other point in the program.
Precautions
If SBN(92) is mistakenly placed in the main program, it will inhibit program
execution past that point, i.e., program execution will return to the beginning
when SBN(92) is encountered.
If either DIFU(13) or DIFU(14) is placed within a subroutine, the operand bit will
not be turned OFF until the next time the subroutine is executed, i.e., the oper-
and bit may stay ON longer than one cycle.
Flags
There are no flags directly affected by these instructions.
5-23-5 MACRO – MCRO(99)
Operand Data Areas
N: Subroutine number
000 to 255
Ladder Symbols
MCRO(99)
@MCRO(99)
I1: First input word
N
I1
N
I1
IR, SR, AR, DM, HR, TC, LR
O1: First output word
IR, SR, AR, DM, HR, LR
O1
O1
Limitations
Description
I1 through I1+3 must be in the same data area, as must O1 through O1+3.
The MACRO instruction allows a single subroutine to replace several subrou-
tines that have identical structure but different operands. There are 4 input
words, SR 290 to SR 293, and 4 output words, SR 294 to SR 297, allocated to
MCRO(99). These 8 words are used in the subroutine and take their contents
from I1 to I1+3 and O1 to O1+3 when the subroutine is executed.
When the execution condition is OFF, MCRO(99) is not executed. When the
execution condition is ON, MCRO(99) copies the contents of I1 to I1+3 to SR 290
to SR 293, copies the contents of O1 to O1+3 to SR 294 to SR 297, and then calls
and executes the subroutine specified in N. When the subroutine is completed,
the contents of SR 294 through SR 297 are then transferred back to O1 to O1+3
before MCRO(99) is completed.
285
Subroutines and Interrupt Control
Section 5-23
In the following example, the contents of DM 0010 through DM 0013 are copied
to SR 290 through SR 293, the contents of DM 0020 through DM 0023 are co-
pied to SR 294 through SR 297, and subroutine 010 is called and executed.
When the subroutine is completed, the contents of SR 294 through SR 297 are
copied back to DM 0020 to DM 0023.
Main program
MCRO(99)
010
DM 0010
DM 0020
Main program
SBN(92)
010
Subroutine
RET(93)
END(01)
Note 1. Subroutines for macros are programmed just like other subroutines, except
that SR 290 to SR 297 contents are transferred in from the designated input
and output words.
2. Not only external I/O words, but internal I/O words can be used for I1 and O1.
3. SR 290 to SR 297 can be used as work bits when not used for macro pro-
grams.
4. MCRO(99) instructions can be nested, but be sure to preserve I/O data
since the instructions use the same 8 I/O words (SR 290 to SR 297).
Precautions
MCRO(99) can be used only for program sections that can be written using four
or fewer consecutive input words and/or four or fewer consecutive output words.
It is thus generally necessary to consider system and program design together
to take full advantage of macro programming.
Be careful that the input and output words properly correspond to the macro in-
put and output words.
Flags
ER:
A subroutine does not exist for the specified subroutine number.
An operand has exceeded a data area boundary.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
A subroutine has called itself.
An active subroutine has been called.
286
Subroutines and Interrupt Control
Section 5-23
Example
The following examples shows the use of four MCRO(99) instructions that ac-
cess the same subroutine. The program section on the left shows the same pro-
gram without the use of MCRO(99).
25313
00000
10000
10001
MCRO(99)
10000
090
Always ON Flag
000
100
00001
00002
10001
MCRO(99)
090
002
00200
10500
10501
10500
105
MCRO(99)
MCRO(99)
090
005
120
00201
00202
10501
12000
00500
12000
12001
090
010
150
00501
00502
12001
15000
SBN(92)
090
29000
29400
29401
01000
15000
15001
29400
29001
29002
01001
01002
29401
15001
RET(93)
5-23-6 INTERRUPT CONTROL – INT(89)
Operand Data Areas
C: Control code
Ladder Symbols
# (000, 001, 002, 100, or 200)
N: Interrupt type
INT(89)
@INT(89)
C
N
D
C
N
D
# (000, 001, or 004)
D: Control data
IR, AR, DM, HR, TC, LR, #
Limitations
D must be between #0000 and #00FF when N=000 and C=000 or 001.
D must be BCD between #0001 and #9999 when N=004 and C=000 or 001.
287
Subroutines and Interrupt Control
Section 5-23
Description
INT(89) is used to control interrupts and performs one of 11 functions depending
on the values of C and N. As shown in the following tables, six of the functions act
on input interrupts, three act on the scheduled interrupt, and the other two mask
or unmask all interrupts.
Interrupt
C
INT(89) Function
Comments
Input interrupts from
Interrupt Input Unit 0
(N=000)
Bits 00 to 07 of D indi-
cate inputs 00 to 07.
000 Mask/unmask input interrupts
001 Clear input interrupts
002 Read current mask status
000 Mask/unmask input interrupts
001 Clear input interrupts
Status written to D.
Input interrupts from
Interrupt Input Unit 1
(N=001)
Bits 00 to 07 of D indi-
cate inputs 00 to 07.
002 Read current mask status
000 Set interrupt interval
Status written to D.
Scheduled (N=004)
---
---
---
001 Set time to first interrupt
002 Read interrupt interval
The following 2 functions depend on the value of C only.
Value of C
100
INT(89) Function
Mask all interrupts
Unmask all interrupts
200
Mask/unmask Input
Interrupts
(N=000 or 001, C=000)
Set N=000 for Interrupt Input Unit 0 and N=001 for Interrupt Input Unit 1. This
function is used to mask and unmask input interrupts 00 to 07.Masked inputs are
recorded, but ignored. When an input is masked, the interrupt program for it will
be run as soon as the bit is unmasked (unless it is cleared beforehand by execut-
ing INT(89) with C=001 and N=000).
Set the corresponding bit in D to 0 to unmask or to 1 to mask an I/O interrupt
input. Bits 00 to 07 correspond to 00 to 07.
Clear Input Interrupts
(N=000 or 001, C=001)
Set N=000 for Interrupt Input Unit 0 and N=001 for Interrupt Input Unit 1. This
function is used to clear I/O interrupt inputs 00 to 07. Since interrupt inputs are
recorded, masked interrupts will be serviced after the mask is removed unless
they are cleared first.
Set the corresponding bit in D to 1 to clear an interrupt input. Bits 00 to 07 corre-
spond to 00 to 07.
Read Current Mask Status
(N=000 or 001, C=002)
Set N=000 for Interrupt Input Unit 0 and N=001 for Interrupt Input Unit 1. This
function is used to write the current mask status for input interrupts 00 to 07 to
word D. The corresponding bit will be ON if the input is masked. (Bits 00 to 07
correspond to 00 to 07.)
Set Interrupt Interval
(N=004, C=000)
This function is used to set the interval between scheduled interrupts. The con-
tent of D (BCD: 0001 to 9999) is multiplied by the scheduled interrupt time unit
(1 ms or 10 ms) to obtain the scheduled interrupt interval.
The scheduled interrupt time unit is set in DM 6622 of the PC Setup. Refer to
3-6-4 PC Setup for details on setting this time unit.
Set Time to First Interrupt
(N=004, C=001)
This function is used to set the time to the first scheduled interrupt. The content
of D (BCD: 0000 to 9999) is multiplied by the scheduled interrupt time unit (1 ms
or 10 ms) to obtain the time to the first scheduled interrupt. The scheduled inter-
rupt time unit is set in DM 6622 of the PC Setup. Refer to 3-6-4 PC Setup for
details on setting this time unit.
Be sure to set the time to the first interrupt. If this setting is not made, the interval
to the first interrupt (set with N=004, C=000) will be uncertain.
Use the First Cycle Flag (SR 25315) for the execution condition to INT(89) when
setting the time to the first interrupt (C=001). The scheduled interrupt might nev-
er occur if the C=001 setting is made continuously.
288
Subroutines and Interrupt Control
Section 5-23
Read Interrupt Interval
(N=004, C=002)
This function is used to write the current setting for the scheduled interrupt inter-
val to word D.
Mask/Unmasking All
Interrupts (C=100/200)
This function is used to mask or unmask all interrupt processing. Masked inputs
are recorded, but ignored. The masked inputs will be serviced as soon as they
are unmasked. This function masks or unmask all interrupts at the same time
and is independent of the masks created with other functions.
The control data, D, and interrupt type, N, are not used for this function. Set them
to #0000.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
C, and/or N are not within specified values.
All interrupts within the subroutine are masked or unmasked.
Example 1: Input Interrupt
This example shows how to unmask a particular interrupt input. Input interrupt
subroutines will be executed when the CPU Unit receives the corresponding in-
terrupt input, regardless of the location in the CPU Unit’s cycle. These interrupts
are useful when using program sections of uncertain length, such as event pro-
grams.
All input interrupts are masked at the start of operation, and the desired interrupt
input is unmasked using INT(89) with N=000 and C=000. As shown in the follow-
ing diagram, the subroutine would be executed if there were an input from input
interrupt 00 of Interrupt Input Unit 0 when that interrupt input was unmasked.
Main program
LD
25315
000
INT(89)
First Cycle Flag
000
#00FE
Only interrupt input
00 is unmasked.
Main program
SBN(92)
00
Interrupt from
interrupt input 00
Subroutine
RET(93)
END(01)
Note Depending on the setting of DM 6621 in the PC Setup, Host Link servicing, Re-
mote I/O servicing, Special I/O Unit servicing, and individual instruction execu-
tion will be completed before the subroutine is executed. Refer to page 280 for
details.
Example 2: Scheduled
Interrupt
This example shows how to set the interval between scheduled interrupts.
Scheduled interrupt subroutines will be executed at fixed intervals, regardless of
the location in the CPU Unit’s cycle. This interrupt is useful for program sections
such as regular monitoring programs.
289
Subroutines and Interrupt Control
Section 5-23
The scheduled interrupt is disabled at the start of operation (the scheduled inter-
rupt interval is 0), so the time to the first interrupt and scheduled interrupt interval
must be set using INT(89) with N=004 and C=001/000. In the following diagram,
the subroutine would be executed every 20 ms if the scheduled interrupt time
unit is set to 10 ms in DM 6622 of the PC Setup.
Main program
LD
25315
001
INT(89)
First Cycle Flag
004
#0002
000
Sets the time to first
interrupt to 20 ms.
INT(89)
004
#0002
Sets the scheduled in-
terrupt interval to 20 ms.
Main program
Scheduled interrupt
every 10 ms.
SBN(92)
Subroutine
99
Return to program ad-
dress before interrupt.
RET(93)
END(01)
Note Depending on the setting of DM 6621 in the PC Setup, Host Link servicing, Re-
mote I/O servicing, Special I/O Unit servicing, and individual instruction execu-
tion will be completed before the subroutine is executed. Refer to page 280 for
details.
290
Step Instructions
Section 5-24
5-24 Step Instructions
The step instructions STEP(08) and SNXT(09) are used in conjunction to set up
breakpoints between sections in a large program so that the sections can be
executed as units and reset upon completion. A section of program will usually
be defined to correspond to an actual process in the application. (Refer to the
application examples later in this section.) A step is like a normal programming
code, except that certain instructions (e.g., IL(02)/ILC(03), JMP(04)/JME(05))
may not be included.
5-24-1 STEP DEFINE and STEP START–STEP(08)/SNXT(09)
Ladder Symbols
STEP(08) B
Definer Data Areas
B: Control bit
STEP(08)
IR, SR, AR, HR, LR
B: Control bit
SNXT(09) B
IR, SR, AR, HR, LR
Limitations
Description
All control bits must be in the same word and must be consecutive.
IR 29800 to IR 29915 cannot be used for B.
STEP(08) uses a control bit in the IR or HR areas to define the beginning of a
section of the program called a step. STEP(08) does not require an execution
condition, i.e., its execution is controlled through the control bit. To start execu-
tion of the step, SNXT(09) is used with the same control bit as used for
STEP(08). If SNXT(09) is executed with an ON execution condition, the step
with the same control bit is executed. If the execution condition is OFF, the step is
not executed. The SNXT(09) instruction must be written into the program so that
it is executed before the program reaches the step it starts. It can be used at dif-
ferent locations before the step to control the step according to two different
execution conditions (see example 2, below). Any step in the program that has
not been started with SNXT(09) will not be executed.
Once SNXT(09) is used in the program, step execution will continue until
STEP(08) is executed without a control bit. STEP(08) without a control bit must
be preceded by SNXT(09) with a dummy control bit. The dummy control bit may
be any unused IR or HR bit. It cannot be a control bit used in a STEP(08).
291
Step Instructions
Section 5-24
Execution of a step is completed either by execution of the next SNXT(09) or by
turning OFF the control bit for the step (see example 3 below). When the step is
completed, all of the IR and HR bits in the step are turned OFF. All timers in the
step except TTIM(––) are reset to their SVs. TTIM(––), counters, shift registers,
bits set or reset with SET or RSET, and bits used in KEEP(11) maintain status.
Two simple steps are shown below.
00000
Starts step execution
SNXT(09) LR 2000
STEP(08) LR 2000
Step controlled by LR 2000
1st step
00001
SNXT(09) LR 2001
STEP(08) LR 2001
Step controlled by LR 2001
2nd step
00002
SNXT(09) LR 2002
STEP(08)
Ends step execution
Address Instruction
Operands
00000
Address Instruction
Operands
00000
00001
00002
LD
00102
STEP(08)
LR
2001
SNXT(09)
STEP(08)
LR
LR
2000
2000
Step controlled by LR 2001
LD
Step controlled by LR 2000
LD
00200
00201
00202
00002
2002
SNXT(09)
STEP(08)
LR
---
00100
00101
00001
2001
SNXT(09)
LR
Steps can be programmed in consecutively. Each step must start with STEP(08)
and generally ends with SNXT(09) (see example 3, below, for an exception).
When steps are programmed in series, three types of execution are possible:
sequential, branching, or parallel. The execution conditions for, and the position-
ing of, SNXT(09) determine how the steps are executed. The three examples
given below demonstrate these three types of step execution.
Precautions
Interlocks, jumps, SBN(92), and END(01) cannot be used within step programs.
Bits used as control bits must not be used anywhere else in the program unless
they are being used to control the operation of the step (see example 3, below).
All control bits must be in the same word and must be consecutive.
If IR or LR bits are used for control bits, their status will be lost during any power
interruption. If it is necessary to maintain status to resume execution at the same
step, HR bits must be used.
292
Step Instructions
Section 5-24
Flags
25407: Step Start Flag; turns ON for one cycle when STEP(08) is executed and
can be used to reset counters in steps as shown below if necessary.
00000
Start
SNXT(09) 01000
01000
STEP(08) 01000
00100
25407
CP
CNT 01
25407
#0003
R
1 cycle
Address Instruction
Operands
Address Instruction
Operands
25407
00000
00001
00002
00003
LD
00000
01000
01000
00100
00004
00005
LD
SNXT(09)
STEP(08)
LD
CNT
01
#
0003
Examples
The following three examples demonstrate the three types of execution control
possible with step programming. Example 1 demonstrates sequential execu-
tion; example 2, branching execution; and example 3, parallel execution.
Example 1:
Sequential Execution
The following process requires that three processes, loading, part installation,
and inspection/discharge, be executed in sequence with each process being re-
set before continuing on the the next process. Various sensors (SW1, SW2,
SW3, and SW4) are positioned to signal when processes are to start and end.
SW 1
SW 4
SW 2
SW 3
Loading
Part installation
Inspection/discharge
293
Step Instructions
Section 5-24
The following diagram demonstrates the flow of processing and the switches
that are used for execution control.
SW1
Process A
Loading
SW2
Process B
Part Installation
SW3
Process C
Inspection/discharge
SW4
294
Step Instructions
Section 5-24
The program for this process, shown below, utilizes the most basic type of step
programming: each step is completed by a unique SNXT(09) that starts the next
step. Each step starts when the switch that indicates the previous step has been
completed turns ON.
00001 (SW1)
00002 (SW2)
00003 (SW3)
00004 (SW4)
Process A started.
SNXT(09) 12800
STEP(08) 12800
Process A
Process A reset.
SNXT(09) 12801
Process B started.
STEP(08) 12801
Process B
Process B reset.
Process C started.
SNXT(09) 12802
STEP(08) 12802
Process C
Process C reset.
SNXT(09) 12803
STEP(08)
Address Instruction
Operands
00001
Address Instruction
Operands
00000
00001
00002
LD
Process B
SNXT(09)
STEP(08)
12800
12800
00100
00101
00102
LD
00003
SNXT(09)
STEP(08)
12802
12802
Process A
00100
00101
00102
LD
00002
12801
12801
Process C
SNXT(09)
STEP(08)
00200
00201
00202
LD
00004
12803
---
SNXT(09)
STEP(08)
295
Step Instructions
Section 5-24
Example 2:
Branching Execution
The following process requires that a product is processed in one of two ways,
depending on its weight, before it is printed. The printing process is the same
regardless of which of the first processes is used. Various sensors are posi-
tioned to signal when processes are to start and end.
Printer
SW A2
SW A1
SW D
Process A
Process B
SW B1
SW B2
Weight scale
Process C
The following diagram demonstrates the flow of processing and the switches
that are used for execution control. Here, either process A or process B is used
depending on the status of SW A1 and SW B1.
SW B1
SW B2
SW A1
SW A2
Process A
Process B
Process C
SW D
End
296
Step Instructions
Section 5-24
The program for this process, shown below, starts with two SNXT(09) instruc-
tions that start processes A and B. Because of the way 00001 (SW A1) and
00002 (SB B1) are programmed, only one of these will be executed to start either
process A or process B. Both of the steps for these processes end with a
SNXT(09) that starts the step for process C.
00001 (SW A1) 00002 (SW B1)
SNXT(09) HR 0000
SNXT(09) HR 0001
00001 (SW A1) 00002 (SW B1)
Process A started.
STEP(08) HR 0000
Process A
00003 (SW A2)
Process A reset.
Process C started.
SNXT(09) HR 0002
STEP(08) HR 0001
Process B
00004 (SW B2)
Process B reset.
Process C started.
SNXT(09) HR 0002
STEP(08) HR 0002
Process C
00005 (SW D)
Process C reset.
SNXT(09) HR 0003
STEP(08)
Address Instruction
Operands
Address Instruction
Operands
00000
LD
00001
00002
0000
00001
00002
00003
00004
00005
00006
AND NOT
SNXT(09)
LD NOT
AND
Process B
HR
00001
00002
0001
00100
00101
00102
LD
00004
SNXT(09)
STEP(08)
HR
HR
0002
0002
SNXT(09)
STEP(08)
HR
HR
0000
Process C
Process A
00200
00201
00202
LD
00005
0003
00100
00101
00102
LD
00003
0002
0001
SNXT(09)
STEP(08)
HR
---
SNXT(09)
STEP(08)
HR
HR
297
Step Instructions
Section 5-24
Example 3:
Parallel Execution
The following process requires that two parts of a product pass simultaneously
through two processes each before they are joined together in a fifth process.
Various sensors are positioned to signal when processes are to start and end.
SW1
SW3
SW5
SW7
Process A
Process B
Process E
Process D
Process C
SW4
SW2
SW6
The following diagram demonstrates the flow of processing and the switches
that are used for execution control. Here, process A and process C are started
together. When process A finishes, process B starts; when process C finishes,
process D starts. When both processes B and D have finished, process E starts.
SW 1 and SW2 both ON
Process A
Process B
Process C
Process D
SW4
SW3
SW5 and SW6 both ON
Process E
SW7
End
The program for this operation, shown below, starts with two SNXT(09) instruc-
tions that start processes A and C. These instructions branch from the same
instruction line and are always executed together, starting steps for both A and
C. When the steps for both A and C have finished, the steps for process B and D
begin immediately.
When both process B and process D have finished (i.e., when the status for both
of them is “ON,” but SW5 and SW6 have turned ON), processes B and D are
reset together by the SNXT(09) at the end of the programming for process B.
Although there is no SNXT(09) at the end of process D, the control bit for it is
turned OFF by executing SNXT(09) LR 0004. This is because the OUT for LR
0003 is in the step reset by SNXT(09) LR 0004, i.e., LR 003 is turned OFF when
SNXT(09) LR 0004 is executed Process B is thus reset directly and process D is
reset indirectly before executing the step for process E.
298
Step Instructions
Section 5-24
00001 (SW1 and SW2))
Process A started.
Process C started.
SNXT(09) LR 0000
SNXT(09) LR 0002
STEP(08) LR 0000
Process A
00002 (SW3)
Process A reset.
Process B started.
SNXT(09) LR 0001
STEP(08) LR 0001
Process B
Used to
turn off
LR 0003
LR 0003
process D.
00004 (SW5 and SW6)
Process E started.
SNXT(09) LR 0004
STEP(08) LR 0002
Process C
00003 (SW4)
Process C reset.
Process D started.
SNXT(09) LR 0003
STEP(08) LR 0003
Process D
STEP(08) LR 0004
Process E
00005 (SW7)
Process E reset.
SNXT(09) LR 0005
STEP(08)
299
Special Instructions
Section 5-25
Address Instruction
Operands
00001
Address Instruction
Operands
00000
00001
00002
00003
LD
00204
STEP(08)
Process C
LR
0002
SNXT(09)
SNXT(09)
STEP(08)
LR
LR
LR
0000
0002
0000
00300
00301
00302
LD
00003
0003
0003
Process A
SNXT(09)
STEP(08)
LR
LR
00100
00101
00102
LD
00002
0001
0001
SNXT(09)
STEP(08)
LR
LR
Process D
STEP(08)
Process E
00400
LR
LR
0004
Process B
00200
00201
00202
00203
LD
LR 0003
LR 0003
00004
OUT
00500
00501
00502
LD
00005
0005
---
AND
SNXT(09)
STEP(08)
SNXT(09)
LR
0004
5-25 Special Instructions
The instructions in this section are used for various operations, including pro-
gramming user error codes and messages, counting ON bits, setting the watch-
dog timer, and refreshing I/O during program execution.
5-25-1 FAILURE ALARM – FAL(06) and
SEVERE FAILURE ALARM – FALS(07)
Ladder Symbols
Definer Data Areas
N: FAL number
FAL(06) N
@FAL(06) N
# (00 to 99)
N: FAL number
FALS(07) N
# (01 to 99)
Limitations
Description
FAL(06) and FALS(07) share the same FAL numbers. Be sure to use a number
in either FAL(06) or FALS(07), not both.
FAL(06) and FALS(07) are provided so that the programmer can output error
numbers for use in operation, maintenance, and debugging. When executed
with an ON execution condition, either of these instructions will output a FAL
number to bits 00 to 07 of SR 253. The FAL number that is output can be be-
tween 01 and 99 and is input as the definer for FAL(06) or FALS(07). FAL(06)
with a definer of 00 is used to reset this area (see below).
FAL Area
25307
25300
1
0
X10
X10
300
Special Instructions
Section 5-25
FAL(06) produces a non-fatal error and FAL(07) produces a fatal error. When
FAL(06) is executed with an ON execution condition, the ALARM/ERROR indi-
cator on the front of the CPU Unit will flash, but PC operation will continue. When
FALS(07) is executed with an ON execution condition, the ALARM/ERROR indi-
cator will light and PC operation will stop.
The system also generates error codes to the FAL area.
Resetting Errors
All FAL error codes will be retained in memory, although only one of these is
available in the FAL area. To access the other FAL codes, reset the FAL area by
executing FAL(06) 00. Each time FAL(06) 00 is executed, another FAL error will
be moved to the FAL area, clearing the one that is already there. FAL error codes
are recorded and will be recalled in the following order: First code generated,
lowest FAL number greater than the first code, lowest FAL number lower than
the first code.
Clearing Messages
FAL(06) 00 is also used to clear message programmed with the instruction,
MSG(46).
If the FAL area cannot be cleared, as is generally the case when FALS(07) is
executed, first remove the cause of the error and then clear the FAL area through
the Programming Console (see 4-6-5 Clearing Error Messages).
5-25-2 CYCLE TIME – SCAN(18)
Operand Data Areas
Mi: Multiplier (BCD)
IR, SR, AR, DM, HR, TC, LR, #
000: Not used.
Ladder Symbols
SCAN(18)
Mi
@SCAN(18)
Mi
000
000
000
000: Not used.
000
Limitations
Description
Mi must be BCD. Only the rightmost three digits of Mi are used.
SCAN(18) is used to set a minimum cycle time. Mi is the minimum cycle time that
will be set in tenths of milliseconds, e.g., if Mi is 1200, the minimum cycle time will
be 120.0 ms. The possible setting range is from 000.0 to 999.0 ms.
If the actual cycle time is less than the cycle time set with SCAN(18) the CPU Unit
will wait until the designated time has elapsed before starting the next cycle. If
the actual cycle time is greater than the set time, the set time will be ignored and
the program will be executed to completion.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
Mi is not BCD.
301
Special Instructions
Section 5-25
5-25-3 TRACE MEMORY SAMPLING – TRSM(45)
Data tracing can be used to facilitate debugging programs. To set up and use
data tracing it is necessary to have a host computer running SSS; no data
tracing is possible from a Programming Console. Data tracing is described in
detail in the SSS Operation Manual. This section shows the ladder symbol for
TRSM(45) and gives an example program.
Ladder Symbol
TRSM(45)
Description
TRSM(45) is used in the program to mark locations where specified data is to be
stored in Trace Memory. Up to 12 bits and up to 3 words may be designated for
tracing (refer to the SSS Operation Manual for details).
TRSM(45) is not controlled by an execution condition, but rather by two bits
in the AR area: AR 2515 and AR 2514. AR 2515 is the Sampling Start bit.
This bit is turned ON to start the sampling processes for tracing. The Sam-
pling Start bit must not be turned ON from the program, i.e., it must be turned
ON only from the peripheral device. AR 2514 is the Trace Start bit. When it is
set, the specified data is recorded in Trace Memory. The Trace Start bit can
be set either from the program or from the Programming Device. A positive
or negative delay can also be set to alter the actual point from which tracing
will begin.
Data can be recorded in any of three ways. TRSM(45) can be placed at one
or more locations in the program to indicate where the specified data is to be
traced. If TRSM(45) is not used, the specified data will be traced when
END(01) is executed. The third method involves setting a timer interval from
the peripheral devices so that the specified data will be tracing at a regular
interval independent of the cycle time (refer to the SSS Operation Manual).
TRSM(45) can be incorporated anywhere in a program, any number of times.
The data in the trace memory can then be monitored via a Programming
Console, host computer, etc.
AR Control Bits and Flags
The following control bits and flags are used during data tracing. The Tracing
Flag will be ON during tracing operations. The Trace Completed Flag will turn
ON when enough data has been traced to fill Trace Memory.
Flag
AR 2515
AR 2514
AR 2513
AR 2512
Function
Sampling Start Bit
Trace Start Bit
Tracing Flag
Trace Completed Flag
Precautions
Example
If TRSM(45) occurs TRSM(45) will not be executed within a JMP(08) – JME(09)
block when the jump condition is OFF.
The following example shows the basic program and operation for data tracing.
Force set the Sampling Start Bit (AR 2515) to begin sampling. The Sampling
Start Bit must not be turned ON from the program. The data is read and stored
into trace memory.
When IR 00000 is ON, the Trace Start Bit (AR 2514) is also turned ON, and the
CPU Unit looks at the delay and marks the trace memory accordingly. This can
mean that some of the samples already made will be recorded as the trace
memory (negative delay), or that more samples will be made before they are re-
corded (positive delay).
302
Special Instructions
Section 5-25
The sampled data is written to trace memory, jumping to the beginning of the
memory area once the end has been reached and continuing up to the start
marker. This might mean that previously recorded data (i.e., data from this sam-
ple that falls before the start marker) is overwritten (this is especially true if the
delay is positive). The negative delay cannot be such that the required data was
executed before sampling was started.
00000
AR
Starts data tracing.
2514
Designates point for
tracing.
TRSM(45)
AR 2513 ON when tracing
Indicates that tracing is in
progress.
00200
AR 2512 ON when trace is complete
Indicates that tracing has
been completed.
00201
Address Instruction
Operands
0000
Address Instruction
Operands
00000
00001
00002
00003
LD
00004
00005
00006
OUT
LD
00200
OUT
TRSM(45)
LD
AR
2514
AR
2512
OUT
00201
AR
2513
5-25-4 MESSAGE DISPLAY – MSG(46)
Ladder Symbols
Operand Data Areas
FM: First message word
MSG(46)
FM
@MSG(46)
FM
IR, SR, AR, DM, HR, LR
Limitations
Description
FM and FM+7 must be in the same data area.
When executed with an ON execution condition, MSG(46) reads eight words of
extended ASCII code from FM to FM+7 and displays the message on the Pro-
gramming Console. The displayed message can be up to 16 characters long,
i.e., each ASCII character code requires eight bits (two digits). Refer to Appendix
I for the extended ASCII codes. Japanese katakana characters are included in
this code.
If not all eight words are required for the message, it can be stopped at any point
by inputting “0D.” When 0D is encountered in a message, no more words will be
read and the words that normally would be used for the message can be used for
other purposes.
Message Buffering and
Priority
Up to three messages can be buffered in memory. Once stored in the buffer, they
are displayed on a first in, first out basis. Since it is possible that more than three
MSG(46)s may be executed within a single cycle, there is a priority scheme,
based on the area where the messages are stored, for the selection of those
messages to be buffered.
The priority of the data areas is as follows for message display:
LR > IR > HR > AR > TC > DM > SR
In handling messages from the same area, those with the lowest ad-
dress values have higher priority.
303
Special Instructions
Section 5-25
In handling indirectly addressed messages (i.e. DM), those with the
lowest DM address values have higher priority.
Clearing Messages
To clear a message, execute FAL(06) 00 or clear it via a Programming Console
using the procedure in 4-6-5 Clearing Error Messages.
If the message data changes while the message is being displayed, the display
will also change.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
Example
The following example shows the display that would be produced for the instruc-
tion and data given when 00000 was ON. If 00001 goes ON, a message will be
cleared.
00000
00001
Address Instruction
Operands
00000
MSG(46)
DM 0010
00000
00001
LD
MSG(46)
DM
0010
00001
00
FAL(06) 00
00002
00003
LD
FAL(06)
DM contents
ASCII
equivalent
DM 0010
DM 0011
DM 0012
DM 0013
DM 0014
DM 0015
DM 0016
DM 0017
4
4
4
4
4
4
4
4
1
3
5
7
9
B
D
F
4
4
4
4
4
4
4
5
2
4
6
8
A
C
E
0
A
B
D
F
H
J
C
E
G
I
MSG
ABCDEFGHIJKLMNOP
K
M
O
L
N
P
5-25-5 LONG MESSAGE – LMSG(47)
Operand Data Areas
S: First source word (ASCII)
IR, SR, AR, DM, HR, TC, LR
---: Not used.
Ladder Symbols
LMSG(47)
@LMSG(47)
S
S
Set to 000
---
---
---
---
---: Not used.
Set to 000
Limitations
S through S+15 must be in the same data area and must be in ASCII. The mes-
sage will be truncated if a null character (0D) is contained between S and S+15.
304
Special Instructions
Section 5-25
Description
LMSG(47) is used to output a 32-character message to a Programming Con-
sole. The message to be output must be in ASCII beginning in word S and end-
ing in S+15, unless a shorter message is desired. A shorter message can be pro-
duced by placing a null character (0D) into the string; no characters from the null
character on will be output.
To output to the Programming Console, it must be set in TERMINAL mode. Al-
though LMSG(47) will be executed as normal, the message will not appear cor-
rectly on the Programming Console unless TERMINAL mode is set. Refer to
5-25-6 TERMINAL MODE – TERM(48) for details on switching to TERMINAL
mode.
When pin 6 of the CPU Unit’s DIP switch is OFF, the Programming Console can
be switched to TERMINAL mode by pressing the CHG Key or by executing
TERM(48) in the program. When pin 6 of the CPU Unit’s DIP switch is ON, the
Programming Console can be switched to Expansion TERMINAL mode by turn-
ing on bit AR 0709.
Flags
ER:
S and S+15 are not in the same data area.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
Example
Although the display is longer and there is a choice of output devices, the coding
for LMSG(47) is the same as that for MSG(46). Refer to Example under the pre-
vious section for an example using MSG(46).
5-25-6 TERMINAL MODE – TERM(48)
Ladder Symbols
TERM(48)
000
@TERM(48)
000
000
000
000
000
Description
When the execution condition is OFF, TERM(48) is not executed. When the
execution condition is ON, TERM(48) switches the Programming Console to
TERMINAL mode. (Instructions MSG(46), LMSG(47), and the keyboard map-
ping function are executed in TERMINAL mode.)
The Programming Console will return to CONSOLE mode when the CHG key is
pressed again. There is no instruction that returns the Programming Console to
CONSOLE mode from the program.
The Programming Console can also be switched to TERMINAL mode by press-
ing the CHG key on the Programming Console before inputting the password or
when the mode is being displayed provided that pin 6 of the CPU Unit’s DIP
switch is OFF. The Programming Console will return to CONSOLE mode when
the CHG key is pressed again.
When pin 6 of the CPU Unit’s DIP switch is ON, the Programming Console can
be switched to Expansion TERMINAL mode by turning on bit AR 0709.
305
Special Instructions
Section 5-25
Example
In the following example, TERM(48) is used to switch the Programming Console
to TERMINAL mode when 00000 is ON. Be sure that pin 6 of the CPU Unit’s DIP
switch is OFF.
00000
Address Instruction
Operands
00000
TERM(48)
000
00000
00001
LD
TERM(48)
000
000
000
000
000
5-25-7 WATCHDOG TIMER REFRESH – WDT(94)
Ladder Symbols
Definer Data Areas
T: Watchdog timer value
WDT(94) T
@WDT(94) T
# (00 to 63)
Description
When the execution condition is OFF, WDT(94) is not executed. When the
execution condition is ON, WDT(94) extends the setting of the cycle monitor
time (watchdog timer) set in DM 6618 of the PC Setup. The default setting is 120
ms.
Timer extension = 100 ms x T
Where, T = 00 to 63 (4-digit BCD)
Precautions
The cycle monitor time (watchdog timer setting) can be set to a maximum of 99 s
with the PC Setup. The WDT(94) instruction can be used to extend the cycle
monitor time to a maximum value of 6400 ms, but only the portion of the cycle
used for instruction execution is extended.
WDT(94) can be executed more than once in a cycle, but the cycle time can’t be
extended by more than 6400 ms total. Any extension over 6400 ms will be ig-
nored. Another WDT(94) instruction won’t be executed if the cycle time has al-
ready been extended by 6400 ms.
Timers might not function properly when the cycle time exceeds 100 ms. When
using WDT(94), the same timer should be repeated in the program at intervals
that are less than 100 ms apart. TIMH(15) should be used only in a scheduled
interrupt routine executed at intervals of 10 ms or less.
Flags
There are no flags affected by this instruction.
5-25-8 I/O REFRESH – IORF(97)
Ladder Symbol
Operand Data Areas
St: Starting word
IORF(97)
IR 000 to IR 049, IR 100 to IR 199,
SR 400 to SR 450
St
E
E: End word
IR 000 to IR 049, IR 100 to IR 199,
SR 400 to SR 450
Limitations
IORF(97) can be used to refresh I/O words allocated to I/O Units, Special I/O
Units, and Interrupt Input Units mounted to the CPU or Expansion I/O Racks.
306
Special Instructions
Section 5-25
It cannot be used for other I/O words, such as I/O Units on Slave Racks or
Group-2 High-density I/O Units.
St must be less than or equal to E.
Description
To refresh I/O words allocated to CPU or Expansion I/O Racks (IR 000 to IR 029
or IR 300 to IR 309), simply specify the first (St) and last (E) I/O words to be re-
freshed. When the execution condition for IORF(97) is ON, all words between St
and E will be refreshed. This will be in addition to the normal I/O refresh per-
formed during the CPU Unit’s cycle.
To refresh I/O words allocated to Special I/O Units 0 through 9 (IR 100 to IR 199),
designate IR 040 to IR 049. These IR words are just used to identify the corre-
sponding Special I/O Unit; execution of IORF(97) will have no effect on the con-
tent of IR 040 to IR 049.
For example, set St to IR 043 and E to IR 045 to refresh the I/O words allocated to
Special I/O Units 3, 4, and 5. The I/O words allocated to those Units (IR 130 to
IR 159) will be refreshed when IORF(97) is executed. This will be in addition to
the normal I/O refresh performed during the CPU Unit’s cycle.
To specify a particular 10-word Special I/O Unit Area (IR 100 to IR 190 or IR 400
to IR 450), input the first word of the 10-word area. (The last digit of the IR word
must be 0.)
Refer to 5-25-9 GROUP-2 HIGH-DENSITY I/O REFRESH – MPRF(61) for de-
tails on refreshing words allocated to Group-2 High-density I/O Units.
Flags
ER:
St and/or E aren’t within the proper setting ranges.
(000 to 029, 040 to 040, 100 to 190, 300 to 309, or 400 to 450).
St and E aren’t within the same setting range.
St is greater than E.
5-25-9 GROUP-2 HIGH-DENSITY I/O REFRESH – MPRF(61)
Operand Data Areas
Ladder Symbols
St: Starting unit number
#0000 to #000F
E: End unit number
#0000 to #000F
000: Set to 000.
---
MPRF(61)
@MPRF(61)
St
E
St
E
000
000
Limitations
Description
MPRF(61) can be used to refresh I/O words allocated to Group-2 High-density
I/O Units only. It cannot be used for other I/O words.
St and E must be between #0000 and #000F. St must be less than or equal to E.
When the execution condition is OFF, MPRF(61) is not executed. When the
execution condition is ON, the I/O words allocated to Group-2 High-density I/O
Units with unit numbers St through E will be refreshed. This will be in addition to
the normal I/O refresh performed during the CPU Unit’s cycle.
It is not possible to specify the I/O words by address, only by the unit number of
the Unit to which they are allocated.
Execution Time
The execution time for MPRF(61) is computed as follows:
T
=
Instruction execution time
MPRF
+ ∑(Group-2 High-density I/O Unit I/O refresh times)
307
Special Instructions
Section 5-25
Refer to 6-1 Cycle Time for a table showing I/O refresh times for Group-2
High-density I/O Units.
Flags
ER:
St or E is not BCD between #0000 and #000F.
St is greater than E.
5-25-10 BIT COUNTER – BCNT(67)
Operand Data Areas
Ladder Symbols
N: Number of words (BCD)
IR, SR, AR, DM, HR, TC, LR, #
SB: Source beginning word
IR, SR, AR, DM, HR, TC, LR
D: Destination word
BCNT(67)
@BCNT(67)
N
SB
D
N
SB
D
IR, SR, AR, DM, HR, TC, LR
Limitations
Description
N must be BCD between 0000 and 6656.
When the execution condition is OFF, BCNT(67) is not executed. When the
execution condition is ON, BCNT(67) counts the total number of bits that are ON
in all words between SB and SB+(N–1) and places the BCD result in D.
Flags
ER:
N is not BCD, or N is 0; SB and SB+(N–1) are not in the same area.
The resulting count value exceeds 9999.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
ON when the count (N) exceeds the data area boundary.
ON when the result is 0.
EQ:
5-25-11 FRAME CHECKSUM – FCS(––)
Operand Data Areas
C: Control data
Ladder Symbols
FCS(––)
@FCS(––)
IR, SR, AR, DM, HR, LR, #
C
C
R : First word in range
1
R
R
1
1
IR, SR, AR, DM, HR, TC, LR
D: First destination word
IR, SR, AR, DM, HR, LR
D
D
Description
FCS(––) can be used to check for errors when transferring data through commu-
nications ports.
When the execution condition is OFF, FCS(––) is not executed. When the
execution condition is ON, FCS(––) calculates the frame checksum of the speci-
fied range by exclusively ORing either the contents of words R to R +N–1 or the
1
1
bytes in words R to R +N–1. The frame checksum value (hexadecimal) is then
1
1
converted to ASCII and output to the destination words (D and D+1).
308
Special Instructions
Section 5-25
The function of bits in C are shown in the following diagram and explained in
more detail below.
C:
15 14 13 12 11
00
Number of items in range (N, BCD)
001 to 999 words or bytes
First byte (when bit 13 is ON)
1 (ON): Rightmost
0 (OFF): Leftmost
Calculation units
1 (ON): Bytes
0 (OFF): Words
Not used. Set to zero.
Number of Items in Range
Calculation Units
The number of items within the range (N) is contained in the 3 rightmost digits of
C, which must be BCD between 001 and 999.
The frame checksum of words will be calculated if bit 13 is OFF and the frame
checksum of bytes will be calculated if bit 13 is ON.
If bytes are specified, the range can begin with the leftmost or rightmost byte of
R . The leftmost byte of R will not be included if bit 12 is ON.
1
1
MSB LSB
R
1
3
5
7
2
4
6
8
1
R +1
1
R +2
1
R +3
1
When bit 12 is OFF the bytes will be ORed in this order: 1, 2, 3, 4, ....
When bit 12 is ON the bytes will be ORed in this order: 2, 3, 4, 5, ....
Conversion to ASCII
The byte frame checksum calculation yields a 2-digit hexadecimal value which is
converted to its 4-digit ASCII equivalent. The word frame checksum calculation
yields a 4-digit hexadecimal value which is converted to its 8-digit ASCII equiva-
lent, as shown below.
Byte frame checksum value
4A
Word frame checksum value
F10B
3 4 4 1
4 6 3 1
3 0 4 2
D
D+1
D
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
The number of items is not 001 to 999 BCD.
The calculation range exceeds the data area.
309
Special Instructions
Section 5-25
Example
When IR 00000 is ON in the following example, the frame checksum (0008) is
calculated for the 8 words from DM 0000 to DM 0007 and the ASCII equivalent
(30 30 30 38) is written to DM 0011 and DM 0010.
00000
Address Instruction
Operands
00000
@FCS(––)
#0008
00000
00001
LD
@FCS(––)
DM 0000
#
0008
0000
0010
DM 0010
DM
DM
FCS
calculation
DM 0000 0001
DM 0001 0002
DM 0002 0003
DM 0003 0004
DM 0004 0005
DM 0005 0006
DM 0006 0007
DM 0007 0008
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
0
0
0
8
ASCII code
conversion
DM 0011 3 0 3 0 DM 0010 3 0 3 8
5-25-12 FAILURE POINT DETECTION – FPD(––)
Ladder Symbols
Operand Data Areas
C: Control data
#
FPD(––)
C
T
T: Monitoring time (BCD)
IR, SR, AR, DM, HR, TC. LR, #
D: First register word
IR, AR, DM, HR, LR
D
Limitations
Description
D and D+8 must be in the same data area when bit 15 of C is ON.
C must be input as a constant.
FPD(––) can be used in the program as many times as desired, but each must
use a different D. It is used to monitor the time between the execution of FPD(––)
and the execution of a diagnostic output. If the time exceeds T, an FAL(06) non-
fatal error will be generated with the FAL number specified in C.
The program sections marked by dashed lines in the following diagram can be
written according to the needs of the particular program application. The proces-
sing programming section triggered by CY is optional and can used any instruc-
tions but LD and LD NOT. The logic diagnostic instructions and execution condi-
tion can consist of any combination of NC or NO conditions desired.
Branch
Execution
condition
FPD(––)
C
T
D
SR 25504
(CY Flag)
Processing after
error detection.
Logic
diagnostic
instructions
Diagnostic
output
310
Special Instructions
Section 5-25
When the execution condition is OFF, FPD(––) is not executed. When the
execution condition is ON, FPD(––) monitors the time until the logic diagnostics
condition goes ON, turning ON the diagnostic output. If this time exceeds T, the
following will occur:
1, 2, 3... 1. An FAL(06) error is generated with the FAL number specified in the first two
digits of C. If 00 is specified, however, an error will not be generated.
2. The logic diagnostic instructions are searched for the first OFF input condi-
tion and this condition’s bit address is output to the destination words begin-
ning at D.
3. The CY Flag (SR 25504) is turned ON. An error processing program section
can be executed using the CY Flag if desired.
4. If bit 15 of C is ON, a preset message with up to 8 ASCII characters will be
displayed on the Peripheral Device along with the bit address mentioned in
step 2.
Control Data
The function of the control data bits in C are shown in the following diagram.
C: 15 14
08 07
00
Not used. Set to zero.
FAL number
(2-digit BCD, 00 to 99)
Diagnostics output
0 (OFF): Bit address output (binary)
1 (ON): Bit address and message output (ASCII)
Logic Diagnostic Instructions If the time until the logic diagnostics condition goes ON exceeds T, the logic diag-
nostic instructions are searched for the OFF input condition. If more than one
input condition is OFF, the input condition on the highest instruction line and
nearest the left bus bar is selected.
00000
00002
Diagnostic
output
00001
00003
When IR 00000 to IR 00003 are ON, the normally closed condition IR 00002
would be found as the cause of the diagnostic output not turning ON.
Diagnostics Output
There are two ways to output the bit address of the OFF condition detected in the
logic diagnostics condition.
1, 2, 3... 1. Bit address output (used when bit 15 of C is OFF).
Bit 15 of D indicates whether or not bit address information is stored in D+1.
If there is, bit 14 of D indicates whether the input condition is normally open
or closed.
D: 15 14 13
00
Not used.
Input condition
0 (OFF): Normally open
1 (ON): Normally closed
Bit address information
0 (OFF): Not recorded in D+1.
1 (ON): Recorded in D+1.
311
Special Instructions
Section 5-25
D+1 contains the bit address code of the input condition, as shown below.
The word addresses, bit numbers, and TC numbers are in binary.
Data
area
D+1 bit status
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IR, SR
(see
note c)
1
1
0
0
0
1
0
0
Word address
Word address
Bit number
Bit number
HR
LR
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
Word address
Bit number
Bit number
0
1
Word address
* Timer or counter number
TC*
Note a) *For the TC area, bit 09 of D+1 indicates whether the number is a
timer or counter. A 0 indicates a timer, and a 1 indicates a counter.
b) The status of the leftmost bit of the bit number (bit 03) is reversed.
c) Although the same word address designations are used for both
ranges, bit 13 is turned OFF to indicate IR 00000 through SR
25515 and turned ON to indicate SR 25600 through IR 51115
Example: If D + 1 contains 1000 0110 0100 1000, IR 10000 would be indi-
cated as follows:
1000 0110 0100 1000
IR
$64 = 100 Bit 00 (inverting status of bit 03)
2. Bit address and message output (used when bit 15 of C is ON).
Bit 15 of D indicates whether or not there is bit address information stored in
D+1 to D+3. If there is, bit 14 of D indicates whether the input condition is
normally open or closed. Refer to the following table.
Words D+5 to D+8 contain information in ASCII that are displayed on a Pe-
ripheral Device along with the bit address when FPD(––) is executed.
Words D+5 to D+8 contain the message preset by the user as shown in the
following table.
Word
D+1
Bits 15 to 08
Bits 07 to 00
20 = space
First ASCII character of bit address
D+2
Second ASCII character of bit address Third ASCII character of bit address
Fourth ASCII character of bit address Fifth ASCII character of bit address
D+3
D+4
2D = “–”
“0”=normally open,
“1”=normally closed
D+5
D+6
D+7
D+8
First ASCII character of message
Third ASCII character of message
Fifth ASCII character of message
Second ASCII character of message
Fourth ASCII character of message
Sixth ASCII character of message
Seventh ASCII character of message Eighth ASCII character of message
Note If 8 characters are not needed in the message, input “0D” after the
last character.
Determining Monitoring Time The procedure below can be used to automatically set the monitoring time, T,
under actual operating conditions when specifying a word operand for T. This
operation cannot be used if a constant is set for T.
1, 2, 3... 1. Switch the PC to MONITOR Mode operation.
2. Connect a Peripheral Device, such as a Programming Console.
3. Use the Peripheral Device to turn ON control bit AR 2508.
4. Execute the program with AR 2508 turned ON. If the monitoring time cur-
rently in T is exceeded, 1.5 times the actual monitoring time will be stored in
T. FAL(06) errors will not occur while AR 2508 is ON.
5. Turn OFF AR 2508 when an acceptable value has been stored in T.
312
Special Instructions
Section 5-25
Example
In the following example, the FPD(––) is set to display the bit address and mes-
sage (“ABC”) when a monitoring time of 123.4 s is exceeded.
SR 25315
SR 25315
LR 0000
MOV(21)
Address Instruction
Operands
25315
#4142
HR 15
00000
00001
LD
MOV(21)
#
4142
15
MOV(21)
#430D
HR
00002
00003
LD
25315
HR 16
MOV(21)
#
430D
16
FPD(––)
#8010
#1234
HR 10
HR
LR
00004
00005
LD
0000
FPD(––)
#
8010
1234
10
#
SR 25504
(CY Flag)
HR
INC(38)
00006
00007
AND
25504
DM 0100
INC(38)
DM
0100
10000
10001
10002
10003
10000
10001
10002
10003
LR 0015
00008
00009
00010
00011
00012
00013
LD
OR
LD NOT
OR NOT
AND LD
OUT
LR
0015
FPD(––) is executed and begins monitoring when LR 0000 goes ON. If LR 0015
does not turn ON within 123.4 s and IR 10000 through IR 10003 are all ON,
IR 10002 will be selected as the cause of the error, an FAL(06) error will be gen-
erated with an FAL number of 10, and the bit address and preset message
(“10002–1ABC”) will be displayed on the Peripheral Device.
HR 10
HR 11
HR 12
HR 13
HR 14
HR 15
HR 16
HR 17
HR 18
0000
0000
0000
0000
0000
4142
430D
0000
0000
HR 10
HR 11
HR 12
HR 13
HR 14
HR 15
HR 16
HR 17
HR 18
C000
2031
3030
3032
2D31
4142
430D
0000
0000
Indicates information, normally closed condition
“1”
“00”
“02”
“–1”
“AB”
“C”, and CR code
The last two words are ignored.
(Displayed as spaces.)
Flags
ER:
CY:
T is not BCD.
C is not a constant or the rightmost two digits of C are not BCD 00 to 99.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
ON when the time between the execution of FPD(––) and the execution
of a diagnostic output exceeds T.
313
Special Instructions
Section 5-25
5-25-13 DATA SEARCH – SRCH(––)
Ladder Symbols
Operand Data Areas
N: Number of words
SRCH(––)
@SRCH(––)
IR, SR, AR, DM, HR, TC, LR, #
N
N
R : First word in range
1
R
R
1
1
IR, SR, AR, DM, HR, TC, LR
C: Comparison data, result word
IR, SR, AR, DM, HR, LR
C
C
Limitations
Description
N must be BCD between 0001 to 6656.
R and R +N–1 must be in the same data area.
1
1
When the execution condition is OFF, SRCH(––) is not executed. When the
execution condition is ON, SRCH(––) searches the range of memory from R to
1
R +N–1 for addresses that contain the comparison data in C. If one or more ad-
1
dresses contain the comparison data, the EQ Flag (SR 25506) is turned ON and
the lowest address containing the comparison data is identified in C+1. The ad-
dress is identified differently for the DM area:
1, 2, 3... 1. For an address in the DM area, the word address is written to C+1. For ex-
ample, if the lowest address containing the comparison data is DM 0114,
then #0114 is written in C+1.
2. For an address in another data area, the number of addresses from the be-
ginning of the search is written to C+1. For example, if the lowest address
containing the comparison data is IR 114 and the first word in the search
range is IR 014, then #0100 is written in C+1.
If none of addresses in the range contain the comparison data, the EQ Flag (SR
25506) is turned OFF and C+1 is left unchanged.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
N is not BCD between 0001 and 6655.
EQ:
ON when the comparison data has been matched in the search range.
314
Special Instructions
Section 5-25
Example
In the following example, the 10 word range from DM 0010 to DM 0019 is
searched for addresses that contain the same data as DM 0000 (#FFFF). Since
DM 0012 contains the same data, the EQ Flag (SR 25506) is turned ON and
#0012 is written to DM 0001.
00001
Address Instruction
Operands
00001
@SRCH(––)
#0010
00000
00001
LD
@SRCH(––)
DM 0010
#
0010
0010
0000
DM 0000
DM
DM
DM 0010 0000
DM 0011 9898
DM 0012 FFFF
DM 0013 9797
DM 0014 AAAA
DM 0015 9595
DM 0016 1414
DM 0017 0000
DM 0018 0000
DM 0019 FFFF
DM 0000 FFFF
DM 0001 0012
5-25-14 EXPANSION DM READ – XDMR(––)
Ladder Symbols
Operand Data Areas
N: Number of words
IR, SR, AR, DM, HR, TC, LR, #
S: First expansion DM word
IR, SR, AR, DM, HR, TC, LR, #
D: First destination word
XDMR(––)
@XDMR(––)
N
S
D
N
S
D
IR, SR, AR, DM, HR, LR
Limitations
N must be BCD between 0001 and 3000.
S must be BCD between 7000 and 9999.
S and S+N–1 must be in the same data area, as must D and D+N–1.
Description
Precautions
When the execution condition is OFF, XDMR(––) is not executed. When the
execution condition is ON, XDMR(––) copies the contents of expansion DM
words S through S+N–1 to the destination words D through D+N–1.
The Expansion DM area must be set in the PC Setup before it can be used in
programming. Do not exceed the set range of the Expansion DM area.
Execution of XDMR(––) is given priority whenever a power interruption occurs.
Flags
ER:
The specified expansion DM words are non-existent. Make sure that
the specified words have been allocated to expansion DM. Refer to
7-2-15 UM Area Allocation for details.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
N is not BCD between 0001 and 3000.
S is not BCD between 7000 and 9999.
315
Special Instructions
Section 5-25
Example
In the following example, the 100 word range from DM 7000 through DM 7099 is
copied to DM 0010 through DM 0109 when IR 00001 is ON.
00001
Address Instruction
Operands
00001
@XDMR(––)
#0100
00000
00001
LD
@XDMR(––)
#7000
#
0100
7000
0010
DM 0010
#
DM
DM 7000 to DM 7099
DM 7000
DM 9999
DM 0010 to DM 0109
DM 0000
DM 6143
5-25-15 INDIRECT EM ADDRESSING – IEMS(––)
Ladder Symbols
Operand Data Areas
C: Control word
IEMS(––)
@IEMS(––)
000, #E000, or #E0B1 to #E0B3
C
C
Limitations
Description
C must be 000, #E000, #E0B0, #E0B1, or #E0B2.
When executed with an ON execution condition, IEMS(––) changes the destina-
tion of indirect DM addressing (ꢀDM) to DM or the specified EM bank. The cur-
rent EM bank number can also be changed when indirect addressing is changed
to EM.
The destination for ꢀDM is switched to the DM area at the start of an interrupt
subroutine. It is also returned to the DM area at the beginning of each scan.
The following table shows the allowed values for C and their functions:
C
IEMS(––) Operation
000
Switches the destination of ꢀDM to the DM area.
#E000 Switches the destination of ꢀDM to the current bank in the EM area.
#E0B0 Switches the destination of ꢀDM to the bank 0 in the EM area.
#E0B1 Switches the destination of ꢀDM to the bank 1 in the EM area.
#E0B2 Switches the destination of ꢀDM to the bank 2 in the EM area.
The content of DM 6031 indicates the current ꢀDM destination and the current
EM bank number as shown in the following table. Use DM 6031 in the ladder-dia-
gram program to determine if the contents of indirect DM addressing is the DM or
EM area. (Programming Devices cannot be used here because bits 08 to 15 will
always indicate the DM area when read from the Programming Device.)
Word
Bits 00 to 07
Bits 08 to 15
DM 6031 Current EM bank number (00 to 02) ꢀDM destination (00: DM; 80: EM)
316
Special Instructions
Section 5-25
Note Input 000 for the second and third operands when using replacement instruc-
tions.
Flags
ER:
C is not one of the allowed values.
Example
In the following example, IEMS(––) changes the destination for ꢀDM to EM
bank 1 and uses indirect addressing to move #1234 into EM 0001 in EM bank 1.
00000
IEMS3
#EOBI
MOV
#1234
: D0000
EM0000
0001
DM0000
0001
1234
5-25-16 SELECT EM BANK – EMBC(––)
Ladder Symbols
Operand Data Areas
N: Bank number
EMBC(––)
@EMBC(––)
IR, SR, AR, DM, HR, LR, #
N
N
Limitations
Description
N must be 0000, 0001, or 0002 and the bank number specified by N must exist in
the CPU Unit.
When executed with an ON execution condition, EMBC(––) changes the current
EM bank to the specified bank number. The CPU Unit can access only the cur-
rent bank, which is indicated in bits 00 through 07 of DM 6031.
An error will occur and EMBC(––) won’t be executed if the specified bank num-
ber doesn’t exist in the CPU Unit.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
The specified bank number, N, doesn’t exist in the CPU Unit.
Example
In the following example, EMBC(––) changes the current bank to bank number 2
when IR 00000 is ON.
00000
EMBC
#0002
00001
@EMBC
#1005
317
Network Instructions
Section 5-26
5-26 Network Instructions
The network instructions are used for communicating with other PCs, BASIC
Units, or host computers linked through the SYSMAC NET Link System, SYS-
MAC LINK System, Ethernet System, or Controller Link System.
5-26-1 NETWORK SEND – SEND(90)
Operand Data Areas
Ladder Symbols
S: Source beginning word
IR, SR, AR, DM, HR, TC, LR
D: Destination beginning word
IR, SR, AR, DM, HR, TC, LR
C: First control data word
SEND(90)
@SEND(90)
S
D
C
S
D
C
IR, SR, AR, DM, HR, TC, LR
Limitations
Description
C through C+2 must be within the same data area and must be within the values
specified below. To be able to use SEND(90), the system must have a SYSMAC
NET Link, SYSMAC LINK Unit, PC Card Unit, or Controller Link Unit mounted.
When the execution condition is OFF, SEND(90) is not executed. When the
execution condition is ON, SEND(90) transfers data beginning at word S, to ad-
dresses specified by D in the designated node on the SYSMAC NET Link, SYS-
MAC LINK System, Ethernet System, or Controller Link System. The control
words, beginning with C, specify the number of words to be sent, the destination
node, and other parameters. The contents of the control data depends on
whether a transmission is being sent in a SYSMAC NET Link System, a SYS-
MAC LINK System, an Ethernet System, or a Controller Link System.
The status of bit 15 of C+1 determines whether the instruction is for a SYSMAC
NET Link System or a SYSMAC LINK/Ethernet/Controller Link System.
Control Data
Ethernet Systems
Set the destination node number to 0 to send the data to all nodes. Refer to the
PC Card Unit Operation Manual for details.
Word
Bits 00 to 07
Bits 08 to 15
C
Number of words (0 to 1000 in 4-digit hexadecimal, i.e., 0000
to 03E8
hex hex)
C+1
Response time limit (0.1 and 25.4 Bits 08 to 11:
seconds in 0.1 s increments in
2-digit hexadecimal without
No. of retries (0 to 15 in
hexadecimal,
decimal point, i.e., 01
to FF
)
hex
i.e., 0
to F
)
hex
hex
hex
Default is 00
(2 seconds)
Bit 12 ON: Direct destination
beginning word
hex
designation
OFF: Indirect designation
Bit 13 ON: Response not
returned.
OFF: Response returned.
Bit 14 ON: Operating level 0
OFF: Operating level 1
Bit 15: Set to 1.
C+2
Destination node (0 to 127 in
2-digit hexadecimal, i.e., 00
Bits 08 to 12:
to
Unit address of destination
hex
7E )*
node. Set to 00
.
hex
hex
Bits 13 to 15: Set to 0.
318
Network Instructions
Section 5-26
SYSMAC NET Link Systems The destination port number is always set to 0. Set the destination node number
to 0 to send the data to all nodes. Set the network number to 0 to send data to a
node on the same Subsystem (i.e., network). Refer to the SYSMAC NET Link
System Manual for details.
Word
Bits 00 to 07
Bits 08 to 15
C
Number of words (0 to 1000 in 4-digit hexadecimal, i.e., 0000
to 03E8
)
hex
hex
C+1
Network number (0 to 127 in 2-digit Bit 12 ON: Direct destination
hexadecimal, i.e., 00
to 7F
)
hex
beginning word
designation
hex
OFF: Indirect designation
Bit 14 ON: Operating level 0
OFF: Operating level 1
Bits 08 to 11, 13 and 15: Set to 0.
C+2
Destination node (0 to 126 in 2-digit Destination port
hexadecimal, i.e., 00 to 7E )* NSB: 00
hex
hex
NSU: 01/02
*The node number of the PC executing the send may be set.
SYSMAC LINK Systems
Set the destination node number to 0 to send the data to all nodes. Refer to the
SYSMAC LINK System Manual for details.
Word
Bits 00 to 07
Bits 08 to 15
C
Number of words (0 to 1000 in 4-digit hexadecimal, i.e., 0000
to 03E8
hex hex)
C+1
Response time limit (0.1 and 25.4 Bits 08 to 11:
seconds in 2-digit hexadecimal
without decimal point, i.e., 00
No. of retries (0 to 15 in
hexadecimal,
to
hex
FF
)
i.e., 0
to F
)
hex
hex
hex
Note: The response time will be Bit 12 ON: Direct destination
2 seconds if the limit is set to 0
There will be no time limit if the
.
beginning word
designation
hex
time limit is set to FF
.
OFF: Indirect designation
hex
Bit 13 ON: Response not
returned.
OFF: Response returned.
Bit 14 ON: Operating level 0
OFF: Operating level 1
Bit 15: Set to 1.
C+2
Destination node (0 to 62 in 2-digit Set to 0.
hexadecimal, i.e., 00 to 3E )*
hex
hex
*The node number of the PC executing the send cannot be set.
319
Network Instructions
Section 5-26
Controller Link Systems
SEND(90) transmits “n” words beginning with S (the beginning source word for
data transmission at the source node) to the “n” words beginning with D (the be-
ginning destination word for data reception at destination node N).
Source node
0
Destination node N
0
15
15
@SEND(90)
D
S
S: Source node beginning send word
D: Destination node beginning receive word
C: Source node first control data word
“n” number
of send
n
L
L
S
D
C
words
n
1514
0
C
“n” number of send words
0000 to 03DE (Hex): 0 to 990 words
0: Destination network address not specified (local network)
1: Destination network address specified.
1514131211
1
8 7
0
C +1
Response monitor time
00 (Hex): 2 s (for 2 Mbps)
Number of retries
0 to F (Hex): 0 to 15 retries
Direct/Indirect
0: Direct; 1: Indirect
4 s (for 1 Mbps)
8 s (for 500 Kbps)
0: Response required
1: Response not required
01 to FE (Hex): 0.1 to 25.4 s (unit: 0.1 s)
FF (Hex):
No response monitoring
0: Operating level 1
1: Operating level 0
Always “1” for Controller Link Networks
15
8 7
0
C + 2
Destination node address (N)
00 to 20 (Hex): 0 to 32
Destination unit address
The same data can be broadcast to all nodes
on the network by setting the destination node ad-
dress to FF (Hex).
The range of node addresses will vary for networks
other than Controller Link Networks.
00 (Hex):
01 (Hex):
PC’s CPU Unit
Computer (user program)
10 to 1F (Hex): Unit nos. 0 to 15
FE (Hex):
Unit connected to network
15
0
C + 3
0
0
Destination network address
00 (Hex): Local network
01 to 7F (Hex): 1 to 127
This setting is enabled only when “Destination network address specified” is set in word C.
When specifying a destination network address, set all the nodes in the routing tables. For
details on routing tables, refer to refer to the section on network interconnections in the Control-
ler Link Unit Operation Manual (W309).
Note 1. When communicating in the same network with CV-series PCs manufac-
tured prior to April 1996, the local network address cannot be set to “00.” Set
a number other than “00” as the local network address in the routing tables,
and then specify that number.
2. With the message service, there is no guarantee that a message to a des-
tination node will reach its destination. It is always possible that the mes-
sage may be lost in transit due to noise or some other condition. When using
the message service, it is advisable to prevent this situation from occurring
by performing resend processing at the node where instructions are issued.
With the SEND, RECV, and CMND(194) instructions, resend processing is
performed automatically once the number of retries has been set, so be sure
to specify a number other than “0” for the number of retries.
320
Network Instructions
Section 5-26
Indirect Destination Beginning Word Designations
D is used to specify the destination beginning word as follows when indirect
specification is designated:
12 to 15
Area type
08 to 11
04 to 07
00 to 03
D
0
Word no. (5th
digit)
D+1 Word no. (4th
digit)
Word no. (3rd
digit)
Word no. (2nd
digit)
Word no. (1st
digit)
SYSMAC NET Link Systems Indirect designations depend on the series of the destination PC.
CV-series PCs
Addresses in parentheses are for the CV500.
Designation
Corresponding CV-series PC words
Area
IR area
Area
code
Word
number
Area
Word number
CIO Area
00
06
07
08
0 to 999
0 to 63
0 to 999
LR area
HR area
SR area
1000 to 1063
0 to 99
1064 to 1163
0 to 27
1164 to 1191
Timer area (PV) 03
0 to 1023
Timer Area
(PV)
0 to 1023 (0 to 511)
DM area
05
0 to 24575
DM Area
0 to 24575 (0 to 8191)
C-series PCs
Designation
Area code
Area
IR area
Word number
00
06
07
08
0 to 511
0 to 63
LR area
HR area
SR area
0 to 99
0 to 27
Timer area (PV) 03
0 to 511
0 to 6655
0 to 6143
DM area
EM area
05
10 to 17 (Bank 0 to 7)
28 to 2F (Bank 8 to 15)
18
(Current bank)
SYSMAC LINK/Ethernet
Systems
Indirect designations depend on the series of the destination PC.
CV-series PCs
Designation
Area
CIO Area
Area code
Word number
0 to 2555
00
01
02
03
04
05
CPU Bus Link Area
Auxiliary Area
Timer Area
0 to 255
0 to 511
0 to 1023
0 to 1023
0 to 24575
0 to 32765
Counter Area
DM Area
EM Area
10 to 17:Bank 0 to 7
18: Current bank
321
Network Instructions
Section 5-26
C-series PCs
Designation
Area
IR area
Area
code
Word
number
00
0 to 511
0 to 63
LR area
HR area
SR area
06
07
08
0 to 99
0 to 27
Timer area (PV) 03
DM area 05
0 to 511
0 to 6655
Controller Link Systems
CV-series PCs have a larger area than C200HX/HG/HE PCs, so the beginning
words for sending and receiving at destination nodes cannot always be directly
specified by means of SEND(192) and RECV(193) operands. Moreover, de-
pending on circumstances, it may be desirable to change the beginning word at
destination nodes.
In such cases, set the “Direct/Indirect” control data designation to “1” (Indirect),
and specify the beginning words for sending as described below.
The beginning receive word is determined by the contents of the destination
node’s D and D+1 words.
@SEND(90)
S: Source node beginning send word
S
D
C
D: Destination node beginning receive word
C: Source node first control data word
1514131211109 8 7 6 5 4 3 2 1 0
0 0 0 0
Word address (5th digit)
D
Area code*
D+1
Word address (1st digit)
Word address (2nd digit)
Word address (3rd digit)
Word address (4th digit)
Note Specify the area code according to the following table.
Destination node: C200HX/HG/HE PC
Area
Destination node: CV-series PC
Area
Code
Code
IR (Internal Relay)
LR (Link Relay)
00
06
07
08
03
05
CIO
00
01
02
03
04
05
CPU Bus Link
Auxiliary
HR (Holding Relay)
AR (Auxiliary Relay)
TC (Timer/Counter)
DM (Data Memory)
EM (Expansion DM)
Timer
Counter
DM (Data Memory)
EM (Expansion DM)
Banks 0 to 7
Banks 8 to 15
Current bank
10 to 17
28 to 2F
18
Banks 0 to 7
Current bank
10 to 17
18
322
Network Instructions
Section 5-26
Examples
This example is for a SYSMAC NET Link System. When 00000 is ON, the follow-
ing program transfers the content of IR 001 through IR 005 to LR 20 through LR
24 on node 10.
00000
Address Instruction
Operands
00000
SEND(90)
001
00000
00001
LD
SEND(90)
LR 20
001
20
DM 0010
LR
DM
0010
Node 10
15
0
DM 0010
DM 0011
DM 0012
0
0
0
0
0
0
0
0
0
5
0
IR 001
IR 002
IR 003
IR 004
IR 005
LR 20
LR 21
LR 22
LR 23
LR 24
A
Flags
ER:
The specified node number is greater than 126 in a SYSMAC NET Link
System, greater than 62 in a SYSMAC LINK System, or greater than
127 in an Ethernet or Controller Link System.
The sent data overruns the data area boundaries.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
There is no SYSMAC NET Link/SYSMAC LINK/PC Card/Controller
Link Unit.
5-26-2 NETWORK RECEIVE – RECV(98)
Operand Data Areas
Ladder Symbols
S: Source beginning word
IR, SR, AR, DM, HR, TC, LR
D: Destination beginning word
IR, SR, AR, DM, HR, TC, LR
C: First control data word
RECV(98)
@RECV(98)
S
D
C
S
D
C
IR, SR, AR, DM, HR, TC, LR
Limitations
Description
C through C+2 must be within the same data area and must be within the values
specified below. To be able to use RECV(98), the system must have a SYSMAC
NET Link, SYSMAC LINK Unit, or PC Card Unit mounted.
When the execution condition is OFF, RECV(98) is not executed. When the
execution condition is ON, RECV(98) transfers data beginning at S from a node
on the SYSMAC NET Link, SYSMAC LINK, Ethernet System to words beginning
at D. The control words, beginning with C, provide the number of words to be
received, the source node, and other transfer parameters.
The status of bit 15 of C+1 determines whether the instruction is for a SYSMAC
NET Link System or a SYSMAC LINK/Ethernet System.
323
Network Instructions
Section 5-26
Control Data
Ethernet Systems
Refer to the PC Card Unit Operation Manual for details.
Word
Bits 00 to 07
Bits 08 to 15
C
Number of words (0 to 1000 in 4-digit hexadecimal, i.e., 0000
to 03E8
hex hex)
C+1
Response time limit (0.1 and 25.4 Bits 08 to 11:
seconds in 0.1 s increments in
2-digit hexadecimal without
No. of retries (0 to 15 in
hexadecimal,
decimal point, i.e., 01
to FF
)
hex
i.e., 0
to F
)
hex
hex
hex
Default is 00
(2 seconds)
Bit 12 ON: Direct source
beginning word
hex
designation
OFF: Indirect designation
Bit 13 ON: Response not
returned.
OFF: Response returned.
Bit 14 ON: Operating level 0
OFF: Operating level 1
Bit 15: Set to 1.
C+2
Source node (0 to 127 in 2-digit
hexadecimal, i.e., 00 to 7F )*
Bits 08 to 12:
Unit address of source
hex
hex
node. Set to 00
.
hex
Bits 13 to 15: Set to 0.
SYSMAC NET Link Systems The source port number is always set to 0. Set the network number to 0 to re-
ceive data to a node on the same Subsystem (i.e., network). Refer to the SYS-
MAC NET Link System Manual for details.
Word
Bits 00 to 07
Bits 08 to 15
C
Number of words (0 to 1000 in 4-digit hexadecimal, i.e., 0000
to 03E8
)
hex
hex
C+1
Network number (0 to 127 in 2-digit Bit 12 ON: Direct source
hexadecimal, i.e., 00
to 7F
)
hex
beginning word designation
OFF: Indirect designation
hex
Bit 14 ON: Operating level 0
OFF: Operating level 1
Bits 08 to 11, 13 and 15: Set to 0.
C+2
Source node (1 to 126 in 2-digit
hexadecimal, i.e., 01 to 7E
Source port
NSB: 00
)
hex
hex
NSU: 01/02
SYSMAC LINK Systems
Refer to the SYSMAC LINK System Manual for details.
Word
Bits 00 to 07
Bits 08 to 15
C
Number of words (0 to 256 in 4-digit hexadecimal, i.e., 0000
to 0100
)
hex
hex
C+1
Response time limit (0.1 and 25.4 Bits 08 to 11:
seconds in 2-digit hexadecimal
without decimal point, i.e., 00
No. of retries (0
to 15 in
to
hex
FF
)
hexadecimal,
hex
i.e., 0
to F
)
hex
hex
Note: The response time will be
2 seconds if the limit is set to 0
There will be no time limit if the
.
Bit 12 ON: Direct source
beginning word
hex
time limit is set to FF
.
designation
OFF: Indirect designation
hex
Bit 13: Set to 0.
Bit 14 ON: Operating level 0
OFF: Operating level 1
Bit 15: Set to 1.
Set to 0.
C+2
Source node (0 to 62 in 2-digit
hexadecimal, i.e., 00 to 3E
)
hex
hex
324
Network Instructions
Section 5-26
Controller Link Systems
RECV(98) receives “m” words beginning with S (the beginning word for data
transmission at the destination node, M) to the words from D (the beginning word
for data reception at the source node) onwards.
Source node
Destination node M
15
15
0
0
D
S
“m” num-
L
ber of
send
L
m
words
@RECV(98)
S: Destination node beginning send word
D: Source node beginning receive word
C: Source node first control data word
S
D
C
1514
0
C
“m” number of send words
0000 to 03DE (Hex): 0 to 990 words
0: Source network address not specified (local network)
1: Source network address specified.
1514131211
C + 1 1
8 7
0
Response monitor time
Number of retries
0 to F (Hex): 0 to 15 retries
Direct/Indirect
0: Direct; 1: Indirect
0: Response required
1: Response not required
00 (Hex):
2 s (for 2 Mbps)
4 s (for 1 Mbps)
8s (for 500 Kbps)
01 to FE (Hex): 0.1 to 25.4 s (unit: 0.1 s)
FF (Hex): No response monitoring
0: Operating level 1
1: Operating level 0
Always “1” for Controller Link Networks
15
8 7
0
C + 2
Destination (transmission source) node address (M)
00 to 20 (Hex): 0 to 32
Destination (transmission source) unit address
The range of node addresses will vary for networks
other than Controller Link Networks.
00 (Hex):
01 (Hex):
PC’s CPU Unit
Computer (user program)
10 to 1F (Hex): Unit nos. 0 to 15
FE (Hex):
Unit connected to network
15
0
C + 3
0
0
Destination network address
00 (Hex): Local network
01 to 7F (Hex): 1 to 127
This setting is enabled only when “Destination network address specified” is set in word C.
When specifying the destination network address, set all the nodes in the routing tables. For
details on the routing tables, refer to the section on network interconnections in the Controller
Link Unit Operation Manual (W309).
Note 1. When communicating in the same network with CV-series PCs manufac-
tured prior to April 1996, the local network address cannot be set to “00.” Set
a number other than “00” as the local network address in the routing tables,
and then specify that number.
325
Network Instructions
Section 5-26
2. With the message service, there is no guarantee that a message to a des-
tination node will reach its destination. It is always possible that the mes-
sage may be lost in transit due to noise or some other condition. When using
the message service, it is advisable to prevent this situation from occurring
by performing resend processing at the node where instructions are issued.
With the SEND, RECV, and CMND(194) instructions, resend processing is
performed automatically once the number of retries has been set, so be sure
to specify a number other than “0” for the number of retries.
Indirect Destination Beginning Word Designations
D is used to specify the sourced beginning word when indirect specification is
designated using the same designations as those used for the destination be-
ginning word for SEND(90).
Examples
This example is for a SYSMAC NET Link System. When 00000 is ON, the follow-
ing program transfers the content of IR 001 through IR 005 to LR 20 through LR
24 on node 10.
00000
Address Instruction
Operands
00000
RECV(98)
001
00000
00001
LD
RECV(98)
LR 20
001
20
DM 0010
LR
DM
0010
Node 10
15
0
DM 0010
DM 0011
DM 0012
0
0
0
0
0
0
0
0
0
5
0
IR 001
IR 002
IR 003
IR 004
IR 005
LR 20
LR 21
LR 22
LR 23
LR 24
A
Flags
ER:
The specified node number is greater than 126 in a SYSMAC NET Link
System, greater than 62 in a SYSMAC LINK System, or greater than
127 in an Ethernet or Controller Link System.
The received data overflows the data area boundaries.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
There is no SYSMAC NET Link/SYSMAC LINK/PC Card/Controller
Link Unit.
326
Network Instructions
Section 5-26
5-26-3 About Network Communications
SEND(90) and RECV(98) are based on command/response processing. That
is, the transmission is not complete until the sending node receives and ac-
knowledges a response from the destination node. Note that the
SEND(90)/RECV(98) Enable Flag is not turned ON until the first END(01) after
the transmission is completed. Refer to the SYSMAC NET Link System Manual
or SYSMAC LINK System Manual for details about command/response opera-
tions.
If multiple SEND(90)/RECV(98) operations are used, the following flags must be
used to ensure that any previous operation has completed before attempting
further send/receive SEND(90)/RECV(98) operations
SR Flag
Functions
SEND(90)/RECV(98)
Enable Flags
(SR 25201, SR 25204)
OFF during SEND(90)/RECV(98) execution (including
command response processing). Do not start a
SEND(90)/RECV(98) operation unless this flag is ON.
SEND(90)/RECV(98)
Error Flags
OFF following normal completion of SEND/RECV (i.e.,
after reception of response signal)
(SR 25200, SR 25203)
ON after an unsuccessful SEND(90)/RECV(98) attempt.
Error status is maintained until the next
SEND(90)/RECV(98) operation.
Error types:
Time-out error (command/response time greater than 1
second)
Transmission data errors
Timing
Successful
send/receive
execution
Send/receive
error
Instruction
received
Transmission Instruction Transmission Instruction
completes
received error
received
normally
Data Processing for
SEND(90)/RECV(98)
Data is transmitted for SEND(90) and RECV(98) for all PCs when
SEND(90)/RECV(98) is executed. Final processing for transmissions/recep-
tions is performed during servicing of peripheral devices and Link Units.
Programming Example:
Multiple
SEND(90)/RECV(98)
To ensure successful SEND(90)/RECV(98) operations, your program must use
the SEND(90)/RECV(98) Enable Flags and SEND(90)/RECV(98) Error Flags to
confirm that execution is possible. The following program shows one example of
how to do this for a SYSMAC NET Link System.
327
Network Instructions
Section 5-26
SEND(90)/RECV(98) Enable Flag
00000
25204
12802
12800 prevents execution of SEND(90) until
RECV(98) (below) has completed. IR 00000
is turned ON to start transmission.
S
R
KEEP(11)
12800
12801
12800
@MOV(21)
#000A
DM 0000
@MOV(21)
#0000
DM 0001
Data is placed into control data words to
specify the 10 words to be transmitted to
node 3 in operating level 1 of network 00
(NSB).
@MOV(21)
#0003
DM 0002
XFER(70)
#0010
000
DM 0010
@SEND(90)
DM 0010
DM 0020
DM 0000
SEND(90)/RECV(98) Error Flag
12800
25203
Turns ON to indicate transmission error.
Resets 12800, above.
00200
12800
00001
25204
DIFU(13)
S
12801
25204
12800
25203
12802 prevents execution of RECV(98)
when SEND(90) above has not completed.
IR 00001 is turned ON to start transmission.
KEEP(11)
12803
12802
12802
R
25204
XFER(70)
Transmitted data moved into words
beginning at DM 0030 for storage.
#0016
000
DM 0030
12802
@MOV(21)
#0010
DM 0003
Data moved into control data words to
specify the 16 words to be transmitted from
node 126 in operating level 1 of network 00
(NSB).
@MOV(21)
#0000
DM 0004
@MOV(21)
#007E
DM 0005
@RECV(98)
HR 10
LR 10
DM 0003
SEND(90)/RECV(98) Error Flag
12802
12802
25203
Turns ON to indicate reception error.
Resets 12802, above.
00201
25204
DIFU(13)
12803
328
Serial Communications Instructions
Section 5-27
Address Instruction
Operands
Address Instruction
Operands
12800
00000 LD
00000
25204
12802
12801
12800
12800
00019 AND NOT
00020 LD
00001 AND
12803
12802
12802
25204
25203
00002 AND NOT
00003 LD
00021 KEEP(11)
00022 LD
00004 KEEP(11)
00005 LD
00023 AND
00024 AND NOT
00025 XFER(70)
00006 @MOV(21)
#
000A
0000
#
0016
000
DM
00007 @MOV(21)
00008 @MOV(21)
00009 @XFER(70)
DM
0030
12802
#
0000
0001
00026 LD
DM
00027 @MOV(21)
#
0010
0003
#
0003
DM
DM
00002
00028 @MOV(21)
00029 @MOV(21)
00030 @RECV(98)
#
0000
0004
#
0010
000
DM
DM
0002
#
007E
0005
00010 @SEND(90)
DM
DM
DM
DM
0010
0020
HR
LR
10
10
0000
00011
LD
12800
25203
00200
12800
25204
12801
00001
25204
DM
0003
00012 AND
00013 OUT
00014 LD
00031 LD
12802
25203
00201
12802
25204
12803
00032 AND
00033 OUT
00034 LD
00015 AND
00016 DIFU(13)
00017 LD
00035 AND
00036 DIFU(13)
00018 AND
5-27 Serial Communications Instructions
5-27-1 RECEIVE – RXD(––)
Operand Data Areas
Ladder Symbols
D: First destination word
IR, SR, AR, DM, HR, TC, LR
C: Control word
RXD(––)
@RXD(––)
D
C
N
D
C
N
IR, SR, AR, DM, HR, TC, LR, #
N: Number of bytes
IR, SR, AR, DM, HR, TC, LR, #
Limitations
Description
D and D+(N÷2)–1 must be in the same data area.
N must be BCD from #0000 to #0256.
When the execution condition is OFF, RXD(––) is not executed. When the
execution condition is ON, RXD(––) reads N bytes of data received at the periph-
eral port, and then writes that data in words D to D+(N÷2)–1. Up to 256 bytes of
data can be read at one time.
If fewer than N bytes are received, the amount received will be read.
329
Serial Communications Instructions
Section 5-27
Note RXD(––) is required to receive data via the peripheral port or RS-232C port only.
Transmission sent from a host computer to a Host Link Unit are processed auto-
matically and do not need to be programmed.
Caution The PC will be incapable of receiving more data once 256 bytes have been re-
ceived if received data is not read using RXD(––). Read data as soon as pos-
sible after the Reception Completed Flag is turned ON (SR 26414 for the periph-
eral port, SR26406 for the RS-232C port).
!
Control Word
The value of the control word determines the port from which data will be read
and the order in which data will be written to memory.
Digit number: 3 2 1 0
Byte order
0: Most significant bytes first
1: Least significant bytes first
CTS and DSR signal monitoring
0: Don’t monitor CTS and DSR signals.
1: Monitor the CTS signal. (Output to bit 15 of D.)
2: Monitor the DSR signal. (Output to bit 15 of D.)
3: Monitor the CTS and DSR signals. (Output to bits 15 and 14 of D.)
Auxiliary reception port (when DR-15 is 0.)
0: Internal RS-232C port
1: Communications port A
2: Communications port B
Port
0: RS-232C port
1: Peripheral port
The order in which data is written to memory depends on the value of digit 0 of C.
Eight bytes of data 12345678... will be written in the following manner:
Digit 0 = 0
Digit 0 = 1
MSB LSB
MSB LSB
D
1
3
5
7
2
4
6
8
D
2
4
6
8
1
3
5
7
D+1
D+2
D+3
D+1
D+2
D+3
Flags
ER:
The CPU Unit is not equipped with an RS-232C port.
Another device is not connected to the specified port.
There is an error in the communications settings (PC Setup) or the oper-
and settings.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
The destination words (D to D+(N÷2)–1) exceed the data area.
Peripheral Port
26414: SR 26414 will be turned ON when data has been received normally at
the peripheral port and will be reset when the data is read using
RXD(––) is executed.
266:
SR 266 contains the number of bytes received at the peripheral port and
is reset to 0000 when RXD(––) is executed.
RS-232C Port
330
Serial Communications Instructions
Section 5-27
26406: SR 26406 will be turned ON when data has been received normally at
the peripheral port and will be reset when the data is read using
RXD(––) is executed.
265:
SR 265 contains the number of bytes received at the RS-232C port and
is reset to 0000 when RXD(––) is executed.
Note Communications flags and counters can be cleared either by specifying 0000 for
N or using the Port Reset Bit (SR 25208 for peripheral port and SR 25209 for
RS-232C port).
5-27-2 TRANSMIT – TXD(––)
Operand Data Areas
Ladder Symbols
S: First source word
IR, SR, AR, DM, HR, TC, LR
C: Control word
TXD(––)
@TXD(––)
S
C
N
S
C
N
IR, SR, AR, DM, HR, TC, LR, #
N: Number of bytes
IR, SR, AR, DM, HR, TC, LR, #
Limitations
Description
S and S+(N÷2)–1 must be in the same data area.
N must be BCD from #0000 to #0256. (#0000 to #0061 in host link mode)
When the execution condition is OFF, TXD(––) is not executed. When the
execution condition is ON, TXD(––) reads N bytes of data from words S to
S+(N÷2)–1, converts it to ASCII, and outputs the data from the specified port.
TXD(––) operates differently in host link mode and RS-232C mode, so these
modes are described separately.
Note The following flags will be ON to indicate that communications are possible
through the various ports. Be sure the corresponding flag is ON before executing
TXD(––).
SR 26405:
SR 26413:
SR 26705:
SR 26713:
RS-232C port
Peripheral port
Host Link Unit #0
Host Link Unit #1
Host Link Mode
N must be BCD from #0000 to #0061 (i.e., up to 122 bytes of ASCII). The value of
the control word determines the port from which data will be output, as shown
below.
Digit number: 3 2 1 0
Byte order
0: Most significant bytes first
1: Least significant bytes first
CTS and DSR signal monitoring (see note)
0: Don’t monitor CTS and DSR signals.
1: Monitor the CTS signal. (Output to bit 15 of D.)
2: Monitor the DSR signal. (Output to bit 15 of D.)
3: Monitor the CTS and DSR signals. (Output to bits 15 and 14 of D.)
Auxiliary reception port (when DR-15 is 0.)
0: Internal RS-232C port
1: Communications port A
2: Communications port B
Port
0: RS-232C port
1: Peripheral port
2: Specifies Host Link Unit #0
3: Specifies Host Link Unit #1
331
Serial Communications Instructions
Section 5-27
Note Data is not output when the CTS and DSR signals are monitored.
The specified number of bytes will be read from S through S+(N/2)–1, converted
to ASCII, and transmitted through the specified port. The bytes of source data
shown below will be transmitted in this order: 12345678...
MSB LSB
S
1
3
5
7
2
4
6
8
S+1
S+2
S+3
The following diagram shows the format for host link command (TXD) sent from
the PC. Depending on their settings, the C200 HX/HG/HE and C200HS auto-
matically attach the prefixes and suffixes, such as the node number, header, and
FCS.
@ X
X
X
X
X
X
.........
X
X
X
∗
CR
Node
Header
Data (122 ASCII characters max.)
FCS Terminator
number code (EX)
RS-232C Mode
Control Word
N must be BCD from #0000 to #0256. The value of the control word determines
the port from which data will be output and the order in which data will be written
to memory.
The value of the control word determines the port from which data will be read
and the order in which data will be written to memory.
Digit number: 3 2 1 0
Byte order
0: Most significant bytes first
1: Least significant bytes first
CTS and DSR signal monitoring (see note)
0: Don’t monitor CTS and DSR signals.
1: Monitor the CTS signal. (Output to bit 15 of D.)
2: Monitor the DSR signal. (Output to bit 15 of D.)
3: Monitor the CTS and DSR signals. (Output to bits 15 and 14 of D.)
Auxiliary reception port
0: Internal RS-232C port
1: Communications port A
2: Communications port B
Port
0: RS-232C port
1: Peripheral port
Note Data is not output when the CTS and DSR signals are monitored.
The specified number of bytes will be read from S through S+(NP2)–1 and trans-
mitted through the specified port.
MSB LSB
S
1
3
5
7
2
4
6
8
S+1
S+2
S+3
332
Serial Communications Instructions
Section 5-27
When digit 0 of C is 0, the bytes of source data shown above will be transmitted in
this order: 12345678...
When digit 0 of C is 1, the bytes of source data shown above will be transmitted in
this order: 21436587...
Note When start and end codes are specified the total data length should be 256 bytes
max., including the start and end codes.
Flags
ER:
Another device is not connected to the peripheral port.
There is an error in the communications settings (PC Setup) or the oper-
and settings.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
The source words (S to S+(N÷2)–1) exceed the data area.
26405: RS-232C Port Communications Enabled Flag
26413: Peripheral Port Communications Enabled Flag
26705: Host Link Unit #0 Communications Enabled Flag
26713: Host Link Unit #1 Communications Enabled Flag
5-27-3 CHANGE RS-232C SETUP – STUP(––)
Operand Data Areas
Ladder Symbols
N: RS-232C port specifier
IR 000, IR 001, or IR 002
S: First source word
STUP(––)
@STUP(––)
N
S
N
S
IR, SR, AR, DM, HR, TC, LR, #
---
---
The 3rd operand is ignored.
Limitations
Description
N must be IR 000, IR 001, or IR 002.
S and S+4 must be in the same data area.
(S can be set to #0000 to change the RS-232C settings to their defaults.)
STUP(––) can’t be executed for the internal RS-232C port if pin 2 of the DIP
switch is ON.
STUP(––) can’t be executed within an interrupt subroutine.
When the execution condition is OFF, STUP(––) is not executed. When the
execution condition is ON, STUP(––) changes the PC Setup settings for the port
specified by N.
N determines which part of the RS-232C Setup is changed.
N
Specified Port
IR 000
IR 001
IR 002
Built-in RS-232C port (PC Setup: DM 6645 to DM 6649)
Communications Board port A (PC Setup: DM 6555 to DM 6559)
Communications Board port B (PC Setup: DM 6550 to DM 6554)
If S is a word address, the contents of S through S+4 are copied to the 5 words in
the PC Setup that contain the settings for the port specified by N.
If S is input as the constant #0000, the settings for the specified port are returned
to their default values.
333
Serial Communications Instructions
Section 5-27
S
Function
Word
address
The contents of S through S+4 are copied to the part of the PC Setup
that contains the settings for the port specified by N.
Constant The settings for the port specified by N are returned to their default val-
(#0000) ues.
Application Example
This example shows a program that transfers the contents of DM 0100 through
DM 0104 to the PC Setup area for Communications Board port A (DM 6555
through DM 6569).
00000
Address Instruction
Operands
00000
@STUP(––)
001
00000
00001
LD
@STUP(––)
DM 0100
000
001
0100
000
DM
The settings are transferred as shown below. The Changing RS-232C Setup
Flag (SR 27504) will be turned OFF when the transfer has been completed.
DM 0100
DM 0101
DM 0102
DM 0103
DM 0104
1001
0803
0000
2000
0000
DM 6555
DM 6556
DM 6557
DM 6558
DM 6559
1001
0803
0000
2000
0000
(Refer to 3-6-4 PC Setup
for details.)
The following table shows the function of the transferred setup data.
Word
DM 0100
DM 0101
Content
(see note)
Function
1001
0803
Enables the communications settings in DM 0101 and
sets the communications mode to RS-232C.
Sets the following communications settings:
9,600 bps, 1 start bit, 8-bit data, 1 stop bit, no parity
DM 0102
DM 0103
DM 0104
0000
2000
0000
No transmission delay (0 ms)
Enables the end code CR, LF.
---
Note For details on the contents of setup data, refer to 3-6-4 PC Setup.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
The port specifier (N) isn’t IR 000, IR 001, or IR 002.
Port A has been specified, but pin 2 of the DIP switch is ON.
The PC Setup is write-protected. (Pin 1 of the DIP switch is ON.)
The specified source words exceed the data area.
The instruction was executed from an interrupt program.
334
Serial Communications Instructions
Section 5-27
5-27-4 PROTOCOL MACRO – PMCR(––)
Operand Data Areas
Ladder Symbols
C: Control word
IR, SR, AR, DM, HR, TC, LR, #
S: First output word
PMCR(––)
@PMCR(––)
C
S
D
C
S
D
IR, SR, AR, DM, HR, TC, LR, #
D: First input word
IR, SR, AR, DM, HR, TC, LR
Limitations
Description
C must be BCD from #1000 to #2999.
DM 6144 through DM 6655 cannot be used for D.
When the execution condition is OFF, PMCR(––) is not executed. When the
execution condition is ON, PMCR(––) calls and executes the specified commu-
nications sequence (protocol data) that has been registered in the Communica-
tions Board installed in the PC.
The send/receive message for the communications sequence registered in the
Communications Board must be set to read or write word data when DM isn’t
specified for S and D. Use a constant when it isn’t necessary to set a word for the
first output word.
When the communications sequence doesn’t require an input word, specify a
word address anyway. Data won’t be stored in the specified word and the con-
tents of the word will be retained. When the communications sequence does re-
quire input words, specify words that aren’t used for any other purpose in the
program.
The input and output words (S and D) can also be set in the communications
sequence registered in the Communications Board.
Note Refer to the Communications Board Operation Manual for details on the Com-
munications Boards and the Protocol Software Operation Manual for details on
communications sequences.
Control Word
The first digit of the control word (1 or 2) specifies the Communications Board
port and the last three digits specify the communications sequence (000 to 999),
as shown in the following diagram.
C:
Digits 2 to 4: Communications sequence number
(000 to 999)
Digit 1: Port specifier
1: Communications port A
2: Communications port B
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
D is not BCD or DM 6144 through DM 6655 has been used for D.
Another PMCR(––) instruction was already in progress when the
instruction was executed.
The port specifier was not 1 or 2.
335
Advanced I/O Instructions
Section 5-28
Example
When IR 00000 is ON and SR 28908 (the Communications Board Port A Instruc-
tion Execution Flag) is OFF, communications sequence 100 is called in the Com-
munications Board and data is transferred through Communications Board
port A.
Send data is read from the range of words beginning at DM 0000 (the first output
word) and reception data is stored in the range of words beginning at DM 0010
(the first input word).
Address Instruction
Operands
00000
00000
28908
00200
00201
00202
LD
PMCR
AND NOT
PMCR(––)
28908
#1100
DM0000
DM0010
#
1100
0000
0010
DM
DM
5-28 Advanced I/O Instructions
Advanced I/O instructions enable control, with a single instruction, of previously
complex operations involving external I/O devices (digital switches, 7-segment
displays, etc.).
There are five advanced I/O instructions, as shown in the following table. All of
these are expansion instructions and must be assigned to function codes before
they can be used.
Name
Mnemonic
Function
7-SEGMENT DISPLAY OUTPUT
7SEG(––)
BCD output to 7-segment dis-
play
DIGITAL SWITCH INPUT
DSW(––)
Data input from a digital switch
HEXADECIMAL KEY INPUT
HKY(––)
Hexadecimal input from 16-key
keypad
TEN-KEY INPUT
MATRIX INPUT
TKY(––)
BCD input from 10-key keypad
Data input from an 8 x 8 matrix
MTR(––)
Although TKY(––) is used only to simplify programming, the other advanced I/O
instructions can be used to shorten cycle time, reduce the need for Special I/O
Units, and reduce system cost. With the exception of TKY(––), however, the ad-
vanced I/O instructions can only be used once each in the program and cannot
be used for I/O Units mounted to Slave Racks, where Special I/O Units must be
used.
5-28-1 7-SEGMENT DISPLAY OUTPUT – 7SEG(––)
Ladder Symbols
Operand Data Areas
S: First source word
7SEG(––)
IR, SR, AR, DM, HR, TC, LR
O: Output word
S
O
C
IR, SR, AR, DM, HR, LR
C: Control data
000 to 007
Limitations
S and S+1 must be in the same data area.
DM 0000 to DM6143 can be used for O.
336
Advanced I/O Instructions
Section 5-28
Do not set C to values other than 000 to 007.
Overview
When the execution condition is OFF, 7SEG(––) is not executed. When the
execution condition is ON, 7SEG(––) reads the source data (either 4 or 8-digit),
converts it to 7-segment display data, and outputs that data to the 7-segment
display connected to the output indicated by O.
The value of C indicates the number of digits of source data and the logic for the
Input and Output Units, as shown in the following table.
Source data Display’s data input logic Display’s latch input logic
C
4 digits (S)
Same as Output Unit
Same as Output Unit
000
Different from Output Unit
Same as Output Unit
001
002
003
004
005
006
007
Different from Output Unit
Same as Output Unit
Different from Output Unit
Same as Output Unit
8 digits
(S, S+1)
Different from Output Unit
Same as Output Unit
Different from Output Unit
Different from Output Unit
If there are 8 digits of source data, they are placed in S and S+1, with the most
significant digits placed in S+1. If there are 4 digits of source data, they are
placed in S.
7SEG(––) displays the 4 or 8-digit data in 12 cycles, and then starts over and
continues displaying the data.
The 7-segment display must provide four data lines and one latch signal line for
each display digit.
Note 1. Consider the cycle time and the characteristics of the 7-segment display
when designing the system.
2. Output bits not used here can be used as ordinary output bits.
Precautions
I/O refreshing must be performed for all I/O points used by 7SEG(––) each time it
is executed to ensure effective operation. The I/O REFRESH instruction must
thus be used with 7SEG(––) whenever 7SEG(––) is used in a subroutine to en-
sure that the I/O points are refreshed each execution. Refer to page 350 for an
example of this type of programming.
7SEG(––) will be executed from the first cycle whenever program execution is
started, including restarts made after power interruptions.
Do not use 7SEG(––) more than twice in the program.
7SEG(––) cannot be used for I/O Units mounted to Slave Racks.
Hardware
This instruction outputs word data to a 7-segment display. It utilizes either 8 out-
put bits for 4 digits or 12 output bits for 8 digits. The 7-segment display is con-
nected to an Output Unit as shown in the diagram below. For 4-digit display, the
data outputs (D0 to D3) are connected to output points 0 through 3 (allocated
word O), and latch outputs (CS0 to CS3) are connected to output points 4
through 7. Output point 12 (for 8-digit display) or output point 8 (for 4-digit dis-
337
Advanced I/O Instructions
Section 5-28
play) will be turned ON when one round of data is displayed, but there is no need
to connect them unless required by the application.
D
0
D
1
D
2
D
3
V
(+)
V
(0)
V
(+)
V
(0)
D
D
D
D
DD
DD
0
1
2
3
SS
SS
LE3
LE2
LE1
LE0
LE3
LE2
LE1
LE0
OD212
0
1
2
4
3
5
6
8
7
9
10
11
12
14
DC
13
15
COM
The outputs must be connected from an Output Unit with 8 or more output points
for four digits or 16 or more output points for eight digits. Basic Output, Special
I/O, or High-density Output Units can be used.
Note 1. Output Unit outputs normally employ negative logic. (Only the PNP output
type employs positive logic.)
2. The 7-segment display may require either positive or negative logic, de-
pending on the model.
3. The 7-segment display must have 4 data signal lines and 1 latch signal line
for each digit.
Using the Instruction
If the first word holding the data to be displayed is specified at S, and the output
word is specified at O, and the SV taken from the table below is specified at C,
then operation will proceed as shown below when the program is executed. If
only four digits are displayed, then only word S will be used.
Data Storage Format
Leftmost 4 digits
S+1
Rightmost 4 digits
S
338
Advanced I/O Instructions
Section 5-28
Timing
The timing of data output is shown in the following table. “O” is the first word hold-
ing display data and “C” is the output word.
Bit(s) in O
Function
Output status (Data and latch logic depends on C)
(4 digits,
1 block)
(4 digits,
2 blocks)
00 to 03
04 to 07
0
1
2
3
Note 0 to 3: Data output for word S
Data output
00 to 03
10
10
10
10
4 to 7: Data output for word S+1
Latch output 0
Latch output 1
Latch output 2
Latch output 3
04
05
06
07
08
09
10
11
One Round Flag
08
12
0
1
2
3
4
5
6
7
8
9
10 11 12
12 cycles required to complete one round
Application Example
This example shows a program for displaying 8-digit BCD numbers at a 7-seg-
ment LED display. Assume that the 7-segment display is connected to output
word IR 100. Also assume that the Output Unit is using negative logic, and that
the 7-segment display logic is also negative for data signals and latch signals.
25313 (Always ON)
7SEG(––)
DM0120
100
004
The 8-digit BCD data in DM 0120 (rightmost 4 digits) and DM 0121 (leftmost 4
digits) are always displayed by means of 7SEG(––). When the contents of
DM 0120 and DM 0121 change, the display will also change.
Flags
ER:
S and S+1 are not in the same data area. (When set to display 8-digit
data.)
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
There is an error in operand settings.
25409: SR 25409 will be ON while 7SEG(––) is being executed.
5-28-2 DIGITAL SWITCH INPUT – DSW(––)
Ladder Symbols
Operand Data Areas
IW: Input word
DSW(––)
IR, SR, AR, DM, HR, LR
OW: Output word
IW
OW
R
IR, SR, AR, DM, HR, LR
R: First result word
IR, SR, AR, DM, HR, LR
339
Advanced I/O Instructions
Section 5-28
Overview
DSW(––) is used to read the value set on a digital switch connected to I/O Units.
When the execution condition is OFF, DSW(––) is not executed. When the
execution condition is ON, DSW(––) reads the 8-digit value set on the digital
switch from IW and places the result in R.
The 8-digit value it is placed in R and R+1, with the most significant digits placed
in R+1.
DSW(––) reads the 8-digit value in 20 executions, and then starts over and con-
tinues reading the data.
The digital switch must provide four data lines and one latch signal line and read
signal line for each digit being input.
Precautions
I/O refreshing must be performed for all I/O points used by DSW(––) each time it
is executed to ensure effective operation. The I/O REFRESH instruction must
thus be used with DSW(––) whenever DSW(––) is used in a subroutine to en-
sure that the I/O points are refreshed each execution. Refer to page 350 for an
example of this type of programming.
DSW(––) will be executed from the first cycle whenever program execution is
started, including restarts made after power interruptions.
Do not use DSW(––) more than twice in the program.
DSW(––) cannot be used for I/O Units mounted to Slave Racks.
Note Input and output bits not used here can be used as ordinary input and output bits.
Hardware
With this instruction, 8-digit BCD set values are read from a digital switch.
DSW(––) utilizes 5 output bits and 8 input bits. Connect the digital switch and the
Input and Output Units as shown in the diagram below. Output point 5 will be
turned ON when one round of data is read, but there is no need to connect output
point 5 unless required for the application.
ID212
Input Unit
0
D
D
D
D
D
D
D
D
CS
CS
CS
CS
D
D
D
D
D
D
D
D
CS
CS
CS
CS
1
3
5
7
9
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
Interface
A7E data line rightmost digits
A7E data line
2
4
A7E
6
8
Leftmost digits
leftmost digits
Rightmost digits
0
1
2
3
0
1
2
3
10
11
12
To A7E chip selection
To A7E RD terminal
13
RD
RD
14
15
COM
COM
OD212
Note An interface to convert signals from 5 V to 24 V is
0
required to connect an A7E digital switch.
1
2
4
3
5
6
7
8
9
10
11
12
13
14
15
Output Unit
COM
COM
340
Advanced I/O Instructions
Section 5-28
The following example illustrates connections for an A7B Thumbwheel Switch.
ID212
Input Unit
0
2
1
3
4
5
6
8
7
9
A7B
Thumbwheel
Switch
10
11
12
8 4 2 1
13
14
OD212
15
COM
Switch no. 8
7
6
5
4
3
2
1
C
COM
0
2
1
3
4
5
6
8
7
9
10
11
12
14
DC
13
15
Output Unit
COM
Note The data read signal is not required in the example.
The inputs must be connected to a DC Input Unit with 8 or more input points and
the outputs must be connected from a Transistor Output Unit with 8 or more out-
put points.
341
Advanced I/O Instructions
Section 5-28
Using the Instruction
If the input word for connecting the digital switch is specified at for word A, and
the output word is specified for word B, then operation will proceed as shown
below when the program is executed.
IW
Four digits: 00 to 03
0
1
2
3
Input data
Leftmost Rightmost
10
10
10
10
Eight digits: 00 to 03, 04 to 07
4 digits
4 digits
Wd 0
00
D+1
D
When only 4 digits are read,
only word D is used.
01
02
03
04
05
CS signal
RD (read) signal
1 Round Flag
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
16 cycles to complete one round of execution
Application Example
This example shows a program for reading 8 digits in BCD from the digital
switch. Assume that the digital switch is connected to IR 000 (input) and IR 100
(output).
00015
05000
10005
05000
05000
DSW
000
100
HR51
10005
@MOV(21)
HR51
DM0000
When IR 00015 turns ON, the IR 05000 will hold itself ON until the One Round
Flag (IR 10005) turns ON upon completion of one round of reading by DSW(––).
The data set from the digital switch by DSW(––) is stored in HR 51.
When the One Round Flag (10005) turns ON after reading has been completed,
the number stored in HR 51 is transferred to DM 0000.
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
R and R+1 are not in the same data area.
25410: ON while DSW(––) is being executed.
342
Advanced I/O Instructions
Section 5-28
5-28-3 HEXADECIMAL KEY INPUT – HKY(––)
Ladder Symbols
Operand Data Areas
IW: Input word
IR, SR, AR, DM, HR, LR
OW: Control signal output word
IR, SR, AR, DM, HR, LR
D: First register word
HKY(––)
IW
OW
D
IR, SR, AR, DM, HR, LR
Limitations
Overview
D and D+2 must be in the same data area.
When the execution condition is OFF, HKY(––) is not executed. When the
execution condition is ON, HKY(––) inputs data from a hexadecimal keypad
connected to the input indicated by IW. The data is input in two ways:
1, 2, 3... 1. An 8-digit shift register is created in D and D+1. When a key is pressed on
the hexadecimal keypad, the corresponding hexadecimal digit is shifted into
the least significant digit of D. The other digits of D, D+1 are shifted left and
the most significant digit of D+1 is lost.
2. The bits of D+2 and bit 4 of OW indicate key input. When one of the keys on
the keypad (0 to F) is being pressed, the corresponding bit in D+2 (00 to 15)
and bit 4 of OW are turned ON.
Note 1. When one of the keypad keys is being pressed, input from the other keys is
disabled.
2. Input and output bits not used here can be used as ordinary input and output
bits.
With this instruction, one key input is read in 4 to 13 cycles. More than one cycle
is required because the ON keys can only be determined as the outputs are
turned ON to test them.
The hexadecimal key input device must be connectable in a 4 x 4 matrix.
Precautions
I/O refreshing must be performed for all I/O points used by HKY(––) each time it
is executed to ensure effective operation. The I/O REFRESH instruction must
thus be used with HKY(––) whenever HKY(––) is used in a subroutine to ensure
that the I/O points are refreshed each execution. Refer to page 350 for an exam-
ple of this type of programming.
HKY(––) will be executed from the first cycle whenever program execution is
started, including restarts made after power interruptions.
Do not use HKY(––) more than twice in the program.
HKY(––) cannot be used for I/O Units mounted to Slave Racks.
343
Advanced I/O Instructions
Section 5-28
Hardware
This instruction inputs 8 digits in hexadecimal from a hexadecimal keyboard. It
utilizes 5 output bits and 4 input bits. Prepare the hexadecimal keyboard, and
connect the 0 to F numeric key switches, as shown below, to input points 0
through 3 and output points 0 through 3. Output point 4 will be turned ON while
any key is being pressed, but there is no need to connect it unless required by
the application.
OD212
C
8
4
0
D
9
5
1
E
A
6
2
F
B
0
1
3
2
7
3
4
5
6
8
7
9
ID212
0
10
1
3
11
2
4
12
13
14
5
15
6
8
COM
7
9
COM
10
11
Output Unit
12
13
14
15
COM
COM
Input Unit
The inputs connected to the input terminals must be on a DC Input Unit with 8 or
more input points and the outputs connected to the output terminals must be
from a Transistor Output Unit with 8 points or more.
344
Advanced I/O Instructions
Section 5-28
Using the Instruction
If the input word for connecting the hexadecimal keyboard is specified at word A,
and the output word is specified at word B, then operation will proceed as shown
below when the program is executed.
IW
00
01
02
03
16-key selection
control signals
16-key
0
to
9
to
F
Status of 16 keys
D+2
00
to
09
to
15
OW
04
Turn ON flags corre-
sponding to input
keys (The flags re-
main ON until the
next input.)
ON for a 12-cycle
period if a key is
pressed.
0 1 2 3 4 5 6 7 8 9101112
Once per 12 cycles
0000 0000
0000
D+1
000F
D
0000
D+1
00F9
D
D
D+1
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
D and D+2 are not in the same data area.
SR 25408:
ON while HKY(––) is being executed.
Example
This example shows a program for inputting numbers from a hexadecimal key-
board. Assume that the hexadecimal keyboard is connected to IR 000 (input)
and IR 100 (output).
25313 (Always ON)
HKY(––)
000
100
DM1000
00015
@XFER(70)
#0002
DM1000
DM0000
The hexadecimal key information that is input to IR 000 by HKY(––) is converted
to hexadecimal and stored in words DM1000 and DM1001.
IR 00015 is used as an “ENTER key,” and when IR 00015 turns ON, the numbers
stored in DM 1000 and DM 1001 are transferred to DM 0000 and DM 0001.
345
Advanced I/O Instructions
Section 5-28
5-28-4 TEN KEY INPUT – TKY(––)
Ladder Symbols
Operand Data Areas
IW: Input word
TKY(––)
IR, SR, AR, DM, HR, LR
IW
D : First register word
1
D
1
2
IR, SR, AR, DM, HR, LR
D
D : Key input word
2
IR, SR, AR, DM, HR, LR
Limitations
Overview
D and D +1 must be in the same data area.
1
1
When the execution condition is OFF, TKY(––) is not executed. When the execu-
tion condition is ON, TKY(––) inputs data from a ten-key keypad connected to
the input indicated by IW. The data is input in two ways:
TKY(––) can be used in several locations in the program by changing the input
word, IW.
1, 2, 3... 1. An 8-digit shift register is created in D and D +1. When a key is pressed on
1
1
the ten-key keypad, the corresponding BCD digit is shifted into the least sig-
nificant digit of D . The other digits of D , D +1 are shifted left and the most
1
1
1
significant digit of D +1 is lost.
1
2. The first ten bits of D indicate key input. When one of the keys on the key-
2
pad (0 to 9) is being pressed, the corresponding bit of D (00 to 09) is turned
2
ON.
Note 1. While one key is being pressed, input from other keys will not be accepted.
2. If more than eight digits are input, digits will be deleted beginning with the
leftmost digit.
3. Input bits not used here can be used as ordinary input bits.
Hardware
This instruction inputs 8 digits in BCD from a 10-key keypad and uses 10 input
points. Prepare a 10-key keypad, and connect it so that the switches for numeric
keys 0 through 9 are input to points 0 through 9 as shown in the following dia-
gram. The inputs on a DC Input Unit with 16 or more input points can be used.
ID212
0
0
2
4
6
8
1
3
5
7
9
10
9
11
12
13
10-key
14
15
COM
COM
0 V
DC Input Unit
346
Advanced I/O Instructions
Section 5-28
Using the Instruction
If the input word for connecting the 10-key keypad is specified for IW, then opera-
tion will proceed as shown below when the program is executed.
IW
D +1
D
1
1
00
01
02
to
Before
execution
0
0
0
0
0
0
0
0
0
0
0
0
1
Input from 10-key
(1)
0
0
0
09
“1” key input
D
2
(2)
(3)
0
0
0
0
0
0
0
0
0
0
0
1
0
00
01
“0” key input
Turn ON flags corre-
sponding to 10-key
inputs (The flags re-
main ON until the
next input.)
1
0
2
02
to
“2” key input
09
(4)
0
0
0
0
1
0
2
9
ON if a key is pressed.
10
“9” key input
(1)
(2) (3)
(4)
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
D and D +1 are not in the same data area.
1
1
Example
In this example, a program for inputting numbers from the 10-key is shown. As-
sume that the 10-key is connected to IR 000.
25313 (Always ON)
TKY(––)
000
DM1000
DM1002
00015
@XFER(70)
#0002
DM1000
DM 0000
The 10-key information input to IR 000 using TKY(––) is converted to BCD and
stored in DM 1000 and DM 1001. Key information is stored in DM 1002.
IR 00015 is used as an “ENTER key,” and when IR 00015 turns ON, the data
stored in DM 1000 and DM 1001 will be transferred to DM 0000 and DM 0001.
347
Advanced I/O Instructions
Section 5-28
5-28-5 MATRIX INPUT – MTR(––)
Ladder Symbols
Operand Data Areas
IW: Input word
MTR(––)
IW
IR, SR, AR, DM, HR, LR
OW: Output word
OW
IR, SR, AR, DM, HR, LR
D: First destination word
IR, SR, AR, DM, HR, LR
D
Limitations
Overview
D and D+3 must be in the same data area.
When the execution condition is OFF, MTR(––) is not executed. When the
execution condition is ON, MTR(––) inputs data from an 8 × 8 matrix and records
that data in D to D+3. Data for all 64 points in the matrix will be recorded even
when fewer than 64 keys are connected.
0
8
1
9
2
3
4
5
6
7
00
01
02
03
04
05
06
07
08
10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
OW bits 00 to 07
(for Output Unit
outputs 00 to 07)
Bit 08 is turned ON to indi-
cate that the entire matrix
has been read.
Key input data is written
to D through D+3 (see
table below).
00 01 02 03 04 05 06 07
IW bits 00 to 07
(for Input Unit inputs 00 to 07)
A selection signal is output to OW bits 00 to 07 consecutively for 3 cycles. Only
one output bit will be turned on at a time. Bit 08 of OW is turned ON for 3 cycles
after 07 to indicate when each round of reading the matrix has been completed.
When one of the 64 keys is pressed, an input will be received at one of the input
bits. The key that was pressed is identified by comparing the output bit to which
the signal was output and input bit at which it was received.
When an key input is detected, the corresponding bit in D through D+3 is turned
ON. The following table shows the correspondence between keys and bits in D
through D+3.
Word
Bits
00 to 15
00 to15
00 to 15
00 to 15
Corresponding Keys
0 to 15
D
D+1
D+2
D+3
16 to 31
32 to 47
48 to 63
348
Advanced I/O Instructions
Section 5-28
Hardware
This instruction inputs up to 64 signals from an 8 x 8 matrix using 8 input points
and 8 output points. Any 8 x 8 matrix can be used. The inputs must be connected
through a DC Input Unit with 8 or more points and the outputs must be connected
through a Transistor Output Unit with 8 or more points. The basic wiring and tim-
ing diagrams for MTR(––) are shown below.
Wiring
8th row
7th row
A8 A7 A6 A5 A4 A3 A2 A1 A0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
1st row
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ID 211 I/O Unit
Timing Diagram
00
01
02
03
04
05
06
07
00
32
64
00
32
64
06
Matrix select signal
Matrix status
Bits indicating
input status
One-round Flag (bit
08 of output word)
Each round completed in 24 executions
Precautions
The 64 keys can be divided into 8 rows (including a row for OW bit 08) which are
scanned consecutively. Since each row is scanned for 3 cycles, a delay of up to
25 cycles can occur before a given row of keys is scanned for inputs.
I/O refreshing must be performed for all I/O points used by MTR(––) each time it
is executed to ensure effective operation. The I/O REFRESH instruction must
thus be used with MTR(––) whenever MTR(––) is used in a subroutine to ensure
that the I/O points are refreshed each execution.
MTR(––) will be executed from the first cycle whenever program execution is
started, including restarts made after power interruptions.
SR 25403, which is turned on while MTR(––) is being executed, is reset in an
interlocked program section and MTR(––) is not executed in an interlocked pro-
gram section.
Do not use MTR(––) more than twice in the program.
MTR(––) cannot be used for I/O Units mounted to Slave Racks.
349
Special I/O Unit Instructions
Section 5-29
Example
The following examples shows programming MTR(––) in a scheduled subrou-
tine, where IORF(97) is programmed to ensure that the I/O words used by
MTR(––) are refreshed each time MTR(––) is executed.
INT(89)
001
004
# 0002
INT(89)
000
004
# 0002
SBN(92)
99
MTR(––)
S
D1
D2
IORF(97)
D1
D2
RET(93)
END(01)
Flags
ER:
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
25403: SR 25403 is ON while MTR(––) is being executed.
5-29 Special I/O Unit Instructions
The Special I/O Unit instructions are used to transfer data to and from the
memory of the specified Special I/O Unit.
5-29-1 SPECIAL I/O UNIT READ – IORD(––)
Operand Data Areas
Ladder Symbols
C: Control code
IORD(––)
@IORD(––)
IR, SR, AR, DM, HR, TC, LR, #
S: Source information
C
S
D
C
S
D
IR, SR, AR, DM, HR, TC, LR, #
D: First destination word
IR, SR, AR, DM, HR, TC, LR
Limitations
Only Special I/O Units mounted to the PC’s CPU Rack or Expansion I/O Racks
can be specified.
The last three digits of S must be BCD (from 001 to 128).
350
Special I/O Unit Instructions
Section 5-29
Description
When the execution condition is OFF, IORD(––) is not executed. When the
execution condition is ON, IORD(––) transfers data from the specified Special
I/O Unit’s memory to words beginning at D. The source information provides the
node number of the Special I/O Unit and the number of words to be read, as
shown in the following diagram.
S:
Digits 2 to 4: Number of words to read (001 to 128)
Digit 1: Node number of the Special I/O Unit (0 to F)
The control code (C) depends on the Special I/O Unit being specified. Refer to
the Unit’s Operating Manual for details.
Example
When IR 00000 goes from OFF to ON, the following instruction transfers 100
words from the memory area of Special I/O Unit number 3 to DM 0100 through
DM 0199.
00000
Address Instruction
Operands
00000
IORD(––)
C
00200
00201
LD
@IORD(––)
#3100
DM 0100
C
#3100
0100
DM
Flags
ER:
The last three digits of S (number of words specifier) isn’t BCD or isn’t
within the range of 001 through 128.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
The source Unit’s unit number isn’t 0 to F or it is mounted on a Slave
Rack.
The received data overflows a data area boundary.
EQ:
ON when the data was read successfully, otherwise OFF.
5-29-2 SPECIAL I/O UNIT WRITE – IOWR(––)
Operand Data Areas
Ladder Symbols
C: Control code
IOWR(––)
@IOWR(––)
IR, SR, AR, DM, HR, TC, LR, #
S: First source word
C
S
D
C
S
D
IR, SR, AR, DM, HR, TC, LR
D: Destination information
IR, SR, AR, DM, HR, TC, LR, #
Limitations
Only Special I/O Units mounted to the PC’s CPU Rack or Expansion I/O Racks
can be specified.
The last three digits of D must be BCD (from 001 to 128).
351
Special I/O Unit Instructions
Section 5-29
Description
When the execution condition is OFF, IOWR(––) is not executed. When the
execution condition is ON, IOWR(––) transfers data from the words beginning at
D to the specified Special I/O Unit’s memory. The destination information pro-
vides the node number of the Special I/O Unit and the number of words to be
written, as shown in the following diagram.
D:
Digits 2 to 4: Number of words to write (001 to 128)
Digit 1: Node number of the Special I/O Unit (0 to F)
The control code (C) depends on the Special I/O Unit being specified. Refer to
the Unit’s Operating Manual for details.
Example
When IR 00000 goes from OFF to ON, the following instruction writes the con-
tents of the 10 words from DM 0100 through DM 0109 to the memory area of
Special I/O Unit number 2.
00000
Address Instruction
Operands
00000
IOWR(––)
C
00200
00201
LD
@IOWR(––)
DM 0100
#2010
C
0100
DM
#2010
Flags
ER:
EQ:
The last three digits of D (number of words specifier) isn’t BCD or isn’t
within the range of 001 through 128.
Indirectly addressed DM word is non-existent. (Content of ꢀDM word is
not BCD, or the DM area boundary has been exceeded.)
The destination Unit’s unit number isn’t 0 to F or it is mounted on a Slave
Rack.
The instruction wasn’t completed normally.
ON when the data was read successfully, otherwise OFF.
352
Special I/O Unit Instructions
Section 5-29
5-29-3 PCMCIA CARD MACRO – CMCR(––)
Operand Data Areas
Ladder Symbols
C: First control word
IR, SR, AR, DM, HR, TC, LR, #
S: First command word
CMCR(––)
@CMCR(––)
C
S
D
C
S
D
IR, SR, AR, DM, HR, TC, LR, #
D: Response word
IR, SR, AR, DM, HR, TC, LR
Limitations
Description
DM 6144 through DM 6655 cannot be used for D.
When the execution condition is OFF, CMCR(––) is not executed. When the
execution condition is ON, CMCR(––) executes a macro process that writes,
reads, compares, or searches the memory of the Card in the PCMCIA Card In-
terface Unit.
When CMCR(––) writes data in a comma-delimited file, that file can be written
entirely in one line. Comma-delimited files that were created in a personal com-
puter are assumed to be written in one of the following formats. (It doesn’t matter
if the comma is in a separate byte.)
4 bytes, comma, 4 bytes, comma, 4 bytes, comma ......
8 bytes, comma, 8 bytes, comma, 8 bytes, comma ......
A file can be appended only if there is free space in the Card and data can be
overwritten only when an acceptable offset has been specified.
The fields in the comma-delimited file must not be enclosed by definers such as
quotation marks.
Control Words
Write the control data in the first control word using the format shown in the fol-
lowing diagram.
Operating level (OFF=level 0, ON=level 1)
Set to 1 to transmit the control codes in C+1 through C+7 to the PC Card Unit.
The function of the port number depends on the process specified.
Set the process number (1 through 4, see below).
Word
0/1
Port
Process number
Control code
Control code
Control code
Control code
Control code
Control code
Control code
Input the drive and filename (in ASCII) of the file to be written,
read, compared, or searched. Be sure to include all three char-
acters of the filename extension. Directories can be specified if
they have been created.
Slot 1 is drive “G:” and slot 2 is drive “H:”.
353
Special I/O Unit Instructions
Section 5-29
Process Number
The process number (1 through 4) determines what function CMCR(––) will per-
form.
Process
number
Process
name
Function
1
Write file
Writes data from the PC’s memory to the specified file
in the Card in the PC Card Unit.
2
3
4
Read file
Reads data from the specified file in the Card in the PC
Card Unit to the PC’s memory.
Compare file
with memory
Compares the specified file in the Card in the PC Card
Unit to data in the PC’s memory.
Search file
Searches the specified file in the Card in the PC Card
Unit.
Port Settings
Process
The port settings (bits 8, 9, and 10) specify details about CMCR(––) operations
and the format of the PC Card files.
Port settings
number
Bit 8
Bit 9
Bit 10
1
2
3
4
OFF:Overwrite existing file.
ON: Create new file.
OFF:Create a comma-delimited
file.
ON: Create a binary file.
OFF:One-word comma delimiter.
ON: Two-word comma delimiter.
OFF:Read the specified file.
ON: Read the number of ele-
ments in the specified file.
OFF:Read as a comma-delimited OFF:One-word comma delimiter.
file.
ON: Two-word comma delimiter.
ON: Read as a binary file.
---
---
OFF:Compare as a comma-delim- OFF:One-word comma delimiter.
ited file.
ON: Compare as a binary file.
ON: Two-word comma delimiter.
OFF:Search as a comma-delim-
ited file.
OFF:One-word comma delimiter.
ON: Two-word comma delimiter.
ON: Search as a binary file.
Command Words
The command words are made up of the data length, offset, and command data.
For the data length, specify the length of the command data +1. The maximum
length of the command data is 1,000 words.
Data length
Offset
Command data
Command data
Command data
Command data
354
Special I/O Unit Instructions
Section 5-29
The data length, offset, and command data settings depend on the process
number that is specified, as shown in the following table.
Process
number
Data length
Offset
Command data
1
Number of words of data Number of elements of write data
Data to be written to the file
(BCD: 1 to 1001)
(0 to FFFF)
999 words max. for one-word comma
Specify number of words for one-word delimiter and binary.
comma delimiter and binary.
Specify number of elements for
two-word comma delimiter.
998 words max. (449 elements) for
two-word comma delimiter.
2
3
4
Always set to 0003.
Number of elements of read data
(0 to FFFF)
Specify the number of words to read
(in hexadecimal, 1 to 3E7).
Specify number of words for one-word 999 ($3E7) words max. for one-word
comma delimiter and binary.
Specify number of elements for
two-word comma delimiter.
comma delimiter and binary.
449 ($1F3) elements max. for
two-word comma delimiter.
Number of words of data Number of elements of compare data
(BCD: 1 to 1001)
Data to be compared.
(0 to FFFF)
999 words max. for one-word comma
Specify number of words for one-word delimiter and binary.
comma delimiter and binary.
Specify number of elements for
two-word comma delimiter.
998 words max. (449 elements) for
two-word comma delimiter.
Specify 3 for one-word
comma delimiter and
binary.
Specify 4 for two-word
comma delimiter.
Number of elements of search data
(0 to FFFF)
Search data
Specify one word of search data for
Specify number of words for one-word one-word comma delimiter and binary.
comma delimiter and binary.
Specify number of elements for
two-word comma delimiter.
Specify two words of search data for
two-word comma delimiter.
Note 1. When an offset of 0 is specified for process number 1 and a file with the
same name already exists, the existing file will be deleted and a new file will
be created. If the data length has been set to 1 (no write data), the instruction
just deletes the existing file. If the offset has been set to 1, data will be ap-
pended to the end of the existing file.
2. A comma-delimited file is a file in which a 1-byte character such as a comma
is inserted after every 4 bytes or 8 bytes of data. An error (termination
code 2) will occur if there are any 2-byte delimiters such as CR+LF. Replace
these 2-byte delimiters with 1-byte delimiters in advance.
Response Data
The response data depends on the process number that was specified, as
shown in the following table.
Process
number
Response data
1
None
2
Contains the data read from the specified file. When the number of
elements is read, it is contained in 2-word hexadecimal.
3
4
None (The result of the comparison is returned in the termination code.)
When the search data is found in the file, its location is returned as the
number of words or data elements (0 to FFFF) from the offset location.
Beginning of the file:
0000
Second word (element):0001
Third word (element): 0002
355
Special I/O Unit Instructions
Section 5-29
SR Bits and the Termination The instruction’s termination code is output to SR 237 after CMCR(––) is
Code
executed. Also, SR 252 contains flags that indicate the instruction’s completion
status (normal/error) and the execution status for operating levels 0 and 1. The
following table shows the function of these bits.
Word
Bit(s)
Function
00 to 07 Termination code output area for operating level 0 after
SR 237
execution of CMCR(––).
08 to 15 Termination code output area for operating level 1 after
execution of CMCR(––).
00
01
03
04
Error Flag for operating level 0 after execution of CMCR(––)
ON when CMCR(––) can be executed for operating level 0
Error Flag for operating level 1 after execution of CMCR(––)
ON when CMCR(––) can be executed for operating level 1
SR 252
The following table shows the meaning of the termination codes.
Code
00
Meaning
Normal completion
01
02
03
04
Parameter error such as offset, file size, or number of words to read
Disk full, file I/O error, or file type error
Non-existent file specified
Comparison or search failed
05 to FE Undefined
FF
Process number error
Flags
ER:
The content of a word containing an indirect DM/EM address is not BCD
or the DM/EM area boundary has been exceeded.
DM 6144 through DM 6655 has been used for D.
The execution enabled flag for the specified operating level (SR 25201
or SR 25204) was OFF.
The operating level specified was not 0 or 1.
Example
By turning IR 00000 OFF → ON → OFF, 100 words of DM data starting from
DM 0100 are written to the file G:\DMSAVE.DAT (Memory Card, slot 1). The DM
area settings are shown after the ladder diagram.
00000 25201
S
KEEP
00100
SR 25201: Execution enabled flag for
operating level 0.
R
00101
00100
Operating level 0
@MOV(21)
Write file (Create new file.)
(One-word comma delimiter file)
#0901
DM 0000
Executes instruction with process
@CMCR(––)
number 1. (Write file)
DM 0000
DM0098
000
00100 25200
00300
IR 00300: Output when error occurs in
execution of CMCR(––).
00100
25201
DIFU(013)00101
IR 00101: Ends execution of CMCR(––).
356
Special I/O Unit Instructions
Section 5-29
DM 0000 to DM 0007 contain the control data and DM 0098 to DM 0199 contain
the command data, as shown below.
Word
DM 0000
DM 0001
DM 0002
DM 0003
DM 0004
DM 0005
DM 0006
DM 0007
Content
---
Function
Control data
ASCII: “G :”
ASCII: “\ D”
ASCII: “M S”
ASCII: “A V”
ASCII: “E .”
ASCII: “D A”
ASCII: “T”
47 3A
5C 44
4D 53
41 56
45 2E
44 41
54
Word
DM 0098
DM 0099
DM 0100
Content
0102
Function
Write data length: 102 (hexadecimal)
Offset: 0
0000
---
Data to be written
:
:
:
:
:
:
DM 0199
---
Data to be written
357
SECTION 6
Program Execution Timing
The timing of various operations must be considered both when writing and debugging a program. The time required to
execute the program and perform other CPU Unit operations is important, as is the timing of each signal coming into and
leaving the PC in order to achieve the desired control action at the right time. This section explains the cycle and shows how to
calculate the cycle time and I/O response times.
6-1 Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-2 Calculating Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-2-1 PC with I/O Units Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-2-2 PC with Host Link and Remote I/O Master Units . . . . . . . . . . . . . . . . . . . . . . . .
6-3 Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-4 I/O Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-4-1 Basic Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-4-2 Remote I/O Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-4-3 Host Link Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-4-4 PC Link Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-4-5 One-to-one Link I/O Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-4-6 Interrupt Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
360
364
365
365
367
376
376
377
380
380
383
385
359
Cycle Time
Section 6-1
6-1 Cycle Time
To aid in PC operation, the average, maximum, and minimum cycle times can be
displayed on the Programming Console or any other Programming Device and
the maximum cycle time and current cycle time values are held in AR 26 and
AR 27. Understanding the operations that occur during the cycle and the ele-
ments that affect cycle time is, however, essential to effective programming and
PC operations.
The major factors in determining program timing are the cycle time and the I/O
response time. One run through all required CPU Unit operations is called a
cycle; the time required for each cycle is called the cycle time.
The overall flow of the CPU Unit operation is as shown in the following flowchart.
360
Cycle Time
Section 6-1
Flowchart of CPU Unit Operation
Power application
Clears IR area and
resets all timers
Initialization
on power-up
Checks I/O Unit connections
Resets watchdog timer
Checks hardware and
Program Memory
Overseeing
processes
NO
Check OK?
YES
Resets watchdog timer and
program address counter
Sets error flags and turns
ON or flashes indicator
Program
execution
Executes user program
ALARM/ERROR
ALARM
(Flashing)
ERROR
(Solid ON)
End of program?
YES
NO
NO
Note A minimum cycle
time can be set
either in DM 6619
of the PC Setup
or by executing
SCAN(18).
Minimum
cycle time?
YES
PC
cycle
time
Cycle time
calculation
Resets watchdog timer and waits
until the set cycle time has elapsed
Calculates cycle time
Resets watchdog timer
I/O
refreshing
Refreshes input bits
and output signals
RS-232C port
servicing
Services RS-232C port
Host Link Unit
servicing
Services Host Link
Peripheral
device
Services Peripheral Devices
servicing
Services Com-
munications
Board
Services Communications
Board
SYSMAC LINK
and SYSMAC
NET Link Unit
servicing
Services SYSMAC LINK and
SYSMAC NET Link Units
361
Cycle Time
Section 6-1
The first three operations immediately after power application are performed
only once each time the PC is turned on. The rest of the operations are per-
formed in cyclic fashion.
The cycle time is the time that is required for the CPU Unit to complete one of
these cycles. This cycle includes basically 9 types of operation: Overseeing,
Program execution, Cycle time calculation, I/O refreshing, Host Link Unit servic-
ing, RS-232C port servicing, Peripheral Device servicing, Communications
Board servicing, and SYSMAC NET/SYSMAC LINK servicing.
The cycle time is the total time required for the PC to perform all 9 of these opera-
tions. The time required for operation 3, cycle time calculation, is negligible and
can be ignored in actual calculations.
Operation
Time required
Function
1. Overseeing
0.7 ms (2.1 ms in the C200HE-CPU11-E)
Watchdog timer reset. I/O Bus, Program
Memory checked. Clock refreshed.
2. Program
execution
Total execution time for all instructions varies Program executed.
with program size, the instructions used, and
execution conditions. Refer to 6-3 Instruction
Execution Times for details.
3. Cycle time
calculation
Negligible, but a wait can be generated to
bring the cycle time up to the minimum set-
ting if one has been made.
Cycle time calculated. When the CYCLE
TIME instruction (SCAN(18)) is executed,
waits until the set time has elapsed and
then resets the watchdog timer.
4. I/O refreshing
Total of following times:
Input bits set according to status of input
signals. Output signals sent according to
status of output bits in memory.
20 µs per input byte (8 points). 20 µs per
output byte (8 points). (12-point Output Units
calculated as 16 points.)
Inputs and Outputs in Remote I/O Sys-
tems refreshed.
PC Link Unit I/O refresh time.
Special I/O Unit refresh time.
Special I/O Units serviced.
Group-2 High-density I/O Units serviced.
1.1 ms per Remote I/O Master Unit +
0.17 ms per I/O word used on Slave Racks.
Group-2 (High-density) I/O Unit refresh time.
Refer to the tables below for details on PC
Link, Special I/O Unit, and Group-2 High-
density I/O Unit refresh times.
5. Host Link Unit servicing 6 ms per Unit max.
Commands from computers connected
through Rack-mounting Host Link Units
processed.
6. RS-232C port servicing
0 ms when no device is connected.
Communications with devices connected
to RS-232C port processed.
0.26 ms minimum or T × 0.05, where T is the
cycle time calculated in operation 3
7. Peripheral device
servicing
0 ms when no device is connected.
Commands from Programming Devices
(computers, Programming Consoles, etc.)
processed.
0.26 ms minimum or T × 0.05, where T is the
cycle time calculated in operation 3
8. Communications Board
servicing
0.5 ms + processing time per port.
Commands from the Communications
Board (RS-232C, RS-422, or RS-485) are
processed.
The processing time per port is as follows:
0.26 ms minimum or T × 0.05, where T is the
cycle time calculated in operation 3
9. SYSMAC NET Link/
0 ms when no Communications Unit is
Commands from computers and other de-
vices connected to SYSMAC NET Link/
SYSMAC LINK/PC Card Units processed.
SYSMAC LINK servicing mounted.
PC card servicing
For C200HS-SLK
j
j or C200HS-SNT
0.8 ms + 15 ms max. per Unit.
For C200HW-SLK j :
3.5 ms max. per Unit.
j
j
:
j
For C200HW-PCU01/PCS01:
6 ms max.
362
Cycle Time
Section 6-1
PC Link Unit I/O Refresh
I/O pts to refresh
512
Time required
(ms)
7.4
256
128
64
4.1
2.7
1.7
Special I/O Unit Refresh
Unit
Time required per Unit
C200H-ID501/215
C200H-OD501/215
C200H-MD501/215
0.6 ms
0.6 ms when set for 32 I/O pts.
1.6 ms when set for dynamic I/O
C200H-CT001-V1/CT002
C200H-CT021
2.0 ms
0.7 ms
C200H-NC111/NC112
C200HW-NC113
C200H-NC211
2.1 ms
2.6 ms
5.0 ms
C200HW-NC213
C200HW-NC413
C200H-MC221
2.9 ms
4.5 ms
2 ms for normal operation
3 ms for refreshing expansion data area
C200H-AD001
1.1 ms
C200H-DA001
0.9 ms
C200H-TS001/TS101
C200H-ASC02
1.2 ms
1.9 ms normally, 5.0 ms for @ format
C200H-IDS01-V1/IDS21
C200H-OV001
2.0 ms normally, 5.5 ms for command transfer
3.3 ms
2.0 ms
2.7 ms
2.0 ms
1.4 ms
2.7 ms
1.0 ms
C200H-FZ001
C200H-TC
j
j
j
C200H-CP114
C200H-AD002
C200H-PID
j
j
j
C200H-DA002
C200HW-SRM21
0.44 ms when the max. number of Slaves is 16.
0.88 ms when the max. number of Slaves is 32.
C200HW-DRM21-V1
C200HW-DRT21
1.72 ms + 0.022 × the number of words
Group-2 High-density I/O
Unit Refresh
Unit
C200H-ID216
C200H-OD218
C200H-ID217
C200H-OD219
Time required per Unit
0.18 ms
0.14 ms
0.31 ms
0.23 ms
NT Links
If the PC is connected to a Programmable Terminal (PT) via a C200HX/HG/HE
Interface Unit, the times shown in the following table will be required to refresh
I/O for the PT.
Number of table entries for PT
I/O refresh time
Minimum setting:
2.5 ms
5.4 ms
Character string table: 0
Numeral table: 0
Maximum setting:
Character string table: 32
Numeral table: 128
363
Calculating Cycle Time
Section 6-2
Watchdog Timer and Long
Cycle Times
Within the PC, the watchdog timer measures the cycle time and compares it to a
set value. If the cycle time exceeds the set value of the watchdog timer, a FALS
9F error is generated and the CPU Unit stops. WDT(94) can be used to extend
the set value for the watchdog timer.
Even if the cycle time does not exceed the set value of the watchdog timer, a long
cycle time can adversely affect the accuracy of system operations as shown in
the following table.
Cycle time (ms)
Possible adverse affects
10 or greater
TIMH(15) inaccurate when TC 016 through TC 511 are used.
(Accuracy when using TC 000 through TC 0015 not affected.)
20 or greater
100 or greater
0.02-second clock pulse (SR 25401) not accurately readable.
0.1-second clock pulse (SR 25500) not accurately readable and
Cycle Time Error Flag (SR 25309) turns ON.
200 or greater
0.2-second clock pulse (SR 25501) not accurately readable.
6,500 or greater
FALS code 9F generated regardless of watchdog timer setting
and the system stops.
Online Editing
When online editing is executed from a Programming Device, operation will be
interrupted for a maximum of 80 ms and interrupts will be masked to rewrite the
user program. No warnings will be given for long cycle times during this interval.
Check the effects on I/O response time before editing the program online.
When bits 00 to 07 of AR 25 contain the password code of “5A,” online editing will
be disabled and the CPU Unit will be in standby status while the Online Edit Dis-
able Bit (AR 2509) is ON. The Online Edit Standby Flag (AR 2510) will be ON
while the CPU Unit is in standby status. Processing will be executed when AR
2509 is turned OFF. (AR 2510 will be turned OFF, too.)
Caution Editing the program online can cause delays in I/O responses with no warnings
being given from the system for the long cycle time produced by editing online.
Before editing online, make sure that delays in I/O responses will not create a
dangerous situation in the controlled system.
!
6-2 Calculating Cycle Time
The PC configuration, the program, and program execution conditions must be
taken into consideration when calculating the cycle time. This means taking into
account such things as the number of I/O points, the programming instructions
used, and whether or not peripheral devices are employed. This section shows
some basic cycle time calculation examples. To simplify the examples, the
instructions used in the programs have been assumed to be all either LD or OUT.
The average execution time for the instructions is thus 0.156 µs. (Execution
times are given in the table in 6-3 Instruction Execution Times.)
364
Calculating Cycle Time
Section 6-2
6-2-1 PC with I/O Units Only
Here, we’ll compute the cycle time for a simple PC. The CPU Unit controls only
I/O Units, eight on the CPU Rack and five on a 5-slot Expansion I/O Rack. The
PC configuration for this would be as shown below. It is assumed that the pro-
gram contains 5,000 instructions requiring an average of 0.156 µs each to
execute.
8-point Input Units 8-point Output Units
CPU Rack
Expansion I/O Rack
16-point Input Units
12-point Output Units
8-point Output Unit
Calculations
The equation for the cycle time from above is as follows:
Cycle time =
Overseeing time + Program execution time + I/O refresh time +
Peripheral device servicing time
Process
Calculation
With Peripheral
Without
Peripheral Device
Device
0.7 ms
0.78 ms
Overseeing
Fixed
0.7 ms
Program execution 0.156 µs/instruction
0.78 ms
× 5,000 instructions
I/O refresh
See below.
0.34 ms
0.26 ms
0.34 ms
0.0 ms
Peripheral device
servicing
Minimum time
Cycle time
Total of above
2.08 ms
1.82 ms
The I/O refresh time would be as follows for two16-point Input Units, four 8-point
Input Units, two 12-point Output Units (12-point Units are treated as 16-point
Units), and five 8-point Output Units controlled by the PC:
(16 pts × 2) + (8 pts × 4)
(16 pts × 2) + (8 pts × 5)
× 20 µs +
× 20 µs = 0.34 ms
8 pts
8 pts
6-2-2 PC with Host Link and Remote I/O Master Units
Here, the cycle time is computed for a PC with a Host Link Unit and Remote I/O
Master Unit installed. The PC configuration for this could be as shown below.
The CPU Unit controls three 8-point Input Units, three 8-point Output Units, a
Host Link Unit, and a Remote I/O Master Unit connected to a Remote I/O Slave
Rack containing four 16-point Input Units and four 12-point Output Units.
365
Calculating Cycle Time
Section 6-2
It is assumed that the program contains 5,000 instructions requiring an average
of 0.156 µs each to execute, and that nothing is connected to the RS-232C port
and no SYSMAC NET/SYSMAC LINK Unit is mounted.
Host Link Unit
8-point
8-point
Remote I/O
Master Unit
Input Units Output Units
CPU Rack
Computer
Slave Rack
16-point
Input Units
12-point
Output Units
Calculations
The equation for the cycle time is as follows:
Cycle time =
Overseeing time + Program execution time
+ I/O refreshing time + Host Link Unit servicing time
+ Peripheral device servicing time
Process
Calculation
With Peripheral
Without
Peripheral Device
Device
0.7 ms
0.78 ms
Overseeing
Fixed
0.7 ms
Program execution 0.156 µs/instruction
0.78 ms
× 5,000 instructions
I/O refresh
See below.
2.58 ms
6.0 ms
2.58 ms
6.0 ms
0.0 ms
Host Link servicing Fixed
Peripheral device
servicing
0.7 + 0.78 + 2.58 +
6 = 10.06
0.50 ms
10.06 × 0.05 = 0.50
Total of above
Cycle time
10.56 ms
10.06 ms
The I/O refreshing time would be as follows for three 8-point Input Units and
three 8-point Output Units mounted in the CPU Rack, and eight Units mounted in
a Slave Rack.
(8 pts × 3) + (8 pts × 3)
× 20 µs + 1.1 ms + 8 Units × 0.17 ms = 2.58 ms
8 pts
366
Instruction Execution Times
Section 6-3
6-3 Instruction Execution Times
The following table lists the execution times for all instructions that are available
for the C200HX/HG/HE. The maximum and minimum execution times and the
conditions which cause them are given where relevant. When “word” is referred
to in the Conditions column, it implies the content of any word except for indirect-
ly addressed DM words. Indirectly addressed DM words, which create longer
execution times when used, are indicated by “ꢀDM.”
Execution times for most instructions depend on whether they are executed with
an ON or an OFF execution condition. Exceptions are the ladder diagram
instructions OUT and OUT NOT, which require the same time regardless of the
execution condition. The OFF execution time for an instruction can also vary de-
pending on the circumstances, i.e., whether it is in an interlocked program sec-
tion and the execution condition for IL is OFF, whether it is between JMP(04) 00
and JME(05) 00 and the execution condition for JMP(04) 00 is OFF, or whether it
is reset by an OFF execution condition. “R,” “IL,” and “JMP” are used to indicate
these three times.
All execution times are given in microseconds unless otherwise noted.
ON execution time (µs)
C200HX C200HG C200HE C200HX C200HG C200HE
OFF execution time (µs)
Instruction
LD
Conditions
For IR and SR 23600 to SR 25515
For SR 25600 to SR 51115
For IR and SR 23600 to SR 25515
For SR 25600 to SR 51115
For IR and SR 23600 to SR 25515
For SR 25600 to SR 51115
For IR and SR 23600 to SR 25515
For SR 25600 to SR 51115
For IR and SR 23600 to SR 25515
For SR 25600 to SR 51115
For IR and SR 23600 to SR 25515
For SR 25600 to SR 51115
---
0.104
0.208
0.104
0.208
0.104
0.208
0.104
0.208
0.104
0.208
0.104
0.208
0.104
0.104
0.208
0.313
0.208
0.313
0.417
0.156
0.313
0.156
0.313
0.156
0.313
0.156
0.313
0.156
0.313
0.156
0.313
0.156
0.156
0.313
0.468
0.313
0.468
0.625
0.312
0.626
0.313
0.626
0.312
0.626
0.313
0.626
0.313
0.626
0.313
0.626
0.313
0.313
0.626
0.936
0.626
0.936
1.25
0.104
0.104
0.104
0.104
0.104
0.104
0.104
0.104
0.104
0.104
0.104
0.104
0.104
0.104
0.208
0.208
0.208
0.208
0.417
22.45
0.417
0.417
22.55
0.417
0.208
0.208
0.208
0.208
0.313
0.313
0.313
0.313
0.156
0.156
0.156
0.156
0.156
0.156
0.156
0.156
0.156
0.156
0.156
0.156
0.156
0.156
0.313
0.313
0.313
0.313
0.625
22.45
0.625
0.625
22.55
0.625
0.313
0.313
0.313
0.313
0.469
0.469
0.469
0.469
0.313
0.313
0.313
0.313
0.313
0.313
0.313
0.313
0.313
0.313
0.313
0.313
0.313
0.313
0.626
0.626
0.626
0.626
1.25
LD NOT
AND
AND NOT
OR
OR NOT
AND LD
OR LD
OUT
---
For IR and SR 23600 to SR 25515
For SR 25600 to SR 51115
For IR and SR 23600 to SR 25515
For SR 25600 to SR 51115
Constant for SV
OUT NOT
TIM
ꢀDM for SV
37.15
1.25
For designated words 256 to 511
Constant for SV
CNT
0.417
0.417
0.417
0.208
0.313
0.208
0.313
0.104
24.75
7.55
0.625
0.625
0.625
0.313
0.468
0.313
0.468
0.156
1.25
1.25
ꢀDM for SV
1.25
37.25
1.25
For designated words 256 to 511
For IR and SR 23600 to SR 25515
For SR 25600 to SR 51115
For IR and SR 23600 to SR 25515
For SR 25600 to SR 51115
---
1.25
SET
0.626
0.936
0.626
0.936
0.312
39.45
22.25
23.95
0.626
0.626
0.626
0.626
0.938
0.938
0.938
0.938
RSET
NOP(00)
END(01)
IL(02)
---
---
ILC(03)
---
9.25
367
Instruction Execution Times
Section 6-3
Instruction
Conditions
ON execution time (µs)
OFF execution time (µs)
C200HX C200HG C200HE C200HX C200HG C200HE
JMP(04)
JME(05)
FAL(06)
---
7.65
7.95
88.6
86.6
---
22.35
22.65
88.6
0.313
0.313
0.313
0.313
0.313
0.469
0.469
0.469
0.469
0.469
0.938
0.938
0.938
0.938
0.938
---
FAL numbers 01 to 99
FAL number 00
---
86.6
FALS(07)
STEP(08)
(see
note 1)
(see
note 2)
---
33.1
15.3
9.25
21.05
47.8
30
0.313
0.469
0.938
SNXT(09)
SFT(10)
---
23.95
35.75
0.313
0.469
0.938
With 1-word shift register
R: 8.05
IL: 8.05 JMP:
8.05
With 100-word shift register
With 250-word shift register
117.8
262.5
132.5
277.2
R: 8.05
R: 8.05
0.208
IL: 8.05 JMP:
8.05
IL: 8.05 JMP:
8.05
KEEP(11)
CNTR(12)
For IR and SR 23600 to SR 25515
For SR 25600 to SR 51115
Constant for SV
0.208
0.318
19.15
0.313
0.469
0.625
0.938
33.85
0.319
0.625
R: 16.95 IL: 11.65 JMP:
11.65
ꢀDM for SV
---
31.45
13.75
13.65
18.35
16.55
18.35
16.55
46.15
28.45
28.35
33.05
31.25
33.05
31.25
31.15
R: 16.95 IL: 11.65 JMP:
11.65
DIFU(13)
DIFD(14)
TIMH(15)
Normal: IL: 13.65 JMP:
13.75
Normal: IL: 13.55 JMP:
13.65 11.85
11.95
---
Interrupt Constant for SV
Normal cycle
Interrupt ꢀDM for SV
Normal cycle
R: 25.05 IL: 24.05 JMP:
14.45
R: 21.95 IL:21.05 JMP:
11.25
R: 37.1
R: 34.1
0.313
IL: 36.5 JMP:
14.45
IL: 33.3 JMP:
11.25
WSFT(16)
CMP(20)
When shifting 1 word
16.45
0.469
0.469
0.938
0.938
When shifting 6,144 words using ꢀDM
6.45 ms
(see
note 2)
When comparing a constant to a word
When comparing two words
0.417
0.521
35.2
0.625
0.781
1.25
1.56
49.9
1.25
1.87
48.4
1.25
1.87
49
0.313
0.313
0.313
When comparing two ꢀDM
MOV(21)
MVN(22)
When transferring a constant to a word 0.417
0.625
0.937
0.469
0.469
0.938
0.938
When comparing two words
0.625
33.7
When transferring ꢀDM to ꢀDM
When transferring a constant to a word 0.417
0.625
0.937
When comparing two words
When transferring ꢀDM to ꢀDM
When converting a word to a word
When converting ꢀDM to ꢀDM
When converting a word to a word
When converting ꢀDM to ꢀDM
When shifting a word
0.625
34.3
BIN(23)
BCD(24)
ASL(25)
19.65
40.5
34.35
55.2
32.95
53.8
26.95
38.05
0.313
0.313
0.313
0.469
0.469
0.469
0.938
0.938
0.938
18.25
39.1
12.25
23.35
When shifting ꢀDM
368
Instruction Execution Times
Section 6-3
Instruction
ASR(26)
ROL(27)
ROR(28)
COM(29)
ADD(30)
Conditions
ON execution time (µs)
C200HX C200HG C200HE C200HX C200HG C200HE
OFF execution time (µs)
When shifting a word
When shifting ꢀDM
11.95
22.95
13.15
24.25
13.15
24.25
11.45
22.65
16.65
18.45
50.1
26.65
37.65
27.85
38.95
27.85
38.95
26.15
37.35
31.35
33.15
64.8
0.313
0.313
0.313
0.313
0.313
0.469
0.469
0.469
0.469
0.469
0.938
0.938
0.938
0.938
0.938
When rotating a word
When rotating ꢀDM
When rotating a word
When rotating ꢀDM
When inverting a word
When inverting ꢀDM
Constant + word → word
Word + word→ word
ꢀDM + ꢀDM → ꢀDM
Constant – word → word
Word – word→ word
ꢀDM – ꢀDM → ꢀDM
Constant × word → word
Word × word→ word
ꢀDM × ꢀDM → ꢀDM
Word ÷ constant → word
Word ÷ word→ word
ꢀDM ÷ ꢀDM → ꢀDM
Constant AND word → word
Word AND word→ word
ꢀDM AND ꢀDM → ꢀDM
Constant OR word → word
Word OR word→ word
ꢀDM OR ꢀDM → ꢀDM
Constant XOR word → word
Word XOR word→ word
ꢀDM XOR ꢀDM → ꢀDM
Constant XNOR word → word
Word XNOR word→ word
ꢀDM XNOR ꢀDM → ꢀDM
When incrementing a word
When incrementing ꢀDM
When decrementing a word
When decrementing ꢀDM
---
SUB(31)
MUL(32)
DIV(33)
16.65
18.45
50.1
31.35
33.15
64.8
0.313
0.313
0.313
0.469
0.469
0.469
0.938
0.938
0.938
31.15
32.95
64.7
45.85
47.65
79.4
30.15
32.35
64.1
44.85
47.05
78.8
ANDW(34)
ORW(35)
14.35
15.25
46.7
29.05
29.95
61.4
0.313
0.313
0.313
0.313
0.469
0.469
0.469
0.469
0.938
0.938
0.938
0.938
14.35
15.25
46.7
29.05
29.95
61.4
XORW(36)
XNRW(37)
14.35
15.25
46.7
29.05
29.95
61.4
14.55
15.45
46.9
29.25
30.15
61.6
INC(38)
11.55
22.45
11.45
22.35
7.22
26.25
37.15
26.15
37.05
21.92
21.92
33.35
26.75
36.65
33.85
34.75
66.4
0.313
0.313
0.469
0.469
0.938
0.938
DEC(39)
STC(40)
CLC(41)
TRSM(45)
MSG(46)
0.313
0.313
0.313
0.313
0.469
0.469
0.469
0.469
0.938
0.938
0.938
0.938
---
7.22
---
18.65
12.05
21.95
19.15
20.05
51.7
Designated as DM
Designated as ꢀDM
Constant + word → word
Word + word → word
ꢀDM + ꢀDM → ꢀDM
Constant – word → word
Word – word → word
ꢀDM – ꢀDM → ꢀDM
ADB(50)
SBB(51)
0.313
0.313
0.469
0.469
0.938
0.938
18.95
19.85
51.7
33.65
34.55
66.4
369
Instruction Execution Times
Section 6-3
Instruction
Conditions
ON execution time (µs)
OFF execution time (µs)
C200HX C200HG C200HE C200HX C200HG C200HE
MLB(52)
Constant × word → word
Word × word → word
ꢀDM × ꢀDM → ꢀDM
Word ÷ constant → word
Word ÷ word → word
ꢀDM ÷ ꢀDM → ꢀDM
Word + word → word
ꢀDM + ꢀDM → ꢀDM
Word – word → word
ꢀDM – ꢀDM → ꢀDM
Word × word → word
ꢀDM × ꢀDM → ꢀDM
Word ÷ word → word
ꢀDM ÷ ꢀDM → ꢀDM
16.95
17.85
49.3
31.65
32.55
64
0.313
0.469
0.938
DVB(53)
17.15
18.05
49.7
31.85
32.75
64.4
0.313
0.469
0.938
ADDL(54)
SUBL(55)
MULL(56)
DIVL(57)
22.45
53.9
37.15
68.6
0.313
0.313
0.313
0.313
0.469
0.469
0.469
0.469
0.938
0.938
0.938
0.938
22.45
53.9
37.15
68.6
110.6
142.6
105.8
135.8
125.3
157.3
120.5
150.5
BINL(58)
BCDL(59)
XFER(70)
When converting words to words
When converting ꢀDM to ꢀDM
When converting words to words
When converting ꢀDM to ꢀDM
When transferring 1 word
35.15
55.9
25.75
46.5
45.3
655
49.85
70.6
0.313
0.313
0.313
0.469
0.469
0.469
0.938
0.938
0.938
40.45
61.2
44.2
When transferring 1,024 words using
653.9
ꢀDM
When transferring 6,143 words using
ꢀDM
3.66 ms
(see
note 3)
BSET(71)
ROOT(72)
When setting a constant to 1 word
19.75
40.9
34.45
55.6
0.313
0.313
0.469
0.469
0.938
0.938
When setting ꢀDM ms to 1,024 words
using ꢀDM
When setting ꢀDM ms to 6,144 words
using ꢀDM
52.3
67
When taking root of word and placing in 41.7
a word
56.4
100.2
When taking root of 99,999,999 in ꢀDM 85.5
and placing in ꢀDM
XCHG(73)
SLD(74)
Between words
Between ꢀDM
14.45
29.15
51.15
30.35
0.313
0.313
0.469
0.469
0.938
0.938
36.45
When shifting 1 word
15.65
When shifting 1,024 DM words using
ꢀDM
2.72 ms
(see
note 2)
When shifting 6,144 DM words using
ꢀDM
16.2 ms
(see
note 2)
SRD(75)
When shifting 1 word
15.65
30.35
0.313
0.469
0.938
When shifting 1,024 DM words using
ꢀDM
2.72 ms
(see
note 2)
When shifting 6,144 DM words using
ꢀDM
16.2 ms
(see
note 2)
MLPX(76)
DMPX(77)
When decoding word to word
When decoding ꢀDM to ꢀDM
When encoding a word to a word
When encoding ꢀDM to ꢀDM
47.3
62
0.313
0.313
0.469
0.469
0.938
0.938
103.8
28.45
111.8
118.5
43.15
126.5
370
Instruction Execution Times
Section 6-3
Instruction
Conditions
ON execution time (µs)
OFF execution time (µs)
C200HX C200HG C200HE C200HX C200HG C200HE
SDEC(78)
When decoding a word to a word
When decoding 2 digits ꢀDM to ꢀDM
When decoding 4 digits ꢀDM to ꢀDM
Word ÷ word → word (equals 0)
Word ÷ word → word (doesn’t equal 0)
ꢀDM ÷ ꢀDM → ꢀDM
26.95
63.3
71.7
62.3
499
41.65
78
0.313
0.469
0.938
86.4
77
FDIV(79)
0.313
0.469
0.938
513.7
857.7
843
DIST(80)
COLL(81)
MOVB(82)
Constant → (word + (word))
ꢀDM → (ꢀDM + (ꢀDM))
(Word + (word)) → word
(ꢀDM + (ꢀDM)) → ꢀDM
When transferring a constant to a word 17.35
27.65
61.5
28.75
64.3
42.35
76.2
0.313
0.313
0.313
0.469
0.469
0.469
0.938
0.938
0.938
43.45
79
32.05
34.15
67.6
When transferring word to a word
19.45
52.9
When transferring ꢀDM to ꢀDM
MOVD(83)
SFTR(84)
When transferring a constant to a word 16.95
31.65
32.95
69
0.313
0.313
0.469
0.469
0.938
0.938
When transferring word to a word
When transferring ꢀDM to ꢀDM
When shifting 1 word
18.25
54.3
20.05
1.1 ms
34.75
When shifting 1,024 ꢀDM using ꢀDM
(see
note 2)
When shifting 6,144 ꢀDM using ꢀDM
6.37 ms
37.25
(see
note 2)
TCMP(85)
Comparing to words in a designated
table
51.95
0.313
0.469
0.938
Comparing to words in a designated table 38.1
52.8
83.8
Comparing ꢀDM → ꢀDM-designated 69.1
table
ASC(86)
Between words
30.1
78.3
60.9
99.2
22.1
---
44.8
93
0.313
0.313
0.469
0.469
0.938
0.938
Between ꢀDM
SEND(90)
1-word transmit
75.6
113.9
36.8
---
1000-word transmit
SBS(91)
SBN(92)
RET(93)
WDT(94)
IORF(97)
---
0.313
0.313
0.313
0.313
0.469
0.469
0.469
0.469
0.469
0.938
0.938
0.938
0.938
0.938
---
---
20.9
10.55
35.6
25.25
---
1-word refresh
110 (IN), 170
(OUT)
110 (IN), 0.313
170
(OUT)
30-word refresh
2002
67.1
105.8
38.5
58.2
24.95
29.05
39.9
18.65
30.45
60.3
93
2000.9
RECV(98)
MCRO(99)
1-word refresh
67.1
0.313
0.313
0.313
0.469
0.469
0.469
0.938
0.938
0.938
1000-word refresh
105.8
53.2
Designating a word parameter
Designating a ꢀDM parameter
When resetting 1 word
When shifting 1 word using ꢀDM
When shifting 10 word using ꢀDM
Constant for SV
72.9
ASFT(––)
39.65
43.75
54.6
Default: (17)
SCAN(––)
33.35
45.15
75
0.313
0.313
0.469
0.469
0.938
0.938
Default: (18) ꢀDM for SV
MCMP(––)
Comparing 2 words, result word
Default: (19) Comparing 2 ꢀDM, result ꢀDM
107.7
371
Instruction Execution Times
Section 6-3
Instruction
Conditions
ON execution time (µs)
OFF execution time (µs)
C200HX C200HG C200HE C200HX C200HG C200HE
LMSG(––)
Word for SV
17.95
27.65
8.55
32.65
42.35
23.25
0.313
0.469
0.938
Default: (47) ꢀDM for SV
TERM(––)
Default: (48)
---
0.313
0.313
0.469
0.469
0.938
0.938
CMPL(––)
When comparing words to words
16.55
38.5
31.25
53.2
Default: (60) When comparing ꢀDM to ꢀDM
MPRF(––) 1 Unit
Default: (61) 10 Units
2.00
16.7
0.313
0.313
0.313
0.469
0.469
0.469
0.938
0.938
0.938
13.00
22.45
142.6
59.7
27.7
XFRB(––)
Sending 1 bit from word to word
37.15
157.3
74.4
Default: (62) Sending FF bits from ꢀDM to ꢀDM
LINE(––)
Default: (63)
When transferring from words to a
constant
When transferring from words to a word 62.1
76.8
197.2
87.4
When transferring ꢀDM to ꢀDM
182.5
72.7
COLM(––)
When transferring from a constant to
words
0.313
0.469
0.938
Default: (64)
When transferring from a word to words 74.9
89.6
205.2
50.05
71
When transferring ꢀDM to ꢀDM
190.5
35.35
56.3
SEC(––)
DM to DM
0.313
0.313
0.313
0.469
0.469
0.469
0.938
0.938
0.938
Default: (65) ꢀDM to ꢀDM
HMS(––)
DM to DM
36.5
51.2
72.4
Default: (66)
BCNT(––)
Default: (67)
ꢀDM to ꢀDM
57.7
Constant for SV
39.1
53.8
ꢀDM for SV
26.5 ms
(see
note 2)
BCMP(––)
Default: (68)
Comparing constant to word-designated 62.1
table
76.8
0.313
0.313
0.469
0.469
0.938
To a word after comparing with a word
63.1
98.2
77.8
Comparing ꢀDM → ꢀDM-designated
table
112.9
APR(––)
SIN designation
ꢀDM for SV
24.25
473
38.95
487.7
42.25
0.938
Default: (69)
TTIM(––)
Setting to a constant
27.55
Constant R: 24.15 JPM:
Default: (87)
input
OFF:
23.15
19.55
IL: 20.55
Setting to ꢀDM
35.5
50.2
Constant R: 36.3
JPM:
31.9
input
IL: 32.7
OFF:
35.30
ZCP(––)
Default: (88)
Comparing a constant to a word
Comparing a word to a word
Comparing ꢀDM to a ꢀDM
Word for SV
16.75
31.45
32.35
64.4
0.313
0.469
0.469
0.938
0.938
17.65
49.7
INT(––)
19.90 to 198.50
(see
0.313
note 3)
Default: (89)
ꢀDM for SV
19.90 to 213.5
(see
note 3)
TKY(––)
Input to DM
25.65
46.7
31.5
73.5
40.35
61.4
30.4
72.4
0.313
0.313
0.469
0.469
0.938
0.938
Input to ꢀDM
RXD(––)
When designating a word
When designating ꢀDM
372
Instruction Execution Times
Section 6-3
Instruction
Conditions
ON execution time (µs)
OFF execution time (µs)
C200HX C200HG C200HE C200HX C200HG C200HE
TXD(––)
When designating a word
When designating ꢀDM
Word-designated 4 digits
56.1
70.8
0.313
0.313
0.469
0.469
0.938
0.938
99.4
114.1
7SEG(––)
19 to 22
(see
note 2)
ꢀDM-designated 4 digits
30 to 34
(see
note 2)
Word-designated 8 digits
19 to 22
(see
note 2)
ꢀDM-designated 8 digits
30 to 34
(see
note 2)
FPD(––)
Word designation, code output
ꢀDM designation, message output
74.60 to 89.40
105.0 to 142.2
(see
note 2)
0.313
0.313
0.469
0.469
0.938
0.938
(see
note 2)
SRCH(––)
Constant for SV
Word for SV
39.7
54.4
1.35 ms
(see
note 2)
ꢀDM for SV
7.73 ms
(see
note 2)
MAX(––)
DM search
31.75
46.45
0.313
0.313
0.469
0.469
0.938
0.938
ꢀDM search
1.31 ms
(see
note 2)
MIN(––)
DM search
31.75
46.45
ꢀDM search
1.31 ms
(see
note 2)
SUM(––)
DM add
26.55
41.25
0.313
0.313
0.469
0.469
0.938
0.938
ꢀDM add
1.30 ms
(see
note 2)
FCS(––)
Add a word → word
26.75
41.45
Add 999 words → ꢀDM
1.05 ms
(see
note 2)
HEX(––)
DM conversion
36.95
102.6
33.05
51.65
117.3
47.75
0.313
0.313
0.469
0.469
0.938
0.938
ꢀDM conversion
AVG(––)
Average of an operation
Average of 64 operations
When designating a word
When designating ꢀDM
Constant for SV
133.8
48.1
148.5
62.8
PID(––)
0.313
0.313
0.469
0.469
0.938
0.938
89.4
104.1
54.6
XDMR(––)
39.9
Word for SV
1.44 ms
(see
note 2)
ꢀDM for SV
Input to DM
Input to ꢀDM
4.19 ms
29 to 34
45 to 51
(see
note 2)
MTR(––)
(see
note 2)
0.313
0.469
0.938
(see
note 2)
ADBL(––)
DM + DM → DM
27.35
60.1
42.05
74.8
0.313
0.313
0.469
0.469
0.938
0.938
ꢀDM + ꢀDM → ꢀDM
DM – DM → DM
SBBL(––)
26.95
59.7
41.65
74.4
ꢀDM – ꢀDM → ꢀDM
373
Instruction Execution Times
Section 6-3
Instruction
Conditions
ON execution time (µs)
OFF execution time (µs)
C200HX C200HG C200HE C200HX C200HG C200HE
MBS(––)
Constant × word → word
DM × DM → DM
20.85
21.65
53.5
21.55
22.45
54.9
45.3
77.1
86.6
118.6
13.95
15.65
36.9
18.65
40.7
15.05
16.85
37.1
18.15
39.7
19.95
53.3
58.3
89.4
23.55
44.3
35
35.55
36.35
68.2
36.25
37.15
69.6
60
0.313
0.469
0.938
ꢀDM × ꢀDM → ꢀDM
DBS(––)
Constant ÷ word → word
DM ÷ DM → DM
0.313
0.469
0.938
ꢀDM ÷ ꢀDM → ꢀDM
MBSL(––)
DBSL(––)
CPS(––)
DM × DM → DM
0.313
0.313
0.313
0.469
0.469
0.469
0.938
0.938
0.938
ꢀDM × ꢀDM → ꢀDM
91.8
101.3
133.3
28.65
30.35
51.6
33.35
55.4
29.75
31.55
51.8
32.85
54.4
34.65
68
DM ÷ DM → DM
ꢀDM ÷ ꢀDM → ꢀDM
When comparing two constants
When comparing DM to DM
When comparing DM to ꢀDM
When comparing two DM
When comparing two ꢀDM
When converting a constant to a word
When converting a word to a word
When converting ꢀDM to ꢀDM
When converting a word to a word
When converting ꢀDM to ꢀDM
When comparing two words
When comparing two ꢀDM
Word for SV
CPSL(––)
0.313
0.313
0.469
0.469
0.938
0.938
NEG(––)
NEGL(––)
ZCPL(––)
SCL(––)
0.313
0.313
0.313
0.313
0.313
0.469
0.469
0.469
0.469
0.469
0.938
0.938
0.938
0.938
0.938
73
ꢀDM for SV
104.1
38.25
59
HKY(––)
DSW(––)
When designating a word
When designating ꢀDM
DM CS output
49.7
49.7
59.7
58.7
58.7
67.7
70.4
DM RD output
35
DM data retrieval
45
ꢀDM CS output
44
ꢀDM RD output
44
ꢀDM data retrieval
53
BXFR(––)
Word designation (1 word)
ꢀDM designation (1,024 words)
71.5
3.68 ms
0.313
0.469
0.938
(see
note 3)
ꢀDM designation (6,144 words)
8.75 ms
(see
note 3)
EMBC(––)
Constant designation
18.45
19.95
33.45
46.4
33.15
34.65
48.15
45.3
0.313
0.313
0.469
0.469
0.938
0.938
Word designation
ꢀDM designation
XFR2(––)
Word designation (1 word)
ꢀDM designation (1,024 words)
ꢀDM designation (6,144 words)
656.2
3.66 ms
655.1
(see
note 3)
BXF2(––)
Word designation (1 word)
72.8
71.7
0.313
0.469
0.938
ꢀDM designation (1,024 words)
3.68 ms
(see
note 3)
ꢀDM designation (6,144 words)
8.75 ms
(see
note 3)
374
Instruction Execution Times
Section 6-3
Instruction
Conditions
ON execution time (µs)
OFF execution time (µs)
C200HX C200HG C200HE C200HX C200HG C200HE
IEMS(––)
Constant designation (Switch to DM.)
19.25
18.15
23.85
0.313
0.469
0.938
Word designation (Switch to EM bank.) 24.95
IORD(––)
IOWR(––)
STUP(––)
---
---
---
(see
note 1)
(see
note 2)
0.313
0.313
0.313
0.469
0.469
0.469
0.938
0.938
0.938
---
(see
note 1)
(see
note 2)
Default RS-232C designation
30.9
61
29.8
59.9
Communications Board Port A
ꢀDM designation
PMCR(––)
Constant for port & Sequence number,
DM for input and output words
41
39.9
54.9
73.1
0.313
0.469
0.938
Constant for port & Sequence number,
ꢀDM for input and output words
56
ꢀDM for port & Sequence number,
74.2
ꢀDM for input and output words
CMCR(––)
0.313
0.469
0.938
Word designation
DM designation
ꢀDM designation
74
72.9
78.9
101.9
80
103
Note 1. Same as the C200HX’s instruction execution time.
2. Add 14.7 µs to the C200HX’s instruction execution time.
3. Add 1.1 µs to the C200HX’s instruction execution time.
375
I/O Response Time
Section 6-4
6-4 I/O Response Time
The I/O response time is the time it takes for the PC to output a control signal
after it has received an input signal. The time it takes to respond depends on the
cycle time and when the CPU Unit receives the input signal relative to the input
refresh period.
The minimum and maximum I/O response time calculations described below
are for where IR 00000 is the input bit that receives the signal and IR 00200 is the
output bit corresponding to the desired output point.
00000
00200
6-4-1 Basic Systems
Minimum I/O Response
Time
The PC responds most quickly when it receives an input signal just prior to the
I/O refresh period in the cycle. Once the input bit corresponding to the signal has
been turned ON, the program will have to be executed once to turn ON the out-
put bit for the desired output signal and then the I/O refresh operation would
have to be repeated to refresh the output bit. The I/O response time in this case
is thus found by adding the input ON-delay time, the cycle time, and the output
ON-delay time. This situation is illustrated below.
Cycle time
Cycle time
Instruction
execution
Instruction
execution
Instruction
execution
Cycle
I/O refresh
Input
signal
CPU Unit reads
input signal
Input
ON delay
Output ON delay
Output
signal
I/O response time
Minimum I/O response time =
Input ON delay + Cycle time + Output ON delay
376
I/O Response Time
Section 6-4
Maximum I/O Response
Time
The PC takes longest to respond when it receives the input signal just after the
I/O refresh phase of the cycle. In this case the CPU Unit does not recognize the
input signal until the end of the next cycle. The maximum response time is thus
one cycle longer than the minimum I/O response time, except that the I/O refresh
time would not need to be added in because the input comes just after it rather
than before it.
Cycle time
Cycle time
Cycle time
Instruction
execution
Instruction
execution
Instruction
execution
Cycle
I/O refresh
Input
signal
CPU Unit reads
input signal
Input
ON
delay
Output
ON delay
Output
signal
I/O response time
Maximum I/O response time =
Input ON delay + (Cycle time × 2) + Output ON delay
Calculation Example
The data in the following table would produce the minimum and maximum cycle
times shown calculated below.
Item
Input ON-delay
Output ON-delay
Cycle time
Time
1.5 ms
15 ms
20 ms
Minimum I/O response time = 1.5 + 20 + 15 = 36.5 ms
Maximum I/O response time = 1.5 + (20 x 2) +15 = 56.5 ms
Note In this example the I/O refresh time is negligible has not been included in the
minimum I/O response time.
6-4-2 Remote I/O Systems
With Remote I/O Systems, only the cycle time of the PC needs to be considered
in computing the I/O response times as long as the remote I/O transmission time
is negligible and smaller than the cycle time. The cycle time, however, is in-
creased by the presence of the Remote I/O System.
The processing that determines and the methods for calculating maximum and
minimum response times from input to output are provided in this section. Cal-
culations assume that both the input and the output are located on Slave Racks
in a Remote I/O System, but the calculations are the same for I/O points on Opti-
cal I/O Units, I/O Link Units, I/O Terminals, etc.
Output on
Input on
Slave Rack
Slave Rack
X
Although more precise equations are possible if required, equations used for the
following calculations do not consider fractions of a scan.
377
I/O Response Time
Section 6-4
In looking at the following timing charts, it is important to remember the se-
quence in which processing occurs during the PC scan, particular that inputs will
not produce programmed actions until the program has been executed.
When calculating the response times involving inputs and outputs from another
CPU Unit connected by an I/O Link Unit, the cycle time of the controlling CPU
Unit and the cycle time of the PC to which the I/O Link Unit is mounted must both
be considered.
Caution Noise may increase I/O delays.
!
Remote I/O Transmission
Times
The remote I/O transmission time is computed as follows:
TRM = Total Slave transmission time for one Master
=
=
=
ΣTRT + ΣTTT
TRT
Transmission time for each Slave
1.4 ms + (0.2 ms × n)
Where n = number of I/O words on the Slave Rack
Optical I/O Unit/I/O Terminal transmission time
2 ms × m
TTT
=
=
Where m = number of Optical I/O Units/I/O Terminals
Minimum I/O Response
Time
The minimum response time occurs when all signals are processed as soon as
they are received. Here, three scans are required so that the program is
executed, as shown in the following diagram.
Time = Input ON delay + cycle time × 3 + output ON delay
Cycle time > Remote I/O transmission times
Cycle time
CPU Unit
Program execution
Transfer to CPU Unit
Master
Slave
Input
Transfer to Master
Slave I/O refresh
Output
378
I/O Response Time
Section 6-4
Maximum I/O Response
Time
The maximum response time occurs when the input just misses the program
execution portion of the scan, meaning that processing must wait for the next
transmission and then the next (i.e., the fourth) scan.
Time = Input ON delay + cycle time × 4 + output ON delay
Cycle time > Remote I/O transmission times
Note Use the maximum cycle time output to AR 26 in computing the maximum I/O re-
sponse time.
Cycle time
CPU Unit
Program execution
Transfer to CPU Unit
Master
Slave
Input
Slave I/O refresh
Transfer to Master
Output
Example Calculations
Calculations would be as shown below for an input ON delay of 1.5 ms, an out-
put ON delay of 15 ms, and a cycle time of 20 ms.
Minimum I/O Response Time
Time = 1.5 ms + (20 ms × 3) + 15 ms = 76.5 ms
Maximum I/O Response Time
Time = 1.5 ms + (20 ms × 4) + 15 ms = 96.5 ms
Note 1. The cycle time may be less than or equal to the remote I/O transmission time
when there are Special I/O Units on Slave Racks. If this is the case, there
may be cycles when I/O is not refreshed between the Master and the
C200HX/HG/HE CPU Unit.
2. Refreshing is performed for Masters only once per cycle, and then only after
confirming completion of the remote cycle.
3. The short duration of ON/OFF status produced by differentiated instructions
can cause inaccurate signals when dealing with Remote I/O Systems un-
less appropriate programming steps are taken.
379
I/O Response Time
Section 6-4
6-4-3 Host Link Systems
The following diagram illustrates the processing that takes place when an input
on one PC is transferred through the Host Link System to turn ON an output on
another PC. Refer to Host Link System documentation for further details.
Output on #31
X
Input on #0
Command/response for Unit # 0
Command/response for Unit # 31
Command
Command
Response
Host computer
Response
Host computer
processing time
Buffer for Host
Link Unit # 0
CPU Unit reads
input signal
Cycle time
PC for Host
Link Unit # 0
I/O refresh
CPU Unit writes
output signal
Host link service
Buffer for Host
Link Unit # 31
Cycle time
PC for Host
Link Unit # 31
I/O refresh
Host link service
Input
signal
Input ON delay
Output ON delay
Output
signal
I/O response time
The equations used to calculate the minimum and maximum cycle times are giv-
en below. The number of cycles required for each PC depends on the amount of
data being read/written.
Minimum response time =
Maximum response time =
Input ON delay + Command transmission time + (Cycle time of PC for Unit #0 × 3) + Response transmis-
sion time + Host computer processing time + Command transmission time + (Cycle time of PC for Unit #31
× 3) + Output ON delay
Input ON delay + Command transmission time + (Cycle time of PC for Unit #0 × 10) + Response transmis-
sion time + Host computer processing time + Command transmission time + (Cycle time of PC for Unit #31
× 10) + Output ON delay
6-4-4 PC Link Systems
The processing that determines and the methods for calculating maximum and
minimum response times from input to output are provided in this subsection.
The following System and I/O program steps will be used in all examples below.
This System contains eight PC Link Units.
380
I/O Response Time
Section 6-4
In looking at the following timing charts, it is important to remember the se-
quence processing occurs during the PC scan, particular that inputs will not pro-
duce programmed-actions until the program has been execution.
PC Link Unit
PC
PC Link Unit
PC
Unit 0
Unit 7
Output on PC
of Unit 7
Input on PC
of Unit 0
X
LR
bit
Input
Output
X
Input
LR XXXX
LR XXXX
Output
X
Note Noise may increase I/O delays.
PC Link Conditions
The PC Link System used in this example consists of the following:
• No. of PCs linked:
• No. of LR points linked: 128 per PC
8
• Maximum PC:
8
• LR points used:
1,024
Minimum Response Time
The following illustrates the data flow that will produce the minimum response
time, i.e., the time that results when all signals and data transmissions are pro-
cessed as soon as they occur.
Program executed.
I/O refresh
Cycle time
PC with
Unit 0
Minimum transmission time
Buffer in Unit 0
PC Link Unit trans-
missions
I/O refresh
Buffer in Unit 7
Program
executed.
PC with
Unit 7
Cycle time
Input
Output
The equation for minimum I/O response time is thus as follows:
Response time = Input ON delay + Cycle time of PC of Unit 0 + Minimum trans-
mission time + (Cycle time of PC of Unit 7 × 2) + Output ON
delay
Inserting the following values into this equation produces a minimum I/O re-
sponse time of 149.3 ms.
Input ON delay:
1.5 ms
381
I/O Response Time
Section 6-4
Output ON delay:
15 ms
Cycle time for PC of Unit 0:
Cycle time for PC of Unit 7:
Minimum transmission time:
20 ms
50 ms
2.8 ms+10 ms=12.8 ms
Maximum Response Time
The following diagram illustrates the data flow that will produce the maximum
response time. Delays occur because signals or data is received just after they
would be processed or because data is sent during processing. In either case,
processing must wait until the next scan/polling cycle.
First output to the buffer in the polling unit is delayed by the setting of the number
of LR bits to be refreshed each scan. A similar delay is present when the LR data
reaches Unit 7. The polling delay is the result of the LR data in its PC being up-
dated immediately after the previous was sent to the buffer in the PC Link Unit,
cause a delay until the next polling cycle. One more polling cycle is then required
before the data reaches the buffer in PC Link Unit 7.
I/O refresh
Cycle time
PC with
Unit 0
PC Link
polling time
Buffer in Unit 0
Polling delay
Induction sequence
processing time
PC Link Unit
transmissions
Maximum
transmission
time
Buffer in Unit 7
PC with
Unit 7
Cycle time
Input
Output
The equation for maximum I/O response time is thus as follows:
Response time = Input ON delay + [Cycle time of PC of Unit 0 × (Number of LR
transfer bits ÷ I/O refresh bits)] + α + (PC Link polling time +
Induction sequence processing time) + {Cycle time of PC of
Unit 7× [(Number of LR transfer bits ÷ I/O refresh bits) × 2 + 1]}
+ β + Output ON delay
If cycle time of PC of Unit 0 > PC Link polling time, α = cycle time of PC of Unit 0. If
cycle time of PC of Unit 0 < PC Link polling time, α = PC Link polling time.
If cycle time of PC of Unit 7 > PC Link polling time, β = cycle time of PC of Unit 7. If
cycle time of PC of Unit 7 < PC Link polling time, β = PC Link polling time.
Inserting the following values into this equation produces a maximum I/O re-
sponse time of 661.3 ms.
Input ON delay:
1.5 ms
Output ON delay:
15 ms
Cycle time for PC of Unit 0:
Cycle time for PC of Unit 7:
PC Link polling time:
20 ms
50 ms
2.8 ms × 8 PCs + 10 ms = 32.4 ms
Induction sequence processing: 15 ms × (8 PCs – 8 PCs) = 0 ms
382
I/O Response Time
Section 6-4
I/O refresh bits for Unit 0
I/O refresh bits for Unit 7
256
256
Reducing Response Time
IORF(97) can be used in programming to shorten the I/O response time greater
than is possible by setting a high number of refresh bits. (Remember, increasing
the number of refresh bits set on the back-panel LED shortens response time,
but increases the cycle time of the PC.)
In programming the PCs for PC Link Units #0 and #7, IORF(97) is executed dur-
ing every PC scan for the PC Link Units. The basic equation for the maximum I/O
response time is as follows:
Response time = Input ON delay + [Cycle time of PC of Unit 0 × (Number of LR
transfer bits ÷ Number of I/O refresh bits ÷ 2)] + α + PC Link
polling time + Induction sequence processing time + {Cycle
time of PC of Unit 7 × [(Number of LR transfer bits ÷ Number of
I/O refresh bits ÷ 2) × 2 + 1]} + β + Output ON delay
If cycle time of PC of Unit 0 > PC Link polling time, α = cycle time of PC of Unit 0. If
cycle time of PC of Unit 0 < PC Link polling time, α = PC Link polling time.
If cycle time of PC of Unit 7 > PC Link polling time, β = cycle time of PC of Unit 7. If
cycle time of PC of Unit 7 < PC Link polling time, β = PC Link polling time.
The required data from the example System configuration is as follows:
Input ON delay
1.5 ms
15 ms
Output ON delay
Cycle time of PC of Unit 0
20 ms + 5.7 ms = 25.7
(5.7 ms required for IORF execution)
Cycle time of PC of Unit 7
50 ms + 5.7 ms = 55.7
(5.7 ms required for IORF execution)
Number of PC Link Units
Number of LR bits
8
1,024
Number of refresh bits for Unit 0
Number of refresh bits for Unit 7
PC Link polling time
256
256
2.8 ms × 8 PCs + 10 ms = 32.4 ms
Induction sequence processing time
15 ms × (8 PCs – 8 PCs) = 0 ms
Placing these values into the equation produces a maximum I/O response time
of 466.9 ms, approximately 200 ms shorter than when IORF is not used.
6-4-5 One-to-one Link I/O Response Time
When two C200HX/HG/HEs are linked one-to-one, the I/O response time is the
time required for an input executed at one of the C200HX/HG/HEs to be output
to the other C200HX/HG/HE by means of one-to-one link communications.
One-to-one link communications are carried out reciprocally between the mas-
ter and the slave. The respective transmission times are as shown below, de-
pending on the number of LR words used.
Number of words used
64 words (LR 00 to LR 63)
Transmission time
39 ms
20 ms
10 ms
32 words (LR 00 to LR 31)
16 words (LR 00 to LR 15)
383
I/O Response Time
Section 6-4
The minimum and maximum I/O response times are shown here, using as an
example the following instructions executed at the master and the slave. In this
example, communications proceed from the master to the slave.
Output (LR)
Input
(LR)
Output
Input
The following conditions are taken as examples for calculating the I/O response
times.
Input ON delay:
Master cycle time:
Slave cycle time:
Output ON delay:
8 ms
10 ms
14 ms
10 ms
Number of LR words: 64 words
Minimum I/O Response Time The C200HX/HG/HE responds most quickly under the following circumstances:
1, 2, 3...
1. The C200HX/HG/HE receives an input signal just prior to the input refresh
phase of the cycle.
2. The master to slave transmission begins immediately.
3. The slave executes communications servicing immediately after comple-
tion of communications.
Input
point
I/O refresh
Overseeing, communica-
tions, etc.
Input ON delay
Input
bit
Master
Cycle time
Instruction
CPU Unit
processing
Instruction
execution
execution
One-to-one link
communications
Master to
Slave
Instruction
execution
Instruction
execution
CPU Unit
processing
Slave
Output ON
delay
Output point
The minimum I/O response time is as follows:
Input ON delay:
8 ms
Master cycle time:
Transmission time:
Slave cycle time:
Output ON delay:
Minimum I/O response time:
10 ms
39 ms
15 ms
10 ms
82 ms
+
Maximum I/O Response Time The C200HX/HG/HE takes the longest to respond under the following circum-
stances:
1, 2, 3...
1. The C200HX/HG/HE receives an input signal just after the input refresh
phase of the cycle.
2. The master to slave transmission does not begin immediately.
384
I/O Response Time
Section 6-4
3. Communications are completed just after the slave executes communica-
tions servicing.
I/O refresh
Input
point
Input ON delay
Overseeing, communica-
tions, etc.
Input
bit
Master
Cycle time
CPU Unit
processing
Instruction
execution
Instruction
execution
Instruction
execution
Master to
Slave
Slave to
Master
Master to
Slave
One-to-one link
communications
CPU Unit
processing
Instruction
execution
Instruction
execution
Instruction
execution
Slave
Output ON
delay
Output point
The maximum I/O response time is as follows:
Input ON delay:
8 ms
Master cycle time:
Transmission time:
Slave cycle time:
10 ms × 2
39 ms × 3
15 ms × 2
10 ms
+
Output ON delay:
Maximum I/O response time:
185 ms
6-4-6 Interrupt Response Times
The response time from the time an interrupt input is received until the interrupt
subroutine execution has been completed is described next.
Input Interrupts
External interrupt input signal
t1
Internal interrupt signal
t2
Interrupt subroutine execution
t1 = ON delay of Interrupt Input Unit
t2 = Software interrupt response time
Total interrupt response time = t1 + t2
The ON delay of Interrupt Input Unit is 0.2 ms or less.
The software interrupt response time depends on the interrupt response param-
eter setting in DM 6620 of the PC Setup. If the DM 6620 is set for the C200H-
compatible mode (0000), the software interrupt response time is less than
10 ms. If the DM 6620 is set for the C200HX/HG/HE mode (1xxx), the software
interrupt response time is less than 1 ms. The total interrupt response time is
thus as shown in the following table.
Interrupt response setting
Total interrupt response time
C200H-compatible mode
(Normal response)
0.2 ms + (Total of following: Special I/O
processing time, Remote I/O processing time,
Host Link servicing time, instruction execution)
C200HS mode
1.2 ms or less
(High-speed response)
385
I/O Response Time
Section 6-4
Scheduled Interrupts
Scheduled in-
terrupt interval
Hardware time clock
Scheduled interrupt
subroutine execution
t3
t3
t3
t3
t3 = Software interrupt response time
Total interrupt response time = t3 (software interrupt response time)
The software interrupt response time depends on the interrupt response param-
eter setting in DM 6620 of the PC Setup. If the DM 6620 is set for the C200H-
compatible mode (0000), the software interrupt response time is less than
10 ms. If the DM 6620 is set for the C200HS mode (1xxx), the software interrupt
response time is less than 1 ms. The total interrupt response time is thus as
shown in the following table.
Interrupt response setting
Total interrupt response time
C200H-compatible mode
(Normal response)
Total of following: Special I/O processing time,
Remote I/O processing time, Host Link
servicing time, instruction execution
C200HS mode
1.0 ms or less
(High-speed response)
Note 1. If there is any instruction in the program that requires longer than 10 ms to
execute when using the C200H-compatible mode, the total interrupt re-
sponse time will be equal to the execution time of the instruction requiring
longer than 10 ms.
2. The above calculations assume that only one interrupt requires executed at
any one time. If multiple interrupts are generated at the same time, execu-
tion of all but the first interrupt will go on standby, increasing the response
times given above.
3. If an interrupt occurs while a C200HS-SLK
j
j
o
r
C
2
0
0
H
S
-
S
N
T
j
j
i
s
b
e
-
ing serviced, the interrupt will not be processed until SYSMAC NET/SYS-
MAC LINK Unit servicing has been completed. The response times in this
case will be as shown in the following table and will not be affected by the
interrupt response setting.
Interrupt
Total interrupt response time
Input interrupt
10.2 ms max.
Scheduled interrupt 10 ms max.
This restriction does not apply when a C200HW-SLKj j is being used with
a C200HX/HG/HE PC.
Interrupt Processing Time
The processing time from receiving an interrupt input, through program execu-
tion, and until a return is made to the original program location is described next.
The limit of the count frequency resulting from using the scheduled interrupt pe-
riod or input interrupts as the count input is determined by the interrupt proces-
sing time.
Interrupt processing time =
Total interrupt response time + Interrupt program execution time +
Interrupt return time
The interrupt program execution time is determined by the content of the inter-
rupt subroutine. This time is negligible f only SBN(92) and RET(93) are
executed.
386
I/O Response Time
Section 6-4
The interrupt return time is 0.04 ms.
Note 1. If there are several elements that can cause interrupts or if the interrupt peri-
od is shorted than the average interrupt processing time, the interrupt sub-
routine will be executed and the main program will not be executed. This will
cause the cycle monitoring time to be exceeded and an FALS 9F error will be
generated, stopping PC operation.
2. The maximum interrupt program execution time is contained in SR 262 and
SR 263.
Interrupt Input Pulse Width
The pulse width input to Interrupt Input Units must be set to within the conditions
shown in the following diagram.
0.5 ms min.
0.2 ms min.
ON time:
OFF time:
0.2 ms min.
0.5 ms min.
387
SECTION 7
Program Monitoring and Execution
This section provides the procedures for monitoring and controlling the PC through a Programming Console. Refer to the
SYSMAC Support Software Operation Manual for SSS procedures if you are using a computer running SSS.
7-1 Monitoring Operation and Modifying Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2 Programming Console Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2-1 Bit/Word Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2-2 Forced Set/Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2-3 Forced Set/Reset Cancel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2-4 Hexadecimal/BCD Data Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2-5 Hex/ASCII Display Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2-6 4-digit Hex/Decimal Display Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2-7 8-digit Hex/Decimal Display Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2-8 Differentiation Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2-9 3-word Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2-10 3-word Data Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2-11 Binary Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2-12 Binary Data Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2-13 Changing Timer/Counter SV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2-14 Expansion Instruction Function Code Assignments . . . . . . . . . . . . . . . . . . . . . . .
7-2-15 UM Area Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2-16 Reading and Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2-17 Expansion Keyboard Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-2-18 Keyboard Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
390
390
390
393
395
396
398
399
400
401
402
402
403
405
406
409
410
411
411
412
389
Programming Console Operations
Section 7-2
7-1 Monitoring Operation and Modifying Data
The simplest form of operation monitoring is to display the address whose oper-
and bit status is to be monitored using the Program Read or one of the search
operations. As long as the operation is performed in RUN or MONITOR mode,
the status of any bit displayed will be indicated.
This section provides other procedures for monitoring data as well as proce-
dures for modifying data that already exists in a data area. Data that can be mo-
dified includes the PV (present value) and SV (set value) for any timer or counter.
All monitor operations in this section can be performed in RUN, MONITOR, or
PROGRAM mode and can be cancelled by pressing CLR.
All data modification operations except for timer/counter SV changes are per-
formed after first performing one of the monitor operations. Data modification is
possible in either MONITOR or PROGRAM mode, but cannot be performed in
RUN mode.
7-2 Programming Console Operations
7-2-1
Bit/Word Monitor
The status of any bit or word in any data area can be monitored using the follow-
ing operation. Although the operation is possible in any mode, ON/OFF status
displays will be provided for bits in MONITOR or RUN mode only.
The Bit/Digit Monitor operation can be entered either from a cleared display by
designating the first bit or word to be monitored or it can be entered from any
address in the program by displaying the bit or word address whose status is to
be monitored and pressing MONTR.
When a bit is monitored, it’s ON/OFF status will be displayed (in MONITOR or
RUN mode); when a word address is designated other than a timer or counter,
the digit contents of the word will be displayed; and when a timer or counter num-
ber is designated, the PV of the timer will be displayed and a small box will ap-
pear if the completion flag of a timer or counter is ON. When multiple words are
monitored, a caret will appear under the leftmost digit of the address designation
to help distinguish between different addresses. The status of TR bits and SR
flags (e.g., the arithmetic flags), cleared when END(01) is executed, cannot be
monitored.
Up to six memory addresses, either bits, words, or a combination of both, can be
monitored at once, although only three of these are displayed at any one time. To
monitor more than one address, return to the start of the procedure and continue
designating addresses. Monitoring of all designated addresses will be main-
tained unless more than six addresses are designated. If more than six address-
es are designated, the leftmost address of those being monitored will be can-
celled.
To display addresses that are being monitored but are not presently on the Pro-
gramming Console display, press MONTR without designating another ad-
dress. The addresses being monitored will be shifted to the right. As MONTR is
pressed, the addresses being monitored will continue shifting to the right until
the rightmost address is shifted back onto the display from the left.
During a monitor operation the up and down keys can be pressed to increment
and decrement the leftmost address on the display and CLR can be pressed to
cancel monitoring the leftmost address on the display. If the last address is can-
celled, the monitor operation will be cancelled. The monitor operation can also
be cancelled regardless of the number of addresses being monitored by press-
ing SHIFT and then CLR.
LD and OUT can be used only to designate the first address to be displayed; they
cannot be used when an address is already being monitored.
390
Programming Console Operations
Section 7-2
Key Sequence
Clears leftmost
address
Cancels monitor
operation
(EM area)
(EM bank 0, 1, or 2.)
Examples
The following examples show various applications of this monitor operation.
Program Read then Monitor
00100
00100READ
TIM
000
T000
1234
T001
o0000
Indicates Completion flag is ON
Monitor operation
is cancelled
00100
TIM
001
391
Programming Console Operations
Section 7-2
Bit Monitor
00000
00000
LD
00001
00001
00001
^ ON
00000
CONT
Note The status of TR bits SR flags SR 25503 to 25507 (e.g., the arithmetic flags),
cleared when END(01) is executed, cannot be monitored.
Word Monitor
00000
00000
CHANNEL
000
00000
CHANNEL LR 01
cL01
FFFF
cL00
0000
EM Area Word Monitor
00000
00000
CHANNEL e0Ć0000
00000
Specify the EM bank and
address to be monitored.
CHANNEL e1Ć0100
e0100
10000
The specified EM word and
its contents are displayed.
392
Programming Console Operations
Section 7-2
Multiple Address Monitoring
00000
00000
TIM
000
T000
0100
00000 T000
0100
00001 T000
0100
00001 T000
OFF 0100
D000000001 T000
^OFF 0100
D000000001 T000
10FF^ OFF 0100
T000D000000001
0100 10FF^ OFF
D000000001
10FF^ OFF
Cancels monitoring
of leftmost address
00001
^ OFF
00000
CONT
00001
00000
Monitor operation
is cancelled
CHANNEL DM 0000
0000000001
S ONR OFF
Indicates Force Reset
in operation.
Indicates Force Set
in operation.
7-2-2
Forced Set/Reset
When the Bit/Digit Monitor operation is being performed and a bit, timer, or
counter address is leftmost on the display, PLAY/SET can be pressed to turn ON
the bit, start the timer, or increment the counter and REC/RESET can be pressed
to turn OFF the bit or reset the timer or counter. Timers will not operate in PRO-
GRAM mode. SR bits cannot be turned ON and OFF with this operation.
393
Programming Console Operations
Section 7-2
Bit status will remain ON or OFF only as long as the key is held down; the original
status will return as soon as the key is released. If a timer is started, the comple-
tion flag for it will be turned ON when SV has been reached.
SHIFT and PLAY/SET or SHIFT and REC/RESET can be pressed to maintain
the status of the bit after the key is released. The bit will not return to its original
status until the NOT key is pressed, or one of the following conditions is met.
1, 2, 3...
1. The Force Status Clear operation is performed.
2. The PC mode is changed. (See note.)
3. Operation stops due to a fatal error or power interruption.
4. The I/O Table Registration operation is performed.
This operation can be used in MONITOR mode to check wiring of outputs from
the PC prior to actual program execution. This operation cannot be used in RUN
mode.
Note The forced set/reset bit status will be maintained when switching from PRO-
GRAM to MONITOR mode if the Force Status Hold Bit is ON and DM 6601 of the
PC Setup has been set maintain the bit’s status. Refer to 3-6-4 PC Setup for de-
tails.
Key Sequence
Example
The following example shows how either bits or timers can be controlled with the
Force Set/Reset operation. The displays shown below are for the following pro-
gram section.
00100
TIM 000
#0123
012.3 s
TIM 000
00500
Address Instruction
Data
00200
00201
LD
00100
000
TIM
#
0123
000
00202
00203
LD
TIM
OUT
00500
394
Programming Console Operations
Section 7-2
The following displays show what happens when TIM 000 is set with 00100 OFF
(i.e., 00500 is turned ON) and what happens when TIM 000 is reset with 00100
ON (i.e., timer starts operation, turning OFF 00500, which is turned back ON
when the timer has finished counting down the SV).
(This example is performed in MONITOR mode.)
0010000500
Monitoring 00100 and 00500.
^ OFF^ OFF
0010000500
Force set bit status.
=
O
N
^
O
F
F
Indicates that force set/reset is in progress.
0010000500
Reset the force-set bit.
= OFF^ OFF
T0000010000500
^ OFF^ OFF
T0000010000500
Monitoring TIM 000.
0123^ OFF^ OFF
Force setting TIM 000
turns ON 00500.
T0000010000500
=
0
0
0
0
^
O
F
F
^
O
N
T0000010000500
0123^ OFF^ OFF
TIM 000 returns to its original status
when PLAY/SET is released.
T0000010000500
o0000^ ON^ ON
Display with 0010 originally ON.
T0000010000500
=
0
1
2
3
^
O
N
^
O
F
F
Timer starts timing, turning
00500 OFF.*
T0000010000500
0122^ ON^ OFF
When the time is up, 00500
goes ON again.
T0000010000500
o0000^ ON^ ON
Indicates that the time is up.
*Timing not done in PROGRAM mode.
7-2-3
Forced Set/Reset Cancel
This operation restores the status of all bits in the I/O, IR, TIM, CNT, HR, AR, or
LR areas which have been force set or reset. It can be performed in PROGRAM
or MONITOR mode.
Key Sequence
When the PLAY/SET and REC/RESET keys are pressed, a beeper will sound. If
you mistakenly press the wrong key, then press CLR and start again from the
beginning.
395
Programming Console Operations
Section 7-2
Example
The following example shows the displays that appear when Restore Status is
carried out normally.
00000
00000
00000FORCE RELE?
00000FORCE RELE
END
7-2-4
Hexadecimal/BCD Data Modification
When the Bit/Digit Monitor operation is being performed and a BCD or hexadeci-
mal value is leftmost on the display, CHG can be input to change the value. SR
words cannot be changed.
If a timer or counter is leftmost on the display, the PV will be displayed and will be
the value changed. See 7-2-13Changing Timer/Counter SV for the procedure to
change SV. PV can be changed in MONITOR mode only when the timer or
counter is operating.
To change contents of the leftmost word address, press CHG, input the desired
value, and press WRITE
Key Sequence
Word currently
monitored on
left of display.
[ Data ]
396
Programming Console Operations
Section 7-2
Example
The following example shows the effects of changing the PV of a timer.
This example is in MONITOR mode
00000
00000
Monitor status of timer PV
that will be changed.
TIM
000
T000
0122
Timing
PRES VAL?
PV decrementing
T000 0119 ????
Timing
Timing
PRES VAL?
T000 0100 0200
PV changed. Timer/counter PVs
can be changed even when the
timer/counter is operating.
T000
0199
Timing
397
Programming Console Operations
Section 7-2
7-2-5
Hex/ASCII Display Change
This operation converts DM data displays from 4-digit hexadecimal data to
ASCII and vice versa.
Key Sequence
Word currently
displayed.
Example
00000
00000
Monitor the desired DM word.
CH
DM 0000
D0000
4412
D0000
"AB"
Press TR to change the display
to ASCII code.
D0000
4142
Press TR again to return the
display to hexadecimal.
398
Programming Console Operations
Section 7-2
7-2-6
4-digit Hex/Decimal Display Change
This operation converts data displays from normal or signed 4-digit hexadecimal
data to decimal and vice versa.
Decimal values from 0 to 65,535 are valid when inputting normal 4-digit hexade-
cimal data, and decimal values from –32,768 to +32,767 are valid when inputting
signed 4-digit hexadecimal data.
Key Sequence
Single word or
3-word monitor
TR
[New data]
TR
currently displayed.
Clear new input data.
Specifies positive
signed data.
(NOT switches between
normal and signed data.)
Specifies negative
signed data.
Example
cL01D000000001
CFC7 1234R OFF
Monitor the desired word.
(Leftmost word in 3-word monitor.)
cL01
Press SHIFT and TR to change the
display to signed decimal.
TR
Ć12345
cL01
53191
Press NOT to switch back and forth
between signed and normal data.
cL01
Ć12345
PRES VAL?
Press CHG to change the content of the
displayed word.
cL01Ć12345
PRES VAL?
Press PLAY/SET to specify positive
signed data.
cL01+12345
PRES VAL?
Input the new value.
cL01+32767
cL01
Press WRITE to enter the new data to
memory.
+32767
cL01D000000001
7FFF 1234R OFF
Press SHIFT and TR to change the
display back to hexadecimal.
TR
399
Programming Console Operations
Section 7-2
7-2-7
8-digit Hex/Decimal Display Change
This operation converts data displays from normal or signed, 4 or 8-digit hexa-
decimal data to decimal and vice versa.
Decimal values from 0 to 4,294,967,295 are valid when inputting normal 8-digit
hexadecimal data, and decimal values from –2,147,483,648 to +2,147,483,647
are valid when inputting signed 8-digit hexadecimal data.
Key Sequence
3-word monitor
TR
[New data]
TR
currently displayed.
Clear new input data.
Specifies positive
signed data.
(NOT switches between
normal and signed data.)
Specifies negative
signed data.
Example
cL01D000000001
8000 1234R OFF
Monitor the first of the desired words.
(Leftmost word in 3-word monitor.)
cL01
Press SHIFT and TR to change the
display to signed decimal.
TR
Ć32768
Press EXT to change the display to
8-digit signed decimal.
(In this case, LR 02 contains FFFE.)
cL02 cL01
Ć0000098304
cL02 cL01
4294868992
Press NOT to switch back and forth
between signed and normal data.
cL02 cL01
Ć0000098304
PRES VAL?
Press CHG to change the contents of
the displayed words.
cL02Ć0000098304
PRES VAL?
Press PLAY/SET to specify positive
signed data.
cL02+0000098304
PRES VAL?
Input the new value.
(1234567890 in this case.)
[New data]
cL02+1234567890
cL02 cL01
Press WRITE to enter the new data to
memory.
+1234567890
cL01D000000001
02D2 1234R OFF
Press SHIFT and TR to change the
display back to hexadecimal.
TR
Rightmost four digits
400
Programming Console Operations
Section 7-2
7-2-8
Differentiation Monitor
This operation can be used to monitor the up or down differentiation status of bits
in the IR, SR, AR, LR, HR, and TC areas. To monitor up or down differentiation
status, display the desired bit leftmost on the bit monitor display, and then press
SHIFT and the Up or Down Arrow Key.
A CLR entry changes the Differentiation Monitor operation back to a normal bit
monitor display.
Key Sequence
Bit monitor in progress
Example
L000000108H2315
Monitor the desired bit so that it is
leftmost on the screen.
OFF OFF ON
L000000108H2315
U@OFF OFF ON
Press SHIFT and Up Arrow to
specify up differentiation (U@).
(Press SHIFT and Down Arrow to
specify down differentiation (D@).
The buzzer will sound when up
(U@) or down (D@) differentiation is
detected.
The original bit monitor display will
return when differentiation
monitoring is completed.
L000000108H2315
OFF OFF ON
Press CLR to cancel differentiation
monitoring and return to the original
bit monitor display.
D0002
0123
401
Programming Console Operations
Section 7-2
7-2-9
3-word Monitor
To monitor three consecutive words together, specify the lowest numbered
word, press MONTR, and then press EXT to display the data contents of the
specified word and the two words that follow it.
A CLR entry changes the Three-word Monitor operation to a single-word display.
Key Sequence
Single-word monitor in progress
Example
00000
00000
Specify the first of the 3 words
you want to monitor.
CHANNEL DM 0000
D0000
89AB
D0002D0001D0000
0123 4567 89AB
Press the Up and Down Arrow
keys to change word addresses.
D0003D0002D0001
ABCD 0123 4567
D0004D0003D0002
EF00 ABCD 0123
D0005D0004D0003
1111 EF00 ABCD
D0004D0003D0002
EF00 ABCD 0123
D0002
0123
7-2-10 3-word Data Modification
This operation changes the contents of a word during the 3-Word Monitor opera-
tion. The blinking square indicates where the data can be changed. After the
new data value is keyed in, pressing WRITE causes the original data to be over-
written with the new data. If CLR is pressed before WRITE, the change operation
will be cancelled and the previous 3-word Monitor operation will resume.
This operation cannot be used to change SR 253 through SR 255. Only those
words displayed on the 3-word Monitor display can be changed.
Key Sequence
3 words currently
displayed
[ Data ]
402
Programming Console Operations
Section 7-2
Example
D0002D0001D0000
0123 4567 89AB
3-word Monitor
in progress.
D0002 3CH CHG?
Stops in the middle
of monitoring.
=
0
1
2
3
4
5
6
7
8
9
A
B
D0002 3CH CHG?
0001 4567 89AB
Input new data.
D0002 3CH CHG?
0001=4567 89AB
D0002 3CH CHG?
0001=2345 89AB
D0002D0001D0000
0001 2345 89AB
Resumes previous
monitoring.
D0002D0001D0000
0123 4567 89AB
7-2-11 Binary Monitor
You can specify that the contents of a monitored word be displayed in binary by
pressing SHIFT and MONTR after the word address has been input. Words can
be successively monitored by using the up and down keys to increment and
decrement the displayed word address. To clear the binary display, press CLR.
Key Sequence
[Word]
Binary
monitor clear
All monitor
clear
(EM area)
(EM bank 0, 1, or 2.)
403
Programming Console Operations
Section 7-2
Example
00000
00000
CHANNEL
000
c000 MONTR
0000000000001111
c001 MONTR
0000010101010100
00000
CHANNEL
001
00000
00000
CHANNEL DM 0000
D0000
FFFF
D0000 MONTR
1111111111111111
D0000
FFFF
00000
CHANNEL DM 0000
0000S0100R0110SR
Indicates Force Reset
in effect
Indicates Force Set
in effect
404
Programming Console Operations
Section 7-2
7-2-12 Binary Data Modification
This operation assigns a new 16-digit binary value to an IR, HR, AR, DM, EM, or
LR word.
The cursor, which can be shifted to the left with the up key and to the right with the
down key, indicates the position of the bit that can be changed. After positioning
to the desired bit, a 0 or a 1 can then be entered as the new bit value. The bit can
also be Force Set or Force Reset by pressing SHIFT and either PLAY/SET or
REC/RESET. An S or R will then appear at that bit position. Pressing the NOT
key will clear the force status, S will change to 1, and R to 0. After a bit value has
been changed, the blinking square will appear at the next position to the right of
the changed bit.
Key Sequence
Word currently
displayed in binary.
(Force Status Clear)
405
Programming Console Operations
Section 7-2
Example
00000
00000
CHANNEL
000
001
00000
CHANNEL
c001 MONTR
0000010101010101
c001 CHG?
=
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
c001 CHG?
1
=
0
0
0
1
0
1
0
1
0
1
0
1
0
1
c001 CHG?
10=0010101010101
c001 CHG?
100=010101010101
c001 CHG?
100S=10101010101
c001 CHG?
100=010101010101
c001 CHG?
10=S010101010101
c001 CHG?
1
=
R
S
0
1
0
1
0
1
0
1
0
1
0
1
c001 MONTR
10RS010101010101
IR bit 00115
IR bit 00100
7-2-13 Changing Timer/Counter SV
There are two ways to change the SV of a timer or counter. It can be done either
by inputting a new value; or by incrementing or decrementing the current SV.
Either method can be used only in MONITOR or PROGRAM mode. In MON-
ITOR mode, the SV can be changed while the program is being executed. Incre-
menting and decrementing the SV is possible only when the SV has been en-
tered as a constant.
To use either method, first display the address of the timer or counter whose SV
is to be changed, presses the down key, and then press CHG. The new value
can then be input numerically and WRITE pressed to change the SV or EXT can
be pressed followed by the up and down keys to increment and decrement the
current SV. When the SV is incremented and/or decremented, CLR can be
pressed once to change the SV to the incremented or decremented value but
remaining in the display that appeared when EXT was pressed or CLR can be
pressed twice to return to the original display with the new SV.
This operation can be used to change a SV from designation as a constant to a
word address designation and visa verse.
406
Programming Console Operations
Section 7-2
Key Sequence
Example
The following examples show inputting a new constant, changing from a
constant to an address, and incrementing to a new constant.
Inputting New SV and
Changing to Word
Designation
00000
00000
TIM
000
000
00201SRCH
TIM
00201 TIM DATA
#0123
00201 TIM DATA
T000 #0123 #????
00201 TIM DATA
T000 #0123 #0124
00201 TIM DATA
#0124
00201 DATA?
T000 #0123 c???
00201 DATA?
T000 #0123 c010
00201 TIM DATA
010
407
Programming Console Operations
Section 7-2
Incrementing and
Decrementing
00000
00000
TIM
000
000
00201SRCH
TIM
00201 TIM DATA
#0123
00201 TIM DATA
T000 #0123 #????
00201DATA ? U/D
T000 #0123 #0123
Current SV (during
change operation)
SV before the change
00201DATA ?
T000 #0123 #0122
00201DATA ?
T000 #0123 #0123
00201DATA ?
T000 #0123 #0124
00201DATA ?
T000 #0124 #????
Returns to original display
with new SV
00201 TIM DATA
#0124
408
Programming Console Operations
Section 7-2
7-2-14 Expansion Instruction Function Code Assignments
This operation is used to read or change the function codes assigned to expan-
sion instructions. There are 18 function codes that can be assigned to expansion
instructions: 17, 18, 19, 47, 48, 60 to 69, and 87 to 89. More than one function
code can be assigned to an expansion instruction.
Note Function Code Assignments can be read in any mode, but can be changed in
PROGRAM mode only.
The function code assignments become possible only when the DIP switch pin 1
is OFF and pin 4 is ON.
Key Sequence
Example
00000
Press CLR to bring up the initial
display.
INST TBL READ
FUN17:ASFT
Press EXT to begin displaying function
code assignments.
INST TBL READ
FUN18:SCAN
Press the Up and Down Arrow keys to
scroll through the function code
assignments.
INST TBL READ
FUN17:ASFT
The Up Arrow key displays function
codes in ascending order:
17, 18, ... , 89, 17, 18, ...
The Down Arrow key displays function
codes in descending order:
17, 89, 88, ... 17, 89, ...
INST TBL READ
FUN18:SCAN
INST TBL CHG?
Press CHG to change the displayed
function code assignment.
FUN18:SCAN→????
INST TBL CHG?
Press the Up and Down Arrow keys to
scroll through the instructions.
FUN18:SCAN→MCMP
INST TBL CHG?
FUN18:SCAN→PID
INST TBL READ
FUN18:PID
Press WRITE to enter the change into
memory.
00000
Press CLR to return to the initial
display.
409
Programming Console Operations
Section 7-2
7-2-15 UM Area Allocation
This operation is used to allocate part of the UM Area for use as expansion DM. It
can be performed in PROGRAM mode only. Memory allocated to expansion DM
is deducted from the ladder program area.
The amount of memory available for the ladder program depends on the amount
of RAM in the CPU Unit. About 15.2 KW of memory is available with the16-KW
RAM and about 31.2 KW is available with the 32-KW RAM.
This operation cannot be used to allocate UM to the I/O comment area. UM can
be allocated to the I/O comment area only with a host computer equipped with
SYSMAC Support Software.
Key Sequence
B 1
D 3
PLAY
Clear memory when
changing allocation
FUN
VER
CHG
CLR
[New data]
WRITE
9
7
SET
Example
00000
Clear memory completely if the UM Area
allocation will be changed.
The current UM Area allocation will be displayed.
“??” will be displayed if the allocation information
has been lost.
DM CM LAD
VER
00 00 15.2
UMAREA CHG?
Press CHG to change the UM Area allocation.
Expansion DM can be set to 00, 01, 02, or 03 KW.
INI DM SIZ:00KW
UMAREA CHG?
INI DM SIZ:02KW
UMAREA SET: CHG
????
Enter the password by pressing PLAY/SET and
9713.
UMAREA SET: CHG
9713
The new UM Area allocation will be displayed. UM
allocated to expansion DM is deducted from the
ladder program.
DM CM LAD
02 00 13.2
00000
Press CLR to return to the initial display.
410
Programming Console Operations
Section 7-2
7-2-16 Reading and Setting the Clock
This operation is used to read or set the CPU Unit’s clock. The clock can be read
in any mode, but it can be set in MONITOR or PROGRAM mode only.
The CPU Unit will reject entries outside of the acceptable range, i.e., 01 to 12 for
the month, 01 to 31 for the day of the month, 00 to 06 for the day of the week, or
00 to 60 for the seconds, but it will not recognize non-existent dates, such as
2/31.
Example
00000
Press CLR to bring up the initial display.
0:TIM
TIM
FUN
94Ć04Ć10
The display will monitor the current date and time.
Press CHG to change the date and/or time.
14:25:58 FRI(5)
TIM CHG?94Ć04Ć10
14:25:58 FRI(5)
The “9” in “94” will blink, indicating that it can be
changed.
TIM CHG?94Ć04Ć10
14:25:58 FRI(5)
Press the Up and Down Arrow keys to move the
cursor through the data and time settings. Input
new values to change settings if necessary.
TIM CHG?94Ć04Ć10
14:25:58 FRI(5)
TIM CHG?94Ć04Ć10
14:25:50 FRI(5)
In this case, a “0” was input to replace the “8.”
0:TIM
00000
Press CLR to return to the initial display.
7-2-17 Expansion Keyboard Mapping
This operation is used to control the ON/OFF status of bits SR 27700 through
SR 27909 by pressing keys on the Programming Console’s keyboard. The
C200HX/HG/HE also supports the Keyboard Mapping operation, which controls
the status of bits in AR 22. These operations can be performed in any PC mode,
but the Programming Console must be in TERMINAL or expansion TERMINAL
mode.
411
Programming Console Operations
Section 7-2
To enable expansion keyboard mapping, pin 6 of the CPU Unit’s DIP switch and
AR 0709 must be ON and AR 0708 must be OFF.
Bits turned ON with this operation can be turned OFF by toggling AR 0708. Turn
AR 0709 OFF to stop expansion keyboard mapping and switch the Program-
ming Console from Expansion TERMINAL mode to CONSOLE mode.
TERMINAL Mode
The Programming Console can be put into TERMINAL mode by pressing CHG
or executing TERM(48) in the program. Pin 6 of the CPU Unit’s DIP switch must
be OFF.
PROGRAM
BZ
CONSOLE mode
<MESSAGE>
Switch the Programming Console to TERMINAL
mode by pressing CHG or executing TERM(48).
NO MESSAGE
PROGRAM
BZ
Press CHG again to return to CONSOLE mode.
Expansion TERMINAL Mode The Programming Console can be put into Expansion TERMINAL mode by turn-
ing ON AR 0709. Pin 6 of the CPU Unit’s DIP switch must be ON.
PROGRAM
BZ
CONSOLE mode
<MESSAGE>
Switch the Programming Console to Expansion
TERMINAL mode by turning AR 0709 ON.
NO MESSAGE
PROGRAM
BZ
Turn AR 0709 OFF to return to CONSOLE mode.
7-2-18 Keyboard Mapping
The C200HX/HG/HE supports the expansion keyboard mapping as well as nor-
mal keyboard mapping. Expansion keyboard mapping controls the status of the
41 bits SR 27700 through SR 27909, while normal keyboard mapping controls
only the 16 bits in AR 22. The status of these bits can be controlled by pressing
the corresponding Programming Console keys when the Programming Console
is in TERMINAL mode or expansion TERMINAL mode.
The following diagram shows how to switch the Programming Console between
CONSOLE mode (normal operating mode) and TERMINAL or expansion TER-
MINAL mode.
Press the CHG Key or
execute TERM(48).
Turn ON AR 0709.
TERMINAL mode
(DIP switch pin 6 OFF)
Expansion TERMINAL mode
(DIP switch pin 6 ON)
CONSOLE mode
Press the CHG key.
Turn OFF AR 0709
or turn OFF DIF switch pin 6.
TERMINAL Mode
The Programming Console can be put into TERMINAL mode by pressing CHG
or executing TERM(48) in the program. Pin 6 of the CPU Unit’s DIP switch must
be OFF.
Press the CHG key again to return to CONSOLE mode.
When the Programming Console is in TERMINAL mode it can perform normal
keyboard mapping and display messages output by MSG(46) or LMSG(47).
412
Programming Console Operations
Section 7-2
With keyboard mapping, bits 00 to 15 of AR 22 will be turned ON when keys 0 to
F are pressed on the Programming Console’s keyboard. A bit will remain ON
after the Programming Console’s key is released.
All bits in AR 22 will be turned OFF when AR 0708 is turned ON. Keyboard map-
ping inputs are disabled when AR 0708 is ON.
In addition to the keyboard mapping function, TERMINAL mode allows mes-
sages output by MSG(46) and LMSG(47) to be displayed on the Programming
Console. These messages will be erased if the Programming Console is switch
back to CONSOLE mode.
Expansion TERMINAL Mode The Programming Console can be put into Expansion TERMINAL mode by turn-
ing ON AR 0709. Pin 6 of the CPU Unit’s DIP switch must be ON.
Turn off AR 0709 or pin 6 of the CPU Unit’s DIP switch to return to CONSOLE
mode.
When the Programming Console is in TERMINAL mode it can perform expan-
sion keyboard mapping and display messages output by MSG(46) or
LMSG(47). With expansion keyboard mapping, bits SR 27700 through
SR 27909 will be turned ON when the corresponding key is pressed on the Pro-
gramming Console’s keyboard. A bit will remain ON after the Programming Con-
sole’s key is released.
All bits from SR 27700 through SR 27909 will be turned OFF when AR 0708 is
turned ON. Expansion keyboard mapping inputs are disabled when AR 0708 is
ON.
In addition to the keyboard mapping function, expansion TERMINAL mode al-
lows messages output by MSG(46) and LMSG(47) to be displayed on the Pro-
gramming Console. These messages will be erased if the Programming Con-
sole is switch back to CONSOLE mode.
The following diagram shows the correspondence between the position of Pro-
gramming Console keys and bits in the SR Area. Each key corresponds 1 to 1
with a bit. Shifted inputs are not recognized. Keys 0 to 15 correspond to bits
SR 27700 to SR 27715, keys 16 to 31 correspond to bits SR 27800 to SR 27815,
and keys 32 to 41 correspond to bits SR 27900 to SR 27909.
FUN key
0
1
2
3
4
5
6
7
8
9
10
16
22
28
34
40
11
17
23
29
35
41
12
18
24
30
36
13
19
25
31
37
14
20
26
32
38
15
21
27
33
39
The following table shows the correspondence between the actual Program-
ming Console keys and bits SR 27700 to SR 27909.
SR word
277
Bit
Corresponding key(s)
00
01
02
FUN
413
Programming Console Operations
Section 7-2
SR word
277
Bit
Corresponding key(s)
03
04
05
*1
*2
06
07
08
09
10
11
12
13
14
15
00
01
02
03
04
05
06
07
08
09
10
278
414
Programming Console Operations
Section 7-2
SR word
278
Bit
Corresponding key(s)
11
12
13
14
15
00
01
02
03
04
279
05
06
*3
07
08
09
VER
415
SECTION 8
Serial Communications
This section provides an overview of the serial communications (Host Link, RS-232C, one-to-one links, NT links, and proto-
col macros) that operate through the RS-232C, RS-422/485, and Peripheral Ports.
8-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-2 Host Link Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-2-1 Host Link Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-2-2 Host Link Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-2-3 Example Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-3 RS-232C Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-3-1 Communications Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-3-2 Communications Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-3-3 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-4 One-to-one PC Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-5 NT Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-6 The Protocol Macro Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-6-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-6-2 Communications Board Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-6-3 Communications Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-6-4 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
418
419
419
422
425
426
427
427
429
430
432
433
433
436
437
440
417
Introduction
Section 8-1
8-1 Introduction
The RS-232C port and peripheral port built into the C200HX/HG/HE PC’s CPU
Unit support the following communications functions:
• Communications with Programming Devices (e.g., Programming Console or
SSS.)
• Host Link communications with personal computers and other external de-
vices.
• RS-232C (no-protocol) communications with personal computers and other
external devices.
• One-to-one link communications with another PC.
• NT link communications (one-to-one or one-to-N) with Programmable Termi-
nals (PTs) equipped with an NT link interface.
In addition to these communications functions, optional Communications
Boards that support Protocol Macros can be installed in most C200HX/HG/HE
PCs.
The following table summarizes the communications functions.
Function
Host Link
Connected device
Connection
Summary
Related
instructions
Host computer or PT
One-to-one Provides communications between a Host Link commands,
or One-to-N host computer and PC. TXD(––)
The PC’s operating status and the
contents of data areas can be moni-
tored from the host computer.
TXD(––) can be used to transmit data
from the PC’s data areas to the host
computer.
RS-232C
(no protocol)
Host computer or
other RS-232C device
One-to-one TXD(––) and RXD(––) can be used to TXD(––), RXD(––)
manage simple data transfer se-
quences such as inputs from bar code
readers or outputs to printers.
Control signals RS, CS, ER, and DR
can be controlled by the instructions.
One-to-one Link PC
One-to-one Makes a one-to-one connection be-
tween two PCs using the LR areas of
the PCs.
---
NT Link
PT
One-to-one Provides data transfers between the
or One-to-N PC and one or more PTs.
---
Protocol Macro Other serial device
One-to-one The Protocol Macro function allows
or One-to-N the user to define separate data trans-
fer sequences and transfer mes-
sages.
PMCR(––)
Up to 1,000 communications se-
quences can be registered.
A support program is provided that
simplifies creation of communications
sequences.
418
Host Link Communications
Section 8-2
8-2 Host Link Communications
8-2-1 Host Link Command Summary
Host Link communications are used to transfer data between the PC and a host
computer (a personal computer or PT). It is possible to monitor the PC’s operat-
ing status and the contents of PC data areas from the host computer using Host
Link commands. It is also possible to transfer data from the PC’s IOM data areas
(IR area, SR area, LR area, HR area, AR area, timer and counter PVs, DM 0000
through DM 6143, and EM 0000 through EM 6143) to a host computer using the
TXD(––) instruction in the ladder program.
RS-232C Connections (1-to-1) Only one PC can be connected with the host computer (one-to-one connection)
when the Host Link is made with RS-232C connections.
Host Link
Host Link
Host
computer
Host
link
IBM PC/AT or compatible
RS-422/485 Connections
(1-to-N)
Up to 32 PCs can be connected with the host computer (one-to-N connection)
when the Host Link is made with RS-422/485 connections.
See
note
Host link
IBM PC/AT or compatible
See
note
See
note
See
note
32 PCs max.
Note: RS-232C ↔ RS-422/485 Adapter
Wiring Ports
Use the wiring diagram shown below as a guide in wiring the port to the external
device. Refer to documentation provided with the computer or other external de-
vice for wire details for it.
419
Host Link Communications
Section 8-2
The connections between the C200HX/HG/HE and a personal computer are il-
lustrated below as an example.
C200HX/HG/HE
Personal computer
Signal
Pin
No.
Pin
No.
Signal
–
FG
SD
RD
RS
CS
–
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
RD
SD
DTR
SG
DSR
RS
–
CS
–
SG
–
Shielded cable
Applicable Connectors
The following connectors are applicable. One plug and one hood are included
with the CPU Unit.
Plug: XM2D-0901 (female) for IBM PC/AT or compatible (OMRON)
or equivalent
Hood: XM2S-0911 (OMRON) or equivalent
Note Ground the FG terminal on the PC and at the computer to 100 Ω or less. Refer to
the C200HX/HG/HE Installation Manual and to the documentation for your com-
puter for details.
Host Link Parameters
The following parameters in the PC Setup must be set in advance to enable Host
Link communications.
Communications Mode
Set the communications mode to Host Link mode. (This is the default setting.)
RS-232C port: Set bits 12 through 15 of DM 6645 to 0.
Peripheral port: Set bits 12 through 15 of DM 6650 to 0.
Node Number Setting
When 1:N connections are being used, set a unique node number from 00 to 31.
When a 1:1 connection is being used, set the PC’s node number to 00.
RS-232C port: Set bits 00 through 07 of DM 6648 (00 to 31).
Peripheral port: Set bits 00 through 07 of DM 6653 (00 to 31).
Standard Port Settings
Standard settings or custom settings can be used for the RS-232C and peripher-
al ports. The standard settings are used when the following bits are set to 0.
(The custom settings are explained below.)
RS-232C port: Bits 00 through 03 of DM 6645 (0: standard; 1: custom).
Peripheral port: Bits 00 through 03 of DM 6650 (0: standard; 1: custom).
The standard settings are shown in the following table.
Item
Setting
Start bits
1
Data length
Stop bits
Parity
7
2
Even
Baud rate
9,600 bps
420
Host Link Communications
Section 8-2
Custom Port Settings
Standard settings or custom settings can be used for the RS-232C and peripher-
al ports. The custom settings are used when the following bits are set to 1.
RS-232C port: Bits 00 through 03 of DM 6645 (0: standard; 1: custom).
Peripheral port: Bits 00 through 03 of DM 6650 (0: standard; 1: custom).
The custom settings for the RS-232C port are defined in DM 6646 and the cus-
tom settings for the peripheral port are defined in DM 6651.
The following settings are valid only when pin 5 on the CPU Unit’s DIP switch is
turned OFF. Be sure to set the communications parameters to the same settings
for both ends of the communications.
Bit
15
0
DM 6646:RS-232C port
DM 6651:Peripheral port
Transmission Frame Format (See table below.)
Baud rate (See table below.)
Parameter
Setting Start bits Data length Stop bits
Parity
Even
Transmission Frame
Format
00
01
02
03
04
05
06
07
08
09
10
11
1
1
1
1
1
1
1
1
1
1
1
1
7
7
7
7
7
7
8
8
8
8
8
8
1
1
1
2
2
2
1
1
1
2
2
2
Odd
None
Even
Odd
None
Even
Odd
None
Even
Odd
None
Parameter
Setting
Baud rate
Baud rate
00
01
02
03
04
1,200 bps
2,400 bps
4,800 bps
9,600 bps
19,200 bps
Transmission Delay Time
Depending on the devices connected to the RS-232C port, it may be necessary
to allow time for transmission. When that is the case, set the transmission delay
to regulate the amount of time allowed. The transmission delay time is set in
units of 10 ms.
RS-232C port: Set DM 6647 from 0000 to 9999 (0 to 99.99 s delay).
Peripheral port: Set DM 6652 from 0000 to 9999 (0 to 99.99 s delay).
421
Host Link Communications
Section 8-2
Note If pin 5 of the CPU Unit’s DIP switch is ON, the standard communications set-
tings will be used regardless of the settings in the PC Setup. The standard set-
tings are as follows:
Item
Node number
Start bits
Setting
00
1
Data length
Stop bits
7
2
Parity
Even
Baud rate
9,600 bps
Transmission delay time None
8-2-2 Host Link Communications
Host link communications are executed by means an exchange of commands
and responses between the host computer and the PC. The command or re-
sponse data that is transferred in one exchange is known as a frame and one
frame can contain up to 131 characters of data.
The frame formats for Host Link commands transmitted from the host computer
and responses returned from the PC are described below. The PC automatically
returns an ASCII-code response when it receives an ASCII-code command
from the host computer. The host computer must have a program that controls
the transmission and reception of the commands and responses.
Command Frame Format
When transmitting a command from the host computer, prepare the command
data in the format shown below.
1
0
x 10 x 10
@
ꢀ
↵
Node no.
Header
code
Text
FCS
Terminator
The header code and text depend on the Host Link command being transmitted.
When a composite command is transmitted, there will be a second sub-header
code.
The FCS (Frame Check Sequence) code is calculated at the host computer and
set in the command frame. The FCS calculation is described later in this section.
The command frame may be up to 131 characters long. A command of 132 char-
acters or more must be divided into more than one frame. To split the command,
use a carriage return delimiter (↵, CHR$(13)) instead of a terminator. A termina-
tor must be used at the end of the last frame.
When dividing commands such as WR, WL, WC, or WD that execute write op-
erations, be careful not to divide into separate frames data that is to be written
into a single word. Be sure to divide frames so that they coincide with the divi-
sions between words.
Item
Function
@
An “@” symbol must be placed at the beginning of every command.
Identify the PC by the node number set in DM 6648 of the PC Setup.
Node no.
Header code Set the 2-character command code.
Text
Set the command parameters.
FCS
Set a 2-character Frame Check Sequence code.
Terminator
Set two characters, “ꢀ” and the carriage return (CHR$(13)) to
indicate the end of the command.
422
Host Link Communications
Section 8-2
Response Frame Format
The response from the PC is returned in the format shown below. Prepare a pro-
gram so that the response data can be interpreted and processed.
1
0
1
0
x 10 x 10
x 16 x 16
@
ꢀ
↵
Node no.
Header
code
End code
Text
FCS
Terminator
The header code and text depend on the Host Link command that was received.
The end code indicates the completion status of the command (e.g., whether or
not an error has occurred).
When the response is longer than 131 characters, it will be divided into more
than one frame. A carriage return delimiter (↵, CHR$(13)) instead of a terminator
will automatically be set at the end of the frame. A terminator will be set at the end
of the last frame.
Item
Node no.
Function
@
An “@” symbol is placed at the beginning of every response.
The PC’s node number set in DM 6648 of the PC Setup.
Header code The 2-character command code is returned.
Text
The results of the command are returned.
FCS
The 2-character Frame Check Sequence code is returned.
Terminator
Two characters, “ꢀ” and the carriage return (CHR$(13)) indicate the
end of the response.
FCS (Frame Check Sequence) When a frame is transmitted, an FCS code is placed just before the delimiter or
terminator in order to check whether an error has occurred in the transmission.
The FCS is 8-bit data converted into two ASCII characters. The 8-bit data is the
result of an EXCLUSIVE OR performed on the data from the beginning of the
frame until the end of the text in that frame (i.e., just before the FCS). Calculating
the FCS each time a frame is received and checking the result against the FCS
that is included in the frame makes it possible to check for data errors in the
frame.
@
1
0
R
R
0
0
0
1
4
2
ꢀ
↵
Header code
FCS calculation range
Text
FCS
Terminator
Node no.
ASCII code
@
1
40
31
30
52
0100
EOR
0011
EOR
0011
EOR
0000
0001
0000
0010
0
R
0101
1
31
0011
0100
i
4
0001
0010
i
2
Calculation
result
Converted to hexadecimal.
Handled as ASCII characters.
423
Host Link Communications
Section 8-2
Communications Sequence The right to send a frame is called the “transmission right.” The Unit that has the
transmission right is the one that can send a frame at any given time. The trans-
mission right is traded back and forth between the host computer and the PC
each time a frame is transmitted. An example communications sequence be-
tween the host computer and PC is described below.
• The host computer sets a delimiter at the end of the first command frame and
transmits the frame.
• When the PC receives the delimiter, it returns the same delimiter to the host
computer.
• After receiving the delimiter from the PC, the host computer transmits the next
frame.
• The PC sets a delimiter at the end of the first response frame and transmits the
frame.
• When the host computer receives the delimiter, it returns the same delimiter to
the PC.
• After receiving the delimiter from the host computer, the PC transmits the next
frame.
• Long transmissions are managed by exchanging delimiters in this way. The
last frame ends with a terminator.
Frame2 (command)
Frame3 (command)
Frame1 (command)
@ Unit No.
Header code
Host com-
puter
Text
Text
Text
FCS
FCS
FCS
Delimiter
Delimiter
Terminator
Delimiter
Delimiter
@ Unit No.
Header code
End code
PC
Text
FCS
Terminator
Frame (response)
Using the TXD(––) Instruction The TXD(––) instruction can be used to transmit data from the PC’s data area to
the host computer. There is no response from the host computer. The TXD(––)
instruction will be executed after the response has been transmitted if TXD(––)
is executed while a response to a Host Link command is being returned to the
host computer.
Host computer
No response
@ Unit No.
Header code
PC
Text
FCS
Terminator
424
Host Link Communications
Section 8-2
8-2-3 Example Programs
Command Transmission
The following type of program must be prepared in the host computer to receive
the data. This program allows the computer to read and display the data re-
ceived from the PC while a host link read command is being executed to read
data from the PC.
10 ’C200HX/HG/HE SAMPLE PROGRAM FOR EXCEPTION
20 CLOSE
30 CLS
40 OPEN ”COM:E73” AS #1
50 ꢀKEYIN
60 INPUT ”DATA ––––––––”,S$
70 IF S$=” ” THEN GOTO 190
80 PRINT ”SEND DATA = ”;S$
90 ST$=S$
100 INPUT ”SEND OK? Y or N?=”,B$
110 IF B$=”Y” THEN GOTO 130 ELSE GOTO ꢀKEYIN
120 S$=ST$
130 PRINT #1,S$
140 INPUT #1,R$
’Sends command to PC
’Receives response from PC
150 PRINT ”RECV DATA = ”;R$
160 IF MID$(R$,4,2)=”EX” THEN GOTO 210 ’Identifies command from PC
170 IF RIGHT$(R$,1)<>”ꢀ” THEN S$=” ”:GOTO 130
180 GOTO ꢀKEYIN
190 CLOSE 1
200 END
210 PRINT ”EXCEPTION!! DATA”
220 GOTO 140
Example Program for FCS
This example shows a BASIC subroutine program for executing an FCS check
on a frame received by the host computer.
400 *FCSCHECK
410 L=LEN(RESPONSE$) ’ .......... Data transmitted and received
420 Q=0:FCSCK$=” ”
430 A$=RIGHT$(RESPONSE$,1)
440 PRINT RESPONSE$,AS,L
450 IF A$=”*” THEN LENGS=LEN(RESPONSE$)-3
ELSE LENGS=LEN(RESPONSE$)-2
460 FCSP$=MID$(RESPONSE$,LENGS+1,2) ’ ... FCS data received
470 FOR I=1 TO LENGS ’ .......... Number of characters in FCS
480 Q=ASC(MID$(RESPONSE$,I,1)) XOR Q
490 NEXT I
500 FCSD$=HEX$(Q)
510 IF LEN(FCSD$)=1 THEN FCSD$=”0”+FCSD$ ’FCS result
520 IF FCSD$<>FCSP$ THEN FCSCK$=”ERR”
530 PRINT”FCSD$=”;FCSD$,”FCSP$=”;FCSP$,”FCSCK$=”;FCSCK$
540 RETURN
Note 1. Normal reception data includes the FCS, delimiter or terminator, and so on.
When an error occurs in transmission, however the FCS or some other data
may not be included. Be sure to program the system to cover this possibility.
2. In this program example, the CR code (CHR$(13)) is not entered for RE-
SPONSE$. When including the CR code, make the changes in lines 430
and 450.
TXD(––) Application Example This example shows a program for using the RS-232C port in the Host Link
mode to transmit 10 bytes of data (DM 0000 to DM 0004) to a computer. From
DM 0000 to DM 0004, “1234” is stored in every word.
425
RS-232C Communications
Section 8-3
The default values are assumed for all of the PC Setup (i.e., the RS-232C port is
used in Host Link mode, the node number is 00, and the standard communica-
tions parameters are used.)
00100SR 26405
@TXD
If SR 26405 (the Transmit Ready Flag) is ON
when IR 00100 turns ON, the ten bytes of
data (DM 0000 to DM 0004) will be trans-
DM 0000
#0000
#0010
mitted.
8-3 RS-232C Communications
This section explains RS-232C communications. The TXD(––) and RXD(––)
instructions can be used with RS-232C communications to output data to a print-
er, input data from a bar code reader or transmit Host Link commands to other
devices equipped with an RS-232C port.
RS-232C Connection
The following diagram shows the RS-232C connection when the RS-232C port
is used in RS-232C mode (no protocol).
Device
equipped with
RS-232C mode
an RS-232C
port
PC Setup Parameters
The following parameters in the PC Setup must be set in advance to enable
RS-232C mode communications through the RS-232C or peripheral ports.
Communications Mode
Set the communications mode to RS-232C mode.
RS-232C port: Set bits 12 through 15 of DM 6645 to 1.
Peripheral port: Set bits 12 through 15 of DM 6650 to 1.
Standard Port Settings
Standard settings or custom settings can be used for the RS-232C and peripher-
al ports. Refer to page 420 for details on the standard communications settings.
Custom Port Settings
Standard settings or custom settings can be used for the RS-232C and peripher-
al ports. Refer to page 421 for details on custom communications settings.
Enabling Start and End Codes
Bit
15
0
DM 6648:RS-232C port
DM 6653:Peripheral port
0
0
End code usage
0: Not set (Amount of reception data specified.)
1: Set (End code specified.)
2: CR/LF
Start code usage
0: Not set
1: Set (Start code specified.)
Defaults: No start code; data reception complete at 256 bytes.
426
RS-232C Communications
Section 8-3
Specify whether or not a start code is to be set at the beginning of the data, and
whether or not an end code is to be set at the end. Instead of setting the end
code, it is possible to specify the number of bytes to be received before the re-
ception operation is completed. Both the codes and the number of bytes of data
to be received are set in DM 6649 or DM 6654.
Setting the Start Code, End Code, and Amount of Reception Data
Bit
15
0
DM 6649:RS-232C port
DM 6654:Peripheral port
End code or number of bytes to be received
For end code: (00 to FF)
For amount of reception data: 2 digits hexadecimal, 00 to FF (00: 256 bytes)
Start code 00 to FF
Defaults: No start code; data reception complete at 256 bytes.
8-3-1 Communications Frame Structure
Up to 259 bytes of data (including the start and end codes) can be transferred
with the execution of one TXD(––) or RXD(––) instruction. When there are two or
more start codes, the first start code will be used. Likewise, when there are two
or more end codes, the first end code will be used.
Avoid using commonly occurring characters for the end code. Use CR and LF for
the end code if data transmissions are being cut short because the end code is
occurring within the body of the transmission data.
• No start code and end code
Data (specified number of bytes)
• Start code only
ST
Data (specified number of bytes)
• End code only
Data (256 bytes or less)
ED
ED
• Both start code and end code
ST
Data (257 bytes or less)
• CR, LF specified for the end code
Data (258 bytes or less)
CR LF
CR LF
• Both start code (00 to FF) and end code (CR, LF)
ST
Data (259 bytes or less)
8-3-2 Communications Procedure
Brief descriptions of the TXD(––) and RXD(––) are provided below.
Transmission (TXD(––))
Refer to 5-27-2 TRANSMIT – TXD(––) for more details. Always include the spe-
cified port’s Transmit Ready Flag as an execution condition for TXD(––) to en-
sure that this Flag is ON before the transmission can be executed.
1, 2, 3...
1. Check to see that SR 26405 (RS-232C Port Transmit Ready Flag), SR
26413 (Peripheral Port Transmit Ready Flag), SR 28305 (Communications
Board Port A Transmit Ready Flag), or SR 28313 (Communications Board
Port B Transmit Ready Flag) is ON.
427
RS-232C Communications
Section 8-3
2. Use the TXD(––) instruction to transmit the data. (Bits 08 to 11 are valid only
when bits 12 to 15 are set to 0.)
(@)TXD
S: Address of first word of data to be transmitted
S
C: Control data
Bits 00 to 03
C
0: Leftmost bytes first
1: Rightmost bytes first
Bits 04 to 07
N
0: Normal data transmission operation
1: Status of bit 15 for the leftmost word of
the transmission data is reflected on the
RTS of the corresponding port.
2: Status of bit 15 for the leftmost word of
the transmission data is reflected on the
DTR of the corresponding port.
3: Statuses of bits 14 and 15 for the
leftmost word of the transmission data are
reflected on the RTS and DTR of the
corresponding port.
Bits 08 to 11
0: Built-in RS-232C port
1: Communications Board port A
2: Communications Board port B
Bits 12 to 15
0: RS-232C port
1: Peripheral port
2: Host Link Unit #1
3: Host Link Unit #2
N: Number of bytes to be transmitted (4 digits BCD), 0000 to
0256 (start and end bits)
3. From the time this instruction is executed until the data transmission is com-
plete, the Transmit Ready Flag (SR 26405, SR 26413, SR 28305, or
SR 28313) will remain OFF. It will turn ON again upon completion of the data
transmission.
Reception (RXD(––))
Refer to 5-27-1 RECEIVE – RXD(––) for more details.
1, 2, 3...
1. Check to see that SR 26406 (RS-232C Port Reception Completed Flag) or
SR 26414 (Peripheral Port Reception Completed Flag) is ON.
2. Use the RXD(––) instruction to receive the data. (Bits 08 to 11 are valid only
when bits 12 to 15 are set to 0.)
(@)RXD
D: Leading word no. for storing reception data
D
C: Control data
C
Bits 00 to 03
0: Leftmost bytes first
N
1: Rightmost bytes first
Bits 04 to 07
0: Normal data reception operation
1: Reads the status of CTS of the
corresponding port into bit 15 for the
leftmost word of the reception data write.
2: Reads the status of DSR of the
corresponding port into bit 15 for the
leftmost word of the reception data write.
3: Reads the statuses of CTS and DSR of
the corresponding port into bits 14 and 15
for the leftmost word of the reception data
write.
Bits 08 to 11
0: Built-in RS-232C port
1: Communications Board port A
2: Communications Board port B
Bits 12 to 15
0: RS-232C port
1: Peripheral port
N: Number of bytes stored (4 digits BCD), 0000 to 0256 (start
and end bits)
428
RS-232C Communications
Section 8-3
3. When RXD(––) is executed, the received data is transferred to the specified
words (without the start and end codes) and the Reception Completed Flag
is turned OFF. The start and end of reception are as follows:
Start: Continuous reception status if the start code is not enabled.
Reception starts when the start code is received if it is enabled.
End:
Reception ends when the end code is received or 259 bytes of data
have been received.
4. The status resulting from reading the data received will be stored in the SR
Area. Check to see that the operation was successfully completed. The con-
tents of these bits will be reset each time RXD(––) is executed.
RS-232C
Peripheral
Error
SR 26400 to SR 26408 to Communications port error code (1 digit BCD)
SR 26403
SR 26411
0: Normal completion
1: Parity error
2: Framing error
3: Overrun error
SR 26404
SR 26407
SR 26412
SR 26415
Communications Error Flag
Reception Overrun Flag (After reception was
completed, the subsequent data was received
before the data was read by means of the RXD
instruction.)
SR 265
SR 266
Number of bytes received (not including start
and end bits)
Note To reset the RS-232C port (i.e., to restore the initial status), turn ON SR 25209.
To reset the Communications Board port A, turn ON SR 28900. To reset the
Communications Board port B, turn ON SR 28901. These bits will turn OFF auto-
matically after the reset.
8-3-3 Application Example
This example shows a program for using the RS-232C port in the RS-232C
mode to transmit 10 bytes of data (DM 0100 to DM 0104) to the computer, and to
store the data received from the computer in the DM area beginning with
DM 0200. Before executing the program, the following PC Setup settings must
be made.
DM 6645:
DM 6648:
1000 (RS-232C port in RS-232C mode; standard settings)
2000 (No start code; end code CR/LF)
The default values are assumed for all other PC Setup settings. The host com-
puter must have the same communications settings and a program to receive
the data transmitted from the PC.
The data 3454 is stored in each word from DM 0100 to DM 0104.
00100
DIFU(13)
@TXD
00101
00101SR 26405
If SR 26405 (the Transmit Ready Flag) is ON
when IR 00100 turns ON, the ten bytes of data
(DM 0100 to DM 0104) will be transmitted, left-
most bytes first.
DM 0100
#0000
#0010
SR 26406
@RXD
When SR 26406 (Reception Completed Flag)
goes ON, the number of bytes of data specified in
SR 265 will be read from the PC’s reception buff-
er and stored in memory starting at DM 0200, left-
most bytes first.
DM 0200
#0000
#0256
The data will be as follows:
“34543454345434543454CR LF”
429
One-to-one PC Links
Section 8-4
8-4 One-to-one PC Links
If two PCs are linked one-to-one by connecting them together through their
RS-232C ports, they can share common LR areas. When two PCs are linked
one-to-one, one of them will serve as the master and the other as the slave.
As shown in the diagram below, when data is written into a word the LR area of
one of the linked Units, it will automatically be written identically into the same
word of the other Unit. Each PC has specified words to which it can write and
specified words that are written to by the other PC. Each can read, but cannot
write, the words written by the other PC.
CPU PS
CPU PS
C200HX/HG/HE
C200HX/HG/HE
Slave
Master
1
Master area
Slave area
Write “1”
Master area
Written automatically.
1
1
Write Slave area
Wiring
Wire the cable as shown in the diagram below using the connector listed.
Applicable Connectors
The following connectors are applicable. One plug and one hood are included
with the CPU Unit. The same connectors can be used for both ends of the cable.
Plug: XM2A-0901 (OMRON) or equivalent
Hood: XM2S-0911 (OMRON) or equivalent
C200HX/HG/HE
C200HX/HG/HE, C200HS, or CQM1
Signal
Abb.
Pin
No.
Pin
No.
Signal
Abb.
FG
SD
RD
RS
CS
–
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
FG
SD
RD
RS
CS
–
–
–
–
–
SG
SG
Note Ground the FG terminal of the PC to a resistance of 100 Ω or less.
430
One-to-one PC Links
Section 8-4
PC Setup
To use a 1:1 link, the only settings necessary are the communications mode and
the link words.
Set the communications mode for one of the PCs to one-to-one link master and
the other PC to one-to-one link slave, and then set the link words in the PC desig-
nated as the master. Bits 08 to 11 are valid only for the master for link one-to-one.
Bit
15
0
DM 6645:RS-232C port
Communications mode
2: One-to-one link slave
3: One-to-one link master
Link words for one-to-one link
0: LR 00 to LR 63
1: LR 00 to LR 31
2: LR 00 to LR 15
Port settings
00: Standard communication parameters
The word used by each PC will be as shown in the following table, according to
the settings for the master, slave, and link words.
DM 6645 setting
Master words
Slave words
LR 00 to LR 63
LR00 to LR31
LR32 to LR63
LR 00 to LR 31
LR00 to LR15
LR16 to LR31
LR 00 to LR 15
LR00 to LR07
LR08 to LR15
Communications Procedure If the settings for the master and the slave are made correctly, then the one-to-
one link will start up automatically when the PCs are turned on.
Application Example
This example shows a program for verifying the conditions for executing a one-
to-one link using the RS-232C ports. Before executing the program, set the fol-
lowing PC Setup parameters.
Master: DM 6645: 3200 (one-to-one link master; link words: LR 00 to LR 15)
Slave: DM 6645: 2000 (one-to-one link slave)
When the following programs are executed in the master and the slave, the sta-
tus of IR 001 of each Unit will be reflected in IR 100 of the other Unit. IR 001 is an
input word and IR 100 is an output word.
In the Master
25313 (Always ON)
MOV(21)
001
LR00
MOV(21)
LR08
100
In the Slave
25313 (Always ON)
MOV(21)
001
LR08
MOV(21)
LR00
100
431
NT Links
Section 8-5
8-5 NT Links
A one-to-one NT link that uses NT link commands can be established by con-
necting the RS-232C port of the PC to the RS-232C port of a Programmable Ter-
minal (PT).
A one-to-N NT link that uses NT link commands can be established by connect-
ing the PC and Programmable Terminal (PT) with RS-422/485 cable.
One-to-one NT Links
One-to-N NT Links
The following diagram shows the connections for a one-to-one NT link.
PT
The following diagram shows the connections for a one-to-N NT link. Up to 8
Programmable Terminals can be connected unless the PC is a C200HE-
CPU
j
j
-
E
.
W
i
t
h
a
C
2
0
0
H
E
-
C
P
U
j
j
-
E
,
u
p
t
o
4
P
r
o
g
r
a
m
m
a
b
l
e
T
e
r
m
i
n
a
l
s
c
a
n
be connected (including connections through a Communications Board).
See
1:N NT link
note
RS-422/485
Note: RS-232C ↔ RS-422/485 Adapter
The following table shows the maximum number of PTs that can be connected to
each port.
PC
RS-232C port
Communications Communications
port A port B
C200HE
C200HX/HG
4
8
4
8
4
8
PC Setup
Make the following settings when establishing an NT link.
Link
Port
Setting
Set bits 12 to 15 of DM 6645 to 4.
One-to-one
Built-in RS-232C port
Communications Board port B Set bits 12 to 15 of DM 6550 to 4.
Communications Board port A Set bits 12 to 15 of DM 6555 to 4.
One-to-N
Built-in RS-232C port
Set bits 12 to 15 of DM 6645 to 5.
Set the max. node number (1 to 7) in
bits 08 to 11 of DM 6545 (1 to 3 for
the C200HE).
Communications Board port B Set bits 12 to 15 of DM 6550 to 5.
Set the max. node number (1 to 7) in
bits 08 to 11 of DM 6550 (1 to 3 for
the C200HE).
Communications Board port A Set bits 12 to 15 of DM 6555 to 5.
Set the max. node number (1 to 7) in
bits 08 to 11 of DM 6555 (1 to 3 for
the C200HE).
432
The Protocol Macro Function
Section 8-6
Restrictions on Use
If the C200H-OV001 Voice Unit is being used, the 1:N mode cannot be used with
the RS-232 port. In that case, either use the NT Link in 1:1 mode or use the 1:N
mode with the port on the communications board.
Applications
Refer to the documentation provided for the NT Link Interface Unit for details on
actual NT link applications.
8-6 The Protocol Macro Function
This section explains how to use the Protocol Macro function.
8-6-1 Introduction
The Protocol Macro function is a communications protocol that controls data
transfers with various communications devices and general-purpose compo-
nents equipped with RS-232C or RS-422/485 ports. The user can easily modify
the data transfer procedures (communications sequences) with OMRON’s Pro-
tocol Support Software and execute the communications sequences from the
ladder program with PMCR(––).
The Communications Boards come equipped with seven communications pro-
cedures. These standard sequences can be used as is or modified to meet the
requirements of a particular application.
Note Refer to the Communications Board Operation Manual for details on Commu-
nications Boards and the Protocol Support Software Operation Manual for de-
tails on the Protocol Support Software.
RS-232C Connection
(One-to-one)
Only one device can be connected with an RS-232C connection. The RS-232C
cable can be up to 15 m long.
(RS-232C)
Basic protocol
RS-232C
Port B
(RS-232C)
Port A
Basic protocol
15 m
15 m
Device with an
RS-232C interface
RS-232C
Device with an
RS-232C interface
433
The Protocol Macro Function
Section 8-6
RS-422/485 Connection
(One-to-N)
An RS-422/485 connection allows 2 or more devices to be connected (one-to-N
connection) with a maximum cable length of 500 m. The RS-422/485 connection
is also useful for distant one-to-one connections.
RS-232C ↔ RS-422/485 Adapter
(RS-232C)
Port B
(RS-422/485)
Port A
RS-232C
RS-422/485
Conversion
Adapter
15 m
NT-AL001
Temperature Controller with
RS-422/485 communications
Temperature Controller with
RS-422/485 communications
Temperature Controller with
RS-422/485 communications
Temperature Controller with
RS-422/485 communications
Temperature Controller with
RS-422/485 communications
Temperature Controller with
RS-422/485 communications
Temperature Controller with
RS-422/485 communications
RS-422/485
Temperature Controller with
RS-422/485 communications
500 m max.
500 m max.
Connection Cable Wiring
The following diagrams show the cable wiring used with Protocol Macro function
communications.
RS-422/485 Adapter Connection (NT-AL001)
C200HX/HG/HE
AL001
434
The Protocol Macro Function
Section 8-6
General Device/Computer Connections (RS/CS Flow, Cross Connection)
Host computer
C200HX/HG/HE
Modem Connection (Straight Connection)
C200HX/HG/HE
Modem
Note Ground the FG terminals on the PC and at the other device to 100 Ω or less.
Refer to the C200HX/HG/HE Installation Manual and the documentation in-
cluded with the other device for details.
435
The Protocol Macro Function
Section 8-6
8-6-2 Communications Board Settings
The following parameters must be set in advance in order to use the Protocol
Macro function through a Communications Board.
Communications Mode
Set the communications mode to Protocol Macro mode.
Port B: Set bits 12 through 15 of DM 6550 to 6.
Port A: Set bits 12 through 15 of DM 6555 to 6.
Standard Port Settings
Standard settings or custom settings can be used for ports A and B. The stan-
dard settings are used when the following bits are set to 0.
Port B: Bits 00 through 03 of DM 6550 (0: standard; 1: custom).
Port A: Bits 00 through 03 of DM 6555 (0: standard; 1: custom).
The standard settings are shown in the following table.
Item
Setting
Start bits
1
Data length
Stop bits
Parity
7
2
Even
Baud rate
9,600 bps
Custom Port Settings
Standard settings or custom settings can be used for ports A and B. The custom
settings are used when the following bits are set to 1.
Port B: Bits 00 through 03 of DM 6550 (0: standard; 1: custom).
Port A: Bits 00 through 03 of DM 6555 (0: standard; 1: custom).
The custom settings for Port B are defined in DM 6551 and the custom settings
for the Port A are defined in DM 6556.
Bit
15
0
DM 6551:Port B
DM 6556:Port A
Transmission Frame Format (See table below.)
Baud rate (See table below.)
Parameter
Setting Start bits Data length Stop bits
Parity
Even
Transmission Frame
Format
00
01
02
03
04
05
06
07
08
09
10
11
1
1
1
1
1
1
1
1
1
1
1
1
7
7
7
7
7
7
8
8
8
8
8
8
1
1
1
2
2
2
1
1
1
2
2
2
Odd
None
Even
Odd
None
Even
Odd
None
Even
Odd
None
436
The Protocol Macro Function
Section 8-6
Parameter
Baud rate
Setting
00
Baud rate
1,200 bps
2,400 bps
4,800 bps
9,600 bps
19,200 bps
01
02
03
04
8-6-3 Communications Procedure
The Protocol Macro’s communications sequences must be created with the Pro-
tocol Support Software and transferred to the Communications Board in ad-
vance. In the PC, the PMCR(––) instruction is executed to execute a commu-
nications sequence stored in the Communications Board.
Communications Sequence Up to 1,000 communications sequences with sequence numbers 000 to 999 can
Structure
be created with the Protocol Support Software. Each communications se-
quence is composed of a maximum of 16 steps. The following table shows the
communications sequence settings.
Item
Function
Parameter settings
Sequence
settings
Transmission control
Sets the transmission control method,
such as X-on/X-off flow control or RS/
CS flow control.
X-on/X-off, RS/CS, modem control, de-
limiter control, or contention control
Link words
Sets the link words for the data link be- IR/SR, LR, HR, AR, DM, and EM areas
tween the PC and Communications
Board.
Monitor time
Sets the monitor time (watchdog timer) Reception standby, reception com-
for communications processing.
pleted, transmission completed
0.01 s, 0.1 s, 1 s, and 1 minute units
Response notification
Repeat counter
Sets the timing for writing the received Scan notification or interrupt notification
data.
Step
settings
Sets the number of times to repeat the Constant 0 to 255
step.
IR/SR, LR, HR, AR, DM, and EM areas
Command
Sets the communications command.
Send, Recv, or Send&Recv
Number of retries
Sets the number of retries when errors 0 to 9
occur for the Send&Recv command.
Transmission wait time Sets the time to wait before sending
the data when transmitting
0.01 s, 0.1 s, 1 s, and 1 minute units
Transmission message Sets the transmission data for the Send Header, address, length, data, error
or Send&Recv commands.
check code, and terminator
Reception message
Reception matrix
Sets the expected reception data for
the Recv or Send&Recv commands.
Header, address, length, data, error
check code, and terminator
Sets the expected reception data (up to Header, address, length, data, error
15 types) for the Recv or Send&Recv check code, terminator, and next pro-
commands and adjusts processing de- cess
pending on the data type.
Response notification
Next process
Sets whether or not to write the re-
ceived data.
Yes/No
End, Goto, Next, or Abort
Sets the next step to go to when the
current step has been completed suc-
cessfully.
Error processing
Sets the next step to go to when an er- End, Goto, Next, or Abort
ror has occurred in the current step.
437
The Protocol Macro Function
Section 8-6
Transmission/Reception
Message Structure
The transmission message and reception message have the following struc-
ture.
Header Address Length
Data
Error check Terminator
Item
Function
Header
Set the data that indicates the beginning of the message.
Address
Set the node number or other identifier that indicates the
destination for the message.
Length
Data
The data length (number of bytes) is added automatically.
Set the message contents.
Error check code Set SUM, LRC, or CRC as the error check code. The specified
error check code will be added automatically when transmitting.
When receiving, error control will be performed automatically
based on the error check code specified in the message and
the specified amount (length) of data will be received.
Terminator
Set the data that indicates the end of the message.
The following attributes can be set for each item in the transmission or reception
message. The abbreviation “R M” stands for reception message and “T M”
stands for transmission message.
Header
Address
Length
Data
Error check Terminator
Data attribute
T M R M T M R M T M R M T M R M T M
R M
---
T M
R M
Constant
ASCII
Yes Yes Yes Yes ---
---
Yes Yes ---
Yes
Yes
“
j
j
j
j
”
HEX
[
j
j
j
j
]
Special characters
CR, STX, etc.
Yes Yes ---
---
---
---
---
Yes Yes ---
Yes Yes ---
---
---
Yes
---
Yes
---
No variable
conversion
First-order equation
using variable (N)
---
---
Yes Yes ---
Wild card (ꢀ)
---
---
---
---
---
---
---
---
---
Yes ---
---
---
---
---
Yes Yes ---
--- Yes ---
Yes ---
---
---
---
---
---
---
---
---
---
---
---
---
Read word (R)
Write word (W)
Yes Yes ---
---
---
Yes ---
Automatic variable:
LNG
---
Yes Yes ---
---
---
Automatic variable:
SUM, LRC, and CRC
---
---
---
---
---
---
---
---
---
---
---
Yes
Yes
---
---
---
---
---
Variable
ASC
First-order equation
using variable (N)
Yes Yes ---
Yes Yes ---
conversion
Wild card (ꢀ)
---
---
---
---
---
---
---
---
---
Yes ---
---
---
---
---
Yes ---
---
---
---
---
---
---
---
---
---
---
---
---
Read word (R)
Write word (W)
Yes Yes ---
Yes Yes ---
---
---
Yes ---
---
---
Yes ---
Automatic variable:
LNG
---
Yes ---
---
---
Automatic variable:
SUM, LRC, and CRC
---
---
---
---
---
---
---
---
---
---
---
Yes
---
---
---
---
---
---
Variable
HEX
First-order equation
using variable (N)
Yes Yes ---
Yes Yes ---
conversion
Wild card (ꢀ)
---
---
---
---
---
---
---
---
---
Yes ---
---
---
---
---
Yes Yes ---
--- Yes ---
Yes ---
---
---
---
---
---
---
---
---
---
---
---
---
Read word (R)
Write word (W)
Yes Yes ---
---
---
Yes ---
Automatic variable:
LNG
---
---
Yes ---
---
---
Automatic variable:
---
---
---
---
---
--- ---
---
---
Yes
---
---
SUM, LRC, and CRC
438
The Protocol Macro Function
Section 8-6
Read Word (R)
Word data can be read by setting the desired attributes for the “address” or
“data” in the transmission and reception messages. When the attribute is set, the
address or data is read from the specified word. There are three ways to specify
the word:
1, 2, 3...
1. The second operand of the PMCR(––) instruction (S, the first output word)
can be used.
Example: R(1)
When the command is “Send,” data is read from the first word following the
word specified for PMCR(––) instruction’s second operand.
2. Input and output words in the communications sequence’s link area can be
used.
Example: R(I1+5)
Specifies the fifth word from the beginning of the receive words in the link
area.
Example: R(O2+1)
Specifies the first word from the second send word in the link area.
3. A data area word address can be specified directly.
Example: R(DM 0000 + 2)
Specifies the second word after DM 0000.
Wild Cards (ꢀ) and Write Word (W)
When receiving data, wild cards (ꢀ) and Write Words can be set for the “address”
or “data.” Their functions are explained below:
1, 2, 3...
1. The address of the word is specified as the PMCR(––) instruction’s third op-
erand (first input word).
2. A wild card can be set in the reception message’s address to receive any
message regardless of the destination. The result is a broadcast commu-
nication.
3. The wild card can be set in the reception message’s data to receive all mes-
sages.
4. The Write Word attribute can be set in the reception message’s address to
receive any message regardless of the destination and write the message in
the data area specified by the reception message’s address.
5. The Write Word attribute can be set in the reception message’s data to re-
ceive all messages and write the message in the data area specified by the
reception message’s address.
First-order Equation Using Variable N
First-order equations that include the variable N can be used for the address and
data entries. Variable N is incremented by 1 each time that a step is repeated by
the repeat counter specified in the communication sequence’s step. Using an
equation with N for the address or data allows the kind of dynamic specifications
shown in the following example:
439
The Protocol Macro Function
Section 8-6
Example: R(2N+6)
Specifies the sixth word following the PMCR(––) instruction’s second operand
for the “address” or “data” and adds two words to the specification each time that
the step is repeated.
Specifying the first address with
2N+6 (a first order equation using N).
Common information
th
6
8
word (N=0)
word (N=1)
Communications data
Communications data
Communications data
Communications data
Communications data
th
th
10 word (N=2)
th
12 word (N=3)
th
14 word (N=4)
th
16 word (N=5)
Error Check Code and Length
A SUM, LRC, or CRC error check code and the data length are automatically
added to the message when it is transmitted. When the message is received, the
data is checked for transmission errors using the error check code and the num-
ber of bytes of data specified by the data length are received.
Reception Matrix
If a reception matrix is set in the reception message, up to 15 types of reception
messages can be set and different processes and error processing can be as-
signed to each type of message.
8-6-4 Application Example
Communications sequences can be called and executed by the PMCR(––)
instruction. The following example shows a communications sequence that
transmits five words of data are transmitted one after the other beginning with
the first word after the PMCR(––) instruction’s second operand and then stores
received data in the word specified in the third operand.
00000 28908
PMCR
#1100
DM0000
DM0010
1, 2, 3...
1. When IR 00000 is ON and SR 28908 (Communications Board Port A
Instruction Execution Flag) is OFF, data communications are carried out
through port A of the Communications Board.
2. DM 0000 is the first word of the transmission data, which is transmitted con-
secutively (5 times) based on the communications sequence’s repeat
counter.
3. The received data is written to the DM area beginning at word DM 0010.
The Send command must be set in the transmission step and the repeat counter
must be set to 5. The Read Word attribute must be used for the data in the trans-
mission message with the PMCR(––) instruction’s second operand, and the
first-order equation R(N+1) must be set.
In order to write the reception message to the data area address specified by the
PMCR(––) instruction’s second operand, the timing for writing the received data
must be set in the response notification parameter of the sequence settings. The
Recv command must be set in each reception step and “Yes” must be set for the
response notification parameter of the step settings.
440
The Protocol Macro Function
Section 8-6
Set the wild card (ꢀ) in the reception message so that all data will be received. In
the next process, set “End” in both the transmission step and the reception step.
In error processing, set “Abort” in both the transmission step and the reception
step.
441
SECTION 9
Troubleshooting
The C200HX/HG/HE provides self-diagnostic functions to identify many types of abnormal system conditions. These func-
tions minimize downtime and enable quick, smooth error correction.
This section provides information on hardware and software errors that occur during PC operation. Program input errors are
described in 4-7 Inputting, Modifying, and Checking the Program. Although described in Section 3 Memory Areas, flags and
other error information provided in SR and AR areas are listed in 9-5 Error Flags.
9-1 Alarm Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-2 Programmed Alarms and Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-3 Reading and Clearing Errors and Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-4 Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-5 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-6 Host Link Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
444
444
444
445
449
450
443
Reading and Clearing Errors and Messages
Section 9-3
9-1 Alarm Indicators
The ALM/ERR indicator on the front of the CPU Unit provides visual indication of
an abnormality in the PC. When the indicator is ON (ERROR), a fatal error (i.e.,
ones that will stop PC operation) has occurred; when the indicator is flashing
(ALARM), a nonfatal error has occurred. This indicator is shown in 2-1-1 CPU
Unit Indicators.
WARNING The PC will turn ON the ALM/ERR indicator, stop program execution, and turn
OFF all outputs from the PC for most hardware errors, for certain fatal software
errors, or when FALS(07) is executed in the program (see tables on following
pages). PC operation will continue for all other errors. It is the user’s
responsibility to take adequate measures to ensure that a hazardous situation
will not result from automatic system shutdown for fatal errors and to ensure that
proper actions are taken for errors for which the system is not automatically shut
down. System flags and other system and/or user-programmed error
indications can be used to program proper actions.
!
9-2 Programmed Alarms and Error Messages
FAL(06), FALS(07), and MSG(46) can be used in the program to provide user-
programmed information on error conditions. With these three instructions, the
user can tailor error diagnosis to aid in troubleshooting.
FAL(06) is used with a FAL number other than 00, which is output to the SR area
when FAL(06) is executed. Executing FAL(06) will not stop PC operation or di-
rectly affect any outputs from the PC.
FALS(07) is also used with a FAL number, which is output to the same location in
the SR area when FALS(07) is executed. Executing FALS(07) will stop PC op-
eration and will cause all outputs from the PC to be turned OFF.
When FAL(06) is executed with a function number of 00, the current FAL number
contained in the SR area is cleared and replaced by another, if more have been
stored in memory by the system.
When MSG(46) is used a message containing specified data area words is dis-
played onto the Programming Console or another Programming Device.
The use of these instructions is described in detail in Section 5 Instruction Set.
9-3 Reading and Clearing Errors and Messages
System error messages can be displayed onto the Programming Console or
other Programming Device.
On the Programming Console, press the CLR, FUN, and MONTR keys. If there
are multiple error messages stored by the system, the MONTR key can be
pressed again to access the next message. If the system is in PROGRAM mode,
pressing the MONTR key will clear the error message, so be sure to write down
all message errors as you read them. (It is not possible to clear an error or a mes-
sage while in RUN or MONITOR mode; the PC must be in PROGRAM mode.)
When all messages have been cleared, “ERR CHK OK” will be displayed.
Details on accessing error messages from the Programming Console are pro-
vided in 7-1 Monitoring Operation and Modifying Data. Procedures for the SSS
are provided in the SSS Operation Manual: C Series respectively.
444
Error Messages
Section 9-4
9-4 Error Messages
There are basically three types of errors for which messages are displayed: ini-
tialization errors, non-fatal operating errors, and fatal operating errors. Most of
these are also indicated by FAL number being transferred to the FAL area of the
SR area.
The type of error can be quickly determined from the indicators on the CPU Unit,
as described below for the three types of errors. If the status of an indicator is not
mentioned in the description, it makes no difference whether it is lit or not.
After eliminating the cause of an error, clear the error message from memory
before resuming operation.
Asterisks in the error messages in the following tables indicate variable numeric
data. An actual number would appear on the display.
The following is a simplified CPU Unit troubleshooting procedure:
1, 2, 3...
1. If the POWER indicator is lit and the RUN indicator is not lit, check the initial-
ization errors.
2. Connect the Programming Console to the PC and check if the mode is dis-
played. If the mode is not displayed, turn off and restart the power supply.
3. If the ALM/ERR indicator is flashing, check the non-fatal operating errors.
4. Change to the RUN or MONITOR mode and check if the RUN indicator is lit.
If the RUN indicator is not lit and all previous steps fail, replace the CPU Unit.
Initialization Errors
The following error messages appear before program execution has been
started. The POWER indicator will be lit and the RUN indicator will not be lit for
either of these.
Error and message
Waiting for Special I/O
or Interrupt Input Units
FAL no.
Probable cause
Possible correction
None
A Special I/O Unit or
Interrupt Input Unit has not
initialized.
Perform the I/O Table Read
operation to check unit
numbers. Replace Unit if it
is indicated by “$” only in
the I/O table.
CPU WAIT'G
(High-density I/O Units will
not appear on I/O Table
Read display for all
peripheral devices.)
Waiting for Remote I/O
None
Power to Remote I/O Unit is Check power supply to
off or terminator cannot be
found.
Remote I/O Units,
CPU WAIT'G
connections between
Remote I/O Units, and
terminator setting.
Non-fatal Operating Errors
The following error messages appear for errors that occur after program execu-
tion has been started. PC operation and program execution will continue after
one or more of these errors have occurred. For each of these errors, the POW-
ER and RUN indicators will be lit and the ALM/ERR indicator will be flashing.
Error and message
FAL error
FAL no.
Probable cause
Possible correction
01 to 99
FAL(06) has been executed Correct according to cause
in program. Check the FAL
number to determine
indicated by FAL number
(set by user).
SYS FAIL FAL**
conditions that would cause
execution (set by user).
Interrupt Input Unit error
8A
An error occurred in data
transfer between the
Interrupt Input Unit and the
CPU Unit.
Replace the Interrupt Input
Unit.
SYS FAIL FAL8A
445
Error Messages
Section 9-4
Error and message
FAL no.
8B
Probable cause
Possible correction
An interrupt subroutine
longer than 10 ms was
executed during I/O
refreshing of a Remote I/O
Unit or during Host Link
servicing.
Check the contents of
SR 262 and SR 263 and
verify that the interrupt
subroutine’s processing
time is less than 10 ms.
Interrupt subroutine error
SYS FAIL FAL8B
An attempt was made to
execute a different type of
Change the program or the
Special I/O Unit cycle
I/O refresh from the type set refresh setting so that the
for the Special I/O Unit
cycle refresh.
same refresh method is
used.
9A
9B
9C
9D
An error occurred in data
transfer between a
High-density I/O Unit and
Check AR 0205 to AR 0214
to identify the Unit with a
problem, replace the Unit,
and restart the PC.
High-density I/O Unit error
SYS FAIL FAL9A
the CPU Unit.
An error has been detected Check and correct the PC
PC Setup error
in the PC Setup. This error
will be generated when the
setting is read or used for
the first time.
Setup settings.
SYS FAIL FAL9B
(SR 27500 to SR 27502
indicate which part of the
PC Setup is incorrect.)
An error has occurred with a Refer to the
Communications Board.
Communications Board error
Communications Board’s
Operation Manual for
details.
SYS FAIL FAL9C
An error has occurred
during data transmission
between UM and a Memory
Cassette because:
Make sure that the PC is in
PROGRAM mode.
Memory Cassette Transfer error
SYS FAIL FAL9D
Make sure that the Memory
Cassette is not
Not in PROGRAM Mode.
write-protected.
UM or Memory Cassette is
read-only.
Make sure that the UM and
Memory Cassette capacity
is sufficient.
Insufficient capacity in UM
or Memory Cassette.
Make sure that SYSMAC
NET data links are not
active during the transfer.
A checksum error occurred
in the Memory Cassette
Transfer the data again.
Cycle time overrun
F8
E7
Watchdog timer has
exceeded 100 ms.
Program cycle time is
longer than recommended.
Reduce cycle time if
possible.
CYCLE TIME OVER
I/O table verification error
Unit has been removed or
Use I/O Table Verify
replaced by a different kind Operation to check I/O table
I/O VER ERR
of Unit, making I/O table
and either connect dummy
Units or register the I/O
table again.
incorrect.
Remote I/O error
B0 or B1
Error occurred in
transmissions between
Remote I/O Units.
Check transmission line
between PC and Master
and between Remote I/O
Units.
REMOTE ERR
*
Remote I/O
Master Unit number
446
Error Messages
Section 9-4
Error and message
Special I/O Unit error
FAL no.
D0
Probable cause
Possible correction
Error has occurred in PC
Link Unit, Remote I/O
Master Unit, between a
Host Link, SYSMAC LINK,
or SYSMAC NET Link Unit
and the CPU Unit, or in
Determine the unit number
of the Unit which caused the
error (AR 00 or SR 282),
correct the error, and toggle
the appropriate Restart Bit
in AR 01, SR 250, or
SIOU ERR
refresh between Special I/O SR 252. If the Unit does not
Unit and the CPU Unit. restart, replace it.
Battery error
F7
Backup battery is missing or Check battery, and replace
its voltage has dropped. if necessary.
BATT LOW
Fatal Operating Errors
The following error messages appear for errors that occur after program execu-
tion has been started. PC operation and program execution will stop and all out-
puts from the PC will be turned OFF when any of the following errors occur. No
CPU Unit indicators will be lit for the power interruption error. For all other fatal
operating errors, the POWER and ALM/ERR indicators will be lit. The RUN out-
put will be OFF.
Error and message
FAL no.
Probable cause
Possible correction
Power interruption
No message.
None
Power has been
interrupted for at least
10 ms.
Check power supply voltage
and power lines. Try to
power-up again.
F1
Memory error
SR 27211 ON:
Check the PC Setup.
MEMORY ERR
A checksum error has
occurred in the PC
Setup (DM 6600 to
DM 6655).
SR 27212 ON:
Check the program.
A checksum error has
occurred in the program,
indicating an incorrect
instruction.
SR 27213 ON
A checksum error has
occurred in an
expansion instruction
change.
SR 27214 ON:
Install the Memory Cassette
correctly.
Memory Cassette was
installed or removed
with the power on.
SR 27215 ON:
Autoboot error.
Check whether the CPU Unit
memory is protected or a
checksum error occurred in the
Memory Cassette.
F0
END(01) is not written
anywhere in program.
Write END(01) at the final
address of the program.
No END(01) instruction
NO END INST
C0 to C3 Error has occurred in
The rightmost digit of the FAL
I/O bus error
the bus line between the number indicates the number of
CPU Unit and I/O Units. the Rack where the error was
detected. Check the cable
I/O BUS ERR
*
Rack no.
connections between Racks.
447
Error Messages
Section 9-4
Error and message
FAL no.
Probable cause
Possible correction
Too many Units
E1
Two or more Special I/O Perform the I/O Table Read
Units or Group-2
High-density I/O Units
operation to check unit
numbers, and eliminate
I/O UNIT OVER
are set to the same unit duplications.
number.
The unit number of a
Special I/O Unit that
requires two words is
set to the last unit
number (9 or F).
Unit numbers of Units that
require two words cannot be set
to the last unit number.
Change the unit number to an
allowed setting.
The I/O number of a
64-pt Group-2
High-density I/O Unit is
set to the last unit
number (9 or F).
Unit numbers of 64-pt Group-2
High-density I/O Units cannot
be set to the last unit number.
Change the unit number to a
valid setting.
Two SYSMAC NET Link Check the SYSMAC NET Link
or SYSMAC LINK Units and SYSMAC LINK Unit
share the same
operating level.
operating levels and eliminate
duplications.
Three or more Interrupt
Up to two Interrupt Input Units
Input Units are mounted. can be mounted.
The unit number of a
Special I/O Unit or
High-density I/O Unit
isn’t within the allowed
setting range.
Set the unit number within the
allowed setting range.
A third Expansion Rack Disconnect the third Rack
has been connected to a unless the PC can
PC which can
accommodate three Racks.
accommodate only two.
E0
Input and output word
designations registered Table Verification operation and
in I/O table do no agree check all Units to see that they
Check the I/O table with I/O
Input-output I/O table error
I/O SET ERROR
with input/output words
required by Units
actually mounted.
are in correct configuration.
When the system has been
confirmed, register the I/O table
again.
01 to 99 FALS has been
or 9F executed by the
Correct according to cause
indicated by FAL number. If FAL
FALS error
SYS FAIL FALS**
program. Check the FAL number is 9F, check watchdog
number to determine
conditions that would
cause execution (Set by
user or by system).
timer and cycle time, which may
be too long.
There is an error in the
CPU.
Turn ON the power again in
PROGRAM mode.
- - - - - - - - - -
- - - - - - - - - -
Check the program.
(Or the previous message may be dis-
played.)
Communications Errors
If errors occur in communications, the indicator the peripheral port and RS-232C
port (COMM) will not light. Check the connection, programming on both ends
(C200HX/HG/HE and peripheral), and then reset the port using the reset bit
(RS-232C port: SR 25209).
Other Error Messages
A number of other error messages are detailed within this manual. Errors in pro-
gram input and debugging can be examined in Section 4 Writing and Inputting
the Program.
448
Error Flags
Section 9-5
9-5 Error Flags
The following table lists the flags and other information provided in the SR and
AR areas that can be used in troubleshooting. Details are provided in 3-4 SR
Area and 3-5 AR Area.
SR Area
Address(es)
Function
23600 to 23615 Node loop status for SYSMAC NET Link system
23700 to 23715 Completion/error code output area for SEND(90)/RECV(98) in SYSMAC LINK/SYSMAC NET Link
24700 to 25015 PC Link Unit Run and Error Flags
25100 to 25115 Remote I/O Error Flags
25200
25203
25206
25208
SYSMAC LINK/SYSMAC NET Link Level 0 SEND(90)/RECV(98) Error Flag
SYSMAC LINK/SYSMAC NET Link Level 1 SEND(90)/RECV(98) Error Flag
Rack-mounting Host Link Unit Level 1 Error Flag
RS-232C Port Error Flag
25300 to 25307 FAL number output area.
25308
25309
25310
25311
25312
25411
25413
25414
25415
Low Battery Flag
Cycle Time Error Flag
I/O Verification Error Flag
Rack-mounting Host Link Unit Level 0 Error Flag
Remote I/O Error Flag
Interrupt Input Unit Error Flag
Interrupt Programming Error Flag
Group-2 High-density I/O Unit Error Flag
Special Unit Error Flag (Special I/O, PC Link, Host Link, Remote I/O Master, SYSMAC NET Link, or
SYSMAC Link Unit Error Flag)
25503
Instruction Execution Error (ER) Flag
26400 to 26403 RS-232C Port Error Code
26404
RS-232C Port Communications Error
26408 to 26411 Peripheral Port Error Code (except Peripheral Mode)
26412
26800 to 26815 Communications Board Error Information
UM Transfer Error Flag: SYSMAC NET data link active during data link table transfer.
Peripheral Port Communications Error Flag (except Peripheral Mode)
27011
27012
27013
27014
27015
27211
27212
27213
27214
27215
27312
27313
27314
27500
27501
27502
UM Transfer Error Flag: Not PROGRAM mode
UM Transfer Error Flag: Read Only
UM Transfer Error Flag: Insufficient capacity or no UM
UM Transfer Error Flag: Board Checksum Error
Memory Error Flag: PC Setup Checksum Error
Memory Error Flag: UM or Ladder Checksum Error
Memory Error Flag: Expansion Instruction Code Change Area Checksum Error
Memory Error Flag: Memory Cassette Online Disconnection
Memory Error Flag: Autoboot Error
IOM Transfer Error Flag: Not PROGRAM mode
IOM Transfer Error Flag: Read Only
IOM Transfer Error Flag: Insufficient capacity
PC Setup Error (DM 6600 to DM 6605)
PC Setup Error (DM 6613 to DM 6623)
PC Setup Error (DM 6635 to DM 6655)
449
Host Link Errors
Section 9-6
Address(es)
Function
28000 to 28015 Group-2 High-density I/O Unit Error Flags for Units 0 to F
28200 to 28215 Special I/O Unit Error Flags for Units 0 to F
28300 to 28303 Communications Board Port A Error Code
28308 to 28311 Communications Board Port B Error Code
AR Area
Address(es)
0000 to 0009
0010
Function
Special I/O or PC Link Unit Error Flags
SYSMAC LINK/SYSMAC NET Link Level 1 System Error Flags
SYSMAC LINK/SYSMAC NET Link Level 0 System Error Flags
Rack-mounting Host Link Unit Level 1 Error Flag
Rack-mounting Host Link Unit Level 0 Error Flag
Remote I/O Master Unit 1 Error Flag
0011
0012
0013
0014
0015
Remote I/O Master Unit 0 Error Flag
0200 to 0204
0205 to 0214
0215
Error Flags for Slave Racks 0 to 4
Group-2 High-density I/O Unit Error Flags (AR 0205 to AR 0214 correspond to I/O numbers 0 to 9.)
Group-2 High-density I/O Unit Error Flag
Optical I/O Units (0 to 7) Error Flags
0300 to 0315
0400 to 0415
0500 to 0515
0600 to 0615
0713 to 0715
1114
Optical I/O Units (8 to 15) Error Flags
Optical I/O Units (16 to 23) Error Flags
Optical I/O Units (24 to 31) Error Flags
Error History Bits
Communications Controller Error Flag Level 0
EEPROM Error Flag for operating level 0
Communications Controller Error Flag Level 1
EEPROM Error Flag for operating level 1
1115
1514
1515
9-6 Host Link Errors
These are the response codes (end codes) that may be returned in the response
frame. When two or more errors occur, the end code for the first error will be re-
turned.
End
code
Contents
Normal completion
Probable cause
Corrective measures
00
01
---
---
Check the relation between the
command and the PC mode.
Not executable in RUN mode
The command that was sent cannot
be executed when the PC is in RUN
mode.
02
Not executable in MONITOR
mode
The command that was sent cannot
be executed when the PC is in
MONITOR mode.
03
04
UM write-protected
Address over
The PC’s UM is write-protected.
Turn OFF pin 1 of the CPU Unit’s
DIP switch.
The program address setting in an
SV Read or SV Change command
exceeds the 65,535 maximum.
Correct the program address setting
and transfer the command again.
13
14
15
FCS error
The FCS is wrong. Either the FCS
calculation is mistaken or there is
adverse influence from noise.
Check the FCS calculation method.
If there was influence from noise,
transfer the command again.
Format error
The command format is wrong or a Check the format and transfer the
command that can’t be divided has command again.
been divided.
Entry number data error
The data is outside of the specified Correct the data and transfer the
range or too long.
command again.
450
Host Link Errors
Section 9-6
End
Contents
Probable cause
Corrective measures
code
16
Command not supported
Frame length error
The operand specified in an SV
Read or SV Change command does
not exist in the program.
Check the command and program.
18
The maximum frame length of 132
bytes was exceeded.
Check the command and divide it
into multiple frames if necessary.
(If the frame exceeds 280 bytes, the
Reception Overflow Flag will be
turned ON and there won’t be a re-
sponse.)
19
23
A3
Not executable
Items to read not registered for
composite command (QQ).
Execute QQ to register items to
read before attempting batch read.
User memory write-protected
Pin 1 on C200HX/HG/HE DIP
switch is ON.
Turn OFF pin 1 of the CPU Unit’s
DIP switch.
Aborted due to FCS error in trans- An FCS error occurred in the se-
mit data
Check the FCS calculation method.
If there was influence from noise,
transfer the command again.
cond or later frame.
A4
Aborted due to format error in
transmit data
The command format did not match Check the format and transfer the
the number of bytes in the second
or later frame.
command again.
A5
A8
Aborted due to entry number data There was a data error in the se-
Correct the data and transfer the
command again.
error in transmit data
cond or later frame.
Aborted due to frame length error
in transmit data
The length of the second or later
frame exceeded the 132-byte max.
Keep frames to 132 bytes or fewer.
Errors without Responses
A response won’t be received with some errors, regardless of the command.
These errors are listed in the following table.
Error
PC operation
Parity overrun or framing error during
command reception
The Communications Error Flag will be turned ON, an error code will
be registered, and receptions will be reset. (The error will be cleared
automatically if communications restart normally.)
A carriage return (CR) isn’t received within
280 bytes.
SR 26407 (RS-232C Port Reception Overflow Flag) will be turned ON.
Communications will return to normal when a normal command is
transmitted.
A command is received that doesn’t have the
Receptions are reset.
@ character at the beginning of the first frame.
Incorrect node number
(Not the local node, hexadecimal, or over 31)
The command is discarded and receptions are reset.
FCS error
A Write command is divided, but an
intermediate frame or the last frame has only
one or two bytes of data.
451
SECTION 10
Host Link Commands
This section describes the host link commands which can be used for host link communications via the C200HX/HG/HE
ports. Refer to 8-2 Host Link Communications for information on the procedures for using host link commands and errors
associated with host link commands.
10-1 Host Link Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-2 Host Link End Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-2-1 End Code Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-2-2 Command/End Code Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3 Host Link Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-1 IR/SR AREA READ –– RR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-2 LR AREA READ –– RL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-3 HR AREA READ –– RH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-4 PV READ –– RC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-5 TC STATUS READ –– RG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-6 DM AREA READ –– RD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-7 AR AREA READ –– RJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-8 EM AREA READ –– RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-9 IR/SR AREA WRITE –– WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-10 LR AREA WRITE –– WL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-11 HR AREA WRITE –– WH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-12 PV WRITE –– WC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-13 TC STATUS WRITE –– WG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-14 DM AREA WRITE –– WD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-15 AR AREA WRITE –– WJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-16 EM AREA WRITE –– WE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-17 SV READ 1 –– R# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-18 SV READ 2 –– R$ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-19 SV READ 3 –– R% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-20 SV CHANGE 1 –– W# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-21 SV CHANGE 2 –– W$ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-22 SV CHANGE 3 –– W% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-23 STATUS READ –– MS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-24 STATUS WRITE –– SC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-25 ERROR READ –– MF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-26 FORCED SET –– KS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-27 FORCED RESET –– KR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-28 MULTIPLE FORCED SET/RESET –– FK . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-29 FORCED SET/RESET CANCEL –– KC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-30 PC MODEL READ –– MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-31 TEST–– TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-32 PROGRAM READ –– RP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-33 PROGRAM WRITE –– WP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-34 I/O TABLE GENERATE –– MI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-35 COMPOUND COMMAND –– QQMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-36 COMPOUND COMMAND DATA READ –– QQIR . . . . . . . . . . . . . . . . . . . . .
10-3-37 ABORT –– XZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-38 INITIALIZE –– ꢀꢀ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-39 TXD RESPONSE –– EX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3-40 Undefined Command –– IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
454
455
455
457
458
458
459
460
461
462
463
464
464
465
466
467
468
469
470
471
472
473
474
476
477
478
480
481
483
484
485
486
488
489
490
491
492
493
494
495
496
497
498
498
499
453
Host Link Command Summary
Section 10-1
10-1 Host Link Command Summary
Command Chart
The commands listed in the chart below can be used for host link communica-
tions with the C200HX/HG/HE.
PC mode
MON
Valid
Header code
Name
Page
RUN
Valid
Valid
PRG
Valid
RR
RL
IR/SR AREA READ
LR AREA READ
HR AREA READ
PV READ
458
459
460
461
462
463
464
464
465
466
467
468
469
470
471
472
473
474
476
477
478
480
481
483
484
485
486
488
489
490
491
492
493
494
495
497
498
498
499
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
RH
RC
RG
RD
RJ
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
TC STATUS READ
DM AREA READ
AR AREA READ
EM AREA READ
IR/SR AREA WRITE
LR AREA WRITE
HR AREA WRITE
PV WRITE
Valid
Valid
RE
WR
WL
WH
WC
WG
WD
WJ
WE
R#
Valid
Not valid Valid
Not valid Valid
Not valid Valid
Not valid Valid
Not valid Valid
Not valid Valid
Not valid Valid
Not valid Valid
TC STATUS WRITE
DM AREA WRITE
AR AREA WRITE
EM AREA WRITE
SV READ 1
Valid
Valid
Valid
Valid
Valid
Valid
R$
SV READ 2
R%
W#
W$
W%
MS
SC
MF
KS
KR
FK
SV READ 3
Not valid Valid
Not valid Valid
Not valid Valid
SV CHANGE 1
SV CHANGE 2
SV CHANGE 3
STATUS READ
STATUS WRITE
ERROR READ
FORCED SET
Valid
Valid
Valid
Valid
Valid
Valid
Not valid Valid
Not valid Valid
Not valid Valid
Not valid Valid
FORCED RESET
MULTIPLE FORCED SET/RESET
FORCED SET/RESET CANCEL
PC MODEL READ
KC
MM
TS
Valid
Valid
Valid
Valid
Valid
Valid
TEST
RP
WP
MI
PROGRAM READ
Not valid Not valid Valid
Not valid Not valid Valid
PROGRAM WRITE
I/O TABLE GENERATE
COMPOUND COMMAND
ABORT (command only)
INITIALIZE (command only)
QQ
XZ
Valid
Valid
Valid
Valid
---
Valid
Valid
Valid
Valid
---
Valid
Valid
Valid
ꢀꢀ
EX
IC
Not valid TXD RESPONSE (response only)
--- Undefined command (response only)
454
Host Link End Codes
Section 10-2
10-2 Host Link End Codes
10-2-1 End Code Summary
These are the response (end) codes that are returned in the response frame.
When two or more errors occur, the end code for the first error will be returned.
End
code
Contents
Normal completion
Probable cause
Corrective measures
00
01
---
---
Check the relation between the
command and the PC mode.
Not executable in RUN mode
The command that was sent cannot
be executed when the PC is in RUN
mode.
02
Not executable in MONITOR
mode
The command that was sent cannot
be executed when the PC is in
MONITOR mode.
03
04
UM write-protected
Address over
The PC’s UM is write-protected.
Turn OFF pin 1 of the CPU Unit’s
DIP switch.
The program address setting in an
SV Read or SV Change command
is above the highest program ad-
dress but less than 65,536.
Correct the program address setting
and transfer the command again.
13
14
FCS error
The FCS is wrong. Either the FCS
calculation is mistaken or there is
adverse influence from noise.
Check the FCS calculation method.
If there was influence from noise,
transfer the command again.
Format error
The command format is wrong or a Check the format and transfer the
command that can’t be divided has command again.
been divided.
15
16
Entry number data error
Command not supported
The data is outside of the specified Correct the data and transfer the
range or too long.
command again.
The operand specified in an SV
Read or SV Change command does
not exist in the program.
Check the command and program.
18
Frame length error
The maximum frame length of 132
bytes was exceeded.
Check the command and divide it
into multiple frames if necessary.
(If the frame exceeds 280 bytes, the
Reception Overflow Flag will be
turned ON and there won’t be a re-
sponse.)
19
20
Not executable
Items to read not registered for
composite command (QQ).
Execute QQ to register items to
read before attempting batch read.
Couldn’t create I/O table
Unrecognized Remote I/O Unit, too Check the Remote I/O System and
many I/O words, or node number
duplication for Remote Optical I/O
Units.
the number of I/O words.
23
A3
User memory protected
Pin 1 on C200HX/HG/HE DIP
switch is ON.
Turn OFF pin 1 of the CPU Unit’s
DIP switch.
Aborted due to FCS error in trans- An FCS error occurred in the se-
mit data
Check the FCS calculation method.
If there was influence from noise,
transfer the command again.
cond or later frame.
A4
Aborted due to format error in
transmit data
The command format did not match Check the format and transfer the
the number of bytes in the second
or later frame.
command again.
A5
A8
Aborted due to entry number data There was a entry number data er-
Correct the data and transfer the
command again.
error in transmit data
ror in the second or later frame.
Aborted due to frame length error
in transmit data
The length of the second or later
frame exceeded the 132-byte max.
Keep frames to 132 bytes or fewer.
455
Host Link End Codes
Errors without Responses
Error
Section 10-2
A response won’t be received with some errors, regardless of the command.
These errors are listed in the following table.
PC operation
Parity overrun or framing error during
command reception
The Communications Error Flag will be turned ON, an error code will
be registered, and receptions will be reset. (The error will be cleared
automatically if communications restart normally.)
A carriage return (CR) isn’t received within
280 bytes.
SR 26407 (RS-232C Port Reception Overflow Flag) will be turned ON.
Communications return to normal when a normal command is
transmitted.
A command is received that doesn’t have the
Receptions are reset.
@ character at the beginning of the first frame.
Incorrect node number
The command is discarded and receptions are reset.
(Not the local node, hexadecimal, or over 31)
A Write command’s intermediate frame or last FCS error
frame has only one or two bytes of data.
456
Host Link End Codes
Section 10-2
10-2-2 Command/End Code Table
The following table shows which end codes can be returned for each command.
Header
RR
RL
Possible End Codes
13 14 15
Comments
00
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
A3
A3
A3
A3
A3
A3
A8 ---
A8 ---
A8 ---
A8 ---
A8 ---
A8 ---
---
00
13 14 15
13 14 15
13 14 15
13 14 15
13 14 15
13 14 15
13 14 15
13 14 15
13 14 15
13 14 15
13 14 15
13 14 15
13 14 15
13 14 15
13 14 15
RH
RC
RG
RD
RJ
00
00
00
00
00
RE
WR
WL
WH
WC
WG
WD
WJ
WE
R#
00
A3
A8 ---
00 01
00 01
00 01
00 01
00 01
00 01
00 01
00 01
00
A3 A4 A5 A8 ---
A3 A4 A5 A8 ---
A3 A4 A5 A8 ---
A3 A4 A5 A8 ---
A3 A4 A5 A8 ---
23 A3 A4 A5 A8 ---
A3 A4 A5 A8 ---
A3 A4 A5 A8 ---
13 14 15 16 18
04 13 14 15 16 18
04 13 14 15 16 18
13 14 15 16 18
23
23
23
23
23
23
---
---
R$
00
R%
W#
W$
W%
MS
SC
MF
KS
00
---
00 01
00 01
00 01
00
---
04 13 14 15 16 18
04 13 14 15 16 18
---
---
13 14
18
---
00
13 14 15
13 14 15
13 14 15
13 14 15
13 14 15
13 14
18 19
18
---
00
---
00 01
00 01
00 01
00 01
00
18
---
KR
FK
18
---
18
---
KC
MM
TS
18
---
13 14
18
---
13 14
18
---
RP
WP
MI
00
13 14
18
23 A3
A8 ---
00 01 02
00 01 02 03
00
13 14 15
13 14
18 19
18
23 A3 A4 A5 A8 ---
---
20
QQ
XZ
13 14 15
18 19
A3 A4 A5 A8 ---
---
---
---
---
No response
No response
No end code
No end code
ꢀꢀ
EX
IC
457
Host Link Commands
Section 10-3
10-3 Host Link Commands
This section explains the various Host Link commands that can be issued from
the host computer to the PC. Refer to 8-2 Host Link Communications for in-
formation on the procedures for using host link commands and errors
associated with host link commands.
10-3-1 IR/SR AREA READ –– RR
Reads the contents of the specified number of IR and SR words, starting from
the specified word.
Command Format
1
0
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 x 10 x 10 x 10 x 10
@
R
R
ꢀ
↵
Node no.
Header
code
Beginning word
(0000 to 0511)
No. of words
(0001 to 0512)
FCS
Terminator
Response Format
1
0
1
0
3
2
1
0
x 10 x 10
x 16 x 16 x 16 x 16 x 16 x 16
@
R
R
ꢀ
↵
Node no.
Header
code
End code
Read data (1 word)
Read data (for number of words read)
FCS
Terminator
Limitations
The text portion of the response’s first frame can contain up to 30 words. If more
than 30 words are read, the data will be returned in multiple frames.
In the second and later frames, the text portion of the response can contain up to
31 words.
The INITIALIZE and ABORT commands can be sent instead of the delimiter for
multiple responses for this command. If other commands are sent, they will be
treated the same as delimiters.
PC Settings
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
OK
An end code of 14 (format error) will be returned if the length of the command is
incorrect and an end code of 15 (entry number data error) will be returned if the
specified words exceed the data area boundaries or aren’t specified in BCD.
End code
00
Contents
Normal completion
FCS error
13
14
15
18
A3
A8
Format error
Entry number data error
Frame length error
Aborted due to FCS error in transmit data
Aborted due to frame length error in transmit data
458
Host Link Commands
Section 10-3
10-3-2 LR AREA READ –– RL
Reads the contents of the specified number of LR words, starting from the speci-
fied word.
Command Format
1
0
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 x 10 x 10 x 10 x 10
@
R
L
ꢀ
↵
Node no.
Header
code
Beginning word
(0000 to 0063)
No. of words
(0001 to 0064)
FCS
Terminator
Response Format
1
0
1
0
3
2
1
0
x 10 x 10
x 16 x 16 x 16 x 16 x 16 x 16
@
R
L
ꢀ
↵
Node no.
Header
code
End code
Read data (1 word)
Read data (for number of words read)
Terminator
FCS
Limitations
The text portion of the response’s first frame can contain up to 30 words. If more
than 30 words are read, the data will be returned in multiple frames.
In the second and later frames, the text portion of the response can contain up to
31 words.
The INITIALIZE and ABORT commands can be sent instead of the delimiter for
multiple responses for this command. If other commands are sent, they will be
treated the same as delimiters.
PC Settings
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
OK
Execution Conditions
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
OK
End Codes
An end code of 14 (format error) will be returned if the length of the command is
incorrect and an end code of 15 (entry number data error) will be returned if the
specified words exceed the data area boundaries or aren’t specified in BCD.
End code
00
Contents
Normal completion
FCS error
13
14
15
18
A3
A8
Format error
Entry number data error
Frame length error
Aborted due to FCS error in transmit data
Aborted due to frame length error in transmit data
459
Host Link Commands
Section 10-3
10-3-3 HR AREA READ –– RH
Reads the contents of the specified number of HR words, starting from the speci-
fied word.
Command Format
1
0
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 x 10 x 10 x 10 x 10
@
R
H
ꢀ
↵
Node no.
Header
code
Beginning word
(0000 to 0099)
No. of words
(0001 to 0100)
FCS
Terminator
Response Format
1
0
1
0
3
2
1
0
x 10 x 10
x 16 x 16 x 16 x 16 x 16 x 16
@
R
H
ꢀ
↵
Node no.
Header
code
End code
Read data (1 word)
Read data (for number of words read)
FCS
Terminator
Limitations
The text portion of the response’s first frame can contain up to 30 words. If more
than 30 words are read, the data will be returned in multiple frames.
In the second and later frames, the text portion of the response can contain up to
31 words.
The INITIALIZE and ABORT commands can be sent instead of the delimiter for
multiple responses for this command. If other commands are sent, they will be
treated the same as delimiters.
PC Settings
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
OK
Execution Conditions
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
OK
End Codes
An end code of 14 (format error) will be returned if the length of the command is
incorrect and an end code of 15 (entry number data error) will be returned if the
specified words exceed the data area boundaries or aren’t specified in BCD.
End code
00
Contents
Normal completion
FCS error
13
14
15
18
A3
A8
Format error
Entry number data error
Frame length error
Aborted due to FCS error in transmit data
Aborted due to frame length error in transmit data
460
Host Link Commands
Section 10-3
10-3-4 PV READ –– RC
Reads the contents of the specified number of timer/counter PVs (present val-
ues), starting from the specified timer/counter.
Command Format
1
0
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 x 10 x 10 x 10 x 10
@
R
C
ꢀ
↵
Node no.
Header
code
Beginning timer/counter No. of timers/counters
(0000 to 0511) (0001 to 0512)
FCS
Terminator
Response Format
1
0
1
0
3
2
1
0
x 10 x 10
x 16 x 16 x 10 x 10 x 10 x 10
@
R
C
ꢀ
↵
Node no.
Header
code
End code
Read data (1 word)
Read data (for number of words read)
FCS
Terminator
Limitations
The text portion of the response’s first frame can contain up to 30 words. If more
than 30 words are read, the data will be returned in multiple frames.
In the second and later frames, the text portion of the response can contain up to
31 words.
The INITIALIZE and ABORT commands can be sent instead of the delimiter for
multiple responses for this command. If other commands are sent, they will be
treated the same as delimiters.
PC Settings
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
OK
Execution Conditions
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
OK
End Codes
An end code of 14 (format error) will be returned if the length of the command is
incorrect and an end code of 15 (entry number data error) will be returned if the
specified words exceed the data area boundaries or aren’t specified in BCD.
End code
00
Contents
Normal completion
FCS error
13
14
15
18
A3
A8
Format error
Entry number data error
Frame length error
Aborted due to FCS error in transmit data
Aborted due to frame length error in transmit data
461
Host Link Commands
Section 10-3
10-3-5 TC STATUS READ –– RG
Reads the status of the Completion Flags of the specified number of timers/
counters, starting from the specified timer/counter. A “1” indicates that the
Completion Flag is ON.
Command Format
1
0
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 x 10 x 10 x 10 x 10
@
R
G
ꢀ
↵
Node no.
Header
code
Beginning timer/counter No. of timers/counters
(0000 to 0511) (0001 to 0512)
FCS
Terminator
Response Format
ON/
OFF
1
0
1
0
x 10 x 10
x 16 x 16
@
R
G
ꢀ
↵
Node no.
Header
code
End code
FCS
Terminator
Read data
(1 timer/counter)
Read data
(for number of TC read)
Limitations
The text portion of the response’s first frame can contain up to 121 words. If more
than 121 words are read, the data will be returned in multiple frames.
In the second and later frames, the text portion of the response can contain up to
124 words.
The INITIALIZE and ABORT commands can be sent instead of the delimiter for
multiple responses for this command. If other commands are sent, they will be
treated the same as delimiters.
PC Settings
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
OK
An end code of 14 (format error) will be returned if the length of the command is
incorrect and an end code of 15 (entry number data error) will be returned if the
specified words exceed the data area boundaries or aren’t specified in BCD.
End code
00
Contents
Normal completion
FCS error
13
14
15
18
A3
A8
Format error
Entry number data error
Frame length error
Aborted due to FCS error in transmit data
Aborted due to frame length error in transmit data
462
Host Link Commands
Section 10-3
10-3-6 DM AREA READ –– RD
Reads the contents of the specified number of DM words, starting from the spe-
cified word.
Command Format
1
0
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 x 10 x 10 x 10 x 10
@
R
D
ꢀ
↵
Node no.
Header
code
Beginning word
(0000 to 9999)
No. of words
(0001 to 10000)
(see note)
FCS
Terminator
Note To specify 10,000 words, input 0000 for the number of words to be read.
Response Format
1
0
1
0
3
2
1
0
x 10 x 10
x 16 x 16 x 16 x 16 x 16 x 16
@
R
D
ꢀ
↵
Node no.
Header
code
End code
Read data (1 word)
Read data (for number of words read)
FCS
Terminator
Limitations
The text portion of the response’s first frame can contain up to 30 words. If more
than 30 words are read, the data will be returned in multiple frames.
In the second and later frames, the text portion of the response can contain up to
31 words.
DM 6656 to DM 6999 do not exist, but an error will not occur if you try to read
these words. Instead, “0000” will be returned as a response. Likewise, “0000”
will be returned for extension DM words (DM 7000 to DM 9999) if extension DM
hasn’t been allocated in the UM area.
The INITIALIZE and ABORT commands can be sent instead of the delimiter for
multiple responses for this command. If other commands are sent, they will be
treated the same as delimiters.
PC Settings
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
OK
An end code of 14 (format error) will be returned if the length of the command is
incorrect and an end code of 15 (entry number data error) will be returned if the
specified words exceed the data area boundaries or aren’t specified in BCD.
End code
00
Contents
Normal completion
FCS error
13
14
15
18
A3
A8
Format error
Entry number data error
Frame length error
Aborted due to FCS error in transmit data
Aborted due to frame length error in transmit data
463
Host Link Commands
Section 10-3
10-3-7 AR AREA READ –– RJ
Reads the contents of the specified number of AR words, starting from the speci-
fied word.
Command Format
1
0
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 x 10 x 10 x 10 x 10
@
R
J
ꢀ
↵
Node no.
Header
code
Beginning word
(0000 to 0027)
No. of words
(0001 to 0028)
FCS
Terminator
Response Format
1
0
1
0
3
2
1
0
x 10 x 10
x 16 x 16 x 16 x 16 x 16 x 16
@
R
J
ꢀ
↵
Node no.
Header
code
End code
Read data (1 word )
FCS
Terminator
Read data
(for number of words read)
Limitations
PC Settings
The text portion of the response’s first frame can contain up to 30 words.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
---
An end code of 14 (format error) will be returned if the length of the command is
incorrect and an end code of 15 (entry number data error) will be returned if the
specified words exceed the data area boundaries or aren’t specified in BCD.
End code
00
Contents
Normal completion
FCS error
13
14
15
18
Format error
Entry number data error
Frame length error
10-3-8 EM AREA READ –– RE
Reads the contents of the specified number of EM words, starting from the spe-
cified word in the specified EM bank.
Command Format
1
0
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 x 10 x 10 x 10 x 10
@
R
E
Bank No.
ꢀ
↵
Node no.
Header
code
Bank no.
(See note.)
Beginning word
(0000 to 6143)
No. of words
(0001 to 6144)
FCS
Terminator
Note Input 00, 01, or 02 to specify bank number 0, 1, or 2. Input two spaces to specify
the current bank.
464
Host Link Commands
Section 10-3
Response Format
1
0
1
0
3
2
1
0
x 10 x 10
x 16 x 16 x 16 x 16 x 16 x 16
@
R
E
ꢀ
↵
Node no.
Header
code
End code
Read data (1 word)
Read data (for number of words read)
FCS
Terminator
Limitations
The text portion of the response’s first frame can contain up to 30 words. If more
than 30 words are read, the data will be returned in multiple frames.
In the second and later frames, the text portion of the response can contain up to
31 words.
If a valid bank number is specified but the PC isn’t equipped with that EM bank,
“0000” will be returned as the read data.
This command can’t be used to change the current bank number.
The INITIALIZE and ABORT commands can be sent instead of the delimiter for
multiple responses for this command. If other commands are sent, they will be
treated the same as delimiters.
PC Settings
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
OK
An end code of 14 (format error) will be returned if the length of the command is
incorrect and an end code of 15 (entry number data error) will be returned if the
specified words exceed the data area boundaries, the specified words aren’t
specified in BCD, or an invalid bank number is specified.
End code
00
Contents
Normal completion
FCS error
13
14
15
18
A3
A8
Format error
Entry number data error
Frame length error
Aborted due to FCS error in transmit data
Aborted due to frame length error in transmit data
10-3-9 IR/SR AREA WRITE –– WR
Writes data to the IR and SR areas, starting from the specified word. Writing is
done word by word.
Command Format
1
0
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 x 16 x 16 x 16 x 16
@
W
R
ꢀ
↵
Node no.
Header
code
Beginning word
(0000 to 0511)
Write data (1 word)
Write data
Terminator
FCS
(for number of words to write)
465
Host Link Commands
Section 10-3
Response Format
1
0
1
0
x 10 x 10
x 16 x 16
@
W
R
ꢀ
↵
Node no.
Header
code
End code
FCS
Terminator
Limitations
PC Settings
Data cannot be written to words 253 to 255. If there is an attempt to write to these
words, no error will result, but nothing will be written to these words.
Except for the first word of the write data, the write data can be divided into multi-
ple frames.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
---
OK
OK
OK
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
OK
Single
Multiple
OK
---
An end code of 14 (format error) will be returned if the length of the command is
incorrect or the first word of write data isn’t in the first frame.
An end code of 15 (entry number data error) will be returned if the specified write
data exceeds the data area boundaries, the beginning word isn’t specified in
BCD, or the write data isn’t hexadecimal. (An end code of A5 will be returned
instead of 15 for non-hexadecimal write data in multiple command frames.)
End code
00
Contents
Normal completion
Not executable in RUN mode
FCS error
01
13
14
15
18
A3
A4
A5
A8
Format error
Entry number data error
Frame length error
Aborted due to FCS error in transmit data
Aborted due to format error in transmit data
Aborted due to entry number data error in transmit data
Aborted due to frame length error in transmit data
10-3-10
LR AREA WRITE –– WL
Writes data to the LR area, starting from the specified word. Writing is done word
by word.
Command Format
1
0
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 x 16 x 16 x 16 x 16
@
W
L
ꢀ
↵
Node no.
Header
code
Beginning word
(0000 to 0063)
Write data (1 word)
Write data
FCS
Terminator
(for number of words to write )
466
Host Link Commands
Section 10-3
Response Format
1
0
1
0
x 10 x 10
x 16 x 16
@
W
L
ꢀ
↵
Node no.
Header
code
End code
FCS
Terminator
Limitations
PC Settings
Except for the first word of the write data, the write data can be divided into multi-
ple frames.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
---
OK
OK
OK
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
OK
Single
Multiple
OK
---
An end code of 14 (format error) will be returned if the length of the command is
incorrect or the first word of write data isn’t in the first frame.
An end code of 15 (entry number data error) will be returned if the specified write
data exceeds the data area boundary, the beginning word isn’t specified in BCD,
or the write data isn’t hexadecimal. (An end code of A5 will be returned instead of
15 for non-hexadecimal write data in multiple command frames.)
End code
00
Contents
Normal completion
Not executable in RUN mode
FCS error
01
13
14
15
18
A3
A4
A5
A8
Format error
Entry number data error
Frame length error
Aborted due to FCS error in transmit data
Aborted due to format error in transmit data
Aborted due to entry number data error in transmit data
Aborted due to frame length error in transmit data
10-3-11
HR AREA WRITE –– WH
Writes data to the HR area, starting from the specified word. Writing is done word
by word.
Command Format
1
0
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 x 16 x 16 x 16 x 16
@
W
H
ꢀ
↵
Node no.
Header
code
Beginning word
(0000 to 0099)
Write data (1 word)
Write data
FCS
Terminator
(for no. of words to write)
Response Format
1
0
1
0
x 10 x 10
x 16 x 16
@
W
H
ꢀ
↵
Node no.
Header
code
End code
FCS
Terminator
467
Host Link Commands
Section 10-3
Limitations
PC Settings
Except for the first word of the write data, the write data can be divided into multi-
ple frames.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
---
OK
OK
OK
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
OK
Single
Multiple
OK
---
An end code of 14 (format error) will be returned if the length of the command is
incorrect or the first word of write data isn’t in the first frame.
An end code of 15 (entry number data error) will be returned if the specified write
data exceeds the data area boundary, the beginning word isn’t specified in BCD,
or the write data isn’t hexadecimal. (An end code of A5 will be returned instead of
15 for non-hexadecimal write data in multiple command frames.)
End code
00
Contents
Normal completion
Not executable in RUN mode
FCS error
01
13
14
15
18
A3
A4
A5
A8
Format error
Entry number data error
Frame length error
Aborted due to FCS error in transmit data
Aborted due to format error in transmit data
Aborted due to entry number data error in transmit data
Aborted due to frame length error in transmit data
10-3-12
PV WRITE –– WC
Writes the PVs (present values) of timers/counters starting from the specified
timer/counter.
Command Format
1
0
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 x 16 x 16 x 16 x 16
@
W
C
ꢀ
↵
Node no.
Header
code
Beginning timer/counter Write data (1 timer/counter)
FCS
Terminator
(0000 to 0511)
Write data
(for no. of PV to write)
Response Format
1
0
1
0
x 10 x 10
x 16 x 16
@
W
C
ꢀ
↵
Node no.
Header
code
End code
FCS
Terminator
Limitations
PC Settings
Except for the first word of the write data, the write data can be divided into multi-
ple frames.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
OK
Read-protected
---
OK
OK
OK
468
Host Link Commands
Section 10-3
Execution Conditions
Commands
Responses
Single
Multiple
Single
Multiple
OK
OK
OK
---
End Codes
An end code of 14 (format error) will be returned if the length of the command is
incorrect or the first word of write data isn’t in the first frame.
An end code of 15 (entry number data error) will be returned if the specified write
data exceeds the data area boundary, the beginning word isn’t specified in BCD,
or the write data isn’t hexadecimal. (An end code of A5 will be returned instead of
15 for non-hexadecimal write data in multiple command frames.)
With Host Link Units, an end code of 15 (entry number data error) will be re-
turned if the write data isn’t BCD.
End code
00
Contents
Normal completion
Not executable in RUN mode
FCS error
01
13
14
15
18
A3
A4
A5
A8
Format error
Entry number data error
Frame length error
Aborted due to FCS error in transmit data
Aborted due to format error in transmit data
Aborted due to entry number data error in transmit data
Aborted due to frame length error in transmit data
10-3-13
TC STATUS WRITE –– WG
Writes the status of the Completion Flags for timers and counters in the TC area,
starting from the specified timer/counter (number). Writing is done number by
number. When a Completion Flag is ON, it indicates that the time or count is up.
Command Format
ON/
OFF
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10
@
W
G
ꢀ
↵
Node no.
Header Beginning timer/counter
code (0000 to 0511)
FCS
Terminator
Write data
(1 timer/counter)
Write data
(for number of TC to write)
Response Format
1
0
1
0
x 10 x 10
x 16 x 16
@
W
G
ꢀ
↵
Node no.
Header
code
End code
FCS
Terminator
PC Settings
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
---
OK
OK
OK
OK
Execution Conditions
Commands
Responses
Single
OK
Multiple
OK
Single
Multiple
OK
---
469
Host Link Commands
Section 10-3
End Codes
An end code of 14 (format error) will be returned if the length of the command is
incorrect or the first word of write data isn’t in the first frame.
An end code of 15 (entry number data error) will be returned if the digits of write
data aren’t 0 or 1, the specified write data exceeds the data area boundary, the
beginning word isn’t specified in BCD, or the write data isn’t hexadecimal. (An
end code of A5 will be returned instead of 15 for non-hexadecimal write data in
multiple command frames.)
End code
00
Contents
Normal completion
Not executable in RUN mode
FCS error
01
13
14
15
18
A3
A4
A5
A8
Format error
Entry number data error
Frame length error
Aborted due to FCS error in transmit data
Aborted due to format error in transmit data
Aborted due to entry number data error in transmit data
Aborted due to frame length error in transmit data
10-3-14
DM AREA WRITE –– WD
Writes data to the DM area, starting from the specified word. Writing is done
word by word.
Command Format
1
0
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 x 16 x 16 x 16 x 16
@
W
D
ꢀ
↵
Node no.
Header
code
Beginning word
(0000 to 9999)
Write data (1 word)
Write data
Terminator
FCS
(for number of words to write)
Response Format
1
0
1
0
x 10 x 10
x 16 x 16
@
W
D
ꢀ
↵
Node no.
Header
code
End code
FCS
Terminator
Limitations
PC Settings
Except for the first word of the write data, the write data can be divided into multi-
ple frames.
DM 6656 to DM 6999 do not exist, but an error won’t occur if the command at-
tempts to write to these words. Likewise, an error won’t occur if the command
attempts to write to extension DM words (DM 7000 to DM 9999) which haven’t
been allocated in the UM area.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
---
OK
OK
---
OK
Execution Conditions
Commands
Responses
Single
OK
Multiple
OK
Single
Multiple
OK
---
470
Host Link Commands
Section 10-3
End Codes
An end code of 14 (format error) will be returned if the length of the command is
incorrect or the first word of write data isn’t in the first frame.
An end code of 15 (entry number data error) will be returned if the specified write
data exceeds the data area boundary, the beginning word isn’t specified in BCD,
or the write data isn’t hexadecimal. (An end code of A5 will be returned instead of
15 for non-hexadecimal write data in multiple command frames.)
End code
00
Contents
Normal completion
Not executable in RUN mode
FCS error
01
13
14
15
18
23
A3
A4
A5
A8
Format error
Entry number data error
Frame length error
User memory protected
Aborted due to FCS error in transmit data
Aborted due to format error in transmit data
Aborted due to entry number data error in transmit data
Aborted due to frame length error in transmit data
10-3-15
AR AREA WRITE –– WJ
Writes data to the AR area, starting from the specified word. Writing is done word
by word.
Command Format
1
0
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 x 16 x 16 x 16 x 16
@
W
J
ꢀ
↵
Node no.
Header
code
Beginning word
(0000 to 0027)
Write data (1 word)
Write data
(for the number of words to write)
FCS
Terminator
Response Format
1
0
1
0
x 10 x 10
x 16 x 16
@
W
J
ꢀ
↵
Node no.
Header
code
End code
Terminator
FCS
Limitations
PC Settings
Except for the first word of the write data, the write data can be divided into multi-
ple frames.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
---
OK
OK
OK
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
OK
Single
Multiple
OK
---
An end code of 14 (format error) will be returned if the length of the command is
incorrect or the first word of write data isn’t in the first frame.
471
Host Link Commands
Section 10-3
An end code of 15 (entry number data error) will be returned if the specified write
data exceeds the data area boundary, the beginning word isn’t specified in BCD,
or the write data isn’t hexadecimal. (An end code of A5 will be returned instead of
15 for non-hexadecimal write data in multiple command frames.)
End code
00
Contents
Normal completion
Not executable in RUN mode
FCS error
01
13
14
15
18
A3
A4
A5
A8
Format error
Entry number data error
Frame length error
Aborted due to FCS error in transmit data
Aborted due to format error in transmit data
Aborted due to entry number data error in transmit data
Aborted due to frame length error in transmit data
10-3-16
EM AREA WRITE –– WE
Writes data to the specified EM area bank, starting from the specified word. Writ-
ing is done word by word.
Command Format
1
0
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 x 16 x 16 x 16 x 16
@
W
E
Bank No.
ꢀ
↵
Bank no.
(See note.)
Node no.
Header
code
Beginning word
(0000 to 6143)
Write data (1 word)
Write data
Terminator
FCS
(for number of words to write)
Note Input 00, 01, or 02 to specify bank number 0, 1, or 2. Input two spaces to specify
the current bank.
Response Format
1
0
1
0
x 10 x 10
x 16 x 16
@
W
E
ꢀ
↵
Node no.
Header
code
End code
FCS
Terminator
Limitations
PC Settings
Except for the first word of the write data, the write data can be divided into multi-
ple frames.
If a valid bank number is specified but the PC isn’t equipped with that EM bank,
the command will be completed normally without writing any data.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
---
OK
OK
OK
OK
Execution Conditions
Commands
Responses
Single
OK
Multiple
OK
Single
Multiple
OK
---
End Codes
An end code of 14 (format error) will be returned if the length of the command is
incorrect or the first word of write data isn’t in the first frame.
472
Host Link Commands
Section 10-3
An end code of 15 (entry number data error) will be returned if the specified write
data exceeds the data area boundary, the beginning word isn’t specified in BCD,
or the write data isn’t hexadecimal. (An end code of A5 will be returned instead of
15 for non-hexadecimal write data in multiple command frames.)
End code
00
Contents
Normal completion
Not executable in RUN mode
FCS error
01
13
14
15
18
A3
A4
A5
A8
Format error
Entry number data error
Frame length error
Aborted due to FCS error in transmit data
Aborted due to format error in transmit data
Aborted due to entry number data error in transmit data
Aborted due to frame length error in transmit data
10-3-17
SV READ 1 –– R#
Searches for the first instance of a TIM, TIMH(15), CNT, CNTR(12), or TTIM(87)
instruction with the specified TC number in the user’s program and reads the PV,
which assumed to be set as a constant. The SV that is read is a 4-digit decimal
number (BCD).
Command Format
1
0
1
2
3
4
3
2
1
0
x 10 x 10
OP OP OP OP x 10 x 10 x 10 x 10
@
R
#
ꢀ
↵
Node no.
Header
code
Mnemonic
TC number
(0000 to 0511)
Terminator
FCS
Use all four characters to specify the timer or counter instruction’s mnemonic.
Add a space to the end of a TIM or CNT mnemonic to make it 4 characters long.
Mnemonic
OP2 OP3
Instruction name
TC number
range
OP1
OP4
(Space)
H
0000 to 0511
TIMER
T
T
C
C
T
I
M
M
T
T
I
HIGH-SPEED TIMER
COUNTER
I
N
N
T
(Space)
R
REVERSIBLE COUNTER
TOTALIZING TIMER
M
Response Format
1
0
1
0
3
2
1
0
x 10 x 10
x 16 x 16 x 10 x 10 x 10 x 10
@
R
#
ꢀ
↵
Node no.
Header
code
End code
SV
FCS
Terminator
Limitations
PC Settings
The second word of the instruction must be a BCD constant from 0000 to 0511.
If the same instruction is used more than once in a program, the SV of the first
one will be read.
The command can’t be executed if the UM area is read-protected.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
OK
Read-protected
OK
OK
OK
---
473
Host Link Commands
Section 10-3
Execution Conditions
Commands
Responses
Single
Multiple
Single
Multiple
OK
---
OK
---
End Codes
An end code of 14 (format error) will be returned if the length of the command is
incorrect.
An end code of 15 (entry number data error) will be returned if an incorrect
instruction mnemonic or TC number is used.
An end code of 16 (command not supported) will be returned if the specified
instruction doesn’t exist in the program.
End code
00
Contents
Normal completion
FCS error
13
14
15
16
18
23
Format error
Entry number data error
Command not supported
Frame length error
User memory protected
10-3-18
SV READ 2 –– R$
Reads the constant SV or the word address where the SV is stored. The SV that
is read is a 4-digit decimal number (BCD) written as the second operand for the
TIM, TIMH(15), CNT, CNTR(12), or TTIM(87) instruction at the specified pro-
gram address in the user’s program.
Command Format
1
0
3
2
1
0
3
2
1
0
ꢀ
↵
x 10 x 10
x 10 x 10 x 10 x 10 OP1 OP2 OP3 OP4 x 10 x 10 x 10 x 10
@
R
$
Node no.
Header
code
Program address
(BCD)
Mnemonic
Timer/counter
(0000 to 0511)
FCS
Terminator
Use all four characters to specify the timer or counter instruction’s mnemonic.
Add a space to the end of a TIM or CNT mnemonic to make it 4 characters long.
Mnemonic
OP2 OP3
Instruction name
TC number
range
OP1
OP4
(Space)
H
0000 to 0511
TIMER
T
T
C
C
T
I
M
M
T
T
I
HIGH-SPEED TIMER
COUNTER
I
N
N
T
(Space)
R
REVERSIBLE COUNTER
TOTALIZING TIMER
M
Response Format
1
0
1
0
3
2
1
0
ꢀ
↵
x 10 x 10
x 16 x 16 OP1 OP2 OP3 OP4 x 10 x 10 x 10 x 10
@
R
$
Node no.
Header
code
End code
Operand
SV
FCS
Terminator
474
Host Link Commands
Section 10-3
The “Operand” parameter indicates the data area where the SV is stored or a
constant. The “SV” parameter indicates the word address or the SV itself if it is a
constant.
Operand
OP2 OP3
Classification
Constant or
word address
OP1
OP4
(Space) IR or SR
C
L
I
O
0000 to 0511
0000 to 0063
0000 to 0099
0000 to 0027
0000 to 6655
0000 to 6655
0000 to 9999
0000 to 6143
0000 to 6143
R
R
R
M
M
O
M
M
(Space) (Space) LR
(Space) (Space) HR
(Space) (Space) AR
(Space) (Space) DM
H
A
D
D
C
E
E
ꢀ
(Space) DM (indirect)
(Space) Constant
N
(Space) (Space) EM
(Space) EM (indirect)
ꢀ
Limitations
PC Settings
The command is valid only when the UM setting is ladder only.
The command can’t be executed if the UM area is read-protected.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
---
Execution Conditions
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
---
End Codes
An end code of 04 (address over) will be returned if the program address is
above the highest program address but less than 65,536 (32,767 in the
C200HS).
An end code of 14 (format error) will be returned if the length of the command is
incorrect.
An end code of 15 (entry number data error) will be returned if the program ad-
dress isn’t specified in BCD or the operand/SV parameters are incorrect.
An end code of 16 (command not supported) will be returned if the specified
instruction doesn’t exist in the program.
End code
00
Contents
Normal completion
Address over
04
13
14
15
16
18
23
FCS error
Format error
Entry number data error
Command not supported
Frame length error
User memory protected
475
Host Link Commands
Section 10-3
10-3-19
SV READ 3 –– R%
Reads the constant SV or the word address where the SV is stored. The SV that
is read is a 4-digit decimal number (BCD) written in the second word of the TIM,
TIMH(15), CNT, CNTR(12), or TTIM(87) instruction at the specified program ad-
dress in the user’s program.
Command Format
1
0
5
4
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 x 10 x 10 OP1 OP2 OP3 OP4 x 10 x 10 x 10 x 10
@
R
%
Node no.
Header
code
Program
address
Mnemonic
Timer/counter
(0000 to 0511)
Must be “0”
ꢀ
↵
FCS
Terminator
Use all four characters to specify the timer or counter instruction’s mnemonic.
Add a space to the end of a TIM or CNT mnemonic to make it 4 characters long.
Mnemonic
OP2 OP3
Instruction name
TC number
range
OP1
OP4
(Space)
H
0000 to 0511
TIMER
T
T
C
C
T
I
M
M
T
T
I
HIGH-SPEED TIMER
COUNTER
I
N
N
T
(Space)
R
REVERSIBLE COUNTER
TOTALIZING TIMER
M
Response Format
1
0
1
0
3
2
1
0
ꢀ
↵
x 10 x 10
x 16 x 16 OP1 OP2 OP3 OP4 x 10 x 10 x 10 x 10
@
R
%
Node no.
Header
code
End code
Operand
SV
FCS
Terminator
The “Operand” parameter indicates the data area where the SV is stored or a
constant. The “SV” parameter indicates the word address or the SV itself if it is a
constant.
Operand
OP2 OP3
Classification
Constant or
word address
OP1
OP4
(Space) IR or SR
C
L
I
O
0000 to 0511
0000 to 0063
0000 to 0099
0000 to 0027
0000 to 6655
0000 to 6655
0000 to 9999
0000 to 6143
0000 to 6143
R
R
R
M
M
O
M
M
(Space) (Space) LR
(Space) (Space) HR
(Space) (Space) AR
(Space) (Space) DM
H
A
D
D
C
E
E
ꢀ
(Space) DM (indirect)
(Space) Constant
N
(Space) (Space) EM
(Space) EM (indirect)
ꢀ
Limitations
The command is valid only when the UM setting is ladder only.
The command can’t be executed if the UM area is read-protected.
SR 253 through SR 255 can’t be specified.
476
Host Link Commands
Section 10-3
PC Settings
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
---
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
---
An end code of 04 (address over) will be returned if the program address is
above the highest program address but less than 65,536 (32,768 in the
C200HS).
An end code of 14 (format error) will be returned if the length of the command is
incorrect.
An end code of 15 (entry number data error) will be returned if the program ad-
dress exceeds the 65,535 maximum (32,767 in the C200HS), the program ad-
dress isn’t specified in BCD, or the mnemonic/SV operands are incorrect.
An end code of 16 (command not supported) will be returned if the specified
instruction doesn’t exist in the program.
End code
00
Contents
Normal completion
Address over
04
13
14
15
16
18
23
FCS error
Format error
Entry number data error
Command not supported
Frame length error
User memory protected
10-3-20
SV CHANGE 1 –– W#
Searches for the first instance of the specified TIM, TIMH(15), CNT, CNTR(12),
or TTIM(87) instruction in the user’s program and changes the SV to new
constant SV specified in the second word of the instruction.
Command Format
1
0
3
2
1
0
3
2
1
0
↵
x 10 x 10
OP1 OP2 OP3 OP4 x 10 x 10 x 10 x 10 x 10 x 10 x 10 x 10
ꢀ
@
W
#
Node no.
Header
code
Mnemonic
Timer/counter
(0000 to 0511)
SV (0000 to 9999)
FCS
Terminator
Use all four characters to specify the timer or counter instruction’s mnemonic.
Add a space to the end of a TIM or CNT mnemonic to make it 4 characters long.
Mnemonic
OP2 OP3
Instruction name
TC number
range
OP1
OP4
(Space)
H
0000 to 0511
TIMER
T
T
C
C
T
I
M
M
T
T
I
HIGH-SPEED TIMER
COUNTER
I
N
N
T
(Space)
R
REVERSIBLE COUNTER
TOTALIZING TIMER
M
477
Host Link Commands
Section 10-3
Response Format
1
0
1
0
x 10 x 10
x 16 x 16
ꢀ
↵
@
W
#
Node no.
Header
code
End code
FCS
Terminator
Limitations
PC Settings
The command can’t be executed unless the SV is BCD from 0000 to 9999.
The command can’t be executed if the UM area is write-protected.
If the same instruction is used more than once in a program, the SV of the first
one will be changed.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
---
OK
OK
---
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
---
An end code of 14 (format error) will be returned if the length of the command is
incorrect.
An end code of 15 (entry number data error) will be returned if the SV isn’t BCD or
the mnemonic/TC number is incorrect.
An end code of 16 (command not supported) will be returned if the specified
instruction doesn’t exist in the program.
End code
00
Contents
Normal completion
Not executable in RUN mode
FCS error
01
13
14
15
16
18
23
Format error
Entry number data error
Command not supported
Frame length error
User memory protected
10-3-21
SV CHANGE 2 –– W$
Changes the contents of the second word of the TIM, TIMH(15), CNT,
CNTR(12), or TTIM(87) at the specified program address in the user’s program.
This can only be done with a program of less than 10K.
Command Format
1
0
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 OP1 OP2 OP3 OP4 x 10 x 10 x 10 x 10
@
W
$
Node no.
Header
code
Program
address
Mnemonic
Timer/counter
(0000 to 0511)
3
2
1
0
OP1 OP2 OP3 OP4 x 10 x 10 x 10 x 10
ꢀ
↵
Operand
SV
FCS
Terminator
478
Host Link Commands
Section 10-3
Use all four characters to specify the timer or counter instruction’s mnemonic.
Add a space to the end of a TIM or CNT mnemonic to make it 4 characters long.
Mnemonic
OP2 OP3
Instruction name
TC number
range
OP1
OP4
(Space)
H
0000 to 0511
TIMER
T
T
C
C
T
I
M
M
T
T
I
HIGH-SPEED TIMER
COUNTER
I
N
N
T
(Space)
R
REVERSIBLE COUNTER
TOTALIZING TIMER
M
The “Operand” parameter indicates the data area where the SV is stored or a
constant. The “SV” parameter indicates the word address or the SV itself if it is a
constant.
Operand
OP2 OP3
Classification
Constant or
word address
OP1
OP4
(Space) IR or SR
C
L
I
O
0000 to 0511
0000 to 0063
0000 to 0099
0000 to 0027
0000 to 6655
0000 to 6655
0000 to 9999
0000 to 6143
0000 to 6143
R
R
R
M
M
O
M
M
(Space) (Space) LR
(Space) (Space) HR
(Space) (Space) AR
(Space) (Space) DM
H
A
D
D
C
E
E
ꢀ
(Space) DM (indirect)
(Space) Constant
N
(Space) (Space) EM
(Space) EM (indirect)
ꢀ
Response Format
1
0
1
0
ꢀ
↵
x 10 x 10
x 16 x 16
@
W
$
Node no.
Header
code
End code
FCS
Terminator
Limitations
PC Settings
The command is valid only when the UM setting is ladder only.
SR 253 through SR 255 can’t be specified.
The command can’t be executed if the UM area is write-protected.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
---
OK
OK
---
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
---
An end code of 14 (format error) will be returned if the length of the command is
incorrect.
An end code of 15 (entry number data error) will be returned if the program ad-
dress isn’t BCD, the program address exceeds the maximum address in the pro-
gram, the mnemonic/TC number is incorrect, or the SV is incorrect.
An end code of 16 (command not supported) will be returned if the specified
instruction doesn’t exist in the program.
End code
00
01
Contents
Normal completion
Not executable in RUN mode
479
Host Link Commands
Section 10-3
End code
04
Contents
Address over
13
14
15
16
18
23
FCS error
Format error
Entry number data error
Command not supported
Frame length error
User memory protected
10-3-22
SV CHANGE 3 –– W%
Changes the contents of the second word of the TIM, TIMH(15), CNT,
CNTR(12), or TTIM(87) at the specified program address in the user’s program.
Command Format
1
0
5
4
3
2
1
0
3
2
1
0
x 10 x 10
x 10 x 10 x 10 x 10 x 10 x 10 OP1 OP2 OP3 OP4 x 10 x 10 x 10 x 10
@
W
%
Node no.
Header
code
Program
address
Mnemonic
Timer/counter
(0000 to 0511)
Must be “0”
3
2
1
0
ꢀ
↵
OP1 OP2 OP3 OP4 x 10 x 10 x 10 x 10
Operand
SV
FCS
Terminator
Use all four characters to specify the timer or counter instruction’s mnemonic.
Add a space to the end of a TIM or CNT mnemonic to make it 4 characters long.
Mnemonic
OP2 OP3
Instruction name
TC number
range
OP1
OP4
(Space)
H
0000 to 0511
TIMER
T
T
C
C
T
I
M
M
T
T
I
HIGH-SPEED TIMER
COUNTER
I
N
N
T
(Space)
R
REVERSIBLE COUNTER
TOTALIZING TIMER
M
The “Operand” parameter indicates the data area where the SV is stored or a
constant. The “SV” parameter indicates the word address or the SV itself if it is a
constant.
Operand
OP2 OP3
Classification
Constant or
word address
OP1
OP4
(Space) IR or SR
C
L
I
O
0000 to 0511
0000 to 0063
0000 to 0099
0000 to 0027
0000 to 6655
0000 to 6655
0000 to 9999
0000 to 6143
0000 to 6143
R
R
R
M
M
O
M
M
(Space) (Space) LR
(Space) (Space) HR
(Space) (Space) AR
(Space) (Space) DM
H
A
D
D
C
E
E
ꢀ
(Space) DM (indirect)
(Space) Constant
N
(Space) (Space) EM
(Space) EM (indirect)
ꢀ
480
Host Link Commands
Section 10-3
Response Format
1
0
1
0
x 10 x 10
x 16 x 16
@
W
%
ꢀ
↵
Node no.
Header
code
End code
FCS
Terminator
Limitations
PC Settings
The command is valid only when the UM setting is ladder only.
SR 253 through SR 255 can’t be specified.
The command can’t be executed if the UM area is write-protected.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
---
OK
OK
---
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
---
An end code of 14 (format error) will be returned if the length of the command is
incorrect.
An end code of 15 (entry number data error) will be returned if the program ad-
dress isn’t BCD, the program address exceeds the maximum address in the pro-
gram, the mnemonic/TC number is incorrect, or the SV is incorrect.
An end code of 16 (command not supported) will be returned if the specified
instruction doesn’t exist in the program.
End code
00
Contents
Normal completion
Not executable in RUN mode
Address over
01
04
13
14
15
16
18
23
FCS error
Format error
Entry number data error
Command not supported
Frame length error
User memory protected
10-3-23
STATUS READ –– MS
Reads the PC operating conditions.
Command Format
1
0
x 10 x 10
@
M
S
ꢀ
↵
Node no.
Header
code
FCS
Terminator
Response Format
1
0
1
0
3
2
1
0
16 characters
ꢀ
↵
x 10 x 10
x 16 x 16 x 16 x 16 x 16 x 16
@
M
S
Node no.
Header
code
End code
Status data
Message
FCS
Terminator
481
Host Link Commands
Section 10-3
“Status data” consists of four digits (two bytes) hexadecimal. The leftmost byte
indicates CPU Unit operation mode, and the rightmost byte indicates the size of
the program area.
3
2
x 16
x 16
Bit
14 13 12 11 10
9
8
15
0
0
Bit
Operation mode
9
0
1
1
8
0
0
1
1: Waiting for Remote I/O
power application
PROGRAM mode
RUN mode
1: Forced Set/Reset in effect
1: Fatal error generated
This area is different
from that of
STATUS WRITE.
MONITOR mode
1: FALS generated
1
0
x 16
x 16
Bit
7
6
5
4
3
2
1
0
1
0
0
0
Program area write enable
0: Disabled (DIP switch pin 1 is ON)
1: Enabled (DIP switch pin 1 is OFF)
Bit
5
Program area
6
4
None
0
0
1
1
1
0
0
0
0
1
0
8 Kbytes
16 Kbytes
24 Kbytes
32 Kbytes
1
0
0
1
PC Settings
PC Mode
MONITOR PROGRAM
UM Area
RUN
Write-protected
Read-protected
OK
OK
OK
OK
OK
Execution Conditions
Commands
Responses
Single
Multiple
---
Single
Multiple
OK
OK
---
End Codes
An end code of 14 (format error) will be returned if the length of the command is
incorrect.
End code
00
Contents
Normal completion
FCS error
13
14
18
Format error
Frame length error
482
Host Link Commands
Section 10-3
10-3-24
STATUS WRITE –– SC
Changes the PC operating mode.
Command Format
1
0
1
0
ꢀ
↵
x 10 x 10
x 16 x 16
@
S
C
Node no.
Header
code
Mode data
FCS
Terminator
Response Format
1
0
1
0
ꢀ
↵
x 10 x 10
x 16 x 16
@
S
C
Node no.
Header
code
End code
FCS
Terminator
“Mode data” consists of two digits (one byte) hexadecimal. With the leftmost two
bits, specify the PC operating mode. Set all of the remaining bits to “0.”
1
0
x 16
x 16
Bit
6
5
4
3
2
1
0
7
0
0
0
0
0
0
Bit
Operation mode
1
0
1
1
0
0
0
1
PROGRAM mode
MONITOR mode
RUN mode
This area is different
from that of STATUS
READ.
PC Settings
PC Mode
MONITOR PROGRAM
UM Area
RUN
Write-protected
Read-protected
OK
OK
OK
OK
OK
Execution Conditions
End Codes
Commands
Responses
Single
Multiple
---
Single
Multiple
OK
OK
---
An end code of 14 (format error) will be returned if the length of the command is
incorrect.
End code
00
Contents
Normal completion
FCS error
13
14
15
18
19
Format error
Entry number data error
Frame length error
Not executable
483
Host Link Commands
Section 10-3
10-3-25
ERROR READ –– MF
Reads and clears errors in the PC. Also checks whether previous errors have
been cleared.
Command Format
1
0
1
0
ꢀ
x 10 x 10
x 10 x 10
↵
@
M
F
Node no.
Header
code
Error clear
FCS
Terminator
For the “error clear” parameter, specify 01 to clear errors and 00 to not clear er-
rors (BCD). Fatal errors can be cleared only when the PC is in PROGRAM
mode.
Response Format
1
0
1
0
3
2
1
0
3
2
1
0
ꢀ
↵
x 10 x 10
x 16 x 16 x 16 x 16 x 16 x 16 x 16 x 16 x 16 x 16
@
M
F
Node no.
Header
code
End code
Error information
(1st word)
Error information
(2nd word)
FCS
Terminator
1st word
3
2
1
0
x 16
x 16
x 16
x 16
Bit
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
(Data from I/O bus)
1: Group 2 (data bus failure)
0
0
0
0
0
0
0: CPU Rack
0
1
1
1: Expansion I/O Rack 1
0: Expansion I/O Rack 2
1: Expansion I/O Rack 3
ON: Battery error (Error code F7)
ON: Special I/O Unit error
ON: System error (FAL)
ON: Memory error (Error code F1)
ON: I/O bus error (Error code C0)
ON: PC link error
ON: Host Link Unit transmission error
ON: No end instruction error (FALS)
ON: System error (FALS)
2nd word
x 16
3
2
1
0
x 16
x 16
x 16
Bit
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
15
0
0
0
FAL, FALS No. (B CD00 to 99)
ON: I/O verify error (Error code F7)
ON: Cycle time overrun (Error code F8)
ON: I/O Unit overflow (Error code E1)
ON: I/O setting error (Error code E0)
ON: Remote I/O error (Error codes B0 to B3)
484
Host Link Commands
Limitations
Section 10-3
When errors are being cleared (error clear = 01), the errors are read after the
error clear function is executed.
PC Settings
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
---
An end code of 14 (format error) will be returned if the length of the command is
incorrect.
An end code of 15 (entry number data error) will be returned if the error clear
parameter isn’t set to 00 or 01.
End code
00
Contents
Normal completion
FCS error
13
14
15
18
Format error
Entry number data error
Frame length error
10-3-26
FORCED SET –– KS
Force sets an IR, SR, LR, HR, or AR bit or the Completion Flag of a timer or
counter. Once a bit has been forced set or reset, that status will be retained until
FORCED SET/RESET CANCEL (KC) is transmitted.
Command Format
1
0
3
2
1
0
1
0
ꢀ
↵
x 10 x 10
OP1 OP2 OP3 OP4 x 10 x 10 x 10 x 10 x 10 x 10
@
K
S
Node no.
Header
code
Operand
Word
address
Bit
FCS
Terminator
For data areas IR, SR, LR, HR, and AR, the “Operand” parameter indicates the
data area where the bit will be force-set and the “Word address” parameter indi-
cates the word address.
For the TC area, “Operand” parameter indicates the mnemonic of the timer or
counter instruction and the “Word address” parameter indicates the TC number.
Operand
OP1 OP2 OP3
Data area/
instruction
Word
address
Bit
OP4
00 to 15
IR or SR
C
L
I
O
(Space) 0000 to 0511
LR
R
R
R
I
(Space) (Space) 0000 to 0063
(Space) (Space) 0000 to 0099
(Space) (Space) 0000 to 0027
HR
H
A
T
T
C
C
T
AR
0000 to 0511 Always
00
TIMER
M
M
T
T
I
(Space)
HIGH-SPEED TIMER
COUNTER
I
H
N
N
T
(Space)
REVERS. COUNTER
TOTALIZING TIMER
R
M
TRANSITION FLAGS
T
N
(Space) (Space) 0000 to 1023
485
Host Link Commands
Section 10-3
Response Format
1
0
1
0
ꢀ
↵
x 10 x 10
x 16 x 16
@
K
S
Node no.
Header
code
End code
FCS
Terminator
Limitations
PC Settings
Bits in SR 253 through SR 255 can’t be specified.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
---
OK
OK
OK
OK
Execution Conditions
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
---
End Codes
An end code of 14 (format error) will be returned if the length of the command is
incorrect.
An end code of 15 (entry number data error) will be returned if the operand, word
address, or bit parameter setting is incorrect.
End code
00
Contents
Normal completion
Not executable in RUN mode
FCS error
01
13
14
15
18
Format error
Entry number data error
Frame length error
10-3-27
FORCED RESET –– KR
Force resets an IR, SR, LR, HR, or AR bit or the Completion Flag of a timer or
counter. Once a bit has been forced set or reset, that status will be retained until
FORCED SET/RESET CANCEL (KC) is transmitted.
Command Format
1
0
3
2
1
0
1
0
ꢀ
↵
x 10 x 10
OP1 OP2 OP3 OP4 x 10 x 10 x 10 x 10 x 10 x 10
@
K
R
Node no.
Header
code
Operand
Word
address
Bit
FCS
Terminator
For data areas IR, SR, LR, HR, and AR, the “Operand” parameter indicates the
data area where the bit will be force-set and the “Word address” parameter indi-
cates the word address.
486
Host Link Commands
Section 10-3
For the TC area, “Operand” parameter indicates the mnemonic of the timer or
counter instruction and the “Word address” parameter indicates the TC number.
Operand
OP1 OP2 OP3
Data area/
instruction
Word
address
Bit
OP4
00 to 15
IR or SR
C
L
I
O
(Space) 0000 to 0511
LR
R
R
R
I
(Space) (Space) 0000 to 0063
(Space) (Space) 0000 to 0099
(Space) (Space) 0000 to 0027
HR
H
A
T
T
C
C
T
AR
0000 to 0511 Always
00
TIMER
M
M
T
T
I
(Space)
HIGH-SPEED TIMER
COUNTER
I
H
N
N
T
(Space)
REVERS. COUNTER
TOTALIZING TIMER
R
M
TRANSITION FLAGS
T
N
(Space) (Space) 0000 to 1023
Response Format
1
0
1
0
x 10 x 10
x 16 x 16
ꢀ
↵
@
K
R
Node no.
Header
code
End code
FCS
Terminator
Limitations
PC Settings
Bits in SR 253 through SR 255 can’t be specified.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
---
OK
OK
OK
OK
Execution Conditions
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
---
End Codes
An end code of 14 (format error) will be returned if the length of the command is
incorrect.
An end code of 15 (entry number data error) will be returned if the operand, word
address, or bit parameter setting is incorrect.
End code
00
Contents
Normal completion
Not executable in RUN mode
FCS error
01
13
14
15
18
Format error
Entry number data error
Frame length error
487
Host Link Commands
Section 10-3
10-3-28
MULTIPLE FORCED SET/RESET –– FK
Force sets, force resets, or cancels the forced status of the bits in one word in the
IR, SR, LR, HR, or AR, or a timer/counter Completion Flag.
Command Format
1
0
3
2
1
0
x 10 x 10
OP1 OP2 OP3 OP4 x 10 x 10 x 10 x 10
@
F
K
Node no.
Header
code
Operand
Word
address
ꢀ
↵
Forced set/reset/cancel data
FCS
Terminator
15
14
13
12
11
10
1
0
Bit
For data areas IR, SR, LR, HR, and AR, the “Operand” parameter indicates the
data area where the bit will be force-set and the “Word address” parameter indi-
cates the word address.
For the TC area, “Operand” parameter indicates the mnemonic of the timer or
counter instruction and the “Word address” parameter indicates the TC number.
Operand
OP1 OP2 OP3
Data area/
instruction
Word
address
Bit
OP4
00 to 15
IR or SR
C
L
I
O
(Space) 0000 to 0511
LR
R
R
R
I
(Space) (Space) 0000 to 0063
(Space) (Space) 0000 to 0099
(Space) (Space) 0000 to 0027
HR
H
A
T
T
C
C
T
AR
0000 to 0511 Always
00
TIMER
M
M
T
T
I
(Space)
HIGH-SPEED TIMER
COUNTER
I
H
N
N
T
(Space)
REVERS. COUNTER
TOTALIZING TIMER
R
M
TRANSITION FLAGS
T
N
(Space) (Space) 0000 to 1023
The 16 bytes of forced set/reset/cancel data specifies what operation will be per-
formed on the specified data area word or Completion Flag. If a timer or counter
is specified, the status of the Completion Flag is force-set or force-reset using
the setting for bit 15, and the settings for bits 00 through 14 will be ignored. Only
force-setting and force-resetting are possible for timers/counters.
Forced set/reset/cancel data
0000
Operation
Bit status not changed
0010
0011
0100
0101
1000
Reset to 0.
Set to 1.
Forced-reset
Forced-set
Cancel forced set/reset status
Response Format
1
0
1
0
x 10 x 10
x 16 x 16
ꢀ
↵
@
F
K
Node no.
Header
code
End code
FCS
Terminator
488
Host Link Commands
Section 10-3
Limitations
Bits in SR 253 through SR 255 can’t be specified.
Only 15 timers/counters or 15 Transition Flags can be set/reset.
The UM settings are not checked when Transition Flags are specified, i.e., as
long as the Transition Flag address does not exceed 1023, the command will be
executed normally even if the specified Flag does not actually exist in the remote
PC.
PC Settings
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
---
OK
OK
OK
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
---
An end code of 14 (format error) will be returned if the length of the command is
incorrect. (The forced set/reset/cancel data is 16 bytes long.)
Note With Host Link Units, an error code of 14 (format error) won’t be returned if data
is specified for bit 15 for a timer/counter or Transition Flag. (The forced set/reset/
cancel data can be one byte long or 16 bytes long.)
An end code of 15 (entry number data error) will be returned if the operand, word
address, or bit parameter setting is incorrect. An end code of 15 will also be re-
turned if the a data specification of 0 or 1 is used for a timer or counter Comple-
tion Flag or for a Transition Flag.
An error code of 15 (entry number data error) will be returned if [$C, $D] is speci-
fied for the forced data when set to TC.
End code
00
Contents
Normal completion
Not executable in RUN mode
FCS error
01
13
14
15
18
Format error
Entry number data error
Frame length error
10-3-29
FORCED SET/RESET CANCEL –– KC
Cancels all forced set and forced reset bits (including those set by FORCED
SET, FORCED RESET, and MULTIPLE FORCED SET/RESET). If multiple bits
are set, the forced status will be cancelled for all of them.
Command Format
1
0
x 10 x 10
ꢀ
↵
@
K
C
Node no.
Header
code
FCS
Terminator
Response Format
1
0
1
0
x 10 x 10
x 16 x 16
ꢀ
↵
@
K
C
Node no.
Header
code
End code
FCS
Terminator
489
Host Link Commands
Section 10-3
PC Settings
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
---
OK
OK
OK
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
---
An end code of 14 (format error) will be returned if the length of the command is
incorrect.
End code
00
Contents
Normal completion
FCS error
13
14
18
Format error
Frame length error
10-3-30
PC MODEL READ –– MM
Reads the model type of the PC. The codes returned for this command are differ-
ent from the NT Link codes.
Command Format
1
0
x 10 x 10
ꢀ
↵
@
M
M
Node no.
Header
code
FCS
Terminator
Response Format
1
0
1
0
1
0
x 10 x 10
x 16 x 16 x 16 x 16
ꢀ
↵
@
M
M
Node no.
Header
code
End code
Model
code
FCS
Terminator
“Model code” indicates the PC model in two digits hexadecimal.
Model code
Model
01
02
03
0E
10
11
12
20
21
22
40
41
42
C250
C500
C120
C2000
C1000H
C2000H/CQM1
C20H/C28H/C40H, C200H, C200HS, C200HX/HG/HE
CV500
CV1000
CV2000
CVM1-CPU01-E
CVM1-CPU11-E
CVM1-CPU21-E
PC Settings
PC Mode
MONITOR PROGRAM
OK OK
UM Area
RUN
Write-protected
Read-protected
OK
OK
OK
490
Host Link Commands
Section 10-3
Execution Conditions
Commands
Responses
Single
Multiple
Single
Multiple
OK
---
OK
---
End Codes
An end code of 14 (format error) will be returned if the length of the command is
incorrect.
End code
00
Contents
Normal completion
FCS error
13
14
18
Format error
Frame length error
10-3-31
TEST–– TS
Returns, unaltered, one block of data transmitted from the host computer.
Command Format
Specify any characters other than the carriage return (CHR$(13)).
1
0
ꢀ
↵
x 10 x 10
122 characters max.
Characters
@
T
S
FCS
Terminator
Node no.
Header
code
Response Format
The same characters specified in the command will be returned unaltered if the
test is successful.
1
0
x 10 x 10
122 characters max.
Characters
ꢀ
↵
@
T
S
FCS
Terminator
Node no.
Header
code
PC Settings
PC Mode
UM Area
RUN
OK
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
Execution Conditions
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
---
End Codes
An end code of 14 (format error) will be returned if a terminator isn’t received in
the first frame.
End code
13
Contents
FCS error
14
18
Format error
Frame length error
491
Host Link Commands
Section 10-3
10-3-32
PROGRAM READ –– RP
Reads the contents of the PC user’s program area in machine language (object
code). The contents are read as a block, from the beginning to the end.
Command Format
1
0
x 10 x 10
ꢀ
↵
@
R
P
Node no.
Header
code
FCS
Terminator
Response Format
1
0
1
0
x 10 x 10
x 16 x 16
ꢀ
↵
@
R
P
Node no.
Header
code
End code
1 byte
Program (for entire UM area)
FCS
Terminator
Limitations
The command is valid only when the UM setting is ladder only.
The command can’t be executed if the UM area is read-protected.
Data is read from the beginning of the ladder area to the maximum limit of the
program area. (For example, $A06C0 through $A7FBF when the UM size is 16K
words and none of the UM area is allocated to expansion DM or I/O comments.)
The beginning read address and the length of the response depend on the UM
area settings (such as the amount of memory allocated to expansion DM).
The response’s first frame can contain up to 30 words of program data. The se-
cond and later frames can contain up to 31 words each.
The INITIALIZE and ABORT commands can be sent instead of the delimiter for
multiple responses for this command. If other commands are sent, they will be
treated the same as delimiters.
PC Settings
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
---
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
OK
An end code of 14 (format error) will be returned if the length of the command is
incorrect.
End code
00
Contents
Normal completion
FCS error
13
14
18
23
A3
A8
Format error
Frame length error
User memory protected
Aborted due to FCS error in transmit data
Aborted due to frame length error in transmit data
492
Host Link Commands
Section 10-3
10-3-33
PROGRAM WRITE –– WP
Writes to the PC user’s program area the machine language (object code) pro-
gram transmitted from the host computer. The contents are written as a block,
from the beginning.
Command Format
1
0
1
0
x 10 x 10
x 16 x 16
ꢀ
↵
@
W
P
Node no.
Header
code
1 byte
FCS
Terminator
Program (Up to maximum memory size)
Response Format
1
0
1
0
ꢀ
↵
x 10 x 10
x 16 x 16
@
W
P
Node no.
Header
code
End code
FCS
Terminator
Limitations
The command is valid only when the UM setting is ladder only.
The command can’t be executed if the UM area is write-protected.
Data is written from the beginning of the ladder area to the maximum limit of the
program area. Here are two examples:
1, 2, 3...
1. $A06C0 through $A7FBF when the UM size is 16K words and none of the
UM area is allocated to expansion DM or I/O comments.
2. $A06E0 through $A7FBF when the UM size is 16K words, 1000 words are
allocated to the expansion DM, and none is allocated to I/O comments.
The beginning write address and maximum size of the program depend on the
UM area settings (such as the amount of memory allocated to expansion DM).
An error won’t occur if the command attempts to write program data beyond the
maximum size of the program area.
The program data can be divided into multiple frames.
PC Settings
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
---
---
OK
---
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
OK
Single
Multiple
OK
---
An end code of 14 (format error) will be returned if the length of the command is
incorrect (the total size of the program is an odd number of bytes) or the first
frame contains no program data.
An end code of 15 (entry number data error) will be returned if the specified write
data isn’t hexadecimal.
End code
00
Contents
Normal completion
01
02
13
Not executable in RUN mode
Not executable in MONITOR mode
FCS error
493
Host Link Commands
Section 10-3
End code
14
Contents
Format error
15
18
19
23
A3
A4
A5
A8
Entry number data error
Frame length error
Not executable
User memory protected
Aborted due to FCS error in transmit data
Aborted due to format error in transmit data
Aborted due to entry number data error in transmit data
Aborted due to frame length error in transmit data
10-3-34
I/O TABLE GENERATE –– MI
Corrects the registered I/O table to match the actual I/O table.
Command Format
1
0
ꢀ
↵
x 10 x 10
@
M
I
Node no.
Header
code
FCS
Terminator
Response Format
1
0
1
0
ꢀ
↵
x 10 x 10
x 16 x 16
@
M
I
Node no.
Header
code
End code
FCS
Terminator
PC Settings
PC Mode
UM Area
RUN
MONITOR PROGRAM
--- OK
Write-protected
Read-protected
---
---
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
---
An end code of 14 (format error) will be returned if the length of the command is
incorrect.
End code
00
Contents
Normal completion
01
02
03
13
14
18
20
Not executable in RUN mode
Not executable in MONITOR mode
UM write-protected
FCS error
Format error
Frame length error
Couldn’t create I/O table
Note The write-protected error code for this command is different from the other com-
mands.
494
Host Link Commands
Section 10-3
10-3-35
COMPOUND COMMAND –– QQMR
Registers at the PC all of the bits, words, and timers/counters that are to be read,
and reads the status of all of them as a batch. The registered information is re-
tained in the PC until it is overwritten by the COMPOUND COMMAND or the
PC’s power is turned off.
Command Format
1
0
3
2
1
0
@
x 10 x 10
Q
Q
M
R
OP1 OP2 OP3 OP4 x 10 x 10 x 10 x 10 OP1 OP2
,
Node no.
Header Sub-header
code code
Read area
Read word address
Data
format
Data break
Single read information
Total read information (128 max.)
3
2
1
0
ꢀ
↵
OP1 OP2 OP3 OP4 x 10 x 10 x 10 x 10 OP1 OP2
,
Data break
Read area
Read word address
Data
format
FCS
Terminator
Single read information
Total read information (128 max.)
The “Read area” indicates the data area, the “Read word address” indicates the
word address, and the “Data format” indicates the bit number (00 to 15) or entire
word (CH).
Operand
OP2 OP3
Data area/instruction
Constant or
word address
OP1
OP4
IR or SR
C
I
O
(Space) 0000 to 0511
LR
L
R
R
R
I
(Space) (Space) 0000 to 0063
(Space) (Space) 0000 to 0099
(Space) (Space) 0000 to 0027
HR
H
A
T
T
C
C
T
AR
0000 to 0511
TIMER
M
M
T
T
I
(Space)
HIGH-SPEED TIMER
COUNTER
I
H
N
N
T
(Space)
REVERSIBLE COUNTER
TOTALIZING TIMER
R
M
DM
D
E
E
E
E
M
M
M
M
M
(Space) (Space) 0000 to 6655
(Space) (Space) 0000 to 6143
EM (current bank)
EM (bank 0)
EM (bank 1)
EM (bank 2)
0
0
0
0
1
2
0000 to 6143
0000 to 6143
0000 to 6143
Each word or bit address is specified one item at a time separated by a break
code (,). The maximum number of items that can be specified is 128 unless an
address in the EM area is specified, in which case the maximum is 100. (When
the PV of a timer/counter is specified, the status of the Completion Flag is also
returned, and must therefore be counted as two items.)
Response Format
1
0
1
0
x 10 x 10
x 16 x 16
ꢀ
↵
@
Q
Q
M
R
Node no.
Header
code
Sub-header End code
code
FCS
Terminator
495
Host Link Commands
Section 10-3
Limitations
The registered data is checked from the beginning and the data will be regis-
tered up to any errors. For example, if a command attempts to register 129
items, a frame length error (end code 18) will occur but the first 128 items will be
registered.
DM 6656 to DM 6999 do not exist, but an error will not occur if you try to register
these words.
Bits and words can be specified in any order and they will be registered in the
order that they were specified.
The data can be divided into multiple frames.
PC Settings
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
OK
Execution Conditions
Commands
Responses
Single
OK
Multiple
OK
Single
Multiple
OK
---
End Codes
An end code of 14 (format error) will be returned if the length of the command is
incorrect or the “,” data break between two items is omitted.
An end code of 15 (entry number data error) will be returned if the “Read area,”
“Read word address,” or “Data format” setting is incorrect.
End code
00
Contents
Normal completion
FCS error
13
14
15
18
19
A3
A4
A5
A8
Format error
Entry number data error
Frame length error
Not executable
Aborted due to FCS error in transmit data
Aborted due to format error in transmit data
Aborted due to entry number data error in transmit data
Aborted due to frame length error in transmit data
10-3-36
COMPOUND COMMAND DATA READ –– QQIR
The bit, word, and timer/counter status is read as a batch according to the read
information that was registered with QQMR.
Command Format
1
0
x 10 x 10
ꢀ
↵
@
Q
Q
I
R
Node no.
Header
code
Sub-header
code
FCS
Terminator
496
Host Link Commands
Section 10-3
Response Format
ON/
OFF
1
0
1
0
3
2
1
0
x 10 x 10
x 16 x 16
x 10 x 10 x 10 x 10
@
Q
Q
I
R
,
Data break
Node no.
Header
code
Sub-header End code
code
Timer/Counter
If PV is specified the sta-
tus of the Completion Flag
is also returned.
ON/
OFF
3
2
1
0
,
,
x 16 x 16 x 16 x 16
ꢀ
↵
,
Word data
FCS
Terminator
IR, SR, LR, HR,
AR, DM
Bit data
ON/OFF
Limitations
PC Settings
The data is read in the same order in which it was registered with QQMR.
A response of “0000” will be returned for non-existent words such as DM 6656 to
DM 6999, unallocated expansion DM, or non-existent EM banks.
The INITIALIZE and ABORT commands can be sent instead of the delimiter for
multiple responses for this command. If other commands are sent, they will be
treated the same as delimiters.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
OK
OK
An end code of 14 (format error) will be returned if the length of the command is
incorrect.
An end code of 19 (not executable) will be returned if there is no registered data.
End code
00
Contents
Normal completion
FCS error
13
14
18
19
A3
A8
Format error
Frame length error
Not executable
Aborted due to FCS error in transmit data
Aborted due to frame length error in transmit data
10-3-37
ABORT –– XZ
Aborts the Host Link command that is currently being processed, allowing the
next command to be received. The ABORT command does not receive a re-
sponse.
Command Format
1
0
x 10 x 10
ꢀ
↵
@
X
Z
Node no.
Header
code
FCS
Terminator
497
Host Link Commands
Section 10-3
Limitations
Multiple responses to a command can be cancelled with this command.
This command is valid even without the FCS code and terminator.
PC Settings
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
OK
Execution Conditions
End Codes
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
---
---
There are no end codes with this command.
10-3-38
INITIALIZE –– ꢀꢀ
Initializes the transmission control procedure of all the PCs connected to the
host computer. The INITIALIZE command does not use node numbers or FCS,
and does not receive a response.
Command Format
ꢀ
ꢀ
↵
@
Limitations
PC Settings
Multiple responses to a command can be cancelled with this command.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
OK
Execution Conditions
Commands
Responses
Single
OK
Multiple
---
Single
Multiple
---
---
End Codes
There are no end codes with this command.
10-3-39
TXD RESPONSE –– EX
This is the response format used when the PC’s TXD(––) instruction is executed
in Host Link mode. (TXD(––) converts the specified data into ASCII code and
transmits it to the host computer with this format.)
Response Format
1
0
x 10 x 10
Data specified in TXD(––)
ꢀ
↵
@
E
X
FCS
Terminator
Node no.
Header
code
Characters (122 max.)
Limitations
PC Settings
The frame can contain up to 122 characters. (TXD(––) doesn’t support multiple
frames.)
There is no command associated with EX.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
OK
Read-protected
OK
OK
---
OK
498
Host Link Commands
Section 10-3
Execution Conditions
Commands
Responses
Single
Multiple
Single
Multiple
---
OK
---
---
End Codes
There are no end codes with this command.
10-3-40
Undefined Command –– IC
This response is returned if the header code of a command cannot be decoded.
Check the header code.
Response Format
1
0
x 10 x 10
ꢀ
↵
@
I
C
Node no.
Header
code
FCS
Terminator
Limitations
PC Settings
This error response will be returned if there are fewer than 6 bytes of data be-
tween a command’s “@” character and the terminator, an incorrect header code
is used, or a frame is corrupted.
There is no command associated with IC.
PC Mode
UM Area
RUN
MONITOR PROGRAM
Write-protected
Read-protected
OK
OK
OK
OK
OK
Execution Conditions
End Codes
Commands
Responses
Single
Multiple
---
Single
Multiple
OK
---
---
There are no end codes with this command.
499
Appendix A
Standard Models
CPU Rack
Name
Specifications
Model number
CPU Units (All models are pro-
vided with clock function and slots
for communications except
CPU11-E.)
UM
DM
I/O points
640
RS-232C
No
---
3.2K words
7.2K words
4K words
6K words
C200HE-CPU11-E
C200HE-CPU32-E
C200HE-CPU42-E
C200HG-CPU33-E
C200HG-CPU43-E
C200HG-CPU53-E
C200HG-CPU63-E
C200HX-CPU34-E
C200HX-CPU44-E
C200HX-CPU54-E
C200HX-CPU64-E
C200HW-PA204
880
No
Yes
No
15.2K words 12K words
31.2K words 24K words
100 to 120/200 to 240 VAC
880
Yes
No
1,184
880
Yes
No
Yes
No
1,184
Yes
Power Supply Units
100 to 120/200 to 240 VAC (with 24-VDC output terminals) C200HW-PA204S
24 VDC
C200HW-PD024
CPU I/O Backplanes
3 slots
5 slots
8 slots
10 slots
C200HW-BC031
C200HW-BC051
C200HW-BC081
C200HW-BC101
Communication Boards
Communications port for SYSMAC LINK and SYSMAC NET C200HW-COM01
Link Units
RS-232C port
C200HW-COM02
C200HW-COM03
RS-422/485 port
Communications port for the SYSMAC LINK Unit and SYS- C200HW-COM04-E
MAC NET Link Unit and a protocol macro function
Two RS-232C ports and a protocol macro function
C200HW-COM05-E
C200HW-COM06-E
RS-422/485 port, an RS-232C port, and a protocol macro
function
Memory Cassettes
EEPROM
4K words
8K words
16K words
C200HW-ME04K
C200HW-ME08K
C200HW-ME16K
(see note)
32K words
C200HW-ME32K
C200HS-MP16K
ROM-JD-B
EPROM
16K words/32K words
Equivalent to 27256, 150 ns, 12.5 V
Equivalent to 27512, 150 ns, 12.5 V
ROM-KD-B
Note: The C200HW-ME16K will be released soon. The EEPROM Memory Cassette can be also used with the
C200HS-ME16K.
501
Standard Models
Appendix A
Expansion I/O Racks
Name
Specifications
100 to 120/200 to 240 VAC
Model number
Power Supply Units
C200HW-PA204
100 to 120/200 to 240 VAC (with 24-VDC output terminals)
24 VDC
C200HW-PA204S
C200HW-PD024
Expansion I/O Backplanes
3 slots
5 slots
8 slots
10 slots
C200HW-BI031
C200HW-BI051
C200HW-BI081
C200HW-BI101
I/O Connecting Cables
The total length of the I/O Connecting Cables
used in a network must be 12 m maximum.
30 cm
C200H-CN311
C200H-CN711
C200H-CN221
C200H-CN521
C200H-CN131
70 cm
200 cm
500 cm
1,000 cm
Slave Racks
Name
Specifications
Model number
Slave
Racks
Remote I/O Slave
Units
100 to 120/200 to 240 VAC (switchable)
APF/PCF
Wired
C200H-RT001-P
24 VDC
C200H-RT002-P
C200H-RT201
C200H-RT202
100 to 120/200 to 240 VAC (switchable)
24 VDC
Backplanes
I/O Blocks
3 slots
5 slots
8 slots
10 slots
C200H-BC031-V2
C200H-BC051-V2
C200H-BC081-V2
C200H-BC101-V2
Input
Specify either 12 or 24 VDC.
G71-IC16
Output
G71-OD16
G7TC-IA16
G7TC-ID16
G7TC-OC16
I/O
Terminals
AC input
DC input
Output
Specify either 100 or 200 VAC.
Specify either 12 or 24 VDC.
Specify either 12 or 24 VDC.
502
Standard Models
Appendix A
I/O Units
Name
Specifications
100 to 120 VAC
Model number
Input Units
AC Input Units
8 pts
C200H-IA121
16 pts
8 pts
100 to 120 VAC
200 to 240 VAC
200 to 240 VAC
12 to 24 VDC
24 VDC
C200H-IA122/IA122V
C200H-IA221
16 pts
8 pts
C200H-IA222/IA222V
C200H-ID211
DC Input Units
DC Input Units
AC/DC Input Units
16 pts
8 pts
C200H-ID212
12 to 24 VAC/DC
24 VAC/DC
C200H-IM211
16 pts
8 pts
C200H-IM212
Interrupt Input Unit
(see note)
12 to 24 VDC
C200HS-INT01
Output
Units
Relay Output Units
8 pts
12 pts
5 pts
2 A, 250 VAC/24 VDC (for resistive load)
2 A, 250 VAC/24 VDC (for resistive load)
C200H-OC221
C200H-OC222
C200H-OC223
2 A, 250 VAC/24 VDC (for resistive load)
Independent commons
8 pts
2 A, 250 VAC/24 VDC (for resistive load)
Independent commons
C200H-OC224
C200H-OC225
16 pts
2 A, 250 VAC/24 VDC (for resistive load)
(see note)
Triac Output Units
8 pts
8 pts
12 pts
8 pts
12 pts
16 pts
8 pts
8 pts
1 A, 120 VAC
C200H-OA121-E
C200H-OA223
C200H-OA222V
C200H-OD411
C200H-OD211
C200H-OD212
C200H-OD213
C200H-OD214
1.2 A, 250 VAC
0.3 A, 250 VAC
1 A, 12 to 48 VDC
0.3 A, 24 VDC
Transistor Output
Units
0.3 A, 24 VDC (see note)
2.1 A, 24 VDC
0.8 A, 24 VDC; source type (PNP); w/load
short protection
8 pts
0.3 A, 5 to 24 VDC; source type (PNP)
0.3 A, 5 to 24 VDC; source type (PNP)
C200H-OD216
C200H-OD217
12 pts
16 pts
1.0 A, 24 VDC; source type (PNP); with load C200H-OD21A
short protection
Analog Timer Unit
4 timers 0.1 to 1 s/1 to 10 s/10 to 60 s/1 min to 10 min C200H-TM001
(switchable)
Variable
Connector w/lead wire (2 m) for 1 external resistor
C4K-CN223
Resistor
Connector
503
Standard Models
Appendix A
Name
Specifications
Model number
B7A Interface Units
15 or 16 Connects to B7A Link Terminals. Standard
input pts transmission delay.
C200H-B7AI1
16
output
Connects to B7A Link Terminals. Standard
transmission delay.
C200H-B7AO1 (see
note)
pts
Note: If the Interrupt Input Unit is mounted on an Expansion I/O Rack, the interrupt function cannot be used and
the Interrupt Input Unit will be treated as an ordinary 8-point Input Unit. Moreover, Interrupt Input Units can-
not be used on Slave Racks. In addition, Interrupt Input Units require that a version 2 (i.e., model numbers
with a “-V2” suffix) Backplane be used at the CPU Rack. If an earlier version Backplane is mounted, the
interrupt function cannot be used. When mounting the C200H-OC225, C200H-OD212, or C200H-B7AO1
to a Backplane, make sure that the model number of the Backplane includes the suffix “-V1” or “-Vj.” The
C200H-OC225, C200H-OD212, or C200H-B7AO1 cannot be mounted to any Backplane the model num-
ber of which does not include the suffix “-V1” or “-Vj.”
Group-2 I/O Units
Name
Specifications
12 VDC
Model number
C200H-ID111
C200H-ID216
C200H-ID217
C200H-OD218
C200H-OD219
C200H-OD21B
DC Input Units
64 pts
32 pts
64 pts
32 pts
64 pts
32 pts
24 VDC
Transistor Output
Units
16 mA at 4.5 V to 100 mA at 26.4 V
24 VDC 0.5 A (5 A/unit)
B7A Interface Units
32 input pts
Connects to B7A Link Terminals.
Standard or high-speed transmission
delay.
C200H-B7A12
C200H-B7A02
C200H-B7A21
32 output pts
16 input and 16
output points
32 input and 32
output points
C200H-B7A22
Special I/O Units
Name
Specifications
Model number
C200H-ID501
C200H-ID215
C200H-OD215
High-density DC Input Units
I/O Units
32 pts
32 pts
32 pts
5 VDC (TTL inputs); w/high-speed input
24 VDC; w/high-speed input
(see note)
Transistor Output
Units
0.1 A, 24 VDC (useable as 128-point
dynamic output unit)
32 pts
35 mA, 5 VDC (TTL outputs) (useable as C200H-OD501
128-point dynamic output unit)
DC Input/Transistor
Output Units
16 input and 16 24-VDC inputs; w/high-speed input; 0.1-A, C200H-MD215
output pts
24-VDC outputs (useable as 128-point
dynamic input unit)
16 input and 16 5-VDC TTL inputs; w/high speed input;
C200H-MD501
C200H-MD115
output pts
35-mA, 5-VDC TTL outputs (useable as
128-point dynamic input unit)
16 input and 16 12-VDC TTL inputs; w/high speed input;
output pts
12-VDC TTL outputs (useable as
128-point dynamic input unit)
504
Standard Models
Appendix A
Name
Specifications
Model number
Analog I/O
Units
Analog Input Units
4 to 20 mA, 1 to 5/0 to 10 V (switchable); 4 inputs; 12 bits
C200H-AD001
4 to 20 mA, 1 to 5/0 to 10 V/–10 to 10V (switchable); 8
C200H-AD002
inputs; 12 bits or BCD
Analog Output Unit
Fuzzy Logic Unit
4 to 20 mA, 1 to 5/0 to 10 V (switchable); 2 outputs
C200H-DA001
C200H-FZ001
Programmed using the Fuzzy Support Software. Up to 8
inputs and 4 outputs.
Fuzzy Support
Available on either 3.5” or 5.25” floppy disks.
C500-SU981-E
Software
Temperature Sensor Units
Thermocouple
K(CA) or J(IC), switchable; 4 inputs
C200H-TS001
C200H-TS002
K(CA) or L(Fe-CuNi) DIN standards;
4 inputs
Pt resistance
thermometer
Pt 100 Ω; 4 inputs
Pt 100 Ω; 4 inputs; DIN and 1989 JIS
standards
C200H-TS101
C200H-TS102
Temperature Control Units
Thermocouple
Transistor output
Voltage output
Current output
Transistor output
C200H-TC001
C200H-TC002
C200H-TC003
C200H-TC101
Pt resistance
thermometer
Voltage output
Current output
C200H-TC102
C200H-TC103
Heat/Cool
Temperature Control Units
Thermocouple
Transistor output
Voltage output
Current output
Transistor output
C200H-TV001
C200H-TV002
C200H-TV003
C200H-TV101
Pt resistance
thermometer
Voltage output
Current output
C200H-TV102
C200H-TV103
C200H-CP114
Cam Positioner Unit
Data Setting Console
Detects angles of rotation by means of a resolver and
provides ON and OFF outputs at specified angles. A
maximum of 48 cam outputs (16 external outputs and 32
internal outputs) maximum are available.
Used to set and monitor data in Temperature Control Units, C200H-DSC01
Cam Positioner Units, PID Control Units, and Heat/Cool
Temperature Control Units.
Connecting Cables
PID Control Units
2 m
4 m
C200H-CN225
C200H-CN425
C200H-PID01
Transistor output; 4 to 20 mA/1 to 5 V/0 to 5V/0 to 10 V
inputs (selectable)
Voltage output; 4 to 20 mA/1 to 5 V/0 to 5V/0 to 10 V inputs C200H-PID02
(selectable)
Current output; 4 to 20 mA/1 to 5 V/0 to 5V/0 to 10 V inputs C200H-PID03
(selectable)
505
Standard Models
Appendix A
Name
Specifications
Model number
C200H-NC111
C200H-NC112
Position Control Units
1 axis
1 axis
Pulse output; speeds: 1 to 100,000 pps
Pulse output; directly connects to
servomotor driver; compatible with line
driver; speeds: 1 to 250,000 pps
1 axis
2 axes
2 axes
4 axes
1 axis
1 axis
2 axes
Pulse output; directly connects to
servodriver
C200HW-NC113
C200H-NC211
C200HW-NC213
C200HW-NC413
C200H-CT001-V1
C200H-CT002
C200H-CT021
C200H-ASC02
Pulse output; speeds: 1 to 250,000 pps,
53 pts per axis
Pulse output; directly connects to
servodriver
Pulse output; directly connects to
servodriver
High-speed Counter Units
Pulse input; counting speed: 50 kcps; 5
VDC/12 VDC/24 VDC
Pulse input; counting speed: 75 kcps;
RS-422 line driver
Pulse input; counting speed: 75 kcps;
RS-422 line driver; 7-digit BCD
ASCII Unit
24K-byte RAM and 24K-byte EEPROM are built-in.
ID Sensor Units
Local application, electromagnetic coupling
Remote application; microwave transmissions
Electromagnetic type
C200H-IDS01-V1
C200H-IDS21
V600-H series
V620-H series
Read/Write Heads
Microwave type
Data Carriers
SRAM type for V600-H series.
EEPROM type for V600-H series.
V600-D
V600-D
j
j
j
R
j
j
j
P
j
j
Voice Unit
60 messages max.; message length: 32, 48, or 64 s
(switchable)
C200H-OV001
Connecting Cable
RS-232C
C200H-CN224
Note: When mounting a High-density I/O Unit as a Special I/O Unit to a Slave Rack, the Remote I/O Master must
be the C200H-RM001-PV1 or C200H-RM201.
Communication Units
Name
Specifications
Model number
SYSMAC LINK Unit
(coaxial cable)
A Bus Connection Unit must be ordered Data link table:
C200HW-SLK23
separately.
918 words
Data link table:
2,966 words
C200HW-SLK24
Terminator
One required for each node at ends of System.
Provided with SYSMAC LINK Unit.
C1000H-TER01
C200H-TL001
Attachment
Stirrup
F Adapter
To connect network
To connect network
C1000H-CE001
C1000H-COV01
F Adapter
Cover
506
Standard Models
Appendix A
Name
Specifications
Connect with H-PCF cable. A Bus
Connection Unit must be ordered
separately.
Model number
SYSMAC LINK Unit
(optical fiber cable)
Data link table:
918 words
C200HW-SLK13
Data link table:
2,966 words
C200HW-SLK14
C200H-APS03
Power Supply
Required when supplying backup power
For 1 or 2
Adapter
Units
Power Cable
Connects Power Supply Adapter and SYSMAC
NET Link Unit.
For 1 Unit
For 2 Units
C200H-CN111
C200H-CN211
3G8F5-SLK21-E
SYSMAC LINK Support
Board (coaxial cable)
To connect IBM PC/AT or compatible as node in SYSMAC LINK
system
SYSMAC NET Link Unit
A Bus Connection Unit must be ordered separately.
C200HS-SNT32
C200H-APS01
C200H-APS02
C200H-CN001
Power Supply
Adapter
Required when supplying backup power
For 1 Unit
For 2 Units
For 1 Unit
Power Cable
Connects Power Supply Included with
Adapter and SYSMAC NET C200H-APS01
Link Unit.
Included with
C200H-APS02
For 2 Units
C200H-CN002
C200HW-CE001
C200HW-CE002
Bus Connection Units
Host Link Units
Connects SYSMAC LINK Unit or SYSMAC NET For 1 Unit
Link Unit to C200HW-COM01/COM04-E
Communications Board
For 2 Units
Rack-mounting
C200H, C200HS,
C200HE,
C200HG, C200HX RS-422
APF/PCF
C200H-LK101-PV1
C200H-LK202-V1
C200H-LK201-V1
C200H-LK401
RS-232C
PC Link Unit
Single level: 32 Units
Multilevel: 16 Units
RS-485
Remote I/O Master
Units
Up to two per PC; connectable to up to 5 Slaves APF/PCF
per PC total
C200H-RM001-PV1
C200H-RM201
Wired
Remote I/O Slave Units
See Racks at beginning of product lists.
SYSMAC NET/SYSMAC LINK Hardware
Name
Specifications
Model number
S3200-NSB11-E
3G8F5-SLK21-E
SYSMAC NET Network Support Board For IBM PC/AT or compatible
SYSMAC LINK Network Support
Board
For IBM PC/AT or compatible, coaxial cable connector
507
Standard Models
Appendix A
Link Adapters
Name
Specifications
Model number
3G2A9-AL001
Link Adapters
3 RS-422 connectors
3 optical connectors (APF/PCF)
3G2A9-AL002-PE
3G2A9-AL002-E
3G2A9-AL003
3 optical connectors (PCF)
1 connector for RS-232C; 2 for RS-422
1 connector each for APF/PCF, RS-422, and RS-232C
1 connector each for PCF, RS-422, and RS-232C
1 connector each for APF/PCF and AGF
1 connector each for PCF and AGF
1 connector for APF/PCF; 2 for AGF
1 connector for PCF; 2 for AGF
3G2A9-AL004-PE
3G2A9-AL004-E
3G2A9-AL005-PE
3G2A9-AL005-E
3G2A9-AL006-PE
3G2A9-AL006-E
B500-AL007-P
O/E converter; 1 connector for RS-485, 1 connector each for
APF/PCF
Used for on-line removal of SYSMAC NET Link Units from the
SYSMAC NET Link System, SYSMAC NET Optical Link Adapter 3
connectors for APF/PCF.
B700-AL001
Optical Fiber Products
Optical Fiber Cable for SYSMAC NET and SYSMAC LINK
H-PCF Optical Fiber Cable with Connectors
System
Appearance
Model number
SYSMAC NET
SYSMAC LINK
S3200-CN
S3200-CN
S3200-CN
S3200-CN
S3200-CN
S3200-CN
j
j
j
j
j
j
j
j
j
j
j
j
j -20-20
j -20-25
j -20-62
j -25-25
j -25-62
j -62-62
508
Standard Models
Appendix A
Model Numbers
The above cable model numbers specify the type of cable, the length, and the type of connectors attached.
S3200-CN
j
j
2.
j
-
2
0
-
2
5
1.
3.
1. S3200-CN specifies H-PCF optical fiber cable.
2. The boxes (j jj) are replaced by codes indicating the standard model lengths, as shown below.
Consult with your OMRON representative for longer cables. When ordering longer cables, omit the portion
represented by the boxes and specify the length in meters separately, e.g., S3200-CN-20-20, 30 m.
Code
201
Length
2 m
Code
152
Length
15 m
501
102
5 m
202
20 m
10 m
Omitted
Over 20 m
3. The last two portions of the model numbers (e.g., 20-25) specify the connectors, as shown below.
Code
Connector
20
25
62
S3200-COCF2011
S3200-COCF2511
S3200-COCH62M
Applicable Optical Fiber Connectors
Model number/Appearance
Applicable Units
SYSMAC NET
CV500-SNT31
SYSMAC LINK
CV500-SLK11
C1000H-SLK11
S3200-COCF2011
S3200-COCF2511
C200HS-SNT32
C200HW-SLK13/14
S3200-COCH62M
S3200-LSU03-01E
S3200-NSUA1-00E
S3200-NSUG4-00E
S3200-NSB11-E
C500-SNT31-V4
B700-AL001
---
All Plastic Optical Fiber Cable for SYSMAC BUS
Name
Specifications
Model number Standards
3G5A2-PF002
Cable only; order desired length in 5 m increments
between 5 and 100 m, or in increments of 200 m or
500 m.
All Plastic Optical Fiber Cable
---
Optical Connectors A
Optical Connectors B
Two optical connectors (brown) for APF (10 m max.) 3G5A2-CO001
Two optical connectors (black) for APF (8 to 20 m) 3G5A2-CO002
All Plastic Optical Fiber Cable
Set
1-m cable with an Optical Connector A connected to 3G5A2-PF101
each end
Optical Fiber Processing Kit
Accessory: 125-mm nipper (Muromoto Tekko’s 550M) 3G2A9-TL101
for APF
509
Standard Models
Appendix A
Plastic Clad Optical Fiber Cable for SYSMAC BUS
Name
Specifications
Model number
3G5A2-OF011
3G5A2-OF101
3G5A2-OF201
3G5A2-OF301
3G5A2-OF501
3G5A2-OF111
3G5A2-OF211
3G5A2-OF311
3G5A2-OF411
3G5A2-OF511
3G5A2-OF002
Standards
Plastic Clad Optical Fiber
Cables (indoor)
Ambient temp:
–10° to 70°C
0.1 m, w/connectors
1 m, w/connectors
2 m, w/connectors
3 m, w/connectors
5 m, w/connectors
10 m, w/connectors
20 m, w/connectors
30 m, w/connectors
40 m, w/connectors
50 m, w/connectors
---
Cable only; order desired length be-
tween 1 and 500 m in increments of
1 m.
Cable only; order desired length be- Ambient temp:
tween 501 and 800 m in increments 0° to 55°C (do
of 1 m.
not expose to di-
rect sunlight)
H-PCF Optical Fiber Cables (For SYSMAC NET, SYSMAC LINK, and SYSMAC BUS)
Name
Specifications
Model number
Stan-
dards
Optical Fiber Cables
SYSMAC NET, SYSMAC LINK
Composite
10 m, black
50 m, black
S3200-HCLB101
S3200-HCLB501
S3200-HCLB102
S3200-HCLB502
S3200-HCLB103
S3200-HCLO101
S3200-HCLO501
S3200-HCLO102
S3200-HCLO502
S3200-HCLO103
---
---
---
cable including
two-core cable
and two-core
power supply
cable
100 m, black
500 m, black
1,000 m, black
10 m, orange
50 m, orange
100 m, orange
500 m, orange
1,000 m, orange
10 m, black
Optical Fiber Cables
SYSMAC NET, SYSMAC LINK,
SYSMAC BUS, SYSMAC WAY
Two-core cable S3200-HCLB101
S3200-HCCB501
50 m, black
100 m, black
500 m, black
1000 m, black
10 m, orange
50 m, orange
100 m, orange
500 m, orange
1,000 m, orange
10 m, black
S3200-HCCB102
S3200-HCCB502
S3200-HCCB103
S3200-HCCO101
S3200-HCCO501
S3200-HCCO102
S3200-HCCO502
S3200-HCCO103
Two-core cord
S3200-HBCB101
S3200-HBCB501
S3200-HBCB102
S3200-HBCB502
S3200-HBCB103
50 m, black
100 m, black
500 m, black
1,000 m, black
510
Standard Models
Appendix A
Name
Specifications
Model number
Stan-
dards
SYSMAC NET:
Full-lock con-
nector for NSU,
NSB, and C500
SYSMAC NET
Link Unit
S3200-COCH62M ---
Optical Fiber Cable Connector
S3200-LSU03-01E
B700-AL001
C500-SNT31-V4
SYSMAC BUS:
Half-lock con-
nector for Re-
mote I/O Mas-
ter, Remote I/O
Slave, Host Link
Unit, and Link
Adapter
S3200-COCH82
C200H-RM001-PV1
C200H-RT001/RT002-P
C500-RM001-(P)V1
C500-RT001/RT002-(P)V1
3G2A9-
j
j
j
(
-
P
)
SYSMAC NET/SYSMAC LINK
C200HS-SNT32
Half-lock con-
nector
S3200-COCF2511
S3200-COCF2011
C200HW-SLK13/14
SYSMAC NET/SYSMAC LINK
CV500-SNT31
Full-lock con-
nector
CV500-SLK11
CV1000H-SLK11
S3200-COCF62M
S3200-COCF62F
To relay at all SYSMAC NET
nodes.
COCF62M and
COCF62F are
used as a pair.
Note: 1. Optical fiber cables must be prepared and connected by specialists.
2. If the user prepares and connects optical fiber cables, the user must take a seminar held under the aus-
pices of Sumitomo Electric Industries, Ltd. and obtain a proper certificate.
3. The Optical Power Tester, Head Unit, Master Fiber Set, and Optical Fiber Assembling Tool are required to
connect optical fiber cables.
4. You may want to use the Plastic Clad Optical Fiber Cable/All Plastic Optical Fiber Cable with connectors
listed on the previous two pages.
Optical Fiber Assembling Tool
Name
Specifications
Model number
Stan-
dards
Optical Fiber Assembling Tool
Used to connect H-PCF and crimp-cut connectors
for optical transmission systems such as the SYS-
MAC C- and CV-series SYSMAC BUS, SYSMAC
LINK and SYSMAC NET.
S3200-CAK1062
---
Note: 1. Optical fiber cables must be prepared and connected by specialists.
2. The Optical Power Tester, Head Unit, Master Fiber set, and Optical Fiber Assembling Tool are required to
connect optical fiber cables.
511
Standard Models
Appendix A
Optical Power Tester
Name
Specifications
SYSMAC NET:
Head Unit
Model number
Stan-
dards
Optical Power Tester (see note)
(provided with a connector
adapter, light source unit, small
single-head plug, hard case,
and AC adapter)
---
S3200-CAT200 S3200-CAT2000
2 (provided with
the Tester)
CV500-SNT31
C200HS-SNT32
SYSMAC LINK:
CV500-SLK11
S3200-CAT270 S3200-CAT2700
2 (provided with
C200HW-SLK13/14
CV1000H-SLK11
the Tester)
SYSMAC BUS:
S3200-CAT282 S3200-CAT2820
2 (provided with
the Tester)
C200H-RM001-PV1
C200H-RT001/RT002-P
C500-RM001-(P)V1
C500-RT001/RT002-(P)V1
SYSMAC NET:
S3200-CAT320 S3200-CAT3200
2 (provided with
the Tester)
S3200-LSU03-01E
C500-SNT31-V4
Note: There is no difference between the light source unit and connector adapter for the Head Unit and those for
the Optical Power Tester.
Head Unit
Name
Specifications
Model number
Stan-
dards
Head Units (a set consisting of
light source unit and connector
adapter)
---
SYSMAC NET:
CV500-SNT31
S3200-CAT2002
C200HS-SNT32
(see note)
SYSMAC LINK:
CV500-SLK11
S3200-CAT2702
S3200-CAT2822
C200HW-SLK13/14
CV1000H-SLK11
SYSMAC BUS:
C500-RM001-(P)V1
C500-RT001/RT002-(P)V1
C200H-RM001-PV1
C200H-RT001/RT002-PV1
SYSMAC NET:
S3200-CAT3202
S3200-LSU03-01E
C500-SNT31-V4
Note: Use a proper Head Unit model for the optical module to be used. If two types of optical modules (unit type
and board type) are used, order an Optical Power Tester plus a proper Head Unit model.
Master Fiber Set
Name
Specifications
Model number
S3200-CAT3201
S3200-CAT2001H
S3200-CAT2821
Stan-
dards
Master Fiber Sets (1 m)
S3200-CAT3202 (SYSMAC NET, NSB, NSU,
Bridge)
---
S3200-CAT2002/CAT2702 (SYSMAC NET, SYS-
MAC LINK)
S3200-CAT2822 (SYSMAC BUS)
Note: 1. The Master Fiber Set is used in combination with the Optical Power Tester to check the optical levels of
optical fiber cables connected to optical fiber cable connectors.
2. Optical fiber cables must be prepared and connected by specialists.
3. The Optical Power Tester, Head Unit, Master Fiber set, and Optical Fiber Assembling Tool are required to
connect optical fiber cables.
512
Standard Models
Appendix A
Programming Devices
Name
Specifications
Model number
Stan-
dards
Hand-Held, w/backlight
C200H-PRO27-E
U, C
U, C
---
Programming Consoles
2-m Connecting Cable included
CQM1-PRO01-E
Programming Console
Mounting Bracket
Used to attach Hand-held Programming Console to a C200H-ATT01
panel.
For Hand-held Programming Con-
sole
2 m
4 m
C200H-CN222
C200H-CN422
---
---
Programming Console
Connecting Cables
Data Setting Console
Used for data input and process value display for the C200H-DSC01
C200H-TC
j
j
j
,
C
2
0
0
H
-
T
V
j
j
j
,
C
2
0
0
H
-
C
P
1
1
4
,
and C200H-PID0j .
For C200H-DSC01
2 m
C200H-CN225
C200H-CN425
CQM1-CIF02
Data Setting Console
Connecting Cables
4 m
Connecting Cable
Used to connect an IBM PC/AT or
compatible to the C200HX/HG/HE.
3.3 m
---
Optional Products
Name
Specifications
Model number
Standards
I/O Unit Cover
Cover for 10-pin terminal block
C200H-COV11
---
Terminal Block Cov-
ers
Short protection for 10-pin terminal block (package of 10 cov- C200H-COV02
ers); 8 pts
Short protection for 19-pin terminal block (package of 10 cov- C200H-COV03
ers); 12 pts
Connector Cover
Space Unit
Protective cover for unused I/O Connecting Cable connectors C500-COV02
Used for vacant slots
C200H-SP001
C200H-BAT09
N, L
---
Battery Set
For C200H or C200HS RAM Memory Unit only
513
Standard Models
Appendix A
Name
Specifications
Model number
Standards
Relay
24 VDC
G6B-1174P-FD-US ---
Backplane Insula-
tion Plates
For C200HW-BC031 (3-slot CPU Backplane)
For C200HW-BC051 (5-slot CPU Backplane)
For C200HW-BC081 (8-slot CPU Backplane)
For C200HW-BC101 (10-slot CPU Backplane)
For C200HW-BI031 (3-slot I/O Backplane)
For C200HW-BI051 (5-slot I/O Backplane)
For C200HW-BI081 (8-slot I/O Backplane)
For C200HW-BI101 (10-slot I/O Backplane)
For 3-slot Backplane
C200H-ATT31
C200H-ATT51
C200H-ATT81
C200H-ATTA1
C200HW-ATT32
C200HW-ATT52
C200HW-ATT82
C200HW-ATTA2
C200H-ATT33
C200H-ATT53
C200H-ATT83
C200H-ATTA3
C500-CE401
---
I/O Brackets
N
For 5-slot Backplane
For 8-slot Backplane
For 10-slot Backplane
---
---
---
---
---
---
External Connectors
Solder terminal; 40p and a Connector Cover
Solderless terminal; 40p and a Connector Cover (Crimp-type) C500-CE402
Pressure welded terminal; 40p C500-CE403
Solder terminal; 40p and a Connector Cover (Horizontal-type) C500-CE404
Crimp-style terminal; 40p and a Connector Cover (Horizontal- C500-CE405
type)
Mounting Rails and Accessories
Name
Specifications
Model number
Standards
---
DIN Track
1 set (2 included)
C200H-DIN01
Mounting Bracket
DIN Tracks
Length: 50 cm; height: 7.3 cm
Length: 1 m; height: 7.3 cm
Length: 1 m; height: 16 mm
---
PFP-50N
PFP-100N
PFP-100N2
PFP-M
End Plate
Spacer
---
PFP-S
Note: Order DIN Tracks, End Plates, and Spacers in units of 10 each.
SYSMAC Support Software (SSS)
Name
Specifications
Model number
Stan-
dards
SYSMAC Support Soft-
3.5”, 2HD for IBM PC/AT compatible
C500-ZL3AT1-E
---
ware (for C20, C
j K, C120, C
C200H, C200HS,
j
j
j P,
j H,
Note: Version 1.0 doesn’t support the additional
functions of the C200HX/HG/HE.
C
j
C200HE, C200HG,
C200HX, C500, C1000H,
C2000H, CQM1, and
CVM1)
514
Standard Models
Appendix A
Protocol Support Software
Name
Specifications
Model number
Stan-
dards
Protocol Support Software
3.5”, 2HD for IBM PC/AT compatible
C200HW-ZW3AT1-E ---
Training Materials
Name
Specifications
Model number
Stan-
dards
SYSMAC Training System
Fuzzy Training System
Includes text book, cassette tape, and input
switch board.
C200H-ETL01-E
---
Includes a Fuzzy Training System Manual, a Main C200H-ETL13-E
Unit, a C200H-MR831 Memory Unit, a C200H-
PRO27-E Programming Console, a C200H-
CN222 Cable for the Programming Console,
C500-SU981-E Fuzzy Training Software, an
RS-232C Cable, and a carrying belt.
---
515
Appendix B
Programming Instructions
A PC instruction is input either by pressing the corresponding Programming Console key(s) (e.g., LD, AND, OR,
NOT) or by using function codes. To input an instruction with its function code, press FUN, the function code, and
then WRITE. Refer to the pages listed programming and instruction details.
Code
Mnemonic
Name
Function
Page
149
—
AND
AND
Logically ANDs status of designated bit with execution
condition.
—
—
AND LD
AND LOAD
Logically ANDs results of preceding blocks.
150
149
AND NOT AND NOT
Logically ANDs inverse of designated bit with execution
condition.
—
—
CNT
LD
COUNTER
LOAD
A decrementing counter.
166
149
Used to start instruction line with the status of the desig-
nated bit or to define a logic block for use with AND LD
and OR LD.
—
—
LD NOT
OR
LOAD NOT
OR
Used to start instruction line with inverse of designated bit. 149
Logically ORs status of designated bit with execution
condition.
149
—
—
OR LD
OR LOAD
OR NOT
Logically ORs results of preceding blocks.
150
149
OR NOT
Logically ORs inverse of designated bit with execution
condition.
—
—
OUT
OUTPUT
Turns ON operand bit for ON execution condition; turns
OFF operand bit for OFF execution condition.
150
150
OUT NOT OUTPUT NOT
Turns operand bit OFF for ON execution condition; turns
operand bit ON for OFF execution condition (i.e., inverts
operation).
—
—
RSET
SET
RESET
SET
Turns the operand bit OFF when the execution condition is 153
ON, and does not affect the status of the operand bit when
the execution condition is OFF.
Turns the operand bit ON when the execution condition is 153
ON, and does not affect the status of the operand bit when
the execution condition is OFF.
—
TIM
TIMER
ON-delay (decrementing) timer operation.
159
158
00
NOP
NO OPERATION
Nothing is executed and program moves to next instruc-
tion.
01
02
END
IL
END
Required at the end of the program.
158
155
If interlock condition is OFF, all outputs are turned OFF
and all timer PVs reset between this IL(02) and the next
ILC(03). Other instructions are treated as NOP; counter
PVs are maintained.
INTERLOCK
03
ILC
INTERLOCK CLEAR
155
If jump condition is OFF, all instructions between JMP(04)
and the corresponding JME(05) are ignored.
04
JMP
JME
FAL
JUMP
157
157
300
05
JUMP END
(@)06
FAILURE ALARM
AND RESET
Generates a non-fatal error and outputs the designated
FAL number to the Programming Console.
07
08
FALS
STEP
SEVERE FAILURE
ALARM
Generates a fatal error and outputs the designated FALS
number to the Programming Console.
300
291
STEP DEFINE
When used with a control bit, defines the start of a new
step and resets the previous step. When used without N,
defines the end of step execution.
09
SNXT
STEP START
Used with a control bit to indicate the end of the step, reset 291
the step, and start the next step.
10
11
12
SFT
SHIFT REGISTER
KEEP
Creates a bit shift register.
171
KEEP
CNTR
Defines a bit as a latch controlled by set and reset inputs. 154
REVERSIBLE
COUNTER
Increases or decreases PV by one whenever the incre-
ment input or decrement input signals, respectively, go
from OFF to ON.
169
517
Programming Instructions
Appendix B
Code
13
Mnemonic
Name
Function
Page
DIFU
DIFFERENTIATE UP
Turns ON the designated bit for one cycle on the rising
edge of the input signal.
151
14
DIFD
DIFFERENTIATE
DOWN
Turns ON the bit for one cycle on the trailing edge.
151
15
TIMH
HIGH-SPEED TIMER A high-speed, ON-delay (decrementing) timer.
164
178
(@)16
WSFT
WORD SHIFT
Shifts data between starting and ending words in word
units, writing zeros into starting word.
17 to 19 For expansion instructions.
20
CMP
COMPARE
Compares the contents of two words and outputs result to 193
GR, EQ, and LE Flags.
(@)21
(@)22
MOV
MVN
MOVE
Copies source data (word or constant) to destination word. 180
MOVE NOT
Inverts source data (word or constant) and then copies it to 180
destination word.
(@)23
(@)24
(@)25
(@)26
BIN
BCD TO BINARY
BINARY TO BCD
Converts four-digit, BCD data in source word into 16-bit
binary data, and outputs converted data to result word.
204
BCD
ASL
ASR
Converts binary data in source word into BCD, and outputs 205
converted data to result word.
ARITHMETIC SHIFT
LEFT
Shifts each bit in single word of data one bit to left, with CY. 175
ARITHMETIC SHIFT
RIGHT
Shifts each bit in single word of data one bit to right, with
CY.
175
(@)27
(@)28
(@)29
(@)30
ROL
ROR
COM
ADD
ROTATE LEFT
ROTATE RIGHT
COMPLEMENT
BCD ADD
Rotates bits in single word of data one bit to left, with CY.
176
Rotates bits in single word of data one bit to right, with CY. 176
Inverts bit status of one word of data.
275
229
Adds two four-digit BCD values and content of CY, and
outputs result to specified result word.
(@)31
(@)32
(@)33
(@)34
SUB
MUL
DIV
BCD SUBTRACT
BCD MULTIPLY
BCD DIVIDE
Subtracts a four-digit BCD value and CY from another
four-digit BCD value and outputs result to the result word.
231
235
236
276
Multiplies two four-digit BCD values and outputs result to
specified result words.
Divides four-digit BCD dividend by four-digit BCD divisor
and outputs result to specified result words.
ANDW
LOGICAL AND
Logically ANDs two 16-bit input words and sets corre-
sponding bit in result word if corresponding bits in input
words are both ON.
(@)35
(@)36
(@)37
ORW
LOGICAL OR
Logically ORs two 16-bit input words and sets correspond- 277
ing bit in result word if one or both of corresponding bits in
input data are ON.
XORW
XNRW
EXCLUSIVE OR
EXCLUSIVE NOR
Exclusively ORs two 16-bit input words and sets bit in re-
sult word when corresponding bits in input words differ in
status.
278
Exclusively NORs two 16-bit input words and sets bit in
result word when corresponding bits in input words are
same in status.
279
(@)38
(@)39
(@)40
(@)41
45
INC
BCD INCREMENT
BCD DECREMENT
SET CARRY
Increments four-digit BCD word by one.
Decrements four-digit BCD word by one.
Sets carry flag (i.e., turns CY ON).
Clears carry flag (i.e., turns CY OFF).
Initiates data tracing.
228
228
229
229
302
DEC
STC
CLC
TRSM
CLEAR CARRY
TRACE MEMORY
SAMPLE
(@)46
MSG
MESSAGE
Displays a 16-character message on the Programming
Console display.
303
47 & 48
(@)50
For expansion instructions.
ADB
BINARY ADD
Adds two four-digit hexadecimal values and content of CY, 243
and outputs result to specified result word.
(@)51
SBB
BINARY SUBTRACT
Subtracts a four-digit hexadecimal value and CY from
another four-digit hexadecimal value and outputs result to
the result word.
245
518
Programming Instructions
Appendix B
Code
Mnemonic
Name
Function
Page
(@)52
MLB
BINARY MULTIPLY
Multiplies two four-digit hexadecimal values and outputs
result to specified result words.
248
(@)53
(@)54
(@)55
DVB
BINARY DIVIDE
Divides four-digit hexadecimal dividend by four-digit hexa- 248
decimal divisor and outputs result to specified result words.
ADDL
SUBL
DOUBLE BCD ADD
Adds two eight-digit values (2 words each) and content of 230
CY, and outputs result to specified result words.
DOUBLE BCD
SUBTRACT
Subtracts an eight-digit BCD value and CY from another
eight-digit BCD value and outputs result to the result
words.
233
(@)56
(@)57
(@)58
MULL
DIVL
BINL
DOUBLE BCD
MULTIPLY
Multiplies two eight-digit BCD values and outputs result to 236
specified result words.
DOUBLE BCD
DIVIDE
Divides eight-digit BCD dividend by eight-digit BCD divisor 237
and outputs result to specified result words.
DOUBLE BCD TO
DOUBLE BINARY
Converts BCD value in two consecutive source words into 205
binary and outputs converted data to two consecutive re-
sult words.
(@)59
BCDL
DOUBLE BINARY TO Converts binary value in two consecutive source words
206
182
DOUBLE BCD
into BCD and outputs converted data to two consecutive
result words.
60 to 69 For expansion instructions.
(@)70
(@)71
(@)72
XFER
BSET
ROOT
BLOCK TRANSFER
Moves content of several consecutive source words to
consecutive destination words.
BLOCK SET
Copies content of one word or constant to several consec- 181
utive words.
SQUARE ROOT
Computes square root of eight-digit BCD value and out-
puts truncated four-digit integer result to specified result
word.
241
(@)73
(@)74
XCHG
SLD
DATA EXCHANGE
Exchanges contents of two different words.
183
ONE DIGIT SHIFT
LEFT
Left shifts data between starting and ending words by one 177
digit (four bits).
(@)75
(@)76
SRD
ONE DIGIT SHIFT
RIGHT
Right shifts data between starting and ending words by
one digit (four bits).
177
MLPX
4-TO-16/8-TO-256
DECODER
Converts up to four hexadecimal digits in source word into 209
decimal values from 0 to 15 and turns ON, in result
word(s), bit(s) whose position corresponds to converted
value.
Can also convert up to eight hexadecimal digits and turn
ON corresponding bits in result words R to R+15.
(@)77
DMPX
16-TO-4/256-TO-8
ENCODER
Determines position of highest ON bit in source word(s)
and writes the ON bit’s position (0 to F) to digit(s) in R.
Can also determine the position of the highest ON bit in
one or two groups of 16 words (S to S+15, S+16 to S+31)
and writes the ON bit’s position (00 to FF) to byte(s) in R.
212
(@)78
(@)79
(@)80
(@)81
(@)82
(@)83
(@)84
(@)85
SDEC
FDIV
7-SEGMENT
DECODER
Converts hexadecimal values from source word to data for 215
seven-segment display.
FLOATING POINT
DIVIDE
Divides one floating point value (Dd+1, Dd) by another
(Dr+1, Dr) and outputs the result to R+1 and R.
238
DIST
SINGLE WORD
DISTRIBUTE
Moves one word of source data to destination word whose 183
address is given by destination base word plus offset.
COLL
MOVB
MOVD
SFTR
TCMP
DATA COLLECT
Extracts data from source word and writes it to destination 185
word.
MOVE BIT
Transfers designated bit of source word or constant to des- 187
ignated bit of destination word.
MOVE DIGIT
Moves hexadecimal content of specified four-bit source
digit(s) to specified destination digit(s) for up to four digits.
188
REVERSIBLE SHIFT
REGISTER
Shifts data in specified word or series of words to either left 173
or right.
TABLE COMPARE
Compares four-digit hexadecimal value with values in table 199
consisting of 16 words.
519
Programming Instructions
Appendix B
Code
Mnemonic
Name
Function
Page
(@)86
ASC
ASCII CONVERT
Converts hexadecimal values from the source word to
eight-bit ASCII code starting at leftmost or rightmost half of
starting destination word.
218
87 to 89 For expansion instructions.
(@)90
(@)91
92
SEND
NETWORK SEND
Used for communications with other PCs linked through
the SYSMAC NET Link System or SYSMAC LINK System.
318
283
284
SBS
SUBROUTINE
ENTRY
Calls and executes subroutine N.
SBN
RET
SUBROUTINE
DEFINE
Marks start of subroutine N.
93
RETURN
Marks the end of a subroutine and returns control to main 284
program.
(@)94
WDT
WATCHDOG TIMER
REFRESH
Increases the watchdog timer PV by 0 to 6300 ms.
306
(@)97
(@)98
IORF
I/O REFRESH
Refreshes all I/O words between the start and end words. 306
RECV
NETWORK RECEIVE Used for communications with other PCs linked through
the SYSMAC NET Link System or SYSMAC LINK System.
323
285
(@)99
MCRO
MACRO
Calls and executes a subroutine replacing I/O words.
Expansion Instructions
The following table shows the instructions that can be treated as expansion instructions. The default function
codes are given for instructions that have codes assigned by default.
Code Mnemonic
Name
Function
Page
178
17
(@)ASFT
ASYNCHRONOUS SHIFT
REGISTER
Creates a shift register that exchanges the contents of
adjacent words when one of the words is zero and the
other is not.
18
19
(@)SCAN CYCLE TIME
Sets the minimum cycle time (0 to 999.0 s).
301
192
(@)MCMP MULTI-WORD COMPARE
Compares a block of 16 consecutive words to another
block of 16 consecutive words.
47
48
(@)LMSG 32-CHARACTER
MESSAGE
Outputs a 32-character message to the Programming
Console.
304
305
196
(@)TERM TERMINAL MODE
Switches the Programming Console to TERMINAL
mode for the normal keyboard mapping operation.
60
61
CMPL
DOUBLE COMPARE
Compares two eight-digit hexadecimal values.
(@)MPRF GROUP-2 HIGH-DENSITY
I/O REFRESH
Refreshes I/O words allocated to Group-2 High-density 307
I/O Units.
62
63
64
(@)XFRB
TRANSFER BITS
Copies the status of up to 255 specified source bits to
the specified destination bits.
189
224
225
(@)LINE
COLUMN TO LINE
Copies a bit column from 16 consecutive words to the
specified word.
(@)COLM LINE TO COLUMN
Copies the 16 bits from the specified word to a bit col-
umn of 16 consecutive words.
65
66
67
(@)SEC
(@)HMS
(@)BCNT
HOURS TO SECONDS
SECONDS TO HOURS
BIT COUNTER
Converts hour and minute data to second data.
Converts second data to hour and minute data.
207
208
Counts the total number of bits that are ON in the speci- 308
fied block of words.
68
69
(@)BCMP BLOCK COMPARE
Judges whether the value of a word is within 16 ranges 197
(defined by lower and upper limits).
(@)APR
ARITHMETIC PROCESS
Performs sine, cosine, or linear approximation
calculations.
263
87
88
TTIM
ZCP
TOTALIZING TIMER
Creates a totalizing timer.
165
200
AREA RANGE COMPARE
Compares a word to a range defined by lower and up-
per limits and outputs the result to the GR, EQ, and LE
flags.
89
(@)INT
INTERRUPT CONTROL
Performs interrupt control, such as masking and un-
masking the interrupt bits for I/O interrupts.
287
520
Programming Instructions
Appendix B
Code Mnemonic
Name
Function
Page
---
---
---
7SEG
7-SEGMENT DISPLAY
OUTPUT
Converts 4- or 8-digit BCD data to 7-segment display
format and then outputs the converted data.
336
249
259
(@)ADBL
AVG
DOUBLE BINARY ADD
Adds two 8-digit binary values (normal or signed data)
and outputs the result to R and R+1.
AVERAGE VALUE
Adds the specified number of hexadecimal words and
computes the mean value. Rounds off to 4 digits past
the decimal point.
---
---
(@)BXF2
CMCR
EM BANK TRANSFER
PCMCIA CARD MACRO
Moves content of several consecutive source words to
consecutive destination words. Words in the current EM
bank can be specified for the source or destination.
191
Performs macros to write files, read files, compare files 353
to memory, search files, and other operations for
PCMCIA Card Interface Units.
---
---
---
---
CPS
SIGNED BINARY
COMPARE
Compares two 16-bit (4-digit) signed binary values and 202
outputs the result to the GR, EQ, and LE flags.
CPSL
DOUBLE SIGNED BINARY Compares two 32-bit (8-digit) signed binary values and 203
COMPARE
outputs the result to the GR, EQ, and LE flags.
(@)DBS
(@)DBSL
DSW
SIGNED BINARY DIVIDE
Divides one 16-bit signed binary value by another and
outputs the 32-bit signed binary result to R+1 and R.
255
256
DOUBLE SIGNED BINARY Divides one 32-bit signed binary value by another and
DIVIDE
outputs the 64-bit signed binary result to R+3 to R.
---
---
DIGITAL SWITCH INPUT
Inputs 4- or 8-digit BCD data from a digital switch.
339
317
(@)EMBC SELECT EM BANK
Changes the current EM bank to the specified bank
number.
---
(@)FCS
FCS CALCULATE
Checks for errors in data transmitted by a Host Link
command.
308
---
---
---
FPD
FAILURE POINT DETECT
ASCII-TO-HEXADECIMAL
Finds errors within an instruction block.
Converts ASCII data to hexadecimal data.
310
219
316
(@)HEX
(@)IEMS
INDIRECT EM
ADDRESSING
Changes the destination of indirect DM addressing
(ꢀDM) to DM or the specified EM bank. This instruction
can be used to change the current EM bank.
---
---
---
---
---
(@)IORD
(@)IOWR
(@)MAX
(@)MBS
(@)MBSL
SPECIAL I/O UNIT READ
SPECIAL I/O UNIT WRITE
FIND MAXIMUM
Transfers data from the specified Special I/O Unit’s
memory to words in the PC.
350
351
257
253
254
Transfers data from words in the PC to the specified
Special I/O Unit’s memory.
Finds the maximum value in specified data area and
outputs that value to another word.
SIGNED BINARY
MULTIPLY
Multiplies the signed binary content of two words and
outputs the 8-digit signed binary result to R+1 and R.
DOUBLE SIGNED BINARY Multiplies two 32-bit (8-digit) signed binary values and
MULTIPLY
outputs the 16-digit signed binary result to R+3 through
R.
---
---
---
(@)MIN
MTR
FIND MINIMUM
MATRIX INPUT
2’S COMPLEMENT
Finds the minimum value in specified data area and
outputs that value to another word.
258
Inputs data from an 8 input point × 8 output point matrix 348
and records that data in D to D+3.
(@)NEG
Converts the four-digit hexadecimal content of the
source word to its 2’s complement and outputs the re-
sult to R.
226
227
266
335
---
---
---
(@)NEGL
(@)PID
DOUBLE 2’S
COMPLEMENT
Converts the eight-digit hexadecimal content of the
source words to its 2’s complement and outputs the re-
sult to R and R+1.
PID CONTROL
PID control is performed according to the operand and
PID parameters that are preset. (The only CQM1 model
that can use PID(––) is the CPU4j .)
(@)PMCR PROTOCOL MACRO
Calls and executes the specified communications se-
quence (protocol) that has been registered in the Com-
munications Board.
521
Programming Instructions
Appendix B
Code Mnemonic
Name
Function
Page
---
---
(@)RXD
RECEIVE
Receives data via a communications port.
329
(@)SBBL
DOUBLE BINARY
SUBTRACT
Subtracts an 8-digit binary value (normal or signed data) 251
from another and outputs the result to R and R+1.
---
---
(@)SCL
SCALING
Performs a scaling conversion on the calculated value. 222
(@)SRCH DATA SEARCH
Searches the specified range of memory for the speci-
fied data. Outputs the word address(es) of words in the
range that contain the data.
314
---
---
(@)STUP
(@)SUM
CHANGE RS-232C SETUP Changes the PC Setup settings for the specified port.
333
261
SUM CALCULATE
Computes the sum of the contents of the words in the
specified range of memory.
---
---
---
(@)TKY
(@)TXD
TEN KEY INPUT
TRANSMIT
Inputs 8 digits of BCD data from a 10-key keypad.
Sends data via a communications port.
346
331
(@)XDMR EXPANSION DM READ
The contents of the designated number of words of the 315
fixed expansion DM data are read and output to the
destination word on the PC side.
---
---
(@)XFR2
ZCPL
EM BLOCK TRANSFER
Moves content of several consecutive source words to
consecutive destination words. Words in the any valid
EM bank can be specified for the source or destination.
This instruction can be used to change the current bank.
190
DOUBLE AREA RANGE
COMPARE
Compares an 8-digit value to a range defined by lower
and upper limits and outputs the result to the GR, EQ,
and LE flags.
201
522
Appendix C
Error and Arithmetic Flag Operation
The following table shows the instructions that affect the N, OF, UF, ER, CY, GR, LE and EQ flags.
In general, N indicates a negative result, OF indicates that the result of a 16-bit calculation is greater than 32,767
(7FFF) or the result of a 32-bit calculation is greater than 2,147,483,647 (7FFF FFFF). UF indicates that the result
of a 16-bit calculation is less than –32,768 (8000) or the result of a 32-bit calculation is less than –2,147,483,648
(8000 0000). Refer to Section 5 Instruction Set for details.
ER indicates that operand data is not within requirements. CY indicates arithmetic or data shift results. GR indi-
cates that a compared value is larger than some standard, LT that it is smaller, and EQ, that it is the same. EQ also
indicates a result of zero for arithmetic operations. Refer to Section 5 Instruction Set for details.
Vertical arrows in the table indicate the flags that are turned ON and OFF according to the result of the instruction.
Although ladder diagram instructions,TIM, and CNT are executed when ER is ON, other instructions with a vertical
arrow under the ER column are not executed if ER is ON. All of the other flags in the following table will also not
operate when ER is ON.
Instructions not shown do not affect any of the flags in the table. Although only the non-differentiated form of each
instruction is shown, differentiated instructions affect flags in exactly the same way.
All 8 flags are turned OFF when END(01) is executed, so their status cannot be monitored with a Programming
Console.
Mnemonic
25503
(ER)
25504
(CY)
25505
(GR)
25506
(EQ)
25507
(LE)
25404
(OF)
25405
(UF)
25402
(N)
Page
TIM
µ
µ
---
---
OFF
---
---
---
---
---
---
---
---
---
µ
---
---
OFF
---
---
---
---
µ
---
---
OFF
---
---
---
---
µ
---
---
OFF
---
---
---
---
µ
---
---
OFF
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
OFF
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
OFF
---
---
---
---
---
µ
159
166
158
171
169
164
178
193
180
180
204
205
175
175
176
176
275
229
231
235
236
276
277
278
279
228
228
229
CNT
END (01)
SFT(10)
CNTR(12)
TIMH(15)
WSFT(16)
CMP(20)
MOV(21)
MVN(22)
BIN(23)
OFF
OFF
µ
µ
µ
µ
µ
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
µ
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
µ
µ
µ
µ
µ
OFF
---
µ
BCD(24)
ASL(25)
ASR(26)
ROL(27)
ROR(28)
COM(29)
ADD(30)
SUB(31)
MUL(32)
DIV(33)
µ
µ
µ
µ
µ
µ
µ
OFF
µ
µ
µ
µ
µ
µ
µ
µ
µ
---
µ
µ
µ
µ
µ
---
---
---
---
µ
µ
µ
µ
µ
---
---
---
---
---
---
---
---
ON
µ
µ
µ
ANDW(34)
ORW(35)
XORW(36)
XNRW(37)
INC(38)
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
---
---
---
DEC(39)
STC(40)
µ
µ
---
---
523
Error and Arithmetic Flag Operation
Appendix C
Mnemonic
25503
(ER)
25504
(CY)
25505
(GR)
25506
(EQ)
25507
(LE)
25404
(OF)
25405
(UF)
25402
(N)
Page
CLC(41)
---
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
---
---
µ
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
µ
---
---
µ
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
µ
---
---
µ
---
---
µ
---
---
µ
229
303
243
245
248
248
230
233
236
237
205
206
182
181
241
183
177
177
209
212
215
238
183
185
187
188
173
199
218
318
283
284
306
306
323
285
MSG(46)
ADB(50)
SBB(51)
µ
µ
µ
µ
µ
MLB(52)
---
---
µ
µ
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
µ
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
µ
µ
DVB(53)
µ
µ
ADDL(54)
SUBL(55)
MULL(56)
DIVL(57)
BINL(58)
BCDL(59)
XFER(70)
BSET(71)
ROOT(72)
XCHG(73)
SLD(74)
µ
---
---
---
---
OFF
---
---
---
---
---
---
---
---
---
---
---
µ
µ
µ
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
µ
µ
µ
µ
µ
---
---
µ
---
---
---
---
---
---
---
---
---
---
---
---
µ
SRD(75)
MLPX(76)
DMPX(77)
SDEC(78)
FDIV(79)
DIST(80)
COLL(81)
MOVB(82)
MOVD(83)
SFTR(84)
TCMP(85)
ASC(86)
µ
µ
µ
---
---
---
---
---
---
---
µ
---
---
---
---
---
---
---
µ
---
---
---
---
µ
---
---
---
µ
SEND(90)
SBS(91)
SBN(92)
WDT(94)
IORF(97)
RECV(98)
MCRO(99)
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
Expansion Instructions
The default function codes are shown for the instructions that have default function codes.
Mnemonic
25503
(ER)
25504
(CY)
25505
(GR)
25506
(EQ)
25507
(LE)
25404
(OF)
25405
(UF)
25402
(N)
Page
7SEG(––)
ADBL(––)
APR(69)
µ
µ
µ
µ
µ
µ
µ
---
µ
---
---
---
---
---
---
---
---
µ
---
---
---
---
---
---
---
---
µ
---
µ
---
µ
336
249
263
178
259
197
308
---
---
---
---
---
µ
---
---
---
---
---
---
---
---
---
---
µ
ASFT(17)
AVG(––)
---
---
---
µ
---
---
---
---
BCMP(68)
BCNT(67)
524
Error and Arithmetic Flag Operation
Appendix C
Mnemonic
25503
(ER)
25504
(CY)
25505
(GR)
25506
(EQ)
25507
(LE)
25404
(OF)
25405
(UF)
25402
(N)
Page
BXF2(––)
CMCR(––)
CMPL(60)
COLM(64)
CPS(––)
CPSL(––)
DBS(––)
DBSL(––)
DSW(––)
EMBC(––)
FCS(––)
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
µ
---
---
---
---
---
---
---
---
---
---
---
µ
---
---
µ
---
---
µ
---
---
µ
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
µ
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
µ
---
---
---
---
---
---
µ
191
353
196
225
202
203
255
256
339
317
308
310
219
343
208
316
287
350
351
224
304
257
253
254
192
258
307
348
226
227
266
335
329
251
301
222
207
314
333
261
305
346
165
331
315
190
189
200
---
µ
µ
---
µ
µ
µ
µ
µ
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
µ
µ
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
µ
µ
µ
---
---
---
---
---
---
µ
---
---
---
---
---
---
---
---
---
---
---
---
---
µ
FPD(––)
HEX(––)
HKY(––)
HMS(66)
IEMS(––)
INT(89)
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
µ
---
---
µ
IORD(––)
IOWR(––)
LINE(63)
LMSG(47)
MAX(––)
MBS(––)
MBSL(––)
MCMP(19)
MIN(––)
µ
µ
---
µ
µ
µ
µ
µ
µ
---
µ
µ
MPRF(61)
MTR(––)
NEG(––)
NEGL(––)
PID(––)
---
---
µ
---
---
µ
µ
µ
µ
---
---
---
µ
---
---
---
µ
---
---
---
µ
PMCR(––)
RXD(––)
SBBL(––)
SCAN(18)
SCL(––)
---
---
µ
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
µ
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
µ
SEC(65)
SRCH(––)
STUP(––)
SUM(––)
TERM(48)
TKY(––)
µ
µ
---
µ
---
---
---
---
---
---
---
---
---
---
---
---
---
---
TTIM(87)
TXD(––)
XDMR(––)
XFR2(––)
XFRB(62)
ZCP(88)
µ
525
Error and Arithmetic Flag Operation
Appendix C
Mnemonic
25503
(ER)
25504
(CY)
25505
(GR)
25506
(EQ)
25507
(LE)
25404
(OF)
25405
(UF)
25402
(N)
Page
ZCPL(––)
µ
---
µ
µ
µ
---
---
---
201
526
Appendix D
Word Assignment Recording Sheets
This appendix contains sheets that can be copied by the programmer to record I/O bit allocations and terminal
assignments, as well as details of work bits, data storage areas, timers, and counters.
527
I/O Bits
Programmer:
Program:
Notes
Date:
Page:
Word:
Bit
Unit:
Word:
Unit:
Field device
Bit
Field device
Notes
00
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
Word:
Bit
Unit:
Word:
Bit
Unit:
Field device
Notes
Field device
Notes
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
528
Work Bits
Programmer:
Program:
Notes
Date:
Page:
Area:
Bit
Word:
Area:
Word:
Usage
Bit
Usage
Notes
00
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
Area:
Bit
Word:
Area:
Bit
Word:
Usage
Notes
Usage
Notes
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
529
Data Storage
Programmer:
Word
Program:
Date:
Page:
Contents
Notes
Word
Contents
Notes
530
Timers and Counters
Programmer:
TC address
Program:
Date:
Page:
T or C
T or C
Set value
Notes
TC address
Set value
Notes
531
Appendix E
Program Coding Sheet
The following page can be copied for use in coding ladder diagram programs. It is designed for flexibility, allowing
the user to input all required addresses and instructions.
When coding programs, be sure to specify all function codes for instructions and data areas (or # for constant) for
operands. These will be necessary when inputting programs though a Programming Console or other Peripheral
Device.
533
Program Coding Sheet
Programmer:
Program:
Date:
Page:
Address
Instruction
Operand(s)
Address
Instruction
Operand(s)
Address
Instruction
Operand(s)
534
Appendix F
Data Conversion Tables
Normal Data
Decimal
BCD
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00010000
00010001
00010010
00010011
00010100
00010101
00010110
00010111
00011000
00011001
00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111
00101000
00101001
00110000
00110001
00110010
Hex
Binary
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
00010010
00010011
00010100
00010101
00010110
00010111
00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111
00100000
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
535
Standard Models
Appendix F
Signed Binary Data
Decimal
16-bit Hex
---
32-bit Hex
2147483647
7FFFFFFF
2147483646
.
---
7FFFFFFE
.
.
.
.
.
.
.
.
---
32768
32767
00008000
00007FFF
7FFF
32766
7FFE
00007FFE
.
.
.
.
.
.
.
.
.
5
4
3
2
1
0005
0004
0003
0002
0001
0000
FFFF
FFFE
FFFD
FFFC
FFFB
00000005
00000004
00000003
00000002
00000001
00000000
FFFFFFFF
FFFFFFFE
FFFFFFFD
FFFFFFFC
FFFFFFFB
0
–1
–2
–3
–4
–5
.
.
.
.
.
.
.
.
.
–32767
8001
FFFF8001
–32768
8000
FFFF8000
–32769
FFFF7FFF
---
.
.
.
.
.
.
.
.
.
–2147483647
---
80000001
–2147483648
---
80000000
536
Appendix G
Extended ASCII
Programming Console Displays
Bits 0 to 3
BIN
Bits 4 to 7
0000 0001 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111
HEX
0
1
2
3
4
5
6
7
A
B
C
D
E
F
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
NUL DLE Space 0 @ P ` p
0 @ P ` p
SOH DC ! 1 A Q a q ! 1 A Q a q
1
STX DC " 2 B R b r " 2 B R b r
2
ETX DC # 3 C S c s # 3 C S c s
3
EOT DC $ 4 D T d t $ 4 D T d t
4
ENQ NAK % 5 E U e u % 5 E U e u
ACK SYN & 6 F V f v & 6 F V f v
BEL ETB ' 7 G W g w ' 7 G W g w
BS
HT
LF
VT
FF
CR
S0
S1
CAN ( 8 H X h x ( 8 H X h x
EM ) 9 I Y i y ) 9 I Y i y
SUB * : J Z j z * : J Z j z
ESC + ; K [ k { + ; K [ k {
FS , < L \ l | , < L \ l |
GS Ć = M ] m } Ć = M ] m }
RS . > N ^ n « . > N ^ n
US / ? O _ o ~ / ? O _ o ~
537
Glossary
address
The location in memory where data is stored. For data areas, an address con-
sists of a two-letter data area designation and a number that designates the
word and/or bit location. For the UM area, an address designates the instruction
location (UM area). In the FM area, the address designates the block location,
etc.
allocation
AND
The process by which the PC assigns certain bits or words in memory for various
functions. This includes pairing I/O bits to I/O points on Units.
A logic operation whereby the result is true if and only if both premises are true.
In ladder-diagram programming the premises are usually ON/OFF states of bits
or the logical combination of such states called execution conditions.
APF
Acronym for all plastic fiber-optic cable.
AR area
arithmetic shift
ASCII
A PC data area allocated to flags, control bits, and work bits.
A shift operation wherein the carry flag is included in the shift.
Short for American Standard Code for Information Interchange. ASCII is used to
code characters for output to printers and other external devices.
ASCII Unit
Backplane
An Intelligent I/O Unit used to program in BASIC. When connected to an NSU on
a Net Link System, commands can be sent to other nodes.
A base onto which Units are mounted to form a Rack. Backplanes provide a se-
ries of connectors for these Units along with wiring to connect them to the CPU
Unit. Backplanes also provide connectors used to connect them to other Back-
planes. In some Systems, different Backplanes are used for different Racks; in
other Systems, Racks differ only according to the Units mounted to them.
BCD
Short for binary-coded decimal.
BCD calculation
An arithmetic calculation that uses numbers expressed in binary-coded deci-
mal.
binary
A number system where all numbers are expressed to the base 2, i.e., any num-
ber can be written using only 1’s or 2’s. Each group of four binary bits is equiva-
lent to one hexadecimal digit.
binary calculation
An arithmetic calculation that uses numbers expressed in binary.
binary-coded decimal
A system used to represent numbers so that each group of four binary bits is
numerically equivalent to one decimal digit.
bit
A binary digit; hence a unit of data in binary notation. The smallest unit of in-
formation that can be electronically stored in a PC. The status of a bit is either ON
or OFF. Different bits at particular addresses are allocated to special purposes,
such as holding the status input from external devices, while other bits are avail-
able for general use in programming.
bit address
The location in memory where a bit of data is stored. A bit address must specify
(sometimes by default) the data area and word that is being addressed, as well
as the number of the bit.
539
Glossary
bit designator
bit number
An operand that is used to designate the bit or bits of a word to be used by an
instruction.
A number that indicates the location of a bit within a word. Bit 00 is the rightmost
(least-significant) bit; bit 15 is the leftmost (most-significant) bit.
building-block PC
A PC that is constructed from individual components, or “building blocks.” With
building-block PCs, there is no one Unit that is independently identifiable as a
PC. The PC is rather a functional assembly of components.
bus bar
The line leading down the left and sometimes right side of a ladder diagram.
Instruction execution proceeds down the bus bar, which is the starting point for
all instruction lines.
call
A process by which instruction execution shifts from the main program to a sub-
routine. The subroutine may be called by an instruction or by an interrupt.
carry flag
A flag that is used with arithmetic operations to hold a carry from an addition or
multiplication operation, or to indicate that the result is negative in a subtraction
operation. The carry flag is also used with certain types of shift operations.
clock pulse
A pulse available at a certain bit in memory for use in timing operations. Various
clock pulses are available with different pulse widths.
clock pulse bit
A bit in memory that supplies a pulse that can be used to time operations. Vari-
ous clock pulse bits are available with different pulse widths, and therefore differ-
ent frequencies.
common data
Data that is stored in the LR Area of a PC and which is shared by other PCs in the
same system. Each PC has a specified section of the LR Area allocated to it.
This allocation is the same in each LR Area of each PC.
Communications Board
A board that is mounted to the optional slot of a C200HX/HG/HE CPU Unit. With
a Communications Board, the CPU Unit can communicate with the SYSMAC
LINK Unit, SYSMAC NET Link Unit, Programmable Terminal, Temperature Con-
troller, personal computer, bar code reader, or any other peripheral device via
RS-232C, RS-422, or RS-485.
condition
An message placed in an instruction line to direct the way in which the terminal
instructions, on the right side, are to be executed. Each condition is assigned to a
bit in memory that determines its status. The status of the bit assigned to each
condition determines, in turn, the execution condition for each instruction up to a
terminal instruction on the right side of the ladder diagram.
constant
An operand for which the actual numeric value is specified by the user, and
which is then stored in a particular address in the data memory.
control bit
A bit in a memory area that is set either through the program or via a Program-
ming Device to achieve a specific purpose, e.g., a Restart bit is turned ON and
OFF to restart a Unit.
Control System
All of the hardware and software components used to control other devices. A
Control System includes the PC System, the PC programs, and all I/O devices
that are used to control or obtain feedback from the controlled system.
controlled system
control signal
The devices that are being controlled by a PC System.
A signal sent from the PC to effect the operation of the controlled system.
540
Glossary
counter
CPU
A dedicated group of digits or words in memory used to count the number of
times a specific process has occurred, or a location in memory accessed
through a TC bit and used to count the number of times the status of a bit or an
execution condition has changed from OFF to ON.
An acronym for central processing unit. In a PC System, the CPU executes the
program, processes I/O signals, communicates with external devices, etc.
CPU Backplane
CPU Rack
A Backplane which is used to create a CPU Rack.
Part of a building-block PC, the CPU Rack contains the CPU Unit, a power sup-
ply, and other Units. With most PCs, the CPU Rack is the only Rack that provides
linkable slots.
CTS
An acronym for clear-to-send, a signal used in communications between elec-
tronic devices to indicate that the receiver is ready to accept incoming data.
cycle
The process used to execute a ladder-diagram program. The program is ex-
amined sequentially from start to finish and each instruction is executed in turn
based on execution conditions.
cycle time
data area
The time required for a single cycle of the ladder-diagram program.
An area in the PC’s memory that is designed to hold a specific type of data, e.g.,
the LR area is designed to hold common data in a PC Link System. Memory
areas that hold programs are not considered data areas.
data area boundary
data sharing
debug
The highest address available within a data area. When designating an operand
that requires multiple words, it is necessary to ensure that the highest address in
the data area is not exceeded.
An aspect of PC Link Systems and of Data Links in Net Link Systems in which
common data areas or common data words are created between two or more
PCs.
A process by which a draft program is corrected until it operates as intended.
Debugging includes both the removal of syntax errors, as well as the fine-tuning
of timing and coordination of control operations.
decimal
A number system where all numbers are expressed to the base 10. In a PC all
data is ultimately stored in binary form, four binary bits are often used to repre-
sent one decimal digit, via a system called binary-coded decimal.
decrement
default
Decreasing a numeric value.
A value automatically set by the PC when the user omits to set a specific value.
Many devices will assume such default conditions upon the application of power.
definer
A number used as an operand for an instruction but that serves to define the
instruction itself, rather that the data on which the instruction is to operate. Defin-
ers include jump numbers, subroutine numbers, etc.
delay
In tracing, a value that specifies where tracing is to begin in relationship to the
trigger. A delay can be either positive or negative, i.e., can designate an offset on
either side of the trigger.
destination
The location where an instruction is to place the data on which it is operating, as
opposed to the location from which data is taken for use in the instruction. The
location from which data is taken is called the source.
541
Glossary
differentiated instruction
differentiation instruction
An instruction that is executed only once each time its execution condition goes
from OFF to ON. Non-differentiated instructions are executed each cycle as long
as the execution condition stays ON.
An instruction used to ensure that the operand bit is never turned ON for more
than one cycle after the execution condition goes either from OFF to ON for a
Differentiate Up instruction or from ON to OFF for a Differentiate Down instruc-
tion.
digit
A unit of storage in memory that consists of four bits.
digit designator
An operand that is used to designate the digit or digits of a word to be used by an
instruction.
distributed control
An automation concept in which control of each portion of an automated system
is located near the devices actually being controlled, i.e., control is decentralized
and ‘distributed’ over the system. Distributed control is one of the fundamental
concepts of PC Systems.
DM area
A data area used to hold only word data. Words in the DM area cannot be ac-
cessed bit by bit.
download
electrical noise
EM area
The process of transferring a program or data from a higher-level computer to a
lower-level computer or PC.
Random variations of one or more electrical characteristics such as voltage, cur-
rent, and data, which might interfere with the normal operation of a device.
Extended data memory area. Like DM, the EM memory can be accessed in word
units only and EM area data is retained when the power to the PC is turned off.
error code
A numeric code generated to indicate that an error exists, and something about
the nature of the error. Some error codes are generated by the system; others
are defined in the program by the operator.
exclusive OR
A logic operation whereby the result is true if one, and only one, of the premises
is true. In ladder-diagram programming the premises are usually the ON/OFF
states of bits, or the logical combination of such states, called execution condi-
tions.
exclusive NOR
A logic operation whereby the result is true if both of the premises are true or both
of the premises are false. In ladder-diagram programming the premises are usu-
ally the ON/OFF states of bits, or the logical combination of such states, called
execution conditions.
execution condition
execution time
The ON or OFF status under which an instruction is executed. The execution
condition is determined by the logical combination of conditions on the same
instruction line and up to the instruction currently being executed.
The time required for the CPU Unit to execute either an individual instruction or
an entire program.
Expansion I/O Backplane
Expansion I/O Rack
A Backplane which is used to create an Expansion I/O Rack.
Part of a building-block PC, an Expansion I/O Rack is connected to either a CPU
Rack or another Expansion I/O Rack to increase the number of slots available
for mounting Units.
542
Glossary
extended counter
extended timer
A counter created in a program by using two or more count instructions in suc-
cession. Such a counter is capable of counting higher than any of the standard
counters provided by the individual instructions.
A timer created in a program by using two or more timers in succession. Such a
timer is capable of timing longer than any of the standard timers provided by the
individual instructions.
Factory Intelligent Terminal A programming device provided with advanced programming and debugging
capabilities to facilitate PC operation. The Factory Intelligent Terminal also pro-
vides various interfaces for external devices, such as floppy disk drives.
fatal error
An error that stops PC operation and requires correction before operation can
continue.
FIT
Abbreviation for Factory Intelligent Terminal.
flag
A dedicated bit in memory that is set by the system to indicate some type of oper-
ating status. Some flags, such as the carry flag, can also be set by the operator
or via the program.
flicker bit
A bit that is programmed to turn ON and OFF at a specific frequency.
floating point decimal
A decimal number expressed as a number between 0 and 1 (the mantissa) multi-
plied by a power of 10, e.g., 0.538 x 10 .
-5
Floppy Disk Interface Unit
force reset
A Unit used to interface a floppy disk drive to a PC so that programs and/or data
can be stored on floppy disks.
The process of forcibly turning OFF a bit via a programming device. Bits are usu-
ally turned OFF as a result of program execution.
force set
The process of forcibly turning ON a bit via a programming device. Bits are usu-
ally turned ON as a result of program execution.
function code
hardware error
A two-digit number used to input an instruction into the PC.
An error originating in the hardware structure (electronic components) of the PC,
as opposed to a software error, which originates in software (i.e., programs).
hexadecimal
A number system where all numbers are expressed to the base 16. In a PC all
data is ultimately stored in binary form, however, displays and inputs on Pro-
gramming Devices are often expressed in hexadecimal to simplify operation.
Each group of four binary bits is numerically equivalent to one hexadecimal digit.
Host Link System
A system with one or more host computers connected to one or more PCs via
Host Link Units so that the host computer can be used to transfer data to and
from the PC(s). Host Link Systems enable centralized management and control
of PC Systems.
Host Link Unit
host computer
An interface used to connect a PC to a host computer in a Host Link System.
A computer that is used to transfer data or programs to from a PC in a Host Link
System. The host computer is used for data management and overall system
control. Host computers are generally personal or business computers.
HR area
A data area used to store and manipulate data, and to preserve data when pow-
er to the PC is turned OFF.
543
Glossary
increment
Increasing a numeric value.
indirect address
An address whose contents indicates another address. The contents of the se-
cond address will be used as the operand. Indirect addressing is possible in the
DM area only.
initialization error
initialize
An error that occurs either in hardware or software during the PC System start-
up, i.e., during initialization.
Part of the startup process whereby some memory areas are cleared, system
setup is checked, and default values are set.
input
The signal coming from an external device into the PC. The term input is often
used abstractly or collectively to refer to incoming signals.
input bit
A bit in the IR area that is allocated to hold the status of an input.
An external device that sends signals into the PC System.
input device
input point
The point at which an input enters the PC System. Input points correspond
physically to terminals or connector pins.
input signal
instruction
A change in the status of a connection entering the PC. Generally an input signal
is said to exist when, for example, a connection point goes from low to high volt-
age or from a nonconductive to a conductive state.
A direction given in the program that tells the PC of an action to be carried out,
and which data is to be used in carrying out the action. Instructions can be used
to simply turn a bit ON or OFF, or they can perform much more complex actions,
such as converting and/or transferring large blocks of data.
instruction block
A group of instructions that is logically related in a ladder-diagram program. Al-
though any logically related group of instructions could be called an instruction
block, the term is generally used to refer to blocks of instructions called logic
blocks that require logic block instructions to relate them to other instructions or
logic blocks.
instruction execution time
instruction line
The time required to execute an instruction. The execution time for any one
instruction can vary with the execution conditions for the instruction and the op-
erands used within it.
A group of conditions that lie together on the same horizontal line of a ladder dia-
gram. Instruction lines can branch apart or join together to form instruction
blocks.
interface
An interface is the conceptual boundary between systems or devices and usual-
ly involves changes in the way the communicated data is represented. Interface
devices such as NSBs perform operations like changing the coding, format, or
speed of the data.
interlock
A programming method used to treat a number of instructions as a group so that
the entire group can be reset together when individual execution is not required.
An interlocked program section is executed normally for an ON execution condi-
tion and partially reset for an OFF execution condition.
interrupt (signal)
A signal that stops normal program execution and causes a subroutine to be run.
A Rack-mounting Unit used to input external interrupts into a PC System.
Interrupt Input Unit
544
Glossary
inverse condition
I/O capacity
A condition that produces an ON execution condition when the bit assigned to it
is OFF, and an OFF execution condition when the bit assigned to it is ON.
The number of inputs and outputs that a PC is able to handle. This number
ranges from around one hundred for smaller PCs to two thousand for the largest
ones.
I/O Control Unit
I/O devices
A Unit mounted to the CPU Rack in certain PCs to monitor and control I/O points
on Expansion I/O Units.
The devices to which terminals on I/O Units, Special I/O Units, or Intelligent I/O
Units are connected. I/O devices may be either part of the Control System, if they
function to help control other devices, or they may be part of the controlled sys-
tem.
I/O Interface Unit
I/O Link
A Unit mounted to an Expansion I/O Rack in certain PCs to interface the Expan-
sion I/O Rack to the CPU Rack.
Created in an Optical Remote I/O System to enable input/output of one or two IR
words directly between PCs. The words are input/output between the PC con-
trolling the Master and a PC connected to the Remote I/O System through an I/O
Link Unit or an I/O Link Rack.
I/O Link Unit
I/O point
A Unit used with certain PCs to create an I/O Link in an Optical Remote I/O Sys-
tem.
The place at which an input signal enters the PC System, or at which an output
signal leaves the PC System. In physical terms, I/O points correspond to termi-
nals or connector pins on a Unit; in terms of programming, an I/O points corre-
spond to I/O bits in the IR area.
I/O response time
I/O table
The time required for an output signal to be sent from the PC in response to an
input signal received from an external device.
A table created within the memory of the PC that lists the IR area words allocated
to each Unit in the PC System. The I/O table can be created by, or modified from,
a Programming Device.
I/O Unit
The most basic type of Unit mounted to a backplane to create a Rack. I/O Units
include Input Units and Output Units, each of which is available in a range of
specifications. I/O Units do not include Special I/O Units, Link Units, etc.
I/O word
IR area
A word in the IR area that is allocated to a Unit in the PC System.
A data area whose principal function is to hold the status of inputs coming into
the system and that of outputs that are to be set out of the system. Bits and words
in the IR that are used this way are called I/O bits and I/O words. The remaining
bits in the IR area are work bits.
JIS
Acronym for Japanese Industrial Standards.
jump
A type of programming where execution moves directly from one point in a pro-
gram to another, without sequentially executing any instructions in between.
Jumps are usually conditional on an execution condition.
jump number
A definer used with a jump that defines the points from and to which a jump is to
be made.
545
Glossary
ladder diagram (program)
A form of program arising out of relay-based control systems that uses circuit-
type diagrams to represent the logic flow of programming instructions. The ap-
pearance of the program is similar to a ladder, and thus the name.
ladder diagram symbol
ladder instruction
A symbol used in a ladder-diagram program.
An instruction that represents the ‘rung’ portion of a ladder-diagram program.
The other instructions in a ladder diagram fall along the right side of the diagram
and are called terminal instructions.
LAN
An acronym for local area network.
leftmost (bit/word)
The highest numbered bits of a group of bits, generally of an entire word, or the
highest numbered words of a group of words. These bits/words are often called
most-significant bits/words.
Link Adapter
link
A Unit used to connect communications lines, either to branch the lines or to con-
vert between different types of cable. There are two types of Link Adapter:
Branching Link Adapters and Converting Link Adapters.
A hardware or software connection formed between two Units. “Link” can refer
either to a part of the physical connection between two Units (e.g., optical links in
Wired Remote I/O Systems) or a software connection created to data existing at
another location (Network Data Links).
linkable slot
Link System
Link Unit
load
A slot on either a CPU or Expansion I/O Backplane to which a Link Unit can be
mounted. Backplanes differ in the slots to which Link Units can be mounted.
A system that includes one or more of the following systems: Remote I/O Sys-
tem, PC Link System, Host Link System, or Net Link System.
Any of the Units used to connect a PC to a Link System. These are Remote I/O
Units, I/O Link Units, PC Link Units, Host Link Units, and Net Link Units.
The processes of copying data either from an external device or from a storage
area to an active portion of the system such as a display buffer. Also, an output
device connected to the PC is called a load.
local area network
logic block
A network consisting of nodes or positions in a loop arrangement. Each node
can be any one of a number of devices, which can transfer data to and from each
other.
A group of instructions that is logically related in a ladder-diagram program and
that requires logic block instructions to relate it to other instructions or logic
blocks.
logic block instruction
An instruction used to locally combine the execution condition resulting from a
logic block with a current execution condition. The current execution condition
could be the result of a single condition, or of another logic block. AND Load and
OR Load are the two logic block instructions.
logic instruction
Instructions used to logically combine the content of two words and output the
logical results to a specified result word. The logic instructions combine all the
same-numbered bits in the two words and output the result to the bit of the same
number in the specified result word.
loop
A group of instructions that can be executed more than once in succession (i.e.,
repeated) depending on an execution condition or bit status.
546
Glossary
LR area
A data area that is used in a PC Link System so that data can be transferred be-
tween two or more PCs. If a PC Link System is not used, the LR area is available
for use as work bits.
main program
masking
All of a program except for the subroutines.
‘Covering’ an interrupt signal so that the interrupt is not effective until the mask is
removed.
Master
Short for Remote I/O Master Unit.
memory area
mnemonic code
Any of the areas in the PC used to hold data or programs.
A form of a ladder-diagram program that consists of a sequential list of the
instructions without using a ladder diagram. Mnemonic code is required to input
a program into a PC when using a Programming Console.
MONITOR mode
A mode of PC operation in which normal program execution is possible, and
which allows modification of data held in memory. Used for monitoring or debug-
ging the PC.
most-significant (bit/word)
NC input
See leftmost (bit/word).
An input that is normally closed, i.e., the input signal is considered to be present
when the circuit connected to the input opens.
nest
Programming one loop within another loop, programming a call to a subroutine
within another subroutine, or programming an IF-ELSE programming section
within another IF-ELSE section.
Net Link System
An optical LAN formed from PCs connected through Net Link Units. A Net Link
System also normally contains nodes interfacing computers and other peripher-
al devices. PCs in the Net Link System can pass data back and forth, receive
commands from any interfaced computer, and share any interfaced peripheral
device.
Net Link Unit
The Unit used to connect PCs to a Net Link System. The full name is “SYSMAC
Net Link Unit.”
Network Service Board
Network Service Unit
node
A device with an interface to connect devices other than PCs to a Net Link Sys-
tem.
A Unit that provides two interfaces to connect peripheral devices to a Net Link
System.
One of the positions in a LAN. Each node incorporates a device that can commu-
nicate with the devices at all of the other nodes. The device at a node is identified
by the node number. One loop of a Net Link System (OMRON’s LAN) can consist
of up to 126 nodes. Each node is occupied by a Net Link Unit mounted to a PC or
a device providing an interface to a computer or other peripheral device.
NO input
An input that is normally open, i.e., the input signal is considered to be present
when the circuit connected to the input closes.
noise interference
nonfatal error
Disturbances in signals caused by electrical noise.
A hardware or software error that produces a warning but does not stop the PC
from operating.
547
Glossary
normal condition
NOT
A condition that produces an ON execution condition when the bit assigned to it
is ON, and an OFF execution condition when the bit assigned to it is OFF.
A logic operation which inverts the status of the operand. For example, AND
NOT indicates an AND operation with the opposite of the actual status of the op-
erand bit.
NSB
NSU
OFF
An acronym for Network Service Board.
An acronym for Network Service Unit.
The status of an input or output when a signal is said not to be present. The OFF
state is generally represented by a low voltage or by non-conductivity, but can be
defined as the opposite of either.
OFF delay
ON
The delay between the time when a signal is switched OFF (e.g., by an input
device or PC) and the time when the signal reaches a state readable as an OFF
signal (i.e., as no signal) by a receiving party (e.g., output device or PC).
The status of an input or output when a signal is said to be present. The ON state
is generally represented by a high voltage or by conductivity, but can be defined
as the opposite of either.
ON delay
The delay between the time when an ON signal is initiated (e.g., by an input de-
vice or PC) and the time when the signal reaches a state readable as an ON sig-
nal by a receiving party (e.g., output device or PC).
one-shot bit
on-line removal
operand
A bit that is turned ON or OFF for a specified interval of time which is longer than
one cycle.
Removing a Rack-mounted Unit for replacement or maintenance during PC op-
eration.
Bit(s) or word(s) designated as the data to be used for an instruction. An operand
can be input as a constant expressing the actual numeric value to be used or as
an address to express the location in memory of the data to be used.
operand bit
A bit designated as an operand for an instruction.
A word designated as an operand for an instruction.
operand word
operating error
An error that occurs during actual PC operation as opposed to an initialization
error, which occurs before actual operations can begin.
Optical I/O Unit
A Unit that is connected in an Optical Remote I/O System to provide 8 I/O points.
Optical I/O Units are not mounted to a Rack.
Optical Slave Rack
OR
A Slave Rack connected through an Optical Remote I/O Slave Unit.
A logic operation whereby the result is true if either of two premises is true, or if
both are true. In ladder-diagram programming the premises are usually ON/OFF
states of bits or the logical combination of such states called execution condi-
tions.
output
The signal sent from the PC to an external device. The term output is often used
abstractly or collectively to refer to outgoing signals.
output bit
A bit in the IR area that is allocated to hold the status to be sent to an output de-
vice.
548
Glossary
output device
output point
An external device that receives signals from the PC System.
The point at which an output leaves the PC System. Output points correspond
physically to terminals or connector pins.
output signal
overseeing
A signal being sent to an external device. Generally an output signal is said to
exist when, for example, a connection point goes from low to high voltage or from
a nonconductive to a conductive state.
Part of the processing performed by the CPU Unit that includes general tasks
required to operate the PC.
overwrite
parity
Changing the content of a memory location so that the previous content is lost.
Adjustment of the number of ON bits in a word or other unit of data so that the
total is always an even number or always an odd number. Parity is generally
used to check the accuracy of data after being transmitted by confirming that the
number of ON bits is still even or still odd.
PC
An acronym for Programmable Controller.
An acronym for printed circuit board.
PCB
PC configuration
The arrangement and interconnections of the Units that are put together to form
a functional PC.
PCF
Acronym for plastic-clad optical fiber cable.
PC Link System
A system in which PCs are connected through PC Link Units to enable them to
share common data areas, i.e., each of the PCs writes to certain words in the LR
area and receives the data of the words written by all other PC Link Units con-
nected in series with it.
PC Link Unit
PC System
The Unit used to connect PCs in a PC Link System.
With building-block PCs, all of the Racks and independent Units connected di-
rectly to them up to, but not including the I/O devices. The boundaries of a PC
System are the PC and the program in its CPU Unit at the upper end; and the I/O
Units, Special I/O Units, Optical I/O Units, Remote Terminals, etc., at the lower
end.
peripheral device
port
Devices connected to a PC System to aid in system operation. Peripheral de-
vices include printers, programming devices, external storage media, etc.
A connector on a PC or computer that serves as a connection to an external de-
vice.
present value
printed circuit board
Printer Interface Unit
program
The current value registered in a device at any instant during its operation. Pres-
ent value is abbreviated as PV.
A board onto which electrical circuits are printed for mounting into a computer or
electrical device.
A Unit used to interface a printer so that ladder diagrams and other data can be
printed out.
The list of instructions that tells the PC the sequence of control actions to be car-
ried out.
549
Glossary
Programmable Controller
A computerized device that can accept inputs from external devices and gener-
ate outputs to external devices according to a program held in memory. Pro-
grammable Controllers are used to automate control of external devices. Al-
though single-component Programmable Controllers are available, building-
block Programmable Controllers are constructed from separate components.
Such building-block Programmable Controllers are formed only when enough of
these separate components are assembled to form a functional assembly, i.e.,
no one individual Unit is called a PC.
programmed alarm
programmed error
An alarm given as a result of execution of an instruction designed to generate the
alarm in the program, as opposed to one generated by the system.
An error arising as a result of the execution of an instruction designed to gener-
ate the error in the program, as opposed to one generated by the system.
programmed message
Programming Console
A message generated as a result of execution of an instruction designed to gen-
erate the message in the program, as opposed to one generated by the system.
The simplest form or programming device available for a PC. Programming
Consoles are available both as hand-held models and as CPU Unit-mounting
models.
Programming Device
A peripheral device used to input a program into a PC or to alter or monitor a
program already held in the PC. There are dedicated programming devices,
such as Programming Consoles, and there are non-dedicated devices, such as
a host computer.
PROGRAM mode
PROM Writer
prompt
A mode of operation that allows inputting and debugging of programs to be car-
ried out, but that does not permit normal execution of the program.
A peripheral device used to write programs and other data into a ROM for per-
manent storage and application.
A message or symbol that appears on a display to request input from the opera-
tor.
PV
Acronym for present value.
Rack
An assembly of various Units on a Backplane that forms a functional unit in a
building-block PC System. Racks include CPU Racks, Expansion I/O Racks, I/O
Racks, and Slave Racks.
refresh
The process of updating output status sent to external devices so that it agrees
with the status of output bits held in memory and of updating input bits in memory
so that they agree with the status of inputs from external devices.
relay-based control
Remote I/O Master Unit
The forerunner of PCs. In relay-based control, groups of relays are intercon-
nected to form control circuits. In a PC, these are replaced by programmable cir-
cuits.
The Unit in a Remote I/O System through which signals are sent to all other Re-
mote I/O Units. The Remote I/O Master Unit is mounted either to a CPU Rack or
an Expansion I/O Rack connected to the CPU Rack. Remote I/O Master Unit is
generally abbreviated to Master.
Remote I/O Slave Unit
A Unit mounted to a Backplane to form a Slave Rack. Remote I/O Slave Unit is
generally abbreviated to Slave.
550
Glossary
Remote I/O System
Remote I/O Unit
A system in which remote I/O points are controlled through a Master mounted to
a CPU Rack or an Expansion I/O Rack connected to the CPU Rack.
Any of the Units in a Remote I/O System. Remote I/O Units include Masters,
Slaves, Optical I/O Units, I/O Link Units, and Remote Terminals.
remote I/O word
reset
An I/O word allocated to a Unit in a Remote I/O System.
The process of turning a bit or signal OFF or of changing the present value of a
timer or counter to its set value or to zero.
return
The process by which instruction execution shifts from a subroutine back to the
main program (usually the point from which the subroutine was called).
reversible counter
reversible shift register
A counter that can be both incremented and decremented depending on the
specified conditions.
A shift register that can shift data in either direction depending on the specified
conditions.
right-hand instruction
rightmost (bit/word)
Another term for terminal instruction.
The lowest numbered bits of a group of bits, generally of an entire word, or the
lowest numbered words of a group of words. These bits/words are often called
least-significant bits/words.
rotate register
A shift register in which the data moved out from one end is placed back into the
shift register at the other end.
RUN mode
The operating mode used by the PC for normal control operations.
scheduled interrupt
An interrupt that is automatically generated by the system at a specific time or
program location specified by the operator. Scheduled interrupts result in the
execution of specific subroutines that can be used for instructions that must be
executed repeatedly for a specified period of time.
self diagnosis
self-maintaining bit
servicing
A process whereby the system checks its own operation and generates a warn-
ing or error if an abnormality is discovered.
A bit that is programmed to maintain either an OFF or ON status until set or reset
by specified conditions.
The process whereby the PC provides data to or receives data from external de-
vices or remote I/O Units, or otherwise handles data transactions for Link Sys-
tems.
set
The process of turning a bit or signal ON.
set value
The value from which a decrementing counter starts counting down or to which
an incrementing counter counts up (i.e., the maximum count), or the time from
which or for which a timer starts timing. Set value is abbreviated SV.
shift register
One or more words in which data is shifted a specified number of units to the right
or left in bit, digit, or word units. In a rotate register, data shifted out one end is
shifted back into the other end. In other shift registers, new data (either specified
data, zero(s) or one(s)) is shifted into one end and the data shifted out at the oth-
er end is lost.
551
Glossary
Slave
Short for Remote I/O Slave Unit.
Slave Rack
A Rack containing a Remote I/O Slave Unit and controlled through a Remote I/O
Master Unit. Slave Racks are generally located away from the CPU Rack.
slot
A position on a Rack (Backplane) to which a Unit can be mounted.
An error that originates in a software program.
software error
software protect
A means of protecting data from being changed that uses software as opposed
to a physical switch or other hardware setting.
source
The location from which data is taken for use in an instruction, as opposed to the
location to which the result of an instruction is to be written. The latter is called
the destination.
Special I/O Unit
SR area
A dedicated Unit that is designed for a specific purpose. Special I/O Units in-
clude Position Control Units, High-Speed Counter Units, Analog I/O Units, etc.
A data area in a PC used mainly for flags, control bits, and other information pro-
vided about PC operation. The status of only certain SR bits may be controlled
by the operator, i.e., most SR bits can only be read.
SSS
Abbreviation for SYSMAC Support Software.
subroutine
A group of instructions placed after the main program and executed only if called
from the main program or activated by an interrupt.
subroutine number
A definer used to identify the subroutine that a subroutine call or interrupt acti-
vates.
SV
Abbreviation for set value.
switching capacity
syntax error
The maximum voltage/current that a relay can safely switch on and off.
An error in the way in which a program is written. Syntax errors can include
‘spelling’ mistakes (i.e., a function code that does not exist), mistakes in specify-
ing operands within acceptable parameters (e.g., specifying reserved SR bits as
a destination), and mistakes in actual application of instructions (e.g., a call to a
subroutine that does not exist).
SYSMAC Support Software
A software package installed on a IBM PC/AT or compatible computer to func-
tion as a Programming Device.
system configuration
system error
The arrangement in which Units in a system are connected.
An error generated by the system, as opposed to one resulting from execution of
an instruction designed to generate an error.
system error message
TC area
An error message generated by the system, as opposed to one resulting from
execution of an instruction designed to generate a message.
A data area that can be used only for timers and counters. Each bit in the TC area
serves as the access point for the SV, PV, and Completion flag for the timer or
counter defined with that bit.
TC number
A definer that corresponds to a bit in the TC area and used to define the bit as
either a timer or a counter.
552
Glossary
terminal instruction
terminator
An instruction placed on the right side of a ladder diagram that uses the final
execution conditions of an instruction line.
The code comprising an asterisk and a carriage return (* CR) which indicates the
end of a block of data, whether it is a single-frame or multi-frame block. Frames
within a multi-frame block are separated by delimiters.
timer
A location in memory accessed through a TC bit and used to time down from the
timer’s set value. Timers are turned ON and reset according to their execution
conditions.
TM area
A memory area used to store the results of a trace.
The distance that a signal can be transmitted.
transmission distance
TR area
A data area used to store execution conditions so that they can be reloaded later
for use with other instructions.
trace
An operation whereby the program is executed and the resulting data is stored in
TM memory to enable step-by-step analysis and debugging.
transfer
The process of moving data from one location to another within the PC, or be-
tween the PC and external devices. When data is transferred, generally a copy
of the data is sent to the destination, i.e., the content of the source of the transfer
is not changed.
trigger address
An address in the program that defines the beginning point for tracing. The actu-
al beginning point can be altered from the trigger by defining either a positive or
negative delay.
UM area
Unit
The memory area used to hold the active program, i.e., the program that is being
currently executed.
In OMRON PC terminology, the word Unit is capitalized to indicate any product
sold for a PC System. Though most of the names of these products end with the
word Unit, not all do, e.g., a Remote Terminal is referred to in a collective sense
as a Unit. Context generally makes any limitations of this word clear.
unit number
A number assigned to some Link Units and Special I/O Units to facilitate identifi-
cation when assigning words or other operating parameters to it.
watchdog timer
A timer within the system that ensures that the cycle time stays within specified
limits. When limits are reached, either warnings are given or PC operation is
stopped depending on the particular limit that is reached.
Wired Slave Rack
word
A Slave Rack connected through a Wired Remote I/O Slave Unit.
A unit of data storage in memory that consists of 16 bits. All data areas consists
of words. Some data areas can be accessed only by words; others, by either
words or bits.
word address
The location in memory where a word of data is stored. A word address must
specify (sometimes by default) the data area and the number of the word that is
being addressed.
word multiplier
A value between 0 and 3 that is assigned to a Master in a Remote I/O System so
that words can be allocated to non-Rack-mounting Units within the System. The
553
Glossary
word setting made on the Unit is added to 32 times the word multiplier to arrive at
the actual word to be allocated.
work bit
A bit in a work word.
work word
A word that can be used for data calculation or other manipulation in program-
ming, i.e., a ‘work space’ in memory. A large portion of the IR area is always re-
served for work words. Parts of other areas not required for special purposes
may also be used as work words, e.g., LR words not used in a PC Link or Net Link
System.
554
Index
definition, 25
Output OFF, 42
A
Control System, definition, 3
controlled system, definition, 3
address tracing. See tracing, data tracing.
addresses, in data area, 26
counters
bits in TC area, 68
changing SV, 406
conditions when reset, 166, 170
creating extended timers, 168
extended, 168
inputting SV, 106
Power OFF, 54
reversible counters, 169
CPU Rack, definition, 15
advanced I/O instructions
7-SEGMENT DISPLAY OUTPUT, 337
DIGITAL SWITCH INPUT, 340
functions, 336
HEXADECIMAL KEY INPUT, 344
MATRIX INPUT, 349
TEN-KEY INPUT, 346
Analog Timer Unit, programming examples, 130
application examples, 383
AR area, 48–55
arithmetic flags, 139
arithmetic operations, flags, 44
ASCII, converting data, 218, 219
CPU Unit, 12
CPU Unit-mounting Device Mounted Flag, 55
operational flow, 360–361
CPU Unit indicators, 13
current EM bank, changing the current bank, 317
cycle, First Cycle Flag, 43
cycle monitor time, extending, 306
cycle time, 360–364
B
battery
calculating, 364–366
controlling, 301
Low Battery Flag, 42
operation without backup battery, 21
BCD
calculations, 228–242
converting, 26
definition, 26
Cycle Time Indicators, 55
displaying on Programming Console, 110
error flag, 43
extending the cycle monitor time, 306
flag for SCAN(18), 55
binary
calculations, 243
definition, 26
signed binary, 28
unsigned binary, 27
D
data
bits
comparison instructions, 192–203
converting, 27, 204–227
decrementing, 228
controlling, 150
forced set/reset, 393
monitoring, 390–393
incrementing, 228
modifying, 402
buzzer, 92
modifying binary data, 405
modifying hex/BCD, 396
moving, 180–192
C
data area, definition, 23
data areas, structure, 25
Data Link table, transferring, 102
data memory, fixed, 57
data retention
in AR area, 49
in HR area, 68
in IR area, 29
in LR area, 69
in SR area, 33
in TC area, 68
in TR area, 71
data tracing, 302–317
flags and control bits, 55
C200H programs, transferring to C200HS, 8
calendar/clock, dedicated bits, 53
canceling, forced set/reset, 395
channel. See word
checksum, calculating frame checksum, 308
clock, reading and setting, 411
clock pulse bits, 43
communications
host link, 422
link, one-to-one, 430
one-to-one, 431
wiring, 419
Communications Board, settings, 65
constants, operands, 139
control bit
decimal
converting display between 4-digit hex and decimal, 399
converting display between 8-digit hex and decimal, 400
555
Index
decrementing, 228
definers, definition, 138
AR and SR area error flags, 449
arithmetic, 44
programming example, 194, 197, 201
CPU Unit-mounting Device Mounted, 55
CY
clearing, 229
setting, 229
delay time, in C500 Remote I/O Systems, 378
differentiated instructions, 140
function codes, 138
digit, monitoring, 390
digit numbers, 26
DIP switch, 20
Cycle Time Error, 43
definition, 24
displays
First Cycle, 43
converting between 4-digit hex and decimal, 399
converting between 8-digit hex and decimal, 400
converting between hex and ASCII, 398
I/O Unit designations, 100
FPD Trigger Bit, 55
I/O Verification Error, 43
Instruction Execution Error, 44
Link Units, 55
Programming Console, English/Japanese switch, 91
Low Battery, 42
Optical I/O Error, 51
Step, 44
flags
DM area
allocating UM to expansion DM, 410
Using EM for indirect addressing, 316
arithmetic, 139
error and arithmetic, 523
signed binary arithmetic, 523
floating-point decimal, division, 238
E
EM (Extended Data Memory) area, 71
forced set/reset, 393
canceling, 395–396
Forced Status Hold Bit, 41
Frame Check Sequence. See frames, FCS
frame checksum, calculating with FCS(––), 308
EM area
changing the current bank, 317
clearing selected EM banks, 95
Using EM for indirect addressing, 316
EM bank number, changing the current bank, 317
ER. See flag, Instruction Execution Error
error codes, programming, 300
frames
dividing, precautions, 422
FCS, 423
function codes, 138
error history, dedicated bits, 52
changing expansion instruction function codes, 409
reading expansion instruction function codes, 409
error messages, programming, 303, 304
errors
clearing messages, 97
fatal, 447
history area, 58
initialization, 445
Instruction Execution Error Flag, 44
message tables, 445–448
messages when inputting programs, 108
non-fatal, 445
G-H
Group-2 High-density I/O Units, 4
Group-2 B7A Interface Units, word allocation, 32
Group-2 High-density I/O Units, word allocation, 32
hexadecimal, definition, 26
programming indications, 444
programming messages, 303, 304
reading and clearing messages, 444
resetting, 301
High-density I/O Units. See Group–2 High–density I/O Units;
Units
host link
communications
See also host link commands
procedures, 422
setting parameters, start and end codes, 426
host link commands
**, 498
EX, 498
FK, 488
IC, 499
KC, 489
KR, 486
KS, 485
SR and AR area flags, 449
execution condition, definition, 76
execution time, instructions, 367–375
expansion DM, allocating UM to, 410
expansion DM area, allocation, 57
Expansion I/O Rack, definition, 15
expansion instructions, 141, 520
changing function code assignments, 409
reading function code assignments, 409
expansion keyboard mapping, 411
MF, 484
MI, 494
MM, 490
MS, 481
QQIR, 496
QQMR, 495
R#, 473
F
FAL area, 42, 300
fatal operating errors, 447
flag
556
Index
R$, 474
R%, 476
RC, 461
RD, 463
RE, 464
RG, 462
RH, 460
RJ, 464
RL, 459
RP, 492
RR, 458
SC, 483
TS, 491
W#, 477
W$, 478
W%, 480
WC, 468
WD, 470
WE, 472
WG, 469
WH, 467
WJ, 471
WL, 466
WP, 493
WR, 465
XZ, 497
7SEG(––), 336
ADB(50), 243
ADBL(––), 249
ADD(30), 229
ADDL(54), 230
AND, 78, 149
combining with OR, 79
AND LD, 81, 150
combining with OR LD, 84
use in logic blocks, 82
AND NOT, 78, 149
ANDW(34), 276
APR(69), 263
ASC(86), 218
ASFT(17), 178
ASL(25), 175
ASR(26), 175
AVG(––), 259
BCD(24), 205
BCDL(59), 206
BCMP(68), 197
BCNT(67), 308
BIN(23), 204
BINL(58), 205
BSET(71), 181
BXF2(––), 191
CLC(41), 229
CMCR(––), 353
CMP(20), 193
Host Link Systems, error bits and flags, 40
Host Link Units, PC cycle time, 365
HR area, 68
CMPL(60), 196
CNT, 166
CNTR(12), 169
COLL(81), 185
COLM(64), 225
COM(29), 275
CPS(––), 202
CPSL(––), 203
DBS(––), 255
I
I/O bit
definition, 29
limits, 29
I/O numbers, 32
DBSL(––), 256
DEC(39), 228
I/O points, refreshing, 306, 307
I/O response time, one-to-one link communications, 383
I/O response times, 376
I/O status, maintaining, 42
I/O table
clearing, 101
reading, 99
registration, 96
verification, 97
Verification Error flag, 43
DIFD(14), 121, 151–152
using in interlocks, 156
using in jumps, 158
DIFU(13), 121, 151–152
using in interlocks, 156
using in jumps, 158
DIST(80), 183
DIV(33), 236
DIVL(57), 237
DMPX(77), 212
DSW(––), 339
I/O Units. See Units
I/O word
allocation, 30
definition, 29
limits, 29
incrementing, 228
indirect addressing, 139
Using EM for indirect addressing, 316
input bit
application, 29
definition, 3
input device, definition, 3
input point, definition, 3
input signal, definition, 3
instruction set, 517
DVB(53), 248
EMBC(––), 317
END(01), 80, 144, 158
execution times, 367–375
FAL(06), 300
FALS(07), 300
FCS(––), 308
FDIV(79), 238
FPD(––), 310
HEX(––), 219
HKY(––), 343
HMS(66), 208
IEMS(––), 316
IL(02), 117, 155–157
557
Index
ILC(03), 117, 155–157
INC(38), 228
SEND(90), 318
SET, 153
SFT(10), 171
INT(89), 287
SFTR(84), 173
SLD(74), 177
SNXT(09), 291
SRCH(––), 314, 315
SRD(75), 177
STC(40), 229
STEP(08), 291
STUP(––), 333
SUB(31), 231
SUBL(55), 233
SUM(––), 261
TCMP(85), 199
TERM(48), 88, 305
terminology, 74
TIM, 159
IORD(––), 350
IORF(97), 306
IOWR(––), 351
JME(05), 157
JMP(04), 157
JMP(04) and JME(05), 119
KEEP(11), 154
in controlling bit status, 121
ladder instructions, 77
LD, 78, 149
LD NOT, 78, 149
LINE(63), 224
LMSG(47), 304
MAX(––), 257
MBS(––), 253
TIMH(15), 164
TKY(––), 346
TRSM(45), 302
TTIM(87), 165
TXD(––), 331
WDT(94), 306
WSFT(16), 178
XCHG(73), 183
XFER(70), 182
XFR2(––), 190
XFRB(62), 189
XNRW(37), 279
XORW(36), 278
ZCP(88), 200
ZCPL(––), 201
MBSL(––), 254
MCMP(19), 192
MCRO(99), 285
MIN(––), 258
MLB(52), 248
MLPX(76), 209
MOV(21), 180
MOVB(82), 187
MOVD(83), 188
MPRF(61), 307
MSG(46), 303
MTR(––), 348
MUL(32), 235
MULL(56), 236
MVN(22), 180
NEG(––), 226
instructions
advanced I/O, 336
NEGL(––), 227
NOP(00), 158
NOT, 76
operands, 74
OR, 79, 149
designations when inputting, 106
instruction set lists, 145
IORF(97), 383
mnemonics list, ladder, 145
combining with AND, 79
OR LD, 82, 150
combining with AND LD, 84
use in logic blocks, 83
OR NOT, 79, 149
ORW(35), 277
OUT, 80, 150
interlocks, 155–157
using self-maintaining bits, 121
interrupts, 279
control, 287
IR area, 29–32
OUT NOT, 80, 150
PID(––), 266
PMCR(––), 335
RECV(98), 323
RET(93), 284
J-L
jump numbers, 157
jumps, 157–158
keyboard mapping, 412
ROL(27), 176
expansion keyboard mapping, 411
ROOT(72), 241
ROR(28), 176
ladder diagram
RSET, 153
branching, 115
RXD(––), 329
SBB(51), 245
IL(02) and ILC(03), 117
using TR bits, 115
SBBL(––), 251
SBN(92), 284
SBS(91), 283
SCAN(18), 301
SCL(––), 222
SDEC(78), 215
SEC(65), 207
controlling bit status
using DIFU(13) and DIFD(14), 121, 151–152
using KEEP(11), 154–159
using OUT and OUT NOT, 80
using SET and RSET, 153
converting to mnemonic code, 76–88
display via SSS, 75
558
Index
instructions
output bit
application, 30
controlling, via Output OFF bit, 42
controlling ON/OFF time, 151
controlling status, 120, 121
definition, 3
combining, AND LD and OR LD, 84
controlling bit status
using KEEP(11), 121
using OUT and OUT NOT, 150
format, 138
output device, definition, 3
output point, definition, 3
output signal, definition, 3
notation, 138
structure, 75
using logic blocks, 81
ladder diagram instructions, 149–150
LEDs. See CPU Unit indicators
leftmost, definition, 26
P
Link System, flags and control bits, 40–41
password, entering on Programming Console, 92
Link Units
See also Units
flags, 55
PC
configuration, 15
definition, 3
flowchart, 361
PC Link Systems
error bits and flags, 40–41
LR area application, 69
logic block instructions, converting to mnemonic code, 81–87
logic blocks. See ladder diagram
logic instructions, 275–279
LR area, 69
PC Setup, 60
default, 60
Peripheral Device Flags, 54
M
mapping, expansion keyboard mapping, 411
memory all clear, 93
memory areas
clearing, 93
Peripheral Devices, Connecting through SYSMAC LINK, 54
peripheral devices, 5
Programming Console, 5, 88–91
SYSMAC Support Software (SSS), 5
peripheral port, communications
receiving, 428
definition, 23
transmitting, 427
Memory Cassettes, transferring C200HS programs, 8
memory clear, 96
power supply, Power OFF Counter, 54
precautions, general, xiii
memory partial clear, 94
present value. See PV
messages, programming, 303, 304
mnemonic code, converting, 76–88
models, C200HS, 501
program execution, 126
Program Memory
setting address and reading content, 104–105
structure, 76
programming
checks for syntax, 108–110
entering and editing, 105
example, using shift register, 172
inputting, modifying and checking, 104–120
inserting and deleting instructions, 112–114
instructions, 517
modifying data, hex/binary, 396
monitoring
binary, 403
differentiation monitoring, 401
monitoring 3 words, 402
mounting Units, location, 15
jumps, 119
precautions, 124
N-O
nesting, subroutines, 283
non-fatal operating errors, 445
normally closed condition, definition, 76
NOT, definition, 76
preparing data in data areas, 181
searching, 111–112
setting and reading from memory address, 104
simplification with differentiated instructions, 152
writing, 74
one-to-one link, wiring, 430
Programming Console, 88–91
See also peripheral devices
one-to-one link communications, I/O response timing, 383
operand bit, 76
programs, transferring from C200H, 8
Protocol Macro function, 433
operands, 138
allowable designations, 138
requirements, 138
PROTOCOL MACRO instruction, 335
PV
accessing via PC area, 69
CNTR(12), 170
timers and counters, 159
operating modes, 91
operation, preparations, 91–103
Optical I/O Unit, Error flag, 51
559
Index
SYSMAC LINK, loop status and completion codes, 38
R
SYSMAC LINK System
Active Node Flags, 52
instructions, 318
service time, 53
Using Peripheral Devices, 54
Racks, types, 15
Remote I/O Master Units, PC cycle time, 365
Remote I/O Systems, error bits and flags, 39
response time calculations, C500 PCs, 380
response times, I/O, 376–387
SYSMAC NET, loop status and completion codes, 38
SYSMAC NET Link System
Data Link Table transferring, 102
instructions, 318
rightmost, definition, 26
RS-232C
communications
one-to-one link, 430
procedures, 426
receiving, 428
service time, 53
SYSMAC Support Software. See peripheral devices
transmitting, 427
connecting Units, 430
RS-232C port, wiring example, 420
T
TC area, 68–69
TC numbers, 68, 159
TERMINAL mode, 88
Key Bits, 54
time, reading and setting the clock, 411
S
self-maintaining bits, using KEEP(11), 154
set value. See SV
timers
bits in TC area, 68
changing SV, 406
conditions when reset, 160, 164
TTIM(120), 165
example using CMP(20), 194
extended timers, 161
flicker bits, 163
settings
communications, host link, 422
Communications Board, 65
PC Setup, 60
Special I/O Unit Area, 67
seven-segment displays, converting data, 215
inputting SV, 106
shift registers, 171–179
ON/OFF delays, 161
one-shot bits, 162
TR area, 71
controlling individual bits, 172
signed binary arithmetic flags, 523
signed binary data, 28
TR bits, use in branching, 115
tracing
See also See data tracing and address tracing.
flags and control bits, 55
Special I/O Unit, programming examples, 126
Special I/O Unit Area, settings, 67
Special I/O Unit Default Area, 57
Special I/O Units. See Units
SR area, 33–48
SSS. See peripheral devices
U-W
UM Area, allocation to expansion DM, 410
UM area, 70
stack operation
COLL(81), 185
DIST(80), 183
status indicators. See CPU Unit indicators
step execution, Step flag, 44
step instructions, 291–300
subroutine number, 284
subroutines, 279–290
SV
accessing via TC area, 69
changing, 406
CNTR(12), 170
timers and counters, 159
Units
definition, 4
High-density I/O Units, definition, 4
I/O Units, definition, 4
Link Units, definition, 4
Special I/O Units, definition, 4
unsigned binary data, 27
watchdog timer, 364
extending, 306
word bit, definition, 24
switches, DIP. See DIP switch
work word, definition, 24
560
Revision History
A manual revision code appears as a suffix to the catalog number on the front cover of the manual.
Cat. No. W303-E1-4
Revision code
The following table outlines the changes made to the manual during each revision. Page numbers refer to the
previous version.
Revision
code
Date
Revised content
1
2
June 1996
Original production
All Pages: “LSS” replaced with “SYSMAC Support Soft-
ware.”
Page 139, 144, 342, 359, 509: CMCR added.
Page 158, 164: Precautions added on programming tim-
ers and counters.
January 1998
Pages xiv, xvi: Cautions added.
Page 7: One “4000” changed to “4096.”
Page 19: Added information on operation without a back-
up battery.
Page 27, 70: CompoBus/D added to IR/SR allocation
table.
Page 237: Program corrected.
Page 265: Corrected graphic (including callout).
Page 267: Added graphics.
Page 278 on: Subroutine numbers corrected to three
digits.
Page 18: Model specifications removed from last table.
Page 30: Note added on Special I/O Unit limitations.
Page 31: Function of SR 25208 corrected.
Pages 43, 44 : Error code tables changed.
Page 47: Function added for AR 0709.
Page 48: Functions added for AR 2411 and AR 2412.
Page 51: Table on clock accuracy added.
Page 89: Power supply cycling information added to step
4 at the top of the page.
Page 264: Modified description of integral time, derivative
time, and time unit.
Page 301: Changed numeric values for WDT(94).
Page 302: “I/O numbers” corrected to “unit numbers.”
Page 311: Added sentence before last table.
Pages 313 to 316: Controller Link information add to
SEND/RECV.
Page 314: Added indirect designation for source/destina-
tion beginning word.
Page 67: I/O comment description changed in table.
Page 58: Paragraph added before table, description of
DM 6602 rewritten, and “6. Peripheral Port Settings (DM
6650 through DM 6654)” removed from list of settings
possible from SSS.
Page 64: Description of Special I/O Unit Settings cor-
rected.
Page 86, 87: Information added on use of SHIFT key to
input hexadecimal A to F.
Page 123: Added “DM 6623.”
Page 321, 322: Notes added.
Page 346: PC card servicing added.
Page 347: Special I/O refresh times corrected.
Page 357: Condition for SRCH corrected.
Page 413: Operand corrected to “#0256.”
Page 416: Information added on use restrictions.
Page 416: Table of maximum number of PTs added and
information added to table.
Page 429: Simplified CPU Unit troubleshooting procedure
added.
Page xiv: Safety precautions rearranged and reworded.
Page 20: Details of communications parameters set in pin
5 of CPU Unit DIP switch changed.
Page 21: Added graphics and Always OFF Flag name.
Page 34 to 37: Changed function details for bits 25412,
26400 to 26403, 26408 to 26411, 26714, 26715, 27004 to
27010, 27200 to 27210, 27303 to 27307, 27503, 27505,
27508 to 27515, 28100 to 28115.
instructions.
3
January 2000
Page 186: Corrected stack pointer details.
Page 187: Changed operand information.
Page 195: Changed operand information.
Page 200: Changed address details.
Page 320: Added EM area designation information for C-se-
ries PCs.
Page 332 and 333: Added operand information.
Page 355: Corrected bit number of SEND(90)/RECV(98)
Enable Flag.
Page 45 and 46: Added error conditions for timeout error.
Page 56: Added information for DM6031.
Page 59: Corrected I/O bus error code.
Page 361: Added refresh times for other Special I/O Units.
Page 428: Added graphic.
Page 430: Changed graphic.
Page 446: Added CPU error information.
Page 447: Added error codes.
Page 468: Corrected beginning words of DM AREA WRITE-
WD command.
Page 61 to 65: Changed minimum servicing time for DM
6613, DM 6614, and DM 6617. Added serial communica-
tions mode for standard port settings in DM 6645 and DM
6650. Changed wording for one-to-one links. Corrected set-
ting for serial communications mode setting in bits 12 to 15
of DM 6650.
Added condition for use of host link mode with the Peripheral
Port.
Page 500 to 503: Corrected and added new model numbers
and specifications.
Page 153: Information added on executing SET and RESET
Page 510 and 511: Corrected model numbers.
4
June 2000
Page v: Minor change made to safety information.
Page 20: Change made to function information for pin 5.
Pages 160, 164, 165: Precautionary information on timers added.
Page 333: Row added to table next to ladder diagram. Note added to middle
graphic and after bottom table.
561
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