Intel® IXF1104 4-Port Gigabit Ethernet
Media Access Controller
Datasheet
The Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller (hereafter referred to as
the IXF1104 MAC) supports IEEE 802.3* 10/100/1000 Mbps applications. The IXF1104 MAC
supports a System Packet Interface Phase 3 (SPI3) system interface to a network processor or
ASIC, and concurrently supports copper and fiber physical layer devices (PHYs).
The copper PHY interface supports the standard and reduced pin-count Gigabit Media
Independent Interface (GMII and RGMII) for high-port-count applications. For fiber
applications the integrated Serializer/Deserializer (SerDes) on each port supports direct
connection to optical modules to reduce PCB area requirements and system cost.
Product Features
Four Independent Ethernet MAC Ports for
Copper or Fiber Physical layer connectivity.
— IEEE 802.3 compliant
Programmable Packet handling
— Filter broadcast, multicast, unicast, VLAN
and errored packets
— Independent Enable/Disable of any port
Copper Mode:
— RGMII for 10/100/1000 Mbps links
— GMII for 1000 Mbps full-duplex links
— IEEE 802.3 MDIO interface
Fiber Mode:
— Automatically pad undersized Tx packets
— Remove CRC from Rx packets
Performance Monitoring and Diagnostics
— RMON Statistics
— CRC calculation and error detection
— Detection of length error, runt, or overly
large packets
— Counters for dropped and errored packets
— Loopback modes
— JTAG boundary scan
— Integrated SerDes interface for direct
connection to 1000BASE-X optical modules
— IEEE 802.3 auto-negotiation or forced mode
— Supports SFP MSA-compatible transceivers
SPI3 interface supports data transfers up to
4 Gbps in both modes:
— 32-bit Multi-PHY mode (133 MHz)
— 4 x 8-bit Single-PHY mode (125 MHz)
IEEE 802.3-compliant Flow Control
.18 μ CMOS process technology
— 1.8 V core, 2.5 V RGMII, GMII, OMI, and
3.3 V SPI3 and CPU
Operating Temperature Ranges:
— Copper Mode: -40°C to +85°C
— Loss-less up to 9.6 KB packets and 5 km links
— Jumbo frame support for 9.6 KB packets
Internal per-channel FIFOs: 32 KB Rx, 10 KB Tx
Flexible 32/16/8-bit CPU interface
— Fiber Mode:
Package Options:
0°C to +70°C
— 552-ball Ceramic BGA (standard)
552-ball Ceramic BGA (RoHS-compliant)
—
— 552-ball Plastic FC-BGA (contact your Intel
Sales Representative)
Applications
Load Balancing Systems
MultiService Switches
Web Caching Appliances
Intelligent Backplane Interfaces
Edge Routers
Base Station Controllers and Transceivers
Serving GPRS Support Nodes (SGSN)
Gateway GPRS Support Nodes (GGSN)
Packet Data Serving Nodes (PDSN)
DSL Access Multiplexers (DSLAM)
Cable Modem Termination Systems (CMTS)
Redundant Line Cards
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Contents
Contents
1.0 Introduction..................................................................................................................................20
What You Will Find in This Document ................................................................................20
Related Documents ............................................................................................................20
2.0 General Description ....................................................................................................................21
3.0 Ball Assignments and Ball List Tables......................................................................................23
Ball Assignments ................................................................................................................23
Ball List Tables ...................................................................................................................24
3.2.1 Balls Listed in Alphabetic Order by Signal Name ..................................................24
3.2.2 Balls Listed in Alphabetic Order by Ball Location ..................................................30
4.0 Ball Assignments and Signal Descriptions ..............................................................................37
4.1.1 Signal Name Conventions .....................................................................................37
4.1.2 Register Address Conventions ..............................................................................37
Interface Signal Groups ......................................................................................................38
Signal Description Tables...................................................................................................39
Ball Usage Summary..........................................................................................................57
Multiplexed Ball Connections..............................................................................................58
4.5.2 SPI3 MPHY/SPHY Ball Connections.....................................................................59
Ball State During Reset ......................................................................................................61
Power Supply Sequencing..................................................................................................63
4.7.1 Power-Up Sequence..............................................................................................63
4.7.2 Power-Down Sequence .........................................................................................63
Pull-Up/Pull-Down Ball Guidelines......................................................................................64
5.0 Functional Descriptions..............................................................................................................66
Media Access Controller (MAC) .........................................................................................66
5.1.1 Features for Fiber and Copper Mode ....................................................................67
5.1.1.2 Automatic CRC Generation ...................................................................67
5.1.1.3 Filtering of Receive Packets ..................................................................67
5.1.1.4 CRC Error Detection ..............................................................................69
5.1.2 Flow Control...........................................................................................................69
5.1.3 Mixed-Mode Operation ..........................................................................................75
5.1.3.2 Key Configuration Registers ..................................................................75
5.1.4 Fiber Mode.............................................................................................................76
5.1.4.1 Fiber Auto-Negotiation...........................................................................77
5.1.4.3 Fiber Forced Mode.................................................................................77
5.1.5 Copper Mode .........................................................................................................77
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5.1.5.1 Speed.....................................................................................................78
5.1.5.2 Duplex....................................................................................................78
5.1.5.3 Copper Auto-Negotiation .......................................................................78
5.1.6 Jumbo Packet Support ..........................................................................................78
5.1.6.1 Rx Statistics ...........................................................................................79
5.1.6.2 TX Statistics...........................................................................................79
5.1.6.3 Loss-less Flow Control...........................................................................79
5.1.7 Packet Buffer Dimensions .....................................................................................80
5.1.7.1 TX and RX FIFO Operation ...................................................................80
5.1.8 RMON Statistics Support.......................................................................................80
5.1.8.1 Conventions...........................................................................................82
5.1.8.2 Advantages............................................................................................83
SPI3 Interface.....................................................................................................................83
5.2.1 MPHY Operation....................................................................................................84
5.2.2 MPHY Logical Timing ............................................................................................84
5.2.2.1 Transmit Timing .....................................................................................85
5.2.2.2 Receive Timing ......................................................................................85
5.2.2.3 Clock Rates............................................................................................87
5.2.2.4 Parity......................................................................................................87
5.2.2.5 SPHY Mode ...........................................................................................87
5.2.2.6 SPHY Logical Timing.............................................................................88
5.2.2.7 Transmit Timing (SPHY)........................................................................88
5.2.2.8 Receive Timing (SPHY).........................................................................88
5.2.2.9 SPI3 Flow Control..................................................................................91
5.2.3 Pre-Pending Function............................................................................................93
Gigabit Media Independent Interface (GMII) ......................................................................93
5.3.1 GMII Signal Multiplexing........................................................................................94
5.3.2 GMII Interface Signal Definition.............................................................................94
Reduced Gigabit Media Independent Interface (RGMII) ....................................................96
5.4.1 Multiplexing of Data and Control............................................................................96
5.4.2 Timing Specifics.....................................................................................................97
5.4.3 TX_ER and RX_ER Coding...................................................................................97
5.4.3.1 In-Band Status .......................................................................................99
5.4.4 10/100 Mbps Functionality.....................................................................................99
MDIO Control and Interface................................................................................................99
5.5.1 MDIO Address.....................................................................................................100
5.5.2 MDIO Register Descriptions ................................................................................100
5.5.3 Clear When Done ................................................................................................100
5.5.4 MDC Generation..................................................................................................100
5.5.5 Management Frames...........................................................................................101
5.5.6 Single MDI Command Operation.........................................................................101
5.5.7 MDI State Machine ..............................................................................................101
5.5.8 Autoscan Operation.............................................................................................103
SerDes Interface...............................................................................................................103
5.6.1 Features...............................................................................................................103
5.6.2 Functional Description .........................................................................................103
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Contents
5.6.2.3 Receiver Operational Overview ...........................................................105
5.6.2.4 Selective Power-Down.........................................................................105
5.6.2.5 Receiver Jitter Tolerance .....................................................................105
5.6.2.6 Transmit Jitter ......................................................................................106
5.6.2.7 Receive Jitter .......................................................................................106
Optical Module Interface...................................................................................................107
5.7.2 Functional Descriptions .......................................................................................108
5.7.2.1 High-Speed Serial Interface.................................................................108
5.7.3 I²C Module Configuration Interface......................................................................110
5.7.3.1 I2C Control and Data Registers............................................................110
5.7.3.2 I2C Read Operation..............................................................................110
5.7.3.3 I2C Write Operation..............................................................................111
5.7.3.4 I²C Protocol Specifics...........................................................................112
5.7.3.5 Port Protocol Operation .......................................................................113
5.7.3.6 Clock and Data Transitions..................................................................113
LED Interface....................................................................................................................115
5.8.1 Modes of Operation .............................................................................................115
5.8.2 LED Interface Signal Description.........................................................................116
5.8.3 Mode 0: Detailed Operation.................................................................................116
5.8.4 Mode 1: Detailed Operation.................................................................................117
5.8.5 Power-On, Reset, Initialization ............................................................................118
5.8.6 LED DATA Decodes............................................................................................118
5.8.6.1 LED Signaling Behavior .......................................................................119
CPU Interface ...................................................................................................................120
5.9.1 Functional Description .........................................................................................121
5.9.1.1 Read Access........................................................................................121
5.9.1.2 Write Access ........................................................................................121
5.9.1.3 CPU Timing Parameters......................................................................122
5.10 TAP Interface (JTAG) .......................................................................................................123
5.10.1 TAP State Machine..............................................................................................123
5.10.2 Instruction Register and Supported Instructions..................................................124
5.10.3 ID Register...........................................................................................................125
5.10.4 Boundary Scan Register......................................................................................125
5.10.5 Bypass Register...................................................................................................125
5.11 Loopback Modes ..............................................................................................................125
5.11.1 SPI3 Interface Loopback .....................................................................................125
5.11.2 Line Side Interface Loopback ..............................................................................126
5.12 Clocks...............................................................................................................................127
5.12.1 System Interface Reference Clocks.....................................................................127
5.12.1.1 CLK125 ................................................................................................128
5.12.2 SPI3 Receive and Transmit Clocks .....................................................................128
5.12.3 RGMII Clocks.......................................................................................................128
5.12.4 MDC Clock...........................................................................................................128
5.12.5 JTAG Clock..........................................................................................................129
5.12.6 I2C Clock..............................................................................................................129
5.12.7 LED Clock............................................................................................................129
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Contents
6.0 Applications...............................................................................................................................130
Change Port Mode Initialization Sequence.......................................................................130
Disable and Enable Port Sequences................................................................................131
6.2.1 Disable Port Sequence........................................................................................131
6.2.2 Enable Port Sequence.........................................................................................131
7.0 Electrical Specifications ...........................................................................................................132
DC Specifications .............................................................................................................133
7.1.1 Undershoot / Overshoot Specifications ...............................................................135
7.1.2 RGMII Electrical Characteristics..........................................................................135
SPI3 AC Timing Specifications.........................................................................................137
7.2.1 Receive Interface Timing.....................................................................................137
7.2.2 Transmit Interface Timing....................................................................................139
RGMII AC Timing Specification ........................................................................................141
GMII AC Timing Specification...........................................................................................142
7.4.1 1000 Base-T Operation .......................................................................................142
SerDes AC Timing Specification.......................................................................................144
MDIO AC Timing Specification.........................................................................................145
7.6.1 MDC High-Speed Operation Timing....................................................................145
7.6.2 MDC Low-Speed Operation Timing.....................................................................145
7.6.3 MDIO AC Timing..................................................................................................146
Optical Module and I2C AC Timing Specification .............................................................147
7.7.1 I2C Interface Timing.............................................................................................147
CPU AC Timing Specification...........................................................................................149
7.8.1 CPU Interface Read Cycle AC Timing.................................................................149
7.8.2 CPU Interface Write Cycle AC Timing.................................................................149
Transmit Pause Control AC Timing Specification.............................................................151
7.10 JTAG AC Timing Specification .........................................................................................152
7.11 System AC Timing Specification.......................................................................................153
7.12 LED AC Timing Specification............................................................................................154
8.0 Register Set................................................................................................................................155
Graphical Representation.................................................................................................155
Per Port Registers ............................................................................................................156
Register Map ....................................................................................................................156
8.4.1 MAC Control Registers........................................................................................163
8.4.2 MAC RX Statistics Register Overview.................................................................174
8.4.3 MAC TX Statistics Register Overview .................................................................178
8.4.4 PHY Autoscan Registers .....................................................................................181
8.4.5 Global Status and Configuration Register Overview ...........................................188
8.4.6 RX FIFO Register Overview ................................................................................193
8.4.7 TX FIFO Register Overview.................................................................................203
8.4.8 MDIO Register Overview.....................................................................................211
8.4.9 SPI3 Register Overview.......................................................................................213
8.4.10 SerDes Register Overview ..................................................................................220
8.4.11 Optical Module Register Overview ......................................................................222
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Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Contents
9.0 Mechanical Specifications........................................................................................................224
Overview...........................................................................................................................224
9.1.1 Features...............................................................................................................224
Package Specifics ............................................................................................................224
Package Information.........................................................................................................225
9.3.1 CBGA Package Diagrams ...................................................................................225
9.3.2 Flip Chip-Plastic Ball Grid Array Package Diagram.............................................227
9.3.3 Top Label Marking Example ................................................................................229
10.0 Product Ordering Information ..................................................................................................230
Figures
Block Diagram ............................................................................................................................21
552-Ball CBGA Assignments (Top View) ...................................................................................23
Interface Signals ........................................................................................................................38
Power Supply Sequencing..........................................................................................................63
Packet Buffering FIFO ................................................................................................................71
Ethernet Frame Format ..............................................................................................................71
PAUSE Frame Format................................................................................................................72
10 Transmit Pause Control Interface...............................................................................................74
11 MPHY Transmit Logical Timing ..................................................................................................85
12 MPHY Receive Logical Timing ...................................................................................................86
13 MPHY 32-Bit Interface................................................................................................................86
14 SPHY Transmit Logical Timing...................................................................................................88
15 SPHY Receive Logical Timing....................................................................................................89
16 SPHY Connection for Two Intel® IXF1104 MAC Ports (8-Bit Interface) .....................................90
17 MAC GMII Interconnect ..............................................................................................................94
18 RGMII Interface ..........................................................................................................................96
19 TX_CTL Behavior .......................................................................................................................98
20 RX_CTL Behavior.......................................................................................................................98
21 Management Frame Structure (Single-Frame Format) ............................................................101
22 MDI State..................................................................................................................................102
23 SerDes Receiver Jitter Tolerance.............................................................................................106
24 I2C Random Read Transaction.................................................................................................111
25 Data Validity Timing..................................................................................................................113
26 Start and Stop Definition Timing...............................................................................................113
27 Acknowledge Timing.................................................................................................................114
28 Random Read...........................................................................................................................115
29 Mode 0 Timing..........................................................................................................................116
30 Mode 1 Timing..........................................................................................................................118
31 Read Timing Diagram - Asynchronous Interface......................................................................121
32 Write Timing Diagram - Asynchronous Interface......................................................................122
33 SPI3 Interface Loopback Path..................................................................................................126
34 Line Side Interface Loopback Path...........................................................................................127
35 SPI3 Receive Interface Timing .................................................................................................137
36 SPI3 Transmit Interface Timing ................................................................................................139
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37 RGMII Interface Timing ............................................................................................................141
38 1000BASE-T Transmit Interface Timing...................................................................................142
39 1000BASE-T Receive Interface Timing....................................................................................143
40 SerDes Timing Diagram ...........................................................................................................144
41 MDC High-Speed Operation Timing.........................................................................................145
42 MDC Low-Speed Operation Timing..........................................................................................145
43 MDIO Write Timing Diagram ....................................................................................................146
44 MDIO Read Timing Diagram ....................................................................................................146
45 Bus Timing Diagram .................................................................................................................147
46 Write Cycle Diagram.................................................................................................................147
47 CPU Interface Read Cycle AC Timing......................................................................................149
48 CPU Interface Write Cycle AC Timing......................................................................................149
49 Pause Control Interface Timing................................................................................................151
50 JTAG AC Timing.......................................................................................................................152
51 System Reset AC Timing .........................................................................................................153
52 LED AC Interface Timing..........................................................................................................154
53 Memory Overview Diagram ......................................................................................................155
54 Register Overview Diagram......................................................................................................156
55 CBGA Package Diagram..........................................................................................................225
56 CBGA Package Side View Diagram.........................................................................................226
57 FC-PBGA Package (Top and Bottom Views)...........................................................................227
58 FC-PBGA Mechanical Specifications .......................................................................................228
59 Package Marking Example.......................................................................................................229
60 Ordering Information – Sample ................................................................................................230
Tables
Ball List in Alphanumeric Order by Signal Name........................................................................24
Ball List in Alphanumeric Order by Ball Location........................................................................30
SPI3 Interface Signal Descriptions.............................................................................................39
SerDes Interface Signal Descriptions.........................................................................................47
GMII Interface Signal Descriptions.............................................................................................48
RGMII Interface Signal Descriptions ..........................................................................................50
Transmit Pause Control Interface Signal Descriptions ...............................................................53
Optical Module Interface Signal Descriptions.............................................................................53
10 MDIO Interface Signal Descriptions ........................................................................................... 54
11 LED Interface Signal Descriptions..............................................................................................55
12 JTAG Interface Signal Descriptions............................................................................................55
13 System Interface Signal Descriptions.........................................................................................55
14 Power Supply Signal Descriptions..............................................................................................56
15 Ball Usage Summary..................................................................................................................57
16 Line Side Interface Multiplexed Balls..........................................................................................58
17 SPI3 MPHY/SPHY Interface.......................................................................................................59
18 Definition of Output and Bi-directional Balls During Hardware Reset.........................................61
19 Power Supply Sequencing .........................................................................................................64
20 Pull-Up/Pull-Down and Unused Ball Guidelines .........................................................................64
21 Analog Power Balls ....................................................................................................................65
22 CRC Errored Packets Drop Enable Behavior.............................................................................69
23 Valid Decodes for TXPAUSEADD[2:0].......................................................................................74
24 Operational Mode Configuration Registers ................................................................................76
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Contents
25 RMON Additional Statistics.........................................................................................................81
26 GMII Interface Signal Definitions ................................................................................................95
27 RGMII Signal Definitions.............................................................................................................97
28 TX_ER and RX_ER Coding Description.....................................................................................97
29 SerDes Driver TX Power Levels...............................................................................................104
30 Intel® IXF1104 MAC-to-SFP Optical Module Interface Connections........................................107
31 LED Interface Signal Descriptions............................................................................................116
32 Mode 0 Clock Cycle to Data Bit Relationship ...........................................................................117
33 Mode 1 Clock Cycle to Data Bit Relationship ...........................................................................118
34 LED_DATA# Decodes..............................................................................................................119
35 LED Behavior (Fiber Mode)......................................................................................................119
36 LED Behavior (Copper Mode) ..................................................................................................120
37 Byte Swapper Behavior ............................................................................................................123
38 Instruction Register Description................................................................................................124
39 Absolute Maximum Ratings......................................................................................................132
40 Recommended Operating Conditions.......................................................................................133
41 DC Specifications .....................................................................................................................134
42 SerDes Transmit Characteristics..............................................................................................134
43 SerDes Receive Characteristics...............................................................................................135
44 Undershoot / Overshoot Limits .................................................................................................135
45 RGMII Power ............................................................................................................................136
46 SPI3 Receive Interface Signal Parameters ..............................................................................138
47 SPI3 Transmit Interface Signal Parameters .............................................................................140
48 RGMII Interface Timing Parameters.........................................................................................141
49 GMII 1000BASE-T Transmit Signal Parameters ......................................................................142
50 GMII 1000BASE-T Receive Signal Parameters .......................................................................143
51 SerDes Timing Parameters ......................................................................................................144
52 MDIO Timing Parameters.........................................................................................................146
53 I2C AC Timing Characteristics ..................................................................................................147
54 CPU Interface Write Cycle AC Signal Parameters ...................................................................150
55 Transmit Pause Control Interface Timing Parameters..............................................................151
56 JTAG AC Timing Parameters ...................................................................................................152
57 System Reset AC Timing Parameters......................................................................................153
58 LED Interface AC Timing Parameters ......................................................................................154
59 MAC Control Registers ($ Port Index + Offset) ........................................................................156
60 MAC RX Statistics Registers ($ Port Index + Offset)................................................................157
61 MAC TX Statistics Registers ($ Port Index + Offset) ................................................................158
62 PHY Autoscan Registers ($ Port Index + Offset)......................................................................159
63 Global Status and Configuration Registers ($ 0x500 - 0X50C) ................................................159
64 RX FIFO Registers ($ 0x580 - 0x5BF)......................................................................................159
65 TX FIFO Registers ($ 0x600 - 0x63E) ......................................................................................160
66 MDIO Registers ($ 0x680 - 0x683)...........................................................................................161
67 SPI3 Registers ($ 0x700 - 0x716).............................................................................................161
68 SerDes Registers ($ 0x780 - 0x798) ........................................................................................162
69 Optical Module Registers ($ 0x799 - 0x79F) ............................................................................162
70 Station Address ($ Port_Index +0x00 – +0x01)........................................................................163
71 Desired Duplex ($ Port_Index + 0x02) .....................................................................................163
72 FD FC Type ($ Port_Index + 0x03) ..........................................................................................163
73 Collision Distance ($ Port_Index + 0x05) .................................................................................164
74 Collision Threshold ($ Port_Index + 0x06) ...............................................................................164
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75 FC TX Timer Value ($ Port_Index + 0x07) ...............................................................................164
76 FD FC Address ($ Port_Index + 0x08 – + 0x09) ......................................................................164
77 IPG Receive Time 1 ($ Port_Index + 0x0A) .............................................................................165
78 IPG Receive Time 2 ($ Port_Index + 0x0B) .............................................................................165
79 IPG Transmit Time ($ Port_Index + 0x0C) ...............................................................................165
80 Pause Threshold ($ Port_Index + 0x0E) ..................................................................................166
81 Max Frame Size (Addr: Port_Index + 0x0F).............................................................................166
82 MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)..........................................................167
83 Flush TX ($ Port_Index + 0x11)................................................................................................167
84 FC Enable ($ Port_Index + 0x12).............................................................................................168
85 FC Back Pressure Length ($ Port_Index + 0x13).....................................................................168
86 Short Runts Threshold ($ Port_Index + 0x14)..........................................................................169
87 Discard Unknown Control Frame ($ Port_Index + 0x15)..........................................................169
88 RX Config Word ($ Port_Index + 0x16)....................................................................................169
89 TX Config Word ($ Port_Index + 0x17) ....................................................................................170
90 Diverse Config Write ($ Port_Index + 0x18).............................................................................171
91 RX Packet Filter Control ($ Port_Index + 0x19) .......................................................................172
92 Port Multicast Address ($ Port_Index +0x1A – +0x1B) ............................................................173
93 MAC RX Statistics ($ Port_Index + 0x20 – + 0x39)..................................................................174
94 MAC TX Statistics ($ Port_Index +0x40 – +0x58) ....................................................................178
95 PHY Control ($ Port Index + 0x60)...........................................................................................181
96 PHY Status ($ Port Index + 0x61) ............................................................................................182
97 PHY Identification 1 ($ Port Index + 0x62) ...............................................................................183
98 PHY Identification 2 ($ Port Index + 0x63) ...............................................................................184
99 Auto-Negotiation Advertisement ($ Port Index + 0x64) ............................................................184
100 Auto-Negotiation Link Partner Base Page Ability ($ Port Index + 0x65)...................................185
101 Auto-Negotiation Expansion ($ Port Index + 0x66) ..................................................................186
102 Auto-Negotiation Next Page Transmit ($ Port Index + 0x67) ...................................................187
103 Port Enable ($0x500)................................................................................................................188
104 Interface Mode ($0x501) ..........................................................................................................188
105 Link LED Enable ($0x502)........................................................................................................189
106 MAC Soft Reset ($0x505).........................................................................................................189
107 MDIO Soft Reset ($0x506) .......................................................................................................190
108 CPU Interface ($0x508)............................................................................................................190
109 LED Control ($0x509)...............................................................................................................190
110 LED Flash Rate ($0x50A).........................................................................................................191
111 LED Fault Disable ($0x50B).....................................................................................................191
112 JTAG ID ($0x50C) ....................................................................................................................192
113 RX FIFO High Watermark Port 0 ($0x580)...............................................................................193
114 RX FIFO High Watermark Port 1 ($0x581)...............................................................................193
115 RX FIFO High Watermark Port 2 ($0x582)...............................................................................193
116 RX FIFO High Watermark Port 3 ($0x583)...............................................................................194
117 RX FIFO Low Watermark Port 0 ($0x58A)...............................................................................194
118 RX FIFO Low Watermark Port 1 ($0x58B)...............................................................................194
119 RX FIFO Low Watermark Port 2 ($0x58C)...............................................................................195
120 RX FIFO Low Watermark Port 3 ($0x58D)...............................................................................195
121 RX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x594 – 0x597)....................................195
122 RX FIFO Port Reset ($0x59E)..................................................................................................196
123 RX FIFO Errored Frame Drop Enable ($0x59F).......................................................................196
124 RX FIFO Overflow Event ($0x5A0) ..........................................................................................197
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125 RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5)......................................198
126 RX FIFO SPI3 Loopback Enable for Ports 0 - 3 ($0x5B2)........................................................199
127 RX FIFO Padding and CRC Strip Enable ($0x5B3) .................................................................200
128 RX FIFO Transfer Threshold Port 0 ($0x5B8)..........................................................................201
129 RX FIFO Transfer Threshold Port 1 ($0x5B9)..........................................................................201
130 RX FIFO Transfer Threshold Port 2 ($0x5BA)..........................................................................202
131 RX FIFO Transfer Threshold Port 3 ($0x5BB)..........................................................................202
132 TX FIFO High Watermark Ports 0 - 3 ($0x600 – 0x603) ..........................................................203
133 TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A – 0x60D)............................................204
134 TX FIFO MAC Threshold Register Ports 0 - 3 ($0x614 – 0x617).............................................205
135 TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E)..............................................206
136 Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F) ...................................207
137 TX FIFO Port Reset ($0x620)...................................................................................................207
138 TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624) ....................................208
140 TX FIFO Occupancy Counter for Ports 0 - 3 ($0x62D – 0x630)...............................................210
142 MDIO Single Command ($0x680).............................................................................................211
144 Autoscan PHY Address Enable ($0x682).................................................................................212
146 SPI3 Transmit and Global Configuration ($0x700)...................................................................213
147 SPI3 Receive Configuration ($0x701) ......................................................................................215
148 Address Parity Error Packet Drop Counter ($0x70A) ...............................................................219
149 TX Driver Power Level Ports 0 - 3 ($0x784).............................................................................220
150 TX and RX Power-Down ($0x787) ...........................................................................................220
151 RX Signal Detect Level Ports 0 - 3 ($0x793)............................................................................220
152 Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794) ..............................................221
153 Optical Module Status Ports 0-3 ($0x799)................................................................................222
154 Optical Module Control Ports 0 - 3 ($0x79A)............................................................................222
155 I2C Control Ports 0 - 3 ($0x79B)...............................................................................................223
156 I2C Data Ports 0 - 3 ($0x79F)...................................................................................................223
157 Product Information ..................................................................................................................230
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Document Number: 278757
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Contents
Revision History
Revision Number: 009
Revision Date: 27-Oct-2005
Page #
Description
supports random single-byte reads and does not guarantee coherency when reading two-byte
registers.
249
Modified Table 208 “I2C Data Ports 0 - 9 ($0x79F)” (changed address from $0x79C to $0x79F).
Revision Number: 008
Revision Date: August 1, 2005 (Sheet 1 of 2)
Page #
Description
Added 552-ball Ceramic Ball Grid Array (CBGA) compliant with RoHS and Product Ordering
Number information.
2.5 V CMOS.
to uPx_ADD[10:0].
changed VIN value to VDD + .3].
45 min and 55 max; Changed Min for RFCLK frequency to 90].
45 min and 55 max].
12
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Contents
Revision Number: 008
Revision Date: August 1, 2005 (Sheet 2 of 2)
Page #
Description
register from “0x0001A0” to “0x000001A0” and changed default value for bit 6 (Half Duplex)
from 1 to 0].
descriptions of register” and register default value].
of register” and register default value].
descriptions of register” and register default value].
descriptions of register” and register default value].
sentence descriptions of register” and register default value].
[added “Need one-sentence descriptions of register” and register default value].
sentence descriptions of register” and register default value].
one-sentence descriptions of register” and register default value].
“MDIO write data to external device”].
for bits 3:0 from “0” to “1” and changed default value for entire register from “0x0020000F” to
“0x00200000”].
from “0xF” to “0x1”].
bits 16:13 from “0xF” to “0x1”].
229
Added Section 9.4, “RoHS Compliance” on page 229.
Datasheet
13
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Contents
Revision Number: 007
Revision Date: March 24, 2004
(Sheet 1 of 5)
Page # Description
All
All
Globally replaced GBIC with Optical Module Interface.
Globally edited signal names.
Globally changed SerDes and PLL analog power ball names as follows:
TXAVTT and RXAVTT changed to AVDD1P8_2
TXAV25 and RXAV25 changed to AVDD2P5_2
All
PLL1_VDDA and PLL2_VDDA changed to AVDD1P8_1
PLL3_VDDA changed to AVDD2P5_1
PLL1_GNDA, PLL2_GNDA, and PLL3_GNDA changed to GND
Reworded and rearranged the Product Features section on page one
Changed Jumbo frame support from “10 kbytes” to “9.6 KB”.
1
21
Changed heading to Section 2.0, “General Description” [was Section 2.0, “Block Diagram”].
Reversed sections as follows:
23/37
Section 3.0, “Ball Assignments and Ball List Tables”
Section 4.0, “Ball Assignments and Signal Descriptions”
Modified Table 1 “Ball List in Alphanumeric Order by Signal Name”:
Changed A10 from VCC to VDD
Changed C12 from VCC to VDD
Changed D11 from VCC to VDD
24
Changed J20 from GND to VDD
Changed Ball A1 from NC to No Pad.
Changed Balls A2, A3, A22, A23, A24, B1, B2, B23, B24, C1, C24, AB1, AB24, AC1, AC2, AC23,
AC24, AD1, AD2, AD3, AD22, AD23, AD24 from NC to No Ball.
Modified Table 2 “Ball List in Alphanumeric Order by Ball Location”
Changed A10 from VCC to VDD
Changed C12 form VCC to VDD
Changed D11 from VCC to VDD
30
Changed J20 from GND to VDD
Changed Ball A1 from NC to No Pad.
Changed Balls A2, A3, A22, A23, A24, B1, B2, B23, B24, C1, C24, AB1, AB24, AC1, AC2, AC23,
AC24, AD1, AD2, AD3, AD22, AD23, AD24 from NC to No Ball.
Updated Figure 4 “Interface Signals” [modified SPI3 interface signals and added MPHY and SPHY
categories; modified signal names].
38
39
Broke old Table 1, “IXF1104 Signal Descriptions” into the following:
Table 3 “SPI3 Interface Signal Descriptions” on page 39 through Table 14 “Power Supply Signal
Descriptions” on page 56
Modified Table 3 “SPI3 Interface Signal Descriptions” on page 39 [edited description for DTPA;
added text to TFCLK description; added text to RFCLK description].
39
50
Modified Table 6 “RGMII Interface Signal Descriptions” [Added Ball Designators; added notes
under descriptions].
51
53
54
Modified Table 7 “CPU Interface Signal Descriptions” [UPX_DATA[16]: deleted J10, added M10].
Modified Table 9 “Optical Module Interface Signal Descriptions” [added Ball Designators].
Modified Table 10 “MDIO Interface Signal Descriptions” [moved note from MDC to MDIO].
Modified Table 14 “Power Supply Signal Descriptions” [added Ball Designators A4, A21, and AD21
to GND; added AVDD1P8_1, AVDD1P8_2, AVDD2P5_1, and AVDD2P5_2].
56
14
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Contents
Revision Number: 007
Revision Date: March 24, 2004
(Sheet 2 of 5)
Page # Description
Modified Section 4.3, “Signal Description Tables” [changed heading from “Signal Naming
Conventions; added new headings Section 4.1.1, “Signal Name Conventions” and Section 4.1.2,
“Register Address Conventions”; and added/enhanced material under headings.
39
Added new Section 4.5, “Multiplexed Ball Connections” with Table 16 “Line Side Interface
Multiplexed Balls” and Table 17 “SPI3 MPHY/SPHY Interface”.
58
63
63
61
64
64
66
Modified Section 4.7, “Power Supply Sequencing” [changed language under this section and added
Section 4.7.1, “Power-Up Sequence” and Section 4.7.2, “Power-Down Sequence”].
Modified Table 5 “Power Supply Sequencing” [deleted 3.3 V Supplies Stable; changed Apply 1.8 V
to VDD, AVDD1P8_1, and AVDD1P8_2; changed Apply 2.5 V to AVDD2P5_1 and AVDD2P5_2].
Modified Table 18 “Definition of Output and Bi-directional Balls During Hardware Reset” [changed
comments for Optical Modules].
Modified Table 20 “Pull-Up/Pull-Down and Unused Ball Guidelines” [changed TRST_L to pull-down;
added MDIO, UPX_RDY_L, I2C_DATA_3:0, and TX_DISABLE_3:0].
Added new Section 4.9, “Analog Power Filtering” [including Figure 6 “Analog Power Supply Filter
Network” on page 65 and Table 21 “Analog Power Balls” on page 65].
Modified/edited text under Section 5.1, “Media Access Controller (MAC)” [rearranged and created
new bullets].
67
67
68
69
Modified first paragraph under Section 5.1.1.1, “Padding of Undersized Frames on Transmit”.
Modified entire Section 5.1.1.3, “Filtering of Receive Packets”.
Added new Section 5.1.1.3.6, “Filter CRC Error Packets”.
Added note under Table 22 “CRC Errored Packets Drop Enable Behavior”.
Added new Section 5.1.2, “Flow Control” including Figure 7 “Packet Buffering FIFO”, Figure 8
“Ethernet Frame Format”, and Figure 9 “PAUSE Frame Format”.
69
73
Replaced Section 5.1.2.1.5, “Transmit Pause Control Interface” [added Table 23 “Valid Decodes for
TXPAUSEADD[2:0]” and modified Table 10 “Transmit Pause Control Interface”.
74
75
76
77
79
Modified Figure 10 “Transmit Pause Control Interface”
Added note under Section 5.1.3.1, “Configuration”.
Added table note to Table 24 “Operational Mode Configuration Registers”.
Added note under Section 5.1.4.3, “Fiber Forced Mode”.
Modified Section 5.1.6.2, “TX Statistics” [added text to third sentence in first paragraph].
Modified Section 5.1.6.3, “Loss-less Flow Control” [changed “two kilometers” to “five kilometers” in
last sentence.
79
80
83
86
Modified Section 5.1.7.1.2, “RX FIFO” [changed 10 KB to 9.6 KB; added text to last paragraph].
Rewrote/replaced Section 5.2, “SPI3 Interface”.
Edited signal names in Figure 13 “MPHY 32-Bit Interface”.
Edited signal names in Figure 16 “SPHY Connection for Two Intel® IXF1104 MAC Ports (8-Bit
Interface)”.
90
Added new Section 5.2.2.9, “SPI3 Flow Control”.
[Removed old “Packet-Level and Byte-Level Transfers” section.}
91
94
Modified Figure 17 “MAC GMII Interconnect” [edited signal names].
Removed old Section 5.3.3 Electrical Requirements and Table 27 “Electrical Requirements” –
changed Input high current Max from 40 to 15 and Input low current Min from -600 to -15.
NA
96
96
Added a note under Section 5.4, “Reduced Gigabit Media Independent Interface (RGMII)”.
Modified Figure 18 “RGMII Interface” [edited signal names].
Datasheet
15
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Contents
Revision Number: 007
Revision Date: March 24, 2004
(Sheet 3 of 5)
Page # Description
98
98
Modified Figure 19 “TX_CTL Behavior” [changed signal names].
Modified Figure 20 “RX_CTL Behavior” [changed signal names].
Modified Section 5.5, “MDIO Control and Interface” [changed 3.3 us to 3.3 ms in fourth paragraph,
third sentence].
99
Modified/replaced all text under Section 5.6, “SerDes Interface” on page 103 [added Table 29
“SerDes Driver TX Power Levels”].
103
NA
NA
Removed old Section 5.6.2.4 AC/DC Coupling.
Removed old Section 5.6.2.9 System Jitter.
Modified Table 30 “Intel® IXF1104 MAC-to-SFP Optical Module Interface Connections” [edited
signal names].
107
107
Modified/replaced text and deleted old “Figure 19. Typical GBIC Module Functional Diagram” under
Section 5.7, “Optical Module Interface”].
108
109
109
110
111
Modified second sentence under Section 5.7.2.2.1, “MOD_DEF_0:3”.
Modified second sentence under Section 5.7.2.2.3, “RX_LOS_0:3”.
Removed third paragraph under Section 5.7.2.2.7, “RX_LOS_INT”.
Modified first and second paragraphs under Section 5.7.3, “I²C Module Configuration Interface”.
Modified Section 5.7.3.3, “I2C Write Operation” [edited portions of text].
Modified Table 31 “LED Interface Signal Descriptions” [changed 0.5 MHz to 720 Hz for LED_CLK
under Signal Description].
116
119
Modified Table 35 “LED Behavior (Fiber Mode)” [changed links under Description to “Link LED
Enable ($0x502)”].
NA
123
123
126
126
127
127
129
130
Removed old Figure 30 “CPU – External and Internal Connections”.
Modified Table 37 “Byte Swapper Behavior” [edited/added new values].
Modified second paragraph under Section 5.10, “TAP Interface (JTAG)”
Modified Figure 33 “SPI3 Interface Loopback Path”.
Added note under Section 5.11.2, “Line Side Interface Loopback”.
Modified Figure 34 “Line Side Interface Loopback Path”.
Changed Section 5.12, “Clocks” [from GBIC output clock to I2C Clock].
Changed Section 5.12.6, “I2C Clock” [from GBIC Clock to I2C Clock].
Added new Section 6.0, “Applications”.
Modified Table 39 “Absolute Maximum Ratings” [changed SerDes analog power to AVDD1P8_2
and AVDD2P5_2; changed “PLL1_VDDA and PLL2_VDDA to AVDD1P8_1; changed PLL3_VDDA
to AVDD2P5_1.
132
133
Modified Table 40 “Recommended Operating Conditions” [changed SerDes analog power to
AVDD1P8_2 and AVDD2P5_2; changed “PLL1_VDDA and PLL2_VDDA to AVDD1P8_1; changed
PLL3_VDDA to AVDD2P5_1.
Modified Table 42 “SerDes Transmit Characteristics” [included SerDes power driver level
information].
134
142
143
146
Modified Table 49 “GMII 1000BASE-T Transmit Signal Parameters” (changed Min values for t1 and
t2.
Modified Table 50 “GMII 1000BASE-T Receive Signal Parameters” (changed Min values for t1 and
t2.
Replaced old MDIO Timing diagram and table with Figure 43 “MDIO Write Timing Diagram”, Figure
44 “MDIO Read Timing Diagram”, and Table 52 “MDIO Timing Parameters”.
16
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Contents
Revision Number: 007
Revision Date: March 24, 2004
(Sheet 4 of 5)
Page # Description
Broke up the old Register Map into Table 59 “MAC Control Registers ($ Port Index + Offset)”,
Table 60 “MAC RX Statistics Registers ($ Port Index + Offset)”, Table 61 “MAC TX Statistics
Registers ($ Port Index + Offset)”, Table 62 “PHY Autoscan Registers ($ Port Index + Offset)”,
Table 63 “Global Status and Configuration Registers ($ 0x500 - 0X50C)”, Table 64 “RX FIFO
Registers ($ 0x580 - 0x5BF)”, Table 65 “TX FIFO Registers ($ 0x600 - 0x63E)”, Table 66 “MDIO
Registers ($ 0x680 - 0x683)”, Table 67 “SPI3 Registers ($ 0x700 - 0x716)”, Table 68 “SerDes
Registers ($ 0x780 - 0x798)”, and Table 69 “Optical Module Registers ($ 0x799 - 0x79F)”.
156
159
159
160
161
161
162
162
Edited Table 63 “Global Status and Configuration Registers ($ 0x500 - 0X50C)” [no offset].
Edited Table 64 “RX FIFO Registers ($ 0x580 - 0x5BF)” [no offset].
Edited Table 65 “TX FIFO Registers ($ 0x600 - 0x63E)” [no offset].
Edited Table 66 “MDIO Registers ($ 0x680 - 0x683)” [no offset].
Edited Table 67 “SPI3 Registers ($ 0x700 - 0x716)” [no offset].
Edited Table 68 “SerDes Registers ($ 0x780 - 0x798)” [no offset].
Edited Table 69 “Optical Module Registers ($ 0x799 - 0x79F)” [no offset].
Modified Table 71 “Desired Duplex ($ Port_Index + 0x02)” [changed 100 Mbps to 1000 Mbps in
register description.
163
Modified Table 82 “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)” [Added text to register
description.]
167
168
169
Modified Table 84 “FC Enable ($ Port_Index + 0x12)” [changed description for bits 1:0].
Modified Table 88 “RX Config Word ($ Port_Index + 0x16)” [edited Register Description text;
changed description and type for bits 13:12].
Modified Table 89 “TX Config Word ($ Port_Index + 0x17)” [edited description and type for bits 14,
13:12.
170
171
172
174
178
Modified Table 90 “Diverse Config Write ($ Port_Index + 0x18)” [edited description and type for bits
18:8; changed bits 3:1 to Reserved; added table note 2].
Renamed/modified Table 91 “RX Packet Filter Control ($ Port_Index + 0x19)” [old register name -
added RX to heading; added table note 2].
Modified Table 93 “MAC RX Statistics ($ Port_Index + 0x20 – + 0x39)” [added note to
RxPauseMacControlReceivedCounter description; edited note 3 and added note 4].
Modified Table 94 “MAC TX Statistics ($ Port_Index +0x40 – +0x58)” [changed “1526-max” to “1523
- max frame size” for Txpkts1519toMaxOctets description].
Modified Table 113 “RX FIFO High Watermark Port 0 ($0x580)”, Table 114 “RX FIFO High
Watermark Port 1 ($0x581)”, Table 115 “RX FIFO High Watermark Port 2 ($0x582)”, and Table 116
“RX FIFO High Watermark Port 3 ($0x583)” [changed bits 11:0 description].
193
195
Renamed and modified Table 121 “RX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x594 –
0x597)”
[old register name: RX FIFO Number of Frames Removed Ports 0 to 3; renamed bit names to
match register names; removed “This register gets updated after one cycle of sw reset is applied”
under Description].
Modified Table 123 “RX FIFO Errored Frame Drop Enable ($0x59F)” [renamed bit names to match
register name].
196
198
Renamed/modified Table 125 “RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5)”
on page 198 [older register name: RX FIFO Dropped Packet Counter for Ports 0 to 3; renamed bit
names to match register name].
Modified Table 126 “RX FIFO SPI3 Loopback Enable for Ports 0 - 3 ($0x5B2)” [renamed heading
and bit name; changed description and type for bits 7:0].
199
201
Renamed Table 128 “RX FIFO Transfer Threshold Port 0 ($0x5B8)” on page 201 [from “RX FIFO
Jumbo Packet Size; changed bit names and edited/added text under description].
Datasheet
17
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Contents
Revision Number: 007
Revision Date: March 24, 2004
(Sheet 5 of 5)
Page # Description
Modified Table 136 “Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F)”
[renamed heading and bit name].
207
208
Modified Table 138 “TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)”
[renamed from TX FIFO Number of Frames Removed Ports 3 - 0].
Modified Table 139 “TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629)” [renamed
from TX FIFO Number of Dropped Packets Ports 0-3 and text under the description].
209
210
211
212
213
Modified Table 141 “TX FIFO Port Drop Enable ($0x63D)” [changed description for bits 3:0].
Modified Table 142 “MDIO Single Command ($0x680)” [changed default; changed description and
default for bits 9:8; changed default for bits 4:0].
Modified Table 144 “Autoscan PHY Address Enable ($0x682)” [added note to register description].
Modified Table 146 “SPI3 Transmit and Global Configuration ($0x700)” [broke out bits 19:16, 7:4,
and 3:0 and changed description text].
Modified Table 147 “SPI3 Receive Configuration ($0x701)” [broke out bits and modified all text
adding SPHY and MPHY modes].
215
221
Modified Table 152 “Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)” [deleted
second paragraph of the Register Description; renamed bits to match caption; changed text under
Description].
222
222
222
NA
Added note under Section 8.4.11, “Optical Module Register Overview”.
Modified Table 153 “Optical Module Status Ports 0-3 ($0x799)” [edited register description].
Modified Table 154 “Optical Module Control Ports 0 - 3 ($0x79A)” [changed register description].
Removed/Reserved Table 190 “TX and RX AC/DC Coupling Selection ($7x780)”.
Deleted old Figure 19, “Typical GBIC Module Functional Diagram” under Section 5.7, “Optical
Module Interface”.
NA
NA
Removed old Section 5.1.1.5, “Pause Command Frames.”
Removed old Table 13. TX FIFO Mini Frame Size for MAC and Padding Enable Port 0 to 3 Register
(Addr: 0x63E) and replaced with Reserved.
180(old)
Revision Number: 006
Revision Date: August 21, 2003
(Sheet 1 of 2)
Page #
Description
19
53
Modified Table 1 “Intel® IXF1104 Signal Descriptions”
Modified Section 5.1.1.1, “Padding of Undersized Frames on Transmit”.
Modified text for etherStatsCollision in Table 9 “RMON Additional Statistics”.
Modified Table 17 “Intel® IXF1104-to-Optical Module Interface Connections”
Modified first paragraph under Section 5.3.1.2, “Clock Rates”.
Modified Section 5.8.2.1, “High-Speed Serial Interface”.
60
87
65
87
100
110
113
119
125
Modified Figure 27 “Microprocessor — External and Internal Connections”.
Changed PECL to LVDS under Section 6.1, “DC Specifications”.
Modified table note 4 in Table 32 “SPI3 Receive Interface Signal Parameters”.
Modified Table 37 “SerDes Timing Parameters”.
Modified Table 40 “Microprocessor Interface Write Cycle AC Signal Parameters”.
18
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Contents
Revision Number: 006
Revision Date: August 21, 2003
(Sheet 2 of 2)
Page #
Description
Modified Table 53 “IPG Receive and Transmit Time Register (Addr: Port_Index + 0x0A – +
0x0C)”.
140
143
143
143
145
148
163
164
169
170
171
172
172
172
172
Modified Table 60 “Short Runts Threshold Register (Addr: Port_Index + 0x14)”.
Modified Table 61 “Discard Unknown Control Frame Register (Addr: Port_Index + 0x15)”.
Modified Table 62 “RX Config Word Register Bit Definition (Addr: Port_Index + 0x16)”.
Modified Table 64 “DiverseConfigWrite Register (Addr: Port_Index + 0x18)”.
Modified Table 67 “RX Statistics Registers (Addr: Port_Index + 0x20 – + 0x39)”.
Modified Table 82 “Microprocessor Interface Register (Addr: 0x508)”.
Modified Table 84 “LED Flash Rate Register (Addr: 0x50A)”.
Modified Table 93 “RX FIFO Errored Frame Drop Enable Register (Addr: 0x59F)”.
Modified Table 96 “RX FIFO Loopback Enable for Ports 0 - 3 Register (Addr: 0x5B2)”.
Added Table 98 “RX FIFO Jumbo Packet Size 0-3 Register (Addr: 0x5B8 – 0x5BB”.
Added Table 99 “RX FIFO Jumbo Packet Size Port 0 Register Bit Definitions (Addr: 0x5B8)”.
Added Table 100 “RX FIFO Jumbo Packet Size Port 1 Register Bit Definitions (Addr: 0x5B9)”.
Added Table 101 “RX FIFO Jumbo Packet Size Port 2 Register Bit Definitions (Addr: 0x5BA)”.
Added Table 102 “RX FIFO Jumbo Packet Size Port 3 Register Bit Definitions (Addr: 0x5BB)”.
Modified Table 110 “TX FIFO Number of Dropped Packets Register Ports 0-3 (Addr: 0x625 –
0x629)”.
178
177
177
177
Modified Table 108 “TX FIFO Port Reset Register (Addr: 0x620)”.
Modified Table 108 “TX FIFO Port Reset Register (Addr: 0x620)”.
Modified Table 107 “Loop RX Data to TX FIFO Register Ports 0 - 3 (Addr: 0x61F)”.
Added Table 111 “TX FIFO Occupancy Counter for Ports 0 - 3 Registers (Addr: 0x62D –
0x630)”.
179
180
181
186
194
Added Table 112 “TX FIFO Port Drop Enable Register (Addr: 0x63D)”.
Modified Table 114 “MDI Single Command Register (Addr: 0x680)”.
Added Table 122 “Tx and Rx Power-Down Register (Addr: 0x787)”.
Replaced Figure 53 “Intel® IXF1104 Example Package Marking”.
Revision 005
Revision Date: April 30, 2003
Page #
Description
Initial external release.
Revisions 001 through 004
Revision Date: April 2001 – December 2002
Page #
Description
Internal releases.
Datasheet
19
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
1.0
Introduction
This document contains information on the IXF1104 MAC, a four-port Gigabit Media Access
Controller that supports IEEE 802.3 10/100/1000 Mbps applications.
1.1
What You Will Find in This Document
This document contains the following sections:
architecture.
methodology and signal descriptions.
IXF1104 ball grid diagram with two ball list tables (by signal name and ball location)
operation of the IXF1104 including general features, and interface types and descriptions.
operating parameters, electrical specifications, and timing parameters.
descriptions, default values for the register set, and detailed information on each register.
1.2
Related Documents
Document
Number
Document
Intel® IXF1104 Media Access Controller Design and Layout Guide
Intel® IXF1104 Media Access Controller Thermal Design Considerations
Intel® IXF1104 Media Access Controller Development Kit Manual
Intel® IXF1104 Media Access Controller Specification Update
278696
278751
278785
278756
Datasheet
20
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
2.0
General Description
The IXF1104 MAC provides up to a 4.0 Gbps interface to four individual 10/100/1000 Mbps full-
duplex or 10/100 Mbps half-duplex-capable Ethernet Media Access Controllers (MACs). The
network processor is supported through a System Packet Interface Phase 3 (SPI3) media interface.
The following PHY interfaces are selected on a per-port basis:
• Serializer/Deserializer (SerDes) with Optical Module Interface support
• Gigabit Media Independent Interface (GMII)
• Reduced Gigabit Media Independent Interface (RGMII).
Figure 1 illustrates the IXF1104 MAC block diagram.
Figure 1. Block Diagram
CPU
uP IF
PHY 1 Device
PHY 2 Device
PHY 3 Device
PHY 4 Device
Intel®
IXF1104 MAC
SPI3
MDIO
B3175-01
21
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Figure 2 illustrates the IXF1104 MAC internal architecture.
Figure 2. Internal Architecture
CPU Interface
RMON Statistics
RGMII/GMII Interface
10/100/1000 MAC
10/100/1000 MAC
10/100/1000 MAC
10/100/1000 MAC
PMA Layer
SerDes
Packet
Buffer
TX
RX
RGMII/GMII Interface
Packet
Buffer
TX
PMA Layer
SerDes
RX
TX
RX
TX
Packet
Buffer
SPI3 Interface
RGMII/GMII Interface
Packet
Buffer
PMA Layer
SerDes
RX
RGMII/GMII Interface
Clock Control Block
Clock Register Block
MDIO
PMA Layer
SerDes
OMI
PLLs
B3176-01
Datasheet
22
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
3.0
Ball Assignments and Ball List Tables
3.1
Ball Assignments
“Ball List in Alphanumeric Order by Ball Location” on page 30 for the IXF1104 MAC ball
assignments.
Figure 3. 552-Ball CBGA Assignments (Top View)
AD AC AB AA
Y
W
W1
W2
V
V1
V2
U
U1
U2
T
R
R1
R2
P
N
N1
N2
M
M1
M2
L
K
K1
K2
J
H
H1
H2
G
G1
G2
F
E
E1
E2
D
D1
D2
C
C1
C2
B
A
A1
AC1 AB1 AA1 Y1
T1
P1
L1
J1
F1
B1
AD1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
AD2
AB2 AA2 Y2
T2
P2
L2
J2
F2
B2
A2
AC2
AD3 AC3 AB3 AA3 Y3
AD4 AC4 AB4 AA4 Y4
AD5 AC5 AB5 AA4 Y5
W3
W4
W5
W6
V3
V4
V5
V6
U3
U4
U5
U6
T3
T4
T5
T6
R3
R4
R5
R6
P13 N3
M3
M4
M5
M6
L3
L4
L5
L6
K3
K4
K5
K6
J3
J4
J5
J6
H3
H4
H5
H6
G3
G4
G5
G6
F3
F4
F5
F6
E3
E4
E5
F6
D3
D4
D5
D6
C3
C4
C5
C6
B3
B4
B5
B6
A3
A4
A5
A6
P4
P5
P6
N4
N5
N6
AD6 AC6 AB6 AA6
Y6
AD7 AC7 AB7 AA7 Y7
W7
V7
U7
T7
R7
P7
N7
M7
L7
K7
J7
H7
H8
H9
G7
G8
G9
F7
F8
F9
E7
E8
E9
D7
D8
D9
G7
C8
C9
B7
B28
B9
A7
A8
A9
AD8 AC8 AB8 AA8 Y8
AD9 AC9 AB9 AA9 Y9
W8
W9
V8
V9
U8
U9
T8
T9
R8
R9
P8
P9
N8
N9
M8
M9
L8
L9
K8
K9
J8
J9
9
10
11
12
13
14
15
9
AD10 AC10 AB10 AA10 Y10 W10 V10 U10 T10 R10 P10 N10 M10 L10 K10 J10 H10 G10 F10 E10 D10 C10 B10 A10
AD11 AC11 AB11 AA11 Y11 W11 V11 U11 T11 R11 P11 N11 M11 L11 K11 J11 H11 G11 F11 E11 D11 C11 B11 A11
10
11
12
13
14
15
AD12 AC12 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 K12 J12 H12 G12 F12 E12 D12 C12 B12 A12
AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 P13 N13 M13 L13 K13 J13 H13 G13 F13 E13 D13 C13 B13 A13
AD14 AC14 AB14 AA14 Y14 W14 V14 U14 T14 R14 P14 N14 M14 L14 K14 J14 H14 G14 F14 E14 D14 C14 B14 A14
AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15 P15 N15 M15 L15 K15 J15 H15 G15 F15 E15 D15 C15 B15 A15
16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 P16 N16 M16 L16 K16 J16 H16 G16 F16 E16 D16 C16 B16 A16 16
AD17 AC17 AB17 AA17 Y17 W17
V17 U17 T17 R17 P17 N17 M17 L17 K17 J17 H17 G17 F17 E17 D17 C17 B17 A17
17
17
AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18 R18 P18 N18 M18 L18 K18 J18 H18 G18 F18 E18 D18 C18 B18 A18
AD19 AC19 AB19 AA19 Y19 W19 V19 U19 T19 R19 P19 N19 M19 L19 K19 J19 H19 G19 F19 E19 D19 C19 B19 A19
18
19
20
21
22
23
24
18
19
20
21
22
23
24
AD20 AC20 AB20 AA20 Y20 W20 V20 U20 T20 R20 P20 N20 M20 L20 K20 J20 H20 G20 F20 E20 D20 C20 B20 A20
AD21 AC21 AB21 AA21 Y21 W21 V21 U21 T21 R21 P21 N121 M21 L21 K21 J21 H21 G21 F21 E21 D21 C21 B21 A21
AD22 AC22 AB22 AA22
W22 V22 U22 T22 R22 P22 N22 M22 L22 K22 J22 H22 G22 F22 E22 D22 C22 B22 A22
Y22
AD23 AC23 AB23 AA23 Y23 W23 V23 U23 T23 R23 P23 N23 M23 L23 K23 J23 H23 G23 F23 E23 D23 C23 B23 A23
AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 P24 N24 M24 L24 K24 J24 H24 G24 F24 E24 D24 C24 B24 A24
AD AC AB AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
= No Pad (A1)
= No Ball (A2, A3, A22, A23, A24, B1, B2, B23, B24, C1, C24, AB1, AB24, AC1, AC2, AC23, AC24, AD1, AD2, AD3,
AD22, AD23, AD24)
B1458-01
23
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
3.2
Ball List Tables
3.2.1
Balls Listed in Alphabetic Order by Signal Name
1. GMII Ball Connection:
2. SPI3 Ball Connection:
3. Fiber Mode Ball Connection:
Table 1. Ball List in Alphanumeric Order by Signal Name
Ball
Location
Ball
Location
Ball
Location
Signal Name
Signal Name
Signal Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D4
D8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
K14
K16
K19
K23
L10
L12
L13
L15
M4
AVDD1P8_1
AVDD1P8_1
AVDD1P8_2
AVDD1P8_2
AVDD2P5_1
AVDD2P5_2
AVDD2P5_2
CLK125
A5
A20
T23
D12
D13
D17
D21
F2
AB16
AD20
R18
U14
AD19
AB6
AB10
AD15
AB17
AA5
AA9
AB15
AC16
D3
F6
COL_01
F10
F15
F19
F23
H4
COL_11
M8
COL_21
M11
M14
M17
M21
N4
COL_31
CRS_01
CRS_11
H8
CRS_21
H12
H13
H17
H21
J10
J15
K2
CRS_31
N8
DTPA_02
DTPA_12
DTPA_22
DTPA_32
GND
N11
N14
N17
N21
P10
P12
P13
P15
L1
A9
J7
B6
K6
GND
B10
B15
B19
K9
GND
K11
GND
24
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Ball
Location
Ball
Location
Ball
Location
Signal Name
Signal Name
Signal Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R2
R6
GND
A21
AD21
L23
L24
M24
N24
P24
K24
M22
L22
W24
V21
N22
D24
E12
F11
G15
H7
NC
NC
P18
R5
GND
R9
I2C_CLK
NC
R10
R12
R13
R15
R20
T6
R11
R14
R16
R19
R23
T10
T15
U4
I2C_DATA_03
NC
I2C_DATA_13
NC
I2C_DATA_23
NC
I2C_DATA_33
NC
LED_CLK
NC
LED_DATA
NC
T7
LED_LATCH
NC
T8
MDC4
NC
T9
U8
MDIO4
NC
T21
T22
U5
U12
U13
U17
U21
W2
MOD_DEF_INT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
U7
NC
U9
NC
U11
U18
V9
W6
NC
W10
W15
W19
W23
AA4
AA8
AA12
AA13
AA17
AA21
AC6
AC10
AC15
AC19
AC14
L20
H18
J21
K7
NC
NC
V10
V11
V13
AB18
AD4
AD5
A2
NC
K18
K20
K22
L18
L19
L21
M7
NC
NC
NC
NC
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
A3
A22
A23
A24
B1
M18
M20
N3
N18
P2
B2
B23
B24
C1
P4
L5
P6
R7
P7
C24
AB1
AB24
AB12
A4
P8
P17
Datasheet
25
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Ball
Location
Ball
Location
Ball
Location
Signal Name
Signal Name
Signal Name
No Ball
No Ball
AC1
AC2
AC23
AC24
AD1
AD2
AD3
AD22
AD23
AD24
A1
RDAT_262
RDAT_272
RDAT_282
RDAT_292
RDAT_302
RDAT_312
RENB_02
RENB_12
RENB_22
RENB_32
REOP_02
REOP_12
REOP_22
REOP_32
RERR_02
RERR_12
RERR_22
RERR_32
RFCLK2
G20
G21
G22
G23
G24
F24
A13
A18
C19
E24
C16
D18
C23
J19
RX_ER_01
RX_ER_11
RX_ER_21
RX_ER_31
RX_LOS_INT3
RX_N_03
RX_N_13
RX_N_23
RX_N_33
RX_P_03
RX_P_13
RX_P_23
RX_P_33
RXC_01
W5
Y12
AA22
U20
P19
R22
U22
R24
V24
P22
V22
T24
U24
V4
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Ball
No Pad
PTPA2
B11
RDAT_02
RDAT_12
RDAT_22
RDAT_32
RDAT_42
RDAT_52
RDAT_62
RDAT_72
RDAT_82
RDAT_92
RDAT_102
RDAT_112
RDAT_122
RDAT_132
RDAT_142
RDAT_152
RDAT_162
RDAT_172
RDAT_182
RDAT_192
RDAT_202
RDAT_212
RDAT_222
RDAT_232
RDAT_242
RDAT_252
A15
A14
B14
C14
C13
D14
E14
F14
A16
G17
D20
H20
A19
G14
G13
E15
G16
E20
F20
B16
C18
E23
J18
RXC_11
AD11
AA24
V23
V8
RXC_21
RXC_31
RXD0_01
RXD0_11
RXD0_21
RXD0_31
RXD1_01
RXD1_11
RXD1_21
RXD1_31
RXD2_01
RXD2_11
RXD2_21
RXD2_31
RXD3_01
RXD3_11
RXD3_21
RXD3_31
RXD4_01
RXD4_11
RXD4_21
RXD4_31
RXD5_01
Y9
RMOD02
RMOD12
RPRTY_02
RPRTY_12
RPRTY_22
RPRTY_32
RSOP_02
RSOP_12
RSOP_22
RSOP_32
RSX2
Y20
Y17
V7
A17
C17
D16
E16
F16
Y11
Y21
Y18
W7
E17
E18
F18
W11
Y22
Y19
Y7
B20
B22
C20
C21
C22
D22
E22
E21
G18
G19
E13
C15
B18
E19
F22
V5
RVAL_02
RVAL_12
RVAL_22
RVAL_32
RX_DV_01
RX_DV_11
RX_DV_21
RX_DV_31
W9
Y23
W18
Y6
AD10
W22
T16
Y5
AB11
Y24
V18
26
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Ball
Location
Ball
Location
Ball
Location
Signal Name
Signal Name
Signal Name
RXD5_11
RXD5_21
RXD5_31
RXD6_01
RXD6_11
RXD6_21
RXD6_31
RXD7_01
RXD7_11
RXD7_21
RXD7_31
STPA2
AC11
V20
T17
AB5
AA11
V19
T18
AC5
Y10
W20
T19
C11
AD12
A11
A12
J22
B3
TDAT222
TDAT232
TDAT242
TDAT252
TDAT262
TDAT272
TDAT282
TDAT292
TDAT302
TDAT312
TDI
F9
C8
G4
G5
G6
G7
G8
G9
F5
TX_EN_01
TX_EN_11
TX_EN_21
TX_EN_31
TX_ER_01
TX_ER_11
TX_ER_21
TX_ER_31
TX_FAULT_INT3
TX_N_03
TX_N_13
TX_N_23
TX_N_33
TX_P_03
TX_P_13
TX_P_23
TX_P_33
TXC_01
AB2
Y8
AC22
V12
W1
AD6
AD17
AB13
P23
F7
Y14
J24
H24
B7
E2
C9
J4
AD14
Y16
TDO
SYS_RST_L
TADR02
TADR12
TCLK
TENB_02
TENB_12
TENB_22
TENB_32
TEOP_02
TEOP_12
TEOP_22
TEOP_32
TERR_02
TERR_12
TERR_22
TERR_32
TFCLK2
AD18
Y13
AD13
W16
AC18
AA1
AD7
AC20
AB14
Y1
TDAT02
A7
F3
TDAT12
C2
TDAT22
C3
E4
H5
A8
K1
E11
J8
TXC_11
TDAT32
D1
TXC_21
TDAT42
C4
TXC_31
TDAT52
C5
TXD0_01
TXD0_11
TXD0_21
TXD0_31
TXD1_01
TXD1_11
TXD1_21
TXD1_31
TXD2_01
TXD2_11
TXD2_21
TXD2_31
TXD3_01
TXD3_11
TXD3_21
TXD3_31
TXD4_01
TDAT62
B5
AC7
AB20
V14
TDAT72
C6
TDAT82
F1
D7
A6
D9
H22
D5
G3
B9
J6
TDAT92
G1
TMOD02
TMOD12
TMS
Y2
TDAT102
TDAT112
TDAT122
TDAT132
TDAT142
TDAT152
TDAT162
TDAT172
TDAT182
TDAT192
TDAT202
TDAT212
G2
AB7
AB21
V15
H1
J1
TPRTY_02
TPRTY_12
TPRTY_22
TPRTY_32
TRST_L
TSOP_02
TSOP_12
TSOP_22
TSOP_32
TSX
J2
Y3
J3
AB9
AB22
V16
H3
E5
J23
C7
E3
C10
J5
E6
AA3
AD9
AB23
V17
E7
E8
E9
E10
E1
AB3
Datasheet
27
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Ball
Location
Ball
Location
Ball
Location
Signal Name
Signal Name
Signal Name
TXD4_11
TXD4_21
AA7
AD16
AA14
AC3
AB8
AB19
Y15
AB4
AD8
AA20
AA16
Y4
UPX_DATA5
UPX_DATA6
UPX_DATA7
UPX_DATA8
UPX_DATA9
UPX_DATA10
UPX_DATA11
UPX_DATA12
UPX_DATA13
UPX_DATA14
UPX_DATA15
UPX_DATA16
UPX_DATA17
UPX_DATA18
UPX_DATA19
UPX_DATA20
UPX_DATA21
UPX_DATA22
UPX_DATA23
UPX_DATA24
UPX_DATA25
UPX_DATA26
UPX_DATA27
UPX_DATA28
UPX_DATA29
UPX_DATA30
UPX_DATA31
UPX_RD_L
UPX_RDY_L
UPX_WIDTH0
UPX_WIDTH1
UPX_WR_L
VDD
N5
M5
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD2
VDD2
VDD2
VDD2
H10
H15
J11
J14
K4
TXD4_31
K5
TXD5_01
P5
TXD5_11
L6
TXD5_21
L7
K8
TXD5_31
N7
K17
K21
L9
TXD6_01
L8
TXD6_11
H9
TXD6_21
J9
L11
L14
L16
P9
TXD6_31
N10
M10
K10
G10
H11
G11
K12
G12
K13
H14
K15
N15
M15
J16
H16
J17
L17
V6
TXD7_01
TXD7_11
AC9
AA18
W14
N20
P20
P21
T20
P3
TXD7_21
P11
P14
P16
R4
TXD7_31
TXPAUSE_ADD0
TXPAUSE_ADD1
TXPAUSE_ADD2
TXPAUSEFR
UPX_ADD0
UPX_ADD1
UPX_ADD2
UPX_ADD3
UPX_ADD4
UPX_ADD5
UPX_ADD6
UPX_ADD7
UPX_ADD8
UPX_ADD9
UPX_ADD10
UPX_BADD0
UPX_BADD1
UPX_CS_L
UPX_DATA0
UPX_DATA1
UPX_DATA2
UPX_DATA3
UPX_DATA4
R8
R17
R21
T11
T14
U10
U15
W4
N1
P1
R1
T1
U1
V1
W21
AA6
AA10
AA15
AA19
C12
D11
J20
A10
B4
V2
V3
U3
M1
T3
U16
T5
T2
W3
R3
T4
D6
L2
VDD
D10
D15
D19
F4
K3
VDD
L3
VDD
B8
M3
VDD
B12
D2
L4
VDD
F21
28
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Ball
Location
Ball
Location
Signal Name
Signal Name
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD4
VDD4
VDD4
VDD4
VDD4
VDD4
VDD4
VDD4
VDD4
VDD4
VDD4
VDD4
VDD4
VDD5
VDD5
VDD5
F8
F12
H2
VDD5
VDD5
VDD5
VDD5
VDD5
VDD5
VDD5
VDD5
VDD5
VDD5
N12
T12
U2
H6
U6
J12
W8
M2
W12
AA2
AC4
AC8
AC12
M6
M9
M12
B13
B17
B21
D23
F13
F17
H19
H23
J13
M13
M16
M19
M23
N13
N16
N19
N23
T13
U19
U23
W13
W17
AA23
AC13
AC17
AC21
N2
N6
N9
Datasheet
29
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
3.2.2
Balls Listed in Alphabetic Order by Ball Location
Table 2. Ball List in Alphanumeric Order by Ball Location
Ball
Location
Ball
Location
Ball
Location
Signal Name
Signal Name
Signal Name
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
C1
GND
PTPA2
C20
C21
C22
C23
C24
D1
RDAT_182
RDAT_192
RDAT_202
REOP_22
No Ball
TDAT32
VDD2
A1
A2
No Pad
No Ball
VDD2
A3
No Ball
VDD3
A4
GND
RDAT_22
GND
A5
AVDD1P8_1
TMOD02
TEOP_02
TERR_02
DTPA_22
VDD
A6
RSOP_02
VDD3
D2
A7
D3
DTPA_02
A8
RVAL_12
GND
D4
GND
A9
D5
TPRTY_02
VDD
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
B1
RDAT_162
VDD3
D6
TADR02
TADR12
RENB_02
RDAT_12
RDAT_02
RERR_02
RDAT_82
RENB_12
RFCLK2
AVDD1P8_1
GND
D7
TFCLK2
RDAT_172
No Ball
D8
GND
D9
TMOD12
VDD
No Ball
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
E1
No Ball
VDD
C2
TDAT12
TDAT22
TDAT42
TDAT52
TDAT72
TSOP_02
TDAT232
TENB_22
TSOP_22
STPA2
GND
C3
GND
C4
RDAT_52
VDD
C5
C6
RDAT_102
GND
C7
No Ball
C8
REOP_12
VDD
No Ball
C9
No Ball
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
RERR_22
GND
No Ball
B2
No Ball
RDAT_212
VDD3
B3
TDAT02
VDD
RDAT_42
RDAT_32
RVAL_02
REOP_02
RDAT_92
RSOP_12
RENB_22
B4
VDD2
B5
TDAT62
GND
NC
TSX
B6
TENB_12
TSOP_12
TEOP_22
TDAT162
B7
TENB_02
E2
E3
B8
VDD2
B9
TPRTY_22
E4
E5
30
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Ball
Location
Ball
Location
Ball
Location
Signal Name
Signal Name
Signal Name
E6
E7
TDAT172
TDAT182
TDAT192
TDAT202
TDAT212
TERR_22
NC
F20
F21
F22
F23
F24
G1
RPRTY_32
VDD
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
J1
VDD
UPX_DATA19
GND
E8
RVAL_32
GND
E9
GND
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
F1
RDAT_312
TDAT92
UPX_DATA24
VDD
G2
TDAT102
TPRTY_12
TDAT242
TDAT252
TDAT262
TDAT272
TDAT282
TDAT292
UPX_DATA18
UPX_DATA20
UPX_DATA22
RMOD12
RMOD02
NC
UPX_DATA29
GND
RSX2
G3
RDAT_62
RPRTY_02
RDAT_112
RDAT_132
RDAT_142
RVAL_22
RPRTY_22
RDAT_232
RDAT_222
RSOP_22
RENB_32
TDAT82
GND
G4
NC
G5
VDD3
G6
RERR_32
GND
G7
G8
TMS
G9
VDD3
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
H1
TDO
TDAT122
TDAT132
TDAT142
TENB_32
TSOP_32
TPRTY_32
DTPA_32
TERR_32
UPX_DATA14
GND
J2
J3
J4
J5
F2
RPRTY_12
RERR_12
RDAT_242
RDAT_252
RDAT_262
RDAT_272
RDAT_282
RDAT_292
RDAT_302
TDAT112
VDD2
J6
F3
TEOP_12
J7
F4
VDD
J8
F5
TDAT302
GND
J9
F6
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
F7
TDAT312
VDD
F8
VDD2
VDD2
F9
TDAT222
GND
VDD3
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
VDD
NC
GND
VDD2
H2
UPX_DATA28
UPX_DATA30
RSOP_32
REOP_32
VDD
VDD3
H3
TDAT152
RDAT_72
GND
H4
GND
H5
TEOP_32
VDD2
RDAT_122
VDD3
H6
H7
NC
NC
RDAT_152
GND
H8
GND
TCLK
H9
UPX_DATA13
TRST_L
Datasheet
31
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Ball
Location
Ball
Location
Ball
Location
Signal Name
Signal Name
Signal Name
J24
K1
TDI
TERR_12
GND
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
M1
VDD
GND
N4
N5
GND
UPX_DATA5
VDD5
K2
VDD
N6
K3
UPX_DATA1
VDD
UPX_DATA31
NC
N7
UPX_DATA11
GND
K4
N8
K5
UPX_DATA7
GND
NC
N9
VDD5
K6
GND
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
P1
UPX_DATA15
GND
K7
NC
NC
K8
VDD
LED_LATCH
I2C_CLK
I2C_DATA_03
UPX_RDY_L
VDD2
VDD5
K9
GND
VDD4
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
L1
UPX_DATA17
GND
GND
UPX_DATA26
VDD4
UPX_DATA21
UPX_DATA23
GND
M2
M3
UPX_DATA3
GND
GND
M4
NC
UPX_DATA25
GND
M5
UPX_DATA6
VDD2
VDD4
M6
TXPAUSE_ADD0
GND
VDD
M7
NC
NC
M8
GND
MOD_DEF_INT
VDD4
GND
M9
VDD2
NC
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
N1
UPX_DATA16
GND
I2C_DATA_23
UPX_ADD2
NC
VDD
NC
VDD2
P2
GND
VDD3
P3
UPX_ADD0
NC
LED_CLK
DTPA_12
UPX_DATA0
UPX_DATA2
UPX_DATA4
GND
GND
P4
UPX_DATA27
VDD3
P5
UPX_DATA8
NC
L2
P6
L3
GND
P7
NC
L4
NC
P8
NC
L5
VDD3
P9
VDD
L6
UPX_DATA9
UPX_DATA10
UPX_DATA12
VDD
NC
P10
P11
P12
P13
P14
P15
P16
P17
GND
L7
GND
VDD
L8
LED_DATA
VDD3
GND
L9
GND
L10
L11
L12
L13
GND
I2C_DATA_13
UPX_ADD1
VDD5
VDD
VDD
GND
GND
N2
VDD
GND
N3
NC
NC
32
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Ball
Location
Ball
Location
Ball
Location
Signal Name
Signal Name
Signal Name
P18
P19
P20
P21
P22
P23
P24
R1
NC
RX_LOS_INT3
TXPAUSE_ADD1
TXPAUSE_ADD2
RX_P_03
TX_FAULT_INT3
I2C_DATA_33
UPX_ADD3
GND
T8
T9
NC
NC
U22
U23
U24
V1
RX_N_13
VDD4
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
U1
GND
RX_P_33
UPX_ADD6
UPX_ADD7
UPX_ADD8
RXC_01
RX_DV_01
UPX_RD_L
RXD1_01
RXD0_01
NC
VDD
VDD5
V2
VDD4
V3
VDD
V4
GND
V5
R2
RXD4_31
RXD5_31
RXD6_31
RXD7_31
TXPAUSEFR
NC
V6
R3
UPX_CS_L
VDD
V7
R4
V8
R5
NC
V9
R6
GND
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
NC
R7
GND
NC
R8
VDD
NC
TX_EN_31
NC
R9
GND
AVDD1P8_2
RX_P_23
UPX_ADD5
VDD5
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
T1
NC
TXD0_31
TXD1_31
TXD2_31
TXD3_31
RX_DV_31
RXD6_21
RXD5_21
MDIO4
GND
NC
U2
NC
U3
UPX_ADD9
GND
GND
U4
NC
U5
NC
GND
U6
VDD5
VDD
U7
NC
AVDD2P5_2
GND
U8
GND
RX_P_13
RXC_31
RX_N_33
TX_ER_01
GND
U9
NC
NC
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
VDD
VDD
NC
RX_N_03
GND
GND
GND
UPX_BADD1
RX_N_23
UPX_ADD4
UPX_BADD0
UPX_ADD10
UPX_WR_L
UPX_WIDTH1
NC
AVDD2P5_2
VDD
VDD
RX_ER_01
GND
T2
UPX_WIDTH0
GND
T3
RXD2_01
T4
NC
VDD5
T5
VDD4
RXD3_11
GND
T6
RX_ER_31
GND
T7
NC
RXD2_11
Datasheet
33
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Ball
Location
Ball
Location
Ball
Location
Signal Name
Signal Name
Signal Name
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
Y1
VDD5
VDD4
AA2
AA3
VDD5
TXD3_01
GND
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AC1
AVDD1P8_2
COL_31
NC
TXD7_31
GND
AA4
AA5
CRS_01
TXD5_21
TXD0_21
TXD1_21
TXD2_21
TXD3_21
No Ball
No Ball
No Ball
TXD5_01
VDD5
TX_P_23
VDD4
AA6
VDD
AA7
TXD4_11
GND
RXD3_31
GND
AA8
AA9
CRS_11
RXD7_21
VDD
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AB1
VDD
RXD6_11
GND
RXD4_21
GND
AC2
GND
AC3
MDC4
TXD4_31
VDD
AC4
TXD0_01
TXD1_01
TXD2_01
TXD7_01
RXD5_01
RXD4_01
RXD3_01
TX_EN_11
RXD0_11
RXD7_11
RXD1_11
RX_ER_11
TX_P_03
TX_N_03
TXD5_31
TX_N_23
RXD0_31
RXD1_31
RXD2_31
RXD0_21
RXD1_21
RXD2_21
RXD3_21
RX_DV_21
TXC_01
AC5
RXD7_01
Y2
TXD6_31
GND
AC6
GND
Y3
AC7
TXD0_11
VDD5
Y4
TXD7_21
VDD
AC8
Y5
AC9
TXD7_11
Y6
TXD6_21
GND
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AD1
GND
Y7
RXD5_11
VDD5
Y8
RX_ER_21
VDD4
Y9
VDD4
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
AA1
RXC_21
No Ball
TX_EN_01
TXD4_01
TXD6_01
RXD6_01
COL_01
TXD1_11
TXD5_11
TXD2_11
COL_11
RX_DV_11
GND
GND
GND
AB2
CRS_31
VDD4
AB3
AB4
TX_P_33
GND
AB5
AB6
TXC_21
VDD4
AB7
AB8
TX_EN_21
No Ball
No Ball
No Ball
No Ball
No Ball
NC
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AD2
TX_ER_31
TXC_31
CRS_21
AD3
AD4
AD5
NC
34
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Ball
Location
Signal Name
AD6
AD7
TX_ER_11
TXC_11
AD8
TXD6_11
TXD3_11
RXD4_11
RXC_11
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
SYS_RST_L
TX_P_13
TX_N_13
COL_21
TXD4_21
TX_ER_21
TX_N_33
CLK125
AVDD2P5_1
GND
No Ball
No Ball
No Ball
Datasheet
35
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
36
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
4.0
Ball Assignments and Signal Descriptions
4.1
Naming Conventions
4.1.1
Signal Name Conventions
Signal names begin with a Signal Mnemonic, and can also contain one or more of the following
designations: a differential pair designation, a serial designation, a port designation (RGMII
interface), and an active low designation. Signal naming conventions are as follows:
Differential Pair + Port Designation. The positive and negative components of differential pairs
tied to a specific port are designated by the Signal Mnemonic, immediately followed by an
underscore and either P (positive component) or N (negative component), and an underscore
followed by the port designation. For example, SerDes interface signals for port 0 are identified as
TX_P_0 and TX_N_0.
Serial Designation. A set of signals that are not tied to any specific port are designated by the
Signal Mnemonic, followed by a bracketed serial designation. For example, the set of 11 CPU
Address Bus signals is identified as UPX_ADD[10:0].
Port Designation. Individual signals that apply to a particular port are designated by the Signal
Mnemonic, immediately followed by an underscore and the Port Designation. For example,
RGMII Transmit Control signals are identified as TX_CTL_0, TX_CTL_1, TX_CTL_2, and so on.
Port Bus Designation. A set of bus signals that apply to a particular port are designated by the
Signal Mnemonic, immediately followed by a bracketed bus designation, followed by an
underscore and the port designation. For example, RGMII transmit data bus signals are identified
as TD[3:0]_0, TD[3:0]_1, TD[3:0]_2, and so on.
Active Low Designation. A control input or indicator output that is active Low is designated by a
final suffix consisting of an underscore followed by an upper case “L”. For example, the CPU cycle
complete identifier is shown as UPX_RDY_L.
4.1.2
Register Address Conventions
Registers located in on-chip memory are accessed using a register address, which is provided in
Hex notation. A Register Address is indicated by the dollar sign ($), followed by the memory
location in Hex.
37
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
4.2
Interface Signal Groups
This section describes the IXF1104 MAC signals in groups according to the associated interface or
Figure 4. Interface Signals
SPHY
MPHY
GMII
RGMII
TXC_0:3
TXC _0: 3
TDAT[7:0]_0:3
TFCLK
TDAT[ 31:0]
TFCLK
TD[3:0]_0
TD[3:0] _1
TD[3:0] _2
TD[3:0]_3
TX_C TL_0: 3
TXD[ 7:0] _0
TXD[ 7:0] _1
TENB_0: 3
TERR _0: 3
TPR TY_0: 3
TENB_0
TERR_0
TPRTY_0
TMOD[1:0]
TSX
TXD[ 7:0] _2
TXD[ 7:0] _3
TX_EN_0:3
TX_ER_0:3
TSOP_0:3
TEOP_0:3
TSOP_0
TEOP_0
RXC_0:3
R XC _0: 3
TADR[1:0]
DTPA_0: 3
TADR[1:0]
DTPA_0:3
STPA
GMII and
RXD[7:0]_3
RD[3:0]_0
RGMII
Interfaces*
SPI3
Interface
RXD[7:0]_2
RXD[7:0]_1
RXD[7:0]_0
RX_D V_0:3
RX_ER_0:3
CRS_0:3
RD[3:0]_1
RD[3:0]_2
RD[3:0]_3
R X_CTL_0:3
PTPA
RDAT[7:0]_0:3
RFCLK
PTPA
R D AT[ 31: 0]
RFCLK
RENB_0:3
RVAL_0: 3
RENB_0
RVAL_0
RERR_0
RPRTY_0
RMOD[1:0]
RSX
COL_0:3
RERR_0:3
RPRTY_0:3
* D at a and clock balls are shared for
GMII and RGMII Interfaces
RSOP_0: 3
REOP_0: 3
RSOP_0
REOP_0
Intel® IXF1104
Media Access
Controller
TMS
TDI
RX_P/N_0:3
TX_P/N_0:3
SerDes
Interface
JTAG
TDO
TCLK
Interface
TRST_L
MDIO
MDC
MDIO
Interface
TX_D ISABLE_0:3
MOD_DEF_0:3
TX_FAU LT_0:3
RX_LOS_0:3
Pause
Control
Interface
Optical
Module
Interface
Si gnals*
*
TXPAUSEADD[2:0]
TXPAUSEFR
TX_FAU LT_IN T
RX_LOS_IN T
MOD_DEF_INT
UPX_WIDTH[1:0]
UPX_D ATA[ 31:0]
UPX_ADD[10:0]
UPX_BADD[1:0]
2
I C_CLK
2
I C_DATA_0:3
** These optical module signals
are mult iplexed on the GMII balls.
CPU
Interface
UPX_WR_L
UPX_RD_L
UPX_CS_L
UPX_RDY_L
System
Interface
SYS_RES_L
CLK125
LED_CLK
LED
Interface
LED_DATA
LED_LATCH
B3181-01
Datasheet
38
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
4.3
Signal Description Tables
The I/O signals, power supplies, or ground returns associated with each IXF1104 MAC connection
Table 3. SPI3 Interface Signal Descriptions (Sheet 1 of 8)
Signal Name
Ball
Type
Standard
Description
Designator
MPHY
SPHY
TDAT31
TDAT30
TDAT29
TDAT28
TDAT27
TDAT26
TDAT25
TDAT24
TDAT7_3
TDAT6_3
TDAT5_3
TDAT4_3
TDAT3_3
TDAT2_3
TDAT1_3
TDAT0_3
F7
F5
Transmit Data Bus.
Carries payload data to the IXF1104 MAC
egress path.
G9
G8
G7
G6
G5
G4
3.3 V
LVTTL
Input
Mode
Bits
32-bit Multi-PHY
4 x 8 Single-PHY
[31:24]
[7:0] for port 3
TDAT23
TDAT22
TDAT21
TDAT20
TDAT19
TDAT18
TDAT17
TDAT16
TDAT7_2
TDAT6_2
TDAT5_2
TDAT4_2
TDAT3_2
TDAT2_2
TDAT1_2
TDAT0_2
C8
F9
Transmit Data Bus.
Carries payload data to the IXF1104 MAC
egress path.
E10
E9
E8
E7
E6
E5
3.3 V
LVTTL
Input
Input
Mode
Bits
32-bit Multi-PHY
4 x 8 Single-PHY
[23:16]
[7:0] for port 2
TDAT15
TDAT14
TDAT13
TDAT12
TDAT11
TDAT10
TDAT9
TDAT7_1
TDAT6_1
TDAT5_1
TDAT4_1
TDAT3_1
TDAT2_1
TDAT1_1
TDAT0_1
H3
J3
J2
Transmit Data Bus.
Carries payload data to the IXF1104 MAC
egress path.
J1
3.3 V
LVTTL
H1
G2
G1
F1
Mode
Bits
32-bit Multi-PHY
4 x 8 Single-PHY
[15:8]
[7:0] for port 1
TDAT8
TDAT7
TDAT6
TDAT5
TDAT4
TDAT3
TDAT2
TDAT1
TDAT0
TDAT7_0
TDAT6_0
TDAT5_0
TDAT4_0
TDAT3_0
TDAT2_0
TDAT1_0
TDAT0_0
C6
B5
C5
C4
D1
C3
C2
B3
Transmit Data Bus.
Carries payload data to the IXF1104 MAC
egress path.
3.3 V
LVTTL
Input
Input
Mode
Bits
32-bit Multi-PHY
4 x 8 Single-PHY
7:0]
[7:0] for port 0
Transmit Clock.
TFCLK is the clock associated with all
transmit signals. Data and control lines are
sampled on the rising edge of TFCLK
(frequency operation range 90 - 133 MHz).
3.3 V
LVTTL
TFCLK
TFCLK
D7
39
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 3. SPI3 Interface Signal Descriptions (Sheet 2 of 8)
Signal Name
Ball
Type
Standard
Description
Designator
MPHY
SPHY
Transmit Parity.
TPRTY indicates odd parity for the TDAT
bus. TPRTY is valid only when a channel
asserts either TENB or TSX. Odd parity is
the default configuration; however, even
TPRTY_0 TPRTY_0
TPRTY_1
D5
G3
B9
J6
3.3 V
LVTTL
Input
TPRTY_2
TPRTY_3
32-bit Multi-PHY mode: TPRTY_0 is the
parity bit covering all 32 bits.
4 x 8 Single-PHY mode: TPRTY_0:3 bits
correspond to the respective TDAT[3:0]_n
channels.
Transmit Write Enable.
TENB_0:3 asserted causes an attached
PHY to process TDAT[n], TMOD, TSOP,
TEOP and TERR signals.
TENB_0
TENB_0
TENB_1
TENB_2
TENB_3
B7
E2
C9
J4
3.3 V
LVTTL
32-bit Multi-PHY mode: TENB_0 is the
enable bit for all 32 bits.
Input
4 x 8 Single-PHY mode: TENB_0:3 bits
correspond to the respective TDAT[3:0]_n
channels and their associated control and
status signals.
Transmit Error.
TERR indicates that there is an error in the
current packet. TERR is valid when
simultaneously asserted with TEOP and
TENB.
TERR_0
TERR_0
TERR_1
TERR_2
TERR_3
A8
K1
E11
J8
3.3 V
LVTTL
Input
32-bit Multi-PHY mode: TERR_0 is the bit
asserted for all 32 bits.
4 x 8 Single-PHY mode: Each bit of
TERR_0:3 corresponds to the respective
TDAT[3:0]_n channel.
Transmit Start-of-Packet.
TSOP indicates the start of a packet and is
valid when asserted simultaneously with
TENB.
TSOP_0
TSOP_0
TSOP_1
TSOP_2
TSOP_3
C7
E3
C10
3.3 V
LVTTL
Input
32-bit Multi-PHY mode: TSOP_0 is the bit
asserted for all 32 bits.
J5
4 x 8 Single-PHY mode: Each bit of
TSOP_0:3 corresponds to the respective
TDAT[3:0]_n channel.
Transmit End-of-Packet.
TEOP indicates the end of a packet and is
valid when asserted simultaneously with
TENB.
TEOP_0
TEOP_0
TEOP_1
TEOP_2
TEOP_3
A7
F3
E4
H5
3.3 V
LVTTL
Input
32-bit Multi-PHY mode: TEOP_0 is the bit
asserted for all 32 bits.
4 x 8 Single-PHY mode: Each bit of
TEOP_0:3 corresponds to the respective
TDAT[3:0]_n channel.
Datasheet
40
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 3. SPI3 Interface Signal Descriptions (Sheet 3 of 8)
Signal Name
Ball
Type
Standard
Description
Designator
MPHY
SPHY
TMOD[1:0] Transmit Word Modulo.
32-bit Multi-PHY mode: TMOD[1:0]
indicates the valid data bytes of TDAT[31:0].
During transmission, TMOD[1:0] should
always be “00” until the last double word is
transferred on TDAT[31:0]. TMOD[1:0]
specifies the valid bytes of TDAT when
TEOP is asserted:
TMOD[1:0] – Valid Bytes of TDAT
00 =4 bytes [31:0]
TMOD1
TMOD0
D9
A6
3.3 V
LVTTL
NA
Input
01 =3 bytes [31:8]
10 =2 bytes [31:16]
11 = 1 byte [31:24]
TENB must be asserted simultaneously for
TMOD[1:0] to be valid.
4 x 8 Single-PHY mode: MOD[1:0] is not
required.
Transmit Start of Transfer.
32-bit Multi-PHY mode: TSX asserted with
TENB = 1 indicates that the PHY address is
present on TDAT[7:0]. The valid values on
TDAT[7:0] are 3, 2, 1, and 0. When
TENB = 0, TSX is not used by the PHY
device.
3.3 V
LVTTL
TSX
NA
E1
Input
Input
NOTE: Only TDAT[1:0] are relevant; all
other bits are “Don’t Care”.
4 x 8 Single-PHY mode: TSX is not used.
TADR[1:0] Transmit PHY Address.
TADR1
TADR0
TADR1
TADR0
A12
A11
3.3 V
LVTTL
The value on TADR[1:0] selects one of the
PHY ports that drives the PTPA signal after
the rising edge of TFCLK.
41
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 3. SPI3 Interface Signal Descriptions (Sheet 4 of 8)
Signal Name
Ball
Type
Standard
Description
Designator
MPHY
SPHY
DTPA_0:3 Direct Transmit Packet
Available.
A direct status indication for transmit FIFOs
of ports 0:3.
When High, DTPA indicates that the amount
of data in the TX FIFO is below the TX FIFO
High watermark. When the High watermark
is crossed, DTPA transitions Low to indicate
that the TX FIFO is almost full. It stays Low
until the amount of data in the TX FIFO
goes back below the TX FIFO Low
watermark. At this point, DTPA transitions
High to indicate that the programmed
number of bytes are now available for data
transfers.
DTPA_0
DTPA_1
DTPA_2
DTPA_3
DTPA_0
DTPA_1
DTPA_2
DTPA_3
D3
L1
A9
J7
3.3 V
LVTTL
Output
NOTE: For more information, see
Table 132 “TX FIFO High
“TX FIFO Low Watermark Register
DTPA is updated on the rising edge of
TFCLK.
Selected-PHY Transmit Packet Available.
STPA is only meaningful in a 32-bit multi-
PHY mode.
STPA is a direct status indication for
transmit FIFOs of ports 0:3.
When High, STPA indicates that the amount
of data in the TX FIFO, specified by the
latest in-band address, is below the
TX FIFO High watermark. When the High
watermark is crossed, STPA transitions Low
to indicate the TX FIFO is almost full. It
stays Low until the amount of data in the
TX FIFO goes back below the TX FIFO Low
watermark. At this point, STPA transitions
High to indicate that the programmed
number of bytes are now available for data
transfers.
3.3 V
LVTTL
STPA
NA
C11
Output
NOTE: For more information, see
Table 132 “TX FIFO High
“TX FIFO Low Watermark Register
STPA provides the status indication for the
selected port to avoid FIFO overflows while
polling is performed. The port reported by
STPA is updated on the following rising
edge of TFCLK after TSX is sampled as
asserted. STPA is updated on the rising
edge of TFCLK.
Datasheet
42
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 3. SPI3 Interface Signal Descriptions (Sheet 5 of 8)
Signal Name
Ball
Type
Standard
Description
Designator
MPHY
SPHY
Polled-PHY Transmit Packet Available.
PTPA allows the polling of the port selected
by the TADR address bus.
When High, PTPA indicates that the amount
of data in the TX FIFO is below the TX FIFO
High watermark. When the High watermark
is crossed, PTPA transitions Low to indicate
that the TX FIFO is almost full. It stays Low
until the amount data in the TX FIFO goes
back below the TX FIFO Low watermark. At
this point, PTPA transitions High to indicate
that the programmed number of bytes are
now available for data transfers.
3.3 V
PTPA
PTPA
B11
Output
LVTTL
NOTE: For more information, see
Table 132 “TX FIFO High
“TX FIFO Low Watermark Register
The port reported by PTPA is updated on
the following rising edge of TFCLK after the
port address on TADR is sampled by the
PHY device.
PTPA is updated on the rising edge of
TFCLK.
RDAT31
RDAT30
RDAT29
RDAT28
RDAT27
RDAT26
RDAT25
RDAT24
RDAT7_3
RDAT6_3
RDAT5_3
RDAT4_3
RDAT3_3
RDAT2_3
RDAT1_3
RDAT0_3
F24
G24
G23
G22
G21
G20
G19
G18
Receive Data Bus.
RDAT carries payload data and in-band
addresses from the IXF1104 MAC.
3.3 V
LVTTL
Output
Output
Output
Mode
Bits
32-bit Multi-PHY
4 x 8 Single-PHY
[31:24]
[7:0] for port 3
RDAT23
RDAT22
RDAT21
RDAT20
RDAT19
RDAT18
RDAT17
RDAT16
RDAT7_2
RDAT6_2
RDAT5_2
RDAT4_2
RDAT3_2
RDAT2_2
RDAT1_2
RDAT0_2
E21
E22
D22
C22
C21
C20
B22
B20
Receive Data Bus.
RDAT carries payload data and in-band
addresses from the IXF1104 MAC.
3.3 V
LVTTL
Mode
Bits
32-bit Multi-PHY
4 x 8 Single-PHY
[23:16]
[7:0] for port 2
RDAT15
RDAT14
RDAT13
RDAT12
RDAT11
RDAT10
RDAT9
RDAT7_1
RDAT6_1
RDAT5_1
RDAT4_1
RDAT3_1
RDAT2_1
RDAT1_1
RDAT0_1
F18
E18
E17
F16
E16
D16
C17
A17
Receive Data Bus.
RDAT carries payload data and in-band
addresses from the IXF1104 MAC.
3.3 V
LVTTL
Mode
Bits
32-bit Multi-PHY
4 x 8 Single-PHY
[15:8]
[7:0] for port 1
RDAT8
43
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 3. SPI3 Interface Signal Descriptions (Sheet 6 of 8)
Signal Name
Ball
Type
Standard
Description
Designator
MPHY
SPHY
RDAT7
RDAT6
RDAT5
RDAT4
RDAT3
RDAT2
RDAT1
RDAT0
RDAT7_0
RDAT6_0
RDAT5_0
RDAT4_0
RDAT3_0
RDAT2_0
RDAT1_0
RDAT0_0
F14
E14
D14
C13
C14
B14
A14
A15
Receive Data Bus.
RDAT carries payload data and in-band
addresses from the IXF1104 MAC.
3.3 V
LVTTL
Output
Mode
Bits
32-bit Multi-PHY
4 x 8 Single-PHY
[7:0]
[7:0] for port 0
Receive Clock.
RFCLK is the clock associated with all
receive signals. Data and controls are
driven on the rising edge of RFCLK
(frequency operation range 90 - 133 MHz).
3.3 V
LVTTL
RFCLK
RFCLK
A19
Input
Receive Parity.
RPRTY indicates odd parity for the RDAT
bus. RPRTY is valid only when a channel
asserts RENB or RSX. Odd parity is the
default configuration; however, even parity
page 215).
RPRTY_0 RPRTY_0
RPRTY_1
E15
G16
E20
F20
3.3 V
LVTTL
Output
RPRTY_2
RPRTY_3
32-bit Multi-PHY mode: RPRTY_0 is the
parity bit for all 32 bits.
4 x 8 Single-PHY mode: Each bit of
RPRTY_0:3 corresponds to the respective
RDAT[3:0]_n channel.
Receive Read Enable.
The RENB signal controls the flow of data
from the receive FIFOs. During data
transfer, RVAL must be monitored as it
indicates if the RDAT[31:0], RPRTY,
RMOD[1:0], RSOP, REOP, RERR, and RSX
are valid. The system may de-assert RENB
at any time if it is unable to accept data from
the IXF1104 MAC. When RENB is sampled
Low, a read is performed from the receive
FIFO and the RDAT[31:0], RPRTY,
RENB_0
RENB_0
RENB_1
RENB_2
RENB_3
A13
A18
C19
E24
RMOD[1:0], RSOP, REOP, RERR, RSX and
RVAL signals are updated on the following
rising edge of RFCLK.
3.3 V
LVTTL
Input
When RENB is sampled High by the PHY
device, a read is not performed, and the
RDAT[31:0], RPRTY, RMOD[1:0], RSOP,
REOP, RERR, RSX, and RVAL signals
remain unchanged on the following rising
edge of RFCLK.
32-bit Multi-PHY Mode: RENB_0 covers all
receive bits.
4 x 8 Single-PHY Mode: The RENB_0:3
bits correspond to the per-port data and
control signals.
Datasheet
44
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 3. SPI3 Interface Signal Descriptions (Sheet 7 of 8)
Signal Name
Ball
Type
Standard
Description
Designator
MPHY
SPHY
Receive Error.
RERR indicates that the current packet is in
error. RERR is only asserted when REOP is
asserted. Conditions that can cause RERR
to be set include FIFO overflow, CRC error,
code error, and runt or giant packets.
NOTE: RERR can only be set for these
conditions if bit 0 in the “SPI3
RERR_0
RERR_0
RERR_1
RERR_2
RERR_3
A16
G17
D20
H20
set to 1.
3.3 V
LVTTL
Output
RERR is considered valid only when RVAL
is asserted.
32-bit Multi-PHY mode: RERR_0 covers
all 32 bits.
4 x 8 Single-PHY mode: The RERR_0:3
bits correspond to the RDAT[7:0]_n
channels.
(n = 0, 1, 2, or 3)
Receive Data Valid.
RVAL indicates the validity of the receive
data signals. RVAL is Low between
transfers and assertion of RSX. It is also
Low when the IXF1104 MAC pauses a
transfer due to an empty receive FIFO.
When a transfer is paused by holding RENB
High, RVAL holds its value unchanged,
although no new data is present on
RDAT[31:0] until the transfer resumes.
When RVAL is High, the RDAT[31:0],
RMOD[1:0], RSOP, REOP, and RERR
signals are valid. When RVAL is Low, the
RDAT[31:0], RMOD[1:0], RSOP, REOP, and
RERR signals are invalid and must be
disregarded.
RVAL_0
RVAL_0
RVAL_1
RVAL_2
RVAL_3
C15
B18
E19
F22
3.3 V
LVTTL
Output
The RSX signal is valid only when RVAL is
Low.
32-bit Multi-PHY mode: RVAL_0 covers all
receive bits.
4 x 8 Single-PHY mode: The RVAL_0:3
bits correspond to the per-port data and
control signals.
Receive Start of Packet.
RSOP indicates the start of a packet when
asserted with RVAL.
RSOP_0
RSOP_0
RSOP_1
RSOP_2
RSOP_3
B16
C18
E23
J18
3.3 V
LVTTL
32-bit Multi-PHY mode: RSOP_0 covers
all 32 bits.
Output
4 x 8 Single-PHY mode: The RSOP_0:3
bits correspond to the RDAT[7:0]_n
channels.
45
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 3. SPI3 Interface Signal Descriptions (Sheet 8 of 8)
Signal Name
Ball
Type
Standard
Description
Designator
MPHY
SPHY
Receive End of Packet.
REOP indicates the end of a packet when
asserted with RVAL.
REOP_0
REOP_0
REOP_1
REOP_2
REOP_3
C16
D18
C23
J19
3.3 V
LVTTL
32-bit Multi-PHY mode: REOP_0 covers
all 32 bits.
Output
4 x 8 Single-PHY mode: The REOP_0:3
bits correspond to the RDAT[7:0]_n
channels.
Receive Word Modulo:
32-bit Multi-PHY mode: RMOD[1:0]
indicates the valid bytes of data in
RDAT[31:0]. During transmission, RMOD is
always “00”, except when the last double-
word is transferred on RDAT[31:0].
RMOD[1:0] specifies the valid packet data
bytes on RDAT[31:0] when REOP is
asserted.
RMOD[1:0]
Valid Bytes of RDAT
RMOD1
RMOD0
G13
G14
3.3 V
LVTTL
NA
Output
00 = 4 bytes [31:0]
01 = 3 bytes [31:8]
10 = 2 bytes [31:16]
11 = 1 byte [31:24]
4 x 8 Single-PHY mode: RMOD[1:0] is not
required.
RMOD is considered valid only when RVAL
is simultaneously asserted.
RENB must be asserted for RMOD[1:0] to
be valid.
Receive Start of Transfer.
32-bit Multi-PHY mode: RSX indicates
when the in-band port address is present on
the RDAT bus. When RSX is High and
RVAL = 0, the value of RDAT[7:0] is the
address of the receive FIFO to be selected.
Subsequent data transfers on RDAT are
from the FIFO specified by this in-band
address. Values of 0, 1, 2, and 3 select the
corresponding port. RSX is ignored when
RVAL is de-asserted.
3.3 V
LVTTL
RSX
NA
E13
Output
4 x 8 Single-PHY mode: RSX is ignored.
Datasheet
46
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 4. SerDes Interface Signal Descriptions
Signal Name
Ball Designator
Type
Standard Description
TX_P_0
TX_P_1
TX_P_2
TX_P_3
Y13
AD13
W16
Output
SerDes
SerDes
SerDes
SerDes
Transmit Differential Output, Positive.
AC18
TX_N_0
TX_N_1
TX_N_2
TX_N_3
Y14
AD14
Y16
AD18
Output
Input
Transmit Differential Output, Negative.
Receive Differential Input, Positive.1
Receive Differential Input, Negative.1
RX_P_0
RX_P_1
RX_P_2
RX_P_3
P22
V22
T24
U24
RX_N_0
RX_N_1
RX_N_2
RX_N_3
R22
U22
R24
V24
Input
1. Internally terminated differentially with 100 Ω.
47
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 5. GMII Interface Signal Descriptions (Sheet 1 of 2)
Signal Name
Ball Designator
Type
Standard Description
TXD7_0
TXD6_0
TXD5_0
TXD4_0
TXD3_0
TXD2_0
TXD1_0
TXD0_0
Y4
AB4
AC3
AB3
AA3
Y3
Y2
Y1
TXD7_1
TXD6_1
TXD5_1
TXD4_1
TXD3_1
TXD2_1
TXD1_1
TXD0_1
AC9
AD8
AB8
AA7
AD9
AB9
AB7
AC7
Transmit Data.
Each bus carries eight data bits [7:0] of
the transmitted data stream to the PHY
device.
RGMII Mode: When a port is
configured in copper mode and the
RGMII interface is selected, only bits
TXD[3:0]_n are used. The data is
transmitted on both edges of TXC_0:3.
2.5 V
CMOS
Output
TXD7_2
TXD6_2
TXD5_2
TXD4_2
TXD3_2
TXD2_2
TXD1_2
TXD0_2
AA18
AA20
AB19
AD16
AB23
AB22
AB21
AB20
Fiber Mode: The following signals
have multiplexed functions when a port
is configured in fiber mode:
TXD4_n: TX_DISABLE_0:3
TXD7_3
TXD6_3
TXD5_3
TXD4_3
TXD3_3
TXD2_3
TXD1_3
TXD0_3
W14
AA16
Y15
AA14
V17
V16
V15
V14
Transmit Enable.
TX_EN_0
TX_EN_1
TX_EN_2
TX_EN_3
AB2
Y8
AC22
TX_EN indicates that valid data is
being driven on the corresponding
Transmit Data: TXD_0, TXD_1, TXD_2,
and TXD_3.
2.5 V
CMOS
Output
Output
V12
Transmit Error:
TX_ER_0
TX_ER_1
TX_ER_2
TX_ER_3
W1
AD6
AD17
AB13
2.5 V
CMOS
TX_ER indicates a transmit error in the
corresponding Transmit Data: TXD_0,
TXD_1, TXD_2, and TXD_3.
Source Synchronous Transmit
Clock.
TXC_0
TXC_1
TXC_2
TXC_3
AA1
AD7
AC20
This clock is supplied synchronous to
the transmit data bus in either RGMII or
GMII mode.
2.5 V
CMOS
Output
AB14
NOTE: Shares the same balls as RXC
on the RGMII interface.
NOTE: Refer to the RGMII interface for shared data and clock signals.
Datasheet
48
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 5. GMII Interface Signal Descriptions (Sheet 2 of 2)
Signal Name
Ball Designator
Type
Standard Description
RXD7_0
RXD6_0
RXD5_0
RXD4_0
RXD3_0
RXD2_0
RXD1_0
RXD0_0
AC5
AB5
Y5
Y6
Y7
W7
V7
V8
RXD7_1
RXD6_1
RXD5_1
RXD4_1
RXD3_1
RXD2_1
RXD1_1
RXD0_1
Y10
AA11
AC11
AD10
W9
W11
Y11
Y9
Receive Data:
Each bus carries eight data bits [7:0] of
the received data stream.
RGMII Mode: When a port ID is
configured in copper mode and the
RGMII interface is selected, only bits
RXD[3:0]_n are used to receive data.
2.5 V
CMOS
Input
Fiber Mode: The following signals
have multiplexed functions when a port
is configured in fiber mode:
RXD7_2
RXD6_2
RXD5_2
RXD4_2
RXD3_2
RXD2_2
RXD1_2
RXD0_2
W20
V19
V20
W22
Y23
Y22
Y21
Y20
RXD4_n: MOD_DEF_0:3
RXD5_n: TX_FAULT_0:3
RXD6_n: RX_LOS_0:3
RXD7_3
RXD6_3
RXD5_3
RXD4_3
RXD3_3
RXD2_3
RXD1_3
RXD0_3
T19
T18
T17
T16
W18
Y19
Y18
Y17
Receive Data Valid.
RX_DV_0
RX_DV_1
RX_DV_2
RX_DV_3
V5
AB11
Y24
V18
2.5 V
CMOS
RX_DV indicates that valid data is
being driven on Receive Data:
RXD[7:0]_n.
Input
RX_ER_0
RX_ER_1
RX_ER_2
RX_ER_3
W5
Y12
AA22
U20
Receive Error.
2.5 V
CMOS
Input
Input
RX_ER indicates an error in Receive
Data: RXD[7:0]_n.
CRS_0
CRS_1
CRS_2
CRS_3
AA5
AA9
AB15
AC16
Carrier Sense.
2.5 V
CMOS
CRS indicates the PHY device has
detected a carrier.
Receiver Reference Clock.
RXC operates at:
RXC_0
RXC_1
RXC_2
RXC_3
V4
AD11
AA24
V23
2.5 V
CMOS
125 MHz for 1 Gigabit
Input
NOTE: Shares the same balls as RXC
on the RGMII interface.
NOTE: Refer to the RGMII interface for shared data and clock signals.
49
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 6. RGMII Interface Signal Descriptions (Sheet 1 of 2)
Ball
Designator
Signal Name
Type
Standard
Description
TXC_0
TXC_1
TXC_2
TXC_3
AA1
AD7
AC20
Source Synchronous Transmit Clock.
2.5 V
CMOS
Output
This clock is supplied synchronous to the transmit
data bus in either RGMII or GMII mode.
AB14
TD3_0
TD2_0
TD1_0
TD0_0
AA3
Y3
Y2
Y1
TD3_1
TD2_1
TD1_1
TD0_1
AD9
AB9
AB7
AC7
Transmit Data.
Bits [3:0] are clocked on the rising edge of TXC.
Bits [7:4] are clocked on the falling edge of TXC.
2.5 V
CMOS
Output
TD3_2
TD2_2
TD1_2
TD0_2
AB23
AB22
AB21
AB20
NOTE: Shares data signals TXD[3:0]_n with the
GMII interface.
TD3_3
TD2_3
TD1_3
TD0_3
V17
V16
V15
V14
Transmit Control.
TX_CTL is TX_EN on the rising edge of TXC and a
logical derivative of TX_EN and TX_ER on the
falling edge of TXC.
TX_CTL_0
TX_CTL_1
TX_CTL_2
TX_CTL_3
AB2
Y8
AC22
2.5 V
CMOS
Output
V12
NOTE: TX_CTL multiplexes with TX_EN_n on the
GMII interface.
Receiver Reference Clock.
Operates at:
125 MHz for 1 Gigabit
25 MHz for 100 Mbps
2.5 MHz for 10 Mbps
RXC_0
RXC_1
RXC_2
RXC_3
V4
AD11
AA24
V23
2.5 V
CMOS
Input
NOTE: Shares the same balls as RXC on the
GMII interface.
Datasheet
50
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 6. RGMII Interface Signal Descriptions (Sheet 2 of 2)
Ball
Designator
Signal Name
Type
Standard
Description
RD3_0
RD2_0
RD1_0
RD0_0
Y7
W7
V7
V8
RD3_1
RD2_1
RD1_1
RD0_1
W9
W11
Y11
Y9
Receive Data.
Bits [3:0] are clocked on the rising edge of RXC.
Bits [7:4] are clocked on the falling edge of RXC.
2.5 V
CMOS
Input
RD3_2
RD2_2
RD1_2
RD0_2
Y23
Y22
Y21
Y20
NOTE: Shares balls with RXD[3:0]_0 on the GMII
interface.
RD3_3
RD2_3
RD1_3
RD0_3
W18
Y19
Y18
Y17
Receive Control.
RX_CTL is RX_DV on the rising edge of RXC and
a logical derivative of RX_DV and RERR on the
falling edge of RXC.
RX_CTL_0
RX_CTL_1
RX_CTL_2
RX_CTL_3
V5
AB11
Y24
V18
2.5 V
CMOS
Input
NOTE: RX_CTL shares the same balls as RX_DV
on the GMII interface.
Table 7. CPU Interface Signal Descriptions (Sheet 1 of 2)
Ball
Designator
Signal Name
Type
Standard
Description
UPX_ADD10
UPX_ADD9
UPX_ADD8
UPX_ADD7
UPX_ADD6
UPX_ADD5
UPX_ADD4
UPX_ADD3
UPX_ADD2
UPX_ADD1
UPX_ADD0
T3
U3
V3
V2
V1
U1
T1
R1
P1
N1
P3
UPX_ADD is the address bus from the
microprocessor.
Input
3.3 V LVTTL
16-bit mode: The data word select uses
UPX_BADD1.
UPX_BADD1
UPX_BADD0
W3
T2
Input
3.3 V LVTTL
8-bit mode: UPX_BADD[1:0] selects the individual
bytes.
51
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 7. CPU Interface Signal Descriptions (Sheet 2 of 2)
Ball
Designator
Signal Name
Type
Standard
Description
UPX_DATA31
UPX_DATA30
UPX_DATA29
UPX_DATA28
UPX_DATA27
UPX_DATA26
UPX_DATA25
UPX_DATA24
UPX_DATA23
UPX_DATA22
UPX_DATA21
UPX_DATA20
UPX_DATA19
UPX_DATA18
UPX_DATA17
UPX_DATA16
UPX_DATA15
UPX_DATA14
UPX_DATA13
UPX_DATA12
UPX_DATA11
UPX_DATA10
UPX_DATA9
UPX_DATA8
UPX_DATA7
UPX_DATA6
UPX_DATA5
UPX_DATA4
UPX_DATA3
UPX_DATA2
UPX_DATA1
UPX_DATA0
L17
J17
H16
J16
M15
N15
K15
H14
K13
G12
K12
G11
H11
G10
K10
M10
N10
J9
H9
L8
N7
L7
L6
P5
K5
M5
Data bus.
32-bit mode: Uses [31:0]
16-bit mode: Uses [15:0]
8-bit mode: Uses [7:0]
Input/
Output
3.3 V LVTTL
N5
L4
M3
L3
K3
L2
UPX_CS_L
UPX_WR_L
UPX_RD_L
R3
T4
V6
Input
Input
Input
3.3 V LVTTL Chip Select. Active Low.
3.3 V LVTTL Write Strobe. Active Low.
3.3 V LVTTL Read Strobe. Active Low.
Cycle complete indicator.
Active Low.
Open
Drain
Output*
NOTE: An external pull-up resistor is required for
proper operation.
NOTE: *Dual-mode I/O
UPX_RDY_L
M1
3.3 V LVTTL
Normal operation: Open drain output
Boundary Scan Mode: Standard CMOS
output
Data bus width select.
UPX_WIDTH[1:0] specifies the CPU bus width.
UPX_WIDTH1
UPX_WIDTH0
T5
U16
UPX_WIDTH[1:0]
Mode
8-bit
Input
3.3 V LVTTL
00
01
1x
16-bit
32-bit
Datasheet
52
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 8. Transmit Pause Control Interface Signal Descriptions
Ball
Designator
Signal Name
Type
Standard Description
TXPAUSEADD2
TXPAUSEADD1
TXPAUSEADD0
P21
P20
N20
2.5 V
CMOS
TXPAUSEADD[2:0] is the port selection address
for pause frame insertion.
Input
Input
2.5 V
CMOS
TXPAUSEFR
T20
TX Pause Interface Strobe.
Table 9. Optical Module Interface Signal Descriptions (Sheet 1 of 2)
Ball
Designator
Signal Name
Type
Standard Description
Transmit Disable:
TX_DISABLE_0:3 outputs disable the Optical
Module Interface transmitter. An external pull-up
resistor usually resident in an optical module is
required for proper operation.
TX_DISABLE_0
TX_DISABLE_1
TX_DISABLE_2
TX_DISABLE_3
AB3
AA7
AD16
AA14
Open
Drain
Output*
2.5 V
CMOS
NOTE: These signals are multiplexed with the
TXD[4]_n bits of the GMII Interface
NOTE: *Dual-mode I/O
Normal operation: Open drain output
Boundary Scan Mode: Standard CMOS
output
MOD_DEF_0:3 inputs determine when an
Optical Module Interface is present.
MOD_DEF_0
MOD_DEF_1
MOD_DEF_2
MOD_DEF_3
Y6
AD10
W22
T16
2.5 V
CMOS
Input
Input
Input
NOTE: These signals are multiplexed with the
RXD[4]_n bits of the GMII interface.
RX_LOS_0:3 inputs determine when the Optical
Module Interface receiver loses synchronization.
RX_LOS_0
RX_LOS_1
RX_LOS_2
RX_LOS_3
AB5
AA11
V19
2.5 V
CMOS
NOTE: These signals are multiplexed with the
T18
RXD[6]_n bits of the GMII interface.
TX_FAULT_0:3 inputs determine an Optical
Module Interface transmitter fault.
TX_FAULT_0
TX_FAULT_1
TX_FAULT_2
TX_FAULT_3
Y5
AC11
V20
T17
2.5 V
CMOS
NOTE: These signals are multiplexed with the
RXD[5]_n bits of the GMII Interface.
Receiver Loss of Signal Interrupt.
RX_LOS_INT is an open drain interrupt output to
signal an RX_LOS condition.
Open
Drain
Output*
2.5 V
CMOS
NOTE: An external pull-up resistor is required
for proper operation.
NOTE: *Dual-mode I/O
RX_LOS_INT
P19
Normal operation: Open drain output
Boundary Scan Mode: Standard CMOS
output
53
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 9. Optical Module Interface Signal Descriptions (Sheet 2 of 2)
Ball
Designator
Signal Name
Type
Standard Description
Transmitter Fault Interrupt.
TX_FAULT_INT is an open drain interrupt output
that signals a TX_FAULT condition.
Open
Drain
Output*
2.5 V
CMOS
NOTE: An external pull-up resistor is
required for proper operation.
NOTE: *Dual-mode I/O
TX_FAULT_INT
P23
Normal operation: Open drain output
Boundary Scan Mode: Standard CMOS
output
Module Definition Interrupt.
MOD_DEF_INT is an open drain interrupt output
that signals a MOD_DEF condition.
Open
Drain
Output*
2.5 V
CMOS
NOTE: An external pull-up resistor is
required for proper operation.
NOTE: *Dual-mode I/O
MOD_DEF_INT
N22
L23
Normal operation: Open drain output
Boundary Scan Mode: Standard CMOS
output
2.5 V
CMOS
I2C_CLK is the clock used for the I2C bus
interface.
I2C_CLK
Output
I2C Data Bus.
I2C DATA_0:3 are the data I/Os for the I2C bus
interface.
I2C DATA_0
I2C DATA_1
I2C DATA_2
I2C DATA_3
L24
M24
N24
P24
Input/
Open
Drain
NOTE: An external pull-up resistor is
required for proper operation.
NOTE: *Dual-mode I/O
Normal operation: Input/ open drain
output
2.5 V
CMOS
Output*
Boundary Scan Mode: Standard CMOS
output
Table 10. MDIO Interface Signal Descriptions
Ball
Designator
Signal Name
Type
Standard Description
MDIO is the management data input and output.
Input/
Output
2.5 V
CMOS
MDIO
MDC
V21
NOTE: An external pull-up resistor is required for
proper operation.
2.5 V
CMOS
W24
Output
MDC is the management clock to external devices.
Datasheet
54
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 11. LED Interface Signal Descriptions
Ball
Designator
Signal Name
Type
Standard Description
2.5 V
CMOS
LED_CLK
K24
Output
Output
Output
LED_CLK is the clock output for the LED block.
2.5 V
CMOS
LED_DATA
LED_LATCH
M22
L22
LED_DATA is the data output for the LED block.
LED_LATCH is the latch enable for the LED block.
2.5 V
CMOS
Table 12. JTAG Interface Signal Descriptions
Ball
Designator
Signal Name
Type
Standard Description
3.3 V
LVTTL
TCLK
TMS
J22
Input
Input
JTAG Test Clock
3.3 V
LVTTL
H22
J24
H24
J23
Test Mode Select
3.3 V
LVTTL
TDI
Input
Test Data Input
3.3 V
LVTTL
TDO
Output
Input
Test Data Output
3.3 V
LVTTL
TRST_L
Test Reset; reset input for JTAG test
Table 13. System Interface Signal Descriptions
Ball
Designator
Signal Name
Type
Standard Description
2.5 V
CMOS
CLK125 is the input clock to PLL; 125 MHz +/-
50 ppm
CLK125
AD19
Input
Input
2.5 V
CMOS
SYS_RES_L
AD12
SYS_RES_L is the system hard reset (active Low).
55
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 14. Power Supply Signal Descriptions
Signal Name
Ball Designator
Type
Standard Description
A4
B15
D12
F2
F19
H12
J10
K9
K19
L12
M4
M17
N11
P10
R2
A21
B19
D13
F6
F23
H13
J15
K11
K23
L13
M8
B6
D4
D17
F10
H4
H17
K2
K14
L5
L15
M11
N4
N17
P13
R7
B10
D8
D21
F15
H8
H21
K6
K16
L10
L20
M14
N8
N21
P15
R9
GND
M21
N14
P12
R6
Input
–
Digital ground
R11
R23
U8
U21
W15
AA8
AA21
R14
T10
U12
W2
R16
T15
U13
W6
W23
R19
U4
U17
W10
AA4
W19
AA12 AA13 AA17
AB12 AC6 AC10
AC14 AC15 AC19 AD21
AVDD1P8_1
AVDD1P8_2
AVDD2P5_1
AVDD2P5_2
A5
A20
T23
Input
Input
Input
Input
1.8 V
1.8 V
2.5 V
2.5 V
Analog 1.8 V supply
Analog 1.8 V supply
Analog 2.5 V supply
Analog 2.5 V supply
AB16
AD20
U14
R18
A10
D11
F21
J14
K17
L14
P14
R17
U10
AA6
C12
D15
H10
J20
K21
L16
P16
R21
U15
D6
D19
H15
K4
L9
P9
R4
T11
W4
D10
F4
J11
K8
L11
P11
R8
T14
W21
VDD
Input
1.8 V
Digital 1.8 V supply
AA10 AA15 AA19
B4
F8
J12
B8
F12
M2
B12
H2
M6
D2
H6
M9
VDD2
VDD3
VDD4
VDD5
Input
Input
Input
Input
3.3 V
3.3 V
2.5 V
2.5 V
Digital 3.3 V supply
Digital 3.3 V supply
Digital 2.5 V supply
Digital 2.5 V supply
M12
B13
F13
J13
M23
B17
F17
M13
B21
H19
M16
D23
H23
M19
N13
T13
W17
N16
U19
N19
U23
N23
W13
AA23 AC13 AC17
AC21
N2
T12
W12
N6
U2
AA2
N9
U6
AC4
N12
W8
AC8
AC12
Datasheet
56
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
4.4
Ball Usage Summary
Table 15. Ball Usage Summary
Type
Quantity
Inputs
158
126
37
Outputs
Bi-directional
Total Signals
Power
321
75
Ground
82
No Connects
Total
74
552
57
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
4.5
Multiplexed Ball Connections
4.5.1
GMII/RGMII/SerDes/OMI Multiplexed Ball Connections
a guide to connect these balls. Some of these balls are multiplexed depending on the mode of
operation selected for that port.
Note: Do not connect any balls marked as unused (NC).
Table 16. Line Side Interface Multiplexed Balls (Sheet 1 of 2)
Copper Mode
Fiber Mode
Unused Port
Ball Designator
Optical Module/
SerDes Signal
GMII Signal
RGMII Signal
TXC_0:3
TXC_0:3
NC
NC
NC
NC
NC
AA1
AD7
AC20
AB14
TXD[3:0]_0
TXD[3:0]_1
TXD[3:0]_2
TXD[3:0]_3
TD[3:0]_0
TD[3:0]_1
TD[3:0]_2
TD[3:0]_3
AA3
AD9
AB23
V17
Y3
AB9
AB22
V16
Y2
AB7
AB21
V15
Y1
AC7
AB20
V14
NC
TXD4_0:3
NC
TX_DISABLE_0:32
NC
AB3
AA7
AD16
AA14
TXD[7:5]_0
TXD[7:5]_1
TXD[7:5]_2
TXD[7:5]_3
Y4
AB4
AD8
AA20
AC3
AB8
AB19
AC9
AA18
W14
NC
AA16
Y15
TX_EN_0:3
TX_ER_0:3
RXC_0:3
TX_CTL_0:3
NC
NC
NC
NC
AB2
W1
V4
Y8
AC22
AD17
AA24
V12
AB13
V23
NC
AD6
AD11
RXC_0:3
GND
GND
RXD[3:0]_0
RXD[3:0]_1
RXD[3:0]_2
RXD[3:0]_3
RD[3:0]_0
RD[3:0]_1
RD[3:0]_2
RD[3:0]_3
Y7
W9
Y23
W18
W7
W11
Y22
Y19
V7
V8
Y9
Y20
Y17
Y11
Y21
Y18
GND
GND
RXD4_0:3
RXD5_0:3
RXD6_0:3
RXD7_0:3
RX_DV_0:3
RX_ER_0:3
CRS_0:3
COL_0:3
GND
GND
GND
GND
GND
RX_CTL_0:3
GND
GND
GND
GND
GND
NC
MOD_DEF_0:31
TX_FAULT_0:31
RX_LOS_0:31
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
Y6
Y5
AD10
AC11
AA11
Y10
W22
V20
T16
T17
AB5
AC5
V5
V19
T18
W20
Y24
T19
GND
AB11
Y12
V18
GND
W5
AA22
AB15
AD15
T24
U20
GND
AA5
AB6
P22
R22
Y13
Y14
AA9
AC16
AB17
U24
GND
AB10
V22
RX_P_0:3
RX_N_0:3
TX_P_0:3
TX_N_0:3
GND
U22
R24
V24
NC
AD13
AD14
W16
Y16
AC18
AD18
NC
NC
NC
1. An external pull-up resistor is required with most optical modules.
2. An open drain I/O, external 4.7 k Ω pull-up resistor is required.
Datasheet
58
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 16. Line Side Interface Multiplexed Balls (Sheet 2 of 2)
Copper Mode
Fiber Mode
Unused Port
Ball Designator
Optical Module/
SerDes Signal
GMII Signal RGMII Signal
NC
NC
TX_FAULT_INT2
RX_LOS_INT2
MOD_DEF_INT2
NC
NC
NC
NC
NC
NC
NC
NC
P23
P19
N22
W24
V21
L23
L24
NC
NC
NC
NC
MDC
MDIO2
NC
MDC
MDIO2
NC
NC
I2C_CLK
NC
NC
I2C_DATA_0:32
M24
N24
P24
1. An external pull-up resistor is required with most optical modules.
2. An open drain I/O, external 4.7 k Ω pull-up resistor is required.
4.5.2
SPI3 MPHY/SPHY Ball Connections
MPHY and SPHY mode.
Table 17. SPI3 MPHY/SPHY Interface (Sheet 1 of 3)
SPI3 Signals
Ball Number
Comments
MPHY
SPHY
F7
G7
F5
G6
G9
G5
G8
G4
TDAT[31:24]
TDAT[7:0]_3
C8
E8
F9
E7
E10
E6
E9
E5
MPHY: Consists of a single 32-bit data
bus
TDAT[23:16]
TDAT[15:8]
TDAT[7:0]
TDAT[7:0]_2
TDAT[7:0]_1
TDAT[7:0]_0
SPHY: Separate 8-bit data bus for each
Ethernet port
H3
H1
J3
G2
J2
G1
J1
F1
C6
D1
B5
C3
C5
C2
C4
B3
To achieve maximum bandwidth, set
TFCLK as follows:
TFCLK
TFCLK
D7
MPHY: 133 MHz
SPHY: 125 MHz.
TPRTY_0
GND
TPRTY_0
TPRTY_1
TPRTY_2
TPRTY_3
TENB_0
TENB_1
TENB_2
TENB_3
D5
G3
B9
J6
MPHY: Use TPRTY_0 as the TPRTY
signal.
SPHY: Each port has its own dedicated
TPRTY_n signal.
GND
GND
TENB_0
VDD2
VDD2
VDD2
B7
E2
C9
J4
MPHY: Use TENB_0 as the TENB
signal.
SPHY: Each port has its own dedicated
TENB_n signal.
59
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 17. SPI3 MPHY/SPHY Interface (Sheet 2 of 3)
SPI3 Signals
MPHY SPHY
TERR_0 TERR_0
Ball Number
Comments
A8
K1
E11
J8
MPHY: Use TERR_0 as the TERR
GND
TERR_1
TERR_2
TERR_3
TSOP_0
TSOP_1
TSOP_2
TSOP_3
TEOP_0
TEOP_1
TEOP_2
TEOP_3
GND
signal.
SPHY: Each port has its own dedicated
TERR_n signal
GND
GND
TSOP_0
GND
C7
E3
C10
J5
MPHY: Use TSOP_0 as the TSOP
signal.
SPHY: Each port has a dedicated
TSOP_n signal.
GND
GND
TEOP_0
GND
A7
F3
MPHY: Use TEOP_0 as the TEOP
signal.
SPHY: Each port has a dedicated
TEOP_n signal.
GND
E4
H5
D9
E1
A12
GND
TMOD[1:0]
TSX
A6
TSX and TMOD[1:0] are only applicable
in MPHY mode.
GND
TADR[1:0]
TADR[1:0]
A11
Used to address port for PTPA signal.
PTPA can be used in MPHY and SPHY
modes.
PTPA
PTPA
B11
DTPA is available on a per-port basis in
both MPHY and SPHY modes.
DTPA_0:3
STPA
DTPA_0:3
NC
D3
L1
A9
J7
C11
STPA is only applicable in MPHY mode.
F24
G21
G24
G20
G23
G19
G22
G18
RDAT[31:24]
RDAT[7:0]_3
E21
C21
E22
C20
D22
B22
C22
B20
MPHY: Consists of a single 32 bit data
bus.
RDAT[23:16]
RDAT[15:8]
RDAT[7:0]
RDAT[7:0]_2
RDAT[7:0]_1
RDAT[7:0]_0
SPHY: Separate 8-bit data bus for each
Ethernet port.
F18
E16
E18
D16
E17
C17
F16
A17
F14
C14
E14
B14
D14
A15
C13
A14,
To achieve maximum bandwidth, set
RFCLK as follows:
RFCLK
RFCLK
A19
MPHY: 133 MHz.
SPHY: 125 MHz.
RPRTY_0
NC
RPRTY_0
RPRTY_1
RPRTY_2
RPRTY_3
RENB_0
RENB_1
RENB_2
RENB_3
E15
G16
E20
F20
A13
A18
C19
E24
MPHY: Use RPRTY_0 as the RPRTY
signal.
SPHY: Each port has a dedicated
RPRTY_n signal.
NC
NC
RENB_0
VDD2
VDD2
VDD2
MPHY: Use RENB_0 as the RENB
signal.
SPHY: Each port has a dedicated
RENB_n signal
Datasheet
60
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 17. SPI3 MPHY/SPHY Interface (Sheet 3 of 3)
SPI3 Signals
Ball Number
Comments
MPHY
SPHY
RERR_0
RERR_0
A16
G17
D20
H20
C15
B18
E19
F22
B16
C18
E23
J18
MPHY: Use RERR_0 as the RERR
signal.
NC
RERR_1
RERR_2
RERR_3
RVAL_0
RVAL_1
RVAL_2
RVAL_3
RSOP_0
RSOP_1
RSOP_2
RSOP_3
REOP_0
REOP_1
REOP_2
REOP_3
NC
SPHY: Each port has a dedicated
RERR_n signal
NC
NC
RVAL_0
NC
MPHY: Use RVAL_0 as the RVAL
signal.
SPHY: Each port has a dedicated
RVAL_n signal.
NC
NC
RSOP_0
NC
MPHY: Use TSOP_0 as the TSOP
signal.
SPHY: Each port has a dedicated
TSOP_n signal.
NC
NC
REOP_0
NC
C16
D18
C23
J19
MPHY: Use TEOP_0 as the TEOP
signal.
SPHY: Each port has a dedicated
TEOP_n signal.
NC
NC
RMOD[1:0]
RSX
G13
E13
G14
RSX and RMOD[1:0] are applicable
only in MPHY mode.
NC
4.6
Ball State During Reset
Table 18. Definition of Output and Bi-directional Balls During Hardware Reset (Sheet 1 of 2)
Interface
Ball Name
DTPA_0:3
Ball Reset State Comment
0x0
0x0
–
–
–
–
–
–
–
–
–
–
–
STPA
PTPA
0x0
RDAT[31:0]
RVAL_0:3
RERR_0:3
RPRTY_0:3
RMOD[1:0]
RSX
0x00000000
0x0
SPI3
0x0
0x0
0x0
0x0
RSOP_0:3
REOP_0:3
0x0
0x0
NOTE: Z = High impedance.
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Table 18. Definition of Output and Bi-directional Balls During Hardware Reset (Sheet 2 of 2)
Interface
JTAG
Ball Name
TDO
Ball Reset State Comment
0x0
High Z
0x0
–
MDIO
Bi-directional
MDIO
CPU
MDC
–
UPX_DATA[31:0]
UPX_RDY_L
LED_CLK
LED_DATA
LED_LATCH
High Z
0X1
Bi-directional
Open-drain output, requires an external pull-up
0x0
–
–
–
LED
0x0
0x0
Fiber mode is the default. Copper interfaces are
disabled.
TXC_0:3
High Z
High Z
Fiber mode is the default.
TXD[7:0]_0
Bit 4 is driven by the optical module as MOD_DEF_0.
Fiber mode is the default.
TXD[7:0]_1
TXD[7:0]_2
TXD[7:0]_3
High Z
High Z
High Z
Bit 4 is driven by the optical module as MOD_DEF_1.
Fiber mode is the default.
GMII/RGMII
Bit 4 is driven by the optical module as MOD_DEF_2.
Fiber mode is the default.
Bit 4 is driven by the optical module as MOD_DEF_3.
Fiber mode is the default.
Copper interfaces are disabled.
TX_EN_0:3
TX_ER_0:3
TX_CTL_0:3
High Z
High Z
High Z
Fiber mode is the default.
Copper interfaces are disabled.
Fiber mode is the default.
Copper interfaces are disabled.
RGMII
TX_P_0:3
0x0
0x0
–
SerDes
TX_N_0:3
–
TX_FAULT_INT
RX_LOS_INT
High Z
High Z
High Z
0x1
Open-drain output, requires external pull-up.
Open-drain output, requires external pull-up.
Open-drain output, requires external pull-up.
–
Optical Module MOD_DEF_INT
I2C_CLK
I2C_DATA_0:3
0xF
Open-drain output, requires external pull-up.
NOTE: Z = High impedance.
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4.7
Power Supply Sequencing
Follow the power-up and power-down sequences described in this section to ensure correct
and analog supplies.
Caution: Failure to follow the sequence described in this section might damage the IXF1104 MAC.
4.7.1
Power-Up Sequence
Ensure that the 1.8 V analog and digital supplies are applied and stable prior to application of the
2.5 V analog and digital supplies.
4.7.2
Power-Down Sequence
Remove the 2.5 V supplies prior to removing the 1.8 V power supplies (the reverse of the power-up
sequence).
Caution: Damage can occur to the ESD structures within the analog I/Os if the 2.5 V digital and analog
supplies exceed the 1.8 V digital and analog supplies by more than 2.0 V during power-up or
power-down.
Figure 5. Power Supply Sequencing
2.5 V Supplies Stable
1.8 V Supplies Stable
Time
Sys_Res
AVDD2P5_1 and AVDD2P5_2
t=0
Apply VDD, AVDD1P8_1, and
Apply VDD4, VDD5,
AVDD1P8_2
NOTE: The 3.3 V supply (VDD2 and VDD3) can be applied at any point during this sequence.
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Table 19. Power Supply Sequencing
Time Delta to
Next Supply1
Power Supply
Power-Up Order
Notes
VDD, AVDD1P8_1,
AVDD1P8_2
First
0
1.8 V supplies
VDD4, VDD5,
AVDD2P5_1,
AVDD2P5_2
Second
10 µs
2.5 V supplies
1. The value of 10 µs given is a nominal value only. The exact time difference between the application of the 2.5 V analog
supply is determined by a number of factors, depending on the power management method used.
NOTE: To avoid damage to the IXF1104 MAC, the TXAV25 supply must not exceed the VDD supply by more
than 2 V at any time during the power-up or power-down sequence.
NOTE: The 3.3 V supply (VDD2 and VDD3) can be applied at any point during this sequence.
4.8
Pull-Up/Pull-Down Ball Guidelines
design for normal operation. Any balls marked as unused (NC) should be unconnected.
Table 20. Pull-Up/Pull-Down and Unused Ball Guidelines
Pin Name
Pull-Up/Pull-Down
Comments
TX_FAULT_INT
RX_LOS_INT
MOD_DEF_INT
TDI
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-down
Pull-up
Pull-up
Pull-up
Pull-up
4.7 k Ω to 2.5 V. Optical module signal with open-drain I/O.
4.7 k Ω to 2.5 V. Optical module signal with open-drain I/O.
4.7 k Ω to 2.5 V. Optical module signal with open-drain I/O.
10 k Ω to 3.3 V. JTAG test pin.
10 k Ω to 3.3 V. JTAG test pin.
10 k Ω to 3.3 V. JTAG test pin.
10 k Ω to 3.3 V. JTAG test pin.
10 k Ω to 3.3 V. JTAG test pin.
4.7 k Ω to 2.5 V
TDO
TMS
TCLK
TRST_L
MDIO
UPX_RDY_L
I2C_DATA_0:3
TX_DISABLE_0:3
4.7 k Ω to 3.3 V
4.7 k Ω to 2.5 V
4.7 k Ω to 2.5 V
4.9
Analog Power Filtering
balls.
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Figure 6. Analog Power Supply Filter Network
Table 21. Analog Power Balls
Ball
Designator
Signal Name
Comments
AVDD1P8_1
AVDD2P5_1
AVDD1P8_2
AVDD2P5_2
A5
AD20
AB16 T23
U14 R18
A20
R: AVDD1P8_1 and AVDD2P5_1 = 5.6 Ω resistor.
R: AVDD1P8_2 and AVDD2P5_2 = 1.0 Ω resistor.
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5.0
Functional Descriptions
5.1
Media Access Controller (MAC)
The IXF1104 MAC main functional block consists of four independent 10/100/1000 Mbps
Ethernet MACs, which support interfaces for fiber and copper connectivity.
• Copper Mode:
— RGMII for 10/100/1000 Mbps full-duplex operation and 10/100 Mbps half-duplex
operation
— GMII for 1000 Mbps full-duplex operation
• Fiber Mode:
— Integrated SerDes/OMI interface for direct connection to optical modules
— 1000 Mbps full-duplex operation in fiber mode
The following features support copper and fiber modes:
• Programmable Options:
— Automatic padding of transmitted packets that are less than the minimum frame size
— Broadcast, multicast, and unicast address filtering on frames received
— Filter and drop packets with errors
— Pre-padded RX frames with two bytes (aligns the Ethernet payload on SPI3 and in
network processor memories)
— Remove CRC from RX frames
— Append CRC to transmitted frames
• Performance Monitoring and Diagnostics:
— Loopback modes
— Detection of runt and overly large packets
— Cyclic Redundancy Check (CRC) calculation and error detection
— RMON statistics for dropped packets, packets with errors, etc.
• Compliant with IEEE Spec 802.3x standard for flow control
— Receive and execute PAUSE Command Frames
• Support for non-standard packet sizes up to 10 KB including loss-less flow control
Note: The IXF1104 MAC does not support 10/100 Mbps operation when configured in GMII mode.
The IXF1104 MAC is fully integrated, designed for use with Ethernet 802.3 frame types, and
compliant to all of the IEEE 802.3 MAC requirements.
The IXF1104 MAC adds preamble and Start-of-Frame Delimiter (SFD) to all frames sent to it
(transmit path) and removes preamble and SFD on all frames received by it (receive path). A CRC
check is also applied to all transmit and receive packets. CRC is optionally appended to transmit
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packets. CRC is removed optionally from receive packets after validation, and is not forwarded to
SPI3. Packets with a bad CRC are marked, counted in the statistics block, and may be optionally
dropped. A bad packet may be signaled with RERR on the SPI3 interface if it is not dropped.
The IXF1104 MAC operates only in full-duplex mode at 1000 Mbps rates on both SerDes and
GMII interface connections. The IXF1104 MAC is capable of operation at 1000 Mbps, full-duplex
in RGMII mode, and at full-duplex and half-duplex operation for 10/100 Mbps links.
5.1.1
Features for Fiber and Copper Mode
line-side interface.
5.1.1.1
Padding of Undersized Frames on Transmit
The padding feature allows Ethernet frames smaller than 64 bytes to be transferred from the SPI3
interface to the TX MAC and padded up to 64 bytes automatically by the MAC. This feature is
Note: When the user selects the padding function, the MAC core adds an automatically calculated CRC
to the end of the transmitted packet.
5.1.1.2
Automatic CRC Generation
Automatic CRC Generation is used in conjunction with the padding feature to generate and append
a correct CRC to any transmit frame. This feature is enabled by setting bit 6 of the “Diverse Config
5.1.1.3
Filtering of Receive Packets
This feature allows the IXF1104 MAC to filter receive packets under various conditions and drop
the packets through an interaction with the Receive FIFO control.
5.1.1.3.1 Filter on Unicast Packet Match
Any frame received in this mode that does not match the Station Address (MAC address) is marked
by the IXF1104 MAC to be dropped. The frame is dropped if the appropriate bit in the “RX FIFO
Errored Frame Drop Enable ($0x59F)" = 1. Otherwise, the frame is sent out the SPI3 interface and
may optionally be signaled with an RERR (see bit 0 in “SPI3 Receive Configuration ($0x701)” on
page 215).
out the SPI3 interface.
Note: The VLAN filter overrides the unicast filter. Therefore, a VLAN frame cannot be filtered based on
the unicast address.
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5.1.1.3.2 Filter on Multicast Packet Match
Any frame received in this mode that does not match the Port Multicast Address (reserved
multicast address recognized by IXF1104 MAC) is marked by the MAC to be dropped. The frame
Otherwise, the frame is sent out the SPI3 interface and may optionally be signaled with an RERR
sent out the SPI3 interface.
5.1.1.3.3 Filter Broadcast Packets
Any broadcast frame received in this mode is marked by the MAC to be dropped. The frame is
Otherwise, the frame is sent out the SPI3 interface and may optionally be signaled with an RERR
sent out the SPI3 interface.
5.1.1.3.4 Filter VLAN Packets
VLAN frames received in this mode are marked by the MAC to be dropped. The frame is dropped
VLAN frame is sent out the SPI3 interface and may optionally be signaled with an RERR (see bit 0
out the SPI3 interface.
5.1.1.3.5 Filter Pause Packets
Pause frames received in this mode are marked by the MAC to be dropped. The frame is dropped if
pause frame is sent out the SPI3 interface and may optionally be signaled with an RERR (see bit 0
out the SPI3 interface.
Note: Pause packets are not filtered if flow control is disabled in the “FC Enable ($ Port_Index + 0x12)”.
5.1.1.3.6 Filter CRC Error Packets
Frames received with an errored CRC are marked as bad frames and may optionally be dropped in
the RX FIFO. Otherwise, the frames are sent to the SPI3 interface and may be optionally signaled
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takes precedence over the other filter bits. Any packet (Pause, Unicast, Multicast or Broadcast
packet) with a CRC error will be marked as a bad frame when the CRC Error Pass Filter bit = 0.
Table 22. CRC Errored Packets Drop Enable Behavior
RX FIFO Errored-
CRC Error
Pass1
RERR
Frame Drop
Actions
Enable3
Enable2
When CRC Errored PASS = 1, CRC errored packets
are not filtered and are passed to the SPI3 interface.
They are not marked as bad, cannot be dropped, and
cannot be signaled with RERR.
1
x
x
Packets are marked as bad but not dropped in the
RX FIFO. These packets are sent to the SPI3
interface, and are signaled with an RERR to the
switch or Network Processor.
0
0
0
0
1
0
Packets are marked as bad but not dropped in the
RX FIFO. These packets are sent to the SPI3
interface, and are not signaled with an RERR.
CRC errored packets are marked as bad, dropped in
the RX FIFO, and never appear at the SPI3 interface.
NOTE: Packet sizes above the RX FIFO Transfer
cannot be dropped in the RX FIFO and are
passed to the SPI3 interface. These packets
can optionally be signaled with RERR on the
SPI3 interface if the RERR Enable bit = 1.
0
1
x
NOTE: x = “DON’T CARE”
5.1.1.4
5.1.2
69
CRC Error Detection
Frames received by the MAC are checked for a correct CRC. When an incorrect CRC is detected
on a received frame, the RX FCSError RMON statistic counter is incremented for each CRC
errored frame. Received frames with CRC errors may optionally be dropped in the RX FIFO (refer
SPI3 interface and may be dropped by the switch or system controller.
Frames transmitted by the MAC are also checked for correct CRC. When an incorrect CRC is
detected on a transmitted frame, the TX CRCError RMON statistic counter is incremented for each
incorrect frame.
Flow Control
Flow Control is an IEEE 802.3x-defined mechanism for one network node to request that its link
partner take a temporary “Pause” in packet transmission. This allows the requesting network node
to prevent FIFO overruns and dropped packets, by managing incoming traffic to fit its available
memory. The temporary pause allows the device to process packets already received or in transit,
thus freeing up the FIFO space allocated to those packets.
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
The IXF1104 MAC implements the IEEE 802.3x standard RX FIFO threshold-based Flow Control
in copper and fiber modes. When appropriately programmed, the MAC can both generate and
respond to IEEE standard pause frames in full-duplex operation. The IXF1104 MAC also supports
externally triggered flow control through the Transmit Pause Control interface.
In half-duplex operation, the MAC generates collisions instead of sending pause frames to manage
the incoming traffic from the link partner
5.1.2.1
802.3x Flow Control (Full-Duplex Operation)
The IEEE 802.3x standard identifies four options related to system flow control:
• No Pause
• Symmetric Pause (both directions)
• Asymmetric Pause (Receive direction only)
• Asymmetric Pause (Transmit direction only)
The IXF1104 supports all four options on a per-port basis. Bits 2:0 of the “FC Enable ($ Port_Index
+ 0x12)” on page 168 provide programmable control for enabling or disabling flow control in each
direction independently.
The IEEE 802.3x flow control mechanism is accomplished within the MAC sublayer, and is based
on RX FIFO thresholds called watermarks. The RX FIFO level rises and falls as packets are
received and processed. When the RX FIFO reaches a watermark (either exceeding a High or
dropping below a Low after exceeding a High), the IXF1104 control sublayer signals an internal
state machine to transmit a PAUSE frame. The FIFOs automatically generate PAUSE frames (also
called control frames) to initiate the following:
• Halt the link partner when the High watermark is reached.
• Restart the link partner when the data stored in the FIFO falls below the Low watermark.
Figure 7 illustrates the IEEE 802.3 FIFO flow control functions.
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Figure 7. Packet Buffering FIFO
MDI
SPI3 Interface
High Watermark
TX FIFO
TX Side
MAC
Data Flow
MAC Transfer Threshold
Low Watermark
High Watermark
Low Watermark
Data Flow
RX FIFO
RX Side
MAC
RX FIFO High
802.3 Flow
Control
TXPAUSEFR (External
Strobe)
802.3x Pause Frame Generation
B3231-01
5.1.2.1.1 Pause Frame Format
Figure 8. Ethernet Frame Format
Number of bytes
Note:
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Figure 9. PAUSE Frame Format
An IEEE 802.3 MAC PAUSE frame is identified by detecting all of the following:
• OpCode of 00-01
• Length/Type field of 88-08
• DA matching the unique multicast address (01-80-C2-00-00-01)
XOFF. A PAUSE frame informs the link partner to halt transmission for a specified length of time.
The PauseLength octets specify the duration of the no-transmit period. If this time is greater than
zero, the link partner must stop sending any further packets until this time has elapsed. This is
referred to as XOFF.
XON. The MAC continues to transmit PAUSE frames with the specified Pause Length as long as
the FIFO level exceeds the threshold. If the FIFO level falls below the threshold before the Pause
Length time expires, the MAC sends another PAUSE frame with the Pause Length time specified
as zero. This is referred to as XON and informs the link partner to resume normal transmission of
packets.
5.1.2.1.2 Pause Settings
The MAC must send PAUSE frames repeatedly to maintain the link partner in a Pause state. The
following two inter-related variables control this process:
• Pause Length is the amount of time, measured in multiples of 512 bit times, that the MAC
requests the link partner to halt transmission for.
• Pause Threshold is the amount of time, measured in multiples of 512 bit times, prior to the
expiration of the Pause Length that the MAC transmits another Pause frame to maintain the
link partner in the pause state.
The transmitted Pause Length in the IXF1104 MAC is set by the “FC TX Timer Value ($
The IXF1104 PAUSE frame transmission interval is set by the “Pause Threshold ($ Port_Index +
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5.1.2.1.3 Response to Received PAUSE Command Frames
When Flow Control is enabled in the receive direction (bit 0 in the “FC Enable ($ Port_Index +
0x12)"), the IXF1104 responds to PAUSE Command frames received from the link partner as
follows:
1. The IXF1104 checks the entire frame to verify that it is a valid PAUSE control frame
addressed to the Multicast Address 01-80-C2-00-00-01 (as specified in IEEE 802.3, Annex
31B) or has a Destinations Address matching the address programmed in the “Station Address
2. If the PAUSE frame is valid, the transmit side of the IXF1104 pauses for the required number
of PAUSE Quanta, as specified in IEEE 802.3, Clause 31.
3. PAUSE does not begin until completion of the frame currently being transmitted.
The IXF1104 response to valid received PAUSE frames is independent of the PAUSE frame filter
Note: Pause packets are not filtered if flow control is disabled in bit 0 of the “FC Enable ($ Port_Index +
5.1.2.1.4 Half-Duplex Operation
Transmit flow control is implemented only in half-duplex operation. Upon entering the flow
control state, the MAC generates a collision for all subsequent receive packets until exiting the
flow control state. Any receive packet in progress when the MAC enters the flow control state will
not be collided with but could be lost due if there is insufficient FIFO depth to complete packet
function.
5.1.2.1.5 Transmit Pause Control Interface
The Transmit Pause Control interface allows an external device to trigger the generation of pause
frames. The Transmit Pause Control interface is completely asynchronous. It consists of three
address signals (TXPAUSEADD[2:0]) and a strobe signal (TXPAUSEFR). The required address
for this interface operation is placed on the TXPAUSEADD[2:0] signals and the TXPAUSEFR is
pulsed High and returned Low. Refer to Figure 10 “Transmit Pause Control Interface” on page 74
control interface.
Control interface operation.
Note: There are two additional decodes provided that allow the user to generate either an XOFF frame or
XON frame from all ports simultaneously.
The default value of this register is 0x05E after reset is applied.
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Table 23. Valid Decodes for TXPAUSEADD[2:0]
TXPAUSEADD_2:0
Operation of TX Pause Control Interface
Transmits a PAUSE frame on every port with a pause_time = ZERO (XON)
(Cancels all previous pause commands).
0x0
Transmits a PAUSE frame on port 0 with pause_time equal to the value programmed
0x1
Transmits a PAUSE frame on port 1 with pause_time equal to the value programmed
0x2
Transmits a PAUSE frame on port 2 with pause_time equal to the value programmed
0x3
Transmits a PAUSE frame on port 3 with pause_time equal to the value programmed
0x4
Reserved. Do not use these addresses. The TX Pause Control interface will not
operate under these conditions.
0x5 to 0x6
0x7
Transmits a PAUSE frame on every port with pause_time equal to the value
Figure 10. Transmit Pause Control Interface
TXPAUSEFR
TXPAUSEADD0
TXPAUSEADD1
TXPAUSEADD2
This example shows the following conditions:
Strobe 1:
Port 0: Transmit Pause Packet (XOFF)
Strobe 2:
All Ports: Transmit Pause Packet with pause_time = 0 (XON)
Strobe 3:
Port 3: Transmit Pause Packet (XOFF)
B3234-01
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
5.1.3
Mixed-Mode Operation
The IXF1104 MAC gives the user the option of configuring each port for 10/100 Mbps half-duplex
copper, 10/100/1000 Mbps full-duplex copper, or 1000 Mbps full-duplex fiber operation. This
gives the IXF1104 MAC the ability to support both copper and fiber operation line-side interfaces
operating at the same time within a single device. (Refer to Figure 16 “Line Side Interface
The IXF1104 MAC provides complete flexibility in line-side connectivity by offering RGMII,
integrated SerDes, and GMII.
5.1.3.1
Configuration
The memory maps (Table 59 “MAC Control Registers ($ Port Index + Offset)” on page 156
into the following two distinct regions:
• Per-Port Registers
• Global Registers
To achieve a desired configuration for a given port, the relevant per-port registers must be
the operation of all ports, such as the SPI3 interface configuration.
summary of important configuration registers.
Note: The initialization sequence provided in Section 6.1, “Change Port Mode Initialization Sequence”
on page 130 must be followed for proper configuration of the IXF1104 MAC.
5.1.3.2
Key Configuration Registers
The following key registers select the operational mode of a given port:
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Table 24. Operational Mode Configuration Registers
Register
Address
Register Name
Description
0x002 – Port 0
0x082 – Port 1
0x102 – Port 2
0x182 – Port 3
whether a port is to be configured for full-duplex or half-duplex
operation.
NOTE: Half-duplex operation is only valid for 10/100 speeds where the
RGMII line interface has been selected.
“Desired Duplex
page 167 determines the MAC operational frequency and mode for a
given port.
($0x794)” on page 221 to 0x0 prior to any change in the
register value. This ensures that a change in the MAC clock
frequency is controlled correctly. If the “Clock and Interface
Mode Change Enable Ports 0 - 3 ($0x794)" is not used
correctly, the IXF1104 MAC may not be configured to the
proper mode.
“MAC IF Mode
and RGMII
Port_Index +
0x010 – Port 0
0x090 – Port 1
0x110 – Port 2
0x190 – Port 3
0x500
Bit 0 – Port 0
Bit 1 – Port 1
Bit 2 – Port 2
Bit 3 – Port 3
to 0x1 to enable a port. This should be the last step in the configuration
process for a port.
copper (RGMII or GMII) line-side interface an integrated SerDes fiber
line-side interface.
0x501
Bit 0 – Port 0
Bit 1 – Port 1
Bit 2 – Port 2
Bit 3 – Port 3
For copper operation for a given port, set the relevant bit to 0x1.
For fiber operation for a given port, set the relevant bit to 0x0.
NOTE: All ports are configured for fiber operation in the IXF1104 MAC
default mode of operation.
indicates to an internal clock generator when to sample the new value
“Interface Mode ($0x501)" (copper/fiber).
0x794
“Clock and
Interface Mode
Bit 0 – Port 0
Ports 0 - 3
When any of these two configuration values are changed for a port, the
corresponding bits must be kept in this register under reset by writing
0x0 to the relevant bit.
Bit 2 – Port 2
Bit 3 – Port 3
NOTE: The initialization sequence provided in Section 6.1, “Change Port Mode Initialization Sequence” on
page 130 must be followed for proper configuration of the IXF1104 MAC.
5.1.4
Fiber Mode
When the IXF1104 MAC is configured for fiber mode, the TX Data path from the MAC is an
internal
10-bit interface as described in the IEEE 802.3z specification. It is connected directly to an internal
SerDes block for serialization/deserialization and transmission/reception on the fiber medium to
and from the link partner.
The MAC contains all of the PCS (8B/10B encoding and 10B/8B decoding) required to encode and
decode the data. The MAC also supports auto-negotiation per the IEEE 802.3z specification via
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When configured for fiber mode, the full set of Optical Module interface control and status signals
is presented through re-use of GMII signals on a per-port basis (see Table 4.5 “Multiplexed Ball
Connections” on page 58). Fiber mode supports only full-duplex Gigabit operation.
5.1.4.1
Fiber Auto-Negotiation
performs hardware-defined auto-negotiation with the “TX Config Word ($ Port_Index + 0x17)"
Note: While the MAC supports auto-negotiation functions, the IXF1104 MAC does not automatically
configure the MAC or other device blocks to be consistent with the auto-negotiation results. This
configuration is done by the user and system software.
5.1.4.2
Determining If Link Is Established in Auto-Negotiation Mode
A valid link is established when the AN_complete bit is set and the RX_Sync bit reports that
synchronization has occurred. Both register bits are located in the “RX Config Word ($ Port_Index
If the link goes down after auto-negotiation is completed, RX_Sync indicates that a loss of
synchronization occurred. The IXF1104 MAC restarts auto-negotiation and attempts to reestablish
a link. Once a link is reestablished, the AN_complete bit is set and the RX_Sync bit shows that
synchronization has occurred.
(AN_enable) must be de-asserted, then re-asserted.
5.1.4.3
Fiber Forced Mode
The MAC fiber operation can be forced to operate at 1000 Mbps full-duplex without completion of
the auto-negotiation function. In this mode, the MAC RX path must achieve synchronization with
the link partner. Once achieved, the MAC TX path is enabled to allow data transmission. This
forced mode is limited to operation with a link partner that operates with a full-duplex link at
1000 Mbps.
5.1.4.4
5.1.5
Determination of Link Establishment in Forced Mode
When the IXF1104 MAC is in forced mode operation, the “RX Config Word ($ Port_Index +
0x16)” bit 20 RX Sync indicates when synchronization occurs and a valid link establishes.
Note: The RX Sync bit indicates a loss of synchronization when the link is down.
Copper Mode
In copper mode, the IXF1104 MAC transmits data on the egress path of the RGMII or GMII
interface, depending on the port configuration defined by the user. The copper MAC receives data
on the ingress path of the RGMII or GMII interface, depending on the port configuration defined
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by the user. The RGMII interface supports operation at 10/100/1000 Mbps when a full-duplex link
is established, and supports 10/100 Mbps when a half-duplex link is established. The GMII
interface only supports a 1000 Mbps full-duplex link.
5.1.5.1
Speed
The copper MAC supports 10 Mbps, 100 Mbps, and 1000 Mbps. All required speed adjustments,
clocks, etc., are supplied by the MAC. The operating speed of the MAC is programmable through
MAC speed setting must be programmed by the system software to match the speed of the attached
PHY for proper IXF1104 MAC operation.
Note: When the IXF1104 MAC is configured to use the GMII interface, the only mode of operation that
is supported is 1000 Mbps full-duplex.
If 10/100 Mbps operation is required in either full-duplex or half-duplex, the IXF1104 MAC must
be configured to use the RGMII interface.
5.1.5.2
5.1.5.3
Duplex
The MAC supports full-duplex or half-duplex depending on the line-side interface that is
IXF1104 MAC duplex setting must be programmed by the system software to match the attached
PHY duplex for proper IXF1104 MAC operation.
Copper Auto-Negotiation
In the copper MAC, auto-negotiation and all other controls of the PHY devices are achieved
through the MDIO interface, and are independent of the MAC controller. See Section 5.5, “MDIO
Control and Interface” on page 99 for further operation details.
Note: In copper mode, auto-negotiation is accomplished by the attached PHY, not the IXF1104 MAC.
Thus, the IXF1104 MAC does not automatically configure the MAC or other blocks in the device
to be consistent with attached PHY auto-negotiation results. This must be accomplished by the user
and system software.
5.1.6
Jumbo Packet Support
The IXF1104 MAC supports jumbo frames. The jumbo frame length is dependent on the
application and the IXF1104 MAC design is optimized for a 9.6 KB jumbo frame length. Larger
lengths can be programmed, but limited system performance may lead to data loss during certain
flow-control conditions
maximum length frame size the MAC can receive or transmit without activating any error counters,
and without truncation.
programmed into this register is 0x05EE (1518). The value is internally adjusted by +4 if the frame
has a VLAN tag. The overall programmable maximum is 0x3FFF or 16383 bytes.
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The register should be programmed to 0x2667 for the 9.6 KB length jumbo frame, optimized for
the IXF1104 MAC. The RMON counters are also implemented for jumbo frame support as
follows:
5.1.6.1
Rx Statistics
• RxOctetsTotalOK (Addr: Port_Index + 0x20)
• RxPkts1519toMaxOctets (Addr: Port_Index + 0x2B)
• RxFCSErrors (Addr: Port_Index + 0x2C)
• RxDatatError (Addr: Port_Index = 0x02E)
• RxAlignErrors (Addr: Port_Index + 0x2F)
• RxLongErrors (Addr: Port_Index + 0x30)
• RxJabberErrors (Addr: Port_Index + 0x31)
• RxVeryLongErrors (Addr: Port_Index + 0x34)
5.1.6.2
TX Statistics
• OctetsTransmittedOK (Addr: Port_Index + 0x40)
• TxPkts1519toMaxOctets (Addr: Port_Index + 0x4B)
• TxExcessiveLengthDrop (Addr: Port_Index + 0x53)
• TxCRCError (Addr: Port_Index + 0x56)
The IXF1104 MAC checks the CRC for all legal-length jumbo frames (frames between 1519 and
the Max Frame Size). On transmission, the MAC can be programmed to append the CRC to the
frame or check the CRC and increment the appropriate counter. On reception, the MAC transmits
these frames across the SPI3 interface (jumbo frames above the setting in the “RX FIFO Transfer
Threshold Port 0 ($0x5B8)” with a bad CRC cannot be dropped and are sent across the SPI3
interface). If the receive frame has a bad CRC, the appropriate counter is incremented and the
RxERR flag is asserted on the SPI3 receive interface.
Jumbo frames also impact flow control. The maximum frame size needs to be taken into account
when determining the FIFO watermarks. The current transmission must be completed before a
Pause frame is transmitted (needed when the receiver FIFO High watermark is exceeded). If the
current transmission is a jumbo frame, the delay may be significant and increase data loss due to
insufficient available FIFO space.
5.1.6.3
Loss-less Flow Control
The IXF1104 MAC supports loss-less flow control when the size of a Jumbo packet is restricted to
9.6 k bytes. If this condition is met, the IXF1104 MAC has sufficient memory resources allocated
to each MAC port to ensure that, if both the IXF1104 MAC and link partner are required to send
Pause packets simultaneously during jumbo packet transfers across a medium of five kilometers of
fiber, no packet data should be lost due to FIFO overflows.
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5.1.7
Packet Buffer Dimensions
5.1.7.1
TX and RX FIFO Operation
5.1.7.1.1 TX FIFO
The IXF1104 MAC TX FIFOs are implemented with 10 KB for each channel. This provides
enough space for at least one maximum size (10 KB) packet per-port storage and ensures that no
under-run conditions occur, assuming that the sending device can supply data at the required data
rate.
A transfer to MAC Threshold parameter, which is user-programmable, determines when the FIFO
signals to the MAC that it has data to send. This is configured for specific block sizes, and the user
must ensure that an under-run does not occur. Also, the threshold can be set above the maximum
size of a normal Ethernet packet. This causes the FIFO to send only data to the MAC when this
threshold is exceeded or when the End-of-Packet marker is received. This second condition
eliminates the possibility of under-run, except when the controlling switch device fails. It can,
however, cause idle times on the media.
5.1.7.1.2 RX FIFO
The IXF1104 MAC RX FIFOs are provisioned so that each port has its own 32 KB of memory
space. This is enough memory to ensure that there is never an over-run on any channel while
transferring normal Ethernet frame size data.
The FIFOs automatically generate Pause control frames to halt the link partner when the High
watermark is reached and to restart the link partner when the data stored in the FIFO falls below the
low-watermark. The RX and TX FIFOs have been sized to support lossless flow control with
9.6 KB packets. The RX FIFO has a programmable transfer threshold that sets the threshold at
which packets become “cut through” and starts transitioning to the SPI3 interface before the EOP
is received. Packets sizes below this threshold are treated as “store and forward.” Once a packet
size exceeds the RX FIFO transfer threshold, it can no longer be dropped by the RX FIFO even if it
is marked to be dropped by the MAC.
5.1.8
RMON Statistics Support
The IXF1104 MAC supplies RMON statistics through the CPU interface. These statistics are
available in the form of counter values that can be accessed at specific addresses in the register
counting from zero. A separate set of RMON statistics is available for each MAC device in the
IXF1104 MAC.
Implementation of the RMON Statistics block is similar to the functionality provided by existing
Intel switch and router products. This implementation allows the IXF1104 MAC to provide all of
the RMON Statistics group as defined by RFC2819. The IXF1104 MAC supports the RMON
registers supported by the IXF1104 MAC that are outside the scope of the RMON RFC2819
document.
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Table 25. RMON Additional Statistics (Sheet 1 of 2)
Definition of RMON
Versus
IXF1104 MAC
Documentation
RMON Ethernet Statistics
Group 1 Statistics
IXF1104 MAC-Equivalent
Statistics
Type
Type
etherStatsindex
Integer 32 NA
NA
NA
NA
NA
Object
NA
etherStatsDataSource
identifier
RX Number of Frames
Removed/
TX Number of Frames
Removed
Counter
32
etherStatsDropEvents
Counter 32 See table note 1
The IXF1104 MAC
has two counters for
receive and transmit
that use different
RxOctetsTotalOK
RxOctetsBad
naming conventions
Counter 32 for the total Octets
and Octets Bad.
Counter
32
etherStatsOctets
OctetsTransmittedOK
OctetsTransmittedBad
These counters must
be combined to meet
the RMON definition
for this statistic.
The IXF1104 MAC
has three counters
forthe etherStatsPkts
that must be
combined to give the
RxUCPkts/TxUCPkts
etherStatsPkts
Counter32 RxBCPkts/TxBCPkts
RxMCPkts/TxMCPkts
Counter 32
total packets as
defined by the
RMON specification.
Same as RMON
Counter 32
etherStatsBroadcastPkts
etherStatsMulticastPkts
Counter32 RxBCPkts/TxBCPkts
Counter32 RxMCPkts/TxMCPkts
specification
Counter 32 See table note 2
The IXF1104 MAC
has two counters for
the alignment and
CRC errors for the
RxAlignErrors
Counter32 RxFCSErrors
TxCRCError
RX side only.
etherStatsCRCAlignErrors
Counter 32
The IXF1104 MAC
has a CRC Error
counter for the TX
side.
The IXF1104 MAC
has two counters,
Counter 32 one for Runt errors
and one for
RxRuntErrors
Counter32 RxShortErrors
Rx Statistics ONLY
etherStatsUndersizedPkts
ShortErrors.
NOTE: The RMON specification requires that this is, “The total number of events where packets were dropped
by the probe due to a lack of resources. This number is not necessarily the number of packets dropped;
it is the number of times this condition is detected." The “RX FIFO Overflow Frame Drop Counter Ports
the IXF1104 MAC support this and increment when either an RX FIFO or TX FIFO overflows. If any
IXF1104 MAC programmable packet filtering is enabled, the “RX FIFO Errored Frame Drop Counter
increment with every frame removed in addition to the existing frames counted due to FIFO overflow.
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Table 25. RMON Additional Statistics (Sheet 2 of 2)
Definition of RMON
Versus
IXF1104 MAC
Documentation
RMON Ethernet Statistics
Group 1 Statistics
IXF1104 MAC-Equivalent
Statistics
Type
Type
RxLongErrors
Same as RMON
specification
etherStatsOversizePkts
Counter32
Counter 32
TxExcessiveLength Drop
Same as RMON
specification
etherStatsFragments
etherStatsJabbers
Counter32 RuntErrors
Counter32 JabberErrors
TxSingleCollision
Counter 32
Counter 32
Same as RMON
specification
The TxTotalCollision
count value is
equivalent to the
RMON specification
minus the
TxMultipleCollision
Counter32
etherStatsCollisions
Counter 32
TxLateCollision
TxTotalCollision
TxLateCollision
RxPkts64Octets/
Counter32
Same as RMON
specification
etherStatsPkts64Octets
Counter 32
Counter 32
Counter32
Counter32
Counter32
Counter32
TxPkts64Octets
RxPkts65to127Octets/
Counter32
Same a RMON
specification
etherStatsPkts65to127Octets
etherStatsPkts128to255Octets
etherStatsPkts256to511Octets
TxPkts65to127Octets
RxPkts128to255Octets/
Counter32
Same a RMON
specification
TxPkts128to255Octets
RxPkts256to511Octets/
Counter32
Same a RMON
specification
TxPkts256to511Octets
RxPkts512to1023Octets/
TxPkts512to1023Octets
Same a RMON
specification
etherStatsPkts512to1023Octets Counter32
etherStatsPkts1023to1518Octets Counter32
RxPkts1023to1518Octets/
TxPkts1023to1518Octets
Same as RMON
specification
Owner
etherStatOwner
String
NA
NA
NA
NA
NA
NA
Entry
etherStatsStatus
Status
NOTE: The RMON specification requires that this is, “The total number of events where packets were dropped
by the probe due to a lack of resources. This number is not necessarily the number of packets dropped;
it is the number of times this condition is detected." The “RX FIFO Overflow Frame Drop Counter Ports
0 - 3 ($0x594 – 0x597)" and “TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)" in
the IXF1104 MAC support this and increment when either an RX FIFO or TX FIFO overflows. If any
IXF1104 MAC programmable packet filtering is enabled, the “RX FIFO Errored Frame Drop Counter
Ports 0 - 3 ($0x5A2 - 0x5A5)" and “TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629)"
increment with every frame removed in addition to the existing frames counted due to FIFO overflow.
5.1.8.1
Conventions
The following conventions are used throughout the RMON Management Information Base (MIB)
and its companion documents.
• Good Packets: Error-free packets that have a valid frame length. For example, on Ethernet,
good packets are error-free packets that are between 64 and 1518 octets long. They follow the
form defined in IEEE 802.3, Section 3.2.
• Bad Packets: Bad packets are packets that have proper framing and recognized as packets, but
contain errors within the packet or have an invalid length. For example, on Ethernet, bad
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packets have a valid preamble and SFD, but have a bad CRC, or are either shorter than 64
octets or longer than 1518 octets.
5.1.8.2
Advantages
The following lists additional IXF1104 MAC registers that support features not documented in
RMON:
• MAC (flow) control frames
• VLAN Tagged
• Sequence Errors
• Symbol Errors
• CRC Error
These additional counters allow for differentiation beyond standard RMON probes.
Note: In fiber mode, a packet transfer with an invalid 10-bit symbol does not always update the statistics
registers correctly.
• Behavior: The IXF1104 MAC 8B10B decoder substitutes a valid code word octet in its place.
The packet transfer is aborted and marked as bad. The new internal length of the packet is
equal to the byte position where the invalid symbol was. No packet fragments are seen at the
next packet transfer.
• Issue: If the invalid 10-bit code is inserted in a byte position of 64 or greater, expected RX
statistics are reported. However, if the invalid code is inserted in a byte position of less than
64, expected RX statistics are not stored.
5.2
SPI3 Interface
The IXF1104 MAC SPI3 Interface is implemented to the System Packet Interface Level 3 (SPI3)
Physical Layer Interface standard. The interface function allows the IXF1104 MAC blocks to
interface to higher-layer network processors or switch fabric.
The IXF1104 MAC transmit interface allows data flows from a network processor or switch fabric
device to the IXF1104 MAC. The receive interface allows data to flow from the IXF1104 MAC to
the network processor or switch fabric device.
This interface receives and transmits data between the MAC and the Network Processor with
compliant SPI3 interfaces. The SPI3 interface operation is defined in the OIF-SPI3-01.0 (available
from the Optical Internet Working Forum [www.oiforum.com]). The OIF specification defines
operation for the transfer of data at data rates of up to 3.2 Gbps when operating at a frequency of
104 MHz. The IXF1104 MAC defines operation for the transfer of data at data rates of up to 4.256
Gbps when operating at a maximum frequency of 133 MHz in MPHY mode and 125 MHz in
SPHY Mode.
There is no guarantee of the number of bytes available since the size of packets is variable. An
IXF1104 MAC port-transmit packet available status is provided on signals DTPA, STPA or PTPA,
indicating the TX FIFO is nearly full.
In the receive direction, RVAL indicates if valid data is available on the receive data bus and is
defined so that data transfers can be aligned with packet boundaries.
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The SPI3 interface supports the following two modes of operation:
• MPHY or 32 bit mode (one 32-bit data bus)
• SPHY or 4 x 8 mode (four individual 8-bit data buses)
5.2.1
MPHY Operation
The MPHY operation mode is selected when bit 21 of the“SPI3 Transmit and Global Configuration
Data Path
The IXF1104 MAC SPI3 interface has a single 32-bit data path in the MPHY configuration mode
32-bit data bus would support only one IXF1104 MAC.
To support variable-length packets, the RMOD[1:0]/TMOD[1:0] signals are defined to specify
valid bytes in the 32-bit data bus structure. Each double-word must contain four valid bytes of
packet data until the last double-word of the packet transfer, which is marked with the end of
packet REOP/TEOP signal. This last double-word of the transfer contains up to four valid bytes
specified by the RMOD[1:0]/TMOD[1:0] signals.
The IXF1104 MAC port selection is performed using in-band addressing. In the transmit direction,
the network processor device selects an IXF1104 MAC port by sending the address on the
TDAT[1:0] bus marked with the TSX signal active and TENB signal inactive. All subsequent
TDAT[1:0] bus operations marked with the TSX signal inactive and the TENB active are packet
data for the specified port.
In the receive direction, the IXF1104 MAC specifies the selected port by sending the address on
the RDAT[1:0] bus marked with the RSX signal active and RVAL signal inactive. All subsequent
RDAT[1:0] bus operations marked with RSX inactive and RVAL active are packet data from the
specified port.
signals. The control signals with the port designator for Port 0 are the only ones used in MPHY
provides a comprehensive list of SPI3 signal descriptions.
5.2.1.1
SPI3 RX Round Robin Data Transmission
The IXF1104 MAC uses a round-robin protocol to service each of the 4 ports dependent upon the
enable status of the port and if there is data available to be taken from the RX FIFO. The round
robin order goes from port 0, port 1, port 2, port 3, and back to port 0. A port is skipped and the
next port is serviced if it has no available transmit data. The data transfer bursts are user-
configurable burst lengths of 64, 128, or 256 bytes. The IXF1104 MAC also has a configurable
pause interval between data transfer bursts on the receive side of the interface. The RX SPI3 burst
5.2.2
MPHY Logical Timing
The SPI3 interface AC timing for MPHY can be found in Section 7.2, “SPI3 AC Timing
Specifications” on page 137. Logical timing in the following diagrams illustrates all signals
associated with MPHY mode.
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5.2.2.1
Transmit Timing
In MPHY mode a packet transmission starts with the TSX signal indicating port address
information is on the data bus. The next clock cycle TENB and TSOP indicate present data on the
bus is the first word in the packet and all subsequent clocks will contain valid data as long as TENB
is active or until TEOP is asserted. Data transmission can be temporally halted when TENB goes
high then resumed when TENB is low. The valid bytes in the final word, during an active TEOP,
are indicated by state of TMOD [1:0].
Figure 11. MPHY Transmit Logical Timing
TFCLK
TENB
TSOP
TEOP
TMOD
[1:0]
TERR
TSX
TDAT
[31:0]
0000
B0-B3
B4-B7
B44-B47 B48-B51 B52-B55
B56-B59 B60-B64 0001
B0-B3
B4-B7
TPRTY
B3216-02
1. Applies to all transmit packet available signals (STPA, PTPA, DTPA_0:3).
5.2.2.2
Receive Timing
A packet is received when RSX indicates port address information on the data bus followed by
RSOP to indicate the data bus contains the first word of a packet. All subsequent data is valid only
while RVAL is High and until REOP is asserted. Receive data can be temporarily halted when
RENB is de-asserted and starts again on the second rising edge of RFCLK following the assertion
of RENB. RMOD indicates the number of valid bytes in the last transfer when REOP is asserted.
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Figure 12. MPHY Receive Logical Timing
Figure 13. MPHY 32-Bit Interface
SPI3 Bus
Network Processor
IXF1104 MPHY
Mode
Line-Side Interface
TFCLK
TENB
TFCLK
Transceiver
TENB_0
Port 0
TDAT[31:0]
TMOD[1:0]
TPRTY
TDAT[31:0]
TMOD[1:0]
TPRTY_0
TSOP_0
TSOP
TEOP
TEOP_0
Transceiver
Port 1
TERR
TSX
TERR_0
TSX
DTPA_0:3
STPA
DTPA_0:3
STPA
Transceiver
PTPA
TADR[1:0]
PTPA
TADR[1:0]
Port 2
RFCLK
RENB
RFCLK
RENB_0
RDAT[31:0]
RMOD[1:0]
RDAT[31:0]
RMOD[1:0]
Transceiver
Port 3
RPRTY
RVAL
RSOP
REOP
RPRTY_0
RVAL_0
RSOP_0
REOP_0
RERR
RSX
RERR_0
RSX
B0660-02
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5.2.2.3
Clock Rates
In MPHY mode, the TFCLK and RFCLK can be independent of each other. TFCLK and RFCLK
should be common to the IXF1104 MAC and the Network Processor. The IXF1104 MAC requires
a single clock source for the transmit path and a single clock source for the receive path.
To allow all four IXF1104 MAC ports to operate at 1 Gbps, the IXF1104 MAC is designed to allow
this interface to be overclocked. This allows operation for data transfer at data rates of up to 4.256
Gbps when operating at an overclocked frequency of 133 MHz.
Note: MPHY mode operates at a maximum clock frequency of 133 MHz (TFCLK and RFCLK).
5.2.2.4
Parity
The IXF1104 MAC can be odd or even (the IXF1104 MAC is odd by default) when calculating
parity on the data bus. This can be changed to accommodate even parity if desired, and can be set
for transmit and receive independently. The RX Parity is set in bit 12 of the “SPI3 Receive
5.2.2.5
SPHY Mode
The SPHY operation mode is selected when bit 21 of the Table 146 “SPI3 Transmit and Global
Configuration ($0x700)” on page 213 is set to 1. The SPHY mode is the default operation for the
IXF1104 MAC SPI3 interface.
5.2.2.5.1 Data Path
The IXF1104 MAC SPI3 interface has four 8-bit data paths that can support four independent 8-bit
dedicated 8-bit SPI3 data bus, each port has it own status signal (unlike MPHY). See the For a
detailed list of all the signals refer to the SPI3 pin multiplexing table....
Furthermore since each port has it own dedicated bus the in band port addressing is not needed.
The 8 bit data bus eliminates the need to have separate control signals determine the number of
valid bytes on an EOP.Therefore TSX, RSX, TMOD[1:0] RMOD[1:0] are not used in SPHY mode.
signals. Unlike MPHY mode, each port has a dedicated control signal associated with each of the
descriptions for all SPI3 signals.
5.2.2.5.2 Receive Data Transmission
Packets are transmitted on each port as they become available from the RX FIFO. The burst length
is determined by the setting of per port burst size and the B2B pause settings in the “SPI3 Receive
Configuration ($0x701)". If the B2B pause setting is zero pause cycles inserted, then the entire
packet will be burst without any pauses unless the Network Processor de-asserts RENB. If the
B2B_Pause setting calls for the insertion of two pause cycles on a port, these are inserted after each
data burst for that port. The data bursts are user configurable for each port in the “SPI3 Receive
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5.2.2.6
SPHY Logical Timing
SPI3 interface AC timing for SPHY can be found in Section 7.2, “SPI3 AC Timing Specifications”
on page 137. Logical timing in the following diagrams illustrates all signals associated with SPHY
mode. SPHY mode is similar to MPHY mode except the following signals are not used:
• TMOD[1:0]
• RMOD[1:0]
• TSX
• RSX
• Address Data appearing on the data bus
5.2.2.7
Transmit Timing (SPHY)
Packet transmission starts when TENB and TSOP indicate present data on the bus is the first word
in the packet. All subsequent clocks will contain valid data as long as TENB is active or until
TEOP is asserted. Data transmission can be temporally halted when TENB goes high then resumed
when TENB is low.
Figure 14. SPHY Transmit Logical Timing
TFCLK
TENB
TSOP
TEOP
TERR
TDAT
B0
B1
B59
B60
B61
B62
B63
B0
B1
B2
[7:0]
TPRTY
B3249-02
5.2.2.8
Receive Timing (SPHY)
A packet is received when RSOP is asserted to indicate the data bus contains the first word of the
packet. All subsequent data is valid only while RVAL is high and until REOP is asserted. Receive
data can be temporarily halted when RENB is de-asserted and starts again on the second rising
edge of RFCLK following the assertion of RENB. When REOP is asserted RMOD indicates the
number of valid bytes in the last transfer.
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Figure 16. SPHY Connection for Two Intel® IXF1104 MAC Ports (8-Bit Interface)
SPI3 Bus
Intel® IXF1104
Network Processor
Port 0
TFCLK
TENB[0]
TFCLK
TENB_0
TDAT[7:0]_0
TPRTY_0
TSOP_0
TEOP_0
TDAT[7:0][0]
TPRTY[0]
TSOP[0]
TEOP[0]
TERR[0]
TERR_0
DTPA[0]
DTPA_0
Line-Side
Interface
Transceiver
Port 0
RFCLK
RFCLK
RENB[0]
RENB_0
RDAT[7:0][0]
RPRTY[0]
RVAL[0]
RDAT[7:0]_0
RPRTY_0
RVAL_0
RSOP[0]
REOP[0]
RERR[0]
RSOP_0
REOP_0
RERR_0
SPI3
Flow Control
PTPA
TADR[1:0]
PTPA
TADR[1:0]
Port 1
TFCLK
TFCLK
TENB[1]
TENB_1
TDAT[7:0]_1
TPRTY_1
TSOP_1
TEOP_1
TDAT[7:0][1]
TPRTY[1]
TSOP[1]
TEOP[1]
TERR_1
DTPA_1
TERR[1]
DTPA[1]
Line-Side
Interface
Transceiver
Port 1
RFCLK
RFCLK
RENB[1]
RENB_1
RDAT[7:0]_1
RPRTY_1
RDAT[7:0][1]
RPRTY[1]
RVAL[1]
RVAL_1
RSOP_1
REOP_1
RERR_1
RSOP[1]
REOP[1]
RERR[1]
B0659-02
5.2.2.8.1 Clock Rates
The TFCLK and RFCLK can be independent of each other in SPHY mode operation. TFCLK and
RFCLK should be common to all the Network Processor devices. The IXF1104 MAC requires an
individual single clock source for the device transmit path and a single clock source for the device
receive path.
The IXF1104 MAC allows this interface to be overclocked so that all four IXF1104 MAC ports can
operate at 1 Gbps. This allows data transfer at data rates of up to 4.0 Gbps when operating at an
overclocked frequency of 125 MHz.
Note: SPHY operates at a maximum frequency of 125 MHz.
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
5.2.2.8.2 Parity
The IXF1104 MAC can be odd or even (the IXF1104 MAC defaults to odd) when calculating
parity on the data bus. This can be changed to accommodate even parity if desired, and can be set
for transmit and receive ports independently. The RX and TX parity sense bits have a direct
relationship to the port parity in SPHY mode.
5.2.2.9
SPI3 Flow Control
The SPI3 packet interface supports transmit and receive data transfers at clock rates independent of
the line bit rate. As a result, the IXF1104 MAC supports packet rate decoupling using internal
FIFOs. These FIFOs are 10 KB per port in the transmit direction (egress from the IXF1104 MAC
to the line interfaces) and 32 KB per port in the receive direction (ingress to the IXF1104 MAC
from the line interfaces).
Control signals are provided to the network processor and the IXF1104 MAC to allow either one to
exercise flow control. Since the bus interface is point-to-point, the receive interface of the
IXF1104 MAC pushes data to the link-layer device. For the transmit interface, the packet available
status granularity is byte-based.
5.2.2.9.1 RX SPI3 Flow Control
In the receive direction, when the IXF1104 MAC has stored an end-of-packet (a complete small
packet or the end of a larger packet) or some predefined number of bytes in its receive FIFO, it
sends the in-band address followed by FIFO data to the link-layer device (in MPHY mode). The
data on the interface bus is marked with the valid signal (RVAL) asserted. The network processor
device can pause the data flow by de-asserting the Receive Read Enable (RENB) signal.
RENB_0:3
RENB_0:3 controls the flow of data from the IXF1104 MAC RX FIFOs. In SPHY mode, there is a
dedicated RENB for each port. In MPHY mode, RENB_0 is used as the global signal covering all
ports. When RENB is sampled Low, the network processor can accept data. A read is performed
from the RX FIFO and the RDAT, RPRTY, RMOD[1:0], RSOP, REOP, RERR, RSX, and RVAL
signals are updated on the following rising edge of RFCLK.
RENB can be asserted High by the Network Processor at any time if it is unable to accept any more
data. When the RENB is sampled High by the IXF1104 MAC, a read of the RX FIFO is not
performed, and the RDAT, RPRTY, RMOD[1:0], RSOP, REOP, RERR, RSX and RVAL signals
remain unchanged on the following rising edge of RFCLK.
5.2.2.9.2 TX SPI3 Flow Control
In the transmit direction, when the IXF1104 MAC has space for some predefined number of bytes
in its transmit FIFO, it informs the Network Processor device by asserting one of the Transmit
Packet Available (TPA) signals. The Network Processor device writes the in-band address followed
by packet data to the IXF1104 MAC using an enable signal (TENB). The network processor device
monitors the TPA signals for a High-to-Low transition, which indicates that the transmit FIFO is
almost full (the number of bytes left in the FIFO is user-selectable by setting the “TX FIFO High
Watermark Ports 0 - 3 ($0x600 – 0x603)", and suspends data transfer to avoid an overflow. The
Network Processor device can pause the data flow by de-asserting the enable signal (TENB).
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
The IXF1104 MAC provides the following three types of TPA signals:
• Dedicated per port Direct Transmit Packet Available (DTPA)
• Selected-PHY Transmit Packet Available (STPA), which is based on the current in-band port
address in MPHY mode.
• Polled-PHY Transmit packet Available (PTPA), which provides FIFO information on the port
selected by the TADR[1:0] signals.
The following three TPA signals (DTPA_0:3, STPA, and PTPA) provide flow control based on the
Register Ports 0 - 3 ($0x60A – 0x60D)” on page 204 for more information.
DTPA_0:3:
A direct status indication for the TX FIFOs of ports [0:3]. When DTPA is High, it indicates the
amount of data in the TX FIFO is below the TX FIFO High watermark. When the High watermark
is crossed, DTPA transitions Low to indicate the TX FIFO is almost full. It stays low until the
amount data in the TX FIFO goes back below the TX FIFO Low watermark. At this point, DTPA
transitions High to indicate the programmed number of bytes are now available for data transfers.
DTPA_0:3 is updated on the rising edge of the TFCLK.
STPA:
STPA provides TX FIFO status for the currently selected port in MPHY mode. When High, STPA
indicates that the amount of data in the TX FIFO for the port selected, specified by the latest in-
band address, is below the TX FIFO High watermark. When the High watermark is crossed, STPA
transitions Low to indicate the TX FIFO is almost full. It stays Low until the amount of data in the
TX FIFO goes back below the TX FIFO Low watermark. At this point, STPA transitions High to
indicate the programmed number of bytes are now available for data transfers.
The port reported by STPA is updated on the rising edge of TFCLK after TSX is sampled as
asserted. STPA is updated on the rising edge of TFCLK.
Note: STPA is only used when the IXF1104 MAC is configured for MPHY mode of operation.
PTPA:
PTPA provides status of the TX FIFO based on the port selected by the TADR[1:0] address bus.
When High, PTPA indicates that the amount of data in the TX FIFO for the port selected is below
the TX FIFO High watermark. When the High watermark is crossed, PTPA transitions Low to
indicate the TX FIFO is almost full. It stays Low until the amount of data in the TX FIFO goes
back below the TX FIFO Low watermark. PTPA then transitions High to indicate the programmed
number of bytes are now available for data transfers.
The port reported by PTPA is updated on the rising edge of TFCLK after the TADR{1:0] port
address is sampled.
PTPA is updated on the rising edge of TFCLK.
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
5.2.3
Pre-Pending Function
The IXF1104 MAC implements a pre-pending feature to allow 1518-byte Ethernet packets to be
pre-padded with two additional bytes of data so that the packet becomes low-word aligned. The
2-byte pre-pend value is all zeros and is inserted before the destination address of the packet being
pre-pended. This value is fixed and cannot be changed.
This function is enabled by writing the appropriate data to the “RX FIFO Padding and CRC Strip
Enable ($0x5B3)" for each port.
A standard 1518-byte Ethernet packet occupies 379 long words (four bytes) with two additional
bytes left over (1518/4 = 379.5). To eliminate the memory-management problems for a network
processor or switch fabric, the two remaining bytes are dealt with by the addition of two bytes to
the start of a packet. This results in a standard 1518-byte Ethernet packet received by the IXF1104
MAC being forwarded to the higher-layer device as a 380-long-word packet. The upper-layer
device is responsible for stripping the additional two bytes.
This feature was added to the IXF1104 MAC to assist in the design of higher-layer memory
management. The addition of the two extra bytes is not the default operation of the IXF1104 MAC
and must be enabled by the user. The default operation of the IXF1104 MAC SPI3 receive interface
forwards data exactly as it is received by the IXF1104 MAC line interface.
5.3
Gigabit Media Independent Interface (GMII)
The IXF1104 MAC supports a subset of the GMII interface standard as defined in IEEE 802.3
2000 Edition for 1 Gbps operation only. This subset is limited to operation at 1000 Mbps full-
duplex.
The GMII Interface operates as a source synchronous interface only and does not accept a TXC
clock provided by a PHY device when operating at 10/100 Mbps speeds.
Note: The RGMII interface must be used for applications that require 10/100/1000 Mbps operation.
The IXF1104 MAC does NOT support 10/100 Mbps copper PHY devices that are implemented
using the MII Interface.
Note: MII operation is not supported by the IXF1104 MAC.
The user can select GMII, RGMII, or Optical Module/SerDes functionality on a per-port basis.
This mode of operation is controlled through a configuration register.
While IEEE 802.3 specifies 3.3 V operation of GMII devices, most PHYs use 2.5 V signaling. The
IXF1104 MAC provides a 2.5 V drive and is 3.3 V-tolerant on inputs.
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Figure 17. MAC GMII Interconnect
TXC_3:0
TXD[7:0]_0
TXD[7:0]_1
TXD[7:0]_2
TXD[7:0]_3
TX_EN_3:0
TX_ER_3:0
TXC_3:0
TXD[7:0]_0
TXD[7:0]_1
TXD[7:0]_2
TXD[7:0]_3
TX_EN_3:0
TX_ER_3:0
RXC_3:0
RXD[7:0]_0
RXD[7:0]_1
RXD[7:0]_2
RXD[7:0]_3
RX_EN_3:0
RX_ER_3:0
CRS_3:0
RXC_3:0
RXD[7:0]_0
RXD[7:0]_1
RXD[7:0]_2
RXD[7:0]_3
RX_EN_3:0
RX_ER_3:0
CRS_3:0
COL_3:0
COL_3:0
B3203-01
5.3.1
5.3.2
GMII Signal Multiplexing
Interface Multiplexed Balls” on page 58 specifies the multiplexing of GMII balls in these modes.
MAC in GMII mode.
GMII Interface Signal Definition
definitions. For information on 1000BASE-T GMII transmit and receive timing diagrams and
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Table 26. GMII Interface Signal Definitions
IXF1104 MAC
Signal
GMII Standard
Signal
Source
Description
TXC_0
TXC_1
TXC_2
TXC_3
Transmit Reference Clock:
IXF1104
MAC
125 MHz for Gigabit operation.
GTX_CLK
TXD[7:0]
TX_EN
MII operation for 10/100 Mbps operation is not
supported.
TXD[7:0]_0
TXD[7:0]_1
TXD[7:0]_2
TXD[7:0]_3
Transmit Data Bus:
IXF1104
MAC
Width of this synchronous output bus varies with the
speed/mode of operation. In 1000 Mbps mode, all 8
bits are used.
TX_EN_0
TX_EN_1
TX_EN_2
TX_EN_3
Transmit Enable:
IXF1104
MAC
Synchronous input that indicates Valid data is being
driven on the TXD[7:0] data bus.
TX_ER_0
TX_ER_1
TX_ER_2
TX_ER_3
Transmit Error:
IXF1104
MAC
TX_ER
Synchronous input to PHY causes the transmission of
error symbols in 1000 Mbps links.
RXC_0
RXC_1
RXC_2
RXC_3
Receive Clock:
RX_CLK
PHY
PHY
Continuous reference clock is 125 MHz +/– 100 ppm.
Receive Data Bus:
RXD[7:0]_0
RXD[7:0]_1
RXD[7:0]_2
RXD[7:0]_3
Width of the bus varies with the speed and mode of
operation. In 1000 Mbps mode, all 8 bits are driven by
the PHY device.
RXD<3:0>
Note: MII operation at 10/100 Mbps is not supported.
RX_DV_0
RX_DV_1
RX_DV_2
RX_DV_3
Receive Data Valid:
RX_DV
RX_ER
CRS
PHY
PHY
PHY
PHY
This signal is asserted when valid data is present on
the corresponding RXD bus.
RX_ER_0
RX_ER_1
RX_ER_2
RX_ER_3
Receive Error:
In 1000 Mbps mode, asserted when error symbols or
carrier extension symbols are received.
Always synchronous to RX_CLK.
CRS_0
CRS_1
CRS_2
CRS_3
Carrier Sense:
Asserted when valid activity is detected at the line-
side interface.
COL_0
COL_1
COL_2
COL_3
Collision:
Asserted when a collision is detected and remains
asserted for the duration of the collision event. In full-
duplex mode, the PHY should force this signal Low.
COL
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
5.4
Reduced Gigabit Media Independent Interface (RGMII)
The IXF1104 MAC supports the RGMII interface standard as defined in the RGMII Version 1.2
specification. The RGMII interface is an alternative to the IEEE 802.3u MII interface.
The RGMII interface is intended as an alternative to the IEEE 802.3u MII and the IEEE 802.3z
GMII. The principle objective of the RGMII is to reduce the number of balls (from a maximum of
28 balls to 12 balls) required to interconnect the MAC and the PHY. This reduction is both cost-
effective and technology-independent. To accomplish this objective, the data paths and all
associated control signals are reduced, control signals are multiplexed together, and both edges of
the clock are used.
• 1000 Mbps operation – clocks operate at 125 MHz
• 100 Mbps operation – clocks operate at 25 MHz
• 10 Mbps operation – clocks operate at 2.5 MHz.
Note: The IXF1104 MAC RGMII interface is multiplexed with signals from the GMII interface. See
Figure 18. RGMII Interface
TXC_3:0
TXD[3:0]_3
TXD[3:0]_2
TXD[3:0]_1
TXD[3:0]_0
TX_CTL_3:0
TXC_3:0
TXD[3:0]_3
TXD[3:0]_2
TXD[3:0]_1
TXD[3:0]_0
TX_CTL_3:0
RXC_3:0
RXD[3:0]_3
RXD[3:0]_2
RXD[3:0]_1
RXD[3:0]_0
RX_CTL_3:0
RXC_3:0
RXD[3:0]_3
RXD[3:0]_2
RXD[3:0]_1
RXD[3:0]_0
RX_CTL_3:0
B3203-01
5.4.1
Multiplexing of Data and Control
Multiplexing of data and control information is achieved by utilizing both edges of the reference
clocks and sending the lower four bits on the rising edge and the upper four bits on the falling edge.
Control signals are multiplexed into a single clock cycle using the same technique. For further
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
5.4.2
5.4.3
Timing Specifics
timing specifics.
TX_ER and RX_ER Coding
To reduce interface power, the transmit error condition (TX_ER) and the receive error condition
(RX_ER) are encoded on the RGMII interface to minimize transitions during normal network
definitions for RGMII.
Table 27. RGMII Signal Definitions
RGMII
Standard Source
Signal
IXF1104
MAC Signal
Description
Depending on speed, the transmit reference clock is 125 MHz, 25
MHz, or 2.5 MHz +/– 50ppm.
TXC_0:3
TXC
MAC
MAC
Contains register bits 3:0 on the rising edge of TXC and register bits
7:4 on the falling edge of TXC.
TD[3:0]_n
TD<3:0>
TXEN is on the leading edge of TXC.
TX_EN
TX_CTL
MAC
TX_EN xor TX_ER is on the falling edge of TXC.
Continuous reference clock is 125 MHz, 25 MHz, or 2.5 MHz +/– 50
ppm.
RXC_0:3
RXC
PHY
PHY
Contains register bits 3:0 on the leading edge of RXC and register bits
7:4 on the trailing edge of RXC.
RD[3:0]_n
RD<3:0>
RX_DV is on the leading edge of RXC.
RX_DV
RX_CTL
PHY
RX_DV or RXERR is the falling edge of RXC.
The value of RGMII_TX_ER and RGMII_TX_EN are valid at the rising edge of the clock while
TX_ER is presented on the falling edge of the clock. RX_ER coding behaves in the same way (see
Table 28. TX_ER and RX_ER Coding Description
Condition
Description
RX_ER = false
Receiving valid frame,
no errors
RX_DV = true
Logic High on rising edge of RXC
Logic High on the falling edge of RXC
Receiving valid frame,
with errors
RX_DV = true
Logic High on rising edge of RXC
RX_ER = true
Logic Low on the falling edge of RXC
Receiving invalid frame
(or no frame)
RX_DV = false
Logic Low on rising edge of RXC
RX_ER = false
Logic Low on the falling edge of RXC
TX_EN = true
TX_ER =false
Transmitting valid frame,
no errors
Logic High on rising edge of TXC
Logic High on the falling edge of TXC
TX_EN = true
TX_ER = true
Transmitting valid frame
with errors
Logic High on rising edge of TXC
Logic Low on the falling edge of TXC
TX_EN = false
TX_ER = false
Transmitting invalid
frame (or no frame)
Logic Low on rising edge of TXC
Logic low on the falling edge of TXC
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Figure 19. TX_CTL Behavior
Valid Frame
TXC_0:3
(at Transmitter)
TD[3:0]
TD[7:4]
TD[3:0]_0:3
TX_CTL_0:3
TX_EN=True TX_ER=False
End-of-Frame
TX_EN=False TX_ER=False
Frame with Error
TXC_0:3
(at Transmitter)
TD[3:0]
TD[7:4]
TD[3:0]_0:3
TX_CTL_0:3
TX_EN=True TX_ER=False
TX_EN=False TX_ER=False
End-of-Frame
B0616-02
Figure 20. RX_CTL Behavior
Valid Frame
RXC_0:3
(at PHY)
RD[3:0]
RD[7:4]
RD[3:0]_0:3
RX_CTL_0:3
RX_DV=True RX_ER=False
RX_DV=False RX_ER=False
End-of-Frame
Frame with Error
RXC_0:3
(at PHY)
RD[3:0]
RD[7:4]
RD[3:0]_0:3
RX_CTL_0:3
RX_DV=True RX_ER=True
RX_DV=False RX_ER=False
End-of-Frame
B3237-01
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
5.4.3.1
In-Band Status
Carrier Sense (CRS) is generated by the PHY when a packet is received from the network
interface. CRS is indicated when:
• RXDV = true.
• RXDV = false, RXERR = true, and a value of FF exists on the RXD[7:0] bits simultaneously.
• Carrier Extend, Carrier Extend Error, or False Carrier occurs (please reference the Hewlett-
Packard* Version 1.2a RGMII Specification for details.).
Carrier Extend and Carrier Extend Error are applicable to Gigabit speeds only. Collision is
determined at the MAC by the assertion of TXEN being true while either CRS or RXDV are true.
The PHY will not assert CRS as a result of TXEN being true.
5.4.4
10/100 Mbps Functionality
The RGMII interface implements the 10/100 Mbps Ethernet Media Independent Interface (MII) by
reducing the clock rate to 25 MHz for 100 Mbps operation and 2.5 MHz for 10 Mbps. The TXC is
generated by the MAC and the RXC is generated by the PHY. During packet reception, the RXC is
stretched on either the positive or negative pulse to accommodate transition from the free-running
clock to a data-synchronous clock domain. When the speed of the PHY changes, a similar
stretching of the positive or negative pulses is allowed. No glitching of the clocks is allowed during
speed transitions.
This interface operates at 10 Mbps and 100 Mbps speeds in the same manner as 1000 Mbps speed,
although the data may be duplicated on the falling edge of the appropriate clock. The MAC holds
TX_CTL Low until it is operating at the same speed as the PHY.
Note: The IXF1104 MAC does not support 10/100 Mbps operation when configured in GMII mode
5.5
MDIO Control and Interface
The IXF1104 MAC supports the IEEE 802.3 MII Management Interface, also known as the
Management Data Input/Output (MDIO) Interface. This interface allows the IXF1104 MAC to
monitor and control each of the PHY devices that are connected to the four ports of IXF1104 MAC
when those ports are in copper mode.
The MDIO Master Interface block is implemented once in the IXF1104 MAC. The MDIO
Interface block contains the logic through which the user accesses the registers in PHY devices
connected to the MDIO/MDC interface, which is controlled by each port.
The MDIO Master Interface block supports the management frame format, specified by IEEE
802.3, clause 22.2.4.5. This block also supports single MDI access through the CPU interface and
an autoscan mode. Autoscan allows the IXF1104 MAC MDIO master to read all 32 registers of the
per-port copper PHYs and store the contents in the IXF1104 MAC. This provides external-CPU-
ready access to the PHY register contents through a single CPU read without the latency of waiting
on the low-speed serial MDIO data bus for each register access.
Scan of a single register with low-frequency operation takes approximately 25.6 µs. Scan of a 32-
register block takes approximately 820 µs, or 3.3 ms for all four ports. Autoscan data is not valid
until approximately 19.2 µs after enabling scan. These numbers scale by 7/50 for high-frequency
operation.
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
5.5.1
5.5.2
MDIO Address
The 5-bit PHY address for the MDIO transactions can be set in the “MDIO Single Command
($0x680)". Bits 5:2 of the PHY address are fixed to a value of 0. Bits 1 and 0 are programmable in
MDIO Register Descriptions
For complete information on the MDI registers, refer to the Table 142 “MDIO Single Command
5.5.3
Clear When Done
completion and is set by the user to start the requested single MDIO Read or Write operation. This
bit is cleared automatically upon operation completion.
5.5.4
MDC Generation
The MDC clock is used for the MDIO/MDC interface. The frequency of the MDC clock is
selectable by setting bit 0, MDC Speed, in an IXF1104 MAC configuration register (see Table 145
5.5.4.1
MDC High-Frequency Operation
The high-frequency MDC is 18 MHz, derived from the 125-MHz system clock by dividing the
frequency by 7.
The duty cycle is as follows:
• MDC High duration: 3 x (1/125 MHz) = 3 x 8 ns = 24 ns
• MDC Low duration: 4 x (1/125 MHz) = 4 x 8 ns = 32 ns
• MDC runs continuously after reset
MDC timing diagram.
5.5.4.2
MDC Low-Frequency Operation
The low-frequency MDC is 2.5 MHz, which is derived from the 125-MHz system clock by
dividing the frequency by 50.
The duty cycle is as follows:
• MDC High duration: 25 x (1/125 MHz) = 25 x 8 ns = 200 ns
• MDC Low duration: 25 x (1/125 MHz) = 25 x 8 ns = 200 ns
• MDC runs continuously after reset
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
timing diagram.
5.5.5
Management Frames
The Management Interface serializes the external register access information into the format
Figure 21. Management Frame Structure (Single-Frame Format)
Start
2 Bits
Op Code PHY Addr REG Addr Turnaround
2 Bits 5 Bits 5 Bits 2 Bits
Data
16 Bits
Preamble
32 Bits
First Bit Transmitted
Last Bit Transmitted
5.5.6
Single MDI Command Operation
Register 0, bit 20 to logic 1, and is automatically cleared when the frame is completed.
The Write data is first set up in Register 1, bits 15:0 for Write operation. Register 0 is initialized
with the appropriate control information (start, op code, etc.) and Register 0, bit 20 is set to logic 1.
Register 0, bit 20 is reset to logic 0 when the frame is complete.
The steps are identical for Read operation except that in Register 1, bits 15:0, the data is ignored.
The data received from the MDIO is read by the CPU interface from Register 1, bits 31:16.
5.5.7
MDI State Machine
The MDI State Machine sequences the information sent to it by the MDIO control registers and
keeps track of the current sequence bit count, enabling or disabling the MDIO driver output (see
101
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Figure 22. MDI State
MDOE = 0
MDO = 0
MDC_EN = 0
Idle
Go = 1
Cnt > 32
Cnt < 32
MDOE = 1
MDO = 1
Preamble
MDC_EN = 1
Cnt = 32
Cnt > 2
Cnt < 2
MDOE = 1
MDO = Reg_Bit_St(Cnt)
Start Bits
MDC_EN = 1
Cnt = 2
Cnt > 2
Cnt < 2
MDOE = 1
MDO = Reg_Bit_Op(Cnt)
Op Code
MDC_EN = 0
Cnt = 2
Cnt > 5
Cnt < 5
MDOE = 1
MDO = Reg_Bit_PA(Cnt)
Phy Addr
MDC_EN = 1
Cnt = 5
Cnt > 5
Cnt < 5
MDOE = 1
MDO = Reg_Bit_RA(Cnt)
Reg Addr
MDC_EN = 1
Cnt = 5
Cnt > 2
Cnt < 2
MDOE = Wr_Op
MDO = Reg_Bit_WO(Cnt)
Turn Around
MDC_EN = 1
Cnt = 2
Cnt < 16
MDOE = Wr_Op
MDO = Data(Cnt)
MDC_EN = 1
Data
Cnt > 16
or (Cnt = 16 and
Go = 0)
Cnt = 16 And Go = 1
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5.5.8
Autoscan Operation
The autoscan function allows the 32 registers in each external PHY (up to four) to be stored
internally in the IXF1104 MAC. Autoscan is enabled by setting bit 1 of the MDI Control register.
When enabled, autoscan runs continuously, reading each PHY register. When a PHY register
access is instigated through the CPU interface, the current autoscan register Read is completed
before the CPU register access starts. Upon completion of the CPU-induced access, the autoscan
functionality restarts from the last autoscan register access.
occupied for each IXF1104 MAC port. The least significant bit (LSB) that is set in the register is
Port 0, the next significant bit that is set is assumed to be port 1, and so on. If more than four bits
are set, the bits beyond the fourth bit are ignored. If less than four bits are set, the round-robin
process returns to the port identified by the LSB being set.
5.6
SerDes Interface
The IXF1104 MAC integrates four integrated Serializer/Deserializer (SerDes) devices that allow
direct connection to optical modules and remove the requirement for external SerDes devices. This
increases integration, which reduces the size of the PCB area required to implement this function,
reduces total power, reduces silicon and manufacturing costs, and improves reliability. Each
SerDes interface is identical and fully compliant with the relevant IEEE 802.3 Specifications,
including auto-negotiation. Each port is also compliant with and supports the requirements of the
Small Form Factor Pluggable (SFP) Multi-Source Agreement (MSA), see Section 5.7, “Optical
The following sections describe the operations supported by each interface, the configurable
options, and the register bits that control these options. A full list of the register addresses and full
5.6.1
Features
The SerDes cores are designed to operate in point-to-point data transmission applications. While
the core can be used across various media types, such as PCB or backplanes, it is configured
specifically for use in 1000BASE-X Ethernet fiber applications in the IXF1104 MAC. The
following features are supported.
• 10-bit data path, which connects to the output/input of the 8B/10B encoder/decoder PCS that
resides in the MAC controller
• Data frequency of 1.25 GHz
• Low power: <200 mW per SerDes port
• Asynchronous clock data recovery
5.6.2
Functional Description
The SerDes transmit interface sends serialized data at 1.25 GHz. The interface is differential with
two signals for transmit operation. The transmit interface is designed to operate in a 100 Ω
differential environment and all the terminations are included on the device. The outputs are high-
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speed SerDes and are capable of operating in either an AC- or DC-coupled environment. AC
coupling is recommended for this interface to ensure that the correct input bias current is supplied
at the receiver.
The SerDes receive interface receives serialized data at 1.25 GHz. The interface is differential with
two signals for the receive operation. The equalizer receives a differential signal that is equalized
for the assumed media channel. The SerDes transmit and receive interfaces are designed to operate
within a 100 Ω differential environment and all terminations are included on the device. The
SerDes is capable of operating in either AC- or DC-coupled environments.
5.6.2.1
Transmitter Operational Overview
The transmit section of the IXF1104 MAC has to serialize the Ten Bit Interface (TBI) data from the
IXF1104 MAC MAC section and outputs this data at 1.25 GHz differential signal levels. The
1.25 GHz differential SerDes signals are compliant with the Small Form Factor Pluggable (SFP)
Multi-Source Agreement (MSA).
The transmitter section takes the contents of the data register within the MAC and synchronously
transfers the data out, ten bits at a time – Least Significant Bit (LSB) first, followed by the next
Most Significant Bit (MSB). When these ten bits have been serialized and transmitted, the next
word of 10-bit data from the MAC is ready to be serialized for transmission.
The data is transmitted by the high-speed current mode differential SerDes output stage using an
internal 1.25 GHz clock generated from the 125 MHz clock input.
5.6.2.2
Transmitter Programmable Driver-Power Levels
The IXF1104 MAC SerDes core has programmable transmitter power levels to enhance usability
in any given application.The SerDes Registers are programmable to allow adjustment of the
transmit core driver output power. When driving a 100 Ω differential terminated network, these
output power settings effectively establish the differential voltage swings at the driver output.
settings. The selected power setting of these inputs is applied to each of the transmit core drivers on
the transmit drivers as a function of the Driver Power Control inputs. The normalized current
setting is 10 mA, which corresponds to the normalized power setting of 1.0. This is the default
setting of the IXF1104 MAC SerDes interface. Other values listed in the Normalized Driver Power
Setting column are multiples of 10 mA. For example, with inputs at 1110, the driver power is the
following:
.5 x 10 mA = 5 mA.
Table 29. SerDes Driver TX Power Levels
Normalized
Driver Power
Setting
DRVPWRx[3] DRVPWRx[2] DRVPWRx[1] DRVPWRx[0]
Driver Power
0
0
1
1
1.33
13.3 mA
NOTE: All other values are reserved.
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Table 29. SerDes Driver TX Power Levels
Normalized
Driver Power
Setting
DRVPWRx[3] DRVPWRx[2] DRVPWRx[1] DRVPWRx[0]
Driver Power
1
1
1
0
1
1
1
0
1
1
1
0
2.0
1.0
0.5
20 mA
10 mA
5 mA
NOTE: All other values are reserved.
5.6.2.3
Receiver Operational Overview
The receiver structure performs Clock and Data Recovery (CDR) on the incoming serial data
stream. The quality of this operation is a dominant factor for the Bit Error Rate (BER) system
performance. Feed forward and feedback controls are combined in one receiver architecture for
enhanced performance. The data is over-sampled and a digital circuit detects the edge position in
the data stream. A signal is not generated if an edge is not found. A feedback loop takes care of
low-frequency jitter phenomenon of unlimited amplitude, while a feed forward section suppresses
high-frequency jitter having limited amplitude. The static edge position is held at a constant
position in the over-sampled by a constant adjustment of the sampling phases with the early and
late signals.
5.6.2.4
5.6.2.5
Selective Power-Down
The IXF1104 MAC offers the ability to selectively power-down any of the SerDes TX or RX ports
Receiver Jitter Tolerance
The SerDes receiver architecture is designed to track frequency mismatch, recover phase, and is
tolerant of low-frequency data jitter. Figure 23 specifies the SerDes core receiver sinusoidal jitter
tracking capabilities.
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Figure 23. SerDes Receiver Jitter Tolerance
Sinusoidal Jitter Mask
16 ui
375 Hz 16 ui
10+1
22.5836 kHz 8.5 ui
0
1.9195 MHz 0.1 ui
5
10-1
0
1
2
3
4
6
7
10
10
10
10
10
10
10
10
Frequency
B0745-02
Note: UI = Unit interval.
5.6.2.6
Transmit Jitter
The SerDes core total transmit jitter, including contributions from the intermediate frequency PLL,
is comprised of the following two components:
• A deterministic component attributed to the SerDes core’s architectural characteristics
• A random component attributed to random thermal noise effects
Since the thermal noise component is random and statistical in nature, the SerDes core total
transmit jitter must be specified as a function of BER.
5.6.2.7
Receive Jitter
The SerDes core total receiver jitter, including contributions from the intermediate frequency PLL,
is comprised of the following two components:
• A deterministic component attributed to the SerDes core architectural characteristics
• A random component attributed to random thermal noise effects.
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5.7
Optical Module Interface
This section describes the connection of the IXF1104 MAC ports to an Optical Module Interface
and details the minimal connections that are supported for correct operation. The registers used for
write control and read status information are documented.
The Optical Module Interface allows the IXF1104 MAC a seamless connection to the Small Form
Factor Optical Modules (SFP) that form the system’s physical media connection, eliminating the
need for any FPGAs or CPUs to process data. All required optical module information is available
to the system CPU through the IXF1104 MAC CPU interface, leading to a more integrated,
reliable, and cost-effective system.
The IXF1104 MAC supports all the functions required for the Small Form Factor pluggable Multi-
Source Agreement (MSA).
There are specific mechanical and electrical requirements for the size, form factor, and connections
supported on all Optical Module Interfaces. There are also specific requirements for each Optical
Module Interface that supports a particular media requirement or interface configuration. These
requirements are detailed in the relevant specifications or manufacturers’ datasheets.IXF1104
MAC
5.7.1
Intel® IXF1104 MAC-Supported Optical Module Interface Signals
To describe the Optical Module Interface operation, three supported signal subgroups are required,
allowing a more explicit definition of each function and implementation. The three subgroups are
as follows:
• High-Speed Serial Interface
• Low-Speed Status Signaling Interface
• I²C Module Configuration Interface
Table 30. Intel® IXF1104 MAC-to-SFP Optical Module Interface Connections (Sheet 1 of 2)
IXF1104 MAC
Signal Names
SFP Signal
Names
Description
Notes
TX_P_0:3
TX_N_0:3
RX_P_0:3
RX_N_0:3
TD+
TD-
Transmit Data, Differential LVDS
Transmit Data, Differential LVDS
Receive Data, Differential LVDS
Receive Data, Differential LVDS
Output from the IXF1104 MAC
Output from the IXF1104 MAC
Input to the IXF1104 MAC
Input to the IXF1104 MAC
RD+
RD-
I2C_CLK output from the
IXF1104 MAC (SCL)
I2C_CLK
MOD-DEF1
MOD-DEF2
MOD-DEF0
Output from the IXF1104 MAC
Input/Output
I2C_DATA_0:3
MOD_DEF_0:3
I2C_DATA I/O (SDA)
MOD_DEF_0 is TTL Low level
during normal operation.
Input to the IXF1104 MAC
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Table 30. Intel® IXF1104 MAC-to-SFP Optical Module Interface Connections (Sheet 2 of 2)
IXF1104 MAC
Signal Names
SFP Signal
Names
Description
Notes
Transmitter disable, logic High,
open collector compatible
TX_DISABLE_0:3 TX DISABLE
Output from the IXF1104 MAC
Input to the IXF1104 MAC
Input to the IXF1104 MAC
Transmitter fault, logic High, open
collector compatible
TX_FAULT_0:3
RX_LOS_0:3
TX FAULT
LOS
Receiver loss-of-signal, logic High,
open collector compatible
5.7.2
Functional Descriptions
High-Speed Serial Interface
5.7.2.1
These signals are responsible for transfer of the actual data at 1.25 Gbps. Table 41 “DC
Specifications” on page 134 shows the data is 8B/10B encoded and transmitted differentially.
The following signals are required to implement the high-speed serial interface:
• TX_P_0:3
• TX_N_0:3
• RX_P_0:3
• RX_N_0:3
5.7.2.2
Low-Speed Status Signaling Interface
The following Low-Speed signals indicate the state of the line through the Optical Module
Interface:
• MOD_DEF_0:3
• TX_FAULT_0:3
• RX_LOS_0:3
• TX_DISABLE_0:3
• MOD_DEF_INT
• TX_FAULT_INT
• RX_LOS_INT
5.7.2.2.1 MOD_DEF_0:3
MOD_DEF_0:3 are direct inputs to the IXF1104 MAC and are pulled to a logic Low level during
normal operation, indicating that a module is present for each channel respectively. If a module is
not present, a logic High is received, which is achieved by an external pull-up resistor at the
IXF1104 MAC device pad.
The status of each bit (one for each port) is found in bits [3:0] of the “Optical Module Status Ports
0-3 ($0x799)” on page 222). Any change in the state of these bits causes a logic Low level on the
MOD_DEF_INT output if this operation is enabled.
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5.7.2.2.2 TX_FAULT_0:3
TX_FAULT_0:3 are inputs to the IXF1104 MAC. These signals are pulled to a logic Low level by
the optical module during normal operation. A logic Low level on these signals indicates no fault
condition exists. If a fault is present, a logic High is received through the use of an external pull-up
resistor at the IXF1104 MAC pad.
The status of each bit (one for each port) can be found in bits [13:10] of the “Optical Module Status
Ports 0-3 ($0x799)” on page 222. Any change in the state of these bits causes a logic Low level on
the TX_FAULT_INT output if this operation is enabled.
5.7.2.2.3 RX_LOS_0:3
RX_LOS_0:3 are inputs to the IXF1104 MAC. These signals are pulled to a logic Low level by the
optical module during normal operation, which indicates that no loss-of-signal exists. If a loss-of-
signal occurs, a logic High is received on these inputs through the use of an external pull-up
resistor at the IXF1104 MAC device pad.
The status of each bit (one for each port) is found in “Optical Module Status Ports 0-3 ($0x799)"
bits [23:20]. Any change in the state of these bits causes a logic Low level on the RX_LOS_INT
output if this operation is enabled.
5.7.2.2.4 TX_DISABLE_0:3
TX_DISABLE_0:3 are outputs from the IXF1104 MAC. These signals are driven to a logic Low
level by the IXF1104 MAC during normal operation. This indicates that the optical module
transmitter is enabled. If the optical module transmitter is disabled, this signal is switched to a logic
High level. On the IXF1104 MAC, these outputs are open drain types and pulled up by the 4.7 k to
10 k pull-up resistor at the Optical Module Interface. Each of these signals is controlled through
5.7.2.2.5 MOD_DEF_INT
MOD_DEF_INT is a single output, open-drain type signal and is active Low. A change in state of
any MOD_DEF_0:3 inputs causes this signal to switch Low and remain in this state until a read of
5.7.2.2.6 TX_FAULT_INT
TX_FAULT_INT is a single output, open-drain type signal and is active Low. A change in state of
any TX_FAULT_0:3 inputs causes this signal to switch Low and remain in this state until a read of
5.7.2.2.7 RX_LOS_INT
RX_LOS_INT is a single output, open-drain type signal and is active low. A change in state of any
of the RX_LOS_3:0 inputs causes this signal to switch low and remain in this state until a Read of
state.
Note: MOD_DEF_INT, TX_FAULT_INT, and RX_LOS_INT are open-drain type outputs. With the
three signals on the device, the system can decide which “Optical Module Status Ports 0-3
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($0x799)" bits to look at to identify the interrupt condition source port. However, this is achieved at
the expense of the three device signals.
5.7.3
I²C Module Configuration Interface
The I²C interface is supported on SFP optical modules. Details of the operation are found in the
SFP Multi-Source Agreement, which details the contents of the registers and addresses accessible
on a given Optical Module Interface supporting this interface.
The SFP MSA identifies up to 512 8-bit registers that are accessible in each optical module. The
Optical Module Interface is read-only and supports either sequential or random access to the 8-bit
parameters. The maximum clock rate of the interface is 100 kHz. All address-select signals on the
internal E²PROM are tied Low to give a device address equal to zero (00h).
Several PHY vendors may offer copper/CAT5-based SFP optical compliant modules. To program
the internal configuration registers of these modules, the IXF1104 MAC I2C interface needs to
provide the capability to write data to the SFP modules.
The IXF1104 MAC I2C interface is designed to allow individual writes of byte-wide data to the
SFP.
The specific interface in the IXF1104 MAC supports only a subset of the full I²C interface, and
only the features required to support the Optical Module Interfaces are implemented. This leads to
the following support features.
• Single I2C_CLK pin connected to all optical modules and implemented to save unnecessary
signals use.
• Four per-port I2C_DATA signals (I²C Data[3:0]) are required because of the optical module
requirement that all modules must be addressed as 00h.
• The interface has both read and write functionality.
• Due to the single internal optical module controller, only one optical module may be accessed
at any one time. Each access contains a single register Read. Since these register accesses will
most likely be done during power-up or discovery of a new module, these restrictions should
not affect normal operation.
• The I2C interface supports byte write accesses to the full address range.
Note: The I2C interface only supports random single-byte reads and does not guarantee coherency when
reading two-byte registers.
5.7.3.1
I2C Control and Data Registers
In the IXF1104 MAC, the entire I²C interface is controlled through the following two registers:
These registers can be programmed by system software using the CPU interface.
5.7.3.2
I2C Read Operation
To perform a read operation using the I2C interface, use the following sequence:
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1. Initialize the Control register by setting the following values:
a. Enable the I2C Controller by setting bit [25] to 0x1.
b. Initiate the I2C transfer by setting bit [24] of the control register to 0x1.
c. Select the port by using bits [17:16].
d. Select the Read mode of operation by setting bit [15] to 0x1.
e. Select the Device ID by setting bits [14:11].
f. Select the register address by setting bits [10:0].
2. Set the Device ID field to 0xA and the register address (bits 10:8) to 0x0 to access the fiber
module serial E2PROM. Setting the Device ID field to 0xA and the Register Address [10:8] to
0x0 permits read-only access.
3. Set the Device ID field to 0xA and the Register Address [10:8] between the values of 0x1 and
0x7 to access the PHY registers.
4. Poll the Read_Valid field, bit 20. The read data is available when this bit is set to 0x1.
Figure 24 shows an 8-bit read access.
Note: The user software ensures the order of the contiguous accesses required to read the High and Low
bytes of 16-bit-wide PHY registers.
Figure 24. I2C Random Read Transaction
S
T
A
R
T
W
R
I
T
E
S
T
A
R
T
R
E
A
D
S
T
O
P
DEVICE
ADDRESS
WORD
ADDRESS
DEVICE
ADDRESS
I2C_Data Line
*
L
S
B
A
C
K
M
S
B
L
S
B
A
C
K
M
S
B
N
O
M
S
B
L
S
B W
R
/
DATAn
A
C
K
DUMMY WRITE
(* = DON'T CARE bit for 1k)
Note: Only one optical module I²C access sequence can be run at any given time. If a second write is
result is returned for the previous write, the data for the first write is lost. An internal state machine
completes the Optical Module Interface register access for the first write. It attempts to place the
data in the DataRead field and checks to see if the WriteCommand bit is 00h. If it is not 00h, it
discards the data and signals the I²C access state machine to begin a new cycle using the data from
the second write.
5.7.3.3
I2C Write Operation
The following sequence provides an example of writing data to Register Address 0xFF for Port 3:
a. Enable the I2C block by setting Register bit 25 to 0x1.
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b. Set the port to be accessed by setting Register bits 17:16 to 0x3.
c. Select a Write access by setting Register bit 15 to 0x0.
d. Set the Device ID Register bits 14:11 to Ah (Atmel compatible).
e. Set the 11-bit register address (Register bits 10:0) to 0FFh.
f. Enable the I2C controller by setting Register bit 2 to 0x1.
g. Initiate the I2C transfer by setting Register bit 24 to 0x1.
All other bits in this register should be set to 0x0.
interface.
2. When this register is written and the I2C Start bit is at a Logic 1, the I2C access state machine
examines the Port Address Select and enables the I2C_DATA_0:3 output for the selected port.
3. The state machines uses the data in the Device ID and Register Address fields to build the data
frame to be sent to the optical module
4. The I2C_DATA_WRITE_FSM internal state machine takes over the task of transferring the
actual data between the IXF1104 MAC and the selected optical module (refer to the details in
5. The I2C_DATA_WRITE_FSM internal state machine uses the data from the Write_Data field
Access is complete.
6. The data is written through the CPU interface. The CPU must poll the Write_Complete bit
until it is set to 0x1. It is safe to request a new access only when this bit is set.
Note: Only one optical module I2C access sequence can be run at any given time. The data for the first
result is returned for the previous Write. Make sure Write complete = 0x1 before starting the next
Write sequence to ensure that no data is lost.
5.7.3.4
I²C Protocol Specifics
Section 5.7.3.4 describes the IXF1104 MAC I²C Protocol behavior, which is controlled by an
internal state machine. Specific protocol states are defined below, with an additional description of
the hardware signals used on the interface.
The Serial Clock Line (I2C_CLK) is an output from the IXF1104 MAC. The serial data is
synchronous with this clock and is driven off the rising edge by the IXF1104 MAC and off the
falling edge by the optical module. The IXF1104 MAC has only one I2C_CLK line that drives all
of the optical modules. I2C_CLK runs continuously when enabled (I²C Enable = 01h0).
The Serial Data (I2C_DATA_3:0) signals (one per port) are bi-directional for serial data transfer.
These signals are open drain.
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5.7.3.5
5.7.3.6
Port Protocol Operation
Clock and Data Transitions
The I2C_DATA is normally pulled High with an extra device. Data on the I2C_DATA pin changes
periods indicate a start or stop condition.
Figure 25. Data Validity Timing
I2C_Data
I2C_Clk
DATA STABLE
DATA STABLE
DATA
CHANGE
5.7.3.6.1 Start Condition
A High-to-Low transition of I2C_DATA, with I2C_CLK High, is a start condition that must
5.7.3.6.2 Stop Condition
A Low-to-High transition of the I2C_DATA with I2C_CLK High is a stop condition. After a Read
sequence, the stop command places the E²PROM and the optical module in a standby power mode
Figure 26. Start and Stop Definition Timing
I2C_Data
I2C_Data
STOP
START
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5.7.3.6.3 Acknowledge
All addresses and data words are serially transmitted to and from the optical module in 8-bit words.
The optical module E²PROM sends a zero to acknowledge that it has received each word, which
Figure 27. Acknowledge Timing
I2C_Data
DATA IN
DATA OUT
START
ACKNOWLEDGE
5.7.3.6.4 Memory Reset
After an interruption in protocol, power loss, or system reset, any 2-wire optical module can be
reset by following three steps:
1. Clock up to 9 cycles
2. Wait for I2C_DATA High in each cycle while I2C_CLK is High
3. Initiate a start condition.
5.7.3.6.5 Device Addressing
All E²PROMs in SFP optical module devices require an 8-bit device address word following a start
condition to enable the chip to read or write. The device address word consists of a mandatory one,
zero sequence for the four most-significant bits. This is common to all devices. The next three bits
are the A2, A1, and A0 device address bits that are tied to zero in an optical module. The eighth bit
of the device address is the Read/Write operation select bit. A Read operation is initiated if this bit
is High and a Write operation is initiated if this bit is Low.
Upon comparison of the device address, the optical module outputs a zero. If a comparison is not
made, the optical module E²PROM returns to a standby state.
5.7.3.6.6 Random Read Operation
A random Read requires a “dummy” Byte/Write sequence to load the data word address. The
“dummy” write is achieved by first sending the device address word with the Read/Write bit
cleared to Low, which signals a Write operation. The optical module acknowledges receipt of the
device address word. The IXF1104 MAC sends the data word address, which is again
acknowledged by the optical module. The IXF1104 MAC generates another start condition. This
completes the “dummy” write and sets the optical module E²PROM pointers to the desired
location.
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The IXF1104 MAC initiates a current address read by sending a device address with the Read/
Write bit set High. The optical module acknowledges the device address and serially clocks out the
data word. The IXF1104 MAC does not respond with a zero but generates a stop condition (see
Figure 28. Random Read
S
T
A
R
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R
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T
E
S
T
A
R
T
R
E
A
D
S
T
O
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DEVICE
ADDRESS
WORD
ADDRESS
DEVICE
ADDRESS
I2C_Data Line
*
L
S
B
A
C
K
M
S
B
L
S
B
A
C
K
M
S
B
N
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M
S
B
L
S
B W
R
/
DATAn
A
C
K
DUMMY WRITE
(* = DON'T CARE bit for 1k)
5.8
LED Interface
The IXF1104 MAC uses a Serial interface, consisting of three signals, to provide LED data to some
form of external driver. This provides the data for 12 separate direct drive LEDs and allows three
LEDs per MAC port.
There are two modes of operation, each with its own separate LED decode mapping. Modes of
operation and LEDs are detailed in the following sections.
5.8.1
Modes of Operation
There are two modes of operation: Mode 0 and Mode 1. Mode selection is accomplished by using
the LED_SEL_MODE bit. This bit is globally selected and controls the operation of all ports (see
Mode 0: (LED_SEL_MODE = 0 [Default]): This mode selects operations compatible with the
SGS Thompson M5450 LED Display Driver device. This device converts the serial data stream,
output by the IXF1104 MAC, into 30 direct-drive LED outputs. Although the LED interface is
capable of driving all 30 LEDs, only twelve will be driven in the four-port IXF1104 MAC, three
LEDs per port.
Mode 1: (LED_SEL_MODE = 1): This mode is used with standard TTL (74LS599) or HCMOS
(74HC599) octal shift registers with latches, providing the most general and cost-effective
implementation of the serial data stream conversion.
In addition to these physical modes of operation, there are two types of specific LED data decodes
available for fiber and copper modes. This option is a global selection and controls the operation of
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5.8.2
LED Interface Signal Description
The IXF1104 MAC LED interface consists of three output signal signals that are 2.5 V CMOS
Table 31. LED Interface Signal Descriptions
Pin Name
Pin #
Pin Description
This signal is an output that provides a continuous clock synchronous to the
serial data stream output on the LED_DATA pin. This clock has a maximum
speed of 720 Hz.
LED_CLK
K24
The behavior of this signal remains constant in all modes of operation.
This signal provides the data, in various formats, as a serial bit stream. The data
must be valid on the rising edge of the LED_CLK signal.
LED_DATA
M22
L22
In Mode 0, the data presented on this pin is TRUE (Logic 1 = High).
In Mode 1, the data presented on this pin is INVERTED (Logic 1 = Low).
This is an output pin, and the signal is used only in Mode 1 as the Latch enable
for the shift register chain.
LED_LATCH
This signal is not used in Mode 0, and should be left unconnected.
5.8.3
Mode 0: Detailed Operation
Note: Please refer to the SGS Thompson* M5450 datasheet for device-operation information.
The operation of the LED Interface in Mode 0 is based on a 36-bit counter loop. The data for each
basic timing relationship and relative positioning in the data stream of each bit.
Figure 29 shows the 36 clocks that are output on the LED_CLK pin. The data is changed on the
falling edge of the clock and is valid for almost the entire clock cycle. This ensures that the data is
valid during the rising edge of the LED_CLK, which clocks the data into the M5450 device.
DATA. The 36-bit data chain is built up as follows:
Figure 29. Mode 0 Timing
1
2
3
4
1
25 26 27 28 29 30 31 32 33 34 35
22 23 24 25 26 27 28 29 30
LED_CLK
LED_DATA
LED_LATCH
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Table 32. Mode 0 Clock Cycle to Data Bit Relationship
LED_DATA
Name
LED_CLK Cycle
LED_DATA Description
This bit synchronizes the M5450 device to expect 35 bits of data to
follow.
1
START BIT
These bits are used only as fillers in the data stream to extend the
length from the actual 12-bit LED DATA to the required 18-bit frame
length. These bits should always be a logic 0.
2:3
4:15
36:38
PAD BITS
These bits are the actual data transmitted to the M5450 device. The
LED DATA 1-12
PAD BITS
The data is TRUE. Logic 1 (LED ON) = High
These bits are used as fillers in the data stream to extend the length
from the actual 30-bit LED DATA to the required 36-bit frame length.
These bits should always be a logic 0.
When implemented on the board with the M5450 device, the LED DATA bit 1 appears on Output
bit 3 of the M5450 and the LED DATA bit 2 appears on Output bit 4, etc. This means that Output
bits 1, 2, and 15 through 35 will never have valid data and should not be used.
5.8.4
Mode 1: Detailed Operation
Note: Please refer to generic specifications for 74LS/HC599 for information on device operation.
The operation of the LED Interface in Mode 1 is based on a 36-bit counter loop. The data for each
LED is placed in turn on the serial data line and clocked out by the LED_CLK. Figure 30 on
page 118 shows the basic timing relationship and relative positioning in the data stream of each bit.
Figure 30 on page 118 shows the 36 clocks which are output on the LED_CLK pin. The data is
changed on the falling edge of the clock and is valid for the almost the entire clock cycle. This
ensures that the data is valid during the rising edge of the LED_CLK, which clocks the data into the
shift register chain devices.
The LED_LATCH signal is required in Mode 1, and latches the data shifted into the shift register
is active High during the Low period on the 35th LED_CLK cycle. This avoids any possibility of
trying to latch data as it is shifting through the register.
When this operation mode is implemented on a board with a shift register chain containing three
74HC599 devices, the LED DATA bit 1 is output on Shift register bit 1, and so on up the chain.
Only Shift register bits 31 and 32 do not contain valid data.
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Note: The LED_DATA signal is now inverted from the state in Mode 0.
Figure 30. Mode 1 Timing
1
2
3
4
1
25 26 27 28 29 30 31 32 33 34 35
22 23 24 25 26 27 28 29 30
LED_CLK
LED_DATA
LED_LATCH
Table 33. Mode 1 Clock Cycle to Data Bit Relationship
LED_CLK Cycle LED_DATA Name LED_DATA Description
This bit has no meaning in Mode 1 operation and is shifted out of
1
START BIT
PAD BITS
the 16-stage shift register chain before the LED_LATCH signal is
asserted.
These bits have no meaning in Mode 1 operation and are shifted
out of the 16-stage shift register chain before the LED_LATCH
signal is asserted.
2:3
These bits are the actual data to be transmitted to the 16-stage shift
register chain. The decode for each bit in each mode is defined in
4:15
LED DATA 1-12
PAD BITS
The data is INVERTD. Logic 1 (LED ON) = Low.
These bits have no meaning in Mode 1 operation and are latched
into positions 31 and 32 in the shift register chain. These bits are
not considered as valid data and should be ignored. They should
always be a Logic 0 = High.
36:38
5.8.5
5.8.6
Power-On, Reset, Initialization
The LED interface is disabled at power-on or reset. The system software controller must enable the
LED interface. The internal state machines and output signals are held in reset until the full Intel®
IXF1104 4-Port Gigabit Ethernet Media Access Controller device configuration is completed. This
is done by setting the LED_ENABLE bit to a logic 1 (see Table 109 “LED Control ($0x509)” on
page 190). The power-on default for this bit is logic 0.
LED DATA Decodes
The data transmitted on the LED_DATA line is determined by programming the global operation
mode as either fiber or copper. Table 34 shows the data decode of the data for both fiber and copper
MACs.
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Note: The data decode of the LED bits is independent of the Physical mode selection.
Table 34. LED_DATA# Decodes
LED_DATA# MAC Port #
Fiber Designation
Copper Designation
1
Rx LED—Amber
Rx LED—Green
TX LED—Green
Rx LED—Amber
Rx LED—Green
TX LED—Green
Rx LED—Amber
Rx LED—Green
TX LED—Green
Rx LED—Amber
Rx LED—Green
TX LED—Green
Link LED—Amber
Link LED—Green
Activity LED—Green
Link LED—Amber
Link LED—Green
Activity LED—Green
Link LED—Amber
Link LED—Green
Activity LED—Green
Link LED—Amber
Link LED—Green
Activity LED—Green
2
3
0
1
2
3
4
5
6
7
8
9
10
11
12
5.8.6.1
LED Signaling Behavior
5.8.6.1.1 Fiber LED Behavior
Table 35. LED Behavior (Fiber Mode)
Type
Status
Description
Synchronization occurs but no packets are received
Off
RX Synchronization has not occurred or no optical
signal exists.
Amber On
The port has remote fault and the “Link LED Enable
($0x502)” is not set (based on remote fault bit setting
received in Rx_Config word).
RXLED
Amber Blinking
RX Synchronization occurs and the “Link LED Enable
($0x502)” bit is set.
Green On
Green Blinking
Off
RX Synchronization occurs and the port is receiving
data.
The port is not transmitting data or the “Link LED
Enable ($0x502)” is not set.
TXLED
The port is transmitting data and the “Link LED Enable
($0x502)” bit is set
Green Blinking
NOTE: Table 35 assumes the port is enabled in the “Port Enable ($0x500)” and the LEDs are enabled in the
“LED Control ($0x509)”. If a port is not enabled, all the LEDs for that port will be off. If the LEDs are not
enabled, all of the LEDs will be off.
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5.8.6.1.2 Copper LED Behavior
Table 36. LED Behavior (Copper Mode)
Type
Status
Description
Port does not have a remote fault and “LED Control
($0x509)” on page 190 bit is not set.
Off
Port has an RGMII RXERR condition detected and
“LED Control ($0x509)” on page 190 bit is set
Amber On
Amber Blinking
Link LED
Port has a remote fault and “LED Fault Disable
($0x50B)” on page 191 is not set.
“LED Control ($0x509)” on page 190 bit is set and port
does not have an RGMII RXERR error or remote fault
condition present.
Green On
Off
Port is not transmitting and receiving data.
“LED Control ($0x509)” on page 190 set: Port is
transmitting and/or receiving.
Activity LED - Green
Blinking
“LED Control ($0x509)” on page 190 not set: Port is
receiving data.
enabled, all the LEDs for that port are off. If the LEDs are not enabled, all of the LEDs are off.
5.9
CPU Interface
The CPU interface block provides access to registers and statistics in the IXF1104 MAC. The
interface is asynchronous externally and operates within the 125 MHz clock domain internally. The
interface provides access to the following:
• Receive statistics registers
• Transmit statistics registers
• Receive FIFO registers
• Transmit FIFO registers
• Global configuration and control registers
• MAC_0 to MAC_3 registers
The CPU interface width can be configured with the two strap signals (UPX_WIDTH[1:0]) to
operate as an 8-bit, 16-bit, or 32-bit bus. All internal accesses to registers are 32-bit (4, 2, or 1 data
cycles respectively are required to fully access a register). When operating in 8-bit or 16-bit mode,
read data for bytes [3:1] is strobed into read holding registers when byte [0] is read. Subsequent
reads of bytes {1, 2, 3} in byte mode or of bytes {2,3} in 16-bit mode are supplied from the holding
register independent of the upper address bits. On write accesses in 8-bit mode, the data of bytes
{0, 1, 2} is similarly captured in internal write holding registers and the complete 32-bit write is
committed when byte[3] is written to the IXF1104 MAC. When writing in 16-bit mode, bytes [1:0]
are captured, and the double-word is committed when bytes [3:2] are written. The complete
address for write is ignored (except for the write which causes the commit operation).
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5.9.1
Functional Description
Read Access
5.9.1.1
Read access involves the following:
• Detect assertion of asynchronous Read control signal and latch address
• Generate internal Read strobe
• Drive valid data onto processor bus
• Assert asynchronous Ready signal for required length of time
Figure 31 shows the timing of the asynchronous interface for Read access.
Figure 31. Read Timing Diagram - Asynchronous Interface
T
CAS
TCAH
uPx_ADD[10:0]
uPx_CsN
T
CRR
uPx_RdN
T
CRH
uPx_Data[31:0]
T
CDRS
T
CDRH
uPx_RdyN
TCDRD
B5103-01
5.9.1.2
Write Access
Write process involves the following:
• Detect assertion of asynchronous Write control signal and latch address
• Detect de-assertion of asynchronous Write control signal and latch data
• Generate internal Write strobe
• Assert asynchronous Ready signal for required length of time
Figure 32 shows the timing of the asynchronous interface for Write accesses.
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Figure 32. Write Timing Diagram - Asynchronous Interface
TCAS
TCAH
uPx_Add[12:0]
uPx_CsN
uPx_WrN
TCWL
TCWH
TCDWH
uPx_Data[31:0]
uPx_RdyN
TCDWS
TCYD
TCDWD
5.9.1.3
5.9.2
CPU Timing Parameters
For information on the CPU interface Read and Write cycle AC timing parameters, refer to Figure
Endian
The Endian of the CPU interface may be changed to allow connection of various CPUs to the
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller. The Endian selection is
The following describes Endianness control:
• There is a byte swapper between the internal 32-bit bus and the external 32-bit bus.
• In 8-bit or 16-bit mode operation, the byte packer/byte unpacker holding registers sink and
source data just like the 32-bit external bus in 32-bit mode.
data[31:0].
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Table 37. Byte Swapper Behavior
Little Endian
Big Endian
16-bit
UPX_BADD
[1:0]
32-bit
16-bit
8-bit1
32-bit
8-bit1
UPX_DATA_ UPX_DATA_ UPX_DATA
UPX_DATA
[31:0]
UPX_DATA
[15:0]
UPX_DATA
[7:0]
[31:0]
[15:0]
[7:0]
[7:0]
[15:8]
[23:16
[31:24]
[7:0]
[15:8]
00
[31:0]
[15:0]
[7:0]
[7:0]
01
10
11
–
–
–
–
[31:16]
–
[15:8]
[23:16]
[31:24]
–
–
–
–
[15:8]
[23:16]
[31:24]
[23:16]
[31:24]
–
1. In 8-bit mode, data is output in Little Endian format regardless of the IXF1104 MAC Endian setting.
5.10
TAP Interface (JTAG)
The IXF1104 MAC includes an IEEE 1149.1 compliant Test Access Port (TAP) interface used
during boundary scan testing. The interface consists of the following five signals:
• TDI – Serial Data Input
• TMS – Test Mode Select
• TCLK – TAP Clock
• TRST_L – Active Low asynchronous reset for the TAP
• TDO – Serial Data Output
TDI and TMS require external pull-up resistors to float the signals High per the IEEE 1149.1
specification. Pull-ups are recommended on TCK and TDO. For normal operation, TRST_L can be
pulled Low, permanently disabling the JTAG interface. If the JTAG interface is used, the TAP
returned to a logic High.
5.10.1
TAP State Machine
The TAP signals drive a TAP controller, which implements the 16-state state machine specified by
the IEEE 1149.1 specification. Following power-up, the TAP controller must be reset by one of
following two mechanisms:
• Asynchronous reset
• Synchronous reset
Asynchronous reset is achieved by pulsing or holding TRST_L Low. Synchronous reset is
achieved by clocking TCLK with five clock pulses while TMS is held or floats High. This ensures
that the boundary scan cells do not block the pin to core connections in the IXF1104 MAC.
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5.10.2
Instruction Register and Supported Instructions
The instruction register is a 4-bit register that enacts the boundary scan instructions. After the state
machine resets, the default instruction is IDCODE. The decode logic in the TAP controller selects
the appropriate data register and configures the boundary scan cells for the current instruction.
Table 38. Instruction Register Description
Instruction
Code
Description
Data Register
BYPASS
EXTEST
SAMPLE
IDCODE
HIGHZ
1111
0000
0001
0110
0101
0111
1-bit Bypass
Bypass
External Test
Boundary Scan
Boundary Scan
ID
Sample Boundary
ID Code Inspection
Float Boundary
Clamp Boundary
Bypass
CLAMP
Bypass
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5.10.3
5.10.4
ID Register
The ID register is a 32-bit register. The IDCODE instruction connects this register between TDI
Boundary Scan Register
The Boundary Scan register is a shift register made up of all the boundary scan cells associated
with the device signals. The number, type, and order of the boundary scan cells are specified in the
IXF1104 MAC BSDL file. The EXTEST and SAMPLE instructions connect this register between
TDI and TDO.
5.10.5
Bypass Register
The Bypass register is a 1-bit register that bypasses the IXF1104 MAC to reduce the JTAG chain
length when accessing other devices on the chain besides the IXF1104 MAC. The BYPASS,
HIGHZ, and CLAMP instructions connect this register between TDI and TDO.
5.11
Loopback Modes
The IXF1104 MAC provides two loopback modes for device diagnostic testing when it has been
integrated into a user system. A line-side loopback allows the line-side receive interface to be
looped back to the transmit line-side interface. A SPI3 loopback mode allows the SPI3 transmit
interface to be looped back to the SPI3 receive interface.
The IXF1104 MAC line-side and SPI3 loopback modes are effective diagnostic tools for validation
of system level connectivity and interface compatibility.
In loopback-mode operation, the data path is internally redirected to allow for the data flow return
path. Redirection requires the data path to circumvent resources that are required during normal
traffic flow. For example, while operating in SPI3 loopback mode, the data path does not pass
through the MAC or TX FIFO and those resource features are not used. The result is a possible
degradation of throughput performance and statistical data accuracy. Intel recommends that
loopback modes be used for diagnostic purposes only.
5.11.1
SPI3 Interface Loopback
To provide a diagnostic loopback feature on the SPI3 interface, it is possible to configure the
IXF1104 MAC to loop back any data written to the IXF1104 MAC through the SPI3 transmit
interface back to the SPI3 receive interface. This is accomplished using the data path shown in
Note: Loopback packets also appear on the line side TX interface.
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Figure 33. SPI3 Interface Loopback Path
SPI3 Internal Loopback
TX FIFO
TX
SPI3 Interface
Block
Line Side
Interface
MAC
RX FIFO
RX
B3229-01
Note: There is a restriction when using this loopback mode. At least one clock cycle is required between
a TEOP assertion and a TSOP assertion. This is required when the pre-pend feature of the receive
FIFO is enabled to allow the addition of the extra two bytes to the data sent on the transmit
interface. Where the pre-pend feature has not been enabled, data can be sent back-to-back on the
transmit SPI3 interface with TSOP following TEOP on the next cycle.
To configure the IXF1104 MAC to use the SPI3 loopback mode, the “RX FIFO SPI3 Loopback
Enable for Ports 0 - 3 ($0x5B2)" must be configured. Each IXF1104 MAC port has a unique bit in
this register designated to control loopback. It is possible to have individual ports in a loopback
mode while other ports continue to operate in a normal mode.
5.11.2
Line Side Interface Loopback
To provide a diagnostic loopback feature on the line-side interfaces, the IXF1104 MAC can be
configured to loop back any data received by the IXF1104 MAC through one of the line interfaces
back to the corresponding transmit line interface. This is done by using the data path shown in
Figure 34. The line-side interface can be either SerDes, RGMII or GMII. Please note that it is not
possible to loop one line-side interface back to a different one (for example, Rx SerDes looped
back to transmit RGMII).
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Figure 34. Line Side Interface Loopback Path
Line Side Internal Loopback
TX
TX FIFO
SPI3 Interface
Block
Line Side
Interface
MAC
RX FIFO
RX
B3230-01
When the IXF1104 MAC is configured in this loopback mode, all of the MAC functions and
features are available, including flow control and pause-packet generation.
FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F)" must be configured. Each IXF1104 MAC port
has a unique bit in this register designated to control the loopback. It is possible to have individual
ports in a loopback mode while other ports continue to operate in a normal mode.
Note: Line side interface loopback packets also appear at the SPI3 interface.
5.12
Clocks
The IXF1104 MAC system interface has several reference clocks, including the following:
• SPI3 data path input clocks
• RGMII input and output clocks
• MDIO output clock
• JTAG input clock
• I2C clock
• LED output clock.
This section details the unique clock source requirements.
5.12.1
System Interface Reference Clocks
The following system interface clock is required by the IXF1104 MAC:
• CLK125
127
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5.12.1.1
CLK125
The system interface clock, which supplies the clock to the majority of the internal circuitry, is the
125 MHz clock. The source of this clock must meet the following specifications:
• 2.5 V CMOS drive
• +/- 50 ppm
• Maximum duty cycle distortion 40/60
5.12.2
SPI3 Receive and Transmit Clocks
The IXF1104 MAC transmit clock requirements include the following:
• 3.3 V LVTTL drive
• +/- 50 ppm
• Maximum frequency of 133 MHz in MPHY mode
• Maximum frequency of 125 MHz in SPHY mode
• Maximum duty cycle distortion 45/55
The IXF1104 MAC meets the following specifications for the receive clock:
• 3.3 V LVTTL drive
• +/- 50 ppm
• Maximum frequency of 133 MHz in MPHY mode
• Maximum frequency of 125 MHz in SPHY mode
• Maximum duty cycle distortion 45/55
5.12.3
RGMII Clocks
The RGMII interface is governed by the Hewlett-Packard* 1.2a specification. The IXF1104 MAC
compliant to this specification with the following:
• 2.5 V CMOS drive
• Maximum duty cycle distortion 40/60
• +/- 100 ppm
• 125 MHz for 1000 Mbps, 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps
5.12.4
MDC Clock
The IXF1104 MAC supports the IEEE 802.3 MII Management Interface, also known as the
Management Data Input/Output (MDIO) Interface. The IXF1104 MAC meets the following
specifications for this clock:
• 2.5 V CMOS drive
• 50/50 duty cycle for 2.5 MHz operation
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• 43/57 duty cycle for 18 MHz operation
5.12.5
JTAG Clock
The IXF1104 MAC supports JTAG. The source of this clock must meet the following
specifications:
• 2.5 V CMOS drive
• Maximum clock frequency 11 MHz
• Maximum duty cycle distortion 40/60
5.12.6
5.12.7
I2C Clock
The IXF1104 MAC supports a single-output I2C clock to support all ten Optical Module interfaces.
The IXF1104 MAC meets the following specifications for this clock:
• 2.5 V CMOS drive
• Maximum clock frequency of 100 KHz
LED Clock
The IXF1104 MAC supports a serial LED data stream and meets the following specifications for
this clock:
• 2.5 V CMOS drive
• Maximum frequency of 720 Hz
• Maximum duty cycle distortion 50/50
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6.0
Applications
6.1
Change Port Mode Initialization Sequence
Use the change port mode initialization sequence after power-up and anytime a port is configured
into or switching between fiber or copper mode, switching to/from RGMII and GMII modes, or
switching speeds and duplex in RGMII mode.
The following sequence applies to all four ports and can be done simultaneously for all ports or as
a subset of the ports.
2. Place the TX FIFO in reset for the port(s) which require a change by asserting (set to 1) the
3. Disable the port(s) which require change by de-asserting (set to 0) the appropriate bits in the
4. Wait 1 μs.
ports being changed.
6. Set the speed, mode, and duplex as follows for the ports being changed:
a. Copper mode:
appropriate speed and RGMII/GMII interface setting.
Note: Half-duplex is supported only when RGMII 10 Mbps or 100 Mbps is selected in the
b. Fiber mode:
Select fiber mode by setting the appropriate bit to 0 in the “Interface Mode ($0x501)”
ports.
being changed.
8. Wait 1 μs.
11. Wait 1 to 2 μs.
a. Copper mode:
Write the reserved bits to the default value.
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Enable packet padding and CRC appending on transmitted packets in bits 6 and 7, as
needed.
Set bit 5 to 0x0.
b. Fiber Mode:
Write the reserved bits to the default value.
Enable Packet padding and CRC Appending on transmitted packets in bits 6 and 7, as
needed.
Set bit 5 to 1 to enable auto-negotiation.
Set bit 5 to 0 to enable forced mode operation.
14. Wait 1 to 2 μs.
15. Perform additional device configurations, as needed.
6.2
Disable and Enable Port Sequences
Intel recommends the following sequences to disable and enable individual ports, and for dropped
links. When a link is dropped, Intel recommends the port be completely reset and flushed to
remove packet fragments that may interfere with the auto-negotiation process on link recovery.
6.2.1
Disable Port Sequence
Use the following sequence to disable an individual port:
3. Introduce some delay to allow completion of packet transmission (not necessary if link is
dropped).
6.2.2
Enable Port Sequence
Use the following sequence to enable an individual port:
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7.0
Electrical Specifications
page 154 represent the target specifications of the following IXF1104 MAC interfaces:
— SPI3
— JTAG
— MDIO
— Pause Control
— CPU
— LED
— System
— GMII and RGMII
— SerDes
— Optical Module
These specifications are not guaranteed and are subject to change without notice. Minimum and
Interface AC Timing Parameters” on page 154 apply over the recommended operating conditions
Table 39. Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Units
Comments
VDD
-0.3
-0.3
-0.3
-0.3
-0.3
-40
2.2
4.25
4.25
2.2
volts
volts
volts
volts
volts
°C
Core digital power
I/O digital power
I/O digital power
Analog power
Analog power
Copper mode
Fiber mode
VDD2, VDD3
VDD4, VDD5
AVDD1P8_1/2
AVDD2P5_1/2
TOPA
Supply voltage
4.25
+85
+70
+150
Ambient
Ambient
Operating
temperature
TOPA
0.0
°C
Storage temperature
TST
-40
°C
–
Caution: Exceeding these values may cause permanent damage to the device. Functional
operation under these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 40. Recommended Operating Conditions
Parameter
Symbol
VDD
Min
Typ
Max
Units
1.65
3.0
–
–
–
1.95
3.6
Volts
Volts
Volts
VDD2, VDD3
VDD4, VDD5
2.3
2.7
Recommended supply voltage
AVDD1P8_1
AVDD1P8_2
1.65
2.3
–
–
1.95
2.7
Volts
Volts
AVDD2P5_1
AVDD2P5_2
VDD
AVDD1P8_1
AVDD1P8_2
–
–
0.780
0.050
–
–
Amps
Amps
SerDes Operation
VDD4
VDD5
AVDD2P5_1
AVDD2P5_2
Transmitting and
receiving in
1000 Mbps mode
Operating Current
VDD2, VDD3
–
–
0.246
0.757
–
–
Amps
Amps
VDD
AVDD1P8_1
AVDD1P8_2
RGMII Operation
VDD4
VDD5
Transmitting and
receiving in
Operating Current
–
0.224
–
Amps
AVDD2P5_1
AVDD2P5_2
1000 Mbps mode
VDD2, VDD3
TOPA
–
0
0.208
–
0.235
70
Amps
°C
Ambient
Recommended
operating
temperature
Case with heat
sink
TOPC-HS
0
0
–
–
122
121
°C
°C
Case without heat
sink
TOPC-NHS
SerDes Operation
Transmitting and
receiving in
1000 Mbps mode
–
–
–
–
2.23
2.84
2.72
3.4
Watts
Watts
Power
consumption
RGMII Operation
Transmitting and
receiving in
1000 Mbps mode
7.1
DC Specifications
The IXF1104 MAC supports the following I/O buffer types:
• 2.5 V CMOS
• 3.3 V LVTTL
• SerDes
133
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Document Number: 278757
Revision Number: 009
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
buffer types. The related driver characteristics are described in this section.
Caution: IXF1104 MAC input signals are not 5 V tolerant. Devices driving the IXF1104 MAC must provide
3.3 V signal levels or use level-shifting buffers to provide 3.3 V-compatible levels. Otherwise,
damage to the IXF1104 MAC will occur.
Table 41. DC Specifications
Parameter
Symbol
Min
Typ
Max
Units
Comments
2.5 V CMOS I/O Cells
Input High voltage
Input low voltage
Output High voltage
Output low voltage
VIH
VIL
1.7
–
–
–
–
–
–
0.7
–
V
V
V
V
2.5 V I/Os
2.5 V I/Os
2.5 V I/Os
2.5 V I/Os
VOH
VOL
2.0
–
0.4
3.3 V I/O Cells
Input High voltage
Input low voltage
Output High voltage
Output low voltage
VIH
VIL
1.7
–
–
–
–
–
–
0.7
–
V
V
V
V
3.3 V LVTTL I/Os
3.3 V LVTTL I/Os
3.3 V LVTTL I/Os
3.3 V LVTTL I/Os
VOH
VOL
2.4
–
0.4
Table 42. SerDes Transmit Characteristics (Sheet 1 of 2)
Normalized
Power
Parameter
Symbol
Min
Typ Max
Units
Comments
Drive
Settings1
0.50
1.00
1.33
2.00
0.50
1.00
1.33
2.00
180
350
425
600
230
440
580
325
700
900
Transmit differential
signal level
AVDD1P8_2 terminated
to 1.8V; Rload = 50 Ω
TxDfPP
mVpp diff
770 1050
1300 1600 1940
1000 1400 1870
AVDD1P8_2 terminated
to 1.8V; RLoad = 50
ohms; FIR coeffs = 0
Transmit common
mode voltage range
TxCMV
mV
800
700
1300 1825
1100 1760
Differential signal rise/ Diff rise/
Rload = 50 Ω; 20% to
1.00
–
60
60
96
132
150
ps
fall time
fall
80% max
Differential output
impedance
Nominal value = 100 Ω
differential
TxDiffZ
105
Ω diff
Receiver differential
voltage requirement at
center of receive eye
mVp-p
diff
RxDiffV
–
200
–
–
–
Datasheet
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Document Number: 278757
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 42. SerDes Transmit Characteristics (Sheet 2 of 2)
Normalized
Power
Parameter
Symbol
Min
Typ Max
Units
Comments
Drive
Settings1
Receiver common
mode voltage range
RxCMV
–
900
1275 1650
mV
–
Receiver termination
impedance
RxZ
–
–
40
50
51
62.5
Ω
–
–
Signal detect level
RxSigDet
125
200 mVp-pdiff
1. Refer to Section 5.6.2.2, “Transmitter Programmable Driver-Power Levels” on page 104.
Table 43. SerDes Receive Characteristics
Normalized
Power
Parameter
Symbol
Min
Typ
Max
Units
Comments
Drive
Settings
Receiver differential
voltage requirement at
center of receive eye
RxDiffV
RxCMV
–
–
200
900
–
–
mVp-p diff
–
–
Receiver common
mode voltage range
1275 1650
mV
Receiver termination
impedance
RxZ
–
–
40
50
51
62.5
Ω
–
–
Signal detect level
RxSigDet
125
200 mVp-pdiff
7.1.1
Undershoot / Overshoot Specifications
The overshoot figures given in this section represent the maximum voltage that can be applied
Caution: If these limits are exceeded, damage to the device will occur.
Table 44. Undershoot / Overshoot Limits
Pin Type
Undershoot
Overshoot
2.5 V CMOS
3.3 V LVTTL
-0.60 V
-0.60 V
3.9 V
3.9 V
7.1.2
RGMII Electrical Characteristics
The RGMII signals (including MDIO/MDC) are based on 2.5V CMOS interface voltages, as
135
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 45. RGMII Power
Symbol
Parameter
Conditions
Min
Max
Units
VOH
VOL
VIH
VIL
IIH
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
IOH = -1.0 MA; V
= MIN
= MIN
2.0
VDD +.3
0.40
VDD +.3
.70
V
V
DD
IOL = 1.0 MA; V
GND -.3
DD
VIH > VIH_MIN; V
VIL < VIL_MAX; V
= MIN
= MIN
–
–
V
DD
DD
V
V
V
= MAX; VIN = 2.5V
= MAX; VIN = 0.4V
–
15
µA
µA
DD
DD
IIL
-15
–
Datasheet
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Document Number: 278757
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
7.2
SPI3 AC Timing Specifications
7.2.1
Receive Interface Timing
Figure 35. SPI3 Receive Interface Timing
RFCLK
THrenb
RENB
TSrenb
RDAT[31:0]
RPRY
TPrdat
TPrprty
TPrmod
TPrsop
TPreop
TPrerr
TPrval
TPrsx
RMOD
RSOP
REOP
RERR
RVAL
RSX
137
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 46. SPI3 Receive Interface Signal Parameters
Symbol
Parameter
Min
Max
Units
–
RFCLK frequency
RFCLK duty cycle
90
45
133
55
MHz
%
–
Tsrenb
Threnb
TPrdat
TPrprty
TPrsop
TPreop
TPrmod
TPrerr
TPrval
TPrsx
RENB setup time to RFCLK
RENB hold time to RFCLK
RFCLK High to RDAT valid
RFCLK High to RPRTY valid
RFCLK High to RSOP valid
RFCLK High to REOP valid
RFCLK High to RMOD valid
RFCLK High to RERR valid
RFCLK High to RVAL valid
RFCLK High to RSX valid
1.8
0.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
NOTES: Receive I/O Timing
1. When a setup time is specified between an input and a clock, the setup time is the time in nanoseconds
from the 1.4-volt point of the input to the 1.4-volt point of the clock.
2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from
the 1.4-volt point of the clock to the 1.4-volt point of the input.
3. Output propagation time is the time in nanoseconds from the 1.4-volt point of the reference signal to the
1.4-volt point of the output.
4. Maximum propagation delays are measured with a 30 pF load when operating OIF-SPI3 standard 104
MHz. Over-clocked rates of 125 MHz or higher are measured using a load of 20 pF.
Datasheet
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
7.2.2
Transmit Interface Timing
Figure 36. SPI3 Transmit Interface Timing
TFCLK
TENB
TStenb
THtenb
TDAT[31:0]
TPRTY
TStdat
THtdat
THtprty
THtmod
THtsop
TStrpty
TStmod
TStsop
TMOD[1:0]
TSOP
TEOP
TSteop
TSterr
TStadr
TStsx
THteop
THterr
THtadr
THtsx
TERR
TADR
TSX
DTPA
TPdtpa
STPA
PTPA
TPstpa
TPptpa
139
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Document Number: 278757
Revision Number: 009
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 47. SPI3 Transmit Interface Signal Parameters
Symbol
Parameter
Min
Max
Units
–
TFCLK frequency
TFCLK duty cycle
–
133
55
–
MHz
%
–
45
TStenb
THtenb
TStdat
THtdat
TStprty
THtprty
TStsop
THtsop
TSteop
THteop
TStmod
THtmod
TSterr
THterr
TStsx
TENB setup time to TFCLK
TENB hold time to TFCLK
TDAT[31:0] setup time to TFCLK
TDAT[31:0} hold time to TFCLK
TRPTY setup time to TFCLK
TPRTY hold time to TFCLK
TSOP setup time to TFCLK
TSOP hold time to TFCLK
TEOP setup time to TFCLK
TEOP hold time to TFCLK
TMOD setup time to TFCLK
TMOD hold time to TFCLK
TERR setup time to TFCLK
TERR hold time to TFCLK
TSX setup time to TFCLK
TSX hold time to TFCLK
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
–
–
–
–
–
–
–
THtsx
–
TStadr
THtadr
TPdtpa
TPstpa
TPptpa
TADR setup time to TFCLK
TADR hold time to TFCLK
TFCLK High to DTPA valid
TFCLK High to STPA valid
TFCLK High to PTPA valid
–
–
3.7
3.7
3.7
NOTES:Transmit I/O Timing:
1. When a setup time is specified between an input and a clock, the setup time is the time in nanoseconds
from the 1.4 V point of the input to the 1.4-volt point of the clock.
2. When a hold time is specified between an input and clock, the hold time is the time in nanoseconds from
the 1.4 V point of the clock to the 1.4-volt point of the input.
3. Output propagation delay time is the time in nanoseconds from the 1.4 V point of the reference signal to the
1.4 V point of the output.
Datasheet
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
7.3
RGMII AC Timing Specification
Figure 37. RGMII Interface Timing
TXC
(at Transmitter)
TSkewT
TD[3:0]
TXEN
TD[7:4]
TXERR
TD[3:0]
TSkewR
TX_CTL[n]
TXC
(at Receiver)
RXC
(at Transmitter)
TSkewT
RD[3:0]
RXDV
RD[7:4]
RXERR
RD[3:0]
TSkewR
RX_CTL
RXC
(at Receiver)
B3251-01
Table 48. RGMII Interface Timing Parameters
Symbol
Parameter
Min
Typ
Max
Unit
TskewT
TskewR
Tcyc
Data-to-Clock Output Skew (at Transmitter)
Data-to-Clock Input Skew (at Receiver)1
Clock Cycle Duration2
-500
1
0
–
500
2.8
8.8
55
ps
ns
ns
%
7.2
45
40
–
8
Duty_T
Duty_G
Tr/Tf
Duty Cycle for Gigabit2
50
50
–
Duty Cycle for 10/100T3
60
%
Rise/Fall Time (20–80%)
.75
ns
1. This implies that PC board design requires clocks to be routed so that an additional trace delay of greater
than 1.5 ns is added to the associated clock signal.
2. For 10 Mbps and 100 Mbps Tcyc scales to 400 ns +/– 40 ns and 40 ns +/– 4 ns respectively.
3. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet’s
clock domain, as long as minimum duty cycle is not violated and stretching occurs for no more than three
Tcyc of the lowest speed transitioned between.
141
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Document Number: 278757
Revision Number: 009
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
7.4
GMII AC Timing Specification
7.4.1
1000 Base-T Operation
7.4.1.1
1000 BASE-T Transmit Interface
Figure 38. 1000BASE-T Transmit Interface Timing
GTX_CLK
TXEn
t1
t2
TXD[7:0]
TXER
CPS
t3
t4
B0634-01
Table 49. GMII 1000BASE-T Transmit Signal Parameters
Symbol
Parameter
Min
Typ1
Max
Unit2
t1
t2
t3
t4
TXD[7:0], TXEN, TXER Set-up to TXC High
TXD[7:0], TXEN, TXER Hold from TXC High
TXEN sampled to CRS asserted
2.5
0.5
–
–
–
–
–
–
ns
ns
–
16
BT
BT
TXEN sampled to CRS de-asserted
–
16
1. Typical values are at 25oC and are for design aid only; not guaranteed and not subject to production
testing.
2. Bit Time (BT) is the duration of one bit as transferred to/from the PHY and is the reciprocal of bit rate. BT for
1000BASE-T = 10-9 or 1 ns.
Datasheet
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Document Number: 278757
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
7.4.1.2
1000BASE-T Receive Interface
Figure 39. 1000BASE-T Receive Interface Timing
RX_CLK
t1
RxDV
RXD[7:0]
CRS
t2
Table 50. GMII 1000BASE-T Receive Signal Parameters
Symbol
t1
t2
Parameter
Min
Typ1
Max
Unit2
RXD[7:0], RX_DV, RXER Setup to Rx_CLK High
RXD[7:0], RX_DV, RXER Hold after Rx_CLK High
2.0
0.0
–
–
–
–
ns
ns
1. Typical values are at 25oC and are for design aid only; not guaranteed and not subject to production
testing.
2. Bit Time (BT) is the duration of one bit as transferred to/from the PHY and is the reciprocal of bit rate. BT for
1000BASE-T = 10-9 or 1 ns.
143
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
7.5
SerDes AC Timing Specification
Figure 40. SerDes Timing Diagram
Table 51. SerDes Timing Parameters
Symbol
Parameter
Min
Max
Units
Tt
Rt
Tv
Rv
Transmit eye width
Receiver eye width
Transmit amplitude
Receiver amplitude
800
280
–
–
–
–
pS
pS
1000
200
mV
mV
Datasheet
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Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
7.6
MDIO AC Timing Specification
The MDIO Interface on the IXF1104 MAC can operate in two modes – low-speed and high-speed.
In low-speed mode, the MDC clock signal operates at a frequency of 2.5 MHz. In high-speed
7.6.1
MDC High-Speed Operation Timing
Figure 41. MDC High-Speed Operation Timing
24 ns
32 ns
(4 X 125 MHz clocks)
(3 X 125 MHz clocks)
MDC
56 ns (17.85 MHz)
7.6.2
MDC Low-Speed Operation Timing
Figure 42. MDC Low-Speed Operation Timing
200 ns
200 ns
(25 X 125 MHz clocks) (25 X 125 MHz clocks)
MDC
400 ns (2.5 MHz)
145
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
7.6.3
MDIO AC Timing
Figure 43. MDIO Write Timing Diagram
VMAX
MDC
VMIN
t1
t2
MDIO
Figure 44. MDIO Read Timing Diagram
VMAX
MDC
t3
MDIO
Table 52. MDIO Timing Parameters
Parameter
Symbol
Min
Typ1
Max
Units
Test Conditions
10
10
10
10
0
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
MDC = 17.8 MHz
MDC = 2.5 MHz
MDC = 17.8 MHz
MDC = 2.5 MHz
MDC = 17.8 MHz
MDC = 2.5 MHz
MDIO Setup before MDC.
t1
t2
t3
–
MDIO Hold after MDC.
–
42
300
MDC to MDIO Output delay
0
1. Typical values are at 25 oC and are for design aid only; not guaranteed and not subject to production
testing.
Datasheet
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Document Number: 278757
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
7.7
Optical Module and I2C AC Timing Specification
7.7.1
I2C Interface Timing
AC timing characteristics.
Figure 45. Bus Timing Diagram
t
HIGH
t
t
F
R
t
t
LOW
LOW
I2C_Clk
t
SU.STO
t
t
t
HD.DAT
t
SU.DAT
HD.STA
SV.SAT
I2C_Data In
t
BUF
t
t
DH
AA
I2C_Data Out
Figure 46. Write Cycle Diagram
I2C_Clk
8th
BIT
I2C_Data
ACK
WORD n
t
(1)
WR
STOP
CONDITION
START
CONDITION
Table 53. I2C AC Timing Characteristics (Sheet 1 of 2)
Symbol
Parameter
Min
Max
Units
f
t
t
t
t
t
t
Clock frequency, SCL
Clock pulse width low
Clock pulse width High
Noise suppression
-
100
kHz
µs
µs
µs
µs
µs
µs
SCL
4.7
4.0
LOW
HIGH
I
100
Clock low to data valid out
0.1
4.5
AA
Time the bus must be free before a new transmission starts
Start hold time
4.7
4.0
-
-
BUF
HD.STA
147
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Document Number: 278757
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 53. I2C AC Timing Characteristics (Sheet 2 of 2)
Symbol
tSU.STA
Parameter
Min
Max
Units
Start setup time
Data in hold time
Data in setup time
Inputs rise time
Inputs fall time
4.7
0
–
–
µs
µs
ns
µs
ns
µs
ns
ms
tHD.DAT
tSU.DAT
tR
200
–
–
1.0
300
–
tF
–
tSU.STO
tDH
Stop setup time
Data out hold time
Write cycle time
4.7
100
–
–
tWR
10
Datasheet
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
7.8
CPU AC Timing Specification
7.8.1
CPU Interface Read Cycle AC Timing
Figure 47. CPU Interface Read Cycle AC Timing
TCAS
TCAH
uPx_ADD[12:0]
TCRR
uPx_CsN
uPx_RdN
TCRH
uPx_Data[31:0]
uPx_RdyN
TCDRS
TCDRH
TCDRD
7.8.2
CPU Interface Write Cycle AC Timing
Figure 48. CPU Interface Write Cycle AC Timing
TCAS
TCAH
uPx_Add[12:0]
uPx_CsN
uPx_WrN
TCWL
TCWH
TCDWH
uPx_Data[31:0]
uPx_RdyN
TCDWS
TCYD
TCDWD
149
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 54. CPU Interface Write Cycle AC Signal Parameters
Symbol
Parameter
Min
Max
Tcas
Tcah
Tcrr
Address, chip select setup time
Address, chip select hold time
Ready assertion to read de-assertion
Read High width
5 ns
10 ns
10 ns
24 ns
10 ns
8 ns
–
–
–
Tcrh
–
Tcdrs
Tcdrh
Tcdrd
Tcwl
Read data setup time to ready assertion
Read data hold time after read de-assertion
Read data driving delay
–
32 ns
355 ns
–
24 ns
40 ns
16 ns
10 ns
5 ns
Write assertion width
Tcwh
Tcdws
Tcdwh
Tcdwd
Tcyd
Ready assertion to write assertion
Write data setup to write de-assertion
Write data hold time after ready assertion
Write data sampling delay
–
–
–
8 ns
32 ns
40 ns
Ready width in write cycle
24 ns
Datasheet
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
7.9
Transmit Pause Control AC Timing Specification
interface operates as an asynchronous interface relative to the main system clock (CLK125). There
is, however, a relationship between the TXPAUSEADD bus and the strobe signal (TXPAUSEFR).
Figure 49. Pause Control Interface Timing
TXPAUSEADD[2:0]
TxPauseFr
Tpw(min) = 16 ns
Thold(min) = 16 ns
Tsu(min) = 16 ns
000
001
010
011
100
: XON packet on all ports
: XOFF Port0
: XOFF Port1
: XOFF Port2
: XOFF Port3
110-101 : Reserved
111 : XOFF on all ports
Table 55. Transmit Pause Control Interface Timing Parameters
Symbol
Parameter
Min
Max
Units
Tsu
Tpw
TXPAUSEADD stable prior to TXPAUSEFR High
TXPAUSEFR pulse width
16
16
16
–
–
–
ns
ns
ns
Thold
TXPAUSEADD stable after TXPAUSEFR High
151
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
7.10
JTAG AC Timing Specification
Figure 50. JTAG AC Timing
Table 56. JTAG AC Timing Parameters
Symbol
Parameter
Min
Max
Units
Tjc
Tjh
TCLK cycle time
TCLK High time
TCLK low time
90
-
ns
ns
ns
ns
ns
ns
0.4 x Tjc 0.6 x Tjc
0.4 x Tjc 0.6 x Tjc
Tjl
Tjval
Tjsu
Tjsh
TCLK falling edge to TDO valid
TMS/TDI setup to TCLK
-
20
5
25
-
TMS/TDI hold from TCLK
-
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
7.11
System AC Timing Specification
Figure 51. System Reset AC Timing
Table 57. System Reset AC Timing Parameters
Symbol
Parameter
Min
Max
Units
Trw
Trt
Reset pulse width
1.0
-
-
µs
µs
Reset recovery time
200
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
7.12
LED AC Timing Specification
Figure 52. LED AC Interface Timing
Tcyc
Tlow
LED_CLK
LED_DATA
LED_LATCH
Thi
Tdatd
Thatl
Tlath
Table 58. LED Interface AC Timing Parameters
Symbol
Parameter
Min
Max
Units
Tcyc
Thi
LED_CLK cycle time
LED_CLK High time
LED_CLK low time
1.36
680
680
2
1.40
700
700
5
ms
µs
µs
ns
µs
µs
Tlow
Tdatd
Tlath
Tlatl
LED_CLK falling edge to LED_DATA valid
LED_CLK rising edge to LED_LATCH rising edge
LED_CLK falling edge to LED_LATCH falling edge
690
690
700
700
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
8.0
8.1
8.2
Register Set
The registers shown in this section provide access for configuration, alarm monitoring, and control
The registers are listed by ascending address in the table.
Document Structure
The following sections are structured to provide a general overview of the register map. Later
sections provide detailed descriptions of each register segment or bit.
All registers are accessed and addressed as 32-bit doublewords. When accessed using 8- or 16-bit
accesses, the CPU interface packs or unpacks the partial accesses into a 32-bit register value.
Graphical Representation
Figure 53 represents an overview of the IXF1104 MAC global control status registers that are used
double word.
Figure 53. Memory Overview Diagram
0x7FF
Global Configuration
- RX Block Configuration
- TX Block Configuration
0x500
0x480
0x400
0x380
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x300
0x280
0x200
0x180
Port 3 MAC Control & Statistics
Port 2 MAC Control & Statistics
Port 1 MAC Control & Statistics
Port 0 MAC Control & Statistics
0x100
0x080
0x000
B0744-01
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
8.3
Per Port Registers
Section 8.4 covers all of the registers that are replicated in each port of the IXF1104 MAC. These
registers perform an identical function in each port.
The address vector for the IXF1104 MAC is 11 bits wide. This allows for 7 bits of port-specific
access and a 4-bit vector to address each port and all global registers. The address format is shown
Figure 54. Register Overview Diagram
10
6
0
Port Select & Global Registers
Per-Port Registers
8.4
Register Map
IXF1104 MAC memory map details. Global control and status registers are used to configure or
report on all ports, and some registers are replicated on a per-port basis.
Note: All IXF1104 MAC registers are 32 bits.
Table 59. MAC Control Registers ($ Port Index + Offset) (Sheet 1 of 2)
Register
Bit Size
Mode1
Ref Page
Offset
32
32
32
32
32
32
32
32
R/W
R/W
R/W
R/W
R
–
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Reserved
R/W
R/W
R/W
FDFCAddressLow
32
32
R/W
R/W
0x08
0x09
FDFCAddressHigh
Reserved
32
32
32
–
R/W
R/W
R/W
RO
–
0x0A
0x0B
0x0C
0x0D
0x0E
32
R/W
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 59. MAC Control Registers ($ Port Index + Offset) (Sheet 2 of 2)
Register
Bit Size
Mode1
Ref Page
Offset
32
32
32
32
32
32
R/W
R/W
R/W
R/W
R/W
R/W
0x0F
0x10
0x11
0x12
0x13
0x14
32
R/W
0x15
32
32
32
32
RO
R/W
R/W
R/W
0x16
0x17
0x18
0x19
PortMulticastAddressLow
32
32
R/W
R/W
0x1A
0x1B
PortMulticastAddressHigh
Table 60. MAC RX Statistics Registers ($ Port Index + Offset) (Sheet 1 of 2)
Register
Bit Size
Mode1
Ref Page
Offset
RxOctetsTotalOK
RxOctetsBAD
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
RxUCPckts
RxMCPkts
RxBCPkts
RxPkts64Octets
RxPkts65to127Octets
RxPkts128to255Octets
RxPkts256to511Octets
RxPkts512to1023Octets
RxPkts1024to1518Octets
RxPkts1519toMaxOctets
RxFCSErrors
RxTagged
RxDataError
RxAlign Errors
RxLongErrors
RxJabberErrors
PauseMacControlReceivedCounter
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 60. MAC RX Statistics Registers ($ Port Index + Offset) (Sheet 2 of 2)
Register
Bit Size
Mode1
Ref Page
Offset
RxUnknownMacControlFrameCounter
RxVeryLongErrors
RxRuntErrors
32
32
32
32
32
32
32
R
R
R
R
R
R
R
0x33
0x34
0x35
0x36
0x37
0x38
0x39
RxShortErrors
RxCarrierExtendError
RxSequenceErrors
RxSymbolErrors
Table 61. MAC TX Statistics Registers ($ Port Index + Offset)
Register
Bit Size
Mode1
Ref Page
Offset
OctetsTransmittedOK
OctetsTransmittedBad
TxUCPkts
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
TxMCPkts
TxBCPkts
TxPkts64Octets
TxPkts65to127Octets
TxPkts128to255Octets
TxPkts256to511Octets
TxPkts512to1023Octets
TxPkts1024to1518Octets
TxPkts1519toMaxOctets
TxDeferred
TxTotalCollisions
TxSingleCollisions
TxMultipleCollisions
TxLateCollisions
TxExcessiveCollisionErrors
TxExcessiveDeferralErrors
TxExcessiveLengthDrop
TxUnderrun
TxTagged
TxCRCError
TxPauseFrames
TxFlowControlCollisionsSend
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 62. PHY Autoscan Registers ($ Port Index + Offset)
Register
Bit Size
Mode1
Ref Page
Offset
32
32
32
32
32
RO
RO
RO
RO
RO
0x60
0x61
0x62
0x63
0x64
32
32
32
32
RO
RO
RO
RO
–
0x65
0x66
0x67
Reserved
0x68 - 0x6F
Table 63. Global Status and Configuration Registers ($ 0x500 - 0X50C)
Register
Bit Size
Mode1
Ref Page
Address
Reserved
32
32
32
32
32
32
32
32
32
32
32
32
R/W
R/W
R/W
RO
–
0x500
0x501
0x502
0x503 - 0x504
0x505
Reserved
R/W
R/W
RO
–
0x506
0x507
R/W
R/W
R/W
R/W
R
0x508
0x509
0x50A
0x50B
0x50C
Table 64. RX FIFO Registers ($ 0x580 - 0x5BF) (Sheet 1 of 2)
Register
Bit Size
Mode1
Ref Page
Address
Reserved
32
32
32
32
32
32
32
32
R/W
R/W
R/W
R/W
RO
–
0x580
0x581
0x582
0x583
0x584 - 0x589
0x58A
R/W
R/W
R/W
0x58B
0x58C
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 64. RX FIFO Registers ($ 0x580 - 0x5BF) (Sheet 2 of 2)
Register
Bit Size
Mode1
Ref Page
Address
Reserved
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
R/W
RO
R
–
0x58D
0x58E - 0x593
0x594
RX FIFO Overflow Frame Drop Counter Port 0
RX FIFO Overflow Frame Drop Counter Port 1
RX FIFO Overflow Frame Drop Counter Port 2
RX FIFO Overflow Frame Drop Counter Port 3
Reserved
–
R
0x595
R
0x596
R
0x597
RO
R/W
R/W
R
0x598 - 0x59D
0x59E
–
Reserved
0x59F
0x5A0
R
0x5A1 - 0x5A5
0x5A2
RX FIFO Errored Frame Drop Counter Port 0
RX FIFO Errored Frame Drop Counter Port 1
RX FIFO Errored Frame Drop Counter Port 2
RX FIFO Errored Frame Drop Counter Port 3
Reserved
R
–
R
0x5A3
R
0x5A4
R
0x5A5
RO
0x5A6 - 0x5B1
32
R/W
0x5B2
Reserved
32
32
32
32
32
32
32
R/W
R
–
0x5B3
0x5B4 - 0x5B7
0x5B8
Reserved
R/W
R/W
R/W
R/W
R
–
0x5B9
0x5BA
0x5BB
0x5BC - 0x5BF
Table 65. TX FIFO Registers ($ 0x600 - 0x63E) (Sheet 1 of 2)
Register
Bit Size
Mode1
Ref Page
Address
TX FIFO High Watermark Port 0
TX FIFO High Watermark Port 1
TX FIFO High Watermark Port 2
TX FIFO High Watermark Port 3
Reserved
32
32
32
32
32
32
32
32
32
R/W
R/W
R/W
R/W
RO
–
0x600
0x601
0x602
0x603
0x604 - 0x609
0x60A
TX FIFO Low Watermark Port 0
TX FIFO Low Watermark Port 1
TX FIFO Low Watermark Port 2
TX FIFO Low Watermark Port 3
R/W
R/W
R/W
R/W
0x60B
0x60C
0x60D
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 65. TX FIFO Registers ($ 0x600 - 0x63E) (Sheet 2 of 2)
Register
Bit Size
Mode1
Ref Page
Address
Reserved
32
32
32
32
32
–
RO
R/W
R/W
R/W
R/W
RO
R
–
0x60E - 0x613
0x614
TX FIFO MAC Threshold Port 0
TX FIFO MAC Threshold Port 1
TX FIFO MAC Threshold Port 2
TX FIFO MAC Threshold Port 3
Reserved
–
0x615
0x616
0x617
0x618 - 0x61D
0x61E
TX FIFO Overflow/Underflow Event/Out of Sequence
Loop RX Data to TX FIFO
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
–
R/W
R/W
R
0x61F
TX FIFO Port Reset
0x620
TX FIFO Overflow Frame Drop Counter Port 0
TX FIFO Overflow Frame Drop Counter Port 1
TX FIFO Overflow Frame Drop Counter Port 2
TX FIFO Overflow Frame Drop Counter Port 3
TX FIFO Errored Frame Drop Counter Port 0
TX FIFO Errored Frame Drop Counter Port 1
TX FIFO Errored Frame Drop Counter Port 2
TX FIFO Errored Frame Drop Counter Port 3
Reserved
0x621
R
0x622
R
0x623
R
0x624
R
0x625
R
0x626
R
0x627
R
0x628
R
0x629 - 0x62C
0x62D
TX FIFO Occupancy Counter for Port 0
TX FIFO Occupancy Counter for Port 1
TX FIFO Occupancy Counter for Port 2
TX FIFO Occupancy Counter for Port 3
Reserved
R
–
R
0x62E
R
0x62F
R
0x630
R
0x631 - 0x63E
Table 66. MDIO Registers ($ 0x680 - 0x683)
Register
Bit Size
Mode1
Ref Page
Address
32
32
32
32
R/W
R/W
R/W
R/W
0x680
0x681
0x682
0x683
Table 67. SPI3 Registers ($ 0x700 - 0x716) (Sheet 1 of 2)
Register
Bit Size
Mode1
Ref Page
Address
32
32
R/W
R/W
0x700
0x701
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 67. SPI3 Registers ($ 0x700 - 0x716) (Sheet 2 of 2)
Register
Bit Size
Mode1
Ref Page
Address
Reserved
32
32
32
R
R
R
–
–
0x702 - 0x709
0x70A
Reserved
0x70B - 0x716
Table 68. SerDes Registers ($ 0x780 - 0x798)
Register
Bit Size
Mode1
Ref Page
Address
Reserved
32
32
32
32
32
32
RO
R/W
RO
–
–
0x780 - 0x783
0x784
Reserved
0x785 - 0x786
0x787
Reserved
R/W
RO
–
0x788 - 0x792
0x793
R/W
32
32
R/W
RO
–
0x794
Reserved
0x795 - 0x798
Table 69. Optical Module Registers ($ 0x799 - 0x79F)
Bit Size
Mode1
Address
Reserved
32
32
32
32
32
R
–
0x799
0x79A
R/W
R/W
RO
0x79B
0x79C - 0x79E
0x79F
R/W
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
8.4.1
MAC Control Registers
provide details on the control and status registers associated with each MAC port. The register
address is ‘Port_index + 0x**’, where the port index is set at any value from 0x0 through 0x5. All
registers are 32-bit. The unused bits of the registers are read-only and are set permanently to zero.
Table 70. Station Address ($ Port_Index +0x00 – +0x01)
Name
Description
Address
Type1
Default
Source MAC address bit 31-0.
This address is inserted in the source address
field when transmitting pause frames, and is also
used to compare against unicast pause frames
at the receiving side.
Station Address
Low
Port_Index
+ 0x00
R/W
0x0000000
Source MAC address bit 47-32.
This address is inserted in the source address
Station Address
field when transmitting pause frames, and is also Port_Index
R/W
0x00000000
used to compare against unicast pause frames
at the receiving side. Bits 15:0 of this register are
assigned to bits 47:32 of the station address.
+ 0x01
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 71. Desired Duplex ($ Port_Index + 0x02)
Bit
Name
Description
Type1
Default
Register Description: Chooses between half-duplex and full-duplex operation in RGMII
100 Mbps or 10 Mbps mode only.
0x00000001
0x00000000
This register must be set to the default value of 1 and must not be changed when operating in
RGMII 1000 Mbps, GMII, or fiber mode.
31:1 Reserved
Reserved
R
0 = Half-duplex
1 = Full-duplex
NOTE: Half-duplex operation applies only to
10/100 Mbps speed on copper media in RGMII
mode only. Gigabit speed on either media requires
full-duplex.
0
Duplex Select
R/W
1
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 72. FD FC Type ($ Port_Index + 0x03)
Name
Description
Address
Type1
Default
This value fills the Type field of the Transmitted
Pause frames. Only bits 15:0 of this register are
used.
Port_Index
+ 0x03
FD FC Type
R/W
0x00008808
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Table 73. Collision Distance ($ Port_Index + 0x05)
Name
Description
Address
Type1
Default
This is a 10-bit value that sets the limit for late
collision. Collisions happening at byte times
beyond the configured value are considered to be
late collisions. (Only valid in half-duplex).
Collision
Distance
Port_Index
+ 0x05
R/W
0x00000043
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
Table 74. Collision Threshold ($ Port_Index + 0x06)
Name
Description
Address
Type1
Default
This is a 4-bit value that sets the limit for
excessive collisions. When the number of
transmission attempts performed for a packet
exceeds this value, it is considered to be an
excessive collision and the frame is dropped.
(Only valid in half-duplex).
Collision
Threshold
Port_Index
+ 0x06
R/W
0x0000000F
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
Table 75. FC TX Timer Value ($ Port_Index + 0x07)
Name
Description
Address
Type1
Default
The 16-bit pause length inserted in the flow
control pause frame sent to the receiving
station. The value is in 512-bit times.
FC TX Timer
Value
Port_Index
+ 0x07
R/W
0x0000005E
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 76. FD FC Address ($ Port_Index + 0x08 – + 0x09)
Name
Description
Address
Type1
Default
The lowest 32 bits of the 48-bit globally
FD FC Address Low assigned multicast pause frame destination
Port_Index
+ 0x08
R/W
0xC2000001
address.
The highest 16 bits (47:32) of the globally
assigned multicast pause frame destination
address. The higher 16-bit address is
Port_Index
+ 0x09
FD FC Address High
R/W
0x00000180
derived from bits 15:0 of this register.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 77. IPG Receive Time 1 ($ Port_Index + 0x0A)
Name
Description
Address
Type1
Default
This timer is used during half-duplex operation
when there is a packet waiting for
transmission from the MAC. This timer starts
after CRS is de-asserted. If CRS is asserted
during this time, no transmission is initiated
and the counter restarts once CRS is de-
asserted again.
Port_Index
+ 0x0A
IPG Receive Time 1
R/W
0x00000008
The value specified in this register is
calculated as follows: (register_value * 8) =
RXIPG1 in terms of bit times. Therefore, a
default value of 8 gives the following: (8 * 8 =
64 bit times for the default).
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 78. IPG Receive Time 2 ($ Port_Index + 0x0B)
Name
Description
Address
Type1
Default
This is only used in half-duplex operation. It
starts counting at the same time as RXIPG1.
Once RXIPG1 expires, a frame is transmitted
when RXIPG2 expires regardless of the CRS
value. If CRS is asserted before RXIPG1
expires, no transmission occurs and both
RXIPG1 an RXIPG2 are reset once CRS is
de-asserted again.
Port_Index
+ 0x0B
IPG Receive Time 2
R/W
0x00000007
The value specified in this register is
calculated as follows: (register_value +5) * 8 =
RXIPG2 in terms of bit times. Therefore, a
default of 7 gives the following:
(7+5) * 8 = 96 bit times for default.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 79. IPG Transmit Time ($ Port_Index + 0x0C)
Name
Description
Address
Type1
Default
This is a 10-bit value configuring IPG time for
back-to-back transmissions.
The value specified in this register is
calculated as follows: (register_value +4) * 8 = Port_Index
IPG Transmit Time
R/W
0x00000008
TXIPG in terms of bit times. Therefore, a
default value of 8 gives the following:
(8+4) * 8 = 96 bit times for the default.
+ 0x0C
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Table 80. Pause Threshold ($ Port_Index + 0x0E)
Name
Description
Address
Type1
Default
When a pause frame has been sent, an internal
timer checks when the next pause frame must
be scheduled for transmission to keep the link
partner in pause mode (this is required only if
the flow control has to be extended for one more
session). The pause threshold value is a 16-bit
value that sets the time in terms of 512-bit
quantum after the previous pause frame when
the next pause frame has to be sent. This
ensures that the link partner is kept in pause
mode continuously.
Pause
Threshold
Port_Index
+ 0x0E
R/W
0x0000002F
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 81. Max Frame Size (Addr: Port_Index + 0x0F)
Name
Description
Address
Type1
Default
This is a 14-bit value configuring the maximum
frame size the MAC can receive or transmit
without activating any error counters, and
without truncation.
This value is excluding the 4-byte CRC in the
transmit direction when CRC append is
enabled in the MAC. Hence, this value has to
be set four bytes less when CRC append is
enabled in the MAC.
Port_Inde
x + 0x0F
Max Frame Size
R/W
0x000005EE
The maximum frame size is internally adjusted
by +4 if the frame is VLAN tagged.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Table 82. MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)
Bit
Name
Description
Type1
Default
Register Description – MAC IF Mode: Determines the MAC operation frequency and mode
per port.
Interface Mode Change Enable Ports 0 - 3 ($0x794)" to ensure a safe transition to a new
operational mode. Changes to this register must follow a proper sequence. Refer to Section
6.1, “Change Port Mode Initialization Sequence” on page 130 for the proper sequence for
changing the port mode and speed.
0x00000003
0x00000000
31:3 Reserved
Reserved
R
These bits are used to define the clock mode and
the RGMII/GMII mode of operation.
000 = Reserved
001 = Reserved
010 = GMII 1000 Mbps operation
011 = Reserved
2:0
Port Mode
R/W
011
100 = RGMII 10 Mbps operation
101 = RGMII 100 Mbps operation
11x = RGMII 1000 Mbps operation
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 83. Flush TX ($ Port_Index + 0x11)
Bit
Name
Description
Type1
Default
Register Description: Used to flush all TX data. It is used if all traffic sent to a port should be
stopped.
0x00000000
0x00000000
0
31:1 Reserved
Flush TX
Reserved
R
This bit flushes all TX data and is used if all the
traffic sent to a port should be stopped.
0
R/W
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Table 84. FC Enable ($ Port_Index + 0x12)
Bit
Name
Description
Type1
Default
Register Description: Indicates which flow control mode is used for the RX and TX MAC.
0x00000007
0x00000000
31:3 Reserved
Reserved
R
When TX HDFC is enabled (half-duplex mode
only), the MAC generates deliberate collisions on
incoming packets when the RX FIFO occupancy
crosses the High Watermark (flow control).
2
TX HDFC
R/W
1
1
0 = Disable TX half-duplex flow control
1 = Enable TX half-duplex flow control
0 = Disable TX full-duplex flow control [the MAC
will not generate internally any flow control
frames based on the RX FIFO watermarks or
the Transmit Pause Control interface
1 = Enable TX full-duplex flow control [enables
the MAC to send flow control frames to the
link partner based on the RX FIFO
1
TX FDFC
R/W
programmable watermarks or the Transmit
Pause Control interface]
0 = Disable RX full-duplex flow control [the MAC
will not respond to flow control frames sent to
it by the link partner]
1 = Enable RX full-duplex flow control [MAC will
respond to flow control frames sent by the link
partner and will stop packet transmission for
the time specified in the flow control frame]
0
RX FDFC
R/W
1
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 85. FC Back Pressure Length ($ Port_Index + 0x13)
Name
Description
Address
Type1
Default
This register sets number the byte cycles
for which the collision has to be applied.
The 6-bit configuration holds the value in
bytes, which applies to the minimum
length/duration of back pressure in half-
duplex mode. Flow control in the receive
path is executed by deliberately colliding
the incoming packets in half-duplex mode.
FC Back Pressure
Length
Port Add +
0x13
R/W
0x0000000C
Register bits 5:0 are used alone.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Table 86. Short Runts Threshold ($ Port_Index + 0x14)
Name
Description
Address
Type1
Default
The 5-bit configuration holds the value in bytes,
which applies to the threshold in determining
between runts and short. The bits 4:0 of this
register are alone used.
A received packet is reported as a short packet
when the length (excluding Preamble and
SFD) is less than this value.
A received packet is reported as a runt packet
when the length (excluding Preamble and
SFD) is equal to or greater than this value and
less than 64-bytes.
Short Runts
Threshold
Port_Index +
0x14
R/W
0x00000008
NOTE: This register is only relevant when the
IXF1104 MAC port is configured for
copper operation (the line side
interface is configured for either RGMII
or GMII).
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 87. Discard Unknown Control Frame ($ Port_Index + 0x15)
Bit
Name
Description
Type1
Default
Register Description: Discards or forwards unknown control frames. Known control frames
are pause frames.
0x00000000
0x00000000
0
31:1 Reserved
Reserved
R
Discard Unknown
Control Frame
0 = Forward unknown control frames
1 = Discard unknown control frames
0
R/W
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 88. RX Config Word ($ Port_Index + 0x16) (Sheet 1 of 2)
Bit
Name
Description
Type1
Default
Register Description: This register is used in fiber MAC only for auto-negotiation and to report
the receive status. The lower 16 bits of this register are the “config_reg” received from the link
partner, as described in IEEE 802.3 2000 Edition, Section 37.2.1.
0x00000000
0x000
31:22 Reserved
Reserved
RO
Auto-negotiation complete. This bit remains
cleared from the time auto-negotiation is reset until
auto-negotiation reaches the “LINK_OK” state. It
remains set until auto-negotiation is disabled or
restarted.
21
An_complete
RO
0
This bit is only valid if auto-negotiation is enabled.
0 = Loss of synchronization
1 = Bit synchronization. The bit remains Low until
20
Rx Sync
RO
0
the register is read.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
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Table 88. RX Config Word ($ Port_Index + 0x16) (Sheet 2 of 2)
Bit
Name
Description
Type1
Default
0 = Receiving idle/data stream
1 = Receiving /C/ ordered sets
19
RX Config
RO
0
0 = RxConfigWord has changed since last read
1 = RxConfigWord has not changed since last
read.
18
Config Changed
R
0
This bit remains High until the register is read.
0 = Have not received an invalid symbol
1 = Have received an invalid symbol
17
16
Invalid Word
RO
RO
0
0
This bit remains High until the register is read.
0 = Device is not receiving idle characters; carrier
sense is true.
1 = Device is receiving idle characters; carrier
Carrier Sense
sense is false.
15
14
Next Page
Reserved
Next Page request
Reserved
RO
RO
0
0
Remote fault definitions:
00 = No error, link okay
01 = Offline
13:122 Remote Fault [1:0]
R/W
00
10 = Link failure
11 = Auto-negotiation_Error
11:9
8
Reserved
Reserved
RO
RO
000
0
Asym Pause
Asym Pause. The ability to send pause frames.
Sym Pause. The ability to send and receive pause
frames.
7
Sym Pause
RO
0
6
5
Half Duplex
Full Duplex
Reserved
Half-duplex
Full-duplex
Reserved
RO
RO
RO
0
0
4:0
0x0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
Table 89. TX Config Word ($ Port_Index + 0x17) (Sheet 1 of 2)
Bit
Name
Description
Type1
Default
Register Description: This register is used in fiber MAC for auto-negotiation only. The
contents of this register are sent as the config_word. The contents of this register are the
“config_reg” sent to the link partner, as described in IEEE 802.3 2000 Edition, subclause 37.2.1.
0x000001A0
31:16 Reserved
Reserved
RO
R/W
R/W
0x0000
15
14
Next Page
Reserved
Next Page request
Write as 0, ignore on read
0
0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
NOTE: A value of 0x0 must be written to all reserved bits of the “TX Config Word ($ Port_Index + 0x17)”
Register.
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Table 89. TX Config Word ($ Port_Index + 0x17) (Sheet 2 of 2)
Bit
Name
Description
Type1
Default
Remote fault definitions:
00 = No error, link okay
01 = Offline
13:122 Remote Fault [1:0]
R/W
00
10 = Link failure
11 = Auto-negotiation_Error
11:9
8
Reserved
Write as 0, ignore on Read
R/W
R/W
000
1
Asym Pause
Asym Pause. The ability to send pause frames.
Sym Pause. The ability to send and receive pause
frames.
7
Sym Pause
R/W
1
6
5
Half Duplex
Full Duplex
Reserved
Half-duplex
R/W
R/W
R/W
0
1
Full-duplex
4:0
Write as 0, ignore on read
0x00
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
NOTE: A value of 0x0 must be written to all reserved bits of the “TX Config Word ($ Port_Index + 0x17)”
Register.
Table 90. Diverse Config Write ($ Port_Index + 0x18) (Sheet 1 of 2)
Bit
Name
Description
Type1
Default
Register Description: This register contains various configuration bits for general use.
0x00110D
0x0000
0x0000
1
31:19 Reserved
18:13 Reserved
Reserved
RO
R/W
R/W
R/W
R/W
Write as 0, ignore on Read.
Write as 1, ignore on Read.
Write as 0, ignore on Read.
Write as 1, ignore on Read.
12
11-9 Reserved2
Reserved2
0x0
8
Reserved2
1
0 = Normal operation
1 = Enable padding of undersized packets
7
pad_enable
R/W
R/W
0
0
NOTE: Assertion of this bit results in the
automatic addition of a CRC to the
padded packet.
0 = Normal operation
1 = Enable automatic CRC appending
6
crc_add
Enable auto-negotiation (used for fiber mode only)
to be performed by the hardware state machines
in the MAC.
The hardware auto-negotiation (AN) state
machine controls the config words transmitted
when this bit is set.
NOTE: In copper mode, this bit must be set to 0
(reserved).
5
AN_enable
Reserved
R/W
R/W
0
0
42
Write as 0, ignore on Read.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
2. Reserved bits must be written to the default value for proper operation.
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Table 90. Diverse Config Write ($ Port_Index + 0x18) (Sheet 2 of 2)
Bit
Name
Description
Type1
Default
3:22 Reserved
Write as 1, ignore on Read.
Write as 0, ignore on Read.
Write as 1, ignore on Read.
R/W
R/W
R/W
11
0
12
02
Reserved
Reserved
1
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
2. Reserved bits must be written to the default value for proper operation.
Table 91. RX Packet Filter Control ($ Port_Index + 0x19) (Sheet 1 of 2)
Bit
Name
Description
Type1
Default
Register Description: This register allows for specific packet types to be marked for filtering
and is used in conjunction with the “RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 0x00000000
31:6 Reserved
Reserved
0
This bit enables a Global filter on frames with a
CRC Error.
0 = When CRC Error Pass = 0, all frames with a
CRC Error are marked as bad.2
1 = Frames with a CRC Error are not marked as
bad and are passed to the SPI3 interface for
transfer as good frames, regardless of the
state of the bits in the “RX FIFO Errored
5
CRC Error Pass
R/W
0
NOTE: When the CRC Error Pass Filter bit = 0, it
takes precedence over the other filter bits.
Any packet, whether is a Pause, Unicast,
Multicast or Broadcast packet with a CRC
error, is marked as a bad frame when
CRC Error Pass = 0
This bit enables a Global filter on Pause frames.
0 = All pause frames are dropped.2
1 = All pause frames are passed to the SPI3
Interface.
4
3
Pause Frame Pass
R/W
R/W
0
0
NOTE: Pause Frames can only be filtered if
RXFD flow control is enabled in the “FC
This bit enables a global filter on VLAN frames.
0 = All VLAN frames are passed to the SPI3
Interface.
VLAN Drop En
1 = All VLAN frames are dropped.2
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
2. Used in conjunction with the “RX FIFO Errored Frame Drop Enable ($0x59F)” on page 196. This allows the
frame to be dropped in the RX FIFO. Otherwise, the frame is sent out the SP3 interface and may be
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Table 91. RX Packet Filter Control ($ Port_Index + 0x19) (Sheet 2 of 2)
Bit
Name
Description
Type1
Default
This bit enables a Global filter on broadcast
frames.
2
B/Cast Drop En
R/W
0
0 = All broadcast frames are passed to the SPI3
Interface.
1 = All broadcast frames are dropped.2
This bit enables a filter on multicast frames.
0 = All muticast frames are good and passed to
the SPI3 Interface.
1 = Only multicast frames with a destination
address that matches the
1
M/Cast Match En
R/W
0
PortMulticastAddress are forwarded. All other
muticast frames are dropped.2
This bit enables a filter on unicast frames.
0 = All unicast frames are good and are passed
to the SPI3 Interface.
1 = Only unicast frames with a Destination
Address that matches the Station Address
are forwarded. All other unicast frames are
dropped.2
0
U/Cast Match En2
R/W
0
NOTE: The VLAN filter overrides the unicast filter.
Therefore, a VLAN frame cannot be
filtered based on the unicast address.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
2. Used in conjunction with the “RX FIFO Errored Frame Drop Enable ($0x59F)” on page 196. This allows the
frame to be dropped in the RX FIFO. Otherwise, the frame is sent out the SP3 interface and may be
optionally signaled with an RERR (see bit 0 of “SPI3 Receive Configuration ($0x701)”.
Table 92. Port Multicast Address ($ Port_Index +0x1A – +0x1B)
Name
Description
Address
Type*
Default
This address compares against multicast frames
at the receiving side if multicast filtering is
enabled.
Port Multicast
Address Low
Port_Index
+ 0x1A
R/W
0x0000000
This register contains bits 31:0 of the address.
This address compares against multicast frames
at the receiving side if Multicast filtering is
enabled.
Port Multicast
Address High
Port_Index
+ 0x1B
R/W
0x00000000
This register contains bits 47:32 of the address.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
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8.4.2
MAC RX Statistics Register Overview
The MAC RX Statistics registers contain the MAC receiver statistic counters and are cleared when
read. The software polls these registers and accumulates values to ensure that the counters do not
wrap. The 32-bit counters wrap after approximately 30 seconds.
Table 93 covers the RX statistics for the four MAC ports. Port_Index is the port number (0, 1, 2, or
3).
Table 93. MAC RX Statistics ($ Port_Index + 0x20 – + 0x39) (Sheet 1 of 4)
Name
Description
Address
Type1
Default
Counts the bytes received in all legal frames,
including all bytes from the destination MAC
address to and including the cyclic redundancy
check (CRC). The initial preamble and Start of
Frame Delimiter (SFD) bytes are not counted.
Port_Index
+ 0x20
RxOctetsTotalOK
R
0x00000000
Counts the bytes received in all bad frames with
legal size (frames with CRC error, alignment
errors, or code violations), including all bytes
from the destination MAC address to (and
including) the CRC. The initial preamble and
SFD bytes are not counted. Frames with illegal
size do not add to this counter (shorts, runts,
longs, jabbers, and very longs).
Port_Index
+ 0x21
RxOctetsBAD2
R
0x00000000
Note: This register does not count octets on
undersized received packets.
The total number of unicast packets received
(excluding bad packets).
Note: This count includes non-pause control and
VLAN packets, which are also counted in other
counters. These packet types are counted twice.
Take care when summing register counts for
reporting Management Information Base (MIB)
information.
Port_Index
+ 0x22
RxUCPkts
RxMCPkts
R
R
0x00000000
0x00000000
The total number of multicast packets received
(excluding bad packets)
Note: This count includes pause control packets,
which are also counted in the PauseMacControl-
ReceivedCounter. These packet types are
counted twice. Take care when summing register
counts for reporting MIB information.
Port_Index
+ 0x23
The total number of Broadcast packets received
(excluding bad packets).
Port_Index
+ 0x24
RxBCPkts
R
R
0x00000000
0x00000000
The total number of packets received (including
bad packets) that were 64 octets in length.
Incremented for tagged packets with a length of
64 bytes, including tag field.
Port_Index
+ 0x25
RxPkts64Octets
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
2. When sending in large frames, the counters can only handle certain limits. The behavior of the LongErrors
and VeryLongErrors counters is as follows: VeryLongErrors counts frames that are 2*maxframesize,
dependent upon where maxframesize is set. If maxframesize sets greater than half of the available count in
RxOctetsBad (2^14-1), VeryLongErrors is never incremented, but LongErrors is incremented. This is due to
a limitation in the counter size, which means that an accurate count will not occur in the RxOctetsBAD
counter if the frame is larger than 2^14-1.
3. This register is relevant only when configured for copper operation.
4. This register is relevant only when configured for fiber operation (line side interface is SerDes).
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Table 93. MAC RX Statistics ($ Port_Index + 0x20 – + 0x39) (Sheet 2 of 4)
Name
Description
Address
Type1
Default
The total number of packets received (including
bad packets) that were 65-127 octets in length.
Incremented for tagged packets with a length of
65-127 bytes, including tag field.
RxPkts65to127
Octets
Port_Index
+ 0x26
R
0x00000000
The total number of packets received (including
bad packets) that were 128-255 octets in length.
Incremented for tagged packets with a length of
128-255 bytes, including tag field.
RxPkts128t0255
Octets
Port_Index
+ 0x27
R
R
R
R
0x00000000
0x00000000
0x00000000
0x00000000
The total number of packets received (including
bad packets) that were 256-511 octets in length.
Incremented for tagged packets with a length of
256-511 bytes, including tag field.
RxPkts256to511
Octets
Port_Index
+ 0x28
The total number of packets received (including
RxPkts512to1023O bad packets) that were 512-1023 octets in
Port_Index
+ 0x29
ctets
length. Incremented for tagged packets with a
length of 512-1023 bytes, including tag field.
The total number of packets received (including
RxPkts1024to1518 bad packets) that were 1024-1518 octets in
Port_Index
+ 0x2A
Octets
length. Incremented for tagged packet with a
length between 1024-1522, including the tag.
The total number of packets received (including
bad packets) that were greater than 1518 octets
in length. Incremented for tagged packet with a
length between 1523-max frame size, including
the tag.
RxPkts1519toMaxO
ctets
Port_Index
+ 0x2B
R
R
0x00000000
0x00000000
Number of frames received with legal size, but
with wrong CRC field (also called Frame Check
Sequence (FCS) field).
NOTE: Legal size is 64 bytes through the value
programmed in the “Max Frame Size
Port_Index
+ 0x2C
RxFCSErrors
Number of OK frames with VLAN tag.
(Type field = 0x8100)
Port_Index
+ 0x2D
RxTagged
R
R
0x00000000
0x00000000
Number of frames received with legal length,
containing a code violation (signaled with
RX_ERR on RGMII).
Port_Index
+ 0x2E
RxDataError3
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
2. When sending in large frames, the counters can only handle certain limits. The behavior of the LongErrors
and VeryLongErrors counters is as follows: VeryLongErrors counts frames that are 2*maxframesize,
dependent upon where maxframesize is set. If maxframesize sets greater than half of the available count in
RxOctetsBad (2^14-1), VeryLongErrors is never incremented, but LongErrors is incremented. This is due to
a limitation in the counter size, which means that an accurate count will not occur in the RxOctetsBAD
counter if the frame is larger than 2^14-1.
3. This register is relevant only when configured for copper operation.
4. This register is relevant only when configured for fiber operation (line side interface is SerDes).
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Table 93. MAC RX Statistics ($ Port_Index + 0x20 – + 0x39) (Sheet 3 of 4)
Name
Description
Address
Type1
Default
Frames with a legal frame size, but containing
less than eight additional bits. This occurs when
the frame is not byte aligned. The CRC of the
frame is wrong when the additional bits are
stripped. If the CRC is OK, then the frame is not
counted but treated as an OK frame. This
counter increments in 10 Mbps or 100 Mbps
RGMII mode only.
Port_Index
+ 0x2F
RxAlignErrors3
R
0x00000000
NOTE: This counter increments in 10 or 100
Mbps RGMII mode only.
Frames bigger than the maximum allowed, with
both OK CRC and the integral number of octets.
Default maximum allowed is 1518 bytes
untagged and 1522 bytes tagged, but the value
can be changed by a register.
Port_Index
+ 0x30
RxLongErrors2
R
0x00000000
Frames bigger than the larger of
2*maxframesize and 50,000 bits are not counted
here, but they are counted in the VeryLongError
counter.
Frames bigger than the maximum allowed, with
either a bad CRC or a non-integral number of
octets. The default maximum allowed is 1518
bytes untagged and 1522 bytes tagged, but the
value can be changed by a register.
Port_Index
+ 0x31
RxJabberErrors
R
R
0x00000000
0x00000000
Frames bigger than the larger of
2*maxframesize and 50,000 bits are not counted
here, but they are counted in the VeryLongError
counter.
Number of Pause MAC control frames received.
This statistic register increments on any valid 64-
byte pause frame with a valid CRC and also
increments on a 64-byte pause frame with an
invalid CRC if bit 5 of the “RX Packet Filter
Control ($ Port_Index + 0x19)” is set to 1.
RxPauseMacContr
olReceivedCounter
Port_Index
+ 0x32
RxUnknownMac
ControlFrame
Counter
Number of MAC control frames received with an
op code different from 0001 (Pause).
Port_Index
+ 0x33
R
R
0x00000000
0x00000000
Frames bigger than the larger of
2*maxframesize and 50,000 bits
Port_Index
+ 0x34
RxVeryLongErrors2
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
2. When sending in large frames, the counters can only handle certain limits. The behavior of the LongErrors
and VeryLongErrors counters is as follows: VeryLongErrors counts frames that are 2*maxframesize,
dependent upon where maxframesize is set. If maxframesize sets greater than half of the available count in
RxOctetsBad (2^14-1), VeryLongErrors is never incremented, but LongErrors is incremented. This is due to
a limitation in the counter size, which means that an accurate count will not occur in the RxOctetsBAD
counter if the frame is larger than 2^14-1.
3. This register is relevant only when configured for copper operation.
4. This register is relevant only when configured for fiber operation (line side interface is SerDes).
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 93. MAC RX Statistics ($ Port_Index + 0x20 – + 0x39) (Sheet 4 of 4)
Name
Description
Address
Type1
Default
The total number of packets received that are
less than 64 octets in length, but longer than or
equal to 96 bit times, which corresponds to a 4-
byte frame with a well-formed preamble and
SFD. This is the shortest fragment and can be
transmitted in case of a collision event on a half-
duplex segment. This counter indicates fragment
sizes, which is expected on half-duplex
segments but not on full-duplex links, and the
counter is only fully updated after receipt of a
good frame following a fragment.
NOTE: The ShortRuntsThreshold register
Port_Index
+ 0x35
RxRuntErrors3
controls the byte count used to
R
0x00000000
determine the difference between Runts
and Shorts and therefore controls which
counter is incremented for a given frame
size. This counter is only updated after
receipt of two good frames.
NOTE: This counter is only valid when the
selected port within the IXF1104 MAC is
operating in copper (RGMII or GMII)
mode. The RuntError counter is not
updated when the selected port within
the IXF1104 MAC is configured to
operated in fiber (SerDes) mode.
The total number of packets received that are
less than 96 bit times, which corresponds to a 4-
byte frame with a well-formed preamble and
SFD. This counter indicates fragment sizes
illegal in all modes and is only fully updated after
reception of a good frame following a fragment.
NOTE: This register is only relevant when the
IXF1104 MAC port is configured for
Port_Index
+ 0x36
RxShort Errors3
R
0x00000000
copper operation (the line side interface
is configured for either RGMII or GMII
operation). This register will not
increment when the IXF1104 MAC port
is configured for fiber operation using
the SerDes interface.
RxCarrier Extend
Error
Port_Index
+ 0x37
Not applicable.
R
R
R
0x00000000
0x00000000
0x00000000
Records the number of sequencing errors that
occur in fiber mode.
Port_Index
+ 0x38
RxSequenceErrors4
RxSymbolErrors4
Records the number of symbol errors
encountered by the PHY.
Port_Index
+ 0x39
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
2. When sending in large frames, the counters can only handle certain limits. The behavior of the LongErrors
and VeryLongErrors counters is as follows: VeryLongErrors counts frames that are 2*maxframesize,
dependent upon where maxframesize is set. If maxframesize sets greater than half of the available count in
RxOctetsBad (2^14-1), VeryLongErrors is never incremented, but LongErrors is incremented. This is due to
a limitation in the counter size, which means that an accurate count will not occur in the RxOctetsBAD
counter if the frame is larger than 2^14-1.
3. This register is relevant only when configured for copper operation.
4. This register is relevant only when configured for fiber operation (line side interface is SerDes).
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
8.4.3
MAC TX Statistics Register Overview
The MAC TX Statistics registers contain all the MAC transmit statistic counters and are cleared
when read. The software must poll these registers to accumulate values and to ensure that the
counters do not wrap. The 32-bit counters wrap after approximately 30 seconds.
Table 94. MAC TX Statistics ($ Port_Index +0x40 – +0x58) (Sheet 1 of 4)
Name
Description
Address
Type1
Default
Counts the bytes transmitted in all legal
frames. The count includes all bytes
from the destination MAC address to
and including the CRC. The initial
preamble and SFD bytes are not
counted. Any initial collided
Port_Index +
0x40
OctetsTransmittedOK
R
0x00000000
transmission attempts before a
successful frame transmission do not
add to this counter.
Counts the bytes transmitted in all bad
frames. The count includes all bytes
from the destination MAC address to
and including the CRC. The initial
preamble and SFD bytes are not
counted.
Late collision counted: The count is
close to the actual number of bytes
transmitted before the frame is
discarded.
Excessive collision counted: The count
is close to the actual number of bytes
transmitted before the frame is
discarded.
Port_Index +
0x41
OctetsTransmittedBad
R
0x00000000
TX under-run counted: The count is
expected to match the number of bytes
actually transmitted before the frame is
discarded.
TX CRC error counted: All bytes not
sent with success are counted by this
counter.
Any initial collided transmission
attempts before a successful frame
transmission do not add to this counter.
The total number of unicast packets
transmitted (excluding bad packets).
Port_Index +
0x42
TxUCPkts
TxMCPkts
R
R
0x00000000
0x00000000
The total number of multicast packets
transmitted (excluding bad packets).
NOTE: This count includes pause
control packets, which are also
counted in the
Port_Index +
0x43
TxPauseFrames Counter.
Thus, these types of packets
are counted twice. Take care
when summing register counts
for reporting MIB information.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 94. MAC TX Statistics ($ Port_Index +0x40 – +0x58) (Sheet 2 of 4)
Name
Description
Address
Type1
Default
The total number of broadcast packets
transmitted (excluding bad packets).
Port_Index +
0x44
TxBCPkts
R
0x00000000
The total number of packets
transmitted (including bad packets) that
were 64 octets in length. Incremented
for tagged packets with a length of 64
bytes, including tag field.
Port_Index +
0x45
TxPkts64Octets
R
R
0x00000000
0x00000000
The total number of packets
transmitted (including bad packets) that
were 65-127 octets in length.
Incremented for tagged packets with a
length of 65-127 bytes, including tag
field.
Port_Index +
0x46
Txpkts65to127Octets
The total number of packets
transmitted (including bad packets) that
were 128-255 octets in length.
Incremented for tagged packets with a
length of 128-255 bytes, including tag
field.
Port_Index +
0x47
Txpkts128to255Octets
Txpkts256to511Octets
Txpkts512to1023Octets
Txpkts1024to1518Octets
Txpkts1519toMaxOctets
R
R
R
R
R
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
The total number of packets
transmitted (including bad packets) that
were 256-511 octets in length.
Incremented for tagged packets with a
length of 256-511 bytes, including tag
field.
Port_Index +
0x48
The total number of packets
transmitted (including bad packets) that
were 512-1023 octets in length.
Incremented for tagged packets with a
length of 512-1023 bytes, including tag
field.
Port_Index +
0x49
The total number of packets
transmitted (including bad packets) that
were 1024-1518 octets in length.
Incremented for tagged packet with a
length between 1024-1522, including
the tag.
Port_Index +
0x4A
The total number of packets
transmitted (including bad packets) that
were greater than 1518 octets in
length. Incremented for tagged packet
with a length between 1523 - max fame
size, including the tag.
Port_Index +
0x4B
Number of times the initial transmission
attempt of a frame is postponed due to
another frame already being
transmitted on the Ethernet network.
TxTotalCollisions.
Port_Index +
0x4C
TxDeferred
R
R
0x00000000
0x00000000
NOTE: NA - half-duplex only
Sum of all collision events.
Port_Index +
0x4D
TxTotalCollisions
NOTE: NA - half-duplex only
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 94. MAC TX Statistics ($ Port_Index +0x40 – +0x58) (Sheet 3 of 4)
Name
Description
Address
Type1
Default
A count of successfully transmitted
frames on a particular interface where
the transmission is inhibited by exactly
one collision. A frame that is counted
by an instance of this object is also
counted by the corresponding instance
of either the UnicastPkts,
Port_Index +
0x4E
TxSingleCollisions
R
0x00000000
MulticastPkts, or BroadcastPkts, and is
not counted by the corresponding
instance of the MultipleCollisionFrames
object.
NOTE: NA - half-duplex only
A count of successfully transmitted
frames on a particular interface for
which transmission is inhibited by more
than one collision. A frame that is
counted by an instance of this object is
also counted by the corresponding
instance of either the UnicastPkts,
MulticastPkts, or BroadcastPkts, and is
not counted by the corresponding
instance of the SingleCollisionFrames
object.
Port_Index +
0x4F
TxMultipleCollisions
R
0x00000000
NOTE: NA - half-duplex only
The number of times a collision is
detected on a particular interface later
than 512 bit-times into the transmission
of a packet. Such frame are terminated
and discarded.
Port_Index +
0x50
TxLateCollisions
R
R
0x00000000
0x00000000
NOTE: NA - half-duplex only
A count of frames, which collides 16
times and is then discarded by the
MAC. Not effecting xMultipleCollisions
Port_Index +
0x51
TxExcessiveCollisionErrors
NOTE: NA - half-duplex only
Number of times frame transmission is
postponed more than 2*MaxFrameSize
because of another frame already
being transmitted on the Ethernet
network. This causes the MAC to
discard the frame.
Port_Index +
0x52
TxExcessiveDeferralErrors
R
0x00000000
NOTE: NA - half-duplex only
Frame transmissions aborted by the
MAC because the frame is longer than
maximum frame size. These frames
are truncated by the MAC when the
maximum frame size violation is
detected by the MAC.
Port_Index +
0x53
TxExcessiveLengthDrop
R
R
0x00000000
0x00000000
Internal TX error that causes the MAC
to end the transmission before the end
of the frame because the MAC did not
get the needed data in time for
transmission. The frames are lost and
a fragment or a CRC error is
Port_Index +
0x54
TxUnderrun
transmitted.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 94. MAC TX Statistics ($ Port_Index +0x40 – +0x58) (Sheet 4 of 4)
Name
Description
Address
Type1
Default
Number of OK frames with VLAN tag.
(Type field = 0x8100).
Port_Index +
0x55
TxTagged
R
0x00000000
Number of frames transmitted with a
legal size but with the wrong CRC field
(also called FCS field).
Port_Index +
0x56
TxCRCError
R
R
0x00000000
0x00000000
Number of pause MAC frames
transmitted.
Port_Index +
0x57
TxPauseFrames
Intentionally generates collisions to
curb reception of incoming traffic due to
insufficient memory available for
additional frames. The port must be in
half-duplex mode with flow control
enabled.
TxFlowControlCollisions
Send
Port_Index +
0x58
R
0x00000000
NOTE: To receive a correct statistic, a
last frame may have to be
transmitted after the last flow
control collisions send.
NOTE: NA - half-duplex only
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
8.4.4
PHY Autoscan Registers
Note: These register hold the current values of the PHY registers only when Autoscan (see Section 5.5.8,
“Autoscan Operation” on page 103) is enabled and the IXF1104 MAC is configured in copper
mode. These registers are not applicable in fiber mode.
Table 95. PHY Control ($ Port Index + 0x60) (Sheet 1 of 2)
Bit
Name
Description
Type1
RO
Default
0x00000010
001000
31:16 Reserved
Reserved
0x0000
0
PHY Soft Reset. Resets the PHY registers to their
default value.
This register bit self-clears after the reset is
complete.
15
Reset
RO
0 = Normal Operation
1 = PHY reset
0 = Disable loopback mode
1 = Enable loopback mode
14
13
Loopback
RO
RO
0
0.6 (Speed<1> 0.13 (Speed<0>)
00 =10 Mbps
Speed Selection
01 =100 Mbps
02
10 =1000 Mbps (manual mode not allowed)
11 = Reserved
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
2. This register is ignored if auto-negotiation is enabled.
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 95. PHY Control ($ Port Index + 0x60) (Sheet 2 of 2)
Bit
Name
Description
Type1
Default
0 = Disable auto-negotiation process
1 = Enable auto-negotiation process
Auto-Negotiation
Enable
12
RO
1
This register bit must be enabled for
1000BASE-T operation.
0 = Normal operation
1 = Power-down
11
10
9
Power-Down
Isolate
RO
RO
RO
RO
0
0
0 =
1 = Electrically isolate PHY from GMII
Restart
Auto-Negotiation
0 = Normal operation
1 = Restart auto-negotiation process
0
0 = Half-duplex mode
1 = Full-duplex mode
8
Duplex Mode
Collision Test
12
0 = Disable COL signal test
1 = Enable COL signal test
7
RO
0
This register bit is ignored unless loopback is
enabled (Register bit 0.14 = 1)
0.6 (Speed<1>) 0.13 (Speed<0>)
00 = 10 Mbps
Speed Selection
1000 Mbps
6
01 = 100 Mbps
RO
RO
02
10 = 1000 Mbps (manual mode now allowed)
11 = Reserved
5:0
Reserved
Reserved
0
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
2. This register is ignored if auto-negotiation is enabled.
Table 96. PHY Status ($ Port Index + 0x61) (Sheet 1 of 2)
Bit
Name
Description
Type1
Default
0x001111001
00001001
31:16 Reserved
Reserved
RO
RO
0
0
0 = PHY not able to operate in 100BASE-T4
1 = PHY able to operate in 100BASE-T4
15
100BASE-T4
0 = PHY not able to operate in 100BASE-X in full-
duplex mode
1 = PHY able to operate in 100BASE-X in full-
100BASE-X
Full-Duplex
14
RO
RO
RO
1
1
1
duplex mode
0 = PHY not able to operate in 100BASE-X in
half-duplex mode
1 = PHY able to operate in 100BASE-X in half-
100BASE-X
Half-Duplex
13
12
duplex mode
0 = PHY not able to operate in 10 Mbps in full-
duplex mode
1 = PHY able to operate in 10 Mbps in full-duplex
10 Mbps
Full-Duplex
mode
1. R = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
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Table 96. PHY Status ($ Port Index + 0x61) (Sheet 2 of 2)
Bit
Name
Description
Type1
Default
0 = PHY not able to operate in 10 Mbps in half-
duplex mode
1 = PHY able to operate in 10 Mbps in half-
duplex mode
10 Mbps
Half-Duplex
11
RO
1
0 = PHY not able to operate in 10BASE-T2 in full-
duplex mode (not supported)
1 = PHY able to operate in 100BASE-T2 in full-
duplex mode
100BASE-T2
Full-Duplex
10
9
RO
RO
0
0
0 = PHY not able to operate in 100BASE-T2 in
half-duplex mode
1 = PHY able to operate in 100BASE-T2 in half-
duplex mode
100BASE-T2
Half-Duplex
0 = No extended status information in Register 15
1 = Extended status information in Register 15
8
7
Extended Status
Reserved
RO
RO
1
0
Reserved
0 = PHY will not accept management frames with
preamble suppressed
1 = PHY will accept management frames with
MF Preamble
Suppression
6
RO
0
preamble suppressed
5
4
Reserved
Reserved
RO
RO
0
0
0 =
Remote Fault
1 = Remote fault condition detected
Auto-Negotiation
Ability
0 =
3
2
1
0
RO
RO
RO
RO
1
0
0
1
1 = PHY is able to perform auto-negotiation
0 = Link is down
1 = Link is up
Link Status
0 = Jabber condition not detected
1 = Jabber condition detected
Jabber Detect
Extended Capability
0 = No extended register capabilities
1 = Extended register capabilities
1. R = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
Table 97. PHY Identification 1 ($ Port Index + 0x62)
Bit
Name
Description
Type1
Default
0x00013
0
31:16 Reserved
15:0 PHY ID Number
Reserved
RO
RO
The PHY identifier is composed of register bits
18.3 of the OUI (Organizationally Unique
Identifier)
h0013
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
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Table 98. PHY Identification 2 ($ Port Index + 0x63)
Bit
Name
Description
Type1
Default
0x001111001
00000000
31:16 Reserved
Reserved
RO
RO
0
The PHY identifier is composed of register bits
24:19 of the OUI (Organizationally Unique
Identifier)
15:10 PHY ID Number
011110
9:4
3:0
Manufacturer’s Model
Six bits containing the manufacturer’s part number
RO
RO
010000
0000
Manufacturer’s
Revision Number
Four bits containing the manufacturer’s revision
number
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
Table 99. Auto-Negotiation Advertisement ($ Port Index + 0x64) (Sheet 1 of 2)
Bit
Name
Description
Type1
Default
0x00000100
111100001
31:16 Reserved
Reserved
RO
RO
RO
RO
RO
0
0
0
0
0
0 =
15
14
13
12
Next Page
Reserved
1 = Manual control of Next Page (software)
Reserved
0 = No remote fault
1 = Remote fault
Remote Fault
Reserved
Reserved
Advertise Asymmetric Pause Direction register bit.
This register bit is used in conjunction with Pause
(Register bit 4.10)
11
10
ASM_DIR
Pause
RO
RO
1
0
0 = Link partner is not capable of asymmetric
pause
1 = Link partner is capable of asymmetric pause
Advertise to link partner that Pause operation is
desired (IEEE 802.3x Standard)
0 = 100BASE-T4 capability is not available
1 = 100BASE-T4 capability is available
The IXF1104 MAC does not support 100BASE-T4,
but allows this register bit to be set to advertise in
auto-negotiation sequence for 100BASE-T4
operation. If this capability is desired, an external
100BASE-T4 transceiver can be switched in.
9
100BASE-T4
RO
0
0 = DTE is not 100BASE-TX, full-duplex mode
100BASE-TX
Full-Duplex
capable
8
7
RO
RO
1
1
1 = DTE is 100BASE-TX, full-duplex mode
capable
0 = DTE is not 100BASE-TX, half-duplex mode
100BASE-TX
Half-Duplex
capable
1 = DTE is 100BASE-TX, half-duplex mode
capable
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
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Table 99. Auto-Negotiation Advertisement ($ Port Index + 0x64) (Sheet 2 of 2)
Bit
Name
Description
Type1
Default
0 = DTE is not 10BASE-T, full-duplex mode
capable
1 = DTE is 10BASE-T, full-duplex mode capable
10BASE-T
Full-Duplex
6
RO
1
0 = DTE is not 10BASE-T, half-duplex mode
capable
1 = DTE is 10BASE-T, half-duplex mode capable
10BASE-T
Half-Duplex
5
RO
RO
1
00001 =IEEE 802.3
00010 =IEEE 802.9 ISLAN-16T
00000 =Reserved for future auto-negotiation
development
Selector Field,
S[4:0]
11111 =Reserved for future auto-negotiation
development
4:0
00001
Unspecified or reserved combinations should not
be transmitted
Setting this field to a value other than 00001 will
most likely cause auto-negotiation to fail
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
Table 100. Auto-Negotiation Link Partner Base Page Ability ($ Port Index + 0x65) (Sheet 1 of 2)
Bit
Name
Description
Type1
Default
0x0---
01001111000
01
31:16 Reserved
Reserved
RO
RO
0
0 = Link partner has no ability to send multiple
pages
15
14
Next Page
NA
1 = Link partner has the ability to send multiple
pages
0 = Link partner has not received Link Code Word
from the IXF1104 MAC
1 = Link partner has received Link Code Word
Acknowledge
RO
NA
from the IXF1104 MAC
0 = No remote fault
1 = Remote fault
13
12
Remote Fault
Reserved
RO
RO
NA
0
Reserved
Advertise Asymmetric Pause Direction Register
bit. This register bit is used in conjunction with
Pause (Register bit 4.10)
11
ASM_DIR
RO
1
0 = Link partner is not capable of asymmetric
pause
1 = Link partner is capable of asymmetric pause
Link partner wants to utilize Pause Operation as
defined in IEEE 802.3x Standard
10
9
Link Partner Pause
1000BASE-T4
RO
RO
0
0
0 = Link partner is not 100BASE-T4 capable
1 = Link partner is 100BASE-T4 capable
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
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Table 100. Auto-Negotiation Link Partner Base Page Ability ($ Port Index + 0x65) (Sheet 2 of 2)
Bit
Name
Description
Type1
Default
0 = Link partner is not 100BASE-TX, full-duplex
mode capable
1 = Link partner is 100BASE-TX, full-duplex
mode capable
100BASE-TX
Full-Duplex
8
RO
1
0 = Link partner is not 100BASE-TX, half-duplex
mode capable
1 = Link partner is 100BASE-TX, half-duplex
mode capable
100BASE-TX
Half-Duplex
7
6
5
RO
RO
RO
1
1
1
0 = Link partner is not 10BASE-T, full-duplex
mode capable
1 = Link partner is 10BASE-T, full-duplex mode
capable
10BASE-T
Full-Duplex
0 = Link partner is not 10BASE-T, half-duplex
mode capable
1 = Link partner is 10BASE-T, half-duplex mode
capable
10BASE-T
Half-Duplex
00001 =IEEE 802.3
00010 =IEEE 802.9 ISLAN-16T
00000 =Reserved for future auto-negotiation
development
11111 =Reserved for future auto-negotiation
development
4:0
Selector Field, S[4:0]
RO
00001
Unspecified or reserved combinations should not
be transmitted
Setting this field to a value other than 00001 will
most likely cause auto-negotiation to fail
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
Table 101. Auto-Negotiation Expansion ($ Port Index + 0x66) (Sheet 1 of 2)
Bit
Name
Description
Type1
Default
0x0000000
0
31:6 Reserved
Reserved
RO
This register bit indicates the status of the auto-
negotiation variable, base page. It flags
synchronization with the auto-negotiation state
diagram allowing detection of interrupted links.
5
Base Page
RO
0
This register bit is only used if Register bit 16.1
(alternate Next Page feature) is set.
0 = base_page = false
1 = base_page = true
Parallel Detection
Fault
0 = Parallel detection fault has not occurred
1 = Parallel detection fault has occurred
4
3
RO
RO
0
0
Link Partner Next Page 0 = Link partner is not Next Page able
Able 1 = Link partner is Next Page able
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
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Table 101. Auto-Negotiation Expansion ($ Port Index + 0x66) (Continued) (Sheet 2 of 2)
Bit
Name
Description
Type1
Default
0 = Local device is not Next Page able
1 = Local device is Next Page able
2
Next Page Able
RO
0
Indicates that a new page has been received and
the received code word has been loaded into
Register 5 (base pages) or Register 8 (next pages)
as specified in the EEE 802.3 Standard.
1
0
Page Received
RO
RO
0
0
This bit clears on Read.
Link Partner Auto-
Negotiation Able
0 = Link partner is not auto-negotiation able
1 = Link partner is auto-negotiation able
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
Table 102. Auto-Negotiation Next Page Transmit ($ Port Index + 0x67)
Bit
Name
Description
Type1
Default
0x0000000
0
31:16 Reserved
Reserved
RO
RO
RO
RO
0 = Last page
1 = Additional Next Pages follow
15
14
13
Next Page (NP)
0
0
0
Reserved
Reserved
0 = Unformatted page
1 = Message page
Message Page (MP)
0 = Cannot comply with message
1 = Complies with message
12
11
Acknowledge 2
Toggle (T)
RO
RO
RO
0
0
0
0 = Previous value of the transmitted Link Code
Word was logic one
1 = Previous value of the transmitted Link Code
Word was logic zero
Message/Unformatted 11-bit message code field
Code Field See IEEE 802.3 Annex 28C
10:0
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
8.4.5
Global Status and Configuration Register Overview
Control and Status Registers.
Table 103. Port Enable ($0x500)
Bit
Name
Description
Type*
Default
Register Description: A control register for each port in the IXF1104 MAC. Port ID = bit
position in the register. To make a port active, the bit must be set High. For example, Port 2
active implies a register value of 0000.0100. Setting the bit to 0 de-asserts the enable. The
default state for this register is for all four ports to be disabled.
0x00000000
31:4 Reserved
Reserved
RO
0x0000000
0
Port 3
3
2
1
0
Port 3 Enable
R/W
0 = Disable
1 = Enable
Port 2
Port 2 Enable
Port 1 Enable
Port 0 Enable
R/W
R/W
R/W
0
0
0
0 = Disable
1 = Enable
Port 1
0 = Disable
1 = Enable
Port 0
0 = Disable
1 = Enable
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 104. Interface Mode ($0x501)
Bit
Name
Description
Type1
Default
Register Description: If_Mode – Four bits of this register determines the PHY interface
mode.
0 = Fiber (SerDes/OMI interface)
1 = Copper (GMII or RGMII interface)
0x00000000
Changes to the data setting of this register must be made in conjunction with the “Clock and
Interface Mode Change Enable Ports 0 - 3 ($0x794)" to ensure a safe transition to a new
The Enable clock mode change bit has to be set back to 1 after the configuration change takes
effect.
31:4 Reserved
Reserved
RO
0x0000000
0
0 = Fiber mode
1 = Copper mode
3
2
1
0
Port 3 Interface Mode
R/W
0 = Fiber mode
1 = Copper mode
Port 2 Interface Mode
Port 1 Interface Mode
Port 0 Interface Mode
R/W
R/W
R/W
0
0
0
0 = Fiber mode
1 = Copper mode
0 = Fiber mode
1 = Copper mode
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 105. Link LED Enable ($0x502)
Bit
Name
Description
Type1
Default
Register Description: Per port bit should be set upon detection of link to enable proper
operation of the link LEDs.
0x00000000
0x00000
31:4 Reserved
Reserved
Port 3 link
R/W
R/W
3
2
1
0
Link LED Enable Port 3
0
0
0
0
0 = No link
1 = Link
Port 2 link
Link LED Enable Port 2
Link LED Enable Port 1
Link LED Enable Port 0
R/W
R/W
R/W
0 = No link
1 = Link
Port 1 link
0 = No link
1 = Link
Port 0 link
0 = No link
1 = Link
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 106. MAC Soft Reset ($0x505)
Bit
Name
Description
Type1
Default
Register Description: Per-port software-activated reset of the MAC core.
0x00000000
0x00000
31:4 Reserved
Reserved
Port 3
R/W
R/W
3
2
1
0
Software Reset MAC 3
0
0
0
0
0 = Reset inactive
1 = Enable
Port 2
Software Reset MAC 2
Software Reset MAC 1
Software Reset MAC 0
R/W
R/W
R/W
0 = Reset inactive
1 = Enable
Port 1
0 = Reset inactive
1 = Enable
Port 0
0 = Reset inactive
1 = Enable
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 107. MDIO Soft Reset ($0x506)
Bit
Name
Description
Type1
Default
Register Description: Software-activated reset of the MDIO module.
0x00000000
0x00000000
31:1 Reserved
Software MDIO Reset
Reserved
RO
0 = Reset inactive
1 = Reset active
0
R/W
0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 108. CPU Interface ($0x508)
Bit
Name
Description
Type1
Default
Register Description: CPU Interface Endian select. Allows the user to select the Endian of
the CPU interface to allow for various CPUs to be connected to the IXF1104 MAC.
0x00000000
0x00
31:25 Reserved
Reserved
RO
R/W
RO
Reserved in Little Endian
Valid in Big endian
24
CPU Endian
0
0x000000
0
0 = Little Endian
1 = Big Endian
23:1 Reserved
Reserved
Reserved in Big Endian
Valid in Little Endian
0
CPU Endian Control
R/W
0 = Little Endian
1 = Big Endian
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
NOTE: Since the Endianess of the bus is unknown when writing to this register, write 0x01000001 to set the
bit and 0x0 to clear it.
Table 109. LED Control ($0x509)
Bit
Name
Description
Type1
Default
Register Description: Global selection of LED mode.
0x00000000
0x00000000
31:2 Reserved
Reserved
RO
0 = Disable LED Block
1 = Enable LED Block
1
LED Enable
R/W
0
0 = Enable LED Mode 0 for use with SGS
Thomson M5450 LED driver (Default)
1 = LED Mode 1 for use with Standard Octal Shift
register
0
LED Control
R/W
0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Datasheet
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 110. LED Flash Rate ($0x50A)
Bit
Name
Description
Type1
Default
Register Description: Global selection of LED flash rate.
0x00000000
0x00000000
31:3 Reserved
Reserved
RO
000 =100 ms flash rate
001 =200 ms flash rate
010 =300 ms flash rate
011 = 400 ms flash rate
100 = 500 ms flash rate
101 = Reserved
LED Flash Rate
Control
2:0
R/W
000
110 = Reserved
111 = Reserved
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 111. LED Fault Disable ($0x50B)
Bit
Name
Description
Type1
Default
Register Description: Per-port fault disable. Disables the LED flashing for local or remote
faults.
0x00000000
0x0000000
31:4 Reserved
Reserved
Port 3
RO
LED Port 3 Fault
3
2
1
0
R/W
0
0
0
0
0 = Fault enabled
1 = Fault disabled
Control
Port 2
LED Port 2 Fault
Control
R/W
R/W
R/W
0 = Fault enabled
1 = Fault disabled
Port 1
LED Port 1 Fault
Control
0 = Fault enabled
1 = Fault disabled
Port 0
LED Port 0 Fault
Control
0 = Fault enabled
1 = Fault disabled
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 112. JTAG ID ($0x50C)
Bit
Name
Description
Type1
Default
Register Description: The value of this register follows the same scheme as the device
identification register found in the IEEE 1149.1 specification. The upper four bits correspond to
silicon stepping. The next 16 bits store a Part ID Number. The next 11 bits contain a JEDEC
manufacturer ID. Bit zero = 1 if the chip is the first in a stack. The encoding scheme used for
the Product ID field is implementation-dependent.
0x10450013
00012
31:28 Version
27:12 Part ID
Version
Part ID
RO
RO
0000010001
010000
JEDEC Continuation
11:8
JEDEC Continuation Characters
RO
0000
Characters
JEDEC ID
Fixed
7:1
0
JEDEC ID
Fixed
RO
RO
0001001
1
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
2. These bits vary with stepping.
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
8.4.6
RX FIFO Register Overview
FIFO High and Low watermarks.
Table 113. RX FIFO High Watermark Port 0 ($0x580)
Bit
Name
Description
Type1
Default
Register Description: The default value of 0x0E6 represents 230 eight-byte locations. This
equates to 1840 bytes of data. A unit entry in this register equates to 8 bytes of data. When the
amount of data stored in the RX FIFO exceeds the high watermark, flow control is
automatically initiated within the MAC to avoid an overflow condition.
0x0E6
31:12 Reserved
Reserved
RO
0x00000
0x0E6
The high water mark value.
RX FIFO High
Watermark Port 0
11: 0
R/W
NOTE: Must be greater than the RX FIFO Low
Watermark and RX FIFO transfer threshold.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 114. RX FIFO High Watermark Port 1 ($0x581)
Bit
Name
Description
Type1
Default
Register Description: The default value of 0x0E6 represents 230 eight-byte locations. This
equates to 1840 bytes of data. A unit entry in this register equates to 8 bytes of data. When the
amount of data stored in the RX FIFO exceeds the high watermark, flow control is
automatically initiated within the MAC to avoid an overflow condition.
0x0E6
31:12 Reserved
Reserved
RO
0x00000
0x0E6
The high water mark value.
RX FIFO High
Watermark Port 1
11: 0
R/W
NOTE: Must be greater than the RX FIFO Low
Watermark and RX FIFO transfer threshold.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 115. RX FIFO High Watermark Port 2 ($0x582)
Bit
Name
Description
Type1
Default
Register Description: The default value of 0x0E6 represents 230 eight-byte locations. This
equates to 1840 bytes of data. A unit entry in this register equates to 8 bytes of data. When the
amount of data stored in the RX FIFO exceeds the high watermark, flow control is
automatically initiated within the MAC to avoid an overflow condition.
0x0E6
31:12 Reserved
Reserved
RO
0x00000
0x0E6
The high water mark value.
RX FIFO High
Watermark Port 2
11: 0
R/W
NOTE: Must be greater than the RX FIFO Low
Watermark and RX FIFO transfer threshold.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 116. RX FIFO High Watermark Port 3 ($0x583)
Bit
Name
Description
Type1
Default
Register Description: The default value of 0x0E6 represents 230 eight-byte locations. This
equates to 1840 bytes of data. A unit entry in this register equates to 8 bytes of data. When the
amount of data stored in the RX FIFO exceeds the high watermark, flow control is
automatically initiated within the MAC to avoid an overflow condition.
0x0E6
31:12 Reserved
Reserved
RO
0x00000
0x0E6
The high water mark value.
RX FIFO High
Watermark Port 3
11: 0
R/W
NOTE: Must be greater than the RX FIFO Low
Watermark and RX FIFO transfer threshold.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 117. RX FIFO Low Watermark Port 0 ($0x58A)
Bit
Name
Description
Type1
Default
Register Description: The default value of 0x072 represents 114 eight-byte locations. This
equates to 912 bytes of data. A unit entry in this register equates to 8 bytes of data. When the
amount of data stored in the RX FIFO falls below the Low Watermark, flow control is
automatically de-asserted within the MAC to allow more line-side data to be captured by the
RX FIFO.
0x072
31:12 Reserved
Reserved
RO
0x00000
0x072
The High Watermark value
NOTE: Should never be greater or equal to the
High Watermark.
RX FIFO Low
Watermark Port 0
11: 0
R/W
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 118. RX FIFO Low Watermark Port 1 ($0x58B)
Bit
Name
Description
Type1
Default
Register Description: The default value of 0x072 represents 114 eight-byte locations. This
equates to 912 bytes of data. A unit entry in this register equates to 8 bytes of data. When the
amount of data stored in the RX FIFO falls below the Low Watermark, flow control is
automatically de-asserted within the MAC to allow more line-side data to be captured by the
RX FIFO.
0x072
31:12 Reserved
Reserved
RO
0x00000
0x072
The High Watermark value
NOTE: Should never be greater or equal to the
High Watermark.
RX FIFO Low
Watermark Port 1
11: 0
R/W
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
2
Table 119. RX FIFO Low Watermark Port 2 ($0x58C)
Bit
Name
Description
Type1
Default
Register Description: The default value of 0x072 represents 114 eight-byte locations. This
equates to 912 bytes of data. A unit entry in this register equates to 8 bytes of data. When the
amount of data stored in the RX FIFO falls below the Low Watermark, flow control is
automatically de-asserted within the MAC to allow more line-side data to be captured by the
RX FIFO.
0x072
31:12 Reserved
Reserved
RO
0x00000
0x072
The High Watermark value
NOTE: Should never be greater or equal to the
RX FIFO Low
Watermark Port 2
11: 0
R/W
High Watermark.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 120. RX FIFO Low Watermark Port 3 ($0x58D)
Bit
Name
Description
Type1
Default
Register Description: The default value of 0x072 represents 114 eight-byte locations. This
equates to 912 bytes of data. A unit entry in this register equates to 8 bytes of data. When the
amount of data stored in the RX FIFO falls below the Low watermark, flow control is
automatically de-asserted within the MAC to allow more line-side data to be captured by the
RX FIFO.
0x072
31:12 Reserved
Reserved
RO
0x00000
0x072
The High watermark value
RX FIFO Low
Watermark Port 3
11: 0
R/W
NOTE: Should never be greater or equal to the
High Watermark.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 121. RX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x594 – 0x597)
Name
Description
Address
Type1
Default
RX FIFO Overflow When RX FIFO on port 0 becomes full or
Frame Drop
Counter on port 0
reset, the number of frames lost/dropped on
this port are shown in this register.
0x594
R
0x00000000
RX FIFO Overflow When RX FIFO on port 1 becomes full or
Frame Drop
reset, the number of frames lost/dropped on
0x595
0x596
0x597
R
R
R
0x00000000
0x00000000
0x00000000
Counter on port 1
this port are shown in this register.
RX FIFO Overflow When RX FIFO on port 2 becomes full or
Frame Drop
Counter on port 2
reset, the number of frames lost/dropped on
this port are shown in this register.
RX FIFO Overflow When RX FIFO on port 3 becomes full or
Frame Drop
reset, the number of frames lost/dropped on
Counter on port 3
this port are shown in this register.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 122. RX FIFO Port Reset ($0x59E)
Bit
Name
Description
Type1
Default
Register Description: The soft reset register for each port in the RX block. Port ID = bit
position in the register. To make the reset active, the bit must be set High. For example, reset
of port 1 implies register value = 0000_0018. Setting the bit to 0 de-asserts the reset.
0x00000000
0x0000000
31:4 Reserved
Reserved
RO
Port 3
Reset RX FIFO for
3
2
1
0
R/W
0
0
0
0
0 = De-assert reset
1 = Reset
Port 3
Port 2
Reset RX FIFO for
Port 2
R/W
R/W
R/W
0 = De-assert reset
1 = Reset
Port 1
Reset RX FIFO for
Port 1
0 = De-assert reset
1 = Reset
Port 0
Reset RX FIFO for
Port 0
0 = De-assert reset
1 = Reset
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 123. RX FIFO Errored Frame Drop Enable ($0x59F) (Sheet 1 of 2)
Bit
Name
Description
Type1
Default
Register Description: This register configures the dropping of error packets (DEBAD).
0x00000000
0x0000000
NOTE: Jumbo packets are not dropped.
31:4 Reserved
Reserved
RO
This bit is used in conjunction with MAC filter bits.
This allows the user to select whether the errored
packets are to be dropped or not.
RX FIFO Errored
Frame Drop Enable
Port 3
3
R/W
0
1 = Frame Drop Enable
0 = Frame Drop Disable
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 123. RX FIFO Errored Frame Drop Enable ($0x59F) (Sheet 2 of 2)
Bit
Name
Description
Type1
Default
This bit is used in conjunction with MAC filter bits.
This allows the user to select whether the errored
packets are to be dropped or not.
RX FIFO Errored
Frame Drop Enable
Port 2
2
R/W
0
1 = Frame Drop Enable
0 = Frame Drop Disable
This bit is used in conjunction with MAC filter bits.
This allows the user to select whether the errored
packets are to be dropped or not.
RX FIFO Errored
Frame Drop Enable
Port 1
1
0
R/W
R/W
0
0
1 = Frame Drop Enable
0 = Frame Drop Disable
This bit is used in conjunction with MAC filter bits.
This allows the user to select whether the errored
packets are to be dropped or not.
RX FIFO Errored
Frame Drop Enable
Port 0
1 = Frame Drop Enable
0 = Frame Drop Disable
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 124. RX FIFO Overflow Event ($0x5A0)
Bit
Name
Description
Type1
Default
Register Description: This register provides a status if a FIFO-full situation occurs (for
example, a FIFO overflow). The bit position equals the port number. This register is cleared on 0x00000000
Read.
31:4 Reserved
Reserved
RO
0x0000000
Port 3
RX FIFO Overflow
3
2
1
0
R
0
0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred
Event on Port 3
Port 2
RX FIFO Overflow
Event on Port 2
R
R
R
0
0
0
0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred
Port 1
RX FIFO Overflow
Event on Port 1
0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred
Port 0
RX FIFO Overflow
Event on Port 0
0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 125. RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5) (Sheet 1 of 2)
Name
Description
Address
Type
Default
This register counts all frames dropped from the
RX FIFO for port 0 by meeting one of the
following conditions:
• Frames are removed in conjunction
with the“RX FIFO Errored Frame
RX FIFO Errored
Frame Drop Counter
on Port 0
0x5A2
R
0x00000000
This register is cleared on Read.
This register counts all frames dropped from the
RX FIFO for port 1 by meeting one of the
following conditions:
• Frames are removed in conjunction
with the“RX FIFO Errored Frame
RX FIFO Errored
Frame Drop Counter
on Port 1
0x5A3
R
0x00000000
This register is cleared on Read.
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 125. RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5) (Sheet 2 of 2)
Name
Description
Address
Type
Default
This register counts all frames dropped from the
RX FIFO for port 2 by meeting one of the
following conditions:
• Frames are removed in conjunction
with the“RX FIFO Errored Frame
RX FIFO Errored
Frame Drop Counter
on Port 2
0x5A4
R
0x00000000
This register is cleared on Read.
This register counts all frames dropped from the
RX FIFO for port 3 by meeting one of the
following conditions:
• Frames are removed in conjunction
with the“RX FIFO Errored Frame
RX FIFO Errored
Frame Drop Counter
on Port 3
0x5A5
R
0x00000000
This register is cleared on Read.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
Table 126. RX FIFO SPI3 Loopback Enable for Ports 0 - 3 ($0x5B2)
Bit
Name
Description
Type1
Default
Register Description: Enables the TX SPI3 port to send packets into the RX_FIFO instead of
into the TX FIFO, creating a SPI3 loopback.
0x00000000
0x00000
0x0
31:12 Reserved
Reserved
RO
SPI3 loopback enable
for Port 3
0 = Disabled
1 = Enabled
11
10
9
R/W
SPI3 loopback enable
for Port 2
0 = Disabled
1 = Enabled
R/W
R/W
0x0
0x0
SPI3 loopback enable
for Port 1
0 = Disabled
1 = Enabled
SPI3 loopback enable
for Port 0
0 = Disabled
1 = Enabled
8
R/W
R/W
0x0
7:0
Reserved
Write as 0, ignore on Read.
0x00
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 127. RX FIFO Padding and CRC Strip Enable ($0x5B3)
Bit
Name
Description
Type1
Default
Register Description: This control register enables to pre-pend every packet with two extra
bytes and also enables the CRC stripping of a packet.
0x00000000
0x000000
31:8 Reserved
Reserved
RO
CRC stripping is enabled for Port 3.
CRC Stripping Enable
for Port 3
7
6
5
4
R/W
0
0
0
0
0 = Disabled
1 = Enabled
CRC stripping is enabled for Port 2.
CRC Stripping Enable
for Port 2
R/W
R/W
R/W
0 = Disabled
1 = Enabled
CRC stripping is enabled for Port 1.
CRC Stripping Enable
for Port 1
0 = Disabled
1 = Enabled
CRC stripping is enabled for Port 0.
CRC Stripping Enable
for Port 0
0 = Pre-pending Disabled
1 = Pre-pending Enabled
Enables pre-pending of two bytes at the start of
every packet – Port 3.
Pre-pending Enable2
Port 3
3
2
1
0
R/W
R/W
R/W
R/W
0
0
0
0
0 = Disabled
1 = Enabled
Enables pre-pending of two bytes at the start of
every packet – Port 2.
Pre-pending Enable2
Port 2
0 = Disabled
1 = Enabled
Enables pre-pending of two bytes at the start of
every packet – Port 1.
Pre-pending Enable2
Port 1
0 = Disabled
1 = Enabled
Enables pre-pending of two bytes at the start of
every packet – Port 0.
Pre-pending Enable2
Port 0
0 = Disabled
1 = Enabled
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
2. Pre-pending should not be enabled in loopback mode.
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 128. RX FIFO Transfer Threshold Port 0 ($0x5B8)
Bit
Name
Description
Type
Default
Register Description: RX FIFO transfer threshold for port 0 in 8-byte location.
0x000000BE
0x00000
31:12 Reserved
Reserved
RO
RX FIFO transfer threshold for port 0. This must
be less than the RX FIFO High water mark.
User definable control register that sets the
threshold where a packet starts transitioning to the
SPI3 interface from the RX FIFO before the EOP
is received. Packets received in the RX FIFO
below this threshold are treated as store and
forward.
RX FIFO Transfer
Threshold - Port 0
11:0
R/W
0x0BE
NOTE: Do not program the RX FIFO transfer
threshold below a setting of 0xBE
(1520bytes).
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 129. RX FIFO Transfer Threshold Port 1 ($0x5B9)
Bit
Name
Description
Type
Default
Register Description: RX FIFO transfer threshold for port 1in 8-byte location.
0x000000BE
0x00000
31:12 Reserved
Reserved
RO
RX FIFO transfer threshold for port 1. This must
be less than the RX FIFO High watermark.
User definable control register that sets the
threshold where a packet starts transitioning to
the SPI3 interface from the RX FIFO before the
EOP is received. Packets received in the RX
FIFO below this threshold are treated as store
and forward.
RX FIFO Transfer
Threshold - Port 1
11:0
R/W
0x0BE
NOTE: Do not program the RX FIFO transfer
threshold below a setting of 0xBE
(1520bytes).
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 130. RX FIFO Transfer Threshold Port 2 ($0x5BA)
Bit
Name
Description
Type
Default
Register Description: RX FIFO transfer threshold for port 2 in 8-byte location.
0x000000BE
0x00000
31:12 Reserved
Reserved
RO
RX FIFO transfer threshold for port 2. This must be
less than the RX FIFO High water mark.
User definable control register that sets the
threshold where a packet starts transitioning to the
SPI3 interface from the RX FIFO before the EOP is
received. Packets received in the RX FIFO below
this threshold are treated as store and forward.
NOTE: Do not program the RX FIFO transfer
threshold below a setting of 0xBE
RX FIFO Transfer
Threshold - Port 2
11:0
R/W
0x0BE
(1520bytes).
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 131. RX FIFO Transfer Threshold Port 3 ($0x5BB)
Bit
Name
Description
Type
Default
Register Description: RX FIFO transfer threshold for port 3 in 8-byte location.
0x000000BE
0x00000
31:12
11:0
Reserved
Reserved
RO
RX FIFO transfer threshold for port 3. This must
be less than the RX FIFO High water mark.
User definable control register that sets the
threshold where a packet starts transitioning to the
SPI3 interface from the RX FIFO before the EOP
is received. Packets received in the RX FIFO
below this threshold are treated as store and
forward.
RX FIFO Transfer
Threshold - Port 3
R/W
0x0BE
NOTE: Do not program the RX FIFO transfer
threshold below a setting of 0xBE
(1520bytes).
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
8.4.7
TX FIFO Register Overview
FIFO High and Low watermark.
Table 132. TX FIFO High Watermark Ports 0 - 3 ($0x600 – 0x603)
Name
Description
Address
Type1
Default
High watermark for TX FIFO Port 0. The
default value of 0x3E0 represents 992 8-byte
locations. This equates to 7936 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO exceeds the high watermark, flow control
is automatically initiated on the SPI3 interface to
request that the switch fabric stops data
TX FIFO High
Watermark Port 0
0x600
R/W
0x000003E0
transfers to avoid an overflow condition.
High watermark for TX FIFO Port 1. The
default value of 0x3E0 represents 992 8-byte
locations. This equates to 7936 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO exceeds the high watermark, flow control
is automatically initiated on the SPI3 interface to
request that the switch fabric stops data
TX FIFO High
Watermark Port 1
0x601
0x602
0x603
R/W
R/W
R/W
0x000003E0
0x000003E0
0x000003E0
transfers to avoid an overflow condition.
High watermark for TX FIFO Port 2. The
default value of 0x3E0 represents 992 8-byte
locations. This equates to 7936 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO exceeds the high watermark, flow control
is automatically initiated on the SPI3 interface to
request that the switch fabric stops data
TX FIFO High
Watermark Port 2
transfers to avoid an overflow condition.
High watermark for TX FIFO Port 3. The
default value of 0x3E0 represents 992 8-byte
locations. This equates to 7936 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO exceeds the high watermark, flow control
is automatically initiated on the SPI3 interface to
request that the switch fabric stops data
TX FIFO High
Watermark Port 3
transfers to avoid an overflow condition.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 133. TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A – 0x60D)
Name
Description
Address
Type1
Default
Low watermark for TX FIFO Port 0. The
default value of 0x0D0 represents 208 8-byte
locations. This equates to 1664 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO falls below the low watermark, flow control
is automatically de-asserted on the SPI3
interface to allow further data to be sent by the
switch fabric to the IXF1104 MAC.
TX FIFO Low
Watermark Port 0
0x60A
R/W
0x000000D0
Low watermark for TX FIFO Port 1. The
default value of 0x0D0 represents 208 8-byte
locations. This equates to 1664 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO falls below the low watermark, flow control
is automatically de-asserted on the SPI3
interface to allow further data to be sent by the
switch fabric to the IXF1104 MAC.
TX FIFO Low
Watermark Port 1
0x60B
0x60C
0x60D
R/W
R/W
R/W
0x000000D0
0x000000D0
0x000000D0
Low watermark for TX FIFO Port 2. The
default value of 0x0D0 represents 208 8-byte
locations. This equates to 1664 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO falls below the low watermark, flow control
is automatically de-asserted on the SPI3
interface to allow further data to be sent by the
switch fabric to the IXF1104 MAC.
TX FIFO Low
Watermark Port 2
Low watermark for TX FIFO Port 3. The
default value of 0x0D0 represents 208 8-byte
locations. This equates to 1664 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO falls below the low watermark, flow control
is automatically de-asserted on the SPI3
interface to allow further data to be sent by the
switch fabric to the IXF1104 MAC.
TX FIFO Low
Watermark Port 3
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 134. TX FIFO MAC Threshold Register Ports 0 - 3 ($0x614 – 0x617)
Name
Description
Address
Type1
Default
MAC threshold for TX FIFO Port 0. The
default value of 0x1BE represents 446 8-byte
locations. This equates to 3568 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO reaches this threshold, data is forwarded
TX FIFO MAC
0x614
R/W
0x000001BE
Threshold Port 0 to the MAC core and line-side interfaces for
onward transmission. By setting the threshold to
an appropriate value, the user can configure the
TX FIFO to operate in a “cut-through” mode
rather than the default “store and forward”
operation mode.
MAC threshold for TX FIFO Port 1. The
default value of 0x1BE represents 446 8-byte
locations. This equates to 3568 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
TX FIFO MAC
FIFO reaches this threshold, data is forwarded
0x615
0x616
0x617
R/W
R/W
R/W
0x000001BE
0x000001BE
0x000001BE
Threshold Port 1 to the MAC core and line-side interfaces for
onward transmission. By setting the threshold to
an appropriate value, the user can configure the
TX FIFO to operate in a “cut-through” mode
rather than the default “store and forward”
operation mode.
MAC threshold for TX FIFO Port 2. The
default value of 0x1BE represents 446 8-byte
locations. This equates to 3568 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
TX FIFO MAC
FIFO reaches this threshold, data is forwarded
Threshold Port 2 to the MAC core and line-side interfaces for
onward transmission. By setting the threshold to
an appropriate value, the user can configure the
TX FIFO to operate in a “cut-through” mode
rather than the default “store and forward”
operation mode.
MAC threshold for TX FIFO Port 3. The
default value of 0x1BE represents 446 8-byte
locations. This equates to 3568 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
TX FIFO MAC
FIFO reaches this threshold, data is forwarded
Threshold Port 3 to the MAC core and line-side interfaces for
onward transmission. By setting the threshold to
an appropriate value, the user can configure the
TX FIFO to operate in a “cut-through” mode
rather than the default “store and forward”
operation mode.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 135. TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E) (Sheet 1 of 2)
Bit
Name
Description
Type1
Default
Register Description: TX FIFO Out of Sequence Event:
These register bits provide status information, and indicate if out-of-sequence data has been
received. The bit position equals the port number + 8. These bits are cleared on Read.
0x0
Register Description: TX FIFO Underflow Event:
This register provides a status that a FIFO Empty situation has occurred (for example, a FIFO
under-run). The bit position equals the port number + 4. This register is cleared on Read.
0x0
Register Description: TX FIFO Overflow Event:
This register provides a status that a FIFO full situation has occurred (for example, a FIFO
overflow). The bit position equals the port number. This register is cleared on Read.
0x0
31:12 Reserved
Reserved
RO
0x00000
Port 3
11
10
9
FOSE3
FOSE2
FOSE1
FOSE0
FUE3
R
0
0
0
0
0
0
0
0
0
0 = FIFO out of sequence event did not occur
1 = FIFO out of sequence event occurred
Port 2
R
R
R
R
R
R
R
R
0 = FIFO out of sequence event did not occur
1 = FIFO out of sequence event occurred
Port 1
0 = FIFO out of sequence event did not occur
1 = FIFO out of sequence event occurred
Port 0
8
0 = FIFO out of sequence event did not occur
1 = FIFO out of sequence event occurred
Port 3
7
0 = FIFO underflow event did not occur
1 = FIFO underflow event occurred
Port 2
6
FUE2
0 = FIFO underflow event did not occur
1 = FIFO underflow event occurred
Port 1
5
FUE1
0 = FIFO underflow event did not occur
1 = FIFO underflow event occurred
Port 0
4
FUE0
0 = FIFO underflow event did not occur
1 = FIFO underflow event occurred
Port 3
3
FOE3
0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 135. TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E) (Sheet 2 of 2)
Bit
Name
Description
Type1
Default
Port 2
2
FOE2
R
0
0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred
Port 1
1
0
FOE1
FOE0
R
R
0
0
0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred
Port 0
0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 136. Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F)
Bit
Name
Description
Type1
Default
Register Description: This register enables data received from the line-side receive interface
through the MAC to be sent to the TX FIFO and back to the line-side transmit interface.
0x00000000
0x0000000
0
31:4 Reserved
Reserved
RO
Port 3 Line-Side
Loopback
0 = Disable line-side loopback
1 = Enable line-side loopback
3
2
1
0
R/W
Port 2 Line-Side
Loopback
0 = Disable line-side loopback
1 = Enable line-side loopback
R/W
R/W
R/W
0
0
0
Port 1 Line-Side
Loopback
0 = Disable line-side loopback
1 = Enable line-side loopback
Port 0 Line-Side
Loopback
0 = Disable line-side loopback
1 = Enable line-side loopback
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 137. TX FIFO Port Reset ($0x620) (Sheet 1 of 2)
Bit
Name
Description
Type1
Default
Register Description: This is a port reset register for each port in the TX block. Port ID = bit
position in the register. To make the port active, the bit must be set to Low. (For example, reset
of Port 3 implies register value = 1000, setting the bit to 1 asserts the port reset).
0x00000000
0x0000000
31:4 Reserved
Reserved
Port 3
RO
3
Port 3 Reset
R/W
0
0 = De-assert Reset
1 = Assert Reset
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 137. TX FIFO Port Reset ($0x620) (Sheet 2 of 2)
Bit
Name
Description
Type1
Default
Port 2
2
Port 2 Reset
R/W
0
0 = De-assert Reset
1 = Assert Reset
Port 1
1
0
Port 1 Reset
Port 0 Reset
R/W
R/W
0
0
0 = De-assert Reset
1 = Assert Reset
Port 0
0 = De-assert Reset
1 = Assert Reset
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 138. TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)
Name
Description
Address
Type*
Default
When TX FIFO on Port 0 becomes full or
reset, the number of frames lost or removed
on this port is shown in this register. This
register is cleared on Read.
TX FIFO overflow
frame drop counter
on Port 0
0x621
R
0x00000000
When TX FIFO on Port 1 becomes full or
reset, the number of frames lost or removed
on this port is shown in this register. This
register is cleared on Read.
TX FIFO overflow
frame drop counter
on Port 1
0x622
0x623
0x624
R
R
R
0x00000000
0x00000000
0x00000000
When TX FIFO on Port 2 becomes full or
reset, the number of frames lost or removed
on this port is shown in this register. This
register is cleared on Read.
TX FIFO overflow
frame drop counter
on Port 2
When TX FIFO on Port 3 becomes full or
reset, the number of frames lost or removed
on this port is shown in this register. This
register is cleared on Read.
TX FIFO overflow
frame drop counter
on Port 3
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 139. TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629)
Name
Description
Address
Type*
Default
This register provides the number of packets
dropped by the TX FIFO due to the following:
Data Parity Errors
Short SOPs (two consecutive SOPs for a port
with no EOP)
TX FIFO errored
frame drop counter
on Port 0
0x625
R
0x00000000
Small Packets (9-14 bytes)
Frames received that are signaled with TERR
on the SPI3 TX interface.
NOTE: This register is cleared on Read.
This register provides the number of packets
dropped by the TX FIFO due to the following:
Data Parity Errors
Short SOPs (two consecutive SOPs for a port
with no EOP)
TX FIFO errored
frame drop counter
on Port 1
0x626
0x627
0x628
R
R
R
0x00000000
0x00000000
0x00000000
Small Packets (9-14 bytes)
Frames received that are signaled with TERR
on the SPI3 TX interface.
NOTE: This register is cleared on Read.
This register provides the number of packets
dropped by the TX FIFO due to the following:
Data Parity Errors
Short SOPs (two consecutive SOPs for a port
with no EOP)
TX FIFO errored
frame drop counter
on Port 2
Small Packets (9-14 bytes)
Frames received that are signaled with TERR
on the SPI3 TX interface.
NOTE: This register is cleared on Read.
This register provides the number of packets
dropped by the TX FIFO due to the following:
Data Parity Errors
Short SOPs (two consecutive SOPs for a port
with no EOP)
TX FIFO errored
frame drop counter
on Port 3
Small Packets (9-14 bytes)
Frames received that are signaled with TERR
on the SPI3 TX interface.
NOTE: This register is cleared on Read.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 140. TX FIFO Occupancy Counter for Ports 0 - 3 ($0x62D – 0x630)
Name
Description
Address
Type
Default
Occupancy for Tx
FIFO Port 0
This register gives the Occupancy for TX FIFO
Port 0. This is a Read only register
0x62D
R
0x00000000
Occupancy for Tx
FIFO Port 1
This register gives the Occupancy for TX FIFO
Port 1. This is a Read only register
0x62E
0x62F
0x630
R
R
R
0x00000000
0x00000000
0x00000000
Occupancy for Tx
FIFO Port 2
This register gives the Occupancy for TX FIFO
Port 2. This is a Read only register
Occupancy for Tx
FIFO Port 3
This register gives the Occupancy for TX FIFO
Port 3. This is a Read only register
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 141. TX FIFO Port Drop Enable ($0x63D)
Bit
Name
Description
Type
Default
Register Description: Independently enables the individual TX FIFOs to drop erroneous
packets.
0x0000000f
0x000000
1
31:4
3
Reserved
Reserved
RO
0 = Disable the TXFIFO from dropping erroneous packets
1 = Enable the TXFIFO to drop erroneous packets
Port 3 Drop
R/W
0 = Disable the TXFIFO from dropping erroneous packets
1 = Enable the TXFIFO to drop erroneous packets
2
1
0
Port 2 Drop
Port 1 Drop
Port 0 Drop
R/W
R/W
R/W
1
1
1
0 = Disable the TXFIFO from dropping erroneous packets
1 = Enable the TXFIFO to drop erroneous packets
0 = Disable the TXFIFO from dropping erroneous packets
1 = Enable the TXFIFO to drop erroneous packets
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
8.4.8
MDIO Register Overview
Table 142. MDIO Single Command ($0x680)
Bit
Name
Description
Type1
Default
Register Description: Gives the CPU the ability to perform single MDIO read and write
accesses to the external PHY for ports that are configured in copper mode.
0x00010000
31:21 Reserved
Reserved
RO
R/W
RO
00000000000
Performs the MDIO operation. Cleared when
done.
20
MDIO Command
0
0 = MDIO ready, operation complete
1 = Perform operation
19:18 Reserved
Reserved
00
MDIO Op Code; two bits identify operation to be
performed:
00 =Reserved
01 =Write operation (as defined in IEEE 802.3,
clause 22.2.4.5)
17:16 OP Code
R/W
01
10 =Read operation (as defined in IEEE 802.3,
clause 22.2.4.5)
11 = Reserved
Reserved
15:10 Reserved
RO
R/W
RO
000000
00
Sets bits 1:0 of the external PHY address. Bits 4:2
of the PHY address are fixed at 000.
9:8
7:5
4:0
PHY Address
Reserved
Reserved
000
Five-bit address to one among 32 registers in an
addressed PHY device.
REG Address
R/W
00000
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 143. MDIO Single Read and Write Data ($0x681)
Bit
Name
Description
Type1
Default
Register Description: MDIO read and write data.
0x00000000
0x0000
31:16 MDIO Read Data
15:0 MDIO Write Data
MDIO Read data from external device.
MDIO Write data to external device.
RO
R/W
0x0000
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 144. Autoscan PHY Address Enable ($0x682)
Bit
Name
Description
Type1
Default
Register Description: Defines valid PHY addresses. Each bit enables the corresponding
PHY address.
0x00000000
0 = Disable the PHY address
1 = Enable the PHY address
NOTE: Autoscan is only applicable for the ports in copper mode.
31:4 Reserved
Reserved
RO
0x0000000
1111
Autoscan PHY address enable
Autoscan PHY
Address
3:0
R/W
0 = Disable address
1 = Enable address
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 145. MDIO Control ($0x683)
Bit
Name
Description
Type1
Default
Register Description: Miscellaneous control bits.
0x00000000
0x000
31:4 Reserved
Reserved
RO
RO
MDIO progress. This bit reflects the status of
MDIO transaction
3
MDIO in Progress
0
0 = MDIO Single command not in progress
1 = MDIO Single Command in progress
Enables the MDIO in progress bit
MDIO in Progress
Enable
2
1
0
R/W
R/W
R/W
0
0
0
0 = Disable MDIO in progress register bit
1 = Enable MDIO in progress register bit
Autoscan enable
Autoscan Enable
MDC Speed
0 = Disable Autoscan
1 = Enable Autoscan
MDC speed
0 = MDC runs at 2.5 MHz
1 = MDC runs at 18 MHz
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
8.4.9
SPI3 Register Overview
provide an overview of the SPI3 registers.
Table 146. SPI3 Transmit and Global Configuration ($0x700) (Sheet 1 of 3)
Bit
Name
Description
Type1
Default
Register Description: This register gives the configuration related to the SPI3 Transmitter
and Global configuration (4 x 8 mode).
0x00200000
31:24 Reserved
Reserved
RO
0x00
0
SPI3 Transmitter Soft
23
22
1 = The SPI3 TX block is reset.
R/W
Reset
SPI3 Receiver Soft
Reset
1 = The SPI3 RX block is reset.
R/W
0
0 = Indicates that SPI3 block operates in 32-bit
MPHY mode.
1 = Indicates that the SPI3 block operates in 4 x 8
SPHY mode.
21
20
SPHY/MPHY Mode
Tx_ad_prtyer_drop
R/W
1
This configuration affects both the SPI3 transmitter
and receiver functionality.
Indicates whether to drop packets received with
parity error during the address selection phase
(Tsx and nTenb High) should be dropped.
0 = Do not drop packets with address parity error
1 = Drop packets with address parity error
R/W
0
This is applicable only in MPHY mode of
operation. This bit is ignored in SPHY (4 x 8) mode
as there will be no address selection.
SPHY/MPHY Mode:
Indicates whether to drop packets with data parity
error for port 3.
19
18
17
Dat_prtyer_drp Port 3
Dat_prtyer_drp Port 2
Dat_prtyer_drp Port 1
R/W
R/W
R/W
0x0
0 = Do not drop packets with data parity error
(default)
1 = Drop packets with data parity error
SPHY/MPHY Mode:
Indicates whether to drop packets with data parity
error for port 2.
0
0 = Do not drop packets with data parity error
(default)
1 = Drop packets with data parity error
SPHY/MPHY Mode:
Indicates whether to drop packets with data parity
error for port 1.
0
0 = Do not drop packets with data parity error
(default)
1 = Drop packets with data parity error
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 146. SPI3 Transmit and Global Configuration ($0x700) (Sheet 2 of 3)
Bit
Name
Description
Type1
Default
SPHY/MPHY Mode:
Indicates whether to drop packets with data parity
error for port 0.
16
Dat_prtyer_drp Port 0
R/W
R/W
0
0 = Do not drop packets with data parity error
(default)
1 = Drop packets with data parity error
15:8 Reserved
Write as 0, ignore on Read.
00000000
SPHY Mode:
Indicates the parity sense to check the parity on
TDAT bus for port 3.
7
6
5
Tx_parity_sense Port 3 0 = Odd Parity
R/W
R/W
R/W
0
0
0
1 = Even Parity
MPHY Mode:
NA
SPHY Mode:
Indicates the parity sense to check the parity on
TDAT bus for port 2.
Tx_parity_sense Port 2 0 = Odd Parity
1 = Even Parity
MPHY Mode:
NA
SPHY Mode:
Indicates the parity sense to check the parity on
TDAT bus for port 1.
Tx_parity_sense Port 1 0 = Odd Parity
1 = Even Parity
MPHY Mode:
NA
SPHY Mode:
Indicates the parity sense to check the parity on
TDAT bus for port 0.
0 = Odd Parity
1 = Even Parity
4
Tx_parity_sense Port 0
R/W
0
MPHY Mode:
Indicates the parity sense to check the parity on
TDAT bus for all ports.
0 = Odd Parity
1 = Even Parity
SPHY Mode:
0 = Disables the selected SPI3TX port 3.
1 = Enables the selected SPI3 TX port 3.
3
Tx_port_enable Port 3
R/W
1
MPHY Mode:
0 = Disables the selected SPI3 TX port 3.
1 = Enables the selected SPI3 TX port 3.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 146. SPI3 Transmit and Global Configuration ($0x700) (Sheet 3 of 3)
Bit
Name
Description
Type1
Default
SPHY Mode:
0 = Disables the selected SPI3 TX port 2
1 = Enables the selected SPI3 TX port 2
2
Tx_port_enable Port 2
R/W
1
MPHY Mode:
0 = Disables the selected SPI3 TX port 2
1 = Enables the selected SPI3 TX port 2
SPHY Mode:
0 = Disables the selected SPI3 TX port 1
1 = Enables the selected SPI3 TX port 1
1
0
Tx_port_enable Port 1
Tx_port_enable Port 0
R/W
R/W
1
1
MPHY Mode:
0 = Disables the selected SPI3 TX port 1
1 = Enables the selected SPI3 TX port 1
SPHY Mode:
0 = Disables the selected SPI3 TX port 0
1 = Enables the selected SPI3 TX port 0
MPHY Mode:
0 = Disables the selected SPI3 TX port 0
1 = Enables the selected SPI3 TX port 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 147. SPI3 Receive Configuration ($0x701) (Sheet 1 of 4)
Bit
Name
Description
Type1
Default
Register Description: This register gives the configuration related to the SPI3 receiver.
0x00000F80
0x0
31:28 Reserved
Reserved
RO
SPHY Mode:
Indicates the number of pause cycles to be
introduced between back-to-back transfers for
port 3.
27
B2B_PAUSE Port 3
R/W
0
0 = Zero pause cycles
1 = Two pause cycles
MPHY Mode:
NA
SPHY Mode:
Indicates the number of pause cycles to be
introduced between back-to-back transfers for
port 2.
26
B2B_PAUSE Port 2
R/W
0
0 = Zero pause cycles
1 = Two pause cycles
MPHY Mode:
NA
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 147. SPI3 Receive Configuration ($0x701) (Continued) (Sheet 2 of 4)
Bit
Name
Description
Type1
Default
SPHY Mode:
Indicates the number of pause cycles to be
introduced between back-to-back transfers for
port 1.
25
B2B_PAUSE Port 1
R/W
0
0 = Zero pause cycles
1 = Two pause cycles
MPHY Mode:
NA
SPHY Mode:
Indicates the number of pause cycles to be
introduced between back-to-back transfers for
port 0.
0 = Zero pause cycles
1 = Two pause cycles
24
B2B_PAUSE Port 0
R/W
0
MPHY Mode:
Indicates the number of pause cycles to be
introduced between back-to-back transfers for all
ports.
0 = Zero pause cycles
1 = Two pause cycles
SPHY Mode:
NA
23:22 RX_BURST Port 3
21:20 RX_BURST Port 2
19:18 RX_BURST Port 1
R/W
R/W
R/W
0x0
0x0
0x0
MPHY Mode:
NA
SPHY Mode:
NA
MPHY Mode:
NA
SPHY Mode:
NA
MPHY Mode:
NA
SPHY Mode:
NA
MPHY Mode:
Selects the maximum burst size on the RX path
for all ports.
17:16 RX_BURST Port 0
R/W
0x0
0x = 64 bytes maximum burst size
10 = 128 bytes maximum burst size
11 = 256 bytes maximum burst size
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 147. SPI3 Receive Configuration ($0x701) (Continued) (Sheet 3 of 4)
Bit
Name
Description
Type1
Default
SPHY Mode:
Indicates the parity sense to check the parity on
RDAT bus for port 3.
15
Rx_parity_sense Port 3 0 = Odd Parity
1 = Even Parity
R/W
0x0
MPHY Mode:
NA
SPHY Mode:
Indicates the parity sense to check the parity on
RDAT bus for port 2.
14
13
Rx_parity_sense Port 2 0 = Odd Parity
1 = Even Parity
R/W
0x0
MPHY Mode:
NA
SPHY Mode:
Indicates the parity sense to check the parity on
RDAT bus for port 1.
Rx_parity_sense Port 1 0 = Odd Parity
1 = Even Parity
R/W
0x0
MPHY Mode:
NA
SPHY Mode:
Indicates the parity sense to check the parity on
RDAT bus for port 0.
0 = Odd Parity
1 = Even Parity
12
Rx_parity_sense Port 0
R/W
0x0
MPHY Mode:
Indicates the parity sense to check the parity on
RDAT bus for all ports.
0 = Odd Parity
1 = Even Parity
SPHY Mode:
0 = Disables the selected SPI3 RX port.
1 = Enables the selected SPI3 RX port.
Rx_port_enable
Port 3
11
10
R/W
R/W
0x1
0x1
MPHY Mode:
0 = Disables the selected SPI3 RX port.
1 = Enables the selected SPI3 RX port.
SPHY Mode:
0 = Disables the selected SPI3 RX port.
1 = Enables the selected SPI3 RX port.
Rx_port_enable
Port 2
MPHY Mode:
0 = Disables the selected SPI3 RX port.
1 = Enables the selected SPI3 RX port.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 147. SPI3 Receive Configuration ($0x701) (Continued) (Sheet 4 of 4)
Bit
Name
Description
Type1
Default
SPHY Mode:
0 = Disables the selected SPI3 RX port.
1 = Enables the selected SPI3 RX port.
Rx_port_enable
Port 1
9
R/W
0x1
MPHY Mode:
0 = Disables the selected SPI3 RX port.
1 = Enables the selected SPI3 RX port.
SPHY Mode:
0 = Disables the selected SPI3 RX port.
1 = Enables the selected SPI3 RX port.
Rx_port_enable
Port 0
8
R/W
0x1
MPHY Mode:
0 = Disables the selected SPI3 RX port.
1 = Enables the selected SPI3 RX port.
SPHY Mode:
NA. Write as 1, ignore on Read.
MPHY Mode:
7
Rx_core_enable
R/W
R/W
0x1
0 = Disables the RX SPI3 core.
1 = Enables the RX SPI3 core.
SPHY Mode:
NA. Write as 0, ignore on Read.
MPHY Mode:
6:1
IBA[5:0]
0x00
Sets the 6-bit value appended to the 2-bit
address during the port address selection.
SPHY Mode/MPHY Mode:
Frames marked to be filtered (based on the
settings in the “RX Packet Filter Control ($
not dropped in the RX FIFO (see “RX FIFO
optionally indicated with an RERR when sent out
the SPI3 interface.
0
RERR_enable
R/W
0
0 = Packets not indicated with RERR.
1 = Packets indicated with RERR.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 148. Address Parity Error Packet Drop Counter ($0x70A)
Bit
Name
Description
Type1
Default
Register Description: This register counts the number of packets dropped due to parity error
detection during the address selection cycle.
0x00000000
0x000000
31:8 Reserved
Reserved
RO
R
This is an 8-bit counter that counts the number of
packets dropped due to parity error detection
during the address selection cycle. This gets
cleared when read and saturates at 8’hFF. There
is only one counter for address parity drop as
address will be used only in MPHY mode of
operation. The counter gets cleared once the
register is read.
Address Parity Error
Packet Drop Counter
7:0
0x00
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
8.4.10
SerDes Register Overview
page 221 define the contents of the SerDes registers at base location 0x780, which contain the
control and status for the four SerDes interfaces on the IXF1104 MAC.
Table 149. TX Driver Power Level Ports 0 - 3 ($0x784)
Bit
Name
Description
Type
Default
Register Description: Allows selection of various programmable drive strengths on each
SerDes port. Refer to Section 5.6.2.2, “Transmitter Programmable Driver-Power Levels” on
0x0000dddd
31:16
15:12
11:8
7:4
Reserved
Reserved
RO
0x0000
1101
DRVPWR3[3:0]
DRVPWR2[3:0]
DRVPWR1[3:0]
DRVPWR0[3:0]
Encoded input that sets Power Level for Port 3
Encoded input that sets Power Level for Port 2
Encoded input that sets Power Level for Port 1
Encoded input that sets Power Level for Port 0
R/W
R/W
R/W
R/W
1101
1101
3:0
1101
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 150. TX and RX Power-Down ($0x787)
Bit
Name
Description
Type
Default
Register Description: TX and RX power-down bits to allow per-port power-down of unused
ports
0x00000000
31:14
13:10
9:4
Reserved
Reserved
RO
R/W
RO
0x0000000
0000
TPWRDWN[3:0]
Reserved
TX power-down for Ports 3-0 (1 = Power-down)
Reserved
0x00
3:0
RPWRDWN[3:0]
RX Power-down for Ports 3-0 (1 = Power-down)
R/W
0000
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 151. RX Signal Detect Level Ports 0 - 3 ($0x793)
Bit
Name
Description
Type1
Default
Register Description: This register shows the status of the Rx input in relation to the level of
the signal being received from the line. This register is meant for debug and test use.
0x00000000
0x0000000
31:4 Reserved
Reserved
RO
RO
Signal Detect for Ports 0-3
3:0
SIGDET[3:0]
0x0
0 = Noise
1 = Signal
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 152. Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)
Bit
Name
Description
Type1
Default
Register Description: This register is used when a change to the operational mode or speed
of the IXF1104 MAC is required. This register ensures that when a change is made that the
internal clocking of the IXF1104 MAC is managed correctly and no unexpected effects of the
operational or speed change are observable on the line interfaces.
0x00000000
0x0000000
31:4 Reserved
Reserved
RO
Enables internal clock generator for Port 3 to
Clock and Interface
0 = Set to zero when changes are being made to
3
2
1
0
Mode Change Enable
R/W
0
0
0
0
Port 32
1 = Set to 1 for the configuration changes to take
effect.
Enables internal clock generator for Port 2 to
Clock and Interface
Mode Change Enable
Port 22
0 = Set to zero when changes are being made to
R/W
R/W
R/W
1 = Set to 1 for the configuration changes to take
effect.
Enables internal clock generator for Port 1 to
Clock and Interface
Mode Change Enable
Port 12
0 = Set to zero when changes are being made to
1 = Set to 1 for the configuration changes to take
effect.
Enables internal clock generator for Port 0 to
Clock and Interface
Mode Change Enable
Port 02
0 = Set to zero when changes are being made to
1 = Set to 1 for the configuration changes to take
effect.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
2. Refer to Section 6.1, “Change Port Mode Initialization Sequence” on page 130 for the proper sequence to
change the port mode and speed in conjunction with this register.
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
8.4.11
Optical Module Register Overview
the Optical Module Registers.
Note: All registers in this section are only applicable to ports that are configured in fiber mode.
Table 153. Optical Module Status Ports 0-3 ($0x799)
Bit
Name
Description
Type1
Default
Register Description: This register provides a means to control and monitor the interface to
the optical modules when a port is used in fiber mode.
0x00000000
31:24 Reserved
Reserved
RO
R
0x00
0x0
23:20 Rx_LOS_3:0
19:14 Reserved
Rx_LOS inputs for Ports 0-3
Reserved
0X00
0x0
13:10 Tx_FAULT_3:0
Tx_FAULT inputs for Ports 0-3
Reserved
R
9:4
3:0
Reserved
0X00
0x0
MOD_DEF_3:0
MOD_DEF inputs for Ports 0-3
R
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 154. Optical Module Control Ports 0 - 3 ($0x79A)
Bit
Name
Description
Type1
Default
Register Description: This register provides access to optical module interrupt enables and
sets the TX_DISABLE output for the ports configured in fiber mode.
0x1E000
31:17 Reserved
Reserved
RO
0x0000
0xF
16:13 I2C_port_enable
When set, individually enables the four I2C ports.
R/W
Enable for RX_LOS_INT operation
1 = Enabled
12
11
10
RX_LOS_EN
R/W
R/W
R/W
0
0
0
Enable for TX_FAULT_INT operation
1 = Enabled
TX_FAULT_EN
MOD_DEF_EN
Enable for MOD_DEF_INT operation
1 = Enabled
9:4
3:0
Reserved
Reserved
RO
0X00
0x0
TX_DISABLE_3:0
Tx_DISABLE outputs for Ports 0-3
R/W
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 155. I2C Control Ports 0 - 3 ($0x79B)
Bit
Name
Description
Type1
Default
Register Description: This register controls and monitors the interface to the optical modules
when used in fiber mode.
0x00000000
31:29 Reserved
Reserved
RO
R
0x0
0
28
27
Port address Err (R)
Port addressing error.
An attempt to write to the protected E2PROM has
occurred.
wp_err
R
0
This bit is set to 1 when a write and subsequent
read from an Optical Module Interface has failed.
This signal should be used to validate the data
being read. Data is only valid if this bit is equal to
zero.
26
no_ack_err
R
0
25
24
23
22
21
20
I2C_enable
I2C_start
Enable the I2C block.
Start the I2C transfer.
Reserved
R/W
R/W
RO
R
0
0
0
0
0
0
0
Reserved
write_complete
Reserved
Bit is asserted when write access is complete.
Reserved
RO
R
Read_complete
Bit asserted when read access is complete.
Reserved
19:18 Reserved
17:16 Port Select
RO
Selects the port for which the I2C transaction is
targeted. Valid range is 0 to 3.
R/W
00
0 = Write transaction
1 = Read transaction
15
Read/Write
R/W
R/W
0
14:11 Device ID
Most-significant four bits of device address field.
0x0
Bits 10:8 select the least-significant three bits of
the device address field
10:0 Register Address
R/W
0x000
Bits 7:0 select the word/register address
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 156. I2C Data Ports 0 - 3 ($0x79F)
Bit
Name
Description
Type1
Default
Register Description: These registers hold data bytes that are read and written using the I2C
interface to Optical Module Interfaces connected to each port of the Intel® IXF1104 4-Port
Gigabit Ethernet Media Access Controller.
0x00000000
31:24 Reserved
23:16 Write Data
15:8 Reserved
Reserved
RO
R/W
RO
0x00
0X00
0x00
0X00
Bit 23=MSB, Bit 16 = LSB
Data to be written to the Optical Module Interface.
Reserved
Bit 7 = MSB, Bit 0 = LSB
7:0
Read Data
R/W
Data read from the Optical Module Interface.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
9.0
Mechanical Specifications
The IXF1104 MAC is packaged in a 576-ball BGA package with 6 balls removed diagonally from
each corner, for a total of 552 balls used measuring 25 mm x 25 mm. The pitch of the package balls
is 1 mm.
9.1
Overview
CBGA (standard and RoHS-compliant) and FC-PBGA packages are suited for applications
requiring high I/O counts and high electrical performance, and are recommended for high-power
applications with high noise immunity requirements.
Note: The FC-PBGA package will not be available until mid-2006. Please see your field sales
representative for more detailed information.
9.1.1
Features
• Flip chip die attach; surface mount second-level interconnect
• High electrical performance
• High I/O counts
• Area array I/O options
• Multiple power-zone offering supports core and four additional voltages
• JEDEC-compliant package
9.2
Package Specifics
The IXF1104 MAC uses the following package:
• 576-ball BGA package with 6 balls removed diagonally from each corner, for a total of 552
balls used
• Ball pitch of 1.0 mm
• Overall package dimensions of 25 mm x 25 mm
Datasheet
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Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
9.3
Package Information
9.3.1
CBGA Package Diagrams
Figure 55. CBGA Package Diagram
Chip
47P6802
Substrate
3.938
7.877
(25 ± 0.2)
Note: All dimensions are in mm.
B0034-01
(575X) (ø0.8 ± 0.05)
L
D A
S
B
S
ø
(0.825 MAX)
(0.325 MIN)
= Ball
= No ball
(23x) TYP
Chip Carrier
A01 Corner
(23)
(25 ± 0.2)
Note: All dimensions are in mm.
B0035-03
225
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Figure 56. CBGA Package Side View Diagram
45L4867 (552)
Solder ball
C4 Encapsulant
Fillet
Chip
0.81 ± 0.1
(2.47 Max)
(2.03 Min)
(6X) (0.77 Max)
(0.69 Min)
(6X) (3.24 Max)
(2.72 Min)
(6X) (4.16 Max)
(3.43 Min)
(0.857 Max)
(0.779 Min)
(3.327 Max)
(2.809 Min)
(4.237 Max)
(3.619 Min)
0.15
C
Seating Plane
Note: All dimensions are in mm.
B0555-01
Datasheet
226
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
9.3.2
Flip Chip-Plastic Ball Grid Array Package Diagram
PBGA mechanical specifications.
Note: Please contact your field sales representative for more information on the FC-PBGA package.
Figure 57. FC-PBGA Package (Top and Bottom Views)
D
A
25.0 Nom – 0.2
TOP VIEW
aaa (0.20)
All around
E
25.0 Nom – 0.2
Terminal A01
Identifier
B
Lid
// ccc (0.35)
A1
C
(0.40 min)
A
(3.27 max)
// bbb (0.25)
C
Substrate
Seating Plane
ddd (0.20)
C
A
B
C
BOTTOM VIEW
01
02
03
e
Basic
1.00 mm
łb
(0.55 min
0.75 max)
M
M
C A
C
B
łeee (0.25)
łfff (0.10)
e
Basic
1.00 mm
Legend:
Notes:
= No Ball
= Ball
All dimensions are in millimeters.
B5181-02
227
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
9.3.3
Top Label Marking Example
Figure 59 shows the IXF1104 MAC non-RoHS-compliant device marking label.
Note:
In contrast to the Pb-Free (RoHS-compliant) package, the non-RoHS-compliant package does not
have the “e1” symbol.
Figure 59. Package Marking Example
Topside fields not to scale
Pin 1 mark
Syww9001
Country
= Intel Product Number
AAA000AAA
= Intel Silicon revision number, A0, A1, B0 …
XX
e1
= Pb-Reduced indicator (Same as Jedec)
= Intel Finished Process Order (FPO) number
= Substrate material number (barely visible)
Syww9001
Substrate PN
Back of the die
(Bare Silicon)
= Manufacturing Lot Number
= Assy plant Country of Origin
JJJJJJJJ
Country
= Quality Level, P: Proto Type, PQ: Potential Qual’able,
“ ”: Production (no marking)
QQ
7.5 x 7.5 mm
= Rework Indicator
++
Substrate PN
25.0 mm
++
25.0 mm
Character Font
Size
0.04 - 0.10”
0.19 - 0.24”
Diameter of Pin 1 mark is 70 mils,
and is located opposite the top-side
substrate “Pin 1” identifier.
®
0.07 - 0.12”
R
0.06 - 0.10”
Note: Diameter of Trademark Circles are 70 mils.
Height of circles surrounding Pb-redced symbol are
equal to overall character height
NOTE: * "Pin 1
" does mean a Pin1 indicator, not an actual mark.
B5131-01
NOTE: The actual product name marking is IXF1104CE, not HFIXF1104CE (leaded version) and
WFIXF1104CE (Pb-reduced), due to lidless package space limitation.
229
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
10.0
Product Ordering Information
Table 157. Product Information
Package
Type
RoHS-
Compliant
Product Number
Revision
B0
CBGA
No
HFIXF1104CE.B0
WFIXF1104CE.B0
HPIXF1104BE.B01
NOTE:
B0
B0
CBGA
PBGA
Yes
No
1. Please contact your field sales representative for detailed
information on the FC-PBGA package.
Datasheet
230
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Figure 60. Ordering Information – Sample
HF
IXF
1104
C
E
B0
Product Revision
xn = 2 Alphanumeric characters
Temperature Range
A = Ambient (0 – 550 C)
C = Commercial (0 – 700 C)
E = Extended (-40 – 850 C)
Internal Package Designator
L = LQFP
P = PLCC
N = DIP
Q = PQFP
H = QFP
T = TQFP
B = BGA
C = CBGA
E = TBGA
K = HSBGA (BGA with heat slug
Product Code
xxxxx = 3-5 Digit alphanumeric
IXA Product Prefix
LXT = PHY layer device
IXE = Switching engine
IXF = Formatting device (MAC/Framer)
IXP = Network processor
Intel Package Designator
B5118-03
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Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
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