Fujitsu MB91460 SERIES FR60 User Manual
FUJITSU SEMICONDUCTOR  
CM71-xxxxx-1E  
CONTROLLER MANUAL  
FR60  
32-BIT MICROCONTROLLER  
MB91460 Series  
User’s Manual  
Version 1.00  
2006-10-22  
- PRELIMINARY -  
FR60  
32-BIT MICROCONTROLLER  
MB91460 Series  
User’s Manual  
•
•
The contents of this document are subject to change without notice.  
Customers are advised to consult with FUJITSU sales representatives before ordering.  
The information, such as descriptions of function and application circuit examples, in this document are presented solely  
for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not  
warrant proper operation of the device with respect to use based on such information. When you develop equipment  
incorporating the device based on such information, you must assume any responsibility arising out of such use of the  
information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information.  
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as  
license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of  
Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party' s intellectual property right or other  
right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other  
rights of third parties which would result from the use of information contained herein.  
The products described in this document are designed, developed and manufactured as contemplated for general use,  
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not  
designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless  
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,  
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic  
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use  
requiring extremely high reliability (i.e., submersible repeater and artificial satellite).  
•
•
Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection  
with above-mentioned uses of the products.  
•
•
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such  
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and  
prevention of over-current levels and other abnormal operating conditions.  
If any products described in this document represent goods or technologies subject to certain restrictions on export under  
the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required  
for export of those products from Japan.  
©2004 FUJITSU LIMITED Printed in Japan  
-i  
TOC  
Chapter 1 Introduction......................................................................................... 1  
1.  
2.  
3.  
4.  
How to Handle the Device ..................................................................................................... 1  
Instruction for Users............................................................................................................... 3  
Caution: debug-related matters ............................................................................................. 6  
How to Use This Document................................................................................................... 7  
Chapter 2 MB91460 Rev.A/Rev.B Overview..................................................... 11  
1.  
2.  
3.  
4.  
Overview.............................................................................................................................. 11  
Features............................................................................................................................... 11  
MB91460 Series Product Lineup......................................................................................... 19  
Block Diagram ..................................................................................................................... 21  
Chapter 3 MB91460 Series Basic Information ................................................. 23  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Memory Map........................................................................................................................ 23  
I/O Map................................................................................................................................ 24  
Interrupt Vector Table.......................................................................................................... 73  
Package............................................................................................................................... 78  
Pin Assignment Diagram ..................................................................................................... 79  
Pin Definitions...................................................................................................................... 80  
I/O Circuit Type.................................................................................................................... 94  
Pin State Table .................................................................................................................... 96  
Chapter 4 CPU Architecture ............................................................................ 105  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
9.  
Overview............................................................................................................................ 105  
Features............................................................................................................................. 106  
CPU ................................................................................................................................... 107  
32-bit/16-bit Bus Converter................................................................................................ 107  
Harvard/Princeton Bus Converter...................................................................................... 107  
Instruction Overview .......................................................................................................... 108  
Data Structure.................................................................................................................... 109  
Word Alignment ................................................................................................................. 110  
Addressing......................................................................................................................... 111  
Chapter 5 CPU Registers................................................................................. 113  
1.  
General-purpose Registers................................................................................................ 113  
2.  
Dedicated Registers .......................................................................................................... 113  
Chapter 6 EIT: Exceptions, Interrupts and Traps.......................................... 121  
1.  
2.  
3.  
4.  
5.  
Overview............................................................................................................................ 121  
Features............................................................................................................................. 121  
EIT Trigger......................................................................................................................... 121  
Return from EIT ................................................................................................................. 121  
EIT Interrupt Level ............................................................................................................. 122  
i
6.  
7.  
8.  
9.  
EIT Vector Table................................................................................................................ 122  
Multiple EIT Processing..................................................................................................... 123  
Operation........................................................................................................................... 125  
Caution .............................................................................................................................. 128  
Chapter 7 Branch Instruction.......................................................................... 129  
1.  
2.  
3.  
4.  
5.  
6.  
Branch Instruction with Delay Slot..................................................................................... 129  
Operation of Branch Instruction with Delay Slot ................................................................ 129  
Actual Example (with Delay Slot)....................................................................................... 130  
Restrictions on Branch Instruction with Delay Slot ............................................................ 131  
Branch Instruction without Delay Slot................................................................................ 132  
Operation of Branch Instruction without Delay Slot ........................................................... 132  
Chapter 8 Device State Transition .................................................................. 133  
1.  
2.  
3.  
Overview............................................................................................................................ 133  
Features............................................................................................................................. 133  
State Transition Diagram................................................................................................... 134  
Chapter 9 Reset ................................................................................................ 139  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
9.  
Overview............................................................................................................................ 139  
Features............................................................................................................................. 139  
Configuration ..................................................................................................................... 140  
Registers............................................................................................................................ 141  
INIT Pin Input (INIT: Settings Initialization Reset) ............................................................ 146  
Watchdog Reset (INIT: Settings Initialization Reset)......................................................... 148  
Software Reset (RST: Operation Initialization Reset)....................................................... 149  
Reset Operation Modes..................................................................................................... 150  
MCU Operation Mode........................................................................................................ 151  
10. Caution .............................................................................................................................. 152  
Chapter 10 Standby............................................................................................ 155  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 155  
Features............................................................................................................................. 155  
Configuration ..................................................................................................................... 156  
Registers............................................................................................................................ 157  
Operation........................................................................................................................... 159  
Settings.............................................................................................................................. 161  
Q&A ................................................................................................................................... 161  
Caution .............................................................................................................................. 165  
Chapter 11 Memory Controller.......................................................................... 167  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
Overview............................................................................................................................ 167  
FLASH Interface ................................................................................................................ 167  
General Purpose RAM....................................................................................................... 167  
Instruction Cache and Data Buffer..................................................................................... 167  
Prefetch ............................................................................................................................. 167  
Fixed Mode and Reset Vectors ......................................................................................... 167  
Registers............................................................................................................................ 168  
ii  
8.  
Explanations of Registers.................................................................................................. 169  
Chapter 12 Instruction Cache............................................................................ 179  
1.  
2.  
3.  
4.  
5.  
General description............................................................................................................ 179  
Main body structure ........................................................................................................... 179  
Operating mode conditions................................................................................................ 185  
Cacheable areas in the instruction cache.......................................................................... 186  
Settings for handling the I-Cache ...................................................................................... 186  
Chapter 13 Clock Control .................................................................................. 189  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 189  
Features............................................................................................................................. 189  
Configuration ..................................................................................................................... 190  
Registers............................................................................................................................ 191  
Operation........................................................................................................................... 199  
Settings.............................................................................................................................. 201  
Q & A ................................................................................................................................. 202  
Caution .............................................................................................................................. 205  
Chapter 14 PLL Interface ................................................................................... 207  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
Overview............................................................................................................................ 207  
Features............................................................................................................................. 207  
Frequency calculation........................................................................................................ 207  
Registers............................................................................................................................ 208  
Recommended Settings .................................................................................................... 212  
Clock Auto Gear Up/Down................................................................................................. 213  
Caution .............................................................................................................................. 215  
Chapter 15 CAN Clock Prescaler ...................................................................... 217  
1.  
2.  
3.  
Overview............................................................................................................................ 217  
Features............................................................................................................................. 217  
Registers............................................................................................................................ 218  
Chapter 16 Clock Supervisor ............................................................................ 221  
1.  
2.  
3.  
4.  
Overview Clock Supervisor................................................................................................ 221  
Clock Supervisor Register ................................................................................................. 222  
Block Diagram Clock Supervisor ....................................................................................... 224  
Operation Modes ............................................................................................................... 225  
Chapter 17 Clock Modulator.............................................................................. 239  
1.  
2.  
3.  
Overview............................................................................................................................ 239  
Clock Modulator Registers................................................................................................. 240  
Application Note................................................................................................................. 247  
Chapter 18 Timebase Counter........................................................................... 249  
1.  
Overview............................................................................................................................ 249  
2.  
Features............................................................................................................................. 249  
iii  
3.  
4.  
5.  
6.  
7.  
8.  
Configuration ..................................................................................................................... 250  
Registers............................................................................................................................ 251  
Operation........................................................................................................................... 253  
Settings.............................................................................................................................. 259  
Q&A ................................................................................................................................... 260  
Caution .............................................................................................................................. 262  
Chapter 19 Timebase Timer............................................................................... 263  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 263  
Features............................................................................................................................. 263  
Configuration ..................................................................................................................... 264  
Register ............................................................................................................................. 265  
Operation........................................................................................................................... 267  
Setting................................................................................................................................ 268  
Q & A ................................................................................................................................. 269  
Caution .............................................................................................................................. 271  
Chapter 20 Software Watchdog Timer.............................................................. 273  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 273  
Features............................................................................................................................. 273  
Configuration ..................................................................................................................... 274  
Register ............................................................................................................................. 275  
Operation........................................................................................................................... 278  
Setting................................................................................................................................ 280  
Q & A ................................................................................................................................. 281  
Caution .............................................................................................................................. 282  
Chapter 21 Hardware Watchdog Timer ............................................................ 283  
1.  
2.  
3.  
4.  
5.  
Overview............................................................................................................................ 283  
Configuration ..................................................................................................................... 284  
Register ............................................................................................................................. 285  
Functions ........................................................................................................................... 287  
Caution .............................................................................................................................. 288  
Chapter 22 Main Oscillation Stabilisation Timer ............................................. 289  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 289  
Features............................................................................................................................. 289  
Configuration ..................................................................................................................... 290  
Register ............................................................................................................................ 291  
Operation........................................................................................................................... 292  
Setting................................................................................................................................ 294  
Q & A ................................................................................................................................. 295  
Caution .............................................................................................................................. 297  
Chapter 23 Sub Oscillation Stabilisation Timer............................................... 299  
1.  
2.  
3.  
Overview............................................................................................................................ 299  
Features............................................................................................................................. 299  
Configuration ..................................................................................................................... 300  
iv  
4.  
5.  
6.  
7.  
8.  
Register ............................................................................................................................. 301  
Operation........................................................................................................................... 303  
Setting................................................................................................................................ 306  
Q & A ................................................................................................................................. 307  
Caution .............................................................................................................................. 309  
Chapter 24 Interrupt Control ............................................................................. 311  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 311  
Features............................................................................................................................. 311  
Configuration ..................................................................................................................... 312  
Registers............................................................................................................................ 313  
Operation........................................................................................................................... 318  
Setting................................................................................................................................ 319  
Q & A ................................................................................................................................. 319  
Caution .............................................................................................................................. 320  
Chapter 25 External Interrupt............................................................................ 321  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 321  
Features............................................................................................................................. 321  
Configuration ..................................................................................................................... 322  
Registers............................................................................................................................ 325  
Operation........................................................................................................................... 327  
Setting................................................................................................................................ 328  
Q & A ................................................................................................................................. 328  
Caution .............................................................................................................................. 331  
Chapter 26 DMA Controller................................................................................ 333  
1.  
2.  
3.  
4.  
5.  
6.  
Overview of the DMA Controller (DMAC) .......................................................................... 333  
DMA Controller (DMAC) Registers.................................................................................... 335  
DMA Controller (DMAC) Operation ................................................................................... 354  
Operation Flowcharts......................................................................................................... 373  
Data Bus............................................................................................................................ 376  
DMA External Interface...................................................................................................... 379  
Chapter 27 Delayed Interrupt ............................................................................ 383  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 383  
Features............................................................................................................................. 383  
Configuration ..................................................................................................................... 383  
Register ............................................................................................................................. 384  
Operation........................................................................................................................... 384  
Setting................................................................................................................................ 385  
Q & A ................................................................................................................................. 385  
Caution .............................................................................................................................. 385  
Chapter 28 Bit Search ........................................................................................ 387  
1.  
2.  
3.  
Overview............................................................................................................................ 387  
Features............................................................................................................................. 387  
Configuration ..................................................................................................................... 388  
v
4.  
5.  
6.  
7.  
8.  
Register ............................................................................................................................. 389  
Operation........................................................................................................................... 391  
Setting................................................................................................................................ 393  
Q & A ................................................................................................................................. 394  
Caution .............................................................................................................................. 395  
Chapter 29 MPU / EDSU..................................................................................... 397  
1.  
2.  
3.  
4.  
5.  
Overview............................................................................................................................ 397  
Features............................................................................................................................. 398  
Break Functions................................................................................................................. 399  
Registers............................................................................................................................ 407  
Quick Reference................................................................................................................ 429  
Chapter 30 I/O Ports........................................................................................... 431  
1.  
2.  
3.  
I/O Ports Functions............................................................................................................ 431  
I/O Circuit Types................................................................................................................ 453  
Port Register Settings........................................................................................................ 454  
Chapter 31 External Bus.................................................................................... 507  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
9.  
Overview of the External Bus Interface ............................................................................. 507  
External Bus Interface Registers ....................................................................................... 512  
Setting Example of the Chip Select Area........................................................................... 542  
Endian and Bus Access..................................................................................................... 543  
Operation of the Ordinary bus interface............................................................................. 562  
Burst Access Operation..................................................................................................... 574  
Address/data Multiplex Interface ....................................................................................... 576  
Prefetch Operation............................................................................................................. 579  
SDRAM/FCRAM Interface Operation ................................................................................ 582  
10. DMA Access Operation ..................................................................................................... 592  
11. Bus Arbitration ................................................................................................................... 608  
12. Procedure for Setting a Register ....................................................................................... 610  
13. Notes on Using the External Bus Interface........................................................................ 611  
Chapter 32 USART (LIN / FIFO) ......................................................................... 613  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 613  
USART Configuration ........................................................................................................ 616  
USART Pins....................................................................................................................... 620  
USART Registers .............................................................................................................. 621  
USART Interrupts .............................................................................................................. 638  
USART Baud Rates........................................................................................................... 642  
USART Operation.............................................................................................................. 647  
Notes on using USART...................................................................................................... 663  
Chapter 33 I2C Controller .................................................................................. 665  
1.  
2.  
3.  
4.  
Overview............................................................................................................................ 665  
I2C Interface Registers...................................................................................................... 667  
I2C Interface Operation ..................................................................................................... 685  
Programming Flow Charts................................................................................................. 687  
vi  
Chapter 34 CAN Controller................................................................................ 691  
1.  
2.  
3.  
4.  
Overview............................................................................................................................ 691  
Register Description .......................................................................................................... 692  
Functional Description ....................................................................................................... 720  
CAN Application................................................................................................................. 724  
Chapter 35 Free-Run Timer ............................................................................... 733  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 733  
Features............................................................................................................................. 733  
Configuration Diagram....................................................................................................... 734  
Registers............................................................................................................................ 735  
Operation........................................................................................................................... 739  
Setting................................................................................................................................ 741  
Q & A ................................................................................................................................. 742  
Caution .............................................................................................................................. 745  
Chapter 36 Input Capture................................................................................... 747  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 747  
Features............................................................................................................................. 747  
Configuration ..................................................................................................................... 748  
Register ............................................................................................................................. 749  
Operation........................................................................................................................... 752  
Settings.............................................................................................................................. 754  
Q&A ................................................................................................................................... 755  
Caution .............................................................................................................................. 758  
Chapter 37 Output Compare.............................................................................. 759  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 759  
Features............................................................................................................................. 759  
Configuration Diagram....................................................................................................... 760  
Registers............................................................................................................................ 761  
Operation........................................................................................................................... 765  
Settings.............................................................................................................................. 767  
Q & A ................................................................................................................................. 768  
Caution .............................................................................................................................. 773  
Chapter 38 Reload Timer ................................................................................... 775  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 775  
Features............................................................................................................................. 775  
Configuration ..................................................................................................................... 776  
Registers............................................................................................................................ 778  
Operation........................................................................................................................... 782  
Setting................................................................................................................................ 787  
Q & A ................................................................................................................................. 789  
Caution .............................................................................................................................. 794  
Chapter 39 Programmable Pulse Generator.................................................... 795  
1.  
Overview............................................................................................................................ 795  
vii  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Features............................................................................................................................. 795  
Configuration ..................................................................................................................... 797  
Registers............................................................................................................................ 799  
Operation........................................................................................................................... 808  
Setting................................................................................................................................ 811  
Q & A ................................................................................................................................. 813  
Caution .............................................................................................................................. 821  
Chapter 40 Pulse Frequency Modulator........................................................... 823  
1.  
2.  
3.  
4.  
PFM Overview ................................................................................................................... 823  
Reload Counter Registers ................................................................................................. 826  
Reload Counter Operation................................................................................................. 830  
PFM Operation and Setting ............................................................................................... 833  
Chapter 41 Up/Down Counter............................................................................ 835  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 835  
Feature .............................................................................................................................. 835  
Configuration ..................................................................................................................... 836  
Register ............................................................................................................................. 840  
Operation........................................................................................................................... 848  
Setting................................................................................................................................ 855  
Q&A ................................................................................................................................... 857  
Caution .............................................................................................................................. 862  
Chapter 42 Sound Generator............................................................................. 863  
1.  
2.  
3.  
Overview............................................................................................................................ 863  
Block Diagram ................................................................................................................... 864  
Registers............................................................................................................................ 865  
Chapter 43 Stepper Motor Controller ............................................................... 871  
1.  
2.  
3.  
4.  
Overview............................................................................................................................ 871  
Registers............................................................................................................................ 872  
Operation........................................................................................................................... 881  
Caution .............................................................................................................................. 883  
Chapter 44 A/D Converter.................................................................................. 885  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
Overview of A/D Converter................................................................................................ 885  
Block Diagram of A/D Converter........................................................................................ 886  
Registers of A/D Converter................................................................................................ 887  
Operation of A/D Converter ............................................................................................... 896  
Setting................................................................................................................................ 899  
Q & A ................................................................................................................................. 901  
Caution .............................................................................................................................. 906  
Chapter 45 D/A Converter.................................................................................. 909  
1.  
2.  
3.  
Overview............................................................................................................................ 909  
Features............................................................................................................................. 909  
Configuration ..................................................................................................................... 910  
viii  
4.  
5.  
6.  
7.  
8.  
Registers............................................................................................................................ 911  
Operation........................................................................................................................... 913  
Setting................................................................................................................................ 914  
Q & A ................................................................................................................................. 915  
Caution .............................................................................................................................. 916  
Chapter 46 Alarm Comparator .......................................................................... 917  
1.  
2.  
3.  
4.  
Overview............................................................................................................................ 917  
Block Diagram .................................................................................................................. 917  
Alarm Comparator Control/Status Register (ACSR).......................................................... 918  
Operation Modes ............................................................................................................... 919  
Chapter 47 LCD Controller ................................................................................ 921  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 921  
Features............................................................................................................................. 921  
Configuration ..................................................................................................................... 922  
Registers............................................................................................................................ 924  
Operation........................................................................................................................... 929  
Setting................................................................................................................................ 934  
Q&A ................................................................................................................................... 935  
Caution .............................................................................................................................. 940  
Chapter 48 Clock Monitor.................................................................................. 941  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 941  
Features............................................................................................................................. 941  
Configuration ..................................................................................................................... 942  
Register ............................................................................................................................. 943  
Operation........................................................................................................................... 945  
Settings.............................................................................................................................. 946  
Q&A ................................................................................................................................... 946  
Caution .............................................................................................................................. 947  
Chapter 49 Real-Time Clock.............................................................................. 949  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 949  
Features............................................................................................................................. 949  
Configuration ..................................................................................................................... 950  
Registers............................................................................................................................ 951  
Operation........................................................................................................................... 956  
Setting................................................................................................................................ 958  
Q&A ................................................................................................................................... 959  
Caution .............................................................................................................................. 961  
Chapter 50 Subclock Calibration Unit .............................................................. 963  
1.  
2.  
3.  
4.  
5.  
Overview............................................................................................................................ 963  
Block Diagram ................................................................................................................... 964  
Timing................................................................................................................................ 965  
Clocks................................................................................................................................ 966  
Register Description .......................................................................................................... 967  
ix  
6.  
Application Note................................................................................................................. 973  
Chapter 51 Low Voltage Reset/Interrupt .......................................................... 975  
1.  
2.  
3.  
Overview............................................................................................................................ 975  
Features............................................................................................................................. 975  
Registers............................................................................................................................ 976  
Chapter 52 Regulator Control ........................................................................... 979  
1.  
2.  
3.  
Overview............................................................................................................................ 979  
Features............................................................................................................................. 979  
Registers............................................................................................................................ 980  
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM........................................ 983  
1.  
2.  
3.  
4.  
5.  
Overview............................................................................................................................ 983  
Check for Boot Conditions................................................................................................. 983  
Registers modified by Boot ROM ...................................................................................... 988  
Flash Access Mode Switching........................................................................................... 989  
Bootloader Update Strategy .............................................................................................. 990  
Chapter 54 Flash Memory.................................................................................. 993  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
Overview............................................................................................................................ 993  
Features............................................................................................................................. 993  
Configuration ..................................................................................................................... 994  
Registers............................................................................................................................ 996  
Access Modes ................................................................................................................... 996  
Flash Access Mode Switching........................................................................................... 997  
Auto Algorithms ................................................................................................................. 999  
Caution ............................................................................................................................ 1007  
Chapter 55 Flash Security ............................................................................... 1009  
1.  
2.  
3.  
4.  
Overview.......................................................................................................................... 1009  
Features........................................................................................................................... 1009  
Flash Security Vectors..................................................................................................... 1010  
Register ........................................................................................................................... 1013  
Chapter 56 Electrical Specification................................................................. 1017  
x
xi  
xii  
Chapter 1 Introduction  
1.How to Handle the Device  
Chapter 1 Introduction  
1. How to Handle the Device  
■ Device Handling Instructions  
This chapter describes latch-up prevention and pin termination.  
● To set latch-up prevention  
Latch up may occur on CMOS ICs when the applied voltage for input terminals or output terminals is higher than V  
CC  
or lower than V , or a voltage higher than the maximum rating voltage is applied between V  
and V . Make sure  
SS  
SS  
CC  
not to apply a voltage higher than the maximum rating voltage since latch up may surge electric current and result in  
the thermal destruction of the device.  
● Termination of unused pin  
An unused pin must be terminated by a pull-up or pull-down resistor externally, or by switching on the internal pull-up  
or pull-down resistor before enabling the pin inputs to avoid transverse current.  
● Power-supply pin  
If multiple V and V exist, as a matter of device design, they are connected to each other to prevent an error when  
CC  
SS  
their voltage should be identical in the device. In order to reduce unnecessary radiation, prevent an strobe signal error  
due to upward ground level, and comply with total output current standard, be sure to externally connect them to power  
supply and ground. Give consideration to connect V  
V
of the device from power supply at low impedance.  
CC and SS  
Near the device, it is preferable to connect about 0.1uF ceramic capacitor as a bypass capacitor between V  
and  
CC  
V
.
SS  
● Crystal-oscillator circuit  
Noise to X0 or X1 pin may cause an error. Make a design for printed board to closely allocate X0, X1, crystal oscillator  
(or ceramic oscillator), bypass capacitor towards ground and the device.  
It is recommended to make a printed board artwork which surrounds X0 and X1 pins using ground.  
The above recommendations also apply to the subclock oscillator pins X0A and X1A.  
● NC and OPEN pin termination  
Do not terminate NC pin and OPEN pin to use.  
● Mode pins (from MD0 to MD2)  
Connect pins from MD0 to MOD2 directly to V or V to use. To avoid entering test mode due to noise, make a short  
CC  
SS  
pattern length between each mode pin on printed board and V or V to connect pins at low impedance.  
CC  
SS  
● At the time of power-on  
Immediately after power-on operation, be sure to reset INIT pin to initialize the setting (INIT). Immediately after power-  
on operation, to ensure the oscillation stabilization time required for oscillation circuit, hold “L”-level input to the pin  
during the oscillation stabilization time required for oscillation circuit. (INIT operation on the pin initializes the setting for  
oscillation stabilization time to minimum value.)  
● Source oscillation input at the time of power-on  
At the time of power-on, be sure to input the clock until the oscillation stabilization wait is over.  
1
   
Chapter 1 Introduction  
1.How to Handle the Device  
● Caution: during the PLL clock operation  
Even if oscillator is disconnected or input is stopped while selecting PLL clock, self-excited oscillation circuit in the PLL  
may continue running at self-running frequency. This self-running operation is not covered by guarantee.  
● For more specification about operating voltage, see the latest data sheet.  
2
Chapter 1 Introduction  
2.Instruction for Users  
2. Instruction for Users  
■ Clock Controls  
By inputting “L” to INIT, ensure clock oscillation stabilization time.  
■ Switching of dual-purpose port  
Use PFR (Port function register) to switch between PORT and dual-purpose port.  
■ Low-power-consumption mode  
• For standby mode, enable synchronous standby (TBCR.SYNCS=“1”) and then use the following sequences.  
(LDI  
(LDI  
STB  
LDUB  
LDUB  
NOP  
NOP  
NOP  
NOP  
NOP  
#value_of_standby, R0  
#_STCR, R12  
R0, @R12  
@R12, R0  
@R12, R0  
value_of_standby is a write data to STCR  
_STCR is the STCR address. (481H)  
Write to Standby Control Register (STCR).  
STCR read for synchronous standby.  
Dammy read STCR again.  
NOP x 5 for timing adjustment.  
In addition, after returning from standby, set I flag, ILM and ICR in order to branch to interrupt handler which  
triggered the return.  
• If you use monitor debugger, you should avoid the following.  
• Do not set breakpoints for command sequence above.  
• Do not conduct stepwise execution for command sequence above.  
■ Power-on sequence  
Power-on and power-off sequence valid for MB91V460 Rev.A. Please review the datasheets of the flash  
devices for a valid power-on and power-off sequence on those devices.  
Power-on sequence: (1) VDD5 , VDD35, HVDD5, VDD5R (2) AVCC, AVRH, V0-V3  
Power-off sequence: (1) AVCC, AVRH, V0-V3 (2) VDD5 , VDD35, HVDD5, VDD5R  
The power supply V3 for LCD must not exceed VDD5. The power-on of V3 should be carried out after power-  
on of VDD5R and VDD5. To power on analogue power supply AVCC and analogue signal, power VDD5R and  
VDD5 on before.  
■ Power supply operating conditions  
Power supply recommendation valid for MB91V460 Rev.A. Please review the datasheets of the flash devices  
for a recommendation of the power supply conditions on those devices.  
[VDD5 = HVDD5 = AVCC] >= VDD35. This is the recommended condition.  
3
   
Chapter 1 Introduction  
2.Instruction for Users  
■ Caution: PS register  
Because some commands previously proceed PS register, interrupt processing routine may be broken during  
the use of debugger or displayed data on PS flag may be updated due to the following excecptional operations  
((1) and (2)).  
In each case, it is designed to correctly re-proceed operations after the return, the operation before and after  
EIT is carried out in accordance with the specification.  
• In immediately preceding DIV0U or DIV0S command,  
• If interrupted by user,  
• If stepwise execution is carried out,  
• If data event or emulator menu made a break,  
The following operation may be generated.  
1. D0 or D1 flag is updated ahead.  
2. EIT processing routine (interruption by user or emulator) is carried out.  
3. After the return from EIT, it executes DIV0U or DIV0S command and then D0 or D1 flag are updated  
to the same value as 1.  
• If you execute each command of ORCCR, STILM, MOV Ri or PS to enable interruption with  
interruption by user generated, the following operation may be generated.  
4. PS register is updated ahead.  
5. EIT processing routine (interruption by user) is carried out.  
6. After the return from EIT, it executes commands above, and then PS register is updated to the same  
value as 1.  
■ Watchdog timer function  
Watchdog timer function equipped with FR60 monitors the progress to ensure that program executes reset  
delay operation within a specified time and resets CPU if reset delay operation was not executed due to  
runaway of program. Once you enable watchdog timer function, it continues running until it is reset.  
By way of exception, reset delay is automatically conducted under the condition where CPU program  
execution is stopped. For this exceptional condition, see “Chapter 20 Software Watchdog Timer (Page  
No.273)“.  
■ Register against read/modify/write command  
SMR register within UART cannot use read/modify/write command. To write in SMR register, write by Byte/  
Half-word/Word in consideration with write control bit (bit-5, 4, 2, 0) rather than accessing by bit-by-bit.  
4
Chapter 1 Introduction  
2.Instruction for Users  
■ Caution: writing to registers which include a status flag  
Writing to a register including a status flag (in particular, interrupt request flag) in order to control the function,  
note that you should not clear status flag unintentionally.  
That is, take care not to clear the flag for status bit and make control bit to be the expected value during the  
writing.  
Especially, for control bits consisting of several bits, bit command is not available since single bit access is  
only acceptable for bit command, you should write into the both of control bit and status flag at the same time  
by Byte/Half-word/Word access. In this case, you should not clear other bits (bits of status flag) unintentionally.  
The following shows registers which mostly include both of several bits and status flag.  
• TBCR  
• OSCR  
• TWCR  
• TCCS0, TCCS1  
• ICS01  
• TMCSR0, TMCSR1, TMCSR2, TMCSR3  
• PCN00, PCN01, PCN02,...  
• ADCSL0, ADCSL1  
• CCR0, CCR1  
Note: For bit command, you do not have to be careful since this matter has been already considered.  
■ Caution: writing to registers which include a status flag  
Writing to a register including a status flag (in particular, interrupt request flag) in order to control the function,  
note that the actual writing to the registers may be delayed. This is because of using write buffers on the  
busses to the resources which accept a write access from CPU immediately but can access the resource  
registers delayed.  
In this case it can happen that within an ISR the interrupt request flag is cleared by writing to the register and  
the ISR is completed with RETI, but the interrupt request flag is still active and the ISR is executed again.  
To synchronize the access to the resources on this architecture please follow this recommendation:  
Use a read access (byte or halfword) to the RBSYNC address to synchronize the CPU operation (e.g. the  
interrupt acceptance of the CPU) to a preceding write access to the resources on R-bus (e.g. to an interrupt  
flag) on following addresses (0x0000-0x01FF, 0x0280-0x037F, 0x0400-0x063F and 0x0C00-0x0FFF).  
Use a read access (byte or halfword) to the CBSYNC address to synchronize the CPU operation (e.g. the  
interrupt acceptance of the CPU) to a preceding write access to the CANs on D-bus (e.g. to an interrupt flag)  
on following addresses (0xC000-0xFFFF).  
5
Chapter 1 Introduction  
3.Caution: debug-related matters  
3. Caution: debug-related matters  
■ Stepwise execution of RETI command  
Under the circumstances where interruption is often generated when carrying out stepwise execution, only  
relevant interrupt processing routine is repeatedly executed after the stepwise execution of RETI. Therefore,  
main routine or low-level interruption program will not be executed.  
To avoid this problem, do not proceed stepwise execution of RETI command.  
Or, upon the time when no debug is needed for relevant interrupt routine, proceed the debug by prohibiting  
relevant interruptions.  
■ Operand break  
Do not set the access for area including system stack pointer address as the target for data event break.  
6
 
Chapter 1 Introduction  
4.How to Use This Document  
4. How to Use This Document  
■ Main terminology: This table shows main terminology used for FR60.  
Term  
Meaning  
32-bit-wide bus for internal instruction.  
I-bus  
Since FR60 series employ internal Harvard architecture, instruction and data are independent bus. For I-bus,  
Harverd/Prinston-bus-converter is connected.  
Internal 32-bit-wide data bus.  
D-bus  
F-bus  
For D-bus, bit search module, Harverd/Prinston-bus-converter, R-bus interface (32-bit⇔16-bit Bus-  
converter), and CAN modules are connected.  
Internal 32-bit-wide bus.  
F-bus is connected to embedded Flash/ROM and embedded RAM.  
Internal 16-bit-wide data bus.  
R-bus  
X-bus  
R-bus is connected to D-bus via R-bus-converter. For R-bus, peripheral function, I/O, clock generator and  
interrupt controller are connected.  
32-bit-wide address and data bus. Via bus-converter for external bus, it accesses to external bus.  
Main clock  
(F  
This a clock which acts as a benchmark for LSI operation triggered by high-speed-side oscillation.  
This is connected to main clock oscillation stabilization timer and clock generator.  
)
CL-MAIN  
Subclock  
This a clock which acts as a benchmark for LSI operation triggered by low-speed-side oscillation.  
This is connected to sub oscillation stabilisation timer, real-time clock and clock generator.  
(F  
)
CL-SUB  
At the maximum speed, base clock has the same cycle as source oscillation. In PLL of the clock generator,  
base clock has clock multiplied by 1, 2, 3, 4, 5, 6, 7 and 8 or clock divided by 2.  
Base clock is basis clock which generates CLKB, CLKP and CKLT in the clock generator.  
Base clock  
(Φ)  
CPU clock  
(CLKB)  
CPU clock is the clock which is referred by CPU, embedded ROM, embedded RAM, bit search module and  
internal bus (I-bus, D-bus, F-bus and X-bus) operations. Generated from the base clock in the clock generator.  
Peripheral clock is the clock which is referred by each peripheral function (peripheral functions other than bit  
search module and CAN) connected to R-bus and R-bus, clock control, interrupt controller, I/O port and  
external interrupt input d operations. Generated from the base clock in the clock generator.  
Peripheral clock  
(CLKP)  
External bus clock  
(CLKT)  
External bus clock is the clock which is referred by external expansion bus interface connected to X-BUS and  
external clock output operations. Generated from the base clock in the clock generator.  
CAN clock  
(CLKCAN)  
CAN clock is the clock which is referred by the CAN modules. Generated from the non modulated PLL  
output clock to ensure operation within CAN network oscillation tolerances.  
Mode which runs based on main clock. This main clock mode has status such as main RUN, main sleep, main  
stop, oscillation stabilization wait RUN, oscillation stabilization wait reset and program reset.  
Main clock mode  
Subclock mode  
Mode which runs based on subclock. This subclock mode has status such as sub RUN, sub sleep, sub stop,  
subclock oscillation stabilization wait RUN and program reset.  
Main RUN  
Sub RUN  
Main RUN is the status which is in main clock mode and also all circuits are operable.  
Sub RUN is the status which is in subclock mode and also all circuits are operable.  
Upon the reset (INITX, RST), return from stop, return from PLL abnormal operation, generation of watchdog  
and during main clock stop, it takes oscillation stabilization time for main clock. Time base timer counts the  
time.  
Oscillation  
stabilization time  
Main clock  
oscillation  
stabilization wait  
Wait time until main clock oscillates after main clock stops in subclock mode.  
Main clock oscillation stabilization timer counts the time.  
7
 
Chapter 1 Introduction  
4.How to Use This Document  
■ Access size and address position  
Offset  
Register name  
Write-only  
Read-only  
Address offset value/Register name  
Address  
Block  
Up/down counter  
0, 1  
Initial value  
Read/write  
Byte access, Half-word access, and Word access are allowed.  
There are three kinds of accesses such as Byte access, Half-word access and Word access. However, note  
that some registers have restricted access. For more information, see “3.2. I/O Map (Page No.24)” or “Detail  
Description of Register” in each chapter.  
B,H,W : Byte access, Half-word access, and Wordaccess are allowed.  
B
: Byte access (Be sure to access by Byte.)  
H
: Half-word access (Be sure to access by Half-word.)  
: Word access (Be sure to access by Word.)  
W
B, H  
H,W  
: Byte access, Half-word access only (Word access is not allowed.)  
: Half-word access, Word access only (Byte access is not allowed.)  
Reference  
The following describes address position to access.  
• In Word access, address becomes multiple of 4. (Lowest order 2 bits mandatorily become “00”.)  
• In Half-word access, address becomes multiple of 2. (Lowest order 1 bit mandatorily becomes “0”.)  
• In Byte access, address will not be changed.  
Therefore, for example, make RCR0 register to use Half-word access,  
For address 0B0H, RCR1+RCR0 register is accessed.  
(When address offset is +1 and +2, (Example: RCR0+UDCR1) Half-word access is not allowed.)  
8
Chapter 1 Introduction  
4.How to Use This Document  
■ About access size and bit position  
Register name Register mark  
Target peripheral device Address  
Access size  
Bit position  
(1) Counter control register (Higher byte)  
This is the register (higher byte) which controls up/down counter operation.  
CCRH0 (Up/down counter 0): address 00B4h (Access: Byte, Half-word, Word)  
CCRH1 (Up/down counter 1): address 00B8h (Access: Byte, Half-word, Word)  
M16E/Reserved  
Initial value  
Attribute  
*
bit15: Enable 16-bit mode  
M16E (CCRH0 only)  
Enable 16-bit mode  
8-bit x 2-channel mode (8-bit mode)  
16-bit x 1-channel mode (16-bit mode)  
*: CCRH1: ReservedAlways write 0 for writing. The read value is indeterminate.  
When access size changes, bit position changes.  
• In the case that address offset value is +0 (Example: CCRH0 register)  
Access size  
Byte  
Address  
Bit position  
0B4 +0  
07  
15  
06  
14  
05  
13  
04  
12  
03  
02  
10  
01  
09  
00  
08  
H
H
H
H
0B4 +0  
Half-word  
Word  
11  
27  
H
0B4 +0  
31  
30  
29  
28  
26  
25  
24  
H
Bit name  
M16E  
CDCF  
CFIE  
CLKS  
CMS1  
CMS0  
CES1  
CES0  
• In the case that address offset value is +1 (Example: CCRL0 register)  
Access size  
Byte  
Address  
Bit position  
0B4 +1  
07  
07  
06  
06  
05  
05  
04  
04  
03  
03  
02  
02  
01  
01  
00  
00  
H
H
H
H
0B4 +0  
Half-word  
Word  
H
0B4 +0  
23  
22  
21  
20  
19  
18  
17  
16  
H
Reserved  
Bit name  
CTUT  
UCRE  
RLDE  
UDCC  
CGSC  
CGE1  
CGE0  
• In the case that address offset value is +2 (Example: UDCR1 register)  
Access size  
Byte  
Address  
Bit position  
0B0 +2  
07  
15  
06  
14  
05  
13  
04  
12  
03  
11  
02  
10  
01  
09  
09  
D9  
00  
08  
08  
D8  
H
H
H
H
0B0 +2  
Half-word  
Word  
H
0B0 +0  
15  
14  
13  
12  
11  
10  
H
Bit name  
D15  
D14  
D13  
D12  
D11  
D10  
• In the case that address offset value is +3 (Example: UDCR 1 register)  
Access size  
Byte  
Address  
Bit position  
0B0 +3  
07  
07  
07  
D7  
06  
06  
06  
D6  
05  
05  
05  
D5  
04  
04  
04  
D4  
03  
03  
03  
D3  
02  
02  
02  
D2  
01  
01  
01  
D1  
00  
00  
00  
D0  
H
H
H
H
0B0 +2  
Half-word  
Word  
H
0B0 +0  
H
Bit name  
9
Chapter 1 Introduction  
4.How to Use This Document  
■ Meaning of Bit Attribute Symbols  
R
: Readable  
W
: Writable  
RM  
: Reading operation during read/modify/write operation.  
“/” (Slash) R/W: Readable and writable. (The read value is the value written.)  
“,” (comma) R,W: Values are different between read and write. (The read value is different from  
the value written.)  
R0  
: The read value is “0”.  
R1  
: The read value is “1”.  
W0  
: Always write “0”.  
W1  
: Always write “1”.  
(RM0)  
(RM1)  
RX  
: read/modify/write operation reads “0”.  
: read/modify/write operation reads “1”.  
: The read value is indeterminate. (Reserved bit or undefined bit)  
: Writing does not affect the operation. (Undefined bit)  
WX  
• Example of how R/W is used  
• R/W  
: Readable and writable. (The read value is the value written.)  
• R,W  
: Readable and writable. (The read value and written value are different.)  
• R,RM/W  
: Readable and writable. (The read value and written value are different. Read/modify/write  
command reads the value written.) Example: port data register  
• R(RM1),W  
: Readable and writable. (The read value and written value are different. Read/modify/write  
command reads 1.) Example: interrupt request flag  
• R/WX  
• R1,W  
: Read-only (Read-only. Writing does not affect the operation.)  
: Write-only (Write-only. The read value is 1.)  
• R0,W  
: Write-only (Write-only. The read value is 0.)  
• RX,W  
• R/W0  
: Write-only (Write-only. The read value is indeterminate.)  
: Reserved bit (The written value is 0. The read value is the value written.)  
: Reserved bit (The written value is 0. The read value is 0.)  
: Reserved bit (The written value is 0. The read value is 1.)  
: Reserved bit (The written value is 0. The read value is indeterminate.)  
: Reserved bit (The written value is 1. The read value is the value written.)  
: Reserved bit (The written value is 1. The read value is 1.)  
: Reserved bit (The written value is 1. The read value is 0.)  
: Reserved bit (The written value is 1. The read value is indeterminate.)  
: Undefined bit (The read value is indeterminate. Writing does not affect the operation.)  
: Undefined bit (The read value is 0. Writing does not affect the operation.)  
• R0/W0  
• R1,W0  
• RX,W0  
• R/W1  
• R1/W1  
• R0,W1  
• RX,W1  
• RX/WX  
• R0/WX  
10  
 
Chapter 2 MB91460 Rev.A/Rev.B Overview  
1.Overview  
Chapter 2 MB91460 Rev.A/Rev.B Overview  
1. Overview  
MB91460 is a series of standard microcontrollers containing a range of I/O peripherals and bus control  
functions. MB91460 features a 32-bit RISC CPU (FR60 series) core and is suitable for embedded control  
applications requiring high-performance and high-speed CPU processing. MB91460 derivatives also contain  
up to 16 kByte instruction cache memory and other internal memories to improve the execution speed of the  
CPU.  
MB91460 Rev.B has the same features as MB91460 Rev.A and adds some additional components in order to  
support infotainment applications. Which components and modules will be included in MB91460 Rev.B is not  
yet decided finally. So this document gives only a proposal at this stage of development.  
MB91460 Rev.B : This series is presently being specified, and not available yet.  
2. Features  
2.1 FR60 CPU Core  
• 32-bit RISC, load/store architecture, pipeline 5 stages  
• Maximum operating frequency: Core clock = 100 MHz (device dependent)  
(Source oscillation= 4 MHz, multiplied by 25 (PLL clock multiplier method))  
• General-purpose registers: 16 x 32 bits  
• 16-bit fixed-length instruction (Base instruction)  
• 32-bit linear address space: 4 Gbytes  
• Instructions suitable for embedded application  
•
•
•
Transfer command between memories  
Bit-processing instruction  
Barrel-shift instructions  
• Instructions supporting C-language  
• Function's enter command /exit command  
• Multi-load/store command of register contents  
• Assembler statement is also easily available  
Register's interlock function  
• Multiplier's embedded application/command level support  
•
•
Signed 32-bit multiplication: 5 cycles  
Signed 16-bit multiplication: 3 cycles  
• Interrupt (PC/PS are saved): 6 cycles (16 priority level)  
• Harvard architecture enables simultaneous execution of program access and data access  
• Memory protection function  
• Embedded debug support  
• Commands compatible with FR family  
2.2 Instruction Cache  
• 2 way set associative I-cache  
•
Up to 4 kByte integrated  
11  
     
Chapter 2 MB91460 Rev.A/Rev.B Overview  
2.Features  
•
•
•
•
4 words (16 bytes) per set  
Variable capacity (4/2/1 kB)  
Lock function enabling programs to be resident  
Available as instruction RAM requiring no wait state when not used as an instruction cache  
• Direct mapped I-cache  
•
•
•
Up to 16 kByte integrated  
Variable capacity (16/8/4/2/1 kB)  
Lock function enabling programs to be resident  
2.3 Interrupt Controller  
• A total of 17 external interrupt lines (1 nonmaskable interrupt pin, 8 normal interrupt pins, 8 interrupt pins  
shared (with peripheral inputs for Wake Up from STOP mode, e.g. CAN RX)  
• Interrupts from internal peripherals (128 interrupt vectors)  
• Priority levels programmable for normal interrupt lines excluding the nonmaskable one (16 levels)  
• Capable of using the normal interrupt and nonmaskable interrupt pins for Wake Up from STOP mode  
2.4 Internal Data RAM  
• Up to 64 kBytes integrated  
• Zero wait state for read/write access  
• Referenced as Data-RAM or D-RAM in this manual  
2.5 Internal Instruction/Data RAM  
• Up to 64 kBytes integrated  
• Zero wait state for read/write access of instructions  
• One wait state for read/write access of data  
• Referenced as General-Purpose-RAM (GP-RAM) or I/D-RAM in this manual  
2.6 Embedded Instruction/Data Memory  
• Up to 4 MByte (Flash or Mask ROM)  
• Programmable wait state for read/write access  
• Flash/ROM security  
2.7 External Bus Interface  
• 8 chip select areas with individual area size, data bus width selection (8, 16, 32-bit) and wait  
• Address bus up to 32 bit wide  
• Programmable auto-wait function or external wait input (RDY)  
• Basic bus cycles : 2 cycles  
• Prefetch function  
• Burst access function  
2.8 DMA Controller  
• Four transfer modes supported: single/block, burst, continuous transfer, and fly-by  
• 5 channels (4 channels for external-to-external transfer)  
12  
Chapter 2 MB91460 Rev.A/Rev.B Overview  
2.Features  
• 3 types of transfer sources (external pins/internal peripherals/and software)  
• Up to 128 selectable internal transfer sources  
• Addressing mode: Specifying up to 32-bit addresses (Increment/decrement/fixed)  
• Transfer mode (Demand transfer/burst transfer/step transfer/block transfer)  
• Fly-by transfer supported (between external I/O and memory)  
• Transferred data size selectable from among 8, 16, and 32 bits  
2.9 Infotainment extension (MB91460 Rev.B)  
• Inter-IC sound bus (I2S)  
•
•
master or slave operation  
operation up to 2.5 MBit/s  
• MOST support (MediaLB for controlling an external MOST IC is integrated)  
•
Digital interface to external MOST controller  
Frame sync pattern support  
•
•
Scalable data rate for streaming, packet, control, isochronous  
System-broadcast channel for administration  
Broadcast support for synchronous data  
•
•
• USB  
•
•
•
•
•
USB 1.1 compliant up to 12Mbit/s (USB 2.0 tbd)  
Configurable endpoints  
Supports control, bulk, interrupt and isochronous transfer  
built-in FIFO for all endpoints  
clock and data recovery  
• Flexray  
•
•
•
•
•
Event or Time triggered protocol  
Asynchronous or synchronous operation  
Fault tolerant operation (2 channels supported)  
Static and dynamic data transfer  
Transfer rates up to 10 MBit/s  
• Ethernet  
MB91460 Rev.B : This series is presently being specified and not available yet.  
13  
Chapter 2 MB91460 Rev.A/Rev.B Overview  
2.Features  
2.10 Peripheral Function  
• General-purpose port : Up to 288  
2
•
N channel open drain port out of above: 8 (for I C)  
• A/D converter : 32 channels (1 unit)  
•
•
•
•
•
•
•
•
Series-parallel type  
Resolution: 10 bits  
Minimum conversion time: 3us  
Single conversion mode  
Continuous conversion mode  
Stop conversion mode  
Activation by software or external trigger can be selected  
Reload timer 7 and A/D Converter co-operate  
• D/A converter : 2 channels  
•
•
•
•
R-2R type  
Resolution: 10 bits  
Conversion rate: 0.45us (when 20 pF load is applied)  
Conversion rate: 2us (when 100 pF load is applied)  
• Alarm comparator : 2 channels  
•
Monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the  
defined thresholds  
•
Status is readable, interrupts can be masked separately  
• External interrupt input : 16 channels  
•
•
•
Can be programmed to be edge sensitive or level sensitive  
Interrupt mask and request pending bits per channel  
6 channels combined with CAN RX for wakeup  
• Non maskable interrupt (NMI) : 1 channel  
Highest priority of all user interrupts  
•
• Bit search module (using REALOS)  
•
Function to search the first bit position of “1”, “0”, “Changed” from MSB (most significant bit) within 1  
word  
• Up/down counter : 16 bits x 2 channels (8 bits x 4 channels)  
•
•
Timer mode, up/down count mode, phase difference mode (x2, x4)  
1
3
Includes clock prescaler (f  
/2 , f  
/2 )  
RES  
RES  
• Reload timer : 16 bits x 8 channels  
14  
Chapter 2 MB91460 Rev.A/Rev.B Overview  
2.Features  
•
•
16-bit reload counter  
1
3
5
6
7
Includes clock prescaler (f  
/2 , f  
/2 , f  
/2 , f  
/2 , f  
/2 )  
RES  
RES  
RES  
RES  
RES  
• Free-run timer : 16 bits x 8 channels  
•
•
•
16-bit free running counter, signals an interrupt when overflow or match with compare register  
2
4
5
6
Includes prescaler (f  
/2 , f  
/2 , f  
/2 , f  
/2 )  
RES  
RES  
RES  
RES  
Timer data register has R/W access  
• PPG : 16 bit x 16 channels  
•
•
•
16 bit down counter, cycle and duty setting registers  
Interrupt at triggering, cycle or duty match  
PWM operation and one-shot operation  
0
2
4
6
•
Internal prescaler allows f  
/2 , f  
/2 , f  
/2 , f  
/2 as counter clock  
RES  
RES  
RES  
RES  
•
•
•
•
•
•
•
•
•
•
•
•
•
Can be triggered by software, reload timer or external trigger  
Reload timer 0/1 available as trigger for PPG 0/1/2/3  
Reload timer 2/3 available as trigger for PPG 4/5/6/7  
Reload timer 4/5 available as trigger for PPG 8/9/10/11  
Reload timer 6/7 available as trigger for PPG 12/13/14/15  
External trigger for PPG 0/8 (shared)  
External trigger for PPG 1/9 (shared)  
External trigger for PPG 2/10 (shared)  
External trigger for PPG 3/11 (shared)  
External trigger for PPG 4/12 (shared)  
External trigger for PPG 5/13 (shared)  
External trigger for PPG 6/14 (shared)  
External trigger for PPG 7/15 (shared)  
• Input capture : 16 bits x 8 channels  
•
•
•
•
•
Rising edge, falling edge or rising & falling edge sensitive  
Free-run timer 0 available as trigger for input capture 0/1  
Free-run timer 1 available as trigger for input capture 2/3  
Free-run timer 4 available as trigger for input capture 4/5  
Free-run timer 5 available as trigger for input capture 6/7  
• Output compare : 16 bits x 8 channels  
•
•
•
•
•
•
Signals an interrupt when a match with of 16-bit IO timer occurs  
An output signal can be generated  
Free-run timer 2 available as trigger for output compare 0/1  
Free-run timer 3 available as trigger for output compare 2/3  
Free-run timer 6 available as trigger for output compare 4/5  
Free-run timer 7 available as trigger for output compare 6/7  
15  
Chapter 2 MB91460 Rev.A/Rev.B Overview  
2.Features  
• LIN-USART (LIN=Local Interconnect Network) : 16 channels  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Full-duplex double buffer system (4 ch with 16 byte RX/TX FIFO buffer each)  
With parity/without parity selectable  
1 or 2 stop bits selectable  
7 or 8 bits data length selectable  
NRZ type transfer format  
Asynchronous /synchronous communications selectable  
Master-slave communication function (multiprocessor mode)  
Dedicated baud rate prescaler is embedded in each channel  
External clock is able to use as transfer clock  
Parity error, frame error, and overrun error detecting functions  
SPI compatible  
LIN master and slave  
LIN USART 0/8 and ICU 0 co-operate (for LIN sync field in slave mode)  
LIN USART 1/9 and ICU 1 co-operate (for LIN sync field in slave mode)  
LIN USART 2/10 and ICU 2 co-operate (for LIN sync field in slave mode)  
LIN USART 3/11 and ICU 3 co-operate (for LIN sync field in slave mode)  
LIN USART 4/12 and ICU 4 co-operate (for LIN sync field in slave mode)  
LIN USART 5/13 and ICU 5 co-operate (for LIN sync field in slave mode)  
LIN USART 6/14 and ICU 6 co-operate (for LIN sync field in slave mode)  
LIN USART 7/15 and ICU 7 co-operate (for LIN sync field in slave mode)  
• CAN : 6 channels  
•
•
•
•
•
•
•
•
Supports CAN protocol version 2.0 part A and B  
Bit rates up to 1 Mbit/s  
Up to 128 message objects  
Each message object has its own identifier mask  
Programmable FIFO mode (cocatenation of message objects)  
Maskable interrupt  
Disabled Automatic Retransmission mode for Time Triggered CAN applications  
Programmable loop-back mode for self-test operation  
2
• I C (400k fast mode) : 4 channels  
•
•
•
•
•
•
•
•
•
•
Master or slave transmission  
Arbitration function  
Clock synchronization function  
Slave address and general call address detect function  
Transfer direction detect function  
Start condition repeat generation and detection function  
Bus error detect function  
Compatible to I2C standard and fast mode specification (operation up to 400 kHz, 10 bit addressing)  
Includes clock divider functionality  
SCL and SDA lines include optional noise filter. The noise filter allows the suppression of spikes in  
16  
Chapter 2 MB91460 Rev.A/Rev.B Overview  
2.Features  
the range of 1 to 1.5 cycles of the resource clock (CLKP)  
• PFM (pulse frequency modulator) : 16 bits x 1 channel  
•
•
16-bit reload timers for generating high/low pulse waveforms  
1
3
5
6
7
Includes clock prescaler (f  
/2 , f  
/2 , f  
/2 , f  
/2 , f  
/2 )  
RES  
RES  
RES  
RES  
RES  
• Sound Generator : 1 channel  
•
•
•
8-bit PWM signal is mixed with tone frequency from 16-bit reload counter  
0
1
2
3
4
PWM clock by internal prescaler: f  
/2 , f  
/2 , f  
/2 , f  
/2 , f  
/2  
RES  
RES  
RES  
RES  
RES  
Tone frequency: PWM frequency / 2 / (reload value + 1)  
• Stepper Motor Controller : 6 channels  
•
•
•
Four high current outputs for each channel  
Two synchronized 8/10-bit PWMs per channel  
Internal prescaling for PMW clock: f  
/1, f  
/4, f  
/5, f  
/6, f  
/8, f  
/10, f  
/12, f  
/16  
RES  
RES  
RES  
RES  
RES  
RES  
RES  
RES  
• LCD controller  
•
•
•
•
•
•
4 common / 40 segment  
Display: Up to 160 cells (for 1/4 duty cycle)  
Duty cycle: Selectable from options: 1/2, 1/3 and 1/4  
Bias: Fixed at 1/3  
Frame period: Selectable from four options. (for clock, peripheral clock or subclock is selectable)  
Driver: Built-in (for internal divided resistors), or external divided resistors can be connected to the  
V0-V3 pins  
•
•
•
•
•
Data memory: Built-in 16-byte data memory for display  
Stop mode: Enable LCD display in the sub-stop mode  
Blank display: Selectable  
Pin: The SEG0-39 of COM0-4 pin usage can be switched between general and specialized purposes  
Others: External divided resistors can be also used to shut off the current when LCD is deactivated  
• Timebase/watchdog timer (26 bits)  
Adjustable watchdog timer interval (between 2 and 2 system clock cycles)  
20  
26  
•
• RC oscillator watchdog timer (16 bits)  
• Real-time clock (counts during stop mode)  
•
•
•
•
•
•
RTC module can be clocked either from 32 kHz crystal, 4 MHz quartz or from the RC Oscillator  
Facility to correct oscillation deviation (subclock calibration)  
Read/write accessible second/minute/ hour registers  
Can signal interrupts every halfsecond/second/ minute/hour/day  
Internal clock divider and prescaler provide exact 1s clock based on a 4 MHz or a 32 kHz clock input  
Prescaler value for 4 MHz is 0F423F  
H
17  
Chapter 2 MB91460 Rev.A/Rev.B Overview  
2.Features  
•
Prescaler value for 32 kHz is 001FFF  
H
• Clock monitor (clock output function): 1 channel  
• Clock supervisor  
•
•
Monitors external 32kHz and 4MHz for fails (e.g. crystal breaks)  
Switches in case of fail to an available recovery clock (subclock or RC clock)  
• Clock modulator (reduction of EME)  
• Subclock calibration  
•
Calibration of the RTC timer in 32 kHz or RC oscillator operation, based on the more accurate 4 MHz  
quartz is possible  
• Main oscillation stabilisation timer  
•
•
23 bit counter for main oscillation stabilisation wait when running in sub clock mode  
Generates an interrupt when stabilisation time has elapsed  
• Sub oscillation stabilisation timer  
•
•
15 bit counter for sub oscillation stabilisation wait when running in main clock mode  
Generates an interrupt when stabilisation time has elapsed  
• Low-consumption modes: SLEEP/Sub-Run/RTC/STOP function  
• Package: BGA660-03EK (Evaluation device MB91V460)  
• CMOS 0.35um technology (Evaluation device MB91V460)  
• Power supply (Evaluation device MB91V460):  
•
•
Single power supply 3.3V  
Single power supply 5V  
18  
Chapter 2 MB91460 Rev.A/Rev.B Overview  
3.MB91460 Series Product Lineup  
3. MB91460 Series Product Lineup  
Feature  
Core frequency  
MB91V460 Rev.A  
MB91V460 Rev.B  
MB91F467DA  
100 MHz  
50 MHz  
0.18um  
yes  
80 MHz  
100 MHz  
Resource frequency  
Technology  
40 MHz  
50 MHz  
0.35um  
0.18um  
Watchdog  
yes  
yes  
Watchdog (RC osc. based)  
Bit Search  
yes (disengageable)  
yes (disengageable)  
yes  
yes  
yes  
yes  
yes  
5 ch  
no  
yes  
yes  
yes  
yes  
5 ch  
tbd  
yes  
Reset Input (INITX)  
Clock Modulator  
Low Power Mode  
DMA  
yes  
yes  
yes  
5 ch  
MAC (uDSP)  
no  
1)  
1)  
1)  
MMU/MPU  
MPU  
MPU  
MPU  
Flash  
Emulation SRAM  
n.a.  
Emulation SRAM  
n.a.  
1 MByte  
yes  
Flash Protection  
D-bus RAM  
64 kByte  
64 kByte  
16 kByte  
4 kByte  
64 kByte  
64 kByte  
16 kByte  
4 kByte  
32 kByte  
32 kByte  
8 kByte  
4 kByte  
I/D-bus RAM  
I-bus RAM / I-Cache  
Boot-ROM / BI-ROM  
RTC  
1 ch  
1 ch  
1 ch  
Free Running Timer  
ICU  
8 ch  
8 ch  
8 ch  
8 ch  
8 ch  
8 ch  
OCU  
8 ch  
8 ch  
4 ch  
Reload Timer  
PPG 16-bit  
8 ch  
8 ch  
8 ch  
16 ch  
16 ch  
12 ch  
PFM 16-bit  
1 ch  
1 ch  
1 ch  
1 ch  
1 ch  
1 ch  
Sound Generator  
Up/Down Counter (8/16-bit)  
4 ch (8-bit) / 2 ch (16-bit)  
4 ch (8-bit) / 2 ch (16-bit)  
3 ch (8-bit) / 1 ch (16-bit)  
C_CAN (32 MsgBuf)  
LIN-USART  
6 ch (128msg)  
4 ch + 4 ch FIFO + 8 ch  
4 ch  
6 ch (128msg)  
4 ch + 4 ch FIFO + 8 ch  
4 ch  
3 ch (32msg)  
1 ch + 4 ch FIFO  
3 ch  
I2C (400k)  
FR external bus  
yes (32bit addr, 32bit data)  
yes (32bit addr, 32bit data)  
yes (26bit addr, 32bit data)  
External Interrupts  
NMI Interrupts  
16 ch  
1 ch  
16 ch  
1 ch  
10 ch  
no  
SMC  
6 ch  
1 ch  
6 ch  
1 ch  
6 ch  
no  
LCD controller (40x4)  
19  
 
Chapter 2 MB91460 Rev.A/Rev.B Overview  
3.MB91460 Series Product Lineup  
Feature  
MB91V460 Rev.A  
MB91V460 Rev.B  
MB91F467DA  
24 ch  
ADC (10 bit)  
32 ch  
2 ch  
32 ch  
2 ch  
Alarm Comparator  
1 ch  
Supply Supervisor  
Clock Supervisor  
yes  
yes  
yes  
yes  
yes  
yes  
Main clock oscillator  
Sub clock oscillator  
RC Oscillator  
PLL  
4 MHz  
32 kHz  
100 kHz  
x 25  
4 MHz  
32 kHz  
4 MHz  
32 kHz  
100 kHz / 2 MHz  
x 25  
100 kHz / 2 MHz  
x 25  
DSU4  
yes  
yes  
no  
yes  
yes  
tbd  
no  
yes  
no  
EDSU  
JTAG Boundary Scan  
Supply Voltage  
3V / 5V  
yes  
tbd  
tbd  
3V / 5V  
yes  
Regulator  
Power Consumption  
Temperatur Range (Ta)  
n.a.  
n.a.  
< 1 W  
0..70 C  
0..70 C  
-40..105 C  
Package  
PGA/BGA  
PGA/BGA  
QFP208  
Power on to PLL run  
Flash Download Time  
< 20 ms  
n.a.  
< 20 ms  
n.a.  
< 20 ms  
< 30 sec (2M)  
2
I S  
no  
no  
no  
no  
yes  
yes  
yes  
yes  
no  
no  
no  
no  
MediaLB (MOST interface)  
USB  
Flexray  
MB91V460 Rev.B : This series is presently being specified and not available yet.  
1) The Memory protection Unit (MPU) is a part of the EDSU functionality  
20  
Chapter 2 MB91460 Rev.A/Rev.B Overview  
4.Block Diagram  
4. Block Diagram  
The following illustration shows the block diagram of MB91460 series.  
Figure 4-1 Block Diagram MB91460 Series  
M − B u s  
D − B u s  
I − B u s  
F − B u s  
21  
 
Chapter 2 MB91460 Rev.A/Rev.B Overview  
4.Block Diagram  
22  
Chapter 3 MB91460 Series Basic Information  
1.Memory Map  
Chapter 3 MB91460 Series Basic Information  
This chapter describes MB91460 series basic information including Memory- and I/O map, inter-  
rupt vector table, pin function list, circuit type and pin state table for each device mode.  
1. Memory Map  
Figure 1-1 Memory Map  
23  
     
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
2. I/O Map  
This section shows the association between memory space and each register of peripheral resources.  
• Table convention  
Address offset/Register name  
Block  
Address  
000000H  
+3  
+0  
+1  
+2  
T-unit  
Port data register  
PDRD[R/W]  
xxxxxxxx  
PDR2[R/W]  
xxxxxxxx  
PDR3[R/W]  
xxxxxxxx  
PDR1[R/W]  
xxxxxxxx  
MSB LSB  
Read/Write attribute (R: Read, W: Write)  
Register initial value ("0", "1", "X" : undefined, "-" : not implemented)  
Register name (First column register is 4n address,  
Second column register is 4n+2 address...)  
Leftmost register address  
(For Word access, first register becomes MSB side of the data.)  
Note: Bit value of register shows initial values as follows.  
•"1": Initial value is "1".  
• "0": Initial value is "0".  
• "X": Initial value is indeterminate.  
• "N/A": No physical register exists in the position.  
Do not use other data access attributes to access data.  
24  
   
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Table 2-1 I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
PDR00 [R/W]  
XXXXXXXX  
PDR01 [R/W]  
XXXXXXXX  
PDR02 [R/W]  
XXXXXXXX  
PDR03 [R/W]  
XXXXXXXX  
000000  
000004  
000008  
H
H
H
PDR04 [R/W]  
XXXXXXXX  
PDR05 [R/W]  
XXXXXXXX  
PDR06 [R/W]  
XXXXXXXX  
PDR07 [R/W]  
XXXXXXXX  
PDR08 [R/W]  
XXXXXXXX  
PDR09 [R/W]  
XXXXXXXX  
PDR10 [R/W]  
XXXXXXXX  
PDR11 [R/W]  
XXXXXXXX  
PDR12 [R/W]  
XXXXXXXX  
PDR13 [R/W]  
XXXXXXXX  
PDR14 [R/W]  
XXXXXXXX  
PDR15 [R/W]  
XXXXXXXX  
00000C  
H
R-bus  
PDR16 [R/W]  
XXXXXXXX  
PDR17 [R/W]  
XXXXXXXX  
PDR18 [R/W]  
XXXXXXXX  
PDR19 [R/W]  
XXXXXXXX  
Port Data  
Register  
000010  
000014  
000018  
H
PDR20 [R/W]  
XXXXXXXX  
PDR21 [R/W]  
XXXXXXXX  
PDR22 [R/W]  
XXXXXXXX  
PDR23 [R/W]  
XXXXXXXX  
H
H
PDR24 [R/W]  
XXXXXXXX  
PDR25 [R/W]  
XXXXXXXX  
PDR26 [R/W]  
XXXXXXXX  
PDR27 [R/W]  
XXXXXXXX  
PDR28 [R/W]  
XXXXXXXX  
PDR29 [R/W]  
XXXXXXXX  
PDR30 [R/W]  
XXXXXXXX  
PDR31 [R/W]  
XXXXXXXX  
00001C  
H
PDR32 [R/W]  
XXXXXXXX  
PDR33 [R/W]  
XXXXXXXX  
PDR34 [R/W]  
XXXXXXXX  
PDR35 [R/W]  
XXXXXXXX  
000020  
H
000024  
-
H
reserved  
00002C  
H
EIRR0 [R/W]  
00000000  
ENIR0 [R/W]  
00000000  
ELVR0 [R/W]  
00000000 00000000  
Ext. INT 0-7  
NMI  
000030  
000034  
000038  
H
EIRR1 [R/W]  
00000000  
ENIR1 [R/W]  
00000000  
ELVR1 [R/W]  
00000000 00000000  
Ext. INT 8-15  
DLYI/I-unit  
H
H
DICR [R/W]  
- - - - - - - 0  
HRCL [R/W]  
0 - - 11111  
*1  
RBSYNC  
00003C  
reserved  
H
RDR00/TDR00  
SCR00 [R/W,W]  
00000000  
SMR00 [R/W,W]  
00000000  
SSR00 [R/W,R]  
00001000  
000040  
[R/W]  
00000000  
H
USART (LIN)  
0
ECCR00  
[R/W,R,W]  
000000XX  
ESCR00 [R/W]  
00000X00  
000044  
res.  
H
25  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
RDR01/TDR01  
[R/W]  
SCR01 [R/W,W]  
00000000  
SMR01 [R/W,W]  
00000000  
SSR01 [R/W,R]  
00001000  
000048  
H
00000000  
USART (LIN)  
1
ECCR01  
[R/W,R,W]  
000000XX  
ESCR01 [R/W]  
00000X00  
00004C  
000050  
res.  
res.  
res.  
H
RDR02/TDR02  
[R/W]  
SCR02 [R/W,W]  
00000000  
SMR02 [R/W,W]  
00000000  
SSR02 [R/W,R]  
00001000  
H
00000000  
USART (LIN)  
2
ECCR02  
[R/W,R,W]  
000000XX  
ESCR02 [R/W]  
00000X00  
000054  
000058  
H
RDR03/TDR03  
[R/W]  
SCR03 [R/W,W]  
00000000  
SMR03 [R/W,W]  
00000000  
SSR03 [R/W,R]  
00001000  
H
00000000  
USART (LIN)  
3
ECCR03  
[R/W,R,W]  
000000XX  
ESCR03 [R/W]  
00000X00  
00005C  
000060  
H
RDR04/TDR04  
[R/W]  
SCR04 [R/W,W]  
00000000  
SMR04 [R/W,W]  
00000000  
SSR04 [R/W,R]  
00001000  
H
USART (LIN)  
4
00000000  
ECCR04  
[R/W,R,W]  
000000XX  
with FIFO  
ESCR04 [R/W]  
00000X00  
FSR04 [R]  
- - - 00000  
FCR04 [R/W]  
0001 - 000  
000064  
H
RDR05/TDR05  
[R/W]  
SCR05 [R/W,W]  
00000000  
SMR05 [R/W,W]  
00000000  
SSR05 [R/W,R]  
00001000  
000068  
H
USART (LIN)  
5
00000000  
ECCR05  
[R/W,R,W]  
000000XX  
with FIFO  
ESCR05 [R/W]  
00000X00  
FSR05 [R]  
- - - 00000  
FCR05 [R/W]  
0001 - 000  
00006C  
000070  
H
RDR06/TDR06  
[R/W]  
SCR06 [R/W,W]  
00000000  
SMR06 [R/W,W]  
00000000  
SSR06 [R/W,R]  
00001000  
H
USART (LIN)  
6
00000000  
ECCR06  
[R/W,R,W]  
000000XX  
with FIFO  
ESCR06 [R/W]  
00000X00  
FSR06 [R]  
- - - 00000  
FCR06 [R/W]  
0001 - 000  
000074  
H
RDR07/TDR07  
[R/W]  
SCR07 [R/W,W]  
00000000  
SMR07 [R/W,W]  
00000000  
SSR07 [R/W,R]  
00001000  
000078  
H
USART (LIN)  
7
00000000  
ECCR07  
[R/W,R,W]  
000000XX  
with FIFO  
ESCR07 [R/W]  
00000X00  
FSR07 [R]  
- - - 00000  
FCR07 [R/W]  
0001 - 000  
00007C  
H
26  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
BGR100 [R/W]  
00000000  
BGR000 [R/W]  
00000000  
BGR101 [R/W]  
00000000  
BGR001 [R/W]  
00000000  
000080  
000084  
000088  
H
H
H
BGR102 [R/W]  
00000000  
BGR002 [R/W]  
00000000  
BGR103 [R/W]  
00000000  
BGR003 [R/W]  
Baudrate  
00000000  
Generator  
USART (LIN)  
0-7  
BGR104 [R/W]  
00000000  
BGR004 [R/W]  
00000000  
BGR105 [R/W]  
00000000  
BGR005 [R/W]  
00000000  
BGR106 [R/W]  
00000000  
BGR006 [R/W]  
00000000  
BGR107 [R/W]  
00000000  
BGR007 [R/W]  
00000000  
00008C  
H
PWC20 [R/W]  
- - - - - - XX XXXXXXXX  
PWC10 [R/W]  
- - - - - - XX XXXXXXXX  
000090  
000094  
000098  
H
Stepper Motor  
0
PWS20 [R/W]  
-0000000  
PWS10 [R/W]  
--000000  
res.  
res.  
H
H
PWC21 [R/W]  
- - - - - - XX XXXXXXXX  
PWC11 [R/W]  
- - - - - - XX XXXXXXXX  
Stepper Motor  
1
PWS21 [R/W]  
-0000000  
PWS11 [R/W]  
--000000  
00009C  
res.  
res.  
H
H
H
H
PWC22 [R/W]  
- - - - - - XX XXXXXXXX  
PWC12 [R/W]  
- - - - - - XX XXXXXXXX  
0000A0  
0000A4  
0000A8  
Stepper Motor  
2
PWS22 [R/W]  
-0000000  
PWS12 [R/W]  
--000000  
res.  
res.  
PWC23 [R/W]  
- - - - - - XX XXXXXXXX  
PWC13 [R/W]  
- - - - - - XX XXXXXXXX  
Stepper Motor  
3
PWS23 [R/W]  
-0000000  
PWS13 [R/W]  
--000000  
0000AC  
res.  
res.  
H
H
H
H
PWC24 [R/W]  
- - - - - - XX XXXXXXXX  
PWC14 [R/W]  
- - - - - - XX XXXXXXXX  
0000B0  
0000B4  
0000B8  
Stepper Motor  
4
PWS24 [R/W]  
-0000000  
PWS14 [R/W]  
--000000  
res.  
res.  
PWC25 [R/W]  
- - - - - - XX XXXXXXXX  
PWC15 [R/W]  
- - - - - - XX XXXXXXXX  
Stepper Motor  
5
PWS25 [R/W]  
-0000000  
PWS15 [R/W]  
--000000  
0000BC  
0000C0  
res.  
res.  
res.  
res.  
res.  
H
PWC0 [R/W]  
-00000--  
PWC1 [R/W]  
-00000--  
res.  
H
H
H
Stepper Motor  
Control  
0-5  
PWC2 [R/W]  
-00000--  
PWC3 [R/W]  
-00000--  
0000C4  
0000C8  
res.  
res.  
PWC4 [R/W]  
-00000--  
PWC5 [R/W]  
-00000--  
0000CC  
reserved  
H
27  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
IBCR0 [R/W]  
00000000  
IBSR0 [R]  
00000000  
ITBAH0 [R/W]  
- - - - - - 00  
ITBAL0 [R/W]  
00000000  
0000D0  
0000D4  
0000D8  
H
H
H
ITMKH0 [R/W]  
00 - - - - 11  
ITMKL0 [R/W]  
11111111  
ISMK0 [R/W]  
01111111  
ISBA0 [R/W]  
- 0000000  
I2C 0  
IDAR0 [R/W]  
00000000  
ICCR0 [R/W]  
- 0011111  
res.  
res.  
IBCR1 [R/W]  
00000000  
IBSR1 [R]  
00000000  
ITBAH1 [R/W]  
- - - - - - 00  
ITBAL1 [R/W]  
00000000  
0000DC  
0000E0  
H
ITMKH1 [R/W]  
00 - - - - 11  
ITMKL1 [R/W]  
11111111  
ISMK1 [R/W]  
01111111  
ISBA1 [R/W]  
- 0000000  
I2C 1  
H
IDAR1 [R/W]  
00000000  
ICCR1 [R/W]  
- 0011111  
0000E4  
0000E8  
res.  
res.  
H
LCDCMR [R/W]  
- - - - 0000  
LCR0 [R/W]  
00010000  
LCR1H [R/W]  
- - - - - - 00  
LCR1L [R/W]  
00000000  
H
0000EC  
VRAM00 [R/W]  
XXXXXXXX  
VRAM01 [R/W]  
XXXXXXXX  
VRAM02 [R/W]  
XXXXXXXX  
VRAM03 [R/W]  
XXXXXXXX  
H
0000F0  
0000F4  
0000F8  
VRAM04 [R/W]  
XXXXXXXX  
VRAM05 [R/W]  
XXXXXXXX  
VRAM06 [R/W]  
XXXXXXXX  
VRAM07 [R/W]  
XXXXXXXX  
H
LCD  
Controller  
VRAM08 [R/W]  
XXXXXXXX  
VRAM09 [R/W]  
XXXXXXXX  
VRAM10 [R/W]  
XXXXXXXX  
VRAM11 [R/W]  
XXXXXXXX  
H
H
VRAM12 [R/W]  
XXXXXXXX  
VRAM13 [R/W]  
XXXXXXXX  
VRAM14 [R/W]  
XXXXXXXX  
VRAM15 [R/W]  
XXXXXXXX  
0000FC  
000100  
VRAM16 [R/W]  
XXXXXXXX  
VRAM17 [R/W]  
XXXXXXXX  
VRAM18 [R/W]  
XXXXXXXX  
VRAM19 [R/W]  
XXXXXXXX  
H
GCN10 [R/W]  
00110010 00010000  
GCN20 [R/W]  
- - - - 0000  
PPG Control  
0-3  
res.  
res.  
res.  
H
GCN11 [R/W]  
00110010 00010000  
GCN21 [R/W]  
- - - - 0000  
PPG Control  
4-7  
000104  
000108  
000110  
000114  
000118  
H
GCN12 [R/W]  
00110010 00010000  
GCN22 [R/W]  
- - - - 0000  
PPG Control  
8-11  
H
H
H
H
PTMR00 [R]  
11111111 11111111  
PCSR00 [W]  
XXXXXXXX XXXXXXXX  
PPG 0  
PPG 1  
PDUT00 [W]  
XXXXXXXX XXXXXXXX  
PCNH00 [R/W]  
0000000 -  
PCNL00 [R/W]  
000000 - 0  
PTMR01 [R]  
11111111 11111111  
PCSR01 [W]  
XXXXXXXX XXXXXXXX  
PDUT01 [W]  
XXXXXXXX XXXXXXXX  
PCNH01 [R/W]  
PCNL01 [R/W]  
00011C  
H
0000000 - 000000 - 0  
28  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
PTMR02 [R]  
11111111 11111111  
PCSR02 [W]  
XXXXXXXX XXXXXXXX  
000120  
000124  
000128  
H
H
H
PPG 2  
PPG 3  
PPG 4  
PPG 5  
PPG 6  
PPG 7  
PPG 8  
PPG 9  
PPG 10  
PPG 11  
PDUT02 [W]  
XXXXXXXX XXXXXXXX  
PCNH02 [R/W]  
0000000 -  
PCNL02 [R/W]  
000000 - 0  
PTMR03 [R]  
11111111 11111111  
PCSR03 [W]  
XXXXXXXX XXXXXXXX  
PDUT03 [W]  
XXXXXXXX XXXXXXXX  
PCNH03 [R/W]  
0000000 -  
PCNL03 [R/W]  
000000 - 0  
00012C  
H
PTMR04 [R]  
11111111 11111111  
PCSR04 [W]  
XXXXXXXX XXXXXXXX  
000130  
000134  
000138  
H
PDUT04 [W]  
XXXXXXXX XXXXXXXX  
PCNH04 [R/W]  
0000000 -  
PCNL04 [R/W]  
000000 - 0  
H
H
PTMR05 [R]  
11111111 11111111  
PCSR05 [W]  
XXXXXXXX XXXXXXXX  
PDUT05 [W]  
XXXXXXXX XXXXXXXX  
PCNH05 [R/W]  
0000000 -  
PCNL05 [R/W]  
000000 - 0  
00013C  
H
PTMR06 [R]  
11111111 11111111  
PCSR06 [W]  
XXXXXXXX XXXXXXXX  
000140  
000144  
000148  
H
PDUT06 [W]  
XXXXXXXX XXXXXXXX  
PCNH06 [R/W]  
0000000 -  
PCNL06 [R/W]  
000000 - 0  
H
H
PTMR07 [R]  
11111111 11111111  
PCSR07 [W]  
XXXXXXXX XXXXXXXX  
PDUT07 [W]  
XXXXXXXX XXXXXXXX  
PCNH07 [R/W]  
0000000 -  
PCNL07 [R/W]  
000000 - 0  
00014C  
H
PTMR08 [R]  
11111111 11111111  
PCSR08 [W]  
XXXXXXXX XXXXXXXX  
000150  
000154  
000158  
H
PDUT08 [W]  
XXXXXXXX XXXXXXXX  
PCNH08 [R/W]  
0000000 -  
PCNL08 [R/W]  
000000 - 0  
H
H
PTMR09 [R]  
11111111 11111111  
PCSR09 [W]  
XXXXXXXX XXXXXXXX  
PDUT09 [W]  
XXXXXXXX XXXXXXXX  
PCNH09 [R/W]  
0000000 -  
PCNL09 [R/W]  
000000 - 0  
00015C  
H
PTMR10 [R]  
11111111 11111111  
PCSR10 [W]  
XXXXXXXX XXXXXXXX  
000160  
000164  
000168  
H
PDUT10 [W]  
XXXXXXXX XXXXXXXX  
PCNH10 [R/W]  
0000000 -  
PCNL10 [R/W]  
000000 - 0  
H
H
PTMR11 [R]  
11111111 11111111  
PCSR11 [W]  
XXXXXXXX XXXXXXXX  
PDUT11 [W]  
XXXXXXXX XXXXXXXX  
PCNH11 [R/W]  
PCNL11 [R/W]  
00016C  
H
0000000 - 000000 - 0  
29  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
P0TMCSRH  
[R/W]  
P0TMCSRL  
[R/W]  
P1TMCSRH  
[R/W]  
P1TMCSRL  
[R/W]  
000170  
H
- 0 - 000 - 0  
- - - 00000  
- 0 - 000 - 0  
- - - 00000  
Pulse  
P0TMRLR [W]  
XXXXXXXX XXXXXXXX  
P0TMR [R]  
XXXXXXXX XXXXXXXX  
Frequency  
Modulator  
000174  
000178  
H
P1TMRLR [W]  
XXXXXXXX XXXXXXXX  
P1TMR [R]  
XXXXXXXX XXXXXXXX  
H
00017C  
000180  
reserved  
H
ICS01 [R/W]  
00000000  
ICS23 [R/W]  
00000000  
res.  
res.  
H
Input  
Capture  
0-3  
IPCP0 [R]  
XXXXXXXX XXXXXXXX  
IPCP1 [R]  
XXXXXXXX XXXXXXXX  
000184  
000188  
H
IPCP2 [R]  
XXXXXXXX XXXXXXXX  
IPCP3 [R]  
XXXXXXXX XXXXXXXX  
H
OCS01 [R/W]  
- - - 0 - - 00 0000 - - 00  
OCS23 [R/W]  
- - - 0 - - 00 0000 - - 00  
00018C  
000190  
H
Output  
Compare  
0-3  
OCCP0 [R/W]  
XXXXXXXX XXXXXXXX  
OCCP1 [R/W]  
XXXXXXXX XXXXXXXX  
H
OCCP2 [R/W]  
XXXXXXXX XXXXXXXX  
OCCP3 [R/W]  
XXXXXXXX XXXXXXXX  
000194  
000198  
H
SGCRH [R/W]  
SGCRL [R/W]  
SGFR [R/W, R]  
H
0000 - - 00  
- - 0 - - 000  
XXXXXXXX XXXXXXXX  
Sound  
Generator  
00019C  
SGAR [R/W]  
00000000  
SGTR [R/W]  
XXXXXXXX  
SGDR [R/W]  
XXXXXXXX  
H
res.  
ADERH [R/W]  
00000000 00000000  
ADERL [R/W]  
00000000 00000000  
0001A0  
H
ADCS1 [R/W]  
00000000  
ADCS0 [R/W]  
00000000  
ADCR1 [R]  
000000XX  
ADCR0 [R]  
XXXXXXXX  
A/D  
Converter  
0001A4  
0001A8  
ADCT1 [R/W]  
00010000  
ADCT0 [R/W]  
00101100  
ADSCH [R/W]  
- - - 00000  
ADECH [R/W]  
- - - 00000  
H
ACSR0 [R/W]  
011XXX00  
ACSR1 [R/W]  
011XXX00  
Alarm Com-  
parator 0-1  
0001AC  
res.  
res.  
H
TMRLR0 [W]  
TMR0 [R]  
XXXXXXXX XXXXXXXX  
0001B0  
H
Reload Timer  
0
XXXXXXXX XXXXXXXX  
reserved  
TMCSRH0  
TMCSRL0  
0001B4  
[R/W] [R/W]  
- - - 00000 0 - 000000  
H
(PPG 0-1)  
30  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
TMRLR1 [W]  
TMR1 [R]  
XXXXXXXX XXXXXXXX  
0001B8  
H
Reload Timer  
1
XXXXXXXX XXXXXXXX  
reserved  
TMCSRH1  
[R/W]  
- - - 00000  
TMCSRL1  
[R/W]  
0 - 000000  
0001BC  
H
H
H
H
(PPG 2-3)  
TMRLR2 [W]  
XXXXXXXX XXXXXXXX  
TMR2 [R]  
XXXXXXXX XXXXXXXX  
0001C0  
0001C4  
0001C8  
Reload Timer  
2
TMCSRH2  
TMCSRL2  
reserved  
[R/W] [R/W]  
- - - 00000 0 - 000000  
(PPG 4-5)  
TMRLR3 [W]  
XXXXXXXX XXXXXXXX  
TMR3 [R]  
XXXXXXXX XXXXXXXX  
Reload Timer  
3
TMCSRH3  
TMCSRL3  
0001CC  
reserved  
[R/W] [R/W]  
- - - 00000 0 - 000000  
H
(PPG 6-7)  
TMRLR4 [W]  
XXXXXXXX XXXXXXXX  
TMR4 [R]  
XXXXXXXX XXXXXXXX  
0001D0  
0001D4  
0001D8  
H
Reload Timer  
4
TMCSRH4  
TMCSRL4  
reserved  
[R/W] [R/W]  
- - - 00000 0 - 000000  
H
H
(PPG 8-9)  
TMRLR5 [W]  
XXXXXXXX XXXXXXXX  
TMR5 [R]  
XXXXXXXX XXXXXXXX  
Reload Timer  
5
TMCSRH5  
TMCSRL5  
0001DC  
reserved  
[R/W] [R/W]  
- - - 00000 0 - 000000  
H
(PPG 10-11)  
TMRLR6 [W]  
XXXXXXXX XXXXXXXX  
TMR6 [R]  
XXXXXXXX XXXXXXXX  
Reload Timer  
6
0001E0  
0001E4  
0001E8  
H
TMCSRH6  
TMCSRL6  
(PPG 12-13)  
reserved  
[R/W] [R/W]  
- - - 00000 0 - 000000  
H
H
TMRLR7 [W]  
XXXXXXXX XXXXXXXX  
TMR7 [R]  
XXXXXXXX XXXXXXXX  
Reload Timer  
7
TMCSRH7  
[R/W] [R/W]  
- - - 00000  
TMCSRL7  
(PPG 14-15)  
(ADC)  
0001EC  
reserved  
H
0 - 000000  
Free Running  
Timer 0  
TCDT0 [R/W]  
XXXXXXXX XXXXXXXX  
TCCS0 [R/W]  
00000000  
0001F0  
res.  
H
(ICU 0-1)  
Free Running  
Timer 1  
TCDT1 [R/W]  
XXXXXXXX XXXXXXXX  
TCCS1 [R/W]  
00000000  
0001F4  
res.  
H
(ICU 2-3)  
31  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
Free Running  
Timer 2  
TCDT2 [R/W]  
XXXXXXXX XXXXXXXX  
TCCS2 [R/W]  
00000000  
0001F8  
res.  
H
(OCU 0-1)  
Free Running  
Timer 3  
TCDT3 [R/W]  
XXXXXXXX XXXXXXXX  
TCCS3 [R/W]  
00000000  
0001FC  
res.  
H
(OCU 2-3)  
000200  
000204  
000208  
DMACA0 [R/W]  
00000000 0000XXXX XXXXXXXX XXXXXXXX  
H
DMACB0 [R/W]  
00000000 00000000 XXXXXXXX XXXXXXXX  
H
H
DMACA1 [R/W]  
00000000 0000XXXX XXXXXXXX XXXXXXXX  
00020C  
DMACB1 [R/W]  
H
00000000 00000000 XXXXXXXX XXXXXXXX  
000210  
000214  
000218  
DMACA2 [R/W]  
00000000 0000XXXX XXXXXXXX XXXXXXXX  
H
DMACB2 [R/W]  
00000000 00000000 XXXXXXXX XXXXXXXX  
H
H
DMAC  
DMACA3 [R/W]  
00000000 0000XXXX XXXXXXXX XXXXXXXX  
00021C  
DMACB3 [R/W]  
H
00000000 00000000 XXXXXXXX XXXXXXXX  
000220  
DMACA4 [R/W]  
H
00000000 0000XXXX XXXXXXXX XXXXXXXX  
000224  
DMACB4 [R/W]  
00000000 00000000 XXXXXXXX XXXXXXXX  
H
H
000228  
-
00023C  
reserved  
reserved  
reserved  
H
000240  
DMACR [R/W]  
0 - - 00000  
H
000244  
-
H
00024C  
H
000250  
DMATEST0 [R/W]  
H
XXXXXXXX 00000000 00000000 0000XXXX  
DMA Test  
(do not use)  
000254  
DMATEST1 [R]  
H
XXXXXXXX XXXXX000 00000000 00000000  
32  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
000258  
-
H
reserved  
00027C  
H
RDR08/TDR08  
[R/W]  
SCR08 [R/W,W]  
00000000  
SMR08 [R/W,W]  
00000000  
SSR08 [R/W,R]  
00001000  
000280  
H
00000000  
USART (LIN)  
8
ECCR08  
[R/W,R,W]  
000000XX  
ESCR08 [R/W]  
00000X00  
000284  
000288  
res.  
H
RDR09/TDR09  
[R/W]  
SCR09 [R/W,W]  
00000000  
SMR09 [R/W,W]  
00000000  
SSR09 [R/W,R]  
00001000  
H
00000000  
USART (LIN)  
9
ECCR09  
[R/W,R,W]  
000000XX  
ESCR09 [R/W]  
00000X00  
00028C  
res.  
H
RDR10/TDR10  
[R/W]  
SCR10 [R/W,W]  
00000000  
SMR10 [R/W,W]  
00000000  
SSR10 [R/W,R]  
00001000  
000290  
H
00000000  
USART (LIN)  
10  
ECCR10  
[R/W,R,W]  
000000XX  
ESCR10 [R/W]  
00000X00  
000294  
000298  
res.  
H
RDR11/TDR11  
[R/W]  
SCR11 [R/W,W]  
00000000  
SMR11 [R/W,W]  
00000000  
SSR11 [R/W,R]  
00001000  
H
00000000  
USART (LIN)  
11  
ECCR11  
[R/W,R,W]  
000000XX  
ESCR11 [R/W]  
00000X00  
00029C  
res.  
H
RDR12/TDR12  
[R/W]  
SCR12 [R/W,W]  
00000000  
SMR12 [R/W,W]  
00000000  
SSR12 [R/W,R]  
00001000  
0002A0  
H
H
H
00000000  
USART (LIN)  
12  
ECCR12  
[R/W,R,W]  
000000XX  
ESCR12 [R/W]  
00000X00  
0002A4  
0002A8  
res.  
RDR13/TDR13  
[R/W]  
SCR13 [R/W,W]  
00000000  
SMR13 [R/W,W]  
00000000  
SSR13 [R/W,R]  
00001000  
00000000  
USART (LIN)  
13  
ECCR13  
[R/W,R,W]  
000000XX  
ESCR13 [R/W]  
00000X00  
0002AC  
res.  
H
33  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
RDR14/TDR14  
[R/W]  
SCR14 [R/W,W]  
00000000  
SMR14 [R/W,W]  
00000000  
SSR14 [R/W,R]  
00001000  
0002B0  
0002B4  
0002B8  
H
H
H
00000000  
USART (LIN)  
14  
ECCR14  
[R/W,R,W]  
000000XX  
ESCR14 [R/W]  
00000X00  
res.  
res.  
RDR15/TDR15  
[R/W]  
SCR15 [R/W,W]  
00000000  
SMR15 [R/W,W]  
00000000  
SSR15 [R/W,R]  
00001000  
00000000  
USART (LIN)  
15  
ECCR15  
[R/W,R,W]  
000000XX  
ESCR15 [R/W]  
00000X00  
0002BC  
H
BGR108 [R/W]  
00000000  
BGR008 [R/W]  
00000000  
BGR109 [R/W]  
00000000  
BGR009 [R/W]  
00000000  
0002C0  
0002C4  
0002C8  
H
H
H
BGR110 [R/W]  
00000000  
BGR010 [R/W]  
00000000  
BGR111 [R/W]  
00000000  
BGR011 [R/W]  
00000000  
Baudrate  
Generator  
USART (LIN)  
8-15  
BGR112 [R/W]  
00000000  
BGR012 [R/W]  
00000000  
BGR113 [R/W]  
00000000  
BGR013 [R/W]  
00000000  
BGR114 [R/W]  
00000000  
BGR014 [R/W]  
00000000  
BGR15 [R/W]  
00000000  
BGR015 [R/W]  
00000000  
0002CC  
0002D0  
H
ICS45 [R/W]  
00000000  
ICS67 [R/W]  
00000000  
res.  
res.  
H
Input  
Capture  
4-7  
IPCP4 [R]  
XXXXXXXX XXXXXXXX  
IPCP5 [R]  
XXXXXXXX XXXXXXXX  
0002D4  
0002D8  
H
IPCP6 [R]  
XXXXXXXX XXXXXXXX  
IPCP7 [R]  
XXXXXXXX XXXXXXXX  
H
OCS45 [R/W]  
- - - 0 - - 00 0000 - - 00  
OCS67 [R/W]  
- - - 0 - - 00 0000 - - 00  
0002DC  
H
Output  
Compare  
4-7  
OCCP4 [R/W]  
XXXXXXXX XXXXXXXX  
OCCP5 [R/W]  
XXXXXXXX XXXXXXXX  
0002E0  
H
OCCP6 [R/W]  
XXXXXXXX XXXXXXXX  
OCCP7 [R/W]  
XXXXXXXX XXXXXXXX  
0002E4  
H
0002E8  
-
H
reserved  
0002EC  
H
Free Running  
Timer 4  
TCDT4 [R/W]  
XXXXXXXX XXXXXXXX  
TCCS4 [R/W]  
00000000  
0002F0  
res.  
H
(ICU 4-5)  
34  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
Free Running  
TCDT5 [R/W]  
XXXXXXXX XXXXXXXX  
TCCS5 [R/W]  
00000000  
Timer 5  
0002F4  
res.  
H
(ICU 6-7)  
Free Running  
Timer 6  
TCDT6 [R/W]  
XXXXXXXX XXXXXXXX  
TCCS6 [R/W]  
00000000  
0002F8  
res.  
res.  
H
(OCU 4-5)  
Free Running  
Timer 7  
TCDT7 [R/W]  
XXXXXXXX XXXXXXXX  
TCCS7 [R/W]  
00000000  
0002FC  
H
(OCU 6-7)  
UDRC1 [W]  
00000000  
UDRC0 [W]  
00000000  
UDCR1 [R]  
00000000  
UDCR0 [R]  
00000000  
000300  
000304  
000308  
H
H
H
Up/Down  
Counter  
0-1  
UDCCH0 [R/W]  
00001000  
UDCCL0 [R/W]  
00000000  
UDCS0 [R/W]  
00000000  
res.  
res.  
UDCCH1 [R/W]  
00001000  
UDCCL1 [R/W]  
00000000  
UDCS1 [R/W]  
00000000  
00030C  
reserved  
H
UDRC3 [W]  
00000000  
UDRC2 [W]  
00000000  
UDCR3 [R]  
00000000  
UDCR2 [R]  
00000000  
000310  
000314  
000318  
H
Up/Down  
Counter  
2-3  
UDCCH2 [R/W]  
00001000  
UDCCL2 [R/W]  
00000000  
UDCS2 [R/W]  
00000000  
res.  
res.  
H
H
UDCCH3 [R/W]  
00001000  
UDCCL3 [R/W]  
00000000  
UDCS3 [R/W]  
00000000  
00031C  
000320  
reserved  
H
GCN13 [R/W]  
00110010 00010000  
GCN23 [R/W]  
- - - - 0000  
PPG Control  
12-15  
res.  
H
000324  
-
H
reserved  
00032C  
H
PTMR12 [R]  
11111111 11111111  
PCSR12 [W]  
XXXXXXXX XXXXXXXX  
000330  
000334  
000338  
H
PPG 12  
PPG 13  
PDUT12 [W]  
XXXXXXXX XXXXXXXX  
PCNH12 [R/W]  
0000000 -  
PCNL12 [R/W]  
000000 - 0  
H
H
PTMR13 [R]  
11111111 11111111  
PCSR13 [W]  
XXXXXXXX XXXXXXXX  
PDUT13 [W]  
PCNH13 [R/W]  
PCNL13 [R/W]  
00033C  
H
XXXXXXXX XXXXXXXX  
0000000 - 000000 - 0  
35  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
PTMR14 [R]  
11111111 11111111  
PCSR14 [W]  
XXXXXXXX XXXXXXXX  
000340  
000344  
000348  
H
H
H
PPG 14  
PDUT14 [W]  
XXXXXXXX XXXXXXXX  
PCNH14 [R/W]  
0000000 -  
PCNL14 [R/W]  
000000 - 0  
PTMR15 [R]  
11111111 11111111  
PCSR15 [W]  
XXXXXXXX XXXXXXXX  
PPG 15  
PDUT15 [W]  
PCNH15 [R/W]  
PCNL15 [R/W]  
00034C  
H
H
XXXXXXXX XXXXXXXX  
0000000 - 000000 - 0  
000350  
-
H
reserved  
00035C  
000360  
DACR [R/W]  
- - - - - 000  
res.  
res.  
res.  
H
D/A  
Converter  
DADR0 [R/W]  
- - - - - - XX XXXXXXXX  
DADR1 [R/W]  
- - - - - - XX XXXXXXXX  
000364  
H
IBCR2 [R/W]  
00000000  
IBSR2 [R]  
00000000  
ITBAH2 [R/W]  
- - - - - - 00  
ITBAL2 [R/W]  
00000000  
000368  
H
ITMKH2 [R/W]  
00 - - - - 11  
ITMKL2 [R/W]  
11111111  
ISMK2 [R/W]  
01111111  
ISBA2 [R/W]  
- 0000000  
00036C  
000370  
I2C 2  
H
IDAR2 [R/W]  
00000000  
ICCR2 [R/W]  
- 0011111  
res.  
res.  
H
IBCR3 [R/W]  
00000000  
IBSR3 [R]  
00000000  
ITBAH3 [R/W]  
- - - - - - 00  
ITBAL3 [R/W]  
00000000  
000374H  
ITMKH3 [R/W]  
00 - - - - 11  
ITMKL3 [R/W]  
11111111  
ISMK3 [R/W]  
01111111  
ISBA3 [R/W]  
- 0000000  
000378  
I2C 3  
H
IDAR3 [R/W]  
00000000  
ICCR3 [R/W]  
- 0011111  
00037C  
res.  
res.  
H
000380  
-
H
reserved  
00038C  
000390  
H
ROMS [R/W]  
XXXXXXXX XXXXXXXX  
ROM Select  
Register  
res.  
H
000394  
-
0003BC  
H
reserved  
reserved  
H
0003C0  
H
H
I-Cache  
0003C4  
ISIZE [R/W]  
- - - - - - 10  
reserved  
36  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
0003D8  
-
H
reserved  
0003E0  
H
0003E4  
ICHCR [R/W]  
I-Cache  
H
reserved  
0 - 000000  
0003E8  
-
H
reserved  
0003EC  
H
BSD0 [W]  
0003F0  
0003F4  
0003F8  
H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BSD1 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
H
Bit Search  
Module  
BSDC [W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BSRR [R]  
0003FC  
H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
000400  
-
H
reserved  
00043C  
H
37  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
ICR00 [R/W]  
---11111  
ICR01 [R/W]  
---11111  
ICR02 [R/W]  
---11111  
ICR03 [R/W]  
---11111  
000440  
000444  
000448  
H
H
H
ICR04 [R/W]  
---11111  
ICR05 [R/W]  
---11111  
ICR06 [R/W]  
---11111  
ICR07 [R/W]  
---11111  
ICR08 [R/W]  
---11111  
ICR09 [R/W]  
---11111  
ICR10 [R/W]  
---11111  
ICR11 [R/W]  
---11111  
ICR12 [R/W]  
---11111  
ICR13 [R/W]  
---11111  
ICR14 [R/W]  
---11111  
ICR15 [R/W]  
---11111  
00044C  
H
ICR16 [R/W]  
---11111  
ICR17 [R/W]  
---11111  
ICR18 [R/W]  
---11111  
ICR19 [R/W]  
---11111  
000450  
000454  
000458  
H
ICR20 [R/W]  
---11111  
ICR21 [R/W]  
---11111  
ICR22 [R/W]  
---11111  
ICR23 [R/W]  
---11111  
H
H
ICR24 [R/W]  
---11111  
ICR25 [R/W]  
---11111  
ICR26 [R/W]  
---11111  
ICR27 [R/W]  
---11111  
ICR28 [R/W]  
---11111  
ICR29 [R/W]  
---11111  
ICR30 [R/W]  
---11111  
ICR31 [R/W]  
---11111  
00045C  
H
Interrupt  
Control  
Unit  
ICR32 [R/W]  
---11111  
ICR33 [R/W]  
---11111  
ICR34 [R/W]  
---11111  
ICR35 [R/W]  
---11111  
000460  
000464  
000468  
H
ICR36 [R/W]  
---11111  
ICR37 [R/W]  
---11111  
ICR38 [R/W]  
---11111  
ICR39 [R/W]  
---11111  
H
H
ICR40 [R/W]  
---11111  
ICR41 [R/W]  
---11111  
ICR42 [R/W]  
---11111  
ICR43 [R/W]  
---11111  
ICR44 [R/W]  
---11111  
ICR45 [R/W]  
---11111  
ICR46 [R/W]  
---11111  
ICR47 [R/W]  
---11111  
00046C  
H
ICR48 [R/W]  
---11111  
ICR49 [R/W]  
---11111  
ICR50 [R/W]  
---11111  
ICR51 [R/W]  
---11111  
000470  
000474  
000478  
H
ICR52 [R/W]  
---11111  
ICR53 [R/W]  
---11111  
ICR54 [R/W]  
---11111  
ICR55 [R/W]  
---11111  
H
H
ICR56 [R/W]  
---11111  
ICR57 [R/W]  
---11111  
ICR58 [R/W]  
---11111  
ICR59 [R/W]  
---11111  
ICR60 [R/W]  
---11111  
ICR61 [R/W]  
---11111  
ICR62 [R/W]  
---11111  
ICR63 [R/W]  
---11111  
00047C  
H
RSRR [R/W]  
10000000  
STCR [R/W]  
00110011  
TBCR [R/W]  
00XXXX00  
CTBR [W]  
XXXXXXXX  
000480  
000484  
000488  
H
Clock  
Control  
Unit  
CLKR [R/W]  
----0000  
WPR [W]  
XXXXXXXX  
DIVR0 [R/W]  
00000011  
DIVR1 [R/W]  
00000000  
H
H
CTEST [R/W]  
XXXX00XX  
C-Unit Test  
(do not use)  
res.  
res.  
res.  
38  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
PLLDIVM [R/W]  
- - - - 0000  
PLLDIVN [R/W]  
- - 000000  
PLLDIVG [R/W]  
- - - - 0000  
PLLMULG [W]  
00048C  
000490  
H
00000000  
PLL Clock  
Gear Unit  
res.  
PLLCTRL [R/W]  
- - - - 0000  
res.  
res.  
H
Main/Sub  
OSCC1 [R/W]  
- - - - - 010  
OSCS1 [R/W]  
00001111  
OSCC2 [R/W]  
- - - - - 010  
OSCS2 [R/W]  
00001111  
Oscillator Con-  
trol  
(do not use)  
000494  
000498  
H
PORTEN [R/W]  
- - - - - - 00  
Port Input  
Enable Control  
res.  
res.  
res.  
H
WTCER [R/W]  
- - - - - - 00  
WTCR [R/W]  
00000000 000 - 00 - 0  
0004A0  
0004A4  
0004A8  
res.  
H
H
H
Real Time  
Clock  
(Watch Timer)  
WTBR [R/W]  
- - - - - - - - - - - XXXXX XXXXXXXX XXXXXXXX  
WTHR [R/W]  
- - - 00000  
WTMR [R/W]  
- - 000000  
WTSR [R/W]  
- - 000000  
res.  
Clock-  
CSVTR [R/W]  
(do not use)  
CSVCR [R/W]  
00011100  
CSCFG [R/W]  
0X000000  
CMCFG [R/W]  
00000000  
Supervisor /  
Selector /  
Monitor  
0004AC  
H
CUCR [R/W]  
- - - - - - - - - - - 0 - - 00  
CUTD [R/W]  
10000000 00000000  
0004B0  
0004B4  
0004B8  
H
H
H
Calibration  
Unit of Sub  
Oscillation  
CUTR1 [R]  
- - - - - - - - 00000000  
CUTR2 [R]  
00000000 00000000  
CMPR [R/W]  
- - 000010 11111101  
CMCR [R/W]  
- 001 - - 00  
res.  
Clock  
Modulation  
CMT1 [R/W]  
00000000 1 - - - 0000  
CMT2 [R/W]  
- - 000000 - - 000000  
0004BC  
H
CANPRE [R/W]  
0 - - - 0000  
CANCKD [R/W]  
- - 000000  
CAN Clock  
Control  
0004C0  
res.  
res.  
H
H
LV Detection  
/ Hardware-  
Watchdog  
LVSEL [R/W]  
00000111  
LVDET [R/W]  
- 0000 - 00  
HWWDE [R/W]  
- - - - - - 00  
HWWD [R/W,W]  
00011000  
0004C4  
0004C8  
Main-/Sub-  
Oscillation Sta-  
bilisation Timer  
OSCRH [R/W]  
000 - - 001  
OSCRL [R/W]  
- - - - - 000  
WPCRH [R/W]  
000 - - 001  
WPCRL [R/W]  
- - - - - - 00  
H
Main/Sub-  
Oscillation  
Standby Con-  
trol /  
OSCCR [R/W]  
- - - - - - 00  
REGSEL [R/W]  
- - 000110  
REGCTR [R/W]  
- - - 0 - - 00  
0004CC  
res.  
H
Main/Sub Reg-  
ulator Control  
39  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
340 Compati-  
bility Mode  
(do not use)  
C340R [R/W]  
- - - - - - - 0  
EISSRH [R/W]  
00000000  
EISSRL [R/W]  
00000000  
0004D0  
res.  
H
SHDE [R/W]  
0 - - - - - - -  
EXTE [R/W]  
00000000  
EXTF [R/W]  
00000000  
0004D4  
res.  
H
Supply Shut  
Down Mode  
EXTLV [R/W]  
00000000 00000000  
0004D8  
res.  
res.  
H
0004DC  
-
H
reserved  
00063C  
H
40  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
ASR0 [R/W]  
00000000 00000000  
ACR0 [R/W]  
1111**00 00000000  
000640  
000644  
000648  
H
H
H
ASR1 [R/W]  
XXXXXXXX XXXXXXXX  
ACR1 [R/W]  
XXXXXXXX XXXXXXXX  
ASR2 [R/W]  
XXXXXXXX XXXXXXXX  
ACR2 [R/W]  
XXXXXXXX XXXXXXXX  
ASR3 [R/W]  
XXXXXXXX XXXXXXXX  
ACR3 [R/W]  
XXXXXXXX XXXXXXXX  
00064C  
H
ASR4 [R/W]  
XXXXXXXX XXXXXXXX  
ACR4 [R/W]  
XXXXXXXX XXXXXXXX  
000650  
000654  
000658  
H
ASR5 [R/W]  
XXXXXXXX XXXXXXXX  
ACR5 [R/W]  
XXXXXXXX XXXXXXXX  
H
H
ASR6 [R/W]  
XXXXXXXX XXXXXXXX  
ACR6 [R/W]  
XXXXXXXX XXXXXXXX  
ASR7 [R/W]  
XXXXXXXX XXXXXXXX  
ACR7 [R/W]  
XXXXXXXX XXXXXXXX  
00065C  
H
AWR0 [R/W]  
01111111 11111*11  
AWR1 [R/W]  
XXXXXXXX XXXXXXXX  
000660  
000664  
000668  
H
External Bus  
Unit  
AWR2 [R/W]  
XXXXXXXX XXXXXXXX  
AWR3 [R/W]  
XXXXXXXX XXXXXXXX  
H
H
AWR4 [R/W]  
XXXXXXXX XXXXXXXX  
AWR5 [R/W]  
XXXXXXXX XXXXXXXX  
AWR6 [R/W]  
XXXXXXXX XXXXXXXX  
AWR7 [R/W]  
XXXXXXXX XXXXXXXX  
00066C  
000670  
H
MCRA [R/W]  
XXXXXXXX  
MCRB [R/W]  
XXXXXXXX  
reserved  
H
000674  
000678  
reserved  
IOWR2 [R/W]  
H
IOWR0 [R/W]  
XXXXXXXX  
IOWR1 [R/W]  
XXXXXXXX  
IOWR3 [R/W]  
XXXXXXXX  
H
XXXXXXXX  
00067C  
000680  
reserved  
H
CSER [R/W]  
00000001  
CHER [R/W]  
11111111  
TCR [R/W]  
0000****  
res.  
H
RCRH [R/W]  
00XXXXXX  
RCRL [R/W]  
XXXX0XXX  
000684  
reserved  
H
000688  
-
H
reserved  
0007F8  
H
ACR0[11:10] depends on Modevector fetch information on buswidth  
TCR[3:0] INIT value = 0000, keeps value after RST  
41  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
MODR [W]  
XXXXXXXX  
0007FC  
res.  
res.  
res.  
Mode Register  
DSU4 / RTM  
H
000800  
-
H
reserved  
reserved  
000BFC  
000C00  
H
TVCTW [W]  
XXXXXXXX  
TVCTR [R]  
- - XXXXXX  
IOS [R/W]  
- - - - - - - 0  
I-Unit Test  
(do not use)  
res.  
H
000C04  
-
H
000CFC  
H
PDRD00 [R]  
XXXXXXXX  
PDRD01 [R]  
XXXXXXXX  
PDRD02 [R]  
XXXXXXXX  
PDRD03 [R]  
XXXXXXXX  
000D00  
000D04  
000D08  
H
PDRD04 [R]  
XXXXXXXX  
PDRD05 [R]  
XXXXXXXX  
PDRD06 [R]  
XXXXXXXX  
PDRD07 [R]  
XXXXXXXX  
H
H
PDRD08 [R]  
XXXXXXXX  
PDRD09 [R]  
XXXXXXXX  
PDRD10 [R]  
XXXXXXXX  
PDRD11 [R]  
XXXXXXXX  
PDRD12 [R]  
XXXXXXXX  
PDRD13 [R]  
XXXXXXXX  
PDRD14 [R]  
XXXXXXXX  
PDRD15 [R]  
XXXXXXXX  
000D0C  
H
R-bus  
PDRD16 [R]  
XXXXXXXX  
PDRD17 [R]  
XXXXXXXX  
PDRD18 [R]  
XXXXXXXX  
PDRD19 [R]  
XXXXXXXX  
Port Data  
Direct Read  
Register  
000D10  
000D14  
000D18  
H
PDRD20 [R]  
XXXXXXXX  
PDRD21 [R]  
XXXXXXXX  
PDRD22 [R]  
XXXXXXXX  
PDRD23 [R]  
XXXXXXXX  
H
H
PDRD24 [R]  
XXXXXXXX  
PDRD25 [R]  
XXXXXXXX  
PDRD26 [R]  
XXXXXXXX  
PDRD27 [R]  
XXXXXXXX  
PDRD28 [R]  
XXXXXXXX  
PDRD29 [R]  
XXXXXXXX  
PDRD30 [R]  
XXXXXXXX  
PDRD31 [R]  
XXXXXXXX  
000D1C  
H
PDRD32 [R]  
XXXXXXXX  
PDRD33 [R]  
XXXXXXXX  
PDRD34 [R]  
XXXXXXXX  
PDRD35 [R]  
XXXXXXXX  
000D20  
H
000D24  
-
H
reserved  
000D3C  
H
42  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
DDR00 [R/W]  
00000000  
DDR01 [R/W]  
00000000  
DDR02 [R/W]  
00000000  
DDR03 [R/W]  
00000000  
000D40  
000D44  
000D48  
H
H
H
DDR04 [R/W]  
00000000  
DDR05 [R/W]  
00000000  
DDR06 [R/W]  
00000000  
DDR07 [R/W]  
00000000  
DDR08 [R/W]  
00000000  
DDR09 [R/W]  
00000000  
DDR10 [R/W]  
00000000  
DDR11 [R/W]  
00000000  
DDR12 [R/W]  
00000000  
DDR13 [R/W]  
00000000  
DDR14 [R/W]  
00000000  
DDR15 [R/W]  
00000000  
000D4C  
000D50  
H
R-bus  
DDR19 [R/W]  
Port Direction  
00000000  
DDR16 [R/W]  
00000000  
DDR17 [R/W]  
00000000  
DDR18 [R/W]  
00000000  
H
Register  
DDR20 [R/W]  
00000000  
DDR21 [R/W]  
00000000  
DDR22 [R/W]  
00000000  
DDR23 [R/W]  
00000000  
000D54  
000D58  
H
DDR24 [R/W]  
00000000  
DDR25 [R/W]  
00000000  
DDR26 [R/W]  
00000000  
DDR27 [R/W]  
00000000  
H
DDR28 [R/W]  
00000000  
DDR29 [R/W]  
00000000  
DDR30 [R/W]  
00000000  
DDR31 [R/W]  
00000000  
000D5C  
H
DDR32 [R/W]  
00000000  
DDR33 [R/W]  
00000000  
DDR34 [R/W]  
00000000  
DDR35 [R/W]  
00000000  
000D60  
H
000D64  
-
H
reserved  
000D7C  
H
PFR00 [R/W]  
11111111  
PFR01 [R/W]  
11111111  
PFR02 [R/W]  
11111111  
PFR03 [R/W]  
11111111  
000D80  
000D84  
000D88  
H
PFR04 [R/W]  
11111111  
PFR05 [R/W]  
11111111  
PFR06 [R/W]  
11111111  
PFR07 [R/W]  
11111111  
H
H
PFR08 [R/W]  
11111111  
PFR09 [R/W]  
11111111  
PFR10 [R/W]  
11111111  
PFR11 [R/W]  
00000000  
PFR12 [R/W]  
00000000  
PFR13 [R/W]  
00000000  
PFR14 [R/W]  
00000000  
PFR15 [R/W]  
00000000  
000D8C  
000D90  
H
R-bus  
PFR19 [R/W]  
Port Function  
00000000  
PFR16 [R/W]  
00000000  
PFR17 [R/W]  
00000000  
PFR18 [R/W]  
00000000  
H
Register  
PFR20 [R/W]  
00000000  
PFR21 [R/W]  
00000000  
PFR22 [R/W]  
00000000  
PFR23 [R/W]  
00000000  
000D94  
000D98  
H
PFR24 [R/W]  
00000000  
PFR25 [R/W]  
00000000  
PFR26 [R/W]  
00000000  
PFR27 [R/W]  
00000000  
H
PFR28 [R/W]  
00000000  
PFR29 [R/W]  
00000000  
PFR30 [R/W]  
00000000  
PFR31 [R/W]  
00000000  
000D9C  
H
PFR32 [R/W]  
00000000  
PFR33 [R/W]  
00000000  
PFR34 [R/W]  
00000000  
PFR35 [R/W]  
00000000  
000DA0  
H
43  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
000DA4  
-
H
reserved  
000DBC  
H
H
EPFR00 [R/W]  
00000000  
EPFR01 [R/W]  
00000000  
EPFR02 [R/W]  
00000000  
EPFR03 [R/W]  
00000000  
000DC0  
000DC4  
000DC8  
EPFR04 [R/W]  
00000000  
EPFR05 [R/W]  
00000000  
EPFR06 [R/W]  
00000000  
EPFR07 [R/W]  
00000000  
H
H
EPFR08 [R/W]  
00000000  
EPFR09 [R/W]  
00000000  
EPFR10 [R/W]  
00000000  
EPFR11 [R/W]  
00000000  
EPFR12 [R/W]  
00000000  
EPFR13 [R/W]  
00000000  
EPFR14 [R/W]  
00000000  
EPFR15 [R/W]  
00000000  
000DCC  
000DD0  
H
R-bus Port  
Extra Function  
Register  
EPFR16 [R/W]  
00000000  
EPFR17 [R/W]  
00000000  
EPFR18 [R/W]  
00000000  
EPFR19 [R/W]  
00000000  
H
EPFR20 [R/W]  
00000000  
EPFR21 [R/W]  
00000000  
EPFR22 [R/W]  
00000000  
EPFR23 [R/W]  
00000000  
000DD4  
000DD8  
H
EPFR24 [R/W]  
00000000  
EPFR25 [R/W]  
00000000  
EPFR26 [R/W]  
00000000  
EPFR27 [R/W]  
00000000  
H
EPFR28 [R/W]  
00000000  
EPFR29 [R/W]  
00000000  
EPFR30 [R/W]  
00000000  
EPFR31 [R/W]  
00000000  
000DDC  
H
EPFR32 [R/W]  
00000000  
EPFR33 [R/W]  
00000000  
EPFR34 [R/W]  
00000000  
EPFR35 [R/W]  
00000000  
000DE0  
H
000DE4  
-
H
reserved  
000DFC  
H
44  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
PODR00 [R/W]  
00000000  
PODR01 [R/W]  
00000000  
PODR02 [R/W]  
00000000  
PODR03 [R/W]  
00000000  
000E00  
000E04  
000E08  
H
H
H
PODR04 [R/W]  
00000000  
PODR05 [R/W]  
00000000  
PODR06 [R/W]  
00000000  
PODR07 [R/W]  
00000000  
PODR08 [R/W]  
00000000  
PODR09 [R/W]  
00000000  
PODR10 [R/W]  
00000000  
PODR11 [R/W]  
00000000  
PODR12 [R/W]  
00000000  
PODR13 [R/W]  
00000000  
PODR14 [R/W]  
00000000  
PODR15 [R/W]  
000E0C  
H
00000000  
R-bus Port  
PODR16 [R/W]  
00000000  
PODR17 [R/W]  
00000000  
PODR18 [R/W]  
00000000  
PODR19 [R/W]  
00000000  
Output Drive  
Select  
Register  
000E10  
000E14  
000E18  
H
PODR20 [R/W]  
00000000  
PODR21 [R/W]  
00000000  
PODR22 [R/W]  
00000000  
PODR23 [R/W]  
00000000  
H
H
PODR24 [R/W]  
00000000  
PODR25 [R/W]  
00000000  
PODR26 [R/W]  
00000000  
PODR27 [R/W]  
00000000  
PODR28 [R/W]  
00000000  
PODR29 [R/W]  
00000000  
PODR30 [R/W]  
00000000  
PODR31 [R/W]  
00000000  
000E1C  
H
PODR32 [R/W]  
00000000  
PODR33 [R/W]  
00000000  
PODR34 [R/W]  
00000000  
PODR35 [R/W]  
00000000  
000E20  
H
000E24  
-
H
reserved  
000E3C  
H
PILR00 [R/W]  
00000000  
PILR01 [R/W]  
00000000  
PILR02 [R/W]  
00000000  
PILR03 [R/W]  
00000000  
000E40  
000E44  
000E48  
H
PILR04 [R/W]  
00000000  
PILR05 [R/W]  
00000000  
PILR06 [R/W]  
00000000  
PILR07 [R/W]  
00000000  
H
H
PILR08 [R/W]  
00000000  
PILR09 [R/W]  
00000000  
PILR10 [R/W]  
00000000  
PILR11 [R/W]  
00000000  
PILR12 [R/W]  
00000000  
PILR13 [R/W]  
00000000  
PILR14 [R/W]  
00000000  
PILR15 [R/W]  
00000000  
000E4C  
H
R-bus Port  
Input Level  
Select  
PILR16 [R/W]  
00000000  
PILR17 [R/W]  
00000000  
PILR18 [R/W]  
00000000  
PILR19 [R/W]  
00000000  
000E50  
000E54  
000E58  
H
Register  
PILR20 [R/W]  
00000000  
PILR21 [R/W]  
00000000  
PILR22 [R/W]  
00000000  
PILR23 [R/W]  
00000000  
H
H
PILR24 [R/W]  
00000000  
PILR25 [R/W]  
00000000  
PILR26 [R/W]  
00000000  
PILR27 [R/W]  
00000000  
PILR28 [R/W]  
00000000  
PILR29 [R/W]  
00000000  
PILR30 [R/W]  
00000000  
PILR31 [R/W]  
00000000  
000E5C  
H
PILR32 [R/W]  
00000000  
PILR33 [R/W]  
00000000  
PILR34 [R/W]  
00000000  
PILR35 [R/W]  
00000000  
000E60  
H
45  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
000E64  
-
H
reserved  
000E7C  
H
EPILR00 [R/W]  
00000000  
EPILR01 [R/W]  
00000000  
EPILR02 [R/W]  
00000000  
EPILR03 [R/W]  
00000000  
000E80  
000E84  
000E88  
H
EPILR04 [R/W]  
00000000  
EPILR05 [R/W]  
00000000  
EPILR06 [R/W]  
00000000  
EPILR07 [R/W]  
00000000  
H
H
EPILR08 [R/W]  
00000000  
EPILR09 [R/W]  
00000000  
EPILR10 [R/W]  
00000000  
EPILR11 [R/W]  
00000000  
EPILR12 [R/W]  
00000000  
EPILR13 [R/W]  
00000000  
EPILR14 [R/W]  
00000000  
EPILR15 [R/W]  
00000000  
000E8C  
H
R-bus Port  
Extra Input  
Level Select  
Register  
EPILR16 [R/W]  
00000000  
EPILR17 [R/W]  
00000000  
EPILR18 [R/W]  
00000000  
EPILR19 [R/W]  
00000000  
000E90  
000E94  
000E98  
H
EPILR20 [R/W]  
00000000  
EPILR21 [R/W]  
00000000  
EPILR22 [R/W]  
00000000  
EPILR23 [R/W]  
00000000  
H
H
EPILR24 [R/W]  
00000000  
EPILR25 [R/W]  
00000000  
EPILR26 [R/W]  
00000000  
EPILR27 [R/W]  
00000000  
EPILR28 [R/W]  
00000000  
EPILR29 [R/W]  
00000000  
EPILR30 [R/W]  
00000000  
EPILR31 [R/W]  
00000000  
000E9C  
H
EPILR32 [R/W]  
00000000  
EPILR33 [R/W]  
00000000  
EPILR34 [R/W]  
00000000  
EPILR35 [R/W]  
00000000  
000EA0  
H
000EA4  
-
H
reserved  
000EBC  
H
46  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
PPER00 [R/W]  
00000000  
PPER01 [R/W]  
00000000  
PPER02 [R/W]  
00000000  
PPER03 [R/W]  
00000000  
000EC0  
000EC4  
000EC8  
H
H
H
PPER04 [R/W]  
00000000  
PPER05 [R/W]  
00000000  
PPER06 [R/W]  
00000000  
PPER07 [R/W]  
00000000  
PPER08 [R/W]  
00000000  
PPER09 [R/W]  
00000000  
PPER10 [R/W]  
00000000  
PPER11 [R/W]  
00000000  
PPER12 [R/W]  
00000000  
PPER13 [R/W]  
00000000  
PPER14 [R/W]  
00000000  
PPER15 [R/W]  
00000000  
000ECC  
H
R-bus Port  
PPER16 [R/W]  
00000000  
PPER17 [R/W]  
00000000  
PPER18 [R/W]  
00000000  
PPER19 [R/W]  
00000000  
Pull-Up/Down  
Enable  
Register  
000ED0  
000ED4  
000ED8  
H
PPER20 [R/W]  
00000000  
PPER21 [R/W]  
00000000  
PPER22 [R/W]  
00000000  
PPER23 [R/W]  
00000000  
H
H
PPER24 [R/W]  
00000000  
PPER25 [R/W]  
00000000  
PPER26 [R/W]  
00000000  
PPER27 [R/W]  
00000000  
PPER28 [R/W]  
00000000  
PPER29 [R/W]  
00000000  
PPER30 [R/W]  
00000000  
PPER31 [R/W]  
00000000  
000EDC  
H
PPER32 [R/W]  
00000000  
PPER33 [R/W]  
00000000  
PPER34 [R/W]  
00000000  
PPER35 [R/W]  
00000000  
000EE0  
H
000EE4  
-
H
reserved  
000EFC  
H
PPCR00 [R/W]  
11111111  
PPCR01 [R/W]  
11111111  
PPCR02 [R/W]  
11111111  
PPCR03 [R/W]  
11111111  
000F00  
000F04  
000F08  
H
PPCR04 [R/W]  
11111111  
PPCR05 [R/W]  
11111111  
PPCR06 [R/W]  
11111111  
PPCR07 [R/W]  
11111111  
H
H
PPCR08 [R/W]  
11111111  
PPCR09 [R/W]  
11111111  
PPCR10 [R/W]  
11111111  
PPCR11 [R/W]  
11111111  
PPCR12 [R/W]  
11111111  
PPCR13 [R/W]  
11111111  
PPCR14 [R/W]  
11111111  
PPCR15 [R/W]  
11111111  
000F0C  
H
R-bus Port  
Pull-Up/Down  
Control  
PPCR16 [R/W]  
11111111  
PPCR17 [R/W]  
11111111  
PPCR18 [R/W]  
11111111  
PPCR19 [R/W]  
11111111  
000F10  
000F14  
000F18  
H
Register  
PPCR20 [R/W]  
11111111  
PPCR21 [R/W]  
11111111  
PPCR22 [R/W]  
11111111  
PPCR23 [R/W]  
11111111  
H
H
PPCR24 [R/W]  
11111111  
PPCR25 [R/W]  
11111111  
PPCR26 [R/W]  
11111111  
PPCR27 [R/W]  
11111111  
PPCR28 [R/W]  
11111111  
PPCR29 [R/W]  
11111111  
PPCR30 [R/W]  
11111111  
PPCR31 [R/W]  
11111111  
000F1C  
H
PPCR32 [R/W]  
11111111  
PPCR33 [R/W]  
11111111  
PPCR34 [R/W]  
11111111  
PPCR35 [R/W]  
11111111  
000F20  
H
47  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
000F24  
-
H
reserved  
000F3C  
H
001000  
001004  
001008  
DMASA0 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
DMADA0 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
H
DMASA1 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
00100C  
DMADA1 [R/W]  
H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
001010  
001014  
001018  
DMASA2 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
DMAC  
DMADA2 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
H
DMASA3 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
00101C  
DMADA3 [R/W]  
H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
001020  
001024  
DMASA4 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
DMADA4 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
H
001028  
-
reserved  
006FFC  
007000  
H
FMCS [R/W]  
01101000  
FCHCR [R/W]  
res.  
H
- - - - - - 00 10000011  
Flash Memory/  
I-Cache  
Control  
FMWT [R/W]  
11111111 11111111  
FMPS [R/W]  
- - - - - 000  
007004  
res.  
H
Register  
FMAC [R]  
007008  
H
00000000 00000000 00000000 00000000  
00700C  
FCHA0 [R/W]  
- - - - - - - - - 0000000 00000000 00000000  
H
I-Cache Non-  
cacheable  
area setting  
Register  
007010  
FCHA1 [R/W]  
- - - - - - - - - 0000000 00000000 00000000  
H
007014  
-
H
reserved  
007FFC  
H
48  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
008000  
-
00BFFC  
H
MB91V460 Boot-ROM size is 4kB : 00B000 - 00BFFC  
(instruction access is 1 waitcycle, data access is 1 waitcycle)  
Boot ROM  
16 kB  
H
H
H
CTRLR0 [R/W]  
00000000 00000001  
STATR0 [R/W]  
00000000 00000000  
00C000  
00C004  
00C008  
H
ERRCNT0 [R]  
00000000 00000000  
BTR0 [R/W]  
00100011 00000001  
H
H
CAN 0  
Control  
Register  
INTR0 [R]  
00000000 00000000  
TESTR0 [R/W]  
00000000 X0000000  
BRPER0 [R/W]  
00000000 00000000  
*2  
00C00C  
CBSYNC0  
H
IF1CREQ0 [R/W]  
00000000 00000001  
IF1CMSK0 [R/W]  
00000000 00000000  
00C010  
00C014  
00C018  
H
IF1MSK20 [R/W]  
11111111 11111111  
IF1MSK10 [R/W]  
11111111 11111111  
H
H
IF1ARB20 [R/W]  
00000000 00000000  
IF1ARB10 [R/W]  
00000000 00000000  
IF1MCTR0 [R/W]  
00000000 00000000  
00C01C  
res.  
H
IF1DTA10 [R/W]  
00000000 00000000  
IF1DTA20 [R/W]  
00000000 00000000  
00C020  
00C024  
H
CAN 0  
IF 1 Register  
IF1DTB10 [R/W]  
00000000 00000000  
IF1DTB20 [R/W]  
00000000 00000000  
H
H
00C028  
-
reserved  
00C02C  
H
IF1DTA20 [R/W]  
00000000 00000000  
IF1DTA10 [R/W]  
00000000 00000000  
00C030  
00C034  
H
IF1DTB20 [R/W]  
00000000 00000000  
IF1DTB10 [R/W]  
00000000 00000000  
H
H
00C038  
-
reserved  
00C03C  
H
49  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
IF2CREQ0 [R/W]  
00000000 00000001  
IF2CMSK0 [R/W]  
00000000 00000000  
00C040  
00C044  
00C048  
H
H
H
IF2MSK20 [R/W]  
11111111 11111111  
IF2MSK10 [R/W]  
11111111 11111111  
IF2ARB20 [R/W]  
00000000 00000000  
IF2ARB10 [R/W]  
00000000 00000000  
IF2MCTR0 [R/W]  
00000000 00000000  
00C04C  
res.  
H
IF2DTA10 [R/W]  
00000000 00000000  
IF2DTA20 [R/W]  
00000000 00000000  
00C050  
00C054  
H
CAN 0  
IF 2 Register  
IF2DTB10 [R/W]  
00000000 00000000  
IF2DTB20 [R/W]  
00000000 00000000  
H
H
00C058  
-
reserved  
00C05C  
H
IF2DTA20 [R/W]  
00000000 00000000  
IF2DTA10 [R/W]  
00000000 00000000  
00C060  
00C064  
H
IF2DTB20 [R/W]  
00000000 00000000  
IF2DTB10 [R/W]  
00000000 00000000  
H
H
00C068  
-
reserved  
00C07C  
H
50  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
TREQR20 [R]  
00000000 00000000  
TREQR10 [R]  
00000000 00000000  
00C080  
00C084  
00C088  
H
H
H
TREQR40 [R]  
00000000 00000000  
TREQR30 [R]  
00000000 00000000  
TREQR60 [R]  
00000000 00000000  
TREQR50 [R]  
00000000 00000000  
TREQR80 [R]  
00000000 00000000  
TREQR70 [R]  
00000000 00000000  
00C08C  
H
NEWDT20 [R]  
00000000 00000000  
NEWDT10 [R]  
00000000 00000000  
00C090  
00C094  
00C098  
H
NEWDT40 [R]  
00000000 00000000  
NEWDT30 [R]  
00000000 00000000  
H
H
NEWDT60 [R]  
00000000 00000000  
NEWDT50 [R]  
00000000 00000000  
NEWDT80 [R]  
00000000 00000000  
NEWDT70 [R]  
00000000 00000000  
00C09C  
H
H
H
H
INTPND20 [R]  
00000000 00000000  
INTPND10 [R]  
00000000 00000000  
00C0A0  
00C0A4  
00C0A8  
CAN 0  
Status Flags  
INTPND40 [R]  
00000000 00000000  
INTPND30 [R]  
00000000 00000000  
INTPND60 [R]  
00000000 00000000  
INTPND50 [R]  
00000000 00000000  
INTPND80 [R]  
00000000 00000000  
INTPND70 [R]  
00000000 00000000  
00C0AC  
H
H
H
H
MSGVAL20 [R]  
00000000 00000000  
MSGVAL10 [R]  
00000000 00000000  
00C0B0  
00C0B4  
00C0B8  
MSGVAL40 [R]  
00000000 00000000  
MSGVAL30 [R]  
00000000 00000000  
MSGVAL60 [R]  
00000000 00000000  
MSGVAL50 [R]  
00000000 00000000  
MSGVAL80 [R]  
00000000 00000000  
MSGVAL70 [R]  
00000000 00000000  
00C0BC  
H
00C0C0  
-
H
reserved  
00C0FC  
H
51  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
CTRLR1 [R/W]  
00000000 00000001  
STATR1 [R/W]  
00000000 00000000  
00C100  
00C104  
00C108  
H
H
H
ERRCNT1 [R]  
00000000 00000000  
BTR1 [R/W]  
00100011 00000001  
CAN 1  
Control  
Register  
INTR1 [R]  
00000000 00000000  
TESTR1 [R/W]  
00000000 X0000000  
BRPER1 [R/W]  
00000000 00000000  
*2  
00C10C  
CBSYNC1  
H
IF1CREQ1 [R/W]  
00000000 00000001  
IF1CMSK1 [R/W]  
00000000 00000000  
00C110  
00C114  
00C118  
H
IF1MSK21 [R/W]  
11111111 11111111  
IF1MSK11 [R/W]  
11111111 11111111  
H
H
IF1ARB21 [R/W]  
00000000 00000000  
IF1ARB11 [R/W]  
00000000 00000000  
IF1MCTR1 [R/W]  
00000000 00000000  
00C11C  
res.  
H
IF1DTA11 [R/W]  
00000000 00000000  
IF1DTA21 [R/W]  
00000000 00000000  
00C120  
00C124  
H
CAN 1  
IF 1 Register  
IF1DTB11 [R/W]  
00000000 00000000  
IF1DTB21 [R/W]  
00000000 00000000  
H
H
00C128  
-
reserved  
00C12C  
H
IF1DTA21 [R/W]  
00000000 00000000  
IF1DTA11 [R/W]  
00000000 00000000  
00C130  
00C134  
H
IF1DTB21 [R/W]  
00000000 00000000  
IF1DTB11 [R/W]  
00000000 00000000  
H
H
00C138  
-
reserved  
00C13C  
H
52  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
IF2CREQ1 [R/W]  
00000000 00000001  
IF2CMSK1 [R/W]  
00000000 00000000  
00C140  
00C144  
00C148  
H
H
H
IF2MSK21 [R/W]  
11111111 11111111  
IF2MSK11 [R/W]  
11111111 11111111  
IF2ARB21 [R/W]  
00000000 00000000  
IF2ARB11 [R/W]  
00000000 00000000  
IF2MCTR1 [R/W]  
00000000 00000000  
00C14C  
res.  
H
IF2DTA11 [R/W]  
00000000 00000000  
IF2DTA21 [R/W]  
00000000 00000000  
00C150  
00C154  
H
CAN 1  
IF 2 Register  
IF2DTB11 [R/W]  
00000000 00000000  
IF2DTB21 [R/W]  
00000000 00000000  
H
H
00C158  
-
reserved  
00C15C  
H
IF2DTA21 [R/W]  
00000000 00000000  
IF2DTA11 [R/W]  
00000000 00000000  
00C160  
00C164  
H
IF2DTB21 [R/W]  
00000000 00000000  
IF2DTB11 [R/W]  
00000000 00000000  
H
H
00C168  
-
reserved  
00C17C  
H
53  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
TREQR21 [R]  
00000000 00000000  
TREQR11 [R]  
00000000 00000000  
00C180  
00C184  
00C188  
H
H
H
TREQR41 [R]  
00000000 00000000  
TREQR31 [R]  
00000000 00000000  
TREQR61 [R]  
00000000 00000000  
TREQR51 [R]  
00000000 00000000  
TREQR81 [R]  
00000000 00000000  
TREQR71 [R]  
00000000 00000000  
00C18C  
H
NEWDT21 [R]  
00000000 00000000  
NEWDT11 [R]  
00000000 00000000  
00C190  
00C194  
00C198  
H
NEWDT41 [R]  
00000000 00000000  
NEWDT31 [R]  
00000000 00000000  
H
H
NEWDT61 [R]  
00000000 00000000  
NEWDT51 [R]  
00000000 00000000  
NEWDT81 [R]  
00000000 00000000  
NEWDT71 [R]  
00000000 00000000  
00C19C  
H
H
H
H
INTPND21 [R]  
00000000 00000000  
INTPND11 [R]  
00000000 00000000  
00C1A0  
00C1A4  
00C1A8  
CAN 1  
Status Flags  
INTPND41 [R]  
00000000 00000000  
INTPND31 [R]  
00000000 00000000  
INTPND61 [R]  
00000000 00000000  
INTPND51 [R]  
00000000 00000000  
INTPND81 [R]  
00000000 00000000  
INTPND71 [R]  
00000000 00000000  
00C1AC  
H
H
H
H
MSGVAL21 [R]  
00000000 00000000  
MSGVAL11 [R]  
00000000 00000000  
00C1B0  
00C1B4  
00C1B8  
MSGVAL41 [R]  
00000000 00000000  
MSGVAL31 [R]  
00000000 00000000  
MSGVAL61 [R]  
00000000 00000000  
MSGVAL51 [R]  
00000000 00000000  
MSGVAL81 [R]  
00000000 00000000  
MSGVAL71 [R]  
00000000 00000000  
00C1BC  
H
00C1C0  
-
H
reserved  
00C1FC  
H
54  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
CTRLR2 [R/W]  
00000000 00000001  
STATR2 [R/W]  
00000000 00000000  
00C200  
00C204  
00C208  
H
H
H
ERRCNT2 [R]  
00000000 00000000  
BTR2 [R/W]  
00100011 00000001  
CAN 2  
Control  
Register  
INTR2 [R]  
00000000 00000000  
TESTR2 [R/W]  
00000000 X0000000  
BRPER2 [R/W]  
00000000 00000000  
*2  
00C20C  
CBSYNC2  
H
IF1CREQ2 [R/W]  
00000000 00000001  
IF1CMSK2 [R/W]  
00000000 00000000  
00C210  
00C214  
00C218  
H
IF1MSK22 [R/W]  
11111111 11111111  
IF1MSK12 [R/W]  
11111111 11111111  
H
H
IF1ARB22 [R/W]  
00000000 00000000  
IF1ARB12 [R/W]  
00000000 00000000  
IF1MCTR2 [R/W]  
00000000 00000000  
00C21C  
res.  
H
IF1DTA12 [R/W]  
00000000 00000000  
IF1DTA22 [R/W]  
00000000 00000000  
00C220  
00C224  
H
CAN 2  
IF 1 Register  
IF1DTB12 [R/W]  
00000000 00000000  
IF1DTB22 [R/W]  
00000000 00000000  
H
H
00C228  
-
reserved  
00C22C  
H
IF1DTA22 [R/W]  
00000000 00000000  
IF1DTA12 [R/W]  
00000000 00000000  
00C230  
00C234  
H
IF1DTB22 [R/W]  
00000000 00000000  
IF1DTB12 [R/W]  
00000000 00000000  
H
H
00C238  
-
reserved  
00C23C  
H
55  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
IF2CREQ2 [R/W]  
00000000 00000001  
IF2CMSK2 [R/W]  
00000000 00000000  
00C240  
00C244  
00C248  
H
H
H
IF2MSK22 [R/W]  
11111111 11111111  
IF2MSK12 [R/W]  
11111111 11111111  
IF2ARB22 [R/W]  
00000000 00000000  
IF2ARB12 [R/W]  
00000000 00000000  
IF2MCTR2 [R/W]  
00000000 00000000  
00C24C  
res.  
H
IF2DTA12 [R/W]  
00000000 00000000  
IF2DTA22 [R/W]  
00000000 00000000  
00C250  
00C254  
H
CAN 2  
IF 2 Register  
IF2DTB12 [R/W]  
00000000 00000000  
IF2DTB22 [R/W]  
00000000 00000000  
H
H
00C258  
-
reserved  
00C25C  
H
IF2DTA22 [R/W]  
00000000 00000000  
IF2DTA12 [R/W]  
00000000 00000000  
00C260  
00C264  
H
IF2DTB22 [R/W]  
00000000 00000000  
IF2DTB12 [R/W]  
00000000 00000000  
H
H
00C268  
-
reserved  
00C27C  
H
56  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
TREQR22 [R]  
00000000 00000000  
TREQR12 [R]  
00000000 00000000  
00C280  
00C284  
00C288  
H
H
H
TREQR42 [R]  
00000000 00000000  
TREQR32 [R]  
00000000 00000000  
TREQR62 [R]  
00000000 00000000  
TREQR52 [R]  
00000000 00000000  
TREQR82 [R]  
00000000 00000000  
TREQR72 [R]  
00000000 00000000  
00C28C  
H
NEWDT22 [R]  
00000000 00000000  
NEWDT12 [R]  
00000000 00000000  
00C290  
00C294  
00C298  
H
NEWDT42 [R]  
00000000 00000000  
NEWDT32 [R]  
00000000 00000000  
H
H
NEWDT62 [R]  
00000000 00000000  
NEWDT52 [R]  
00000000 00000000  
NEWDT82 [R]  
00000000 00000000  
NEWDT72 [R]  
00000000 00000000  
00C29C  
H
H
H
H
INTPND22 [R]  
00000000 00000000  
INTPND12 [R]  
00000000 00000000  
00C2A0  
00C2A4  
00C2A8  
CAN 2  
Status Flags  
INTPND42 [R]  
00000000 00000000  
INTPND32 [R]  
00000000 00000000  
INTPND62 [R]  
00000000 00000000  
INTPND52 [R]  
00000000 00000000  
INTPND82 [R]  
00000000 00000000  
INTPND72 [R]  
00000000 00000000  
00C2AC  
H
H
H
H
MSGVAL22 [R]  
00000000 00000000  
MSGVAL12 [R]  
00000000 00000000  
00C2B0  
00C2B4  
00C2B8  
MSGVAL42 [R]  
00000000 00000000  
MSGVAL32 [R]  
00000000 00000000  
MSGVAL62 [R]  
00000000 00000000  
MSGVAL52 [R]  
00000000 00000000  
MSGVAL82 [R]  
00000000 00000000  
MSGVAL72 [R]  
00000000 00000000  
00C2BC  
H
00C2C0  
-
H
reserved  
00C2FC  
H
57  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
CTRLR3 [R/W]  
00000000 00000001  
STATR3 [R/W]  
00000000 00000000  
00C300  
00C304  
00C308  
H
H
H
ERRCNT3 [R]  
00000000 00000000  
BTR3 [R/W]  
00100011 00000001  
CAN 3  
Control  
Register  
INTR3 [R]  
00000000 00000000  
TESTR3 [R/W]  
00000000 X0000000  
BRPER3 [R/W]  
00000000 00000000  
*2  
00C30C  
CBSYNC3  
H
IF1CREQ3 [R/W]  
00000000 00000001  
IF1CMSK3 [R/W]  
00000000 00000000  
00C310  
00C314  
00C318  
H
IF1MSK23 [R/W]  
11111111 11111111  
IF1MSK13 [R/W]  
11111111 11111111  
H
H
IF1ARB23 [R/W]  
00000000 00000000  
IF1ARB13 [R/W]  
00000000 00000000  
IF1MCTR3 [R/W]  
00000000 00000000  
00C31C  
res.  
H
IF1DTA13 [R/W]  
00000000 00000000  
IF1DTA23 [R/W]  
00000000 00000000  
00C320  
00C324  
H
CAN 3  
IF 1 Register  
IF1DTB13 [R/W]  
00000000 00000000  
IF1DTB23 [R/W]  
00000000 00000000  
H
H
00C328  
-
reserved  
00C32C  
H
IF1DTA23 [R/W]  
00000000 00000000  
IF1DTA13 [R/W]  
00000000 00000000  
00C330  
00C334  
H
IF1DTB23 [R/W]  
00000000 00000000  
IF1DTB13 [R/W]  
00000000 00000000  
H
H
00C338  
-
reserved  
00C33C  
H
58  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
IF2CREQ3 [R/W]  
00000000 00000001  
IF2CMSK3 [R/W]  
00000000 00000000  
00C340  
00C344  
00C348  
H
H
H
IF2MSK23 [R/W]  
11111111 11111111  
IF2MSK13 [R/W]  
11111111 11111111  
IF2ARB23 [R/W]  
00000000 00000000  
IF2ARB13 [R/W]  
00000000 00000000  
IF2MCTR3 [R/W]  
00000000 00000000  
00C34C  
res.  
H
IF2DTA13 [R/W]  
00000000 00000000  
IF2DTA23 [R/W]  
00000000 00000000  
00C350  
00C354  
H
CAN 3  
IF 2 Register  
IF2DTB13 [R/W]  
00000000 00000000  
IF2DTB23 [R/W]  
00000000 00000000  
H
H
00C358  
-
reserved  
00C35C  
H
IF2DTA23 [R/W]  
00000000 00000000  
IF2DTA13 [R/W]  
00000000 00000000  
00C360  
00C364  
H
IF2DTB23 [R/W]  
00000000 00000000  
IF2DTB13 [R/W]  
00000000 00000000  
H
H
00C368  
-
reserved  
00C37C  
H
59  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
TREQR23 [R]  
00000000 00000000  
TREQR13 [R]  
00000000 00000000  
00C380  
00C384  
00C388  
H
H
H
TREQR43 [R]  
00000000 00000000  
TREQR33 [R]  
00000000 00000000  
TREQR63 [R]  
00000000 00000000  
TREQR53 [R]  
00000000 00000000  
TREQR83 [R]  
00000000 00000000  
TREQR73 [R]  
00000000 00000000  
00C38C  
H
NEWDT23 [R]  
00000000 00000000  
NEWDT13 [R]  
00000000 00000000  
00C390  
00C394  
00C398  
H
NEWDT43 [R]  
00000000 00000000  
NEWDT33 [R]  
00000000 00000000  
H
H
NEWDT63 [R]  
00000000 00000000  
NEWDT53 [R]  
00000000 00000000  
NEWDT83 [R]  
00000000 00000000  
NEWDT73 [R]  
00000000 00000000  
00C39C  
H
H
H
H
INTPND23 [R]  
00000000 00000000  
INTPND13 [R]  
00000000 00000000  
00C3A0  
00C3A4  
00C3A8  
CAN 3  
Status Flags  
INTPND43 [R]  
00000000 00000000  
INTPND33 [R]  
00000000 00000000  
INTPND63 [R]  
00000000 00000000  
INTPND53 [R]  
00000000 00000000  
INTPND83 [R]  
00000000 00000000  
INTPND73 [R]  
00000000 00000000  
00C3AC  
H
H
H
H
MSGVAL23 [R]  
00000000 00000000  
MSGVAL13 [R]  
00000000 00000000  
00C3B0  
00C3B4  
00C3B8  
MSGVAL43 [R]  
00000000 00000000  
MSGVAL33 [R]  
00000000 00000000  
MSGVAL63 [R]  
00000000 00000000  
MSGVAL53 [R]  
00000000 00000000  
MSGVAL83 [R]  
00000000 00000000  
MSGVAL73 [R]  
00000000 00000000  
00C3BC  
H
00C3C0  
-
H
reserved  
00C3FC  
H
60  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
CTRLR4 [R/W]  
00000000 00000001  
STATR4 [R/W]  
00000000 00000000  
00C400  
00C404  
00C408  
H
H
H
ERRCNT4 [R]  
00000000 00000000  
BTR4 [R/W]  
00100011 00000001  
CAN 4  
Control  
Register  
INTR4 [R]  
00000000 00000000  
TESTR4 [R/W]  
00000000 X0000000  
BRPER4 [R/W]  
00000000 00000000  
*2  
00C40C  
CBSYNC4  
H
IF1CREQ4 [R/W]  
00000000 00000001  
IF1CMSK4 [R/W]  
00000000 00000000  
00C410  
00C414  
00C418  
H
IF1MSK24 [R/W]  
11111111 11111111  
IF1MSK14 [R/W]  
11111111 11111111  
H
H
IF1ARB24 [R/W]  
00000000 00000000  
IF1ARB14 [R/W]  
00000000 00000000  
IF1MCTR4 [R/W]  
00000000 00000000  
00C41C  
res.  
H
IF1DTA14 [R/W]  
00000000 00000000  
IF1DTA24 [R/W]  
00000000 00000000  
00C420  
00C424  
H
CAN 4  
IF 1 Register  
IF1DTB14 [R/W]  
00000000 00000000  
IF1DTB24 [R/W]  
00000000 00000000  
H
H
00C428  
-
reserved  
00C42C  
H
IF1DTA24 [R/W]  
00000000 00000000  
IF1DTA14 [R/W]  
00000000 00000000  
00C430  
00C434  
H
IF1DTB24 [R/W]  
00000000 00000000  
IF1DTB14 [R/W]  
00000000 00000000  
H
H
00C438  
-
reserved  
00C43C  
H
61  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
IF2CREQ4 [R/W]  
00000000 00000001  
IF2CMSK4 [R/W]  
00000000 00000000  
00C440  
00C444  
00C448  
H
H
H
IF2MSK24 [R/W]  
11111111 11111111  
IF2MSK14 [R/W]  
11111111 11111111  
IF2ARB24 [R/W]  
00000000 00000000  
IF2ARB14 [R/W]  
00000000 00000000  
IF2MCTR4 [R/W]  
00000000 00000000  
00C44C  
res.  
H
IF2DTA14 [R/W]  
00000000 00000000  
IF2DTA24 [R/W]  
00000000 00000000  
00C450  
00C454  
H
CAN 4  
IF 2 Register  
IF2DTB14 [R/W]  
00000000 00000000  
IF2DTB24 [R/W]  
00000000 00000000  
H
H
00C458  
-
reserved  
00C45C  
H
IF2DTA24 [R/W]  
00000000 00000000  
IF2DTA14 [R/W]  
00000000 00000000  
00C460  
00C464  
H
IF2DTB24 [R/W]  
00000000 00000000  
IF2DTB14 [R/W]  
00000000 00000000  
H
H
00C468  
-
reserved  
00C47C  
H
62  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
TREQR24 [R]  
00000000 00000000  
TREQR14 [R]  
00000000 00000000  
00C480  
00C484  
00C488  
H
H
H
TREQR44 [R]  
00000000 00000000  
TREQR34 [R]  
00000000 00000000  
TREQR64 [R]  
00000000 00000000  
TREQR54 [R]  
00000000 00000000  
TREQR84 [R]  
00000000 00000000  
TREQR74 [R]  
00000000 00000000  
00C48C  
H
NEWDT24 [R]  
00000000 00000000  
NEWDT14 [R]  
00000000 00000000  
00C490  
00C494  
00C498  
H
NEWDT44 [R]  
00000000 00000000  
NEWDT34 [R]  
00000000 00000000  
H
H
NEWDT64 [R]  
00000000 00000000  
NEWDT54 [R]  
00000000 00000000  
NEWDT84 [R]  
00000000 00000000  
NEWDT74 [R]  
00000000 00000000  
00C49C  
H
H
H
H
INTPND24 [R]  
00000000 00000000  
INTPND14 [R]  
00000000 00000000  
00C4A0  
00C4A4  
00C4A8  
CAN 4  
Status Flags  
INTPND44 [R]  
00000000 00000000  
INTPND34 [R]  
00000000 00000000  
INTPND64 [R]  
00000000 00000000  
INTPND54 [R]  
00000000 00000000  
INTPND84 [R]  
00000000 00000000  
INTPND74 [R]  
00000000 00000000  
00C4AC  
H
H
H
H
MSGVAL24 [R]  
00000000 00000000  
MSGVAL14 [R]  
00000000 00000000  
00C4B0  
00C4B4  
00C4B8  
MSGVAL44 [R]  
00000000 00000000  
MSGVAL34 [R]  
00000000 00000000  
MSGVAL64 [R]  
00000000 00000000  
MSGVAL54 [R]  
00000000 00000000  
MSGVAL84 [R]  
00000000 00000000  
MSGVAL74 [R]  
00000000 00000000  
00C4BC  
H
00C4C0  
-
H
reserved  
00C4FC  
H
63  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
CTRLR5 [R/W]  
00000000 00000001  
STATR5 [R/W]  
00000000 00000000  
00C500  
00C504  
00C508  
H
H
H
ERRCNT5 [R]  
00000000 00000000  
BTR5 [R/W]  
00100011 00000001  
CAN 5  
Control  
Register  
INTR5 [R]  
00000000 00000000  
TESTR5 [R/W]  
00000000 X0000000  
BRPER5 [R/W]  
00000000 00000000  
*2  
00C50C  
CBSYNC5  
H
IF1CREQ5 [R/W]  
00000000 00000001  
IF1CMSK5 [R/W]  
00000000 00000000  
00C510  
00C514  
00C518  
H
IF1MSK25 [R/W]  
11111111 11111111  
IF1MSK15 [R/W]  
11111111 11111111  
H
H
IF1ARB25 [R/W]  
00000000 00000000  
IF1ARB15 [R/W]  
00000000 00000000  
IF1MCTR5 [R/W]  
00000000 00000000  
00C51C  
res.  
H
IF1DTA15 [R/W]  
00000000 00000000  
IF1DTA25 [R/W]  
00000000 00000000  
00C520  
00C524  
H
CAN 5  
IF 1 Register  
IF1DTB15 [R/W]  
00000000 00000000  
IF1DTB25 [R/W]  
00000000 00000000  
H
H
00C528  
-
reserved  
00C52C  
H
IF1DTA25 [R/W]  
00000000 00000000  
IF1DTA15 [R/W]  
00000000 00000000  
00C530  
00C534  
H
IF1DTB25 [R/W]  
00000000 00000000  
IF1DTB15 [R/W]  
00000000 00000000  
H
H
00C538  
-
reserved  
00C53C  
H
64  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
IF2CREQ5 [R/W]  
00000000 00000001  
IF2CMSK5 [R/W]  
00000000 00000000  
00C540  
00C544  
00C548  
H
H
H
IF2MSK25 [R/W]  
11111111 11111111  
IF2MSK15 [R/W]  
11111111 11111111  
IF2ARB25 [R/W]  
00000000 00000000  
IF2ARB15 [R/W]  
00000000 00000000  
IF2MCTR5 [R/W]  
00000000 00000000  
00C54C  
res.  
H
IF2DTA15 [R/W]  
00000000 00000000  
IF2DTA25 [R/W]  
00000000 00000000  
00C550  
00C554  
H
CAN 5  
IF 2 Register  
IF2DTB15 [R/W]  
00000000 00000000  
IF2DTB25 [R/W]  
00000000 00000000  
H
H
00C558  
-
reserved  
00C55C  
H
IF2DTA25 [R/W]  
00000000 00000000  
IF2DTA15 [R/W]  
00000000 00000000  
00C560  
00C564  
H
IF2DTB25 [R/W]  
00000000 00000000  
IF2DTB15 [R/W]  
00000000 00000000  
H
H
00C568  
-
reserved  
00C57C  
H
65  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
TREQR25 [R]  
00000000 00000000  
TREQR15 [R]  
00000000 00000000  
00C580  
00C584  
00C588  
H
H
H
TREQR45 [R]  
00000000 00000000  
TREQR35 [R]  
00000000 00000000  
TREQR65 [R]  
00000000 00000000  
TREQR55 [R]  
00000000 00000000  
TREQR85 [R]  
00000000 00000000  
TREQR75 [R]  
00000000 00000000  
00C58C  
H
NEWDT25 [R]  
00000000 00000000  
NEWDT15 [R]  
00000000 00000000  
00C590  
00C594  
00C598  
H
NEWDT45 [R]  
00000000 00000000  
NEWDT35 [R]  
00000000 00000000  
H
H
NEWDT65 [R]  
00000000 00000000  
NEWDT55 [R]  
00000000 00000000  
NEWDT85 [R]  
00000000 00000000  
NEWDT75 [R]  
00000000 00000000  
00C59C  
H
H
H
H
CAN 5  
Status Flags  
INTPND25 [R]  
00000000 00000000  
INTPND15 [R]  
00000000 00000000  
00C5A0  
00C5A4  
00C5A8  
INTPND45 [R]  
00000000 00000000  
INTPND35 [R]  
00000000 00000000  
INTPND65 [R]  
00000000 00000000  
INTPND55 [R]  
00000000 00000000  
INTPND85 [R]  
00000000 00000000  
INTPND75 [R]  
00000000 00000000  
00C5AC  
H
H
H
H
MSGVAL25 [R]  
00000000 00000000  
MSGVAL15 [R]  
00000000 00000000  
00C5B0  
00C5B4  
00C5B8  
MSGVAL45 [R]  
00000000 00000000  
MSGVAL35 [R]  
00000000 00000000  
MSGVAL65 [R]  
00000000 00000000  
MSGVAL55 [R]  
00000000 00000000  
MSGVAL85 [R]  
00000000 00000000  
MSGVAL75 [R]  
00000000 00000000  
00C5BC  
H
00C5C0  
-
H
reserved  
00EFFC  
H
66  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
BCTRL [R/W]  
- - - - - - - - - - - - - - - - 11111100 00000000  
00F000  
00F004  
00F008  
H
H
H
BSTAT [R/W]  
- - - - - - - - - - - - - 000 00000000 10 - - 000000  
BIAC [R]  
00000000 00000000 00000000 00000000  
BOAC [R]  
00000000 00000000 00000000 00000000  
00F00C  
H
BIRQ [R/W]  
00000000 00000000 00000000 00000000  
00F010  
H
00F014  
-
H
reserved  
00F01C  
H
BCR0 [R/W]  
- - - - - - - - 00000000 00000000 00000000  
00F020  
00F024  
00F028  
H
EDSU / MPU  
BCR1 [R/W]  
- - - - - - - - 00000000 00000000 00000000  
H
H
BCR2 [R/W]  
- - - - - - - - 00000000 00000000 00000000  
BCR3 [R/W]  
- - - - - - - - 00000000 00000000 00000000  
00F02C  
H
BCR4 [R/W]  
- - - - - - - - 00000000 00000000 00000000  
00F030  
00F034  
00F038  
H
BCR5 [R/W]  
- - - - - - - - 00000000 00000000 00000000  
H
H
BCR6 [R/W]  
- - - - - - - - 00000000 00000000 00000000  
BCR7 [R/W]  
- - - - - - - - 00000000 00000000 00000000  
00F03C  
H
00F040  
-
H
reserved  
00F07C  
H
67  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
BAD0 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
00F080  
00F084  
00F088  
H
H
H
BAD1 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD2 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD3 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
00F08C  
H
BAD4 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
00F090  
00F094  
00F098  
H
BAD5 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
H
BAD6 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD7 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
00F09C  
H
H
H
H
EDSU / MPU  
BAD8 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
00F0A0  
00F0A4  
00F0A8  
BAD9 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD10 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD11 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
00F0AC  
H
H
H
H
BAD12 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
00F0B0  
00F0B4  
00F0B8  
BAD13 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD14 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD15 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
00F0BC  
H
68  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
BAD16 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
00F0C0  
00F0C4  
00F0C8  
H
H
H
BAD17 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD18 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD19 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
00F0CC  
H
BAD20 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
00F0D0  
00F0D4  
00F0D8  
H
BAD21 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
H
BAD22 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD23 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
00F0DC  
H
EDSU / MPU  
BAD24 [R/W]  
00F0E0  
00F0E4  
00F0E8  
H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD25 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
H
BAD26 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD27 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
00F0EC  
H
BAD28 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
00F0F0  
00F0F4  
00F0F8  
H
BAD29 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
H
BAD30 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD31 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
00F0FC  
H
00F100  
-
H
reserved  
00FFFC  
H
69  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
010000  
-
013FFC  
H
Cache TAG way 1  
(010000 - 0107FC )  
H
H
H
H
014000  
-
H
Cache TAG way 2  
(014000 - 0147FC )  
2 way set  
associative  
I-Cache  
H
H
017FFC  
018000  
-
01BFFC  
H
Cache RAM way 1  
(018000 - 0187FC )  
4kB  
H
H
H
01C000  
-
01FFFC  
H
Cache RAM way 2  
(01C000 - 01C7FC )  
H
H
H
70  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
Block  
+0  
+1  
+2  
+3  
020000  
-
02FFFC  
H
MB91V460 D-RAM size is 64kB : 020000 - 02FFFC  
D-RAM  
64 kB  
H
H
(data access is 0 waitcycles)  
H
H
H
H
H
030000  
-
03FFFC  
H
MB91V460 I-/D-RAM size is 64kB : 030000 - 03FFFC  
(instruction access is 0 waitcycles, data access is 1 waitcycle)  
I-/D-RAM  
64 kB  
H
H
040000  
-
H
ROMS00 area (128kB)  
05FFFC  
060000  
-
H
ROMS01 area (128kB)  
ROMS02 area (128kB)  
ROMS03 area (128kB)  
ROMS04 area (128kB)  
07FFFC  
080000  
-
H
09FFFC  
0A0000  
-
H
0BFFFC  
H
0C0000  
-
H
0DFFFC  
H
0E0000  
-
0FFFF4  
H
ROMS05 area (128kB)  
FMV [R]  
H
0FFFF8  
H
06 00 00 00  
Fixed  
H
Reset/Mode  
Vector  
FRV [R]  
00 00 BF F8  
0FFFFC  
H
H
100000  
-
13FFFC  
H
ROMS06 area (256kB)  
ROMS07 area (256kB)  
ROMS08 area (256kB)  
ROMS09 area (256kB)  
H
140000  
-
H
17FFFC  
H
180000  
-
H
1BFFFC  
H
1C0000  
-
H
1FFFFC  
H
71  
Chapter 3 MB91460 Series Basic Information  
2.I/O Map  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
200000  
-
27FFFC  
H
ROMS10 area (512kB)  
ROMS11 area (512kB)  
ROMS12 area (512kB)  
ROMS13 area (512kB)  
ROMS14 area (512kB)  
ROMS15 area (512kB)  
H
280000  
-
H
2FFFFC  
H
H
300000  
-
H
37FFFC  
380000  
-
H
3FFFFC  
H
400000  
-
H
47FFFC  
H
480000  
-
H
4FFFFC  
H
Write operations to address 0FFFF8 and 0FFFFC are not possible. When reading these addresses, the values  
H
H
shown above will be read.  
Notes:  
*1  
Use a read access (byte or halfword) to this address to synchronize the CPU operation (e.g. the interrupt accep-  
tance of the CPU) to a preceding write access to the resources on R-bus (e.g. to an interrupt flag) on following  
addresses (0x0000-0x01FF, 0x0280-0x037F, 0x0400-0x063F and 0x0C00-0x0FFF).  
*2  
Use a read access (byte or halfword) to this address to synchronize the CPU operation (e.g. the interrupt accep-  
tance of the CPU) to a preceding write access to the CANs on D-bus (e.g. to an interrupt flag) on following addresses  
(0xC000-0xFFFF).  
72  
Chapter 3 MB91460 Series Basic Information  
3.Interrupt Vector Table  
3. Interrupt Vector Table  
This section shows the allocation of interrupt and interrupt vector/interrupt register.  
*1  
*2  
Interrupt number  
Interrupt level  
Interrupt vector  
Interrupt  
Hexa-  
decimal  
Setting  
Register  
Register  
address  
Default Vector  
address  
*8  
Decimal  
Offset  
RN  
Reset  
0
1
2
3
4
00  
-
-
-
-
-
-
-
-
-
-
0x3FC  
0x3F8  
0x3F4  
0x3F0  
0x3EC  
0x000FFFFC  
0x000FFFF8  
0x000FFFF4  
0x000FFFF0  
0x000FFFEC  
Mode vector  
01  
System reserved  
System reserved  
System reserved  
CPU supervisor mode  
02  
03  
04  
5
6
7
05  
06  
07  
-
-
-
-
-
-
0x3E8  
0x3E4  
0x3E0  
0x000FFFE8  
0x000FFFE4  
0x000FFFE0  
*6  
(INT #5 instruction)  
Memory Protection excep-  
*6  
tion  
Co-processor  
*5  
fault trap  
Co-processor  
8
08  
09  
0A  
-
-
-
-
-
-
0x3DC  
0x3D8  
0x3D4  
0x000FFFDC  
0x000FFFD8  
0x000FFFD4  
*5  
error trap  
*5  
9
INTE instruction  
Instruction break  
10  
*5  
exception  
*5  
11  
12  
13  
0B  
0C  
0D  
-
-
-
-
-
-
0x3D0  
0x3CC  
0x3C8  
0x000FFFD0  
0x000FFFCC  
0x000FFFC8  
Operand break trap  
*5  
Step trace trap  
*5  
NMI interrupt (tool)  
Undefined instruction  
exception  
14  
0E  
-
-
0x3C4  
0x000FFFC4  
F fixed  
NMI request  
15  
16  
17  
18  
19  
20  
21  
22  
23  
0F  
10  
11  
12  
13  
14  
15  
16  
17  
0x3C0  
0x3BC  
0x3B8  
0x3B4  
0x3B0  
0x3AC  
0x3A8  
0x3A4  
0x3A0  
0x000FFFC0  
0x000FFFBC  
0x000FFFB8  
0x000FFFB4  
0x000FFFB0  
0x000FFFAC  
0x000FFFA8  
0x000FFFA4  
0x000FFFA0  
H
External Interrupt 0  
External Interrupt 1  
External Interrupt 2  
External Interrupt 3  
External Interrupt 4  
External Interrupt 5  
External Interrupt 6  
External Interrupt 7  
0, 16  
1, 17  
2, 18  
3, 19  
20  
ICR00  
ICR01  
ICR02  
ICR03  
0x440  
0x441  
0x442  
0x443  
21  
22  
23  
73  
   
Chapter 3 MB91460 Series Basic Information  
3.Interrupt Vector Table  
External Interrupt 8  
External Interrupt 9  
External Interrupt 10  
External Interrupt 11  
External Interrupt 12  
External Interrupt 13  
External Interrupt 14  
External Interrupt 15  
Reload Timer 0  
Reload Timer 1  
Reload Timer 2  
Reload Timer 3  
Reload Timer 4  
Reload Timer 5  
Reload Timer 6  
Reload Timer 7  
Free Run Timer 0  
Free Run Timer 1  
Free Run Timer 2  
Free Run Timer 3  
Free Run Timer 4  
Free Run Timer 5  
Free Run Timer 6  
Free Run Timer 7  
CAN 0  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
2A  
2B  
2C  
2D  
2E  
2F  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
0x39C  
0x398  
0x394  
0x390  
0x38C  
0x388  
0x384  
0x380  
0x37C  
0x378  
0x374  
0x370  
0x36C  
0x368  
0x364  
0x360  
0x35C  
0x358  
0x354  
0x350  
0x34C  
0x348  
0x344  
0x340  
0x33C  
0x338  
0x334  
0x330  
0x32C  
0x328  
0x324  
0x320  
0x31C  
0x318  
0x000FFF9C  
0x000FFF98  
0x000FFF94  
0x000FFF90  
0x000FFF8C  
0x000FFF88  
0x000FFF84  
0x000FFF80  
0x000FFF7C  
0x000FFF78  
0x000FFF74  
0x000FFF70  
0x000FFF6C  
0x000FFF68  
0x000FFF64  
0x000FFF60  
0x000FFF5C  
0x000FFF58  
0x000FFF54  
0x000FFF50  
0x000FFF4C  
0x000FFF48  
0x000FFF44  
0x000FFF40  
0x000FFF3C  
0x000FFF38  
0x000FFF34  
0x000FFF30  
0x000FFF2C  
0x000FFF28  
0x000FFF24  
0x000FFF20  
0x000FFF1C  
0x000FFF18  
ICR04  
ICR05  
ICR06  
ICR07  
ICR08  
ICR09  
ICR10  
ICR11  
ICR12  
ICR13  
ICR14  
ICR15  
ICR16  
ICR17  
ICR18  
ICR19  
ICR20  
0x444  
0x445  
0x446  
0x447  
0x448  
0x449  
0x44A  
0x44B  
0x44C  
0x44D  
0x44E  
0x44F  
0x450  
0x451  
0x452  
0x453  
0x454  
4, 32  
5, 33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
CAN 1  
CAN 2  
CAN 3  
CAN 4  
CAN 5  
USART (LIN) 0 RX  
USART (LIN) 0 TX  
USART (LIN) 1 RX  
USART (LIN) 1 TX  
6, 48  
7, 49  
8, 50  
9, 51  
74  
Chapter 3 MB91460 Series Basic Information  
3.Interrupt Vector Table  
USART (LIN) 2 RX  
USART (LIN) 2 TX  
USART (LIN) 3 RX  
USART (LIN) 3 TX  
System reserved  
Delayed Interrupt  
58  
59  
60  
61  
62  
63  
64  
3A  
3B  
3C  
3D  
3E  
3F  
40  
0x314  
0x310  
0x30C  
0x308  
0x304  
0x300  
0x2FC  
0x000FFF14  
0x000FFF10  
0x000FFF0C  
0x000FFF08  
0x000FFF04  
0x000FFF00  
0x000FFEFC  
52  
53  
54  
55  
ICR21  
ICR22  
ICR23  
0x455  
0x456  
0x457  
*4  
*3  
System reserved  
(ICR24)  
(0x458)  
*3  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
41  
42  
43  
44  
45  
46  
47  
48  
49  
4A  
4B  
4C  
4D  
4E  
4F  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
5A  
5B  
0x2F8  
0x2F4  
0x2F0  
0x2EC  
0x2E8  
0x2E4  
0x2E0  
0x2DC  
0x2D8  
0x2D4  
0x2D0  
0x2CC  
0x2C8  
0x2C4  
0x2C0  
0x2BC  
0x2B8  
0x2B4  
0x2B0  
0x2AC  
0x2A8  
0x2A4  
0x2A0  
0x29C  
0x298  
0x294  
0x290  
0x000FFEF8  
0x000FFEF4  
0x000FFEF0  
0x000FFEEC  
0x000FFEE8  
0x000FFEE4  
0x000FFEE0  
0x000FFEDC  
0x000FFED8  
0x000FFED4  
0x000FFED0  
0x000FFECC  
0x000FFEC8  
0x000FFEC4  
0x000FFEC0  
0x000FFEBC  
0x000FFEB8  
0x000FFEB4  
0x000FFEB0  
0x000FFEAC  
0x000FFEA8  
0x000FFEA4  
0x000FFEA0  
0x000FFE9C  
0x000FFE98  
0x000FFE94  
0x000FFE90  
System reserved  
USART (LIN, FIFO) 4 RX  
USART (LIN, FIFO) 4 TX  
USART (LIN, FIFO) 5 RX  
USART (LIN, FIFO) 5 TX  
USART (LIN, FIFO) 6 RX  
USART (LIN, FIFO) 6 TX  
USART (LIN, FIFO) 7 RX  
USART (LIN, FIFO) 7 TX  
I2C 0 / I2C 2  
10, 56  
11, 57  
12, 58  
13, 59  
60  
ICR25  
ICR26  
ICR27  
ICR28  
ICR29  
ICR30  
ICR31  
ICR32  
ICR33  
ICR34  
ICR35  
ICR36  
ICR37  
0x459  
0x45A  
0x45B  
0x45C  
0x45D  
0x45E  
0x45F  
0x460  
0x461  
0x462  
0x463  
0x464  
0x465  
61  
62  
63  
I2C 1 / I2C 3  
USART (LIN) 8 RX  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
USART (LIN) 8 TX  
USART (LIN) 9 RX  
USART (LIN) 9 TX  
USART (LIN) 10 RX  
USART (LIN) 10 TX  
USART (LIN) 11 RX  
USART (LIN) 11 TX  
USART (LIN) 12 RX  
USART (LIN) 12 TX  
USART (LIN) 13 RX  
USART (LIN) 13 TX  
USART (LIN) 14 RX  
USART (LIN) 14 TX  
USART (LIN) 15 RX  
USART (LIN) 15 TX  
75  
Chapter 3 MB91460 Series Basic Information  
3.Interrupt Vector Table  
Input Capture 0  
92  
5C  
5D  
5E  
5F  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
6A  
6B  
6C  
6D  
6E  
6F  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
7A  
7B  
7C  
7D  
0x28C  
0x288  
0x284  
0x280  
0x27C  
0x278  
0x274  
0x270  
0x26C  
0x268  
0x264  
0x260  
0x25C  
0x258  
0x254  
0x250  
0x24C  
0x248  
0x244  
0x240  
0x23C  
0x238  
0x234  
0x230  
0x22C  
0x228  
0x224  
0x220  
0x21C  
0x218  
0x214  
0x210  
0x20C  
0x208  
0x000FFE8C  
0x000FFE88  
0x000FFE84  
0x000FFE80  
0x000FFE7C  
0x000FFE78  
0x000FFE74  
0x000FFE70  
0x000FFE6C  
0x000FFE68  
0x000FFE64  
0x000FFE60  
0x000FFE5C  
0x000FFE58  
0x000FFE54  
0x000FFE50  
0x000FFE4C  
0x000FFE48  
0x000FFE44  
0x000FFE40  
0x000FFE3C  
0x000FFE38  
0x000FFE34  
0x000FFE30  
0x000FFE2C  
0x000FFE28  
0x000FFE24  
0x000FFE20  
0x000FFE1C  
0x000FFE18  
0x000FFE14  
0x000FFE10  
0x000FFE0C  
0x000FFE08  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
ICR38  
ICR39  
ICR40  
ICR41  
ICR42  
ICR43  
ICR44  
ICR45  
ICR46  
0x466  
0x467  
0x468  
0x469  
0x46A  
0x46B  
0x46C  
0x46D  
0x46E  
0x46F  
0x470  
0x471  
0x472  
0x473  
0x474  
0x475  
0x476  
Input Capture 1  
93  
Input Capture 2  
94  
Input Capture 3  
95  
Input Capture 4  
96  
Input Capture 5  
97  
Input Capture 6  
98  
Input Capture 7  
99  
Output Compare 0  
Output Compare 1  
Output Compare 2  
Output Compare 3  
Output Compare 4  
Output Compare 5  
Output Compare 6  
Output Compare 7  
Sound Generator  
Pulse Frequ. Modulator  
System reserved  
System reserved  
Prog. Pulse Gen. 0  
Prog. Pulse Gen. 1  
Prog. Pulse Gen. 2  
Prog. Pulse Gen. 3  
Prog. Pulse Gen. 4  
Prog. Pulse Gen. 5  
Prog. Pulse Gen. 6  
Prog. Pulse Gen. 7  
Prog. Pulse Gen. 8  
Prog. Pulse Gen. 9  
Prog. Pulse Gen. 10  
Prog. Pulse Gen. 11  
Prog. Pulse Gen. 12  
Prog. Pulse Gen. 13  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
*4  
ICR47  
ICR48  
ICR49  
ICR50  
ICR51  
ICR52  
ICR53  
ICR54  
15, 96  
97  
98  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
76  
Chapter 3 MB91460 Series Basic Information  
3.Interrupt Vector Table  
Prog. Pulse Gen. 14  
Prog. Pulse Gen. 15  
Up/Down Counter 0  
Up/Down Counter 1  
Up/Down Counter 2  
Up/Down Counter 3  
Real Time Clock  
Calibration Unit  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
7E  
7F  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
8A  
8B  
8C  
8D  
8E  
8F  
90  
0x204  
0x200  
0x1FC  
0x1F8  
0x1F4  
0x1F0  
0x1EC  
0x1E8  
0x1E4  
0x1E0  
0x1DC  
0x1D8  
0x1D4  
0x1D0  
0x1CC  
0x1C8  
0x1C4  
0x1C0  
0x1BC  
0x000FFE04  
0x000FFE00  
0x000FFDFC  
0x000FFDF8  
0x000FFDF4  
0x000FFDF0  
0x000FFDEC  
0x000FFDE8  
0x000FFDE4  
0x000FFDE0  
0x000FFDDC  
0x000FFDD8  
0x000FFDD4  
0x000FFDD0  
0x000FFDCC  
0x000FFDC8  
0x000FFDC4  
0x000FFDC0  
0x000FFDBC  
110  
111  
ICR55  
ICR56  
ICR57  
ICR58  
ICR59  
ICR60  
ICR61  
ICR62  
0x477  
0x478  
0x479  
0x47A  
0x47B  
0x47C  
0x47D  
0x47E  
A/D Converter 0  
-
14, 112  
Alarm Comparator 0  
Alarm Comparator 1  
Low Voltage Detection  
-
Timebase Overflow  
PLL Clock Gear  
DMA Controller  
ICR63  
-
0x47F  
-
Main/Sub OSC stability wait  
*7  
Boot Security vector  
145  
to  
255  
91  
to  
FF  
0x1B8  
to  
0x000  
0x000FFDB8  
to  
0x000FFC00  
Used by the INT  
instruction.  
-
-
Table 3-1 Interrupt Vector Table  
Notes:  
*1  
The ICRs are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is  
provided for each interrupt request.  
*2  
The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table  
base register value (TBR). The TBR specifies the top of the EIT vector table. The addresses listed in the table are  
for the default TBR value (0x000FFC00). The TBR is initialized to this value by a reset. After execution of the inter-  
nal boot ROM TBR is set to 0x000FFC00.  
*3  
Used by REALOS  
*4  
ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0x0C03 : IOS[0])  
System reserved  
Memory Protection Unit (MPU) support  
Only for MB91V460. Please see Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM (Page No.983) for boot  
*5  
*6  
*7  
security vectors used on flash devices.  
*8  
RN resource number used for DMA operation. No number means that this resource interrupt cannot be used to  
trigger a DMA transfer.  
77  
Chapter 3 MB91460 Series Basic Information  
4.Package  
4. Package  
■ BGA-660P-M02 package (BGA660-03EK): MB91V460  
Figure 4-1 External Dimension of BGA660-03EK  
78  
 
Chapter 3 MB91460 Series Basic Information  
5.Pin Assignment Diagram  
5. Pin Assignment Diagram  
■ MB91V460 (BGA660 package)  
Figure 5-1 Pin Assignment Diagram of BGA660-03EK  
79  
 
Chapter 3 MB91460 Series Basic Information  
6.Pin Definitions  
6. Pin Definitions  
CMOS/  
Pull Up/CMOS Hyst/  
I/O  
P00_7  
P00_6  
P00_5  
P00_4  
P00_3  
P00_2  
P00_1  
P00_0  
P01_7  
P01_6  
P01_5  
P01_4  
P01_3  
P01_2  
P01_1  
P01_0  
P02_7  
P02_6  
P02_5  
P02_4  
P02_3  
P02_2  
P02_1  
P02_0  
P03_7  
P03_6  
P03_5  
P03_4  
P03_3  
P03_2  
P03_1  
P03_0  
X1  
Function PFR=1 EPFR=1 Special Type  
Dwn Auto / TTL Input Stop  
Usage  
Output  
AL38  
AJ37  
AJ36  
AJ35  
AH36  
AH35  
AK38  
AJ38  
AH37  
AG37  
AG35  
AG36  
AF35  
AF36  
AH38  
AF37  
AG38  
AE37  
AE36  
AD37  
AD36  
AC37  
AF38  
AE38  
AD35  
AC35  
AB37  
AC36  
AA37  
AB36  
AD38  
AC38  
AB35  
AA36  
AB38  
AA35  
W37  
315  
314  
311  
310  
309  
308  
307  
305  
304  
302  
300  
299  
298  
297  
295  
294  
293  
292  
289  
288  
287  
286  
285  
283  
282  
280  
278  
277  
276  
275  
273  
271  
272  
270  
267  
266  
257  
256  
255  
253  
262  
261  
259  
258  
257  
256  
255  
253  
252  
251  
249  
250  
247  
248  
246  
244  
245  
243  
241  
240  
239  
238  
237  
236  
234  
233  
231  
232  
229  
230  
228  
227  
226  
225  
222  
221  
211  
212  
209  
207  
D31  
D30  
D29  
D28  
D27  
D26  
D25  
D24  
D23  
D22  
D21  
D20  
D19  
D18  
D17  
D16  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D31  
D30  
D29  
D28  
D27  
D26  
D25  
D24  
D23  
D22  
D21  
D20  
D19  
D18  
D17  
D16  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TP04_0 U/D CH / A / TTL  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
no  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
D8  
D8  
D7  
D7  
D6  
D6  
D5  
D5  
D4  
D4  
D3  
D3  
D2  
D2  
D1  
D1  
D0  
D0  
-
-
TO00_1  
TO00_0  
TO01_1  
TO01_0  
TC10_0  
-
-
-
-
-
OSC  
OSC  
OSC  
OSC  
-
X1  
X0  
-
X0  
-
-
-
X1A  
-
-
X1A  
-
-
X0A  
-
-
X0A  
MONCLK  
P04_7  
P04_6  
P04_5  
-
-
MONCLK  
8mA  
V35  
A31  
A30  
A29  
A31  
A30  
A29  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
Stop  
Stop  
Stop  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
V38  
U38  
80  
 
Chapter 3 MB91460 Series Basic Information  
6.Pin Definitions  
V37  
V36  
U37  
U36  
U35  
T35  
T38  
T37  
R38  
R37  
T36  
R36  
P37  
N37  
P38  
N38  
P35  
P36  
N35  
N36  
M37  
L37  
M38  
M35  
L38  
L35  
M36  
L36  
K37  
J37  
252  
251  
250  
249  
248  
246  
243  
242  
241  
240  
239  
237  
236  
234  
233  
231  
230  
229  
228  
227  
226  
224  
221  
220  
219  
218  
217  
215  
214  
212  
211  
209  
208  
207  
206  
205  
202  
200  
199  
197  
196  
195  
194  
193  
192  
208  
205  
206  
203  
204  
202  
200  
199  
198  
197  
196  
195  
194  
193  
192  
190  
189  
188  
187  
186  
185  
184  
182  
181  
180  
179  
178  
177  
176  
175  
174  
172  
171  
170  
169  
168  
167  
165  
164  
163  
162  
161  
160  
159  
158  
P04_4  
P04_3  
P04_2  
P04_1  
P04_0  
P05_7  
P05_6  
P05_5  
P05_4  
P05_3  
P05_2  
P05_1  
P05_0  
P06_7  
P06_6  
P06_5  
P06_4  
P06_3  
P06_2  
P06_1  
P06_0  
P07_7  
P07_6  
P07_5  
P07_4  
P07_3  
P07_2  
P07_1  
P07_0  
P08_7  
P08_6  
P08_5  
P08_4  
P08_3  
P08_2  
P08_1  
P08_0  
P09_7  
P09_6  
P09_5  
P09_4  
P09_3  
P09_2  
P09_1  
P09_0  
A28  
A27  
A26  
A25  
A24  
A23  
A22  
A21  
A20  
A19  
A18  
A17  
A16  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
A28  
A27  
A26  
A25  
A24  
A23  
A22  
A21  
A20  
A19  
A18  
A17  
A16  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
A8  
A8  
A7  
A7  
A6  
A6  
A5  
A5  
A4  
A4  
A3  
A3  
A2  
A2  
A1  
A1  
A0  
A0  
RDY  
BRQ  
RDY  
BRQ  
K38  
J38  
BGRNTX BGRNTX  
K35  
K36  
J35  
RDX  
WRX3  
WRX2  
WRX1  
WRX0  
CSX7  
CSX6  
CSX5  
CSX4  
CSX3  
CSX2  
CSX1  
CSX0  
RDX  
WRX3  
WRX2  
WRX1  
WRX0  
CSX7  
CSX6  
CSX5  
CSX4  
CSX3  
CSX2  
CSX1  
CSX0  
J36  
H37  
G37  
H38  
G38  
H36  
F38  
G35  
E38  
F37  
81  
Chapter 3 MB91460 Series Basic Information  
6.Pin Definitions  
E37  
G36  
F36  
F35  
D38  
E35  
C38  
D37  
E36  
C37  
D36  
B36  
C35  
B35  
C34  
A36  
D34  
A35  
D33  
B34  
C33  
B33  
C32  
A34  
B32  
A33  
B31  
D31  
C31  
D30  
C30  
A32  
B30  
A31  
B29  
C29  
D29  
C28  
D28  
A30  
A29  
B28  
B27  
D27  
C27  
190  
189  
187  
186  
185  
184  
183  
178  
177  
176  
175  
171  
170  
169  
168  
166  
165  
164  
163  
161  
160  
159  
158  
156  
155  
154  
153  
149  
148  
147  
146  
144  
143  
142  
141  
138  
137  
136  
135  
134  
132  
131  
129  
127  
126  
157  
156  
154  
153  
152  
151  
150  
147  
148  
145  
146  
143  
142  
141  
139  
138  
137  
136  
135  
134  
133  
132  
131  
130  
129  
128  
127  
125  
124  
123  
122  
120  
119  
118  
117  
116  
115  
114  
113  
112  
111  
110  
108  
107  
106  
P10_7  
P10_6  
P10_5  
P10_4  
P10_3  
P10_2  
P10_1  
P10_0  
P11_7  
P11_6  
P11_5  
P11_4  
P11_3  
P11_2  
P11_1  
P11_0  
P12_7  
P12_6  
P12_5  
P12_4  
P12_3  
P12_2  
P12_1  
P12_0  
P13_7  
P13_6  
P13_5  
P13_4  
P13_3  
P13_2  
P13_1  
P13_0  
P14_7  
P14_6  
P14_5  
P14_4  
P14_3  
P14_2  
P14_1  
P14_0  
P15_7  
P15_6  
P15_5  
P15_4  
P15_3  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
TP04_0 U/D CH / A / TTL  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
TTL (extbus) 4mA  
MCLKE MCLKE  
MCLKI  
MCLKO MCLKO /MCLKO  
^
MCLKI /MCLKI  
WEX  
BAAX  
ASX  
WEX  
BAAX  
ASX  
^
^
^
SYSCLK SYSCLK /SYSCLK  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IOWRX IOWRX  
IORDX IORDX  
DEOP3 DEOP3  
DEOTX3 DEOTX3 DEOP3  
DACKX3 DACKX3  
DREQ3 DREQ3  
DEOP2 DEOP2  
^
^
-
DEOTX2 DEOTX2 DEOP2  
DACKX2 DACKX2  
DREQ2 DREQ2  
DEOP1 DEOP1  
^
^
-
DEOTX1 DEOTX1 DEOP1  
DACKX1 DACKX1  
DREQ1 DREQ1  
DEOP0 DEOP0  
^
^
-
DEOTX0 DEOTX0 DEOP0  
DACKX0 DACKX0  
DREQ0 DREQ0  
^
^
-
-
-
-
-
-
-
-
-
-
-
-
-
ICU7/TIN7 TIN7 TTG15/7TP00_0 U/D  
ICU6/TIN6 TIN6 TTG14/6TP00_0 U/D  
ICU5/TIN5 TIN5 TTG13/5TP00_0 U/D  
ICU4/TIN4 TIN4 TTG12/4TP00_0 U/D  
ICU3/TIN3 TIN3 TTG11/3TP00_0 U/D  
ICU2/TIN2 TIN2 TTG10/2TP00_0 U/D  
ICU1/TIN1 TIN1 TTG9/1 TP00_0 U/D  
ICU0/TIN0 TIN0 TTG8/0 TP00_0 U/D  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
-
-
-
-
-
-
-
-
-
-
-
-
-
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
OCU7  
OCU6  
OCU5  
OCU4  
OCU3  
TOT7  
TOT6  
TOT5  
TOT4  
TOT3  
-
-
-
-
-
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
82  
Chapter 3 MB91460 Series Basic Information  
6.Pin Definitions  
D26  
C26  
A28  
B26  
A27  
B25  
C25  
B24  
C24  
B23  
A26  
A25  
D24  
D23  
B22  
C23  
B21  
C22  
A24  
D22  
A23  
C21  
A22  
D21  
A21  
D20  
B20  
C20  
A20  
C19  
A19  
D19  
B19  
D18  
A18  
A17  
B18  
C18  
B17  
C17  
D17  
D16  
A16  
B16  
A15  
125  
124  
122  
121  
120  
119  
116  
115  
114  
113  
112  
110  
109  
107  
105  
104  
103  
102  
100  
99  
105  
104  
102  
101  
100  
99  
97  
96  
95  
94  
93  
92  
91  
90  
88  
89  
86  
87  
85  
82  
83  
80  
79  
77  
78  
75  
76  
73  
74  
71  
72  
70  
69  
68  
67  
65  
64  
63  
62  
61  
60  
58  
57  
55  
56  
P15_2  
P15_1  
P15_0  
P16_7  
P16_6  
P16_5  
P16_4  
P16_3  
P16_2  
P16_1  
P16_0  
P17_7  
P17_6  
P17_5  
P17_4  
P17_3  
P17_2  
P17_1  
P17_0  
P18_7  
P18_6  
P18_5  
P18_4  
P18_3  
P18_2  
P18_1  
P18_0  
P19_7  
P19_6  
P19_5  
P19_4  
P19_3  
P19_2  
P19_1  
P19_0  
P20_7  
P20_6  
P20_5  
P20_4  
P20_3  
P20_2  
P20_1  
P20_0  
P21_7  
P21_6  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OCU2  
OCU1  
OCU0  
PPG15  
PPG14  
PPG13  
PPG12  
PPG11  
PPG10  
PPG9  
PPG8  
PPG7  
PPG6  
PPG5  
PPG4  
PPG3  
PPG2  
PPG1  
PPG0  
-
TOT2  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
TOT1  
TOT0  
ATGX  
PFM  
SGO  
SGA  
^
^
^
^
-
-
-
-
-
-
-
-
-
98  
SCK7 ZIN3/CK7  
97  
SOT7  
SIN7  
-
BIN3  
AIN3  
-
94  
93  
92  
SCK6 ZIN2/CK6  
91  
SOT6  
SIN6  
-
BIN2  
90  
AIN2  
89  
-
88  
SCK5  
SOT5  
SIN5  
-
CK5  
87  
^
86  
^
85  
-
84  
SCK4  
SOT4  
SIN4  
-
CK4  
83  
^
^
-
82  
80  
79  
SCK3 ZIN1/CK3  
78  
SOT3  
SIN3  
-
BIN1  
AIN1  
-
77  
76  
75  
SCK2 ZIN0/CK2  
73  
SOT2  
SIN2  
-
BIN0  
AIN0  
-
70  
69  
68  
SCK1  
CK1  
83  
Chapter 3 MB91460 Series Basic Information  
6.Pin Definitions  
B15  
C16  
C15  
B14  
B13  
A14  
A13  
D14  
C14  
D13  
C13  
B12  
B11  
A12  
D12  
A11  
D11  
C12  
C11  
B10  
B9  
67  
66  
53  
54  
P21_5  
P21_4  
P21_3  
P21_2  
P21_1  
P21_0  
P22_7  
P22_6  
P22_5  
P22_4  
P22_3  
P22_2  
P22_1  
P22_0  
P23_7  
P23_6  
P23_5  
P23_4  
P23_3  
P23_2  
P23_1  
P23_0  
P24_7  
P24_6  
P24_5  
P24_4  
P24_3  
P24_2  
P24_1  
P24_0  
P25_7  
P25_6  
P25_5  
P25_4  
P25_3  
P25_2  
P25_1  
P25_0  
P26_7  
P26_6  
P26_5  
P26_4  
P26_3  
P26_2  
P26_1  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SOT1  
SIN1  
^
-
-
-
-
-
-
-
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
-
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
3mA  
3mA  
3mA  
3mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
3mA  
3mA  
3mA  
3mA  
4mA  
4mA  
4mA  
4mA  
30mA  
30mA  
30mA  
30mA  
30mA  
30mA  
30mA  
30mA  
30mA  
30mA  
30mA  
30mA  
30mA  
30mA  
30mA  
^
-
64  
52  
-
-
-
63  
51  
SCK0  
SOT0  
SIN0  
CK0  
-
61  
49  
^
^
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
60  
50  
-
58  
47  
SCL1  
SDA1  
SCL0  
SDA0  
TX5  
TP02_0  
-
-
-
-
I2C  
57  
46  
INT15 TP02_0  
TP02_0  
INT14 TP02_0  
I2C  
56  
45  
-
I2C  
55  
44  
I2C  
54  
42  
-
TP00_0 U/D  
INT13 TP00_0 U/D  
TP00_0 U/D  
INT12 TP00_0 U/D  
TP00_0 U/D  
INT11 TP00_0 U/D  
TP00_0 U/D  
INT10 TP00_0 U/D  
TP00_0 U/D  
INT9 TP00_0 U/D  
TP00_0 U/D  
INT8 TP00_0 U/D  
-
53  
43  
RX5  
-
51  
41  
TX4  
-
-
48  
39  
RX4  
-
47  
38  
TX3  
-
-
46  
37  
RX3  
-
45  
36  
TX2  
-
-
44  
35  
RX2  
-
42  
34  
TX1  
-
-
41  
33  
RX1  
-
39  
32  
TX0  
-
-
A10  
A9  
38  
31  
RX0  
-
36  
29  
INT7  
SCL3 TP02_0  
SDA3 TP02_0  
SCL2 TP02_0  
SDA2 TP02_0  
-
-
-
-
I2C  
D10  
C10  
D9  
35  
28  
INT6  
I2C  
34  
26  
INT5  
I2C  
33  
27  
INT4  
I2C  
C9  
32  
25  
INT3  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
TP00_0 U/D  
-
B8  
29  
24  
INT2  
-
B7  
27  
23  
INT1  
-
A8  
26  
20  
INT0  
-
D2  
688  
687  
685  
684  
683  
682  
680  
678  
679  
677  
675  
674  
673  
672  
668  
576  
575  
573  
572  
571  
570  
568  
567  
566  
565  
562  
563  
560  
561  
558  
SMC2M5  
SMC2P5  
SMC1M5  
SMC1P5  
SMC2M4  
SMC2P4  
SMC1M4  
SMC1P4  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
E3  
C1  
E4  
D1  
F4  
E2  
F2  
F3  
SMC2M3 AN31  
SMC2P3 AN30  
SMC1M3 AN29  
SMC1P3 AN28  
SMC2M2 AN27  
SMC2P2 AN26  
SMC1M2 AN25  
G3  
E1  
G2  
F1  
H2  
H4  
84  
Chapter 3 MB91460 Series Basic Information  
6.Pin Definitions  
J4  
H3  
J3  
666  
667  
665  
663  
662  
661  
660  
657  
656  
655  
654  
20  
557  
556  
555  
552  
553  
550  
551  
547  
548  
545  
546  
14  
P26_0  
P27_7  
P27_6  
P27_5  
P27_4  
P27_3  
P27_2  
P27_1  
P27_0  
ALARM_1  
ALARM_0  
P28_7  
P28_6  
P28_5  
P28_4  
P28_3  
P28_2  
P28_1  
P28_0  
P29_7  
P29_6  
P29_5  
P29_4  
P29_3  
P29_2  
P29_1  
P29_0  
P30_7  
P30_6  
P30_5  
P30_4  
P30_3  
P30_2  
P30_1  
P30_0  
P31_7  
P31_6  
P31_5  
P31_4  
P31_3  
P31_2  
P31_1  
P31_0  
P32_7  
P32_6  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SMC1P2 AN24  
SMC2M1 AN23  
SMC2P1 AN22  
SMC1M1 AN21  
SMC1P1 AN20  
SMC2M0 AN19  
SMC2P0 AN18  
SMC1M0 AN17  
SMC1P0 AN16  
-
-
-
-
-
-
-
-
-
-
-
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TA02_0  
TA02_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
AN IN  
AN IN  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
-
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
SMC / AN  
Ana In  
Ana In  
AN / DA  
AN / DA  
AN  
30mA  
30mA  
30mA  
30mA  
30mA  
30mA  
30mA  
30mA  
30mA  
-
G1  
J2  
H1  
K2  
K3  
K4  
L3  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
L4  
-
-
-
A5  
B5  
C7  
C6  
D6  
A4  
D5  
A3  
B4  
C5  
B3  
C4  
C2  
D3  
J1  
AN15  
AN14  
AN13  
AN12  
AN11  
AN10  
AN9  
DA1 TP01_0  
DA0 TP01_0  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
17  
13  
16  
12  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TP03_0 U/D  
TP03_0 U/D  
TP03_0 U/D  
TP03_0 U/D  
TP03_0 U/D  
TP03_0 U/D  
TP03_0 U/D  
TP03_0 U/D  
TP03_0 U/D  
TP03_0 U/D  
TP03_0 U/D  
TP03_0 U/D  
TP03_0 U/D  
TP03_0 U/D  
14  
10  
AN  
13  
11  
AN  
12  
8
AN  
11  
9
AN  
10  
6
AN8  
AN  
5
4
AN7  
AN  
4
3
AN6  
AN  
3
2
AN5  
AN  
2
1
AN4  
AN  
690  
689  
653  
650  
651  
648  
646  
645  
644  
643  
641  
640  
639  
638  
635  
634  
633  
632  
631  
629  
628  
626  
578  
577  
544  
543  
542  
541  
540  
538  
539  
536  
534  
535  
532  
533  
529  
530  
527  
528  
526  
524  
525  
523  
AN3  
AN  
AN2  
AN  
AN1  
AN  
L2  
AN0  
AN  
K1  
M2  
M4  
M3  
N4  
N3  
L1  
V3  
TP08_0  
TP07_0  
TP07_0  
TP07_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD V3  
V2  
LCD V0,V1,V2 4mA  
LCD V0,V1,V2 4mA  
LCD V0,V1,V2 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
V1  
V0  
COM3  
COM2  
COM1  
COM0  
SEG39  
SEG38  
SEG37  
SEG36  
SEG35  
SEG34  
SEG33  
SEG32  
SEG31  
N2  
M1  
P2  
P3  
R2  
R3  
T2  
N1  
P1  
R4  
T4  
SEG30 SCK15  
85  
Chapter 3 MB91460 Series Basic Information  
6.Pin Definitions  
U2  
T3  
624  
623  
622  
621  
619  
618  
617  
616  
613  
612  
611  
610  
609  
608  
607  
606  
605  
604  
603  
602  
601  
599  
598  
597  
596  
595  
594  
592  
589  
588  
587  
586  
585  
583  
582  
580  
579  
577  
576  
575  
574  
573  
572  
570  
566  
522  
521  
520  
519  
517  
516  
515  
514  
512  
511  
510  
509  
508  
507  
506  
505  
503  
504  
501  
502  
499  
497  
498  
495  
496  
493  
494  
492  
489  
490  
487  
488  
486  
484  
485  
483  
481  
479  
480  
477  
478  
475  
476  
474  
472  
P32_5  
P32_4  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SEG29 SOT15  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH / A  
CH (old)  
CH (old)  
CH (old)  
CH (old)  
CH (old)  
CH (old)  
CH (old)  
CH (old)  
CH (old)  
CH (old)  
CH (old)  
CH (old)  
CH (old)  
CH (old)  
CH (old)  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
no  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
LCD COM/SEG 4mA  
SEG28  
SEG27  
SIN15  
-
V2  
P32_3  
U3  
P32_2  
SEG26 SCK14  
SEG25 SOT14  
R1  
P32_1  
U4  
P32_0  
SEG24  
SEG23  
SIN14  
-
T1  
P33_7  
V3  
P33_6  
SEG22 SCK13  
SEG21 SOT13  
U1  
P33_5  
V4  
P33_4  
SEG20  
SEG19  
SIN13  
-
V1  
P33_3  
W4  
P33_2  
SEG18 SCK12  
SEG17 SOT12  
W2  
P33_1  
W3  
P33_0  
SEG16  
SEG15  
SIN12  
-
W1  
P34_7  
Y3  
P34_6  
SEG14 SCK11  
SEG13 SOT11  
Y1  
P34_5  
Y4  
P34_4  
SEG12  
SEG11  
SIN11  
-
Y2  
P34_3  
AA4  
AA1  
AB1  
AA2  
AA3  
AB2  
AB3  
AB4  
AC4  
AC1  
AC2  
AD1  
AD2  
AC3  
AD3  
AE2  
AF2  
AE1  
AF1  
AE4  
AE3  
AF4  
AF3  
AG2  
AH2  
AG4  
P34_2  
SEG10 SCK10  
P34_1  
SEG9  
SOT10  
P34_0  
SEG8  
SIN10  
P35_7  
SEG7  
-
P35_6  
SEG6  
SCK9  
P35_5  
SEG5  
SOT9  
P35_4  
SEG4  
SIN9  
P35_3  
SEG3  
-
P35_2  
SEG2  
SCK8  
P35_1  
SEG1  
SOT8  
P35_0  
SEG0  
SIN8  
INITX  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TC02_0 Up  
TC01_0 Up  
MCU control  
MCU control  
MCU control  
MCU control  
MCU control  
MCU control  
MCU control  
MCU control  
MCU control  
MCU control  
MCU control  
MCU control  
MCU control  
MCU control  
MCU control  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RSTX  
no  
HSTX  
TC00_0  
-
no  
NMIX  
TC01_0 Up  
no  
MD_2  
TC02_0  
TC02_0  
TC02_0  
TC00_0  
TC00_0  
TC00_0  
TC00_0  
TC00_0  
TC00_0  
TC00_0  
-
-
-
-
-
-
-
-
-
-
no  
MD_1  
no  
MD_0  
no  
ADC_SEL  
ALARM_SEL  
SRAM_SFX  
FSC_DISABLE  
CSV_KILL  
HWWDG_KILL  
FIX_ENX  
EDSU_BREAKX  
no  
no  
no  
no  
no  
no  
no  
TC01_0 Up  
no  
86  
Chapter 3 MB91460 Series Basic Information  
6.Pin Definitions  
AG1  
AH1  
AH4  
AG3  
AH3  
AJ2  
AK2  
AJ1  
AK1  
AJ4  
AJ3  
AK4  
AK3  
AL2  
AM2  
AL1  
AM1  
AL3  
AN1  
AM4  
AP1  
AN2  
AP2  
AM3  
AN3  
AN4  
AR1  
AP4  
AT1  
AR2  
AP3  
AT2  
AR3  
AU3  
AT4  
AU4  
AT5  
AV3  
AR5  
AV4  
AR6  
AU5  
AT6  
AU6  
AT7  
567  
565  
564  
563  
561  
560  
558  
557  
555  
554  
553  
552  
551  
548  
546  
545  
543  
542  
541  
540  
539  
538  
536  
535  
533  
532  
531  
530  
529  
524  
523  
522  
521  
517  
516  
515  
514  
512  
511  
510  
509  
507  
506  
505  
504  
471  
469  
470  
467  
465  
466  
464  
462  
460  
461  
458  
459  
457  
456  
454  
453  
450  
451  
448  
449  
446  
447  
445  
444  
443  
442  
441  
440  
439  
436  
435  
434  
433  
432  
430  
431  
428  
426  
427  
424  
425  
423  
421  
422  
419  
ICLK  
ICD_3  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TE22_0  
TE21_0  
TE21_0  
TE21_0  
TE21_0  
TE10_0  
TE10_0  
TE10_0  
TE01_0  
TE02_0  
TE00_0  
TE03_0  
TE11_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C
C
C
C
C
-
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
8mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
-
ICD_2  
ICD_1  
ICD_0  
ICS_2  
ICS_1  
-
ICS_0  
-
BREAK  
PLEVEL  
EXRAM  
TRSTX  
TCLK  
C
C
C
C
-
-
-
-
8mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
TOEX  
-
TWRX  
-
TCE1X  
TADSCX  
TAD_15  
TAD_14  
TAD_13  
TAD_12  
TAD_11  
TAD_10  
TAD_9  
TAD_8  
TAD_7  
TAD_6  
TAD_5  
TAD_4  
TAD_3  
TAD_2  
TAD_1  
TAD_0  
TDT_68  
TDT_67  
TDT_66  
TDT_65  
TDT_64  
TDT_63  
TDT_62  
TDT_61  
TDT_60  
TDT_59  
TDT_58  
TDT_57  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C
C
C
C
C
C
C
C
C
C
C
C
87  
Chapter 3 MB91460 Series Basic Information  
6.Pin Definitions  
AV5  
AU7  
502  
501  
500  
499  
495  
494  
493  
492  
490  
489  
488  
487  
484  
483  
482  
481  
480  
478  
477  
475  
473  
472  
471  
470  
468  
467  
466  
465  
462  
461  
460  
459  
458  
456  
455  
453  
451  
450  
449  
448  
446  
445  
444  
443  
440  
417  
420  
416  
418  
415  
412  
413  
410  
408  
409  
406  
407  
404  
405  
402  
403  
401  
400  
399  
398  
396  
395  
394  
392  
390  
391  
388  
389  
386  
385  
383  
384  
382  
381  
380  
379  
377  
376  
375  
374  
371  
372  
369  
370  
368  
TDT_56  
TDT_55  
TDT_54  
TDT_53  
TDT_52  
TDT_51  
TDT_50  
TDT_49  
TDT_48  
TDT_47  
TDT_46  
TDT_45  
TDT_44  
TDT_43  
TDT_42  
TDT_41  
TDT_40  
TDT_39  
TDT_38  
TDT_37  
TDT_36  
TDT_35  
TDT_34  
TDT_33  
TDT_32  
TDT_31  
TDT_30  
TDT_29  
TDT_28  
TDT_27  
TDT_26  
TDT_25  
TDT_24  
TDT_23  
TDT_22  
TDT_21  
TDT_20  
TDT_19  
TDT_18  
TDT_17  
TDT_16  
TDT_15  
TDT_14  
TDT_13  
TDT_12  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
AV6  
AU8  
AR8  
AT8  
AR9  
AT9  
AV7  
AU9  
AV8  
AU10  
AT10  
AR10  
AT11  
AR11  
AV9  
AV10  
AU11  
AU12  
AR12  
AT12  
AR13  
AT13  
AV11  
AU13  
AV12  
AU14  
AT14  
AU15  
AT15  
AU16  
AV13  
AV14  
AR15  
AR16  
AU17  
AT16  
AU18  
AT17  
AV15  
AR17  
AV16  
AT18  
AV17  
88  
Chapter 3 MB91460 Series Basic Information  
6.Pin Definitions  
AR18  
AV18  
AR19  
AU19  
AT19  
AV19  
AT20  
AV20  
AR20  
AU20  
AR21  
AV21  
AV22  
AU21  
AT21  
AU22  
AT22  
AR22  
AR23  
AV23  
AU23  
AV24  
AU24  
AT23  
AT24  
AU25  
AU26  
AV25  
AV26  
AR25  
AT25  
AR26  
AT26  
AU27  
AU28  
AV27  
AR27  
AV28  
AR28  
AT27  
AT28  
AU29  
AU30  
AV29  
AV30  
439  
438  
437  
436  
435  
434  
433  
432  
431  
430  
429  
428  
426  
425  
424  
423  
422  
421  
419  
416  
415  
414  
413  
412  
410  
409  
407  
406  
404  
403  
402  
401  
400  
399  
397  
394  
393  
392  
391  
390  
388  
387  
385  
384  
382  
367  
366  
365  
364  
363  
362  
361  
360  
359  
358  
357  
356  
354  
353  
351  
352  
349  
350  
348  
346  
345  
344  
343  
342  
340  
339  
338  
336  
335  
334  
333  
332  
330  
331  
329  
328  
327  
326  
325  
324  
322  
321  
320  
319  
317  
TDT_11  
TDT_10  
TDT_9  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE00_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C
C
C
C
C
C
C
C
C
C
C
C
C
-
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
-
TDT_8  
TDT_7  
TDT_6  
TDT_5  
TDT_4  
TDT_3  
TDT_2  
TDT_1  
TDT_0  
EMRAM  
ECSX  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
EWRX_3  
EWRX_2  
EWRX_1  
EWRX_0  
EECSX  
EEWEX  
EEOEX  
EEBEX_3  
EEBEX_2  
EEBEX_1  
EEBEX_0  
EEA_20  
EEA_19  
EEA_18  
EEA_17  
EEA_16  
EEA_15  
EEA_14  
EEA_13  
EEA_12  
EEA_11  
EEA_10  
EEA_9  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EEA_8  
-
EEA_7  
-
EEA_6  
-
EEA_5  
-
EEA_4  
-
EEA_3  
-
EEA_2  
-
EEA_1  
-
89  
Chapter 3 MB91460 Series Basic Information  
6.Pin Definitions  
AR29  
AT29  
AR30  
AT30  
AU31  
AU32  
AV31  
AV32  
AT31  
AV33  
AR32  
AV34  
AU33  
AU34  
AT32  
AT33  
AR33  
AV35  
AR34  
AV36  
AU35  
AT34  
AU36  
AT35  
AT37  
AR36  
AR37  
AP36  
AT38  
AP35  
AR38  
AN35  
AP37  
AN36  
AN37  
AM36  
AP38  
AM37  
AN38  
AL37  
AL35  
AL36  
AK35  
AK36  
AM38  
381  
380  
379  
378  
375  
373  
372  
370  
369  
368  
367  
366  
365  
363  
362  
360  
359  
358  
357  
356  
351  
350  
349  
348  
344  
343  
342  
341  
339  
338  
337  
336  
334  
333  
332  
331  
329  
328  
327  
326  
322  
321  
320  
319  
317  
316  
315  
314  
313  
311  
310  
309  
307  
306  
305  
304  
303  
302  
300  
301  
299  
297  
298  
295  
296  
292  
291  
290  
289  
288  
287  
286  
285  
283  
282  
281  
280  
279  
278  
277  
276  
275  
274  
273  
272  
269  
268  
267  
266  
265  
EEA_0  
EED_31  
EED_30  
EED_29  
EED_28  
EED_27  
EED_26  
EED_25  
EED_24  
EED_23  
EED_22  
EED_21  
EED_20  
EED_19  
EED_18  
EED_17  
EED_16  
EED_15  
EED_14  
EED_13  
EED_12  
EED_11  
EED_10  
EED_9  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TE10_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE20_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE00_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
TE10_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
no  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
Tool  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
-
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
-
EED_8  
EED_7  
EED_6  
EED_5  
EED_4  
EED_3  
EED_2  
EED_1  
EED_0  
IHIT_3  
IHIT_2  
-
IHIT_1  
-
IHIT_0  
-
FLASH_RDY  
FLASH_ALE  
FLASH_SYNC  
FLASH_ATDIN  
FLASH_EQIN  
FLASH_RD32  
FLASH_BYTEX  
FLASH_SECUR  
C
-
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
4mA  
-
-
-
-
-
-
90  
Chapter 3 MB91460 Series Basic Information  
6.Pin Definitions  
AK37  
316  
263  
FLASH_FRSTX  
-
-
-
-
TE10_0  
-
-
no  
Tool  
4mA  
0.0  
0.0  
637  
615  
591  
569  
313  
291  
269  
245  
223  
201  
179  
172  
152  
130  
118  
96  
531  
513  
491  
473  
260  
242  
224  
201  
183  
166  
149  
144  
126  
109  
98  
VDD5  
VDD5  
VDD5  
VDD5  
VDD5  
VDD5  
VDD5  
VDD5  
VDD5  
VDD5  
VDD5  
VDD5  
VDD5  
VDD5  
VDD5  
VDD5  
VDD5  
VDD5  
VDD5  
VDD5  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TS02_0  
TS02_0  
TS02_0  
TS02_0  
TS02_0  
TS02_0  
TS02_0  
TS02_0  
TS02_0  
TS02_0  
TS02_0  
TS02_0  
TS02_0  
TS02_0  
TS02_0  
TS02_0  
TS02_0  
TS02_0  
TS02_0  
TS02_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VDD 5V  
VDD 5V  
VDD 5V  
VDD 5V  
VDD 5V  
VDD 5V  
VDD 5V  
VDD 5V  
VDD 5V  
VDD 5V  
VDD 5V  
VDD 5V  
VDD 5V  
VDD 5V  
VDD 5V  
VDD 5V  
VDD 5V  
VDD 5V  
VDD 5V  
VDD 5V  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.0  
0.0  
AR7  
AP11  
AP19  
AP23  
AP31  
AM35  
AH34  
AD34  
T34  
H34  
H35  
E32  
81  
E28  
72  
59  
E20  
50  
40  
E12  
28  
22  
D8  
6
5
M5  
T5  
642  
620  
600  
578  
306  
284  
268  
254  
232  
210  
188  
167  
145  
123  
101  
81  
537  
518  
500  
482  
254  
235  
223  
210  
191  
173  
155  
140  
121  
103  
84  
VSS5  
VSS5  
VSS5  
VSS5  
VSS5  
VSS5  
VSS5  
VSS5  
VSS5  
VSS5  
VSS5  
VSS5  
VSS5  
VSS5  
VSS5  
VSS5  
VSS5  
VSS5  
VSS5  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y5  
AD5  
AJ34  
AE34  
AA34  
W34  
R34  
L34  
G34  
B37  
E31  
E27  
E23  
E19  
E15  
E11  
C3  
66  
59  
48  
37  
30  
9
7
0.0  
0.0  
681  
671  
569  
559  
HVDD5  
HVDD5  
-
-
-
-
-
-
-
-
TS02_0  
TS02_0  
-
-
-
-
-
-
VDD 5V  
VDD 5V  
-
-
91  
Chapter 3 MB91460 Series Basic Information  
6.Pin Definitions  
0.0  
659  
549  
HVDD5  
-
-
-
-
TS02_0  
-
-
-
VDD 5V  
-
B2  
F5  
H5  
686  
676  
664  
574  
564  
554  
HVSS5  
HVSS5  
HVSS5  
-
-
-
-
-
-
-
-
-
-
-
-
TS00_0  
TS00_0  
TS00_0  
-
-
-
-
-
-
-
-
-
VSS  
VSS  
VSS  
-
-
-
E9  
C8  
A7  
D7  
A6  
B6  
25  
23  
24  
21  
22  
19  
21  
19  
18  
17  
16  
15  
AVSS  
AVRL  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TA03_0  
TA01_0  
TA01_0  
TA00_0  
TA01_0  
TA00_0  
-
-
-
-
-
-
AVSS  
AVRH/L  
AVRH/L  
AVCC  
-
-
-
-
-
-
AVSS  
AVRH/L  
AVRH/L  
AVCC  
-
-
-
-
-
-
AVRH5  
AVCC5  
AVRH3  
AVCC3  
AVRH/L  
AVCC  
AVRH/L  
AVCC  
Y38  
W36  
W38  
W35  
261  
260  
259  
258  
216  
215  
214  
213  
VDD5R  
VDD5R  
VDD5R  
VDD5R  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TA00_0  
TA00_0  
TA00_0  
TA00_0  
-
-
-
-
AVCC  
AVCC  
AVCC  
AVCC  
-
-
-
-
AVCC  
AVCC  
AVCC  
AVCC  
-
-
-
-
AA38  
Y35  
Y37  
Y36  
265  
264  
263  
262  
220  
219  
218  
217  
VCC3C  
VCC3C  
VCC3C  
VCC3C  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TA10_0  
TA10_0  
TA10_0  
TA10_0  
-
-
-
-
ANA OUT  
ANA OUT  
ANA OUT  
ANA OUT  
-
-
-
-
VCC3C  
VCC3C  
VCC3C  
VCC3C  
-
-
-
-
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
0.0  
J5  
562  
549  
527  
497  
474  
463  
452  
420  
411  
389  
376  
354  
324  
323  
468  
455  
437  
414  
397  
387  
378  
347  
341  
323  
312  
294  
271  
270  
VDD3  
VDD3  
VDD3  
VDD3  
VDD3  
VDD3  
VDD3  
VDD3  
VDD3  
VDD3  
VDD3  
VDD3  
VDD3  
VDD3  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TS01_0  
TS01_0  
TS01_0  
TS01_0  
TS01_0  
TS01_0  
TS01_0  
TS01_0  
TS01_0  
TS01_0  
TS01_0  
TS01_0  
TS01_0  
TS01_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N5  
U5  
AD4  
AE5  
AN5  
AP9  
AH5  
AK5  
AT3  
556  
544  
528  
513  
491  
469  
447  
463  
452  
438  
429  
411  
393  
373  
VSS3  
VSS3  
VSS3  
VSS3  
VSS3  
VSS3  
VSS3  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
-
-
-
-
-
-
-
AU2  
AP8  
AP12  
AP16  
92  
Chapter 3 MB91460 Series Basic Information  
6.Pin Definitions  
AP20  
AP24  
AP28  
AP30  
AT36  
AU37  
AL34  
427  
405  
383  
371  
355  
340  
318  
355  
337  
318  
308  
293  
284  
264  
VSS3  
VSS3  
VSS3  
VSS3  
VSS3  
VSS3  
VSS3  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
TS00_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
-
-
-
-
-
-
-
93  
Chapter 3 MB91460 Series Basic Information  
7.I/O Circuit Type  
7. I/O Circuit Type  
The table below describes the circuit types which are used on the evaluation device MB91V460 Rev.A.  
Please refer to the datasheets for information about the circuit type of each pin used on the flash devices.  
CMOS/  
Pull Up/  
Pull Down  
CMOS Hyst./  
Automotive/  
TTL  
Type  
Input Stop  
Usage  
Output drive  
TP00_0  
TP01_0  
TP02_0  
TP03_0  
TP04_0  
TP05_0  
TP06_0  
TP07_0  
TP08_0  
Up / Dn  
CH / A  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
yes  
-
4 mA  
4 mA  
3 mA  
4 mA  
4 mA  
30 mA  
4 mA  
4 mA  
4 mA  
-
CH / A  
A/D in / D/A out  
I2C  
-
CH / A  
Up / Dn  
CH / A  
A/D in  
Up / Dn  
CH / A / TTL  
CH / A  
External Bus  
SMC / A/D in  
LCD COM/SEG  
LCD V0/V1/V2  
LCD V3  
-
-
-
-
CH / A  
CH / A  
CH / A  
TC00_0  
TC01_0  
TC02_0  
TC02_1  
TC10_0  
-
CH  
CH  
CH  
CH  
-
no  
no  
no  
no  
no  
MCU control  
MCU control  
MCU control  
MD0/MD1/MD2  
MONCLK  
-
Up  
Up  
-
-
-
-
-
8 mA  
TA00_0  
TA01_0  
TA02_0  
TA03_0  
TA10_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AVCC  
-
-
-
-
-
AVRH/AVRL  
A/D in  
AVSS  
VDD 3V  
TO00_0  
TO00_1  
TO01_0  
TO01_1  
-
-
-
-
-
-
-
-
yes  
yes  
yes  
yes  
X0  
-
-
-
-
X1  
X0A  
X1A  
TE00_0  
TE01_0  
TE02_0  
TE03_0  
TE10_0  
-
C
C
C
C
-
no  
no  
no  
no  
no  
Tool  
Tool  
Tool  
Tool  
Tool  
-
Dn (ctrl)  
-
Up  
Up  
-
-
-
4 mA  
94  
 
Chapter 3 MB91460 Series Basic Information  
7.I/O Circuit Type  
TE11_0  
TE20_0  
TE21_0  
TE22_0  
-
-
no  
no  
no  
no  
Tool  
Tool  
Tool  
Tool  
8 mA  
4 mA  
4 mA  
8 mA  
-
C
C
C
Dn (ctrl)  
-
TS00_0  
TS01_0  
TS02_0  
-
-
-
-
-
-
-
-
-
VSS  
VDD  
VDD 5V  
95  
Chapter 3 MB91460 Series Basic Information  
8.Pin State Table  
8. Pin State Table  
Explanation of the meaning of words and phrases used in the pin state table according to the chosen mode.  
• Input enable: It is possible to input a signal to the device.  
• Input fixed: To prevent leakage by floating inputs, the input level is fixed to "0" internally.  
• Hi-Z: The pin is put in a high impedance state.  
• State hold: The state (input/output) of the pin immediately before changing the state is maintained. In case  
of output, the output value of the pin is maintained.  
Table 8-1 Pin State Table  
Device  
State  
after Reset  
Functio  
n
at Reset and Vector at SLEEP  
at STOP  
HIZ = 0  
at STOP  
HIZ = 1 Remarks  
Port  
Name  
PFR=1 EPFR=1 Special (INIT, RST)  
Fetch  
AL38  
AJ37  
AJ36  
AJ35  
AH36  
AH35  
AK38  
AJ38  
AH37  
AG37  
AG35  
AG36  
AF35  
AF36  
AH38  
AF37  
AG38  
AE37  
AE36  
AD37  
AD36  
AC37  
AF38  
AE38  
315  
314  
311  
310  
309  
308  
307  
305  
304  
302  
300  
299  
298  
297  
295  
294  
293  
292  
289  
288  
287  
286  
285  
283  
262  
261  
259  
258  
257  
256  
255  
253  
252  
251  
249  
250  
247  
248  
246  
244  
245  
243  
241  
240  
239  
238  
237  
236  
P00_7  
P00_6  
P00_5  
P00_4  
P00_3  
P00_2  
P00_1  
P00_0  
P01_7  
P01_6  
P01_5  
P01_4  
P01_3  
P01_2  
P01_1  
P01_0  
P02_7  
P02_6  
P02_5  
P02_4  
P02_3  
P02_2  
P02_1  
P02_0  
D31  
D30  
D29  
D28  
D27  
D26  
D25  
D24  
D23  
D22  
D21  
D20  
D19  
D18  
D17  
D16  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D31  
D30  
D29  
D28  
D27  
D26  
D25  
D24  
D23  
D22  
D21  
D20  
D19  
D18  
D17  
D16  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Output Hi-Z, Output Hi-Z,  
Output:  
State hold State hold,  
Input fixed  
Output: HiZ,  
Input fixed  
Input  
Input  
enabled  
enabled  
Output Hi-Z, Output Hi-Z,  
Output:  
State hold State hold,  
Input fixed  
Output: HiZ,  
Input fixed  
Input  
Input  
enabled  
enabled  
Output Hi-Z, Output Hi-Z,  
Output:  
State hold State hold,  
Input fixed  
Output: HiZ,  
Input fixed  
Input  
Input  
enabled  
enabled  
D8  
D8  
96  
   
Chapter 3 MB91460 Series Basic Information  
8.Pin State Table  
AD35  
AC35  
AB37  
AC36  
AA37  
AB36  
AD38  
AC38  
AB35  
AA36  
AB38  
AA35  
W37  
V35  
282  
280  
278  
277  
276  
275  
273  
271  
272  
270  
267  
266  
257  
256  
255  
253  
252  
251  
250  
249  
248  
246  
243  
242  
241  
240  
239  
237  
236  
234  
233  
231  
230  
229  
228  
227  
226  
224  
221  
220  
219  
218  
217  
215  
214  
234  
233  
231  
232  
229  
230  
228  
227  
226  
225  
222  
221  
211  
212  
209  
207  
208  
205  
206  
203  
204  
202  
200  
199  
198  
197  
196  
195  
194  
193  
192  
190  
189  
188  
187  
186  
185  
184  
182  
181  
180  
179  
178  
177  
176  
P03_7  
P03_6  
P03_5  
P03_4  
P03_3  
P03_2  
P03_1  
P03_0  
X1  
D7  
D6  
D7  
D6  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D5  
D5  
Output Hi-Z, Output Hi-Z,  
Output:  
Output: HiZ,  
Input fixed  
D4  
D4  
Input  
Input  
State hold State hold,  
Input fixed  
enabled  
enabled  
D3  
D3  
D2  
D2  
D1  
D1  
D0  
D0  
Oscillator  
STOP if  
Oscillator  
STOP if  
-
-
Oscillator  
ON  
Oscillator  
ON  
Oscillator  
ON  
OSCD1 is OSCD1 is  
set  
set  
X0  
-
-
Oscillator  
STOP if  
Oscillator  
STOP if  
X1A  
-
-
Oscillator  
ON  
Oscillator  
ON  
Oscillator  
ON  
OSCD2 is OSCD2 is  
set  
set  
X0A  
-
-
MONCL  
Output Hi-Z Output HiZ State hold State hold State hold  
K
-
-
Single Chip  
mode: Mode  
P04_7  
P04_6  
P04_5  
P04_4  
P04_3  
P04_2  
P04_1  
P04_0  
P05_7  
P05_6  
P05_5  
P05_4  
P05_3  
P05_2  
P05_1  
P05_0  
P06_7  
P06_6  
P06_5  
P06_4  
P06_3  
P06_2  
P06_1  
P06_0  
P07_7  
P07_6  
P07_5  
P07_4  
P07_3  
P07_2  
P07_1  
P07_0  
A31  
A30  
A29  
A28  
A27  
A26  
A25  
A24  
A23  
A22  
A21  
A20  
A19  
A18  
A17  
A16  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
A31  
A30  
A29  
A28  
A27  
A26  
A25  
A24  
A23  
A22  
A21  
A20  
A19  
A18  
A17  
A16  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
V38  
Ext.Bus  
mode:  
U38  
V37  
Address  
Output  
Output Hi-Z,  
Input  
Output:  
State hold State hold,  
Input fixed  
Output: HiZ,  
Input fixed  
Single Chip  
mode:  
enabled  
V36  
Output Hi-Z,  
Input  
U37  
U36  
U35  
T35  
enabled  
T38  
Ext.Bus  
mode:  
T37  
Address  
Output  
Output Hi-Z,  
Input  
Output:  
State hold State hold,  
Input fixed  
R38  
R37  
T36  
Output: HiZ,  
Input fixed  
Single Chip  
mode:  
enabled  
Output Hi-Z,  
Input  
enabled  
R36  
P37  
N37  
P38  
Ext.Bus  
mode:  
N38  
P35  
Address  
Output  
Output Hi-Z,  
Input  
Output:  
State hold State hold,  
Input fixed  
Output: HiZ,  
Input fixed  
Single Chip  
mode:  
enabled  
P36  
Output Hi-Z,  
Input  
N35  
N36  
M37  
L37  
enabled  
A8  
A8  
A7  
A7  
M38  
M35  
L38  
A6  
A6  
Ext.Bus  
mode:  
A5  
A5  
Address  
Output  
Output Hi-Z,  
Input  
Output:  
State hold State hold,  
Input fixed  
A4  
A4  
Output: HiZ,  
Input fixed  
Single Chip  
mode:  
enabled  
L35  
A3  
A3  
Output Hi-Z,  
Input  
M36  
L36  
A2  
A2  
enabled  
A1  
A1  
K37  
A0  
A0  
97  
Chapter 3 MB91460 Series Basic Information  
8.Pin State Table  
Output Hi-Z,  
Input  
J37  
K38  
J38  
K35  
K36  
J35  
J36  
H37  
G37  
H38  
G38  
H36  
F38  
G35  
E38  
F37  
212  
211  
209  
208  
207  
206  
205  
202  
200  
199  
197  
196  
195  
194  
193  
192  
175  
174  
172  
171  
170  
169  
168  
167  
165  
164  
163  
162  
161  
160  
159  
158  
P08_7  
P08_6  
P08_5  
P08_4  
RDY  
BRQ  
RDY  
BRQ  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
enabled  
BGRNT BGRNT  
X
X
Ext.Bus  
mode:  
Output Hi-Z,  
Input  
Output:  
State hold State hold,  
Input fixed  
RDX  
RDX  
Output: HiZ,  
Input fixed  
Control  
Output  
enabled  
P08_3 WRX3 WRX3  
P08_2 WRX2 WRX2  
P08_1 WRX1 WRX1  
P08_0 WRX0 WRX0  
P09_7 CSX7 CSX7  
P09_6 CSX6 CSX6  
P09_5 CSX5 CSX5  
P09_4 CSX4 CSX4  
P09_3 CSX3 CSX3  
P09_2 CSX2 CSX2  
P09_1 CSX1 CSX1  
P09_0 CSX0 CSX0  
Single Chip  
mode:  
Output Hi-Z,  
Input  
enabled  
Ext.Bus  
mode:  
Chip Select  
Output  
Output Hi-Z,  
Input  
Output:  
State hold State hold,  
Input fixed  
Output: HiZ,  
Input fixed  
Single Chip  
mode:  
enabled  
Output Hi-Z,  
Input  
enabled  
Output Hi-Z,  
Input  
enabled  
E37  
190  
157  
P10_7  
-
-
-
-
Ext.Bus  
mode:  
MCLKE  
Output  
Single Chip  
mode:  
Output Hi-Z,  
Input  
enabled  
Output Hi-Z,  
Input  
Output:  
State hold State hold,  
Input fixed  
Output: HiZ,  
Input fixed  
enabled  
G36  
189  
156  
P10_6 MCLKE MCLKE  
^
-
Output Hi-Z,  
Input  
enabled  
F36  
F35  
D38  
E35  
C38  
D37  
E36  
C37  
D36  
B36  
C35  
B35  
C34  
A36  
187  
186  
185  
184  
183  
178  
177  
176  
175  
171  
170  
169  
168  
166  
154  
153  
152  
151  
150  
147  
148  
145  
146  
143  
142  
141  
139  
138  
P10_5 MCLKI MCLKI /MCLKI  
P10_4 MCLKO MCLKO /MCLKO  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Ext.Bus  
mode:  
Control/  
Clock  
P10_3 WEX  
P10_2 BAAX BAAX  
P10_1 ASX ASX  
WEX  
^
^
Output  
Single Chip  
mode:  
^
/
Output Hi-Z,  
Input  
enabled  
P10_0 SYSCLKSYSCLKSYSCLK  
P11_7  
P11_6  
P11_5  
P11_4  
P11_3  
P11_2  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Output Hi-Z, Output Hi-Z,  
Output:  
State hold State hold,  
Input fixed  
Output: HiZ,  
Input fixed  
Input  
Input  
enabled  
enabled  
P11_1 IOWRX IOWRX  
P11_0 IORDX IORDX  
98  
Chapter 3 MB91460 Series Basic Information  
8.Pin State Table  
D34  
A35  
D33  
B34  
C33  
B33  
C32  
A34  
B32  
A33  
B31  
D31  
C31  
D30  
C30  
A32  
B30  
A31  
B29  
C29  
D29  
C28  
D28  
A30  
A29  
B28  
B27  
D27  
C27  
D26  
C26  
A28  
B26  
A27  
B25  
C25  
B24  
C24  
B23  
A26  
165  
164  
163  
161  
160  
159  
158  
156  
155  
154  
153  
149  
148  
147  
146  
144  
143  
142  
141  
138  
137  
136  
135  
134  
132  
131  
129  
127  
126  
125  
124  
122  
121  
120  
119  
116  
115  
114  
113  
112  
137  
136  
135  
134  
133  
132  
131  
130  
129  
128  
127  
125  
124  
123  
122  
120  
119  
118  
117  
116  
115  
114  
113  
112  
111  
110  
108  
107  
106  
105  
104  
102  
101  
100  
99  
P12_7 DEOP3 DEOP3  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P12_6 DEOTX3DEOTX3 DEOP3  
P12_5 DACKX3DACKX3  
P12_4 DREQ3 DREQ3  
P12_3 DEOP2 DEOP2  
^
^
-
Output Hi-Z, Output Hi-Z,  
Output:  
Output: HiZ,  
Input fixed  
Input  
Input  
State hold State hold,  
Input fixed  
enabled  
enabled  
P12_2 DEOTX2DEOTX2 DEOP2  
P12_1 DACKX2DACKX2  
P12_0 DREQ2 DREQ2  
P13_7 DEOP1 DEOP1  
^
^
-
P13_6 DEOTX1DEOTX1 DEOP1  
P13_5 DACKX1DACKX1  
P13_4 DREQ1 DREQ1  
P13_3 DEOP0 DEOP0  
^
^
-
Output Hi-Z, Output Hi-Z,  
Output:  
Output: HiZ,  
Input  
Input  
State hold State hold,  
Input fixed  
enabled  
enabled  
Input fixed  
P13_2 DEOTX0DEOTX0 DEOP0  
P13_1 DACKX0DACKX0  
^
^
P13_0 DREQ0 DREQ0  
ICU7/  
P14_7  
P14_6  
P14_5  
P14_4  
P14_3  
P14_2  
P14_1  
P14_0  
P15_7  
P15_6  
P15_5  
P15_4  
P15_3  
P15_2  
P15_1  
P15_0  
P16_7  
P16_6  
P16_5  
P16_4  
P16_3  
P16_2  
P16_1  
P16_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TIN7  
TIN7 TTG15/7  
TIN6 TTG14/6  
TIN5 TTG13/5  
TIN4 TTG12/4  
TIN3 TTG11/3  
TIN2 TTG10/2  
TIN1 TTG9/1  
TIN0 TTG8/0  
ICU6/  
TIN6  
ICU5/  
TIN5  
ICU4/  
Output Hi-Z, Output Hi-Z,  
Output:  
Output: HiZ,  
TIN4  
Input  
Input  
State hold State hold,  
Input fixed  
ICU3/  
TIN3  
enabled  
enabled  
Input fixed  
ICU2/  
TIN2  
ICU1/  
TIN1  
ICU0/  
TIN0  
OCU7 TOT7  
OCU6 TOT6  
OCU5 TOT5  
OCU4 TOT4  
OCU3 TOT3  
OCU2 TOT2  
OCU1 TOT1  
OCU0 TOT0  
PPG15 ATGX  
PPG14 PFM  
PPG13 SGO  
PPG12 SGA  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Output Hi-Z, Output Hi-Z,  
Output:  
Output: HiZ,  
Input  
Input  
State hold State hold,  
Input fixed  
enabled  
enabled  
Input fixed  
Output Hi-Z, Output Hi-Z,  
Output:  
Output: HiZ,  
97  
Input  
Input  
State hold State hold,  
Input fixed  
enabled  
enabled  
Input fixed  
96  
PPG11  
PPG10  
PPG9  
^
^
^
^
95  
94  
93  
PPG8  
99  
Chapter 3 MB91460 Series Basic Information  
8.Pin State Table  
A25  
D24  
D23  
B22  
C23  
B21  
C22  
A24  
D22  
A23  
C21  
A22  
D21  
A21  
D20  
B20  
C20  
A20  
C19  
A19  
D19  
B19  
D18  
A18  
A17  
B18  
C18  
B17  
C17  
D17  
D16  
A16  
B16  
A15  
B15  
C16  
C15  
B14  
B13  
A14  
110  
109  
107  
105  
104  
103  
102  
100  
99  
92  
91  
90  
88  
89  
86  
87  
85  
82  
83  
80  
79  
77  
78  
75  
76  
73  
74  
71  
72  
70  
69  
68  
67  
65  
64  
63  
62  
61  
60  
58  
57  
55  
56  
53  
54  
52  
51  
49  
50  
P17_7  
P17_6  
P17_5  
P17_4  
P17_3  
P17_2  
P17_1  
P17_0  
P18_7  
P18_6  
P18_5  
P18_4  
P18_3  
P18_2  
P18_1  
P18_0  
P19_7  
P19_6  
P19_5  
P19_4  
P19_3  
P19_2  
P19_1  
P19_0  
P20_7  
P20_6  
P20_5  
P20_4  
P20_3  
P20_2  
P20_1  
P20_0  
P21_7  
P21_6  
P21_5  
P21_4  
P21_3  
P21_2  
P21_1  
P21_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PPG7  
PPG6  
PPG5  
PPG4  
PPG3  
PPG2  
PPG1  
PPG0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Output Hi-Z, Output Hi-Z,  
Output:  
State hold State hold,  
Input fixed  
Output: HiZ,  
Input fixed  
Input  
Input  
enabled  
enabled  
ZIN3/  
98  
SCK7  
SOT7  
SIN7  
-
CK7  
97  
BIN3  
AIN3  
-
Output Hi-Z, Output Hi-Z,  
Output:  
State hold State hold,  
Input fixed  
94  
Output: HiZ,  
Input fixed  
Input  
Input  
enabled  
enabled  
93  
ZIN2/  
92  
SCK6  
SOT6  
SIN6  
-
CK6  
91  
BIN2  
90  
AIN2  
89  
-
88  
SCK5  
SOT5  
SIN5  
-
CK5  
87  
^
Output Hi-Z, Output Hi-Z,  
Output:  
State hold State hold,  
Input fixed  
86  
^
Output: HiZ,  
Input fixed  
Input  
Input  
enabled  
enabled  
85  
-
84  
SCK4  
SOT4  
SIN4  
-
CK4  
83  
^
^
-
82  
80  
ZIN1/  
79  
SCK3  
SOT3  
SIN3  
-
CK3  
78  
BIN1  
AIN1  
-
Output Hi-Z, Output Hi-Z,  
Output:  
State hold State hold,  
Input fixed  
77  
Output: HiZ,  
Input fixed  
Input  
Input  
enabled  
enabled  
76  
ZIN0/  
75  
SCK2  
SOT2  
SIN2  
-
CK2  
73  
BIN0  
70  
AIN0  
69  
-
68  
SCK1  
SOT1  
SIN1  
-
CK1  
67  
^
Output Hi-Z, Output Hi-Z,  
Output:  
State hold State hold,  
Input fixed  
66  
^
Output: HiZ,  
Input fixed  
Input  
Input  
enabled  
enabled  
64  
-
CK0  
^
63  
SCK0  
SOT0  
SIN0  
61  
60  
^
100  
Chapter 3 MB91460 Series Basic Information  
8.Pin State Table  
A13  
58  
47  
P22_7  
-
SCL1  
-
-
STOP: Input  
enabled if PFR is  
set (for Ext.INT)  
D14  
C14  
57  
56  
46  
45  
P22_6  
P22_5  
-
-
SDA1  
SCL0  
-
-
INT15  
-
STOP: Input  
enabled if PFR is  
set (for Ext.INT)  
Output Hi-Z, Output Hi-Z,  
Output:  
Output: HiZ,  
Input fixed  
D13  
C13  
55  
54  
44  
42  
P22_4  
P22_3  
-
-
SDA0  
TX5  
-
-
INT14  
-
Input  
Input  
State hold State hold,  
Input fixed  
enabled  
enabled  
STOP: Input  
enabled if PFR is  
set (for Ext.INT)  
B12  
B11  
53  
51  
43  
41  
P22_2  
P22_1  
-
-
RX5  
TX4  
-
-
INT13  
-
STOP: Input  
enabled if PFR is  
set (for Ext.INT)  
A12  
D12  
48  
47  
39  
38  
P22_0  
P23_7  
-
-
RX4  
TX3  
-
-
INT12  
-
STOP: Input  
enabled if PFR is  
set (for Ext.INT)  
A11  
D11  
46  
45  
37  
36  
P23_6  
P23_5  
-
-
RX3  
TX2  
-
-
INT11  
-
STOP: Input  
enabled if PFR is  
set (for Ext.INT)  
Output Hi-Z, Output Hi-Z,  
Output:  
Output: HiZ,  
Input fixed  
C12  
C11  
44  
42  
35  
34  
P23_4  
P23_3  
-
-
RX2  
TX1  
-
-
INT10  
-
Input  
Input  
State hold State hold,  
Input fixed  
enabled  
enabled  
STOP: Input  
enabled if PFR is  
set (for Ext.INT)  
B10  
B9  
41  
39  
33  
32  
P23_2  
P23_1  
-
-
RX1  
TX0  
-
-
INT9  
-
STOP: Input  
enabled if PFR is  
set (for Ext.INT)  
A10  
38  
31  
P23_0  
-
RX0  
-
INT8  
101  
Chapter 3 MB91460 Series Basic Information  
8.Pin State Table  
A9  
D10  
C10  
D9  
C9  
B8  
B7  
A8  
D2  
E3  
C1  
E4  
D1  
F4  
E2  
F2  
F3  
G3  
E1  
G2  
F1  
H2  
H4  
J4  
36  
35  
29  
28  
P24_7  
P24_6  
P24_5  
P24_4  
P24_3  
P24_2  
P24_1  
P24_0  
P25_7  
P25_6  
P25_5  
P25_4  
P25_3  
P25_2  
P25_1  
P25_0  
P26_7  
P26_6  
P26_5  
P26_4  
P26_3  
P26_2  
P26_1  
P26_0  
P27_7  
P27_6  
P27_5  
P27_4  
P27_3  
P27_2  
P27_1  
P27_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
INT7  
INT6  
INT5  
INT4  
INT3  
INT2  
INT1  
INT0  
-
SCL3  
-
SDA3  
34  
26  
-
SCL2  
Output Hi-Z, Output Hi-Z,  
Output:  
State hold State hold,  
Input fixed  
STOP: Input  
enabled if PFR is  
set (for Ext.INT)  
33  
27  
-
SDA2  
Output: HiZ,  
Input fixed  
Input  
Input  
enabled  
enabled  
32  
25  
-
-
29  
24  
-
-
27  
23  
-
-
26  
20  
-
-
SMC2M  
688  
687  
685  
684  
683  
682  
680  
678  
679  
677  
675  
674  
673  
672  
668  
666  
667  
665  
663  
662  
661  
660  
657  
656  
655  
654  
20  
576  
575  
573  
572  
571  
570  
568  
567  
566  
565  
562  
563  
560  
561  
558  
557  
556  
555  
552  
553  
550  
551  
547  
548  
545  
546  
14  
5
-
-
SMC2P5  
-
-
SMC1M  
5
-
-
Output Hi-Z, Output Hi-Z,  
Output:  
State hold State hold,  
Input fixed  
SMC1P5  
-
-
Output: HiZ,  
Input fixed  
Input  
Input  
SMC2M  
enabled  
enabled  
4
-
-
SMC2P4  
-
-
SMC1M  
4
-
-
-
SMC1P4  
-
SMC2M  
3
AN31  
-
SMC2P3 AN30  
SMC1M  
-
3
AN29  
-
Output Hi-Z, Output Hi-Z,  
Output:  
State hold State hold,  
Input fixed  
SMC1P3 AN28  
SMC2M  
-
Output: HiZ,  
Input fixed  
Input  
Input  
enabled  
enabled  
2
AN27  
-
SMC2P2 AN26  
SMC1M  
-
2
AN25  
-
SMC1P2 AN24  
SMC2M  
-
H3  
J3  
1
AN23  
-
SMC2P1 AN22  
SMC1M  
-
G1  
J2  
1
AN21  
-
Output Hi-Z, Output Hi-Z,  
Output:  
State hold State hold,  
Input fixed  
SMC1P1 AN20  
SMC2M  
-
Output: HiZ,  
Input fixed  
Input  
Input  
enabled  
enabled  
H1  
K2  
K3  
K4  
L3  
0
AN19  
-
SMC2P0 AN18  
SMC1M  
-
0
AN17  
-
SMC1P0 AN16  
-
ALARM_  
1
-
-
-
-
-
-
-
-
-
-
-
-
analog input analog input State hold State hold State hold  
ALARM_  
0
L4  
-
-
A5  
B5  
C7  
C6  
D6  
A4  
D5  
A3  
P28_7  
P28_6  
P28_5  
P28_4  
P28_3  
P28_2  
P28_1  
P28_0  
AN15  
AN14  
AN13  
AN12  
AN11  
AN10  
AN9  
AN8  
DA1  
17  
13  
DA0  
16  
12  
-
-
-
-
-
-
Output Hi-Z, Output Hi-Z,  
Output:  
State hold State hold,  
Input fixed  
14  
10  
Output: HiZ,  
Input fixed  
Input  
Input  
enabled  
enabled  
13  
11  
12  
8
11  
9
10  
6
102  
Chapter 3 MB91460 Series Basic Information  
8.Pin State Table  
B4  
C5  
B3  
C4  
C2  
D3  
J1  
5
4
P29_7  
P29_6  
P29_5  
P29_4  
P29_3  
P29_2  
P29_1  
P29_0  
P30_7  
P30_6  
P30_5  
P30_4  
P30_3  
P30_2  
P30_1  
P30_0  
P31_7  
P31_6  
P31_5  
P31_4  
P31_3  
P31_2  
P31_1  
P31_0  
P32_7  
P32_6  
P32_5  
P32_4  
P32_3  
P32_2  
P32_1  
P32_0  
P33_7  
P33_6  
P33_5  
P33_4  
P33_3  
P33_2  
P33_1  
P33_0  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AN7  
AN6  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4
3
3
2
AN5  
Output Hi-Z, Output Hi-Z,  
Output:  
Output: HiZ,  
Input fixed  
2
1
AN4  
Input  
Input  
State hold State hold,  
Input fixed  
enabled  
enabled  
690  
689  
653  
650  
651  
648  
646  
645  
644  
643  
641  
640  
639  
638  
635  
634  
633  
632  
631  
629  
628  
626  
624  
623  
622  
621  
619  
618  
617  
616  
613  
612  
611  
610  
609  
608  
578  
577  
544  
543  
542  
541  
540  
538  
539  
536  
534  
535  
532  
533  
529  
530  
527  
528  
526  
524  
525  
523  
522  
521  
520  
519  
517  
516  
515  
514  
512  
511  
510  
509  
508  
507  
AN3  
AN2  
AN1  
L2  
AN0  
K1  
M2  
M4  
M3  
N4  
N3  
L1  
V3  
V2  
V1  
Output Hi-Z, Output Hi-Z,  
Output:  
Output: HiZ,  
V0  
Input  
Input  
State hold State hold,  
Input fixed  
enabled  
enabled  
Input fixed  
COM3  
COM2  
COM1  
COM0  
SEG39  
SEG38  
SEG37  
SEG36  
SEG35  
SEG34  
SEG33  
SEG32  
SEG31  
N2  
M1  
P2  
P3  
R2  
R3  
T2  
N1  
P1  
R4  
T4  
U2  
T3  
V2  
U3  
R1  
U4  
T1  
V3  
U1  
V4  
V1  
W4  
W2  
W3  
Output Hi-Z, Output Hi-Z,  
Output:  
Output: HiZ,  
Input  
Input  
State hold State hold,  
Input fixed  
enabled  
enabled  
Input fixed  
SEG30 SCK15  
SEG29 SOT15  
SEG28 SIN15  
Output Hi-Z, Output Hi-Z,  
Output:  
Output: HiZ,  
Input  
Input  
State hold State hold,  
Input fixed  
enabled  
enabled  
Input fixed  
SEG27  
-
SEG26 SCK14  
SEG25 SOT14  
SEG24 SIN14  
SEG23  
-
SEG22 SCK13  
SEG21 SOT13  
SEG20 SIN13  
Output Hi-Z, Output Hi-Z,  
Output:  
Output: HiZ,  
Input  
Input  
State hold State hold,  
Input fixed  
enabled  
enabled  
Input fixed  
SEG19  
-
SEG18 SCK12  
SEG17 SOT12  
SEG16 SIN12  
103  
Chapter 3 MB91460 Series Basic Information  
8.Pin State Table  
W1  
Y3  
607  
606  
605  
604  
603  
602  
601  
599  
598  
597  
596  
595  
594  
592  
589  
588  
587  
586  
585  
583  
582  
580  
579  
506  
505  
503  
504  
501  
502  
499  
497  
498  
495  
496  
493  
494  
492  
489  
490  
487  
488  
486  
484  
485  
483  
481  
P34_7  
P34_6  
P34_5  
P34_4  
P34_3  
P34_2  
P34_1  
P34_0  
P35_7  
P35_6  
P35_5  
P35_4  
P35_3  
P35_2  
P35_1  
P35_0  
INITX  
RSTX  
HSTX  
NMIX  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SEG15  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SEG14 SCK11  
SEG13 SOT11  
SEG12 SIN11  
Y1  
Output Hi-Z, Output Hi-Z,  
Output:  
State hold State hold,  
Input fixed  
Y4  
Output: HiZ,  
Input fixed  
Input  
Input  
enabled  
enabled  
Y2  
SEG11  
-
AA4  
AA1  
AB1  
AA2  
AA3  
AB2  
AB3  
AB4  
AC4  
AC1  
AC2  
AD1  
AD2  
AC3  
AD3  
AE2  
AF2  
AE1  
SEG10 SCK10  
SEG9 SOT10  
SEG8 SIN10  
SEG7  
-
SEG6 SCK9  
SEG5 SOT9  
Output Hi-Z, Output Hi-Z,  
Output:  
State hold State hold,  
Input fixed  
SEG4  
SEG3  
SIN9  
-
Output: HiZ,  
Input fixed  
Input  
Input  
enabled  
enabled  
SEG2 SCK8  
SEG1 SOT8  
SEG0  
SIN8  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Input enabled  
Input enabled  
MD_2  
MD_1  
MD_0  
104  
Chapter 4 CPU Architecture  
1.Overview  
Chapter 4 CPU Architecture  
This chapter describes the architecture of FR60 family CPU.  
1. Overview  
The CPUs of the FR60 family series employ RISC architecture and advanced function instructions for  
embedded application.  
CPU of FR60 family employs Harvard architecture whose instruction bus and data bus are independent. “32-  
bit/16-bit bus converter” realizes the interface between CPU and peripheral functions. “Harvard/Princeton bus  
converter” connects both of I-bus and D-bus and realizes the interface between CPU and bus controller.  
Figure 1-1 Connection Diagram of Internal Architecture  
FR CPU  
I-Bus  
D-Bus  
Embedded  
Flash or  
ROM  
Embedded  
I-Cache  
Embedded  
RAM  
Embedded  
RAM  
32  
32  
32  
32  
32  
32  
Harvard/Princeton  
Bus Converter  
F-Bus  
M-Bus  
Bus Converter  
32 <-> 16  
32  
32  
32  
DMA  
Controller  
R-Bus  
13  
X-Bus  
16  
32  
32  
Bus Converter  
16 bit  
Resources  
32 bit  
Resources  
T-Bus  
32  
32  
External Bus  
105  
   
Chapter 4 CPU Architecture  
2.Features  
2. Features  
■ Features of internal architecture  
• RISC architecture  
• Base instruction: 1 instruction/1 cycle  
• 32-bit architecture  
• General-purpose register: 32-bit x 16  
• 4GB of linear memory space  
• Equipped with multiplier.  
•32-bit x 32-bit multiplication: 5 cycles  
•16-bit x 16-bit multiplication: 3 cycles  
• Enhanced interrupt processing function  
•High-speed respond (6 cycles)  
•Support of multiple interrupts  
•Level mask function (16 levels)  
• Enhanced instruction for I/O operation  
•Transfer instruction between memories  
•Bit-processing instruction  
• Highly efficient code  
• Length of base instruction words: 16 bits  
• Standby mode (Low power consumption mode)  
• Sleep/Stop  
• Setting function of clock division ratios  
106  
 
Chapter 4 CPU Architecture  
3.CPU  
3. CPU  
The CPU realizes the compact implementation of a 32-bit RISC FR architecture.  
It employs a 5-stage instruction pipeline method to execute 1 instruction per 1 cycle.  
This pipeline consists of the following stages.  
•
•
•
•
•
Instruction fetch (IF): outputs instruction address to fetch instruction.  
Instruction decode (ID): decodes fetched instruction and reads register.  
Execution (EX): executes operation.  
Memory access (MA): loads data for memory or accesses stored data.  
Write back to register (WB): writes back data to registers.  
Figure 3-1 Instruction Pipeline  
CLK  
WB  
MA  
EX  
ID  
Instruction 1  
Instruction 2  
WB  
MA  
EX  
ID  
Instruction 3  
Instruction 4  
WB  
MA  
EX  
ID  
WB  
MA  
EX  
Instruction 5  
Instruction 6  
IF  
WB  
MA  
IF  
WB  
No instruction is executed in random order. If instruction A enters into pipeline before instruction B, instruction  
A always reaches to write-back stage before instruction B.  
1 instruction is executed per 1 cycle.  
However, to execute the instruction, multiple cycles are required for load/store instruction with memory wait,  
branch instruction without delay slot and multi-cycle instruction. In addition, a slow instruction degrades  
instruction execution speed.  
4. 32-bit/16-bit Bus Converter  
This converter generates the interface between D-bus which executes 32-bit high-speed access and R-bus  
which executes 16-bit access in order to realize data access from CPU to peripheral functions.  
If 32-bit access comes from CPU, this converter converts the access into two 16-bit accesses to access to R  
bus. Some peripheral functions have restrictions of access width.  
5. Harvard/Princeton Bus Converter  
This converter realizes interface between instruction access and data access of CPU, to realize smooth  
interface with external bus.  
The CPU employs the Harvard architecture whose instruction bus and data bus are independent while it  
employs single-bus Princeton architecture for bus controller to control external bus. This bus converter  
prioritizes instruction accesses and data accesses of CPU, and executes access control to bus controller. This  
always optimizes access sequence to external bus.  
107  
     
Chapter 4 CPU Architecture  
6.Instruction Overview  
6. Instruction Overview  
The FR60 family supports logic operation, bit operation and direct addressing instruction optimized  
for embedded application as well as general RISC instruction system. Instruction-set list is shown  
in the appendix. Since each instruction is 16-bit length (some instruction is 32-bit or 48-bit length), it  
enables you to generate compact program code.  
Instruction sets are grouped into the following a through f function groups.  
■ Arithmetic Operation  
This group consists of standard arithmetic operation instruction (addition, subtraction and  
comparison) and shift instruction (logic shift and arithmetic shift). For addition and subtraction, the  
operation with carry used for multiple word length operation and the operation useful for address  
calculation without changing flag value are allowed.  
In addition, it includes 32-bit x 32-bit and 16-bit x 16-bit multiplication instruction as well as 32-bit/  
32-bit step division instruction.  
It provides transfer instruction of immediate value which sets immediate value to register, and  
transfer instruction between registers.  
All arithmetic instructions are operated using general-purpose register and multiply & divide register  
within CPU.  
■ Load and Store  
Load/store is the instruction to read and write to memory. This is also used for read and write to  
peripheral functions (I/O) within chip.  
Load and store consist of 3 type access lengths including byte, half-word and word. In addition to  
general register-indirect memory addressing, some instructions allow register-indirect memory  
addressing with displacement or with register increment/decrement.  
■ Branch  
This is the instruction for branch, call, interrupt and return. Branch instruction consists of  
instructions with and without delay slot. For more information of branch instruction, see “Chapter 7  
Branch Instruction (Page No.129)”.  
■ Logical Operation and Bit Operation  
Logical operation instruction allows the logical operation of AND, OR and EOR between general-  
purpose registers or general-purpose register and memory (and I/O). Bit operation instruction  
allows the direct operation of data of memory (and I/O). Memory addressing is general register  
indirect.  
■ Direct Addressing  
Direct addressing instruction is the instruction to access between I/O and general-purpose register,  
or between I/O and memory. By directly instructing I/O address rather than register indirect, it  
enables high-speed and high-efficient access. Some instructions allow register-indirect memory  
addressing with register increment/decrement.  
■ Others  
This is the instruction which executes flag setting, stack operation, sign extension and zero  
extension within PS register. It provides the function entrance/exit which supports high-level  
language, and register multi-load/store instruction.  
108  
 
Chapter 4 CPU Architecture  
7.Data Structure  
7. Data Structure  
FR60 has two data allocations as follows.  
■ Bit Ordering  
FR60 uses little endian as bit ordering.  
Figure 7-1 Bit Structure of Bit Ordering  
bit  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0  
MSB  
LSB  
■ Byte Ordering  
FR60 uses big endian as byte ordering.  
Figure 7-2 Bit Structure of Byte Ordering  
LSB  
0
MSB  
bit31  
Memory  
23  
15  
7
11001100 11111111 00010001  
10101010  
bit  
7
0
10101010  
11001100  
n address  
(n+1) address  
(n+2) address  
(n+3) address  
11111111  
00010001  
109  
 
Chapter 4 CPU Architecture  
8.Word Alignment  
8. Word Alignment  
Since instructions and data are accessed by byte, allocated addresses vary by instruction length or  
data width.  
■ Program Access  
FR60 program is required to be allocated in addresses multiplied by 2.  
PC's bit0 is cleared for instruction execution upon the PC update.  
(PC bit 0 may be set when odd address is specified for branching address, however, it is invalid. Since the  
instruction is required to be allocated in addresses multiplied by 2, there is no odd address exception.)  
■ Data Access  
FR60 provides the following alignment for addresses depending on data width when executing data  
access.  
•
•
•
Word access  
Half-word access : Address is multiplied by 2. (Lowest order bit is mandatorily 0.)  
Byte access: : Address is multiplied by 1.  
: Address is multiplied by 4. (Lowest order 2 bits are mandatorily 00.)  
Upon the word and half-word data accesses, some bits mandatorily become 0 for computing results  
of effective address. For example, in the case of addressing mode of @(R13, Ri), register value  
before addition is used as is (even if lowest order bit is 1), and lower bits of addition results are  
masked. Register values before computing are not masked.  
[Example] LD @(R13, R2), R0  
R13  
R2  
00002222  
00000003  
+)  
00002225H  
00002224H  
Addition results  
Address pin  
Lower 2 bits are  
mandatorily masked.  
110  
 
Chapter 4 CPU Architecture  
9.Addressing  
9. Addressing  
Address space is 32-bit linear.  
■ Map  
Figure 9-1 Map  
Byte data  
0000 0000H  
0000 0100H  
Direct addressing area  
Half-word data  
Word data  
0000 0200H  
0000 0400H  
000F FC00H  
000F FFFFH  
Vector table  
FFFF FFFFH  
32  
FR60’s logical address space is 4GB (2 addresses), CPU accesses the data linearly.  
■ Direct Addressing Area  
The following areas are used for I/O.  
These spaces are referred to as direct addressing area where you can specify direct operand address by the  
instruction.  
These direct areas vary by data size to be accessed.  
•
•
•
Byte access  
Half-word access : 0 - 1FF  
Word access : 0 - 3FF  
: 0 - 0FF  
H
H
H
111  
 
Chapter 4 CPU Architecture  
9.Addressing  
112  
Chapter 5 CPU Registers  
1.General-purpose Registers  
Chapter 5 CPU Registers  
1. General-purpose Registers  
Registers R0 through R15 are general-purpose registers. These registers are used for accumulator and  
memory access pointers on various operations.  
Figure 1-1 General-purpose Registers  
32 bit  
[Initial value]  
XXXX XXXXH  
...  
R0  
R1  
...  
...  
...  
...  
...  
...  
R12  
R13  
R14  
R15  
...  
AC  
FP  
SP  
XXXX XXXXH  
0000 0000H  
Of 16 registers, the following registers are reserved for special application.  
• R13: Virtual accumulator  
• R14: Frame pointer  
• R15: Stack pointer  
Initial values by reset are indeterminate for R0 through R14. Initial value by reset is 00000000 (SSP value)  
H
for R15.  
2. Dedicated Registers  
Dedicated registers consist of program counter (PC), program status (PS), table-base register (TBR), return  
pointer (RP), system stack pointer (SSP), user stack pointer (USP) and multiply & divide register (MDH/MDL).  
Figure 2-1 Dedicated Registers List  
Program counter  
Program status  
Table-base register  
Return pointer  
System stack pointer  
User stack pointer  
Multiply & divide register  
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Chapter 5 CPU Registers  
2.Dedicated Registers  
2.1 PC: Program Counter  
Program Counter (PC) consists of 32 bits.  
Figure 2-2 Bit Structure of Program Counter (PC)  
[Initial value]  
XXXXXXXXH  
0
31  
PC  
Program counter (PC) indicates active instruction address.  
Upon the execution of the instruction, program counter (PC)’s bit 0 is cleared.  
2.2 PS: Program Status Register  
Program status register (PS) is the register to hold program status which consists of three parts including ILM, SCR  
and CCR.  
All undefined bits are reserved bit. Upon the reading, “0” is always read. Writing is invalid.  
Program status register (PS) consists of condition code register (CCR), system condition code register (SCR) and  
interrupt level mask register (ILM).  
Figure 2-3 Bit Structure of Program Status (PS)  
bit  
31  
20  
16  
10  
8 7  
0
SCR  
ILM  
CCR  
■ CCR: Condition Code Register  
Figure 2-4 Structure of Condition Code Register (CCR)  
3
4
I
2
Z
1
0
7
-
6
5
bit  
Initial value  
--00XXXXB  
N
S
V
C
-
• [Bit 5] S: Stack flag  
This bit specifies stack pointer.  
S
Description  
Uses R15 as SSP. Upon generating EIT, this bit automatically becomes “0”.  
(Note that the value saved in stack is the value before clear.)  
0
1
Uses R15 as USP.  
This bit becomes “0” by reset.  
After using R15 as USP, write “0” before executing RETI instruction.  
• [Bit 4] I: Interrupt-enable flag  
This bit enables and disables user interrupt request.  
I
Description  
Disables user interrupt.  
0
Upon executing INT instruction, this bit becomes “0”.  
(Note that the value saved in stack is the value before clear.)  
Enables user interrupt.  
Mask processing of user interrupt request is controlled by the value which is held in ILM.  
1
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Chapter 5 CPU Registers  
2.Dedicated Registers  
This bit becomes “0” by reset.  
• [Bit 3] N: Negative flag  
This bit indicates the sign when operation results is deemed as integer represented by two’s-complement numbers.  
N
0
Description  
It indicates that operation result is positive value.  
It indicates that operation result is negative value.  
1
• [Bit 2] Z: Zero flag  
It indicates whether operation result is 0 or not.  
Z
Description  
It indicates that operation result is other than 0.  
It indicates that operation result is 0.  
0
1
• [Bit 1] V: Overflow flag  
This bit deems that operand used for operation as integer represented by two’s-complement numbers, and indicates  
whether overflow was generated or not as the result of operation results.  
V
0
Description  
It indicates that overflow was not generated as the result of operation.  
It indicates that overflow was generated as the result of operation.  
1
• [Bit 0] C: Carry flag  
This bit indicates whether carry or borrow from highest-order bit was generated or not as the result of operation.  
Value  
Description  
It indicates that neither carry nor borrow is generated.  
It indicates that either carry or borrow is generated.  
0
1
■ SCR: System Condition Code Register  
Figure 2-5 Structure of System Condition Code Register (SCR)  
10  
9
8
T
[Initial value]  
XX0  
D1 D0  
B
SCR  
This section describes each bit structure of system condition code register (SCR).  
• [Bit 10, 9] D1 and D0: Step division flag  
D1 and D0 bits hold intermediate data during the execution of step division.  
Do not modify data during the execution of division processing.  
If other processes is executed during the execution of step division, step division is assured to be restarted by saving  
and returning PS register value.  
Initial status by reset is indeterminate for D1 and D0 bits.  
Upon executing DIV0S instruction, these bits are set by referring to dividend and divisor.  
Upon executing DIV0U instruction, these bits mandatorily become “00”.  
• [Bit 8] T: Step trace trap flag  
This bit is the flag to specify whether to enable step trace trap or not.  
T value  
Description  
0
Disables step trace trap.  
Enables step trace trap.  
In this case, all user interrupts are disabled.  
1
This bit is initialized to “0” by reset.  
The function of step trace trap is used for emulator. During the use of emulator, you cannot use this bit for user  
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Chapter 5 CPU Registers  
2.Dedicated Registers  
program.  
■ ILM: Interrupt Level Mask Register  
Figure 2-6 Register Structure of Interrupt Level Mask Register (ILM)  
20 19 18 17 16 [Initial value]  
01111  
B
ILM4 ILM3 ILM2 ILM1 ILM0  
• This is the register to hold interrupt level mask value. This bit uses the value held in ILM as level mask.  
• ILM indicates corresponding interrupt level from interrupt requests entered in CPU.  
• Interrupt requests are accepted only if it’s priority is higher than the level.  
• For level value, the highest priority is 0 (00000 ), and the lowest priority is 31 (11111 ).  
B
B
• Program has some restrictions on configurable data.  
•
When original value is between 16 and 31,  
Configurable new values are the value between 16 and 31.  
If you execute the instruction to set the value between 0 and 15, “specified value +16” value is set.  
When original value is between 0 and 15,  
•
You can set any value between 0 and 31.  
These values are initialized to 15 (01111 ) by reset.  
B
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Chapter 5 CPU Registers  
2.Dedicated Registers  
■ Caution: PS Register  
Since some instructions have already processed PS register in advance, the following exception operations may break  
interrupt processing routine during the use of debugger, or update PS flag data.  
In either cases, after returning from EIT, it is designed to execute the correct process so that operations before and  
after EIT will be processed in accordance with specification.  
• At instruction right before DIV0U/DIV0S instruction, the following 1. to 3. operation may be executed.  
• If user interrupt is received,  
• If step execution is executed,  
• If data event or emulator menu is broken,  
1. D0 or D1 flag is updated in first.  
2. EIT processing routine (user interrupt or emulator) is executed.  
3. After returning from EIT, it executes DIV0U/DIV0S instruction and updates D0/D1 flag to the same value  
as 1.  
• When user interrupt is generated, if you execute each instruction of ORCCR, STILM, MOV Ri or PS to  
enable interrupt, the following operations are generated.  
1. Updates PS register in first.  
2. Executes EIT processing routine (user interrupt).  
3. After returning from EIT, executes the instruction above and updates PS register to the same value as  
1.  
Note: For EIT, See “Chapter 6 EIT: Exceptions, Interrupts and Traps (Page No.121)”.  
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Chapter 5 CPU Registers  
2.Dedicated Registers  
2.3 TBR: Table-base Register  
Table-base register (TBR) consists of 32 bits.  
Figure 2-7 Bit Structure of Table-base Register (TBR)  
31  
0
[Initial value]  
000FFC00H  
TBR  
Table-base register holds head address of vector table used for EIT processes.  
Vector address is made by adding offset value specified in TBR and EIT each.  
2.4 RP: Return Pointer  
Return pointer (RP: Return Pointer) consists of 32 bits.  
Figure 2-8 Bit Structure of Return Pointer (RP)  
[Initial value]  
XXXXXXXXH  
31  
0
RP  
Return pointer (RP) holds addresses returned from sub routines.  
Upon executing CALL, PC values are set in this RP.  
Upon executing RET, RP data are set in this PC.  
2.5 SSP: System Stack Pointer  
System stack pointer (SSP) is used for the pointer which receives EIT and indicates stack to save/return data for return  
operation.  
System stack pointer (SSP) consists of 32 bits.  
Figure 2-9 Bit Structure of System Stack Pointer (SSP)  
[Initial value]  
00000000H  
0
31  
SSP  
When S flag is “0”, it works as R15. You can explicitly specify SSP.  
Upon generating EIT, it is used for the pointer which specifies the stack to save PS and PC.  
During the EIT process, this pointer reduces the value by 8, and adds 8 to the value during the return from EIT by  
executing RETI instruction.  
System stack pointer (SSP) works as general-purpose register R15 when S flag within CCR is “0”.  
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Chapter 5 CPU Registers  
2.Dedicated Registers  
2.6 USP: User Stack Pointer  
User Stack Pointer (USP) consists of 32 bits.  
Figure 2-10 Bit Structure of User Stack Pointer (USP)  
[Initial value]  
00000000H  
31  
0
USP  
When S flag is “1”, this pointer works as R15.  
You can explicitly specify USP.  
You can not use it for RETI instruction.  
This pointer saves and returns PC and PS values at the position where system stack pointer (SSP) indicates. After  
interrupt, it stores PC in address where SSP indicates, and PS in (SSP+4) address.  
Figure 2-11 Interrupt Stack  
[Before interrupt]  
80000000H  
Memory  
[After interrupt]  
7FFFFFF8H  
[Example]  
SSP  
SSP  
80000000H  
7FFFFFFCH  
7FFFFFF8H  
80000000H  
7FFFFFFCH  
7FFFFFF8H  
PS  
PC  
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Chapter 5 CPU Registers  
2.Dedicated Registers  
2.7 MDH, MDL: Multiply & Divide Register  
Multiply & Divide register (MDH/MDL) consists of 32 bits.  
Figure 2-12 Bit Structure of Multiply & Divide Register (MDH/MDL)  
31  
0
MDH  
MDL  
This is the register for multiplication and division and consists of 32 bits.  
Initial value by reset is indeterminate.  
■ At the executing multiplication  
When 32 bits x 32 bits multiplication, operation results of 64 bits are stored in multiplication/division store register as  
the following allocation.  
• MDH: Upper 32 bits  
• MDL: Lower 32 bits  
When 16 bits x 16 bits multiplication, results are stored as follows.  
• MDH: Indeterminate.  
• MDL: Results of 32 bits  
■ At the executing division  
Upon starting operation, dividend is stored in MDL.  
By computing division by executing DIV0S/DIV0U, DIV1, DIV2, DIV3, or DIV4S instruction, results are stored in MDL  
and MDH.  
• MDH: Remainder  
• MDL: Quotient  
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Chapter 6 EIT: Exceptions, Interrupts and Traps  
1.Overview  
Chapter 6 EIT: Exceptions, Interrupts and Traps  
1. Overview  
EIT means that some events interrupt current program to execute other programs. EIT stands for Exception,  
Interrupt and Trap.  
• Exception is  
the event which is generated in association with active context. It is returned to the instruction which triggered the  
exception.  
• Interrupt is  
the event which is generated regardless of active context. Interrupt is triggered by hardware.  
• Trap is  
the event which is generated in association with active context. Some trap is specified by program such as system call.  
It is returned to the instruction following the instruction which triggered the trap.  
2. Features  
• Supports multiple interrupts.  
• Level mask function for interrupt (User can use 15 level.)  
• Trap instruction (INT)  
• EIT for emulator trigger (hardware/software)  
3. EIT Trigger  
• Reset  
• User interrupt (peripheral function and external interrupt)  
• Delayed interrupt  
• Undefined-instruction exception  
• Trap instruction (INT)  
• Trap instruction (INTE)  
• Step trace trap  
• Coprocessor absent trap  
• Coprocessor error trap  
• CPU supervisor mode  
• Memory protection violation  
4. Return from EIT  
To return from EIT, use RETI instruction.  
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Chapter 6 EIT: Exceptions, Interrupts and Traps  
5.EIT Interrupt Level  
5. EIT Interrupt Level  
Interrupt level is between 0 and 31, and controlled with 5 bits.  
Table 5-1 Interrupt Level of EIT  
Level  
Description  
Remarks  
Binary  
Decimal  
00000  
...  
...  
0
...  
...  
3
(Reserved for system)  
...  
...  
00011  
(Reserved for system)  
00100  
4
INTE instruction  
Step trace trap  
If original value of ILM is between 16 and 31, these  
values are not configurable to ILM by program.  
00101  
...  
...  
5
...  
...  
14  
(Reserved for system)  
...  
...  
01110  
(Reserved for system)  
01111  
15  
NMI (for users)  
10000  
10001  
...  
...  
11110  
11111  
16  
17  
...  
...  
30  
31  
Interrupt  
Interrupt  
...  
When ILM is set, user Interrupt is disabled.  
When ICR is set, Interrupt is disabled.  
...  
Interrupt  
N/A  
Only 16 through 31 levels are operable.  
Undefined-instruction exception, coprocessor absent trap, coprocessor error trap and INT instruction are not  
affected by interrupt level. Also, ILM is not changed by interrupt level.  
6. EIT Vector Table  
For EIT vector table, see the chapter of “3. Interrupt Vector Table (Page No.73)”.  
Vector for EIT is between address which table-base register [TBR] indicates and a 1 kByte area.  
Its size is 4 bytes per one vector. For vector number/vector address/trigger, see “3. Interrupt Vector Table  
(Page No.73)”.  
Address arithmetic is as follows.  
Vector address = [TBR] + Offset value = [TBR] + {03FC - 4 x Vector number (No.)}  
H
Lower two bits as the result of addition are always used for “00”.  
000FFC00 through 000FFFFF areas are initial values of vector table by reset.  
H
H
If you rewrite the TBR value, the mode and reset vectors always use the fixed address of 000FFFF8 ,  
H
000FFFFC .  
H
122  
   
Chapter 6 EIT: Exceptions, Interrupts and Traps  
7.Multiple EIT Processing  
7. Multiple EIT Processing  
If multiple EITs are generated at the same time, CPU repeats the operation which selects one of the EIT to  
accept, and then executes EIT sequence, and detects EIT again. If there is no EIT to accept upon detecting  
EIT, CPU executes instruction of the last accepted EIT handler. Therefore, if multiple EITs are generated at  
the same time, execution sequence of each EIT handler is determined by the following two parameters.  
■ Priority Level of Receipt of EIT Triggers  
Priority level of receipt of EIT triggers means the sequence to select which EIT triggers to execute by saving  
PS and PC in order to update PC and masking other triggers where appropriate.  
EIT does not always mean first-in first-out handler.  
Table 7-1 Priority Level of Receipt of EIT Triggers and Mask for Other Triggers  
Priority for accepting EITs  
EIT  
Masking of other EITs  
All EITs are cleared  
1
2
Reset  
Instruction Break  
INTE instruction  
Other EITs are canceled (ILM = 4)  
Other EITs are canceled (ILM = 4)  
Other EITs are canceled (I-flag = 0)  
3
4
Undefined instruction exception  
5
INT instruction / Coprocessor exceptions I-flag = 0  
6
Memory protection violation  
User interrupt  
I-flag = 0  
7
ILM = level of accepted INT  
ILM = 15  
8
NMI (user)  
9
NMI (emulator)  
Step Trace trap  
Operand Break  
Other EITs are canceled (ILM = 4)  
Other EITs are canceled (ILM = 4)  
Other EITs are canceled (ILM = 4)  
10  
11  
■ How to Mask Other Triggers upon the Receipt  
Table below shows the execution sequence of each handler for multiple EIT triggers generated at the same  
time when considering mask processes for other triggers upon the receipt of EIT triggers.  
Table 7-2 Execution Sequence of EIT Handlers  
Handler execution Priority  
EIT  
Masking of other EITs  
All EITs are cleared  
1
2
Reset  
Undefined instruction exception  
Instruction Break  
INTE instruction  
Other EITs are canceled (I-flag = 0)  
Other EITs are canceled (ILM = 4)  
Other EITs are canceled (ILM = 4)  
Other EITs are canceled (ILM = 4)  
Other EITs are canceled (ILM = 4)  
Other EITs are canceled (ILM = 4)  
ILM = 15  
3
4
5
NMI (emulator)  
6
Step Trace trap  
7
Operand Break  
8
NMI (user)  
9
Memory protection violation  
I-flag = 0  
10  
11  
INT instruction / Coprocessor exceptions I-flag = 0  
User interrupt ILM = level of accepted INT  
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Chapter 6 EIT: Exceptions, Interrupts and Traps  
7.Multiple EIT Processing  
Figure 7-1 Multiple EITs Process  
NMI handler  
Main routine  
INT instruction  
handler  
(1) First execution  
User interrupt  
handler  
Priority  
(High) Generation of NMI  
(2) Second execution  
(Middle) Execution of INT instruction  
(Low) Execution of user interrupt  
(3) Third execution  
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Chapter 6 EIT: Exceptions, Interrupts and Traps  
8.Operation  
8. Operation  
In the following sections, note that source “PC” means instruction address which detected each EIT trigger.  
Similarly, “address of next instruction” means the following addresses based on the instruction which detected  
the EIT.  
• When LDI is 32: PC+6  
• When LDI is 20, and it is COPOP, COPLD, COPST or COPSV: PC+4  
• For other instructions: PC+2  
8.1 User Interrupt operation  
If user interrupt request occurs, it determines whether to receive its request or not in the following sequence.  
■ How to determine whether to receive interrupt request or not  
1. Selects the interrupt which holds the highest priority level (the smallest number) by comparing interrupt  
request levels generated at the same time.  
For the level to be compared, it uses the value which ICR holds corresponding to maskable interrupt.  
2. Selects the interrupt request which has the earliest interrupt number if multiple interrupt requests with the  
same priority level are generated.  
>
3. Where “Interrupt level  
Level mask value”, the interrupt request is masked without receipt. Where  
=
“Interrupt level < Level mask value”, it goes forward to Step 4.  
4. When selected interrupt request is maskable interrupt, if I flag is 0, its Interrupt request is masked without  
receipt and if I flag is 1, it goes forward to Step 5.  
5. If conditions above are satisfied, interrupt requests are received between instruction processes.  
If user interrupt requests are received upon detecting EIT requests, CPU executes the following operations  
according to the Interrupt number for the interrupt request received.  
■ Operation  
1. The contents of the program status (PS) are saved to the system stack.  
2. The address of the next instruction is saved to the system stack.  
3. The value of the system stack pointer (SSP) is reduced by 8.  
4. The value (level) of the accepted interrupt is stored in the “ILM”.  
5. The value “0” is written to the “S” flag in the condition code register (CCR) in the program status (PS).  
6. The vector address of the accepted interrupt is stored in the program counter (PC).  
After the interrupt sequence, EIT is checked again before executing the main program handler’s instruction. If  
any receivable EIT is generated at this time, the CPU goes to EIT process sequence.  
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Chapter 6 EIT: Exceptions, Interrupts and Traps  
8.Operation  
8.2 Operation of INT Instruction  
INT No. u8 instruction is operated as follows.  
Branches to interrupt handler of vector specified in u8.  
■ Operation  
1. The contents of the program status (PS) are saved to the system stack.  
2. The address of the next instruction is saved to the system stack.  
3. The value of the system stack pointer (SSP) is reduced by 8.  
4. The value “0” is written to the “I” flag in the condition code register (CCR) in the program status (PS).  
5. The value “0” is written to the “S” flag in the condition code register (CCR) in the program status (PS).  
6. The value ‘TBR+3FC -4 x u8’ is stored in the program counter (PC).  
H
8.3 Operation of INTE Instruction  
INTE instruction is operated as follows.  
Branches to vector interrupt handler of vector number 9.  
■ Operation  
1. The contents of the program status (PS) are saved to the system stack.  
2. The address of the next instruction is saved to the system stack.  
3. The value of the system stack pointer (SSP) is reduced by 8.  
4. The value (level) “4” is stored in the “ILM”.  
5. The value “0” is written to the “S” flag in the condition code register (CCR) in the program status (PS).  
6. The value ‘TBR+3D8 ’ is stored in the program counter (PC).  
H
During the execution of step, EIT is not generated by INTE.  
Since INTE instruction is used for the device, do not use it.  
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Chapter 6 EIT: Exceptions, Interrupts and Traps  
8.Operation  
8.4 Operation of Step Trace Trap  
If you set T flag at SCR within PS and enable step trace trap function, step trace trap is generated with each  
executing instruction.  
■ Condition for detecting step trace trap  
T flag = 1  
Instructions are other than delayed branch command.  
During the execution of instructions other than INTE instructions or step trace trap process routines.  
If conditions above are satisfied, it is broken between instruction operations.  
■ Operation  
1. The contents of the program status (PS) are saved to the system stack.  
2. The address of the next instruction is saved to the system stack.  
3. The value of the system stack pointer (SSP) is reduced by 8.  
4. The value (level) “4” is stored in the “ILM”.  
5. The value “0” is written to the “S” flag in the condition code register (CCR) in the program status (PS).  
6. The value ‘TBR+3CC ’ is stored in the program counter (PC).  
H
If you set T flag to enable step trace trap, user interrupt is disabled.  
In addition, EIT will not be generated by INTE instruction.  
FR60 generates traps from next instruction to instruction which set T flag.  
8.5 Operation of Undefined-instruction Exception  
If any undefined instruction is detected upon decoding instruction, undefined-instruction exception is  
generated.  
■ Condition for detecting undefined-instruction exception  
• Upon the decoding instruction, undefined instruction is detected.  
• It is out of delayed slot. (It is not the instruction which is right after delay branch instruction.)  
If conditions above are satisfied, undefined-instruction exception will be generated.  
■ Operation  
1. The contents of the program status (PS) are saved to the system stack.  
2. The address of the instruction that caused the undefined instruction exception is saved to the system stack.  
3. The value of the system stack pointer (SSP) is reduced by 8.  
4. The value “0” is written to the “S” flag in the condition code register (CCR) in the program status (PS).  
5. The value ‘TBR+3C4 ’ is stored in the program counter (PC).  
H
Address of the instruction which detected undefined-instruction exception is saved as PC.  
127  
Chapter 6 EIT: Exceptions, Interrupts and Traps  
9.Caution  
8.6 Coprocessor Absent Trap  
If you execute coprocessor instruction for unmounted coprocessor, coprocessor absent trap is generated.  
■ Operation  
1. The contents of the program status (PS) are saved to the system stack.  
2. The address of the instruction that caused the undefined instruction exception is saved to the system stack.  
3. The value of the system stack pointer (SSP) is reduced by 8.  
4. The value “0” is written to the “S” flag in the condition code register (CCR) in the program status (PS).  
5. The value ‘TBR+3E0 ’ is stored in the program counter (PC).  
H
8.7 Coprocessor Error Trap  
If error occurs during the use of coprocessor, coprocessor error trap is generated when you execute  
coprocessor instruction in order to operate the coprocessor next time.  
■ Operation  
1. The contents of the program status (PS) are saved to the system stack.  
2. The address of the instruction that caused the undefined instruction exception is saved to the system stack.  
3. The value of the system stack pointer (SSP) is reduced by 8.  
4. The value “0” is written to the “S” flag in the condition code register (CCR) in the program status (PS).  
5. The value ‘TBR+3DC ’ is stored in the program counter (PC).  
H
8.8 Operation of RETI Instruction  
RETI instruction is the instruction which returns from EIT process routine.  
■ Operation  
1. Load data from stack indicated by (R15)* to the program counter (PC).  
2. Increment R15+4 and store to R15.  
3. Load data from stack indicated by (R15)* to the program status (PS).  
4. Increment R15+4 and store to R15.  
RETI instruction should be executed with S flag “0”.  
9. Caution  
• Since INTE instruction is used for the Debug Support Unit (DSU), do not use it in any application.  
• Delay slot for branch instruction has restrictions on EIT.  
See “Chapter 7 Branch Instruction (Page No.129)”.  
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Chapter 7 Branch Instruction  
1.Branch Instruction with Delay Slot  
Chapter 7 Branch Instruction  
FR60 can instruct the operation with and without delay slot for branch instruction.  
1. Branch Instruction with Delay Slot  
• Branch instruction with delay slot  
JMP:D @Ri  
BRA:D label9  
BC:D label9  
BV:D label9  
BLE:D label9  
CALL:D label12  
BNO:D label9  
BNC:D label9  
BNV:D label9  
BGT:D label9  
CALL:D @Ri  
BEQ:D label9  
BN:D label9  
BLT:D label9  
BLS:D label9  
RET:D  
BNE:D label9  
BP:D label9  
BGE:D label9  
BHI:D label9  
2. Operation of Branch Instruction with Delay Slot  
Operation with delay slot executes the instruction located in the next address where a branch instruction exists  
(referred to as delay slot) and then branches before executing branched instructions.  
Since it executes delay slot instruction before branch operation, apparent execution rate becomes 1 cycle.  
Instead, if delay slot has no valid instruction, NOP instruction must be entered.  
• Example  
;
Sequence of instruction  
ADD R1 R2  
BRA:D LABEL  
;
; Branch instruction  
MOV  
...  
R2  
R3 ; Delay slot ...... To be executed before the branch.  
LABEL : ST  
R3  
@R4 ; Branched instruction  
In conditional branch instruction, regardless of whether branch parameter is approved or not, instructions  
located in delay slot are executed.  
In delay branch instruction, execution sequence of some instructions seems opposite, however, it only applies  
to updating process on the PC. Any other operation (register update/look-up) is executed in the order of  
description.  
129  
       
Chapter 7 Branch Instruction  
3.Actual Example (with Delay Slot)  
3. Actual Example (with Delay Slot)  
3.1 JMP:D @Ri / CALL:D @Ri Instruction  
Ri referred in JMP:D @Ri / CALL:D @Ri instruction remains intact even if instructions within delay  
slot update Ri.  
• Example  
LDI:32  
JMP:D  
LDI:8  
...  
#Label,  
@R0  
#0,  
R0  
; Branches to Label.  
R0 ; Not affect any branched address.  
3.2 RET:D Instruction  
RP referred in RET:D instruction remains intact even if instructions within delay slot update RP.  
• Example  
RET:D  
MOV  
...  
; Branches to the address previously specified in RP.  
RP ; Not affect any return operation.  
R8,  
3.3 Bcc:D rel Instruction  
Flag referred in Bcc:D rel instruction also remains unaffected by instructions within delay slot.  
• Example  
ADD  
BC:D  
ANDCCR #0  
...  
#1,  
Overflow  
R0 ; Change of flag  
; Branches in accordance with the execution result of instructions above.  
; This flag update is not referred in branch instruction above.  
3.4 CALL:D Instruction  
When RP is referred using the instruction within delay slot of CALL:D instruction, the data updated  
by CALL:D instruction is read out.  
• Example  
CALL:D Label  
; Branches by updating RP.  
MOV  
...  
RP,  
R0 ; Transfers RP based on the execution results of CALL: D above.  
130  
 
Chapter 7 Branch Instruction  
4.Restrictions on Branch Instruction with Delay Slot  
4. Restrictions on Branch Instruction with Delay Slot  
4.1 Available Instructions for Delay Slot  
Instructions which meet the following requirements can only be executed in delay slot.  
• 1-cycle instruction  
• Non-branch instruction  
• Instruction which does not affect any operation even if its sequence is changed.  
“1-cycle instruction” indicates instructions whose number of cycles column in the instruction list table is  
described with “1”, “a”, “b”, “c” or “d”.  
4.2 Step Trace Trap  
Step trace trap is not generated between the execution of branch instruction with delay slot and delay slot.  
4.3 Interrupt  
Interrupt is not acceptable between the execution of branch instruction with delay slot and delay slot.  
4.4 Undefined-instruction Exception  
If undefined instruction exists in delay slot, undefined instruction-exception is not generated. In this case,  
undefined instruction works as NOP instruction.  
131  
 
Chapter 7 Branch Instruction  
5.Branch Instruction without Delay Slot  
5. Branch Instruction without Delay Slot  
• Branch instruction without delay slot:  
JMP @Ri  
CALL label12  
BNO label9  
BNC label9  
BNV label9  
BGT label9  
CALL @Ri  
BEQ label9  
BN label9  
BLT label9  
BLS label9  
RET  
BRA label9  
BC label9  
BV label9  
BLE label9  
BNE label9  
BP label9  
BGE label9  
BHI label9  
6. Operation of Branch Instruction without Delay Slot  
Operation without delay slot executes instructions in the order of instructions and never executes  
the instruction located in the next address where a branch instruction exists before branch.  
• Example  
;
Sequence of instruction  
ADD R1 R2  
BRA:D LABEL  
;
; Branch instruction (without delay slot)  
MOV  
...  
R2  
R3 ; Not to be executed.  
LABEL ST  
R3  
@R4 ; Branched instruction  
The number of execution cycles of branch instruction without delay slot is 2 cycles for branch and 1  
cycle for no branch.  
Unlike the branch instruction with delay slot where NOP is described because appropriate  
instruction cannot be entered, it can increase efficiency of instruction code.  
Select the operation with delay slot when valid instruction can be set in delay slot. Otherwise select  
the operation without delay slot. This selection enables FR60 to satisfy both of execution rate and  
code efficiency.  
132  
   
Chapter 8 Device State Transition  
1.Overview  
Chapter 8 Device State Transition  
1. Overview  
MB91460 basically has devices state and flow as shown below.  
For more information, see “3. State Transition Diagram (Page No.134)”.  
Status transition  
Power-on  
Watchdog reset  
INITX  
INT-pin input  
Setting-initialization reset  
Oscillation-stabilization  
wait reset  
Operation-initialization  
reset  
Software-reset instruction  
Run  
Oscillation-stabilization RUN  
Interrupt request  
Sleep  
Stop  
Interrupt request  
2. Features  
■ Device state  
• RUN (Normal operation): State where the program is executed.  
• SLEEP: State where the program is stopped (peripheral circuits are operating).  
• STOP: State where the device is stopped.  
• Oscillation-stabilization-wait RUN: State to return from the STOP to the RUN state (waiting until clock  
oscillation is stabilized).  
• Oscillation-stabilization-wait reset: State for waiting until the clock oscillation is stabilized after INIT.  
• Operation-initialization reset (RST): State where the program is initialized.  
• Setting-initialization reset (INIT): State where all settings are initialized.  
■ Standby mode (Low-power-consumption mode)  
SLEEP and STOP above are standby modes.  
133  
     
Chapter 8 Device State Transition  
3.State Transition Diagram  
3. State Transition Diagram  
This section describes state transition.  
Figure 3-1 State Transition of MB91460 Series  
1
2
3
4
5
6
7
8
pin = 0 (INIT)  
pin = 1 (Cancel of INIT)  
Termination of oscillation-stabilization wait  
Cancel of reset (RST)  
Software reset (RST)  
Sleep (Writing instruction)  
Stop (Writing instruction)  
Interrupt  
INIT  
INIT  
Priority of transition request  
Setting-initialization reset (INIT)  
Termination of oscillation-stabilization wait  
Operation-initialization reset (RST)  
Interrupt request  
Highest  
priority  
Power-on  
1
Stop  
Sleep  
Lowest  
priority  
9
External interrupt requiring no clock  
Switching from main to sub (Writing instruction)  
Switching from sub to main (Writing instruction)  
Watchdog reset (INIT)  
10  
11  
12  
13  
Setting initialization  
(INIT)  
Sub-sleep (Writing instruction)  
2
Main clock mode  
1
Oscillation-  
stabilization-  
wait reset  
Main stop  
1
1
9
3
1
Program reset  
(RST)  
Oscillation-  
stabilization-wait RUN  
3
4
7
5
Main RUN  
1
12  
1
Main sleep  
6
8
10  
Subclock mode  
11  
1
1
1
8
12  
1
Sub-RUN  
Sub-sleep  
13  
7
5
3
4
Oscillation-  
Program reset  
(RST)  
stabilization-wait RUN  
MB91460 does not stop  
oscillation while waiting  
time is generated.  
1
9
Sub-stop *  
* To switch clock source between main and sub, in the RUN status where switched clock is stable,  
switch clock source register (CLKR) between bit 1 and 0 (CLKS1 and CLKS0 bit).  
134  
 
Chapter 8 Device State Transition  
3.State Transition Diagram  
3.1 RUN (Normal Operation)  
This is the state where program is executed with all clocks and all circuits are enabled.  
This state has various paths for a state transition. However, if the synchronous reset mode is selected the  
state transition operations for some requests are different from normal reset mode. For more information, see  
the chapter of “Chapter 9 Reset (Page No.139)”.  
3.2 SLEEP  
This is the state where only the CPU's program execution is stopped and the peripheral circuits are operating.  
Embedded memories and internal/external buses are stopped unless the DMA controller requests them. This  
state is entered by program operation.  
•
Upon generation of valid interrupt requests the SLEEP state is cancelled and the RUN mode (Normal  
operation) is entered.  
Upon generation of the setting-initialization reset request by the external INITX pin the setting-initialization  
reset state (INIT) is entered.  
Upon generation of the operation-initialization reset request (external RSTX or software reset) the  
operation-initialization reset state (RST) is entered.  
•
•
3.3 STOP  
All internal circuits are stopped, all internal clocks and the PLL is stopped. Main/Sub oscillation and RC  
oscillation (which can be connected to the Real Time Clock (RTC) can be stopped by setting the related  
registers). This state is entered by program operation.  
Additionally high impedance for external pins can be enabled by setting the related register.  
•
Upon generation of specific valid interrupt requests (requiring no clock), active oscillation timer interrupt or  
main clock oscillation stabilization timer interrupt request the oscillation stabilization wait RUN state is entered.  
Upon generation of the setting-initialization reset request by the external INITX pin the setting-initialization  
reset state (INIT) is entered.  
Upon generation of the operation-initialization reset request (external RSTX or software reset) the  
•
•
operation-initialization reset state (RST) is entered.  
The Real Time Clock (RTC) can be supplied in the STOP mode with either main or sub oscillation clock, if the  
control bits for oscillation disable (OSCDx of the STCR register) are not set to disable.  
The Real Time Clock (RTC) can be supplied in the STOP mode with the RC oscillation clock, if the control bit  
for oscillation enable (RCE of the CSVCR register) is not set to disable.  
3.4 Oscillation-stabilization-wait RUN  
All internal circuits are stopped except for clock generation control parts (timebase counter and device state  
control parts). All internal clocks are stopped while oscillation circuits and enabled main PLL is operated. This  
state is entered automatically after the return from STOP.  
•
•
High-impedance control of external pins by STOP is cancelled.  
After the configured oscillation-stabilization-wait time has passed the RUN (Normal operation) state is  
entered.  
•
Upon generation of the setting-initialization reset request by the external INITX pin the setting-initialization  
reset state (INIT) is entered.  
•
Upon generation of the operation-initialization reset request (external RSTX or software reset) the  
operation-initialization reset state (RST) is entered.  
135  
Chapter 8 Device State Transition  
3.State Transition Diagram  
3.5 Oscillation-stabilization-wait Reset  
This is the state where the device is stopped. This state is entered upon a setting-initialization reset  
(INIT).  
All internal circuits are stopped except for clock generation control parts (timebase counter and  
device state control parts). All internal clocks are stopped while oscillation circuits and main PLL (if  
enabled) are operating.  
•
•
•
High-impedance control of external pins by STOP is cancelled.  
For internal circuits this state outputs operation-initialization reset (RST).  
After configured oscillation-stabilization-wait time has passed the oscillation-stabilization-wait  
reset state is entered.  
•
Upon generation of the setting-initialization reset request by the external INITX pin the setting-  
initialization reset state (INIT) is entered.  
3.6 Operation-initialization Reset (RST)  
This is the state where the program execution is initialized. Upon receipt of the operation-  
initialization reset (external RSTX pin or software reset) request or the termination of the oscillation-  
stabilization-wait reset (RST) this state is active.  
CPU’s program is stopped and program counter is initialized. All peripheral circuits are initialized  
except for some peripheral circuits. All internal clocks, oscillation circuits and enabled main PLL are  
operating.  
•
•
For internal circuits this state asserts operation-initialization reset (RST).  
Upon clear of request of operation-initialization reset (RST) this state transits to the RUN  
(normal operation) state and executes the operation-initialization reset sequence. Upon returning  
from setting-initialization reset (INIT) this state executes the setting-initialization reset sequence.  
•
Upon generation of the setting-initialization reset request by the external INITX pin the setting-  
initialization reset state (INIT) is entered.  
3.7 Setting-initialization Reset (INIT)  
This is the state where all settings are initialized. Upon receipt of request of setting-initialization  
reset (INIT) this state is active.  
CPU’s program is stopped and program counter is initialized. All peripheral circuits are initialized.  
Oscillation circuits are operating while the main PLL is stopped. All internal clocks are operating  
except while “L” level is input to the external INITX pin.  
•
For internal circuits this state asserts the setting-initialization reset (INIT) and the operation-  
initialization reset (RST).  
Upon clear of the setting-initialization reset (INIT) request this state cancels the setting-  
•
initialization reset state and then enters to the oscillation-stabilization-wait reset. After that it  
executes the operation-initialization reset sequence.  
3.8 Priority of Each Request of State Transition  
In any state, each request of the state transition is subject to the following priority:  
[Highest  
priority]  
Request of setting-initialization reset (INIT)  
Termination of oscillation-stabilization-wait time (This is generated only in status of  
oscillation-stabilization-wait reset and oscillation-stabilization-wait RUN.)  
Request of operation-initialization reset (RST)  
Request of valid interrupt (This is generated only in RUN, sleep or stop status.)  
Request of stop mode (Writing in register) (This is generated only in RUN status.)  
Request of sleep mode (Writing in register) (This is generated only in RUN status.)  
[Lowest  
priority]  
136  
Chapter 8 Device State Transition  
3.State Transition Diagram  
137  
Chapter 8 Device State Transition  
3.State Transition Diagram  
138  
Chapter 9 Reset  
1.Overview  
Chapter 9 Reset  
1. Overview  
When a reset is triggered, the device halts the program and all hardware operation, and then initializes all  
states. This state is called a reset.  
When the reset trigger condition is removed, the device changes from this initialized state to restart the  
program and hardware operation. The series of steps from removal of the reset condition until operation starts  
is called the reset cancellation sequence.  
Figure 1-1 Flow of Reset Operation  
Power ON  
INIT pin input  
From any state  
Settings initialization reset  
Watchdog timeout  
Oscillation stabilization  
wait reset  
Operation initialization  
reset  
RUN  
Software reset instruction  
2. Features  
• Types of reset  
• INIT pin input: Settings initialization reset (INIT)  
• RST pin input: Operation initialization reset (RST)  
• HSTX pin input: Settings initialization reset (INIT)  
• Watchdog reset: Settings initialization reset (INIT)*  
• Software reset: Operation initialization reset (RST)  
• Low Voltage reset: Setting initialization reset (INIT)  
*: Although a watchdog reset triggers the same settings initialization reset (INIT) as the INITX pin input, it does  
not initialize the oscillation stabilization time selection bits (OS[1:0]) and reset cause flags (INIT, HSTB, WDOG,  
ERST, SRST and LINIT).  
• Cause of reset can be determined  
• The cause of the previous reset is stored in a series of flags (INIT, HSTB, WDOG, ERST, SRST and  
LINIT) in the RSRR register.  
• Operation after reset condition is removed  
• Operation mode: Determined by the mode pins and mode data.  
139  
       
Chapter 9 Reset  
3.Configuration  
• A settings initialization reset (INIT) is followed by an operation reset (RST) after the oscillation  
stabilization time elapses.  
3. Configuration  
Figure 3-1 Configuration Diagram  
MOD0  
State transition control circuit (reset related)  
MOD1  
MOD2  
SLEEP  
STCR: bit7  
0
1
Do not change to sleep mode  
Change to sleep mode  
Sleep signal  
Stop signal  
STOP  
STCR: bit7  
0
1
Do not change to stop mode  
Change to stop mode  
OSCD1  
STCR:bit1  
Main clock continues to operate during stop mode  
Main clock halts during stop mode  
0
1
State  
transition  
control  
circuit  
Clock control  
HIZ  
STCR: bit0  
0
1
Maintain pin states during stop mode  
Set pins to high impedance during stop mode  
Pin control  
Internal interrupts, external interrupts  
SRST  
STCR: bit4  
Initialization reset (INIT)  
0
1
Trigger software reset  
Do not trigger software reset  
INIT  
Operation reset (RST)  
RSRR:bit7  
No INIT pin input  
INIT  
0
Oscillation stabilization wait ended  
1
INIT pin input occurred  
Clear counter and  
start oscillation  
stabilization wait  
SRST  
RSRR: bit3  
No software reset (RST)  
0
1
Time-base counter  
(oscillation stabilization wait)  
Software reset (RST)occurred  
Watchdog timer  
WDOG  
RSRR: bit5  
0
1
No watchdog timeout  
Watchdog timeout(INIT) occurred  
Figure 3-2 Register List  
RSRR/STCR  
140  
 
Chapter 9 Reset  
4.Registers  
4. Registers  
4.1 RSRR: Reset Cause Register  
Stores the cause of the previous reset, and sets the period and activation control for the watchdog timer.  
• RSRR: Address 0480h (Access: Byte, Half-word)  
7
6
5
4
3
2
1
0
bit  
INIT  
HSTB  
WDOG  
ERST  
SRST  
LINIT  
WT1  
WT0  
Initial value  
(INIT pin input)  
1
-
0
-
0
-
0
0
0
-
0
0
0
0
Initial value  
(Watchdog reset)  
X
X
Initial value  
(Software reset)  
X
X
X
-
-
X
0
0
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/W  
R/W  
Attribute  
Note: See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.  
Reading the reset request cause returns the reset cause flags and then clears the flag values to “0”.  
If multiple resets occur prior to reading the register, the resulting flag values contain the bitwise OR of the flags  
for each reset. That is, more than one flag may be set to “1”.  
• Bit7: Initialization reset occurred flag  
Indicates whether a reset (INIT) was triggered by INIT pin input.  
INIT  
Meaning  
No INIT has been triggered by the INIT pin input.  
INIT has been triggered by the INIT pin input.  
0
1
The initialization reset occurred flag (INIT) is cleared to “0” after reading.  
• Bit6: Hardware Standby reset occurred flag  
Indicates whether a reset (INIT) was triggered by HST pin input.  
HSTB  
Meaning  
No INIT has been triggered by the HST pin input.  
INIT has been triggered by the HST pin input.  
0
1
The hardware standby reset occurred flag (HSTB) is cleared to “0” after reading.  
• Bit5: Watchdog reset occurred flag  
Indicates whether a reset (INIT) was triggered by the watchdog timer.  
WDOG  
Meaning  
No INIT has been triggered by the watchdog timer.  
INIT has been triggered by the watchdog timer.  
0
1
The watchdog reset occurred flag (WDOG) is cleared to “0” after reading.  
• Bit4: External reset occurred flag  
Indicates whether a reset (RST) was triggered by the RST pin input.  
ERST  
Meaning  
No RST has been triggered by the RST pin input.  
RST has been triggered by the RST pin input.  
0
1
The external reset occurred flag (ERST) is cleared to “0” after reading.  
• Bit3: Software reset occurred flag  
141  
 
Chapter 9 Reset  
4.Registers  
Indicates whether a software reset has been triggered by writing to the software reset bit (STCR.SRST).  
SRST Meaning  
No RST has been triggered by a software reset.  
RST has been triggered by a software reset.  
0
1
The software reset occurred flag (SRST) is cleared to “0” after reading.  
• Bit2: Low voltage reset occurred flag  
Indicates whether a reset (INIT) was triggered by the low voltage detection.  
LINIT  
Meaning  
No INIT has been triggered by the low voltage detection.  
INIT has been triggered by the low voltage detection.  
0
1
The low voltage reset occurred flag (LINIT) is cleared to “0” after reading.  
• Bit1-0: Watchdog period selection  
The watchdog period selection bits (WT[1:0]) can set the period of the watchdog timer to the following:  
20  
21  
22  
23  
24  
25  
26  
27  
(F x 2 to 2 , F x 2 to 2 , F x 2 to 2 , F x 2 to 2  
)
See “Chapter 20 Software Watchdog Timer (Page No.273)” for details.  
142  
Chapter 9 Reset  
4.Registers  
4.2 STCR: Standby Control Register  
This register is used for software reset control (changing to standby mode, pin control in stop mode, and clock  
oscillation halted in stop mode), and specifies the oscillation stabilization wait time.  
Note: See also “Chapter 10 Standby (Page No.155)”.  
• STCR: Address 0481h (Access: Byte, Half-word)  
7
6
5
4
3
2
1
0
bit  
STOP  
SLEEP  
HIZ  
SRST  
OS1  
OS0  
OSCD2  
OSCD1  
Initial value  
(INIT pin input)  
0
0
0
0
1
1
1
1
0
0
1
1
1
1
Initial value  
(Watchdog reset)  
X
X
Initial value  
(Software reset)  
0
0
X
1
X
X
X
X
R/W  
R/W  
R/W  
R1,W  
R/W  
R/W  
RX/WX  
R/W  
Attribute  
Note: See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.  
• Bit7: Stop mode  
Writing “1” to the stop mode bit (STOP) changes to stop mode.  
See “Chapter 10 Standby (Page No.155)” for details.  
• Bit6: Sleep mode  
Writing “1” to the sleep mode bit (SLEEP) changes to sleep mode.  
See “Chapter 10 Standby (Page No.155)” for details.  
• Bit5: High impedance mode  
Writing “1” to the high impedance mode bit (HIZ) sets pin to high impedance (Hi-z) during stop mode.  
See “Chapter 10 Standby (Page No.155)” for details.  
• Bit4: Software reset  
Writing “0” to the software reset bit triggers a software reset.  
SRST  
Operation  
0
1
Trigger a software reset  
Do not trigger a software reset  
• Note that negative logic is used.  
• The read value is always “1”.  
• Bit3-2: Oscillation stabilization time selection  
The oscillation stabilization time selection bits (OS[1:0]) set the oscillation stabilization time as follows:  
1
11  
16  
22  
(F2 x 2 , F2 x 2 , F2 x 2 , F2 x 2  
)
The count is supplied by the timebase counter.  
1
Initialized to “00” (F2 x 2 , main clock) by a reset triggered by INIT pin input.  
See “Chapter 19 Timebase Timer (Page No.263)” for details.  
• Bit1: Halt sub clock oscillation  
Writing “1” to the halt sub clock oscillation bit (OSCD2) halts the oscillation of the sub clock during stop mode.  
• Bit0: Halt main clock oscillation  
Writing “1” to the halt main clock oscillation bit (OSCD1) halts the oscillation of the main clock during stop mode.  
143  
Chapter 9 Reset  
4.Registers  
4.3 MOD: Mode Pins  
These pins specify the location of the mode vector and reset vector that are read after the MCU is  
reset.  
Mode pins  
Reset vector  
Access area  
Mode name  
Remarks  
MD2 MD1 MD0  
Internal ROM mode  
vector  
0
0
0
0
0
1
Internal  
External  
External ROM mode  
vector  
4.4 Mode Vector  
The data written to the mode register (MODR) by the mode vector fetch operation is called the  
mode data. (The mode register is an internal register and cannot be written to or read from  
directly.)  
After the mode register is set, the MCU operates in accordance with the modes (bus mode and  
access mode) set in this register.  
The mode data is set by all types of reset. Setting the mode data from the user program is not  
possible.  
• Mode Vector: Address 000FFF8h (Access: Byte, Half-word, Word)  
31  
0
30  
0
29  
0
28  
0
27  
0
26  
25  
24  
Bit  
ROMA  
WTH1  
WTH0  
Operation mode setting bits  
• Bit32-27: Reserved bits  
Always set these bits to “00000”.  
If a value other than “00000” is set, the operation of the MCU is not guaranteed.  
• Bit26: Internal ROM enable  
Specifies whether to enable the internal ROM area.  
ROMA  
Function  
Remarks  
0
1
External ROM mode  
Internal ROM mode  
Enables the external ROM area.  
Enables the internal ROM area.  
Always set to “1”.  
• Bit25-24: Bus width setting  
This sets the bus width for external bus mode.  
WTH1  
WTH0  
Function  
8-bit bus width  
Remarks  
0
0
1
1
0
1
0
1
16-bit bus width  
32-bit bus width  
Single chip mode  
• Bit23-0: Undefined bits  
4.5 Reset Vector  
The MCU starts program execution from the address specified by the mode vector.  
144  
Chapter 9 Reset  
4.Registers  
Initial value to load into PC.  
Address  
007FD  
H
MODR  
Mode  
Vector  
000FFFF8  
000FFFFC  
XXXXXXXX XXXXXXXX XXXXXXXX  
H
H
Reset  
Vector  
PC  
4.6 Device Mode Overview  
The following table gives an overview about supported device mode combinations on the MB91460 series:  
Mode pins  
Mode/Reset  
Vector  
access area  
FIXED  
ROM  
Bus  
width  
Mode/Reset ROMA access WTH[1:0]  
Remarks  
MD2 MD1 MD0  
Vector  
area  
Yes  
1
0
Internal  
10  
00  
01  
10  
11  
00  
01  
10  
11  
00  
01  
10  
11  
00  
01  
10  
11  
32bit  
8bit  
Fixed Mode Data is 0x06  
16bit  
32bit  
Single  
8bit  
External  
Internal  
External  
Internal  
0
0
0
Internal  
Setting not supported  
No  
16bit  
32bit  
Single  
8bit  
1
0
1
16bit  
32bit  
Single  
8bit  
Setting not supported  
Setting not supported  
0
0
1
External  
-
16bit  
32bit  
Single  
Remarks:  
• On the MB91460 series the ROM area is from 0x0004:0000 up to 0xFFFF:FFFF  
145  
Chapter 9 Reset  
5.INIT Pin Input (INIT: Settings Initialization Reset)  
5. INIT Pin Input (INIT: Settings Initialization Reset)  
5.1 Trigger  
The pin is used to trigger a settings initialization reset.  
A settings initialization reset (INIT) request remains active while the pin remains at the “L” level.  
Keep the “L” level for the main oscillation stabilisation time.  
5.2 Releasing the Reset Request  
Inputting an “H” level to the pin after the main oscillation stabilisation time releases the settings  
initialization reset (INIT) request.  
5.3 Flag  
When an pin request triggers a settings initialization reset (INIT), the settings initialization reset flag  
(RSRR.INIT) is set to “1”.  
5.4 Reset Level  
This reset has the maximum reset level and initializes all settings. This type of reset is called the  
settings initialization reset (INIT)  
A settings initialization reset (INIT) triggered by INIT pin input has the highest priority of all resets  
and has priority over all other inputs, operations, and states.  
When a settings initialization reset (INIT) occurs, it is followed by an operation reset (RST) after the  
oscillation stabilization time elapses.  
5.5 Initialization Triggered by INIT Pin Input (INIT)  
• Device operation mode (bus mode and external bus width setting)  
• All internal clock related settings (clock source selection, main PLL control, division setting)  
• All settings relating to the external bus CS0 area  
• All other settings related to pin states  
• All areas initialized by an operation reset (RST)  
• Program operation  
• CPU and internal bus  
• Peripheral circuit register contents  
• I/O port settings  
• Device operation mode (bus mode and external bus width setting)  
146  
 
Chapter 9 Reset  
5.INIT Pin Input (INIT: Settings Initialization Reset)  
5.6 Reset Cancellation Sequence  
After the cancellation (removal) of the settings initialization reset (external INITX pin) request the device  
performs the following operations in the sequence listed.  
1. Removal of settings initialization reset (INIT)  
2. Set operation reset (RST) state and start internal clock  
3. Clear operation reset (RST) state and change to normal operation (RUN)  
4. Read mode vector from address 000FFFF8  
H
5. Write mode vector to MODR (mode register)  
6. Read reset vector from address 000FFFFC  
7. Write reset vector in PC (program counter)  
H
Start program execution from the address specified by PC (program counter)  
Note: See explanation in “5. Operation (Page No.253)”.  
147  
 
Chapter 9 Reset  
6.Watchdog Reset (INIT: Settings Initialization Reset)  
6. Watchdog Reset (INIT: Settings Initialization Reset)  
6.1 Trigger  
Writing to the watchdog timer control register (RSRR) starts the watchdog timer. Once started, a  
watchdog reset request is generated unless “A5 ” and “5A ” are written to the watchdog reset  
H
H
delay register (WPR) within the time specified by the watchdog period selection bits  
(RSRR.WT[1:0]).  
6.2 Releasing the Reset Request  
The watchdog reset request invokes a settings initialization reset (INIT). The watchdog reset  
request is released after the request is received and the settings initialization reset (INIT)  
generated, or when an operation reset (RST) occurs.  
6.3 Flag  
When watchdog reset request triggers a settings initialization reset (INIT), the watchdog timeout  
flag (RSRR.WDOG) is set to “1”.  
6.4 Reset Level  
This reset has the maximum reset level and initializes all settings. This type of reset is called the  
settings initialization reset (INIT).  
When a settings initialization reset (INIT) occurs, it is followed by an operation reset (RST) after the  
oscillation stabilization time elapses.  
6.5 Initialization Triggered by Watchdog Reset (INIT)  
Same as for a reset triggered by an INIT pin input.  
However, the oscillation stabilization time selection bits (STCR.OS[1:0]) and reset cause flags  
(INIT, WDOG, SRST) are not initialized and retain their existing values.  
6.6 Reset Cancellation Sequence  
Same as for INIT pin input.  
(See “Chapter 20 Software Watchdog Timer (Page No.273)” for details.)  
148  
 
Chapter 9 Reset  
7.Software Reset (RST: Operation Initialization Reset)  
7. Software Reset (RST: Operation Initialization Reset)  
7.1 Trigger  
Writing “0” to the software reset bit (STCR.SRST) generates a software reset request.  
A software reset requests an operation reset (RST).  
7.2 Releasing the Reset Request  
The software reset request is released after the request is received and the operation reset (RST) generated.  
7.3 Flag  
When software reset request triggers an operation reset (RST), the software reset flag (RSRR.SRST) is set to  
“1”.  
7.4 Reset Level  
This is a normal level reset which only initializes the program and is called an operation reset (RST).  
The following section lists the main items initialized by an operation reset (RST):  
7.5 Items Initialized by Operation Reset (RST)  
• Program operation  
• CPU and internal bus  
• Content of registers in peripheral circuits  
• I/O port settings  
• Device operation mode (bus mode and external bus width setting)  
7.6 Reset Cancellation Sequence  
After cancellation (removal) of the operation reset (RST) request, the device performs the following operations  
in the sequence listed.  
1. Removal of operation reset (RST) and change to RUN state  
2. Read mode vector from address 000FFFF8  
H
3. Write mode vector to MODR (mode register)  
4. Read reset vector from address 000FFFFC  
H
5. Write reset vector to the PC (program counter)  
6. Start program execution from the address specified by the PC (program counter)  
149  
   
Chapter 9 Reset  
8.Reset Operation Modes  
8. Reset Operation Modes  
The following two different modes can be used for an operation reset (RST):  
• Normal (asynchronous) reset mode  
• Synchronous reset mode  
Which mode to use is specified by the synchronous reset operation enable bit (TBCR.SYNCR).  
Pin input resets and watchdog resets always use normal reset mode.  
For software resets, either normal reset mode or synchronous reset mode can be selected.  
8.1 Normal (Asynchronous) Reset Mode  
Normal reset operation refers to the mode when the device goes to the operation reset (RST) state  
immediately after an operation reset (RST) request occurs.  
For a normal reset, the device changes to the reset (RST) state immediately after a reset (RST)  
request is received regardless of the current state of internal bus access.  
In normal reset mode, the result on any bus operation that is in progress at the time the device  
changes state is not guaranteed. However, acceptance of the operation reset (RST) request is  
guaranteed.  
Setting the synchronous reset operation enable bit (TBCR.SYNCR) to “0” specifies normal reset  
mode.  
Normal reset mode is the default setting after a settings initialization reset (INIT).  
8.2 Synchronous Reset Operation  
Synchronous reset operation refers to the mode when the device does not go to the operation reset  
(RST) state after a operation reset (RST) request until after all bus access has halted.  
In synchronous reset mode, the device does not go to the reset (RST) state when a reset (RST)  
request is received if internal bus access is still in progress.  
When such a reset request is received, a sleep request is issued to the internal bus. The device  
does not change to the operation reset (RST) state until all buses have shutdown operation and  
changed to sleep mode.  
In synchronous reset mode, the results of bus operations are guaranteed because the device does  
not change state until all bus access has halted.  
However, if bus access should not halt for some reason, no requests can be received while bus  
operation continues. In such a case, the settings initialization reset (INIT) remains available at any  
time.  
The following lists cases in which bus access may not stop:  
If bus wait is enabled due to continuous input of RDY (ready request) to the external expansion bus  
interface.  
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Chapter 9 Reset  
9.MCU Operation Mode  
9. MCU Operation Mode  
After release of a reset, the MCU starts operation in the mode specified by the mode pins and mode data.  
Operation mode  
Bus mode  
Single chip mode  
Internal ROM/external bus mode  
External ROM/external bus mode  
Access mode  
32-bit bus width  
16-bit bus width  
8-bit bus width  
9.1 Bus Modes and Access Modes  
■ Bus mode  
The bus mode controls internal ROM operation and the external access function. The bus mode is specified  
by the mode setting pins (MD2, MD1, MD0) and internal ROM enable bit (Mode-Vector. ROMA).  
The FR60 has the following three bus modes.  
● Single chip mode  
In this mode, internal I/O, internal RAM, and internal ROM are available but access to other areas is  
disabled. External pins are used either by the peripheral functions or as general-purpose ports. Pins cannot  
be used as bus pins. This mode can not be used when using the fixed mode/reset vector as implemented  
on most of the MB91460 series devices.  
● Internal ROM, external bus mode  
In this mode, internal I/O, internal RAM, and internal ROM are available, and access to areas for which  
external access is enabled results in access to the external area. Some external pins function as bus pins.  
● External ROM, external bus mode  
In this mode, internal I/O and internal RAM are available but access to internal ROM is prohibited. Access  
to internal ROM areas and areas for which external access is enabled results in access to the external  
area. Some external pins function as bus pins.  
■ Access mode  
The access mode controls the width of the external data bus and is set by the WTH[1:0] bits in the mode data.  
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Chapter 9 Reset  
10.Caution  
10. Caution  
• INIT pin input  
Ensure that a settings initialization reset (INIT) is applied to this pin when the power is turned on. Also,  
after turning on the power, ensure a sufficient oscillation stabilization wait time is provided for the  
oscillation circuit by holding the input to the pin at the “L” level for the required time.  
Note: The INIT reset triggered by INIT pin input initializes the oscillation stabilization wait time to its  
minimum value.  
• Watchdog reset  
When a settings initialization reset (INIT) is triggered by a watchdog reset request, the oscillation  
stabilization time is not initialized. Also, in main RUN or sub RUN mode, no oscillation stabilization wait  
occurs in response to a watchdog reset request if the main clock is not halted.  
• Software reset  
If “1” (synchronous reset mode) is set to the synchronous reset operation enable bit (TBCR.SYNCR) when  
an operation reset (RST) is triggered by a software reset request, the operation reset (RST) does not occur  
until all bus access halts. Accordingly, there may be a long delay before the operation reset (RST) occurs,  
depending on the bus usage.  
• Settings initialization reset (INIT)  
A settings initialization reset (INIT) invokes an operation reset (RST) after the oscillation stabilization wait  
time elapses.  
• Reset cause flags (INIT), (HSTB), (WDOG), (ERST), (SRST) and (LINIT)  
• Reading the reset cause register clears all the reset cause flags to “0”.  
• If more than one reset occurs before the reset cause register is read, the flag values are  
ORed and more than one flag may be set to “1”.  
• Reset mode  
A settings initialization reset (INIT) initializes the reset mode to normal reset mode.  
• DMA controller  
As the DMA controller halts any transfer when a request is received, it does not cause any delay in  
changing device state.  
• Pin states during a reset  
See “8. Pin State Table (Page No.96)” for details about pin states during a reset.  
152  
 
Chapter 9 Reset  
10.Caution  
153  
Chapter 9 Reset  
10.Caution  
154  
Chapter 10 Standby  
1.Overview  
Chapter 10 Standby  
1. Overview  
Two standby modes (low power consumption modes) are available.  
•
•
Sleep mode: Stops the program  
Stop mode: Shuts down the device  
Note: It is possible to keep the Real Time Clock active in STOP mode (see chapter RTC).  
2. Features  
■ Sleep mode  
• Device state in sleep mode:  
• Halts the program.  
• CPU program execution only stops. Peripheral functions can continue to operate.  
• The internal memory and internal bus halt.  
• Transition to sleep mode:  
• Sleep mode is invoked by the program.  
• Recovery from sleep mode:  
• Generation of a valid interrupt request ends sleep mode (returns to normal operation)  
• An INIT pin input or generation of a watchdog reset invokes an initialization reset (INIT)  
followed by an operation reset (RST).  
■ Stop mode  
• Device state in stop mode:  
• The overall device halts.  
• Internal circuits halt (with some exceptions)  
• Internal clock signals halt (with some exceptions)  
• Whether or not the oscillation circuit halts can be controlled by a setting (programmable).  
• All external pins can be set to high impedance (programmable, excludes some pins)  
• Transition to stop mode:  
• Stop mode is invoked by the program.  
• Recovery from stop mode:  
• The following four interrupt requests change the device to the oscillation stabilization wait state.  
•External level-detect or edge-detect interrupt  
•Interrupt generated by oscillation stabilization wait timer for the main clock when oscillation not halted.  
•Interrupt generated by oscillation stabilization wait timer for the sub clock when oscillation not halted.  
•Real time clock interrupt when oscillation not halted.  
• Input to the INITX pin invokes an initialization reset (INIT) and then an operation reset (RST).  
155  
       
Chapter 10 Standby  
3.Configuration  
3. Configuration  
Figure 3-1 Configuration Diagram  
State transition control circuit  
(for standby modes)  
SLEEP  
STCR: bit7  
SYNCS  
TBCR: bit0  
Do not change to sleep mode.  
Change to sleep mode.  
Setting prohibited  
Synchronous standby  
0
1
0
1
Sleep signal  
Stop signal  
STOP  
STCR: bit7  
0
1
Do not change to stop mode.  
Change to stop mode.  
OSCD1  
STCR: bit0  
Do not halt main clock oscillation during stop mode.  
Halt main clock oscillation during stop mode.  
0
1
Clock control  
State  
transition  
control  
circuit  
HIZ  
STCR: bit5  
0
1
Maintain same states during stop mode.  
Set pins to high impedance during stop mode.  
Pin control  
Internal interrupts,  
external interrupts  
SRST  
STCR: bit4  
Initialize settings (INIT)  
0
1
Generate software reset.  
Do not generate software reset.  
INIT  
Initialize operation (RST)  
RSRR: bit7  
INIT  
0
No INIT pin input  
Oscillation stabilization  
wait finished  
Counter cleared,  
oscillation  
stabilization  
wait  
1
INIT pin input occurred (INIT)  
SRST  
RSRR: bit3  
No software reset (RST)  
0
1
Time-base counter  
(oscillation stabilization wait)  
Software reset (RST) occurred  
Watchdog timer  
WDOG  
RSRR: bit5  
0
1
No watchdog timeout  
Watchdog timeout (INIT) occurred  
Figure 3-2 Register List  
Standby control  
156  
 
Chapter 10 Standby  
4.Registers  
4. Registers  
4.1 STCR: Standby Control Register  
Used to control transition to the stop and sleep standby modes, and to specify the pin states and whether to  
halt the oscillation during stop mode.  
Note: See “Chapter 9 Reset (Page No.139)” also.  
• STCR: Address 0481h (Access: Byte)  
7
6
5
4
3
2
1
0
bit  
STOP  
SLEEP  
HIZ  
SRST  
OS1  
OS0  
OSCD2  
OSCD1  
Initial value  
(INITX pin input)  
0
0
0
0
1
1
1
1
0
0
1
1
1
1
Initial value  
(Watchdog reset)  
X
X
0
0
X
1
X
X
X
X
Initial value (Software reset)  
Attribute  
R/W  
R/W  
R/W  
R1, W  
R/W  
R/W  
R/W  
R/W  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7: Stop mode  
STOP  
Operation  
0
1
Does not change to stop mode.  
Changes to stop mode.  
• Goes to “0” when a reset (INIT pin input or software reset) occurs or on recovery from stop mode.  
• Going directly from main PLL operation to stop mode is prohibited. (See “8. Caution (Page No.165)”.)  
• Bit6: Sleep mode  
SLEEP  
Operation  
0
1
Does not change to sleep mode.  
Changes to sleep mode.  
• If this bit and the stop mode bit (STOP) bit are set to “1” at the same time, the device goes to stop mode.  
• Goes to “0” when a reset (INIT pin input or software reset) occurs or on recovery from sleep mode.  
• Bit5: High impedance mode  
HIZ  
0
Operation  
Maintain same pin states when changing to stop mode.  
Set pin outputs to high impedance (Hi-z) during stop mode.  
1
• The default setting is high impedance.  
• Bit4: Software reset (SRST)  
• Setting this bit to “0” invokes a software reset.  
• Bit3-2: Oscillation stabilization time selection (OS[1:0])  
• Setting these bits in the range “00”-“11” sets the oscillation stabilization time to use after recovering from  
stop mode.  
An INIT pin input reset or watchdog reset initialize this setting to its initial value.  
(See “Chapter 18 Timebase Counter (Page No.249)”.)  
• Bit1: Sub clock oscillation halt  
OSCD2  
Operation of sub clock during stop mode  
Continue oscillation  
0
1
Halt oscillation  
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Chapter 10 Standby  
4.Registers  
• Bit0: Main clock oscillation halt  
OSCD1  
Operation of main clock during stop mode  
Continue oscillation  
0
1
Halt oscillation  
4.2 TBCR: Timebase timer control register  
This register controls the timebase timer interrupts and the options for resets and standby  
operation.  
Note: See also “Chapter 19 Timebase Timer (Page No.263)”.  
• TBCR: Address 0482h (Access: Byte)  
7
6
5
4
3
2
1
0
bit  
TBIF  
TBIE  
TBC2  
TBC1  
TBC0  
---  
SYNCR  
SYNCS  
Initial value (INIT pin,  
watchdog)  
0
0
X
X
X
X
X
X
0
0
Initial value (Software  
reset)  
0
0
X
X
X
X
R(RM1),W  
R/W  
R/W  
R1,W  
R/W RX/WX RX/WX  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7: Interrupt request flag for timebase timer  
• This flag goes to “1” when a timebase timer interrupt request occurs  
• Bit6: Interrupt request enable for the timebase timer  
• Writing “1” to this bit enables timebase timer interrupt requests.  
• Bit5-3: Interval time selection for timebase timer  
• Writing a value in the range “000”-“111” to these bits selects the interval time for the timebase timer.  
11  
12  
13  
22  
23  
24  
25  
26  
(F x 2 , x 2 , x 2 , x 2 , x 2 , x 2 , x 2 , x 2 )  
• Bit2: Reserved Writing does not affect the operation. The read value is undefined.  
• Bit1: Enable synchronous reset operation  
• Selects a normal reset “0” or a synchronous reset “1”.  
• Bit0: Enable synchronous standby operation  
SYNCS  
Operation  
0
1
Normal reset operation (Not permitted on this model).  
Enable synchronous standby operation (always set this before changing to a standby mode).  
158  
Chapter 10 Standby  
5.Operation  
5. Operation  
5.1 Sleep Mode  
■ Entering sleep mode  
Writing “1” to the sleep mode bit (STCR.SLEEP) changes to sleep mode. The device remains in this mode  
until an event occurs to wakeup the device from sleep mode.  
(See “8. Caution (Page No.165)”.)  
■ Device state in sleep mode  
• CPU program execution stops. (Peripheral functions continue to operate.)  
• The internal memory and internal bus halt.  
• Circuits that halt during sleep mode  
• Bit search module  
• All internal memory (inclusive I-cache)  
• Internal/external bus  
• Circuits that do not halt during sleep mode  
• Oscillation circuit, main PLL (if enabled)  
• Clock generation control circuit  
• Interrupt controller  
• External interrupts  
• DMA  
• Peripherals  
■ Recovery and other items  
• Generation of an interrupt request that is currently enabled changes the device back to RUN mode. (Restores  
normal operation.)  
• An INIT pin input or generation of a watchdog reset invokes an initialization reset (INIT) followed by an  
operation reset (RST).  
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Chapter 10 Standby  
5.Operation  
5.2 Stop mode  
■ Entering stop mode  
Writing “1” to the stop mode bit (STCR.STOP) changes to stop mode.  
The device remains in this mode until an event occurs to wakeup the device from stop mode.  
(See “8. Caution (Page No.165)”.)  
■ Device state in stop mode  
• The overall device halts (internal circuits halt and the internal clock signals halt).  
• Circuits that halt during stop mode  
All internal circuits except those listed below.  
• Circuits that do not halt during stop mode  
• Oscillation circuits that are not specified to be halted  
•
•
•
Oscillation circuit for main clock (if not disabled)  
Oscillation circuit for sub clock (if not disabled)  
Main PLL circuit if oscillation circuit for main clock is enabled and PLL circuit is enabled  
and main regulator is kept enabled.  
• Peripheral functions that are driven directly by the oscillation and which have not been  
specified to be halted.  
•
Real Time Clock (if not disabled) and main or sub clock oscillation is enabled and the  
RTC clock source is set to the enabled oscillation  
•
LCDC (if LCD display enabled for sub-stop mode and subclock selected as the clock  
source.)  
• Pin states (High impedance or maintain previous state)  
• When pin outputs are set to go to high impedance during stop mode  
•
High impedance output: Pins that are set as general purpose ports and pins that have  
been selected for use by peripheral functions.  
• When pin outputs are set to maintain their previous states during stop mode  
•
Maintain previous state: Pins that are set as general purpose ports and pins that have  
been selected for use by peripheral functions.  
• When set as external interrupts  
•
Input available state:  
Pins set as external interrupt inputs using level detection or edge detection.  
(Whether the pin output during stop mode has been set to either high impedance or  
maintain previous state.)  
■ Recovery and other items  
• Any of the following interrupt requests cause the device to go to the oscillation stabilization wait  
RUN state and then to change back to RUN mode after the oscillation stabilization time elapses  
(return to normal operation).  
• External interrupts set to level detection or edge detection and that do not require a specific  
clock.  
• Real Time Clock interrupt (if operating)  
• An INIT pin input or generation of a watchdog reset invokes an initialization reset (INIT) followed  
by an operation reset (RST) after the oscillation stabilization time.  
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Chapter 10 Standby  
6.Settings  
6. Settings  
Table 6-1 Settings Required to Change to Sleep Mode  
Setting  
procedure*  
Setting  
Interrupt settings  
Setting register  
(See the chapter for each peripheral function.)  
Timebase timer control register (TBCR)  
Standby control register (STCR)  
—
Synchronous standby settings  
Change to sleep mode  
See 7.1  
See 7.1  
—
Operational restrictions  
(See “8. Caution (Page No.165)”.)  
*:For the setting procedure, refer to the section indicated by the number.  
Table 6-2 Settings Required to Change to Stop Mode  
Setting  
procedure*  
Setting  
Setting register  
Selects the oscillation stabilization  
wait time  
(See “Chapter 18 Timebase Counter (Page No.249)”.)  
—
Interrupt settings  
(See the chapter for each peripheral function.)  
Timebase timer control register (TBCR)  
Standby control register (STCR)  
—
Synchronous standby settings  
Change to stop mode  
Operational restrictions  
See 7.2  
See 7.2  
—
(See “8. Caution (Page No.165)”.)  
*: For the setting procedure, refer to the section indicated by the number.  
7. Q&A  
7.1 How do I change to sleep mode?  
Before you can change to sleep mode, you must first set the synchronous standby operation enable bit  
(TBCR.SYNCS).  
Operation  
Synchronous standby operation enable bit (SYNCS)  
To enable synchronous standby operation  
Set to “1”.  
Note: Setting (SYSNCS=“0”) is prohibited.  
Set using the sleep mode bit (STCR.SLEEP).  
Operation  
When you do not want to change to sleep mode  
To change to sleep mode  
Sleep mode bit (SLEEP)  
Set to “0”.  
Set to “1”.  
Note: Some restrictions apply when changing to sleep mode. See “8. Caution (Page No.165)” for details.  
161  
   
Chapter 10 Standby  
7.Q&A  
7.2 How do I change to stop mode?  
• When operating on the main PLL clock, the operating clock must be set to the main clock divided  
by two.  
See “7.3 How do I select the operating clock source? (Page No.202)” for details about changing  
the operating clock.  
• Before you can change to stop mode, you must first set the synchronous standby operation  
enable bit (TBCR.SYNCS). See section 7.1.  
• Set using the stop mode bit (STCR.STOP).  
Operation  
When you do not want to change to stop mode  
To change to stop mode  
Stop mode bit (STOP)  
Set to “0”.  
Set to “1”.  
Note: Some restrictions apply when changing to stop mode. See “8. Caution (Page No.165)” for  
details.  
7.3 How do I set pins to high impedance (Hi-z) during stop mode?  
Set using the high impedance mode bit (STCR.HIZ).  
Operation  
High impedance mode bit (HIZ)  
Set to “0”.  
When you do not want to set pins to high impedance during stop  
mode  
To set pins to high impedance during stop mode  
Set to “1”.  
Note: Some ports do not go to high impedance in some circumstances. (See “5.2 Stop mode (Page  
No.160)”.)  
7.4 How do I halt the main clock oscillation during stop mode?  
Use the main clock oscillation stop bit (STCR.OSCD1).  
Operation  
Main clock oscillation stop bit (OSCD1)  
Set to “0”.  
When you do not want to halt the main clock oscillation in stop  
mode  
To halt the main clock oscillation during stop mode  
Set to “1”.  
7.5 How do I recover from sleep mode?  
Two methods are available to recover from sleep mode.  
• Generation of a valid interrupt request changes to RUN mode (restores normal operation).  
If using interrupt processing, remember to set the I flag (I), interrupt level mask register (ILM),  
and interrupt control register (ICR).  
• An INIT pin input or generation of a watchdog reset invokes an initialization reset (INIT) followed by  
an operation reset (RST).  
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Chapter 10 Standby  
7.Q&A  
7.6 How do I recover from stop mode?  
The following events end stop mode:  
• The following four interrupts change the device to the oscillation stabilization wait state.  
• External level-detect interrupt or edge-detect interrupt.  
• Oscillation stabilization wait timer for the main clock when oscillation not halted.  
• Sub oscillation stabilisation timer when oscillation not halted.  
• Real time clock when oscillation not halted.  
If using interrupt processing, remember to set the I flag (I), interrupt level mask register (ILM), and interrupt  
control register (ICR).  
• Input to the INIT pin invokes an initialization reset (INIT) followed by an oscillation stabilization delay and  
then an operation reset (RST).  
In the case of an INIT pin input, an oscillation stabilization wait is required, depending on the width of the  
INIT pin input.  
See also “Chapter 13 Clock Control (Page No.189)” and “Chapter 18 Timebase Counter (Page No.249)”.  
163  
Chapter 10 Standby  
7.Q&A  
164  
Chapter 10 Standby  
8.Caution  
8. Caution  
• Points to note when changing to sleep mode  
When changing to sleep mode, set the synchronous standby operation enable bit (TBCR.SYNCS= “1”).  
Also, in order to change to sleep mode with synchronous standby operation enabled, the STCR register  
must be read after writing to the SLEEP bit. Always use the following sequence.  
(LDI  
(LDI  
STB  
LDUB @R12, R0  
LDUB @R12, R0  
#value_of_sleep, R0) ; value_of_sleep contains the write data for STCR.  
#_STCR, R12)  
R0, @R12  
; _STCR is the address of STCR (481H).  
; Write to standby control register (STCR).  
; STCR read required for synchronous standby.  
; Second dummy read to STCR.  
NOP  
NOP  
NOP  
NOP  
NOP  
; NOP x 5 required for timing  
• Points to note when changing to stop mode  
When changing to sleep mode, set the synchronous standby operation enable bit (TBCR.SYNCS= “1”).  
Also, in order to change to stop mode with synchronous standby operation enabled, the STCR register  
must be read after writing to the STOP bit. Always use the following sequence.  
(LDI  
(LDI  
STB  
LDUB @R12, R0  
LDUB @R12, R0  
#value_of_stop, R0) ; value_of_stop contains the write data for STCR.  
#_STCR, R12)  
R0, @R12  
; _STCR is the address of STCR (481H).  
; Write to standby control register (STCR).  
; STCR read required for synchronous standby.  
; Second dummy read to STCR.  
NOP  
NOP  
NOP  
NOP  
NOP  
; NOP x 5 required for timing  
• When the main PLL is selected as the operation clock source  
When the main PLL is selected as the operation clock source, change the operation clock source selection  
to main clock divided by two before changing to stop mode.  
See “Chapter 13 Clock Control (Page No.189)” for details.  
The restrictions that apply to the clock divide ratio setting are the same as for normal operation. Also, you  
do not necessarily have to halt the PLL oscillation.  
• If interrupts are disabled in the interrupt control register (ICR=“00011111B”), the device will not recover from stop  
or sleep mode when an interrupt occurs.  
• Pin high impedance control in stop mode  
Setting the high impedance bit (STCR.HIZ) to “1” sets pin outputs to high impedance during stop mode. If  
the high impedance bit (STCR.HIZ) is set to “0”, pins retain the states they have prior to entering stop  
mode.  
See “8. Pin State Table (Page No.96)” for details such as the operation of specific pins.  
165  
 
Chapter 10 Standby  
8.Caution  
166  
Chapter 11 Memory Controller  
1.Overview  
Chapter 11 Memory Controller  
1. Overview  
This module combines the interfaces to the F-Bus memory resources, FLASH and General Purpose RAM (also ref-  
erenced as I/D-RAM). These memories can be combined CODE and DATA storage. While code fetch is possible  
in general via the F-Bus at the FR core, due to performance reasons the code fetch is accellerated by a direct I-Bus  
connection in MB91460 series MCUs.  
For FLASH access the interface contains an instruction cache and data read buffer. A prefetch mechanism removes  
CPU internal code fetch latencies for linear code.  
In addition the module includes the definition of the Fixed Mode Vector (FMV) and the Fixed Reset Vector (FRV),  
depending on the device mode.  
2. FLASH Interface  
•
•
Wait timing  
Generation of FLASH control signals ATDIN and EQIN for synchronous access.  
(this version supports independent timing configuration of ADTIN, EQIN and Wait)  
•
•
•
•
Generation of CEX, WEX and OEX  
Handling of 32 or 64 bit read mode and 16 or 32 bit read/write mode for programming  
Support of external SRAM for emulation devices with 1:1 timing transparency (same wait cycles)  
Measures for FLASH macro test and parallel programming support  
3. General Purpose RAM  
•
Zero wait cycle access (code), one wait cycle access (data) to shared code/data memory (up to 64 kByte),  
also referenced as I/D-RAM  
4. Instruction Cache and Data Buffer  
•
•
•
Up to 16 kByte Instruction cache (4k word entries, one way direct mapped, prefetch miss option)  
Size configuration for the evaluation device (0, 4, 8 and 16 kB)  
1 or 2 dword (32 or 64 bit) data read buffer (not available on MB91460 series)  
5. Prefetch  
•
•
Prefetch of consecutive instruction word address to the cache buffer  
Prefetch is canceled in case of prefetch miss (branch or data access), thus it works without any penalties in  
the prefetch miss case.  
•
The FLASH macro needs to support FLASH access cycle cancelation at any point, that means it may not  
affect the timing of the next complete access cycle (no special recovery condition required from previous  
access cancelation).  
6. Fixed Mode and Reset Vectors  
•
Mode vector address: 0x000ffff8; return 0x06000000 for internal vector mode  
167  
               
Chapter 11 Memory Controller  
7.Registers  
•
•
Reset vector address: 0x000ffffc; return 0x00030000 at RAM execution mode (jump to test pro-  
gram) or return 0x0000bff8 in any other case (jump to Boot ROM)  
If FMCS_FIXE is switched off, the FLASH memory can be accessed on addresses 0x000ffff8 and  
0x000ffffc. FIXE is set at reset.  
7. Registers  
● List of FLASH-IF Registers  
Table 7-1 FLASH-IF Registers Summary  
Address  
Register  
Block  
+0  
+1  
+2  
+3  
7000  
7004  
FMCS [R/W] FMCR [R/W] FCHCR [R/W]  
FLASH_IF  
H
H
01101000  
----0000  
------00 1000011  
FMWT2[R/W] FMPS [R/W]  
FMWT [R/W]  
1
-101---- -----000  
11111111 01111111  
11111111 01011101  
2
7008  
FMAC  
[R]  
H
00000000 00000000 00000000 00000000  
700C  
FCHA0  
H
-------- -0000000 00000000 00000000  
7010  
FCHA1  
H
-------- -0000000 00000000 00000000  
Remarks:  
• Read and write access to all registers is byte, halfword and word.  
• FMCR and FMWT2 registers are not available on MB91V460  
• The initial values of the waitcycle setting register FMWT differs between the flash-less evaluation device  
MB91V460 and devices with embedded flash memory  
Notes:  
1)  
Initial value on MB91V460  
2)  
Initial value on MB91F467DA  
168  
 
Chapter 11 Memory Controller  
8.Explanations of Registers  
8. Explanations of Registers  
● FLASH Interface Control Register  
⇐ Bit no.  
Control Register byte 0  
Address : 7000H  
31  
30  
29  
28  
27  
26  
25  
24  
FMCS  
ASYNC FIXE (BIRE) RDYEG RDY  
RDYI RW16 LPM  
(R/W) (R/W) (R/W) (R)  
(R) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(0)  
(1)  
(1)  
(0)  
(1)  
(0)  
(0)  
(0)  
⇐ Bit no.  
23  
22  
21  
20  
19  
18  
17  
16  
Control Register byte 1  
Address : 7001H  
-
-
-
-
LOCK PHASE PF2I RD64  
FMCR  
(-)  
(X)  
(-)  
(X)  
(-)  
(X)  
(-) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(X)  
(0)  
(0)  
(0)  
(0)  
⇐ Bit no.  
Control Register byte 2  
15  
14  
13  
12  
11  
10  
9
8
FCHCR  
-
-
-
-
-
-
REN (TAGE)  
Address : 7002H  
(-)  
(X)  
(-)  
(X)  
(-)  
(X)  
(-)  
(X)  
(-)  
(X)  
(-) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(X)  
(0)  
(0)  
⇐ Bit no.  
7
6
5
4
3
2
1
0
Control Register byte 3  
Address : 7003H  
FCHCR  
FLUSH (DBEN) PFEN PFMC LOCK ENAB SIZE1 SIZE0  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(1)  
(0)  
(0)  
(0)  
(0)  
(0)  
(1)  
(1)  
FLASH Memory Control and Status Register (FMCS)  
• BIT[31]: ASYNC - ASYNChronous access enable  
0
1
Synchronous FLASH access (default)  
Asynchronous FLASH access  
The ASYNC bit is cleared at reset, which enables the fast synchronous FLASH access mode by default. To switch  
to asynchronous mode, set this bit (however it is basically not recommended to set this bit, neither in read nor in  
write access).  
• BIT[30]: FIXE - FIXed reset and mode vector Enable  
0
1
Disable FMV/FRV and enable FLASH access at mode vector address  
Output the fixed mode or reset vector at address hit (default)  
The FIXE bit is set by default.  
To enable FLASH access on address 0x000ffff8 and 0x000ffffc, clear this bit.  
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Chapter 11 Memory Controller  
8.Explanations of Registers  
• BIT[29]: BIRE - Burn-In ROM Enable  
0
1
Disable Burn-In ROM and enable FLASH access at Burn-In ROM address  
Enable access to the Burn-In ROM (default)  
The BIRE bit is a reserved bit and should not be used.  
• BIT[28]: RDYEG - RDY status hold and qittation register  
0
1
Auto algorithm not started or started and not compleated (default)  
The FLASH auto-algorithm has been completed since last register read access.  
The RDYEG bit is cleared after reset.  
The bit is set after 0->1 transition of FMCS_RDY. The bit shows that the RDY signal of the FLASH is or  
was active (compleated auto-algorithm). The RDYEG bit is cleared automatically at read access to ad-  
dress 0x7000.  
The RDYEG bit is read-only status information.  
Remark: The function of this status bit is not guaranteed when running the CPU on frequencies lower  
than 1MHz.  
• BIT[27]: RDY - FLASH RDY status of auto-algorithm  
This bit shows the status of the RDY line of the FLASH macro. RDY is used to signalize the state of the  
FLASH macro in case of an auto-algoriythm was started (e.g. sector erase, chip erase). If RDY returns  
to ’1’, the auto-algorithm has been completed.  
The RDY bit is read-only status information.  
Remark: The function of this status bit is not guaranteed when running the CPU on frequencies lower  
than 1MHz.  
• BIT[26]: RDYI - RDY output force  
0
1
Inactive (default)  
Force the RDY output to ’1’  
This bit is reserved for FLASH test. Do not set this bit.  
• BIT[25]: RW16 - 16 bit Read/Write enable to FLASH  
0
1
32 bit read and write access to FLASH is enabled (default)  
16 bit read and write access to FLASH is enabled  
This bit is cleared after reset. There is a 32 bit read and write access to the FLASH memory enabled by  
default.  
Setting of the RW16 bit implies switching from 32 bit into 16 bit mode. When it is intended to write data  
to the flash memory (or while chip erase or sector erase) then code fetch from the flash memory is not  
supported.  
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Chapter 11 Memory Controller  
8.Explanations of Registers  
Important remark: To maintain data consistency it is strongly recommended to disable the instruction cache while  
writing to the FLASH memory and to flush the instruction cache (FLUSH=1) after completing the write procedure to  
the FLASH memory.  
Important remark: It is not allowed to switch between the 16 bit, the 32 bit and the 64 bit mode while reading instruc-  
tions or data from the FLASH memory.  
• BIT[24]: LPM - Low Power Mode  
0
1
Low power mode off (default)  
Low power mode enabled  
This bit is cleared after reset. The low power mode is switched off by default.  
If LPM=0, CEX is permanently asserted to ’0’ (active). This enables fastest possible FLASH access timing.  
Setting this bit to ’1’ enables the low power mode. CEX is asserted low only in case of FLASH access. In between  
the FLASH macro is in stand-by mode.  
Remark: On the MB91460 series with embedded FLASH memories it is not necessary to use this setting  
since the FLASH memory supports an “automatic sleep mode” which puts the FLASH automatically in a  
low power consumption state when not accessed.  
FLASH Memory Control Register (FMCR)  
The FMCR register is not available on the evaluation device MB91V460.  
• BIT[19]: LOCK - ALEH auto-update lock  
0
1
ALEH setting auto update is enabled (default)  
ALEH setting auto update is disabled  
FLASH memories embedded on the MB91460 series require a certain timing between ATDIN falling edge and EQIN  
rising edge. This timing is named tALEH and has usually the same length as the ATDIN duration.  
By writing the setting of ATDIN length to the FMWT.ATD[2:0] bits, the FMWT2.ALEH[2:0] bits will be updated auto-  
matically to the same setting. To avoid this automatic update it is possible to set the ALEH LOCK bit.  
It is also possible to apply a different setting to the FMWT2.ALEH[2:0] bits by writing first to the FMWT.ATD[2:0] bits  
and second to the FMWT2.ALEH[2:0] bits.  
• BIT[18]: PHASE - ATDIN/EQIN clock phase  
0
1
ATDIN/EQIN generation is in phase with the core clock (default)  
ATDIN/EQIN generation is inverted to the core clock  
At lower core clock frequencies it can be beneficial to change the ATDIN/EQIN generation to inverted core clock to  
save a waitcycle compared to the generation of these signals in phase with the core clock.  
It is recommended to always refer to the setting requirements of ATDIN, EQIN and waitcycles for each product  
which are provided by Fujitsu (see the related datasheets).  
(PHASE setting is not available on MB91460 series)  
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Chapter 11 Memory Controller  
8.Explanations of Registers  
• BIT[17]: PF2I - Prefetch 32 bit (2 instructions) only  
0
1
Prefetch 64 bit (default)  
Prefetch 32 bit only  
When switching on 64 bit read mode (RD64=1) then prefetch will be performed on instruction address  
IA+8 (when current access is aligned at IA+0) and on instruction address IA+4 (when current access is  
aligned at IA+4). However, the setting of PF2I=1 in the 64 bit read mode will cause a prefetch only on  
next instruction address IA+4 (independent of current access alignment is IA+0 or IA+4).  
Usually prefetching 64 bit is superior to 32 bit only, however it can be the case on strong fragmented  
code that the performance deteriorates due to replacement of cache entries. In this case it can be sen-  
sible to switch to 32 bit prefetch only.  
• BIT[16]: RD64 - Enable 64 bit read mode  
0
1
64 bit read mode is disabled (default)  
64 bit read mode is enabled  
Some embedded FLASH memories supports switching the 64 bit read mode to increase the access per-  
formance. Please contact Fujitsu if this feature is available on the product you are using.  
This bit is cleared after reset. The 32 bit read and write access to the FLASH memory is enabled by de-  
fault.  
Setting of the RD64 bit implies switching from 32 bit into 64 bit mode. Writing data to the flash memory  
is not supported in the 64 bit read only mode.  
Important remark: It is not allowed to switch between the 16 bit, the 32 bit and the 64 bit mode while  
reading instructions or data from the FLASH memory.  
FLASH Cache Control Register (FCHCR)  
• BIT[9]: REN - Non-cacheable area Range Enable  
0
1
FCHA1 defines address mask (default)  
FCHA1 defines second point for the non-cacheable address range from FCHA0 to FCHA1  
The bit is cleared after reset. The address defined in FCHA0 is combined with a bit mask defined in  
FCHA1 to define the non-cacheable area.  
If the REN bit is set, the non-cacheable area is defined by two points. The non-cacheable range is from  
addresses greather than or equal to FCHA0 up to addresses less than or equal to FCHA1.  
• BIT[8]: TAGE - TAG RAM access Enable  
0
1
Memory mapped TAG RAM access disabled (default)  
Memory mapped TAG RAM access enabled  
The bit is set to 0 after reset.  
(TAG RAM access is not available on MB91460 series).  
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Chapter 11 Memory Controller  
8.Explanations of Registers  
• BIT[7]: FLUSH - Flush instruction cache entries  
0
1
Flushing the instruction cache entries has been completed  
Actually flushing the instruction cache entries  
This bit is set after reset.  
If the FLUSH bit is set, the instruction cache entries are flushed sequentially. During this initialization the cache is  
disabled. The initialization has a duration of 1 clock cycle per cache entry. The number of valid entries depends on  
the configured cache size.  
After completion (all entries are flushed) the FLUSH bit is cleared by hardware.  
Writing a ’1’ to this bit triggers the flushing of the cache entries.  
Important remark: It is not allowed to set the cache size configuration (FCHCR.SZ[1:0]) and FLUSH at the same  
time (same write access). Always first set the size configuration before flushing the cache.  
• BIT[6]: DBEN - Data Buffer ENable  
0
1
Buffering of read data is disabled (default)  
Buffering of read data is enabled  
This bit is cleared after reset. The read data buffer is disabled by default.  
Setting the DBEN bit enables the data read buffer. This is useful to speed up reading of data structures of 8 or 16  
bit operands. There is one word data buffer implemented. If the same 32 or 64 bit word address is accessed con-  
secutively, the data is read from the buffer.  
(Data buffer is not available on MB91460 series)  
• BIT[5]: PFEN - PreFetch ENable  
0
1
Prefetch of instructions is disabled (default)  
Prefetch of instructions is enabled  
This bit is cleared after reset. The prefetch of instructions is disabled by default.  
Setting the PFEN bit enables the code prefetch from the next word on instruction address IA+4. Prefetch eliminates  
any latency in the code fetch path of the MCU to the FLASH memory for linear code.  
When switching on 64 bit read mode (RD64=1) then prefetch will be performed on instruction address IA+8 (when  
current access is aligned at IA+0) and on instruction address IA+4 (when current access is aligned at IA+4). How-  
ever, the setting of PF2I=1 in the 64 bit read mode will cause a prefetch only on next instruction address IA+4 (in-  
dependent of current access alignment is IA+0 or IA+4).  
A running prefetch cycle can be directly taken over from a matching instruction access. If there is no instruction ac-  
cess in between, the prefetched instruction word is stored in cache memory. If there is an FLASH access (code or  
data) to an address different from the prefetch address, the prefetch cycle is canceled immediately.  
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Chapter 11 Memory Controller  
8.Explanations of Registers  
• BIT[4]: PFMC - Prefetch Miss Cache enable  
0
1
Standard cache algorithm (default)  
Prefetch misses are cached only  
This bit is cleared after reset. The prefetch miss cache is disabled by default. The instruction cache uses the stand-  
ard algorithm of writing cache entries for each accessed instruction word from FLASH.  
Setting the PFMC bit switches to a second write algorithm for cache entries. This algorithm writes only this instruc-  
tion words to the cache, which are causing prefetch miss conditions.  
The FR CPU requests approximately one instruction word (which contains two 16 bit instruction codes) in two clock  
cycles. If the FLASH data throughput (one word in two cycles) is sufficient for the needs of the CPU, the PFMC  
option is useful in most cases.  
If the FLASH access time is two clock cycles, normally no wait states are generated when the next instruction word  
is requested from a consecutive address and prefetch is enabled. Thus, caching such linear code segments in con-  
junction with prefetch may not improve the code fetch performance, which is at the optimum already. More interest-  
ing is to improve the situation for branches in the code, where prefetch could not remove the latency of accessing  
it. If FPMC is set to ’1’, the cache algorithm stores only these FLASH accesses, which have caused a wait condition  
due to a prefetch miss condition (not mached predicted address).  
The effect of this algorithm is, that the restricted amount of cache entries is utilized more efficiently. Usually the  
same performance can be reached with half the cache size. Or, in other words, the cache is as same efficient as it  
would have the doubled size.  
The efficiency of the PFMC algorithm depends on the structure of the application.  
• BIT[3]: LOCK - Global lock of cache entries  
0
1
Write of cache entries enabled (default)  
Writing of cache entries is disabled, the cache contents is locked  
This bit is cleared during reset. The cache entries are writable by default.  
If the LOCK bit is set, no new entries can be written to cache memory. The old contents of cache entries remains  
in memory. There is only a global lock feature for all cache entries.  
• BIT[2]: ENAB - Instruction cache enable  
0
1
The instruction cache is disabled (default)  
Enable the instruction cache  
This bit is cleared after reset. By default the instruction cache is disabled.  
If the ENAB bit is set, the instruction cache is switched on. The instruction cache is dedicated to FLASH access only.  
The cache is utilized by the prefetch algorithm as prefetch buffer. Hence prefetch can be used in an unbuffered form  
with cache disabled.  
Cache miss did not cause code fetch penalties. The FLASH access is started in parallel, independent from cache  
hit or miss evaluation.  
(If the cache is disabled, the cache entries and the TAG RAM contents can be accessed memory mapped. This  
feature is disabled in this version of the interface, see the explanaition of the TAGE bit.)  
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Chapter 11 Memory Controller  
8.Explanations of Registers  
• BIT[1:0]: SZ[1:0] - Cache size configuration  
00  
01  
10  
11  
0kByte - Cache disabled  
4kByte (1024 entries)  
8kByte (2048 entries)  
16kByte (4096 entries) (default)  
The cache size is set to ’11’ after reset.  
The cache size can be configured on the evaluation device (EVA).  
Remark: The number of cache entries determines the TAG initialization period at device startup, see the explanai-  
tion of the FLUSH bit above.  
Important remark: On products with less than 16kByte instruction cache it is recommended to set the size configu-  
ration in the system startup according to the available cache size.  
Important remark: It is not allowed to set the cache size configuration (FCHCR.SZ[1:0]) and FLUSH at the same  
time (same write access). Always first set the size configuration before flushing the cache.  
● FLASH Memory Wait Timing Register (FMWT)  
⇐ Bit no.  
Wait Timing Register byte 0  
Address : 7004H  
31  
30  
29  
28  
27  
26  
25  
24  
FMWT  
WTP1 WTP0 WEXH1 WEXH0 WTC3 WTC2 WTC1 WTC0  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
⇐ Bit no.  
23  
22  
21  
20  
19  
18  
17  
16  
Wait Timing Register byte 1  
Address : 7005H  
FMWT  
(FRAM) ATD2 ATD1 ATD0  
EQ3  
EQ2  
EQ1  
EQ0  
(
R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(0)  
(1) (1/0) (1)  
(1)  
(1)  
(1/0) (1)  
⇐ Bit no.  
Wait Timing Register byte 2  
15  
14  
13  
12  
11  
10  
9
8
FMWT2  
-
ALEH2 ALEH1 ALEH0  
-
-
-
-
Address : 7006H  
(-)  
(1)  
(0)  
(1)  
(-)  
(-)  
(X)  
(-)  
(X)  
(-)  
(X)  
Read/write ⇒  
Default value⇒  
(X) (R/W) (R/W) (R/W) (X)  
⇐ Bit no.  
7
6
5
4
3
2
1
0
Wait Timing Register byte 3  
Address : 7007H  
FMPS  
-
-
-
-
-
PS2  
PS1  
PS0  
(
-
)
(
-
)
(
-
)
(
-
)
(-) (R/W) (R/W) (R/W)  
(X) (0) (0) (0)  
Read/write ⇒  
Default value⇒  
(X)  
(X)  
(X)  
(X)  
Remarks:  
• ATD[2:0] setting is 0x7 on MB91V460 and 0x5 on MB91F467DA  
• EQ[3:0] setting is 0xF on MB91V460 and 0xD on MB91F467DA  
• FMWT2 is not available on MB91V460  
• BIT[31:30]: WTP[1:0] - Wait cycles for FLASH in page access  
WTP is set to 3 after reset.  
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Chapter 11 Memory Controller  
8.Explanations of Registers  
WTP controls the wait timing of the FLASH access in case of page hit for Page Mode FLASH. The WTP  
configuration is in units of clock cycles. The value of WTP should be set to the intra page access time  
(cycle time) of the FLASH memory in number of clock cycles, subtracted by one.  
The setting is used if the page size PS[2:0] is set different to 0.  
• BIT[29:28]: WEXH[1:0] - Minimum WEX High timing requirement  
WEXH is set to 3 after reset. The minimum high time duration of WEX is 5 cycles by default.  
Setting an other value reduces the WEX high time to 2 fixed cycles + WEXH.  
• BIT[27:24]: WTC[3:0] - Wait cycles for FLASH memory access  
WTC is set to 15 after reset.  
WTC controls the wait timing of the FLASH access. The WTC configuration is in units of clock cycles.  
The value of WTC should be set to the access time (cycle time) of the FLASH memory in number of clock  
cycles, subtracted by one.  
• BIT[23]: FRAM - Wait cycles for F-Bus general purpose RAM memory access  
FRAM is set to 0 after reset.  
This is a reserved bit. This version on MB91V460 has no configurable wait timing to F-Bus RAM, it op-  
erates with fixed 0 wait states RAM access.  
• BIT[22:20]: ATD[2:0] - Duration of the ATDIN signal for FLASH memory access  
MB91V460: ATD is set to 7 after reset. ATD defaults to 4 clock cycles.  
MB91F467DA: ATD is set to 5 after reset. ATD defaults to 3 clock cycles.  
ATD controls the timing of the ATDIN signal for FLASH access. The ATD configuration is in units of half  
clock cycles. The effective high duration of ATDIN equals to tATDIN=(ATD+1)*0.5 clock cycles.  
• BIT[19:16]: EQ[3:0] - Duration of the EQIN signal for FLASH memory access  
MB91V460: EQ is set to 15 after reset. EQ defaults to 8 clock cycles.  
MB91F467DA: EQ is set to 13 after reset. EQ defaults to 7 clock cycles.  
EQ controls the timing of the EQIN signal for FLASH access. The EQ configuration is in units of half clock  
cycles. The effective high duration of EQIN equals to tEQIN=(EQ+1)*0.5 clock cycles.  
• BIT[14:12]: ALEH[2:0] - Duration of the ALEH time for FLASH memory access  
MB91V460: not available  
MB91F467DA: ALEH is set to 5 after reset. ALEH defaults to 3 clock cycles.  
ALEH controls the timing of the ATDIN falling edge to EQIN rising edge for FLASH access.  
The EQ configuration is in units of half clock cycles. The effective duration of ALEH equals to  
tALEH=(ALEH+1)*0.5 clock cycles.  
Important remark: ALEH[2:0] is updated automatically to the same value as ATD[2:0] when writing to  
ATD[2:0]. Usually the ALEH time equals the ATD time, so there is normarlly no reason to update  
ALEH[2:0] in particular.  
Even though it is possible to program ALEH[2:0] with a different value than ATD[2:0] by:  
- Writing a different value to ALEH[2:0] after writing to ATD[2:0], or  
- Setting the FMCR.LOCK bit to disable the auto update  
176  
Chapter 11 Memory Controller  
8.Explanations of Registers  
FLASH access cycle waveform  
flash_start  
FMA  
ATDIN  
EQIN  
flash_wait  
DO  
tATD  
tALEH  
tWTC  
tRC  
tEQ  
Figure 8-1 Timing of a FLASH access cycle  
Figure 8-1 shows the example of a FLASH access cycle. In the FMWT register the three parts of the FLASH timing  
tATD, tALEH, tEQ and tWTC can be configured independently. The table below lists the configuration values for  
this example.  
Symbol  
tATD  
Length  
1.5 cycles  
1.5 cycles  
3 cycles  
Setup  
ATD=2  
tALEH  
tEQ  
ALEH=2  
EQ=5  
tWTC  
6 cycles  
WTC=6  
The resulting FLASH access cycle (tRC) time is 7 cycles (WTC+1).  
• BIT[2:0]: PS[2:0] - Page size definition for Page Mode FLASH  
PS is set to 0 after reset. Page Mode FLASH is disabled by default.  
This setting defines the page size to 2^PS in number of bytes.  
E.g. for Am29PL320D/MBM29PL3200 with a page size of 16 byte the value of PS has to be set to 4.  
(Embedded FLASH memories on MB91460 series do not support page mode)  
177  
 
Chapter 11 Memory Controller  
8.Explanations of Registers  
● FLASH Memory Adddress Check register (FMAC)  
FMAC [R]  
Address  
7008  
+0  
+1  
-0000000  
+2  
00000000  
+3  
00000000  
--------  
H
This register captures the address at the begin of a FLASH access cycle for test purposes.  
The register could be read only.  
● Non-cacheable area definition  
The non-cacheable area definition registers FCHA0 and FCHA1 define the FLASH region not to be cached. Not  
used bits are read back as zero. The tables below define the initial values of the registers. The point defined by  
FCHA0 = 0 and mask bits off is located outside the FLASH region, thus initially the whole FLASH region will be  
cached.  
FCHA0 [R/W]  
Address  
700C  
+0  
+0  
+1  
-0000000  
+2  
+3  
00000000  
--------  
--------  
00000000  
H
FCHA1 [R/W]  
+1  
Address  
7010  
+2  
+3  
00000000  
-0000000  
00000000  
H
If the FCHCR_REN bit is cleared, the address range is defined by the address given by FCHA0, masked with the  
bits set to ’1’ in FCHA1.  
Example 1 (Point and mask range definition):  
- FCHCR_REN = 0  
- FCHA0 = 0x000F:A300  
- FCHA1 = 0x0000:FFFF  
The non-cacheable area is defined from 0x000F:0000 to 0x000F:FFFF.  
Example 2 (Point to point range definition):  
- FCHCR_REN = 1  
- FCHA0 = 0x000F:A300  
- FCHA1 = 0x000F:F7FF  
The non-cacheable area is defined from 0x000F:A300 to 0x000F:F7FF.  
178  
Chapter 12 Instruction Cache  
1.General description  
Chapter 12 Instruction Cache  
This chapter describes the instruction cache memory included in MB91460 family members and  
its operation.  
1. General description  
The instruction cache is a fast local memory for temporary storage. Once an instruction is  
accessed to be fetched from external slower memory, the instruction cache holds the instruction  
code inside to increase the speed of accessing the same code from then on. The instruction  
cache data RAM and tag RAM are made directly read/write-accessible by software by setting the  
RAM mode. To turn off the instruction cache after turning it on once, be sure to use the  
subroutine shown in Section 4.2.4 "Settings for handling the I-Cache".  
2. Main body structure  
•
•
•
FR basic instruction length:  
Block arrangement system:  
Block  
2 bytes  
2-way set associative system  
128 blocks per way  
16 bytes per block (= 4 sub-blocks)  
4 bytes per sub-block (= 1 bus access unit)  
Figure 2-1 Instruction Cache Structure  
4 bytes  
4 bytes  
I3  
4 bytes  
I2  
4 bytes  
I1  
4 bytes  
I0  
Way 1  
Cache tag  
Sub-block 2  
Sub-block 3  
Sub-block 1  
Sub-block 0  
Block 0  
128 Blocks  
Cache tag  
Cache tag  
Sub-block 2  
Sub-block 2  
Sub-block 3  
Sub-block 3  
Sub-block 1  
Sub-block 1  
Block 127  
Block 0  
Sub-block 0  
Sub-block 0  
Way 2  
128 Blocks  
Cache tag  
Sub-block 2  
Sub-block 3  
Sub-block 1  
Block 127  
Sub-block 0  
179  
     
Chapter 12 Instruction Cache  
2.Main body structure  
Figure 2-2 Instruction Cache Tag  
Way 1  
31  
09  
08  
Address tag  
Reserved  
07  
06  
05  
04  
03  
02  
01  
00  
SBV3 SBV2 SBV1 SBV0 TAGV Reserved LRU  
ETLK  
TAG valid  
Sub-block valid  
LRU  
Entry lock  
Way 2  
31  
09  
08  
Address tag  
07  
Reserved  
06  
05  
04  
03  
02  
01  
00  
SBV3 SBV2 SBV1 SBV0 TAGV  
Reserved  
ETLK  
TAG valid  
Sub-block valid  
Entry lock  
[Bits 31 to 9] Address tag  
This area stores the upper 23 bits of the memory address of the instruction cached in the  
corresponding block. For example, memory address IA of the instruction data stored in sub-  
block k in block i is obtained from the following equation:  
11  
4
2
IA = address tag x 2 + i x 2 + k x 2  
The address tag is used to check for a match with the instruction address requested for  
access by the CPU. The CPU and cache behave as follows depending on the result of the  
cache check:  
1) When the requested instruction data exists in the cache (hit), the cache transfers the data  
to the CPU within the cycle.  
2) When the requested instruction data does not exist in the cache (miss), the CPU and  
cache obtain the data loaded by external access at the same time.  
[Bits 7 to 4] SBV3 to SBV0: Sub-block valid bits  
When SBV* contains "1", the corresponding sub-block holds the current instruction data at  
the address located by the tag. Each sub-block usually holds two instructions (including  
immediate-value transfer instructions).  
[Bit 3] TAGV: TAG valid bit  
This bit indicates whether the address tag value is valid. When the bit contains "0", the  
corresponding block is invalid regardless of the settings of the sub-block validation bits. (The  
180  
Chapter 12 Instruction Cache  
2.Main body structure  
FLUSHbit is set to "0" when the cache is flushed.)  
[Bit 1] LRU bit (way 1 only)  
This bit exists only in the instruction cache tag in way 1. The bit indicates way 1 or 2 as the  
way containing the last entry accessed in the selected set. When set to "1", the LRU bit  
indicates that the entry of the set in way 1 is the last entry accessed. When set to "0", it  
indicates that the one in way 2 is the last entry accessed.  
[Bit 0] ETLK: Entry lock bit  
This bit is used to lock all the entries in the block corresponding to the tag in the cache. When  
set to "1", the entries are locked and are not updated when a cache miss occurs. Note,  
however, that invalid sub-blocks are updated. If a cache miss occurs with both of ways 1 and  
2 in the entry lock states, access to external memory takes place after losing one cycle used  
for evaluating the cache miss.  
● Control register structure  
ISIZE (8 bit)  
7
6
5
4
3
2
1
0
Initial value  
0000 03C7  
---- --10  
-
-
-
-
-
-
-
-
-
-
-
-
SIZE1 SIZE0  
R/W R/W  
H
B
ISIZE [bits 1 to 0] : SIZE1 and SIZE0  
These bits set the cache capacity. The combination of the settings determines the cache size,  
IRAM size, and the address map in RAM mode as shown in Figure I-CACHE-3. When the  
cache size is changed, be sure to flush the cache and release the entry lock before turning on  
the cache.  
CACHE Size Register  
SIZE1  
SIZE0  
Size  
0
0
1
1
0
1
0
1
1 KB  
2 KB  
4 KB (initial value)  
Setting disabled  
ICHCR [bits 7 to 0] :  
The ICHCR (I-Cache Control Register) controls the operation of the instruction cache. Writing  
a value to the ICHCR has no effect on the caching of any instruction fetched within three  
cycles that follow.  
ICHCR (8 bit)  
7
6
5
4
3
2
1
0
Initial value  
0000 03E7  
0-00 0000  
RAM  
R/W  
-
-
GBLK ALFL EOLK ELKR FLUSH ENAB  
R/W R/W R/W R/W R/W R/W  
H
B
181  
Chapter 12 Instruction Cache  
2.Main body structure  
[Bit 7] RAM: RAM Mode  
Setting this bit to "1" causes the cache to operate in RAM mode. By placing the cache in RAM  
mode, the cache RAM is mapped as shown in Figure I-CACHE-3 while the cache is enabled  
with the ENAB bit set to "1".  
[Bit 5] GBLK: Global lock bit  
This bit locks all of the current entries in the cache. Setting the GBLK bit to "1" prevents the  
valid entries in the cache from being updated when a cache miss occurs. Note, however, that  
invalid sub-blocks are updated then. Fetching of instruction data in the global lock state is  
performed in the same way as not in that state.  
[Bit 4] ALFL: Auto lock fail bit  
This bit (ALFL) is set to 1 if locking is attempted on an entry that is already locked. If, during  
entry autolock, an entry update is attempted on an entry that is already locked, no new entry  
is locked in the instruction cache regardless of what the user intends. Reference this bit for  
debugging of a program or similar purpose. Clear this bit by writing 0 to it.  
[Bit 3] EOLK: Entry auto lock bit  
This bit enables or disables auto-locking for each entry in the instruction cache. An entry  
accessed (but resulting in a miss) with the EOLK bit containing "1" is locked when the entry  
lock bit in the cache tag is set to "1" by hardware. Once locked, the entry is not updated at  
any cache miss that follows until it is unlocked. Note, however, that invalid sub-blocks are  
updated. To ensure the entry lock, set this bit after flushing.  
[Bit 2] ELKR: Entry lock release bit  
This bit specifies the clearing of the entry lock bits in all cache tags. When the ELKR bit is set  
to "1" in a cycle, the entry lock bits in all cache tags are cleared to "0" in the next cycle. Note  
that the content of this bit is retained for only one clock cycle; it is cleared to "0" in the clock  
cycle that follows.  
[Bit 1] FLUSH: Flush bit  
This bit specifies the flushing of the instruction cache. Setting the FLUSH bit to "1" flushes the  
cache. Note that the content of this bit is retained for only one clock cycle; it is cleared to "0"  
in the clock cycle that follows.  
[Bit 0] ENAB:Enable bit  
This bit enables or disables the instruction cache. Setting the ENAB bit to "0" disables the  
cache, where the CPU directly accesses external memory to request instructions without  
cache intervention. While disabled, the cache retains its contents.  
182  
Chapter 12 Instruction Cache  
2.Main body structure  
Figure 2-3 I-Cache Address Map  
183  
Chapter 12 Instruction Cache  
2.Main body structure  
Figure 2-4 I-Cacheable Area  
184  
Chapter 12 Instruction Cache  
3.Operating mode conditions  
3. Operating mode conditions  
● Cache status in various operating modes  
The table below indicates the prevailing state for disable and flush when the associated bit is  
changed by bit manipulation instruction, etc.  
Immediately  
after a Reset  
Disable (FNAB=0)  
Flushed  
Contents  
undefined  
The preceding state is held.  
Rewriting is impossible while  
the cache is disabled.  
The preceding state is held.  
Cache Memory  
Tag  
Address  
Contents  
undefined  
The preceding state is held.  
Rewriting is impossible while  
the cache is disabled.  
The preceding state is held.  
Tag  
Sub-block  
Valid Bit  
Contents  
undefined  
The preceding state is held.  
Rewriting is impossible while  
the cache is disabled.  
The preceding state is held.  
The preceding state is held.  
LRU Bit  
Contents  
undefined  
The preceding state is held.  
Rewriting is impossible while  
the cache is disabled.  
Entry Lock  
Bit  
Contents  
undefined  
The preceding state is held.  
Rewriting is impossible while  
the cache is disabled.  
The preceding state is held.  
(entry lock release is required)  
TAG Valid  
Bit  
Contents  
undefined  
The preceding state is held.  
Flushingis possible while the  
cache is disabled.  
All entries are invalid.  
RAM  
Normal Mode  
Unlock  
The preceding state is held.  
Flushing is possible while  
the cache is disabled.  
The preceding state is held.  
The preceding state is held.  
The preceding state is held.  
The preceding state is held.  
The preceding state is held.  
The preceding state is held.  
Control  
Register  
Global  
Lock  
The preceding state is held.  
Rewriting is possible while  
the cache is disabled.  
Auto lock  
Fail  
No fail  
The preceding state is held.  
Rewriting is possible while  
the cache is disabled.  
Entry Auto  
Lock  
Unlock  
The preceding state is held.  
Rewriting is possible while  
the cache is disabled.  
Entry Lock  
Release  
No release  
The preceding state is held.  
Rewriting is possible while  
the cache is disabled.  
Enable  
Flush  
Disable  
Disabled  
Not flushed  
The preceding state is held.  
Rewriting is possible while  
the cache is disabled.  
Flushed in cycle following  
memory accessing.  
Reverts to 0 subsequently.  
185  
 
Chapter 12 Instruction Cache  
4.Cacheable areas in the instruction cache  
● Cache Entry Update  
Cache entries are updated as shown in the following table.  
Unlock  
Lock  
Hit  
Not updated  
Not updated.  
Miss  
The memory data is loaded, and the Not updated at tag miss.  
cache entry data is updated.  
Updated when sub-block invalid.  
4. Cacheable areas in the instruction cache  
•
The instruction cache can cache data only in external bus space.  
•
Even when the contents of external memory are updated by DMA transfer, the instruction  
cache does not refresh its contents to be coherent with the new contents of the memory. In  
this case, flush the cache to give it coherence.  
•
Each chip select area can be set as a non-cacheable area. The penalty for this is one cycle  
compared to the cache off state. (See Section 5.5 "Setting Chip Select Areas" in Chapter 5  
"EXTERNAL INTERFACE".)  
5. Settings for handling the I-Cache  
1)  
Initializing  
To use the I-Cache, first, clear the cache contents. Erase the old data by setting the register  
FLUSH bit and ELKR bit to 1.  
Idi #0x000003e7,r0  
Idi #0B00000110,r1  
// I-Cache control register address  
// FLUSH bit (bit 1)  
// ELKR bit (bit 2)  
stb r1,@r0  
// Writing to register  
The cache is now initialized.  
Enabling (turning ON) cache  
To enable the I-Cache, set the ENAB bit to 1.  
Idi #0x000003e7,r0  
2)  
// I-Cache control register address  
// ENAB bit (bit 0)  
Idi #0B00000001,r1  
stb r1,@r0  
// Writing to register  
All subsequently-accessed instructions will be cached.  
Cache can be validated and initialized at the same time.  
Idi #0x000003e7,r0  
Idi #0B00000111,r1  
// I-Cache control register address  
// ENAB bit (bit 0)  
// FLUSH bit (bit 1)  
// ELKR bit (bit 2)  
// Writing to register  
stb r1,@r0  
3)  
Disabling (turning OFF) cache  
186  
   
Chapter 12 Instruction Cache  
5.Settings for handling the I-Cache  
To disable the I-Cache, set the ENAB bit to 0.  
Idi #0x000003e7,r0  
// I-Cache control register address  
Idi #0B00000000,r1  
// ENAB bit (bit 0)  
stb r1,@r0  
// Writing to register  
In the resultant state (same as state prevailing after reset), there appears to be no cache.  
The cache can be turned off if the processing may experience problems due to cache  
overhead  
4)  
Locking all cached instructions  
To lock all the currently-cached instructions in the I-Cache, set the register GBLK bit to 1.  
The ENAB bit must also be set to 1. If it is not, the cache is turned OFF, so instructions  
locked in the cache cannot be used.  
Idi #0x000003e7,r0  
Idi #0B00100001,r1  
// I-Cache control register address  
// ENAB bit (bit 0)  
// GBLK bit (bit 5)  
stb r1,@r0  
// Writing to register  
5)  
Locking specific cached instructions  
To lock a specific group of instructions (e.g., subroutines) in the cache, set the EOLK bit to 1  
before executing such instructions.  
Instructions locked in this manner are accessed rapidly as if using high-speed internal ROM.  
Idi #0x000003e7,r0  
Idi #0B00001001,r1  
// I-Cache control register address  
// ENAB bit (bit 0)  
// EOLK bit (bit 3)  
stb r1,@r0  
// Writing to register  
The above instruction lock becomes effective starting with the instruction next to the stb  
instruction although it depends on the memory wait count. Set the EOLK bit to 0 when the  
group of instructions which want to lock is ended.  
Idi #0x000003e7,r0  
Idi #0B00000101,r1  
// I-Cache control register address  
// ENAB bit (bit 0)  
// EOLK bit (bit 3)  
stb r1,@r0  
// Writing to register  
6)  
Unlocking cached instructions  
To release the lock, proceed as follows.  
Idi #0x000003e7,r0  
Idi #0B00000000,r1  
stb r1,@r0  
// I-Cache control register address  
//Cash disabled  
// Writing to register  
// ELKR bit (bit 2)  
Idi #0B00000100,r1  
stb r1,@r0  
// Writing to register  
187  
Chapter 12 Instruction Cache  
5.Settings for handling the I-Cache  
Only lock information is released; locked instructions are replaced sequentially with new  
instructions according to the state of the LRU bit.  
188  
Chapter 13 Clock Control  
1.Overview  
Chapter 13 Clock Control  
1. Overview  
The clock control circuit consists of the source oscillator, base clock generator, and operating clock generator.  
The circuit supports a range of clock speeds from the high speed clock (100MHz maximum) to the low speed  
clock (32.768kHz).  
Source oscillation  
Base clock generator  
Operating clock generator  
Divider  
Divider  
Divider  
CPU clock  
Main clock  
(source oscillation)  
Divide by 2  
PLL  
Peripheral clock  
External bus clock  
Selector  
Sub clock  
(source oscillation)  
Base clock  
2. Features  
■ Source oscillation  
• Main clock (F  
): 4MHz  
CL-MAIN  
Input from the X0/X1 pins and used as the high speed clock  
• Subclock (F ): 32.768kHz  
CL-SUB  
Input from the X0A/X1A pins and used as the low speed clock  
• Subclock (F ): 100kHz  
CL-SUB  
RC oscillator and used as the low speed clock  
■ Base clock (F): Selectable from 3 different clocks  
• Main PLL (programmable) : F  
x (MxN)\M  
CL-MAIN  
CL-MAIN  
CL-SUB  
• Main clock divided by 2  
• Subclock  
: F  
: F  
divided by 2  
■ Operating clocks: Selectable from 16 different speeds  
• CPU clock (CLKB): F/1, /2, /3, /4, /5, /6, /7, /8, ..., /16  
The clock used by the CPU, internal memory, and internal buses. The circuits that use this clock are as  
follows.  
•
•
•
CPU, internal RAM, internal ROM, bit search module,  
I bus, D bus, F bus, X bus  
On-chip debug support unit (DSU)  
• Peripheral clock (CLKP): F/1, /2, /3, /4, /5, /6, /7, /8, ..., /16  
The clock used by the peripheral functions and peripheral bus. The circuits that use this clock are as  
follows.  
•
•
•
•
•
Peripheral bus  
Clock controller (bus interface unit only)  
Interrupt controller  
I/O ports  
External interrupt inputs, UART, 16-bit timer, and similar peripheral functions  
189  
       
Chapter 13 Clock Control  
3.Configuration  
• External bus clock (CLKT): F/1, /2, /3, /4, /5, /6, /7, /8, ..., /16  
The clock used by the external bus expansion interface. The circuits that use this clock are as follows.  
•
•
External bus expansion interface  
External CLK output  
3. Configuration  
Figure 3-1 Configuration Diagram  
DIVR1: bit 7-4  
No division  
Divide by 2  
Divide by 3  
Divide by 4  
Divide by 5  
Divide by 6  
Divide by 7  
Divide by 8  
Divide by 9-15  
Divide by 16  
DIVR0: bit 7-4  
No division  
Divide by 2  
Divide by 3  
Divide by 4  
Divide by 5  
Divide by 6  
Divide by 7  
Divide by 8  
Divide by 9-15  
Divide by 16  
T3-T0  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
B3-B0  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
Set PLL multiplier  
PLL1EN  
CLKR: bit2  
Halt PLL  
0
1
PLLDIVM: bit5-0  
PLLDIVN: bit5-0  
Enable (start) PLL  
Set PLL autogear  
OSCDS1  
OSCCR: bit0  
Main clock continues to  
run in subclock mode  
0
PLLDIVG: bit5-0  
PLLMULG: bit7-0  
1000-1110  
1000-1110  
Main clock halts in  
subclock mode  
1
1111  
1111  
CPU clock  
X0  
X1  
Main clock  
source  
Divider  
PLL  
(F  
)
CLKB  
(F  
)
CLK-MAIN  
Peripheral clock  
(F  
Divider  
)
CLKP  
Divide by 2  
Subclock  
source  
Base  
clock  
(φ)  
External bus clock  
(F  
X0A  
X1A  
Divider  
)
CLKT  
( F  
)
CLK-SUB  
Base clock  
(φ)  
DIVR1: bit3-0  
P3-P0  
No division  
Divide by 2  
Divide by 3  
Divide by 4  
Divide by 5  
Divide by 6  
Divide by 7  
Divide by 8  
Divide by 9-15  
Divide by 16  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000-1110  
1111  
CLKS1-  
CLKS0  
Permitted  
change  
CLKR: bit6-4  
SCKEN  
CLKR: bit3  
Main clock divided by 2  
(main clock mode)  
0
1
Subclock selection prohibited  
Subclock selection enabled  
00  
00=>01, 10  
Main clock divided by 2  
(main clock mode)  
01=>11, 00  
10=>00  
01  
10  
11  
Main PLL  
(main clock mode)  
OSCD2  
STCR: bit1  
0
1
Continue oscillation in stop mode  
Halt oscillation in stop mode  
Subclock  
(subclock mode)  
11=>01  
OSCD1  
STCR: bit0  
0
1
Continue oscillation in stop mode  
Halt oscillation in stop mode  
Figure 3-2 Register List  
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Chapter 13 Clock Control  
4.Registers  
4. Registers  
4.1 CLKR: Clock Source Control Register  
Selects the clock source for the base clock used to run the MCU and controls the PLL.  
• CLKR: Address 0484h (Access: Byte)  
7
-
6
-
5
-
4
-
3
2
1
0
bit  
SCKEN PLL1EN CLKS1  
CLKS0  
Initial value (INIT pin input,  
X
X
X
X
0
0
0
0
watchdog reset)  
Initial value  
(Software reset)  
X
X
X
X
X
X
X
X
R/W0  
R/W0  
R/W0  
R/W0  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7-4: Reserved bitAlways write “0” to this bit. The read value is the value written.  
• Bit3: Subclock select enable  
SCKEN  
Function  
0
1
Prohibit subclock selection [Initial value]  
Enable subclock selection  
• Modifying the subclock selection enable bit (SCKEN) while the subclock is selected as the clock source  
(CLKS[1:0]=“11”) is prohibited (result is not guaranteed). Only modify the setting when the main clock is  
selected.  
(See the explanation for the clock source selection bits (CLKS[1:0]) for details of how to change the clock  
source.)  
• Bit2: Enable main PLL operation  
PLL1EN  
Function  
0
1
Halt main PLL (Initial value)  
Enable main PLL operation  
• Modifying the main PLL operation enable bit (PLL1EN) while the main PLL is selected as the clock  
source (CLKS[1:0]=“10”) is prohibited.  
• Modifying the main PLL operation enable bit (PLL1EN) while the clock autogear function is active (gear  
up or gear down) is prohibited. Always check the gear status flags before changing the PLL state (see  
chapter "Clock Auto Gear Up/Down" on P. 213 ).  
• If the main clock oscillation is halted (STCR.OSCD1=“1”), the main PLL halts during stop mode even if  
the PLL enable bit (PLL1EN) is set to “1”. If main PLL operation is enabled (PLL1EN=“1”), the main clock  
operates using the PLL after recovering from stop mode.  
(See the explanation for the clock source selection bits (bits 1-0:) for details of changing the clock  
source.)  
• Bit1-0: Clock source selection  
CLKS1 CLKS0  
Clock source setting  
Main clock input from X0/X1 divided by 2 (Initial value)  
Main clock input from X0/X1 divided by 2  
Main PLL  
Mode  
Main clock mode  
0
0
1
1
0
1
0
1
Main clock mode  
Main clock mode  
Subclock mode  
Subclock  
• When changing the clock mode, the value of CLKS0 may not be modified while CLKS1 is “1”.  
The table below lists the cases in which the CLKS1- CLKS0 bits may be modified.  
• There is no setting to select the subclock divided by 2.  
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Chapter 13 Clock Control  
4.Registers  
• After setting “11B” (subclock), insert one or more NOP instructions.  
• Selecting the subclock as the clock source is prohibited while the subclock selection enable bit (SCKEN)  
is “0”. (See table for details.)  
Table 4-1 Cases When the CLKS1 and CLKS0 Bits May or May Not be Modified  
Modify permitted  
“00” → “01” or “10”  
“01” → “11” or “00”  
“10” → “00”  
Modify not permitted  
“00” → “11”  
“01” → “10”  
“10” → “01” or “11”  
“11” → “00” or “10”  
“11” → “01”  
Example: To select the subclock after an INIT reset, first write “01 ” and then write “11 ” (subclock).  
B
B
(See “8. Caution (Page No.205)”.)  
192  
Chapter 13 Clock Control  
4.Registers  
4.2 DIV0R: Clock Division Setting Register 0  
Sets the division ratio for the clocks used for internal device operation.  
DIVR0: Address 0486h (Access: Byte, Half-word)  
7
6
5
4
3
2
1
0
bit  
B3  
B2  
B1  
B0  
P3  
P2  
P1  
P0  
Initial value (INIT pin input,  
watchdog reset)  
0
0
0
0
0
0
1
1
Initial value  
(software reset)  
X
X
X
X
X
X
X
X
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Sets up the clock for the CPU and internal buses (CLKB), and the clock for the peripheral circuits and  
peripheral bus (CLKP).  
• Bit7-4: CLKB division selection  
B3-B0  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
CPU clock (CLKB) division ratio  
Φ/1 (initial value)  
Φ/2  
Φ/3  
Φ/4  
Φ/5  
Φ/6  
Φ/7  
Φ/8  
Φ/9  
Φ/10  
Φ/11  
Φ/12  
Φ/13  
Φ/14  
Φ/15  
Φ/16  
• Do not change the division ratio with B3-B0 if current CLKB frequency is equal or above 80MHz !  
• Sets the clock division ratio for the clock used by the CPU, internal memory, and internal buses (CLKB).  
The 16 options listed in the table are available.  
• Do not set a division ratio that exceeds the maximum operating frequency of the device.  
• Bit3-0: CLKP division selection  
P3-P0  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
Peripheral clock (CLKP) division ratio  
Φ/1  
Φ/2  
Φ/3  
Φ/4 (initial value)  
Φ/5  
Φ/6  
Φ/7  
Φ/8  
Φ/9  
Φ/10  
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Chapter 13 Clock Control  
4.Registers  
1010  
1011  
1100  
1101  
1110  
1111  
Φ/11  
Φ/12  
Φ/13  
Φ/14  
Φ/15  
Φ/16  
• Sets the clock division ratio for the clock used by the peripheral circuits and peripheral bus (CLKP).  
The 16 options listed in the table are available.  
• Do not set a division ratio that exceeds the maximum operating frequency of the MCU.  
194  
Chapter 13 Clock Control  
4.Registers  
4.3 DIV1R: Clock Division Setting Register 1  
Sets the division ratio for the clocks used for internal device operation.  
• DIVR1: Address 0487h (Access: Byte, Half-word)  
7
T3  
0
6
T2  
0
5
T1  
0
4
T0  
0
3
–
2
–
1
–
0
–
bit  
0
0
0
0
Initial value (INIT pin input, watchdog reset)  
Initial value (software reset)  
Attribute  
X
X
X
X
X
X
X
X
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
Sets the clock division ratio (relative to the base clock) for the clock used by the external bus interface (CLKT).  
• Bit7-4: CLKT division selection  
T3-T0  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
External bus clock (CLKT) division ratio  
Φ/1 (initial value)  
Φ/2  
Φ/3  
Φ/4  
Φ/5  
Φ/6  
Φ/7  
Φ/8  
Φ/9  
Φ/10  
Φ/11  
Φ/12  
Φ/13  
Φ/14  
Φ/15  
Φ/16  
• Sets the clock division ratio for the clock used by the external bus interface (CLKT).  
The 16 options listed in the table are available.  
• Do not set a division ratio that exceeds the maximum operating frequency of the device.  
• If you modify the CLKP division selection bits, the new division ratio applies from the next clock after the  
setting is modified.  
• Bit3-0: Reserved bit Always write “0” to this bit. The read value is the value written.  
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Chapter 13 Clock Control  
4.Registers  
4.4 CSCFG: Clock Source Configuration Register  
This register controls the main clock oscillation in subclock mode  
• CSCFG: Address 04AEh (Access: Byte)  
7
6
5
4
3
2
1
0
bit  
EDSUEN PLLLOCK RCSEL MONCKI  
CSC3  
CSC2  
CSC1  
CSC0  
Initial value (INIT pin  
input, watchdog reset)  
0
X
0
0
0
0
0
0
Initial value  
(software reset)  
X
X
R
X
X
X
X
X
X
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• bit7: EDSU/MPU Enable  
EDSUEN  
Function  
EDSU/MPU is (clock) disabled [Initial value]  
0
1
EDSU/MPU is (clock) enabled  
• bit6: PLL Lock  
PLLLOCK  
Function  
0
1
PLL is in the un-locked state  
PLL is in the locked state  
• bit5: RC Oscillator Selector  
RCSEL  
Function  
0
1
RC oscillation is set to 100 kHz [Initial value]  
RC oscillation is set to 2 MHz  
The selected oscillation frequency is supplied to Clock Control Unit (for Subclock Operation) and Flash Security Unit  
(change the oscillation to 2 MHz for faster CRC generation). Hardware Watchdog (RC based Watchdog), Real Time  
Clock, Calibration Unit, LCD and Clock Supervisor Module are always supplied with 100 kHz independent of this  
setting.  
• bit4: Clock Monitor MONCLK inverter  
MONCKI  
Function  
MONCLK mark level is low [Initial value]  
MONCLK mark level is high  
0
1
See chapter “Clock Monitor (Page No.941)” about information about this function.  
• Bit3-0: Clock Source Selection  
CSC3-CSC0  
Function  
--00  
--01  
--10  
--11  
-0--  
Real Time Clock is sourced by Main Oscillation  
Real Time Clock is sourced by Sub Oscillation  
Real Time Clock is sourced by RC Oscillation  
Setting prohibited  
Subclock Calibration is sourced by Sub Oscillation  
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Chapter 13 Clock Control  
4.Registers  
-1--  
0---  
1---  
Subclock Calibration is sourced by RC Oscillation  
LCD Controller is sourced by Sub Oscillation  
LCD Controller is sourced by RC Oscillation  
197  
Chapter 13 Clock Control  
4.Registers  
4.5 OSCCR: Oscillation Control Register  
This register controls the main clock oscillation in subclock mode  
• OSCCR: Address 04CCh (Access: Byte)  
7
–
6
–
5
–
4
–
3
–
2
–
1
0
bit  
OSCDS2 OSCDS1  
Initial value (INIT pin  
input, watchdog reset)  
X
X
X
X
X
X
X
X
0
0
0
0
Initial value  
(software reset)  
X
X
X
X
RX/WX RX/WX RX/WX RX/WX RX/WX RX/WX  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• bit7-2: Undefined bit  
Writing does not affect the operation. The read value is undefined.  
• bit1: Halt sub clock oscillation in subclock on RC oscillation mode bit  
OSCDS2  
Operation when written to  
Read value meaning  
Does not halt sub clock during subclock on RC  
oscillation mode.  
Sub clock mode can be selected after the  
oscillation stabilization time elapses.  
0
Halt sub clock during subclock on RC oscillation  
mode.  
1
Selecting sub clock mode is prohibited.  
• When the sub clock is selected (CSVCR.SCKS=’0’), specifying the sub clock to halt during subclock  
mode (OSCDS2=“1”) is prohibited.  
(See “8. Caution (Page No.205)”.)  
• bit0: Halt main clock oscillation in subclock mode bit  
OSCDS1  
Operation when written to  
Does not halt main clock during subclock mode.  
Halt main clock during subclock mode.  
Read value meaning  
Main clock mode can be selected after the  
oscillation stabilization time elapses.  
0
1
Selecting main clock mode is prohibited.  
• When the main clock is selected (CLKS[1:0]=“00”, “01”, “10”), specifying the main clock to halt during  
subclock mode (OSCDS1=“1”) is prohibited.  
(See “8. Caution (Page No.205)”.)  
198  
Chapter 13 Clock Control  
5.Operation  
5. Operation  
This section describes how to setup and switch between clocks.  
5.1 Clock Setup Sequence (Example)  
(1) Main clock oscillation stabilization, sub clock oscillation stabilization  
(2) Operate using initial values (main clock divided by 2).  
Setup  
operating  
clocks.  
(2) Set divide ratios for operating clocks. (CLKB, CLKP, CLKT)  
(3) Select PLL multiplier. ( PLLS[2:0] )  
(4) Enable main PLL operation (PLL1EN), and enable sub clock operation (PLL2EN).  
(4) Wait for main PLL to lock (See oscillation stabilization wait chapter).  
(5) Select clock source. (CLKS[1:0] )  
Setup  
base  
clock.  
Main clock mode (divided by 2)  
(“00”)  
Main clock mode (divided by 2)  
(“01”)  
Main PLL mode  
(“10”)  
Sub clock mode  
(“11”)  
5.2 Halting and Restarting the Main Clock Oscillation During Subclock Mode (Example)  
(1) Select sub clock mode.  
Select clock source. (CLKS [1:0] = “11”)  
(2) Halt main PLL (PLL1EN = "0"), halt main clock oscillation (OSCDS1 = "0")  
Sub clock mode  
with main clock  
halted  
(3) Change to standby mode  
(See standby chapter.)  
(See standby chapter.)  
(3) Recover from standby mode.  
Sub clock mode operation  
(4) Main clock oscillation (OSCDS1 = “0”)  
Main clock oscillation stabilization (See oscillation stabilization wait chapter)  
(1) Select main clock mode (divided by 2).  
Select clock source. (CLKS[1:0] = “01”)  
Change to main  
PLL operation  
(1) Start main PLL oscillation (PLL1E = “01”)  
(4) Wait for main PLL to lock  
(See oscillation stabilization wait chapter)  
(5) Select main PLL mode.  
Select clock source. (CLKS[1:0] = “00”)  
Select clock source. (CLKS[1:0] = “11”)  
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Chapter 13 Clock Control  
5.Operation  
5.3 Notes  
■ Main PLL control  
After initialization, the main PLL oscillation is halted. While halted, the output of the main PLL cannot be  
selected as the clock source.  
After the program starts, first set the multiplier for the main PLL that you want to use as the clock source and  
then, after allowing a time for the main PLL to lock, change the clock source. The recommended method for  
waiting for the main PLL to lock is to use the timebase timer interrupt.  
You cannot halt the main PLL while the output of the main PLL is selected as the clock source.  
Writing to the register has no effect. If you wish to stop the main PLL such as when changing to stop mode,  
first select the main clock divided by 2 as the clock source and then halt the main PLL.  
If the main clock oscillation is set to halt during stop mode by the main clock oscillation stop bit  
(STCR.OSCD1=“1”), the main PLL stops automatically when the MCU changes to stop mode and you do not  
need to halt the main PLL (CLKR.PLL1EN=“0”) explicitly beforehand. The main PLL also restarts automatically  
on recovering from stop mode. When the oscillation is not set to halt during stop mode (STCR.OSCD1=“0”),  
the main PLL does not stop automatically. In this case, halt the main PLL explicitly (CLKR.PLL1EN=“0”) before  
changing to stop mode.  
■ Main PLL multiplier  
When changing the main PLL multiplier setting to a value different to the initial value, set this before or at the  
same time as you enable the main PLL after program execution starts. After changing the multiplier setting,  
wait for the main PLL lock time before switching the clock source. The recommended method for waiting for  
the main PLL to lock is to use the timebase timer interrupt.  
To modify the main PLL multiplier setting during normal operation, first change the clock source to something  
other than the main PLL. As in the above case, after changing the multiplier setting, wait for the main PLL lock  
time before changing the clock source.  
The main PLL multiplier setting can be changed while the main PLL is in use. In this case, the MCU  
automatically goes to the oscillation stabilization wait state after the multiplier setting is modified and program  
execution halts for the time specified as the oscillation stabilization wait time. Program execution doe not halt  
when changing to a clock source other than the main PLL.  
■ Clock division  
The clocks used to drive the internal operation of the device allow division ratios relative to the base clock to  
be set independently for each clock. This function allows the optimum operating frequency to be selected for  
each circuit.  
The division ratios are set in the operating clock division setting registers (DIVR0 and DIVR1). These registers  
contain 4-bit settings that specify the ratio for each clock. The division ratio relative to the base clock =  
(register value+1). The duty ratio is always 50, even if an odd numbered division ratio is set.  
If a setting is modified, the new setting applies from the next rising edge of the clock.  
The division ratio settings are not initialized by an operation reset (RST) and the settings from before the reset  
are maintained. The ratio settings are only initialized by a settings initialization reset (INIT). When changing  
the clock source from its initial setting to a high speed clock, always set the division ratio first.  
Device operation is not guaranteed if the result of the clock source selection, main PLL multiplier setting, and  
division ratio setting is a frequency that is higher than the maximum permitted frequency. Please take care  
with these settings. (In particular, take care with the sequence in which you change clock source settings.)  
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Chapter 13 Clock Control  
6.Settings  
6. Settings  
Table 6-1 Settings for Operating at 1/2 of the Main Clock  
Setting  
procedure*  
Setting  
Setting register  
Clock source control register (CLKR)  
Clock source selection  
See 7.3  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-2 Settings for Operating Using the Main PLL  
Setting  
procedure*  
Setting  
Main PLL operation enable  
Clock source selection  
Setting register  
See 7.1  
See 7.3  
Clock source control register (CLKR)  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-3 Settings for Operating Using the Subclock  
Setting  
procedure*  
Setting  
Subclock selection enable  
Clock source selection  
Setting register  
See 7.1  
See 7.3  
Clock source control register (CLKR)  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-4 Settings for Selecting the Division Ratio for the Operating Clocks  
Setting  
procedure*  
Setting  
Setting register  
Clock source selection  
Operating clock division ratio selection  
Clock source control register (CLKR)  
See 7.3  
Operating clock division setting registers  
(DIVR0, DIVR1)  
See 7.4  
*: For the setting procedure, refer to the section indicated by the number.  
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Chapter 13 Clock Control  
7.Q & A  
7. Q & A  
7.1 How do I enable or disable clock operation?  
• There is no operation enable bit for the main clock. Main clock operation is always enabled.  
(Halting the oscillation in subclock mode or stop mode is handled separately.)  
• Main PLL operation is enabled by the main PLL operation enable bit (CLKR.PLL1EN).  
Operation  
Main PLL operation enable bit (PLL1EN)  
To halt the main PLL  
Set to “0”.  
Set to “1”.  
To enable operation of the main PLL  
Initially, the PLL is halted and therefore PLL operation must be enabled and the PLL started after setting the PLL  
multiplier ratio.  
• The subclock on the MB91460 does not halt and therefore no corresponding operation enable bit is  
provided.  
Instead, the subclock selection enable bit (CLKR.SCKEN) is used.  
Operation  
Subclock selection enable bit (SCKEN)  
Subclock selection prohibited  
To enable selection of the subclock  
Set to “0”.  
Set to “1”.  
7.2 How do I select the main PLL multiplier ratio?  
• The PLL multiplier can be set by using the PLL interface registers PLLDIVM and PLLDIVN (see chapter  
"PLL Interface" on P. 207 ).  
7.3 How do I select the operating clock source?  
Use the clock source selection bits (CLKR.CLKS[1:0]) to select main clock divided by 2, main PLL, or the  
subclock as the operating clock source.  
Operating clock source  
Clock source selection bits (CLKS[1:0])  
To change from the initial value to the main clock divided by 2 Set initial values “00” or “01”.  
To change from the initial value to the main PLL  
To change from the initial value to the subclock  
To change from the subclock to the main clock divided by 2  
To change from the subclock to main PLL  
Change from the initial values “00” to “10”.  
First change from the initial values “00” to “01”, and  
then to “11”.  
Change from “11” to “01”.  
First change from “11” to “01”, next set  
“00”, and then set “10”.  
To change from main PLL to the main clock divided by 2  
To change from main PLL to the subclock  
Change from “10” to “00”.  
First change from “10” to “00”, next set  
“01”, and then set “11”.  
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Chapter 13 Clock Control  
7.Q & A  
7.4 How do I set the operation clock division ratios?  
• CPU clock setting  
The CPU clock setting is set using the CLKB division ratio selection bits (DIVR0.B[3:0]).  
Example frequency  
CLKB division ratio selection  
bits(B[3:0])  
PLL multiplier ratio  
When F = 32MHz When F = 16MHz  
Φ
Φ
F
F
F
F
F
F
F
F
F
= 32.0MHz  
F
F
F
F
F
F
F
F
F
= 16.0MHz  
To select no division  
To select divide by 2  
To select divide by 3  
To select divide by 4  
To select divide by 5  
To select divide by 6  
To select divide by 7  
To select divide by 8  
To select divide by 16  
Set to “0000”.  
Set to “0001”.  
Set to “0010”.  
Set to “0011”.  
Set to “0100”.  
Set to “0101”.  
Set to “0110”.  
Set to “0111”.  
Set to “1111”.  
CLKB  
CLKB  
CLKB  
CLKB  
CLKB  
CLKB  
CLKB  
CLKB  
CLKB  
CLKB  
CLKB  
CLKB  
CLKB  
CLKB  
CLKB  
CLKB  
CLKB  
CLKB  
= 16.0MHz  
= 10.6MHz  
= 8.00MHz  
= 6.40MHz  
= 5.33MHz  
= 4.57MHz  
= 4.00MHz  
= 2.00MHz  
= 8.00MHz  
= 5.33MHz  
= 4.00MHz  
= 3.20MHz  
= 2.66MHz  
= 2.28MHz  
= 2.00MHz  
= 1.00MHz  
• Peripheral clock setting  
The peripheral clock setting is set using the CLKP division ratio selection bits (DIVR0.P[3:0]).  
Example frequency  
CLKP division ratio selection bits  
(P[3:0])  
PLL multiplier ratio  
When F = 32MHz When F = 16MHz  
Φ
Φ
F
F
F
F
F
F
F
F
F
= 32.0MHz  
F
F
F
F
F
F
F
F
F
= 16.0MHz  
To select no division  
To select divide by 2  
To select divide by 3  
To select divide by 4  
To select divide by 5  
To select divide by 6  
To select divide by 7  
To select divide by 8  
To select divide by 16  
Set to “0000”.  
Set to “0001”.  
Set to “0010”.  
Set to “0011”.  
Set to “0100”.  
Set to “0101”.  
Set to “0110”.  
Set to “0111”.  
Set to “1111”.  
CLKP  
CLKP  
CLKP  
CLKP  
CLKP  
CLKP  
CLKP  
CLKP  
CLKP  
CLKP  
CLKP  
CLKP  
CLKP  
CLKP  
CLKP  
CLKP  
CLKP  
CLKP  
= 16.0MHz  
= 10.6MHz  
= 8.00MHz  
= 6.40MHz  
= 5.33MHz  
= 4.57MHz  
= 4.00MHz  
= 2.00MHz  
= 8.00MHz  
= 5.33MHz  
= 4.00MHz  
= 3.20MHz  
= 2.66MHz  
= 2.28MHz  
= 2.00MHz  
= 1.00MHz  
• Setting for the external bus clock  
The setting for the external bus clock is set using the CLKT division ratio selection bits (DIVR1.T[3:0]).  
Example frequency  
CLKT division ratio selection bits  
(T[3:0])  
PLL multiplier ratio  
When F = 32MHz When F = 16MHz  
Φ
Φ
F
F
F
F
F
F
F
F
F
= 32.0MHz  
F
F
F
F
F
F
F
F
F
= 16.0MHz  
To select no division  
To select divide by 2  
To select divide by 3  
To select divide by 4  
To select divide by 5  
To select divide by 6  
To select divide by 7  
To select divide by 8  
To select divide by 16  
Set to “0000”.  
Set to “0001”.  
Set to “0010”.  
Set to “0011”.  
Set to “0100”.  
Set to “0101”.  
Set to “0110”.  
Set to “0111”.  
Set to “1111”.  
CLKT  
CLKT  
CLKT  
CLKT  
CLKT  
CLKT  
CLKT  
CLKT  
CLKT  
CLKT  
CLKT  
CLKT  
CLKT  
CLKT  
CLKT  
CLKT  
CLKT  
CLKT  
= 16.0MHz  
= 10.6MHz  
= 8.00MHz  
= 6.40MHz  
= 5.33MHz  
= 4.57MHz  
= 4.00MHz  
= 2.00MHz  
= 8.00MHz  
= 5.33MHz  
= 4.00MHz  
= 3.20MHz  
= 2.66MHz  
= 2.28MHz  
= 2.00MHz  
= 1.00MHz  
203  
Chapter 13 Clock Control  
7.Q & A  
7.5 How do I halt the main clock in sub clock mode?  
Set using the “halt main clock oscillation in subclock mode” bit (OSCCR.OSCDS1).  
Operation in subclock mode  
To not halt the main clock  
Halt main clock oscillation in subclock mode bit (OSCDS1)  
Set to “0”.  
Set to “1”.  
To halt the main clock  
(See “8. Caution (Page No.205)”.)  
7.6 How do I halt the sub clock in sub clock on RC oscillator mode?  
Set using the “halt main clock oscillation in subclock mode” bit (OSCCR.OSCDS2).  
Halt sub clock oscillation in subclock on RC oscillation mode bit  
Operation in subclock mode  
(OSCDS2)  
To not halt the sub clock  
To halt the sub clock  
Set to “0”.  
Set to “1”.  
(See “8. Caution (Page No.205)”.)  
7.7 How do I halt the sub clock in main clock mode?  
Operation in mainclock mode  
To not halt the sub clock  
To halt the sub clock  
Halt sub clock oscillation in main mode bit (OSCD2)  
Set to “0”.  
Set to “1”.  
204  
Chapter 13 Clock Control  
8.Caution  
8. Caution  
• Operation is not guaranteed if the clock source selection, main PLL multiplier setting, and division ratio  
setting result in a frequency that exceeds the maximum.  
• Take care with the sequence in which you set or modify the clock source selection.  
• When the main clock oscillation is set to halt during subclock mode (OSCDS1 = “1”), selecting the main  
clock (CLKS[1:0])=“00”, “01”, or “10”) is prohibited. To select the main clock, set (OSCDS1=“0”) and then  
change to the main clock after waiting for the main clock oscillation to stabilize. Use the main clock  
oscillation stabilization wait timer to provide the wait time. See “Chapter 22 Main Oscillation Stabilisation  
Timer (Page No.289)” for details.  
• When the sub clock oscillation is set to halt during subclock mode (OSCDS2 = “1”), selecting the sub clock  
(CSVCR.SCKS=“0”) is prohibited. To select the sub clock, set (OSCDS2=“0”) and then change to the sub  
clock after waiting for the sub clock oscillation to stabilize. Use the sub clock oscillation stabilization wait  
timer to provide the wait time. See “Chapter 23 Sub Oscillation Stabilisation Timer (Page No.299)” for  
details.  
• When the main clock oscillation is halted (OSCDS1 = “1”) or the sub clock oscillation is halted (OSCDS2 =  
“1”) an oscillation stabilization wait time (for main clock or subclock) is also required if a reset (INIT) occurs  
that switches the clock source to the main clock. In this case, operation after the reset is not guaranteed if  
the wait time set in the oscillation stabilization time selection bits (STCR.OS[1:0]) does not satisfy the  
oscillation stabilization time requirement for the main clock.  
Always set the oscillation stabilization time selection bits (STCR.OS[1:0]) to a value that provides an  
adequate oscillation stabilization time for the main clock.  
In the case of an INIT reset triggered by the INIT pin, the “L” level input must be maintained for long enough  
for the main clock oscillation to stabilize.  
See “Chapter 18 Timebase Counter (Page No.249)” and “Chapter 22 Main Oscillation Stabilisation Timer  
(Page No.289)” for details of the oscillation stabilization wait.  
• When changing to stop mode, the main PLL must either be halted or de-selected. Either set the main clock  
oscillation halt bit (STCR.OSCD1 = “1”) to halt automatically or change the operating clock to main clock  
divided by two before changing to stop mode.  
205  
 
Chapter 13 Clock Control  
8.Caution  
206  
Chapter 14 PLL Interface  
1.Overview  
Chapter 14 PLL Interface  
1. Overview  
• This blockdiagram (simplified) shows the integration of the PLL and the PLL Interface with the multiplier  
control logic (1/M, 1/N for basic frequency multiplication and 1/G for clock auto gear).  
Clock Unit  
XIN1  
CPU-Core  
Resources  
Ext Bus  
PLLIN  
PLL  
Interface  
X
PLL  
Clocktree  
1/G  
1/M  
1/N  
M
U
X
CLKB  
CLKP  
CLKT  
CK  
MAIN  
Osc.  
M
U
X
FB  
Phase  
Correction  
FB1 delay  
2. Features  
• Free programmable divide-by-M counter in the range of 1..16  
• Free programmable divide-by-N counter in the range of 1..64  
• Clock auto gear up/down function to prevent voltage drops and surges  
3. Frequency calculation  
• CLKB frequency is determined by :  
f(CLKB) = [ Main-Osc * (PLLDIVM_DVM+1) *( PLLDIVN_DVN+1) ] / [ (PLLDIVM_DVM+1) * (DIVR0_B+1) ]  
• CLKP frequency is determined by :  
f(CLKP) = [ Main-Osc * (PLLDIVM_DVM+1) *( PLLDIVN_DVN+1) ] / [ (PLLDIVM_DVM+1) * (DIVR0_P+1) ]  
• CLKT frequency is determined by :  
f(CLKT) = [ Main-Osc * (PLLDIVM_DVM+1) *( PLLDIVN_DVN+1) ] / [ (PLLDIVM_DVM+1) * (DIVR1_T+1) ]  
207  
         
Chapter 14 PLL Interface  
4.Registers  
4. Registers  
4.1 PLL Control Registers  
Controls the PLL multiplier ratio (divide-by-M and divide-by-N) and the automatic clock gear up/down function.  
• PLLDIVM: Address 048Ch (Access: Byte, Halfword, Word)  
7
-
6
-
5
-
4
-
3
2
1
0
bit  
DVM3  
DVM2  
DVM1  
DVM0  
Initial value (INIT pin input,  
watchdog reset)  
0
0
0
0
0
0
0
0
Initial value  
(Software reset)  
0
0
0
0
X
X
X
X
R0/W0  
R0/W0  
R0/W0  
R0/W0  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7-4: Reserved bits. Always write “0” to these bits.  
• Bit3-0: PLL divide-by-M selection  
DVM3-DVM0  
0000  
PLL output divided-by-M (generates Φ: Base clock)  
Source (F  
) : 1 (no division)  
CL-PLL  
Source (F  
) : 2 (division by 2)  
0001  
CL-PLL  
Source (F  
Source (F  
) : 3 (division by 3)  
0010  
CL-PLL  
) : 4 (division by 4)  
) : 5 (division by 5)  
) : 6 (division by 6)  
) : 7 (division by 7)  
) : 8 (division by 8)  
.....  
0011  
CL-PLL  
Source (F  
Source (F  
Source (F  
Source (F  
0100  
CL-PLL  
CL-PLL  
CL-PLL  
CL-PLL  
0101  
0110  
0111  
......  
Source (F  
) : 16 (division by 16)  
1111  
CL-PLL  
(Note)  
(Note)  
Even though it is possible to select no division ratio (:1) for the divide-by-M counter it is not  
recommended. The resulting output clock will have an odd clock duty ratio (direct PLL output).  
Always select at least a division ratio > 1 and an even division ratio (:2, :4, :6, etc.).  
Even though it is possible to select an odd division ratio (:3, :5, :7, etc.) for the divide-by-M counter it  
is not recommended. The resulting output clock will have an odd clock duty ratio. Always select an  
even division ratio (:2, :4, :6, etc.).  
(Note)  
(Note)  
The register value can not be changed once PLL is selected as clock source (CLKS[1:0]=”10”).  
It is strongly recommended to disable the PLL (CLKR.PLL1EN=0) while or after changing the  
PLLDIVM and PLLDIVN registers and to enable the PLL (CLKR.PLL1EN=1) afterwards.  
• PLLDIVN: Address 048Dh (Access: Byte, Halfword, Word)  
7
-
6
-
5
4
3
2
1
0
bit  
DVN5  
DVN4  
DVN3  
DVN2  
DVN1  
DVN0  
Initial value (INIT pin input,  
watchdog reset)  
0
0
0
0
0
0
0
0
Initial value  
(Software reset)  
0
0
X
X
X
X
X
X
R0/WX  
R0/WX  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
208  
 
Chapter 14 PLL Interface  
4.Registers  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7-6: Reserved bits.The read value is always “0”.  
• Bit5-0: PLL divide-by-N selection  
DVN5-DVN0  
000000  
000001  
000010  
000011  
000100  
000101  
000110  
000111  
......  
Φ: Base clock divide-by-N (feedback to PLL)  
Base clock (F  
) : 1 (no division)  
CL-MAIN  
Base clock (F  
) : 2 (division by 2)  
) : 3 (division by 3)  
) : 4 (division by 4)  
) : 5 (division by 5)  
) : 6 (division by 6)  
) : 7 (division by 7)  
) : 8 (division by 8)  
CL-MAIN  
Base clock (F  
Base clock (F  
Base clock (F  
Base clock (F  
Base clock (F  
Base clock (F  
CL-MAIN  
CL-MAIN  
CL-MAIN  
CL-MAIN  
CL-MAIN  
CL-MAIN  
.....  
Base clock (F  
) : 64 (division by 64)  
111111  
CL-MAIN  
(Note)  
(Note)  
The register value can not be changed once PLL is selected as clock source (CLKS[1:0]=”10”).  
It is strongly recommended to disable the PLL (CLKR.PLL1EN=0) while or after changing the  
PLLDIVM and PLLDIVN registers and to enable the PLL (CLKR.PLL1EN=1) afterwards.  
• PLLDIVG: Address 048Eh (Access: Byte, Halfword, Word)  
7
-
6
-
5
-
4
-
3
2
1
0
bit  
DVG3  
DVG2  
DVG1  
DVG0  
Initial value (INIT pin input,  
watchdog reset)  
0
0
0
0
0
0
0
0
Initial value  
(Software reset)  
0
0
0
0
X
X
X
X
R0/W0  
R0/W0  
R0/W0  
R0/W0  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7-4: Reserved bits.Always write “0” to these bits.  
• Bit3-0: PLL auto gear start/end divide-by-G selection  
DVG3-DVG0  
0000  
PLL output divided-by-G start/end frequency (generates Φ: Base clock)  
Auto gear disabled (inital value)  
Source (F  
) : 2 (division by 2)  
0001  
CL-PLL  
Source (F  
Source (F  
) : 3 (division by 3)  
0010  
0011  
0100  
0101  
0110  
0111  
......  
CL-PLL  
) : 4 (division by 4)  
) : 5 (division by 5)  
) : 6 (division by 6)  
) : 7 (division by 7)  
) : 8 (division by 8)  
.....  
CL-PLL  
Source (F  
Source (F  
Source (F  
Source (F  
CL-PLL  
CL-PLL  
CL-PLL  
CL-PLL  
Source (F  
) : 16 (division by 16)  
1111  
CL-PLL  
(Note)  
(Note)  
See chapter 6. Clock Auto Gear Up/Down for detailed information on how to use this function.  
Even though it is possible to select an odd division ratio (:3, :5, :7, etc.) for the divide-by-G counter it  
is not recommended. Always select an even division ratio (:2, :4, :6, etc.).  
(Note)  
The register value can not be changed once PLL is selected as clock source (CLKS[1:0]=”10”).  
209  
Chapter 14 PLL Interface  
4.Registers  
• PLLMULG: Address 048Fh (Access: Byte, Halfword, Word)  
7
6
5
4
3
2
1
0
bit  
MLG7  
MLG6  
MLG5  
MLG4  
MLG3  
MLG2  
MLG1  
MLG0  
Initial value (INIT pin input,  
watchdog reset)  
0
0
0
0
0
0
0
0
Initial value  
(Software reset)  
X
X
X
X
X
X
X
X
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7-6: Reserved bitThe read value is always “0”.  
• Bit5-0: PLL auto gear divide-by-G step multiplier selection  
MLG5-MLG0  
00000000  
00000001  
00000010  
00000011  
00000100  
00000101  
00000110  
00000111  
......  
Divide-by-G step multiplier  
Divide-by-G step x 1 (multiply by 1)  
Divide-by-G step x 2 (multiply by 2)  
Divide-by-G step x 3 (multiply by 3)  
Divide-by-G step x 4 (multiply by 4)  
Divide-by-G step x 5 (multiply by 5)  
Divide-by-G step x 6 (multiply by 6)  
Divide-by-G step x 7 (multiply by 7)  
Divide-by-G step x 8 (multiply by 8)  
.....  
11111111  
Divide-by-G step x 256 (multiply by 256)  
(Note)  
(Note)  
See chapter 6. Clock Auto Gear Up/Down for detailed information on how to use this function.  
The register value can not be changed once PLL is selected as clock source (CLKS[1:0]=”10”).  
• PLLCTRL: Address 0490h (Access: Byte, Halfword, Word)  
7
-
6
-
5
-
4
-
3
2
1
0
bit  
IEDN  
GRDN  
IEUP  
GRUP  
Initial value (INIT pin input,  
watchdog reset)  
0
0
0
0
0
0
0
0
Initial value  
(Software reset)  
0
0
0
0
X
X
X
X
R/W  
R/W  
R/W  
R/W  
R/W  
RM1/W  
R/W  
RM1/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7-4: Reserved bitThe read value is always “0”.  
• Bit3: Interrupt Enable Gear DOWN.  
IEDN  
Function  
Gear DOWN interrupt disabled [Initial value]  
Gear DOWN interrupt enabled  
0
1
• Bit2: Interrupt Flag Gear DOWN.  
GRDN  
Function  
0
1
Gear DOWN interrupt not active [Initial value]  
Gear DOWN interrupt active  
210  
Chapter 14 PLL Interface  
4.Registers  
• While switching from clock source PLL to clock source oscillator this flag is set when the divide-by-G  
counter reaches the programmed end value.  
• This bit is read as “1” at a Read-Modify-Write instructions. Writing “1” has no effect.  
• Bit1: Interrupt Enable Gear UP.  
IEUP  
Function  
0
1
Gear UP interrupt disabled [Initial value]  
Gear UP interrupt enabled  
• Bit2: Interrupt Flag Gear UP.  
GRUP  
Function  
0
1
Gear UP interrupt not active [Initial value]  
Gear UP interrupt active  
• While switching from clock source oscillator to clock source PLL this flag is set when the divide-by-G  
counter reaches the end value defined by the divide-by-M counter.  
• This bit is read as “1” at a Read-Modify-Write instructions. Writing “1” has no effect.  
211  
Chapter 14 PLL Interface  
5.Recommended Settings  
5. Recommended Settings  
PLL Input  
(CK)  
[MHz]  
Frequency Parameter Clockgear Parameter PLL Output  
Core base  
Clock  
[MHz]  
(X)  
DIVM  
DIVN  
DIVG  
MULG  
[MHz]  
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
2
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
24  
24  
24  
24  
20  
20  
20  
20  
16  
16  
16  
16  
12  
12  
12  
24  
24  
24  
24  
24  
28  
32  
32  
200  
100  
96  
92  
88  
84  
80  
76  
72  
68  
64  
60  
56  
52  
48  
44  
40  
36  
32  
28  
24  
20  
16  
12  
192  
184  
176  
168  
160  
152  
144  
136  
128  
120  
112  
104  
96  
2
2
2
2
2
2
2
2
2
2
2
2
2
88  
4
160  
144  
128  
112  
144  
160  
160  
144  
4
4
8
4
7
6
6
8
5
10  
12  
4
3
• Important remark: Not all settings which are shown in this table are available for all devices. Please consult  
the available datasheet for each device for the maximum allowed PLL output and the allowed maximum  
frequencies for each clock domain (CLKB, CLKP and CLKT) respectively.  
212  
 
Chapter 14 PLL Interface  
6.Clock Auto Gear Up/Down  
6. Clock Auto Gear Up/Down  
To avoid voltage drops and surges when switching the clock source from oscillator to high frequency PLL/  
DLL output (or vice versa), a clock smooth gear-up and gear-down circuitry is implemented with the PLL  
interface.  
The main functionality is implemented using two divide-by counters (divide-by-M and divide-by-G  
counter), where one supplies the PLL feedback always with the target frequency (divide-by-M counter),  
and the other (divide-by-G counter) which increases the frequency from a programmable frequency divi-  
sion given by the divide-by-G setting (DIVG) up to the target frequency given by the divide-by-M setting  
(DIVM), or decreases the frequency from the divide-by-M setting (DIVM) down to the programmable end  
frequency (DIVG).  
In this sense only a setting of DIVG > DIVM is a valid clock gear specification to scale the system clock  
from slower frequencies to faster frequencies (when gearing up) and from faster frequencies to slower  
ones (when gearing down).  
The frequency steps are performed in multiple of the PLL output frequency, e,g, the setting of: Oscillator  
= 4 MHz, M = 2, N = 20 (which is a frequency multiplication of M * N = 40 with PLL output = 160 MHz  
and frequency output to C-Unit = 80 MHz).  
The gear divider can be set to any even divider, in this example it is G = 20, which causes the following  
gear-up when switching from oscillator to PLL:  
1. step : 1 cycle of 8.0 MHz (8.0 MHz equals 20 cycles of the PLL output)  
2. step : 2 cycles of 8.4 MHz (8.4 MHz equals 19 cycles of the PLL output)  
3. step : 3 cycles of 8.8 MHz (8.8 MHz equals 18 cycles of the PLL output)  
:
17. step : 17 cycles of 40.0 MHz (40.0 MHz equals 4 cycles of the PLL output)  
18. step : 18 cycles of 53.3 MHz (53.3 MHz equals 3 cycles of the PLL output)  
19. step : 19 cycles of 80.0 MHz (80.0 MHz equals 2 cycles of the PLL output)  
-> Target frequency reached by transition to last step (here from 18. to 19.)  
Each step can be multiplied by setting a multiplication value in the gear multiplier register. The duration  
from generating the start frequency up to reaching the target frequency can be calculated by the following  
formula:  
i
i
⎛
⎜
⎝
⎞
duration = mul ⋅ t ⋅  
k ⋅ (i – k + 1) –  
k ⋅ (i – k + 1)  
⎟
∑
∑
⎠
k = 1  
k = j + 1  
213  
   
Chapter 14 PLL Interface  
6.Clock Auto Gear Up/Down  
this equals to (resolved closed arithmetic series of the first sum term):  
i
⎛
⎞
i ⋅ (i + 1) ⋅ (i + 2)  
duration = mul ⋅ t ⋅ ----------------------------------------- –  
k ⋅ (i – k + 1)  
⎜
⎟
∑
6
⎝
⎠
k = j + 1  
with i = G ; j = G - M ; mul = MULG ; t = 1/f(pllout)  
For the above given setting this equals 1483 PLL output clock cycles with a duration from the start fre-  
quency to the target frequency of 9262500 ps (about 9.3 us).  
214  
Chapter 14 PLL Interface  
7.Caution  
7. Caution  
When using the clock auto-gear function it is strongly recommended to make use of the gear up and gear  
down flags (PLLCTRL.GRUP, PLLCTRL.GRDN) to evaluate the current state of this function to avoid  
malfunctions in the clock system due to setting changes prior to completion.  
Procedure example:  
• Set the PLL interface registers (PLLDIVN, PLLDIVM, PLLDIVG, PLLMULG) according to the selected  
frequency and gear duration  
• Switch on the PLL (CLKR.PLL1EN=’1’)  
• If you want to receive interrupts after gearing up or down, also enable the corresponding interrupt  
enables (PLLCTRL.IEUP, PLLCTRL.IEDN)  
• Wait for the PLL stabilization time  
• Set the base clock division registers (DIV0R, DIV1R)  
• Switch the clock source to the PLL (CLKR.CLKS “00”-> “10”)  
• Wait for the PLLCTRL.GRUP gear up flag (either by polling or by interrupt) before switching the  
clock source back to oscillation or confirm the setting of PLLCTRL.GRUP=’1’ before changing bits in  
the CLKR register  
• Switch the clock source to Oscillator (CLKR.CLKS “10”-> “00”)  
• Wait for PLLCTRL.GRDN gear down flag (either by polling or by interrupt) before switching the clock  
source back to PLL or confirm the setting of PLLCTRL.GRDN=’1’ before changing bits in the CLKR  
register  
• Switch off the PLL (CLKR.PLL1EN=’0’)  
215  
 
Chapter 14 PLL Interface  
7.Caution  
216  
Chapter 15 CAN Clock Prescaler  
1.Overview  
Chapter 15 CAN Clock Prescaler  
1. Overview  
• This blockdiagram (simplified) shows the integration of the CAN and the CAN Interface with the CAN clock  
prescaler logic (1/C) and clock source selector.  
CAN Clock Prescaler  
X
M
U
X
CLKCAN  
PLL  
CAN  
Controller  
RX/TX  
1/C  
CK  
MAIN  
Osc.  
FB  
CLKCAN  
CLKB  
Clock Unit  
CAN  
Interface  
CLKB  
CLKB  
D-Bus  
• Remark: If the CLKCAN source is set either to main oscillator or to PLL output then the clock for the  
CAN is not influenced by the clock modulation. If the CLKCAN source is set core clock CLKB then  
the clock for the CAN is also modulated (if the clock modulator is enabled).  
2. Features  
• CAN clock source selectable out of Main Oscillation, Base Clock (CLKB) and PLL output  
• Free programmable divide-by-C counter in the range of 1..16  
• Individual clock disable function for each CAN controller  
217  
     
Chapter 15 CAN Clock Prescaler  
3.Registers  
3. Registers  
3.1 CAN Clock Control Register  
Controls the CAN clock source, the clock division ratio and the clock disable.  
• CANPRE: Address 04C0h (Access: Byte)  
7
-
6
-
5
4
3
2
1
0
bit  
CPCKS1 CPCKS0  
DVC3  
DVC2  
DVC1  
DVC0  
Initial value (INIT pin input,  
watchdog reset)  
0
0
0
0
0
0
0
0
Initial value  
(Software reset)  
0
0
X
X
X
X
X
X
R0/W0  
R0/W0  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7-6: Reserved bitAlways write “0” to these register bits.  
• Bit5-4: CAN Prescaler ClocK Selection  
CPCKS1-CPCKS0  
Prescaler clock source  
CLKB, core clock (inital)  
PLL output  
00  
01  
10  
11  
reserved  
Main oscillation  
• Bit3-0: Source clock Divide-by-C selection  
DVC3-DVC0  
0000  
Source clock divided-by-C (generates CANCLK)  
Source clock : 1 (no division)  
Source clock : 2 (division by 2)  
Source clock : 3 (division by 3)  
Source clock : 4 (division by 4)  
Source clock : 5 (division by 5)  
Source clock : 6 (division by 6)  
Source clock : 7 (division by 7)  
Source clock : 8 (division by 8)  
.....  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
......  
1111  
Source clock : 16 (division by 16)  
(Note)  
(Note)  
Do not exceed the specified upper frequency limit of CANCLK (e.g. 20 MHz) e.g. by setting prescaler  
values exceeding this limit, or by switching the prescaler clock source to a higher frequency clock  
without switching previously the prescaler values to higher division rates.  
If prescaler source is selected to PLL output: Even though it is possible to select no division ratio (:1)  
for the divide-by-C counter it is not recommended. The resulting output clock will have an odd clock  
duty ratio (direct PLL output can have up to 90:10 duty). Always select at least a division ratio > 1.  
• CANCKD: Address 04C1h (Access: Byte)  
7
-
6
-
5
4
3
2
1
0
bit  
CANCKD5 CANCKD4 CANCKD3 CANCKD2 CANCKD1 CANCKD0  
Initial value (INIT pin input,  
watchdog reset)  
0
0
0
0
0
0
0
0
218  
 
Chapter 15 CAN Clock Prescaler  
3.Registers  
Initial value  
(Software reset)  
0
0
0
0
X
X
X
X
R/W0  
R/W0  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7-6: Reserved bitAlways write “0” to these register bits.  
• Bit5-0: CAN clock disable  
CANCKD5-CANCKD0  
Function  
-----0  
-----1  
----0-  
----1-  
---0--  
---1--  
--0---  
--1---  
-0----  
-1----  
0-----  
1-----  
CAN controller 0 is enabled  
CAN controller 0 is disabled  
CAN controller 1 is enabled  
CAN controller 1 is disabled  
CAN controller 2 is enabled  
CAN controller 2 is disabled  
CAN controller 3 is enabled  
CAN controller 3 is disabled  
CAN controller 4 is enabled  
CAN controller 4 is disabled  
CAN controller 5 is enabled  
CAN controller 5 is disabled  
219  
Chapter 15 CAN Clock Prescaler  
3.Registers  
220  
Chapter 16 Clock Supervisor  
1.Overview Clock Supervisor  
Chapter 16 Clock Supervisor  
This section gives an overview of the Clock Supervisor. Purpose of the Clock Supervisor is the  
supervision of the main and sub oscillation clock. In case of main oscillation clock failure the  
Clock Supervisor control logic will take action, i.e. switching to an internal RC-oscillation clock,  
depending on the operation mode set in the control register.  
1. Overview Clock Supervisor  
The Clock Supervisors purpose is the supervision of the main and sub oscillation clocks. In case of a clock failure  
(main clock and/or sub-clock) it can be replaced by an on-chip RC-oscillation clock, depending on the  
configuration.  
If a clock the MCU currently uses, fails for a certain time (20-80µs for main clock / 160-640µs for sub-clock) the  
MCU is reset and the reset cause can be checked after reset vector fetch.  
If the sub-clock is failing while the MCU is in main clock mode reset can be delayed until the transition to sub-  
clock mode or no reset will be initiated. The user can choose the behaviour with a control bit in the Clock  
Supervisor Control Register.  
There are two independent supervisors one for the main clock and one for the sub-clock. They can be enabled/  
disabled seperately.  
Main clock and sub-clock supervisor are disabled and re-enabled automatically if the corresponding oscillator is  
disabled and re-enabled.  
If the MCU changes to stop mode, the RC-oscillator is automatically disabled. It will be enabled again upon wake-  
up from stop mode.  
There are two status bits in the Clock Supervisor Control Register which indicate the failure of the main clock and  
sub-clock. These bits can be available at two port pins (device dependent).  
Single clock devices can use the RC-oscillation clock as sub-clock.  
221  
   
Chapter 16 Clock Supervisor  
2.Clock Supervisor Register  
2. Clock Supervisor Register  
This section lists the Clock Supervisor Control Register and describes the function of each bit in  
detail.  
■ Clock Supervisor Control Register (CSVCR)  
The Clock Supervisor Control Register (CSVCR) sets the operation mode of the Clock Supervisor. Figure 2-1  
shows the configuration of the Clock Supervisor Control Register.  
Figure 2-1 Configuration Clock Supervisor Control Register (CSVCR)  
7
6
5
4
3
2
1
0
Initial Value  
0 0 0 1 1 1 0 0  
SCKS MM SM RCE MSVE SSVE SRST OUTE  
0004AD  
H
B
R/W  
R
R
R/W R/W  
R/W R/W  
R/W  
bit0  
OUTE  
Output enable  
0
1
Do not enable ports for MM and SM output  
Enable ports for MM and SM output  
bit1  
SRST  
Sub-clock mode reset  
do not perform reset upon transition from main clock to  
sub-clock modes if sub-clock is already missing  
0
1
perform reset upon transition from main clock to sub-  
clock modes if sub-clock is already missing  
bit2  
SSVE  
0
Sub-clock supervisor enable  
disable sub-clock supervisor  
enable sub-clock supervisor  
1
bit3  
MSVE  
Main clock supervisor enable  
disable main clock supervisor  
enable main clock supervisor  
0
1
bit4  
RCE  
0
RC oscillator enable  
disable RC-oscillator  
enable RC-oscillator  
1
bit5  
SM  
0
Sub-clock missing  
Missing sub-clock has not been detected  
Missing sub-clock has been detected  
1
bit6  
MM  
0
Main clock missing  
Missing main clock has not been detected  
Missing main clock has been detected  
1
bit7  
SCKS  
Sub clock select (only used for single clock devices)  
32k oscillation used as subclock  
0
1
R/W  
R
:
Readable and writable  
Read only  
RC oscillation used as subclock  
:
:
Initial value  
222  
   
Chapter 16 Clock Supervisor  
2.Clock Supervisor Register  
Table 2-1 describes the function of each bit of the Clock Supervisor Control Register (CSVCR).  
Table 2-1 Functional Description of each bit of the Clock Supervisor Control Register  
Bit  
Name  
Function  
7
SCKS  
(Sub-clock  
select)  
This bit is to select between 32k external oscillation and internal RC  
oscillation as subclock. If this bit is 0 then the external 32k oscillation is  
used as subclock, if it’s 1 then the internal RC oscillation is used as  
subclock.This bit is cleared to ’0’ by Power-On reset or external reset.  
Other types of reset will not affect this bit.  
6
5
4
MM  
(Main  
missing)  
If this bit is 1, the main clock supervisor has detected that the main  
clock oscillation clock coming from X0, X1 is missing, e.g. by a broken  
crystal. If this bit is 0, a missing main clock has not been detected.  
Writing this bit has no effect. This bit is cleared to ’0’ by Power-On reset  
or external reset. Other types of reset will not affect this bit.  
SM  
(Sub-clock  
missing)  
If this bit is 1, the sub-clock supervisor has detected that the sub  
oscillation clock coming from X0A, X1A is missing, e.g. by a broken  
crystal. If this bit is 0, a missing sub-clock has not been detected.  
Writing this bit has no effect. This bit is cleared to ’0’ by Power-On reset  
or external reset. Other types of reset will not affect this bit.  
RCE  
Setting this bit to 1 enables the RC-oscillator. Do not disable the RC-  
(RC-oscillator oscillator by setting this bit to 0 while the main or sub-clock supervisors  
enable)  
are still enabled. First the supervisors must be disabled, then it must be  
checked that MM and SM are ’0’, then RCE can be set to ’0’. If either  
MM or SM bits are ’1’, RCE must not be set to ’0’. This bit is set to ’1’ by  
Power-On reset or external reset. Other types of reset will not affect this  
bit.  
3
2
1
MSVE  
(Main  
supervisor  
enable)  
Setting this bit to 1 enables the main clock supervisor. When this bit is  
clock set to 1, the RC-oscillator must have been enabled by the RCE bit for at  
least 100µs. This bit is set to ’1’ by Power-On reset only. Other types of  
reset will not affect this bit.  
SSVE  
Setting this bit to 1 enables the sub-clock supervisor. When this bit is  
set to 1, the RC-oscillator must have been enabled by the RCE bit for at  
least 100µs. This bit is set to ’1’ by Power-On reset only. Other types of  
reset will not affect this bit.  
(Sub-clock  
supervisor  
enable)  
SRST  
(Sub-clock  
mode reset)  
If this bit is set to 1, a reset is performed upon transition from main/PLL  
clock mode to sub-clock mode if the sub-clock is already missing. If this  
bit is set to 0, no reset is performed in this case. This bit is cleared to ’0’  
by Power-On reset or external reset. Other types of reset will not affect  
this bit.  
0
OUTE  
(Output  
enable)  
This bit can be used as an output enable to output the signals MM (bit 3  
of CSVCR) and SM (bit 4 of CSVCR) to port pins. If this bit is set to ’1’,  
the ports are enabled for MM and SM output. This bit is cleared to ’0’ by  
Power-On reset or external reset. Other types of reset will not affect this  
bit.  
223  
 
Chapter 16 Clock Supervisor  
3.Block Diagram Clock Supervisor  
3. Block Diagram Clock Supervisor  
This section presents a block diagram of the Clock Supervisor. The building blocks of the Clock  
Supervisor are:  
l Main Clock Supervisor  
l Sub-Clock Supervisor  
l Control Logic  
l RC-Oscillator  
■ Block Diagram Clock Supervisor  
Figure 3-1 Bock Diagram Clock Supervisor  
Internal Bus  
Clock Supervisor  
Control Logic  
EXT_RST  
PONR  
EXT_RST_OUT  
OUTE  
ERSX  
PONR  
TB_ST  
ERSXO  
Clock Supervisor Control Register  
CSVCR  
OSC_STAB  
RC-Oscillator  
7
6
5
4
3
2
1
0
SCKS MM SM RCE MSVE SSVE SRST OUTE  
RC_CLK  
STBY RC_CLK  
RCE  
SM  
SCKS  
MM  
SCLK_MISSING  
MCLK_MISSING  
RC_CLK  
Timeout Counter  
TO_MCLK  
CLK  
OR  
TO_SCLK  
MCLK  
S
0
1
MCLK_OUT  
MUX  
Main Clock  
Supervisor  
MCLK NO_MCLK  
EN  
MCLK_STBY  
SCLK  
STBY  
RC_CLK  
RC_CLK  
S
0
1
SCLK_OUT  
Sub-Clock  
Supervisor  
MUX  
SCLK NO_SCLK  
EN  
SCLK_STBY  
STBY  
RC_CLK  
RC_CLK  
Remark: SCLK_OUT and MCLK_OUT can be observed using the Clock Monitor Module. SCLK_MISSING and  
MCLK_MISSING can be programmed to device specific outputs (see the datasheet of the used device for the infor-  
mation which pins are used) by setting OUTE=1.  
224  
 
Chapter 16 Clock Supervisor  
4.Operation Modes  
4. Operation Modes  
This section describes all operation modes of the Clock Supervisor.  
■ Operation mode with initial settings  
In case the clock supervisor control register (CSVCR) is not configured at the beginning of the user program, the  
RC-oscillator, the main clock supervisor and the sub-clock supervisor is enabled.  
•
•
The RC-oscillator is enabled at power-on.  
The main clock supervisor is enabled after the ’oscillation stabilisation wait time’ with the rising edge of signal  
OSC_STAB or in case the main clock is missing before the completion of the ’oscillation stabilisation wait  
time’, after the ’main clock timeout’ (TO_MCLK) from the timeout counter. The timeout counter is clocked with  
RC-oscillation clock. If the main clock is missing from power-on, the power-on reset state is never left, which in  
this case is a safe state. The user must make sure with external pull-up/pull-down resistors that all relevant  
signal are pulled to the correct level.  
•
•
•
The sub-clock supervisor is enabled after the completion of the ’sub-clock timeout’ (TO_SCLK) from the  
timeout counter. The timeout counter is clocked with RC-oscillation clock.  
If the main clock stops while the main clock supervisor is enabled, the main clock is replaced with the RC-  
oscillation clock, the MM bit is set to ’1’ and reset (EXT_RST_OUT) is asserted.  
If the sub-clock stops and the sub-clock supervisor is enabled, the behaviour depend on whether the MCU is  
in main clock mode or in sub-clock mode. If the sub-clock stops in sub-clock mode, the RC-oscillation clock  
divided by two substitutes the sub-clock, the SM bit is set to ’1’ and reset (EXT_RST_OUT) is asserted. If the  
sub-clock stops in main clock mode, the RC-oscillation clock divided by two substitutes the sub-clock, the SM  
bit is set to ’1’ and no reset occurs upon transition to sub-clock mode, since the SRST bit has its initial value of  
’0’.  
225  
 
Chapter 16 Clock Supervisor  
4.Operation Modes  
Figure 4-1 Timing Diagram: Initial settings, main clock missing during power-on reset  
PONR  
MCLK  
SCLK  
RC_CLK  
OSC_STAB  
TO_MCLK  
TO_SCLK  
MSVE  
MSEN  
SSVE  
SSEN  
MCLK_STBY  
SCLK_STBY  
SRST  
EXT_RST  
EXT_RST_OUT  
MCLK_OUT  
SCLK_OUT  
MCLK_MISSING  
SCLK_MISSING  
226  
Chapter 16 Clock Supervisor  
4.Operation Modes  
Figure 4-2 Timing Diagram: Initial settings, main clock missing during ’oscillation stabilisation wait time’  
PONR  
MCLK  
SCLK  
RC_CLK  
OSC_STAB  
TO_MCLK  
TO_SCLK  
MSVE  
MSEN  
SSVE  
SSEN  
MCLK_STBY  
SCLK_STBY  
SRST  
EXT_RST  
EXT_RST_OUT  
MCLK_OUT  
SCLK_OUT  
MCLK_MISSING  
SCLK_MISSING  
227  
Chapter 16 Clock Supervisor  
4.Operation Modes  
Figure 4-3 Timing Diagram: Initial settings, main clock missing after ’oscillation stabilisation wait time’  
PONR  
MCLK  
SCLK  
RC_CLK  
OSC_STAB  
TO_MCLK  
TO_SCLK  
MSVE  
MSEN  
SSVE  
SSEN  
MCLK_STBY  
SCLK_STBY  
SRST  
EXT_RST  
EXT_RST_OUT  
MCLK_OUT  
SCLK_OUT  
MCLK_MISSING  
SCLK_MISSING  
228  
Chapter 16 Clock Supervisor  
4.Operation Modes  
Figure 4-4 Timing Diagram: Initial settings, sub-clock missing before timeout  
PONR  
MCLK  
SCLK  
RC_CLK  
OSC_STAB  
TO_MCLK  
TO_SCLK  
MSVE  
MSEN  
SSVE  
SSEN  
MCLK_STBY  
SCLK_STBY  
SRST  
EXT_RST  
EXT_RST_OUT  
MCLK_OUT  
SCLK_OUT  
MCLK_MISSING  
SCLK_MISSING  
229  
Chapter 16 Clock Supervisor  
4.Operation Modes  
Figure 4-5 Timing Diagram: Initial settings, sub-clock missing after timeout  
PONR  
MCLK  
SCLK  
RC_CLK  
OSC_STAB  
TO_MCLK  
TO_SCLK  
MSVE  
MSEN  
SSVE  
SSEN  
MCLK_STBY  
SCLK_STBY  
SRST  
EXT_RST  
EXT_RST_OUT  
MCLK_OUT  
SCLK_OUT  
MCLK_MISSING  
SCLK_MISSING  
230  
Chapter 16 Clock Supervisor  
4.Operation Modes  
■ Disabling the RC-oscillator and the clock supervisors  
The initial point of this scenario is that the RC-oscillator and main clock or sub-clock supervisor is enabled.  
•
The RC-oscillator can be disabled by setting bit RCE (bit 4 of CSVCR) to ’0’. First disable the main clock and  
sub-clock supervisor. Do not disable the RC-oscillator while either the main clock or sub-clock supervisor is  
still enabled. Then check that both SM and MM (bit 5 and bit 6 of CSVCR) are still ’0’. Disable the RC-  
oscillator by setting RCE to ’0’. If either SM or MM bit is ’1’, RCE must not be set to ’0’.  
•
•
The main clock supervisor is disabled by setting MSVE (bit 3 of CSVCR) to ’0’.  
The sub-clock supervisor is disabled by setting SSVE (bit 2 of CVSVR) to ’0’.  
Figure 4-6 Timing Diagram: Disabling the RC-oscillator and the clock supervisors  
PONR  
MCLK  
SCLK  
RCE  
RC_CLK  
OSC_STAB  
TO_MCLK  
TO_SCLK  
MSVE  
MSEN  
SSVE  
SSEN  
MCLK_STBY  
SCLK_STBY  
SRST  
EXT_RST  
EXT_RST_OUT  
MCLK_OUT  
SCLK_OUT  
MCLK_MISSING  
SCLK_MISSING  
231  
Chapter 16 Clock Supervisor  
4.Operation Modes  
■ Re-enabling the RC-oscillator and the clock supervisors  
The initial point of this scenario is that the RC-oscillator and both main clock and sub-clock supervisor are  
disabled.  
•
•
The RC-oscillator can be enabled by setting RCE (bit 4 of CSVCR) to ’1’.  
The main clock supervisor is enabled by setting MSVE (bit 3 of CSVCR) to ’1’. Enabling of the main clock  
supervisor must only take place 100µs after the RC-oscillator is enabled. The software has to take care that  
this time constraint is met.  
•
The sub- clock supervisor is enabled by setting SSVE (bit 2 of CSVCR) to ’1’. Enabling of the sub-clock  
supervisor must only take place 100µs after the RC-oscillator is enabled. The software has to take care that  
this time constraint is met.  
Figure 4-7 Timing Diagram: Re-enabling the RC-oscillator and the clock supervisors  
PONR  
MCLK  
SCLK  
RCE  
RC_CLK  
OSC_STAB  
TO_MCLK  
TO_SCLK  
MSVE  
MSEN  
SSVE  
SSEN  
MCLK_STBY  
SCLK_STBY  
SRST  
EXT_RST  
EXT_RST_OUT  
MCLK_OUT  
SCLK_OUT  
MCLK_MISSING  
SCLK_MISSING  
232  
Chapter 16 Clock Supervisor  
4.Operation Modes  
■ Sub-clock modes  
The main clock supervisor is automatically disabled in sub-clock modes. The enable bit MSVE remains  
unchanged. At transition from sub-clock mode to main clock mode the main clock supervisor is enabled after the  
’oscillation stabilisation wait time’ with the rising edge of signal OSC_STAB or in case the main clock is missing  
before the completion of the ’oscillation stabilisation wait time’, after the ’main clock timeout’ (TO_MCLK) from  
the timeout counter. The timeout counter is clocked with RC-oscillation clock.  
■ Changing the behaviour upon transition to sub-clock mode if the sub-clock has already  
stopped in main clock mode  
If the sub-clock has stopped in main clock mode and this was detected by the sub-clock supervisor, the  
behaviour upon transition to sub-clock mode depends on the state of the SRST bit.  
•
If SRST is set to ’0’ (initial value), reset is not asserted at the transition to sub-clock mode. The transition is  
performed using the RC-oscillation clock as sub-clock. In this case it is recommended to check the SM bit  
before the transition to sub-clock mode to get the information if sub-clock or RC-oscillation clock is used.  
•
If SRST is set to ’1’, reset is asserted at the transition to sub-clock mode.  
The following timing diagrams (Figure 4-8, Figure 4-9, Figure 4-10) illustrate this behaviour.  
Figure 4-8 Timing Diagram: Sub-clock missing in main clock mode, SRST=0  
PONR  
MCLK  
SCLK  
RC_CLK  
OSC_STAB  
TO_MCLK  
TO_SCLK  
MSVE  
MSEN  
SSVE  
SSEN  
MCLK_STBY  
SCLK_STBY  
SRST  
EXT_RST  
EXT_RST_OUT  
MCLK_OUT  
SCLK_OUT  
MCLK_MISSING  
SCLK_MISSING  
Clock Mode  
Main  
Sub  
233  
 
Chapter 16 Clock Supervisor  
4.Operation Modes  
Figure 4-9 Timing Diagram: Sub-clock missing in main clock mode, SRST=1  
PONR  
MCLK  
SCLK  
RC_CLK  
OSC_STAB  
TO_MCLK  
TO_SCLK  
MSVE  
MSEN  
SSVE  
SSEN  
MCLK_STBY  
SCLK_STBY  
SRST  
EXT_RST  
EXT_RST_OUT  
MCLK_OUT  
SCLK_OUT  
MCLK_MISSING  
SCLK_MISSING  
Clock Mode  
Main  
Main  
234  
 
Chapter 16 Clock Supervisor  
4.Operation Modes  
Figure 4-10 Timing Diagram: Waking up from sub-clock mode  
PONR  
MCLK  
SCLK  
RC_CLK  
OSC_STAB  
TO_MCLK  
TO_SCLK  
MSVE  
MSEN  
SSVE  
SSEN  
MCLK_STBY  
SCLK_STBY  
SRST  
EXT_RST  
EXT_RST_OUT  
MCLK_OUT  
SCLK_OUT  
MCLK_MISSING  
SCLK_MISSING  
Clock Mode  
Main  
Sub  
Main  
235  
 
Chapter 16 Clock Supervisor  
4.Operation Modes  
■ Stop mode  
If RC-oscillator, main clock and sub-clock supervisors are enabled, they will be automatically disabled at  
transition into stop mode. The corresponding enable bits in the clock supervisor control register remain  
unchanged. So after wake-up from stop mode the RC-oscillator and the clock supervisors will be enabled again. If  
the corresponding enable bits are set to ’0’, the RC-oscillator and the clock supervisors will stay disabled after  
wake-up from stop mode.  
•
•
The RC-oscillator is enabled immediately after wake-up from stop mode.  
The main clock supervisor is enabled after the ’oscillation stabilisation wait time’ with the rising edge of the  
signal OSC_STAB or in case the main clock is missing after wake-up from stop mode, after the ’main clock  
timeout’ (TO_MCLK) from the timeout counter. The timeout counter is clocked with RC-oscillation clock.  
•
The sub-clock supervisor is enabled after the ’sub-clock timeout’ (TO_SCLK) from the timeout counter which is  
clocked with the RC-oscillation clock.  
Figure 4-11 Timing Diagram: Waking up from stop mode  
PONR  
MCLK  
SCLK  
RCE  
RC_CLK  
OSC_STAB  
TO_MCLK  
TO_SCLK  
MSVE  
MSEN  
SSVE  
SSEN  
MCLK_STBY  
SCLK_STBY  
SRST  
EXT_RST  
EXT_RST_OUT  
MCLK_OUT  
SCLK_OUT  
MCLK_MISSING  
SCLK_MISSING  
Clock Mode  
Main  
Stop  
Main  
236  
Chapter 16 Clock Supervisor  
4.Operation Modes  
■ Operation with single clock device  
In a single clock device the sub-clock supervisor can provide the RC-oscillation clock as sub-clock. To enable this  
feature, SCKS bit (bit7 of CSVCR) must be set to ’1’ (refer to Table 2-1for precautions when modifying this bit)  
and SRST must be ’0’ (initial value). Before the transition to sub-clock mode, it has to be confirmed by software  
that the sub-clock has been substituted by the RC-oscillation clock. This can be accomplished by checking that  
SM bit (bit 5 of CSVCR) is ’1’ and RCE bit (bit 4 of CSVCR) is ’1’.  
Figure 4-12 Timing Diagram: Sub-clock mode with single clock device  
PONR  
MCLK  
SCLK  
RCE  
RC_CLK  
OSC_STAB  
TO_MCLK  
TO_SCLK  
MSVE  
MSEN  
SSVE  
SSEN  
MCLK_STBY  
SCLK_STBY  
SRST  
EXT_RST  
EXT_RST_OUT  
MCLK_OUT  
SCLK_OUT  
MCLK_MISSING  
SCLK_MISSING  
SCKS  
Clock Mode  
Main  
Sub  
237  
Chapter 16 Clock Supervisor  
4.Operation Modes  
■ Check if reset was asserted by the Clock Supervisor  
To find out whether the Clock Supervisor has asserted reset , the software must check the reset cause by reading  
the WDTC register at address A8 . If ERST (bit 4 of WDTC) is set, the cause was either external reset at the  
H
RSTX pin or the clock supervisor. If neither SM bit nor MM bit (bit 5 and bit 6 of CSVCR) is set, reset cause was  
the external reset. If SM is ’1’ the reset cause is a missing sub-clock and if MM is ’1’ the reset cause is a missing  
main clock.  
238  
Chapter 17 Clock Modulator  
1.Overview  
Chapter 17 Clock Modulator  
This chapter provides an overview of the Clock Modulator and its features. It describes the reg-  
ister structure and operation of the Clock Modulator.  
1. Overview  
The clock modulator is intended for the reduction of electromagnetic interference - EMI, by spreading the  
spectrum of the clock signal over a wide range of frequencies.  
The module is fed with an unmodulated reference clock with frequency F0, provided by the PLL circuit. This  
reference clock is frequency modulated, controlled by a random signal.  
The mean frequency of the modulated clock is equal to the reference clock frequency F0.  
Figure 1-1 Frequency spectrum of the modulated clock (fundamentals only)  
modulation range  
frequency  
F
F
F
max  
min  
0
● Modulation degree and frequency resolution in frequency modulation mode  
Maximum and minimum frequencies (F  
and F ) of the modulated clock are defined by the modulation  
min  
max  
degree parameter. Furthermore the resolution of the modulation range is selectable in 7 steps from low (1) to high  
(7). Higher resolution implies a finer granularity of discrete frequencies in the spectrum of the modulated clock but  
less possible modulation degrees.  
In general the highest possible frequency resolution combined with the highest possible modulation degree  
results in the highest EMI reduction. But for some cases lower modulation degrees may result in a better EMI  
behavior. Please refer to the table of possible settings in Table 2-4 Modulation Parameter settings.  
239  
   
Chapter 17 Clock Modulator  
2.Clock Modulator Registers  
2. Clock Modulator Registers  
This section lists the clock modulator registers and describes the function of each register in de-  
tail.  
● Clock modulator registers  
Figure 2-1 Clock modulator registers  
7
6
5
4
3
2
1
0
Address:  
CMPRL (lower)  
0004B9  
H
Initial value  
1 1 1 1 1 1 0 1B  
R/W R/W R/W R/W R/W R/W R/W R/W  
15 14 13 12 11 10  
9
8
CMPRH (upper)  
0004B8  
H
-
-
Initial value  
X X 0 0 0 0 0 1 0B  
-
-
R/W R/W R/W R/W R/W R/W  
7
-
6
5
4
3
2
-
1
0
CMCR  
FMOD  
Re-  
served served  
Re-  
Re-  
served RUN  
FMOD PDX  
R/W R/W  
0004BB  
Initial value  
H
X 0 0 1 0 X 0 0B  
-
-
R/W R/W R/W  
R
240  
 
Chapter 17 Clock Modulator  
2.Clock Modulator Registers  
● Clock Modulator Control Register (CMCR)  
The Control Register (CMCR) has the following functions:  
Set the modulator to power down mode  
Modulator enable/disable in frequency modulation mode  
Indicates the status of the modulator  
Figure 2-2 Configuration of the clock modulator control register (CMCR)  
7
6
5
4
3
2
1
0
CMCR  
FMOD  
RUN  
Re-  
Re-  
Re-  
-
-
FMOD PDX  
R/W R/W  
-
-
0004BB  
Initial value  
served served served  
H
X 0 0 1 0 X 0 0B  
R/W R/W R/W  
R
bit 0  
PDX  
Power down bit  
0
1
power down mode  
power up  
bit 1  
FMOD  
Frequency modulation enable bit  
Frequency modulation mode disabled  
Frequency modulation mode enabled  
0
1
bit 3  
FMOD  
RUN  
Modulator status in frequency modulation mode  
0
1
Clock frequency unmodulated  
Clock frequency modulated  
bit 4,5,6  
Reserved  
Always write 1 to this bit  
Always write 0 to this bit  
bit 4  
bit 5,6  
R/W  
R
X
:
:
:
Readable and writable  
Read only  
Undefined value  
-
:
:
Undefined  
Initial value  
The bits FMODRUN, FMOD, PDX control or indicate the status of the frequency modulation mode. Frequency  
modulation mode needs some additional configuration (CMPR register).  
241  
Chapter 17 Clock Modulator  
2.Clock Modulator Registers  
● Clock modulator control register contents  
Table 2-1 Function of each bit of the clock modulator control register (1 / 2)  
Bit name  
undefined  
Function  
bit7  
bit 6 to 5  
bit 4  
Reserved  
Reserved  
Always write 0 to this bit.  
Always write 1 to this bit.  
bit 3  
FMOD RUN:  
Modulator status  
in frequency  
modulation mode  
bit  
"0": MCU is running with unmodulated clock  
"1": MCU is running with frequency modulated clock  
•
FMODRUN indicates the status of the modulator output clock in frequency  
modulation mode (FMOD=1). If the output clock is frequency modulated,  
MODRUN is set to 1, otherwise MODRUN is set to 0.  
•
After enabling the frequency modulation mode by setting FMOD to 1, the modulator  
is calibrated. During this time, the clock is unmodulated. Therefore it takes several  
us before the output clock switches to modulated clock and the FMODRUN bit is set  
to 1. The calibration time depends on the frequency of the oscillator. At oscillator  
(Fc) = 4MHz : Calibration time = 64.00us (calibration time = 256/Fc).  
During normal operation, after calibration is finished, the clock is not switched to  
unmodulated clock anymore.  
Due to the synchronization of the FMOD signal and the synchronized switching to  
unmodulated clock, it takes less than 9 x T0 (input clock period) before FMODRUN  
changes to 0 and the clock switches to unmodulated clock after the modulator is  
disabled.  
•
•
•
•
The FMODRUN bit is read only. Writing to FMODRUN has no effect.  
Before changing the parameter register CMPR, the modulator must be disabled ->  
FMOD=0 and FMODRUN=0.  
bit 2  
Undefined  
242  
Chapter 17 Clock Modulator  
2.Clock Modulator Registers  
Table 2-1 Function of each bit of the clock modulator control register (2 / 2)  
Bit name  
Function  
bit 1  
FMOD:  
"0": Frequency modulation disabled.  
"1": Frequency modulation enabled.  
Frequency  
modulation  
enable bit  
•
•
To enable the modulator in frequency modulation mode, FMOD must be set to 1.  
Before the modulator can be enabled, the PLL must deliver a stable reference clock  
(PLL lock time must be elapsed).  
•
•
The specified PLL frequency range for frequency modulation mode is 15 MHz to 25  
MHz.  
Each PLL output frequency offers a set of possible modulation parameters. The  
selected setting (CMPR register) and the PLL frequency must match.  
Please refer to the CMPR register description.  
•
•
Whenever the PLL output frequency is changed or the PLL is switched off e.g. in  
power down modes, the modulator must be disabled before -> FMOD=0 and  
FMODRUN=0.  
Before the modulator can be enabled, it must be switched from power down to active  
mode by setting PDX to 1. And the startup time of 6us must be awaited.  
Please refer to the application note for a description of the recommended startup  
sequence.  
•
•
Before the modulator can be enabled in frequency modulation mode, a proper setting  
must be selected via the parameter register CMPR.  
After enabling the frequency modulation mode by setting FMOD to 1, the modulator  
is calibrated. During this time, the clock is unmodulated. Therefore the output clock  
does not switch immediately to modulated clock. The status of the clock (frequency  
modulated / unmodulated) is indicated by the FMODRUN status bit. Please refer to  
the FMODRUN bit description.  
•
•
Due to the synchronization of the FMOD signal and the synchronized switching to  
unmodulated clock, it takes less than 9 x T0 (input clock period) before the clock  
switches to unmodulated clock after the modulator is disabled. The modulator can be  
disabled at any time.  
Before changing the parameter register CMPR, the modulator must be disabled ->  
FMOD=0 and FMODRUN=0.  
bit 0  
PDX:  
Power down bit  
"0": Power down mode  
"1": Power up  
•
PDX is the power down signal for the modulator. Before the frequency modulation  
mode can be enabled, this bit must be set to 1 and the startup time of 6us must be  
awaited. Please refer to the application note for a description of the recommended  
startup sequence.  
•
Before switching to power down mode (PDX=0), the modulator must be disabled ->  
FMOD=0 and FMODRUN=0.  
In the Table below the modulator states are summarized:  
Table 2-2 States of the modulator  
FMODRUN  
(read only)  
FMOD  
PDX  
modulator disabled  
0
0
0
1
0
0
modulator power on,  
waiting modulator startup time (> 6 us)  
243  
Chapter 17 Clock Modulator  
2.Clock Modulator Registers  
Table 2-2 States of the modulator  
FMODRUN  
(read only)  
FMOD  
PDX  
modulator enabled in frequency modulation mode,  
modulator is calibrating, modulation not active  
1
1
0
1
modulator is running in frequency modulation mode  
modulation is active  
1
1
others not allowed  
● Clock Modulation Parameter Register (CMPR)  
The Modulation Parameter Register (CMPR) determines the modulation degree in frequency modulation  
mode.  
Figure 2-3 Modulation parameter register  
7
6
5
4
3
2
1
0
Address:  
CMPRL (lower)  
0004B9  
Initial value  
H
1 1 1 1 1 1 0 1B  
R/W R/W R/W R/W R/W R/W R/W R/W  
15 14 13 12 11 10  
9
8
CMPRH (upper)  
0004B8  
H
Initial value  
X X 0 0 0 0 0 1 0 B  
R/W R/W R/W R/W R/W R/W  
: Readable and writable  
: Undefined value  
: Undefined  
R/W  
X
• The modulation parameter determines the degree of modulation and the maximal and minimal occurring  
frequencies in the modulated clock. Please refer to the application note for a description of an approach to  
select the optimal setting.  
• Each set of possible modulation parameters refers to a particular PLL frequency. The PLL frequency and the  
selected parameter must match. Please refer to the following table of possible settings.  
• The modulation parameter affects only the frequency modulation mode.  
Note:  
The modulation parameter must be changed only when the modulator is disabled and the RUN flag is 0  
(FMOD=0, FMODRUN=0).  
● Modulation parameter register contents  
Table 2-3 Function of each bit of the modulation parameter register (CMPR)  
Bit name  
Undefined  
Function  
bit 15, 14  
244  
Chapter 17 Clock Modulator  
2.Clock Modulator Registers  
Table 2-3 Function of each bit of the modulation parameter register (CMPR)  
Bit name Function  
MP13 to 0:  
bit 13 to 0  
Depending on the PLL frequency the following modulation parameter settings are  
possible. The corresponding CMPR register value is stated in the most right column.  
Modulation  
Parameter bits  
245  
Chapter 17 Clock Modulator  
2.Clock Modulator Registers  
F0:  
Frequency of unmodulated input clock (PLL frequency)  
T0:  
Period of unmodulated input clock (PLL clock period)  
resolution:  
resolution of frequencies in the modulated clock. low (1) to high (7)  
minimal frequency occurring in the frequency modulated clock  
F
F
:
min  
:
maximal frequency occurring in the frequency modulated clock  
max  
phase skew:  
The maximal phase shift of the modulated clock relative to the unmodulated  
reference clock in terms of clock periods of the unmodulated clock.  
Example: phase skew=1.44  
In worst case, a sequence of n periods of the modulated clock can be 1.44*T0  
shorter or 1.44*T0 longer than a sequence of n periods of the unmodulated  
reference clock.  
n can be any number > 50 periods  
phase skew 50:  
CMPR:  
phase skew for sequences with n<= 50 periods  
register setting of the CMPR register  
n periods  
reference clock  
-
phase skew  
+
n periods  
n periods  
modulated clock  
Note: NOT ALL SETTINGS ARE ALLOWED ON EVERY DEVICE!  
Please consider the actual maximal allowed clock frequency of the MCU (refer to the data sheet).  
246  
Chapter 17 Clock Modulator  
3.Application Note  
The table below shows the recommended setting for several MCU clocks and modulation parameters:  
Table 2-4 Modulation Parameter settings  
F0 (MHz) resolution  
mod  
degree  
F
(MHz)  
F
+/- phase  
skew  
50  
[periods]  
+/- phase  
skew  
min/max  
[periods]  
CMPR  
min  
max  
(MHz)  
Please refer to the datasheet of each device about modulation parameter settings.  
3. Application Note  
Startup/stop sequence for frequency modulation mode.  
Modulation parameter for frequency modulation mode.  
● Recommended startup sequence for frequency modulation mode  
start  
1.  
2.  
3.  
Switch modulator from power down to power up mode PDX=1  
Switch on PLL  
Wait PLL lock time (refer to the MCM flag description in the CLOCK chapter of the hardware  
manual). At the same time the modulator starts up.  
4.  
5.  
Set CMPR register to a proper setting  
Enable frequency modulation mode FMOD=1  
After the calibration is finished, the clock switches from unmodulated to modulated clock and  
the FMODRUN flag changes to 1  
... running...  
stop  
6.  
7.  
8.  
9.  
Disable modulator FMOD=0  
Wait until FMODRUN changes to 0  
Switch to power down mode PDX=0  
Disable PLL, switch to power down mode, etc.  
Note:  
Do not enable the modulator before the PLL lock time has elapsed. Do not disable the PLL while the  
modulator is running.  
● Modulation parameter for frequency modulation mode  
It is not possible to recommend a particular modulation parameter setting to achieve a particular reduction in EMI.  
The best setting depends much on the actual application, the whole system and the requirements.  
In order to find the optimal modulation parameter setting in frequency modulation mode, the following approach is  
247  
   
Chapter 17 Clock Modulator  
3.Application Note  
recommended.  
1.  
2.  
3.  
define the required PLL frequency based on  
performance needs  
e.g. 16 MHz  
determine the maximal allowed clock frequency of e.g. 32 MHz  
the MCU  
choose the setting with the highest resolution and  
the highest modulation degree, whose maximal  
frequency is below the maximal allowed clock  
frequency of the MCU.  
e.g. resolution:7, degree:2, CMPR=0x05F2  
(F = 30.34 MHz)  
max  
4.  
5.  
perform EMI measurements  
if the EMI measurements does not fulfill the  
requirements, you may either  
reduce the modulation degree at the same  
frequency resolution  
e.g. resolution:7, degree:1, CMPR=0x03F9  
(this may improve the reduction in the upper  
frequency band > 100 MHz, but decrease the  
reduction of the fundamental < 100 MHz)  
or  
or  
increase the modulation degree at a lower  
frequency resolution  
e.g. resolution:5, degree:3, CMPR=0x0771  
(this may improve the reduction of the fundamental  
< 100 MHz, but worsen the reduction in the upper  
frequency band > 100 MHz)  
6.  
repeat item 3) with the new setting and continue  
until the best settings is identified  
● Recommended settings  
The following table lists some example conditions for PLL clock and maximal allowed MCU clock frequency and  
the recommended clock modulator setting:  
Table 3-1 Some example conditions for PLL clock  
F0  
PLL clock  
frequency  
maximalallowed  
MCU clock  
frequency (refer  
to the data  
clock modulator setting  
resolution  
modulation  
degree  
F
CMPR  
max  
sheet)  
Please refer to the datasheet of each device about modulation parameter settings.  
248  
Chapter 18 Timebase Counter  
1.Overview  
Chapter 18 Timebase Counter  
1. Overview  
The timebase counter is a 26-bit up-counter that counts the subclock or the main clock divided by two.  
When recovering from a state in which the selected clock source for the MCU has been, or may have been,  
halted, the MCU automatically changes to the oscillation stabilization wait state to avoid any unstable output  
from the oscillator.  
During the oscillation stabilization wait time, supply of internal and external clocks is halted and only the  
timebase counter continues to operate until the time set by the oscillation stabilization wait time setting has  
elapsed.  
Time-base counter when used to  
generate the oscillation stabilization wait  
Watchdog timer  
Time-base timer  
Time-base counter  
Base clock  
26-bit counter  
State transition  
control circuit  
Oscillation stabilization wait control signal  
The timebase counter, timebase timer, and watchdog timer are collectively called the watchdog control unit.  
2. Features  
2.1 Timebase Counter (when used to generate the oscillation stabilization wait)  
Type  
: 26-bit up-counter  
Number  
: 1  
Clock source (F2): Main clock divided by two, or subclock  
Clear  
: Cleared automatically when changing to oscillation stabilization wait state.  
2.2 Events that Invoke an Oscillation Stabilization Wait  
■ Events that invoke an oscillation stabilization wait using the timebase counter  
● Wait time after a settings initialization: Invoked automatically (timebase counter)  
• INIT Initial oscillation stabilization wait after pin input  
• Watchdog reset  
• If the main clock oscillation has not been halted: Oscillation stabilization wait not required  
• If the main clock oscillation has halted: Oscillation stabilization wait is required  
Example: If a watchdog reset occurs during subclock mode with main clock oscillation halted  
● Wait time after recovering from stop mode: Invoked automatically (timebase counter)  
• Stop mode cases when clock oscillation circuit is halted:  
• The oscillation stabilization wait time for the intended oscillation circuit is required  
• Wait time for main PLL to lock is required (if main PLL is used)  
• Stop mode cases when clock oscillation circuit is not halted:  
Oscillation stabilization wait is not required unless the clock oscillation (main/PLL) has been halted.  
● When recovering from abnormal state with main PLL selected  
Automatically goes to the oscillation stabilization wait state to allow time for the main PLL to lock.  
249  
       
Chapter 18 Timebase Counter  
3.Configuration  
■ Events that invoke an oscillation stabilization wait using other than the timebase counter  
● Wait time after power on: Provided by pin input  
● Wait time after changing from subclock to main clock: Using the main oscillation stabilization wait  
timer to generate this time is recommended.  
● When recovering from main clock oscillation halted: Enabling the main clock oscillation and  
waiting for oscillation to stabilize is required.  
● Main PLL lock wait time (for main clock operation): Using the timebase timer interrupt to generate  
this time is recommended.  
• A wait time is required after the main PLL operation is enabled.  
• A wait time is required after the main PLL multiplier setting is changed.  
3. Configuration  
Figure 3-1  
Configuration Diagram  
Time-base counter  
(when used to generate the oscillation stabilization wait)  
OS1-OS0  
STCR:bit 3-2  
0
0
1
1
0
φ2 x 21  
11  
φ2 x  
φ2 x  
φ2 x  
1
0
1
2
2
2
16  
22  
Oscillation stabilization  
wait control signal  
CKS1-CKS0  
CLKR :bit 1-0  
CL-MAIN /2  
0
0
0
1
0
1
F
1
1
CL-SUB  
F
/2  
Time-base counter  
(26-bit counter)  
0
1
2
3
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25  
F CL-MAIN /2  
21 22 23 24  
210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226  
CL-SUB  
F
Base clock  
(φ2)  
- INIT pin input  
- Watchdog reset  
- STOP  
Figure 3-2 Register List  
250  
 
Chapter 18 Timebase Counter  
4.Registers  
4. Registers  
4.1 STCR: Standby Control Register  
Controls transition to standby modes, pin states during stop mode, whether to halt the clock during stop mode,  
the oscillation stabilization wait time, and software reset.  
Note: See also “Chapter 10 Standby (Page No.155)” and “Chapter 20 Software Watchdog Timer (Page  
No.273)” chapters.  
• STCR: Address 0481h (Access: Byte)  
7
6
5
4
3
2
1
0
bit  
STOP SLEEP  
HIZ  
SRST  
OS1  
OS0 OSCD2 OSCD1  
Initial value  
(INITX pin input)  
0
0
1
1
0
0
1
1
0
0
0
0
1
X
1
1
X
X
X
X
1
X
1
X
Initial value (Watchdog)  
Initial value (Software reset)  
Attribute  
R/W  
R/W  
R/W  
R1,W  
R/W  
R/W  
RX,W  
R/W  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7: Stop mode (STOP)  
• Setting “1” changes to stop mode.  
• Bit6: Sleep mode (SLEEP)  
• Setting “1” changes to sleep mode.  
• If this bit and the stop mode bit (STOP) bit are set to “1” at the same time, the device goes to stop mode.  
• Bit5: High impedance mode (HIZ)  
• Setting “0” specifies that pins maintain the same states they have on entering stop mode.  
• Setting “1” specifies that pin outputs go to high impedance (Hi-z) during stop mode.  
• Bit4: Software reset (SRST)  
• Setting “0” triggers a software reset.  
• Note that negative logic is used.  
• Bit3-2: Oscillation stabilization time selection  
The oscillation stabilization wait time after a reset (INIT) or on recovering from stop mode.  
Oscillation  
OS[1:0]  
When using main clock  
When using subclock  
stabilization  
wait time  
(For a 4.0MHz main clock)  
(For a 32.768kHz subclock)  
1
00  
01  
10  
11  
1.00µs  
1.0ms  
32ms  
2s  
61µs  
62.5ms  
2.0s  
Φ2 × 2  
Φ2 × 2  
Φ2 × 2  
Φ2 × 2  
11  
16  
22  
128s  
• F2: Main clock divided by two or subclock  
1
• In the case of a reset triggered by an INIT pin input, operation defaults to “00” (F2 x 2 , main clock).  
• In the case of other resets or on recovering from stop mode, the specified clock (main or sub) and  
oscillation stabilization wait time (OS[1:0]) are used.  
• The count is performed by the timebase counter.  
• Bit1: Sub clock oscillation halt (OSCD2)  
Setting “1” specifies that the sub clock oscillation halts in stop mode.  
• bit0: Main clock oscillation halt (OSCD1)  
Setting “1” specifies that the main clock oscillation halts in stop mode.  
(See “8. Caution (Page No.262)”.)  
251  
 
Chapter 18 Timebase Counter  
4.Registers  
4.2 CLKR: Clock Source Control Register  
Selects the clock source for the base clock used to run the MCU and controls the PLL.  
Note: See also the “Chapter 13 Clock Control (Page No.189)”.  
• CLKR: Address 0484h (Access: Byte)  
7
-
6
-
5
-
4
-
3
2
1
0
bit  
SCKEN PLL1EN CLKS1  
CLKS0  
Initial value  
(INIT pin input)  
X
X
X
X
0
0
0
0
Initial value  
(Software reset)  
X
X
X
X
X
X
X
X
R/W0  
R/W0  
R/W0  
R/W0  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7-4: Reserved bit Always write “0” to this bit. The read value is the value written.  
• Bit3: Subclock selection enable (SCKEN)  
• Setting this bit to “1” enables the subclock to be selected.  
• Bit2: Main PLL operation enable (PLL1EN)  
• Setting this bit to “1” starts main PLL operation. Main PLL can be selected as the operating clock after the  
main PLL has locked.  
• Bit1-0: Clock source selection  
CLKS1 CLKS0  
Clock source setting  
The main clock input from X0/X1 divided by 2 (initial value)  
The main clock input from X0/X1 divided by 2  
Main PLL  
Mode  
0
0
1
1
0
1
0
1
Main clock mode  
Main clock mode  
Main clock mode  
Subclock mode  
Subclock  
When changing the clock mode, the value of CLKS0 cannot be modified if CLKS1 is “1”  
The table below lists the cases when the CLKS1 - CLKS0 bits may or may not be modified.  
Table 4-1 Cases When the CLKS1 and CLKS0 Bits May or May Not be Modified  
Modify permitted  
“00” -> “01” or “10”  
“01” -> “11” or “00”  
“10” -> “00”  
Modify not permitted  
“00” -> “11”  
“01” -> “10”  
“10” -> “01” or “11”  
“11” -> “00” or “10”  
“11” -> “01”  
Example: To select the subclock after an INIT reset, first write “01 ” and then write “11 ” (subclock)  
B
B
The clock source for the timebase counter during the oscillation stabilization wait time is set by the clock source  
selection bits.  
Clock source for timebase  
CLKS1  
CLKS0  
Mode  
counter during oscillation stabilization wait time  
The main clock input from X0/X1 divided by 2 (initial value)  
Subclock  
0
0
1
1
0
1
0
1
Main clock mode  
Subclock mode  
252  
Chapter 18 Timebase Counter  
5.Operation  
5. Operation  
This section describes the events that trigger an oscillation stabilization wait and the operation in each case.  
5.1 INIT Pin Input  
An oscillation stabilization wait is required after power on. As the wait time provided by the initialized timebase  
counter is too short, the INIT pin input must be held at the “L” level.  
Figure 5-1 Using the Width of the Pin Input to Provide the Oscillation Stabilization Wait Time  
Using the INIT pin input to trigger  
a reset and provide the oscillation  
stabilization wait time for the  
main clock  
Example power-on Vcc  
(1)  
(3)  
Example main clock startup  
Time-base  
counter count  
Provide a sufficient oscillation  
stabilization wait time  
(5)  
21  
000h  
21 (Bit 0 output)  
Time  
Initial value of oscillation  
stabilization wait time is too short  
(6)  
(2)  
INIT pin input  
State transition  
(5)  
(4)  
(2)  
(7) (8)  
Main RUN  
Undefined  
Oscillation stabilization wait reset  
Operation initialization (SRST)  
Reset cancellation sequence  
Settings initialization  
(INIT)  
(1) Power turned on  
(2) Start INIT pin input (Settings initialization reset)  
(3) Main clock oscillation starting  
(4) INIT pin input (to provide a sufficient time for the main clock oscillation to stabilize)  
(5) INIT pin input removed. The timebase counter is initialized and starts counting.  
(6) Oscillation stabilization wait time provided by timebase timer/counter (Initial value = minimum value)  
(If the INITX pin input (4) is not maintained, the wait time is too short.)  
(7) Operation initialization reset, reset cancellation sequence  
(8) Main RUN  
■ INIT Pin input when main clock running  
The device goes to the operation initialization reset (RST) state automatically after the minimum oscillation  
stabilization wait time elapses.  
253  
   
Chapter 18 Timebase Counter  
5.Operation  
5.2 Watchdog Reset (The specified oscillation stabilization wait time is generated  
automatically)  
If a watchdog reset occurs while the main clock oscillation is halted, the oscillation stabilization wait time is  
generated automatically. (See figure below.)  
Figure 5-2 Watchdog Reset when Main Clock Halted (Sub RUN)  
Using the time-base counter to  
provide the oscillation stabilization  
wait time for the main clock  
(4)  
Example main clock startup  
Provide a sufficient oscillation  
Time-base  
counter  
count  
stabilization wait time  
(6)  
222  
(4)  
Time  
000h  
(1) 222 (Bit 21 output)  
(6)  
(7)  
Watchdog  
(3)  
Internal reset signal  
(5)  
(8) (9)  
Main RUN  
(2)  
Sub RUN with main clock  
oscillation halted  
Oscillation stabilization wait reset  
State transition  
Operation initialization (SRST)  
Reset cancellation sequence  
Settings initialization  
(INIT)  
22  
(1) Oscillation stabilization wait time selection (Example: Main clock divided by two x 2  
)
(Set the interval time beforehand to provide an adequate oscillation stabilization wait time.)  
(2) Sub RUN with main clock oscillation halted  
(3) Watchdog reset occurs  
(4) Main clock oscillation starts  
The timebase counter is cleared and starts counting.  
(5) Oscillation stabilization wait  
(6) Time set as the timebase timer interval time (time set in (1))  
(7) Reset released, operation initialization (SRST)  
(8) Operation initialization, reset sequence  
(9) Main RUN  
Note: If a watchdog reset occurs when the main clock oscillation is halted during subclock mode (subclock is  
being used as clock source) by the main clock oscillation halt bit (OSCCR.OSCDS1), the device changes  
to the oscillation stabilization wait state after the settings initialization reset (INIT) is released. The device  
then changes to the operation initialization reset (RST) state after the oscillation stabilization wait time  
elapses.  
254  
Chapter 18 Timebase Counter  
5.Operation  
■ Watchdog reset when main clock operating  
Although no oscillation stabilization wait is required in this case, the specified wait time is generated  
automatically.  
5.3 Recovering from Stop Mode via an Interrupt  
■ When changing from main PLL operation to stop mode with the main clock oscillation halted  
(STCR.OSCD[2:1]=“11”):  
The main oscillation circuit generates the selected oscillation stabilization time automatically.  
Figure 5-3 Recovering from Stop Mode with the Main Clock Halted to  
Main PLL Operation via an Interrupt  
Using the time-base timer to wait  
main PLL lock  
(8)  
(5)  
Example main PLL  
startup  
Provide a sufficient oscillation  
stabilization wait time.  
(1)  
213  
(9)  
Time-base  
counter count  
(4)  
(3)  
Time  
000h  
Clear the time-base counter.  
(CTBR)  
“A5” “5A”  
Enable main PLL (PLL1EN)  
(5)  
Enable the time base timer  
interrupt request. (PLL1EN)  
(7)  
Time base timer interrupt  
request (PLL1EN)  
(6)  
(9)  
Setting or switching  
the main PLL value  
(PLL1S[2:0])  
(2)  
“111”  
“00”  
(10)  
Clock switching (CLKS[1:0])  
“10”  
Operation of the divided- by-2 main clock  
(1) Enabled interrupt is generated (end stop mode)  
Operation of the PLL clock  
(2) The timebase counter is cleared automatically and then starts counting.  
(3) Oscillation stabilization wait time (specified value)  
(Set the interval time beforehand to provide an adequate oscillation stabilization wait time.)  
(4) Interval time for timebase counter  
(5) Main PLL operation  
255  
 
Chapter 18 Timebase Counter  
5.Operation  
■ When changing to stop mode without halting the clock oscillation circuit (main PLL/main/  
sub):  
Although no oscillation stabilization wait is required in this case, a wait is generated automatically. Accordingly,  
it is recommended that you set the interval time to its minimum value before changing to stop mode.  
• When recovering from stop mode, the device goes to the oscillation stabilization wait state immediately  
after stop mode is released.  
• The next state after the oscillation stabilization wait completes depends on what triggered recovery from  
stop mode.  
• If recovery was triggered by an enabled external interrupt, sub oscillation stabilisation timer interrupt, or  
main oscillation stabilization wait timer interrupt, the device goes to the normal operating state (RUN).  
Note: If the main PLL continues to operate in stop mode, changing to stop mode with the main PLL clock set as  
the active clock is not permitted. Always set the active clock to the main clock divided by two or the  
subclock beforehand.)  
5.4 The lock wait time for the main PLL must be generated by software.  
■ Wait time after main PLL operation enabled:  
Using the timebase timer interrupt is recommended  
However, the main PLL must not be selected as the clock source.  
■ Wait time after main PLL multiplier modified:  
Using the timebase timer interrupt is recommended  
However, the main PLL must not be selected as the clock source.  
See “Chapter 19 Timebase Timer (Page No.263)” for details.  
5.5 Generating an Oscillation Stabilization Wait when Changing from Subclock Mode to  
Main Clock Mode  
■ When main clock continues to run during subclock mode:  
• If not using main PLL after changing clock: No oscillation stabilization wait time  
• If using main PLL after changing clock: Main PLL lock wait is required.  
(Using the timebase timer interrupt is recommended. See “5.3 Recovering from Stop Mode via an Interrupt  
(Page No.255)”.)  
■ When main clock halts during subclock mode:  
• A main clock oscillation stabilization wait is required before changing clock.  
(Use the oscillation stabilization wait timer for the main clock. See “Chapter 22 Main Oscillation Stabilisation  
Timer (Page No.289)”.)  
• When using the main PLL: A further wait is required for the main PLL to lock.  
(Using the timebase timer interrupt is recommended. See “5.3 Recovering from Stop Mode via an Interrupt  
(Page No.255)”.)  
5.6 When Recovering from an Abnormal State with the Main PLL Selected  
When the main PLL is set as the clock source and a problem of some sort occurs in main PLL control (such as  
the multiplier setting being changed or the main PLL enable bit modified during main PLL operation), the  
device goes to the oscillation stabilization wait state automatically to provide the main PLL lock time. The  
device then goes to normal operating mode after the oscillation stabilization wait elapses.  
256  
Chapter 18 Timebase Counter  
5.Operation  
5.7 Types of Oscillation Stabilization Wait  
■ Timebase counter  
Automatically provides a count for the oscillation stabilization wait time.  
When a trigger occurs to change the device to the oscillation stabilization wait state, the timebase counter is  
cleared and then starts counting the specified oscillation stabilization wait time.  
■ “L” level input to INIT pin  
When device operation is restarted by inputting an “L” level to the INIT pin while the oscillation is halted (the  
three cases listed below), the width of the “L” level input provides the stabilization time required by the  
oscillation circuit.  
• INIT pin input after power turned on.  
• INIT pin input when oscillation halted during stop mode  
• INIT pin input when subclock selected as clock source and main clock oscillation halted.  
■ Timebase timer  
Using the timebase timer to generate the main PLL lock time is recommended.  
See “Chapter 20 Software Watchdog Timer (Page No.273)” for details.  
■ Main oscillation stabilization wait timer  
Used when restarting the main clock while operating in subclock mode.  
See “Chapter 22 Main Oscillation Stabilisation Timer (Page No.289)” for details.  
■ Sub oscillation stabilisation wait timer  
Used when restarting the subclock while operating in main clock mode.  
See “Chapter 23 Sub Oscillation Stabilisation Timer (Page No.299)” for details.  
257  
Chapter 18 Timebase Counter  
5.Operation  
5.8 Whether or not a Stabilization Wait is Required for Each State Transition  
See figure below.  
258  
Chapter 18 Timebase Counter  
6.Settings  
6. Settings  
Table 6-1 Settings Required to Specify the Oscillation Stabilization Wait Time  
Setting  
procedure*  
Setting  
Setting register  
Oscillation stabilization wait time setting  
Standby control register (STCR)  
See 7.1.  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-2 Settings Required to Setup an INITX Pin Reset  
Setting  
Setting item  
Setting procedure  
Refer to the oscillator parameters and the reset  
parameters in the Data Sheet.  
INITX pin input  
–
• Settings required to specify the oscillation stabilization wait time for the main clock  
See “Chapter 22 Main Oscillation Stabilisation Timer (Page No.289)”.  
• Settings required to specify the PLL lock wait time  
See “Chapter 19 Timebase Timer (Page No.263)”.  
259  
 
Chapter 18 Timebase Counter  
7.Q&A  
7. Q&A  
7.1 How do I setup the oscillation stabilization wait time that is generated automatically?  
Use the oscillation stabilization wait time selection bits (STCR.OS[1:0]). (The following lists likely scenarios  
and the required settings.)  
Example oscillation stabilization wait time  
after a reset (INIT) or on  
Oscillation  
stabilization wait  
time selection bits  
(OS[1:0])  
recovering from stop mode  
Scenario  
Oscillation  
stabiliza-  
tion  
4.0MHz  
Main clock  
running  
32.768kHz  
Subclock  
running  
wait time  
To not halt the main PLL or oscillator during stop mode  
(No oscillation stabilization wait time required)  
1
Set “00”.  
Set “01”.  
1.00µs  
61µs  
Φ2 × 2  
To not stop the oscillator during external clock input or  
stop mode  
11  
1.0ms  
62.5ms  
Φ2 × 2  
(Main PLL lock wait time)  
When using an oscillator with a fast stabilization time  
such as a ceramic resonator  
16  
Set to “10”.  
Set to “11”.  
32ms  
2s  
2.0s  
Φ2 × 2  
(Oscillation stabilization wait time (medium))  
When using a standard quartz oscillator  
(Oscillation stabilization wait time (long))  
22  
128s  
Φ2 × 2  
• F2: Main clock divided by 2, or subclock  
1
• In the case of an INIT pin input, operation defaults to “00” (F2 x 2 =main clock divided by 4).  
• For other resets and when recovering from stop mode, the operation is in accordance with the specified  
clock (main or sub) and oscillation stabilization wait time (OS[1:0]) setting.  
• The count is performed by the timebase counter.  
• Once the time is selected, it is not initialized except by a settings initialization triggered by the external  
INIT pin.  
260  
 
Chapter 18 Timebase Counter  
7.Q&A  
7.2 How do I set the oscillation stabilization wait time without generating it  
automatically?  
The settings described below for various cases are required.  
Oscillation  
Is oscillation  
stabilization wait  
required?  
State (before  
transition)  
Condition (after  
transition)  
To set the oscillation  
stabilization wait time  
PLL  
×
Main  
Sub  
×
Wait time after power on  
×
×
Subclock operation  
(main clock halted)  
As the automatic oscillation  
stabilization wait (minimum  
value) is too short, the width of  
the INIT pin must be sufficient  
to provide the stabilization time.  
×
O
Operation after INIT Main clock  
signal input defaults to oscillation  
Sub sleep, sub stop  
(main clock halted)  
main clock (1/2)  
(Initial value)  
stabilization wait  
is required  
×
×
×
×
O
Main clock oscillation  
stabilization wait  
O/×  
Oscillation  
Main  
Is oscillation  
stabilization wait  
required?  
State (before  
transition)  
Main clock  
oscillation enabled  
To set the oscillation  
stabilization wait time  
PLL  
Sub  
Main clock  
oscillation  
stabilization wait generate the time is  
is required recommended.  
Using the main clock oscillation  
stabilization wait timer to  
Subclock operation  
(main clock halted)  
×
×
O
Main clock running  
Oscillation  
Main  
Is oscillation  
stabilization wait  
required?  
State (before  
transition)  
Main PLL running  
and enabled  
To set the oscillation  
stabilization wait time  
PLL  
×
Sub  
O
Subclock running (main  
clock running)  
Start main PLL  
oscillation/  
Change PLL  
O
O
Using the timebase timer to  
generate the main PLL lock wait  
time is recommended.  
Main PLL lock  
wait required  
Main clock (1/2) running  
×
O
multiplier setting  
O: Oscillation running,  
×: Oscillation halted  
7.3 What is the clear timing for the timebase counter?  
• The timebase counter is only cleared automatically by INIT pin input.  
The timebase counter automatically starts counting after being cleared.  
• The timebase counter can also be cleared by software.  
See “Chapter 19 Timebase Timer (Page No.263)” for details.  
261  
Chapter 18 Timebase Counter  
8.Caution  
8. Caution  
• Clock source  
If the clock selected as the clock source is not stable, an oscillation stabilization wait time is required.  
• Oscillation stabilization wait time  
The wait time set in the oscillation stabilization time selection bits (STCR.OS[1:0]) is not initialized by any  
reset except a reset triggered by the external INITX pin input, the RC based watchdog or the Clock  
Supervisor. For other resets including settings initialization resets (timebase counter based watchdog reset)  
and operation initialization resets (RST), the wait time set prior to the reset is used.  
• Watchdog reset (Timebase Counter based watchdog)  
Although an oscillation stabilization wait time is not required if a watchdog reset occurs while the main clock  
is running (main or sub), a wait time is generated automatically. In this case, the oscillation stabilization wait  
time (STCR.OS[1:0]) is not initialized.  
• “L” level input to INIT pin  
As the oscillation stabilization wait time is initialized to its minimum value when an initialization is triggered  
by an INIT pin input, the wait time in this case is too short. Ensure the INIT pin input width is long enough to  
provide the oscillation stabilization wait time.  
In the following three cases, maintain the INIT pin input at the “L” level for long enough to provide the  
oscillation stabilization wait time required by the oscillation circuit.  
• INIT pin input after turning on the power  
• INIT pin input after oscillation halted in stop mode  
• INIT pin input when subclock selected as the clock source and main clock oscillation halted  
(Accordingly, to stabilize the oscillation of both the main and subclocks, input an “L” level to the INIT pin for  
long enough to provide a sufficient oscillation stabilization time for both the main and subclocks.)  
• Main PLL lock wait  
If enabling the main PLL from the halted state after program execution starts, the main PLL must not be  
used until after sufficient time has elapsed for the main PLL to lock.  
Similarly, when changing the multiplier setting for the main PLL when the PLL is running, the new main PLL  
clock must not be used until sufficient time has elapsed for the main PLL to lock.  
Using the timebase timer interrupt to generate the main PLL lock wait time is recommended.  
• Cases when oscillation stabilization wait is not required  
Although no oscillation stabilization wait is required when recovering via an interrupt from main stop or sub  
stop mode when the main clock oscillation has not been halted, the oscillation stabilization wait is generated  
automatically. Setting the wait time to its minimum value prior to entering stop mode is recommended.  
262  
 
Chapter 19 Timebase Timer  
1.Overview  
Chapter 19 Timebase Timer  
1. Overview  
The timebase timer is a selector that uses the output from a 26-bit timebase counter using the base clock (F).  
The timebase timer is an interval-interrupt generating timer that is used to acquire main PLL lock wait time and  
to count a long time.  
Watchdog control section  
Watchdog timer  
Timebase  
counter  
Base  
clock  
26-bit counter  
(φ)  
Timebase timer  
Selector  
Timebase timer interrupt  
2. Features  
■ Timebase timer (TBT)  
• Type  
: Detects timebase timer bit output and generates an interval interrupt.  
: 1  
• Quantity  
• Interval time: 8 types (Timebase timer bit output)  
11  
12  
13  
22  
23  
24  
Period =2 /F , 2 /F , 2 /F , 2 /F , 2 /F , 2 /F ,  
F
F
F
F
F
F
25  
26  
2 /F , 2 /F  
F
F
• Operation start/stop: Always in operation (Can be replaced by interrupt request enable control)  
• Timebase counter clear: Continuously writes “A5”“5A” in the timebase counter clear register CTBR using the  
software.  
263  
       
Chapter 19 Timebase Timer  
3.Configuration  
3. Configuration  
Figure 3-1 Configuration  
Timebase timer  
Interval time  
Timebase timer  
TBC2-TBC0  
TBCR:bit 5 -3  
11  
0
1
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
φ x  
φ x  
φ x  
φ x  
2
2
2
2
12  
13  
22  
φ x223  
TBIE  
TBCR:bit 6  
24  
φ x  
2
2
0
1
Interrupt disable  
Interrupt enable  
0
25  
φ x  
φ x 226  
TBIF  
TBCR:bit 7  
Timebase  
0
1
Without interrupt request  
With interrupt request  
Timer interrupt  
(#46)  
1
WRITE; 0: Flag clear  
Timebase counter  
(26-bit counter)  
0
1
2
3
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25  
Base clock  
21 22 23 24  
210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226  
(φ)  
Timer clear  
CTBR  
Clears the counter  
after writing "A5h"  
and then "5Ah."  
Figure 3-2 List of Registers  
264  
 
Chapter 19 Timebase Timer  
4.Register  
4. Register  
4.1 TBCR: Timebase Timer Control Register  
This register is used to set timebase timer interrupt control, reset/ standby operation option etc.  
Note: Refer also to “Chapter 10 Standby (Page No.155)”.  
• TBCR: Address 0482h (Access: Byte)  
7
6
5
4
3
2
1
0
bit  
TBIF  
TBIE  
TBC2  
TBC1  
TBC0  
---  
SYNCR SYNCS  
Initial value  
(INIT terminal input,  
watchdog reset)  
0
0
X
X
X
X
0
0
Initial value  
(the software reset)  
0
0
X
X
X
X
X
X
R(RM1),W R/W  
R/W  
R/W  
R/W  
RX/WX RX/WX  
R/W  
Attribute  
(Refer to “Meaning of Bit Attribute Symbols (Page No.10)” for the attributes.)  
• Bit7: Timebase timer interrupt request flag  
Operation  
TBIF  
Read  
Write  
0
1
With no interrupt request  
Flag is cleared  
With interrupt request  
(The interval time set by the timebase timer  
has elapsed)  
Writing does not affect operation  
• An interrupt request is generated if the timebase timer interrupt request enable bit is “1”, and if the  
timebase timer interrupt request flag is “1”.  
• Bit6: Timebase timer interrupt request enable  
TBIE  
Operation  
0
1
Disabling the timebase timer interrupt request  
Enabling the timebase timer interrupt request  
• Bit5-3: Selecting the timebase timer interval time  
Example  
TBC2-TBC0  
Interval time  
While the main clock operates While the subclock operates  
(4.0MHz, PLL8 multiply)  
(32.768kHz)  
62.5ms  
125ms  
250ms  
128s  
11  
000  
001  
010  
011  
100  
101  
110  
111  
64.0µs  
128µs  
Φ × 2  
12  
Φ × 2  
13  
256µs  
Φ × 2  
22  
131ms  
262ms  
524ms  
1048ms  
2097ms  
Φ × 2  
23  
256s  
Φ × 2  
24  
512s  
Φ × 2  
25  
1024s  
Φ × 2  
26  
2048s  
Φ × 2  
• Be sure to set the interval time before an interrupt.  
(Oscillation stability wait time used when returning to the stop caused by an interrupt)  
• Bit2: Reserved bit  
Writing does not affect the operation. The read value is indefinite.  
265  
 
Chapter 19 Timebase Timer  
4.Register  
• Bit1: Enabling the synchronous reset operation  
SYNCR  
Operation  
0
1
Ordinary reset operation  
Synchronous reset operation enable  
• Ordinary operation reset: Immediately resets the operation initialization when the operation initialization  
reset (RST) request is generated.  
Synchronous reset: Resets the operation initialization after all accesses to the bus have stopped.  
• Bit0: Synchronous standby operation enable  
SYNCS  
Operation  
0
1
Ordinary reset operation (In this product, any setting is prohibited)  
Synchronous standby operation enable (Be sure to set before making the transition to standby)  
4.2 CTBR: Timebase Counter Clear Register  
This register is used to initialize the timebase counter.  
• CTBR: Address 0483h (Access: Byte)  
7
D7  
6
D6  
5
D5  
4
D4  
3
D3  
2
D2  
1
D1  
0
D0  
bit  
X
X
X
X
X
X
X
X
Initial value  
Attribute  
RX/W  
RX/W  
RX/W  
RX/W  
RX/W  
RX/W  
RX/W  
RX/W  
(Refer to “Meaning of Bit Attribute Symbols (Page No.10)” for the attributes)  
• Continuously writing “A5 ”, “5A ” in the timebase counter clear register clears the timebase counter  
H
H
immediately after writing “5A ”. (All bits are “0”)  
H
There is no time restrictions between “A5 ” and “5A ”, but if “A5 ” is written followed by the one other than  
H
H
H
“5A ”, you should write “A5 ” again. If not, the timebase counter cannot be cleared even if “5A ” is written.  
H
H
H
• The read value is indefinite.  
• Clearing the timebase counter using the timebase counter clear register temporarily modifies the relevant  
items shown below.  
• Oscillation stability wait interval  
• Watchdog timer period  
• Timebase timer period  
266  
Chapter 19 Timebase Timer  
5.Operation  
5. Operation  
Timebase timer operation is described.  
5.1 Timebase Timer Interrupt Example (Main PLL Lock Wait)  
Main PLL lock wait  
by the timebase timer  
(8)  
(5)  
Example of  
the Main PLL  
oscillation  
600 µsec. or more  
(1)  
(1)  
211  
Timebase  
counter  
count  
(4)  
(3)  
Time  
000h  
Clears the  
timebase counter  
(CTBR)  
“A5” “5A”  
Main PLL enable (PLL1EN)  
(5)  
Timebase timer interrupt  
request enable (PLL1EN)  
(7)  
Timebase timer interrupt  
request (PLL1EN)  
(6)  
(9)  
Main PLL value  
setting/switching  
(PLL1S[2:0])  
(2)  
“111”  
(10)  
Clock switching (CLKS[1:0])  
“00”  
“10”  
Operation with the 2-dividing main clock  
Operation with the PLL clock  
(1) Selecting the interval value in the timebase timer  
(2) Selecting the main PLL value (Setting / Switching)  
(3) Writing data in the timebase counter clear register in the order of “A5” and “5A”  
(4) Writing “5A” clears the timebase counter and causes the count to start from”0”  
(5) Enables the main PLL to operate  
(6) Clears the timebase timer interrupt request using the software  
(7) Setting the timebase timer interrupt request enable bit to “1”  
(8) The main PLL locks  
(9) A timebase timer interrupt occurs when the timebase timer interval time has elapsed  
(10)Setting the main PLL to the operation clock  
267  
 
Chapter 19 Timebase Timer  
6.Setting  
6. Setting  
Table 6-1 Setting Required for the Timebase Timer  
Setting  
method*  
Setting  
Setting the interval time  
Setting register  
Timebase timer control register  
control register (TBCR)  
Refer to 7.1  
Refer to 7.5  
Timebase counter clear register  
(CTBR)  
Timebase counter clear  
*: Refer to the number for more information on the setting method.  
Table 6-2 Setting Required for Interrupting the Timebase Timer  
Setting  
method*  
Setting  
Setting register  
Setting the timebase timer interrupt vector and  
interrupt level  
Refer to “Chapter 24 Interrupt  
Control (Page No.311)”  
Refer to 7.6  
Refer to 7.7  
Setting the main clock oscillation stability wait timer interrupt  
Interrupt request clear  
Interrupt request enable  
Timebase timer control register  
control register (TBCR)  
*: Refer to the number for more information on the setting method.  
268  
 
Chapter 19 Timebase Timer  
7.Q & A  
7. Q & A  
7.1 What are the types of interval time used in the timebase timer (and the timebase  
counter used by the timebase timer) and how to select them?  
There are eight types of interval time, and they are set using the interval selection bit (TBCR.TBC[2:0]).  
Example Interval time  
Timebase timer  
Interval time  
Interval selection bit  
(TBC[2:0])  
FΦ =  
32.768kHz  
FΦ =2MHz  
FΦ = 32MHz  
11  
Set the value to “000”  
Set the value to “001”  
Set the value to “010”  
Set the value to “011”  
Set the value to “100”  
Set the value to “101”  
Set the value to “110”  
Set the value to “111”  
1.024ms  
2.048ms  
4.096ms  
2.097s  
62.5ms  
125ms  
256ms  
128s  
64µs  
128µs  
256µs  
131ms  
262ms  
524ms  
1.04s  
How to select Φ × 2  
How to select Φ × 2  
How to select Φ × 2  
How to select Φ × 2  
How to select Φ × 2  
How to select Φ × 2  
How to select Φ × 2  
How to select Φ × 2  
?
?
?
?
?
12  
13  
22  
23  
24  
25  
26  
4.194s  
256s  
8.388s  
512s  
?
16.77s  
1024s  
2048s  
?
?
33.55s  
2.09s  
F: This is the base clock. (Refer to “Chapter 13 Clock Control (Page No.189)”.)  
7.2 What Is the count clock of the timebase counter?  
The count clock is a base clock. Refer to “Chapter 13 Clock Control (Page No.189)”.  
7.3 How to operate the timebase timer?  
The timebase timer is always operating. (Setting is unnecessary.)  
However, to use interval interrupt, interrupt setting is required.  
7.4 How is the timebase timer (=timebase counter) operation stopped?  
It cannot be stopped.  
7.5 How is the timebase counter (=timebase timer) cleared?  
If you write {A5 } and {5A } successively in the timebase counter clear register CTBR, the timebase counter  
H
H
is cleared immediately after {5A }. (All bits are “0”.)  
H
However, if the timebase counter is cleared, the watchdog timer is affected. (Refer to “8. Caution (Page  
No.271)”)  
7.6 How about the interrupt-associated registers?  
Setting timebase timer’s interrupt vector and interrupt level  
The relationship between the interrupt level and vector is shown in the following table.  
Refer to “Chapter 24 Interrupt Control (Page No.311)” for more information on the interrupt level and interrupt  
vector.  
Interrupt vector (default)  
Interrupt level setting bit (ICR[4:0])  
#140  
Address: 0FFDCCh  
Interrupt level register (ICR62)  
Address: 047Eh  
The interrupt request flag (TBCR.TBIF) cannot automatically be cleared. As a result, clear it by the software  
before returning from an interrupt service. (Write “0” in the interrupt request flag (TBIF).)  
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Chapter 19 Timebase Timer  
7.Q & A  
7.7 What are the interrupt types?  
One type of interrupt is available, and an interrupt is generated when the interval time that is set using the  
interval selection bit (TBCR.TBC[2:0]) has elapsed. (Selection is unnecessary.)  
7.8 How is an interrupt enabled?  
Interrupt request enable and interrupt request flag  
Setting interrupt enable is conducted using the interrupt request enable bit (TBCR.TBIE).  
Interrupt request enable bit (TBIE)  
Interrupt disable  
Interrupt enable  
Set the value to “0”  
Set the value to “1”  
Clearing the interrupt request is performed using the interrupt request bit (TBCR.TBIF).  
Interrupt request bit (TBIF)  
Interrupt request clear  
“0” is written  
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Chapter 19 Timebase Timer  
8.Caution  
8. Caution  
• The main PLL needs the PLL lock wait time after operation enable and after modifying the rate of multiply.  
We recommend that this main PLL lock wait time be acquired using the timebase interrupt.  
The lockup time of PLL is approximately 600us. Make sure that the PLL lock wait time is set to a value a  
little larger than 600us.  
• Regarding the interval setting  
• When modifying the timebase timer interval time, set the interrupt request enable bit (TBIE) to “0” in  
advance to disable an interrupt.  
• The timebase counter is always counting. Clear the timebase counter before enabling an interrupt to  
acquire an accurate interval interrupt time using the timebase timer.  
(If not, an interrupt request may be generated immediately after an interrupt enable.)  
• About clearing the timebase counter using a program  
• If you write data in the timebase counter clear register CTBR in the order of “A5 ” and “5A ” the  
H
H
timebase counter is cleared immediately after writing “5A ”. (All bits are “0.”)  
H
• Although there are no restrictions on the write timings for “A5 ” and “5A ” writing “A5 ” followed by a one  
H
H
H
other than “5A ” the clearing operation is not performed if “A5 ” is not written again even if “5A ” is  
H
H
H
written.  
• If the timebase counter is cleared, the reset signal to the watchdog is generated with a delay once.  
• About clearing the timebase counter by the hardware  
The timebase counter is cleared by the STOP mode and the setting initialization reset (INIT pin input,  
watchdog reset). (All bits are “0.”)  
• In the stop mode  
When returning to the interrupt from a stop, the timebase counter is used to acquire the clock oscillation  
stability wait time. As a result, there is a possibility to unintentionally generate timebase timer’s interval  
interrupt. Therefore, disable the timebase timer interrupt not to use the timebase timer before the stop is set.  
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Chapter 19 Timebase Timer  
8.Caution  
272  
Chapter 20 Software Watchdog Timer  
1.Overview  
Chapter 20 Software Watchdog Timer  
1. Overview  
The software watchdog timer consists of a selector that uses the output from a 26-bit timebase counter using  
the base clock (F) and a one-bit counter.  
The watchdog timer generates the watchdog reset (initial setting reset) if the generation delay operation (an  
interval watchdog reset) is disabled due to problems such as program runaway.  
Watchdogcontrolsection  
Watchdogtimer
Watchdog
Selector
reset
Counter
Timebase
counter
Base
clock
(f)
26-bitcounter
Timebasetimer
2. Features  
■ Watchdog timer  
• Type  
: Generates the watchdog reset (INIT) with the overflow from one-bit counter  
• Quantity : 1  
• Count clock (interval time): Bit output from the timebase timer  
20  
22  
24  
26  
4 types  
2 /F , 2 /F , 2 /F , 2 /F  
F
F
F
F
(Can be set only once after the reset (RST).)  
• Clearing 1-bit counter:  
Successively writes “A5”“5A” to watchdog reset generation delay register WPR by the software.  
• Operation start/stop: This timer starts to operate once it writes data to the watchdog control register RSRR  
for the first time after the reset (RST). This timer stops only by the reset (RST).  
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Chapter 20 Software Watchdog Timer  
3.Configuration  
3. Configuration  
Figure 3-1 Configuration Diagram  
-Sleep  
-Stop  
-Oscillation stability  
wait RUN  
Timebase counter  
(26-bit counter)  
0
1
2
3
13 14 15 16 17 18 19 20 21 22 23 24 25  
214 215 216 217 218 219 220 221 222 223 224 225 226  
Base clock  
Temporary stop  
21 22 23 24  
(φ)  
Watchdog timer  
For watchdog detection  
WIF  
Watchdog reset  
To the reset  
OSCR:bit 7  
Timer clear  
0
1
1-bit  
counter  
Without interrupt request  
With interrupt request  
WRITE; 0: Flag clear  
circuit  
WT1-WT0  
RSRR:bit2-1  
20  
0
0
0
1
0
1
φ x  
φ x  
φ x  
φ x  
2
2
22  
24  
WPR  
CTBR  
1
1
2
2
Clears the counter  
after writing “A5h”  
and then “5Ah”.  
Clears the counter  
after writing “A5h”  
and then “5Ah”.  
26  
Figure 3-2 List of Registers  
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Chapter 20 Software Watchdog Timer  
4.Register  
4. Register  
4.1 RSRR: Watchdog Timer Control Register  
This register is used to set watchdog timer periods, and execute the startup control.  
(This register also functions as the reset cause register that stores previously generated reset causes.)  
Note: Refer also to “Chapter 9 Reset (Page No.139)”.  
• RSRR: Address 0480h (Access: Byte, Half-word)  
7
6
5
4
3
2
1
0
bit  
INIT  
HSTB  
WDOG  
ERST  
SRST  
LINIT  
WT1  
WT0  
Initial value  
(INIT pin input)  
1
0
0
0
0
0
0
0
-
X
-
X
-
X
X
-
X
-
-
X
0
0
0
0
Initial value (Watchdog reset)  
Initial value (Software reset)  
Attribute  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/W  
R/W  
(For the attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
The watchdog timer starts once it writes the watchdog timer control register.  
• Bit7: Initialization reset occurred flag  
Indicates whether a reset (INIT) was triggered by INIT pin input.  
INIT  
Meaning  
No INIT has been triggered by the INIT pin input.  
INIT has been triggered by the INIT pin input.  
0
1
The initialization reset occurred flag (INIT) is cleared to “0” after reading.  
• Bit6: Hardware Standby reset occurred flag  
Indicates whether a reset (INIT) was triggered by HST pin input.  
HSTB  
Meaning  
No INIT has been triggered by the HST pin input.  
INIT has been triggered by the HST pin input.  
0
1
The hardware standby reset occurred flag (HSTB) is cleared to “0” after reading.  
• Bit5: Watchdog reset occurred flag  
Indicates whether a reset (INIT) was triggered by the watchdog timer.  
WDOG  
Meaning  
No INIT has been triggered by the watchdog timer.  
INIT has been triggered by the watchdog timer.  
0
1
The watchdog reset occurred flag (WDOG) is cleared to “0” after reading.  
• Bit4: External reset occurred flag  
Indicates whether a reset (RST) was triggered by the RST pin input.  
ERST  
Meaning  
No RST has been triggered by the RST pin input.  
RST has been triggered by the RST pin input.  
0
1
The external reset occurred flag (ERST) is cleared to “0” after reading.  
• Bit3: Software reset occurred flag  
Indicates whether a software reset has been triggered by writing to the software reset bit (STCR.SRST).  
SRST  
Meaning  
No RST has been triggered by a software reset.  
0
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Chapter 20 Software Watchdog Timer  
4.Register  
1
RST has been triggered by a software reset.  
The software reset occurred flag (SRST) is cleared to “0” after reading.  
• Bit2: Low voltage reset occurred flag  
Indicates whether a reset (INIT) was triggered by the low voltage detection.  
LINIT  
Meaning  
No INIT has been triggered by the low voltage detection.  
INIT has been triggered by the low voltage detection.  
0
1
The low voltage reset occurred flag (LINIT) is cleared to “0” after reading.  
• Bit1-0: Watchdog interval time selection  
Interval between the time when WPR is last  
The minimum writing interval required for WPR  
so that the watchdog timer may not be reset  
written with 5A and when the watchdog is  
H
reset  
WT1 WT0  
(Interval time of the timebase counter  
selection bit)  
(Watchdog interval time)  
20  
20  
21  
23  
25  
27  
0
0
1
1
0
1
0
1
Φ × 2 (Initial value)  
Φ × 2 to Φ × 2  
22  
22  
Φ × 2  
Φ × 2 to Φ × 2  
24  
24  
Φ × 2  
Φ × 2 to Φ × 2  
26  
26  
Φ × 2  
Φ × 2 to Φ × 2  
(Φ: Base clock)  
• A total of four watchdog interval times are available to be selected.  
• Only the data firstly written after a reset is valid, and the other data sets are invalid.  
• Watchdog interval time selection bit can be read to know the set value.  
Note: For more information on bits used for timers other than the watchdog timer, refer to “Chapter 9 Reset  
(Page No.139)”.  
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Chapter 20 Software Watchdog Timer  
4.Register  
4.2 WPR: Watchdog Reset Generation Postponement Register  
This register is used to postpone the generation of watchdog reset.  
• WPR: Address 0485h (Access: Byte)  
7
D7  
6
D6  
5
D5  
4
D4  
3
D3  
2
D2  
1
D1  
0
D0  
bit  
X
X
X
X
X
X
X
X
Initial value (INIT)  
Initial value (RST)  
Attribute  
X
X
X
X
X
X
X
X
RX,W  
RX,W  
RX,W  
RX,W  
RX,W  
RX,W  
RX,W  
RX,W  
(Refer to “Meaning of Bit Attribute Symbols (Page No.10)” for the attributes.)  
• If “A5 ” and “5A ” are successively written in the watchdog reset generation postponement register and  
H
H
immediately after writing “5A ” the 1-bit counter used to detect the watchdog is set to “0” to postpone the  
H
generation of a watchdog reset.  
Although there are no restrictions on the write timings for “A5 ” and “5A ”, if “A5 ” and a value other  
H
H
H
than “5A ” are written, “A5 ” must be written again. If not, writing “5A ” does not set the 1-bit counter to  
H
H
H
“0”.  
• The read value is indefinite.  
• Both “A5 ” and “5A ” must be written within the specified interval as shown below to prevent the  
H
H
watchdog reset from being generated. The intervals are shown in the following table according to the  
watchdog interval time selection bit (RSRR.WT[1:0]).  
WT1  
WT0  
Minimum interval required for writing data in WPR  
20  
0
0
1
1
0
1
0
1
Within Φ × 2 (Initial value)  
22  
Within Φ × 2  
24  
Within Φ × 2  
26  
Within Φ × 2  
4.3 CTBR: Timebase Counter Clear Register  
This register is used to initialize the timebase counter.  
• CTBR: Address 0483h (Access: Byte)  
For more information, refer to “Chapter 19 Timebase Timer (Page No.263)”.  
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Chapter 20 Software Watchdog Timer  
5.Operation  
5. Operation  
This section describes the watchdog operation.  
5.1 Watchdog (Detecting Runaway)  
Count value of  
the timer counter  
(11)  
(8)  
(1)  
(6)  
Interval period  
selection  
(3)  
(8)  
(7)  
(6)  
(3)  
Bit output of  
the timer counter  
(Bits 15, 17, 19 and 21)  
(12)  
Runaway  
detection  
Watchdog  
(3) (4)  
Watchdog timer  
startup  
(5) (6)  
(8)  
(2)  
Reading from the RSRR  
register  
Periodically writing  
“A5” and “5A” in the  
WPR register  
(10)  
(4)  
(5)  
(7)  
Clear by  
software  
Clear by  
software  
Clear by  
software  
With  
no clear  
(12)  
(13)  
WDOG bit  
Setting initialization reset  
(INIT)  
Normal operation  
Runaway  
Reset  
(9)  
(1) Setting interval time  
(2) Watchdog startup (Watchdog timer clear)  
(3) Interval signal output from the timebase counter. The watchdog timer counts.  
(4) Within the interval time, by software periodic writing to the WPR register with “A5” and “5A” has been performed.  
The watchdog timer clears.  
(5) Within the interval time, by software periodic writing to the WPR register with “A5” and “5A” has been performed.  
The watchdog timer clears.  
(6) Interval signal output from the timebase counter. The watchdog timer counts.  
(7) Within the interval time, by software periodic writing to the WPR register with “A5” and “5A” has been performed.  
Watchdog timer clears.  
(8) Interval signal output from the timebase counter. The watchdog timer counts.  
(9) MCU runs away (the runaway of MCU is assumed).  
(10) Within interval time, by software writing to the WPR register with “A5” and “5A” has not been performed.  
(11) Interval signal output from the timebase counter. The watchdog timer counts.  
(12) Runaway is detected, WODOG flag has been changed to “1”.  
(13) Watchdog reset (INIT) has been generated.  
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Chapter 20 Software Watchdog Timer  
5.Operation  
5.2 Starting the Watchdog Timer and Setting the Watchdog Timer Period  
The watchdog timer starts once it first writes data to the RSRR (Reset cause register/Watchdog timer control  
register) after the reset (RST). At this time, Bits 1 and 0 (WT1 and WT0 bits) set the watchdog timer interval  
time. Only the setting for the interval time executed first after the reset is valid, and the other settings executed  
at a later time are invalid.  
5.3 Postponing the Generation of a Watchdog Reset  
Once watchdog timer is started, it is necessary that the WPR (watchdog reset generation postponement  
register) should be written periodically with {A5 } and {5A } in this order by software. This operation is used to  
H
H
set the 1-bit counter for detecting the watchdog reset to “0”.  
5.4 Confirming that the Watchdog Reset has been Generated  
The 1-bit counter for detecting the watchdog reset is set at the falling edge of the output of the timebase  
counter where an interval is set. In addition, if the second falling edge is detected while the 1-bit counter is set,  
the request for the setting initialization reset (INIT) is generated as the watchdog reset.  
5.5 Temporarily Stopped Watchdog Timer (Automatic Generation Postponement)  
The watchdog timer resets the 1-bit counter used for detecting the watchdog reset to “0” as initialization while  
CPU program operation is stopped. In this state, the generation of the watchdog reset is postponed. The  
states where programs stop running are concretely shown below.  
• Sleep  
• Stop  
• Oscillation stability wait RUN  
• Is in break when using the emulator debugger and monitor debugger, only if DSU4 is mounted  
• Is in break when using the embedded debug support unit (only if EDSU and EMMODE is enabled)  
• Period between the time when executing the INTE command and when executing RETI, only if DSU4 is  
mounted  
• Step trace trap (break per each command with PS register T flag=“1”), only if DSU4 is mounted  
In addition, clearing the timebase counter simultaneously initializes the 1-bit counter used for detecting the  
watchdog reset, thus causing the reset timing of the watchdog to be postponed.  
5.6 Stopping the Watchdog Timer  
Once the watchdog timer is started, the watchdog timer operation cannot be stopped until the initialization  
reset (RST) is generated.  
The watchdog timer is stopped under these states shown below where the operation initialization reset (RST)  
is generated until it is restarted by software.  
• Operation initialization reset (RST)  
• Setting initialization reset (INIT)  
• Oscillation stability wait reset  
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Chapter 20 Software Watchdog Timer  
6.Setting  
6. Setting  
Table 6-1 Setting Required for Using the Watchdog Timer  
Setting  
Interval time setting  
Startup of the watchdog  
Setting register  
Watchdog timer control register (RSRR)  
Setting method  
Refer to 7.1  
Refer to 7.2  
*: Refer to the number for more information on the setting method.  
Table 6-2 Setting Required for Delaying the Generation of the Watchdog  
Setting  
Setting register  
Setting method  
Setting required for delay the generation of the  
watchdog reset  
Watchdog reset generation delay register  
(WPR)  
Refer to 7.3  
*: Refer to the number for more information on the setting method.  
Table 6-3 Setting Required for Checking the Generation of the Watchdog  
Setting  
Setting register  
Setting method  
Watchdog generation check  
Watchdog timer control register (RSRR)  
Refer to 7.5  
*: Refer to the number for more information on the setting method.  
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Chapter 20 Software Watchdog Timer  
7.Q & A  
7. Q & A  
7.1 What are the types of watchdog interval time and how are they selected?  
There are four types of the interval period, and they are set using the interval selection bit (RSRR.WT[1:0]).  
Interval  
Selection bit  
(WT[1:0])  
Example) Interval Time  
Watchdog  
Interval time  
FΦ =80.0MHz  
FΦ = 2.00MHz  
FΦ = 32.768kHz  
Set the value to  
“00”  
20  
13.1 ms  
0.524 s  
2.097 s  
8.388 s  
33.554 s  
32.0 s  
To select Φ × 2  
To select Φ × 2  
To select Φ × 2  
To select Φ × 2  
Set the value to  
“01”  
22  
24  
26  
52.4 ms  
209.7 ms  
838.8 ms  
128.0 s  
512.0 s  
2048.0 s  
Set the value to  
“10”  
Set the value to  
“11”  
Note: F: Base clock. (Refer to “Chapter 13 Clock Control (Page No.189)”.)  
Only the data sets first written after the reset (INIT pin input, watchdog reset, software  
reset) are valid, and the other data sets are invalid.  
7.2 How is the watchdog operation started (set to valid)?  
Writing data in the watchdog timer control register RSRR causes the watchdog timer to be started (set to  
valid). Writing data in the interval selection bit (RSRR.WT[1:0]) causes the watchdog to be started.  
7.3 How can we check that the watchdog reset has been generated?  
If the watchdog reset flag (RSRR.WDOG) is set to “1”, the watchdog reset has been generated.  
7.4 How is the watchdog stopped?  
The watchdog cannot be stopped by the software.  
The watchdog can be stopped only with the reset (INIT pin input, watchdog reset).  
7.5 How do I clear the watchdog timer (1-bit counter)?  
Successively writing “A5 ” and “5A ” in the watchdog reset generation postponement register WPR causes  
H
H
the 1-bit counter used for detecting the watchdog to be cleared immediately after writing “5A ”. In this state,  
H
the reset timing of the watchdog can be postponed.  
In addition, if the timebase timer is cleared, the 1-bit counter used for detecting the watchdog is simultaneously  
reset.  
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Chapter 20 Software Watchdog Timer  
8.Caution  
8. Caution  
• Although the watchdog interval time corresponds to the one twice as long as the watchdog 1-bit counter, the  
watchdog timer clear operation only clears the 1-bit counter used for detecting the watchdog. As a result, the  
time margin to clear the watchdog timer is different from the interval time.  
Watchdog interval time selection  
Time margin to clear the watchdog timer  
Interval time during which the watchdog  
reset is generated  
WT1-WT0  
20  
20  
21  
23  
25  
27  
00  
01  
10  
11  
Φ × 2 (Initial value)  
Φ × 2 to Φ × 2  
22  
22  
Φ × 2  
Φ × 2 to Φ × 2  
24  
24  
Φ × 2  
Φ × 2 to Φ × 2  
26  
26  
Φ × 2  
Φ × 2 to Φ × 2  
• The watchdog timer is started once data is written in the watchdog timer control register.  
• The watchdog timer control register is also the reset cause register and the status (INIT, HSTB, WDOG,  
ERST, SRST and LINIT) is set to “0” when it is read.  
• The watchdog reset holds the oscillation stability wait time.  
(Refer to “Chapter 18 Timebase Counter (Page No.249)”.)  
• The watchdog reset from the main RUN or the sub-RUN where the main clock oscillation is in process  
cannot have the oscillation stability wait time because the main clock is oscillating.  
• Refer to “Chapter 19 Timebase Timer (Page No.263)” for the method of clearing the timebase counter that is the  
count source for the watchdog timer.  
• Clearing the timebase counter causes the watchdog reset timing to be postponed once.  
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Chapter 21 Hardware Watchdog Timer  
1.Overview  
Chapter 21 Hardware Watchdog Timer  
1. Overview  
The hardware watchdog timer (R/C oscillation based) provides a system reset if an internal  
watchdog timer is not cleared within the postponement duration.  
● Hardware watchdog timer  
This watchdog timer starts counting after the setting initialization reset (INIT) automatically. Clearing the  
counter in the postponement duration is necessary to continue running an application. Otherwise if the counter  
is not cleared within the postponement duration, e.g. due to infinite loop in the application, this module  
provides a reset signal (initialisation reset, INIT), which width is typical 20us (2 RC clock cycles at typical  
100kHz).  
If the CPU is in a standby mode as described below, this watchdog timer stops:  
• SLEEP mode: the CPU stops, the peripherals run.  
• STOP mode: the CPU and the peripherals stop.  
• RTC mode: the CPU and the peripherals stop but the RTC module and the oscillator run.  
If one of the below condition occurs, the watchdog counter is cleared:  
• Writing “0” to CL bit in the HWWD register  
• Initialisation Reset (INIT)  
• Operational Reset (RST)  
• Oscillation stops  
• Transition to the SLEEP/RTC/STOP mode  
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Chapter 21 Hardware Watchdog Timer  
2.Configuration  
2. Configuration  
Hardware watchdog timer consists of two sub-blocks:  
• Watchdog timer  
• Timer control and status register  
● Block diagram of the hardware watchdog timer  
Figure 2-1 Block Diagram of hardware watchdog timer  
Watchdog timer  
This is a timer to supervise CPU operation. The counter needs to be cleared periodically after releasing the  
reset.  
Hardware watchdog timer control status register  
This register has the reset flag and clear bit for the counter.  
Occuring of the watchdog reset  
If the counter has not been cleared periodically, this module provides a setting initialization reset (INIT). The  
width of internal reset signal is 63 times the system base clock. After the watchdog reset the normal system  
reset procedure starts. For more details about this procedure, see the corresponding section in the device  
state description.  
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Chapter 21 Hardware Watchdog Timer  
3.Register  
3. Register  
3.1 Hardware watchdog timer control and status register  
Hardware watchdog timer control status register (with reset flag and clear bit).  
• HWWD: Address 04C7h (Access: Byte)  
7
6
5
4
3
2
1
0
bit  
RESV0  
RESV0  
RESV0  
RESV1  
CL  
RESV0  
RESV0  
CPUF  
Initial value (INIT pin input,  
watchdog reset)  
0
0
0
1
1
0
0
0
Initial value  
(Software reset)  
0
0
0
1
1
0
0
X
R/W0  
R/W0  
R/W0  
R/W1  
W
R/W0  
R/W0  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7-5: Reserved bits. Always write “0” to these bits.  
• Bit4: Reserved bit. Always write “1” to this bit.  
• Bit3: CL (counter clear).  
CL  
0
Function  
By writing ‘0’ the watchdog timer is cleared  
Writing ‘1’ has no effect  
1
This bit is write only, it is always read as ‘1’.  
• Bit2-1: Reserved bits. Always write “0” to these bits.  
• Bit0: CPUF (CPU reset Flag).  
Function  
CPUF  
0
1
Watchdog reset not triggered  
Watchdog reset triggered (overflow of watchdog timer occured)  
This bit is initialized by external reset input (INITX) or clock supervisor reset, but not by internal reset.  
Writing ‘0’ clears this bit, writing ‘1’ has no effect.  
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Chapter 21 Hardware Watchdog Timer  
3.Register  
3.2 Hardware watchdog timer duration register  
Hardware watchdog timer duration register (elongation of the trigger duration).  
• HWWDE: Address 04C6h (Access: Byte)  
7
-
6
-
5
-
4
-
3
-
2
-
1
0
bit  
ED1  
ED0  
Initial value (INIT pin input,  
watchdog reset)  
-
-
-
-
-
-
0
0
Initial value  
(Software reset)  
-
-
-
-
-
-
0
0
RX/W0  
RX/W0  
RX/W0  
RX/W0  
RX/W0  
RX/W0  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7-2: Reserved bits. Always write “0” to these bits.  
• Bit1-0: ED (Elongate watchdog duration).  
ED1-0  
00  
Function  
The watchdog period is 2^16 RC clock cycles [initial setting]  
The watchdog period is 2^17 RC clock cycles *)  
The watchdog period is 2^18 RC clock cycles *)  
The watchdog period is 2^19 RC clock cycles *)  
01  
10  
11  
*) This setting is not available on MB91V460.  
286  
Chapter 21 Hardware Watchdog Timer  
4.Functions  
4. Functions  
If the watchdog timer is not cleared periodically, a setting initialization reset (INIT) occurs. In this case the  
value of registers in CPU is not guaranteed.  
● Function of the hardware watchdog timer  
After releasing INITX the hardware watchdog timer starts immediately without stabilization time. If the timer is  
not cleared periodically, setting initialization (INIT) reset occurs.  
● Period of the hardware watchdog timer  
The timer width is 16-bit. Since the RC oscillator is used as clock source of the hardware watchdog timer, the  
duration of the timer deviates with the RC oscillator accuracy:  
ED1-0  
Min.  
5
327.68  
655.36  
1310.72  
2621.44  
Typ.  
10  
655.36  
1310.72  
2621.44  
5242.88  
Max.  
20  
1310.72  
2621.44  
5242.88  
10485.76  
RC oscillation cycle (u s)  
Watchdog term (ms)  
00  
01  
10  
11  
Note: The watchdog duration elongation (ED1-0) setting is not available on MB91V460. In that case ED1-0 is  
always “00”.  
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Chapter 21 Hardware Watchdog Timer  
5.Caution  
5. Caution  
● Software disabling is not possible  
The watchdog timer starts counting immediately after reset (release of INITX). Software cannot stop  
the counting.  
● Hardware disabling is only possible on the evaluation device MB91V460  
The watchdog timer can be permanently disabled by setting the corresponding jumper of the  
evaluation board (this is not possible on flash devices with this watchdog timer). So always ensure  
correct configuration of the evalution system to reflect the behaviour of the flash device.  
● Postponement of reset  
In order to postpone the watchdog reset, the clearing of the watchdog timer is necessary. Whenever the CL bit  
of register is set to ‘0’ (there is no minimum writing limitation), the timer is cleared and the occurrance of reset  
is postponed. Just writing to the register without setting CL to ‘0’ does not clear the timer.  
● Timer stop and clear  
In modes where the CPU does not work (SLEEP, STOP or RTC mode), the timer is cleared first then the  
counting is stopped.  
● During DMA transfer  
During DMA transfer between D-bus modules, the writing ‘0’ to CL bit is not possible. Thus, if the transfer time  
is more than 328ms (calculated from the fastest frequency of the RC oscillator as minimum period), a reset  
occurs.  
● Duration setting  
Unlike on MB91V460 Rev.A it is possible on flash devices to elongate the duration of the watchdog reset.  
● RC clock frequency  
Unlike on MB91V460 Rev.A it is possible on flash devices to change the RC clock frequency to 2MHz. Even  
though the watchdog timer is always operated with a frequency of 100kHz (10us) typical.  
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Chapter 22 Main Oscillation Stabilisation Timer  
1.Overview  
Chapter 22 Main Oscillation Stabilisation Timer  
1. Overview  
The main clock oscillation stabilisation timer is a 23-bit counter that counts the main clock. This timer does not  
affect the selection of clock source operated by MCU/dividing setting.  
This timer is mainly used for acquiring main clock oscillation stability wait time to resume main clock oscillation  
after the main clock oscillation has been stopped (OSCCR.OSCDS1=1) while the subclock is being operated.  
In addition, this timer is best suited for interval timers or system clocks for real time OS.  
Main clock  
(Source oscillation)  
Up-counter  
Selector  
Interrupt  
2. Features  
• Type  
: 23-bit free run counter  
: 1  
• Quantity  
• Clock source  
: Main clock (source oscillation) --- Period = 1/F  
CL-MAIN  
• Interval time  
: 3 types  
12  
17  
23  
Period =2 /F  
, 2 /F  
, 2 /F  
,
CL-MAIN  
CL-MAIN  
CL-MAIN  
(1.0ms, 32.7ms, 2s / main clock 4MHz)  
• Cause of timer clear: (Software, overflow, reset (INIT))  
• Operation start/stop : Can be operated/stopped by the software.  
• Interrupt  
: Main clock oscillation stability wait interrupt (Interval interrupt)  
: Cannot read/write. (Clear only)  
• Count value  
289  
       
Chapter 22 Main Oscillation Stabilisation Timer  
3.Configuration  
3. Configuration  
Figure 3-1 Configuration Diagram  
Main clock oscillation stability wait timer  
Interval time  
WS1-0  
OSCR:bit 2-1  
0
0
0
1
0
1
Setting disable  
212  
F
CL-MAIN  
/
217 / FCL-MAIN  
223 / FCL-MAIN  
1
1
WIE  
OSCR:bit 6  
0
Interrupt disable  
Interrupt enable  
1
0
Timer operation enable  
WIF  
OSCR:bit 7  
READ:  
WEN  
OSCR:bit 5  
Main clock  
0
1
Operation stop  
0
1
Without interrupt request  
With interrupt request  
WRITE  
Operation enable  
Oscillation stability  
wait interrupt (#46)  
1
0
1
Flag clear  
Not affected  
23-bit free run timer  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22  
18 219 220  
222 223  
Main clock  
(Source oscillation)  
21 22 23 24 25 26 27 28 29 210 211 212 213 214 215 216 217  
2
2
Timer clear  
WCL  
OSCR:bit 2  
Timer clear  
0
1
Does not affect the operation  
Figure 3-2 List of Registers  
Note: Refer to “Chapter 24 Interrupt Control (Page No.311)” for the ICR register and the interrupt vector.  
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Chapter 22 Main Oscillation Stabilisation Timer  
4.Register  
4. Register  
4.1 OSCRH: Control Register for the Main Clock Oscillation Stability Wait Timer  
This register is used to select the interval time, clear the timer, control the interrupt, control the timer such as  
stop, and confirm the state of the timer.  
• OSCRH: Address 04C8h (Access: Byte)  
7
6
5
4
–
3
–
2
1
0
bit  
WIF  
WIE  
WEN  
WS1  
WS0  
WCL  
Initial value  
(INIT terminal input,  
watchdog reset)  
0
0
0
X
X
0
0
1
Initial value  
(Software reset)  
X
X
X
X
X
X
X
X
R(RM1),W  
R/W  
R/W  
RX/W0 RX/W0  
R/W  
R/W  
R1,W  
Attribute  
(For the attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• Bit7: Timer interrupt request flag  
WIF  
Read Operation  
Without interrupt request  
With interrupt request  
Write Operation  
0
1
Clears interrupt request flags  
Writing does not affect operation  
• The timer interrupt request flag bit is set to “1” at the falling edge of the selected interval period output.  
• Bit6: Interrupt request enable  
WIE  
Operation  
0
1
Interrupt request disable  
Interrupt request enable  
• If the timer interrupt request flag (WIF) is set to “1” while the interrupt request enable (WIE) is “1” an  
interrupt request is immediately generated.  
• Bit5: Timer operation enable  
WEN  
Operation  
0
1
Stops timer operation  
Enables timer operation  
• Bit4-3: Reserved bit Be sure to write “0”. The read value is “0”.  
• Bit2-1: Interval period selection  
WS1  
WS0  
Interval period (At 4MHz)  
0
0
Setting prohibted  
12  
0
1
1
1
0
1
2
2
2
/F  
/F  
/F  
(1.0ms)  
(32.7ms)  
(2.0s)  
CL-MAIN  
CL-MAIN  
CL-MAIN  
17  
23  
• The reset does not initialize. Be sure to set it after the startup.  
• Bit0: Timer clear  
WCL  
Operation  
0
1
Clears the main clock oscillation stability wait timer  
Writing does not affect operation  
• The timer is also cleared by INITX terminal input and watchdog reset.  
(Refer to “8. Caution (Page No.297)”.)  
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Chapter 22 Main Oscillation Stabilisation Timer  
5.Operation  
5. Operation  
This section describes the main clock oscillation stability wait timer operation.  
5.1 Main Clock Oscillation Stability Wait  
17  
(1) Selects the interval time. (WS[1:0]) (In this example, 2 /F  
(2) Sets timer clear (WCL=“0”) by the software.  
is selected.)  
CL-MAIC  
(3) Sets flag clear (WIF=“0”) and interrupt request enable (WIE=“1”) by the software.  
(4) Sets timer count enable (WEN=“1”) by the software.  
(5) Releases main clock stop (OSCCR.OSCDS1=“0”) while the subclock is in operation by the software, and starts  
main clock oscillation.  
(6) Starts counting (The timer counts up using the main clock (source oscillation).)  
(7) Stabilizes the main clock oscillation.  
17  
(8) The selected interval time is used. (Detects the falling edge of the dividing 2 .)  
(9) Generates a main clock oscillation stability wait interrupt.  
(10) Processing caused by an interrupt (Software): Operation clock switching (Sub-RUN => main RUN)  
(11) Disables interrupt request (WIE=“0”) and clears interrupt request (WIF=“0”).  
(12) Stops counting (WEN=“0”).  
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Chapter 22 Main Oscillation Stabilisation Timer  
5.Operation  
5.2 Interval Interrupt  
17  
(1) Selects the interval time (WS[1:0]). (In this example, 2 /F  
is selected.)  
CL-MAIC  
(2) Clears the timer (WCL=“0”), clears flags (WIF=“0”), enables interrupt request (WIE=“1”), enables timer count  
(WEN=“1”) by the software.  
(3) The timer counts up using the main clock (source oscillation).  
17  
(4) Generates interval interrupt at the selected interval time (Falling of the dividing 2 ).  
(5) Processing caused by an interrupt (Software): Clears interrupt request (WIF=“0”).  
(6) Repeats Items (3) to (5)  
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Chapter 22 Main Oscillation Stabilisation Timer  
6.Setting  
6. Setting  
Figure 6-1 Settings Required for Using the Main Clock Oscillation Stability Wait Timer  
Setting  
method*  
Setting  
Setting register  
Setting interval time  
Count clear  
7.1  
7.4  
7.3  
Main clock oscillation stability wait  
timer control register (OSCRH)  
Counting operation start  
*: Refer to the number for more information on the setting method.  
Figure 6-2 Settings Required for Enabling the Main Clock Oscillation Stability Wait Timer Interrupt  
Setting  
method*  
Setting  
Setting register  
Sets the main clock oscillation stability wait timer  
interrupt vector and  
Sets free run timer interrupt level  
Refer to “Chapter 24 Interrupt Con-  
trol (Page No.311)”.  
7.5  
Sets the main clock oscillation stability wait timer interrupt  
Clears interrupt request  
Enables interrupt request  
The main clock oscillation stability  
wait timer control register (OSCRH)  
7.7  
*: Refer to the number for more information on the setting method.  
Figure 6-3 Settings Required for Stopping the Main Clock Oscillation Stability Wait Timer  
Setting  
method*  
Setting  
Setting register  
The main clock oscillation stability  
wait timer control register (OSCRH)  
Sets the main clock oscillation stability wait timer stop  
7.8  
*: Refer to the number for more information on the setting method.  
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Chapter 22 Main Oscillation Stabilisation Timer  
7.Q & A  
7. Q & A  
7.1 What are the types of interval time (wait time) and how are they selected?  
There are 3 types of interval time, and they are set with the interval selection bit (OSCRH.WS[0:1]).  
Count period  
Interval (Wait time) Example  
At F = 4.00MHz  
Interval time  
Interval selection bit (WS[1:0])  
CLKP  
12  
Set the value to “01”  
Set the value to “10”  
Set the value to “11”  
1.00ms  
To set the value to 2 /F  
CL-MAIN  
CL-MAIN  
CL-MAIN  
17  
32.7ms  
2.00 s  
To set the value to 2 /F  
23  
To set the value to2 /F  
Note: Setting (WS[1:0]=“00”) is prohibited.  
7.2 How do I select the count clock?  
The count clock is the main clock (source oscillation). (Cannot be selected.)  
7.3 How is the main clock oscillation stability wait timer count operation enabled/  
disabled?  
Sets with the timer operation enable bit (OSCRH.WEN).  
Operation  
Timer operation enable bit (WEN)  
Set the value to “0”  
To stop the main clock oscillation stability wait timer  
To start the main clock oscillation stability wait timer  
Set the value to “1”  
7.4 How is the main clock oscillation stability wait timer cleared?  
The following methods are used to clear the main clock oscillation stability wait timer.  
• Sets with the clear bit (OSCRH.WCL).  
Operation  
Clear bit (WCL)  
To clear the main clock oscillation stability wait timer  
Writes “1”  
• Performs a reset.  
Clears the free run timer with the operation initialization reset (INIT terminal input, watchdog reset).  
(Value is held without being cleared even if a software reset is performed.)  
• The overflow (Next of “FFFFFFh”) of the main clock oscillation stability wait timer causes the count value to  
be reset to “000000 ”.  
H
7.5 What happens with the interrupt-associated registers?  
Setting the interrupt vector and interrupt level of the main clock oscillation stability wait timer  
The relationship between the interrupt level and the interrupt vector is shown in the following table.  
Refer to “Chapter 24 Interrupt Control (Page No.311)” for the interrupt level and interrupt vector.  
Interrupt vector (Default)  
Interrupt level setting bit (ICR4-ICR0)  
#143  
Address: 0FFDC0h  
Interrupt level register (ICR63)  
Address: 047Fh  
As the interrupt request flag (OSCRH.WIF) is not automatically cleared, clear it before returning to interrupt  
processing by the software. (Writes “0” in the WIF bit.)  
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Chapter 22 Main Oscillation Stabilisation Timer  
7.Q & A  
7.6 What are the types of interrupt?  
There is one type of interrupt called the main clock oscillation stability wait timer interrupt.  
(Selection is unnecessary.)  
7.7 how is an interrupt enabled?  
Interrupt request enable and interrupt request flag  
Setting the interrupt enable is performed with the interrupt request enable bit (OSCRH.WIE).  
Interrupt request enable bit (WIE)  
Interrupt disable  
Interrupt enable  
Set the value to “0”  
Set the value to “1”  
Clearing an interrupt request is performed with the interrupt request bit (OSCRH.WIF).  
Interrupt request bit (WIF)  
Interrupt request clear  
Writes “0”  
7.8 How is the main clock oscillation stability wait timer stopped counting?  
Sets with the timer operation enable bit (OSCRH.WEN). Refer to 7.3.  
In addition, if the MCU stops the main clock while the subclock is being operated, the main clock oscillation  
stability wait timer also stops counting.  
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Chapter 22 Main Oscillation Stabilisation Timer  
8.Caution  
8. Caution  
• To wait until the main clock oscillation stability is attained while the subclock is in operation, it is necessary  
to acquire wait time using the main clock oscillation stability wait timer.  
(An unstable clock may be supplied to the entire device, and normal operation is not guaranteed if the MCU  
operation mode is switched from the sub-RUN to the main RUN mode without waiting until the main clock  
oscillation becomes stable.)  
• The value for the oscillation stability wait time is an estimated value because the oscillation period of the  
main clock oscillation is unstable for the beginning immediately after the oscillation has started.  
• If the main clock oscillation stops, the main clock oscillation stability wait interrupt (interval interrupt) is not  
generated either because the main clock oscillation stability wait timer stops. The main clock oscillation  
should be enabled for processing that uses the main clock oscillation stability wait interrupt (interval  
interrupt).  
• The flag is set to “1” (flag setting preference) if the timer interrupt request (WIF=“1”) and the writing  
operation where “0” is written by software in the flag occur simultaneously.  
• The main clock oscillation stability wait timer is counted up with the main clock. As a result, in the following  
state, the counting of the timer used to stop the main clock oscillation also stops.  
• If the timer operation enable bit (OSCRH.WEN) is “0”, the timer stops counting.  
• If the main clock is stopped in the stop mode (STCR.OSCD1=“1”), the timer stops counting from the  
moment the stop mode is activated.  
• If the main clock oscillation is stopped (OSCCR.OSCDS1=“1”) during subclock operation, the timer stops  
while the subclock is in operation.  
• If you want to enable (WIE=“1”) the interrupt request after the reset is released, and the interval time to be  
modified, be sure to simultaneously set the interrupt request flag (WIF) and the clear bit (WCL) to “0”  
beforehand.  
• The timer interrupt request bit (WIF), timer interrupt request enable bit (WIE), timer enable bit (WEN) and  
timer clear bit (WCL) are initialized using the setting initialization reset (INIT terminal input, watchdog reset).  
• Be sure to set the interval selection bit (WS[1:0]) after startup (after setting initialization reset) by the  
software.  
• The main clock oscillation stability wait timer control register should be initialized (to set the initial value) only  
with the setting initialization reset (INIT terminal input, watchdog reset) because the software reset does not  
initialize the register and the current value is held.  
• If the counter clear (WPCR.WCL=“0”) and the overflow for the selected bit occur simultaneously, the  
interrupt request flag (WIF) is not set to “1”.  
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Chapter 22 Main Oscillation Stabilisation Timer  
8.Caution  
298  
Chapter 23 Sub Oscillation Stabilisation Timer  
1.Overview  
Chapter 23 Sub Oscillation Stabilisation Timer  
1. Overview  
The sub oscillation stabilisation timer is a 15-bit counter that is counted up with the subclock. This timer does  
not affect the selection/dividing setting of the MCU operating clock.  
This timer is used to acquire subclock oscillation stability wait time if the subclock oscillation is resumed mainly  
when the subclock oscillation is stopped while the main clock is in operation.  
This timer is can be used for acquiring sub clock oscillation stability wait time to resume sub clock oscillation  
after the sub clock oscillation has been stopped (OSCCR.OSCDS2=1) while the RC oscillator is being  
operated.  
Sub clock  
(Source oscillation)  
Up-counter  
Selector  
Interrupt  
2. Features  
• Type  
: 15-bit free run counter  
: 1  
• Quantity  
• Clock source  
: Subclock (source oscillation) --- Period = 1/F  
= 1/32.768kHz  
CL-SUB  
• Interval time  
: 4 types  
10  
13  
14  
15  
Period = 2 /F  
, 2 /F  
, 2 /F  
, 2 /F  
,
CL-SUB  
CL-SUB  
CL-SUB  
CL-SUB  
(31.25ms, 0.25s, 0.50s, 1.00s)  
• Timer clear cause: (Software, overflow, reset (INIT))  
• Interrupt  
: clock interrupt (interval interrupt)  
: Cannot read and write (Clear only)  
• Count value  
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Chapter 23 Sub Oscillation Stabilisation Timer  
3.Configuration  
3. Configuration  
Figure 3-1 Configuration Diagram  
Clock timer  
Interval time  
WS1-0  
WPCR:bit 2-1  
210 / FCL-SUB  
213 / FCL-SUB  
214 / FCL-SUB  
215 / FCL-SUB  
0
0
1
0
1
0
1
1
WIE  
WPCR:bit 6  
0
Interrupt disable  
Interrupt enable  
1
0
WIF  
WPCR:bit 7  
Clock timer  
Interrupt (#49)  
0
1
Without interrupt request  
With interrupt request  
Clock timer  
(14-bit free run timer)  
1
WRITE; 0: Flag clear  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14  
Sub-clock  
(Source oscillation)  
32.768 kHz  
21 22 23 24 25 26 27 28 29 210 211 212 213 214 215  
Timer clear  
WCL  
WPCR:bit 2  
Timer clear  
Does not affect the operation  
0
1
Figure 3-2 List of Registers  
Note: For the ICR register and interrupt vector, refer to “Chapter 24 Interrupt Control (Page No.311)”.  
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Chapter 23 Sub Oscillation Stabilisation Timer  
4.Register  
4. Register  
4.1 WPCRH: Sub oscillation stabilisation timer Control Register  
This register is used to select interval time, clear the timer, control interrupt, control timer stop etc., and  
confirm the states.  
• WPCRH: Address 04CAh (Access: Byte)  
7
WIF  
6
5
WEN  
0
4
–
3
–
2
1
0
bit  
WIE  
0
WS1  
0
WS0  
0
WCL  
1
0
X
X
Initial value (At INIT) *1  
Attribute  
R(RM1),W  
R/W  
R/W  
RX/W0 RX/W0  
R/W  
R/W  
R1,W  
(For the attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
(Refer to “8. Caution (Page No.309)”.)  
• Bit7: Sub oscillation stabilisation timer interrupt request flag  
WIF  
Read Operation  
Without interrupt request  
With interrupt request  
Write Operation  
0
1
Clears the interrupt request flag  
Writing does not affect operation  
• The sub oscillation stabilisation timer interrupt request flag bit is set to “1” at the falling edge of the  
selected interval period output.  
• Bit6: Interrupt request enable  
WIE  
Operation  
0
1
Interrupt request is prohibited  
Interrupt request enable  
• If the interrupt request enable bit is set to “1” an interrupt request is enabled.  
• If the sub oscillation stabilisation timer interrupt request flag is (WIF=“1”), and if the interrupt request  
enable bit (WIE) is set to “1”, an interrupt request is immediately generated.  
• Bit5: Timer operation enable  
WEN  
Operation  
0
1
Stops timer operation  
Enables timer operation  
• Bit4-3: Reserved bit Be sure to write “0”. The read value is “0”.  
• Bit2-1: Interval period selection  
Interval period (F  
= 32.768kHz)  
WS1  
WS0  
CL-SUB  
10  
13  
14  
15  
0
0
1
1
0
1
0
1
2
2
2
2
/F  
/F  
/F  
/F  
(31.25ms)  
(0.25s)  
CL-SUB  
CL-SUB  
CL-SUB  
CL-SUB  
(0.50s)  
(1.00s)  
• Bit0: Timer clear  
WCL  
Operation  
0
1
Clears the sub oscillation stabilisation timer.  
Writing does not affect write operation.  
• The timer is also cleared by INITX terminal input and watchdog reset.  
Notes 1: Initial value can be set using the setting initialization reset (INIT terminal input,  
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Chapter 23 Sub Oscillation Stabilisation Timer  
4.Register  
watchdog reset), but the operation initialization reset (Software reset) holds the current  
value instead of initializing it.  
2: If you set the interrupt request enable (WIE=“1”), and the interval period selection  
(WS[1:0]) after canceling the reset, be sure to simultaneously set the timer interrupt  
request flag (WIF) and the timer clear (WCL) “0”.  
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Chapter 23 Sub Oscillation Stabilisation Timer  
5.Operation  
5. Operation  
5.1 Subclock Oscillation Stability Wait Interrupt  
Figure 5-1 Reference  
(7)  
(5)  
Subclock  
oscillation example  
Clock timer  
counting  
(8)  
(8)  
0400h  
(6)  
0000h  
Time  
210 (Bit 9)  
(1)  
Subclock stop bit  
(4)  
WCL  
(2)  
(11)  
(9)  
WIF  
WIE  
(3)  
(3)  
(11)  
Operation clock mode  
Subclock  
Main clock  
(10)  
10  
(1) Selects the interval (WS[1:0]) (In this example, 2 /F  
is selected.)  
CL-SUB  
(2) Sets the timer so that it is cleared (WCL=“0”) by software.  
(3) Sets the flag clear (WIF=“0”) and the interrupt request enable (WIE=“1”) by software.  
(4) Sets the subclock stop release (OSCCR.OSCDS1=“0”) while the subclock is in operation by software.  
(5) The subclock oscillation starts.  
(6) Counts up with the subclock (source oscillation).  
(7) Make the subclock oscillation stable.  
10  
(8) Makes the interval time be the selected time. (Detects the falling of 2 dividing.)  
(9) If the flag (WIF) becomes “1”, the subclock oscillation stability wait interrupt request is generated.  
(10) Processing cause by an interrupt (Software): Switching the operation clock (Sub-RUN => main RUN)  
(11) Interrupt request disable (WIE=“0”) and the interrupt request clear (WIF=“0”).  
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Chapter 23 Sub Oscillation Stabilisation Timer  
5.Operation  
5.2 Interval Interrupt (Clock Interrupt)  
Clock timer  
counting  
(4)  
4000h  
(3)  
(4)  
2000h  
(3)  
(2)  
0000h  
Time  
(1) 213 (Bit12)  
(4)  
(4)  
(5)  
WCL  
WIF  
WIE  
(2)  
(6)  
(6)  
(2)  
(2)  
(5)  
13  
(1) Selects the interval time. (WS[1:0]) (In this example, 2 /F  
is selected.)  
CL-SUB  
(2) Sets the timer clear (WCL=“0”), flag clear (WIF=“0”) and interrupt request enable (WIE=“1”) by the software.  
(3) The timer counts up with the subclock (Source oscillation).  
13  
(4) Makes the interval time be the selected time. (Detects the fall of 2 .)  
(5) If the flag (WIF) is set to “1”, interval interrupt request (Clock interrupt request) is generated.  
(6) Processing caused by an interrupt (Software): The interrupt request clear (WIF=“0”)  
(Arbitrary processing such as clock counting)  
(7) Repeats Items (3) to (6).  
304  
Chapter 23 Sub Oscillation Stabilisation Timer  
5.Operation  
5.3 Returning from the Stop Mode due to Interval Operation (Clock Interrupt)  
Clock timer  
counting  
7FFFh  
4000h  
(2)  
0000h  
(3) 214 (Bit 13)  
(7)  
Interval time  
WCL  
WIF  
WIE  
(1)  
(10)  
(8)  
(4)  
(5)  
(9)  
(6)  
Main  
RUN  
Sub-  
RUN  
Sub-  
RUN  
Sub-  
RUN  
Sub-  
RUN  
Sub-  
RUN  
Sub-  
RUN  
STOP  
STOP  
STOP  
STOP  
STOP  
MCU state  
Oscillation stability wait time  
(1) The sub oscillation stabilisation timer is cleared by software. (Writes “0” to WCL.)  
(2) Counts up the sub oscillation stabilisation timer with the subclock.  
(3) Selects the interval time. (In this example, 0.5 second: Selects WS[1:0]=“10”.)  
(4) Sets the flag clear (WIF=“0”) and sub oscillation stabilisation timer interrupt enable (WIE=“1”) by the software.  
(5) Switches the MCU operation from the main RUN to sub-RUN.  
(6) Switches to the stop mode.  
(7) Makes the interval time be the selected time. (0.5 second)  
(8) The interrupt request flag (WIF) is set to “1”.  
(9) As the interrupt request is enabled (WIE=“1”), returns from the stop mode to sub-RUN.  
(10) Clears the interrupt request flag by software. (Writes “0” to the WIF.)  
(11) Repeats Items (6) from (10).  
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Chapter 23 Sub Oscillation Stabilisation Timer  
6.Setting  
6. Setting  
Table 6-1 Settings Required for Using the Sub oscillation stabilisation timer  
Setting  
method*  
Setting  
Setting register  
Setting the interval time  
Count clear  
Refer to 7.1.  
Refer to 7.4.  
Sub oscillation stabilisation timer control  
register (WPCRH)  
*: Refer to the number for more information on the setting method.  
Table 6-2 Items Required for Enabling the Sub oscillation stabilisation timer Interrupt  
Setting  
method*  
Setting  
Setting register  
Setting the interrupt vector and the free run timer level of  
the sub oscillation stabilisation timer  
Refer to “Chapter 24 Interrupt Control  
(Page No.311)”.  
Refer to 7.5.  
Refer to 7.7.  
Setting the sub oscillation stabilisation timer interrupt  
Clearing the interrupt request  
Enabling the interrupt request  
Sub oscillation stabilisation timer control  
register (WPCRH)  
*: Refer to the number for more information on the setting method.  
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Chapter 23 Sub Oscillation Stabilisation Timer  
7.Q & A  
7. Q & A  
7.1 What are the types of interval time (wait time) and how are they selected?  
There are three types of interval time, and they are set with the interval selection bit (WPCRH.WS[1:0]).  
Count period  
Interval (Wait time) Example  
= 32.768kHz  
Interval time  
F
Interval selection bit (WS[1:0])  
CL-SUB  
To set the interval time to  
Set the value to “00”.  
Set the value to “01”.  
Set the value to “10”.  
Set the value to “11”.  
31.25ms  
10  
2
/F  
CL-SUB  
To set the interval time to  
0.25s  
0.50s  
1.00s  
13  
2
/F  
CL-SUB  
To set the interval time to  
14  
2
/F  
CL-SUB  
To set the interval time to  
15  
2
/F  
CL-SUB  
7.2 How is the count clock selected?  
The count clock is the subclock (source oscillation).  
7.3 How is the sub oscillation stabilisation timer cleared?  
The following methods are available to clear the sub oscillation stabilisation timer.  
• Sets the clear bit (WPCRH.WCL).  
Operation  
Clear bit (WCL)  
To clear the sub oscillation stabilisation  
timer  
Writes “1”  
• Performs a reset.  
Clears the 15-bit free run timer with the initialization reset (INIT terminal input, watchdog reset).  
Note: The operation initialization reset (Software reset) holds the count of a 15-bit free run timer.  
• The overflow of the sub oscillation stabilisation timer (Next count-up for “FFFFh”) causes the count value to  
be reset to “0000 ”.  
H
7.4 What are interrupt-associated registers?  
Setting the interrupt vector and the interrupt level of the sub oscillation stabilisation timer  
The relationship between the interrupt level and the vector is shown in the following table.  
Refer to “Chapter 24 Interrupt Control (Page No.311)” for more information on the interrupt level and the  
interrupt vector.  
Interrupt vector (Default)  
Interrupt level setting bit (ICR[4:0])  
#143  
Address: 0FFDC0h  
Interrupt level register (ICR63)  
Address: 047Fh  
As the interrupt request flag (WPCRH.WIF) is not automatically cleared, clear it before returning from the  
interrupt processing by the software. (Writes “0” to the WIF bit.)  
7.5 What are the types of interrupt?  
There is one type for the interrupt, and it is generated with the interval time (Subclock oscillation stability wait).  
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Chapter 23 Sub Oscillation Stabilisation Timer  
7.Q & A  
7.6 How is the interrupt enabled?  
The interrupt request enable and the interrupt request flag  
The interrupt enable is set with the interrupt request enable bit (WPCRH.WIE).  
Interrupt request enable bit (WIE)  
Interrupt disable  
Interrupt enable  
Set the value to “0”  
Set the value to “1”  
The interrupt request is cleared with the interrupt request bit (WPCRH.WIF).  
Interrupt request bit (WIF)  
Interrupt request clear  
Writes “0”  
7.7 How is the sub oscillation stabilisation timer stopped counting?  
Sets with the timer operation enable bit (WPCRH.WEN). Refer to 7.3.  
In addition, if the MCU stops the sub clock while the mainclock is being operated, the sub clock oscillation  
stability wait timer also stops counting.  
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Chapter 23 Sub Oscillation Stabilisation Timer  
8.Caution  
8. Caution  
• If the setting request (WIF=“1”) of the timer interrupt request flag and the writing timing where “0” is written to  
the flag by the software occur simultaneously, the flag is set to “1”.  
• If the interrupt request is enabled (WIE=“1”) after defeating a reset, and if the interval time is changed, be  
sure to simultaneously set “0” to the interrupt request enable flag (WIF) and the clear bit (WCL).  
• Read-modify-write  
The interrupt request flag (WIF) is always read as “1” with the Read-modify-write.  
• The setting initialization reset (INIT terminal input, watchdog reset) initializes the values of the timer interrupt  
request bit (WIF), timer interrupt request enable bit (WIE), timer enable bit (WEN) and timer clear bit (WCL)  
to “0”, but cannot initialize the interval period selection bit (WS[1:0]). Be sure to set it by the software.  
• Setting the initial value of the sub oscillation stabilisation timer control register is possible using the  
initialization reset (INIT terminal input, watchdog reset), but the operation initialization reset (Software reset)  
holds the current value instead of initializing the value of the sub oscillation stabilisation timer control  
register.  
• The value for the oscillation stability wait time is an estimated value because the oscillation period of the  
main clock oscillation is unstable for the beginning immediately after the oscillation has started.  
• An unstable clock may be supplied to the entire device, and normal operation is not guaranteed if the  
subclock is made to oscillate starting from subclock stopped state, and if the MCU operation mode is  
switched from the main RUN to the sub-RUN mode without waiting until the subclock oscillation becomes  
stable. Be sure to acquire the subclock oscillation stability wait time using the sub oscillation stabilisation  
timer, etc. (If the main clock is selected as the clock source, the oscillation stability wait time for the subclock  
may not be acquired.)  
• The value for the oscillation stability wait time is an estimated value because the oscillation period of the  
subclock is unstable for the beginning immediately after it has started.  
• As the sub oscillation stabilisation timer stops while the subclock stops oscillating, a clock interrupt (interval  
interrupt) is not generated either. If processing using the clock interrupt (interval interrupt) is performed,  
enable the subclock oscillation. (Do not stop the subclock oscillation).  
• The sub oscillation stabilisation timer counts up with the subclock. As a result, the timer stops counting  
because the subclock stops oscillating under the following conditions.  
• If the subclock is set that it stops in the stop mode (Subclock oscillation enable bit* =“1”), and then the  
mode is switched to the stop mode, the sub oscillation stabilisation timer stops counting while in the stop  
mode.  
• If you want the sub oscillation stabilisation timer to continue counting while in stop mode, set the subclock  
oscillation enable bit to “0” before switching the mode to the stop mode.  
• If the subclock stop bit =“1” while in the subclock, and if the subclock is specified so that it stops  
oscillating while the subclock is in operation, the sub oscillation stabilisation timer stops, too, while the  
subclock is in operation.  
309  
 
Chapter 23 Sub Oscillation Stabilisation Timer  
8.Caution  
310  
Chapter 24 Interrupt Control  
1.Overview  
Chapter 24 Interrupt Control  
1. Overview  
Interrupt control manages interrupt reception and arbitration.  
Wakeup  
NMI  
Priority judging circuit  
Interrupt level/  
interrupt vector  
generator  
Level  
NMI processing  
HLDREQ  
cancel  
request  
Interrupt  
priority  
judging circuit  
HALT  
Interrupt requests  
To the CPU  
(peripheral function,  
INT instruction, and  
delayed interrupt)  
Vector number  
2. Features  
• Functions  
• Detection of interrupt requests  
• Priority determination (determined by level and number)  
• Interrupt level propagation of the factor of the priority to the CPU  
• Interrupt number propagation of the factor of the priority to the CPU  
• Request (to the CPU) to return from stop mode by a valid interrupt (Wakeup)  
• Interrupt level  
• Reserved for System: level 0 to 14  
• MNI  
: level 15  
• Interrupt  
: level 16 to 31  
• Interrupt disable : level 32  
(As the interrupt level goes up, the number goes down.)  
• Number of interrupt triggers  
• NMI  
: 1  
• Interrupt from peripheral functions: 128  
• Delayed interrupt : 1  
• Reserved for system (for REALOS): 2  
• INT instruction : 111  
311  
       
Chapter 24 Interrupt Control  
3.Configuration  
3. Configuration  
Figure 3-1 Configuration Diagram  
Priority judging circuit  
The enabled interrupt request  
NMI  
Interrupt  
request  
enable bit  
Wakeup  
Level  
NMI processing  
Interrupt level  
/interrupt  
number  
generator  
Interrupt  
Interrupt  
HLDREQ  
cancel  
request  
Interrupt priority  
judging circuit  
To the CPU  
request  
cause  
flag  
HALT  
Number  
Interrupt control register  
ICR (4-0)  
Cannot be set.  
00000  
01111  
10000  
Higher interrupt  
11110  
11111  
Lower interrupt  
Disable interrupts  
Figure 3-2 Configuration Diagram  
RAM  
(PS, PC)  
Interrupt control (CPU side)  
The inside of the CPU  
Interrupt level mask register  
ILM (4-0) ILM register in CPU  
SSP  
Rewrite  
00000  
l
System processing  
I flag  
01111  
PS  
0
Disable  
Prioritization  
10000  
l
11110  
Interrupt processing  
Initial level  
1
Enable  
PC  
11111  
Interrupt level [ICRxx: ICR (4-0)]  
Interrupt number (#)  
Table base register  
Initial value: FFC00  
TBR  
Interrupt  
control  
circuit  
Interrupt number (#) x 4 + TBR  
Address  
Vector table  
(1k Bytes)  
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Chapter 24 Interrupt Control  
4.Registers  
4. Registers  
4.1 ICR: Interrupt Control Register  
The register that specifies the interrupt level of an interrupt request.  
#16 External Interrupt 0  
: Address 0440  
ICR00  
ICR01  
ICR02  
ICR03  
ICR04  
ICR05  
ICR06  
ICR07  
ICR08  
ICR09  
ICR10  
ICR11  
ICR12  
ICR13  
ICR14  
ICR15  
ICR16  
ICR17  
ICR18  
ICR19  
ICR20  
ICR21  
ICR22  
ICR23  
ICR24  
ICR25  
ICR26  
ICR27  
ICR28  
(Access: Byte)  
H
H
H
H
H
H
H
H
H
H
#17 External Interrupt 1  
#18 External Interrupt 2  
#19 External Interrupt 3  
#20 External Interrupt 4  
#21 External Interrupt 5  
#22 External Interrupt 6  
#23 External Interrupt 7  
#24 External Interrupt 8  
#25 External Interrupt 9  
#26 External Interrupt 10  
#27 External Interrupt 11  
#28 External Interrupt 12  
#29 External Interrupt 13  
#30 External Interrupt 14  
#31 External Interrupt 15  
#32 Reload Timer 0  
#33 Reload Timer 1  
#34 Reload Timer 2  
#35 Reload Timer 3  
#36 Reload Timer 4  
#37 Reload Timer 5  
#38 Reload Timer 6  
#39 Reload Timer 7  
#40 Free Run Timer 0  
#41 Free Run Timer 1  
#42 Free Run Timer 2  
#43 Free Run Timer 3  
#44 Free Run Timer 4  
#45 Free Run Timer 5  
#46 Free Run Timer 6  
#47 Free Run Timer 7  
#48 CAN 0  
#49 CAN 1  
#50 CAN 2  
#51 CAN 3  
#52 CAN 4  
: Address 0441  
: Address 0442  
: Address 0443  
: Address 0444  
: Address 0445  
: Address 0446  
: Address 0447  
: Address 0448  
: Address 0449  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
: Address 044A  
: Address 044B  
H
H
H
: Address 044C  
: Address 044D  
: Address 044E  
H
H
H
: Address 044F  
: Address 0450  
H
H
H
H
H
H
H
: Address 0451  
: Address 0452  
: Address 0453  
: Address 0454  
: Address 0455  
: Address 0456  
#53 CAN 5  
#54 USART (LIN) 0 RX  
#55 USART (LIN) 0 TX  
#56 USART (LIN) 1 RX  
#57 USART (LIN) 1 TX  
#58 USART (LIN) 2 RX  
#59 USART (LIN) 2 TX  
#60 USART (LIN) 3 RX  
#61 USART (LIN) 3 TX  
#62 System reserved  
#63 Delayed Interrupt  
#64 System reserved (*1)  
#65 System reserved (*1)  
#66 USART (LIN, FIFO) 4 RX  
#67 USART (LIN, FIFO) 4 TX  
#68 USART (LIN, FIFO) 5 RX  
#69 USART (LIN, FIFO) 5 TX  
#70 USART (LIN, FIFO) 6 RX  
#71 USART (LIN, FIFO) 6 TX  
#72 USART (LIN, FIFO) 7 RX  
#73 USART (LIN, FIFO) 7 TX  
: Address 0457 (*2)  
H
: Address 0458  
H
: Address 0459  
H
: Address 045A  
H
: Address 045B  
H
: Address 045C  
H
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Chapter 24 Interrupt Control  
4.Registers  
#74 I2C 0 / I2C 2  
#75 I2C 1 / I2C 3  
: Address 045D  
: Address 045E  
ICR29  
ICR30  
ICR31  
ICR32  
ICR33  
ICR34  
ICR35  
ICR36  
ICR37  
ICR38  
ICR39  
ICR40  
ICR41  
ICR42  
ICR43  
ICR44  
ICR45  
ICR46  
ICR47  
ICR48  
ICR49  
ICR50  
ICR51  
ICR52  
ICR53  
ICR54  
ICR55  
ICR56  
ICR57  
ICR58  
ICR59  
ICR60  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
(Access: Byte)  
H
#76 USART (LIN) 8 RX  
#77 USART (LIN) 8 TX  
#78 USART (LIN) 9 RX  
#79 USART (LIN) 9 TX  
#80 USART (LIN) 10 RX  
#81 USART (LIN) 10 TX  
#82 USART (LIN) 11 RX  
#83 USART (LIN) 11 TX  
#84 USART (LIN) 12 RX  
#85 USART (LIN) 12 TX  
#86 USART (LIN) 13 RX  
#87 USART (LIN) 13 TX  
#88 USART (LIN) 14 RX  
#89 USART (LIN) 14 TX  
#90 USART (LIN) 15 RX  
#91 USART (LIN) 15 TX  
#92 Input Capture 0  
#93 Input Capture 1  
#94 Input Capture 2  
#95 Input Capture 3  
#96 Input Capture 4  
#97 Input Capture 5  
#98 Input Capture 6  
#99 Input Capture 7  
#100 Output Compare 0  
#101 Output Compare 1  
#102 Output Compare 2  
#103 Output Compare 3  
#104 Output Compare 4  
#105 Output Compare 5  
#106 Output Compare 6  
#107 Output Compare 7  
#108 Sound Generator  
#109 Phase Frequ. Modulator  
#110 System reserved  
#111 System reserved  
#112 Prog. Pulse Gen. 0  
#113 Prog. Pulse Gen. 1  
#114 Prog. Pulse Gen. 2  
#115 Prog. Pulse Gen. 3  
#116 Prog. Pulse Gen. 4  
#117 Prog. Pulse Gen. 5  
#118 Prog. Pulse Gen. 6  
#119 Prog. Pulse Gen. 7  
#120 Prog. Pulse Gen. 8  
#121 Prog. Pulse Gen. 9  
#122 Prog. Pulse Gen. 10  
#123 Prog. Pulse Gen. 11  
#124 Prog. Pulse Gen. 12  
#125 Prog. Pulse Gen. 13  
#126 Prog. Pulse Gen. 14  
#127 Prog. Pulse Gen. 15  
#128 Up/Down Counter 0  
#129 Up/Down Counter 1  
#130 Up/Down Counter 2  
#131 Up/Down Counter 3  
#132 Real Time Clock  
#133 Calibration Unit  
H
H
: Address 045F  
: Address 0460  
H
H
H
H
H
H
H
H
H
H
: Address 0461  
: Address 0462  
: Address 0463  
: Address 0464  
: Address 0465  
: Address 0466  
: Address 0467  
: Address 0468  
: Address 0469  
: Address 046A  
: Address 046B  
H
H
H
: Address 046C  
: Address 046D  
: Address 046E  
H
H
: Address 046F (*2)  
H
: Address 0470  
H
: Address 0471  
H
: Address 0472  
H
: Address 0473  
H
: Address 0474  
H
: Address 0475  
H
: Address 0476  
H
: Address 0477  
H
: Address 0478  
H
: Address 0479  
H
: Address 047A  
H
#134 A/D Converter 0  
: Address 047B  
H
#135  
-
#136 Alarm Comparator 0  
#137 Alarm Comparator 1  
: Address 047C  
H
314  
Chapter 24 Interrupt Control  
4.Registers  
#138 Low Voltage Detection  
#139 SMC Comparator 0-5  
#140 Timebase Overflow  
#141 PLL Clock Gear  
#142 DMA Controller  
#143 Main/Sub OSC stability wait  
: Address 047D  
: Address 047E  
ICR61  
ICR62  
ICR63  
(Access: Byte)  
H
(Access: Byte)  
(Access: Byte)  
H
H
: Address 047F  
(*1) : Used by REALOS  
(*2): ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0x0C03 : IOS[0])  
315  
Chapter 24 Interrupt Control  
4.Registers  
ICR (Interrupt Control Register) is a register in the interrupt controller, and it specifies the interrupt level for  
each interrupt request. ICR corresponds to each of interrupt request input. ICR is mapped to the I/O space.  
• ICR00 – ICR63  
7
–
6
–
5
–
4
3
2
1
0
bit  
ICR4  
ICR3  
ICR2  
ICR1  
ICR0  
Initial  
value  
–
–
–
1
1
1
1
1
RX/WX  
RX/WX  
RX/WX  
R/WX  
R/W  
R/W  
R/W  
R/W  
Attribute  
(About attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• Bit 7-5: Undefined. Writing does not affect the operation. The read value is indeterminate.  
• Bit 4-0: Interrupt level setting bits  
ICR4-ICR0 bits  
0000-01110  
01111  
Interrupt level  
Description  
0-14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Reserved for system (cannot to be set)  
NMI  
The highest level  
(High)  
10000  
10001  
10010  
10011  
10100  
10101  
10110  
10111  
11000  
11001  
11010  
11011  
11100  
11101  
(Low)  
11110  
The lowest level  
Disable interrupts  
11111  
• The interrupt level setting bit specifies the interrupt level of the corresponding interrupt request.  
• When the interrupt level set to the interrupt control register is the same as, or higher than the level mask  
value set to the ILM register of the CPU, the interrupt request is masked by the CPU side.  
316  
Chapter 24 Interrupt Control  
4.Registers  
4.2 Interrupt Vector  
Interrupt vector that corresponds to a vector number (#) with TBR register set to 0FFC00h (initial value):  
#00  
#01  
: Address  
: Address  
FFFBCh  
FFFB8h  
#07  
: Address  
: Address  
: Address  
FFFE0h  
FFF00h  
FFDC0h  
#63  
#143  
32 bits  
• Set the address of each interruption handling routine to the corresponding vector.  
• The address of a vector = TBR (table vector register) + {3FCH - 4 x vector number (#)}  
• EIT used by system (#0-#14)  
Interrupt number  
Interrupt level (fixed)  
Factor  
#0  
0
Reset vector  
#1  
1
Mode vector  
#2-#4  
#5  
–
Reserved for system  
CPU Supervisor Mode  
Memory Protection Exception  
Coprocessor absence trap  
Coprocessor error trap  
INTE instruction  
5
#6  
6
#7  
7
#8  
8
#9  
9
#10  
#11  
#12  
#13  
#14  
#15  
10  
11  
12  
13  
14  
15  
Instruction break exception  
Operand break trap  
Step trace trap  
MNI request (TOOL)  
Undefined-instruction exception  
NMI request  
317  
Chapter 24 Interrupt Control  
5.Operation  
5. Operation  
The following section explains priority determination operation of interrupt control.  
The Flow of the Interrupt Process  
Interrupt cause generated  
The interrupt request flag is set to “1”.  
CPU processing  
Is the interrupt level higher than  
the interrupt mask level?  
NO  
NO  
NO  
(ICR) < (ILM)  
Are interrupt requests enabled?  
YES  
YES  
The interrupt request is transmitted to  
the interrupt control circuit.  
Are interrupts enabled?  
I flag = 1  
Priority determination  
Interrupt control circuit  
YES  
Is not the corresponding interrupt disabled?  
(ICR) < 31?  
Wait until the executed instructions finish  
YES  
Interrupt level = 31  
Interrupt number  
= indeterminate  
Which interrupt has the lowest level  
among the interrupt requests?  
Transition processing to interrupts  
- Save to the system stack (PS and PC)  
- Set an interrupt level to ILM  
- System stack enabled  
The lowest interrupts  
- Branch to the interrupt routine  
(PC <= interrupt vector)  
Which interrupt has the lowest  
number (#) among the lowest  
interrupt requests?  
The interrupt with  
the lowest number  
The interrupt level and the interrupt number  
are transmitted to the CPU.  
■ Priority determination  
• The interrupt control circuit selects the highest priority factor from those that have been generated  
simultaneously, and outputs the factor's interrupt level (ICR) and interrupt number (#) to the CPU.  
• The priority level criteria of an interrupt cause are the following conditions.  
• The value of the interrupt level is not 31. (31 is “interrupt disable”)  
• The factors with the smallest interrupt level.  
• Among these, the factor that has the smallest interrupt number.  
• If nothing is applicable by the above-mentioned criteria, interrupt level 31 (11111 ) is sent to the CPU. In this  
B
case, the interrupt number is indeterminate.  
318  
 
Chapter 24 Interrupt Control  
6.Setting  
6. Setting  
Table 6-1 Setting Required to Use Interrupts  
Setting  
Procedure  
Setting  
Setting Registers  
Interrupt control registers (ICR00 to ICR63)  
Setting the interrupt level  
Clearing the interrupt request flags  
Enabling interrupt requests  
I flag setting  
See 7.1  
See the corresponding chapter for each peripheral function.  
See the corresponding chapter for each peripheral function.  
CCR register  
–
–
See 7.5  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-2 Setting that Requires the Setting within Interrupt Processing  
Setting  
Procedure  
Setting  
Setting Registers  
Clearing the interrupt request flags  
See the corresponding chapter for each peripheral function.  
–
7. Q & A  
7.1 How can I set interrupt levels?  
Set by Interrupt control registers (ICR00 to ICR63).  
It is necessary to set interrupt levels in advance to the control registers of the applicable interrupts.  
Interrupt control registers ICR00 to ICR63  
How to specify the highest level  
How to specify a level  
Set 16.  
Set any level (from 16 to 30).  
Set 30.  
How to specify the lowest level  
When interrupt is not used  
Set 31 (interrupt disable).  
• Since the bit of the interrupt control register (ICR[4]) is fixed to “1”, 0 to 15 cannot be set to a register.  
7.2 How do I enable interrupts?  
To enable interrupts, all of the following three settings should be set:  
• Set the value 16 to 30 to the applicable register in the interrupt control registers (ICR00-ICR63).  
• Set the interrupt request enabling bit of the applicable peripheral function to “1” (enable) (See the chapter  
for the corresponding peripheral function).  
• Set the interrupt enabling flag (I) to “1.”  
7.3 How do I disable interrupts?  
To disable interrupts, at least one of the following three settings should be set:  
• Set the value 31 to the applicable register in the interrupt control registers (ICR00-ICR63).  
• Set the interrupt request enabling bit of the applicable peripheral function to “0” (disable).  
• Set the interrupt enabling flag (I) to “0” (disable all interrupts.)  
319  
   
Chapter 24 Interrupt Control  
8.Caution  
7.4 How can I set an I flag?  
−>In C:  
I flag is set to “1” (interrupt enable) by writing __EI();.  
I flag is set to “0” (interrupt disable) by writing __DI();.  
Two underscores  
8. Caution  
Interrupt request flags are not cleared automatically. Make sure to clear them in the interrupt process.  
(They are usually cleared by writing “0” to the bit of the interrupt request flag, however, there are some  
exceptions depending on the type of peripheral functions. See the chapter for the corresponding peripheral  
function.)  
320  
 
Chapter 25 External Interrupt  
1.Overview  
Chapter 25 External Interrupt  
1. Overview  
External interrupt detects a signal input to an external interrupt input pin, and generates an interrupt request.  
Edge  
detection  
circuit  
Pins  
Interrupt requests  
2. Features  
• Quantity  
: 16 (INT input -- 16 channels: INT0-INT15)  
• Interrupt levels: 4 levels  
• “L” level  
• “H” level  
• Rising edge  
• Falling edge  
321  
     
Chapter 25 External Interrupt  
3.Configuration  
3. Configuration  
Figure 3-1 Configuration Diagram  
External interrupts 0 - 7  
Detect level setting  
External interrupt request enable flag  
LB0, LA0  
LB1, LA1  
LB2, LA2  
LB3, LA3  
LB4, LA4  
LB5, LA5  
LB6, LA6  
LB7, LA7  
ELVR0 : bit 1-0,  
ELVR0 : bit 3-2,  
ELVR0 : bit 5-4,  
ELVR0 : bit 7-6,  
ELVR0 : bit 9-8,  
ELVR0 : bit 11-10,  
ELVR0 : bit 13-12,  
ELVR0 : bit 15-14,  
EN0,  
EN1,  
EN2,  
EN3,  
EN4,  
EN5,  
EN6,  
EN7  
ENIR0 : bit 0  
ENIR0 : bit 1  
ENIR0 : bit 2  
ENIR0 : bit 3  
ENIR0 : bit 4  
ENIR0 : bit 5  
ENIR0 : bit 6  
ENIR0 : bit 7  
External interrupt request flag  
0
0
1
1
0
1
0
1
Detect at “L” level  
ER0,  
ER1,  
ER2,  
ER3,  
ER4,  
ER5,  
ER6,  
ER7  
EIRR0: bit n0  
EIRR0: bit n1  
EIRR0: bit n2  
EIRR0: bit n3  
EIRR0: bit n4  
EIRR0: bit n5  
EIRR0: bit n6  
EIRR0: bit n7  
Detect at “H” level  
Detect at the rising edge  
0
Disable interrupts  
Enable interrupts  
Detect at the falling edge  
1
0
1
INT0/P24.0  
INT1/P24.1  
INT2/P24.2  
Pins  
INT3/P24.3  
Interrupt request  
(#16, #17, #18, #19,  
#20, #21, #22, #23)  
Edge detection circuit  
INT4/SDA2/P24.4  
INT5/SCL2/P24.5  
INT6/SDA3/P24.6  
INT7/SCL3/P24.7  
0
1
No interrupt requests  
Interrupt request present  
WRITE 0: Flag clear  
(Inputs of other peripheral  
function macros)  
Read of the port  
1
(Outputs of other peripheral function macros)  
From the port data register  
0
Register number  
External  
External interrupt  
request level  
setting bit  
Enable external  
interrupt  
External  
interrupt  
P24.0 DDR24: bit0  
Port  
function  
---  
Interrupt  
number direction bit  
The data  
SDA2 PFR24: bit4  
SCL2 PFR24: bit5  
SDA3 PFR24: bit6  
SCL3 PFR24: bit7  
interrupt  
Pins  
P24.1 DDR24: bit1  
P24.2 DDR24: bit2  
P24.3 DDR24: bit3  
P24.4 DDR24: bit4  
P24.5 DDR24: bit5  
P24.6 DDR24: bit6  
P24.7 DDR24: bit7  
request bit  
requests  
INT0  
INT1  
INT2  
INT3  
INT4  
INT5  
INT6  
INT7  
0
1
LB0, LA0  
LB1, LA1  
LB2, LA2  
LB3, LA3  
LB4, LA4  
LB5, LA5  
LB6, LA6  
LB7, LA7  
ER0  
ER1  
ER2  
ER3  
ER4  
ER5  
ER6  
ER7  
EN0  
EN1  
EN2  
EN3  
EN4  
EN5  
EN6  
EN7  
#16  
#17  
#18  
#19  
#20  
#21  
#22  
#23  
P24.0  
P24.1  
P24.2  
P24.3  
P24.4  
P24.5  
P24.6  
P24.7  
---  
---  
---  
2
3
4
5
0
1
General-purpose port  
Peripheral  
SDA2  
SCL2  
SDA3  
SCL3  
Input only  
Enable output  
0
1
6
7
322  
 
Chapter 25 External Interrupt  
3.Configuration  
Figure 3-2 Configuration Diagram  
External interrupts 8 - 15  
Detect level setting  
External interrupt request enable flag  
LB8, LA8  
LB9, LA9  
ELVR1 : bit 1-0,  
ELVR1 : bit 3-2,  
ELVR1 : bit 5-4,  
ELVR1 : bit 7-6,  
ELVR1 : bit 9-8,  
ELVR1 : bit 11-10,  
ELVR1 : bit 13-12,  
ELVR1 : bit 15-14  
EN0,  
EN1,  
EN2,  
EN3,  
EN4,  
EN5,  
EN6,  
EN7  
ENIR1 : bit 0  
ENIR1 : bit 1  
ENIR1 : bit 2  
ENIR1 : bit 3  
ENIR1 : bit 4  
ENIR1 : bit 5  
ENIR1 : bit 6  
ENIR1 : bit 7  
LB10, LA10  
LB11, LA11  
LB12, LA12  
LB13, LA13  
LB14, LA14  
LB15, LA15  
External interrupt request flag  
0
0
1
1
0
1
0
1
Detect at “L” level  
ER0,  
ER1,  
ER2,  
ER3,  
ER4,  
ER5,  
ER6,  
ER7  
EIRR1: bit n0  
EIRR1: bit n1  
EIRR1: bit n2  
EIRR1: bit n3  
EIRR1: bit n4  
EIRR1: bit n5  
EIRR1: bit n6  
EIRR1: bit n7  
Detect at “H” level  
Detect at the rising edge  
0
Disable interrupts  
Enable interrupts  
Detect at the falling edge  
1
INT8/RX0/P23.0  
INT9/RX1/P23.2  
INT10/RX2/P23.4  
INT11/RX3/P23.6  
INT12/RX4/P22.0  
INT13/RX5/P22.2  
INT14/SDA0/P22.4  
INT15/SDA1/P22.6  
Pins  
Interrupt request  
(#24, #25, #26, #27  
#28, #29, #30, #31)  
Edge detection circuit  
0
1
No interrupt requests  
Interrupt request present  
WRITE 0: Flag clear  
(Inputs of other peripheral  
function macros)  
Read of the port  
1
(Outputs of other peripheral function macros)  
From the port data register  
0
Register number  
External  
interrupt  
External interrupt  
request level  
setting bit  
Enable external  
External  
interrupt  
Interrupt  
number direction bit  
The data  
Port  
Pins  
interrupt  
requests  
RX0 PFR23: bit0  
RX1 PFR23: bit2  
RX2 PFR23: bit4  
RX3 PFR23: bit6  
P23.0 DDR23: bit0  
P23.2 DDR23: bit2  
P23.4 DDR23: bit4  
P23.6 DDR23: bit6  
P22.0 DDR22: bit0  
P22.2 DDR22: bit2  
P22.4 DDR22: bit4  
P22.6 DDR22: bit6  
request bit  
function  
INT8  
INT9  
8
9
LB8, LA8  
LB9, LA9  
ER8  
ER9  
EN8  
EN9  
#24  
#25  
#26  
#27  
#28  
#29  
#30  
#31  
P23.0  
P23.2  
P23.4  
P23.6  
P22.0  
P22.2  
P22.4  
P22.6  
RX0  
RX1  
RX2  
LB10, LA10  
LB11, LA11  
LB12, LA12  
LB13, LA13  
LB14, LA14  
LB15, LA15  
ER10  
ER11  
ER12  
ER13  
ER14  
ER15  
EN10  
EN11  
EN12  
EN13  
EN14  
EN15  
INT10  
INT11  
INT12  
INT13  
INT14  
INT15  
10  
11  
12  
13  
RX4  
RX5  
SDA0  
SDA1  
PFR22: bit0  
PFR22: bit2  
PFR22: bit4  
PFR22: bit6  
RX3  
RX4  
RX5  
14  
15  
SDA0  
SDA1  
0
1
General-purpose port  
Peripheral  
Input only  
0
1
Enable output  
Figure 3-3 Register List  
323  
Chapter 25 External Interrupt  
3.Configuration  
Figure 3-4 Register List  
Note: See “Chapter 24 Interrupt Control (Page No.311)” about ICR register and interrupt vectors.  
324  
Chapter 25 External Interrupt  
4.Registers  
4. Registers  
4.1 ELVR: Interrupt Request Level Register  
The register that selects request detection of external interrupts.  
• ELVR0 (INT0-INT7): Address 032H (access: Half-word, Word)  
15  
14  
13  
12  
11  
10  
9
8
Bit  
LB7  
LA7  
LB6  
LA6  
LB5  
LA5  
LB4  
LA4  
0
0
0
0
0
0
0
0
Initial value  
Attribute  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
7
6
5
4
3
2
1
0
Bit  
LB3  
LA3  
LB2  
LA2  
LB1  
LA1  
LB0  
LA0  
0
0
0
0
0
0
0
0
Initial value  
Attribute  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
(About attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• ELVR1 (INT8-INT15): Address 036H (access: Half-word, Word)  
15  
14  
13  
12  
11  
10  
9
8
Bit  
LB15  
LA15  
LB14  
LA14  
LB13  
LA13  
LB12  
LA12  
0
0
0
0
0
0
0
0
Initial value  
Attribute  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
7
6
5
4
3
2
1
0
Bit  
LB11  
LA11  
LB10  
LA10  
LB9  
LA9  
LB8  
LA8  
0
0
0
0
0
0
0
0
Initial value  
Attribute  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
(About attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.)  
Interrupt request level bits (LBn, LAn) are registers that select request detection.  
2 bits (LBn, LAn) are assigned to each external interrupt INTn.  
LBn  
LAn  
Description  
Detect “L” level and generate an interrupt request.  
0
0
1
1
0
1
0
1
Detect “H” level and generate an interrupt request.  
Detect the rise and generate an interrupt request.  
Detect the fall and generate an interrupt request.  
When the request input is a level (LAn, LBn = “00” or “01”), and when the INTn pin input is the valid level, the  
corresponding bit (ERn) will be re-set to “1” even if the external interrupt request bit (ERn) is set to “0”.  
Note: n = 0 to 15  
325  
 
Chapter 25 External Interrupt  
4.Registers  
4.2 EIRR: Interrupt Request Register  
Status bit of a request of an external interrupt.  
• EIRR0 (INT0-INT7): Address 030H (access: Byte, Half-word, Word)  
7
ER7  
0
6
ER6  
0
5
ER5  
0
4
ER4  
0
3
ER3  
0
2
ER2  
0
1
ER1  
0
0
ER0  
0
Bit  
Initial value  
Attribute  
R (RM1), W R (RM1), W R (RM1), W R (RM1), W R (RM1), W R (RM1), W  
R (RM1), W R (RM1), W  
(About attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• EIRR1 (INT8-INT15): Address 034H (access: Byte, Half-word, Word)  
7
ER15  
0
6
ER14  
0
5
ER13  
0
4
ER12  
0
3
ER11  
0
2
ER10  
0
1
ER9  
0
0
ER8  
0
Bit  
Initial value  
Attribute  
R (RM1), W R (RM1), W R (RM1), W R (RM1), W R (RM1), W R (RM1), W  
R (RM1), W R (RM1), W  
(About attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.)  
An external interrupt request bit (ERn) indicates the corresponding external interrupt request.  
Description  
ERn  
Read value  
No external interrupt request present  
External interrupt request present  
Write value  
Clear external interrupt factor bits  
No effect on operation  
0
1
Note: n = 0 to 15  
4.3 ENIR: Interrupt Request Enable Register  
Enable bit of external interrupt requests.  
• ENIR0 (INT0-INT7): Address 031H (access: Byte, Half-word, Word)  
7
6
5
4
3
2
1
0
Bit  
EN7  
EN6  
EN5  
EN4  
EN3  
EN2  
EN1  
EN0  
0
0
0
0
0
0
0
0
Initial value  
Attribute  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
(About attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• ENIR1 (INT8-INT15): Address 035H (access: Byte, Half-word, Word)  
7
6
5
4
3
2
1
0
Bit  
EN15  
EN14  
EN13  
EN12  
EN11  
EN10  
EN9  
EN8  
0
0
0
0
0
0
0
0
Initial value  
Attribute  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
(About attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.)  
An external interrupt request enable bit (ENn) enables the corresponding external interrupt request.  
ERn  
Description  
0
1
External interrupt request output disable  
External interrupt request output enable  
Note: n = 0 to 15  
326  
Chapter 25 External Interrupt  
5.Operation  
5. Operation  
Level detection  
(2)  
(2)  
(1)  
(1)  
INT (“H”)  
(“L”)  
(3)  
(4)  
Valid edge  
Clear by software  
Interrupt request (ER)  
(5)  
Edge detection  
Internal clock  
(CLKP divided by two)  
(2)  
Required to maintain the level more than  
before and after the edge (3 x CLKP)  
(1)  
INT (rising)  
(fallling)  
(1)  
(2)  
(3)  
(4)  
Valid edge  
Clear by software  
Interrupt requests (ER)  
(5)  
(1) External interrupt signal (INT) input  
(2) Detect interrupt signals (level/edge).  
(3) Valid edge signal (3xCLKP above required)  
(4) An interrupt request generated.  
(5) The interrupt request is cleared with software.  
Remark: When waking up from STOP mode with edge detection enabled a minimum pulse pulse width (>  
50ns) of the INT signal trigger must be fulfilled.  
327  
 
Chapter 25 External Interrupt  
6.Setting  
6. Setting  
Table 6-1 Setting Required in Order to Use External Interrupts  
Setting  
Procedures*  
Setting  
Setting of detect level  
Setting Registers  
External interrupt request level setting register  
(ELVR0 - ELVR1)  
See 7.1  
See 7.2  
–
Data direction register (DDR22, DDR23, DDR24)  
Port function register (PFR22, PFR23, PFR24)  
Set INT pin as the input.  
External interrupt  
External inputs  
→Inputs the signal to INT0 - INT15 pins.  
Note: For the setting procedure, refer to the section indicated by the number.  
7. Q & A  
7.1 What are the types and setting procedures of detect levels?  
There are 4 types of detect levels: “L” level, “H” level, rise, and fall  
Carry out in Detection level bit (ELVR0. LBx, LAx) x = 0-7, and (ELVR1. LBx, LAx) x = 8-15.  
Operation mode  
Use as “L” level detection  
Use as “H” level detection  
Use as rise detection  
Detection level bit (LBn, LAn) n = 0-15  
Sets to “00”  
Sets to “01”  
Sets to “10”  
Sets to “11”  
Use as fall detection  
7.2 How do I set INT pin as the input?  
Use data direction registers (DDR22, DDR23, DDR24).  
Use port function register (PFR22, PFR23, PFR24).  
Operation  
Data Direction bits  
DDR24.0  
DDR24.1  
DDR24.2  
DDR24.3  
DDR24.4  
DDR24.5  
DDR24.6  
DDR24.7  
DDR23.0  
DDR23.2  
DDR23.4  
DDR23.6  
DDR22.0  
DDR22.2  
DDR22.4  
DDR22.6  
Setting  
Port Function bit  
PFR24.0  
PFR24.1  
PFR24.2  
PFR24.3  
PFR24.4  
PFR24.5  
PFR24.6  
PFR24.7  
PFR23.0  
PFR23.2  
PFR23.4  
PFR23.6  
PFR22.0  
PFR22.2  
PFR22.4  
PFR22.6  
Setting  
To use INT0 pin input  
To use INT1 pin input  
To use INT2 pin input  
To use INT3 pin input  
To use INT4 pin input  
To use INT5 pin input  
To use INT6 pin input  
To use INT7 pin input  
To use INT8 pin input  
To use INT9 pin input  
To use INT10 pin input  
To use INT11 pin input  
To use INT12 pin input  
To use INT13 pin input  
To use INT14 pin input  
To use INT15 pin input  
Set to “0”  
Set to “0”  
Set to “0”  
Set to “0”  
Set to “0”  
Set to “0”  
Set to “0”  
Set to “0”  
Set to “0”  
Set to “0”  
Set to “0”  
Set to “0”  
Set to “0”  
Set to “0”  
Set to “0”  
Set to “0”  
Set to “1”  
Set to “1”  
Set to “1”  
Set to “1”  
Set to “1”  
Set to “1”  
Set to “1”  
Set to “1”  
Set to “1”  
Set to “1”  
Set to “1”  
Set to “1”  
Set to “1”  
Set to “1”  
Set to “1”  
Set to “1”  
Remark: Even though the external interrupt can be even used with setting DDR=0 and PFR=0 (general  
purpose port input mode), the input line will be disabled when setting STOP mode with HIZ.  
328  
   
Chapter 25 External Interrupt  
7.Q & A  
7.3 What interrupt registers are used?  
Setting of interrupt vectors of external interrupts, and interrupt levels  
The relationship among external interrupt numbers, interrupt levels, and vectors is shown in the table below.  
See “Chapter 24 Interrupt Control (Page No.311)” about the details of interrupt levels and interrupt vectors.  
Interrupt vectors (default)  
Interrupt level setting bits (ICR[4:0])  
#16  
INT0  
INT1  
INT2  
INT3  
INT4  
INT5  
INT6  
INT7  
INT8  
INT9  
INT10  
INT11  
INT12  
INT13  
INT14  
INT15  
Address: 0FFFBCh  
Interrupt level register (ICR00)  
Address: 00440h  
#17  
Address: 0FFFB8h  
#18  
Address: 0FFFB4h  
Interrupt level register (ICR01)  
Address: 00441h  
#19  
Address: 0FFFB0h  
#20  
Address: 0FFFACh  
Interrupt level register (ICR02)  
Address: 00442h  
#21  
Address: 0FFFA8h  
#22  
Address: 0FFFA4h  
Interrupt level register (ICR03)  
Address: 00443h  
#23  
Address: 0FFFA0h  
#24  
Address: 0FFF9Ch  
Interrupt level register (ICR04)  
Address: 00444h  
#25  
Address: 0FFF98h  
#26  
Address: 0FFF94h  
Interrupt level register (ICR05)  
Address: 00445h  
#27  
Address: 0FFF90h  
#28  
Address: 0FFF8Ch  
Interrupt level register (ICR06)  
Address: 00446h  
#29  
Address: 0FFF88h  
#30  
Address: 0FFF84h  
Interrupt level register (ICR07)  
Address: 00447h  
#31  
Address: 0FFF80h  
7.4 Interrupt types  
Interrupt causes are limited to external interrupts. There is no bit for selection.  
329  
Chapter 25 External Interrupt  
7.Q & A  
7.5 How do I enable, disable, and clear interrupts?  
Enable flag for interrupt requests, interrupt request flag  
Use interrupt enabling bits (ENIR0.ENx. x = 0-7) and (ENIR1.ENx. x = 8-15) to enable interrupts.  
Interrupt enabling bit (En [n = 0-15])  
To disable interrupt requests  
To enable interrupt requests  
Sets to “0”  
Sets to “1”  
Use interrupt request bits (EIRR0.ERx. x = 0-7) and (EIRR1.ERx. x = 8-15) to clear interrupt requests.  
Interrupt request bit (Ern [n = 0-15])  
To clear interrupt requests  
Writes “0”  
330  
Chapter 25 External Interrupt  
8.Caution  
8. Caution  
• When the request input is a level (LAn, LBn = “00” or “01”) and when the INT pin input is the set active level,  
the corresponding bit (ERn) will be re-set to “1” even if the external interrupt request bit (ERn) is set to “0”.  
Note: n = 0 to 15  
• Before enabling the external interrupt request with ENn = “1” it is recommended to clear the external  
interrupt request bit (set ERn to “0”) to avoid interrupts caused by previous matches of the input trigger (the  
IRQ flag is set independently of the setting of ENn).  
Note: n = 0 to 15  
• Before going into standby (stop mode), make sure to disable unused external interrupts (ENn = “0”).  
Note: n = 0 - 15  
• Minimum 3x CLKP (peripheral clock) is required for the pulse width to detect the edge presence when the  
request level is set to the edge request.  
• When waking up from STOP mode with edge detection enabled a minimum pulse width (> 50ns) of the INT  
signal trigger must be fulfilled.  
• The interrupt request to the interrupt controller remains active even if an external interrupt request is input  
from the external interrupt pin INTn and canceled afterward, since the interrupt request flag (ERn) is present.  
To cancel the interrupt request to the interrupt controller, the interrupt request flag must be cleared (ERn =  
“0”) with software. (See the diagram in “5. Operation (Page No.327)”)  
Note: n = 0 to 15  
331  
 
Chapter 25 External Interrupt  
8.Caution  
332  
Chapter 26 DMA Controller  
1.Overview of the DMA Controller (DMAC)  
Chapter 26 DMA Controller  
1. Overview of the DMA Controller (DMAC)  
The DMA controller (DMAC) is a module that implements DMA (Direct Memory Access) transfer  
on FR family devices. When this module is used to control DMA transfer, various kinds of data  
can be transferred at high speed by bypassing the CPU, enhancing system performance.  
■ Hardware Configuration  
The DMA controller (DMAC) consists mainly of the following blocks:  
Five independent DMA channels  
•
•
•
•
•
•
•
•
•
•
5-channel independent access control circuit  
32-bit address registers (reload specifiable, two registers for each channel)  
16-bit transfer count register (reload specifiable, one register for each channel)  
4-bit block count register (one for each channel)  
Up to 128 internal transfer request sources  
External transfer request input pins: DREQ0, DREQ1, DREQ2, DREQ3 (for ch0-3 only)  
External transfer request acceptance output pins: DACK0, DACK1, DACK2, DACK3 (for ch0-3 only)  
DMA end output pins: DEOP0, DEOP1, DEOP2, DEOP3 (for ch0-3 only)  
Fly-by transfer (memory to I/O and I/O to memory) (for ch0-3 only)  
2-cycle transfer  
■ Main Functions  
The following are the main functions related to data transfer by the DMA controller (DMAC):  
Data can be transferred independently over multiple channels (5 channels)  
● Priority (ch.0>ch.1>ch.2>ch.3>ch.4)  
● The order can be rotated between ch.0 and ch.1.  
● DMAC start sources  
•
•
•
External dedicated pin input (edge detection/level detection for ch0-3 only)  
Built-in peripheral requests (shared interrupt requests, including external interrupts)  
Software request (register write)  
● Transfer mode  
•
•
Demand transfer, burst transfer, step transfer, and block transfer  
Addressing mode: 32-bit full addressing (increment/decrement/fixed)  
The address increment/decrement range is from -255 to +255.  
Data types: Byte, halfword, and word length  
•
•
Single shot/reload selectable  
333  
   
Chapter 26 DMA Controller  
1.Overview of the DMA Controller (DMAC)  
■ Block Diagram  
Figure 1-1"Block Diagram of the DMA Controller (DMAC)" is a block diagram of the DMA controller (DMAC).  
Figure 1-1 Block Diagram of the DMA Controller (DMAC)  
Counter  
DMA activation  
source  
selection circuit  
& request  
acceptance  
control  
Buffer  
DMA transfer request to  
the bus controller  
Peripheral activation request/stop input  
External pin activation request/stop input  
Selector  
DTC 2-stage register  
DTCR  
Counter  
Buffer  
DSS[3:0]  
Priority circuit  
IRQ[4:0]  
To interrupt controller  
Peripheral interrupt clear  
ERIR,EDIR  
Selector  
Read  
Write  
Read/write  
control  
MCLREQ  
BLK register  
TYPE.MOD,WS  
State  
transition  
circuit  
To bus  
controller  
DMA control  
SADM,SASZ[7:0] SADR  
DSAD 2-stage register  
Write back  
Access  
address  
DDAD 2-stage register  
DADM,DASZ[7:0] DADR  
Write back  
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Chapter 26 DMA Controller  
2.DMA Controller (DMAC) Registers  
2. DMA Controller (DMAC) Registers  
This section describes the configuration and functions of the registers used by the DMA control-  
ler (DMAC).  
■ DMA Controller (DMAC) registers  
Figure 2-1"DMA Controller (DMAC) Registers" shows the registers of the DMA controller (DMAC).  
Figure 2-1 DMA Controller (DMAC) Registers  
(bit)  
ch.0  
ch.0  
ch.1  
ch.1  
31 24 23 16 15 08 07 00  
Control/status register A  
Control/status register B  
Control/status register A  
Control/status register B  
(DMACA0)  
(DMACB0)  
(DMACA1)  
(DMACB1)  
(DMACA2)  
(DMACB2)  
(DMACA3)  
(DMACB3)  
(DMACA4)  
(DMACB4)  
(DMACR)  
ch.2  
ch.2  
Control/status register A  
Control/status register B  
ch.3  
ch.3  
ch.4  
ch.4  
Control/status register A  
Control/status register B  
Control/status register A  
Control/status register B  
All-channel control register  
ch.0  
ch.0  
ch.1  
ch.1  
ch.2  
ch.2  
ch.3  
Transfer source address register  
Transfer destination address register  
Transfer source address register  
Ttransfer destination address register  
Transfer source address register  
Transfer destination address register  
Transfer source address register  
Transfer destination address register  
Transfer source address register  
Transfer destination address register  
(DMASA0)  
(DMADA0)  
(DMASA1)  
(DMADA1)  
(DMASA2)  
(DMADA2)  
(DMASA3)  
(DMADA3)  
(DMASA4)  
(DMADA4)  
ch.3  
ch.4  
ch.4  
■ Notes on Setting Registers  
When the DMA controller (DMAC) is set, some bits need to be set while DMA is stopped. If they are set while  
DMA is in progress (during transfer), correct operation cannot be guaranteed.  
An asterisk following a bit when its function is described later indicates that the operation of the bit is affected if it  
is set during DMAC transfer. Rewrite this bit while DMAC transfer is stopped (start is disabled or temporarily  
stopped).  
335  
   
Chapter 26 DMA Controller  
2.DMA Controller (DMAC) Registers  
If the bit is set while DMA transfer start is disabled (when DMAE of DMACR=0, or DENB of DMACA=0), the  
setting takes effect when start is enabled.  
If the bit is set while DMA transfer is temporarily stopped (DMAH[3:0] of DMACR not equal to 0000 or PAUS of  
B
DMACA=1), the setting takes effect when temporary stopping is canceled.  
2.1 Control/Status Registers A (DMACA0 to 4)  
Control/status registers A (DMACA0 to 4) control the operation of the DMAC channels. There is  
a separate register for each channel.  
This section describes the configuration and functions of control/status registers A (DMACA0 to  
4).  
■ Bit Configuration of Control/Status Registers A (DMACA0 to 4)  
Figure 2-2"Bit Configuration of Control/Status Registers A (DMACA0 to 4)" shows the bit configuration of control/  
status registers A (DMACA0 to 4).  
Figure 2-2 Bit Configuration of Control/Status Registers A (DMACA0 to 4)  
bit  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value  
Address 000200H (ch0)  
000208H (ch1)  
000000000000XXXX  
IS[4:0]  
EIS[3:0]  
BLK[3:0]  
DENB PAUS STRG  
000210H (ch2) bit  
000218H (ch3)  
000220H (ch4)  
15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
DTC[15:0]  
XXXXXXXXXXXXXXXXB  
■ Detailed Bit of Control/Status Registers A (DMACA0 to 4)  
The following describes the functions of the bits of control/status registers A (DMACA0 to 4).  
[Bit 31] DENB (Dma ENaBle): DMA operation enable bit  
This bit, which corresponds to a transfer channel, is used to enable and disable DMA transfer.  
The activated channel starts DMA transfer when a transfer request is generated and accepted.  
All transfer requests that are generated for a deactivated channel are disabled.  
When the transfer on an activated channel reaches the specified count, this bit is set to 0 and transfer stops.  
The transfer can be forced to stop by writing 0 to this bit. Be sure to stop a transfer forcibly (0 write) only after  
temporarily stopping DMA using the PUAS bit (Bit30 of DMACA). If the transfer is forced to stop without first  
temporarily stopping DMA, DMA stops but the transferred data cannot be guaranteed. Check whether DMA is  
stopped using the DSS[2:0] bits [Bit18-16 of DMACB].  
DENB  
Function  
0
1
Disables operation of DMA on the corresponding channel (initial value).  
Enables operation of DMA on the corresponding channel.  
•
•
•
If a stop request is accepted during reset: Initialized to 0.  
This bit is readable and writable.  
If the operation of all channels is disabled by Bit15 (DMAE bit) of the DMAC all-channel control register  
(DMACR), writing 1 to this bit is disabled and the stopped state is maintained. If the operation is disabled by  
the above bit while it is enabled by this bit, 0 is written to this bit and the transfer is stopped (forced stop).  
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Chapter 26 DMA Controller  
2.DMA Controller (DMAC) Registers  
[Bit 30] PAUS (PAUSe)*: Temporary stop instruction  
This bit temporarily stops DMA transfer on the corresponding channel. If this bit is set, DMA transfer is not  
performed before this bit is cleared (While DMA is stopped, the DSS bits are 1xx .  
B
If this bit is set before starting, DMA transfer continues to be temporarily stopped.  
New transfer requests that occur while this bit is set are accepted, but no transfer starts before this bit is  
cleared (See 3.9"Operation from Starting to End/Stopping").  
PAUS  
Function  
0
1
Enables operation of the corresponding channel DMA (initial value)  
Temporarily stops DMA on the corresponding channel.  
•
•
When reset: Initialized to 0.  
This bit is readable and writable.  
[Bit 29] STRG (Software TRiGger): Transfer request  
This bit generates a DMA transfer request for the corresponding channel. If 1 is written to this bit, a transfer  
request is generated when write operation to the register is completed and transfer on the corresponding  
channel is started.  
However, if the corresponding channel is not activated, operations on this bit are disabled.  
If starting by a write operation to the DMAE bit and a transfer request occurring due to this bit are  
simultaneous, the transfer request is enabled and transfer is started. If writing of 1 to the PAUS bit and a  
transfer request occurring due to this bit are simultaneous, the transfer request is enabled, but DMA transfer is  
not started before 0 is written to the PAUS bit.  
STRG  
Function  
Disabled  
DMA starting request  
0
1
•
•
•
When reset: Initialized to 0.  
The read value is always 0.  
Only a write value of 1 is valid. If 0 is write, operation is not affected.  
337  
Chapter 26 DMA Controller  
2.DMA Controller (DMAC) Registers  
[Bits 28 to 24] IS4 to 0 (Input Select)*: Transfer source selection  
These bits select the source of a transfer request note that the software transfer request by the STRG bit  
function is always valid regardless of the setting of these bits. As listed in Table 2-1 "Settings for Transfer  
Request Sources".  
Table 2-1 Settings for Transfer Request Sources  
IS  
EIS  
RN  
Function  
Transfer stop request  
00000  
-
-
-
Activation by hardware prohibited  
00001  
-
Setting prohibited  
-
-
not available  
01101  
Setting prohibited  
01110  
01111  
-
-
-
External DMA-pin high level or rising edge  
External DMA-pin low level or falling edge  
External Interrupt 0  
-
10000 0000  
10001 0000  
10010 0000  
10011 0000  
10100 0000  
10101 0000  
10110 0000  
10111 0000  
11000 0000  
11001 0000  
0
1
2
3
4
5
6
7
8
9
-
External Interrupt 1  
-
External Interrupt 2  
-
External Interrupt 3  
-
Reload Timer 0  
-
Reload Timer 1  
-
USART (LIN) 0 RX  
available  
USART (LIN) 0 TX  
-
USART (LIN) 1 RX  
available  
USART (LIN) 1 TX  
-
11010 0000 10  
11011 0000 11  
11100 0000 12  
11101 0000 13  
11110 0000 14  
11111 0000 15  
USART (LIN, FIFO) 4 RX  
USART (LIN, FIFO) 4 TX  
USART (LIN, FIFO) 5 RX  
USART (LIN, FIFO) 5 TX  
A/D Converter  
available  
-
available  
-
-
-
Programmable Pulse Generator (PPG) 0  
•
•
•
When reset: IS4-0 is initialized to 00000 .  
B
When reset: EIS3-0 is initialized to 0000 .  
B
These bits are readable and writable.  
338  
 
Chapter 26 DMA Controller  
2.DMA Controller (DMAC) Registers  
Notes:  
•
•
•
If DMA start resulting from an interrupt from a peripheral function is set (IS=1xxxx ), disable interrupts from  
B
the selected peripheral function with the ICR register.  
If demand transfer mode is selected, only IS[4:0]=01110 , 01111 can be set. Starting by other sources is  
B
B
disabled.  
External request input is valid only for CH0, 1, and 2. External request input cannot be selected for CH2, CH3  
and 4. Whether level detection or edge detection is used is determined by the mode setting. Level detection is  
selected for demand transfer. For all other cases, edge detection is selected.  
[Bits 23 to 20] EIS3 to 0 (Extended Input Select)*: Extended Transfer Source Selection  
These bits select the source of a transfer request note that the software transfer request by the STRG bit  
function is always valid regardless of the setting of these bits. As listed in Table 2-2 "Settings for Extended  
Transfer Request Sources".  
Table 2-2 Settings for Extended Transfer Request Sources  
IS  
EIS  
RN  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
Function  
Transfer stop request  
10000 0001  
10001 0001  
10010 0001  
10011 0001  
10100 0001  
10101 0001  
10110 0001  
10111 0001  
11000 0001  
11001 0001  
11010 0001  
11011 0001  
11100 0001  
11101 0001  
11110 0001  
11111 0001  
10000 0010  
10001 0010  
10010 0010  
10011 0010  
10100 0010  
10101 0010  
External Interrupt 0  
External Interrupt 1  
External Interrupt 2  
External Interrupt 3  
External Interrupt 4  
External Interrupt 5  
External Interrupt 6  
External Interrupt 7  
res.  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
res.  
res.  
res.  
res.  
res.  
res.  
res.  
Reload Timer 0  
Reload Timer 1  
Reload Timer 2  
Reload Timer 3  
Reload Timer 4  
Reload Timer 5  
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Chapter 26 DMA Controller  
2.DMA Controller (DMAC) Registers  
Table 2-2 Settings for Extended Transfer Request Sources  
IS  
EIS  
RN  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
Function  
Transfer stop request  
10110 0010  
10111 0010  
11000 0010  
11001 0010  
11010 0010  
11011 0010  
11100 0010  
11101 0010  
11110 0010  
11111 0010  
10000 0011  
10001 0011  
10010 0011  
10011 0011  
10100 0011  
10101 0011  
10110 0011  
10111 0011  
11000 0011  
11001 0011  
11010 0011  
11011 0011  
11100 0011  
11101 0011  
11110 0011  
11111 0011  
10000 0100  
10001 0100  
10010 0100  
10011 0100  
10100 0100  
10101 0100  
Reload Timer 6  
-
Reload Timer 7  
-
Free Run Timer 0  
Free Run Timer 1  
Free Run Timer 2  
Free Run Timer 3  
Free Run Timer 4  
Free Run Timer 5  
Free Run Timer 6  
Free Run Timer 7  
USART (LIN) 0 RX  
USART (LIN) 0 TX  
USART (LIN) 1 RX  
USART (LIN) 1 TX  
USART (LIN) 2 RX  
USART (LIN) 2 TX  
USART (LIN) 3 RX  
USART (LIN) 3 TX  
-
-
-
-
-
-
-
-
available  
-
available  
-
available  
-
available  
-
USART (LIN, FIFO) 4 RX  
USART (LIN, FIFO) 4 TX  
USART (LIN, FIFO) 5 RX  
USART (LIN, FIFO) 5 TX  
USART (LIN, FIFO) 6 RX  
USART (LIN, FIFO) 6 TX  
USART (LIN, FIFO) 7 RX  
USART (LIN, FIFO) 7 TX  
USART (LIN) 8 RX  
available  
-
available  
-
available  
-
available  
-
available  
USART (LIN) 8 TX  
-
USART (LIN) 9 RX  
available  
USART (LIN) 9 TX  
-
USART (LIN) 10 RX  
available  
-
USART (LIN) 10 TX  
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Chapter 26 DMA Controller  
2.DMA Controller (DMAC) Registers  
Table 2-2 Settings for Extended Transfer Request Sources  
IS  
EIS  
RN  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
Function  
Transfer stop request  
10110 0100  
10111 0100  
11000 0100  
11001 0100  
11010 0100  
11011 0100  
11100 0100  
11101 0100  
11110 0100  
11111 0100  
10000 0101  
10001 0101  
10010 0101  
10011 0101  
10100 0101  
10101 0101  
10110 0101  
10111 0101  
11000 0101  
11001 0101  
11010 0101  
11011 0101  
11100 0101  
11101 0101  
11110 0101  
11111 0101  
10000 0110  
10001 0110  
10010 0110  
10011 0110  
10100 0110  
10101 0110  
USART (LIN) 11 RX  
USART (LIN) 11 TX  
USART (LIN) 12 RX  
USART (LIN) 12 TX  
USART (LIN) 13 RX  
USART (LIN) 13 TX  
USART (LIN) 14 RX  
USART (LIN) 14 TX  
USART (LIN) 15 RX  
USART (LIN) 15 TX  
Input Capture 0  
available  
-
available  
-
available  
-
available  
-
available  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Input Capture 1  
Input Capture 2  
Input Capture 3  
Input Capture 4  
Input Capture 5  
Input Capture 6  
Input Capture 7  
Output Compare 0  
Output Compare 1  
Output Compare 2  
Output Compare 3  
Output Compare 4  
Output Compare 5  
Output Compare 6  
Output Compare 7  
Programmable Pulse Generator 0  
Programmable Pulse Generator 1  
Programmable Pulse Generator 2  
Programmable Pulse Generator 3  
100 Programmable Pulse Generator 4  
101 Programmable Pulse Generator 5  
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Chapter 26 DMA Controller  
2.DMA Controller (DMAC) Registers  
Table 2-2 Settings for Extended Transfer Request Sources  
IS  
EIS  
RN  
Function  
Transfer stop request  
10110 0110  
10111 0110  
11000 0110  
11001 0110  
11010 0110  
11011 0110  
11100 0110  
11101 0110  
11110 0110  
11111 0110  
10000 0111  
10001 0111  
10010 0111  
102 Programmable Pulse Generator 6  
103 Programmable Pulse Generator 7  
104 Programmable Pulse Generator 8  
105 Programmable Pulse Generator 9  
106 Programmable Pulse Generator 10  
107 Programmable Pulse Generator 11  
108 Programmable Pulse Generator 12  
109 Programmable Pulse Generator 13  
110 Programmable Pulse Generator 14  
111 Programmable Pulse Generator 15  
112 ADC 0  
-
-
-
-
-
-
-
-
-
-
-
-
-
113 res.  
114 res.  
•
•
•
When reset: IS4-0 is initialized to 00000 .  
B
When reset: EIS3-0 is initialized to 0000 .  
B
These bits are readable and writable.  
[Bits 19 to 16] BLK3 to 0 (BLocK size): Block size specification  
These bits specify the block size for block transfer on the corresponding channel. The value specified by these  
bits becomes the number of words in one transfer unit (more exactly, the repetition count of the data width  
setting). If block transfer will not be performed, set 01 (size 1). This register value is ignored during demand  
H
transfer. The size becomes 1.  
BLK  
Function  
XXXX  
Block size of the corresponding channel  
B
•
•
•
•
When reset: Not initialized.  
These bits are readable and writable.  
If 0 is specified for all bits, the block size becomes 16 words.  
During reading, the block size is always read (reload value).  
[Bits 15 to 00] DTC (Dma Terminal Count register)*: Transfer count register  
The DTC register stores the transfer count. Each register has 16-bit length.  
All registers have a dedicated reload register. When the register is used for a channel that is enabled to reload  
the transfer count register, the initial value is automatically written back to the register when the transfer is  
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Chapter 26 DMA Controller  
2.DMA Controller (DMAC) Registers  
completed.  
DTC  
Function  
XXXX  
Transfer count for the corresponding channel  
B
When DMA transfer is started, data in this register is stored in the counter buffer of the DMA-dedicated transfer  
counter and is decremented by 1 (subtraction) after each transfer unit. When DMA transfer is completed, the  
contents of the counter buffer are written back to this register and then DMA ends. Thus, the transfer count value  
during DMA operation cannot be read.  
•
•
•
When reset: Not initialized.  
These bits are readable and writable. Always access DTC using halfword length or word length.  
During reading, the count value is read. The reload value cannot be read.  
2.2 Control/Status Registers B (DMACB0 to 4)  
Control/status registers B (DMACB0 to 4) control the operation of each DMAC channel and exist  
independently for each channel.  
This section describes the configuration of control/status registers B (DMACB0 to 4) and their  
functions.  
■ Bit Configuration of Control/Status Register B (DMACB0 to 4)  
Figure 2-3"Bit Configuration of Control/Status Registers B (DMACB0 to 4)" shows the bit configuration of control/  
status registers B (DMACB0 to 4).  
Figure 2-3 Bit Configuration of Control/Status Registers B (DMACB0 to 4)  
bit  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value  
Address 000204H (ch0)  
00020CH (ch1)  
0000000000000000  
TYPE[1:0] MOD[1:0] WS[1:0] SADM DADM DTCR SADR DADR ERIE EDIE  
DSS[2:0]  
1 0  
000214H (ch2)  
00021CH (ch3)  
000224H (ch4)  
bit  
15 14 13 12 11 10  
SASZ[7:0]  
9
8
7
6
5
4
3
2
DASZ[7:0]  
XXXXXXXXXXXXXXXXB  
■ Detailed Bit of Control/Status Register B (DMACB0 to 4)  
The following describeds the functions of the bits of control status register B (DMACB0 to 4).  
[Bits 31 to 30] TYPE (TYPE)*: Transfer type setting  
These bits are the transfer type setting bits and set the type of operation for the corresponding channel.  
•
•
2-cycle transfer mode: In this mode, the transfer source address (DMASA) and transfer destination address  
(DMADA) are set and transfer is performed by repeating the read operation and write operation for the number  
of times specified by the transfer count. All areas can be specified as a transfer source or transfer destination  
(32-bit address).  
Fly-by transfer mode: In this mode, external <--> external transfer is performed in one cycle by setting a  
memory address as the transfer destination address (DMADA). Be sure to specify an external area for the  
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memory address.  
Table 2-3 Settings for the Transfer Types  
TYPE  
Function  
00  
01  
10  
11  
2-cycle transfer (initial value)  
Fly-by: Memory --> I/O transfer  
Fly-by: I/O --> memory transfer  
Setting disabled  
B
B
B
B
•
•
When reset: Initialized to 00 .  
B
These bits are readable and writable.  
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[Bits 29, 28] MOD (MODe)*: Transfer mode setting  
These bits are the transfer mode setting bits and set the operating mode of the corresponding channel.  
Table 2-4 Settings for Transfer Modes  
MOD  
Function  
Block/step transfer mode (initial value)  
Burst transfer mode  
00  
01  
10  
11  
B
B
B
B
Demand transfer mode  
Setting disabled  
•
•
When reset: Initialized to 00 .  
B
These bits are readable and writable.  
[Bits 27 to 26] WS (Word Size)*: Transfer data width selection  
These bits are the transfer data width selection bits and are used to select the transfer data width of the  
corresponding channel. Transfer operations are repeated in units of the data width specified in this register for  
as many times as the specified count.  
Table 2-5 Selection of the Transfer Data Width  
WS  
Function  
Byte-width transfer (initial value)  
Halfword-width transfer  
Word-width transfer  
00  
01  
10  
11  
B
B
B
B
Setting disabled  
•
•
When reset: Initialized to 00 .  
B
These bits are readable and writable.  
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[Bit 25] SADM (Source-ADdr. Count-Mode select)*: Transfer source address count mode specification  
This bit specifies the address processing of the transfer source address of the corresponding channel in each  
transfer operation.  
An address increment is added or an address decrement is subtracted after each transfer operation according  
to the specified transfer source address count width (SASZ). When the transfer is completed, the next access  
address is written to the corresponding address register (DMASA).  
As a result, the transfer source address register is not updated until DMA transfer is completed.  
To make the address always the same, specify 0 or 1 for this register and make the address count width  
(SAAZ and DASZ) equal to 0.  
SADM  
Function  
0
1
Increments transfer source address. (initial value)  
Decrements the transfer source address.  
•
•
When reset: Initialized to 0.  
This bit is readable and writable.  
[Bit 24] DADM (Destination-ADdr. Count-Mode select)*: Transfer destination address count mode  
specification  
This bit specifies the address processing for the transfer destination address of the corresponding channel in  
each transfer operation.  
An address increment is added or an address decrement is subtracted after each transfer operation according  
to the specified transfer destination address count width (DASZ). When the transfer is completed, the next  
access address is written to the corresponding address register (DMADA).  
As a result, the transfer destination address register is not updated until the DMA transfer is completed.  
To make the address always the same, specify 0 or 1 for this register and make the address count width  
(SASZ, DASZ) equal to 0.  
DADM  
Function  
0
1
Increments the transfer source address. (initial value)  
Decrements the transfer source address.  
•
•
When reset: Initialized to 0.  
This bit is readable and writable.  
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[Bit 23] DTCR (DTC-reg. Reload)*: Transfer count register reload specification  
This bit controls reloading of the transfer count register for the corresponding channel.  
If reload operation is enabled by this bit, the count register value is restored to its initial value after the transfer  
is completed then DMAC stops and then waiting starts for new transfer requests (an activation request by  
STRG or IS setting). If this bit is 1, the DENB bit is not cleared.  
DENB=0 or DMAE=0 must be set to stop the transfer. In either case, the transfer is forcibly stopped.  
If reloading of the counter is disabled, a single shot operation occurs. In single shot operation, operation stops  
after the transfer is completed even if reload is specified in the address register. The DENB bit is also cleared  
in this case.  
DTCR  
Function  
0
1
Disables transfer count register reloading (initial value)  
Enables transfer count register reloading.  
•
•
When reset: Initialized to 0.  
This bit is readable and writable.  
[Bit 22] SADR (Source-ADdr.-reg. Reload)*: Transfer source address register reload specification  
This bit controls reloading of the transfer source address register for the corresponding channel.  
If this bit enables the reload operation, the transfer source address register value is restored to its initial value  
after the transfer is completed.  
If reloading of the counter is disabled, a single shot operation occurs. In single shot operation, operation stops  
after the transfer is completed even if reload is specified in the address register. The address register value  
also stops in this case while the initial value is being reloaded.  
If this bit disables the reload operation, the address register value when the transfer is completed is the  
address to be accessed next to the final address. When address increment is specified, the next address is an  
incremented address.  
SADR  
Function  
0
1
Disables transfer source address register reloading. (initial value)  
Enables transfer source address register reloading.  
•
•
When reset: Initialized to 0.  
This bit is readable and writable.  
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[Bit 21] DADR (Dest.-ADdr.-reg. Reload)*: Transfer destination address register reload specification  
This bit controls reloading of the transfer destination address register for the corresponding channel.  
If this bit enables reloading, the transfer destination address register value is restored to its initial value after  
the transfer is completed.  
The details of other functions are the same as those described for Bit22 (SADR).  
DADR  
Function  
0
1
Disables transfer destination address register reloading. (initial value)  
Enables transfer destination address register reloading.  
•
•
When reset: Initialized to 0.  
This bit is readable and writable.  
[Bit 20] ERIE (ERror Interrupt Enable)*: Error interrupt output enable  
This bit controls the occurrence of an interrupt for termination after an error occurs. The nature of the error that  
occurred is indicated by DSS2 to 0. Note that an interrupt occurs only for specific termination causes and not  
for all termination causes (Refer to bits DSS2 to 0, which are Bits 18 to 16).  
ERIE  
Function  
0
1
Disables error interrupt request output. (initial value)  
Enables error interrupt request output.  
•
•
When reset: Initialized to 0.  
This bit is readable and writable.  
[Bit 19] EDIE (EnD Interrupt Enable)*: End interrupt output enable  
This bit controls the occurrence of an interrupt for normal termination.  
EDIE  
Function  
0
1
Disables end interrupt request output. (initial value)  
Enables end interrupt request output.  
•
•
When reset: Initialized to 0.  
This bit is readable and writable.  
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[Bits 18 to 16] DSS2 to 0 (DMA Stop Status)*: Transfer stop source indication  
These bits indicate a code (end code) of 3 bits that indicates the source of stopping or termination of DMA  
transfer on the corresponding channel. For a list of end codes, see Table 2-6"End Codes".  
Table 2-6 End Codes  
DSS  
Function  
Interrupt  
000  
Initial value  
None  
Error  
Error  
End  
B
B
B
B
x01  
x10  
x11  
Address error (underflow/overflow)  
Transfer stop request  
Normal end  
DMA stopped temporarily (due, for example, to None  
DMAH, PAUS bit, and an interrupt)  
1xx  
B
A transfer stop request is set only when it is requested by a peripheral device or the external pin DSTP function is  
used.  
The Interrupt column indicates the type of interrupts that can occur.  
•
•
•
When reset: Initialized to 000 .  
B
These bits can be cleared by writing 000 to them.  
B
These bits are readable and writable. Note that the only valid written value is 000.  
[Bits 15 to 8] SASZ (Source Addr count SiZe)*: Transfer source address count size specification  
These bits specify the increment or decrement width for the transfer source address (DMASA) of the  
corresponding channel in each transfer operation. The value set by these bits becomes the address  
increment/decrement for each transfer unit. The address increment/decrement conforms to the instruction in  
the transfer source address count mode (SADM).  
SASZ  
XX  
Function  
Specify the increment/decrement width of the transfer source address. 0 to 255  
H
•
•
When reset: Not initialized  
These bits are readable and writable.  
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[Bits 7 to 0] DASZ (Des Addr count SiZe)*: Transfer destination address count size specification  
These bits specify the increment or decrement width for the transfer destination address (DMADA) of the  
corresponding channel in each transfer operation. The value set by these bits becomes the address  
increment/decrement for each transfer unit. The address increment/decrement conforms to the instruction in  
the transfer destination address count mode (DADM).  
DASZ  
XX  
Function  
Specify the increment/decrement width of the transfer destination address. 0 to 255  
H
•
•
When reset: Not initialized  
These bits are readable and writable.  
2.3 Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to 4/  
DMADA0 to 4)  
The transfer source/transfer destination address setting registers (DMASA0 to 4/DMADA0 to 4)  
control the operation of the DMAC channels. There is a separate register for each channel.  
This section describes the configuration and functions of the transfer source/transfer destination  
address setting registers (DMASA0 to 4/DMADA0 to 4).  
■ Bit Configuration of Transfer Source/Transfer Destination Address Setting Registers  
(DMASA0 to 4/DMADA0 to 4)  
The transfer source/transfer destination address setting registers (DMASA0 to 4/DMADA0 to 4) are a group of  
registers that store the transfer source/transfer destination addresses. Each register is 32 bits length.  
Figure 2-4"Bit Configuration of the Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to  
4/DMADA0 to 4)" shows the bit configuration of the transfer source/transfer destination address setting registers  
(DMASA0 to 4/DMADA0 to 4).  
Figure 2-4 Bit Configuration of the Transfer Source/Transfer Destination Address Setting Registers  
(DMASA0 to 4/DMADA0 to 4)  
Address  
Initial value  
bit  
bit  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16  
DMASA[31:16]  
001000H (ch0)  
001008H (ch1)  
001010H (ch2)  
001018H (ch3)  
001020H (ch4)  
XXXXXXXXXXXXXXXX  
15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
XXXXXXXXXXXXXXXXB  
DMASA[15:0]  
Address  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value  
bit  
bit  
001004H (ch0)  
00100CH (ch1)  
001014H (ch2)  
00101CH (ch3)  
001024H (ch4)  
DMADA[31:16]  
XXXXXXXXXXXXXXXX  
15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
DMADA[16:0]  
XXXXXXXXXXXXXXXXB  
Detailed Bit of Transfer Source/Transfer  
Destination Address Setting Register (DMASA0 to 4/DMADA0 to 4)  
The following describes the functions of the bits of each transfer source/transfer destination address setting  
register (DMASA0 to 4/DMADA0 to 4).  
[Bits 31 to 0] DMASA (DMA Source Addr)*: Transfer source address setting  
These bits set the transfer source address.  
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[Bits 31 to 0] DMADA (DMA Destination Addr)*: Transfer destination address setting  
These bits set the transfer destination address.  
If DMA transfer is activated, data in this register is stored in the counter buffer of the DMA-dedicated address  
counter and then the address is calculated according to the settings for the transfer operation. When the DMA  
transfer is completed, the contents of the counter buffer are written back to this register and then DMA ends.  
Thus, the address counter value during DMA operation cannot be read.  
All registers have a dedicated reload register. When the register is used for a channel that is enabled for  
reloading of the transfer source/transfer destination address register, the initial value is automatically written  
back to the register when the transfer is completed. Other address registers are not affected.  
•
•
•
When reset: Not initialized.  
These bits are readable and writable. For this register, be sure to access these bits as 32-bit data.  
If these bits are read during transfer, the address before the transfer is read. If they are read after transfer, the  
next access address is read. Because the reload value cannot be read, it is not possible to read the transfer  
address in real time.  
Note:  
Do not set any of the DMAC’s registers using this register. DMA transfer is not possible for the DMAC’s  
registers themselves.  
2.4 DMAC All-Channel Control Register (DMACR)  
The DMAC all-channel control register (DMACR) controls the operation of the all five DMAC  
channels. Be sure to access this register using byte length.  
This section describes the configuration and functions of the DMAC all-channel control register  
(DMACR).  
■ Bit Configuration of DMAC All-Channel Control Register (DMACR)  
Figure 2-5"Bit Configuration of the DMAC All-Channel Control Register (DMACR)" shows the bit configuration of  
the DMAC all-channel control register (DMACR).  
Figure 2-5 Bit Configuration of the DMAC All-Channel Control Register (DMACR)  
Initial value  
bit  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16  
Address 000240H  
-
-
-
-
-
-
-
-
-
-
0XX00000XXXXXXXX  
DMAE  
PM01  
DMAH[3:0]  
bit  
15 14 13 12 11 10  
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
XXXXXXXXXXXXXXXXB  
-
-
-
-
-
-
■ Detailed Bit of DMAC All-Channel Control Register (DMACR)  
The following describes the bit functions of the DMAC all-channel control register (DMACR) bits.  
[Bit 31] DMAE (DMA Enable): DMA operation enable  
This bit controls the operation of all DMA channels.  
If DMA operation is disabled with this bit, transfer operations on all channels are disabled regardless of the  
start/stop settings for each channel and the operating status. Any channel carrying out transfer cancels the  
requests and stops transfer at a block boundary. All start operations on each channel in a disabled state are  
disabled.  
If this bit enables DMA operation, start/stop operations are enabled for each channels. Simply enabling DMA  
operation with this bit does not activate each channel.  
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DMA operation can be forced to stop by writing 0 to this bit. However, be sure to force stopping (0 write) only  
after temporarily stopping DMA using the DMAH[3:0] bits [Bit27 to 24 of DMACR]. If forced stopping is carried  
out without first temporarily stopping DMA, DMA stops, but the transfer data cannot be guaranteed. Check  
whether DMA is stopped using the DSS[2:0] bits [Bit18 to 16 of DMACB].  
DMAE  
Function  
0
1
Disables DMA transfer on all channels. (initial value)  
Enables DMA transfer on all channels.  
•
•
When reset: Initialized to 0.  
This bit is readable and writable.  
[Bit 28] PM01 (Priority mode ch0,1 robine): Channel priority rotation  
This bit is set to alternate priority for each transfer between Channel0 and Channel1.  
PM01  
Function  
Fixes the priority. (ch0 > ch1)(initial value)  
Alternates priority. (ch1 > ch0)  
0
1
•
•
When reset: Initialized to 0.  
This bit is readable and writable.  
[Bits 27 to 24] DMAH (DMA Halt): DMA temporary stop  
These bits control temporary stopping of all DMA channels. If these bits are set, DMA transfer is not performed  
on any channel before these bits are cleared.  
When DMA transfer is activated after these bits are set, all channels remain temporarily stopped.  
Transfer requests that occur on channels for which DMA transfer is enabled (DENB=1) while these bits are set  
are all enabled. The transfer can be started by clearing all these bits.  
DMAH  
0000  
Function  
Enables the DMA operation on all channels. (initial value)  
Temporarily stops DMA operation on all channels.  
B
Other than 0000  
B
•
•
When reset: Initialized to 0.  
These bits are readable and writable.  
[Bits 30, 29, and 23 to 0] (Reserved): Unused bits  
These bits are unused.  
•
A read value is undefined.  
2.5 Other Functions  
The MB91460 series has the DACK, DEOP, and DREQ pins, which can be used for external  
transfer. These pins can also be used as general-purpose ports.  
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■ Pin Function of the DACK, and DEOP, and DREQ pins  
To use the DACK, DEOP, or DREQ pins for external transfer, a switch must be made from the port function to the  
DMA pin function.  
To make the switch, set the PFR register.  
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3. DMA Controller (DMAC) Operation  
A DMA controller (DMAC) is built into all FR family devices. The FR family DMAC is a multi-func-  
tional DMAC that controls data transfer at high speed without the use of CPU instructions.  
This section describes the operation of the DMAC.  
■ Principal Operations  
•
•
Functions can be set for each transfer channel independently.  
Once starting has been enabled, a channel starts transfer operation only after a specified transfer request has  
been detected.  
•
•
After a transfer request is detected, a DMA transfer request is output to the bus controller and the bus right is  
acquired by the bus controller before the transfer is started.  
The transfer is carried out as a sequence conforming to the mode settings made independently for the  
channel being used.  
■ Transfer Mode  
Each DMA channel performs transfer according to the transfer mode set by the MOD[1:0] bits of its DMACB  
register.  
● Block/step transfer  
Only a single block transfer unit is transferred in response to one transfer request. DMA then stops requesting the  
bus controller for transfer until the next transfer request is received.  
The block transfer unit is the specified block size (BLK[3:0] of DMACA).  
● Burst transfer  
Transfer in response to one transfer request is carried out continuously for the number of times in the specified  
transfer count is reached.  
The specified transfer count is the transfer count (BLK[3:0] of DMACA X DTC[15:0] of DMACA) X block size.  
● Demand transfer  
Transfer is carried out continuously until the transfer request input (detected with a level at the DREQ pin) from  
an external device or a specified transfer count is reached.  
The specified transfer count in a demand transfer is the specified transfer count (DTC[15:0] of DMACA). The  
block size is always 1 and the register value is ignored.  
■ Transfer Type  
● 2-cycle transfer (normal transfer)  
The DMA controller operates using a read operation and a write operation as its unit of operation.  
Data is read from an address in the transfer source register and then written to another address in the transfer  
destination register.  
● Fly-by transfer (memory --> I/O)  
The DMA controller operates using a read operation as its unit of operation.  
If DMA transfer is performed when fly-by transfer is set, DMA issues a fly-by transfer (read) request to the bus  
controller and the bus controller lets the external interface carry out the fly-by transfer (read).  
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● Fly-by transfer (I/O --> memory)  
The DMA controller operates using a write operation as its unit of operation.  
Otherwise, operation is the same as fly-by transfer (memory --> I/O) operation.  
Access areas used for MB91460 series fly-by transfer must be external areas.  
■ Transfer Address  
The following types of addressing are available and can be set independently for each channel transfer source  
and transfer destination.  
The method for specifying the address setting register (DMASA/DMADA) for a 2-cycle transfer and the method  
for a fly-by transfer are different.  
● Specifying the address for a 2-cycle transfer  
The value read from a register (DMASA/DMADA) in which an address has been set in advance is used as the  
address for access. After receiving a transfer request, DMA stores the address from the register in the temporary  
storage buffer and then starts transfer.  
After each transfer (access) operation, the next access address is generated (increment/decrement/fixed  
selectable) by the address counter and then written to the temporary storage buffer. Because the contents of the  
temporary storage buffer are written back to the register (DMASA/DMADA) after each block transfer unit is  
completed, the address register (DMASA/DMADA) value is updated after each block transfer unit is completed,  
making it impossible to determine the address in real time during transfer.  
● Specifying the address for a fly-by transfer  
In a fly-by transfer, the value read from the transfer destination address register (DMADA) is used as the address  
for access. The transfer source address register (DMASA) is ignored. Be sure to specify an external area as the  
address to be set.  
After receiving a transfer request, DMA stores the address from the register in the temporary storage buffer and  
then starts transfer.  
After each transfer (access) operation, the next access address is generated (increment/decrement/fixed  
selectable) by the address counter and then written to the temporary storage buffer. Because the contents of this  
temporary storage buffer are written back to the register (DMADA) after each block transfer unit is completed, the  
address register (DMADA) value is updated after each block transfer unit is completed, making it impossible to  
determine the address in real time during transfer.  
■ Transfer Count and Transfer End  
● Transfer count  
The transfer count register is decremented (-1) after each block transfer unit is completed. When the transfer  
count register becomes 0, counting for the specified transfer ends, and the transfer stops with the end code  
displayed or is reactivated *.  
Like the address register, the transfer count register value is updated only after each block transfer unit.  
*: If transfer count register reloading is disabled, the transfer ends. If reloading is enabled, the register value is  
initialized and then waits for transfer (DTCR of DMACB)  
● Transfer end  
Listed below are the sources for transfer end. When transfer ends, a source is indicated as the end code  
(DSS[2:0] of DMACB).  
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•
•
•
•
End of the specified transfer count (DMACA:BLK[3:0] x DMACA:DTC[15:0]) => Normal end  
A transfer stop request from a peripheral circuit or the external pin (DSTP) occurred => Error  
An address error occurred => Error  
A reset occurred => Reset  
The transfer stop source is indicated (DSS) and the transfer end interrupt or error interrupt for the end source is  
generated.  
3.1 Setting a Transfer Request  
The following three types of transfer requests are provided to activate DMA transfer:  
• External transfer request pin  
• Built-in peripheral request  
• Software request  
Software requests can always be used regardless of the settings of other requests.  
■ External Transfer Request Pin  
A transfer request is generated by input to the input pin prepared for a channel.  
The MB91460 series supports channels 0-3 (DREQ0-3).  
If the input is valid at this point, the following sources are selected depending on the settings for the transfer type  
and the start source:  
● Edge detection  
If the transfer type is block, step, or burst transfer, select edge detection:  
•
•
Falling edge detection: Set with the transfer source selection register. When IS[4:0] of DMACA=01110 .  
B
Rising edge detection: Set with the transfer source selection register. When IS[4:0] of DMACA=01111 .  
B
● Level detection  
If the transfer type is demand transfer, select level detection:  
•
•
H level detection: Set with the transfer source selection register. When IS[4:0] of DMACA=01110 .  
B
L level detection: Set with the transfer source selection register. When IS[4:0] of DMACA=01111 .  
B
■ Built-in Peripheral Request  
A transfer request is generated by an interrupt from the built-in peripheral circuit.  
For each channel, set the peripheral’s interrupt by which a transfer request is generated (When IS[4:0] of  
DMACA=1xxxx.)  
The built-in peripheral request cannot be used together with an external transfer request.  
Note:  
Because an interrupt request used in a transfer request seems like an interrupt request to the CPU, disable  
interrupts from the interrupt controller (ICR register).  
■ Software Request  
A transfer request is generated by writing to the trigger bit of a register (STRG of DMACA).  
The software request is independent of the external transfer request pin and built-in peripheral request and can  
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always be caused.  
If a software request occurs together with a start (transfer enable) request, the transfer is started by immediate  
output of a DMA transfer request to the bus controller.  
3.2 Transfer Sequence  
The transfer type and the transfer mode that determine, for example, the operation sequence  
after DMA transfer has started can be set independently for each channel (Settings for  
TYPE[1:0] and MOD[1:0] of DMACB).  
■ Selection of the Transfer Sequence  
The following sequence can be selected with a register setting:  
•
•
•
•
•
•
Burst 2-cycle transfer  
Demand 2-cycle transfer  
Block/step 2-cycle transfer  
Burst fly-by transfer  
Demand fly-by transfer  
Block/step fly-by transfer  
● Burst 2-cycle transfer  
In a burst 2-cycle transfer, as many transfers as specified by the transfer count are performed continuously for  
one transfer source. For a 2-cycle transfer, all 32-bit areas can be specified using a transfer source/transfer  
destination address.  
A peripheral transfer request, software transfer request, or external pin (DREQ) edge input detection request can  
be selected as the transfer source.  
Table 3-1 Specifiable transfer addresses (burst 2-cycle transfer)  
Transfer source addressing  
All 32-bit areas specifiable  
Direction  
=>  
Transfer destination addressing  
All 32-bit areas specifiable  
The following are some features of a burst transfer:  
When one transfer request is received, transfer is performed continuously until the transfer count register reaches  
0.  
The transfer count is the transfer count x block size (BLK[3:0] of DMACA x DTC[15:0] of DMACA).  
Another request occurring during transfer is ignored.  
If the reload function of the transfer count register is enabled, the next request is accepted after transfer ends.  
If a transfer request for another channel with a higher priority is received during transfer, the channel is switched  
at the boundary of the block transfer unit. Processing resumes only after the transfer request for the other  
channel is cleared.  
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Figure 3-1 Example of burst transfer for a start on an external pin rising edge, number of blocks =1, and  
transfer count = 4  
Transfer request ( edge)  
Bus operation  
Transfer count  
Transfer end  
SA DA SA DA SA DA SA DA  
CPU  
CPU  
4
3
2
1
0
● Burst fly-by transfer  
A burst fly-by transfer has the same features as a 2-cycle transfer except that the transfer area can only be  
external areas, and the transfer unit is read (memory --> I/O) or write (I/O --> memory) only.  
Table 3-2 Specifiable transfer addresses (burst fly-by transfer)  
Transfer source addressing  
Direction  
None  
Transfer destination addressing  
External area  
Specification not required (invalid)  
● Demand Transfer 2-Cycle Transfer  
A demand transfer sequence is generated only if H level or L level of an external pin is selected as a transfer  
request. Select the level with IS[3:0] of DMACA.  
The following are some features of a continuous transfer:  
The following are some features of a continuous transfer:  
•
•
Each transfer operation of a transfer request is checked. While the external input level is within the range of  
the specified transfer request levels, transfer is performed continuously without the request being cleared. If  
the external input changes, the request is cleared and the transfer stops at the transfer boundary. This  
operation is repeated for the number of times specified by the transfer count.  
Otherwise, operations are the same as those of a burst transfer.  
Figure 3-2 Example of demand transfer for a start with the external pin at H level, number of blocks = 1,  
and transfer count = 3  
Transfer request (H level)  
Bus operation  
Transfer count  
Transfer end  
CPU  
SA DA SA DA  
CPU  
SA DA  
1
3
2
0
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Table 3-3 Specifiable transfer addresses (demand transfer 2-cycle transfer)  
Transfer source address  
External area  
Direction  
Transfer destination addressing  
External area  
External area  
External area  
Built-in IO  
Built-in RAM  
External area  
External area  
Built-in IO  
Built-in RAM  
Note:  
For a demand transfer, be sure to set an external area address for the transfer source or transfer destination or  
both. Since DMA transfer is adjusted to the external bus timing in demand transfer mode, access to external  
areas is always needed.  
● Demand transfer fly-by transfer  
A demand transfer fly-by transfer has the same features as a 2-cycle transfer except that the transfer area can  
only be external areas, and the transfer unit is read (memory --> I/O) or write (I/O --> memory) only.  
Table 3.2-3 Specifiable transfer addresses (demand transfer fly-by transfer)  
Transfer source addressing  
Direction  
=>  
Transfer destination addressing  
External area  
Specification not required (invalid)  
● Step/block transfer 2-cycle transfer  
For a step/block transfer (Transfer for each transfer request is performed as many times as the specified block  
count), all 32-bit areas can be specified as the transfer source/transfer destination address.  
Table 3-4 Specifiable transfer addresses (step/block transfer 2-cycle transfer)  
Transfer source addressing  
All 32-bit areas specifiable  
Direction  
=>  
Transfer destination addressing  
All 32-bit areas specifiable  
[Step transfer]  
If 1 is set as the block size, a step transfer sequence is generated.  
The following are some features of a step transfer:  
•
•
If a transfer request is received, the transfer request is cleared after one transfer operation and then the  
transfer is stopped (The DMA transfer request to the bus controller is canceled).  
Another request occurring during transfer is ignored.  
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•
If a transfer request for another channel with a higher priority is received during transfer, the channel is  
switched after the transfer is stopped and then restarted. Priority in a step transfer is valid only if transfer  
requests occur simultaneously.  
[Block transfer]  
If any value other than 1 is specified as the block size, a block transfer sequence is generated.  
The following are some features of a block transfer:  
•
The block transfer has the same features as those of a step transfer except that one transfer unit consists of  
multiple transfer cycle counts (number of blocks).  
Figure 3-4 Example of block transfer for a start for an external pin on a rising edge, number of blocks = 2,  
and transfer count = 2  
Transfer request ( edge)  
Bus operation  
Number of blocks  
Transfer count  
Transfer end  
CPU  
SA DA SA DA  
SA DA SA DA  
CPU  
0
2
1
2
1
2
1
● Step/block transfer fly-by transfer  
This transfer has the same features as those of a 2-cycle transfer except that the transfer area can only be  
external areas, and the transfer unit is read (memory --> I/O) or write (I/O --> memory) only.  
Table 3-5 Specifiable transfer addresses (step/block transfer fly-by transfer)  
Transfer source addressing  
Direction  
None  
Transfer destination addressing  
External area  
Specification not required (invalid)  
3.3 General Aspects of DMA Transfer  
This section describes the block size for DMA transfers and the reload operation.  
■ Block Size  
•
•
•
The unit and increment for transfer data is a set of (the number set in the block size specification register x  
data width) data.  
Since the amount of data transferred in one transfer cycle is determined by the value specified as the data  
width, one transfer unit is consists of the number of transfer cycles for the specified block size.  
If a transfer request with a higher priority is received during transfer or if a temporary stop request for a  
transfer occurs, the transfer stops only at the transfer unit boundary, whether or not the transfer is a block  
transfer. This arrangement makes it possible to protect data for which division or temporary stopping is not  
desirable. However, if the block size is large, response time decreases.  
•
Transfer stops immediately only when a reset occurs, in which case the data being transferred cannot be  
guaranteed.  
■ Reload Operation  
In this module, the following three types of reloading can be set for each channel:  
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● Transfer count register reloading  
After transfer is performed the specified number of times, the initial value is set in the transfer count register again  
and waiting for a start request starts.  
Set this type of reloading when the entire transfer sequence is to be performed repeatedly.  
If reload is not specified, the count register value remains 0 after the transfer is performed the specified number of  
times and no further transfer is performed.  
● Transfer source address register reloading  
After transfer is performed the specified number of times, the initial value is set in the transfer source address  
register again.  
Set this type of reloading when transfer is to be repeated from a fixed area in the transfer source address area.  
If reload is not specified, the transfer source address register value after the transfer is performed the specified  
number of times becomes the next address. Use this type when the address area is not fixed.  
● Transfer destination address register reloading  
After transfer is performed the specified number of times, the initial value is set in the transfer destination address  
register again.  
Set this type of reloading when transfer is to be repeated to a fixed area in the transfer destination address area.  
(The processing hereafter is the same as described in "Transfer source address register reloading" above.)  
•
If only reloading of the transfer source/transfer destination register is enabled, restart after transfer is  
performed the specified number of times is not implemented and only the values of each address register are  
set.  
● Special examples of operating mode and the reload operation  
•
If transfer is performed in continuous transfer mode by external pin input level detection and transfer count  
register reloading is used, transfer continues by reloading even though transfer ends during continuous input.  
Also in this case, an end code is set.  
•
•
If it is preferable that processing stops when data transfer ends and starts after input is detected again, do not  
specify reload.  
For a transfer in burst, block, or step transfer mode, transfer stops temporarily after reload when data transfer  
ends. Transfer does not start until new transfer request input is detected.  
3.4 Addressing Mode  
Specify the transfer destination/transfer source address independently for each transfer chan-  
nel.  
■ Address Register Specifications  
The following two methods are provided to specify an address register. The method specified depends on the  
transfer sequence.  
•
In 2-cycle transfer mode, set the transfer source address in the transfer source address setting register  
(DMADA) and the transfer destination address in the transfer destination address setting register (DMASA).  
•
In fly-by transfer mode, specify the memory address in the transfer destination address setting register  
(DMASA). In this case, the value in the transfer source address setting register (DMADA) is ignored.  
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■ Features of the Address Register  
This register has the maximum 32-bit length. With 32-bit length, all space in the memory map can be accessed.  
■ Function of the Address Register  
•
•
The address register is read in each access operation and the read value is sent to the address bus.  
At the same time, the address for the next access is calculated by the address counter and the address  
register is updated using the calculated address.  
•
For address calculation, increment or decrement is selected independently for each channel, transfer  
destination, and transfer source. The address increment/decrement width is specified by the address count  
size register (SASZ/DASZ of DMACB).  
•
•
If reloading is not enabled, the address resulting from the address calculation of the last address remains in  
the address register when the transfer ends.  
If reloading is enabled, the initial value of the address is reloaded.  
Notes:  
•
If an overflow or underflow occurs as a result of 32-bit length full address calculation, an address error is  
detected and transfer on the relevant channel is stopped. Refer to the description for the items related to the  
end code.  
•
•
Do not set any of the DMAC’s registers as the address register.  
For demand transfer, be sure to set an address in an external area for the transfer source, transfer  
destination, or both.  
•
Do not let the DMAC transfer data to any of the DMAC’s registers.  
3.5 Data Types  
Select the data length (data width) transferred in one transfer operation from the following:  
• Byte  
• Halfword  
• Word  
■ Data Length (Data width)  
Since the word boundary specification is also observed in DMA transfer, different low-order bits are ignored if an  
address with a different data length is specified for the transfer destination/transfer source address.  
•
•
•
Byte: The actual access address and the addressing match.  
Halfword: The actual access address has 2-byte length starting with 0 as the lowest-order bit.  
Word: The actual access address has a 4-byte length starting with 00 as the lowest-order 2 bits.  
If the lowest-order bits in the transfer source address and transfer destination address are different, the  
addresses as set are output on the internal address bus. However, each transfer target on the bus is accessed  
after the addresses are corrected according to the above rules.  
3.6 Transfer Count Control  
Specify the transfer count within the range of the maximum 16-bit length (1 to 65536).  
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■ Transfer Count Control  
Set the transfer count value in the transfer count register (DTC of DMACA).  
The register value is stored in the temporary storage buffer when the transfer starts and is decremented by the  
transfer counter. When the counter value becomes 0, end of transfer end for the specified count is detected, and  
the transfer on the channel is stopped or waiting for a restart request starts (when reload is specified).  
The following are some features of the group of transfer count registers:  
•
•
•
Each register has 16-bit length.  
All registers have a dedicated reload register.  
If transfer is activated when the register value is 0, transfer is performed 65536 times.  
■ Reload Operation  
•
•
•
The reload operation can be used only if reloading is enabled in a register that allows reloading.  
When transfer is activated, the initial value of the count register is saved in the reload register.  
If the transfer counter counts down to 0, end of transfer is reported and the initial value is read from the reload  
register and written to the count register.  
3.7 CPU Control  
When a DMA transfer request is accepted, DMA issues a transfer request to the bus controller.  
The bus controller passes the right to use the internal bus to DMA at a break in bus operation  
and DMA transfer starts.  
■ DMA Transfer and Interrupts  
•
•
During DMA transfer, interrupts are generally not accepted until the transfer ends.  
If a DMA transfer request occurs during interrupt processing, the transfer request is accepted and interrupt  
processing is stopped until the transfer is completed.  
•
If, as an exception, an NMI request or an interrupt request with a higher level than the hold suppress level set  
by the interrupt controller occurs, DMAC temporarily cancels the transfer request via the bus controller at a  
transfer unit boundary (one block) to temporarily stop the transfer until the interrupt request is cleared. In the  
meantime, the transfer request is retained internally. After the interrupt request is cleared, DMAC reissues a  
transfer request to the bus controller to acquire the right to use the bus and then restarts DMA transfer.  
■ Suppressing DMA  
When an interrupt source with a higher priority occurs during DMA transfer, an FR family device interrupts the  
DMA transfer and branches to the relevant interrupt routine. This feature is valid as long as there are any interrupt  
requests. When all interrupt sources are cleared, the suppression feature no longer works and the DMA transfer  
is restarted by the interrupt processing routine. Thus, if you want to suppress restart of DMA transfer after  
clearing interrupt sources in the interrupt source processing routine at a level that interrupts DMA transfer, use  
the DMA suppress function. The DMA suppress function can be activated by writing any value other than 0 to the  
DMAH[3:0] bits of the DMA all-channel control register and can be stopped by writing 0 to these bits.  
This function is mainly used in the interrupt processing routines. Before the interrupt sources in an interrupt  
processing routine are cleared, the DMA suppress register is incremented by 1. If this is done, then no DMA  
transfer is performed. After interrupt processing, decrement the DMAH[3:0] bits by 1 before returning. If multiple  
interrupts have occurred, DMA transfer continues to be suppressed since the DMAH[3:0] bits are not 0 yet. If a  
single interrupt has occurred, the DMAH[3:0] bits become 0. DMA requests are then enabled immediately.  
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Note:  
•
•
Since the register has only four bits, this function cannot be used for multiple interrupts exceeding 15 levels.  
Be sure to assign the priority of the DMA tasks at a level that is at least 15 levels higher than other interrupt  
levels.  
3.8 Hold Arbitration  
When a device is operating in external bus extended mode, an external hold function can be  
used. The relationship between external hold requests and DMA transfer requests by this mod-  
ule when the hold function can be used is described below.  
■ DMA Transfer Request during External Hold  
DMA transfer is started when an external bus area is accessed, DMA transfer is temporarily stopped. When the  
external hold is released, DMA transfer is restarted.  
■ External Hold Request During DMA Transfer  
The device is externally held. When an external bus area is accessed by DMA transfer, DMA transfer is  
temporarily stopped. When the external hold is released, DMA transfer is restarted.  
■ Simultaneous Occurrence of a DMA Transfer Request and an External Hold Request  
The device is externally held and internal DMA transfer is started. When an external bus area is accessed by  
DMA transfer, DMA transfer is temporarily stopped. When the external hold is released, DMA transfer is  
restarted.  
3.9 Operation from Starting to End/Stopping  
Starting of DMA transfer is controlled independently for each channel, but before transfer starts,  
the operation of all channels needs to be enabled. This section describes operation from starting  
to end/stopping.  
■ Operation Start  
● Enabling operation for all channels  
Before activating each DMAC channel, operation for all channels needs to be enabled in advance with the DMA  
operation enable bit (DMAE of DMACR). All start settings and transfer requests that occurred before operation is  
enabled are invalid.  
● Starting transfer  
The transfer operation can be started by the operation enable bit of the control register for each channel. If a  
transfer request to an activated channel is accepted, the DMA transfer operation is started in the specified mode.  
● Starting from a temporary stop  
If a temporary stop occurs before starting with channel-by-channel or all-channel control, the temporary stopped  
state is maintained even though the transfer operation is started. If transfer requests occur in the meantime, they  
are accepted and retained. When temporary stopping is released, transfer is started.  
■ Transfer Request Acceptance and Transfer  
Sampling for transfer requests set for each channel starts after starting.  
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If edge detection is selected for the external pin start source and a transfer request is detected, the request is  
retained within DMAC until the clear conditions are met (when the external pin start source is selected for block,  
step, or burst transfer).  
If level detection or peripheral interrupt start is selected for the external pin start source, DMAC continues the  
transfer until all transfer requests are cleared. When they are cleared, DMAC stops the transfer after one transfer  
unit (demand transfer or peripheral interrupt start).  
Since peripheral interrupts are handled as level detection, use interrupt clear by DMA to handle the interrupts.  
Transfer requests are always accepted while other channel requests are being accepted and transfer performed.  
The channel that will be used for transfer is determined for each transfer unit after priority has been checked.  
■ Clearing Peripheral Interrupts by DMA  
This DMA has a function that clears peripheral interrupts. This function works when peripheral interrupt is  
selected as the DMA start source (when IS[4:0]=1xxxx ).  
B
Peripheral interrupts are cleared only for the set start sources. That is, only the peripheral functions set by IS[4:0]  
are cleared.  
The timing for clearing an interrupt depends on the transfer mode (See Section 4."Operation Flowcharts").  
•
•
Block/step transfer: If block transfer is selected, a clear signal is generated after one block (step) transfer.  
Burst transfer: If burst transfer is selected, a clear signal is generated after transfer is performed the specified  
number of times.  
•
Demand transfer: Since only start requests from external pins are supported in demand transfer, no clear  
signal is generated.  
■ Temporary Stopping  
DMA transfer is stopped temporary in the following cases:  
● Setting of temporary stopping by writing to the control register (Set independently for each  
channel or all channels simultaneously)  
If temporary stopping is set using the temporary stop bit, transfer on the corresponding channel is stopped until  
release of temporary stopping is set again. You can check the DSS bits for temporary stopping.  
● NMI/hold suppress level interrupt processing  
If an NMI request or an interrupt request with a higher level than the hold suppress level occurs, all channels on  
which transfer is in progress are temporarily stopped at the boundary of the transfer unit and the bus right is  
returned to give priority to NMI/interrupt processing. Transfer request accepted during NMI/interrupt processing  
are retained, initiating a wait for completion of NMI processing.  
Channels for which requests are retained restart transfer after NMI/interrupt processing is completed.  
■ Operation End/Stopping  
The end of DMA transfer is controlled independently for each channel. It is also possible to disable operation for  
all channels at once.  
● Transfer end  
If reloading is disabled, transfer is stopped, "Normal end" is displayed as the end code, and all transfer requests  
are disabled after the transfer count register becomes 0 (Clear the DENB bit of DMACA).  
If reloading is enabled, the initial value is reloaded, "Normal end" is displayed as the end code, and a wait for  
transfer requests starts after the transfer count register becomes 0 (Do not clear the DENB bit of DMACA).  
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● Disabling all channels  
If the operation of all channels is disabled with the DMA operation enable bit DMAE, all DMAC operations,  
including operations on active channels, are stopped. Then, even if the operation of all channels is enabled again,  
no transfer is performed unless a channel is restarted. In this case, no interrupt whatever occurs.  
■ Stopping Due To an Error  
In addition to normal end after transfer for the number of times specified, stopping as the result of various types of  
errors and the forced stopping are provided.  
● Transfer stop requests from peripheral circuits  
Depending on the peripheral circuit that outputs a transfer request, a transfer stop request is issued when an  
error is detected (Example: Error when data is received at or sent from a communications system peripheral).  
The DMAC, when it receives such a transfer stop request, displays "Transfer stop request" as the end code and  
stops the transfer on the corresponding channel.  
Table 3-6 Stopping due to an Error  
IS  
EIS  
Function  
Transfer stop request  
10110  
11000  
11010  
11100  
0000  
0000  
0000  
0000  
USART 0 RX *1  
USART 1 RX *1  
USART 4 RX *1  
USART 5 RX *1  
Yes  
Yes  
Yes  
Yes  
10000  
10010  
10100  
10110  
11000  
11010  
11100  
11110  
0011  
0011  
0011  
0011  
0011  
0011  
0011  
0011  
USART 0 RX *1  
USART 1 RX *1  
USART 2 RX *1  
USART 3 RX *1  
USART 4 RX *1  
USART 5 RX *1  
USART 6 RX *1  
USART 7 RX *1  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
10000  
10010  
10100  
10110  
11000  
11010  
11100  
11110  
0100  
0100  
0100  
0100  
0100  
0100  
0100  
0100  
USART 8 RX *1  
USART 9 RX *1  
USART 10 RX *1  
USART 11 RX *1  
USART 12 RX *1  
USART 13 RX *1  
USART 14 RX *1  
USART 15 RX *1  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
others  
others  
None  
*1 : A transfer stop request is issued when an error is detected  
For details of the conditions under which a transfer stop request is generated, see the specifications for each  
peripheral circuit.  
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■ Occurrence of an Address Error  
If inappropriate addressing, as shown below in parenthesis, occurs in an addressing mode, an address error is  
detected (if an overflow or underflow occurs in the address counter when a 32-bit address is specified).  
If an address error is detected, "An address error occurred" is displayed as the end code and transfer on the  
corresponding channel is stopped.  
3.10 DMAC Interrupt Control  
Independent of peripheral interrupts that become transfer requests, interrupts can also be output  
for each DMAC channel.  
■ DMAC Interrupt Control  
The following interrupts can be output for each DMAC channel:  
•
•
•
Transfer end interrupt: Occurs only when operation ends normally.  
Error interrupt: Transfer stop request due to a peripheral circuit (error due to a peripheral)  
Error interrupt: Occurrence of address error (error due to software)  
All of these interrupts are output according to the meaning of the end code.  
An interrupt request can be cleared by writing 000 to DSS2 to 0 (end code) of DMACS. Be sure to clear the end  
B
code by writing 000 before restarting.  
B
If reloading is enabled, the transfer is automatically restarted. At this point, however, the end code is not cleared  
and is retained until a new end code is written when the next transfer ends.  
Since only one end source can be displayed in an end code, the result after considering the order of priority is  
displayed when multiple sources occur simultaneously. The interrupt that occurs at this point conforms to the  
displayed end code.  
The following shows the priority for displaying end codes (in order of decreasing priority):  
•
•
Reset  
Clearing by writing 000  
B
•
•
•
•
Peripheral stop request or external pin input (DSTP) stop request  
Normal end  
Stopping when address error detected  
Channel selection and control  
■ DMA Transfer during Sleep  
•
•
The DMAC can also operate in sleep mode.  
If you anticipate operations during sleep mode, note the following:  
•
Since the CPU is stopped, DMAC registers cannot be rewritten. Make settings before sleep mode is  
entered.  
•
The sleep mode is released by an interrupt. Thus, if a peripheral interrupt is selected as the DMAC start  
source, interrupts must be disabled by the interrupt controller.  
•
If you do not want to release sleep mode with a DMAC end interrupt, disable these interrupts.  
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3.11 Channel Selection and Control  
Up to five channels can be simultaneously set as transfer channels. In general, an independent  
function can be set for each channel.  
■ Priority Among Channels  
Since DMA transfer is possible only on one channel at a time, priority must be set for the channels.  
Two modes, fixed and rotation, are provided as the priority settings and can be selected for each channel group  
(described later).  
● Fixed mode  
The order of priority is fixed by channel number, with priority decreasing from channel 0 to channel 4:  
(ch.0 > ch.1 > ch.2 > ch.3 > ch.4)  
If a transfer request with a higher priority is received during a transfer, the transfer channel becomes the channel  
with the higher priority when the transfer for the transfer unit (number set in the block size specification register x  
data width) ends.  
When higher priority transfer is completed, transfer is restarted on the previous channel.  
Figure 3-5 Timing Example in Fixed Mode  
ch0 transfer request  
ch1 transfer request  
Bus operation  
Transfer ch  
CPU  
SA DA SA DA SA DA SA DA  
ch1 ch0 ch0 ch1  
CPU  
ch0 transfer end  
ch1 transfer end  
● Rotation mode (ch.0 to ch.1 only)  
When operation is enabled, the initial states have the same order that they would have in fixed mode, but at the  
end of each transfer operation, the priority of the channels is reversed. Thus, if more than one transfer request is  
output at the same time, the channel is switched after each transfer unit.  
This mode is effective when continuous or burst transfer is set.  
Figure 3-6 Timing Example in Rotation Mode  
ch0 transfer request  
ch1 transfer request  
Bus operation  
Transfer ch  
CPU  
SA DA SA DA SA DA SA DA  
ch1 ch0 ch1 ch0  
CPU  
ch0 transfer end  
ch1 transfer end  
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■ Channel Group  
The order of priority is set as shown in the following table.  
MODE  
Priority  
ch0 > ch1  
ch0 > ch1  
Remarks  
Fixed  
−
The initial state is the top row.  
If transfer occurs for the top row, the priority  
is reversed.  
Rotation  
ch0 < ch1  
3.12 Supplement on External Pin and Internal Operation Timing  
This section provides supplementary information about external pins and internal operation tim-  
ing.  
■ Minimum Effective Pulse Width of the DREQ pin Input  
Only channels 0-3 are applicable for the MB91460 series.  
In all transfer modes for burst, step, block, and demand transfers, the minimum width required is five system  
clock cycles (5 cycles of CLKT).  
Note:  
DACK output does not indicate acceptance of DREQ input. DREQ input is always accepted if DMA is enabled  
but transfer has not started. Therefore, it is not necessary to retain DREQ input until DACK output is asserted  
(except in demand transfer mode).  
■ Negate Timing of the DREQ Pin Input when a Demand Transfer Request is Stopped  
● For 2-cycle transfer  
For a demand transfer, be sure to set an address in an external area for the transfer source, the transfer  
destination, or both.  
•
If the transfer type is external <--> external: Negate before the last sense timing of the clock in the L section of  
the external WRn pin output when accessing the transfer source for the last DMA transfer (section where  
DACK = L and WRn = L). If DREQ is negated later than this, a DMA request may be sensed, resulting in  
negation until the next transfer.  
•
If the transfer type is external <--> internal: Negate before the last sense timing of the clock in the L section of  
the external RD pin output when accessing the transfer source for the last DMA transfer (Section where DACK  
= L and RD = L). If DREQ is negated later than this, a DMA request may be sensed, resulting in negation until  
the next transfer  
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Chapter 26 DMA Controller  
3.DMA Controller (DMAC) Operation  
Figure 3-7 Negate timing example of the DREQ pin input for 2-cycle external transfer --> internal transfer  
Bus operation  
Area  
CPU  
SA DA SA DA  
*1 *2 *1 *2  
CPU  
*1: External  
SA DA SA DA  
*1 *2 *1 *2  
*2: Internal  
External D bus  
DACK  
DEOP  
RD  
WR  
DREQ (H level)  
•
If the transfer is internal <--> external: Negate before the last sense timing of the clock in the L section of the  
external WRn pin output when accessing the transfer source for the last DMA transfer (Section of DACK =  
1and WRn = L). If DREQ is negated later than this, a DMA request may be sensed, resulting in negation until  
the next transfer.  
● For fly-by (read/write) transfer  
For a demand transfer, be sure to set an address in an external area for the transfer destination.  
•
For fly-by (read) transfer: After the IOWR pin output for the last DMA transfer goes to the H level, negate  
DREQ while the external RD pin output is at the L level. (section where DACK=L & RD=L). If DREQ is negated  
later than this, the negation may continue until the next transfer.  
•
For fly-by (write) transfer: After the external WRn pin output for the last DMA transfer goes to the H level,  
negate DREQ while IORD is at the L level. (section where DACK=L & RD=L). If DREQ is negated later than  
this, the negation may continue until the next transfer.  
Figure 3-8 Negate timing example of the DREQ pin input for fly-by (write) transfer  
Bus operation  
*1: External  
*2: Internal  
Area  
*1  
*2  
*1  
*2  
*1  
*2  
*1  
*2  
External D bus  
DACK  
DEOP  
RD  
WR  
DREQ (H level)  
■ Timing of the DREQ Pin Input for Continuing Transfer over the Same Channel  
● For burst, step, block, and demand transfers  
Operation in which transfer is continued over the same channel by the DREQ pin input cannot be guaranteed. If  
DREQ is reasserted at the fastest timing to clear requests retained internally after the transfer ends, at least one  
system clock cycle (one CLK output cycle) is provided to detect transfer requests for other channels. If, as a  
result, a transfer request for another channel with a higher priority is detected, transfer on that channel will be  
started.  
370  
Chapter 26 DMA Controller  
3.DMA Controller (DMAC) Operation  
Even if DREQ is reasserted earlier, it is ignored because the transfer has not been completed. If no transfer  
requests for other channels occur, transfer over the same channel is restarted by reasserting DREQ when the  
DACK pin output is asserted.  
■ Timing of DACK Pin Output  
The DACK output of this DMAC indicates that transfer with respect to an accepted transfer request is being  
performed.  
The output of DACK is basically synchronized with the address output of external bus access timing. To use  
DACK output, it is necessary to enable the DACK output with a port.  
■ Timing of the DEOP Pin Output  
•
The DEOP output of this DMA indicates that DMA transfer for the specified number of times of the accepted  
channel has been completed.  
•
DEOP output is output when access to an external area of the last transfer block starts. Thus, if any value  
other than 1 is set (block transfer mode) as the block size, DEOP is output when the last data of the last block  
is transferred. In this case, the acceptance of the next DREQ is already started even during transfer (before  
DEOP output) if the DACK pin output is asserted.  
•
The DEOP output is synchronized with RD and WRn of external bus access timing. However, if the transfer  
source/transfer destination is internal access, DEOP is not output. To use DEOP output, it is necessary to  
enable the DEOP output using the port register.  
■ If an External Pin Transfer Request is Reentered During Transfer  
● For burst, step, and block transfers  
While the DACK signal is asserted within the DMAC, the next transfer request, if it is entered, is disabled.  
However, since operation of the external bus control unit and operation of the DMAC are not completely  
synchronous, the circuit must be initialized to create DREQ pin input using DACK and DEOP output to enable  
transfer requests by using DREQ input.  
● For a demand transfer  
If reloading of the transfer count register is specified when transfer for as many transfers as specified has been  
completed, another transfer request is accepted.  
■ If Another Transfer Request Occurs During Block Transfer  
No request is detected before the transfer of the specified blocks is completed. At the block boundaries, transfer  
requests accepted at that time are evaluated and then transfer on the channel with the highest priority is  
performed.  
■ Transfer Between External I/O and External Memory  
As targets of transfer by the DMAC, external I/O and external memory are not distinguished. Specify an external  
I/O as a fixed external address.  
To perform fly-by transfer, set the address of external memory in the transfer destination address register. For  
external I/O, use DACK output and the signal decoded by the read signal RD or write signal WRn pin.  
371  
Chapter 26 DMA Controller  
3.DMA Controller (DMAC) Operation  
■ AC Characteristics of DMAC  
DREQ pin input, DACK pin output, and DEOP pin output are provided as the external pins related to the DMAC,.  
Output timing is synchronized with external bus access (refer to the AC standard for the DMAC).  
372  
Chapter 26 DMA Controller  
4.Operation Flowcharts  
4. Operation Flowcharts  
This section contains operation flowcharts for the following transfer modes:  
• Block transfer  
• Burst transfer  
• Demand transfer  
■ Block Transfer  
Figure 4-1"Operation Flowchart for Block Transfer" shows the flowchart for block transfer.  
Figure 4-1 Operation Flowchart for Block Transfer  
DMA stop  
DENB=>0  
DENB=1  
Activation request  
wait  
Reload enable  
Activation request  
Load the initial address,  
transfer count, and number  
of blocks  
Calculate the address for  
transfer source address access  
One-time access for fly-by  
Calculate the address for transfer  
destination address access  
Number of blocks - 1  
BLK=0  
Only when the peripheral  
interrupt activation source  
is selected  
Transfer count - 1  
Write back the address,  
transfer count, and  
number of blocks  
Interrupt clear  
DTC=0  
Interrupt cleared  
DMA interrupted  
DMA transfer end  
Block transfer  
- Can be activated by all activation sources (selection).  
- Can access to all areas.  
- The number of blocks can be set.  
- Interrupt clear is issued when transfer of the specified  
number of blocks is completed.  
- The DMA interrupt is issued when transfer for the number  
of times specified is completed.  
■ Burst Transfer  
Figure 4-2"Operation Flowchart for Burst Transfer" shows the operation flowchart for burst transfer.  
373  
   
Chapter 26 DMA Controller  
4.Operation Flowcharts  
Figure 4-2 Operation Flowchart for Burst Transfer  
DMA stop  
DENB=1  
DENB=>0  
Activation request  
wait  
Reload enable  
Load the initial address,  
transfer count, and  
number of blocks  
Calculate the address for  
transfer source address access  
One-time access for fly-by  
Calculate the address for transfer  
destination address access  
Number of blocks - 1  
BLK=0  
Transfer count - 1  
DTC=0  
Write back the address,  
transfer count, and number  
of blocks  
Only when the peripheral interrupt  
activation source is selected  
Interrupt clear  
Interrupt cleared  
DMA interrupted  
DMA transfer end  
Burst transfer  
- Can be activated by all activation sources (selection).  
- Can access to all areas.  
- The number of blocks can be set.  
- Interrupt clear and the DMA interrupt are issued when  
transfer for the number of times specified is completed.  
■ Demand Transfer  
Figure 4-3"Operation Flowchart for Demand Transfer" shows the operation flowchart for demand transfer.  
374  
 
Chapter 26 DMA Controller  
4.Operation Flowcharts  
Figure 4-3 Operation Flowchart for Demand Transfer  
DMA stop  
DENB=>0  
DENB=1  
None  
Activation request  
wait  
Reload enable  
Activation request  
Load the initial address,  
transfer count, and  
number of blocks  
Calculate the address for  
transfer source address access  
One-time access for fly-by  
Calculate the address for transfer  
destination address access  
Number of transfer - 1  
Write back the address,  
transfer count, and number  
of blocks  
DTC=0  
Only when the peripheral interrupt  
activation source is selected  
Interrupt cleared  
Interrupt clear  
DMA transfer end  
DMA interrupted  
Demand transfer  
- Only requests (level detection) from the external pin (DREQ) are accepted. Activation by  
other sources is disabled.  
- Access to an external area is required (since access to an external area becomes the  
next activation source).  
- The number of blocks is always 1, regardless of the settings.  
- Interrupt clear and the DMA interrupt are issued when transfer for the number of times  
specified is completed.  
375  
 
Chapter 26 DMA Controller  
5.Data Bus  
5. Data Bus  
This section shows the flow of data during 2-cycle transfer and fly-by transfer.  
■ Flow of Data During 2-Cycle Transfer  
Figure 14.5-1 shows examples of six types of transfer during 2-cycle transfer.  
Figure 5-1 Examples of 2-Cycle Transfer (Continued on next page)  
External area => external area transfer  
MB91460  
MB91460  
DMAC  
DMAC  
Write cycle  
I-bus  
Read cycle  
I-bus  
X-bus  
X-bus  
Bus controller  
Data buffer  
Bus controller  
D-bus  
D-bus Data buffer  
F-bus  
RAM  
F-bus  
IO  
RAM  
IO  
External area => internal RAM area transfer  
MB91460  
MB91460  
DMAC  
DMAC  
Read cycle  
I-bus  
Write cycle  
I-bus  
X-bus  
X-bus  
Bus controller  
Data buffer  
Bus controller  
Data buffer  
D-bus  
D-bus  
F-bus  
RAM  
F-bus  
RAM  
IO  
IO  
External area => built-in I/O area transfer  
MB91460  
MB91460  
DMAC  
DMAC  
Read cycle  
I-bus  
Write cycle  
I-bus  
X-bus  
X-bus  
Bus controller  
D-bus Data buffer  
Bus controller  
Data buffer  
D-bus  
F-bus  
RAM  
F-bus  
RAM  
IO  
IO  
376  
 
Chapter 26 DMA Controller  
5.Data Bus  
Built-in I/O area => internal RAM area transfer  
MB91460  
MB91460  
DMAC  
DMAC  
Write cycle  
I-bus  
Read cycle  
I-bus  
X-bus  
X-bus  
Bus controller  
Data buffer  
Bus controller  
Data buffer  
D-bus  
D-bus  
F-bus  
RAM  
F-bus  
RAM  
IO  
IO  
Internal RAM area => external area transfer  
MB91460  
MB91460  
DMAC  
DMAC  
Read cycle  
I-bus  
Write cycle  
I-bus  
X-bus  
X-bus  
Bus controller  
Data buffer  
Bus controller  
Data buffer  
D-bus  
D-bus  
F-bus  
RAM  
F-bus  
RAM  
IO  
IO  
Internal RAM area => built-in I/O area transfer  
MB91460  
MB91460  
DMAC  
DMAC  
Write cycle  
I-bus  
Read cycle  
I-bus  
X-bus  
X-bus  
Bus controller  
Data buffer  
Bus controller  
Data buffer  
D-bus  
D-bus  
F-bus  
RAM  
F-bus  
RAM  
IO  
IO  
■ Flow of Data During Fly-By Transfer  
Figure 5-2"Examples of Fly-By Transfer" shows examples of two types of transfer during fly-by transfer.  
377  
Chapter 26 DMA Controller  
5.Data Bus  
Figure 5-2 Examples of Fly-By Transfer  
Fly-by transfer (memory to I/O)  
MB91460  
DMAC  
Memory read by RD or CSn  
Read cycle  
I-bus  
X-bus  
Bus controller  
Data buffer  
D-bus  
F-bus  
RAM  
I/O write by RD or DACK  
I/O  
Fly-by transfer (I/O to memory)  
MB91460  
DMAC  
Memory write by WR or CSn  
Read cycle  
I-bus  
X-bus  
Bus controller  
Data buffer  
D-bus  
I/O read by WR or DACK  
F-bus  
RAM  
I/O  
378  
 
Chapter 26 DMA Controller  
6.DMA External Interface  
6. DMA External Interface  
This section provides operation timing charts for the DMA external interface.  
■ DMA External Interface Pins  
DMA channels 0-3 have the following DMA-dedicated pins (DREQ, DACK, and DEOP):  
•
•
•
•
•
DREQ: DMA transfer request input pin for demand transfer. A transfer is requested with an input.  
DACK: This pin becomes active (L output) when DMA accesses an external area via the external interface.  
DEOP: This pin becomes active (L output) in synchronization with the last access to complete DMA transfer.  
IORD: This signal becomes active when the direction I/O -> memory is selected for fly-by transfer.  
IOWR: This signal becomes active when the direction memory -> I/O is selected for fly-by transfer.  
Note:  
Refer to 4.10 "DMA Access Operation" for the operation example of DMA external interface.  
6.1 Input Timing of the DREQx Pin  
The DREQx pin is a DMA start request signal. If the pin is also used as a port, enable the DREQ  
input using the PFR register. This section shows the input timing of the DREQx pin.  
■ Timing of Transfer Other Than Demand Transfer  
For transfer other than demand transfer, set the DMA start source to edge detection. Although there is no rule for  
rise/fall timing, use three or more clock cycles as the holding time the DREQ signal. To make another transfer  
request, enter the request after the DMA transfer is completed (make a request after DEOP is output).  
If a request is made before DEOP is output, it may be ignored.  
Figure 6-1"Timing Chart for Transfer Other Than the Demand Transfer" shows the timing chart for transfer other  
than demand transfer.  
Figure 6-1 Timing Chart for Transfer Other Than the Demand Transfer  
When a DREQ edge is requested (for 2-cycle transfer)  
MCLK  
DREQ  
A24 to 0  
RD  
#RD1  
#WR1  
#RD2  
#WR2  
WR  
DEOP  
CPU operation  
DMA transfer  
CPU  
3 or more cycles  
The next request must be after DEOP output  
379  
   
Chapter 26 DMA Controller  
6.DMA External Interface  
■ Timing of Demand Transfer  
For demand transfer, set the DMA start source to level detection. Although there is no rule for starting,  
synchronize with RD/WRn of the DMA transfer when stopping a transfer. The sense timing is the rise of MCLK in  
the final external access.  
Figure 6-2"Timing Chart for Demand Transfer" shows the timing chart for demand transfer.  
Figure 6-2 Timing Chart for Demand Transfer  
When a DREQx level is requested (for 2-cycle transfer)  
MCLK  
DREQ  
A24 to 0  
RD  
#RD1  
#WR1  
#RD2  
#WR2  
WR  
CPU operation  
DMA transfer  
CPU  
Sense point of the 3rd transfer request  
Note:  
In this case, because 2-cycle transfer is used and the transfer source and transfer destination are an external  
area, negate from the fall of #RD2 to before the final MCLK rise of #WR2 to stop the two DMA transfer  
operations.  
6.2 FR30 Compatible Mode of DACK  
FR30 compatible mode of DACK makes the DACK timing identical to the timing of DMA used in  
FR30 series devices. This section provides the timing charts for the DACK pin in FR30 compat-  
ible mode for the following examples of transfer mode setting:  
• 2-cycle transfer mode  
• Fly-by transfer mode  
■ Transfer Mode Settings  
Set the transfer mode using the PFR register corresponding to the DACK pin.  
When setting PFR, match the transfer mode (2-cycle transfer/fly-by transfer) of the corresponding DMA channel.  
Note:  
If 2-cycle transfer is set in FR30 compatible mode, the transfer is synchronized with RD or WR/WRn. To use  
WR, enable WR by setting 0x1x for TYPE3-0 of the external interface ACR register.  
B
● 2-cycle transfer mode  
Figure 6-3"Timing Chart in 2-Cycle Transfer Mode" shows the timing chart in 2-cycle transfer mode.  
380  
 
Chapter 26 DMA Controller  
6.DMA External Interface  
Figure 6-3 Timing Chart in 2-Cycle Transfer Mode  
RD  
DQMU/L  
WR/WRn  
*
DACK (AKxx=111 )  
B
Same timing as the chip select  
2-cycle transfer setting disabled  
*
*
DACK (AKxx=001 )  
B
DACK (AKxx=010 )  
B
*
*
DACK (AKxx=011 )  
B
DACK (AKxx=100 )  
B
*
*
DACK (AKxx=101 )  
B
DACK (AKxx=110 )  
B
* : AKxx is the setting value in the PFR register that corresponds to the DMA channel.  
● Fly-by transfer mode  
Figure 6-4"Timing Chart in Fly-By Transfer Mode" shows the timing chart in fly-by transfer mode.  
Figure 6-4 Timing Chart in Fly-By Transfer Mode  
RD  
DQMU/L  
WR/WRn  
IORD  
IOWR  
*
DACK(AKxx=111 )  
Same timing as the chip select  
B
*
*
DACK(AKxx=001 )  
B
DACK(AKxx=010 ) Fly-by transfer setting disabled  
B
*
DACK(AKxx=011 ) Fly-by transfer setting disabled  
B
*
DACK(AKxx=100 ) Fly-by transfer setting disabled  
B
*
DACK(AKxx=101 ) Fly-by transfer setting disabled  
B
*
DACK(AKxx=110 ) Fly-by transfer setting disabled  
B
Memory to I/O  
I/O to memory  
Memory to I/O I/O to memory  
* : AKxx is the setting value in the PFR register that corresponds to the DMA channel.  
381  
   
Chapter 26 DMA Controller  
6.DMA External Interface  
382  
Chapter 27 Delayed Interrupt  
1.Overview  
Chapter 27 Delayed Interrupt  
1. Overview  
The delayed interrupt, or the delayed interrupt module is used to generate an interrupt used for task switching.  
Delay interrupt  
control circuit  
Software request  
Interrupt request (#63)  
2. Features  
• Type: Interrupt request bit (There is no interrupt request enable bit)  
• Quantity: 1  
• Other:  
• The software generates/releases interrupt request.  
• Real time OS uses the delayed interrupt for task switching.  
3. Configuration  
Figure 3-1 Configuration Diagram  
Delay interrupt  
Delay interrupt control bit  
DLYI  
Read  
DICR: bit 0  
Write  
0
1
0
1
Without interrupt  
With interrupt  
Delay interrupt release  
Delay interrupt request  
Delay interrupt control circuit  
Interrupt request (#63)  
Figure 3-2 List of Registers  
383  
       
Chapter 27 Delayed Interrupt  
4.Register  
4. Register  
4.1 DICR: Delayed Interrupt Control Register  
This register controls to generate/clear the delayed interrupt.  
• DICR: Address 0038h (Access: Byte)  
7
–
–
6
–
–
5
–
–
4
–
–
3
–
–
2
–
–
1
–
–
0
DLYI  
0
bit  
Initial value  
Attribute  
RX/  
WX  
RX/WX RX/WX RX/WX RX/WX  
RX/WX RX/WX  
R/W  
(Refer to “Meaning of Bit Attribute Symbols (Page No.10)” for the attributes.)  
• Bit7-1: Undefined: Writing does not affect operation. The read value is undefined.  
• Bit0: Delayed interrupt control bit  
DLYI  
Read operation  
Write operation  
0
1
No delayed interrupt request  
Delayed interrupt request  
Delayed interrupt request clear  
Delayed interrupt request generation  
5. Operation  
Delayed interrupt service  
Preference interrupt  
(5)  
(4)  
Delay  
Delay interrupt  
(6) (7)  
Task B  
OS  
Task A  
(1)  
(2)  
(3)  
A task dispatch request is generated.  
Setting for the dispatch destination (Delay return destination)  
Setting for the delay interrupt request (Generating)  
(1) In OS, a request for task B dispatch is generated  
(2) OS sets the delayed interrupt return destination (dispatch destination)  
(3) OS sets the delayed interrupt (delayed interrupt generation)  
(4) When OS returns, the interrupt with the highest priority sequence takes place, because an interrupt  
service is prohibited in OS  
(5) When the interrupt with the highest priority is completed, delayed interrupt takes place  
(6) In delayed interrupt, delayed interrupt is released  
(7) Returned from the delayed interrupt (dispatched to task B)  
384  
   
Chapter 27 Delayed Interrupt  
6.Setting  
6. Setting  
Table Setting required for the delayed interrupt generation/clear  
Table 6-1 Setting required for the delay interrupt generation/clear  
Setting  
Setting register  
Setting method*  
Refer to “Chapter 24 Interrupt Con-  
trol (Page No.311)”  
Vector for delay interrupt  
Delayed interrupt setting.  
Refer to 7.1  
Delayed interrupt control register  
(DICR)  
Refer to 7.2  
Generating interrupt request/Releasing interrupt request  
*: Refer to the number for the setting method.  
7. Q & A  
7.1 What are interrupt-associated registers?  
Setting for the delay interrupt vector and interrupt level  
The relationship between the delay interrupt level and the delay interrupt vector is shown in the following table.  
Refer to “Chapter 24 Interrupt Control (Page No.311)” for more information on the interrupt level and interrupt  
vector.  
Interrupt vector (default)  
Interrupt level setting bit (ICR[4:0])  
#63  
Interrupt level register (ICR23)  
Address: 00457h  
Address: 0FFF00h  
The interrupt request bit (DICR.DLYI) cannot automatically be released, and it should be released by the  
software before returning from an interrupt service. (“0” is written for DLYI bit)  
Remark: For REALOS compatibility reasons, ICR23 and ICR47 can be exchanged by setting the REALOS  
compatibility bit (addr 0x0C03 : IOS[0]) if necessary.  
7.2 How is the interrupt request generated/cleared?  
The delayed interrupt request bit (DICR.DLYI) performs this function.  
Interrupt request enable bit (DLYI)  
Clearing an interrupt request  
Generating an interrupt request  
Sets the value to “0”  
Sets the value to “1”  
The delayed interrupt does not have an interrupt request enable bit.  
8. Caution  
• The delay interrupt request bit is the same as general interrupt request flags. It should be used to clear  
delayed interrupt request bit in an interrupt routine in addition to switching tasks.  
• The delayed interrupt function can use real time OS (REALOS). As a result, the delayed interrupt function is  
prohibited in a piece of user software when using real time OS.  
385  
     
Chapter 27 Delayed Interrupt  
8.Caution  
386  
Chapter 28 Bit Search  
1.Overview  
Chapter 28 Bit Search  
1. Overview  
The bit search module is used to detect 0, 1 or changing position for data written in specific registers.  
Detection  
circuit  
0-position register  
(0-position,  
1-pos. and  
changing  
position)  
Result register  
1-position register  
Changing-pos. register  
2. Features  
• Function: Detects the first changing position by scanning data written in data register from MSB to LSB.  
• 0 detection  
• 1 detection  
Detects the first ‘0’ changing position.  
Detects the first ‘1’ changing position.  
• Changing position detectionDetects the position where data first changes.  
• Quantity: 1  
• Other: Can read internal data.  
(This can be used to restore the previous state when it is used for bit search during interrupt service or  
handler.)  
387  
     
Chapter 28 Bit Search  
3.Configuration  
3. Configuration  
Figure 3-1 Configuration Diagram  
Detection mode selection  
Bit search  
Lowest four bits  
of the address  
Operation selection  
for BSD0/BSD1/BSDC  
Address decoder  
0-detection  
1-detection  
0000  
0100  
0-/1-/Changing-position-detection  
data register  
1000  
Changing-position-detection  
Write only  
BSD0/ BSD1/ BSDC  
Run only  
Detection result  
Detection circuit  
(0-/1-/Changing-positions)  
Detection data (BSD1)  
BSRR  
Figure 3-2 List of Registers  
Bit search  
388  
 
Chapter 28 Bit Search  
4.Register  
4. Register  
4.1 BSD0: 0 Detection Register / BSD1:1 Detection Register / BSDC: Changing position  
Detection Data Register  
This is a register for setting the bit search detection data.  
• BSD0: Address 03F0 (Access: Word)  
H
• BSD1: Address 03F4 (Access: Word)  
H
• BSDC: Address 03F8 (Access: Word)  
H
31  
0
0
0
bit  
BSD0  
Indefinite  
W
Initial value  
Attribute  
31  
31  
bit  
BSD1  
Indefinite  
R,W  
Initial value  
Attribute  
bit  
BSDC  
Indefinite  
W
Initial value  
Attribute  
(For the attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• Write data used to detect 0, 1 and changing position in each of the registers BSD0, BSD1 and BSDC.  
• The result is stored in the detection result register BSRR.  
• During 0 detection, the position where “0” is first detected is stored for data written in the order of  
MSB(bit31) to LSB(bit0).  
• During 1 detection, the position where “1” is first detected is stored for data written in the order of  
MSB(bit31) to LSB(bit0).  
• During change position detection, the position where a value different from MSB(bit31) is first detected is  
stored for data written in the order of bit30 to LSB(bit0).  
• The register BSD0 used for 0 detection and the BSRC register used for changing position detection are  
write-only. The value during read operation is indefinite.  
• Data saved in the bit search can be read if the register BSR1 used to detect 1 is read.  
Previous detection result can be restored by re-writing previously read data in the BSR1 used for detecting  
1. This applies to the processes for the 0 detection and the changing position detection.This function can be  
used to restore a specific state when using a bit search in processing such as interrupt handler.  
389  
 
Chapter 28 Bit Search  
4.Register  
4.2 BSRR: Detection Result Register  
This register is used to read a bit search result.  
• BSRR: Address 03FC (Access: Word)  
H
31  
0
bit  
BSRR  
Initial  
value  
Indefinite  
R
Attribute  
(For the attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• Detection result for data written in the 0 detection register BSD0, the 1-detection register BSD1 and the  
changing-position-detection register BSDC can be read. Data last written can be read. However, the type of  
result cannot be identified: Information on 0 detection,1 detection or changing position detection is not  
included.  
A 0 can be read at detection position bit31(MSB), and continues reading 31 at detection position bit0(LSB)  
by adding 1 at the next position toward bit0(LSB). A value of 32 is read when not detected.  
• The detection result register is read-only, and a write operation is invalid.  
390  
Chapter 28 Bit Search  
5.Operation  
5. Operation  
5.1 Zero detection  
11111111111 111 11 2  
Bit position from MSB  
0123456 789 ABCDEF0123456789ABCDEF 0  
1111111 111 000 000 0000000000 000 000  
>>>>>>>>>> 0  
Data  
Scan  
AH (10 Decimal  
)
Detection result  
(1) Bit position from MSB  
(2) Written data (Starts to search once data is written.)  
(3) Detects “0” by scanning from MSB.  
(4) Detected bit position  
(5) Detection result  
If ‘0’ does not exist (That is, numeric value is FFFFFFFF ), ‘32’ is returned as detection result.  
H
• Execution example  
Write data  
11111111111111111111000000000000 (FFFFF000 )  
Read value  
Æ
(Decimal notation)  
20  
B
H
11111000010010011110000010101010 (F849E0AA )  
Æ
Æ
Æ
5
1
32  
B
H
10000000000000101010101010101010 (8002AAAA )  
B
H
11111111111111111111111111111111 (FFFFFFFF )  
B
H
5.2 One Detection  
1111111111 111 111 2  
Bit position from MSB  
Data  
Scan  
0123456789 ABCDEF0123456789ABCDEF 0  
0000000000 000 000 001111111111 11 11  
>>>>>>>>>>>>>>>>>>1  
12H (18Decimal  
)
Detection result  
(1) Bit position from MSB  
(2) Written data (Detection operation starts once data is written.)  
(3) Detect “1” scan starting with the MSB.  
(4) Detected bit position  
(5) Detection result  
If ‘1’ does not exist (That is, if numeric value is 00000000 ), value of ‘32’ is returned as detection result.  
H
• Execution example  
Write data  
00100000000000000000000000000000 (20000000 )  
Read value  
Æ
(Decimal notation)  
2
B
H
00000001001000110100010101100111 (01234567 )  
Æ
Æ
Æ
Æ
7
B
H
00000000000000111111111111111111 (0003FFFF )  
14  
31  
32  
B
H
00000000000000000000000000000001 (00000001 )  
B
H
00000000000000000000000000000000 (00000000 )  
B
H
391  
 
Chapter 28 Bit Search  
5.Operation  
5.3 Changing Position Detection  
11111111111 11 111 2  
0123456789 ABCDEF0123456789ABCDEF 0  
Bit position from MSB  
0000000000 00 000 111000000000 00 000  
Data  
Scan  
>>>>>>>>>>>>>>>*  
FH (15Decimal  
)
Detection result  
(1) Bit position from MSB  
(2) Written data (Detection starts once data is written.)  
(3) Detects the changing position by scanning from MSB.  
(4) Detected bit position  
(5) Detection result  
A value of ‘32’ is returned as detection result if changing position does not exist.  
A value of ‘0’ is not returned as detection result for changing position detection.  
• Execution example  
Write data  
00100000000000000000000000000000 (20000000 )  
Read value  
Æ
(Decimal notation)  
2
B
H
00000001001000110100010101100111 (01234567 )  
Æ
Æ
Æ
Æ
Æ
Æ
Æ
Æ
7
B
H
00000000000000111111111111111111 (0003FFFF )  
14  
31  
32  
20  
5
B
H
00000000000000000000000000000001 (00000001 )  
B
H
00000000000000000000000000000000 (00000000 )  
B
H
11111111111111111111000000000000 (FFFFF000 )  
B
H
11111000010010011110000010101010 (F849E0AA )  
B
H
10000000000000101010101010101010 (8002AAAA )  
1
32  
B
H
11111111111111111111111111111111 (FFFFFFFF )  
B
H
Table 5-1 The Relationship Between the Bit Position and the Value to be Returned (Decimal Notation)  
Detected  
bit position  
Return  
value  
Detected  
bit position  
Return  
value  
Detected  
bit position  
Detected  
bit position  
Return value  
Return value  
31  
30  
29  
28  
27  
26  
25  
24  
0
1
2
3
4
5
6
7
23  
22  
21  
20  
19  
18  
17  
16  
8
15  
14  
13  
12  
11  
10  
9
16  
17  
18  
19  
20  
21  
22  
23  
7
24  
25  
26  
27  
28  
29  
30  
31  
32  
9
6
10  
11  
12  
13  
14  
15  
5
4
3
2
1
8
0
Nonexistent  
392  
Chapter 28 Bit Search  
6.Setting  
6. Setting  
Table 6-1 Settings Required for “Zero” Position Detection  
Setting  
Setting  
Setting register  
*
method  
Data write & scan start  
Converted value read  
“Zero” position detection data register (BSD0)  
Detection result register (BSRR)  
Refer to 7.1.  
Refer to 7.2.  
*: For detailed description contents, refer to the reference destination number.  
Table 6-2 Setting Required for Using “One” Position Detection  
Setting  
Setting  
Setting register  
*
method  
Data write & scan start  
Converted value read  
“One” position detection data register (BSD1)  
Detection result register (BSRR)  
Refer to 7.1.  
Refer to 7.2.  
*: For detailed description contents, refer to the reference destination number.  
Table 6-3 Setting Required for Using Changing Position Detection  
Setting  
Setting  
Setting register  
*
method  
Data write & scan start  
Converted value read  
Changing position detection data register (BSDC)  
Detection result register (BSRR)  
Refer to 7.1.  
Refer to 7.2.  
*: For detailed description contents, refer to the reference destination number.  
393  
 
Chapter 28 Bit Search  
7.Q & A  
7. Q & A  
7.1 How is data written?  
Writes data with the detection data registers (BSD0, BSD1, BSDC).  
Operation mode  
Detection data register  
“Zero” position detection write  
“One” position detection write  
Changing position detection write  
Writes data in (BSD0)  
Writes data in (BSD1)  
Writes data in (BSDC)  
7.2 How is scanning started?  
Scanning is started once data is written in the detection data registers (BSD0, BSD1, BSDC).  
7.3 How is a result read?  
The detection result register (BSRR) is read.  
7.4 How is the previous bit search state restored?  
The following restoration processes are performed.  
If you need to restore the previous bit search state after a bit search has been executed in an interrupt  
handler.  
1) Reads data from the one detection data register, and saves the contents. (evacuation)  
2) The Bit search is used.  
3) Writes data evacuated in Item 1) in the one detection data register. (restoration)  
Using the above procedures, the value to be read next from the detection result register is the one that was  
written in the bit search executed in 1) or before.  
The bit search state can be correctly restored using the above procedures even if the 0-detection, 1-detection  
or changing-position-detection data register has been written last.  
394  
   
Chapter 28 Bit Search  
8.Caution  
8. Caution  
The following are the remarks on using the bit search module.  
• The macros are for REALOS(OS), and the user cannot use them when using REALOS.  
• If the relevant detection is not found, a detection result of 32(decimal), 10(hexadecimal) or 10000(binary) is  
returned.  
• A value of “0” is not returned for the changing position detection.  
• The data registers (0-detection/1-detection/ changing-position-detection) is a write-only, and accessed by  
word.  
However, the 1-detection read address is assigned to an internal data register for restoration so that you can  
restore previous bit search state. (Refer to “7.3 How is a result read? (Page No.394)”.)  
• The 0-detection register BS0, 1-detection register BSD1 and changing-position-detection register BSDC are  
included in one register in terms of the structure. The operation is selected with the lowest four bits of the  
accessing address.  
395  
 
Chapter 28 Bit Search  
8.Caution  
396  
Chapter 29 MPU / EDSU  
1.Overview  
Chapter 29 MPU / EDSU  
1. Overview  
Memory Protection Unit (MPU) and Embedded Debug Support Unit (EDSU) for MB91460 series.  
Remark: The MPU/EDSU module features a clock disable function. For enabling the MPU/EDSU module it  
is necessary to set the EDSUEN bit in the CSCFG register. See chapter “CSCFG: Clock Source Configura-  
tion Register (Page No.196)” for further information.  
The features are scalable in units of ’Comparator Groups’. The number of this Groups can be defined from one to  
eight. Features of one Comparator Group are listed below:  
•
A total number of 4 Breakpoints, could be programmed to:  
—
—
—
—
4 Instruction Address Breakpoints  
4 Operand Address Breakpoints (programmable on datasize and access type)  
2 Operand Address Breakpoints and 2 Instruction Address Breakpoints  
2 Operand Address Breakpoints and 2 Data Value Breakpoints  
•
•
2 Masks possible to assign (reduces the number of breakpoints)  
2 Range Functions  
•
•
Break Trigger programmable on resource interrupts  
MPU functionality  
—
—
—
User and SuperVisor permission for read/write/execute  
Default permissions for the whole MCU address range  
Permission definition for two address ranges per Comparator Group  
(8 Groups result in 16 MPU Channels)  
—
—
—
—
Can detect DMA accesses on the D-Bus and Resource address regions  
Register set is locked in User mode  
Dynamic configuration possible, privileged configuration with INT #5 is not interruptible  
A permission violation causes an MPUPV trap  
•
•
Capture register for Instruction Address and Operand Address (for MPU and Operand Break)  
Capture information for MPU channel index, DMA flag, Operand Size and Access Type  
397  
   
Chapter 29 MPU / EDSU  
2.Features  
2. Features  
One Comparator Group offers up to 4 Breakpoints. One Group consists of two full-featured range comparators with  
the option to use two point registers as mask information. The following features could be partially mixed-up:  
4 Instruction Address Breakpoints  
Up to 4 instruction address breakpoints can be defined.  
Two instruction breakpoints can be masked. The other two registers can operate as mask registers then. Also mask-  
able is a break address range made with two points and one mask register.  
Two absolute address ranges for instruction breakpoints can be defined where 2 or 4 out of 4 instruction breakpoint  
registers are assigned for the range.  
4 Operand Address Breakpoints  
Up to 4 operand address breakpoints can be defined.  
Two operand breakpoints can be masked. The other two registers can operate as mask registers then. Also mask-  
able is a break address range made with two points and one mask register.  
Two absolute address ranges for operand breakpoints can be defined where 2 or 4 out of 4 operand breakpoint  
registers are assigned for the range.  
Operand breaks can be selected for datasizes: byte, halfword and word on access types: read, read-modify-write  
and write.  
2 Operand Data Value Breakpoints  
Up to 2 operand data value breakpoints can be defined.  
The definition of one data value range is possible.  
One data value breakpoint can be masked by defining the other point as mask register.  
The Operand Address and Data Value Breakpoints can be switched to a combined trigger condition.  
Memory protection  
Two channels/ranges could be defined to operate in memory protection mode.  
Possible is the protection of two Operand Address ranges, two Instruction Address Ranges or a combination of one  
Operand and one Instruction Address range.  
Read/write or execute permissions could be defined for each channel, both for the normal User and the SuperVisor  
mode.  
398  
 
Chapter 29 MPU / EDSU  
3.Break Functions  
3. Break Functions  
3.1 Instruction address break  
The instruction address point break is the most basic break that occurs when an instruction is fetched at the address  
specified by the break address data registers BAD[3:0]. Setting the CTC[1:0] bits of the control register BCR0 to ’00’  
provides this mode. The bits EP[3:0] in BCR0 enable the break points.  
Up to 4 instruction breakpoints from channels 0 to 3 can be set. All instruction break events are ORed into instruction  
break exception requests to the CPU.  
2 of the break address registers can operate as mask registers (BAD0, BAD2) for masking the instruction address  
which is being fetched. Mask register BAD0 can be assigned either to BAD1 (same channel) or BAD2/3 (opposite  
channel), mask register BAD2 can be assigned either to BAD3 or BAD0/1.  
Normally Instruction break address and mask information reside in the same channel. So BAD3 contains the in-  
struction break address and BAD2 the address mask information. The channel is enabled with EP3. The same ap-  
plies for channel BAD1 (address), BAD0 (mask) and EP1 (enable).  
But some cases require enabling point 2 (EP2) or the range function (ER1). Then BAD2 holds Instruction Address  
information and could not carry the address mask. In that cases (when EP2 or ER1 are set) the mask information  
is taken from the opposite BAD0 register. The same applies for EP0 and ER0 - which enables the use of the oppo-  
site BAD2 register for the mask information.  
Example:  
CTC  
EP1  
00  
Type: Instruction Address Break  
Enable break point address BAD1  
Set mask BAD0 for break address BAD1  
Set break address  
1
1
EM0  
BAD1  
BAD0  
0x12345678  
0x00000FFF  
Set break mask  
Break occurs at 0x12345000 to 0x12345FFF  
On break at BAD[3:0] the respective flags BD[3:0] in the break interrupt request register BIRQ will be set to ’1’. They  
have to be reset by software in the instruction break routine.  
Channels 0 and 1 (BAD0, BAD1) can be set up to function as address range match. Setting the ER0 bit of the control  
register BCR0 to ’1’ provides this mode. BAD0 is the lower address and BAD1 is the upper address for address  
comparison. In this mode the mask register BAD2 will mask both channels 0 and 1, if the mask feature is enabled  
by EM0 = ’1’.  
Alternatively channels 2 and 3 (BAD2, BAD3) can be set up to function as address range match. Setting the ER1  
bit of the control register BCR0 to ’1’ provides this mode. BAD2 is the lower address and BAD3 is the upper address  
for address comparison. In this mode the mask register BAD0 will mask both channels 2 and 3, if the mask feature  
is enabled by EM1 = ’1’.  
Example:  
CTC  
EP0  
00  
Type: Instruction Address Break  
Enable break point on BAD0  
1
EP1  
1
1
Enable break point on BAD1  
ER0  
Enable address range function on BAD0, BAD1  
Enable address mask function on BAD0, BAD1  
Set lower break address  
EM0  
1
BAD0  
BAD1  
BAD2  
0x12345200  
0x12345300  
0xF0000000  
Set upper break address  
Set break mask  
399  
   
Chapter 29 MPU / EDSU  
3.Break Functions  
Break occurs at 0x02345200 to 0x02345300,or  
at 0x12345200 to 0x12345300,or  
at 0x22345200 to 0x22345300, etc.  
The resulting setting of the BD[1:0] status bits indicates the point, respective the area in which the break has oc-  
cured.  
Table 3-1 Instruction Break Detection Status Bits (BD)  
BD1  
BD0  
0
1
Match on point (instruction address == 0x12345200), or  
Match on point (instruction address == 0x22345200), etc  
1
1
0
1
Match on point (instruction address == 0x12345300), or  
Match on point (instruction address == 0x22345300), etc  
Match on range (0x12345200 < instruction address < 0x12345300), or  
Match on range (0x22345200 < instruction address < 0x22345300), etc  
In the instruction address break mode the following important point has to be considered:  
To precisely determine the instruction address where a break occurs, use the PC value saved on the stack during  
entry to the instruction break interrupt service routine.  
3.2 Operand address break  
The operand break function causes a break for the data access address which can be specified by the the operand  
address break registers BAD[3:0]. Setting the CTC[1:0] bits of the control register BCR0 to ’01’ provides this mode.  
The bits EP[3:0] in BCR0 enable the break points.  
Up to 4 breakpoints from channels 0 to 3 can be set. All operand break events are ORed into a operand break ex-  
ception interrupt request to the CPU.  
For the address mask function the same applies, what is stated in section 3.1 for the Instruction Address Break.  
Example:  
CTC  
EP1  
01  
Type: Operand Address Break  
Enable break point address BAD1  
Set mask BAD0 for break address BAD1  
Set break address  
1
1
EM0  
BAD1  
BAD0  
0x12345678  
0x00000FFF  
Set break mask  
Break occurs at 0x12345000 to 0x12345FFF  
On break at BAD[3:0] the respective flags BD[3:0] in the break interrupt request register BIRQ will be set to ’1’. They  
have to be reset by software in the operand break exception routine.  
Channels 0 and 1 (BAD0, BAD1) can be set up to function as address range match. Setting the ER0 bit of the control  
register BCR0 to ’1’ provides this mode. BAD0 is the lower address and BAD1 is the upper address for address  
comparison. In this mode the mask register BAD2 will mask both channels 0 and 1, if the mask feature is enabled  
by EM0 = ’1’.  
Alternatively channels 2 and 3 (BAD2, BAD3) can be set up to function as address range match. Setting the ER1  
bit of the control register BCR0 to ’1’ provides this mode. BAD2 is the lower address and BAD3 is the upper address  
for address comparison. In this mode the mask register BAD0 will mask both channels 2 and 3, if the mask feature  
is enabled by EM1 = ’1’.  
400  
Chapter 29 MPU / EDSU  
3.Break Functions  
Example:  
CTC  
EP0  
01  
Type: Operand Address Break  
1
Enable break point on BAD0  
Enable break point on BAD1  
EP1  
1
1
ER0  
Enable address range function on BAD0, BAD1  
Enable address mask function on BAD0, BAD1  
Set lower break address  
EM0  
1
BAD0  
BAD1  
BAD2  
0x12345200  
0x12345300  
0xF0000000  
Set upper break address  
Set break mask  
Break occurs at 0x02345200 to 0x02345300,or  
at 0x12345200 to 0x12345300,or  
at 0x22345200 to 0x22345300, etc.  
The resulting setting of the BD[1:0] status bits indicates the point, respective the area in which the break has oc-  
cured.  
Table 3-2 Operand Break Detection Status Bits (BD)  
BD1  
BD0  
0
1
1
1
0
1
Match on point (operand address == 0x12345200), or  
Match on point (operand address == 0x22345200), etc  
Match on point (operand address == 0x12345300), or  
Match on point (operand address == 0x22345300), etc  
Match on range (0x12345200 < operand address < 0x12345300), or  
Match on range (0x22345200 < operand address < 0x22345300), etc  
The access data length and read/write break attributes can also be specified by the control register BCR0, bits  
OBS[1:0] and OBT[1:0]. When the mask function is disabled by setting EM1 = EM0 = 0 (all bits effective), the rela-  
tionship between breakpoint setting, and break by access address is shown below:  
Table 3-3 Operand size and operand address relations  
Access data  
length  
Access  
address  
Address set in BOA0, BOA1  
4n + 1 4n + 2  
4n + 0  
4n + 3  
4n + 0  
Hit  
-
-
-
4n + 1  
4n + 2  
4n + 3  
4n + 0  
4n + 1  
4n + 2  
4n + 3  
-
Hit  
-
-
-
8 bit  
-
Hit  
-
-
-
-
Hit  
-
Hit  
Hit  
-
Hit  
Hit  
-
-
-
-
16 bit  
Hit  
Hit  
Hit  
Hit  
-
-
401  
Chapter 29 MPU / EDSU  
3.Break Functions  
Table 3-3 Operand size and operand address relations  
Access data  
length  
Access  
address  
Address set in BOA0, BOA1  
4n + 1 4n + 2  
4n + 0  
4n + 3  
4n + 0  
Hit  
Hit  
Hit  
Hit  
Hit  
Hit  
Hit  
Hit  
Hit  
Hit  
Hit  
Hit  
Hit  
Hit  
Hit  
Hit  
4n + 1  
4n + 2  
4n + 3  
32 bit  
In Operand address break mode the Operand Address, causing the break is captured in the BOAC register. Addi-  
tional BIAC holds the instruction address of the instruction, which was executed one cycle before the break causing  
data operation. This is normally the instruction, which has caused the data transfer.  
In the operand address break mode the following important points have to be considered:  
1) In the FR family architecture, if data access is performed with misalignment, the lower address bit 0 will be ig-  
nored for halfword and the lower address bits 0 and 1 for word access. The mask register could be programmed  
accordingly.  
2) The EDSU operand break does not always occur immediately after completion of execution of the instruction  
causing the break event.  
3) Please see also information at chapter 3.4 Using operand with data break  
3.3 Data value break  
The data value break causes a break if specified data is read or written at a data access to an address specified by  
the CPU. The data can be specified by the the data value break registers BAD0 and BAD1. Setting the CTC[1:0]  
bits of the control register BCR0 to ’11’ provides this mode. The bits EP0 and EP1 in BCR0 enable the break con-  
dition.  
Up to 2 break points from channels 0 to 1 can be set. All data value break events are ORed into a operand break  
exception to the CPU.  
1 mask register (BAD0) is available for masking the data value (stored in BAD1) and 1 mask register (BAD2) is avail-  
able for masking the operand address (BAD3) which is being accessed. Mask registers BAD2 and BAD0 can be  
enabled with EM1 and EM0.  
The data on which a break should be executed must be masked by a data-mask on the bus, requiring 32-bit setting  
considering the address and data length (see table below). This is required due to the byte position of the operand  
is dependent from the operand address. The setting of data length of the control register BCR0 OBS[1:0] could be  
configured to all ignored. The data length is controllable by mask setting to the BAD0 register implicitely.  
On break at BAD[1:0] the respective flags BD[1:0] in the break interrupt request register BIRQ will be set to ’1’. They  
have to be reset by software in the operand break exception routine.  
In Operand data value break mode the Operand Address, causing the break is captured in the BOAC register. Ad-  
ditional BIAC holds the instruction address of the instruction, which was executed one cycle before the break caus-  
ing data operation. This is normally the instruction, which has caused the data transfer.  
In the data value break mode the following important points have to be considered:  
1) The data value break is also executed for matching DMA transfers. This could lead to unexpected behaviour due  
to parallel processes. The filter bits FDMA and FCPU could be set for dedicated investigations.  
402  
Chapter 29 MPU / EDSU  
3.Break Functions  
2) The EDSU data break does not always occur immediately after completion of execution of the instruction causing  
the break event.  
3) Please see also information at chapter 3.4 Using operand with data break  
Table 3-4  
Access data  
length  
Address set  
to BAD3/2  
MASK set to BAD0  
Position of valid  
data in BAD1/0  
(indicated by *)  
Remarks  
4n + 0  
4n + 1  
4n + 2  
4n + 3  
4n + 0  
4n + 1  
4n + 2  
4n + 3  
4n + 0  
4n + 1  
4n + 2  
4n + 3  
0x00FFFFFF  
0xFF00FFFF  
0xFFFF00FF  
0xFFFFFF00  
0x0000FFFF  
0x0000FFFF  
0xFFFF0000  
0xFFFF0000  
0x00000000  
0x00000000  
0x00000000  
0x00000000  
**-- ----  
--** ----  
---- **--  
---- --**  
**** ----  
**** ----  
---- ****  
---- ****  
**** ****  
**** ****  
**** ****  
**** ****  
8 bit  
Possibly intended to  
use address mask in  
BAD3 for address  
bit 0  
16 bit  
32 bit  
Possibly intended to  
use address mask in  
BAD3 for address  
bits 1 and 0;  
Data mask not  
required, two chan-  
nels could be used  
Notes:  
1) The mask values for the BAD0 register in the table are a minimum set of bits. Setting more masking bits permits  
masking bits not needed to be compared with transfer data.  
2) "Position of valid data in BAD1, BAD0" provides an 8-bit hexadecimal image for MSB on the left and LSB on the  
right. Data at bit positions indicated by * in the BAD1, BAD0 registers is compared with data on the data bus, ac-  
cording to the access data length and access address.  
3.4 Using operand with data break  
Using operand address with data value break together is enabled with setting both EP3 and EP1, and/or both EP2  
and EP0 together with setting the bit COMB = ’1’ for the data value break mode set with CTC = ’11’.  
In other words: a break in channel 0 will occur at a match on operand address in BAD2 and a match on data value  
in BAD0. A break in channel 1 will occur at a match on operand address in BAD3 and a match on data value in  
BAD1. It is not possible to mix them vice versa.  
403  
 
Chapter 29 MPU / EDSU  
3.Break Functions  
On break both BD0 and BD2, respective BD1 and BD3 are set. They have to be reset by software in the operand  
break exception routine.  
Table 3-5 Operand address and data value break combinations  
EP3/2  
EP1/0  
COMB  
Function  
0
0
0
No break detection  
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
0
1
1
1
1
Independent data break (match value on any operand address)  
Independent Operand break (match operand address)  
Independent Data break and Operand break  
No break detection  
No break detection  
No break detection  
Data value break (match both operand address and value)  
3.5 Memory Protection  
Due to the availability of address range comparators for the operand and instruction addresses the wish is obvios,  
to use the same comparator hardware as a memory protection unit (MPU).  
Following table list the possible type configurations and its feasibility to be used for memory protection. The number  
of break points and MPU channels is valid for 8 comparator groups implemented.  
Table 3-6 Comparator Type Configuration  
CTC  
CMP1 Input  
CMP0 Input  
Max. Break Points  
(MPE=0)  
Max. MPU Channels  
(MPE=1)  
00  
IA  
IA  
32 Instruction breaks  
32 Operand breaks  
16 + 16 IA/OA breaks  
16 ranges with execute  
permissions  
01  
10  
OA  
OA  
OA  
IA  
16 ranges with read/  
write permissions  
8 ranges with read/  
write and execute per-  
missions or 8+8 inde-  
pendent ranges  
11  
OA  
DT  
16 data value breaks  
-
Additional to the given hardware there were made some extensions to provide the user with a more likely configu-  
ration of read, write and execute permissions instead of the more bus applicable definition of the operand break size  
and type definitions OBS/OBT, including read-modify-write. With the introduction of the SuperVisor mode a defini-  
tion of User and SuperVisor permissions is possible.  
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Chapter 29 MPU / EDSU  
3.Break Functions  
Permissions can be set for the comparator channel CMP1 and CMP0 separately, indicated by the symbol index.  
Table 3-7 Meaning of the permission config bits  
Symbol  
SRX[1:0] SuperVisor Read permission  
SW[1:0] SuperVisor Write permission  
URX[1:0] User Read permission  
UW[1:0] User Write permission  
Data Mode (OA)  
Instruction Mode (IA)  
SuperVisor eXecute permission  
-
User eXecute permission  
-
At each time an instruction is executed or an operand is accessed, the actual valid permissions were evaluated.  
This evaluation is divided into operand access (OA-based) and code execution (IA-based).  
For each part the highest priority region hit is searched for. The highest channel number has the highest priority  
(strict priority scheme). If a channel hit was found, the permissions defined for this channel will apply. If no channel  
hit was detected, the default permissions apply.  
After the actual permissions are evaluated (valid for actual data access, if any, and actual instruction) the permis-  
sions were checked. If the exceute permission is not set or if the read or write permissions do not fit to the type of  
the actual access, a protection violation will be indicated. This causes a CPU trap to the memory protection violation  
MPUPV handler routine. The CPU switches directly to SuperVisor mode in this case.  
The config register space of the EDSU is protected against random access in User mode. Only in SuperVisor mode  
or Emulation mode the register file enables write access. For configuration a system interrupt INT #5 was defined,  
which switches in SuperVisor mode (SV bit remains set during the execution of the INT #5-ISR). Except debugger  
interrupts by the emulator and NMI the SuperVisor ISR is not interruptible.  
Exceptions caused by the memory protection and the break unit for debugging are separated. In that way the mem-  
ory protection functionality can be debugged itself.  
3.6 Break Factors  
Summary of the internal break factors and the executed events:  
Break on instruction address  
Break on operand address  
Break on data value  
->  
->  
->  
->  
->  
->  
->  
->  
Causes Instruction Break  
Causes Operand Break  
Causes Operand Break  
Causes Tool NMI  
Resource Interrupt (BREAK)  
Step Trace Trap  
Causes Step Trace Trap  
Causes INTE  
Execution of the INTE instr.  
Execution of INT #5  
CPU SuperVisor Mode  
Causes MPUPV Trap  
Memory protection exception  
405  
Chapter 29 MPU / EDSU  
3.Break Functions  
Break factors and corresponding interrupt numbers and vectors:  
Table 3-8 Interrupt numbers and vectors of break factors  
Interrupt  
Interrupt number  
Interrupt level  
Interrupt vector  
Offset Default Vector  
Decimal  
Hexa-  
Setting  
Register  
Register  
address  
decimal  
address  
CPU supervisor mode  
(INT #5 instruction)  
5
05  
06  
-
-
0x3E8  
0x3E4  
0x000FFFE8  
Memory protection  
exception  
6
-
-
0x000FFFE4  
INTE instruction  
9
09  
-
-
-
-
0x3D8  
0x3D4  
0x000FFFD8  
0x000FFFD4  
Instruction break  
exception  
10  
0A  
Operand break  
exception  
11  
0B  
-
-
0x3D0  
0x000FFFD0  
Step trace trap  
12  
13  
0C  
0D  
-
-
-
-
0x3CC  
0x3C8  
0x000FFFCC  
0x000FFFC8  
NMI interrupt (tool)  
406  
 
Chapter 29 MPU / EDSU  
4.Registers  
4. Registers  
4.1 List of EDSU Registers  
Table 4-1 EDSU Registers Summary  
Address  
Register  
Block  
+0  
+1  
+2  
+3  
F000  
BCTRL [R/W]  
-------- -------- 11111100 00000000  
EDSU  
H
H
1
F004  
F008  
BSTAT [R/W0]  
-------- -----000 00000000 10--0000  
BIAC  
[R]  
H
00000000 00000000 00000000 00000000  
F00C  
BOAC  
[R]  
H
00000000 00000000 00000000 00000000  
F010  
BIRQ [R/W]  
H
00000000 00000000 00000000 00000000  
F014 ...F01F  
reserved  
-
H
H
F020  
F024  
F028  
BCR0  
[R/W]  
H
H
H
-------- 00000000 00000000 00000000  
BCR1  
[R/W]  
-------- 00000000 00000000 00000000  
BCR2 [R/W]  
-------- 00000000 00000000 00000000  
BCR3 [R/W]  
F02C  
H
-------- 00000000 00000000 00000000  
F030  
F034  
F038  
BCR4 [R/W]  
H
-------- 00000000 00000000 00000000  
BCR5 [R/W]  
H
H
-------- 00000000 00000000 00000000  
BCR6 [R/W]  
-------- 00000000 00000000 00000000  
BCR7 [R/W]  
F03C  
H
-------- 00000000 00000000 00000000  
F040 ...F07F  
reserved  
-
H
H
407  
 
Chapter 29 MPU / EDSU  
4.Registers  
Table 4-1 EDSU Registers Summary  
Address  
Register  
Block  
+0  
+1  
+2  
+3  
EDSU  
F080  
BAD0  
[R/W]  
H
H
H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
F084  
F088  
BAD1  
[R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD2 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD3 [R/W]  
F08C  
H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
F090  
F094  
F098  
BAD4 [R/W]  
H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD5 [R/W]  
H
H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD6 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD7 [R/W]  
F09C  
H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
F0A0  
F0A4  
F0A8  
BAD8 [R/W]  
H
H
H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD9 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD10 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
F0AC  
BAD11 [R/W]  
H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
F0B0  
F0B4  
F0B8  
BAD12 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
BAD13 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
H
BAD14 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
F0BC  
BAD15 [R/W]  
H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
408  
Chapter 29 MPU / EDSU  
4.Registers  
Table 4-1 EDSU Registers Summary  
Address  
Register  
Block  
+0  
BAD16 [R/W]  
+1  
+2  
+3  
EDSU  
F0C0  
F0C4  
F0C8  
H
H
H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD17 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD18 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
F0CC  
BAD19 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
H
H
H
F0D0  
F0D4  
F0D8  
BAD20 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD21 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
BAD22 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
F0DC  
BAD23 [R/W]  
H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
F0E0  
F0E4  
F0E8  
BAD24 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
BAD25 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
H
BAD26 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
F0EC  
BAD27 [R/W]  
H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
F0F0  
F0F4  
F0F8  
BAD28 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
BAD29 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
H
H
BAD30 [R/W]  
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
F0FC  
BAD31 [R/W]  
H
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX  
1.RMW - read returns ’1’ for each flag, for write only ’0’ (clear) is supported.  
Remark: Read and write access to all registers is byte, halfword and word.  
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Chapter 29 MPU / EDSU  
4.Registers  
4.2 Explanations of Registers  
● EDSU Control Register (BCTRL)  
⇐ Bit no.  
EDSU Control Register byte 2  
Address : F002H  
15  
14  
13  
12  
11  
10  
9
8
SR  
SW  
SX  
UR  
UW  
UX  
FCPU FDMA  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
(0)  
(0)  
⇐ Bit no.  
7
6
5
4
3
2
1
0
EDSU Control Register byte 3  
Address : F003H  
EEMM PFD SINT1 SINT0 EINT1 EINT0 EINTT EINTR  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
Default Permission Register  
The default permission register defines the lowest priority access permissions for the whole memory and I/O ad-  
dress range of the MCU. Lowest priority means, that the default permissions take effect for all address regions,  
which are NOT covered by any dedicated channel configuration, operating in MPU mode. Default read, write and  
execute permissions could be defined for the super visior mode (SV=1) and the normal user mode (SV=0). The su-  
per visor mode (SV) is indicated by bit 6 of the CCR in the program status word of the CPU. After the INIT condition  
all permissions are set (access allowed).  
BIT[15]: SR - Super visor default Read permission register  
0
1
Super visor is not permitted to read data  
Super visor is permitted to read data (default)  
BIT[14]: SW - Super visor default Write permission register  
0
1
Super visor is not permitted to write data  
Super visor is permitted to write data (default)  
BIT[13]: SX - Super visor default eXecute permission register  
0
1
Super visor is not permitted to execute code  
Super visor is permitted to execute code (default)  
BIT[12]: UR - User default Read permission register  
0
1
User is not permitted to read data  
User is permitted to read data (default)  
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Chapter 29 MPU / EDSU  
4.Registers  
BIT[11]: UW - User default Write permission register  
0
1
User is not permitted to write data  
User is permitted to write data (default)  
BIT[10]: UX - User default eXecute permission register  
0
1
User is not permitted to execute code  
User is permitted to execute code (default)  
CPU and DMA Filter Option Register  
BIT[9]: FCPU - Filter CPU access  
0
1
Trigger on CPU accesses (default)  
Do not trigger on CPU accesses  
FCPU controls the filter operation for CPU accesses triggered by operand compare channels (Operand address  
break, data value break and memory data protection).  
If FCPU is set to ’1’, all CPU acesses are masked out. If set to ’0’ CPU acesses can cause break function.  
BIT[8]: FDMA - Filter DMA access  
0
1
Trigger on DMA accesses (default)  
Do not trigger on DMA accesses  
FDMA controls the filter operation for DMA accesses triggered by operand compare channels (Operand address  
break, data value break and memory data protection).  
If FDMA is set to ’1’, all DMA acesses are masked out. If set to ’0’ DMA acesses can cause break function.  
Important Note for FDMA: Only DMA accesses over D-Bus were detected. The operands for an explicite DMA trig-  
ger condition have to be located in the D-Bus address area (This is the case for D-bus RAM, CAN and all R-Bus  
resources in the MB91460 family). Otherwise the DMA transfer could not be recognized by the EDSU. This function  
was mainly intendet to disable the trigger on DMA accesses (filter out the operand change condition by DMA), com-  
plete address range DMA trigger conditions are not supported.  
Enable Interrupt Register  
BIT[7]: EEMM - Enable Emulation Mode  
0
Disable emulation mode (default)  
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Chapter 29 MPU / EDSU  
4.Registers  
1
Enable emulation mode  
If EEMM is set to ’1’ then the emulation mode is entered during Step Trace Mode and EDSU exceptions Instruction  
Break, Operand Break and Tool NMI. During emulation mode the Watchdog Timer (WDT) is disabled. EDSU trig-  
gered emulation mode is left with the RETI instruction.  
Set to ’0’ disables emulation mode function. The WDT is not stopped during Step Trace and EDSU exceptions.  
BIT[6]: PFD - Phantom Filter Disable  
0
1
Instruction break detection uses phantome filter (default)  
Phantome Filter disabled  
The default (PFD=0) is to use policies to filter out phantom interrupts and wrong status bits, which may be set in  
addition.  
•
The instruction fetched, after RETI was executed, is normally the instruction on which the break point was set.  
Fetch is repeated after processing the breakpoint handler ISR before executing the instruction at the break  
point. The filter avoids that the trigger of the break condition will be repeated.  
•
Not granted Instruction Break exceptions are timed out  
—
—
Pre-fetched, but not executed commands  
Commands after delayed slot instruction  
•
•
Consecutive break conditions which are pre-fetched are not allowed to set flags. Only the instruction at which  
the break condition occures at first time can set status bits accordingly.  
Nested Instruction breaks are not allowed (break within the break handler ISR)  
BIT[5:4]: SINT[1:0] - Select resource INTerrupt source  
SINT[1:0]  
00  
MB91V460  
Resource  
Tool NMI by interrupt on source 0 selected (default)  
Tool NMI by interrupt on source 1 selected  
Tool NMI by interrupt on source 2 selected  
Tool NMI by interrupt on source 3 selected  
UART 0 RX / UART 0 TX  
UART 1 RX / UART 1 TX  
UART 2 RX / UART 2 TX  
CAN 0 / CAN 1  
01  
10  
11  
SINT[1:0]  
MB91F467DA  
Tool NMI by interrupt on source 0 selected (default)  
Tool NMI by interrupt on source 1 selected  
Tool NMI by interrupt on source 2 selected  
Tool NMI by interrupt on source 3 selected  
Resource  
00  
01  
10  
11  
UART 2 RX / UART 2 TX  
UART 4 RX / UART 4 TX  
UART 5 RX / UART 5 TX  
CAN 0 / CAN 1  
SINT1 and SINT0 select the active resource interrupt source.  
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Chapter 29 MPU / EDSU  
4.Registers  
BIT[3]: EINT1 - Enable extended INTerrupt 1  
0
1
Disable extended interrupt source 1 (default)  
Enable extended interrupt source 1  
If EINT1 is set to ’1’ then a Tool NMI will be generated on an extended interrupt event at source channel 1. Set to  
’0’ disables this function.  
Remark: EINT1 interrupt source is not available for the MB91460 series.  
BIT[2]: EINT0 - Enable extended INTerrupt 0  
0
1
Disable extended interrupt source 0 (default)  
Enable extended interrupt source 0  
If EINT0 is set to ’1’ then a Tool NMI will be generated on an extended interrupt event at source channel 0. Set to  
’0’ disables this function.  
Remark: EINT1 and EINT0 can be used for indicating a signal line event which can be used for generating a BREAK  
function. The sources of these interrupts are hardwired in the MCU and can be for example: external interrupt ports,  
general purpose I/O port pins, other resources, etc. This has to be defined in the device specification.  
BIT[1]: EINTT - Enable INTerrupt on Transmit  
0
1
Disable transmit interrupt source channels 0 to 3 (default)  
Enable transmit interrupt source channels 0 to 3  
If EINTT is set to ’1’ then a Tool NMI will be generated on a transmit interrupt event at source channels 0 to 3 set  
by TXINT[1:0]. Setting EINTT to ’0’ disables this function.  
Remark: If SINT[1:0] is set to “11” this bit enables the interrupt of CAN channel 1 (CAN has one interrupt  
request for both reception and transmission).  
BIT[0]: EINTR - Enable INTerrupt on Receive  
0
1
Disable receive interrupt source channels 0 to 3 (default)  
Enable receive interrupt source channels 0 to 3  
If EINTR is set to ’1’ then a Tool NMI will be generated on a receive interrupt event at source channels 0 to 3 set by  
RXINT[1:0]. Setting EINTR to ’0’ disables this function.  
Remark: If SINT[1:0] is set to “11” this bit enables the interrupt of CAN channel 0 (CAN has one interrupt  
request for both reception and transmission).  
413  
Chapter 29 MPU / EDSU  
4.Registers  
● EDSU Status Register (BSTAT)  
⇐ Bit no.  
EDSU Status Register byte 2  
Address : F006H  
15  
14  
13  
12  
11  
10  
9
8
IDX4 IDX3  
IDX2  
IDX1  
IDX0 CDMA CSZ1 CSZ0  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
⇐ Bit no.  
7
6
5
4
3
2
1
0
EDSU Status Register byte 3  
Address : F007H  
CRW1 CRW0  
PV  
RST  
INT1  
INT0  
INTT INTR  
(
(0)  
R
)
(
(0)  
R
)
(
R/W) (R/W) (R/W) (R/W) (R)  
(0) (1) (0) (0) (0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
BIT[15:11]: IDX[4:0] - Channel Index Indication of MPUPV Trigger  
In the case of triggering a memory protection violation (MPUPV), the index of the channel pair 0...15 is saved in The  
IDX register, which caused the trigger. The channel pairs are normally used as range comparators.  
If no MPU chanel has detected a hit on its address range, the default permissions apply. If the default permissions  
are violated, IDX is set to the value 16 (overrun). If the permissions of a matching MPU channel are violated, IDX  
shows the index of the appropriate break detection bits BIRQ_BD[31:0]. The break detection bits belonging tho this  
comparator are BD[2*IDX] and BD[2*IDX+1].  
In case of multiple range hits and/or trigger conditions, the channel with the highest priority trigger condittion is in-  
dicated by IDX[4:0]. The priority raises with the channel index.  
IDX  
0-15 Points to the channel number of the last protection violation  
16 The last protection violation was caused by the violation of the default permissions  
Description  
The channel index indication register can be read only.  
Access Type Capture Register  
In case of a trap caused by a memory protection violation or an operand/data value break condition, the status bits  
[12:8] capture type information about the break causing operand access. In case of a memory protection fault due  
to the violation of execution permissions, this information is also captured, regardless if there was an active operand  
access or not.  
Access type capture register are read only.  
BIT[10]: CDMA - Capture DMA Indication  
0
1
The operand access was executed by the CPU  
The operand access was executed by the DMA controller  
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Chapter 29 MPU / EDSU  
4.Registers  
BIT[9:8]: CSZ[1:0] - Capture Operand Size  
00  
01  
10  
11  
The operand has a bit size of 8  
The operand has a bit size of 16  
The operand has a bit size of 32  
reserved  
BIT[7:6]: CRW[1:0] - Capture Operand Access Type  
00  
01  
10  
11  
The operand has been read  
The operand has been read by read-modify-write indicated  
The operand has been written  
no operand access  
BIT[5]: PV - Protection Violation Detection  
0
1
There was no protection violation on read, write and execute permissions  
A protection violation (MPUPV) has been occured  
If this bit is set after a protection violation, a MPUPV trap is indicated to the CPU. The occurance of a protection  
violation means, that there was a read or write access to a defined address region, which was not permitted or code  
was executed without execute permissions for this address region. As consequence the CPU switches to super vi-  
sor mode (SV=1) and calls the handler routine for interrupt number #6 (see table 3-8).  
This bit should be cleared by writing ’0’ in the MPUPV trap handler routine.  
BIT[4]: RST - Operation Initialization Reset (RST) Detection  
The reset operation of FRex family is divided into two levels, setting initialization reset (INIT) and operation initiali-  
zation reset (RST). When INIT occurs, RST occures at the same time implicitely.  
0
1
Operation Reset was not triggered since last BSTAT read or clear  
Operation Reset was triggered since last BSTAT read or clear  
The RST bit is read only, any write access to this bit will be ignored. RST is cleared after BSTAT is read (read from  
any byte address within the 32 bit word). RST has same behaviour for read and read-modify-write access.  
The RST bit can be used for reset detection. It is set in any case of operation initialization reset is triggered. Debug  
monitor software can use this to detect if the communication device to the debugger front end needs to be re-con-  
figured after an operation reset. This is important for debugging of boot procedures and soft reset handling. After  
reading the EDSU status word the RST bit is cleared automatically.  
Break Interrupt Register  
415  
Chapter 29 MPU / EDSU  
4.Registers  
BIT[3]: INT1 - INTerrupt on extended source 1  
0
1
Interrupt on extended source channel 1 not detected (default)  
Interrupt on extended source channel 1 detected  
INT1 reflects the status of the extended interrupt source channel 1. It is set to ’1’ if a high level on the extended  
interrupt signal line has been occured. The status of ’1’ is stored until cleared by software.  
Writing ’0’ resets the INT1 bit to ’0’. Writing ’1’ to this bit is ignored. On a Read Modify Write instruction INT1 is read  
as ’1’.  
BIT[2]: INT0 - INTerrupt on extended source 0  
0
1
Interrupt on extended source channel 0 not detected (default)  
Interrupt on extended source channel 0 detected  
INT0 reflects the status of the extended interrupt source channel 0. It is set to ’1’ if a high level on the extended  
interrupt signal line has been occured. The status of ’1’ is stored until cleared by software.  
Writing ’0’ resets the INT0 bit to ’0’. Writing ’1’ to this bit is ignored. On a Read Modify Write instruction INT0 is read  
as ’1’.  
BIT[1]: INTT - INTerrupt on Transmit source  
0
1
Interrupt on transmit source not detected (default)  
Interrupt on transmit source channel detected  
INTT reflects the status of the transmit interrupt source channels 0 to 3 (can be selected by TXINT[1:0]). It is set to  
’1’ on a high level on the transmit interrupt signal line and ’0’ on a low level on the signal line.  
This bit is read-only. It can be set to ’0’ by clearing the appropriate interrupt bit in the selected resource.  
Remark: If SINT[1:0] is set to “11” this bit indicates the interrupt of CAN channel 1 (CAN has one interrupt  
request for both reception and transmission).  
BIT[0]: INTR - INTerrupt on Receive source  
0
1
Interrupt on receive source not detected (default)  
Interrupt on receive source channel detected  
INTR reflects the status of the receive interrupt source channels 0 to 3 (can be selected by RXINT[1:0]). It is set to  
’1’ on a high level on the receive interrupt signal line and ’0’ on a low level on the signal line.  
This bit is read-only. It can be set to ’0’ by clearing the appropriate interrupt bit in the selected resource.  
Remark: If SINT[1:0] is set to “11” this bit indicates the interrupt of CAN channel 1 (CAN has one interrupt  
request for both reception and transmission).  
416  
Chapter 29 MPU / EDSU  
4.Registers  
● EDSU Instruction Address Capture Register (BIAC)  
BIAC [R]  
Address  
F008  
+0  
00000000  
+1  
00000000  
+2  
00000000  
+3  
00000000  
H
This register captures the address of the instruction (IA), which has caused the protection violation or the operand/  
data value break. This register could be read only.  
● EDSU Operand Address Capture Register (BOAC)  
BOAC [R]  
Address  
F00C  
+0  
00000000  
+1  
00000000  
+2  
00000000  
+3  
00000000  
H
This register captures the address of the operand access (OA), which has caused the protection violation or the  
operand/data value break. This register could be read only.  
● EDSU Break Detection Interrupt Request Register (BIRQ)  
BIRQ [R/W]  
Address  
F010  
+0  
00000000  
+1  
00000000  
+2  
00000000  
+3  
00000000  
H
BIRQ collects all break detection bits of all channels, regardless of the type configuration of each channel. The ac-  
tual implementation consists of 8 groups of channels, that are 32 single point channels totally.  
Each group of channels consists of 4 channels and 4 bits for break detection in the BIRQ register. Each group has  
two comparator pairs. Each pair consists of two point comparators which could build a range comparator by setting  
the range enable bit. Such a range comparator pair is connected to the instruction address, operand address or the  
data value information - selected by the comparator type configuration.  
For detection of combined operand address and data value breaks two of such comparator pairs are combined to-  
gether. Than the break detection (BD) bits are set only if both conditions are matching simultaneously.  
BIT[31:0]: BD[31:0] - Break Detection register  
0
1
Break factor not detected (default)  
Break factor detected on channel according the bit position [31:0]  
BD[31:0] reflects the status of the break detection. It is set to ’1’ at match with BAD31...BAD0 accordingly (and if  
the mask condition is satisfied, if enabled by EM1/0). For bit pairs [31:30], [29:28], ..., [1:0] range matches could  
apply, if the range function using two points is enabled by ER1/0.  
Break factors could be  
•
instruction address break,  
417  
Chapter 29 MPU / EDSU  
4.Registers  
•
•
•
•
operand address break,  
data value break,  
combined operand address and data value break and  
memory protection violation.  
Writing ’0’ resets the BD[31:0] bits to ’0’. Writing ’1’ to these bits is ignored. On a Read Modify Write instruction all  
BD bits are read as ’1’.  
BD1/BD0 setting at enabled address range function (also valid for the other pairs of BD bits in neighbourhood):  
If the operand address range function is enabled with ER0 in addition to the point enables EP1 and EP0, then the  
BD1 and BD0 detection bits are set in the following manner:  
Table 4-2 BD Coding for Match on Start/Endoint or Range  
BD1  
BD0  
Compare value: Instruction, Operand Address, Data Value  
No match (Default)  
0
0
1
1
0
1
0
1
Match on point (compare value == BAD0)  
Match on point (compare value == BAD1)  
Match on range (BAD0 < compare value < BAD1)  
418  
 
Chapter 29 MPU / EDSU  
4.Registers  
● EDSU Channel Configuration Register (BCR0...BCR7)  
⇐ Bit no.  
⇐ Bit no.  
⇐ Bit no.  
⇐ Bit no.  
EDSU Ch. Config Register 0, byte 0  
Address : F020H  
31  
30  
29  
28  
27  
26  
25  
24  
-
-
-
-
-
-
-
-
(-)  
(X)  
(-)  
(X)  
(-)  
(X)  
(-)  
(X)  
(-)  
(X)  
(-)  
(X)  
(-)  
(X)  
(-)  
(X)  
Read/write ⇒  
Default value⇒  
23  
22  
21  
20  
19  
18  
17  
16  
EDSU Ch. Config Register 0, byte 1  
Address : F021H  
SRX1 SW1 SRX0 SW0  
URX1 UW1  
URX0 UW0  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(0)  
Read/write ⇒  
Default value⇒  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
EDSU Ch. Config Register 0, byte 2  
Address : F022H  
15  
14  
13  
12  
11  
10  
9
8
MPE COMB CTC1 CTC0 OBS1 OBS0 OBT1 OBT0  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(0)  
Read/write ⇒  
Default value⇒  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
7
6
5
4
3
2
1
0
EDSU Ch. Config Register 0, byte 3  
Address : F023H  
EP3  
EP2  
EP1  
EP0  
EM1  
EM0  
ER1  
ER0  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(0) (0) (0) (0) (0) (0) (0) (0)  
Read/write ⇒  
Default value⇒  
For each group of four channels one channel configuration register (BCR0...BCR7) is implemented. It holds the con-  
figuration set for the according group of channels. The following table shows the relationship, which channel con-  
figuration, break point address/data registers and break detection bits belong together.  
Table 4-3 Relationship of BCR, BAD and BIRQ registers  
Group Config Address/Data BADx Usage  
Point  
EP0  
EP1  
EP2  
EP3  
EP0  
EP1  
EP2  
EP3  
EP0  
EP1  
EP2  
EP3  
Mask  
Combination  
BIRQ  
BD0  
BD1  
BD2  
BD3  
BD4  
BD5  
BD6  
BD7  
BD8  
BD9  
BD10  
BD11  
Point0, Mask0  
Point1  
EM0  
range 0  
BCR0  
BCR1  
BCR2  
BAD0  
BAD1  
BAD2  
BAD3  
BAD4  
BAD5  
BAD6  
BAD7  
BAD8  
BAD9  
BAD10  
BAD11  
OA0  
OA1  
DT0  
DT1  
OA0  
OA1  
DT0  
DT1  
OA0  
OA1  
DT0  
DT1  
ER0  
Point2, Mask1  
Point3  
EM1  
EM0  
EM1  
EM0  
EM1  
range 1  
ER1  
Point0, Mask0  
Point1  
range 0  
ER0  
Point2, Mask1  
Point3  
range 1  
ER1  
Point0, Mask0  
Point1  
range 0  
ER0  
Point2, Mask1  
Point3  
range 1  
ER1  
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Chapter 29 MPU / EDSU  
4.Registers  
Table 4-3 Relationship of BCR, BAD and BIRQ registers  
Group Config Address/Data BADx Usage  
Point  
EP0  
EP1  
EP2  
EP3  
EP0  
EP1  
EP2  
EP3  
EP0  
EP1  
EP2  
EP3  
EP0  
EP1  
EP2  
EP3  
EP0  
EP1  
EP2  
EP3  
Mask  
Combination  
BIRQ  
BD12  
BD13  
BD14  
BD15  
BD16  
BD17  
BD18  
BD19  
BD20  
BD21  
BD22  
BD23  
BD24  
BD25  
BD26  
BD27  
BD28  
BD29  
BD30  
BD31  
Point0, Mask0  
Point1  
EM0  
range 0  
BCR3  
BCR4  
BCR5  
BCR6  
BCR7  
BAD12  
BAD13  
BAD14  
BAD15  
BAD16  
BAD17  
BAD18  
BAD19  
BAD20  
BAD21  
BAD22  
BAD23  
BAD24  
BAD25  
BAD26  
BAD27  
BAD28  
BAD29  
BAD30  
BAD31  
OA0  
OA1  
DT0  
DT1  
OA0  
OA1  
DT0  
DT1  
OA0  
OA1  
DT0  
DT1  
OA0  
OA1  
DT0  
DT1  
OA0  
OA1  
DT0  
DT1  
ER0  
Point2, Mask1  
Point3  
EM1  
EM0  
EM1  
EM0  
EM1  
EM0  
EM1  
EM0  
EM1  
range 1  
ER1  
Point0, Mask0  
Point1  
range 0  
ER0  
Point2, Mask1  
Point3  
range 1  
ER1  
Point0, Mask0  
Point1  
range 0  
ER0  
Point2, Mask1  
Point3  
range 1  
ER1  
Point0, Mask0  
Point1  
range 0  
ER0  
Point2, Mask1  
Point3  
range 1  
ER1  
Point0, Mask0  
Point1  
range 0  
ER0  
Point2, Mask1  
Point3  
range 1  
ER1  
Group of Channels, Permission Definition Register  
The permission definition registers are valid only for the group of channels operating in MPU mode. This is the case  
if MPE is set to ’1’. If the group does not operate in MPU mode, the permission configuration is not required (don’t  
care).  
Normally MPU channels operate in range mode for the address definitions.  
The type of the permission, which could be set-up, depends on the comparator type configuration (CTC) for each  
comparator pair. MPU channels could be configured either to check instruction addresses (IA) or operand address-  
es (OA). IA ranges could be used to define exceute permissions. OA ranges could be used to define read and write  
permissions.  
The comparator type for MPU usage could be set to  
•
•
CTC=0: both IA ranges define execute permissions,  
CTC=1: both OA ranges define read/write permissions and  
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Chapter 29 MPU / EDSU  
4.Registers  
•
CTC=2: IA range 0 defines execute permissions and OA range 1 defines read/write permissions.  
Data value (DT) detection by setting CTC=3 is not possible to use in MPU mode.  
Permission configurations exist for read, write and execute for two CPU modes, the super visor mode and the user  
mode. Super visor permissions are valid for SV=1 and user permissions are valid for SV=0.  
BIT[23]: SRX1 - Super visor Read/eXecute permission register for range 1  
Setting valid for CTC == 0 (Instruction address range comparator):  
0
1
Super visor has no execute permission on address range 1(default)  
Super visor has execute permission on address range 1  
Setting valid for CTC == 1 or CTC == 2 (Operand address range comparator):  
0
1
Super visor has no read permission on address range 1 (default)  
Super visor has read permission on address range 1  
BIT[22]: SW1 - Super visor Write permission register for range 1  
Setting valid for CTC == 1 or CTC == 2 (Operand address range comparator):  
0
1
Super visor has no write permission on address range 1 (default)  
Super visor has write permission on address range 1  
BIT[21]: SRX0 - Super visor Read/eXecute permission register for range 0  
Setting valid for CTC == 0 or CTC == 2 (Instruction address range comparator):  
0
1
Super visor has no execute permission on address range 0 (default)  
Super visor has execute permission on address range 0  
Setting valid for CTC == 1 (Operand address range comparator):  
0
1
Super visor has no read permission on address range 0 (default)  
Super visor has read permission on address range 0  
BIT[20]: SW1 - Super visor Write permission register for range 0  
Setting valid for CTC == 1 (Operand address range comparator):  
0
1
Super visor has no write permission on address range 0 (default)  
Super visor has write permission on address range 0  
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Chapter 29 MPU / EDSU  
4.Registers  
BIT[19]: URX1 - User Read/eXecute permission register for range 1  
Setting valid for CTC == 0 (Instruction address range comparator):  
0
1
User has no execute permission on address range 1(default)  
User has execute permission on address range 1  
Setting valid for CTC == 1 or CTC == 2 (Operand address range comparator):  
0
1
User has no read permission on address range 1 (default)  
User has read permission on address range 1  
BIT[18]: UW1 - User Write permission register for range 1  
Setting valid for CTC == 1 or CTC == 2 (Operand address range comparator):  
0
1
User has no write permission on address range 1 (default)  
User has write permission on address range 1  
BIT[17]: URX0 - User Read/eXecute permission register for range 0  
Setting valid for CTC == 0 or CTC == 2 (Instruction address range comparator):  
0
1
User has no execute permission on address range 0 (default)  
User has execute permission on address range 0  
Setting valid for CTC == 1 (Operand address range comparator):  
0
1
User has no read permission on address range 0 (default)  
User has read permission on address range 0  
BIT[16]: UW1 - User Write permission register for range 0  
Setting valid for CTC == 1 (Operand address range comparator):  
0
1
User has no write permission on address range 0 (default)  
User has write permission on address range 0  
Group of Channels, Mode Configuration Register  
BIT[15]: MPE - Memory Protection Enable  
0
The group of channels operates as debug interface and defines breakpoints (default)  
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Chapter 29 MPU / EDSU  
4.Registers  
1
The group of channels operates in memory protection mode  
Some restrictions apply with the setting of the MPE bit.  
MPE=0 (break unit):  
•
permission registers are don’t care (BCRx bits [23:16])  
MPE=1 (memory protection unit):  
•
•
OBS and OBT should be set to ’3’ (BCRx bits [11:8], any size and any type)  
CTC should not be set to ’3’ (BCRx bits [13:12], data value check not supported in this mode)  
BIT[14]: COMB - Channel Combination Enable  
0
1
No combination between channels (default)  
Combination between channels is effective  
Depending on the MPE configuration bit the COMB feature has different meaning.  
(A) COMB=1 and MPE=0 (break unit, combined operand address and data value break):  
The break detection conditions are combined before setting the BIRQ_BD bits and signalizing an operand break  
condition. Setting the COMB bit is required for defining a data value break on a specific operand address. If the  
COMB bit is set to ’1’, both conditions, matching operand address (OA) and matching data value (DT), are required  
to be true. Setting the COMB bit makes only sense in the OA/DT mode, defined by CTC=3.  
The AND-combination is effective between channels 3 (OA1) and 1 (DT1) and between channels 2 (OA0) and 0  
(DT0). It is assumed that no range operation is defined (ER1=ER0=0).  
BIRQ_BD3 = BIRQ_BD1 = BD3 && BD1;  
BIRQ_BD2 = BIRQ_BD0 = BD2 && BD0;  
If channels 3 and 2 define an operand address range (OA1:OA0) by setting ER1=1 and/or channels 1 and 0 define  
a data value range (DT1:DT0) by setting ER0=1, the break detection bits of each channel are AND-combined with  
the ORed channels of the opposite range comparator break detection outputs.  
BIRQ_BD3 = BD3 && (BD1 || BD0);  
BIRQ_BD2 = BD2 && (BD1 || BD0);  
BIRQ_BD1 = BD1 && (BD3 || BD2);  
BIRQ_BD0 = BD0 && (BD3 || BD2);  
This offers the same interpretation of the BIRQ break detction bits (see table 4-2 for coding of match on start point,  
range or end point) as it would be the case for range detection with COMB=0. BD3 and BD2 hold the coding for the  
operand address (OA) match, whereas BD1 and BD0 hold the coding for the data value (DT) match. The COMB bit  
set to ’1’ ensures that both conditions, the OA match and the DT match must be true to set the appropriate BD bit  
in the end.  
If the COMB bit is set to ’0’ all break detection bits are passed to the BIRQ register in it’s original form. The compa-  
rator channels match conditions are independent from each other.  
(B) COMB=1 and MPE=1 (memory protection unit, combined rwx permissions on single range):  
In memory protection mode the COMB bit has the meaning of combined data read/write and code execute permis-  
sions, set for the same address range. The setting is only meaningful for the combination of operand address (OA)  
comparators on channels 3 and 2 and instruction address (IA) comparators on channels 1 and 2 in the mode  
CTC=2.  
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Chapter 29 MPU / EDSU  
4.Registers  
The COMB bit set to ’1’ causes the IA comparator CMP0 to use the same BADx point definitions as the OA com-  
parator CMP1. Point 3 and Point 2 define the address range for both comparators CMP0 and CMP1. This has the  
effect that the entry of Point 0/Mask 0 is not allocated for the Point set-up and could be used for masking either one  
or both comparators. The Point 1 entry is not useable in this case.  
If the COMB bit is set to ’0’ both comparators have independent address configurations. The comparators can either  
define read/write permissions for data protection or define execute permissions for code protection. Each compa-  
rator can define an address region by a range between two points (ER=1) or by one point with a mask (EM=1).  
BIT[13:12]: CTC[1:0] - Comparator Type Config  
CTC  
CMP1  
IA  
CMP0  
IA  
Break Function  
MPU Function  
0
1
2
4 instruction break points  
2 regions for code protection  
(x permissions)  
OA  
OA  
OA  
IA  
4 operand break points  
2 regions for data protection  
(rw permissions)  
2 instruction break points +  
2 operand break points  
1 region for code protection  
(x permissions) and  
1 region for data protection  
(rw permissions) or  
1 region for combined code  
and data protection  
(rwx permissions)  
3
OA  
DT  
2 operand break points +  
2 data value breaks,  
not applicable  
normally with combination  
One group of channels contains 2 range comparator blocks. Each comparator block can detect a range hit between  
two points or two independent point hits. The point configuration is stored in dedicated BADx registsers for each  
channel (4 BADx registers for each group of channels).  
The comparator type configuration (CTC) controls the input multiplexing of the compare value for each of the two  
range comparator blocks CMP1 and CMP0. CMP1 combines the break detection channels 3 and 2. The compare  
value for CMP1 can be assigned either to the instruction address (IA) or to the operand address (OA). CMP0 com-  
bines the break detection channels 1 and 0. The compare value for CMP0 can be assigned to the instruction ad-  
dress (IA), to the operand address (OA) or to the data value (DT). The table above defines the input compare values  
for CMP1 and CMP0, depending on the CTC setting.  
In addition a mask for each comparator block could be defined (see the definition of the EM bits later). In this case  
the BADx register, which contains the mask information, is not available for the point configuration. Thus the usage  
of the mask feature restricts the number of points or channels, which are available in total.  
BIT[11:8]: OBS[1:0], OBT[1:0] - Operand Break Size / Operand Break Type register 1  
Datasize  
Access type  
OBT0  
OBS1  
OBS0  
OBT1  
0
0
Byte (Default)  
0
0
Read (Default)  
0
1
1
0
Halfword  
Word  
0
1
1
0
Read-Modify-Write  
Write  
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Chapter 29 MPU / EDSU  
4.Registers  
Datasize  
Access type  
OBT0  
OBS1  
OBS0  
OBT1  
1
1
All (Byte, Hword, Word)  
1
1
All (Read, RMW, Write)  
The operand break size register OBS configures the datasize and the operand break type register OBT configures  
the access type if the channel is configured to operand address break or data value break detection.  
Setting to ’all’ in datasize will cause detection of byte, halfword and word data sizes. Setting to ’all’ in access type  
will cause detection of Read, Read-Modify-Write and Write access types.  
Enable Break Point Register  
BIT[7]: EP3 - Enable break Point 3 register  
0
1
Break point 3 register is disabled (default)  
Break point 3 register is enabled  
If EP3 is enabled then the input value of CMP1 will be compared with the point 3 register content (BAD index =  
3+group offset, BAD3 for group 0 channel 3, BAD7 for group 1 channel 3, ...).  
The input value and the point value is masked if the mask function is enabled by EM1. On a compare match a break  
exception will be executed. CTC and MPE control the selection of the input value and the type of the break excep-  
tion.  
BIT[6]: EP2 - Enable break Point 2 register  
0
1
Break point 2 register is disabled (default)  
Break point 2 register is enabled  
If EP2 is enabled then the input value of CMP1 will be compared with the point 2 register content (BAD index =  
2+group offset, BAD2 for group 0 channel 2, BAD6 for group 1 channel 2, ...).  
The input value and the point value is masked if the mask function is enabled by EM1. On a compare match a break  
exception will be executed. CTC and MPE control the selection of the input value and the type of the break excep-  
tion.  
EP2 controls in addition to enabling and allocating point 2 the selection of the mask register. Point 2 is also the de-  
fault place for storing the CMP1 mask value. But, if point 2 is enabled, the mask could not be stored there and the  
mask input of CMP1 switches to point 0 (to the opposite comparator).  
BIT[5]: EP1 - Enable break Point 1 register  
0
1
Break point 1 register is disabled (default)  
Break point 1 register is enabled  
If EP1 is enabled then the input value of CMP0 will be compared with the point 1 register content (BAD index =  
1+group offset, BAD1 for group 0 channel 1, BAD5 for group 1 channel 1, ...).  
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Chapter 29 MPU / EDSU  
4.Registers  
The input value and the point value is masked if the mask function is enabled by EM0. On a compare match a break  
exception will be executed. CTC and MPE control the selection of the input value and the type of the break excep-  
tion.  
BIT[4]: EP0 - Enable break Point 0 register  
0
1
Break point 0 register is disabled (default)  
Break point 0 register is enabled  
If EP0 is enabled then the input value of CMP0 will be compared with the point 0 register content (BAD index =  
0+group offset, BAD0 for group 0 channel 0, BAD4 for group 1 channel 0, ...).  
The input value and the point value is masked if the mask function is enabled by EM0. On a compare match a break  
exception will be executed. CTC and MPE control the selection of the input value and the type of the break excep-  
tion.  
EP0 controls in addition to enabling and allocating point 0 the selection of the mask register. Point 0 is also the de-  
fault place for storing the CMP0 mask value. But, if point 0 is enabled, the mask could not be stored there and the  
mask input of CMP0 switches to point 2 (to the opposite comparator).  
If memory protection is enabled (MPE=1) in conjunction with the combination bit set (COMB=1), the address range  
is defined by point 3 and point 2 and is valid for both comparators COMB1 and COMB0. So the points 1 and 0 are  
not required for the range definition of CMP0, independent from the point enable EP0 and EP1, which normally are  
set in this case. Thus point 0 could be used for storing the mask value for both comparators CMP1 and CMP0 and  
the exception described in the paragraph above did not apply for this case.  
Enable Mask And Range Register  
BIT[3]: EM1 - Enable Mask for CMP1  
0
1
Mask function for CMP1 is disabled (default)  
Mask function for CMP1 is enabled  
If EM1 is enabled the comparator CMP1 matches only these bit positions, which are set to ’0’ and are not masked  
by the mask register. All inputs for points and the compare value itself are OR-combined with the value from the  
mask register. The compare operations point match or range detection are derived based on these OR-masked val-  
ues.  
The selection of the appropriate BADx register (point 2 or 0) for the mask value depends on EP2 and ER1. If at least  
one of both bits are enabled, the mask usage switches to point 0 due to the allocation of point 2. Otherwise the  
default mask stored in point 2 applies for CMP1.  
BIT[2]: EM0 - Enable Mask for CMP0  
0
1
Mask function for CMP0 is disabled (default)  
Mask function for CMP0 is enabled  
If EM0 is enabled the comparator CMP0 matches only these bit positions, which are set to ’0’ and are not masked  
by the mask register. All inputs for points and the compare value itself are OR-combined with the value from the  
mask register. The compare operations point match or range detection are derived based on these OR-masked val-  
ues.  
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Chapter 29 MPU / EDSU  
4.Registers  
The selection of the appropriate BADx register (point 0 or 2) for the mask value depends on EP0 and ER0. If at least  
one of both bits are enabled, the mask usage switches to point 2 due to the allocation of point 0. Otherwise the  
default mask stored in point 0 applies for CMP0. If MPE=1 and COMB=1 the mask is taken from point 0, regardless  
of the setting of EP0 and ER0.  
BIT[1]: ER1 - Enable Range for CMP1  
0
1
Range detection CMP1 (channels 2-3) is disabled (default)  
Range detection CMP1 (channels 2-3) is enabled  
If ER1 is enabled then the registers BADx, point 3 and point 2 will be used for range comparison:  
Point 2 <= Compare Value <= Point 3.  
If a mask is set with EM1 then both point registers will be masked with the mask register content.  
Point 3 and Point 2 are taken from BAD[x+3] and BAD[x+2], the mask is stored in Point 0, BAD[x+0].  
The ’x’ is the group offset and calculates by the group index multiplied with 4.  
BIT[0]: ER0 - Enable Range for CMP0  
0
1
Range detection CMP0 (channels 0-1) is disabled (default)  
Range detection CMP0 (channels 0-1) is enabled  
If ER0 is enabled then the registers BADx, point 1 and point 0 will be used for range comparison:  
Point 0 <= Compare Value <= Point 1.  
If a mask is set with EM0 then both point registers will be masked with the mask register content.  
In the special case of MPE=1 together with COMB=1, Point 1 and Point 0 are taken from the opposite channel  
BAD[x+3] and BAD[x+2] and the mask is stored in Point 0, BAD[x+0]. Otherwise Point 1 and Point 0 are taken from  
BAD[x+1] and BAD[x+0], the mask is stored in Point 2, BAD[x+2].  
The ’x’ is the group offset and calculates by the group index multiplied with 4.  
● Break Address/Data register (BAD0...BAD31)  
The BADx registers define 32 break point addresses, data values or mask information for the 8 groups of channels.  
For each group of channels there are 4 dedicated BAD registers. BAD0, BAD1, BAD2 and BAD3 belong to Group  
0, BAD4, BAD5, BAD6 and BAD7 belong to Group 1 and so on. The functionality described below for the registers  
of group 0 is representative for all the other groups too. The index of the BADx registers has to be incremented by  
4 for each of the next group indexes.  
BAD0 (BAD4, BAD8, ..., BAD28) [R/W]  
Address  
F080  
+0  
+1  
+2  
+3  
XXXXXXXX  
XXXXXXXX  
XXXXXXXX  
XXXXXXXX  
H
This register sets the 32 bit comparison value for break point 0 of CMP0. In range mode (set with ER0) the register  
value of BAD0 functions as lower address limit. In addition BAD0 could be used as mask register.  
In the special case of MPE=1 and COMB=1 BAD0 is not used for the point definition. CMP0 gets its point configu-  
ration then from BAD2.  
427  
Chapter 29 MPU / EDSU  
4.Registers  
BAD1 (BAD5 BAD9, ..., BAD29) [R/W]  
Address  
+0  
XXXXXXXX  
+1  
+2  
+3  
F084  
XXXXXXXX  
XXXXXXXX  
XXXXXXXX  
H
This register sets the 32 bit comparison value for break point 1 of CMP0. In range mode (set with ER0) the register  
value of BAD1 functions as upper address limit.  
In the special case of MPE=1 and COMB=1 BAD1 is not used for the point definition. CMP0 gets its point configu-  
ration then from BAD3.  
BAD2 (BAD6, BAD10, ..., BAD30) [R/W]  
Address  
F088  
+0  
+1  
+2  
+3  
XXXXXXXX  
XXXXXXXX  
XXXXXXXX  
XXXXXXXX  
H
This register sets the 32 bit comparison value for break point 2 of CMP1. In range mode (set with ER1) the register  
value of BAD2 functions as lower address limit. In addition BAD2 could be used as mask register.  
BAD3 (BAD7, BAD11, ..., BAD31) [R/W]  
Address  
F08C  
+0  
+1  
+2  
+3  
XXXXXXXX  
XXXXXXXX  
XXXXXXXX  
XXXXXXXX  
H
This register sets the 32 bit comparison value for break point 3 of CMP1. In range mode (set with ER1) the register  
value of BAD3 functions as upper address limit.  
428  
Chapter 29 MPU / EDSU  
5.Quick Reference  
5. Quick Reference  
Figure 5-1 Register Quick Reference  
429  
 
Chapter 29 MPU / EDSU  
5.Quick Reference  
BCR1  
BCR1  
OBS1  
OBS−Match  
BAD7  
BAD6  
Point 3  
Point 2  
Mask 1  
Value  
IA/OA  
CMP1  
BD3  
BD2  
BD7  
BD6  
IA  
OA  
Comparator GROUP 1  
BAD5  
BAD4  
Point 1  
Point 0  
Mask 0  
Value  
IA/OA/DT  
CMP0  
BD1  
BD0  
BD5  
BD4  
IA  
OA  
DT  
BCR0  
BCR0  
OBS0  
OBS−Match  
BAD3  
BAD2  
Point 3  
Point 2  
Mask 1  
Value  
IA/OA  
CMP1  
BD3  
BD2  
BD3  
BD2  
IA  
OA  
Comparator GROUP 0  
BAD1  
BAD0  
Point 1  
Point 0  
Mask 0  
Value  
IA/OA/DT  
CMP0  
BD1  
BD0  
BD1  
BD0  
IA  
OA  
DT  
Figure 5-2 Comparator Group Structure (drawn for two groups)  
430  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Chapter 30 I/O Ports  
1. I/O Ports Functions  
For enabling the resource functions, please refer to section ........  
Circuit  
Type  
Pin Name  
I/O Signal  
Function  
INITX  
RSTX  
HSTX  
NMIX  
INITX  
RSTX  
HSTX  
NMIX  
MD2  
TC02_0 Reset input, low active  
TC01_0 Reset input, low active  
TC00_0 Hardware Standby input, low active  
TC01_0 Non-maskable Interrupt input, low active  
TC02_1 Mode Pin 2  
MD2  
MD1  
MD1  
TC02_1 Mode Pin 1  
MD0  
MD0  
TC02_1 Mode Pin 0  
X0  
X0  
TO00_0 Main Oscillation input  
TO00_1 Main Oscillation output  
TO01_0 Sub Oscillation input  
TO01_1 Sub Oscillation output  
TA02_0 ALARM comparator input channel 0  
TA02_0 ALARM comparator input channel 1  
TC01_0 EDSU BREAK input, low active  
TC10_0 Clock Monitor Output  
Port 00  
X1  
X1  
X0A  
X0A  
X1A  
X1A  
ALARM0  
ALARM1  
EBREAKX  
MONCLK  
ALARM0  
ALARM1  
EBREAKX  
MONCLK  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P00_7  
D31  
P00_7  
P00_6  
P00_5  
P00_4  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
I/O pin for bit 31 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P00_6  
D30  
I/O pin for bit 30 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P00_5  
D29  
I/O pin for bit 29 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P00_4  
D28  
I/O pin for bit 28 of the external data bus. This function is enabled when the  
external bus is enabled.  
431  
     
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P00_3  
I/O Signal  
Function  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P00_3  
D27  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
I/O pin for bit 27 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P00_2  
D26  
P00_2  
P00_1  
P00_0  
I/O pin for bit 26 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P00_1  
D25  
I/O pin for bit 25 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P00_0  
D24  
I/O pin for bit 24 of the external data bus. This function is enabled when the  
external bus is enabled.  
Port 01  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P01_7  
D23  
P01_7  
P01_6  
P01_5  
P01_4  
P01_3  
P01_2  
P01_1  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
I/O pin for bit 23 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P01_6  
D22  
I/O pin for bit 22 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P01_5  
D21  
I/O pin for bit 21 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P01_4  
D20  
I/O pin for bit 20 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P01_3  
D19  
I/O pin for bit 19 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P01_2  
D18  
I/O pin for bit 18 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P01_1  
D17  
I/O pin for bit 17 of the external data bus. This function is enabled when the  
external bus is enabled.  
432  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P01_0  
I/O Signal  
Function  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P01_0  
D16  
TP04_0  
I/O pin for bit 16 of the external data bus. This function is enabled when the  
external bus is enabled.  
Port 02  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P02_7  
D15  
P02_7  
P02_6  
P02_5  
P02_4  
P02_3  
P02_2  
P02_1  
P02_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
I/O pin for bit 15 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P02_6  
D14  
I/O pin for bit 14 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P02_5  
D13  
I/O pin for bit 13 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P02_4  
D12  
I/O pin for bit 12 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P02_3  
D11  
I/O pin for bit 11 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P02_2  
D10  
I/O pin for bit 10 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P02_1  
D9  
I/O pin for bit 9 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P02_0  
D8  
I/O pin for bit 8 of the external data bus. This function is enabled when the  
external bus is enabled.  
Port 03  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P03_7  
D7  
P03_7  
P03_6  
TP04_0  
TP04_0  
I/O pin for bit 7 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P03_6  
D6  
I/O pin for bit 6 of the external data bus. This function is enabled when the  
external bus is enabled.  
433  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P03_5  
I/O Signal  
Function  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P03_5  
D5  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
I/O pin for bit 5 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P03_4  
D4  
P03_4  
P03_3  
P03_2  
P03_1  
P03_0  
I/O pin for bit 4 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P03_3  
D3  
I/O pin for bit 3 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P03_2  
D2  
I/O pin for bit 2 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P03_1  
D1  
I/O pin for bit 1 of the external data bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P03_0  
D0  
I/O pin for bit 0 of the external data bus. This function is enabled when the  
external bus is enabled.  
Port 04  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P04_7  
A31  
P04_7  
P04_6  
P04_5  
P04_4  
P04_3  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
I/O pin for bit 31 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P04_6  
A30  
I/O pin for bit 30 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P04_5  
A29  
I/O pin for bit 29 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P04_4  
A28  
I/O pin for bit 28 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P04_3  
A27  
I/O pin for bit 27 of the external address bus. This function is enabled when  
the external bus is enabled.  
434  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P04_2  
I/O Signal  
Function  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P04_2  
A26  
TP04_0  
TP04_0  
TP04_0  
I/O pin for bit 26 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P04_1  
A25  
P04_1  
P04_0  
I/O pin for bit 25 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P04_0  
A24  
I/O pin for bit 24 of the external address bus. This function is enabled when  
the external bus is enabled.  
Port 05  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P05_7  
A23  
P05_7  
P05_6  
P05_5  
P05_4  
P05_3  
P05_2  
P05_1  
P05_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
I/O pin for bit 23 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P05_6  
A22  
I/O pin for bit 22 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P05_5  
A21  
I/O pin for bit 21 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P05_4  
A20  
I/O pin for bit 20 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P05_3  
A19  
I/O pin for bit 19 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P05_2  
A18  
I/O pin for bit 18 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P05_1  
A17  
I/O pin for bit 17 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P05_0  
A16  
I/O pin for bit 16 of the external address bus. This function is enabled when  
the external bus is enabled.  
Port 06  
435  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P06_7  
I/O Signal  
Function  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P06_7  
A15  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
I/O pin for bit 15 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P06_6  
A14  
P06_6  
P06_5  
P06_4  
P06_3  
P06_2  
P06_1  
P06_0  
I/O pin for bit 14 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P06_5  
A13  
I/O pin for bit 13 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P06_4  
A12  
I/O pin for bit 12 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P06_3  
A11  
I/O pin for bit 11 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P06_2  
A10  
I/O pin for bit 10 of the external address bus. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P06_1  
A9  
I/O pin for bit 9 of the external address bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P06_0  
A8  
I/O pin for bit 8 of the external address bus. This function is enabled when the  
external bus is enabled.  
Port 07  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P07_7  
A7  
P07_7  
P07_6  
P07_5  
TP04_0  
TP04_0  
TP04_0  
I/O pin for bit 7 of the external address bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P07_6  
A6  
I/O pin for bit 6 of the external address bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P07_5  
A5  
I/O pin for bit 5 of the external address bus. This function is enabled when the  
external bus is enabled.  
436  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P07_4  
I/O Signal  
Function  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P07_4  
A4  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
I/O pin for bit 4 of the external address bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P07_3  
A3  
P07_3  
P07_2  
P07_1  
P07_0  
I/O pin for bit 3 of the external address bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P07_2  
A2  
I/O pin for bit 2 of the external address bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P07_1  
A1  
I/O pin for bit 1 of the external address bus. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P07_0  
A0  
I/O pin for bit 0 of the external address bus. This function is enabled when the  
external bus is enabled.  
Port 08  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P08_7  
RDY  
P08_7  
P08_6  
P08_5  
P08_4  
P08_3  
P08_2  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
Input pin for external wait (if RDY enabled for the corresponding CS area).  
This function is enabled when the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P08_6  
BRQ  
Input pin for external bus request (if sharing enabled for the corresponding CS  
area). This function is enabled when the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P08_5  
BGRNTX  
P08_4  
RDX  
Output pin for external bus granted (if sharing enabled for the corresponding  
CS area). This function is enabled when the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
Output pin for external bus read strobe. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P08_3  
WRX3  
P08_2  
WRX2  
Output pin for external bus write strobe. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
Output pin for external bus write strobe. This function is enabled when the  
external bus is enabled.  
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Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P08_1  
I/O Signal  
Function  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P08_1  
WRX1  
P08_0  
WRX0  
TP04_0  
TP04_0  
Output pin for external bus write strobe. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P08_0  
Output pin for external bus write strobe. This function is enabled when the  
external bus is enabled.  
Port 09  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P09_7  
CSX7  
P09_6  
CSX6  
P09_5  
CSX5  
P09_4  
CSX4  
P09_3  
CSX3  
P09_2  
CSX2  
P09_1  
CSX1  
P09_0  
CSX0  
P09_7  
P09_6  
P09_5  
P09_4  
P09_3  
P09_2  
P09_1  
P09_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
TP04_0  
Output pin for external bus chip select area 7. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
Output pin for external bus chip select area 6. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
Output pin for external bus chip select area 5. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
Output pin for external bus chip select area 4. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
Output pin for external bus chip select area 3. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
Output pin for external bus chip select area 2. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
Output pin for external bus chip select area 1. This function is enabled when  
the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
Output pin for external bus chip select area 0. This function is enabled when  
the external bus is enabled.  
Port 10  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P10_7  
P10_7  
TP04_0  
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Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P10_6  
I/O Signal  
Function  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P10_6  
MCLKE  
P10_5  
MCLKI  
MCLKI  
P10_4  
MCLKO  
MCLKO  
P10_3  
WEX  
TP04_0  
Output pin for external bus memory clock enable. This function is enabled  
when the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
Input pin for external bus memory clock. This function is enabled when the  
external bus is enabled.  
P10_5  
P10_4  
TP04_0  
Input pin for external bus memory clock (inverted input). This function is  
enabled when the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
Output pin for external bus memory clock. This function is enabled when the  
external bus is enabled.  
TP04_0  
Output pin for external bus memory clock (inverted output). This function is  
enabled when the external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P10_3  
P10_2  
P10_1  
TP04_0  
TP04_0  
TP04_0  
Output pin for external bus write strobe. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P10_2  
BAAX  
Output pin for external bus burst access. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P10_1  
ASX  
Output pin for external bus address strobe. This function is enabled when the  
external bus is enabled.  
General purpose I/O. This function is enabled in the single-chip mode or by  
setting the corresponding PFR to ‘0’.  
P10_0  
SYSCLK  
SYSCLK  
Output pin for external bus clock. This function is enabled when the external  
bus is enabled.  
P10_0  
TP04_0  
Output pin for external bus clock (inverted output). This function is enabled  
when the external bus is enabled.  
Port 11  
P11_7  
P11_6  
P11_5  
P11_4  
P11_3  
P11_2  
P11_7  
P11_6  
P11_5  
P11_4  
P11_3  
P11_2  
TP04_0 General purpose I/O.  
TP04_0 General purpose I/O.  
TP04_0 General purpose I/O.  
TP04_0 General purpose I/O.  
TP04_0 General purpose I/O.  
TP04_0 General purpose I/O.  
P11_1  
General purpose I/O.  
TP04_0  
P11_1  
IOWRX  
Output pin for DMA memory to I/O fly-by transfer.  
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Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P11_0  
I/O Signal  
Function  
P11_0  
IORDX  
General purpose I/O.  
TP04_0  
Output pin for DMA I/O to memory fly-by transfer.  
Port 12  
P12_7  
DEOP3  
P12_6  
General purpose I/O.  
P12_7  
P12_6  
TP04_0  
Output pin for DMA end of transfer.  
General purpose I/O.  
DEOTX3  
DEOP3  
P12_5  
TP04_0 Input pin for DMA transfer stop request.  
Output pin for DMA end of transfer.  
General purpose I/O.  
TP04_0  
P12_5  
P12_4  
P12_3  
DACKX3  
P12_4  
Output pin for DMA transfer request acknowledgement.  
General purpose I/O.  
TP04_0  
DREQ3  
P12_3  
Input pin for DMA transfer request.  
General purpose I/O.  
TP04_0  
DEOP2  
P12_2  
Output pin for DMA end of transfer.  
General purpose I/O.  
P12_2  
DEOTX2  
DEOP2  
P12_1  
TP04_0 Input pin for DMA transfer stop request.  
Output pin for DMA end of transfer.  
General purpose I/O.  
TP04_0  
P12_1  
P12_0  
DACKX2  
P12_0  
Output pin for DMA transfer request acknowledgement.  
General purpose I/O.  
TP04_0  
DREQ2  
Input pin for DMA transfer request.  
Port 13  
P13_7  
DEOP1  
P13_6  
General purpose I/O.  
TP04_0  
P13_7  
P13_6  
Output pin for DMA end of transfer.  
General purpose I/O.  
DEOTX1  
DEOP1  
P13_5  
TP04_0 Input pin for DMA transfer stop request.  
Output pin for DMA end of transfer.  
General purpose I/O.  
TP04_0  
P13_5  
P13_4  
P13_3  
DACKX1  
P13_4  
Output pin for DMA transfer request acknowledgement.  
General purpose I/O.  
TP04_0  
DREQ1  
P13_3  
Input pin for DMA transfer request.  
General purpose I/O.  
TP04_0  
DEOP0  
P13_2  
Output pin for DMA end of transfer.  
General purpose I/O.  
P13_2  
DEOTX0  
DEOP0  
P13_1  
TP04_0 Input pin for DMA transfer stop request.  
Output pin for DMA end of transfer.  
General purpose I/O.  
TP04_0  
P13_1  
P13_0  
DACKX0  
P13_0  
Output pin for DMA transfer request acknowledgement.  
General purpose I/O.  
TP04_0  
DREQ0  
Input pin for DMA transfer request.  
Port 14  
440  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P14_7  
I/O Signal  
Function  
P14_7  
ICU7  
General purpose I/O.  
Data sample input pin for input capture ICU 7.  
Event input pin for the reload timer RLT 7.  
TP00_0  
TP00_0  
TP00_0  
TP00_0  
TP00_0  
TP00_0  
TP00_0  
TP00_0  
TIN7  
TTG15/7  
P14_6  
ICU6  
Event input pin for the programmable pulse generators PPG 15 and PPG 7.  
General purpose I/O.  
Data sample input pin for input capture ICU 6.  
Event input pin for the reload timer RLT 6.  
P14_6  
P14_5  
P14_4  
P14_3  
P14_2  
P14_1  
P14_0  
TIN6  
TTG14/6  
P14_5  
ICU5  
Event input pin for the programmable pulse generators PPG 14 and PPG 6.  
General purpose I/O.  
Data sample input pin for input capture ICU 5.  
Event input pin for the reload timer RLT 5.  
TIN5  
TTG13/5  
P14_4  
ICU4  
Event input pin for the programmable pulse generators PPG 13 and PPG 5.  
General purpose I/O.  
Data sample input pin for input capture ICU 4.  
Event input pin for the reload timer RLT 4.  
TIN4  
TTG12/4  
P14_3  
ICU3  
Event input pin for the programmable pulse generators PPG 12 and PPG 4.  
General purpose I/O.  
Data sample input pin for input capture ICU 3.  
Event input pin for the reload timer RLT 3.  
TIN3  
TTG11/3  
P14_2  
ICU2  
Event input pin for the programmable pulse generators PPG 11 and PPG 3.  
General purpose I/O.  
Data sample input pin for input capture ICU 2.  
Event input pin for the reload timer RLT 2.  
TIN2  
TTG10/2  
P14_1  
ICU1  
Event input pin for the programmable pulse generators PPG 10 and PPG 2.  
General purpose I/O.  
Data sample input pin for input capture ICU 1.  
Event input pin for the reload timer RLT 1.  
TIN1  
TTG9/1  
P14_0  
ICU0  
Event input pin for the programmable pulse generators PPG 9 and PPG 1.  
General purpose I/O.  
Data sample input pin for input capture ICU 0.  
Event input pin for the reload timer RLT 0.  
TIN0  
TTG8/0  
Event input pin for the programmable pulse generators PPG 8 and PPG 0.  
Port 15  
P15_7  
OCU7  
TOT7  
P15_6  
OCU6  
TOT6  
General purpose I/O.  
P15_7  
P15_6  
TP00_0 Waveform output pin for output compare OCU 7.  
Output pin for the reload timer RLT 7.  
General purpose I/O.  
TP00_0 Waveform output pin for output compare OCU 6.  
Output pin for the reload timer RLT 6.  
441  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P15_5  
I/O Signal  
Function  
P15_5  
OCU5  
TOT5  
P15_4  
OCU4  
TOT4  
P15_3  
OCU3  
TOT3  
P15_2  
OCU2  
TOT2  
P15_1  
OCU1  
TOT1  
P15_0  
OCU0  
TOT0  
General purpose I/O.  
TP00_0 Waveform output pin for output compare OCU 5.  
Output pin for the reload timer RLT 5.  
General purpose I/O.  
P15_4  
P15_3  
P15_2  
P15_1  
P15_0  
TP00_0 Waveform output pin for output compare OCU 4.  
Output pin for the reload timer RLT 4.  
General purpose I/O.  
TP00_0 Waveform output pin for output compare OCU 3.  
Output pin for the reload timer RLT 3.  
General purpose I/O.  
TP00_0 Waveform output pin for output compare OCU 2.  
Output pin for the reload timer RLT 2.  
General purpose I/O.  
TP00_0 Waveform output pin for output compare OCU 1.  
Output pin for the reload timer RLT 1.  
General purpose I/O.  
TP00_0 Waveform output pin for output compare OCU 0.  
Output pin for the reload timer RLT 0.  
Port 16  
P16_7  
PPG15  
ATGX  
P15_6  
PPG14  
PFM  
General purpose I/O.  
P16_7  
P16_6  
P16_5  
P16_4  
TP00_0 Waveform output pin for programmable pulse generator PPG 15.  
A/D converter external trigger input.  
General purpose I/O.  
TP00_0 Waveform output pin for programmable pulse generator PPG 14.  
Waveform output pin for pulse frequency modulator PFM.  
General purpose I/O.  
P15_5  
PPG13  
SGO  
TP00_0 Waveform output pin for programmable pulse generator PPG 13.  
Waveform output pin for sound generator SG.  
General purpose I/O.  
P15_4  
PPG12  
SGA  
TP00_0 Waveform output pin for programmable pulse generator PPG 12.  
Amplitude output pin for sound generator SG.  
P15_3  
PPG11  
P15_2  
PPG10  
P15_1  
PPG9  
P15_0  
PPG8  
General purpose I/O.  
P16_3  
P16_2  
P16_1  
P16_0  
TP00_0  
Waveform output pin for programmable pulse generator PPG 11.  
General purpose I/O.  
TP00_0  
Waveform output pin for programmable pulse generator PPG 10.  
General purpose I/O.  
TP00_0  
Waveform output pin for programmable pulse generator PPG 9.  
General purpose I/O.  
TP00_0  
Waveform output pin for programmable pulse generator PPG 8.  
Port 17  
442  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P17_7  
P17_6  
P17_5  
P17_4  
P17_3  
P17_2  
P17_1  
P17_0  
I/O Signal  
Function  
P17_7  
PPG7  
P17_6  
PPG6  
P17_5  
PPG5  
P17_4  
PPG4  
P17_3  
PPG3  
P17_2  
PPG2  
P17_1  
PPG1  
P17_0  
PPG0  
General purpose I/O.  
TP00_0  
TP00_0  
TP00_0  
TP00_0  
TP00_0  
TP00_0  
TP00_0  
TP00_0  
Waveform output pin for programmable pulse generator PPG 7.  
General purpose I/O.  
Waveform output pin for programmable pulse generator PPG 6.  
General purpose I/O.  
Waveform output pin for programmable pulse generator PPG 5.  
General purpose I/O.  
Waveform output pin for programmable pulse generator PPG 4.  
General purpose I/O.  
Waveform output pin for programmable pulse generator PPG 3.  
General purpose I/O.  
Waveform output pin for programmable pulse generator PPG 2.  
General purpose I/O.  
Waveform output pin for programmable pulse generator PPG 1.  
General purpose I/O.  
Waveform output pin for programmable pulse generator PPG 0.  
Port 18  
P18_7  
P18_6  
P18_7  
TP00_0 General purpose I/O.  
General purpose I/O.  
P18_6  
SCK7  
ZIN3  
Clock I/O pin for LIN-USART 7.  
TP00_0  
8-bit reset input pin of the Up-/Down Counter UDC 2/3.  
Input for the 16-bit I/O Timer FRT 7.  
General purpose I/O.  
CK7  
P18_5  
SOT7  
BIN3  
P18_5  
TP00_0 Serial data output pin for LIN-USART 7.  
8-bit down-count input pin of the Up-/Down Counter UDC 2/3.  
General purpose I/O.  
P18_4  
SIN7  
P18_4  
P18_3  
TP00_0 Serial data input pin for LIN-USART 7.  
8-bit up-count input pin of the Up-/Down Counter UDC 2/3.  
AIN3  
P18_3  
TP00_0 General purpose I/O.  
General purpose I/O.  
P18_2  
SCK6  
ZIN2  
Clock I/O pin for LIN-USART 6.  
TP00_0  
P18_2  
8/16-bit reset input pin of the Up-/Down Counter UDC 2/3.  
CK6  
Input for the 16-bit I/O Timer FRT 6.  
General purpose I/O.  
P18_1  
SOT6  
BIN2  
P18_1  
P18_0  
TP00_0 Serial data output pin for LIN-USART 6.  
8/16-bit down-count input pin of the Up-/Down Counter UDC 2/3.  
General purpose I/O.  
P18_0  
SIN6  
TP00_0 Serial data input pin for LIN-USART 6.  
8/16-bit up-count input pin of the Up-/Down Counter UDC 2/3.  
AIN2  
Port 19  
443  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P19_7  
I/O Signal  
Function  
P19_7  
TP00_0 General purpose I/O.  
P19_6  
SCK5  
CK5  
General purpose I/O.  
P19_6  
P19_5  
TP00_0 Clock I/O pin for LIN-USART 5.  
Input for the 16-bit I/O Timer FRT 5.  
General purpose I/O.  
P19_5  
SOT5  
P19_4  
SIN5  
TP00_0  
TP00_0  
Serial data output pin for LIN-USART 5.  
General purpose I/O.  
P19_4  
P19_3  
Serial data input pin for LIN-USART 5.  
P19_3  
TP00_0 General purpose I/O.  
P19_2  
SCK4  
CK4  
General purpose I/O.  
P19_2  
TP00_0 Clock I/O pin for LIN-USART 4.  
Input for the 16-bit I/O Timer FRT 4.  
P19_1  
SOT4  
P19_0  
SIN4  
General purpose I/O.  
TP00_0  
P19_1  
P19_0  
Serial data output pin for LIN-USART 4.  
General purpose I/O.  
TP00_0  
Serial data input pin for LIN-USART 4.  
Port 20  
P20_7  
P20_6  
P20_7  
TP00_0 General purpose I/O.  
General purpose I/O.  
P20_6  
SCK3  
ZIN1  
Clock I/O pin for LIN-USART 3.  
TP00_0  
8-bit reset input pin of the Up-/Down Counter UDC 0/1.  
CK3  
Input for the 16-bit I/O Timer FRT 3.  
General purpose I/O.  
P20_5  
SOT3  
BIN1  
P20_5  
TP00_0 Serial data output pin for LIN-USART 3.  
8-bit down-count input pin of the Up-/Down Counter UDC 0/1.  
General purpose I/O.  
P20_4  
SIN3  
P20_4  
P20_3  
TP00_0 Serial data input pin for LIN-USART 3.  
8-bit up-count input pin of the Up-/Down Counter UDC 0/1.  
AIN1  
P20_3  
TP00_0 General purpose I/O.  
General purpose I/O.  
P20_2  
SCK2  
ZIN0  
Clock I/O pin for LIN-USART 2.  
TP00_0  
P20_2  
8/16-bit reset input pin of the Up-/Down Counter UDC 0/1.  
CK2  
Input for the 16-bit I/O Timer FRT 2.  
General purpose I/O.  
P20_1  
SOT2  
BIN0  
P20_1  
P20_0  
TP00_0 Serial data output pin for LIN-USART 2.  
8/16-bit down-count input pin of the Up-/Down Counter UDC 0/1.  
General purpose I/O.  
P20_0  
SIN2  
TP00_0 Serial data input pin for LIN-USART 2.  
8/16-bit up-count input pin of the Up-/Down Counter UDC 0/1.  
AIN0  
444  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
I/O Signal  
Function  
Port 21  
P21_7  
P21_6  
P21_7  
TP00_0 General purpose I/O.  
P21_6  
SCK1  
CK1  
General purpose I/O.  
TP00_0 Clock I/O pin for LIN-USART 1.  
Input for the 16-bit I/O Timer FRT 1.  
General purpose I/O.  
P21_5  
SOT1  
P21_4  
SIN1  
P21_5  
TP00_0  
TP00_0  
Serial data output pin for LIN-USART 1.  
General purpose I/O.  
P21_4  
P21_3  
Serial data input pin for LIN-USART 1.  
P21_3  
TP00_0 General purpose I/O.  
P21_2  
SCK0  
CK0  
General purpose I/O.  
P21_2  
TP00_0 Clock I/O pin for LIN-USART 0.  
Input for the 16-bit I/O Timer FRT 0.  
P21_1  
SOT0  
P21_0  
SIN0  
General purpose I/O.  
TP00_0  
P21_1  
P21_0  
Serial data output pin for LIN-USART 0.  
General purpose I/O.  
TP00_0  
Serial data input pin for LIN-USART 0.  
Port 22  
P22_7  
SCL1  
P22_6  
SDA1  
INT15  
P22_5  
SCL0  
P22_4  
SDA0  
INT14  
P22_3  
TX5  
General purpose I/O.  
TP02_0  
P22_7  
P22_6  
P22_5  
P22_4  
P22_3  
P22_2  
P22_1  
P22_0  
Serial clock I/O pin for I2C 1.  
General purpose I/O.  
TP02_0 Serial data I/O pin for I2C 1.  
External interrupt request input pin for INT 15.  
General purpose I/O.  
TP02_0  
Serial clock I/O pin for I2C 0.  
General purpose I/O.  
TP02_0 Serial data I/O pin for I2C 0.  
External interrupt request input pin for INT 14.  
General purpose I/O.  
TP00_0  
Transmission output pin for CAN 5.  
P22_2  
RX5  
General purpose I/O.  
TP00_0 Reception input pin for CAN 5.  
External interrupt request input pin for INT 13.  
INT13  
P22_1  
TX4  
General purpose I/O.  
TP00_0  
Transmission output pin for CAN 4.  
P22_0  
RX4  
General purpose I/O.  
TP00_0 Reception input pin for CAN 4.  
External interrupt request input pin for INT 12.  
INT12  
Port 23  
445  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P23_7  
I/O Signal  
Function  
P23_7  
TX3  
General purpose I/O.  
TP00_0  
Transmission output pin for CAN 3.  
General purpose I/O.  
P23_6  
RX3  
P23_6  
P23_5  
P23_4  
P23_3  
P23_2  
P23_1  
P23_0  
TP00_0 Reception input pin for CAN 3.  
External interrupt request input pin for INT 11.  
INT11  
P23_5  
TX2  
General purpose I/O.  
TP00_0  
Transmission output pin for CAN 2.  
General purpose I/O.  
P23_4  
RX2  
TP00_0 Reception input pin for CAN 2.  
External interrupt request input pin for INT 10.  
INT10  
P23_3  
TX1  
General purpose I/O.  
TP00_0  
Transmission output pin for CAN 1.  
General purpose I/O.  
P23_2  
RX1  
TP00_0 Reception input pin for CAN 1.  
External interrupt request input pin for INT 9.  
INT9  
P23_1  
TX0  
General purpose I/O.  
TP00_0  
Transmission output pin for CAN 0.  
General purpose I/O.  
P23_0  
RX0  
TP00_0 Reception input pin for CAN 0.  
External interrupt request input pin for INT 8.  
INT8  
Port 24  
P24_7  
INT7  
General purpose I/O.  
P24_7  
P24_6  
P24_5  
P24_4  
TP02_0 External interrupt request input pin for INT 7.  
Serial clock I/O pin for I2C 3.  
SCL3  
P24_6  
INT6  
General purpose I/O.  
TP02_0 External interrupt request input pin for INT 6.  
Serial data I/O pin for I2C 3.  
SDA3  
P24_5  
INT5  
General purpose I/O.  
TP02_0 External interrupt request input pin for INT 5.  
Serial clock I/O pin for I2C 2.  
SCL2  
P24_4  
INT4  
General purpose I/O.  
TP02_0 External interrupt request input pin for INT 4.  
Serial data I/O pin for I2C 2.  
SDA2  
P24_3  
INT3  
General purpose I/O.  
TP00_0  
P24_3  
P24_2  
P24_1  
P24_0  
External interrupt request input pin for INT 3.  
P24_2  
INT2  
General purpose I/O.  
TP00_0  
External interrupt request input pin for INT 2.  
P24_1  
INT1  
General purpose I/O.  
TP00_0  
External interrupt request input pin for INT 1.  
P24_0  
INT0  
General purpose I/O.  
TP00_0  
External interrupt request input pin for INT 0.  
446  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
I/O Signal  
Function  
Port 25  
P25_7  
SMC2M5  
P25_6  
General purpose I/O.  
P25_7  
P25_6  
P25_5  
P25_4  
P25_3  
P25_2  
P25_1  
P25_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
TP05_0  
PWM output 2M (-) stepper motor controller 5.  
General purpose I/O.  
SMC2P5  
P25_5  
PWM output 2P (+) stepper motor controller 5.  
General purpose I/O.  
SMC1M5  
P25_4  
PWM output 1M (-) stepper motor controller 5.  
General purpose I/O.  
SMC1P5  
P25_3  
PWM output 1P (+) stepper motor controller 5.  
General purpose I/O.  
SMC2M4  
P25_2  
PWM output 2M (-) stepper motor controller 4.  
General purpose I/O.  
SMC2P4  
P25_1  
PWM output 2P (+) stepper motor controller 4.  
General purpose I/O.  
SMC1M4  
P25_0  
PWM output 1M (-) stepper motor controller 4.  
General purpose I/O.  
SMC1P4  
PWM output 1P (+) stepper motor controller 4.  
Port 26  
P26_7  
SMC2M3  
AN31  
General purpose I/O.  
P26_7  
P26_6  
P26_5  
P26_4  
P26_3  
P26_2  
P26_1  
TP05_0 PWM output 2M (-) stepper motor controller 3.  
Analog input pin 31 for the A/D converter 1.  
General purpose I/O.  
P26_6  
SMC2P3  
AN30  
TP05_0 PWM output 2P (+) stepper motor controller 3.  
Analog input pin 30 for the A/D converter 1.  
General purpose I/O.  
P26_5  
SMC1M3  
AN29  
TP05_0 PWM output 1M (-) stepper motor controller 3.  
Analog input pin 29 for the A/D converter 1.  
General purpose I/O.  
P26_4  
SMC1P3  
AN28  
TP05_0 PWM output 1P (+) stepper motor controller 3.  
Analog input pin 28 for the A/D converter 1.  
General purpose I/O.  
P26_3  
SMC2M2  
AN27  
TP05_0 PWM output 2M (-) stepper motor controller 2.  
Analog input pin 27 for the A/D converter 1.  
General purpose I/O.  
P26_2  
SMC2P2  
AN26  
TP05_0 PWM output 2P (+) stepper motor controller 2.  
Analog input pin 26 for the A/D converter 1.  
General purpose I/O.  
P26_1  
SMC1M2  
AN25  
TP05_0 PWM output 1M (-) stepper motor controller 2.  
Analog input pin 25 for the A/D converter 1.  
447  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P26_0  
I/O Signal  
Function  
P26_0  
SMC1P2  
AN24  
General purpose I/O.  
TP05_0 PWM output 1P (+) stepper motor controller 2.  
Analog input pin 24 for the A/D converter 1.  
Port 27  
P27_7  
SMC2M1  
AN23  
General purpose I/O.  
P27_7  
P27_6  
P27_5  
P27_4  
P27_3  
P27_2  
P27_1  
P27_0  
TP05_0 PWM output 2M (-) stepper motor controller 1.  
Analog input pin 23 for the A/D converter 1.  
General purpose I/O.  
P27_6  
SMC2P1  
AN22  
TP05_0 PWM output 2P (+) stepper motor controller 1.  
Analog input pin 22 for the A/D converter 1.  
General purpose I/O.  
P27_5  
SMC1M1  
AN21  
TP05_0 PWM output 1M (-) stepper motor controller 1.  
Analog input pin 21 for the A/D converter 1.  
General purpose I/O.  
P27_4  
SMC1P1  
AN20  
TP05_0 PWM output 1P (+) stepper motor controller 1.  
Analog input pin 20 for the A/D converter 1.  
General purpose I/O.  
P27_3  
SMC2M0  
AN19  
TP05_0 PWM output 2M (-) stepper motor controller 0.  
Analog input pin 19 for the A/D converter 1.  
General purpose I/O.  
P27_2  
SMC2P0  
AN18  
TP05_0 PWM output 2P (+) stepper motor controller 0.  
Analog input pin 18 for the A/D converter 1.  
General purpose I/O.  
P27_1  
SMC1M0  
AN17  
TP05_0 PWM output 1M (-) stepper motor controller 0.  
Analog input pin 17 for the A/D converter 1.  
General purpose I/O.  
P27_0  
SMC1P0  
AN16  
TP05_0 PWM output 1P (+) stepper motor controller 0.  
Analog input pin 16 for the A/D converter 1.  
Port 28  
P28_7  
AN15  
DA1  
General purpose I/O.  
P28_7  
P28_6  
TP01_0 Analog input pin 15 for the A/D converter 1.  
Analog output pin 1 for the D/A converter 1.  
General purpose I/O.  
P28_6  
AN14  
DA0  
TP01_0 Analog input pin 14 for the A/D converter 1.  
Analog output pin 0 for the D/A converter 1.  
P28_5  
AN13  
P28_4  
AN12  
General purpose I/O.  
TP03_0  
P28_5  
P28_4  
Analog input pin 13 for the A/D converter 1.  
General purpose I/O.  
TP03_0  
Analog input pin 12 for the A/D converter 1.  
448  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P28_3  
I/O Signal  
Function  
P28_3  
AN11  
P28_2  
AN10  
P28_1  
AN9  
General purpose I/O.  
TP03_0  
TP03_0  
TP03_0  
TP03_0  
Analog input pin 11 for the A/D converter 1.  
General purpose I/O.  
P28_2  
Analog input pin 10 for the A/D converter 1.  
General purpose I/O.  
P28_1  
Analog input pin 9 for the A/D converter 1.  
General purpose I/O.  
P28_0  
AN8  
P28_0  
Analog input pin 8 for the A/D converter 1.  
Port 29  
P29_7  
AN7  
General purpose I/O.  
P29_7  
P29_6  
P29_5  
P29_4  
P29_3  
P29_2  
P29_1  
P29_0  
TP03_0  
TP03_0  
TP03_0  
TP03_0  
TP03_0  
TP03_0  
TP03_0  
TP03_0  
Analog input pin 7 for the A/D converter 1.  
General purpose I/O.  
P29_6  
AN6  
Analog input pin 6 for the A/D converter 1.  
General purpose I/O.  
P29_5  
AN5  
Analog input pin 5 for the A/D converter 1.  
General purpose I/O.  
P29_4  
AN4  
Analog input pin 4 for the A/D converter 1.  
General purpose I/O.  
P29_3  
AN3  
Analog input pin 3 for the A/D converter 1.  
General purpose I/O.  
P29_2  
AN2  
Analog input pin 2 for the A/D converter 1.  
General purpose I/O.  
P29_1  
AN1  
Analog input pin 1 for the A/D converter 1.  
General purpose I/O.  
P29_0  
AN0  
Analog input pin 0 for the A/D converter 1.  
Port 30  
P30_7  
V3  
General purpose I/O.  
P30_7  
P30_6  
P30_5  
P30_4  
P30_3  
P30_2  
P30_1  
TP08_0  
TP07_0  
TP07_0  
TP07_0  
TP06_0  
TP06_0  
TP06_0  
Analog input pin external reference voltage V3 LCD controller.  
General purpose I/O.  
P30_6  
V2  
Analog input pin external reference voltage V2 LCD controller.  
General purpose I/O.  
P30_5  
V1  
Analog input pin external reference voltage V1 LCD controller.  
General purpose I/O.  
P30_4  
V0  
Analog input pin external reference voltage V0 LCD controller.  
General purpose I/O.  
P30_3  
COM3  
P30_2  
COM2  
P30_1  
COM1  
Common driver output pin 3 LCD controller.  
General purpose I/O.  
Common driver output pin 2 LCD controller.  
General purpose I/O.  
Common driver output pin 1 LCD controller.  
449  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P30_0  
I/O Signal  
Function  
P30_0  
COM0  
General purpose I/O.  
TP06_0  
Common driver output pin 0 LCD controller.  
Port 31  
P31_7  
SEG39  
P31_6  
SEG38  
P31_5  
SEG37  
P31_4  
SEG36  
P31_3  
SEG35  
P31_2  
SEG34  
P31_1  
SEG33  
P31_0  
SEG32  
General purpose I/O.  
P31_7  
P31_6  
P31_5  
P31_4  
P31_3  
P31_2  
P31_1  
P31_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
TP06_0  
Segment driver output pin 39 LCD controller.  
General purpose I/O.  
Segment driver output pin 38 LCD controller.  
General purpose I/O.  
Segment driver output pin 37 LCD controller.  
General purpose I/O.  
Segment driver output pin 36 LCD controller.  
General purpose I/O.  
Segment driver output pin 35 LCD controller.  
General purpose I/O.  
Segment driver output pin 34 LCD controller.  
General purpose I/O.  
Segment driver output pin 33 LCD controller.  
General purpose I/O.  
Segment driver output pin 32 LCD controller.  
Port 32  
P32_7  
SEG31  
P32_6  
SEG30  
SCK15  
P32_5  
SEG29  
SOT15  
P32_4  
SEG28  
SIN15  
General purpose I/O.  
P32_7  
P32_6  
TP06_0  
Segment driver output pin 31 LCD controller.  
General purpose I/O.  
TP06_0 Segment driver output pin 30 LCD controller.  
Clock I/O pin for LIN-USART 15.  
General purpose I/O.  
P32_5  
TP06_0 Segment driver output pin 29 LCD controller.  
Serial data output pin for LIN-USART 15.  
General purpose I/O.  
P32_4  
P32_3  
P32_2  
TP06_0 Segment driver output pin 28 LCD controller.  
Serial data input pin for LIN-USART 15.  
P32_3  
SEG27  
P32_2  
SEG26  
SCK14  
P32_1  
SEG25  
SOT14  
General purpose I/O.  
TP06_0  
Segment driver output pin 27 LCD controller.  
General purpose I/O.  
TP06_0 Segment driver output pin 26 LCD controller.  
Clock I/O pin for LIN-USART 14.  
General purpose I/O.  
P32_1  
TP06_0 Segment driver output pin 25 LCD controller.  
Serial data output pin for LIN-USART 14.  
450  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P32_0  
I/O Signal  
Function  
P32_0  
SEG24  
SIN14  
General purpose I/O.  
TP06_0 Segment driver output pin 24 LCD controller.  
Serial data input pin for LIN-USART 14.  
Port 33  
P33_7  
SEG23  
P33_6  
SEG22  
SCK13  
P33_5  
SEG21  
SOT13  
P33_4  
SEG20  
SIN13  
P33_3  
SEG19  
P33_2  
SEG18  
SCK12  
P33_1  
SEG17  
SOT12  
P33_0  
SEG16  
SIN12  
General purpose I/O.  
TP06_0  
P33_7  
P33_6  
Segment driver output pin 23 LCD controller.  
General purpose I/O.  
TP06_0 Segment driver output pin 22 LCD controller.  
Clock I/O pin for LIN-USART 13.  
General purpose I/O.  
P33_5  
TP06_0 Segment driver output pin 21 LCD controller.  
Serial data output pin for LIN-USART 13.  
General purpose I/O.  
P33_4  
P33_3  
P33_2  
TP06_0 Segment driver output pin 20 LCD controller.  
Serial data input pin for LIN-USART 13.  
General purpose I/O.  
TP06_0  
Segment driver output pin 19 LCD controller.  
General purpose I/O.  
TP06_0 Segment driver output pin 18 LCD controller.  
Clock I/O pin for LIN-USART 12.  
General purpose I/O.  
P33_1  
P33_0  
TP06_0 Segment driver output pin 17 LCD controller.  
Serial data output pin for LIN-USART 12.  
General purpose I/O.  
TP06_0 Segment driver output pin 16 LCD controller.  
Serial data input pin for LIN-USART 12.  
Port 34  
P34_7  
SEG15  
P34_6  
SEG14  
SCK11  
P34_5  
SEG13  
SOT11  
P34_4  
SEG12  
SIN11  
General purpose I/O.  
TP06_0  
P34_7  
P34_6  
Segment driver output pin 15 LCD controller.  
General purpose I/O.  
TP06_0 Segment driver output pin 14 LCD controller.  
Clock I/O pin for LIN-USART 11.  
General purpose I/O.  
P34_5  
TP06_0 Segment driver output pin 13 LCD controller.  
Serial data output pin for LIN-USART 11.  
General purpose I/O.  
P34_4  
P34_3  
TP06_0 Segment driver output pin 12 LCD controller.  
Serial data input pin for LIN-USART 11.  
P34_3  
SEG11  
General purpose I/O.  
TP06_0  
Segment driver output pin 11 LCD controller.  
451  
Chapter 30 I/O Ports  
1.I/O Ports Functions  
Circuit  
Type  
Pin Name  
P34_2  
I/O Signal  
Function  
P34_2  
SEG10  
SCK10  
P34_1  
SEG9  
General purpose I/O.  
TP06_0 Segment driver output pin 10 LCD controller.  
Clock I/O pin for LIN-USART 10.  
General purpose I/O.  
P34_1  
P34_0  
TP06_0 Segment driver output pin 9 LCD controller.  
Serial data output pin for LIN-USART 10.  
General purpose I/O.  
SOT10  
P34_0  
SEG8  
TP06_0 Segment driver output pin 8 LCD controller.  
Serial data input pin for LIN-USART 10.  
SIN10  
Port 35  
P35_7  
SEG7  
P35_6  
SEG6  
SCK9  
P35_5  
SEG5  
SOT9  
P35_4  
SEG4  
SIN9  
General purpose I/O.  
TP06_0  
P35_7  
P35_6  
Segment driver output pin 7 LCD controller.  
General purpose I/O.  
TP06_0 Segment driver output pin 6 LCD controller.  
Clock I/O pin for LIN-USART 9.  
General purpose I/O.  
P35_5  
TP06_0 Segment driver output pin 5 LCD controller.  
Serial data output pin for LIN-USART 9.  
General purpose I/O.  
P35_4  
P35_3  
P35_2  
TP06_0 Segment driver output pin 4 LCD controller.  
Serial data input pin for LIN-USART 9.  
P35_3  
SEG3  
P35_2  
SEG2  
SCK8  
P35_1  
SEG1  
SOT8  
P35_0  
SEG0  
SIN8  
General purpose I/O.  
TP06_0  
Segment driver output pin 3 LCD controller.  
General purpose I/O.  
TP06_0 Segment driver output pin 2 LCD controller.  
Clock I/O pin for LIN-USART 8.  
General purpose I/O.  
P35_1  
P35_0  
TP06_0 Segment driver output pin 1 LCD controller.  
Serial data output pin for LIN-USART 8.  
General purpose I/O.  
TP06_0 Segment driver output pin 0 LCD controller.  
Serial data input pin for LIN-USART 8.  
452  
Chapter 30 I/O Ports  
2.I/O Circuit Types  
2. I/O Circuit Types  
2.1 I/O Cell List MB91V460  
Input  
Analog  
Line  
Output  
Driver  
CMOS (C)  
CMOS Hysteresis (CH)  
Automotive (AH)  
Type  
Comment  
Pull Up / Down  
(50 kOhm)  
Input Stop  
TP00_0  
TP01_0  
TP02_0  
TP03_0  
TP04_0  
TP05_0  
TP06_0  
TP07_0  
TP08_0  
TC00_0  
Up/Down switch  
CH / AH switch  
CH / AH switch  
CH / AH switch  
CH / AH switch  
CH / AH / TTL Switch  
CH / AH switch  
CH / AH switch  
CH / AH switch  
CH / AH switch  
CCH  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
Stop  
-
-
4 mA  
4 mA  
3 mA  
4 mA  
4 mA  
30 mA  
4 mA  
4 mA  
4 mA  
-
-
-
In/Out  
ADC / DAC  
I2C  
-
-
Input  
-
Up/Down switch  
AN  
Up/Down switch  
External Bus  
SMC / ADC  
LCD COM / SEG  
LCD V0 / V1 / V2  
LCD V3  
-
-
-
-
-
Input  
-
In/Out  
In/Out  
-
HSTX  
RSTX / NMIX  
EBREAKX  
TC01_0  
Up  
CCH  
-
-
-
TC02_0  
TC02_1  
TC10_0  
TO00_0  
TO00_1  
TO01_0  
TO01_1  
TA02_0  
Up  
CCH  
-
-
-
-
INITX  
MD  
-
-
-
-
-
-
-
CCH  
-
-
-
-
-
-
-
-
-
-
8 mA  
MONCLK  
Stop  
Stop  
Stop  
Stop  
-
-
-
-
-
-
-
4 MHz Oscillator  
4 MHz Oscillator  
32 kHz Oscillator  
32 kHz Oscillator  
ALARM  
-
-
-
Input  
Note: This table shows the I/O cells used for MB91V460. Please refer to the appropriate datasheet for I/O circuits  
used on flash devices.  
Note: The most I/O cells have programmable input levels (CH / AH [/ TTL]). About the programming, see section  
Port Input Level Selection on page 498.  
Note: For the programming of input pull-up or pull-down function, see section Programmable Pull-Up/Pull Down  
Resistors on page 500.  
2.2 I/O Input Voltages (VIL/VIH)  
There are various types of input stages. The following table lists the input voltages VIL / VIH.  
Type  
Description  
VIL  
VIH  
C
CMOS input  
0.25 x VDD  
0.3 x VDD  
0.2 x VDD  
0.5 x VDD  
0.8 V  
0.65 x VDD  
0.7 x VDD  
0.8 x VDD  
0.8 x VDD  
2.1 V  
CH  
CMOS Hysteresis Trigger input (I/O Port)  
CMOS Hysteresis Trigger input (Control)  
CMOS Automotive Hysteresis Trigger input  
TTL Input  
CCH  
AH  
TTL  
453  
 
Chapter 30 I/O Ports  
3.Port Register Settings  
3. Port Register Settings  
3.1 General Rules  
For all ports, the following rules are valid:  
1. All port inputs are disabled by default to avoid transverse current floating before the ports are  
configured by software. After configuring each port pin according to its function it is necessary to enable the  
port inputs with the global port enable (PORTEN.GPORTEN). See section Port Input Enable on page 457.  
2. Each port has a Port Data Register direct read (PDRD) to sample the pin data with CLKP. This register is  
read-only.  
3. Each port has a Data Direction Register (DDR) to switch the port's input/output direction. After reset, all  
ports are input (DDR=0x00).  
•
Port Input mode (PFR = "0" and DDR = "0")  
PDRD read : Reads the sampled pin data.  
PDR read  
: Reads the sampled pin data.  
PDR write : Writes the PDR setting value, has no effect on the pin value.  
•
Port Output mode (PFR = "0" and DDR = "1")  
PDRD read : Reads the sampled pin data.  
PDR read  
: Reads the PDR register value.  
PDR write : Writes the PDR setting value to the corresponding external pins.  
4. On a Read-Modify-Write instruction (bit operations) always the PDR register is read independent of the  
Data Direction Register (DDR) settings.  
5. Certain ports have a Port Function Register (PFR) and an Extra Port Function Register (EPFR). To enable  
the function determined by EPFR=’1’ it is necessary to also set PFR=’1’. On MB91V460 the behaviour of  
setting EPFR=’1’ and PFR=’0’ equals the port input/output mode (reserved for future use).  
6. Each port has a Port Input Level Register (PILR) to bit-wise select the input level (CMOS-Hysteresis /  
Automotive [/ TTL]). The default value depends on the function of the port.  
The input level can be set in every device mode. See section Port Input Level Selection on page 498.  
7. Certain ports have programmable Pull-Ups/Pull-Downs (50 kOhm) which are enabled bit-wise by their Pull-  
Up/Pull-Down Enable Registers (PPER) and Pull-Up/Pull-Down Control Registers (PPCR). See section  
Programmable Pull-Up/Pull Down Resistors on page 500.  
8. Each port has one or two Port Function Registers: PFR and, if necessary, Extra PFR (EPFR). Together,  
they can serve up to 3 resource I/O’s per pin. See section Port Function Register Setup on page 458.  
9. Port setup controlled by the MD[2:0] pins and the mode register MODR overwrites the setup in the port  
registers. E.g. External Bus Mode overwrites port register setup. The external bus signal output can be  
disabled by setting the PFR of the pin to port mode (PFR=’0).  
10.Resource input lines are generally connected to the pin and are enabled by setting the appropriate  
functionality inside the resource. There are exceptions which are listed in Port Function Register Setup on  
page 458.  
11.External Interrupt input lines are always connected to the pin and are enabled in the External Interrupt  
unit.  
12.In STOP mode (STCR:STOP set and STCR:HIZ not set) all pins keep their state (input or output  
depending on the configuration before entering the STOP mode) and the input stages and lines are  
internally fixed to avoid transverse current. External interrupt input pins are not fixed if the corresponding  
pin is selected by using the PFR=’1’ setting and the corresponding external interrupt is enabled with the  
ENIR0, resp. ENIR1 registers. Pull-Ups and Pull-Downs are enabled.  
13.In STOP-HIZ mode (STCR:STOP and STCR:HIZ set) all pins are switching to input (high impedance state)  
and all input stages and lines are internally fixed to avoid floating. External interrupt input pins are not fixed  
if the corresponding pin is selected by using the PFR=’1’ setting and the corresponding external interrupt is  
enabled with the ENIR0, resp. ENIR1 registers. Pull-Ups and Pull-Downs are disabled.  
454  
 
Chapter 30 I/O Ports  
3.Port Register Settings  
14.Resource output lines are enabled by setting the corresponding PFR and/or EPFR bit in the port. Details  
see section Port Function Register Setup on page 458. LIN-USART outputs (SOT) must be enabled  
additionally by setting the SOE bit in the LIN-USART control.  
15.Resource bidirectional signals (e.g. SCK of the LIN-USART) are enabled by setting the corresponding  
PFR and/or EPFR bit in the port. The signal direction is controlled by the setup of the resource, e.g. via the  
output enable bits. Details see section Port Function Register Setup on page 458.  
455  
Chapter 30 I/O Ports  
3.Port Register Settings  
3.2 I/O Port Block Diagram  
Port Bus  
PILR  
EPILR  
External bus interface inputs  
Peripheral inputs  
TTL  
PDRD read  
&
&
&
Automotive  
Hysteresis  
PDRD  
CLKP  
0
1
CMOS  
Hysteresis  
STOP or  
GPORTEN  
PDR read  
PPER  
PPCR  
50 kOhm  
Pull Up/  
Down  
Control  
Out Driver  
Pin  
1. Peripheral output  
2. Peripheral output  
Output  
MUX  
PDR  
DDR  
50 kOhm  
Port  
Direction  
Control  
PFR  
EPFR  
PODR  
PDR:  
Port Data Register  
Address 0x000h + #port (Port00: 0x000h, Port01: 0x001h,...)  
Address = PDR + 0xD00h  
PDRD: Port Data Direct Register  
DDR:  
PFR:  
Data Direction Register  
Port Function Register  
Address = PDR + 0xD40h  
Address = PDR + 0xD80h  
EPFR: Extra PFR Port Function Register  
PODR: Port Output Drive Register  
Address = PDR + 0xDC0h  
Address = PDR + 0xE00h  
Address = PDR + 0xE40h  
Address = PDR + 0xE80h  
Address = PDR + 0xEC0h  
Address = PDR + 0xF00h  
optional  
optional  
optional  
optional  
optional  
optional  
PILR:  
Port Input Level selection Register  
EPILR: Port Input Level selection Register  
PPER: Port Pull up/down Enable Register  
PPCR: Port Pull up/down Control Register  
456  
Chapter 30 I/O Ports  
3.Port Register Settings  
3.3 Port Input Enable  
This section describes the Port Input Enable function.  
■ PORTEN: Port Input Enable.  
Addr  
7
-
6
-
5
-
4
-
3
-
2
-
1
0
initial  
PORTEN  
0498h  
CPORTEN GPORTEN  
R/W R/W  
---- --00  
-
-
-
-
-
-
All port inputs are disabled by default to avoid transverse current floating in the IO input stages and the  
subsequent logic. After configuring all ports according to their functional specification (input level, output drive,  
pull-up or pull-down resistor, etc.) it is mandatory to globally enable the inputs by setting the port input enable bit.  
GPORTEN  
0 - The inputs of all ports are disabled.  
1 - The inputs of all ports are enabled.  
CPORTEN  
0 - The inputs of the bootloader communication ports are disabled.  
1 - The inputs of the bootloader communication ports are enabled.  
457  
 
Chapter 30 I/O Ports  
3.Port Register Settings  
3.4 Port Function Register Setup  
This section describes the Port Function Registers of each port.  
■ P00: The functions of Port 00 are controlled by PFR00  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR00  
0D80h  
PFR00.7  
PFR00.6  
PFR00.5  
PFR00.4  
PFR00.3  
PFR00.2  
PFR00.1  
PFR00.0  
1111 1111  
EPFR00  
0DC0h  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P00[7:0] is input/output for data  
lines D[31:24]. Otherwise, the port can be used as general purpose port.  
PFR00.7  
PFR00.6  
PFR00.5  
PFR00.4  
PFR00.3  
PFR00.2  
PFR00.1  
PFR00.0  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
458  
 
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P01: The functions of Port 01 are controlled by PFR01  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR01  
0D81h  
PFR01.7  
PFR01.6  
PFR01.5  
PFR01.4  
PFR01.3  
PFR01.2  
PFR01.1  
PFR01.0  
1111 1111  
EPFR01  
0DC1h  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P01[7:0] is input/output for data  
lines D[23:16]. Otherwise, the port can be used as general purpose port.  
PFR01.7  
PFR01.6  
PFR01.5  
PFR01.4  
PFR01.3  
PFR01.2  
PFR01.1  
PFR01.0  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
459  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P02: The functions of Port 02 are controlled by PFR02  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR02  
0D82h  
PFR02.7  
PFR02.6  
PFR02.5  
PFR02.4  
PFR02.3  
PFR02.2  
PFR02.1  
PFR02.0  
1111 1111  
EPFR02  
0DC2h  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P02[7:0] is input/output for data  
lines D[15:8]. Otherwise, the port can be used as general purpose port.  
PFR02.7  
PFR02.6  
PFR02.5  
PFR02.4  
PFR02.3  
PFR02.2  
PFR02.1  
PFR02.0  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
460  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P03: The functions of Port 03 are controlled by PFR03  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR03  
0D83h  
PFR03.7  
PFR03.6  
PFR03.5  
PFR03.4  
PFR03.3  
PFR03.2  
PFR03.1  
PFR03.0  
1111 1111  
EPFR03  
0DC3h  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P03[7:0] is input/output for data  
lines D[7:0]. Otherwise, the port can be used as general purpose port.  
PFR03.7  
PFR03.6  
PFR03.5  
PFR03.4  
PFR03.3  
PFR03.2  
PFR03.1  
PFR03.0  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
461  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P04: The functions of Port 04 are controlled by PFR04  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR04  
0D84h  
PFR04.7  
PFR04.6  
PFR04.5  
PFR04.4  
PFR04.3  
PFR04.2  
PFR04.1  
PFR04.0  
1111 1111  
EPFR04  
0DC4h  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P04[7:0] is input/output for  
address lines A[31:24]. Otherwise, the port can be used as general purpose port.  
PFR04.7  
PFR04.6  
PFR04.5  
PFR04.4  
PFR04.3  
PFR04.2  
PFR04.1  
PFR04.0  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
462  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P05: The functions of Port 05 are controlled by PFR05  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR05  
0D85h  
PFR05.7  
PFR05.6  
PFR05.5  
PFR05.4  
PFR05.3  
PFR05.2  
PFR05.1  
PFR05.0  
1111 1111  
EPFR05  
0DC5h  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P05[7:0] is input/output for  
address lines A[23:16]. Otherwise, the port can be used as general purpose port.  
PFR05.7  
PFR05.6  
PFR05.5  
PFR05.4  
PFR05.3  
PFR05.2  
PFR05.1  
PFR05.0  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
463  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P06: The functions of Port 06 are controlled by PFR06  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR06  
0D86h  
PFR06.7  
PFR06.6  
PFR06.5  
PFR06.4  
PFR06.3  
PFR06.2  
PFR06.1  
PFR06.0  
1111 1111  
EPFR06  
0DC6h  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P06[7:0] is input/output for  
address lines A[15:8]. Otherwise, the port can be used as general purpose port.  
PFR06.7  
PFR06.6  
PFR06.5  
PFR06.4  
PFR06.3  
PFR06.2  
PFR06.1  
PFR06.0  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
464  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P07: The functions of Port 07 are controlled by PFR07  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR07  
0D87h  
PFR07.7  
PFR07.6  
PFR07.5  
PFR07.4  
PFR07.3  
PFR07.2  
PFR07.1  
PFR07.0  
1111 1111  
EPFR07  
0DC7h  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P07[7:0] is input/output for  
address lines A[7:0]. Otherwise, the port can be used as general purpose port.  
PFR07.7  
PFR07.6  
PFR07.5  
PFR07.4  
PFR07.3  
PFR07.2  
PFR07.1  
PFR07.0  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
465  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P08: The functions of Port 08 are controlled by PFR08  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR08  
0D88h  
PFR08.7  
PFR08.6  
PFR08.5  
PFR08.4  
PFR08.3  
PFR08.2  
PFR08.1  
PFR08.0  
1111 1111  
EPFR08  
0DC8h  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P08[7:0] is input/output for  
external bus control signals RDY, BRQ, BGRNTX, RDX, WRX[3:0]. Otherwise, the port can be used as general  
purpose port.  
PFR08.7  
PFR08.6  
PFR08.5  
PFR08.4  
PFR08.3  
PFR08.2  
PFR08.1  
PFR08.0  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port):  
External bus function is RDY  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port):  
External bus function is BRQ  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port):  
External bus function is BGRNTX  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port):  
External bus function is RDX  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port):  
External bus function is WRX3  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port):  
External bus function is WRX2  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port):  
External bus function is WRX1  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port):  
External bus function is WRX0  
466  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P09: The functions of Port 09 are controlled by PFR09  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR09  
0D89h  
PFR09.7  
PFR09.6  
PFR09.5  
PFR09.4  
PFR09.3  
PFR09.2  
PFR09.1  
PFR09.0  
1111 1111  
EPFR09  
0DC9h  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P09[7:0] is input/output for  
external bus control signals CSX[7:0]. Otherwise, the port can be used as general purpose port.  
PFR09.7  
PFR09.6  
PFR09.5  
PFR09.4  
PFR09.3  
PFR09.2  
PFR09.1  
PFR09.0  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port).  
467  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P10: The functions of Port 10 are controlled by PFR10 and EPFR10  
Addr  
7
-
6
5
4
3
2
1
0
initial  
PFR10  
0D8Ah  
PFR10.6  
PFR10.5  
PFR10.4  
PFR10.3  
PFR10.2  
PFR10.1  
PFR10.0  
-111 1111  
EPFR10  
0DCAh  
-
-
EPFR10.5 EPFR10.4  
R/W R/W  
-
-
-
EPFR10.0  
R/W  
--00 ---0  
R/W  
R/W  
R/W  
R/W  
R/W  
If the external bus interface is enabled (by mode pins MD[2:0] or mode vector), P10[7:0] is input/output for  
external bus control signals MCLKE, MCLKI, MCLKO, WEX, BAAX, ASX, SYSCLK. Otherwise, the port can be  
used as general purpose port.  
PFR10.6  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port):  
External bus function is MCLKE  
PFR10.5  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port):  
EPFR10.5 0 - External bus function is MCLKI  
1 - External bus function is MCLKI (inverted input)  
PFR10.4  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port):  
EPFR10.4 0 - External bus function is MCLKO  
1 - External bus function is MCLKO (inverted output)  
PFR10.3  
PFR10.2  
PFR10.1  
PFR10.0  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port):  
External bus function is WEX  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port):  
External bus function is BAAX  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port):  
External bus function is ASX  
0 - Port is in general purpose port mode.  
1 - Port is in external bus mode (if external bus is enabled otherwise general purpose port):  
EPFR10.4 0 - External bus function is SYSCLK  
1 - External bus function is SYSCLK (inverted output)  
468  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P11: The functions of Port 11 are controlled by PFR11  
Addr  
7
-
6
-
5
-
4
-
3
-
2
-
1
0
initial  
PFR11  
0D8Bh  
PFR11.1  
PFR11.0  
---- --00  
EPFR11  
0DCBh  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
P11[7:0] is input/output for DMA control signals IOWRX, IORDX. Otherwise, the port can be used as general  
purpose port.  
PFR11.1  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
DMA function is IOWRX output  
PFR11.0  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
DMA function is IORDX output  
469  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P12: The functions of Port 12 are controlled by PFR12 and EPFR12  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR12  
0D8Ch  
PFR12.7  
PFR12.6  
PFR12.5  
PFR12.4  
PFR12.3  
PFR12.2  
PFR12.1  
PFR12.0  
0000 0000  
EPFR12  
0DCCh  
-
EPFR12.6  
R/W  
-
-
-
EPFR12.2  
R/W  
-
-
-0-- -0--  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
P12[7:0] is input/output for DMA control signals DEOP, DEOTX, DACKX, DREQ for DMA channels 2 and 3.  
Otherwise, the port can be used as general purpose port.  
PFR12.7  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
DMA function is DEOP3 output  
PFR12.6  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
EPFR12.6 0 - DMA function is DEOTX3 input  
1 - DMA function is DEOP3 output  
PFR12.5  
PFR12.4  
PFR12.3  
PFR12.2  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
DMA function is DACKX3 output  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
DMA function is DREQ3 input  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
DMA function is DEOP2 output  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
EPFR12.2 0 - DMA function is DEOTX2 input  
1 - DMA function is DEOP2 output  
PFR12.1  
PFR12.0  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
DMA function is DACKX2 output  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
DMA function is DREQ2 input  
470  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P13: The functions of Port 13 are controlled by PFR13 and EPFR13  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR13  
0D8Dh  
PFR13.7  
PFR13.6  
PFR13.5  
PFR13.4  
PFR13.3  
PFR13.2  
PFR13.1  
PFR13.0  
0000 0000  
EPFR13  
0DCDh  
-
EPFR13.6  
R/W  
-
-
-
EPFR13.2  
R/W  
-
-
-0-- -0--  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
P13[7:0] is input/output for DMA control signals DEOP, DEOTX, DACKX, DREQ for DMA channels 0 and 1.  
Otherwise, the port can be used as general purpose port.  
PFR13.7  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
DMA function is DEOP1 output  
PFR13.6  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
EPFR13.6 0 - DMA function is DEOTX1 input  
1 - DMA function is DEOP1 output  
PFR13.5  
PFR13.4  
PFR13.3  
PFR13.2  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
DMA function is DACKX1 output  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
DMA function is DREQ1 input  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
DMA function is DEOP0 output  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
EPFR13.2 0 - DMA function is DEOTX0 input  
1 - DMA function is DEOP0 output  
PFR13.1  
PFR13.0  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
DMA function is DACKX0 output  
0 - Port is in general purpose port mode.  
1 - Port is in DMA function mode:  
DMA function is DREQ0 input  
471  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P14: The functions of Port 14 are controlled by PFR14 and EPFR14  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR14  
0D8Eh  
PFR14.7  
PFR14.6  
PFR14.5  
PFR14.4  
PFR14.3  
PFR14.2  
PFR14.1  
PFR14.0  
0000 0000  
EPFR14  
0DCEh  
EPFR14.7 EPFR14.6 EPFR14.5 EPFR14.4 EPFR14.3 EPFR14.2 EPFR14.1 EPFR14.0 0000 0000  
R/W R/W R/W R/W R/W R/W R/W R/W  
P14[7:0] is input/output for Input Capture inputs ICU[7:0], Reload Timer triggers TIN[7:0] and PWM inputs  
TTG[15:0]. Otherwise, the port can be used as general purpose port.  
PFR14.7  
PFR14.6  
PFR14.5  
PFR14.4  
PFR14.3  
PFR14.2  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is TIN7 and TTG15/7 input, and  
EPFR14.7 0 - Resource function is ICU7 input  
1 - ICU7 is internally connected to LSYN of LIN-UART 7/15  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is TIN6 and TTG14/6 input, and  
EPFR14.6 0 - Resource function is ICU6 input  
1 - ICU6 is internally connected to LSYN of LIN-UART 6/14  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is TIN5 and TTG13/5 input, and  
EPFR14.5 0 - Resource function is ICU6 input  
1 - ICU5 is internally connected to LSYN of LIN-UART 5/13  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is TIN4 and TTG12/4 input, and  
EPFR14.4 0 - Resource function is ICU4 input  
1 - ICU4 is internally connected to LSYN of LIN-UART 4/12  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is TIN3 and TTG11/3 input, and  
EPFR14.3 0 - Resource function is ICU3 input  
1 - ICU3 is internally connected to LSYN of LIN-UART 3/11  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is TIN2 and TTG10/2 input, and  
EPFR14.2 0 - Resource function is ICU2 input  
1 - ICU2 is internally connected to LSYN of LIN-UART 2/10  
PFR14.1  
472  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Chapter 30 I/O Ports  
3.Port Register Settings  
Resource function is TIN1 and TTG9/1 input, and  
EPFR14.1 0 - Resource function is ICU1 input  
1 - ICU1 is internally connected to LSYN of LIN-UART 1/9  
PFR14.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is TIN0 and TTG8/0 input, and  
EPFR14.0 0 - Resource function is ICU0 input  
1 - ICU0 is internally connected to LSYN of LIN-UART 0/8  
473  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P15: The functions of Port 15 are controlled by PFR15 and EPFR15  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR15  
0D8Fh  
PFR15.7  
PFR15.6  
PFR15.5  
PFR15.4  
PFR15.3  
PFR15.2  
PFR15.1  
PFR15.0  
0000 0000  
EPFR15  
0DCFh  
EPFR15.7 EPFR15.6 EPFR15.5 EPFR15.4 EPFR15.3 EPFR15.2 EPFR15.1 EPFR15.0 0000 0000  
R/W R/W R/W R/W R/W R/W R/W R/W  
P15[7:0] is input/output for Output Compare outputs OCU[7:0] and Reload Timer outputs TOT[7:0]. Otherwise,  
the port can be used as general purpose port.  
PFR15.7  
PFR15.6  
PFR15.5  
PFR15.4  
PFR15.3  
PFR15.2  
PFR15.1  
PFR15.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR15.7 0 - Resource function is OCU7 output  
1 - Resource function is TOT7 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR15.6 0 - Resource function is OCU6 output  
1 - Resource function is TOT6 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR15.5 0 - Resource function is OCU5 output  
1 - Resource function is TOT5 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR15.4 0 - Resource function is OCU4 output  
1 - Resource function is TOT4 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR15.3 0 - Resource function is OCU3 output  
1 - Resource function is TOT3 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR15.2 0 - Resource function is OCU2 output  
1 - Resource function is TOT2 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR15.1 0 - Resource function is OCU1 output  
1 - Resource function is TOT1 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR15.0 0 - Resource function is OCU0 output  
1 - Resource function is TOT0 output  
474  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P16: The functions of Port 16 are controlled by PFR16 and EPFR16  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR16  
0D90h  
PFR16.7  
PFR16.6  
PFR16.5  
PFR16.4  
PFR16.3  
PFR16.2  
PFR16.1  
PFR16.0  
0000 0000  
EPFR16  
0DD0h  
EPFR16.7 EPFR16.6 EPFR16.5 EPFR16.4  
R/W R/W R/W R/W  
-
-
-
-
0000 ----  
R/W  
R/W  
R/W  
R/W  
P16[7:0] is input/output for Programmable Pulse Generator outputs PPG[15:8], external ADC trigger ATGX,  
Pulse Frequency Modulator output PFM, and Sound Generator outputs SGO/SGA. Otherwise, the port can be  
used as general purpose port.  
PFR16.7  
PFR16.6  
PFR16.5  
PFR16.4  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR16.7 0 - Resource function is PPG15 output  
1 - Resource function is ATGX input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR16.6 0 - Resource function is PPG14 output  
1 - Resource function is PFM output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR16.5 0 - Resource function is PPG13 output  
1 - Resource function is SGO output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR16.4 0 - Resource function is PPG12 output  
1 - Resource function is SGA output  
PFR16.3  
PFR16.2  
PFR16.1  
PFR16.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is PPG11 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is PPG10 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is PPG9 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is PPG8 output  
475  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P17: The functions of Port 17 are controlled by PFR17  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR17  
0D91h  
PFR17.7  
PFR17.6  
PFR17.5  
PFR17.4  
PFR17.3  
PFR17.2  
PFR17.1  
PFR17.0  
0000 0000  
EPFR17  
0DD1h  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
P17[7:0] is input/output for Programmable Pulse Generator outputs PPG[15:8]. Otherwise, the port can be used  
as general purpose port.  
PFR17.7  
PFR17.6  
PFR17.5  
PFR17.4  
PFR17.3  
PFR17.2  
PFR17.1  
PFR17.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is PPG7 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is PPG6 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is PPG5 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is PPG4 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is PPG3 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is PPG2 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is PPG1 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is PPG0 output  
476  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P18: The functions of Port 18 are controlled by PFR18 and EPFR18  
Addr  
7
-
6
5
4
3
-
2
1
0
initial  
PFR18  
0D92h  
PFR18.6  
PFR18.5  
PFR18.4  
PFR18.2  
PFR18.1  
PFR18.0  
-000 -000  
EPFR18  
0DD2h  
-
EPFR18.6 EPFR18.5  
R/W R/W  
-
-
EPFR18.2 EPFR18.1  
R/W R/W  
-
-00- -00-  
R/W  
R/W  
R/W  
R/W  
P18[7:0] is input/output for LIN-UART serial communication signals SCK, SOT, SIN of channels 6 and 7, Up-/  
Down-Counter inputs ZIN, BIN, AIN of channels 2 and 3, and Free Run Timer FRT inputs CK of channels 6 and  
7. Otherwise, the port can be used as general purpose port.  
PFR18.6  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR18.6 0 - Resource function is SCK7 input/output  
1 - Resource function is ZIN3 and CK7 input  
PFR18.5  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR18.5 0 - Resource function is SOT7 output  
1 - Resource function is BIN3 input  
PFR18.4  
PFR18.2  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SIN7 and AIN3 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR18.2 0 - Resource function is SCK6 input/output  
1 - Resource function is ZIN2 and CK6 input  
PFR18.1  
PFR18.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR18.1 0 - Resource function is SOT6 output  
1 - Resource function is BIN2 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SIN6 and AIN2 input  
477  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P19: The functions of Port 19 are controlled by PFR19 and EPFR19  
Addr  
7
-
6
5
4
3
-
2
1
0
initial  
PFR19  
0D93h  
PFR19.6  
PFR19.5  
PFR19.4  
PFR19.2  
PFR19.1  
PFR19.0  
-000 -000  
EPFR19  
0DD3h  
-
EPFR19.6  
R/W  
-
-
-
EPFR19.2  
R/W  
-
-
-0-- -0--  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
P19[7:0] is input/output for LIN-UART serial communication signals SCK, SOT, SIN of channels 4 and 5, and  
Free Run Timer FRT inputs CK of channels 4 and 5. Otherwise, the port can be used as general purpose port.  
PFR19.6  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR19.6 0 - Resource function is SCK5 input/output  
1 - Resource function is CK5 input  
PFR19.5  
PFR19.4  
PFR19.2  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SOT5 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SIN5 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR19.2 0 - Resource function is SCK4 input/output  
1 - Resource function is CK4 input  
PFR19.1  
PFR19.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SOT4 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SIN4 input  
478  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P20: The functions of Port 20 are controlled by PFR20 and EPFR20  
Addr  
7
-
6
5
4
3
-
2
1
0
initial  
PFR20  
0D94h  
PFR20.6  
PFR20.5  
PFR20.4  
PFR20.2  
PFR20.1  
PFR20.0  
-000 -000  
EPFR20  
0DD4h  
-
EPFR20.6 EPFR20.5  
R/W R/W  
-
-
EPFR20.2 EPFR20.1  
R/W R/W  
-
-00- -00-  
R/W  
R/W  
R/W  
R/W  
P20[7:0] is input/output for LIN-UART serial communication signals SCK, SOT, SIN of channels 2 and 3, Up-/  
Down-Counter inputs ZIN, BIN, AIN of channels 0 and 1, and Free Run Timer FRT inputs CK of channels 2 and  
3. Otherwise, the port can be used as general purpose port.  
PFR20.6  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR20.6 0 - Resource function is SCK3 input/output  
1 - Resource function is ZIN1 and CK3 input  
PFR20.5  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR20.5 0 - Resource function is SOT3 output  
1 - Resource function is BIN1 input  
PFR20.4  
PFR20.2  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SIN3 and AIN1 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR20.2 0 - Resource function is SCK2 input/output  
1 - Resource function is ZIN0 and CK2 input  
PFR20.1  
PFR20.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR20.1 0 - Resource function is SOT2 output  
1 - Resource function is BIN0 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SIN2 and AIN0 input  
479  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P21: The functions of Port 21 are controlled by PFR21 and EPFR21  
Addr  
7
-
6
5
4
3
-
2
1
0
initial  
PFR21  
0D95h  
PFR21.6  
PFR21.5  
PFR21.4  
PFR21.2  
PFR21.1  
PFR21.0  
-000 -000  
EPFR21  
0DD5h  
-
EPFR21.6  
R/W  
-
-
-
EPFR21.2  
R/W  
-
-
-0-- -0--  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
P21[7:0] is input/output for LIN-UART serial communication signals SCK, SOT, SIN of channels 0 and 1, and  
Free Run Timer FRT inputs CK of channels 0 and 1. Otherwise, the port can be used as general purpose port.  
PFR21.6  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR21.6 0 - Resource function is SCK1 input/output  
1 - Resource function is CK1 input  
PFR21.5  
PFR21.4  
PFR21.2  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SOT1 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SIN1 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR21.2 0 - Resource function is SCK0 input/output  
1 - Resource function is CK0 input  
PFR21.1  
PFR21.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SOT0 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SIN0 input  
480  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P22: The functions of Port 22 are controlled by PFR22  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR22  
0D96h  
PFR22.7  
PFR22.6  
PFR22.5  
PFR22.4  
PFR22.3  
PFR22.2  
PFR22.1  
PFR22.0  
0000 0000  
EPFR22  
0DD6h  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
P22[7:0] is input/output for I2C serial communication signals SCL, SDA of channels 0 and 1, CAN serial  
communication signals TX, RX of channels 4 and 5, and External Interrupt Triggers INT[15:12]. Otherwise, the  
port can be used as general purpose port.  
PFR22.7  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SCL1 open drain  
PFR22.6  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SDA1 open drain, and INT15 input  
Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this  
the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and  
interrupt is enabled with ENIR1.EN15 set to ‘1’.  
PFR22.5  
PFR22.4  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SCL0 open drain  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SDA0 open drain, and INT14 input  
Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this  
the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and  
interrupt is enabled with ENIR1.EN14 set to ‘1’.  
PFR22.3  
PFR22.2  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is TX5 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is RX5 input, and INT13 input  
Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this  
the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and  
interrupt is enabled with ENIR1.EN13 set to ‘1’.  
PFR22.1  
PFR22.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is TX4 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
481  
Chapter 30 I/O Ports  
3.Port Register Settings  
Resource function is RX4 input, and INT12 input  
Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this  
the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and  
interrupt is enabled with ENIR1.EN12 set to ‘1’.  
Remark: It is generally possible to use input only resource functions (like e.g. INT, ICU, CAN.RX, UART.SIN)  
also in the Port I/O input mode (PFR=’0’ and DDR=’0’). In that case the internal input line is forced to low in  
STOP-HIZ mode.  
482  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P23: The functions of Port 23 are controlled by PFR23  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR23  
0D97h  
PFR23.7  
PFR23.6  
PFR23.5  
PFR23.4  
PFR23.3  
PFR23.2  
PFR23.1  
PFR23.0  
0000 0000  
EPFR23  
0DD7h  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
P23[7:0] is input/output for CAN serial communication signals TX, RX of channels 0 to 3, and External Interrupt  
Triggers INT[11:8]. Otherwise, the port can be used as general purpose port.  
PFR23.7  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is TX3 output  
PFR23.6  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is RX3 input, and INT11 input  
Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this  
the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and  
interrupt is enabled with ENIR1.EN11 set to ‘1’.  
PFR23.5  
PFR23.4  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is TX2 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is RX2 input, and INT10 input  
Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this  
the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and  
interrupt is enabled with ENIR1.EN10 set to ‘1’.  
PFR23.3  
PFR23.2  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is TX1 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is RX1 input, and INT9 input  
Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this  
the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and  
interrupt is enabled with ENIR1.EN9 set to ‘1’.  
PFR23.1  
PFR23.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is TX0 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
483  
Chapter 30 I/O Ports  
3.Port Register Settings  
Resource function is RX0 input, and INT8 input  
Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this  
the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and  
interrupt is enabled with ENIR1.EN8 set to ‘1’.  
Remark: It is generally possible to use input only resource functions (like e.g. INT, ICU, CAN.RX, UART.SIN)  
also in the Port I/O input mode (PFR=’0’ and DDR=’0’). In that case the internal input line is forced to low in  
STOP-HIZ mode.  
484  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P24: The functions of Port 24 are controlled by PFR24  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR24  
0D98h  
PFR24.7  
PFR24.6  
PFR24.5  
PFR24.4  
PFR24.3  
PFR24.2  
PFR24.1  
PFR24.0  
0000 0000  
EPFR24  
0DD8h  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
P24[7:0] is input/output for I2C serial communication signals SCL, SDA of channels 2 and 3, and External  
Interrupt Triggers INT[7:0]. Otherwise, the port can be used as general purpose port.  
PFR24.7  
PFR24.6  
PFR24.5  
PFR24.4  
PFR24.3  
PFR24.2  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SCL3 open drain, and INT7 input  
Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this  
the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and  
interrupt is enabled with ENIR0.EN7 set to ‘1’.  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SDA3 open drain, and INT6 input  
Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this  
the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and  
interrupt is enabled with ENIR0.EN6 set to ‘1’.  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SCL2 open drain, and INT5 input  
Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this  
the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and  
interrupt is enabled with ENIR0.EN5 set to ‘1’.  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SDA2 open drain, and INT4 input  
Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this  
the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and  
interrupt is enabled with ENIR0.EN4 set to ‘1’.  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is INT3 input  
Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this  
the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and  
interrupt is enabled with ENIR0.EN3 set to ‘1’.  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is INT2 input  
485  
Chapter 30 I/O Ports  
3.Port Register Settings  
Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this  
the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and  
interrupt is enabled with ENIR0.EN2 set to ‘1’.  
PFR24.1  
PFR24.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is INT1 input  
Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this  
the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and  
interrupt is enabled with ENIR0.EN1 set to ‘1’.  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is INT0 input  
Remark: This pin supports external interrupt wake up from STOP-HIZ mode. Because of this  
the internal input line is not forced to low in STOP-HIZ mode if the PFR is set to ‘1’ and  
interrupt is enabled with ENIR0.EN0 set to ‘1’.  
Remark: It is generally possible to use input only resource functions (like e.g. INT, ICU, CAN.RX, UART.SIN)  
also in the Port I/O input mode (PFR=’0’ and DDR=’0’). In that case the internal input line is forced to low in  
STOP-HIZ mode.  
486  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P25: The functions of Port 25 are controlled by PFR25  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR25  
0D99h  
PFR25.7  
PFR25.6  
PFR25.5  
PFR25.4  
PFR25.3  
PFR25.2  
PFR25.1  
PFR25.0  
0000 0000  
EPFR25  
0DD9h  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
P25[7:0] is input/output for Stepper Motor PWM output signals and Comparator Inputs SMC2M, SMC2P,  
SMC1M, SMC1P of channels 4 and 5. Otherwise, the port can be used as general purpose port.  
PFR25.7  
PFR25.6  
PFR25.5  
PFR25.4  
PFR25.3  
PFR25.2  
PFR25.1  
PFR25.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SMC2M5 output, CMP5 input if selected  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SMC2P5 output, CMP5 input if selected  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SMC1M5 output, CMP5 input if selected  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SMC1P5 output, CMP5 input if selected  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SMC2M4 output, CMP4 input if selected  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SMC2P4 output, CMP4 input if selected  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SMC1M4 output, CMP4 input if selected  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SMC1P4 output, CMP4 input if selected  
487  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P26: The functions of Port 26 are controlled by PFR26 and EPFR26  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR26  
0D9Ah  
PFR26.7  
PFR26.6  
PFR26.5  
PFR26.4  
PFR26.3  
PFR26.2  
PFR26.1  
PFR26.0  
0000 0000  
EPFR26  
0DDAh  
EPFR26.7 EPFR26.6 EPFR26.5 EPFR26.4 EPFR26.3 EPFR26.2 EPFR26.1 EPFR26.0 0000 0000  
R/W R/W R/W R/W R/W R/W R/W R/W  
P26[7:0] is input/output for Stepper Motor PWM output signals and Comparator Inputs SMC2M, SMC2P,  
SMC1M, SMC1P of channels 2 and 3, and A/D converter analogue inputs AN[31:24]. Otherwise, the port can be  
used as general purpose port.  
PFR26.7  
PFR26.6  
PFR26.5  
PFR26.4  
PFR26.3  
PFR26.2  
PFR26.1  
PFR26.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR26.7 0 - Resource function is SMC2M3 output, CMP3 and/or AN31 input if selected  
1 - Resource function is AN31 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR26.6 0 - Resource function is SMC2P3 output, CMP3 and/or AN30 input if selected  
1 - Resource function is AN30 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR26.5 0 - Resource function is SMC1M3 output, CMP3 and/or AN29 input if selected  
1 - Resource function is AN29 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR26.4 0 - Resource function is SMC1P3 output, CMP3 and/or AN28 input if selected  
1 - Resource function is AN28 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR26.3 0 - Resource function is SMC2M2 output, CMP2 and/or AN27 input if selected  
1 - Resource function is AN27 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR26.2 0 - Resource function is SMC2P2 output, CMP2 and/or AN26 input if selected  
1 - Resource function is AN26 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR26.1 0 - Resource function is SMC1M2 output, CMP2 and/or AN25 input if selected  
1 - Resource function is AN25 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR26.0 0 - Resource function is SMC1P2 output, CMP2 and/or AN24 input if selected  
1 - Resource function is AN24 input  
488  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P27: The functions of Port 27 are controlled by PFR27 and EPFR27  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR27  
0D9Bh  
PFR27.7  
PFR27.6  
PFR27.5  
PFR27.4  
PFR27.3  
PFR27.2  
PFR27.1  
PFR27.0  
0000 0000  
EPFR27  
0DDBh  
EPFR27.7 EPFR27.6 EPFR27.5 EPFR27.4 EPFR27.3 EPFR27.2 EPFR27.1 EPFR27.0 0000 0000  
R/W R/W R/W R/W R/W R/W R/W R/W  
P27[7:0] is input/output for Stepper Motor PWM output signals and Comparator Inputs SMC2M, SMC2P,  
SMC1M, SMC1P of channels 0 and 1, and A/D converter analogue inputs AN[23:16]. Otherwise, the port can be  
used as general purpose port.  
PFR27.7  
PFR27.6  
PFR27.5  
PFR27.4  
PFR27.3  
PFR27.2  
PFR27.1  
PFR27.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR27.7 0 - Resource function is SMC2M1 output, CMP1 and/or AN23 input if selected  
1 - Resource function is AN23 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR27.6 0 - Resource function is SMC2P1 output, CMP1 and/or AN22 input if selected  
1 - Resource function is AN22 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR27.5 0 - Resource function is SMC1M1 output, CMP1 and/or AN21 input if selected  
1 - Resource function is AN21 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR27.4 0 - Resource function is SMC1P1 output, CMP1 and/or AN20 input if selected  
1 - Resource function is AN20 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR27.3 0 - Resource function is SMC2M0 output, CMP0 and/or AN19 input if selected  
1 - Resource function is AN19 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR27.2 0 - Resource function is SMC2P0 output, CMP0 and/or AN18 input if selected  
1 - Resource function is AN18 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR27.1 0 - Resource function is SMC1M0 output, CMP0 and/or AN17 input if selected  
1 - Resource function is AN17 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR27.0 0 - Resource function is SMC1P0 output, CMP0 and/or AN16 input if selected  
1 - Resource function is AN16 input  
489  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P28: The functions of Port 28 are controlled by PFR28  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR28  
0D9Ch  
PFR28.7  
PFR28.6  
PFR28.5  
PFR28.4  
PFR28.3  
PFR28.2  
PFR28.1  
PFR28.0  
0000 0000  
EPFR28  
0DDCh  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
P28[7:0] is input/output for A/D converter analogue inputs AN[15:8], and D/A converter analogue outputs  
DA[1:0]. Otherwise, the port can be used as general purpose port.  
PFR28.7  
PFR28.6  
PFR28.5  
PFR28.4  
PFR28.3  
PFR28.2  
PFR28.1  
PFR28.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is AN15 input and/or DA1 output if D/A converter output is enabled  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is AN14 input and/or DA0 output if D/A converter output is enabled  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is AN13 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is AN12 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is AN11 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is AN10 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is AN9 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is AN8 input  
490  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P29: The functions of Port 29 are controlled by PFR29  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR29  
0D9Dh  
PFR29.7  
PFR29.6  
PFR29.5  
PFR29.4  
PFR29.3  
PFR29.2  
PFR29.1  
PFR29.0  
0000 0000  
EPFR29  
0DDDh  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
P29[7:0] is input/output for A/D converter analogue inputs AN[7:0]. Otherwise, the port can be used as general  
purpose port.  
PFR29.7  
PFR29.6  
PFR29.5  
PFR29.4  
PFR29.3  
PFR29.2  
PFR29.1  
PFR29.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is AN7 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is AN6 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is AN5 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is AN4 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is AN3 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is AN2 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is AN1 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is AN0 input  
491  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P30: The functions of Port 30 are controlled by PFR30  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR30  
0D9Eh  
PFR30.7  
PFR30.6  
PFR30.5  
PFR30.4  
PFR30.3  
PFR30.2  
PFR30.1  
PFR30.0  
0000 0000  
EPFR30  
0DDEh  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
P30[7:0] is input/output for LCD controller reference voltage analogue inputs V[3:0], and LCD controller common  
driver outputs COM[3:0]. Otherwise, the port can be used as general purpose port.  
PFR30.7  
PFR30.6  
PFR30.5  
PFR30.4  
PFR30.3  
PFR30.2  
PFR30.1  
PFR30.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is V3 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is V2 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is V1 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is V0 input  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is COM3 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is COM2 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is COM1 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is COM0 output  
492  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P31: The functions of Port 31 are controlled by PFR31  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR31  
0D9Fh  
PFR31.7  
PFR31.6  
PFR31.5  
PFR31.4  
PFR31.3  
PFR31.2  
PFR31.1  
PFR31.0  
0000 0000  
EPFR31  
0DDFh  
-
-
-
-
-
-
-
-
---- ----  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
P31[7:0] is input/output for LCD controller segment driver outputs SEG[39:32]. Otherwise, the port can be used  
as general purpose port.  
PFR31.7  
PFR31.6  
PFR31.5  
PFR31.4  
PFR31.3  
PFR31.2  
PFR31.1  
PFR31.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SEG39 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SEG38 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SEG37 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SEG36 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SEG35 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SEG34 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SEG33 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SEG32 output  
493  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P32: The functions of Port 32 are controlled by PFR32 and EPFR32  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR32  
0DA0h  
PFR32.7  
PFR32.6  
PFR32.5  
PFR32.4  
PFR32.3  
PFR32.2  
PFR32.1  
PFR32.0  
0000 0000  
EPFR32  
0DE0h  
-
EPFR32.6 EPFR32.5 EPFR32.4  
R/W R/W R/W  
-
EPFR32.2 EPFR32.1 EPFR32.0  
R/W R/W R/W  
-000 -000  
R/W  
R/W  
P32[7:0] is input/output for LCD controller segment driver outputs SEG[31:24], and LIN-UART serial  
communication signals SCK, SOT, SIN of channels 14 and 15. Otherwise, the port can be used as general  
purpose port.  
PFR32.7  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SEG31 output  
PFR32.6  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR32.6 0 - Resource function is SEG30 output  
1 - Resource function is SCK15 input/output  
PFR32.5  
PFR32.4  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR32.5 0 - Resource function is SEG29 output  
1 - Resource function is SOT15 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR32.4 0 - Resource function is SEG28 output  
1 - Resource function is SIN15 input  
PFR32.3  
PFR32.2  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SEG27 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR32.2 0 - Resource function is SEG26 output  
1 - Resource function is SCK14 input/output  
PFR32.1  
PFR32.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR32.1 0 - Resource function is SEG25 output  
1 - Resource function is SOT14 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR32.0 0 - Resource function is SEG24output  
1 - Resource function is SIN14 input  
494  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P33: The functions of Port 33 are controlled by PFR33 and EPFR33  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR33  
0DA1h  
PFR33.7  
PFR33.6  
PFR33.5  
PFR33.4  
PFR33.3  
PFR33.2  
PFR33.1  
PFR33.0  
0000 0000  
EPFR33  
0DE1h  
-
EPFR33.6 EPFR33.5 EPFR33.4  
R/W R/W R/W  
-
EPFR33.2 EPFR33.1 EPFR33.0  
R/W R/W R/W  
-000 -000  
R/W  
R/W  
P33[7:0] is input/output for LCD controller segment driver outputs SEG[23:16], and LIN-UART serial  
communication signals SCK, SOT, SIN of channels 12 and 13. Otherwise, the port can be used as general  
purpose port.  
PFR33.7  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SEG23 output  
PFR33.6  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR33.6 0 - Resource function is SEG22 output  
1 - Resource function is SCK13 input/output  
PFR33.5  
PFR33.4  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR33.5 0 - Resource function is SEG21 output  
1 - Resource function is SOT13 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR33.4 0 - Resource function is SEG20 output  
1 - Resource function is SIN13 input  
PFR33.3  
PFR33.2  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SEG19 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR33.2 0 - Resource function is SEG18 output  
1 - Resource function is SCK12 input/output  
PFR33.1  
PFR33.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR33.1 0 - Resource function is SEG17 output  
1 - Resource function is SOT12 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR33.0 0 - Resource function is SEG16 output  
1 - Resource function is SIN12 input  
495  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P34: The functions of Port 34 are controlled by PFR34 and EPFR34  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR34  
0DA2h  
PFR34.7  
PFR34.6  
PFR34.5  
PFR34.4  
PFR34.3  
PFR34.2  
PFR34.1  
PFR34.0  
0000 0000  
EPFR34  
0DE2h  
-
EPFR34.6 EPFR34.5 EPFR34.4  
R/W R/W R/W  
-
EPFR34.2 EPFR34.1 EPFR34.0  
R/W R/W R/W  
-000 -000  
R/W  
R/W  
P34[7:0] is input/output for LCD controller segment driver outputs SEG[15:8], and LIN-UART serial  
communication signals SCK, SOT, SIN of channels 10 and 11. Otherwise, the port can be used as general  
purpose port.  
PFR34.7  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SEG15 output  
PFR34.6  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR34.6 0 - Resource function is SEG14 output  
1 - Resource function is SCK11 input/output  
PFR34.5  
PFR34.4  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR34.5 0 - Resource function is SEG13 output  
1 - Resource function is SOT11 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR34.4 0 - Resource function is SEG12 output  
1 - Resource function is SIN11 input  
PFR34.3  
PFR34.2  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SEG11 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR34.2 0 - Resource function is SEG10 output  
1 - Resource function is SCK10 input/output  
PFR34.1  
PFR34.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR34.1 0 - Resource function is SEG9 output  
1 - Resource function is SOT10 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR34.0 0 - Resource function is SEG8 output  
1 - Resource function is SIN10 input  
496  
Chapter 30 I/O Ports  
3.Port Register Settings  
■ P35: The functions of Port 35 are controlled by PFR35 and EPFR35  
Addr  
7
6
5
4
3
2
1
0
initial  
PFR35  
0DA3h  
PFR35.7  
PFR35.6  
PFR35.5  
PFR35.4  
PFR35.3  
PFR35.2  
PFR35.1  
PFR35.0  
0000 0000  
EPFR35  
0DE3h  
-
EPFR35.6 EPFR35.5 EPFR35.4  
R/W R/W R/W  
-
EPFR35.2 EPFR35.1 EPFR35.0  
R/W R/W R/W  
-000 -000  
R/W  
R/W  
P35[7:0] is input/output for LCD controller segment driver outputs SEG[7:0], and LIN-UART serial  
communication signals SCK, SOT, SIN of channels 8 and 9. Otherwise, the port can be used as general purpose  
port.  
PFR35.7  
PFR35.6  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SEG7 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR35.6 0 - Resource function is SEG6 output  
1 - Resource function is SCK9 input/output  
PFR35.5  
PFR35.4  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR35.5 0 - Resource function is SEG5 output  
1 - Resource function is SOT9 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR35.4 0 - Resource function is SEG4 output  
1 - Resource function is SIN9 input  
PFR35.3  
PFR35.2  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
Resource function is SEG3 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR35.2 0 - Resource function is SEG2 output  
1 - Resource function is SCK8 input/output  
PFR35.1  
PFR35.0  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR35.1 0 - Resource function is SEG1 output  
1 - Resource function is SOT8 output  
0 - Port is in general purpose port mode.  
1 - Port is in resource function mode:  
EPFR35.0 0 - Resource function is SEG0 output  
1 - Resource function is SIN8 input  
497  
Chapter 30 I/O Ports  
3.Port Register Settings  
3.5 Port Input Level Selection  
The input levels of each port can be programmed bit-wise between CMOS Hysteresis type A and B, Automotive  
Hysteresis and TTL level.  
CMOS Hysteresis type A:  
CMOS Hysteresis type B:  
Automotive Hysteresis:  
TTL  
VIL=0.3 x VDD  
VIL=0.2 x VDD  
VIL=0.5 x VDD  
VIL=0.8 V  
VIH=0.7 x VDD  
VIH=0.8 x VDD  
VIH=0.8 x VDD  
VIH=2.1 V  
For setup, the Port Input Level Registers (PILR, EPILR) of each port are used.  
Port Input Level  
PILRx.y  
EPILRx.y  
0 (default)  
0 (default)  
CMOS Hysteresis A  
1
0
1
0
1
1
Automotive Hysteresis  
TTL  
CMOS Hysteresis B  
Addr  
7
6
5
4
3
2
1
0
initial  
PILR00  
PILR01  
PILR02  
PILR03  
PILR04  
PILR05  
PILR06  
PILR07  
PILR08  
PILR09  
PILR10  
PILR11  
PILR12  
PILR13  
PILR14  
PILR15  
PILR16  
PILR17  
PILR18  
PILR19  
0E40h  
PILR00.7  
PILR01.7  
PILR02.7  
PILR03.7  
PILR04.7  
PILR05.7  
PILR06.7  
PILR07.7  
PILR08.7  
PILR09.7  
PILR10.7  
PILR11.7  
PILR12.7  
PILR13.7  
PILR14.7  
PILR15.7  
PILR16.7  
PILR17.7  
PILR18.7  
PILR19.7  
PILR00.6  
PILR00.5  
PILR00.4  
PILR00.3  
PILR00.2  
PILR00.1  
PILR00.0  
0000 0000  
0E41h  
0E42h  
0E43h  
0E44h  
0E45h  
0E46h  
0E47h  
0E48h  
0E49h  
0E4Ah  
0E4Bh  
0E4Ch  
0E4Dh  
0E4Eh  
0E4Fh  
0E50h  
0E51h  
0E52h  
0E53h  
PILR01.6  
PILR02.6  
PILR03.6  
PILR04.6  
PILR05.6  
PILR06.6  
PILR07.6  
PILR08.6  
PILR09.6  
PILR10.6  
PILR11.6  
PILR12.6  
PILR13.6  
PILR14.6  
PILR15.6  
PILR16.6  
PILR17.6  
PILR18.6  
PILR19.6  
PILR01.5  
PILR02.5  
PILR03.5  
PILR04.5  
PILR05.5  
PILR06.5  
PILR07.5  
PILR08.5  
PILR09.5  
PILR10.5  
PILR11.5  
PILR12.5  
PILR13.5  
PILR14.5  
PILR15.5  
PILR16.5  
PILR17.5  
PILR18.5  
PILR19.5  
PILR01.4  
PILR02.4  
PILR03.4  
PILR04.4  
PILR05.4  
PILR06.4  
PILR07.4  
PILR08.4  
PILR09.4  
PILR10.4  
PILR11.4  
PILR12.4  
PILR13.4  
PILR14.4  
PILR15.4  
PILR16.4  
PILR17.4  
PILR18.4  
PILR19.4  
PILR01.3  
PILR02.3  
PILR03.3  
PILR04.3  
PILR05.3  
PILR06.3  
PILR07.3  
PILR08.3  
PILR09.3  
PILR10.3  
PILR11.3  
PILR12.3  
PILR13.3  
PILR14.3  
PILR15.3  
PILR16.3  
PILR17.3  
PILR18.3  
PILR19.3  
PILR01.2  
PILR02.2  
PILR03.2  
PILR04.2  
PILR05.2  
PILR06.2  
PILR07.2  
PILR08.2  
PILR09.2  
PILR10.2  
PILR11.2  
PILR12.2  
PILR13.2  
PILR14.2  
PILR15.2  
PILR16.2  
PILR17.2  
PILR18.2  
PILR19.2  
PILR01.1  
PILR02.1  
PILR03.1  
PILR04.1  
PILR05.1  
PILR06.1  
PILR07.1  
PILR08.1  
PILR09.1  
PILR10.1  
PILR11.1  
PILR12.1  
PILR13.1  
PILR14.1  
PILR15.1  
PILR16.1  
PILR17.1  
PILR18.1  
PILR19.1  
PILR01.0  
PILR02.0  
PILR03.0  
PILR04.0  
PILR05.0  
PILR06.0  
PILR07.0  
PILR08.0  
PILR09.0  
PILR10.0  
PILR11.0  
PILR12.0  
PILR13.0  
PILR14.0  
PILR15.0  
PILR16.0  
PILR17.0  
PILR18.0  
PILR19.0  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
498  
 
Chapter 30 I/O Ports  
3.Port Register Settings  
PILR20  
PILR21  
PILR22  
PILR23  
PILR24  
PILR25  
PILR26  
PILR27  
PILR28  
PILR29  
PILR30  
PILR31  
PILR32  
PILR33  
PILR34  
PILR35  
0E54h  
0E55h  
0E56h  
0E57h  
0E58h  
0E59h  
0E5Ah  
0E5Bh  
0E5Ch  
0E5Dh  
0E5Eh  
0E5Fh  
0E60h  
0E61h  
0E62h  
0E63h  
PILR20.7  
PILR21.7  
PILR22.7  
PILR23.7  
PILR24.7  
PILR25.7  
PILR26.7  
PILR27.7  
PILR28.7  
PILR29.7  
PILR30.7  
PILR31.7  
PILR32.7  
PILR33.7  
PILR34.7  
PILR20.6  
PILR21.6  
PILR22.6  
PILR23.6  
PILR24.6  
PILR25.6  
PILR26.6  
PILR27.6  
PILR28.6  
PILR29.6  
PILR30.6  
PILR31.6  
PILR32.6  
PILR33.6  
PILR34.6  
PILR20.5  
PILR21.5  
PILR22.5  
PILR23.5  
PILR24.5  
PILR25.5  
PILR26.5  
PILR27.5  
PILR28.5  
PILR29.5  
PILR30.5  
PILR31.5  
PILR32.5  
PILR33.5  
PILR34.5  
PILR20.4  
PILR21.4  
PILR22.4  
PILR23.4  
PILR24.4  
PILR25.4  
PILR26.4  
PILR27.4  
PILR28.4  
PILR29.4  
PILR30.4  
PILR31.4  
PILR32.4  
PILR33.4  
PILR34.4  
PILR20.3  
PILR21.3  
PILR22.3  
PILR23.3  
PILR24.3  
PILR25.3  
PILR26.3  
PILR27.3  
PILR28.3  
PILR29.3  
PILR30.3  
PILR31.3  
PILR32.3  
PILR33.3  
PILR34.3  
PILR20.2  
PILR21.2  
PILR22.2  
PILR23.2  
PILR24.2  
PILR25.2  
PILR26.2  
PILR27.2  
PILR28.2  
PILR29.2  
PILR30.2  
PILR31.2  
PILR32.2  
PILR33.2  
PILR34.2  
PILR20.1  
PILR21.1  
PILR22.1  
PILR23.1  
PILR24.1  
PILR25.1  
PILR26.1  
PILR27.1  
PILR28.1  
PILR29.1  
PILR30.1  
PILR31.1  
PILR32.1  
PILR33.1  
PILR34.1  
PILR20.0  
PILR21.0  
PILR22.0  
PILR23.0  
PILR24.0  
PILR25.0  
PILR26.0  
PILR27.0  
PILR28.0  
PILR29.0  
PILR30.0  
PILR31.0  
PILR32.0  
PILR33.0  
PILR34.0  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
0000 0000  
PILR35.7  
R/W  
PILR35.6  
R/W  
PILR35.5  
R/W  
PILR35.4  
R/W  
PILR35.3  
R/W  
PILR35.2  
R/W  
PILR35.1  
R/W  
PILR35.0  
R/W  
Addr  
7
6
5
4
3
2
1
0
initial  
EPILR00 0E80h EPILR00.7 EPILR00.6 EPILR00.5 EPILR00.4 EPILR00.3 EPILR00.2 EPILR00.1 EPILR00.0 0000 0000  
EPILR01 0E81h EPILR01.7 EPILR01.6 EPILR01.5 EPILR01.4 EPILR01.3 EPILR01.2 EPILR01.1 EPILR01.0 0000 0000  
EPILR02 0E82h EPILR02.7 EPILR02.6 EPILR02.5 EPILR02.4 EPILR02.3 EPILR02.2 EPILR02.1 EPILR02.0 0000 0000  
EPILR03 0E83h EPILR03.7 EPILR03.6 EPILR03.5 EPILR03.4 EPILR03.3 EPILR03.2 EPILR03.1 EPILR03.0 0000 0000  
EPILR04 0E84h EPILR04.7 EPILR04.6 EPILR04.5 EPILR04.4 EPILR04.3 EPILR04.2 EPILR04.1 EPILR04.0 0000 0000  
EPILR05 0E85h EPILR05.7 EPILR05.6 EPILR05.5 EPILR05.4 EPILR05.3 EPILR05.2 EPILR05.1 EPILR05.0 0000 0000  
EPILR06 0E86h EPILR06.7 EPILR06.6 EPILR06.5 EPILR06.4 EPILR06.3 EPILR06.2 EPILR06.1 EPILR06.0 0000 0000  
EPILR07 0E87h EPILR07.7 EPILR07.6 EPILR07.5 EPILR07.4 EPILR07.3 EPILR07.2 EPILR07.1 EPILR07.0 0000 0000  
EPILR08 0E88h EPILR08.7 EPILR08.6 EPILR08.5 EPILR08.4 EPILR08.3 EPILR08.2 EPILR08.1 EPILR08.0 0000 0000  
EPILR09 0E89h EPILR09.7 EPILR09.6 EPILR09.5 EPILR09.4 EPILR09.3 EPILR09.2 EPILR09.1 EPILR09.0 0000 0000  
EPILR10 0E8Ah EPILR10.7 EPILR10.6 EPILR10.5 EPILR10.4 EPILR10.3 EPILR10.2 EPILR10.1 EPILR10.0 0000 0000  
EPILR11 0E8Bh EPILR11.7 EPILR11.6 EPILR11.5 EPILR11.4 EPILR11.3 EPILR11.2 EPILR11.1 EPILR11.0 0000 0000  
EPILR12 0E8Ch EPILR12.7 EPILR12.6 EPILR12.5 EPILR12.4 EPILR12.3 EPILR12.2 EPILR12.1 EPILR12.0 0000 0000  
EPILR13 0E8Dh EPILR13.7 EPILR13.6 EPILR13.5 EPILR13.4 EPILR13.3 EPILR13.2 EPILR13.1 EPILR13.0 0000 0000  
EPILR14 0E8Eh  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
---- ----  
---- ----  
EPILR15 0E8Fh  
499  
Chapter 30 I/O Ports  
3.Port Register Settings  
EPILR16 0E90h  
EPILR17 0E91h  
EPILR18 0E92h  
EPILR19 0E93h  
EPILR20 0E94h  
EPILR21 0E95h  
EPILR22 0E96h  
EPILR23 0E97h  
EPILR24 0E98h  
EPILR25 0E99h  
EPILR26 0E9Ah  
EPILR27 0E9Bh  
EPILR28 0E9Ch  
EPILR29 0E9Dh  
EPILR30 0E9Eh  
EPILR31 0E9Fh  
EPILR32 0EA0h  
EPILR33 0EA1h  
EPILR34 0EA2h  
EPILR35 0EA3h  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
---- ----  
---- ----  
---- ----  
---- ----  
---- ----  
---- ----  
---- ----  
---- ----  
---- ----  
---- ----  
---- ----  
---- ----  
---- ----  
---- ----  
---- ----  
---- ----  
---- ----  
---- ----  
---- ----  
---- ----  
-
-
-
-
-
-
-
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
3.6 Programmable Pull-Up/Pull Down Resistors  
The Ports listed in the following table have 50 kOhm Pull-Up resistors, which can be enabled bit-wise. The  
function is enabled by the Port Pull Enable Registers (PPER) and controlled by the Port Pull Control Register  
(PPCR). The PPCR selects Pull-Up or Pull-Down. The Pull-Up/Pull-Down is disabled automatically in the STOP-  
HiZ mode (STCR:STOP and STCR:HIZ set).  
Port Pull-Up/Pull-Down Enable Registers  
Bit  
0 (default)  
1
PPERx.y  
Pull-Up/Pull-Down disabled  
Pull-Up/Pull-Down enabled  
Addr  
7
6
5
4
3
2
1
0
initial  
PPER00 0EC0h PPER00.7 PPER00.6 PPER00.5 PPER00.4 PPER00.3 PPER00.2 PPER00.1 PPER00.0 0000 0000  
PPER01 0EC1h PPER01.7 PPER01.6 PPER01.5 PPER01.4 PPER01.3 PPER01.2 PPER01.1 PPER01.0 0000 0000  
500  
 
Chapter 30 I/O Ports  
3.Port Register Settings  
PPER02 0EC2h PPER02.7 PPER02.6 PPER02.5 PPER02.4 PPER02.3 PPER02.2 PPER02.1 PPER02.0 0000 0000  
PPER03 0EC3h PPER03.7 PPER03.6 PPER03.5 PPER03.4 PPER03.3 PPER03.2 PPER03.1 PPER03.0 0000 0000  
PPER04 0EC4h PPER04.7 PPER04.6 PPER04.5 PPER04.4 PPER04.3 PPER04.2 PPER04.1 PPER04.0 0000 0000  
PPER05 0EC5h PPER05.7 PPER05.6 PPER05.5 PPER05.4 PPER05.3 PPER05.2 PPER05.1 PPER05.0 0000 0000  
PPER06 0EC6h PPER06.7 PPER06.6 PPER06.5 PPER06.4 PPER06.3 PPER06.2 PPER06.1 PPER06.0 0000 0000  
PPER07 0EC7h PPER07.7 PPER07.6 PPER07.5 PPER07.4 PPER07.3 PPER07.2 PPER07.1 PPER07.0 0000 0000  
PPER08 0EC8h PPER08.7 PPER08.6 PPER08.5 PPER08.4 PPER08.3 PPER08.2 PPER08.1 PPER08.0 0000 0000  
PPER09 0EC9h PPER09.7 PPER09.6 PPER09.5 PPER09.4 PPER09.3 PPER09.2 PPER09.1 PPER09.0 0000 0000  
PPER10 0ECAh PPER10.7 PPER10.6 PPER10.5 PPER10.4 PPER10.3 PPER10.2 PPER10.1 PPER10.0 0000 0000  
PPER11 0ECBh PPER11.7 PPER11.6 PPER11.5 PPER11.4 PPER11.3 PPER11.2 PPER11.1 PPER11.0 0000 0000  
PPER12 0ECCh PPER12.7 PPER12.6 PPER12.5 PPER12.4 PPER12.3 PPER12.2 PPER12.1 PPER12.0 0000 0000  
PPER13 0ECDh PPER13.7 PPER13.6 PPER13.5 PPER13.4 PPER13.3 PPER13.2 PPER13.1 PPER13.0 0000 0000  
PPER14 0ECEh PPER14.7 PPER14.6 PPER14.5 PPER14.4 PPER14.3 PPER14.2 PPER14.1 PPER14.0 0000 0000  
PPER15 0ECFh PPER15.7 PPER15.6 PPER15.5 PPER15.4 PPER15.3 PPER15.2 PPER15.1 PPER15.0 0000 0000  
PPER16 0ED0h PPER16.7 PPER16.6 PPER16.5 PPER16.4 PPER16.3 PPER16.2 PPER16.1 PPER16.0 0000 0000  
PPER17 0ED1h PPER17.7 PPER17.6 PPER17.5 PPER17.4 PPER17.3 PPER17.2 PPER17.1 PPER17.0 0000 0000  
PPER18 0ED2h PPER18.7 PPER18.6 PPER18.5 PPER18.4 PPER18.3 PPER18.2 PPER18.1 PPER18.0 0000 0000  
PPER19 0ED3h PPER19.7 PPER19.6 PPER19.5 PPER19.4 PPER19.3 PPER19.2 PPER19.1 PPER19.0 0000 0000  
PPER20 0ED4h PPER20.7 PPER20.6 PPER20.5 PPER20.4 PPER20.3 PPER20.2 PPER20.1 PPER20.0 0000 0000  
PPER21 0ED5h PPER21.7 PPER21.6 PPER21.5 PPER21.4 PPER21.3 PPER21.2 PPER21.1 PPER21.0 0000 0000  
PPER22 0ED6h PPER22.7 PPER22.6 PPER22.5 PPER22.4 PPER22.3 PPER22.2 PPER22.1 PPER22.0 0000 0000  
PPER23 0ED7h PPER23.7 PPER23.6 PPER23.5 PPER23.4 PPER23.3 PPER23.2 PPER23.1 PPER23.0 0000 0000  
PPER24 0ED8h PPER24.7 PPER24.6 PPER24.5 PPER24.4 PPER24.3 PPER24.2 PPER24.1 PPER24.0 0000 0000  
PPER25 0ED9h PPER25.7 PPER25.6 PPER25.5 PPER25.4 PPER25.3 PPER25.2 PPER25.1 PPER25.0 0000 0000  
PPER26 0EDAh PPER26.7 PPER26.6 PPER26.5 PPER26.4 PPER26.3 PPER26.2 PPER26.1 PPER26.0 0000 0000  
PPER27 0EDBh PPER27.7 PPER27.6 PPER27.5 PPER27.4 PPER27.3 PPER27.2 PPER27.1 PPER27.0 0000 0000  
PPER28 0EDCh PPER28.7 PPER28.6 PPER28.5 PPER28.4 PPER28.3 PPER28.2 PPER28.1 PPER28.0 0000 0000  
PPER29 0EDDh PPER29.7 PPER29.6 PPER29.5 PPER29.4 PPER29.3 PPER29.2 PPER29.1 PPER29.0 0000 0000  
PPER30 0EDEh PPER30.7 PPER30.6 PPER30.5 PPER30.4 PPER30.3 PPER30.2 PPER30.1 PPER30.0 0000 0000  
PPER31 0EDFh PPER31.7 PPER31.6 PPER31.5 PPER31.4 PPER31.3 PPER31.2 PPER31.1 PPER31.0 0000 0000  
PPER32 0EE0h PPER32.7 PPER32.6 PPER32.5 PPER32.4 PPER32.3 PPER32.2 PPER32.1 PPER32.0 0000 0000  
PPER33 0EE1h PPER33.7 PPER33.6 PPER33.5 PPER33.4 PPER33.3 PPER33.2 PPER33.1 PPER33.0 0000 0000  
PPER34 0EE2h PPER34.7 PPER34.6 PPER34.5 PPER34.4 PPER34.3 PPER34.2 PPER34.1 PPER34.0 0000 0000  
PPER35 0EE3h PPER35.7 PPER35.6 PPER35.5 PPER35.4 PPER35.3 PPER35.2 PPER35.1 PPER35.0 0000 0000  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
501  
Chapter 30 I/O Ports  
3.Port Register Settings  
Port Pull-Up/Pull-Down Control Registers  
1 (default)  
Bit  
0
PPCRx.y  
Pull Down is selected  
Pull-Up is selected  
Addr  
7
6
5
4
3
2
1
0
initial  
PPCR00  
PPCR01  
PPCR02  
PPCR03  
PPCR04  
PPCR05  
PPCR06  
PPCR07  
PPCR08  
PPCR09  
0F00h PPCR00.7 PPCR00.6 PPCR00.5 PPCR00.4 PPCR00.3 PPCR00.2 PPCR00.1 PPCR00.0 1111 1111  
0F01h PPCR01.7 PPCR01.6 PPCR01.5 PPCR01.4 PPCR01.3 PPCR01.2 PPCR01.1 PPCR01.0 1111 1111  
0F02h PPCR02.7 PPCR02.6 PPCR02.5 PPCR02.4 PPCR02.3 PPCR02.2 PPCR02.1 PPCR02.0 1111 1111  
0F03h PPCR03.7 PPCR03.6 PPCR03.5 PPCR03.4 PPCR03.3 PPCR03.2 PPCR03.1 PPCR03.0 1111 1111  
0F04h PPCR04.7 PPCR04.6 PPCR04.5 PPCR04.4 PPCR04.3 PPCR04.2 PPCR04.1 PPCR04.0 1111 1111  
0F05h PPCR05.7 PPCR05.6 PPCR05.5 PPCR05.4 PPCR05.3 PPCR05.2 PPCR05.1 PPCR05.0 1111 1111  
0F06h PPCR06.7 PPCR06.6 PPCR06.5 PPCR06.4 PPCR06.3 PPCR06.2 PPCR06.1 PPCR06.0 1111 1111  
0F07h PPCR07.7 PPCR07.6 PPCR07.5 PPCR07.4 PPCR07.3 PPCR07.2 PPCR07.1 PPCR07.0 1111 1111  
0F08h PPCR08.7 PPCR08.6 PPCR08.5 PPCR08.4 PPCR08.3 PPCR08.2 PPCR08.1 PPCR08.0 1111 1111  
0F09h PPCR09.7 PPCR09.6 PPCR09.5 PPCR09.4 PPCR09.3 PPCR09.2 PPCR09.1 PPCR09.0 1111 1111  
PPCR10 0F0Ah PPCR10.7 PPCR10.6 PPCR10.5 PPCR10.4 PPCR10.3 PPCR10.2 PPCR10.1 PPCR10.0 1111 1111  
PPCR11 0F0Bh PPCR11.7 PPCR11.6 PPCR11.5 PPCR11.4 PPCR11.3 PPCR11.2 PPCR11.1 PPCR11.0 1111 1111  
PPCR12 0F0Ch PPCR12.7 PPCR12.6 PPCR12.5 PPCR12.4 PPCR12.3 PPCR12.2 PPCR12.1 PPCR12.0 1111 1111  
PPCR13 0F0Dh PPCR13.7 PPCR13.6 PPCR13.5 PPCR13.4 PPCR13.3 PPCR13.2 PPCR13.1 PPCR13.0 1111 1111  
PPCR14 0F0Eh PPCR14.7 PPCR14.6 PPCR14.5 PPCR14.4 PPCR14.3 PPCR14.2 PPCR14.1 PPCR14.0 1111 1111  
PPCR15 0F0Fh PPCR15.7 PPCR15.6 PPCR15.5 PPCR15.4 PPCR15.3 PPCR15.2 PPCR15.1 PPCR15.0 1111 1111  
PPCR16  
PPCR17  
PPCR18  
PPCR19  
PPCR20  
PPCR21  
PPCR22  
PPCR23  
PPCR24  
PPCR25  
0F10h PPCR16.7 PPCR16.6 PPCR16.5 PPCR16.4 PPCR16.3 PPCR16.2 PPCR16.1 PPCR16.0 1111 1111  
0F11h PPCR17.7 PPCR17.6 PPCR17.5 PPCR17.4 PPCR17.3 PPCR17.2 PPCR17.1 PPCR17.0 1111 1111  
0F12h PPCR18.7 PPCR18.6 PPCR18.5 PPCR18.4 PPCR18.3 PPCR18.2 PPCR18.1 PPCR18.0 1111 1111  
0F13h PPCR19.7 PPCR19.6 PPCR19.5 PPCR19.4 PPCR19.3 PPCR19.2 PPCR19.1 PPCR19.0 1111 1111  
0F14h PPCR20.7 PPCR20.6 PPCR20.5 PPCR20.4 PPCR20.3 PPCR20.2 PPCR20.1 PPCR20.0 1111 1111  
0F15h PPCR21.7 PPCR21.6 PPCR21.5 PPCR21.4 PPCR21.3 PPCR21.2 PPCR21.1 PPCR21.0 1111 1111  
0F16h PPCR22.7 PPCR22.6 PPCR22.5 PPCR22.4 PPCR22.3 PPCR22.2 PPCR22.1 PPCR22.0 1111 1111  
0F17h PPCR23.7 PPCR23.6 PPCR23.5 PPCR23.4 PPCR23.3 PPCR23.2 PPCR23.1 PPCR23.0 1111 1111  
0F18h PPCR24.7 PPCR24.6 PPCR24.5 PPCR24.4 PPCR24.3 PPCR24.2 PPCR24.1 PPCR24.0 1111 1111  
0F19h PPCR25.7 PPCR25.6 PPCR25.5 PPCR25.4 PPCR25.3 PPCR25.2 PPCR25.1 PPCR25.0 1111 1111  
PPCR26 0F1Ah PPCR26.7 PPCR26.6 PPCR26.5 PPCR26.4 PPCR26.3 PPCR26.2 PPCR26.1 PPCR26.0 1111 1111  
PPCR27 0F1Bh PPCR27.7 PPCR27.6 PPCR27.5 PPCR27.4 PPCR27.3 PPCR27.2 PPCR27.1 PPCR27.0 1111 1111  
502  
Chapter 30 I/O Ports  
3.Port Register Settings  
PPCR28 0F1Ch PPCR28.7 PPCR28.6 PPCR28.5 PPCR28.4 PPCR28.3 PPCR28.2 PPCR28.1 PPCR28.0 1111 1111  
PPCR29 0F1Dh PPCR29.7 PPCR29.6 PPCR29.5 PPCR29.4 PPCR29.3 PPCR29.2 PPCR29.1 PPCR29.0 1111 1111  
PPCR30 0F1Eh PPCR30.7 PPCR30.6 PPCR30.5 PPCR30.4 PPCR30.3 PPCR30.2 PPCR30.1 PPCR30.0 1111 1111  
PPCR31 0F1Fh PPCR31.7 PPCR31.6 PPCR31.5 PPCR31.4 PPCR31.3 PPCR31.2 PPCR31.1 PPCR31.0 1111 1111  
PPCR32  
PPCR33  
PPCR34  
PPCR35  
0F20h PPCR32.7 PPCR32.6 PPCR32.5 PPCR32.4 PPCR32.3 PPCR32.2 PPCR32.1 PPCR32.0 1111 1111  
0F21h PPCR33.7 PPCR33.6 PPCR33.5 PPCR33.4 PPCR33.3 PPCR33.2 PPCR33.1 PPCR33.0 1111 1111  
0F22h PPCR34.7 PPCR34.6 PPCR34.5 PPCR34.4 PPCR34.3 PPCR34.2 PPCR34.1 PPCR34.0 1111 1111  
0F23h PPCR35.7 PPCR35.6 PPCR35.5 PPCR35.4 PPCR35.3 PPCR35.2 PPCR35.1 PPCR35.0 1111 1111  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Note:  
PPCR Register bits can only be written, if the attached PPER register bit is low (resistors disabled).  
3.7 Programmable Port Output Drive  
The Ports listed in the following table have a programmable output drive option, which can be enabled bit-wise.  
The function is enabled by the Port Output Drive Registers (PODR).  
Port Output Drive Registers  
Bit  
0 (default)  
1
PODRx.y  
5 mA output drive  
2 mA output drive  
Addr  
7
6
5
4
3
2
1
0
initial  
PODR00 0E00h PODR00.7 PODR00.6 PODR00.5 PODR00.4 PODR00.3 PODR00.2 PODR00.1 PODR00.0 0000 0000  
PODR01 0E01h PODR01.7 PODR01.6 PODR01.5 PODR01.4 PODR01.3 PODR01.2 PODR01.1 PODR01.0 0000 0000  
PODR02 0E02h PODR02.7 PODR02.6 PODR02.5 PODR02.4 PODR02.3 PODR02.2 PODR02.1 PODR02.0 0000 0000  
PODR03 0E03h PODR03.7 PODR03.6 PODR03.5 PODR03.4 PODR03.3 PODR03.2 PODR03.1 PODR03.0 0000 0000  
PODR04 0E04h PODR04.7 PODR04.6 PODR04.5 PODR04.4 PODR04.3 PODR04.2 PODR04.1 PODR04.0 0000 0000  
PODR05 0E05h PODR05.7 PODR05.6 PODR05.5 PODR05.4 PODR05.3 PODR05.2 PODR05.1 PODR05.0 0000 0000  
PODR06 0E06h PODR06.7 PODR06.6 PODR06.5 PODR06.4 PODR06.3 PODR06.2 PODR06.1 PODR06.0 0000 0000  
PODR07 0E07h PODR07.7 PODR07.6 PODR07.5 PODR07.4 PODR07.3 PODR07.2 PODR07.1 PODR07.0 0000 0000  
PODR08 0E08h PODR08.7 PODR08.6 PODR08.5 PODR08.4 PODR08.3 PODR08.2 PODR08.1 PODR08.0 0000 0000  
PODR09 0E09h PODR09.7 PODR09.6 PODR09.5 PODR09.4 PODR09.3 PODR09.2 PODR09.1 PODR09.0 0000 0000  
PODR10 0E0Ah PODR10.7 PODR10.6 PODR10.5 PODR10.4 PODR10.3 PODR10.2 PODR10.1 PODR10.0 0000 0000  
PODR11 0E0Bh PODR11.7 PODR11.6 PODR11.5 PODR11.4 PODR11.3 PODR11.2 PODR11.1 PODR11.0 0000 0000  
PODR12 0E0Ch PODR12.7 PODR12.6 PODR12.5 PODR12.4 PODR12.3 PODR12.2 PODR12.1 PODR12.0 0000 0000  
PODR13 0E0Dh PODR13.7 PODR13.6 PODR13.5 PODR13.4 PODR13.3 PODR13.2 PODR13.1 PODR13.0 0000 0000  
503  
Chapter 30 I/O Ports  
3.Port Register Settings  
PODR14 0E0Eh PODR14.7 PODR14.6 PODR14.5 PODR14.4 PODR14.3 PODR14.2 PODR14.1 PODR14.0 0000 0000  
PODR15 0E0Fh PODR15.7 PODR15.6 PODR15.5 PODR15.4 PODR15.3 PODR15.2 PODR15.1 PODR15.0 0000 0000  
PODR16 0E10h PODR16.7 PODR16.6 PODR16.5 PODR16.4 PODR16.3 PODR16.2 PODR16.1 PODR16.0 0000 0000  
PODR17 0E11h PODR17.7 PODR17.6 PODR17.5 PODR17.4 PODR17.3 PODR17.2 PODR17.1 PODR17.0 0000 0000  
PODR18 0E12h PODR18.7 PODR18.6 PODR18.5 PODR18.4 PODR18.3 PODR18.2 PODR18.1 PODR18.0 0000 0000  
PODR19 0E13h PODR19.7 PODR19.6 PODR19.5 PODR19.4 PODR19.3 PODR19.2 PODR19.1 PODR19.0 0000 0000  
PODR20 0E14h PODR20.7 PODR20.6 PODR20.5 PODR20.4 PODR20.3 PODR20.2 PODR20.1 PODR20.0 0000 0000  
PODR21 0E15h PODR21.7 PODR21.6 PODR21.5 PODR21.4 PODR21.3 PODR21.2 PODR21.1 PODR21.0 0000 0000  
PODR22 0E16h PODR22.7 PODR22.6 PODR22.5 PODR22.4 PODR22.3 PODR22.2 PODR22.1 PODR22.0 0000 0000  
PODR23 0E17h PODR23.7 PODR23.6 PODR23.5 PODR23.4 PODR23.3 PODR23.2 PODR23.1 PODR23.0 0000 0000  
PODR24 0E18h PODR24.7 PODR24.6 PODR24.5 PODR24.4 PODR24.3 PODR24.2 PODR24.1 PODR24.0 0000 0000  
PODR25 0E19h PODR25.7 PODR25.6 PODR25.5 PODR25.4 PODR25.3 PODR25.2 PODR25.1 PODR25.0 0000 0000  
PODR26 0E1Ah PODR26.7 PODR26.6 PODR26.5 PODR26.4 PODR26.3 PODR26.2 PODR26.1 PODR26.0 0000 0000  
PODR27 0E1Bh PODR27.7 PODR27.6 PODR27.5 PODR27.4 PODR27.3 PODR27.2 PODR27.1 PODR27.0 0000 0000  
PODR28 0E1Ch PODR28.7 PODR28.6 PODR28.5 PODR28.4 PODR28.3 PODR28.2 PODR28.1 PODR28.0 0000 0000  
PODR29 0E1Dh PODR29.7 PODR29.6 PODR29.5 PODR29.4 PODR29.3 PODR29.2 PODR29.1 PODR29.0 0000 0000  
PODR30 0E1Eh PODR30.7 PODR30.6 PODR30.5 PODR30.4 PODR30.3 PODR30.2 PODR30.1 PODR30.0 0000 0000  
PODR31 0E1Fh PODR31.7 PODR31.6 PODR31.5 PODR31.4 PODR31.3 PODR31.2 PODR31.1 PODR31.0 0000 0000  
PODR32 0E20h PODR32.7 PODR32.6 PODR32.5 PODR32.4 PODR32.3 PODR32.2 PODR32.1 PODR32.0 0000 0000  
PODR33 0E21h PODR33.7 PODR33.6 PODR33.5 PODR33.4 PODR33.3 PODR33.2 PODR33.1 PODR33.0 0000 0000  
PODR34 0E22h PODR34.7 PODR34.6 PODR34.5 PODR34.4 PODR34.3 PODR34.2 PODR34.1 PODR34.0 0000 0000  
PODR35 0E23h PODR35.7 PODR35.6 PODR35.5 PODR35.4 PODR35.3 PODR35.2 PODR35.1 PODR35.0 0000 0000  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
504  
Chapter 30 I/O Ports  
3.Port Register Settings  
505  
Chapter 30 I/O Ports  
3.Port Register Settings  
506  
Chapter 31 External Bus  
1.Overview of the External Bus Interface  
Chapter 31 External Bus  
The external bus interface controller controls the interfaces with the internal bus for chips and  
with external memory and I/O devices.  
This chapter explains each function of the external bus interface and its operation.  
1. Overview of the External Bus Interface  
1.1 Features  
● The external bus interface has the following features:  
• Addresses of up to 32 bits (4 GB space) can be output.  
• Various kinds of external memory (8-bit/16-bit/32-bit modules) can be directly connected and multiple  
access timings can be mixed and controlled.  
• Asynchronous SRAM and asynchronous ROM/FLASH memory (multiple write strobe method or byte enable  
method)  
• Page mode ROM/FLASH memory (Page sizes 2, 4, and 8 can be used)  
• Burst mode ROM/FLASH memory (such as MBM29BL160D/161D/162D)  
• Address/data multiplex bus (8-bit/16-bit width only)  
• SDRAM (FCRAM modules are also supported, including two - and four - bank types with CAS latency 1 to 8)  
• Synchronous memory (such as ASIC built-in memory) (Synchronous SRAM cannot be directly connected)  
• Eight independent banks (chip select areas) can be set, and chip select corresponding to each bank can be  
output.  
• The size of each area can be set in multiples of 64 KB (64 KB to 2 GB for each chip select area).  
• An area can be set at any location in the logical address space (Boundaries may be limited depending on  
the size of the area.)  
● In each chip select area, the following functions can be set independently:  
• Enabling and disabling of the chip select area (Disabled areas cannot be accessed)  
• Setting of the access timing type to support various kinds of memory  
• Detailed access timing setting (individual setting of the access type such as the wait cycle)  
• Setting of the data bus width (8-bit/16-bit)  
• Setting of the order of bytes (big or little endian) (Only big endian can be set for the CS0 area)  
• Setting of write disable (read-only area)  
• Enabling and disabling of fetches from the built-in cache  
• Enabling and disabling of the prefetch function  
• Maximum burst length setting (1, 2, 4, 8)  
● A different detailed timing can be set for each access timing type.  
• For the same type of access timing, a different setting can be made in each chip select area.  
• Auto-wait can be set to up to 15 cycles (asynchronous SRAM, ROM, Flash, and I/O area).  
• The bus cycle can be extended by external RDY input (asynchronous SRAM, ROM, Flash, and I/O area).  
• The first access wait and page wait can be set (burst, page mode, and ROM/FLASH area).  
• Various kinds of idle/recovery cycles and setting delays can be inserted.  
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Chapter 31 External Bus  
1.Overview of the External Bus Interface  
• Capable of setting timing values such as the CAS latency and RAS - CAS delay (SDRAM area)  
• Capable of controlling the distributed/centralized auto - refresh, self - refresh, and other refresh timings  
(SDRAM area)  
● Fly-by transfer by DMA can be performed.  
• Transfer between memory and I/O can be performed in a single access operation.  
• The memory wait cycle can be synchronized with the I/O wait cycle in fly-by transfer.  
• The hold time can be secured by only extending transfer source access.  
• Idle/recovery cycles specific to fly-by transfer can be set.  
● External bus arbitration using BRQ and BGRNT can be performed.  
● Pins that are not used by the external interface can be used as general-purpose I/O ports through  
settings.  
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Chapter 31 External Bus  
1.Overview of the External Bus Interface  
1.2 Block Diagram  
Figure 1-1 Block Diagram of the External Bus Interface  
Internal address bus  
Internal data bus  
32  
32  
External data bus  
MUX  
write buffer  
switch  
read buffer  
switch  
DATA BLOCK  
ADDRESS BLOCK  
+1 or +2  
External address bus  
address buffer  
ASR  
ASZ  
CS0  
CS7  
comparator  
SRAS,SCAS,  
SDRAM control  
RCR  
SWE,MCLKE,  
DQMUU,DQMUL,  
DQMLU,DQMLL  
underflow  
refresh counter  
External terminal controller  
RD  
WR0,WR1,  
WR2,WR3,  
AS,BAA  
all-block control  
registers  
control  
BRQ  
BGRNT  
RDY  
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Chapter 31 External Bus  
1.Overview of the External Bus Interface  
1.3 I/O Pins  
The I/O pins are external bus interface pins (Some pins have other uses).  
The following lists the I/O pins for each interface:  
● Ordinary bus interface  
•
•
•
•
•
•
A31 to A00, D31 to D00 (AD15 to AD00)  
CS0, CS1, CS2, CS3, CS4, CS5, CS6, CS7  
AS, SYSCLK, MCLK  
RD  
WR, WR0(UUB), WR1(ULB), WR2(ULB), WR3(ULB)  
RDY, BRQ, BGRNT  
● Memory interface  
•
•
•
•
•
MCLK, MCLKE  
MCLKI (for SDRAM)  
LBA(=AS), BAA (for burst ROM/FLASH)  
SRAS, SCAS, SWE (=WR) (for SDRAM)  
DQMUU,DQMUL,DQMLU,DQMLL (for SDRAM (=WR0, WR1, WR2, WR3))  
● DMA interface  
•
•
•
•
IOWR, IORD  
DACK0, DACK1  
DREQ0, DREQ1  
DEOP0, DEOP1  
1.4 Register List  
Figure 1-2 "List of External Bus Interface Registers" shows the registers used by the external bus interface:  
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Chapter 31 External Bus  
1.Overview of the External Bus Interface  
Figure 1-2 List of External Bus Interface Registers  
31  
24 23  
ASR0  
ASR1  
ASR2  
ASR3  
ASR4  
ASR5  
ASR6  
ASR7  
AWR0  
AWR2  
AWR4  
AWR6  
16 15  
08 07  
ACR0  
ACR1  
ASR2  
ACR3  
ACR4  
ACR5  
ACR6  
ACR7  
AWR1  
AWR3  
AWR5  
AWR7  
00  
Address  
00000640H  
00000644H  
00000648H  
0000064cH  
00000650H  
00000654H  
00000658H  
0000065cH  
00000660H  
00000664H  
00000668H  
0000066cH  
00000670H  
00000674H  
00000678H  
0000067cH  
00000680H  
00000684H  
00000688H  
0000068cH  
MCRA  
Reserved  
Reserved  
MCRB  
Reserved  
IOWR0  
Reserved  
IOWR2  
Reserved  
IOWR3  
Reserved  
IOWR1  
Reserved  
CSER  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
TCR  
Reserved  
CHER  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
000007f8H  
000007fcH  
(MODR)  
Reserved  
Reserved  
Reserved  
*1: Reserved indicates a reserved register. Be sure to set "0".  
*2: MODR cannot be accessed from user programs.  
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Chapter 31 External Bus  
2.External Bus Interface Registers  
2. External Bus Interface Registers  
This section explains the registers used in the external bus interface.  
■ Register Types  
The following registers are used by the external bus interface:  
•
•
•
•
•
•
•
•
•
•
Area select registers (ASR0-7)  
Area configuration registers (ACR0-7)  
Area wait registers (AWR0-7)  
Memory configuration register (MCRA for SDRAM/FCRAM auto - precharge OFF mode)  
Memory configuration register (MCRB for FCRAM auto - precharge ON mode)  
I/O wait registers for DMAC (IOWR0-3)  
Chip select enable register (CSER)  
Cache enable register (CHER)  
Pin/timing control register (TCR)  
Mode register (MODR)  
2.1 Area Select Registers 0-7(ASR0-7)  
This section explains the configuration and functions of area select registers 0-7 (ASR0-7).  
■ Configuration of area select registers 0-7 (ASR0-7)  
The area select registers (ASR0-7: Area Select Registers 0-7) specify the start address of each chip select area  
of CS0-CS7.  
Figure 2-1 "Configuration of the Area Select Registers (ASR0-7)" shows the configuration of area select registers  
0-7 (ASR0-7: Area Select Register).  
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Chapter 31 External Bus  
2.External Bus Interface Registers  
Figure 2-1 Configuration of the Area Select Registers (ASR0-7)  
Initial value  
INIT RST  
ASR0  
15  
14  
13  
12  
12  
12  
12  
12  
12  
12  
12  
2
1
0
Access  
W/R  
00000640H A31 A30 A29  
A18 A17 A16 0000H 0000H  
ASR1  
15  
14  
13  
2
1
0
00000644H A31 A30 A29  
A18 A17 A16 xxxxH xxxxH  
W/R  
W/R  
W/R  
W/R  
W/R  
W/R  
W/R  
ASR2  
15  
14  
13  
2
1
0
00000648H A31 A30 A29  
A18 A17 A16 xxxxH xxxxH  
ASR3  
15  
14  
13  
2
1
0
0000064CH A31 A30 A29  
A18 A17 A16 xxxxH xxxxH  
ASR4  
15  
14  
13  
2
1
0
00000650H A31 A30 A29  
A18 A17 A16 xxxxH xxxxH  
ASR5  
15  
14  
13  
2
1
0
00000654H A31 A30 A29  
A18 A17 A16 xxxxH xxxxH  
ASR6  
15  
14  
13  
2
1
0
00000658H A31 A30 A29  
A18 A17 A16 xxxxH xxxxH  
ASR7  
15  
14  
13  
2
1
0
0000065CH A31 A30 A29  
A18 A17 A16 xxxxH xxxxH  
■ Functions of Bits in the Area Select Registers (ASR0-7)  
The start address can be set in the high-order 16 bits (bits A31-A16). Each chip select area starts with the  
address set in this register and covers the range set by the four bits ASZ3-0 of the ASR0-7 registers.  
The boundary of each chip select area obeys the setting of the four bits ASZ3-0 of the ACR0-7 registers. For  
example, if an area of 1 MB is set by the four bits ASZ3-0, the low-order four bits of the ASR0-7 registers are  
ignored and only bits A31-20 are valid.  
The ASR0 register is initialized to 0000 by INIT and RST. ASR1-7 are not initialized by INIT and RST, and are  
H
therefore undefined. After starting chip operation, be sure to set the corresponding ASR register before enabling  
each chip select area with the CSER register.  
2.2 Area Configuration Registers 0-7 (ACR0-7)  
This section explains the configuration and functions of area configuration registers 0-7 (ACR0-  
7).  
■ Configuration of Area Configuration Registers 0-7 (ACR0-7)  
The area configuration registers 0-7 (ACR0-7: FArea Configuration Register 0-7) set the function of each chip  
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Chapter 31 External Bus  
2.External Bus Interface Registers  
select area.  
Figure 2-2 "Configuration of Area Configuration Registers 0-7 (ACR0-7)" shows the configuration of area  
configuration registers 0-7 (ACR0-7).  
Figure 2-2 Configuration of Area Configuration Registers 0-7 (ACR0-7) (Continued on next page)  
Initial value  
15  
14  
13  
12  
11  
10  
9
8
ACR0H  
INIT  
RST  
Access  
00000642H ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 1111**00B 1111**00B W/R  
7
6
5
4
0
3
2
1
0
ACR0L  
00000000B 00000000B  
00000643H SREN PFEN WREN  
TYP3 TYP2 TYP1 TYP0  
W/R  
15  
14  
13  
12  
11  
10  
9
8
ACR1H  
00000646H ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 XxxxxxxxB xxxxxxxxB W/R  
7
6
5
4
3
2
1
0
ACR1L  
00000647H SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB XxxxxxxxB W/R  
15  
14  
13  
12  
11  
10  
9
8
ACR2H  
xxxxxxxxB xxxxxxxxB  
0000064AH ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0  
W/R  
7
6
5
4
3
2
1
0
ACR2L  
0000064BH SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB W/R  
15  
14  
13  
12  
11  
10  
9
8
ACR3H  
0000064EH ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB W/R  
7
6
5
4
3
2
1
0
ACR3L  
XxxxxxxxB xxxxxxxxB  
0000064FH SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0  
W/R  
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Chapter 31 External Bus  
2.External Bus Interface Registers  
Initial value  
ACR4H  
15  
14  
13  
12  
11  
10  
9
8
INIT  
RST  
Access  
00000652H ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB W/R  
ACR4L  
7
6
5
4
3
2
1
0
00000653H SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB W/R  
ACR5H  
15  
14  
13  
12  
11  
10  
9
8
00000656H ASZ3 ASZ2 ASZ1 ASZ0 DBW1DBW0 BST1 BST0  
xxxxxxxxB xxxxxxxxB  
W/R  
7
6
5
4
3
2
1
0
ACR5L  
00000657H SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 xxxxxxxxB xxxxxxxxB W/R  
ACR6H  
15  
14  
13  
12  
11  
10  
9
8
0000065AH ASZ3 ASZ2 ASZ1 ASZ0 DBW1DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB W/R  
ACR6L  
7
6
5
4
3
2
1
0
0000065BH SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0  
xxxxxxxxB xxxxxxxxB  
W/R  
W/R  
W/R  
ACR7H  
0000065EH ASZ3 ASZ2 ASZ1 ASZ0 DBW1DBW0 BST1 BST0 xxxxxxxxB xxxxxxxxB  
15  
14  
13  
12  
11  
10  
9
8
ACR7L  
7
6
5
4
3
2
1
0
0000065FH  
xxxxxxxxB xxxxxxxxB  
SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0  
The following explains the function of each bit:  
[Bits 15-12] ASZ3-0 (Area Size Bits 3-0)  
These bits set the area size. Table 2-1 "Area Size Settings" shows their settings.  
Table 2-1 Area Size Settings  
ASZ3  
ASZ2  
ASZ1  
ASZ0  
Size of each chip select area  
64 KB (00010000 byte, ASR A[31:16] bits are valid)  
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
H
128 KB (00020000 byte, ASR A[31:17] bits are valid)  
H
256 KB (00040000 byte, ASR A[31:18] bits are valid)  
H
512 KB (00080000 byte, ASR A[31:19] bits are valid)  
H
1 MB (00100000 byte, ASR A[31:20] bits are valid)  
H
2 MB (00200000 byte, ASR A[31:21] bits are valid)  
H
4 MB (00400000 byte, ASR A[31:22] bits are valid)  
H
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Chapter 31 External Bus  
2.External Bus Interface Registers  
Table 2-1 Area Size Settings  
ASZ3  
ASZ2  
ASZ1  
ASZ0  
Size of each chip select area  
8 MB (00800000 byte, ASR A[31:23] bits are valid)  
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
H
16 MB (01000000 byte, ASR A[31:24] bits are valid)  
H
32 MB (02000000 byte, ASR A[31:25] bits are valid)  
H
64 MB (04000000 byte, ASR A[31:26] bits are valid)  
H
128 MB (08000000 byte, ASR A[31:27] bits are valid)  
H
256 MB (10000000 byte, ASR A[31:28] bits are valid)  
H
512 MB (20000000 byte, ASR A[31:29] bits are valid)  
H
1024 MB (40000000 byte, ASR A[31:30] bits are valid)  
H
2048 MB (80000000 byte, ASR A[31] bit is valid)  
H
ASZ3-0 are used to set the size of each area by modifying the number of bits for address comparison to a value  
different from ASR. Thus, an ASR contains bits that are not compared. Bits ASZ3-0 of ACR0 are initialized to  
1111 (0F ) by RST. Despite this setting, however, the CS0 area just after RST is executed is specially set from  
B
H
00000000 to FFFFFFFF (setting of entire area). The entire-area setting is reset after the first write to ACR0  
H
H
and an appropriate size is set as indicated in Table 2-1 "Area Size Settings".  
[Bits 11-10] DBW1-0 (Data Bus Width 1-0)  
These bits set the data bus width of each chip select area as indicated in Table 2-2 "Setting of the Data Bus  
Width of Each Chip Select Area":  
Table 2-2 Setting of the Data Bus Width of Each Chip Select Area  
DBW1  
DBW0  
Data bus width  
0
0
1
1
0
1
0
1
8 bits (byte access)  
16 bits (halfword access)  
32 bits (word access)  
Reserved Setting disabled  
The same values as those of the WTH bits of the mode vector are written automatically to bits DBW1-0 of ACR0  
during the reset sequence.  
[Bits 9-8] BST1-0 (Burst Size 1-0)  
These bits set the maximum burst length of each chip select area as indicated in Table 2-3 "Setting of the  
Maximum Burst Length of Each Chip Select".  
Table 2-3 Setting of the Maximum Burst Length of Each Chip Select  
BST1  
BST0  
Maximum burst length  
0
0
0
1
1 (single access)  
2 bursts (address boundary: 1 bit)  
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Chapter 31 External Bus  
2.External Bus Interface Registers  
Table 2-3 Setting of the Maximum Burst Length of Each Chip Select  
BST1  
BST0  
Maximum burst length  
4 bursts (address boundary: 2 bits)  
8 bursts (address boundary: 3 bits)  
1
1
0
1
In areas for which a burst length other than the single access is set, continuous burst access is performed within  
the address boundary determined by the burst length only when prefetch access is performed or data having a  
size exceeding the bus width is read.  
Setting of 2 bursts or less as the maximum burst length in the bus width 16-bit area is recommended.  
RDY input is ignored in areas for which any burst length other than the single access is set.  
[Bit 7] SREN (ShaRed Enable)  
This bit sets enabling or disabling of sharing of each chip select area by BRQ/BGRNT as indicated in the  
following table.  
SREN  
Sharing enable/disable  
Disable sharing by BRQ/BGRNT  
(CSn cannot be high impedance)  
0
Enable sharing by BRQ/BGRNT  
(CSn can be high impedance)  
1
In areas where sharing is enabled, chip select output (CSn) is set to high impedance while the bus is open  
(during BGRNT=Low output). In areas where sharing is disabled, chip select output (CSn) is not set to high  
impedance even though the bus is open (during BGRNT=Low output).  
Access strobe output (AS, BAA, RD, WR0, WR1, WR2, WR3, WR, MCLK, MCLKE) is set to high impedance only  
if sharing of all areas enabled by CSER is enabled.  
[Bit 6] PFEN (PreFetch Enable)  
This bit sets enabling and disabling of prefetching of each chip select area as indicated in the following table.  
PFEN  
Prefetch enable/disable  
Disable prefetch  
Enable prefetch  
0
1
When reading from an area for which prefetching is enabled, the subsequent address is read in advance and  
stored in the built-in prefetch buffer. When the stored address is accessed from the internal bus, the lookahead  
data in the prefetch buffer is returned without performing external access.  
For more information, see Section 8. "Prefetch Operation".  
[Bit 5] WREN(WRite Enable)  
This bit sets enabling and disabling of writing to each chip select area.  
WREN  
Write enable/disable  
0
Disable write  
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Chapter 31 External Bus  
2.External Bus Interface Registers  
WREN  
Write enable/disable  
1
Enable write  
If an area for which write operations are disabled is accessed for a write operation from the internal bus, the  
access is ignored and no external access at all is performed. Set the WREN bit of areas for which write  
operations are not required, such as data areas, to 0.  
[Bit 4] LEND (Little ENDian select)  
This bit sets the order of bytes of each chip select area as indicated in the following table.  
LEND  
Order of bytes  
0
1
Big endian  
Little endian  
Be sure to set the LEND bit of ACR0 to 0. CS0 supports only the big endian method.  
[Bits 3-0] TYP3-0 (TYPe select)  
These bits set the access type of each chip select area as indicated in Table 2-4 "Access Type Settings for  
Each Chip Select Area".  
Table 2-4 Access Type Settings for Each Chip Select Area  
TYP3  
TYP2  
TYP1  
TYP0  
Access type  
Normal access (asynchronous SRAM, I/O,  
and single/page/burst-ROM/FLASH)  
0
0
x
x
Address data multiplex access (8/16-bit bus  
width only)  
0
0
0
1
x
x
x
x
x
x
0
1
Disable WAIT insertion by the RDY pin.  
Enable WAIT insertion by the RDY pin  
(disabled during bursts).  
Use the WR0-WR3 pins as write strobes  
(WEn is always H).  
0
x
0
x
*1  
0
1
1
1
1
1
1
1
x
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
x
0
1
0
1
0
1
0
Use the WEn pin as the write strobe.  
*2  
Memory type A: SDRAM/FCRAM  
*2  
Memory type B: FCRAM  
Setting disabled  
Setting disabled  
Setting disabled  
Setting disabled  
Setting disabled  
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Chapter 31 External Bus  
2.External Bus Interface Registers  
Table 2-4 Access Type Settings for Each Chip Select Area  
TYP3  
TYP2  
TYP1  
TYP0  
Access type  
Mask area setting (The access type is the  
same as that of the overlapping area)  
1
1
1
1
*3  
*1: If this setting is made, WR0-WR3 can be used as the enable of each bit.  
*2: Only the ACR6 and ACR7 registers are valid. The ACR0, ACR1, ACR2, ACR3, ACR4,  
and ACR5 registers are disabled.  
*3: See the CS area mask setting function (next bullet).  
Set the access type as the combination of all bits.  
For details of the operations of each access type, see the explanation of operation of each type.  
● CS area mask setting function  
If you want to set an area some of whose operation settings are changed for a certain CS area (referred to as the  
base setting area), you can set TYPE3-0 of ARC in another CS area to 1111 so that the area can function as a  
mask setting area.  
If you do not use the mask setting function, disable any overlapping area settings for multiple CS areas.  
Access operations to the mask setting area are as follows:  
•
•
•
CS corresponding to a mask setting area is not asserted.  
CS corresponding to a base setting area is not asserted.  
For the following ACR settings, the settings on the mask setting area side are valid:  
•
•
•
•
•
Bits 11-10 (DBW1-0): Bus width setting  
Bits 9-8 (BST1-0): Burst length setting  
Bit 7 (SREN): Sharing-enable setting  
Bit 6 (PFEN): Prefetch-enable setting  
Bit 5 (WREN): Write-enable setting (For this setting only, only a setting that is the same as that of the base  
setting area is allowed)  
•
Bit 4 (LEND): Little endian setting  
•
For the following ACR setting, the setting on the base setting area side is valid:  
Bits 3-0 (TYPE3-0): Access type setting  
•
•
•
For the AWR settings, the settings on the mask setting area side are valid.  
For the CHER settings, the settings on the mask setting area side are valid.  
A mask setting area can be set for only part of another CS area (base setting area). You cannot set a mask  
setting area for an area without a base setting area. Use care when setting ASR and bits ASZ3-0 of ACR.  
The following restrictions apply when using these bits:  
•
•
•
A write-enable setting cannot be implemented by a mask.  
Write-enable settings in the base CS area and the mask setting area must be identical.  
If write operations to a mask setting area are disabled, the area is not masked and operates as a base CS  
area.  
•
If write operations to the base CS area are disabled but are enabled to the mask setting area, the area has no  
base, resulting in malfunctions.  
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Chapter 31 External Bus  
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2.3 Area Wait Register (AWR0-7)  
This section explains the configuration and functions of the area wait registers  
(AWR0-7).  
■ Configuration of the Area Wait Registers (AWR0-7)  
The area wait registers (AWR0-7: Area Wait Register 0-7) specify various kinds of waits for each chip select area.  
Figure 2-3 "Configuration of the Area Wait Registers (AWR0-7)" shows the configuration of the area wait  
registers (AWR0-7).  
Figure 2-3 Configuration of the Area Wait Registers (AWR0-7) (Continued on next page)  
Initial value  
AWR0H  
31  
30  
29  
28  
27  
26  
25  
24  
INIT  
RST  
Access  
W/R  
00000660H W15 W14 W13 W12 W11 W10 W09 W08  
01111111b  
01111111b  
AWR0L  
23  
22  
21  
20  
19  
18  
17  
16  
00000661H W07 W06 W05 W04 W03 W02 W01 W00  
W/R  
11111011B  
11111011B  
15  
14  
13  
12  
11  
10  
9
8
AWR1H  
00000662H W15 W14 W13 W12 W11 W10 W09 W08  
xxxxxxxxb  
xxxxxxxxb  
xxxxxxxxb  
xxxxxxxxb  
W/R  
W/R  
7
6
5
4
3
2
1
0
AWR1L  
00000663H W07 W06 W05 W04 W03 W02 W01 W00  
31  
30  
29  
28  
27  
26  
25  
24  
AWR2H  
xxxxxxxxb  
xxxxxxxxb  
xxxxxxxxb  
xxxxxxxxb  
00000664H W15 W14 W13 W12 W11 W10 W09 W08  
W/R  
W/R  
23  
22  
21  
20  
19  
18  
17  
16  
AWR2L  
00000665H W07 W06 W05 W04 W03 W02 W01 W00  
15  
14  
13  
12  
11  
10  
9
8
AWR3H  
00000666H W15 W14 W13 W12 W11 W10 W09 W08  
W/R  
W/R  
xxxxxxxxb  
xxxxxxxxb  
xxxxxxxxb  
xxxxxxxxb  
AWR3L  
00000667H W07 W06 W05 W04 W03 W02 W01 W00  
7
6
5
4
3
2
1
0
31  
30  
29  
28  
27  
26  
25  
24  
AWR4H  
xxxxxxxxb  
xxxxxxxxb  
xxxxxxxxb  
xxxxxxxxb  
00000668H W15 W14 W13 W12 W11 W10 W09 W08  
W/R  
W/R  
AWR4L  
23  
22  
21  
20  
19  
18  
17  
16  
00000669H W07 W06 W05 W04 W03 W02 W01 W00  
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Initial value  
AWR5H  
0000066AH W15 W14 W13 W12 W11 W10 W09 W08  
15  
14  
13  
12  
11  
10  
9
8
INIT  
RST  
Access  
W/R  
xxxxxxxxb  
xxxxxxxxb  
AWR5L  
7
6
5
4
3
2
1
0
xxxxxxxxb  
xxxxxxxxb  
W/R  
0000066BH W07 W06 W05 W04 W03 W02 W01 W00  
31  
30  
29  
28  
27  
26  
25  
24  
AWR6H  
xxxxxxxxb  
xxxxxxxxb  
xxxxxxxxb  
xxxxxxxxb  
W/R  
W/R  
0000066CH W15 W14 W13 W12 W11 W10 W09 W08  
23  
22  
21  
20  
19  
18  
17  
16  
AWR6L  
0000066DH W07 W06 W05 W04 W03 W02 W01 W00  
AWR7H  
15  
14  
13  
12  
11  
10  
9
8
W/R  
W/R  
xxxxxxxxb  
xxxxxxxxb  
xxxxxxxxb  
xxxxxxxxb  
0000066EH W15 W14 W13 W12 W11 W10 W09 W08  
7
6
5
4
3
2
1
0
AWR7L  
0000066FH W07 W06 W05 W04 W03 W02 W01 W00  
The function of each bit changes according to the access type (TYP(3-0) bits) setting of the ACR0-7 registers,. A  
chip select area determined by either of the following settings becomes the area for normal access or a address/  
data multiplex access operation.  
TYP3  
TYP2  
TYP1  
TYP0  
Access type  
Normal access (asynchronous SRAM, I/O,  
and single/page/burst-ROM/FLASH)  
0
0
x
x
Address data multiplex access (8/16-bit bus  
width only)  
0
1
x
x
The following lists the functions of each AWR0-7 bit for a normal access or address/data multiplex access area.  
Since the initial values of registers other than AWR0 are undefined, set them to their initial values before enabling  
each area with the CSER register.  
The following explains the functions of the bits in the area wait registers (AWR0-7).  
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[Bits 15-12] W15-12 (First Wait Cycle)  
These bits set the number of auto-wait cycles to be inserted into the first access cycle of each cycle. Except  
for the burst access cycles, only this wait setting is used.  
Table 2-5 "Settings for the Number of Auto-Wait Cycles (During First Access)" lists the settings for the number  
of auto-wait cycles during first access.  
Table 2-5 Settings for the Number of Auto-Wait Cycles (During First Access)  
W15  
W14  
W13  
W12  
First access wait cycle  
Auto-wait cycle 0  
0
0
0
0
0
0
0
1
Auto-wait cycle 1  
...  
...  
1
1
1
1
Auto-wait cycle 15  
[Bits 11-8] W11-08 (Inpage Access Wait Cycle)  
These bits set the number of auto-wait cycles to be inserted into the inpage access cycle during burst access.  
They are valid only for burst cycles.  
Table 2-6 "Settings for the Number of Auto-Wait Cycles (During Burst Access)" lists the settings for the  
number of auto-wait cycles during burst access.  
Table 2-6 Settings for the Number of Auto-Wait Cycles (During Burst Access)  
W11  
W10  
W09  
W08  
Inpage access wait cycle  
Auto-wait cycle 0  
0
0
0
0
0
0
0
1
Auto-wait cycle 1  
...  
...  
1
1
1
1
Auto-wait cycle 15  
If the same value is set for the first access wait cycle and inpage access wait cycle, the access time for the  
address in each access cycle is not the same. This is because the inpage access cycle contains an address  
output delay.  
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[Bits 7,6] W07-06 (Read -> Write Idle Cycle)  
The read -> write idle cycle is set to prevent collision of read data and write data on the data bus when a write  
cycle follows a read cycle. During an idle cycle, all chip select signals are negated and the data terminals  
maintain the high impedance state. If a write cycle follows a read cycle or an access operation to another chip  
select area occurs after a read cycle, the specified idle cycle is inserted. Table 2-7 "Settings of the Idle Cycle"  
lists the settings for idle cycles.  
Table 2-7 Settings of the Idle Cycle  
W07  
W06  
Read -> write idle cycles  
0
0
1
1
0
1
0
1
0 cycle  
1 cycle  
2 cycles  
3 cycles  
[Bits 5, 4] W05, W04 (Write Recovery Cycle)  
The write recovery cycle is set if a device that limits the access period after write access is to be controlled.  
During a write recovery cycle, all chip select signals are negated and the data pins maintain the high  
impedance state. If the write recovery cycle is set to 1 or more, a write recovery cycle is always inserted after  
write access.  
Table 2-8 "Settings for the Number of Write Recovery Cycles" lists the settings for the number of write  
recovery cycles.  
Table 2-8 Settings for the Number of Write Recovery Cycles  
W05  
W04  
Write recovery cycles  
0
0
1
1
0
1
0
1
0 cycle  
1 cycle  
2 cycles  
3 cycles  
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Chapter 31 External Bus  
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[Bits 3] W03 (WR0-WR3, WRn Output Timing Selection)  
The WR0-WR3, WRn output timing setting selects whether to use write strobe output as an asynchronous  
strobe or synchronous write enable. The asynchronous strobe setting corresponds to normal memory/IO.  
The synchronous enable setting corresponds to clock-synchronized memory/IO (such as the memory in an  
ASIC).  
W03  
WR0-WR3, WRn output timing selection  
MCLK synchronous write enable output (valid from AS=L)  
Asynchronous write strobe output (normal operation)  
0
1
If synchronous write enable (W03 bit of AWR is 1) is used, operations are as follows:  
•
•
•
The timing of synchronous write enable output assumes that the output is captured by the rising edge of  
MCLK output of an external memory access clock. This timing is different from the asynchronous strobe  
output timing.  
The WR0-WR3 and WRn terminal output asserts synchronous write enable output at the timing at which AS  
pin output is asserted. For a write to an external bus, the synchronous write enable output is L. For a read  
from an external bus, the synchronous write enable output is H.  
Write data is output from the external data output pin in the clock cycle following the cycle in which  
synchronous write enable output is asserted. If write data cannot be output because the internal bus is  
temporarily unavailable, assertion of synchronous write enable output may be extended until write data can be  
output.  
•
Read strobe output (RD) functions as an asynchronous read strobe regardless of the setting of the WR0-WR3  
and WRn output timing. Use it as is for controlling the data I/O direction.  
If synchronous write enable output is used, the following restrictions apply:  
•
Do not make the following additional wait settings:  
•
•
CSn -> RD/WRn setup (Always set 0 for the W01 bit of AWR)  
First wait cycle setting (Always set 0000 for the W15-W12 bits of AWR)  
B
•
Do not make the following access type settings (TYPE3-0 bits in the ACR register (bits 3-0))  
•
•
•
Address/data multiplex bus setting (Always set 0 for the TYPE2 bit of ACR)  
Setting to use WR0-WR3 as a strobe (Always set 0 for the TYPE1 bit of ACR)  
RDY input enable setting (Always set 0 for the TYPE0 bit of ACR)  
•
For synchronous write enable output, always set 1(00 for bits BST1-0 bits of ACR) as the burst length.  
B
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Chapter 31 External Bus  
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[Bits 2] W02 (Address -> CSn Delay)  
The address -> CSn delay setting is made when a certain type of setup is required for the address when CSn  
falls or CSn edges are needed for successive accesses to the same chip select area.  
Set the address and set the delay from AS output to CS0-CS7 output.  
W02  
Address -> CSn delay  
0
1
No delay  
Delay  
If no delay is selected by setting 0, assertion of CS0-CS7 starts at the same timing that AS is asserted. If, at this  
point, successive accesses are made to the same chip select area, assertion of CS0-CS7 without change  
between two access operations may continue.  
If delay is specified by selecting 1, assertion of CS0-CS7 starts when the external clock memory MCLK output  
rises. If, at this point, successive accesses are made to the same chip select area, CS0-CS7 are negated at a  
timing between two access operations. If CS delay is selected, one setup cycle is inserted before asserting the  
read/write strobe after assertion of the delayed CSn (operation is the same as the CSn ->RD/WE setup setting of  
W01).  
The address -> CSn delay setting works for DACK signal (basic mode) output to the same area in the same way.  
DACK output in basic mode has the same waveforms as those of CS output to the same area.  
[Bits 1] W01 (CSn -> RD/WRn Setup Extension Cycle)  
The CSn -> RD/WRn setup extension cycle is set to extend the period before the read/write strobe is asserted  
after CSn is asserted. At least one setup extension cycle is inserted before the read/write strobe is asserted  
after CS is asserted.  
W01  
CSn -> RD/WRn setup delay cycle  
0
1
0 cycle  
1 cycle  
If 0 cycle is selected by setting 0, RD/WR0-WR3/WRn are output at the earliest when external clock MCLK output  
rises just after CS is asserted. WR0-WR3/WRn may be delayed one cycle or more depending on the internal bus  
state.  
If 1 cycle is selected by setting 1, RD/WR0-WR3/WRn are always output 1 cycle or more later.  
When successive accesses are made within the same chip select area without negating CSn, a setup extension  
cycle is not inserted. If a setup extension cycle for determining the address is required, set the W02 bit and insert  
the address -> CSn delay. Since CSn is negated for each access operation, the setup extension cycle is  
enabled.  
If the CSn delay set by W02 is inserted, this setup cycle is always enabled regardless of the setting of the W01  
bit.  
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[Bits 0] W00 (RD/WRn -> CSn Hold Extension Cycle)  
The RD/WRn -> CSn hold extension cycle is set to extend the period before negating CSn after the read/write  
strobe is negated. One hold extension cycle is inserted before CSn is negated after the read/write strobe is  
negated.  
W00  
RD/WRn -> CSn hold extension cycle  
0
1
0 cycle  
1 cycle  
If 0 cycle is selected by setting 0, CS0-CS7 are negated after the hold delay after it starts on the rising edge of  
external memory clock MCLK output after RD/WR0-WR3/WRn are negated.  
If 1 cycle is selected by setting 1, CS0-CS7 are negated one cycle later.  
When making successive accesses within the same chip select area without negating CSn, the hold extension  
cycle is not inserted. If a hold extension cycle for determining the address is required, set the W02 bit and insert  
the address -> CSn delay. Since CSn is negated for each access operation, this hold extension cycle is enabled.  
● Memory type A(SDRAM/FCRAM) and Memory type B(FCRAM)  
The chip select areas for which the access type (TYP3 to TYP0 bits) in the ACR6 and ACR7 registers has been  
set as in Table 1.2 - 18 serve for SDRAM/FCRAM access.  
Table 1.2 - 18 lists the access type settings (TYP3 to TYP0 bits).  
Table 2-9 Access Type Settings (TYP3 - TYP0 Bits)  
TYP3 TYP2 TYP1 TYP0  
Access type  
1
0
0
0
Memory type A: SDRAM/FCRAM (Auto - precharge is not used.)  
The following explains those functions of individual bits in AWR6 and AWR7 which apply to SDRAM access  
areas. As the initial value is undefined, set the access type before each area is enabled by the chip select area  
enable register (CSER).  
For all the areas connected to SDRAM/FCRAM, use the same settings for this type of registers.  
The following summarizes the functions of individual bits in the area wait registers (AWR6 and AWR7).  
[Bit 15] W15: Reserved bit  
Be sure to set this bit to 0.  
[Bits 14 - 12] W14 to W12 (RAS - CAS delay Cycle): RAS - CAS delay cycles  
Set these bits to the number of cycles from RAS output to CAS output.  
Table 4.2 - 19 lists the settings for the number of cycles from RAS output to CAS output.  
Table 2-10 Setting the Number of Cycles from RAS Output to CAS Output  
W14  
W13  
0
W12  
RAS-CAS delay cycle  
0
0
0
0
1 cycle  
2 cycles  
...  
0
...  
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Chapter 31 External Bus  
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Table 2-10 Setting the Number of Cycles from RAS Output to CAS Output  
W14  
W13  
W12  
RAS-CAS delay cycle  
1
1
1
8 cycles  
For all the areas connected to SDRAM/FCRAM, set these bits to the same RAS - CAS delay cycle.  
[Bit 11] W11: Reserved bit  
Be sure to set this bit to 0.  
[Bits 10 - 8] W10 to W08 (CAS latency Cycle): CAS latency  
Set these bits to the CAS latency.  
Table 4.2 - 20 lists the settings for the CAS latency.  
Table 2-11 CAS Latency Setting  
W10  
W09  
0
W08  
CAS latency  
1 cycle  
2 cycles  
...  
0
0
0
0
0
...  
1
1
1
8 cycles  
For all the areas connected to SDRAM/FCRAM, set these bits to the same CAS latency.  
[Bits 7 - 6] W07 and W06 (Read - >Write Cycle): Read - to - write cycle  
Set these bits to the minimum number of cycles from the last read data input cycle to the write command  
issuance. Set the minimum number of cycles taken until issuance.  
Table 4.2 - 21 lists the settings for the read - to - write cycle.  
Table 2-12 Read - to - write cycle  
W07  
W06  
Read - to - write cycle  
1 cycle  
0
0
1
1
0
1
0
1
2 cycles  
3 cycles  
4 cycles  
For all the areas connected to SDRAM/FCRAM, set these bits to the same read - to - write cycle.  
The number of read - to - write idle cycles is one smaller than the number of cycles set by this bit.  
[Bits 5 - 4] W05 and W04 (Write Recovery Cycle): Write recovery cycle  
Set these bits to the minimum number of cycles from the last write data output to the next read command  
issuance.  
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Chapter 31 External Bus  
2.External Bus Interface Registers  
Table 4.2 - 22 lists the settings for the write recovery cycle.  
Table 2-13 Write recovery cycle  
W05  
W04  
Write recovery cycle  
Prohibited  
0
0
1
1
0
1
0
1
2 cycles  
3 cycles  
4 cycles  
For all the areas connected to SDRAM/FCRAM, set these bits to the same write recovery cycle.  
[Bits 3 - 2] W03 and W02 (RAS Active time): RAS active time  
Set these bits to the minimum number of cycles for RAS active time.  
Table 4.2 - 23 lists the settings for RAS active time.  
Table 2-14 RAS active time  
W03  
W02  
RAS active time  
1 cycle  
0
0
1
1
0
1
0
1
2 cycles  
5 cycles  
6 cycles  
For all the areas connected to SDRAM/FCRAM, set these bits to the same RAS active time.  
[Bits 1 - 0] W01 and W00 (RAS precharge cycle): RAS precharge cycles  
Set these bits to the number of RAS precharge cycles.  
Table 4.2 - 24 lists the settings for the RAS precharge cycle.  
Table 2-15 RAS precharge cycle  
W03  
W02  
RAS precharge cycle  
1 cycle  
0
0
1
1
0
1
0
1
2 cycles  
3 cycles  
4 cycles  
For all the areas connected to SDRAM/FCRAM, set these bits to the same RAS precharge cycle.  
2.4 Memory setting register (MCRA for SDRAM/FCRAM auto - precharge OFF mode)  
This section describes the configuration and the function of memory setting register (MCRA for  
SDRAM/FCRAM auto - precharge OFF mode).  
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Chapter 31 External Bus  
2.External Bus Interface Registers  
■ Structure of the Memory Setting Register (MCRA for SDRAM/FCRAM auto - precharge OFF  
mode)  
Memory setting register (MCRA for SDRAM/FCRAM auto - precharge OFF mode)  
The memory setting register (MCRA: Memory Setting Register for extend type - A for SDRAM/FCRAM auto -  
precharge OFF mode) is used to make various settings for SDRAM/FCRAM connected to the chip select area.  
Figure 2-4 shows the bit configuration of the memory setting register (MCRA for SDRAM/FCRAM auto -  
precharge OFF mode).  
Figure 2-4 Bit configuration of the memory setting register (MCRA for SDRAM/FCRAM auto - precharge  
OFF mode)  
Initial value  
bit  
31  
30  
29  
28  
27  
26  
25  
24  
XXXXXXXX (INIT)  
B
00000670  
Reserved PSZ2 PSZ1 PSZ0 WBST BANK ABS1 ABS0  
Address  
H
XXXXXXXX (RST)  
B
R/W R/W  
R/W R/W R/W R/W  
R/W  
R/W  
The register serves as the area for making various settings for SDRAM/FCRAM connected to the chip select area  
for which the access type (TYP3 to TYP0 bits) in the ACR6 and ACR7 registers has been set as in Table 2-25 .  
Table 2-25 lists the access type settings (TYP3 to TYP0 bits).  
Table 2-16 Access type settings (TYP3 to TYP0 bits)  
TYP3 TYP2 TYP1 TYP0  
Access type  
1
0
0
0
Memory type A:SDRAM/FCRAM(not used auto precharge)  
MCRB shares register hardware with MCRA. Updating the MCRA therefore updates the MCRB accordingly.  
The following summarizes the functions of individual bits in the memory setting register (MCRA for SDRAM/  
FCRAM auto - precharge OFF mode).  
[Bit 31] Reserved bit  
Be sure to set this bit to 0.  
[Bits 30 - 28] PSZ2, PSZ1, PSZ0 (Page SiZe): Page size  
Set these bits to the page size of SDRAM to be connected.  
Table 2-26 lists the settings for the page size of SDRAM connected.  
Table 2-17 Settings for the page size of SDRAM  
PSZ2 PSZ1 PSZ0  
Page size of SDRAM  
8-bit column address:A0 to A7(256 memory words)  
9-bit column address:A0 to A8(512 memory words)  
10-bit column address:A0 to A9(1024 memory words)  
11-bit column address:A0 to A9, A11(2048memory words)  
Prohibited  
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
[Bit 27] WBST (Write BurST enable): Write burst setting  
Set this bit to select whether to burst - write for write access.  
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Table 2-27 lists the settings for burst write.  
Table 2-18 Settings for burst write  
WBST  
Settings for burst write  
0
1
Single write  
Burst write  
For connecting FCRAM, be sure to set the bit to 1.  
FCRAM supports neither burst read nor single write mode.  
[BIt 26] BANK (BANK type select): Bank number setting  
Set this bit to the number of banks of SDRAM to be connected.  
Table 2-28 lists the settings for bank number.  
Table 2-19 settings for bank number  
BANK  
Settings for bank number  
0
1
2 banks  
4 banks  
[Bits 25 - 24] ABS1, ABS0 (Active Bank Select): Setting of active bank number  
Set these bits to the maximum number of banks to be made active simultaneously.  
Table 2-29 lists the settings for the number of active banks.  
Table 2-20 Settings for the number of active banks  
ABS1 ABS0  
Number of active banks  
0
0
1
1
0
1
0
1
1 bank  
2 banks  
3 banks  
4 banks  
2.5 Memory setting register (MCRB for FCRAM auto - precharge ON mode)  
This section describes the memory setting register (MCRB for FCRAM auto - precharge ON  
mode).  
■ Structure of the Memory Setting Register (MCRB for FCRAM auto - precharge ON mode)  
Settings for Memory configuration register (MCRB: Memory Configuration Register for extend type - B for FCRAM  
auto - precharge ON mode) is used to make various settings for FCRAM connected to the chip select area.  
Figure 2-5 shows the bit configuration of the memory setting register (MCRB for FCRAM auto - precharge ON  
mode).  
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Chapter 31 External Bus  
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Figure 2-5 Structure of the Memory Setting Register (MCRB for FCRAM auto - precharge ON mode)  
Initial value  
bit  
23  
22  
21  
20  
19  
18  
17  
16  
XXXXXXXX (INIT)  
B
00000671  
Reserved PSZ2 PSZ1 PSZ0 WBST BANK ABS1 ABS0  
Address  
H
XXXXXXXX (RST)  
B
R/W R/W  
R/W R/W R/W R/W  
R/W  
R/W  
The register serves as the area for making various settings for FCRAM connected to the chip select area for  
which the access type (TYP3 to TYP0 bits) in the ACR6 and ACR7 registers has been set as in Table 2-30 .  
Table 2-30 lists the access type settings (TYP3 to TYP0 bits).  
Table 2-21 Access type settings (TYP3 to TYP0 bits)  
TYP3 TYP2 TYP1 TYP0  
Access type  
1
0
0
1
Memory type B: FCRAM (used auto precharge)  
MCRB shares register hardware with MCRA. Updating the MCRB therefore updates the MCRA accordingly.  
The functions are the same as MCRA. Note, however, that the function of the WBST bit is not available to this  
TYPE setting.  
(FCRAM supports neither burst read nor single write mode.)  
2.6 I/O Wait Registers for DMAC (IOWR0-3)  
This section explains the configuration and functions of the I/O wait registers for DMAC (IOWR0-  
3).  
■ Configuration of the I/O Wait Registers for DMAC (IOWR0-3)  
The I/O wait registers for DMAC (IOWR0-3: I/O Wait Register for DMAC 0-3) set various kinds of waits during  
DMA fly-by access.  
Figure 2-6 "Configuration of the I/O wait registers for DMAC (IOWR0, 1, 2, 3)" shows the configuration of the I/O  
wait registers for DMAC (IOWR0-3).  
Figure 2-6 Configuration of the I/O Wait Registers for DMAC (IOWR0-3)  
Initial value  
INIT  
RST  
Access  
W/R  
IOWR0  
31  
30  
29  
28  
27  
26  
25  
24  
xxxxxxxxb  
xxxxxxxxb  
0000 0678H RYE0 HLD0 WR01 WR00 IW03 IW02 IW01 IW00  
23  
22  
21  
20  
19  
18  
17  
16  
IOWR1  
xxxxxxxxb  
xxxxxxxxb  
xxxxxxxxb  
xxxxxxxxb  
0000 0679H RYE1 HLD1 WR11 WR10 IW13 IW12 IW11 IW10  
W/R  
W/R  
W/R  
15  
14  
13  
12  
11  
10  
9
8
IOWR2  
0000 067aH RYE2 HLD2 WR21 WR20 IW23 IW22 IW21 IW20 xxxxxxxxb  
7
6
5
4
3
2
1
0
IOWR3  
0000 067bH RYE3 HLD3 WR31 WR30 IW33 IW32 IW31 IW30 xxxxxxxxb  
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Chapter 31 External Bus  
2.External Bus Interface Registers  
■ Functions of Bits in the I/O Wait Registers for DMAC (IOWR0-3)  
The following explains the functions of the bits in the I/O wait registers for DMAC.  
[Bits 31, 23] RYE0,1 (RDY enable 0,1)  
These bits set the wait control, using RDY, of channels 0-3 during DMAC fly-by access.  
RYEn  
RDY function setting  
Disable RDY input for I/O access.  
Enable RDY input for I/O access.  
0
1
When 1 is set, wait insertion by the RDY pin can be performed during fly-by transfer on the relevant channel.  
IOWR and IORD are extended until the RDY pin is enabled. Also, RD/WR0-WR3/WR on the memory side are  
extended synchronously. If the chip select area of the fly-by transfer destination is set to RDY-enabled in the  
ACR register, wait insertion by the RDY pin can be performed regardless of the RYEn bit of IOWR. When the  
chip select area of the fly-by transfer destination is set to RDY-disabled in the ACR register, wait insertion by the  
RDY pin can only be performed during fly-by access if the area is set to RDY-enabled by the RYEn bit on the  
IOWR side.  
[Bits 30,22] HLD0,1 (Hold Wait Control)  
These bits control the hold cycle of the read strobe signal on the transfer source access side during DMA fly-  
by access.  
HLDn  
Hold wait setting  
Do not insert a hold extension cycle.  
Insert a hold extension cycle to extend the read cycle by one cycle.  
0
1
If 0 is set, the read strobe signal (RD for memory -> I/O and IORD for I/O -> memory) and the write strobe signal  
(IOWR for memory -> I/O and WR0-WR3 and WR for I/O -> memory) on the transfer source access side are  
output at the same timing.  
If 1 is set, the read strobe signal is output one cycle longer than the write strobe signal to secure a hold time for  
data at the transfer source access side when sending it to the transfer destination.  
[Bits 29, 28, 21, 20] WR01/00, WR11/00 (I/O Idle Wait)  
These bits set the number of idle cycles for continuous access during DMA fly-by access. Table 2-22 "Settings  
for the Number of I/O Idle Cycles" lists the settings for the number of I/O idle cycles.  
Table 2-22 Settings for the Number of I/O Idle Cycles  
WRn1  
WRn0  
Setting of the number of I/O idle cycles  
0
0
1
1
0
1
0
1
0 cycle  
1 cycle  
2 cycles  
3 cycles  
If one or more cycles is set as the number of idle cycles, cycles equal to the number specified are inserted after I/  
O access during DMA fly-by access. During the idle cycles, all CS and strobe output is negated and the data pin  
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Chapter 31 External Bus  
2.External Bus Interface Registers  
is set to the high impedance state.  
533  
Chapter 31 External Bus  
2.External Bus Interface Registers  
[Bits 27-24, 19-16, 11-8] IW03-00,IW13-10 (I/O Access Wait)  
These bits set the number of auto-wait cycles for I/O access during DMA fly-by access.  
Table 2-23 "Settings for the Number of I/O Wait Cycles" lists the settings for the number of I/O wait cycles.  
Table 2-23 Settings for the Number of I/O Wait Cycles  
IWn3  
IWn2  
IWn1  
IWn0  
Number of I/O wait cycles  
0 cycle  
0
0
0
0
0
0
0
1
1 cycle  
...  
...  
1
1
1
1
15 cycle  
Because data is synchronized between the transfer source and transfer destination, the I/O side setting of the  
IWnn bits and the wait setting for the fly-by transfer destination (such as memory), whichever is larger, is used as  
the number of wait cycles to be inserted. Consequently, more wait cycles than specified by the IWnn bits may be  
inserted.  
2.7 Chip Select Enable Register (CSER)  
Because data is synchronized between the transfer source and transfer destination, the I/O side  
setting of the IWnn bits and the wait setting for the fly-by transfer destination (such as memory),  
whichever is larger, is used as the number of wait cycles to be inserted. Consequently, more  
wait cycles than specified by the IWnn bits may be inserted.  
■ Configuration of the Chip Select Enable Register (CSER)  
The chip select enable register (CSER: Chip Select Enable register) enables and disables each chip select area.  
Figure 2-7 "Configuration of the Chip Select Enable Register (CSER)" shows the configuration of the chip select  
enable register (CSER).  
Figure 2-7 Configuration of the Chip Select Enable Register (CSER)  
Initial value  
INIT  
RST  
Access  
R/W  
31  
30  
29  
28  
27  
26  
25  
24  
00000680H CSE7 CSE6 CSE5 CSE4 CSE3 CSE2 CSE1 CSE0 00000001B 00000001B  
■ Functions of Bits in the Chip Select Enable Register (CSER)  
The following explains the functions of the bits in the chip select enable register (CSER).  
[Bits 31-24] CSE7-0 (Chip Select Enable 0-7)  
These bits are the chip select enable bits for CS0-CS7.  
The initial value is 00000001 , which enables only the CS0 area.  
B
When 1 is written, a chip select area operates according to the settings of ASR0-7, ACR0-7, and AWR0-7.  
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Chapter 31 External Bus  
2.External Bus Interface Registers  
Before setting this register, be sure to make all settings required for the corresponding chip select areas.  
CSE7-0  
Area control  
Disable  
0
1
Enable  
Table 2-24 " CSn Corresponding to the Chip Select Enable Bits" lists the corresponding CSn for the chip select  
enable bits.  
Table 2-24 CSn Corresponding to the Chip Select Enable Bits  
CSE bit  
Corresponding CSn  
Bit 24: CSE0  
Bit 25: CSE1  
Bit 26: CSE2  
Bit 27: CSE3  
Bit 28: CSE4  
Bit 29: CSE5  
Bit 30: CSE6  
Bit 31: CSE7  
CS0  
CS1  
CS2  
CS3  
CS4  
CS5  
CS6  
CS7  
2.8 Cache Enable Register (CHER)  
This section explains the configuration and functions of the cache enable register (CHER).  
■ Configuration of the Cache Enable Register (CHER)  
The cache enable register (CHER: CacHe Enable Register) controls the transfer of data read from each chip  
select area.  
Figure 2-8 "Configuration of the Cache Enable Register (CHER)" shows the configuration of the cache enable  
register (CHER).  
Figure 2-8 Configuration of the Cache Enable Register (CHER)  
Initial value  
23  
22  
21  
20  
19  
18  
17  
16  
INIT  
RST  
Access  
00000681H CHE7 CHE6 CHE5 CHE4 CHE3 CHE2 CHE1 CHE0 11111111B 111111111B R/W  
■ Functions of Bits in the Cache Enable Register (CHER)  
The following explains the functions of the bits in the cache enable register (CHER).  
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Chapter 31 External Bus  
2.External Bus Interface Registers  
[Bits 23-16] CHE7-0 (Cache Enable 7-0)  
These bits enable and disable each chip select area for transfers to the built-in cache.  
CHEn  
Cache area setting  
0
1
Not a cache area (data read from the applicable area is not saved in the cache)  
Cache area (data read from the applicable area is saved in the cache)  
2.9 Pin/Timing Control Register (TCR)  
This section explains the configuration and functions of the pin/timing control register and its  
function.  
■ Configuration of the Pin/Timing Control Register (TCR)  
The pin/timing control register (TCR: Terminal and Limiting Control Register) controls the functions related to the  
general external bus interface controller, such as the setting of common pin functions and timing control.  
Figure 2-9 "Configuration of the Pin/Timing Control Register (TCR)" shows the configuration of the pin/timing  
control register (TCR).  
Figure 2-9 Configuration of the Pin/Timing Control Register (TCR)  
Initial value  
7
6
5
4
3
2
1
0
INIT  
RST  
Access  
R/W  
Reserved Reserved Reserved  
00000683H BREN PSUS PCLR  
RDW1 RDW0 00000000B 0000xxxxB  
■ Functions of Bits in the Pin/Timing Control Register (TCR)  
The following explains the functions of the bits in the pin/timing control register (TCR).  
[Bit 7] BREN (BRQ Enable)  
This bit enables BRQ pin input and external bus sharing.  
BREN  
BRQ input enable setting  
No bus sharing by BRQ/BGRNT.  
BRQ input is disabled.  
0
Bus sharing by BRQ/BGRNT.  
BRQ input is enabled.  
1
In the initial state (0), BRQ input is ignored. When 1 is set, the bus is made open (control with high impedance)  
and BGRNT is activated (L level is output) when the bus is ready to be made open after the BRQ input becomes  
H level.  
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Chapter 31 External Bus  
2.External Bus Interface Registers  
[Bit 6] PSUS (Prefetch suspend)  
This bit controls temporary stopping of prefetch to all areas.  
PSUS  
Prefetch control  
0
1
Enable prefetch  
Suspend prefetch  
If 1 is set, no new prefetch operation is performed before 0 is written. Since during this time the contents of the  
prefetch buffer are not deleted unless a prefetch buffer occurs, clear the prefetch buffer using the PCLR bit  
function (bit 5) before restarting prefetch.  
[Bit 5] PCLR (Prefetch buffer clear)  
This bit completely clears the prefetch buffer.  
PCLR  
Prefetch buffer control  
0
1
Normal state  
Clear the prefetch buffer.  
If 1 is written, the prefetch buffer is cleared completely. When clearing is completed, the bit value automatically  
returns to 0. Interrupt (set to 1) the prefetch by the PSUS bit (bit 6) and then clear the buffer (It is also possible to  
write 11 to both the PSUS and PCLR bits).  
B
[Bit 4-2] Reserved  
This bit is reserved. Be sure to set it to 0.  
[Bits 1,0] RDW1,0 (Reduce Wait cycle)  
These bits instruct all chip select areas and fly-by I/O channels to reduce only the number of auto-wait cycles  
in the auto-access cycle wait settings uniformly while the AWR register settings are retained unchanged. The  
settings for idle cycles, recovery cycles, setup, and hold cycles are not affected. Table 2-25 "Settings for Wait  
Cycle Reduction" lists the settings for the wait cycle reduction for combinations of these bits.  
Table 2-25 Settings for Wait Cycle Reduction  
RDW1  
RDW0  
Wait cycle reduction  
Normal wait (AWR0-7 settings)  
0
0
1
1
0
1
0
1
1/2 (1-bit shift to the right) of the AWR0-7 settings  
1/4 (2-bit shift to the right) of the AWR0-7 settings  
1/8 (3-bit shift to the right) of the AWR0-7 settings  
The purpose of this function is to prevent an excessive access cycle wait during operation on a low-speed clock  
(for example, when the base clock is switched to low speed or the frequency division ratio setting of the external  
bus clock is large).  
To reset the wait cycle in these cases, each of the AWRs must usually be rewritten one at a time. However,  
when the RDW1/0 bit function is used, the access cycle wait is reduced for all of the AWRs in a single operation  
while all of the other high-speed clock settings in each register are retained.  
Before returning the clock to high speed, be sure to reset the RDW1/0 bits to 00 .  
B
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Chapter 31 External Bus  
2.External Bus Interface Registers  
2.10 Refresh Control Register (RCR)  
This section describes the bit configuration and functions of the refresh control register (RCR).  
■ Structure of the Refresh Control Register (RCR)  
The refresh control register (RCR) is used to make various refresh control settings for SDRAM.  
The setting of this register is meaningless as long as SDRAM control is not set for any area, in that case the  
register value must not be updated from the initial state.  
When read by a Read - modify - Write instruction, the SELF, RRLD, and PON bits always return to 0.  
Figure 2-10 shows the bit configuration of the refresh control register (RCR).  
Figure 2-10 Structure of the Refresh Control Register (RCR)  
Initial value  
bit  
RCRH  
31  
30  
29  
28  
27  
26  
25  
24  
00XXXXXX (INIT)  
B
Address  
Address  
0000 0684H  
SELF RRLD RFINT5 RFINT4 RFINT3 RFINT2 RFINT1 RFINT0  
00XXXXXX (RST)  
B
W/R  
16  
W/R  
21  
W/R  
20  
W/R  
19  
W/R  
17  
W/R  
18  
W/R  
23  
W/R  
22  
bit  
RCRL  
XXXX0XXX (INIT)  
B
0000 0685H BRST RFC2 RFC1 RFC0 PON  
W/R W/R  
W/R  
TRC2 TRC1 TRC0  
XXXX0XXX (RST)  
B
W/R  
W/R  
W/R  
W/R  
W/R  
■ Bit Functions of the Refresh Control Register (RCR)  
The following summarizes the functions of individual bits in the refresh control register (RCR).  
[Bit 31] SELF (SELF refresh assert): Self - refresh control  
This bit is used to control the self - refresh mode for memory that supports the self - refresh mode.  
Table 4.2-42 lists the settings for self - refresh control.  
Table 2-26 Settings for self - refresh control  
SELF  
Self - refresh control  
Auto - refresh or power - down  
Transition to self-refresh mode  
0
1
Setting the bit to 1 performs a self - refresh after issuing the SELF command. Writing 0 terminates the self -  
refresh mode.  
To hold the contents of SDRAM when putting the LSI into stop mode, use this bit to enter the self - refresh mode  
before entering the stop mode. At this time, centralized refreshing is performed before transition to the self -  
refresh mode. External access requests generated before it is completed are put on hold. The mode transits to  
the stop mode.  
The device is released from the self - refresh mode either when 0 is written to this bit or access to SDRAM  
occurs. At this time, centralized refreshing is performed immediately after the release. If external access such as  
SDRAM access is attempted, therefore, the external access request is kept on hold and the CPU stops operation  
for a while. An attempt to put the LSI into the stop mode when it cannot enter the self - refresh mode causes it to  
directly enter the power save mode, resulting in corruption of data in SDRAM.  
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Chapter 31 External Bus  
2.External Bus Interface Registers  
When read by a Read - modify - Write instruction, the SELF, RRLD, and PON bits always return to 0.  
(Bit 30) RRLD (Refresh counter ReLoaD): Refresh counter start control  
This bit is used to start and reload the fresh counter.  
Table 4.2-43 shows the function of refresh counter startup control.  
Table 2-27 Function of refresh counter startup control  
RRLD  
Refresh counter startup control  
Disable (no operation)  
Execute auto - refreshing once and reload the RFINT value.  
0
1
The refresh counter is inactive in the initial state.  
If this bit is set to 1 in this state, all the SDRAM areas currently enabled in the CSER are auto - refreshed either  
once in distributed refresh mode or the RFC - specified number of times in centralized refresh mode. After that,  
the values in the RFINT5 to RFINT0 bits are reloaded.  
From then on, the refresh counter starts being decremented. Whenever the counter causes an underflow from  
000000 , repeatedly, the values in the RFINT5 to RFINT0 bits are reloaded while at the same time auto -  
B
refreshing is performed once.  
The bit returns to 0 upon completion of reloading.  
To stop auto - refreshing, write 000000 to the RFINT5 to RFINT0 bits.  
B
When read by a Read - modify - Write instruction, the bit always returns a zero.  
[Bits 29 - 24] RFINT5 to RFINT0 (ReFresh INTerval): Auto - refresh interval  
Set these bits to the interval for automatic refreshing.  
The auto - refresh interval can be obtained for distributed refresh mode {(REFINT5 - REFINT0 value) x 32 x  
(external bus clock cycle)} or for centralized refresh mode {(REFINT5 - REFINT0 value) x 32 x (RFC specified  
number of times) x (external bus clock cycle)}  
Calculate the design value in consideration of the maximum RAS active time.  
The refresh counter keeps on being decremented even while the auto - refresh command is being issued.  
[Bit 23] BRST (BuRST refresh select): Burst refresh control  
This bit is used to control the operation mode for auto - refreshing.  
Table 4.2-44 shows the function of burst refresh control.  
Table 2-28 Function of burst refresh control  
BRST  
Burst refresh control  
0
1
Distributed refresh (Auto - refresh is activated at intervals.)  
Burst refresh (Auto - refresh is activated repeatedly at one time.)  
When distributed refreshing is set, the auto - refresh command is issued once at every refresh interval.  
When burst refreshing is set, the auto - refresh command is issued continuously for the number of times set in the  
refresh counter at every refresh interval.  
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Chapter 31 External Bus  
2.External Bus Interface Registers  
[Bits 22 - 20] RFC2, RFC1, RFC0 (ReFresh Count): Refresh count  
Set these bits to the number of times a refresh must be performed to refresh all SDRAM.  
Table 4.2-45 shows the number of times to refresh.  
Table 2-29 Number of times to refresh  
RFC2  
RFC1  
RFC0  
Number of times to refresh  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
256  
512  
1024  
2048  
4096  
8192  
Setting prohibited  
Refresh prohibited  
The number of times to refresh specified here is the number of times centralized refreshing is performed before  
and after transition to the self - refresh mode. When burst refreshing has been selected with the BRST bit, the  
number of times to refresh is also the number of times the refresh command is issued at every refresh interval.  
[Bit 19] PON (Power ON): Power - on control  
This bit is used to control the SDRAM (FCRAM) power - on sequence.  
Table 4.2-46 shows the function of power - on control.  
Table 2-30 Function of power - on control  
PON  
Power-on control  
0
1
Disabled (no-operation)  
Start power-on sequence  
Writing 1 to the PON bit starts the SDRAM power - on sequence.  
Before starting the power - on sequence, be sure to set the relevant registers such as AWR, MCRA(B), and  
CSER.  
This bit returns to 0 as soon as the power - on sequence is started.  
When enabling the PON bit, set RFINT and enable RRLD to activate the refresh counter.  
Refreshing is not performed only with the PON bit.  
Do not enable this bit along with the SELF bit.  
When read by a Read - modify - Write instruction, the bit always returns 0.  
[Bits 18 - 16] TRC2, TRC1, TRC0 (Time of Refresh Cycle): Refresh cycle (tRC)  
These bits set the refresh cycle (tRC).  
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Chapter 31 External Bus  
2.External Bus Interface Registers  
Table 4.2-47 lists the settings for the refresh cycle (tRC).  
Table 2-31 Settings for the refresh cycle (tRC)  
TRC2  
TRC1  
TRC0  
Refresh cycle (tRC)  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4
5
6
7
8
9
10  
11  
541  
Chapter 31 External Bus  
3.Setting Example of the Chip Select Area  
3. Setting Example of the Chip Select Area  
In the external bus interface, a total of eight chip select areas can be set.  
This section presents an example of setting the chip select area.  
■ Example of Setting the Chip Select Area  
The address space of each area can be placed, in units of a minimum of 64 KB, anywhere in the 4 GB space  
using ASR0-7 (Area Select Registers) and ACR0-7 (Area Configuration Registers). When bus access is made to  
an area specified by these registers, the corresponding chip select signals (CS0-CS7) are activated (L output)  
during the access cycle.  
● Example of setting ASRs and ASZ3-0  
•
•
•
ASR1=0003 ACR1 ASZ3-0=0000 : Chip select area 1 is assigned to 00030000 to 0003FFFF .  
H
B
H
H
ASR2=0FFC ACR2 ASZ3-0=0010 : Chip select area 2 is assigned to 0FFC0000 to 10000000 .  
H
B
H
H
ASR3=0011 ACR3 SZ3-0=0100 : Chip select area 3 is assigned to 00100000 to 00200000 .  
H
B
H
H
Since at this point 1 MB is set for bits ASZ3-0 of the ACR, the unit for boundaries 1 MB and bits 19-16 of ASR3  
are ignored. Before there is any writing to ACR0 after a reset, 00000000 -FFFFFFFF is assigned to chip select  
H
H
area 0.  
Set the chip select areas so that there is no overlap.  
Figure 3-1 "Example of Setting the Chip Select Area" shows an example of setting the chip select area.  
Figure 3-1 Example of Setting the Chip Select Area  
(Initial value)  
00000000H  
(Example)  
00000000H  
00030000H  
00040000H  
00100000H  
Area 1  
Area 3  
64 KB  
1 MB  
Area 0  
00200000H  
0FFC0000H  
Area 2  
256 KB  
0FFFFFFFH  
FFFFFFFFH  
FFFFFFFFH  
542  
   
Chapter 31 External Bus  
4.Endian and Bus Access  
4. Endian and Bus Access  
There is a one-to-one correspondence between the WR0-WR3 control signal and the byte loca-  
tion regardless of the endian method (big or little) and the data bus width. The following sum-  
marizes the location of bytes on the data bus of the MB91460 series used according to the  
specified data bus width and the corresponding control signal for each bus mode.  
■ Relationship between Data Bus Width and Control Signal  
This section summarizes the location of bytes on the data bus used according to the specified data bus width and  
the corresponding control signal for each bus mode.  
● Ordinary bus interface  
Figure 4-1 Data Bus Width and Control Signal on the Ordinary Bus Interface  
a) 32-bit bus width  
b) 16-bit bus width  
c) 8-bit bus width  
data bus Control signal  
data bus Control signal data bus Control signal  
D31  
WR0  
(UUB)  
WR0  
(UUB)  
WR0  
(UUB)  
WR1  
WR1  
-
-
-
-
-
-
(ULB)  
(ULB)  
WR2  
(LUB)  
-
-
-
-
WR3  
(LLB)  
D0  
(D15 to 0 are not used)  
(D23 to 0 are not used)  
● Time division I/O interface  
Figure 4-2 Data Bus Width and Control Signal in the Time Division I/O Interface  
a) 16-bit bus width  
b) 8-bit bus width  
data bus Control signal  
data bus Control signal  
D31  
A15 to 8  
WR0  
A7 to 0  
WR0  
A7 to 0  
WR1  
-
-
-
-
-
-
-
-
-
D16  
-
-
-
-
-
-
(D15 to 0 are not used)  
(D23 to 0 are not used)  
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Chapter 31 External Bus  
4.Endian and Bus Access  
● SDRAM Interface  
Figure 4-3 Data bus width of the SDRAM (FCRAM) interface and its control signals  
a)32-bit bus width b)16-bit bus width c)8-bit bus width  
Data bus Control signalData bus Control signaDlata bus  
D31  
Control si  
DQMUU  
DQMUL  
DQMLU  
DQMLL  
DQMUU  
DQMUU  
DQMUL  
-
-
-
-
-
-
-
-
-
-
D0  
(D15 to 0 are not used.)  
(D23 to 0 are not used.)  
4.1 Big Endian Bus Access  
With the exception of the CS0 area of the MB91460 series, either the big endian method or the  
little endian method can be selected for each chip select area. If 0 is set for the LEND bit of the  
ACR register, the area is treated as big endian. The MB91460 series is normally big endian and  
performs external bus access.  
■ Data Format  
The relationship between the internal register and the external data bus is as follows:  
● Word access (when LD/ST instruction executed)  
Figure 4-4 Relationship between Internal Register and External Data Bus for Word Access  
Internal register  
External register  
D31  
AA  
D31  
AA  
D23  
BB  
D23  
BB  
D15  
CC  
D7  
D15  
CC  
D7  
DD  
D0  
DD  
D0  
544  
Chapter 31 External Bus  
4.Endian and Bus Access  
Figure 4-5 Relationship between the Internal Register and External Data Bus for Halfword Access  
a) Output address low-order  
digits "00"  
b) Output address low-order  
digits "10"  
Internal register External bus  
Internal register External bus  
D31  
D31  
D31  
D31  
AA  
BB  
D23  
D23  
D23  
D23  
D15  
D7  
D15  
D7  
D15  
D7  
D15  
D7  
AA  
BB  
AA  
BB  
AA  
BB  
D0  
D0  
D0  
D0  
Figure 4-6 Relationship between Internal Register and External Data Bus for Byte Access  
a) Output address  
low-order digits "00"  
b) Output address  
low-order digits "01"  
c) Output address  
low-order digits "10"  
d) Output address  
low-order digits "11"  
Internal  
register  
External  
bus  
Internal  
register  
External  
bus  
Internal  
register  
External  
bus  
Internal  
register  
External  
bus  
D31  
D31  
D31  
D31  
D31  
D31  
D31  
D23  
D31  
AA  
D23  
D15  
D7  
D23  
D23  
D15  
D7  
D23  
D15  
D7  
D23  
D15  
D7  
D23  
D15  
D7  
D23  
D15  
D7  
AA  
D15  
D7  
D15  
D7  
AA  
AA  
AA  
AA  
AA  
AA  
D0  
D0  
D0  
D0  
D0  
D0  
D0  
D0  
■ Data Bus Width  
● 32-bit bus width  
Figure 4-7 Relationship between Internal Register and External Bus Having 32-Bit Bus Width  
Internal resistor  
External bus  
D31  
D31  
AA  
BB  
CC  
DD  
AA  
BB  
CC  
DD  
Read/Write  
D23  
D15  
D07  
D23  
D15  
D07  
545  
Chapter 31 External Bus  
4.Endian and Bus Access  
● 16-bit bus width  
Figure 4-8 Relationship between Internal Register and External Bus Having 16-Bit Bus Width  
Internal register  
External bus  
Output address low-order digits  
"00"  
"10"  
D31  
D31  
D23  
read/write  
AA  
BB  
CC  
DD  
AA  
BB  
CC  
DD  
D23  
D15  
D07  
● 8-bit bus width  
Figure 4-9 Relationship between Internal Register and External Bus having 8-Bit bus Width  
Internal register  
External bus  
Output address low-order digits  
"00"  
"10"  
"01"  
"11"  
DD  
read/write  
D31  
D23  
D15  
D07  
D31  
AA BB CC  
AA  
BB  
CC  
DD  
■ External Bus Access  
Figure 4-11 "External bus Access for 16-Bit Bus Width" and Figure 4-12 "External Bus Access for 8-Bit Bus  
Width" show external bus access (16-bit/8-bit bus width) separately for word, halfword, and byte access. The  
following items are included in Figure 4-11 "External bus Access for 16-Bit Bus Width" and Figure 4-12 "External  
Bus Access for 8-Bit Bus Width":  
•
•
•
Access byte location  
Program address and output address  
Bus access count  
The MB91460 series does not detect misalignment errors.  
Therefore, for word access, the lower two bits of the output address are always 00 regardless of whether 00, 01,  
10, or 11 is specified as the lower two bits by the program. For halfword access, the lower two bits of the output  
address are 00 if the lower two bits specified by the program are 00 or 01, and are 10 if 10 or 11.  
546  
Chapter 31 External Bus  
4.Endian and Bus Access  
● 32-bit bus width  
Figure 4-10 External bus Access for 32-Bit Bus Width  
(a) PA1/PA0="00"  
(b) PA1/PA0="01"  
(c) PA1/PA0="10"  
(d) PA1/PA0="11"  
→(1) Output A1/A0="00"  
→(1) Output A1/A0="00"  
→(1) Output A1/A0="00"  
→(1) Output A1/A0="00"  
MSB LSB  
(1)  
(1)  
(1)  
(1)  
00 01  
10  
11  
00 01  
10  
11  
00 01  
00 01  
10  
11  
10  
11  
32bit  
● 16-bit bus width  
Figure 4-11 External bus Access for 16-Bit Bus Width  
(A) Word access  
(a) PA1/PA0="00"  
(b) PA1/PA0="01"  
(c) PA1/PA0="10"  
(1) Output A1/A0="00"  
(2) Output A1/A0="10"  
(d) PA1/PA0="11"  
(1) Output A1/A0="00"  
(2) Output A1/A0="10"  
(1) Output A1/A0="00"  
(2) Output A1/A0="10"  
(1) Output A1/A0="00"  
(2) Output A1/A0="10"  
LSB  
MSB  
(1)  
(2)  
00  
10  
01  
11  
(1)  
(2)  
(1)  
(2)  
00  
10  
01  
11  
00  
10  
01  
11  
(1)  
(2)  
00  
10  
01  
11  
(B) Halfword access  
(a) PA1/PA0="00"  
(b) PA1/PA0="01"  
(1) Output A1/A0="00"  
(c) PA1/PA0="10"  
(1) Output A1/A0="00"  
(d) PA1/PA0="11"  
(1) Output A1/A0="00"  
(1) Output A1/A0="00"  
(1)  
(1)  
00  
10  
01  
11  
00  
10  
01  
11  
00  
10  
01  
11  
00  
10  
01  
11  
(1)  
(1)  
(C) Byte access  
(a) PA1/PA0="00"  
(b) PA1/PA0="01"  
(1) Output A1/A0="00"  
(c) PA1/PA0="10"  
(1) Output A1/A0="00"  
(d) PA1/PA0="11"  
(1) Output A1/A0="00"  
(1) Output A1/A0="00"  
(1)  
01  
11  
(1)  
01  
11  
00  
10  
00  
10  
00  
10  
01  
11  
00  
10  
01  
11  
(1)  
(1)  
547  
 
Chapter 31 External Bus  
4.Endian and Bus Access  
● 8-bit bus width  
Figure 4-12 External Bus Access for 8-Bit Bus Width  
(A) Word access  
(a) PA1/PA0="00"  
(1) Output A1/A0="00"  
(b) PA1/PA0="01"  
(1) Output A1/A0="00"  
(c) PA1/PA0="10"  
(1) Output A1/A0="00"  
(d) PA1/PA0="11"  
(1) Output A1/A0="00"  
(2) Output A1/A0="01"  
(3) Output 1/A0="10"  
(4) Output 1/A0="11"  
(2) Output A1/A0="01"  
(3) Output 1/A0="10"  
(4) Output 1/A0="11"  
(2) Output A1/A0="01"  
(3) Output 1/A0="10"  
(4) Output 1/A0="11"  
(2) Output A1/A0="01"  
(3) Output 1/A0="10"  
(4) Output 1/A0="11"  
MSB LSB  
00  
01  
10  
11  
00  
01  
10  
11  
00  
01  
10  
11  
00  
01  
10  
11  
(1)  
(2)  
(3)  
(4)  
(1)  
(2)  
(3)  
(4)  
(1)  
(2)  
(3)  
(4)  
(1)  
(2)  
(3)  
(4)  
8bit  
(B) Halfword access  
(a) PA1/PA0="00"  
(1) Output A1/A0="00"  
(b) PA1/PA0="01"  
(c) PA1/PA0="10"  
(1) Output A1/A0="10"  
(d) PA1/PA0="11"  
(1) Output A1/A0="10"  
(1) Output A1/A0="00"  
(2) Output A1/A0="01"  
(2) Output A1/A0="01"  
(2) Output A1/A0="11"  
(2) Output A1/A0="11"  
00  
01  
10  
11  
00  
01  
10  
11  
00  
01  
00  
01  
(1)  
(2)  
(1)  
(2)  
10  
11  
10  
11  
(1)  
(2)  
(1)  
(2)  
(C) Byte access  
(a) PA1/PA0="00"  
(1) Output A1/A0="00"  
(b) PA1/PA0="01"  
(1) Output A1/A0="00"  
(c) PA1/PA0="10"  
(1) Output A1/A0="10"  
(d) PA1/PA0="11"  
(1) Output A1/A0="10"  
00  
01  
10  
11  
00  
01  
10  
11  
00  
01  
10  
11  
00  
01  
10  
11  
(1)  
(1)  
(1)  
(1)  
■ Example of Connection with External Devices  
Figure 4-13 "Example of Connecting the MB91460 Series to External Devices" shows an example of connection  
the MB91460 series to external devices.  
548  
 
Chapter 31 External Bus  
4.Endian and Bus Access  
Figure 4-13 Example of Connecting the MB91460 Series to External Devices  
This LSI  
D31  
to  
D24  
D23  
to  
D16  
D15  
to  
D08  
D07  
to  
D00  
* For 16/8-bit devices, use the data bus on  
the MSB side of this LSI.  
WR3  
WR0  
WR1  
WR2  
00  
01  
10  
11  
0
1
0
D31 D24 D23 D16 D15 D08 D07 D00  
D15 D08 D07 D00  
D07  
D00  
32-bit device  
(low-order 2 bits of  
the address 00 to 11)  
*16-bit device  
(low-order 1 bit of  
the address 0/1)  
*8-bit device  
4.2 Little Endian Bus Access  
Little endian (LER) external bus access is performed for an area for which the little endian meth-  
od is set.  
Little endian bus access on the MB91460 series is implemented by using the bus access oper-  
ation used for the big endian method. Basically, the order of output addresses and control signal  
output are the same as for the big endian method and the byte locations on the data bus are  
swapped in accordance with the bus width.  
Note that, when a connection is made, the big endian area and the little endian area must be  
kept physically separate.  
■ Differences between Little Endian and Big Endian  
The following explains the differences between little endian and big endian.  
The order of addresses that are output is the same for little endian and big endian.  
The data bus control signal used for 32/16/8-bit bus width is the same for little endian and big endian.  
● Word access  
The byte data on the MSB side for big endian address 00 becomes byte data on the LSB side when the little  
endian method is used.  
For a word address, the locations of all four bytes in the word are reversed:  
00 -> 11, 01 -> 10, 10 -> 01, 11 -> 00  
549  
 
Chapter 31 External Bus  
4.Endian and Bus Access  
● Halfword access  
The byte data on the MSB side for the big endian address 0 becomes byte data on the LSB side when the little  
endian method is used.  
For halfword access, the byte locations of two bytes are reversed.  
0 -> 1, 1 -> 0  
● Byte access  
There is no difference between little endian and big endian.  
■ Restrictions on the Little Endian Area  
•
If prefetch is enabled for a little endian area, always use word access to access the area. If data written to the  
prefetch buffer is accessed with any length other than word length, the correct endian conversion is not  
performed and the wrong data will be read. The reason is hardware restrictions related to the endian  
conversion mechanism.  
•
Do not place any instruction code in a little endian area.  
■ Data Format  
The relationship between the internal register and external data bus is as follows:  
Figure 4-14 Relationship between the Internal Register and External Data Bus for Word Access  
(1) Word access (when executing the LD/ST instructions)  
External bus  
Internal register  
D31  
DD  
D31  
AA  
D23  
CC  
D23  
BB  
D15  
BB  
D15  
CC  
D7  
D7  
AA  
DD  
D0  
D0  
Figure 4-15 Relationship between Internal Register and External Data Bus for Halfword Access  
(2) Halfword access (when executing the LDUH/STH instructions)  
a) Output address low-order digits "00"  
Internal register External bus  
b) Output address low-order digits "10"  
Internal register External bus  
D31  
D31  
D23  
D31  
D23  
D31  
D23  
BB  
AA  
D23  
D15  
D7  
D15  
D7  
D15  
D7  
D15  
D7  
AA  
BB  
AA  
BB  
BB  
AA  
D0  
D0  
D0  
D0  
550  
Chapter 31 External Bus  
4.Endian and Bus Access  
Figure 4-16 Relationship between Internal Register and External Data Bus for Byte Access  
(3) Halfword access (when executing the LDUB/STB instructions)  
a) Output address  
low-orderdigits "00"  
b) Output address  
c) Output address  
low-order digits "10"  
d) Output address  
low-order digits "11"  
low-order digits "01"  
Internal  
register  
External  
bus  
Internal  
register  
External  
bus  
Internal  
register  
External  
bus  
Internal  
register  
External  
bus  
D31  
D31  
D23  
D31  
D31  
D31  
D31  
D31  
D31  
AA  
D23  
D15  
D7  
D23  
D15  
D7  
D23  
D15  
D7  
D23  
D23  
D15  
D7  
D23  
D15 D15  
D23  
D15  
D7  
AA  
D15  
AA  
D7  
D0  
D7  
D0  
D7  
D0  
AA  
AA  
AA  
AA  
AA  
D0  
D0  
D0  
D0  
D0  
■ Data Bus Width  
The following shows the relationships between the internal register and external data bus for each data bus width.  
● 32-bit bus width  
Figure 4-17 Relationship between Internal Register and External Bus Data for 32-bit Bus Width  
Internal resistor  
External bus  
D31  
D31  
AA  
BB  
CC  
DD  
Read/Write  
DD  
CC  
BB  
AA  
D23  
D15  
D07  
D23  
D15  
D07  
● 16-bit bus width  
Figure 4-18 Relationship between Internal Register and External Bus Data for 16-bit Bus Width  
Internal register  
External bus  
Output address low-order digits  
"00" "10"  
D31  
D23  
D31  
AA  
BB  
CC  
DD  
read/write  
DD BB  
CC AA  
D23  
D15  
D07  
551  
Chapter 31 External Bus  
4.Endian and Bus Access  
● 8-bit bus width  
Figure 4-19 Relationship between the Internal Register and External Data Bus in the 8-bit Bus Width  
Internal register  
External bus  
Output address low-order digits  
"00" "01" "10" "11"  
D31  
D23  
D31  
read/write  
AA  
BB  
CC  
DD  
DD CC BB  
AA  
D15  
D07  
■ Examples of Connection with External Devices  
The following shows examples of connecting the MB91460 series to external devices for each bus width.  
● 32-bit bus width  
Figure 4-20 Example of Connecting the MB91460 Series to External Devices (32-Bit Bus Width)  
This LSI  
D31  
|
D23  
|
D15  
|
D07  
|
D24  
D16  
D08  
D00  
00  
01  
10  
11  
11  
10  
01  
00  
D24D23 D16D15 D08D07  
D31 D24D23 D16D15 D08D07 D00  
D31  
D00  
big endian area  
little endian area  
552  
Chapter 31 External Bus  
4.Endian and Bus Access  
● 16-bit bus width  
Figure 4-21 Example of Connecting the MB91460 Series to External Devices (16-Bit Bus Width)  
This LSI  
D31  
to  
D23  
to  
D24  
D16  
WR0  
WR1  
0
1
0
1
D15 D08 D07 D00  
D15 D08 D07 D00  
big endian area  
little endian area  
● 8-bit bus width  
Figure 4-22 Example of Connecting the MB91460 Series to External Devices (8-Bit Bus Width)  
This LSI  
D31  
to  
D24  
WR0  
D07 D00  
D07 D00  
big endian area  
little endian area  
553  
Chapter 31 External Bus  
4.Endian and Bus Access  
4.3 Comparison of Big Endian and Little Endian External Access  
This section shows a comparison of big endian and little endian external access in word access,  
halfword access, and byte access for each bus width.  
554  
Chapter 31 External Bus  
4.Endian and Bus Access  
■ Word Access  
Big endian mode  
Little endian mode  
32-bit bus  
width  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address: Lower 2-bit: "0"  
address : "0"  
D31  
D31  
D31  
D31  
WR0  
WR1  
AA  
BB  
CC  
DD  
AA  
BB  
CC  
WR0  
WR1  
AA  
BB  
CC  
DD  
DD  
CC  
BB  
WR2  
WR3  
WR2  
WR3  
DD  
(1)  
AA  
(1)  
D00  
D00  
D00  
D00  
16-bit bus  
width  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address: "0" "2"  
D31  
address: "0" "2"  
D31  
D31  
D31  
WR0  
WR1  
AA  
BB  
CC  
DD  
AA CC  
WR0  
WR1  
AA  
BB  
CC  
DD  
DD BB  
CC AA  
BB DD  
D16  
D16  
D16  
D00  
D00  
(1) (2)  
(1) (2)  
8-bit bus  
width  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address:  
"0" "1" "2" "3"  
address:  
"0" "1" "2" "3"  
D31  
D31  
D31  
D31  
WR0  
WR0  
AA  
BB  
CC  
DD  
DD CC BB AA  
AA  
BB  
CC  
DD  
AA BB CC DD  
D24  
D24  
D00  
D00  
(1) (2) (3) (4)  
(1) (2) (3) (4)  
555  
Chapter 31 External Bus  
4.Endian and Bus Access  
■ Halfword Access  
Big endian mode  
Little endian mode  
32-bit bus  
width  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address : "0"  
address : "0"  
D31  
D31  
D31  
D31  
WR0  
WR1  
AA  
BB  
WR0  
WR1  
BB  
AA  
-
-
AA  
-
-
AA  
BB  
BB  
D00  
D00  
D00  
D00  
(1)  
(1)  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address : "2"  
address : "2"  
D31  
D31  
D31  
D31  
-
-
-
-
WR2  
WR3  
WR2  
WR3  
DD  
CC  
DD  
CC  
CC  
DD  
CC  
(1)  
DD  
(1)  
D00  
D00  
D00  
D00  
556  
Chapter 31 External Bus  
4.Endian and Bus Access  
Big endian mode  
Little endian mode  
16-bit bus  
width  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address: "0"  
address: "2"  
D31  
D31  
D31  
D31  
WR0  
WR1  
WR0  
WR1  
AA  
BB  
B
A
D16  
D16  
AA  
BB  
AA  
BB  
D00  
D00  
(1)  
(1)  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address: "2"  
address: "2"  
D31  
D31  
D31  
D31  
WR0  
WR1  
WR0  
WR1  
CC  
DD  
CC  
DD  
D16  
D16  
CC  
DD  
CC  
DD  
D00  
D00  
(1)  
(1)  
8-bit bus  
width  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address: "0" "1"  
address: "0" "1"  
D31  
D31  
D31  
D31  
WR0  
WR0  
AA BB  
BB AA  
D24  
D24  
AA  
AA  
BB  
BB  
D00  
D31  
D00  
D00  
D31  
D00  
(1) (2)  
(1) (2)  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address: "2" "3"  
address: "2" "3"  
D31  
D31  
WR0  
WR0  
CC DD  
DD CC  
D24  
D24  
CC  
CC  
DD  
DD  
D00  
D00  
D00  
D00  
(1) (2)  
(1) (2)  
557  
Chapter 31 External Bus  
4.Endian and Bus Access  
■ Byte Access  
558  
Chapter 31 External Bus  
4.Endian and Bus Access  
Big endian mode  
Little endian mode  
32-bit bus  
width  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address : "0"  
address : "0"  
D31  
D31  
D31  
D31  
WR0  
AA  
WR0  
AA  
-
-
-
-
-
AA  
-
AA  
D00  
D00  
D31  
D00  
D00  
D31  
(1)  
(1)  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address : "1"  
address : "1"  
D31  
D31  
-
-
WR1  
BB  
WR1  
BB  
-
-
-
-
BB  
BB  
D00  
D00  
D31  
D00  
D00  
D31  
(1)  
(1)  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address : "2"  
address : "2"  
D31  
D31  
-
-
-
-
WR2  
-
CC  
WR2  
-
CC  
(1)  
CC  
CC  
D00  
D00  
D31  
D00  
D00  
D31  
(1)  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address : "3"  
address : "3"  
D31  
D31  
-
-
-
-
-
-
WR3  
DD  
(1)  
DD  
WR3  
DD  
(1)  
DD  
D00  
D00  
D00  
D00  
559  
Chapter 31 External Bus  
4.Endian and Bus Access  
Big endian mode  
Little endian mode  
16-bit bus  
width  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address: "0"  
address: "0"  
D31  
D31  
D31  
D31  
WR0  
WR0  
AA  
AA  
D16  
D16  
AA  
AA  
D00  
D00  
(1)  
(1)  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address: "1"  
address: "1"  
D31  
D00  
D31  
D31  
D31  
BB  
BB  
WR1  
WR1  
D16  
D16  
BB  
BB  
D00  
(1)  
(1)  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address: "2"  
address: "2"  
D31  
D00  
D31  
D31  
D31  
WR0  
WR0  
CC  
CC  
D16  
D16  
CC  
CC  
D00  
(1)  
(1)  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address: "3"  
address: "3"  
D31  
D00  
D31  
D31  
D31  
DD  
DD  
WR1  
WR1  
D16  
D16  
DD  
DD  
D00  
(1)  
(1)  
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Chapter 31 External Bus  
4.Endian and Bus Access  
Big endian mode  
Little endian mode  
8-bit bus  
width  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address: "0"  
address: "0"  
D31  
D31  
D31  
D31  
WR0  
WR0  
AA  
AA  
D24  
D24  
AA  
AA  
D00  
D00  
(1)  
(1)  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address: "1"  
address: "1"  
D31  
D31  
D31  
BB  
D31  
BB  
WR0  
WR0  
D24  
D24  
BB  
BB  
D00  
D31  
D00  
D31  
(1)  
(1)  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address: "2"  
address: "2"  
D31  
CC  
D31  
CC  
WR0  
WR0  
D24  
D24  
CC  
CC  
D00  
D31  
D00  
D31  
(1)  
(1)  
Internal  
Reg  
External  
terminal  
Control  
terminal  
Internal  
Reg  
External  
terminal  
Control  
terminal  
address: "3"  
address: "3"  
D31  
DD  
D31  
DD  
WR0  
WR0  
D24  
D24  
DD  
DD  
D00  
D00  
(1)  
(1)  
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Chapter 31 External Bus  
5.Operation of the Ordinary bus interface  
5. Operation of the Ordinary bus interface  
This section explains operation of the ordinary bus interface.  
■ Ordinary Bus Interface  
For the ordinary bus interface, two clock cycles are the basic bus cycles for both read access and write access.  
The following operational phases of the ordinary bus interface are explained below with the use of a timing chart.  
•
•
•
•
•
•
•
•
•
•
•
Basic timing (for successive accesses)  
WRn + byte control type  
Read -> write  
Write -> write  
Auto-wait cycle  
External wait cycle  
Synchronous write enable output  
CSn delay setting  
CSn -> RD/WRn setup, RD/WE -> CSn hold setting  
DMA fly-by transfer (I/O -> memory)  
DMA fly-by transfer (memory -> I/O)  
5.1 Basic Timing  
This section shows the basic timing for successive accesses.  
■ Basic Timing (For Successive Accesses)  
Figure 5-1 "Basic Timing (For Successive Accesses)" shows the operation timing for (TYP3-0 = 0000 , AWR =  
B
0008 )  
H
562  
   
Chapter 31 External Bus  
5.Operation of the Ordinary bus interface  
Figure 5-1 Basic Timing (For Successive Accesses)  
MCLK  
A[31:0]  
AS  
#1  
#2  
CSn  
RD  
READ  
D[31:0]  
WRn  
#1  
#2  
WRITE  
D[31:0]  
#1  
#2  
•
•
AS is asserted for one cycle in the bus access start cycle.  
A31-0 continues to output the address of the location of the start byte in word/halfword/byte access from the  
bus access start cycle to the bus access end cycle.  
•
•
If the W02 bit of the AWR0-7 registers is 0, CS0-CS7 are asserted at the same timing as AS. For successive  
accesses, CS0-CS7 are not negated. If the W00 bit of the AWR register is 0, CS0-CS7 are negated after the  
bus cycle ends. If the W00 bit is 1, CS0-CS7 are negated one cycle after bus access ends.  
RD and WR0-WR3 are asserted from the 2nd cycle of the bus access. Negation occurs after the wait cycle of  
bits W15-W12 of the AWR register is inserted. The timing of asserting RD and WR0-WR3 can be delayed by  
one cycle by setting the W01 bit of the AWR register to 1. However, depending on the internal state, the  
assertion of WR0-WR3 may not start in the 2nd cycle and may even be delayed if the W01 bit is set to 0.  
•
•
If a setting is made so that WR0-WR3 is used like TYP3-0=0x0xB, WRn is always H.  
For read access, D31-0 is read when MCLK rises in the cycle in which the wait cycle ended after RD was  
asserted.  
•
For write access, data output to D31-0 starts at the timing at which WR0-WR3 are asserted.  
5.2 Operation of WRn + Byte Control Type  
This section shows the operation timing for the WRn + byte control type.  
■ Operation Timing of the WRn + Byte Control Type  
Figure 5-2 "Timing Chart for the WRn + Byte Control Type" shows the operation timing for (TYP3-0 = 0010 ,  
B
AWR = 0008 ).  
H
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Chapter 31 External Bus  
5.Operation of the Ordinary bus interface  
Figure 5-2 Timing Chart for the WRn + Byte Control Type  
MCLK  
A[31:0]  
AS  
CSn *  
RD  
WR0,WR1  
WR2,WR3  
READ  
D[31:0]  
WR  
WR0,WR1  
WRITE  
WR2,WR3  
D[31:0]  
•
Operation of AS, CSn, RD, A31-0, and D31-16 is the same as that described in 5.1 "Basic Timing". WRn is  
asserted from the 2nd cycle of the bus access. Negation occurs after the wait cycle of bits W15-W12 of the  
AWR register is inserted. The timing of asserting RD and WR0-WR3 can be delayed by one cycle by setting  
the W01 bit of the AWR register to 1. However, depending on the internal state, assertion of WR0-WR3 may  
not start in the 2nd cycle and may even be delayed if the W01 bit is set to 0. (Operation is the same as that for  
WR0-WR3 described in 5.1 "Basic Timing" .)  
•
•
WR0-WR3 indicate the byte location expressed with negative logic when they are used for access as the byte  
enable signal. Assertion continues from the bus access start cycle to the bus access end cycle and changes  
at the same timing as the address timing. The byte location for access is indicated for both read access and  
write access.  
For write access, data output to D31-16 starts at the timing at which WRn is asserted. If the areas defined by  
TYP3-0=0x0x (WR0-WR3 used) and TYP3-0=0x1x (WRn + byte control) are mixed, be sure to make the  
B
B
following setting for all areas that will be used. (For details, see the notes).  
•
•
Set at least one read -> write idle cycle.  
Set at least one write recovery cycle.  
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Chapter 31 External Bus  
5.Operation of the Ordinary bus interface  
5.3 Read -> Write Operation  
This section shows the operating timing for read -> write.  
■ Operation Timing of Read -> Write  
Figure 5-3 "Timing Chart for Read -> Write" shows the operation timing for (TYP3-0=0000 , AWR=0048 ).  
B
H
Figure 5-3 Timing Chart for Read -> Write  
Read Idle * Write  
MCLK  
A[31:0]  
AS  
CSn  
RD  
WRn  
D[31:0]  
•
•
•
Setting of the W07/W06 bits of the AWR register enables 0-3 idle cycles to be inserted.  
Settings in the CS area on the read side are enabled.  
This idle cycle is inserted if the next access after a read access is write access or access to another area.  
5.4 Write -> Write Operation  
This section shows the operation timing for write -> write.  
■ Write -> Write Operation  
Figure 5-4 "Timing Chart for the Write -> Write Operation" shows the operation timing for (TYP3-0=0000 ,  
B
WR=0018 ).  
H
565  
 
Chapter 31 External Bus  
5.Operation of the Ordinary bus interface  
Figure 5-4 Timing Chart for the Write -> Write Operation  
Write Write recovery * Write  
MCLK  
A[31:0]  
AS  
CSn  
WRn  
D[31:0]  
•
•
•
Setting of the W05/W04 bits of the AWR register enables 0-3 write cycles to be inserted.  
After all of the write cycles, recovery cycles are generated.  
Write recovery cycles are also generated if write access is divided into phases for access with a bus width  
wider than that specified.  
5.5 Auto-Wait Cycle  
This section shows the operation timing for the auto-wait cycle.  
■ Auto-Wait Cycle Timing  
Figure 5-5 "Timing Chart for the Auto-Wait Cycle" shows the operation timing for (TYP3-0=0000 , AWR=2008 ).  
B
H
566  
 
Chapter 31 External Bus  
5.Operation of the Ordinary bus interface  
Figure 5-5 Timing Chart for the Auto-Wait Cycle  
Basic cycle Wait cycle *  
MCLK  
A[31:0]  
AS  
CSn  
RD  
D[31:0]  
WRn  
D[31:0]  
Setting of the W15-12 bits (first wait cycles) of the AWR register enables 0-15 auto-wait cycles to be set.  
In Figure 5-5 "Timing Chart for the Auto-Wait Cycle", two auto-wait cycles are inserted, making a total of four  
cycles for access. If auto-wait is set, the minimum number of bus cycles is 2 cycles + (first wait cycles). For a  
write operation, the minimum number of bus cycles may be still longer depending on the internal state.  
5.6 External Wait Cycle  
This section shows the operation timing for the external wait cycle.  
■ External Wait Cycle Timing  
Figure 5-6 "Timing Chart for the External Wait Cycle" shows the operation timing for (TYP3-0=0001 ,  
B
AWR=2008 ).  
H
567  
 
Chapter 31 External Bus  
5.Operation of the Ordinary bus interface  
Figure 5-6 Timing Chart for the External Wait Cycle  
Basic cycle 2 auto-wait cycles Wait cycle by RDY  
MCLK  
A[31:0]  
AS  
CSn  
RD  
D[31:0]  
WRn  
D[31:0]  
RDY  
Release  
Wait  
Setting 1 for the TYP0 bit of the ACR register and enabling the external RDY input pin enables external wait  
cycles to be inserted.  
In Figure 4.5 - 6, the oblique - lined portion of the RDY pin is invalid because the wait based on the automatic wait  
cycle remains in effect.  
The value at the RDY input pin is evaluated from the last automatic wait cycle on.  
Once a wait cycle is completed, the value at the PDY input pin remains invalid until the next access cycle is  
started.  
5.7 Synchronous Write Enable Output  
This section shows the operation timing for synchronous write enable output.  
■ Operation Timing for Synchronous Write Enable Output  
Figure 5-7 "Timing Chart for Synchronous Write Enable Output" shows the operation timing for (TYP3-0=0000 ,  
B
AWR=0000 ).  
H
568  
 
Chapter 31 External Bus  
5.Operation of the Ordinary bus interface  
Figure 5-7 Timing Chart for Synchronous Write Enable Output  
MCLK  
A[31:0]  
#1  
#2  
AS  
CSn *  
RD  
Read  
Write  
D[31:0]  
WRn  
#1  
#2  
D[31:0]  
#1  
#2  
•
•
If synchronous write enable output is enabled (If the W03 bit of the AWR is 1), operation is as follows.  
WR0-WR3 and WRn pin output asserts synchronous write enable output at the timing at which AS pin output  
is asserted. For a write to an external bus, the synchronous write enable output is L. For a read from an  
external bus, the synchronous write enable output is H.  
•
•
Write data is output from the external data output pin in the clock cycle following the cycle in which  
synchronous write enable output is asserted. If write data cannot be output because the internal bus is  
temporarily unavailable, assertion of synchronous write enable output may be extended until write data can be  
output.  
Read strobe output (RD) functions as an asynchronous read strobe regardless of the setting of WR0-WR3 and  
WRn output timing. Use it as is for controlling the data I/O.  
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Chapter 31 External Bus  
5.Operation of the Ordinary bus interface  
•
If synchronous write enable output is used, the following restrictions apply:  
Do not set the following additional wait because the timing for synchronous write enable output becomes  
meaningless:  
- CS -> RD/WRn setup (Always write 0 to the W01 bit of AWR)  
- First wait cycle setting (Always write 0000 to bits W15-W12 of AWR)  
Do not set the following access types (TYPE3-0 bits (Bits 3-0) in the ACR register) because the timing for  
synchronous write enable output becomes meaningless:  
- Multiplex bus setting (Always write 0 to the TYPE2 bit of ACR)  
- RDY input enable setting (Always write 0 to the TYPE0 bit of ACR)  
Always set the burst length to "1" (BST1 to 0 bit = 0) for the synchronous write enable output  
5.8 CSn Delay Setting  
This section shows the operation timing for the CSn delay setting.  
■ Operation Timing for the CS Delay Setting  
Figure 5-8 "Operation Timing Chart for the CS Delay Setting" shows the operation timing for (TYP3-0=0000 ,  
B
AWR=000C ).  
H
Figure 5-8 Operation Timing Chart for the CS Delay Setting  
MCLK  
A[31:0]  
AS  
CSn  
RD  
READ  
D[31:0]  
WRn  
WRITE  
D[31:0]  
If the W02 bit is 1, assertion starts in the cycle following the cycle in which AS is asserted. For successive  
accesses, a negation period is inserted.  
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Chapter 31 External Bus  
5.Operation of the Ordinary bus interface  
5.9 CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Setting  
This section shows the operation timing for the CSn -> RD/WRn setup and RD/WRn -> CSn hold  
settings.  
■ Operation Timing for the CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Settings  
Figure 5-9 "Timing Chart for the CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Settings" shows the operation  
timing for (TYP3-0=0000 AWR=000B ).  
B
H
Figure 5-9 Timing Chart for the CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Settings  
MCLK  
A[31:0]  
AS  
CSn  
CS->RD/WR  
Delay  
RD/WR->CS  
Delay  
RD  
READ  
D[31:0]  
WRn  
WRITE  
D[31:0]  
•
•
•
•
•
Setting 1 for the W01 bit of the AWR register enables the CSn -> RD/WRn setup delay to be set. Set this bit  
to extend the period between chip select assertion and read/write strobe.  
Setting 1 for the W00 bit of the AWR register enables the RD/WRn -> CSn hold delay to be set. Set this bit to  
extend the period between read/write strobe negation and chip select negation.  
The CSn -> RD/WRn setup delay (W01 bit) and RD/WRn -> CSn hold delay (W00 bit) can be set  
independently.  
When making successive accesses within the same chip select area without negating the chip select, neither  
a CSn -> RD/WRn setup delay nor an RD/WRn -> CSn hold delay is inserted.  
If a setup cycle for determining the address or a hold cycle for determining the address is needed, set 1 for the  
address -> CSn delay setting (W02 bit of the AWR register).  
5.10 DMA Fly-By Transfer (I/O -> Memory)  
This section shows the operation timing for DMA fly-by transfer (I/O -> memory).  
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Chapter 31 External Bus  
5.Operation of the Ordinary bus interface  
■ Operation Timing for DMA Fly-By Transfer (I/O -> Memory)  
Figure 5-10 "Timing Chart for DMA Fly-By Transfer (I/O -> Memory)" shows the operation timing for (TYP3-  
0=0000 , AWR=0008 , IOWR=51 ). This timing chart shows a case in which a wait is not set on the memory  
B
H
H
side.  
Figure 5-10 Timing Chart for DMA Fly-By Transfer (I/O -> Memory)  
I/O wait I/O hold I/O idle I/O wait I/O hold  
cycle * wait * cycle cycle * wait *  
Basic cycle  
Basic cycle  
MCLK  
A[31:0]  
AS  
CSn  
WRn  
D[31:0]  
IORD  
•
•
•
Setting 1 for the HLD bit of the IOWR0-3 registers enables the I/O read cycle to be extended by one cycle.  
Setting bits IW3-0 of the IOWR0-3 registers enables 0-15 wait cycles to be inserted.  
If wait is also set on the memory side (AWR15-12 is not 0), the larger value is used as the wait cycle after  
comparison with the I/O wait (IW3-0 bits).  
5.11 DMA Fly-By Transfer (Memory -> I/O)  
This section shows the operation timing for DMA fly-by transfer (memory -> I/O).  
■ Operation Timing for DMA Fly-By Transfer (Memory -> I/O)  
Figure 5-11 "Timing Chart for DMA Fly-By Transfer (Memory -> I/O)" shows the operation timing chart for (TYP3-  
0=0000 , AWR=0008 , IOWR=51 ). This timing chart shows a case in which a wait is not set on the memory  
B
H
H
side.  
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Chapter 31 External Bus  
5.Operation of the Ordinary bus interface  
Figure 5-11 Timing Chart for DMA Fly-By Transfer (Memory -> I/O)  
I/O wait I/O hold I/O idle  
cycle *1 wait *2 cycle  
I/O wait I/O hold  
cycle *1 wait *2  
Basic cycle  
Basic cycle  
MCLK  
A[31:0]  
AS  
CSn  
RD  
D[31:0]  
IOWR  
•
•
•
•
•
Setting 1 for the HLD bit of the IOWR0-3 registers enables the I/O read cycle to be extended by one cycle.  
Setting the WR1,0 bits of the IOWR0-3 registers enables 0-3 write recovery cycles to be inserted.  
If the write recovery cycle is set to 1 or more, a write recovery cycle is always inserted after write access.  
Setting bits IW3-0 of the IOWR0-3 registers enables 0-15 wait cycles to be inserted.  
If wait is also set on the memory side (AWR15-12 is not 0), the larger value is used as the wait cycle after  
comparison with the I/O wait (IW3-0 bits).  
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Chapter 31 External Bus  
6.Burst Access Operation  
6. Burst Access Operation  
In the external bus interface, the operation that transfers successive data items in one access  
sequence is called burst access. The normal access cycle (that is, not burst access) is called  
single access. One access sequence starts with an assertion of AS and CSn and ends with ne-  
gation of CSn. Multiple data items two or more units of data of the unit set for the area.  
This section explains burst access operation.  
■ Burst Access Operation  
Figure 6-1 "Timing chart for burst access" shows the operation timing chart for (first wait cycle=1, inpage access  
wait cycle=1, TYP3-0=0000 , AWR=1108 ).  
B
H
Figure 6-1 Timing Chart for Burst Access  
First  
cycle  
wait  
Inpage  
access  
wait  
Inpage  
access  
wait  
Inpage  
access  
wait  
MCLK  
A[31:0]  
AS (LBA)  
CSn  
RD  
WR  
WRn  
WRn  
BAA  
D[31:0]  
•
•
In addition to more efficient use of access cycles when a sizable amount of data of asynchronous memory  
such as page mode ROM and burst flash memory is read, burst cycles can also be used for reading from  
normal asynchronous memory.  
The access sequence when burst cycles are used can be divided into the following two types:  
- First access cycle  
The first access cycle is the start cycle for the burst access and operates in the same way as the normal single  
access cycle.  
- Page access cycle  
The page access cycle is a cycle following the first access cycle in which both CSn and RD (read strobe) are  
asserted. Wait cycles that are different from those set for a single cycle can be set. The page access cycle is  
repeated while access remains in the address boundary determined by the burst length setting. When access  
within the address boundary ends, burst access terminates and CSn is negated.  
•
Setting of the W15-W12 bits of the AWR register enable the first 0-15 wait cycles to be inserted. At this point,  
574  
   
Chapter 31 External Bus  
6.Burst Access Operation  
the minimum number of the first access cycles is the wait cycles + 2 cycles (three cycles in the timing chart  
shown in Figure 6-1 "Timing Chart for Burst Access").  
•
•
Setting of the W11-W08 bits of the AWR register enables 0-15 page wait cycles to be inserted. At this point,  
the page access cycles can be obtained from the page wait cycles + 1 cycle (Two cycles in the timing chart  
shown in Figure 6-1 "Timing Chart for Burst Access")  
Setting of the BST bits of the ACR register enables the burst length to be set as 1, 2, 4, or 8. If the burst  
length is set to 1, single access mode is set and only the first cycle is repeated. However, if the data bus width  
is set to 32 bits (the BST bits of the ACR register are 10 ), set the burst length to 4 or less (A malfunction  
B
occurs if the burst length is set to 8).  
•
If burst access is enabled, burst access is used when prefetch access or transfer with a larger size than the  
specified data bus width is performed. For example, if word access to an area whose data bus width is set to  
8 bits and burst length to 4 is performed, access of 4 bursts is performed once instead of repeating byte  
access four times.  
•
•
Since RDY input is ignored in areas for which burst access is set, do not set TYP3-0=0xx1 .  
B
The LBA and BAA signals are designed for burst FLASH memory. LBA indicates the start of access and BAA  
indicates the address increment.  
•
A31-0 is updated after the wait cycles that were set during burst access.  
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Chapter 31 External Bus  
7.Address/data Multiplex Interface  
7. Address/data Multiplex Interface  
This section explains the following three cases of operation of the address/data multiplex inter-  
face:  
• Without external wait  
• With external wait  
• CSn -> RD/WRn setup  
■ Without External Wait  
Figure 7-1 "Timing Chart for the Address/Data Multiplex Interface (without External Wait)" shows the operation  
timing chart for (TYP3-0=0100 , AWR=0008 ).  
B
H
Figure 7-1 Timing Chart for the Address/Data Multiplex Interface (without External Wait)  
MCLK  
address[31:0]  
A[31:0]  
AS  
CSn  
RD  
READ  
D[31:16]  
data[15:0]  
address[15:0]  
address[15:0]  
WR  
WRITE  
D[31:0]  
data[15:0]  
•
Making a setting such as TYP3-0=01xx in the ACR register enables the address/data multiplex interface to  
B
be set.  
•
•
If the address/data multiplex interface is set, set 8 bits or 16 bits for the data bus width (DBW1-0 bits).  
In the address/data multiplex interface, the total of 3 cycles of 2 address output cycles + 1 data cycle becomes  
the basic number of access cycles.  
•
•
In the address output cycles, AS is asserted as the output address latch signal.  
As with a normal interface, the address indicating the start of access is output to A31-0 during the time division  
bus cycle. Use this address if you want to use an address more than 8/16 bits in the address/data multiplex  
interface.  
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Chapter 31 External Bus  
7.Address/data Multiplex Interface  
•
•
As with the normal interface, auto-wait (AWR15-12), read -> write idle cycle (AWR7-6), write recovery (AWR5-  
4), address -> CSn delay (AWR2), CSn -> RD/WRn setup delay (AWR1), and RD/WRn -> CSn hold delay  
(AWR0) can be set.  
In areas for which the address/data multiplex interface is set, set 1(DBW1-0=00 ) as the burst length.  
B
■ With External Wait  
Figure 7-2 "Timing Chart for the Address/Data Multiplex Interface (with External Wait)" shows the operation timing  
chart for (TYP3-0=0101 , AWR=1008 ).  
B
H
Figure 7-2 Timing Chart for the Address/Data Multiplex Interface (with External Wait)  
MCLK  
A[31:0]  
AS  
address[31:0]  
CSn  
RD  
READ  
D[31:16]  
address[15:0]  
address[15:0]  
data[15:0]  
WR  
WRITE  
data[15:0]  
D[31:16]  
Release  
RDY  
External wait  
Making a setting such as TYP3-0=01x1 in the ACR register enables RDY input in the address/data multiplex  
B
interface.  
■ CSn -> RD/WRn Setup  
Figure 7-3 "Timing Chart for the Address/Data Multiplex Interface (CSn -> RD/WRn Setup)" shows the operation  
timing chart for (TYP3-0=0101 , AWR=100B ).  
B
H
577  
 
Chapter 31 External Bus  
7.Address/data Multiplex Interface  
Figure 7-3 Timing Chart for the Address/Data Multiplex Interface (CSn -> RD/WRn Setup)  
MCLK  
A[31:0]  
AS  
address[31:0]  
CSn  
RD  
READ  
D[31:16]  
address[15:0]  
data[15:0]  
WR  
WRITE  
data[15:0]  
address[15:0]  
D[31:16]  
Setting 1 for the CSn -> RD/WRn setup delay (AWR1) enables the multiplex address output cycle to be extended  
by one cycle as shown in Figure 7-3 "Timing Chart for the Address/Data Multiplex Interface (CSn -> RD/WRn  
Setup)", allowing the address to be latched directly to the rising edge of AS. Use this setting if you want to use  
AS as an ALE (Address Latch Enable) strobe without using MCLK.  
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Chapter 31 External Bus  
8.Prefetch Operation  
8. Prefetch Operation  
This section explains the prefetch operation.  
■ Prefetch Operation  
The external bus interface controller contains a prefetch buffer consisting of 16 x 8 bits.  
If the PSUS bit of the TCR register is 0 and read access to an area to which the PFEN bit of the ACR register is  
set to 1 occurs, the subsequent address is prefetched and then stored in the prefetch buffer.  
If the stored address is accessed from the internal bus, the lookahead data in the prefetch buffer is returned  
without external access being performed. This can reduce the wait time for successive accesses to the external  
bus areas.  
● Basic conditions for starting external access using prefetch  
External bus access using prefetch occurs when the following conditions are met:  
•
•
•
The PSUS bit of the TCR register is 0.  
Neither sleep mode nor stop mode is set.  
Read access by the external bus to a chip select area for which prefetch is enabled has been performed.  
DMA access and read access by a read modified write system instruction, however, are excluded.  
•
•
No external bus access request (external bus area access to an area for which prefetch is not enabled or DMA  
transfer with an external bus area) other than the prefetch access has occurred.  
The part of the prefetch buffer for the next operation of capturing the prefetch access is completely empty.  
While the above conditions are met, the prefetch access will continue. If external bus area access to an area for  
which prefetch is not enabled occurs after prefetch access, prefetch access to the area for which prefetch is  
enabled will continue as long as the prefetch buffer clear conditions are not met.  
For an access that mixes multiple prefetch-enabled areas and multiple prefetch-disabled areas, the prefetch  
buffer always holds data of the prefetch-enabled area accessed last. Since, in this case, access to prefetch-  
disabled areas does not affect the prefetch buffer state at all, data in the prefetch buffer is not wasted even if  
prefetch-disabled data access and prefetch-enabled instruction fetch are mixed.  
● Optional clear for temporary stopping of a prefetch access  
Setting 1 for the PSUS bit of the TCR register temporarily stops a prefetch. The prefetch can be restarted by  
setting the PSUS bit to 0. At this point, the contents of the buffer are retained if no error occurs or a buffer clear  
such as occurs when the PCLR bit is set does not occur.  
Setting 1 for the PCLR bit of the TCR register completely clears the prefetch buffer. Clear the buffer by setting  
the PSUS bit when prefetch is interrupted.  
Prefetch is temporarily stopped for the minimum unit (64 KB) of the boundary=chip select area where the high-  
order 16 bits of an address change. If the boundary is crossed, first a buffer read error occurs and then prefetch  
starts in a new area.  
● Unit for one prefetch access operation  
The unit for one prefetch access operation is determined by the DBW bits (bus width) and BST bits (burst length).  
Prefetch access always occurs with the full size of the bus width specified by the DBW bits and access for the  
count of the burst length set by the BST bits in one access operation is performed. That is, if any value other  
than 00 is set for the BST bits, the prefetch always occurs in page mode/burst mode. Keep in mind whether  
B
ROM/RAM is conformable and enough access time is applicable. (Set an appropriate value bits W15-08 bits of  
the AWR register).  
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Chapter 31 External Bus  
8.Prefetch Operation  
During burst access, successive accesses occur only within the address boundary that that is determined by the  
burst length. Thus, if the boundary is crossed, for example, 4 bytes of free space are available in the buffer,  
these 4 bytes cannot be accessed in one operation (If the prefetch buffer starts at xxxxxx0E , 4 bytes of free  
H
space are available in the buffer, and two bursts are set even though the bus width is 16 bits, only 2 bytes,  
xxxxxx0E and xxxxxx0F , can be captured in the next prefetch access).  
H
H
The following provides two examples:  
•
Area whose bus width is set to 16 bits and whose burst length is set to 2  
The amount of data read into the buffer in one prefetch operation is 4 bytes. In this case, prefetch access is  
delayed until 4 bytes of free space are available in the prefetch buffer.  
•
Area whose bus width is set to 8 bits and whose burst length is set to 8  
The amount of data read into the buffer in one prefetch operation is 8 bytes. In this case, prefetch access is  
delayed until 8 bytes of free space are available in the prefetch buffer.  
● Burst length setting and prefetch efficiency  
If requests for external bus access, other than prefetch access, to or errors in the prefetch buffer occur during one  
operation of prefetch access as explained in the previous bullet, "Unit of one prefetch access operation," these  
access requests must wait until access to the prefetch buffer that is being executed is completed.  
Thus, if the burst length is too long, the efficiency and reaction of bus access other than prefetch may be  
degraded. If, on the other hand, the burst length is set to 1, many read cycles may be wasted even if burst/page  
access memory is connected because single access is always performed.  
If settings are made so that the amount of data read in one prefetch access operation is large, prefetch access  
can be started only after free space in the prefetch buffer for this amount is available. Thus, access to the  
prefetch buffer is infrequent, and the external bus tends to be idle. For example, if the bus width is set to 16 bits  
and the burst length is set to 8, the amount of data read into the buffer in one prefetch operation is 16 bytes.  
Thus, a new prefetch access can be started only after the prefetch buffer is completely empty.  
Adjust the optimum burst length to suit use and the environment after taking the above into consideration.  
Generally, when connecting asynchronous memory to which burst/page access cannot be applied, it is best to set  
the burst length to 1 (single access). Conversely, when memory whose burst/page access cycle is short is  
connected, it is better to set the burst length to any value other than 1 (single access). In this case, it is best to  
make the setting so that 8 bytes (half of the buffer) are read in one read operation according to the bus width.  
However, the optimum condition varies with the frequency of external access and varies with the frequency  
divide-by rate setting of the external access clock.  
● Reading from the prefetch buffer  
Data stored in the prefetch buffer is read in response to access from the internal bus if an address matches, and  
no external access is performed. In reading from the buffer, addresses can be hit (up to 16 bytes) if they are in  
the forward direction but not continuous, so that a second read from the external bus is avoided, if possible, even  
for a short forward branch.  
If the address currently being accessed for prefetch matches during access from the internal bus, a wait signal is  
returned internally before data is captured after prefetch access is completed. In this case, no buffer error occurs.  
If an address in the prefetch buffer matches when a read is performed for DMA transfer, data in the prefetch  
buffer is not used, and instead, external data is read by the external bus. In this case, a buffer error occurs. The  
prefetch is not continued and no prefetch access is performed until a new external access operation to a prefetch-  
enabled area occurs.  
● Clearing/updating the prefetch buffer  
If either of the following conditions is met, the prefetch buffer is completely cleared:  
•
If 1 is written to the PCLR bit of the TCR register  
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Chapter 31 External Bus  
8.Prefetch Operation  
•
If a buffer read error occurs. A buffer read error is if any of the following events occurs:  
•
•
•
When no address is found in the buffer that matches in an to read from a prefetch-enabled area. In this  
case, the external bus is accessed again. Data read in this case is not stored in the buffer, but the prefetch  
access is started from the subsequent address to store addresses in the buffer.  
In an access to read from a prefetch-enabled area with a read modified system instruction. In this case,  
the external bus is accessed again. Data read in this case is not stored in the buffer. Also, no prefetch  
access is performed (This is because data is written to the next address).  
In an access to read from a prefetch-enabled area for DMA transfer. In this case, the external bus is  
accessed again. Data read in this case is not stored in the buffer. Also, no prefetch access is performed.  
•
If a buffer write hit occurs. A buffer write hit is as follows:  
•
When the address of just one byte that matches is found in the buffer in an access to write to a prefetch-  
enabled area. In this case, the external bus is accessed again, but no prefetch access is performed before  
a new read access occurs.  
Only part of the prefetch buffer is cleared when the following condition is met:  
If a buffer read hit occurs  
•
In this case, only the part of the buffer before the hit address is cleared.  
● Restrictions on prefetch-enabled areas  
If prefetch to a little endian area is enabled, be sure to access the area using word access. If data read into the  
prefetch buffer is accessed with any length other than word length, the correct endian conversion is not  
performed and thus the wrong data will be read. This is due to hardware restrictions related to the endian  
conversion mechanism.  
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Chapter 31 External Bus  
9.SDRAM/FCRAM Interface Operation  
9. SDRAM/FCRAM Interface Operation  
This section describes the operations of the SDRAM/FCRAM interface.  
■ SDRAM/FCRAM interface  
The chip select areas can be used as SDRAM/FCRAM interface by setting the TYP3 to TYP0 bits in the area  
configuration register (ACR) to 100X .  
B
This section provides timing charts to describe the following operations of the SDRAM/FCRAM interface.  
•
•
•
•
Burst read/write (Settings: Page hit, CAS latency 2)  
Single read/write (Settings: Page hit, CAS latency 3, auto - precharge OFF)  
Single read (Settings: Page miss, CAS latency 3, auto - precharge OFF)  
Single read/write (Settings: CAS latency 1, TYP 1001 , auto - precharge ON)  
B
•
Auto - refresh  
■ Burst Read/Write Operation Timing  
Figure 4.9 - 1 shows the operation timings assuming that page hits and CAS latency 2 are set.  
Figure 9-1 Burst Read/Write Timing Chart  
MCLK  
A
#1  
#1  
#1  
#2  
#3  
#4  
D
#1  
#2  
#3  
#4  
SRAS,SCAS,  
SWE  
WRIT  
READ  
Write recovery  
Cas Latency  
Write cycle  
Read cycle  
•
•
•
•
•
All of the A13 to A0 pins may not be used depending on the SDRAM capacity. See Section " Memory  
Connection Examples " .  
The MCLK is a clock signal input to SDRAM. Signals such as addresses, data, and commands are input to  
SDRAM at the rise of the MCLK.  
Set the W05 and W04 bits in the area wait register (AWR) to the write recovery cycle according to the  
SDRAM/FCRAM standards.  
Set the W10 to W08 bits in the area wait register (AWR) to the CAS latency according to the SDRAM/FCRAM  
standards.  
Set the burst length using the BST bit in the area configuration register (ACR).  
■ Single Read/Write Operation Timing  
Figure 9-2 shows the operation timings assuming that page hits, CAS latency 3, and no auto - precharge are set.  
582  
 
Chapter 31 External Bus  
9.SDRAM/FCRAM Interface Operation  
Figure 9-2 Single Read/Write Timing Chart  
MCLK  
A
#1  
#1  
#1  
#1  
D
SRAS,SCAS,  
SWE  
READ  
WRIT  
Read Write  
Idle cycle  
Cas Latency  
Read cycle  
Write cycle  
Set the W07 and W06 bits in the area wait register (AWR) to the read - to - write idle cycle according to the  
SDRAM/FCRAM standards.  
■ Single Read Operation Timing  
Figure 9-3 shows the operation timings assuming that page misses, CAS latency 3, and no auto - precharge are  
set.  
Figure 9-3 Single Read Timing Chart  
MCLK  
A
BA  
Row  
ACT  
#1  
D
#1  
SRAS,SCAS,  
SWE  
PRE  
READ  
RAS precharge cycle  
(tRP)  
RAS → CAS delay  
(tRCD)  
Cas Latency  
•
•
•
When a page miss occurs, a read operation is performed after the PRE charge and ACTV commands are  
issued.  
Set the W01 and W00 bits in the area wait register (AWR) to the RAS precharge cycle (tRP) according to the  
SDRAM/FCRAM standards.  
Set the W14 to W12 bits in the area wait register (AWR) to the RAS - to - CAS delay (tRCD) according to the  
SDRAM/FCRAM standards.  
■ Single Read/Write Operation Timing  
Figure 9-4 shows the operation timings assuming that CAS latency 1, TYP = 1001 , and auto - precharge are set.  
B
583  
   
Chapter 31 External Bus  
9.SDRAM/FCRAM Interface Operation  
Figure 9-4 Single Read/Write Timing Chart  
MCLK  
A
Row  
Row  
#2  
Col  
Col  
#1  
Row  
Col  
D
#3  
SRAS,SCAS,  
ACTV  
WRITA ACTV  
READA ACTV  
WRITA  
SWE  
CL+BL-1  
CL+BL-1  
•
•
Setting TYP to 1001 causes a read/write command with auto - precharge to be issued. Since the cycle from  
B
READA/WRITA issuance to ACTV issuance is fixed at CL + BL - 1, however, TYP can be set to 1001 only  
B
when FCRAM is connected.  
This timing is effective, for example, for recurring page misses as it eliminates the cycle for issuing the PRE  
command.  
■ Auto - refresh Operation Timing  
Figure 9-5 shows auto - refresh operation timings.  
Figure 9-5 Auto - refresh Timing Chart  
MCLK  
A
D
SRAS,SCAS,  
SWE  
REF  
ACTV  
tRC  
Refresh cycle  
•
The refresh command is issued every " refresh control register's (RCR's) RFINT5 - RFINT0 value x 32 " cycles  
and access is restarted upon completion of each refresh.  
•
•
Set the TRC bit in the refresh control register (RCR) according to the SDRAM/FCRAM standards.  
Satisfy the maximum RAS active time as well.  
9.1 Self Refresh  
This section describes self - refreshing.  
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Chapter 31 External Bus  
9.SDRAM/FCRAM Interface Operation  
■ Self Refresh  
Writing 1 to the SELF bit in the refresh control register (RCR) causes the SDRAM/FCRAM interface to initiate the  
self - refresh transition sequence.  
After executing auto - refreshing the number of times set in the RFC2 to RFC0 bits, the SDRAM/FCRAM interface  
issues the SELF command to SDRAM/FCRAM to enter the self - refresh mode.  
The device is released from the self - refresh mode either when 0 is written to the SELF bit or read/write access  
to SDRAM/FCRAM occurs.  
The SDRAM/FCRAM interface issues the SELFX command to execute auto - refreshing the number of times set  
in the RFC2 to RFC0 bits upon detection of writing 0 to the SELF bit or access to SDRAM/FCRAM in the self -  
refresh mode.  
Even when access to SDRAM/FCRAM by DMA transfer occurs after setting the self - refresh mode and putting  
the chip into sleep mode, the self - refresh mode is canceled.  
● Self - refresh mode transition procedure  
1. Set SELF bit to "1".  
2. Issue the REF command the number of times set in the RFC2 to RFC0 bits.  
3. Issue SELF command  
● Self - refresh mode reset procedure  
1. Set the SELF bit to 0 or access to SDRAM/FCRAM.  
2. Issue SELFX command  
3. Issue the REF command the number of times set in the RFC2 to RFC0 bits.  
4. Transition to the normal access state  
9.2 Power-on Sequence  
This section describes the power - on sequence.  
■ Power-on Sequence  
Setting the PON bit in the refresh control register (RCR) to 1 initiates the power - on sequence.  
Take the following steps to set the PON bit to 1 for transition to the power - on sequence.  
1. Reserve the clock stabilization wait time specified in the SDRAM/FCRAM manual.  
2. Set ACR, AWR, MCRA(B).  
3. Set the CSER to enable the area to which SDRAM/FCRAM has been connected.  
4. Set the PON bit to 1 while setting the RCR value.  
Taking the above steps causes the SDRAM/FCRAM interface to execute the following power - on sequence.  
5. Execute the PALL command.  
6. Execute the REF command eight times.  
7. The mode register is set according to the BST bit in the ACR, CL (CAS Latency) bit in the AWR, and the  
WBST bit in the MCRA.  
8. Transition to the normal access state  
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Chapter 31 External Bus  
9.SDRAM/FCRAM Interface Operation  
9.3 Connecting SDRAM/FCRAM to Many Areas  
This section shows the connecting SDRAM/FCRAM to many areas.  
■ Connecting SDRAM/FCRAM to Many Areas  
SDRAM/FCRAM can basically be set for all chip select areas. When connecting SDRAM/FCRAM to several  
areas, connect the same type of modules. Also it needs considerations about bus load when connecting SDRAM/  
FCRAM to several areas.  
More precisely, connect the modules common in the following register settings.  
•
Area configuration register (ACR): Set all of the DBW1 - DBW0, BST1 - BST0, and TYP3 - TYP0 bits to the  
same.  
•
•
•
Area wait register (AWR): Set all the bits to the same.  
Memory setting register (MCR): All the settings are the same as the registers are common.)  
Refresh control register (RCR): All the settings are the same as the registers are common.)  
To enable the two areas at a time, execute the power - on sequence, auto - refresh, and self - refresh at the same  
time.  
9.4 Address Multiplexing Format  
This section describes the address multiplexing format.  
■ Address Multiplexing Format  
SDRAM/FCRAM access addresses correspond to row, bank, and column addresses differently depending on the  
settings of the ASZ3 to ASZ0, DBW1 and DBW0, PSZ2 to PSZ0, and BANK bits.  
Addresses are arranged in the order of Column, BANK, and Row addresses, starting from the least significant bit.  
Set each bit as shown below.  
•
ASZ3 to ASZ0 bits: Set these bits to the total amount of SDRAM/FCRAM connected to the corresponding  
area. For using two modules in parallel, set the total amount. Affects the number of row addresses.  
•
DBW1 and DBW0 bits: Set these bits to the data bus width. (Set the bits to " 16 bits " for connecting a pair of  
eight - bit modules in parallel.) Column addresses are shifted according to the data bus width setting. 8 bits:  
Do not shift. 16 bits: Shift one bit. 32 bits: Shift two bits.  
•
•
PSZ2 to PSZ0 bits: Set these bits to the number of column addresses used for SDRAM/FCRAM.  
BANK bit: Set this bit to the number of SDRAM/FCRAM bank addresses.  
Figure 4.9 - 6 shows examples of combinations of access addresses and Row/BANK/Column addresses.  
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Chapter 31 External Bus  
9.SDRAM/FCRAM Interface Operation  
Figure 9-6 Examples of combinations of access addresses and Row/BANK/Column addresses  
4M bytes (set ASZ to 0110B), 8-bit bus width (set DBW to 00B  
)
256 column (set PSZ to 000B), 2 banks (set BANK to 0B  
)
2221  
9 8 7  
BA  
0
Access address bit  
31  
ROW  
COLUMN  
External address pin  
A14  
A12A11A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  
16M bytes (set ASZ to 1000B), 16-bit bus width (set DBW to 01B  
)
512 column (set PSZ to 001B), 4 banks (set BANK to 1B  
)
24 23  
12 1110 9  
BA  
1 0  
COLUMN  
Access address bit  
31  
ROW  
A15A14  
A11A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  
External address pin  
64M bytes (set ASZ to 1010B), 32-bit bus width (set DBW to 10B  
)
512 column (set PSZ to 001B), 4 banks (set BANK to 1B  
)
26 25  
13121110  
BA  
2 1 0  
Access address bit  
31  
ROW  
COLUMN  
A15A14  
A12A11A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  
External address pin  
9.5 Memory Connection Example  
This section shows the memory connection example.  
Memory Connection Example  
The SDRAM/FCRAM interface is connected to SDRAM/FCRAM as shown in Table 4.9 - 1 in principle.  
Table 9-1 SDRAM/FCRAM Interface to SDRAM/FCRAM Connection Table  
SDRAM/  
FCRAM  
interface  
pin  
SDRAM/  
FCRAM pin  
Remarks  
MCLKO  
CLK  
CKE  
RAS  
MCLKE  
SRAS (AS)  
SCAS (BAA) CAS  
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Chapter 31 External Bus  
9.SDRAM/FCRAM Interface Operation  
Table 9-1 SDRAM/FCRAM Interface to SDRAM/FCRAM Connection Table  
SDRAM/  
FCRAM  
interface  
pin  
SDRAM/  
FCRAM pin  
Remarks  
SWE (WR)  
CS0 to CS7  
A0 to A9  
WE  
CS  
All chip select areas can be set as SDRAM/FCRAM space.  
A0 to A9  
Addresses do not have to be shifted depending on the bus  
width.  
A10/AP  
A11 to A13  
A14  
A10/AP  
A11 to A13  
BA0  
A10 for row address output; otherwise AP  
Connected to the address used for SDRAM/FCRAM.  
BA for 2 bank product  
A15  
BA1  
The pin is not used for a two - bank module.  
D31 to D0  
DQ  
The connection changes depending on the endian method  
and data bus width.  
For detailed connection, see Section " 4. Endian and Bus  
Access " .  
DQMUU,  
DQMUL,  
DQMLU,  
DQMLL  
DQM  
The connection changes depending on the endian method  
and data bus width.  
For detailed connection, see Section " 4. Endian and Bus  
Access " .  
● Using 8 - bit SDRAM/FCRAM (Big endian)  
Total data bus width of 32 bits: Use four SDRAM/FCRAM modules.  
Total data bus width of 16 bits: Use two SDRAM/FCRAM modules.  
Figure 9-7 shows how to use 64 - Mbit SDRAM (one bank address and 12 row addresses).  
588  
Chapter 31 External Bus  
9.SDRAM/FCRAM Interface Operation  
Figure 9-7 Using 64 - Mbit SDRAM  
This LSI  
CS6  
or  
DQMUU  
DQMLU  
MCLKO  
DQ31-0  
[31-24]  
A14  
A11-A0  
CS7  
SRAS SCAS SWE MCLKE  
DQMUL  
DQMLL  
BA  
BA  
IA11-IA0  
CKE DQM  
RAS CAS WE  
CLK  
CLK  
CLK  
DQ7-DQ0  
[23-16]  
CS  
CS  
CS  
CS  
SDRAM(No.1)  
DQ7-DQ0  
IA11-IA0  
CKE DQM  
RAS CAS WE  
SDRAM(No.2)  
[15-8]  
DQ7-DQ0  
[7-0]  
BA IA11-IA0  
CKE  
DQM  
RAS CAS WE  
SDRAM(No.3)  
BA  
IA11-IA0  
CKE  
DQM CLK  
DQ7-DQ0  
RAS CAS WE  
SDRAM(No.4)  
When SDRAM modules are used with a total data width of 16 bits, SDRAMs No. 3 and No. 4 are not required and  
DQ15 to DQ0 must be left open.  
● Using 16 - bit SDRAM/FCRAM  
Total data width of 32 bits: Use two or four SDRAM modules.  
Total data width of 16 bits: Use one or two SDRAM modules.  
Figure 9-8 shows how to use 64-Mbit SDRAM (two bank addresses and 12 row addresses).  
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Chapter 31 External Bus  
9.SDRAM/FCRAM Interface Operation  
Figure 9-8 Using 64 - Mbit SDRAM  
This LSI  
DQMUU  
SRAS SCAS SWE MCLKE  
DQMLU  
DQMLL  
A11-A0  
MCLKO  
DQ31-0  
A15 A14  
DQMUL  
CS7 CS6  
[31-16]  
BA1BA0 IA11-IA0  
DQ15-DQ0  
[15-0]  
CKE DQMUDQML  
RAS CAS WE  
CLK  
CLK  
CLK  
CLK  
CS  
CS  
CS  
CS  
SDRAM(No.1)  
CKE DQMUDQML  
RAS CAS WE  
DQ15-DQ0  
[31-16]  
BA1BA0  
IA11-IA0  
SDRAM(No.2)  
CKE DQMU DQML  
DQ15-DQ0  
[15-0]  
RAS CAS WE  
BA1BA0IA11-IA0  
SDRAM(No.3)  
IA11-IA0  
BA1BA0  
CKE DQMUDQML  
DQ15-DQ0  
RAS CAS WE  
SDRAM(No.4)  
When using one SDRAM module with a data width of 16 bits, SDRAMs No. 2, No. 3, and No. 4 are not required  
and DQ15 to DQ0 must be left open.  
When two SDRAM modules are used with a data width of 16 bits, SDRAMs No. 2 and No. 4 are not required.  
When two SDRAM modules are used with a data width of 32 bits, SDRAMs No. 3 and No. 4 are not required.  
● Using 32 - bit SDRAM  
When the data width is 32 bits: Use one or two SDRAM modules.  
Figure 9-9 shows 64-Mbit SDRAM (one bank address and 12 row addresses).  
Figure 9-9 Using 64 - Mbit  
This LSI  
DQMUU  
MCLKE  
DQMLU  
DQMUL DQMLL  
MCLKO  
DQ31-0  
CS7 CS6 A14  
SRAS SCAS SWE  
A11-A0  
[31-0]  
BA IA11-IA0  
CKE DQM3 DQM2DQM1DQM0 CLK  
RAS CAS WE  
DQ31-DQ0  
CS  
CS  
SDRAM(No.1)  
[31-0]  
CKE DQM3 DQM2DQM1 DQM0 CLK  
DQ31-DQ0  
BA IA11-IA0  
RAS CAS WE  
SDRAM(No.2)  
590  
   
Chapter 31 External Bus  
9.SDRAM/FCRAM Interface Operation  
SDRAM No. 2 is not required when the device is used with only one SDRAM module.  
591  
Chapter 31 External Bus  
10.DMA Access Operation  
10. DMA Access Operation  
This section explains DMA access operation.  
■ DMA Access Operation  
This section explains the following five DMA operations:  
•
•
•
•
•
DMA fly-by transfer (I/O -> memory)  
DMA fly-by transfer (memory -> I/O)  
2-cycle transfer (internal RAM -> I/O, RAM)  
2-cycle transfer (external -> I/O)  
2-cycle transfer (I/O -> external)  
10.1 DMA Fly-By Transfer (I/O -> Memory)  
This section explains DMA fly-by transfer (I/O -> memory).  
■ DMA Fly-By Transfer (I/O -> Memory)  
Figure 10-1 "Timing Chart for DMA Fly-By Transfer (I/O -> Memory)" shows the operation timing chart for (TYP3-  
0=0000 , AWR=0008 , IOWR=41 ).  
B
H
H
Figure 10-1 "Timing Chart for DMA Fly-By Transfer (I/O -> Memory)" shows when case when a wait is not set on  
the memory side.  
592  
 
Chapter 31 External Bus  
10.DMA Access Operation  
Figure 10-1 Timing Chart for DMA Fly-By Transfer (I/O -> Memory)  
I/O wait I/O hold  
cycle wait  
Basic cycle  
MCLK  
memory address  
A[31:0]  
AS  
CSn  
WRn  
D[31:0]  
DACKn  
FR30  
compatible  
mode  
DEOPn  
DACKn  
DEOPn  
IORD  
Basic  
mode  
Sense timing in  
demand mode  
DREQn  
n = 0, 1, 2  
•
•
•
•
•
Setting 1 for the W01 bit of the AWR register enables the CSn -> RD/WRn setup delay to be set. Set this bit  
to extend the period between assertion of chip select and the read/write strobe.  
Setting 1 for the W00 bit of the AWR register enables the RD/WRn -> CSn hold delay to be set. Set this bit to  
extend the period between negation of the read/write strobe and negation of chip select.  
nThe CSn -> RD/WRn setup delay (W01 bit) and RD/WRn -> CS hold delay (W00 bit) can be set  
independently.  
When successive accesses are made within the same chip select area without negating the chip select,  
neither CSn -> RD/WRn setup delay nor RD/WRn -> CSn hold delay is inserted.  
If a setup cycle for determining the address or a hold cycle for determining the address is needed, set 1 for the  
address -> CSn delay setting (W02 bit of the AWR register).  
For I/O on the data output side, a read strobe of three bus cycles extended by the I/O wait cycle and I/O hold wait  
cycle is generated. For memory on the receiving side, a write strobe of two bus cycles extended by the I/O wait  
cycle is generated. The I/O hold wait cycle does not affect the write strobe. However, the address and CS signal  
are retained until the fly-by bus access cycles end.  
593  
 
Chapter 31 External Bus  
10.DMA Access Operation  
10.2 DMA Fly-By Transfer (Memory -> I/O)  
This section explains DMA fly-by transfer (memory -> I/O).  
■ DMA Fly-By Transfer (Memory -> I/O)  
Figure 10-2 "Timing chart for DMA Fly-By Transfer (Memory -> I/O)" shows the operation timing chart for (TYP3-  
0=0000 , AWR=0008 , IOWR=41 ).  
B
H
H
Figure 10-2 "Timing chart for DMA Fly-By Transfer (Memory -> I/O)" shows a case in which a wait is not set on  
the memory side.  
Figure 10-2 Timing chart for DMA Fly-By Transfer (Memory -> I/O)  
I/O wait I/O hold  
Basic cycle  
cycle  
wait  
MCLK  
memory address  
A[31:0]  
AS  
CSn  
RD  
D[31:0]  
DACKn  
FR30  
compatible  
mode  
DEOPn  
DACKn  
DEOPn  
IORD  
Basic  
mode  
Sense timing in  
demand mode  
DREQn  
•
•
•
•
•
Setting 1 for the HLD bit of the IOWR0-3 registers extends the I/O read cycle by one cycle.  
Setting bits WR1-0 bits of the IOWR0-3 registers enables 0-3 write recovery cycles to be inserted.  
If the write recovery cycle is set to 1 or more, a write recovery cycle is always inserted after write access.  
Setting bits IW3-0 of the IOWR0-3 registers enables 0-15 wait cycles to be inserted.  
If wait is also set on the memory side (AWR15-12 is not 0), the larger value is used as the wait cycle after  
comparison with the I/O wait (IW3-0 bits).  
594  
 
Chapter 31 External Bus  
10.DMA Access Operation  
Reference:  
For memory on the data output side, a read strobe of three bus cycles extended by the I/O wait cycle and I/O  
hold wait cycle is generated. For I/O on the receiving side, a write strobe of two bus cycles extended by the I/  
O wait cycle is generated. The I/O hold wait cycle does not affect the write strobe. However, the address and  
CS signal are retained until the fly-by bus access cycles end.  
10.3 DMA Fly-By Transfer (I/O -> SDRAM/FCRAM)  
This section describes the operation of DMA fly - by transfer (I/O device to SDRAM/FCRAM).  
■ DMA Fly-By Transfer (I/O -> SDRAM/FCRAM)  
Figure 4.10 - 3 shows an operation timing chart assuming TYP3 to TYP0 set to 1000B, AWR set to 0051H, and  
IOWR set to 41H.  
595  
Chapter 31 External Bus  
10.DMA Access Operation  
Figure 10-3 Timing Chart for DMA Fly - by Transfer (I/O to SDRAM/FCRAM)  
I/O wait  
cycle  
I/O hold  
wait  
Basic cycle  
MCLK  
memory  
address  
A31 to 0  
AS  
CSn  
SRAS  
SCAS  
WRn(SWE)  
D31 to 0  
DACKn  
FR30  
compatible  
mode  
DEOPn  
DACKn  
DEOPn  
Basic  
mode  
IORD  
DREQn  
596  
Chapter 31 External Bus  
10.DMA Access Operation  
•
•
For the I/O device on the data output side, a read strobe of three bus cycles extended by the I/O wait cycle  
and I/O hold wait cycle is generated.  
For SDRAM/FCRAM on the receiving side, a WRIT command is issued at the timing that allows writing after  
the I/O wait cycle. The I/O wait cycle may be longer depending on the SDRAM/FCRAM bank active state and  
SDRAM/FCRAM wait setting.  
•
•
•
The I/O hold wait cycle does not affect the write strobe. Note, however, that the CS signal is retained until the  
fly - by bus access cycles end.  
For fly - by transfer from an I/O device to SDRAM/FCRAM, be sure to set the HLD bit in the DMAC I/O wait  
register (IOWR) to 1 to enable the I/O hold wait cycle.  
Fly - by transfer must always be performed between data buses having the same bus width.  
10.4 DMA Fly-By Transfer (SDRAM/FCRAM -> I/O)  
This section describes the operation of DMA fly - by transfer (SDRAM/FCRAM device to I/O).  
■ DMA Fly-By Transfer (SDRAM/FCRAM -> I/O)  
Figure 1.10 - 4 shows an operation timing chart assuming TYP3 to TYP0 set to 1000B, AWR set to 0051H, and  
IOWR set to 42H.  
597  
Chapter 31 External Bus  
10.DMA Access Operation  
● At SDRAM page hit (Shortest)  
Figure 10-4 Timing Chart for DMA Fly - by Transfer (SDRAM/FCRAM to I/O) with Page Hits (Shortest)  
SDRAM  
basic cycle  
I/O hold  
wait  
I/O wait  
cycle  
I/O  
basic cycle  
MCLK  
column  
address  
A31 to 0  
CSn  
SRAS  
SCAS  
WRn(SWE)  
MCLKE  
D31 to 0  
DACKn  
DEOPn  
Basic  
mode  
Data setup  
IOWR  
DREQn  
598  
Chapter 31 External Bus  
10.DMA Access Operation  
If SDRAM access is shorter than I/O access, the SDRAM access is extended by the I/O access (base access  
plus I/O wait).  
Figure 4.10 - 5 shows an operation timing chart assuming TYP3 to TYP0 set to 1000B, AWR set to 0051H, and  
IOWR set to 42H.  
● At SDRAM page misses  
Figure 10-5 Timing Chart for DMA Fly - by Transfer (SDRAM/FCRAM to I/O) with Page Misses  
I/O hold  
wait  
SDRAM basic cycle  
I/O basic cycle  
I/O wait  
MCLK  
Bank  
address  
Row  
address  
Column  
address  
A31 to 0  
CSn  
SRAS  
SCAS  
WRn(SWE)  
MCLKE  
D31 to 0  
DACKn  
DEOPn  
Basic  
mode  
IOWR  
DREQn  
•
•
If SDRAM access is extended, for example, by precharging when a page miss occurs in reference to SDRAM,  
the SDRAM access exceeds the set I/O access, so that the I/O access is extended to be longer than the  
SDRAM access. When the I/O device requires data setup, therefore, the I/O wait cycle must be set such that I/  
O access is longer than the maximum SDRAM access cycle. For the above settings, set the number of I/O  
wait cycles to at least 4.  
For SDRAM/FCRAM on the data output side, a READ command is issued at the timing that satisfies the I/O  
wait cycle. If the I/O hold cycle has been set, then, a DESL command is issued to insert the I/O hold cycle in  
the cycle immediately followed by the  
599  
Chapter 31 External Bus  
10.DMA Access Operation  
•
For the I/O device on the receiving side, a write strobe of two bus cycles extended by the I/O wait cycle is  
generated.  
•
•
•
The I/O hold wait cycle does not affect the write strobe.  
Fly - by transfer must always be performed between data buses having the same bus width.  
When the I/O wait cycle is used to reserve data setup time, the I/O wait value must be set according to the  
page miss condition. A page hit therefore generates a penalty. If this penalty generated at a page hit causes a  
problem, prepare an external circuit as illustrated in Figure 4.10 - 6c to use an external wait cycle based on the  
CAS signal, thereby extending I/O access to reserve data setup time.  
Figure 10-6 Sample Circuit Solving a Fly - by Penalty Using External Wait Cycles Based on the CAS  
Signal (CL = 2)  
This LSI  
SDRAM  
CLK  
CKE  
MCLK  
MCLKE  
SRAS  
SCAS  
SME  
RAS  
CAS  
WE  
DQMUU  
DQMUL  
A11-A0  
A14  
DQMU  
DQML  
IA11-IA0  
BA0  
BA1  
A15  
D31-D16  
CS6  
DQ15-DQ0  
CS  
I/O  
Q
D
FF  
CK  
RDY  
IORD  
IOWR  
DACK  
DREQ  
Note:  
•
•
For CL = 3, provide two stages of MCLK - based FF to cause a delay of another cycle.  
If any device requires an external wait cycle, add a logic gate to the RDY signal as required.  
Figure 10-7 Timing Chart for Fly - by Penalty Solution Using External Wait Cycles Based on the CAS  
600  
Chapter 31 External Bus  
10.DMA Access Operation  
Signal (CL = 2)  
I/O hold  
wait  
SDRAM basic access  
I/O basic cycle  
External RDY wait  
MCLK  
Bank  
Address  
Row  
Address  
Column  
Address  
A31 to 0  
CSn  
SRAS  
SCAS  
WRn(SWE)  
MCLKE  
D31 to 0  
DACKn  
DEOPn  
Basic mode  
IOWR  
DREQn  
RDY  
The rise of the IOWR signal can be delayed one cycle by extending SDRAM read access one cycle when the  
signal resulting from OR (negative - logic AND) operation of the CAS signal and the chip select signal for the  
SDRAM area subject to transfer is input t  
As the external wait signal is generated based on the CAS signal rise timing in this case, the data setup time from  
the SDRAM data output to the I/O device can be reserved for one cycle, regardless of a page hit or miss in  
SDRAM.  
Set the external wait using the RYE0 and RYE1 bits in the DMAC I/O wait register such that the RDY function of  
the DMA fly - by access channel to be used is enabled.  
When the CAS latency is 3, SDRAM data output is delayed one cycle. Add one stage of FF by the MCLK to input  
the signal delayed one cycle from the above diagram to the RDY pin.  
601  
Chapter 31 External Bus  
10.DMA Access Operation  
10.5 2-Cycle Transfer (Internal RAM -> External I/O, RAM)  
This section explains 2-cycle transfer (internal RAM -> external I/O, RAM) operation.  
The timing is the same as for external I/O, RAM -> internal RAM.  
■ 2-Cycle Transfer (Internal RAM -> External I/O, RAM)  
Figure 10-8 "Timing Chart for 2-cycle Transfer (Internal RAM -> External I/O, RAM)" shows the operation timing  
chart for (TYP3-0=0000 , AWR=0008 , IOWR=00 ).  
B
H
H
Figure 10-8 "Timing Chart for 2-cycle Transfer (Internal RAM -> External I/O, RAM)" shows a case in which a wait  
is not set on the I/O side.  
Figure 10-8 Timing Chart for 2-cycle Transfer (Internal RAM -> External I/O, RAM)  
MCLK  
I/O address  
A[31:0]  
AS  
CSn  
(I/O side)  
WRn  
D[31:0]  
DACKn  
DEOPn  
FR30  
compatible  
mode  
DACKn  
DEOPn  
Basic  
mode  
DREQn  
•
•
The bus is accessed in the same way as an interface when DMAC transfer is not performed.  
DACKn/DEOPn is not output in the internal RAM access cycles.  
10.6 2-Cycle Transfer (External -> I/O)  
This section explains 2-cycle transfer (external -> I/O) operation.  
602  
 
Chapter 31 External Bus  
10.DMA Access Operation  
■ 2-Cycle Transfer (External -> I/O)  
Figure 10-9 "Timing Chart for 2-Cycle Transfer (External -> I/O" shows the operation timing chart for (TYP3-  
0=0000 , AWR=0008 , IOWR=00 ).  
B
H
H
Figure 10-9 "Timing Chart for 2-Cycle Transfer (External -> I/O" shows a case in which a wait is not set for  
memory and I/O.  
Figure 10-9 Timing Chart for 2-Cycle Transfer (External -> I/O)  
MCLK  
memory address  
idle  
I/O address  
A[31:0]  
AS  
CSn  
RD  
CSn  
WRn  
D[31:0]  
DACKn  
DEOPn  
FR30  
compatible  
mode  
DACKn  
DEOPn  
Basic  
mode  
DREQn  
•
•
The bus is accessed in the same way as an interface when the DMAC transfer is not performed.  
In basic mode, DACKn/DEOPn is output in both transfer source bus access and transfer destination bus  
access.  
10.7 2-Cycle Transfer (I/O -> External)  
This section explains 2-cycle transfer (I/O -> external) operation.  
603  
 
Chapter 31 External Bus  
10.DMA Access Operation  
■ 2-Cycle Transfer (I/O -> External)  
Figure 10-10 "Timing Chart for 2-Cycle Transfer (I/O -> External)" shows the operation timing chart for (TYP3-  
0=0000 , AWR=0008 , IOWR=00 ).  
B
H
H
Figure 10-10 "Timing Chart for 2-Cycle Transfer (I/O -> External)" shows a case in which a wait is not set for  
memory and I/O.  
Figure 10-10 Timing Chart for 2-Cycle Transfer (I/O -> External)  
MCLK  
I/O address  
idle  
memory address  
A[31:0]  
AS  
CSn  
WRn  
CSn  
RD  
D[31:0]  
DACKn  
DEOPn  
FR30  
compatible  
mode  
DACKn  
DEOPn  
Basic  
mode  
DREQn  
•
•
The bus is accessed in the same way as an interface when the DMAC transfer is not performed.  
In basic mode, DACKn/DEOPn is output both in the transfer source bus access and transfer destination bus  
access.  
10.8 2-Cycle Transfer (I/O -> SDRAM/FCRAM)  
This section describes the operation of two - cycle transfer (I/O device to SDRAM/FCRAM).  
604  
 
Chapter 31 External Bus  
10.DMA Access Operation  
■ 2-Cycle Transfer (I/O -> SDRAM/FCRAM)  
Figure 4.10 - 11 shows an operation timing chart assuming TYP3 to TYP0 set to 1000B, AWR set to 0051H, and  
IOWR set to 00H.  
Figure 10-11 Timing Chart for Two - cycle Transfer (I/O to SDRAM/FCRAM)  
MC LK  
I/O  
address  
memory  
address  
A31 to 0  
AS  
idle  
CS n  
SRAS  
SCAS  
WRn(SWE)  
CSn  
RD  
D31 to 0  
DACKn  
DEOPn  
DACKn  
DEOPn  
DREQn  
FR30  
compatible  
mode  
Basic mode  
10.9 2-Cycle Transfer (SDRAM/FCRAM -> I/O)  
This section describes the operation of two - cycle transfer (SDRAM/FCRAM to I/O device).  
■ 2-Cycle Transfer (SDRAM/FCRAM -> I/O)  
Figure 1.10 - 12 shows a timing chart for two - cycle transfer (SDRAM/FCRAM to I/O)  
605  
Chapter 31 External Bus  
10.DMA Access Operation  
Figure 10-12 Timing Chart for Two - cycle Transfer (SDRAM/FCRAM to I/O)  
MCLK  
A31 to 0  
AS  
memory  
address  
I/O address  
CSn  
RD  
CSn  
SRAS  
SCAS  
WRn(SWE)  
D31 to 0  
DACKn  
DEOPn  
DACKn  
DEOPn  
DREQn  
FR30  
compatible  
mode  
Basic  
mode  
606  
Chapter 31 External Bus  
10.DMA Access Operation  
•
•
Bus access is the same as that of the interface for non - DMA transfer.  
In base mode, DACKn/DEOPn is output at both of transfer source bus access and transfer destination bus  
access.  
607  
Chapter 31 External Bus  
11.Bus Arbitration  
11. Bus Arbitration  
This section shows timing charts for releasing the bus right and for acquiring the bus right.  
■ Releasing the Bus Right  
Figure 11-1 "Timing Chart for Releasing the Bus Right" shows the timing chart for releasing the bus right. Figure  
11-2 "Timing Chart for Releasing the Bus Right" shows the timing chart for acquiring the bus right.  
Figure 11-1 Timing Chart for Releasing the Bus Right  
MCLK  
A23 to A0  
AS  
CSn *  
RD  
Read  
D31 to D16  
BRQ  
BGRNT  
1 cycle  
608  
   
Chapter 31 External Bus  
11.Bus Arbitration  
Figure 11-2 Timing Chart for Acquiring the Bus Right  
MCLK  
A23 to A0  
AS  
CSn *  
WE  
Read  
D31 to D16  
BRQ  
BGRNT  
1 cycle  
•
•
•
•
•
Setting 1 for the BREN bit of the TRC register enables bus arbitration by BRQ/BGRNT to be performed.  
When the bus right is released, the pin is set to high impedance and then BGRNT is asserted one cycle later.  
When the bus right is acquired, BGRNT is negated and then each pin is activated one cycle later.  
CSn is set to high impedance only if the SREN bit in the ACR0-7 registers is set.  
If all areas enabled by the CSER register are shared (the SREN bit of the ACR register is 1), AS, BAA, RD,  
WE, and WR0-WR3 are set to high impedance.  
609  
 
Chapter 31 External Bus  
12.Procedure for Setting a Register  
12. Procedure for Setting a Register  
This section explains the procedure for setting a register.  
■ Procedure for Setting a Register  
Using the following procedures to make external bus interface settings:  
1. Before rewriting the contents of a register, be sure to set the CSER register so that the corresponding area is  
not used (0). If you change the settings while 1 is set, access before and after the change cannot be  
guaranteed.  
2. Use the following procedure to change a register:  
•
•
•
•
•
Set 0 for the CSER bit corresponding to the applicable area.  
Set both ASR and ACR at the same time using word access.  
Set AWR.  
Set the CHER bit corresponding to the applicable area.  
Set the CSER bit corresponding to the applicable area.  
3. The CS0 area is enabled after a reset is released. If the area is used as a program area, the register contents  
need to be rewritten while the CSER bit is 1. In this case, make the settings described in 2) to 4) above in the  
initial state with a low-speed internal clock. Then, switch the clock to a high-speed clock.  
4. Use the following procedure to change the register value in an area for which prefetch:  
•
•
•
•
•
•
•
Set 0 for the bit of CSER corresponding to the applicable area.  
Set 1 for both the PSUS bit and PCLR bit of the TCR register.  
Set both ASR and ACR at the same time using word access.  
Set AWR.  
Set the CHER bit corresponding to the applicable area.  
Set 0 for both the PSUS bit and PCLR bit of the TCR register.  
Set 1 for the bit of CSER corresponding to the applicable area.  
610  
 
Chapter 31 External Bus  
13.Notes on Using the External Bus Interface  
13. Notes on Using the External Bus Interface  
This section explains some notes when using the external bus interface.  
■ Notes for Use  
If settings are made so that the area (TYP3-0=0x0x ) where WR0-WR3 are used as a write strobe and the area  
B
(TYP3-0=0x1x ) where WR is used as a write strobe are mixed, be sure to make the following setting in all areas  
B
that will be used:  
•
•
Set at least one read -> write idle cycle (other than AWR W07-W06=00 ).  
B
Set at least one write recovery cycle (other than AWR W05-W04=00 ).  
B
However, if WR0-WR3 are disabled (ROM only is connected) in the area (TYP3-0=0x0x ) where WR0-WR3 are  
B
used as a write strobe, the above restriction does not apply. Also, the above restriction does not apply if both the  
address -> RD/WRn setup cycle (W01=1) and RD/WRn -> address hold cycle (W00=1) are set in the area (TYP3-  
0=0x1x ) where WE is used as a write strobe.  
B
611  
 
Chapter 31 External Bus  
13.Notes on Using the External Bus Interface  
612  
Chapter 32 USART (LIN / FIFO)  
1.Overview  
Chapter 32 USART (LIN / FIFO)  
1. Overview  
This chapter explains the function and operation of the USART. The USART with LIN (Local Interconnect  
Network) - Function is a general-purpose serial data communication interface for performing synchronous or  
asynchronous communication with external devices. 16 bytes transmission and reception FIFOs are available  
for selected channels.  
The USART provides bidirectional communication function (normal mode), master-slave communication  
function (multiprocessor mode in master/slave systems), and special features for LIN-bus systems (working  
both as master or as slave device).  
(Note)  
This chapter only lists the registers and addresses of USART04. Please refer to the IO-Map for the  
addresses of the other USARTs.  
■ USART Functions  
USART is a general-purpose serial data communication interface for transmitting serial data to and receiving  
data from another CPU or peripheral devices. It has the functions listed in  
table 1-1.  
Table 1-1 USART functions  
Function  
Item  
Data buffer  
Serial Input  
Full-duplex  
5 times oversampling in asynchronous mode  
Transfer mode  
- Clock synchronous (start-stop synchronization and  
start-stop-bit-option)  
- Clock asynchronous (using start-, stop-bits)  
Baud rate  
- A dedicated baud rate generator is provided, which  
consists of a 15-bit-reload counter  
- An external clock can be input and also be adjusted  
by the reload counter  
Data length  
- 7 bits (not in synchronous or LIN mode)  
- 8 bits  
Signal mode  
Non-return to zero (NRZ) and return to zero (RZ)  
Start bit timing  
Clock synchronization to the falling edge of the start bit  
in asynchronous mode  
Reception error  
detection  
- Framing error  
- Overrun error  
- Parity error  
Interrupt request  
- Reception interrupt (reception complete, reception  
error detect, Bus-Idle, LIN-Synch-break detect)  
- Transmission interrupt (transmission complete)  
613  
     
Chapter 32 USART (LIN / FIFO)  
1.Overview  
Table 1-1 USART functions (continued)  
Master-slave communication  
function  
(multiprocessor mode)  
One-to-n communication (one master to n slaves)  
(This function is supported both for master and slave  
system).  
Synchronous mode  
Transceiving pins  
LIN bus options  
Function as Master- or Slave-USART  
Direct access possible  
- Operation as master device  
- Operation as slave device  
- Generation of LIN-Sync-break  
- Detection of LIN-Sync-break  
- Detection of start/stop edges in LIN-Sync-field  
connected to ICU 0 and 2  
Synchronous serial clock  
The synchronous serial clock can be output  
continuously on the SCK pin for synchronous  
communication with start & stop bits  
Clock delay option  
16 word deep FIFO  
Special synchronous Clock Mode for delaying clock  
(useful for SPI-compliance)  
FIFO can be activated with receive progammable  
trigger level  
■ USART operation modes  
The USART operates in four different modes, which are determined by the MD0- and the MD1-bit of the Serial  
mode register (SMR04). Mode 0 and 2 are used for bidirectional serial communication, mode 1 for master/  
slave communication and mode 3 for LIN master/slave communication.  
Table 1-2 USART operation modes  
Operation  
mode  
Data length  
Synchroniza-  
tion of mode  
Length  
of  
stop bit  
data bit  
directio  
n*  
parity  
disabled  
parity  
enabled  
0
1
2
3
normal mode  
multiprocessor  
normal mode  
LIN mode  
7 or 8  
asynchronous  
asynchronous  
synchronous  
asynchronous  
1 or 2  
1 or 2  
0, 1 or 2  
1
L/M  
L/M  
L/M  
L
7 or 8 + 1**  
8
-
-
8
* means the data bit transfer format: LSB or MSB first.  
** "+1" means the indicator bit of the address/data selection in the multiprocessor mode, instead of parity.  
Mode 1 operation is supported both for master or slave operation of USART in a master-slave connection  
system. In Mode 3 the USART function is locked to 8N1-Format, LSB first.  
If the mode is changed, USART cuts off all possible transmission or reception and then awaits new action.  
The MD1 and MD0 bits of the Serial Mode Register (SMR04) determine the operation mode of USART04 as  
shown in the following table:  
614  
Chapter 32 USART (LIN / FIFO)  
1.Overview  
Table 1-3 Mode Bit Setting  
MD1  
MD0  
Mode  
Description  
0
0
1
1
0
1
0
1
0
1
2
3
Asynchronous (normal mode)  
Asynchronous (multiprocessor mode)  
Synchronous (normal mode)  
Asynchronous (LIN mode)  
■ USART Interrupts  
Table 1-4 USART interrupts  
Interrupt  
cause  
Interrupt  
number  
Interrupt control register  
Interrupt Vector  
Offset Default address  
Register name  
Address  
USART04  
reception  
interrupt  
#66 (42 )  
ICR25  
0459  
0459  
2F4  
000FFEF4  
H
H
H
H
H
USART04  
transmission  
interrupt  
#67 (43 )  
ICR25  
2F0  
000FFEF0  
H
H
H
615  
Chapter 32 USART (LIN / FIFO)  
2.USART Configuration  
2. USART Configuration  
■ USART consists of the following blocks:  
• Reload Counter  
• Reception Control Circuit  
• Reception Shift Register  
• Reception Data Register  
• Transmission Control Circuit  
• Transmission Shift Register  
• Transmission Data Register  
• Error Detection Circuit  
• Oversampling Unit  
• Interrupt Generation Circuit  
• LIN Break Generation  
• LIN Break and Synch Field Detection  
• Bus Idle Detection Circuit  
• Serial Mode Register (SMR04)  
• Serial Control Register (SCR04)  
• Serial Status Register (SSR04)  
• Extended Com. Contr. Reg. (ECCR04)  
• Extended Status/Contr. Reg. (ESCR04)  
• FIFO Control Register (FCR04)  
• FIFO Status Register (FSR04)  
616  
 
Chapter 32 USART (LIN / FIFO)  
2.USART Configuration  
Figure 2-1 USART Block Diagram  
(OTO,  
EXT,  
REST)  
PE ORE  
FRE  
CLK  
TIE  
RIE  
transmission clock  
LBIE  
LBD  
BIE  
RBI  
TBI  
Reload  
Interrupt  
Generation  
circuit  
reception clock  
TRANSMISSION  
Counter  
CONTROL  
SCK0  
RECEPTION  
CIRCUIT  
CONTROL  
CIRCUIT  
Pin  
Start bit  
Detection  
circuit  
Transmission  
Start circuit  
reception  
IRQ  
Restart Reception  
Reload Counter  
SIN0  
transm.  
IRQ  
TDRE  
Received  
Bit counter  
Transmission  
Bit counter  
Pin  
SOT0  
Over-  
sampling  
Unit  
Received  
Parity counter  
Transmission  
Parity counter  
Pin  
RDRF  
reception  
SOT  
SIN  
complete  
SIN  
LIN break  
Signal  
to ICU  
LIN  
break  
genera-  
tion  
and Synch  
Field  
Reception  
shift register  
Transmission  
shift register  
Detection  
circuit  
transmission  
start  
circuit  
Bus idle  
Detection  
circuit  
Error  
Detection  
LBR  
LBL1  
LBL0  
Signal  
to EI2OS  
PE  
ORE  
FRE  
TDR (FIFO)  
RDR (FIFO  
RBI  
TBI  
LBD  
Internal data bus  
LBIE  
LBD  
LBL1  
LBL0  
SOPE  
SIOP  
CCO  
PE  
ORE  
FRE  
RDRF  
TDRE  
BDS  
RIE  
PEN  
P
SBL  
CL  
A/D  
CRE  
RXE  
TXE  
MD1  
LBR  
MD0  
(OTO)  
(EXT)  
(REST)  
UPCL  
SCKE  
SOE  
MS  
SCDE  
SSM  
BIE  
RBI  
TBI  
SSR  
ECCR  
SSR  
register  
ESCR  
register  
SCR0  
register  
register  
register  
TIE  
SCES  
■ Explanation of the different blocks  
• Reload Counter  
The reload counter functions as the dedicated baud rate generator. It can select external input clock or internal  
clock for the transmitting and receiving clocks. The reload counter has a 15 bit register for the reload value.  
The actual count of the transmission reload counter can be read via the BGR0/1 registers.  
• Reception Control Circuit  
The reception control circuit consists of a received bit counter, start bit detection circuit, and received parity  
counter. The received bit counter counts reception data bits. When reception of one data item for the specified  
data length is complete, the received bit counter sets the Reception data register full flag. When the FIFO is  
enabeld, the flag is set if the triggerlevel is reached. The start bit detection circuit detects start bits from the  
serial input signal and sends a signal to the reload counter to synchronize it to the falling edge of these start  
bits. The reception parity counter calculates the parity of the reception data.  
• Reception Shift Register  
The reception shift register fetches reception data input from the SIN04 pin, shifting the data bit by bit. When  
reception is complete, the reception shift register transfers receive data to the RDR04 register.  
617  
Chapter 32 USART (LIN / FIFO)  
2.USART Configuration  
• Reception Data Register  
This register retains reception data. Serial input data is converted and stored in this register. If the FIFO is  
enabled up to 16 receptions can be saved, the trigger level is progammable.  
• Transmission Control Circuit  
The transmission control circuit consists of a transmission bit counter, transmission start circuit, and  
transmission parity counter.The transmission bit counter counts transmission data bits. When the transmission  
of one data item of the specified data length is complete, the transmission bit counter sets the Transmission  
data register full flag. The transmission start circuit starts transmission when data is written to TDR04. The  
transmission parity counter generates a parity bit for data to be transmitted if parity is enabled.  
• Transmission Shift Register  
The transmission shift register transfers data written to the TDR04 register to itself and outputs the data to the  
SOT04 pin, shifting the data bit by bit.  
• Transmission Data Register  
This register sets transmission data. Data written to this register is converted to serial data and output.  
If the FIFO is enabled up to 16 transmissions can be saved and continuously transmitted  
• Error Detection Circuit  
The error detection circuit checks if there was any error during the last reception. If an error has occurred it  
sets the corresponding error flags.  
• Oversampling Unit  
The oversampling unit oversamples the incoming data at the SIN04 pin for five times. It is switched off in  
synchronous operation mode.  
• Interrupt Generation Circuit  
The interrupt generation circuit administers all cases of generating a reception or transmission interrupt. If a  
corresponding enable flag is set and an interrupt case occurs the interrupt will be generated immediately.  
• LIN Break and Synchronization Field Detection Circuit  
The LIN break and LIN synchronization field detection circuit detects a LIN break, if a LIN master node is  
sending a message header. If a LIN break is detected a special flag bit is generated. The first and the fifth  
falling edge of the synchronization field is recognized by this circuit by generating an internal signal for the  
Input Capture Unit to measure the actual serial clock time of the transmitting master node.  
• LIN Break Generation Circuit  
The LIN break generation circuit generates a LIN break of a determined length.  
• Bus Idle Detection circuit  
The bus idle detection circuit recognizes if neither reception nor transmission is going on. In this case the  
circuit generates a special flag bit.  
• Serial Mode Register  
This register performs the following operations:  
• Selecting the USART operation mode  
• Selecting a clock input source  
• Selecting if an external clock is connected “one-to-one” or connected to the reload counter  
• Resetting the USART (preserving the settings of the registers)  
• Specifying whether to enable serial data output to the corresponding pin  
• Specifying whether to enable clock output to the corresponding pin  
• Serial Control Register  
This register performs the following operations:  
• Specifying whether to provide parity bits  
• Selecting parity bits  
• Specifying a stop bit length  
618  
Chapter 32 USART (LIN / FIFO)  
2.USART Configuration  
• Specifying a data length  
• Selecting a frame data format in mode 1  
• Clearing the error flags  
• Specifying whether to enable transmission  
• Specifying whether to enable reception  
• Serial Status Register  
This register checks the transmission and reception status and error status, and enables and disables  
transmission and reception interrupt requests.  
• Extended Status/Control Register  
This register provides several LIN functions, direct access to the SIN04 and SOT04 pin and setting for the  
USART synchronous clock mode.  
• Extended Communication Control Register  
The extended communication control register provides bus idle recognition interrupt settings, synchronous  
clock settings, and the LIN break generation.  
• FIFO Control Register  
With the FCR4 register the TX/RX FIFOs can be enabled, the RX interrupt triggerlevel can be set and the  
FIFO status register mode can be set.  
• FIFO Status Register  
With the FSR4 register shows the number of valid RX/TX data in the FIFO buffers.  
619  
Chapter 32 USART (LIN / FIFO)  
3.USART Pins  
3. USART Pins  
■ USART Pins  
The USART pins also serve as general ports. Table 3-1 lists the pin functions, I/O formats, and settings  
required to use USART.  
Table 3-1 USART04 Pins  
Pull-up  
Pull-down  
Standby  
control  
Setting required to use  
pin  
Pin name  
Pin function  
I/O format  
Set port function mode:  
PFR: bit0 = 1,  
EPFR: bit0 = 0  
Port I/O or serial  
data input  
SIN04  
Set to output enable mode:  
SMR04: SOE = 1,  
Set port function mode:  
PFR: bit1 = 1  
Port I/O or serial  
data output  
CMOS output and  
CMOS hystere-  
sis, CMOS Auto-  
motive hysteresis,  
TTL input  
SOT04  
SCK04  
Program-  
mable  
Provided  
EPFR: bit1 = 0  
Set port function mode:  
PFR: bit2 = 1  
EPFR: bit2 = 0  
Set to output enable mode  
when a clock is output  
SMR04: SCKE = 1  
Port I/O or serial  
clock input/output  
Figure 3-1 Block Diagram of USART pins  
Port Bus  
PDR read  
Peripheral input  
Peripheral output  
PDR  
Pin  
PFR  
DDR  
620  
   
Chapter 32 USART (LIN / FIFO)  
4.USART Registers  
4. USART Registers  
The following table defines the USART04 registers:  
Table 4-1 USART04 Registers  
Address  
bit 15  
bit 8  
bit 7  
bit 0  
060 , 061  
SCR04 (Serial Control Register)  
SSR04 (Serial Status Register)  
SMR04 (Serial Mode Register)  
H
H
H
H
062 , 063  
RDR04/TDR04 (Rx, Tx Data Register)  
H
064 , 065  
ESCR04 (Extended Status/Control  
Reg.)  
ECCR04 (Extended Comm. Contr.  
Reg.)  
H
066 , 067  
FSR04 (FIFO status register)  
FCR04 (FIFO control register)  
H
H
H
088 , 089  
BGR104 (Baud Rate Generator Reg. 1) BGR004 (Baud Rate Generator Reg. 0)  
H
(Note)  
FSR (FIFO status register) and FCR (FIFO control register) register are only available on USARTs  
with FIFO option, i.e. USART ch. 4-7.  
4.1 Serial Control Register 04 (SCR04)  
This register specifies parity bits, selects the stop bit and data lengths, selects a frame data format in mode 1,  
clears the reception error flag, and specifies whether to enable transmission and reception.  
621  
 
Chapter 32 USART (LIN / FIFO)  
4.USART Registers  
Figure 4-1 Serial Control Register 04 (SCR04)  
Initial value  
15 14 13 12 11 10  
9
8
B
0 0 0 0 0 0 0 0  
R/W R/W R/W R/W R/W W R/W R/W  
bit8  
TXE  
Transmission enable  
0
1
Disable Transmission  
Enable Transmission  
bit9  
RXE  
0
Reception enable  
Disable Reception  
Enable Reception  
1
bit10  
Clear Reception errors  
CRE  
write  
read  
0
1
ignored  
read always returns 0  
Clear all reception  
errors (PE, FRE, ORE)  
bit11  
AD  
0
Address / Data bit  
Data bit  
1
Address bit  
bit12  
CL  
0
Character (Data frame) Length  
7 bits  
8 bits  
1
bit13  
SBL  
0
Stop bit length  
Parity setting  
Parity Enable  
1 stop bit  
1
2 stop bits  
bit14  
P
0
1
Even Parity enabled  
Odd Parity enabled  
bit15  
PEN  
0
Parity disabled  
Parity enabled  
R/W  
W
:
:
:
Readable and writable  
Write only  
1
Initial value  
622  
Chapter 32 USART (LIN / FIFO)  
4.USART Registers  
Table 4-2 Functions of each bit of control register 04 (SCR04)  
Bit name  
Function  
This bit selects whether to add a parity bit during transmission in  
serial asynchronous mode or detect it during reception.  
Parity is only provided in mode 0 and in mode 2 if SSM of the  
ECCR04 is selected. This bit is fixed to 0 (no parity) in mode 3  
(LIN).  
bit15 PEN: Parity enable  
bit  
bit14 P: Parity selection bit When parity is provided and enabled this bit selects even (0) or  
odd (1) parity  
bit13 SBL: Stop bit length  
selection bit  
This bit selects the length of the stop bit of an asynchronous data  
frame or a synchronous frame if SSM of the ECCR04 is selected.  
This bit is fixed to 0 (1 stop bit) in mode 3 (LIN).  
bit12 CL: Data length  
selection bit  
This bit specifies the length of transmission or reception data. This  
bit is fixed to 1 (8 bits) in mode 2 and 3.  
bit11 AD: Address/Data  
selection bit *  
This bit specifies the data format in multiprocessor mode 1. Writing  
to this bit determines an address or data frame to be sent next,  
reading from it returns the last received kind of frame. “1” indicates  
an address frame, “0” indicates a usual data frame.  
Note:  
During a RMW-Read cycle the AD bit returns the value to be  
sent instead of the last received AD bit.  
see table below*  
bit10 CRE: Clear reception This bit clears the FRE, ORE, and PE flag of the Serial Status  
error flags bit  
Register (SSR04). This bit also clears a possible reception  
interrupt caused by errors.  
Writing a 1 to it clears the error flag.  
Writing a 0 has no effect.  
Reading from it always returns 0.  
bit9  
bit8  
RXE: Reception  
enable bit  
This bit enables USART reception.  
If this bit is set to 0, USART disables the reception of data frames.  
The LIN break detection in mode 0 or 3 remains unaffected.  
TXE: Transmission  
enable bit  
This bit enables USART transmission. If this bit is set to 0, USART  
disables the transmission of data frames.  
* see table 4-3 for R/W options  
Table 4-3 * Read/Write options of AD-Bit  
Cycle  
Action  
Write  
Normal Read Read received AD-Bit  
RMW-Read Read data to be sent from AD-Bit  
Write data to be sent to AD-Bit  
623  
 
Chapter 32 USART (LIN / FIFO)  
4.USART Registers  
4.2 Serial Mode Register 04 (SMR04)  
This register selects an operation mode and baud rate clock and specifies whether to enable output of serial  
data and clocks to the corresponding pin.  
Figure 4-2 Configuration of the Serial Mode register 04 (SMR04)  
Initial value  
7
6
5
4
3
2
1
0
B
0 0 0 0 0 0 0 0  
R/W R/W R/W R/W  
W
W R/W R/W  
bit0  
SOE  
Serial Output enable  
0
1
disable SOT04 pin (high Z)  
enable SOT04 pin (TxData)  
bit1  
SCKE  
Serial Clock Output enable  
0
1
External Serial Clock Input  
Internal Serial Clock Output  
bit2  
USART programmable clear (Software Reset)  
UPCL  
write  
read  
0
1
ignored  
always 0  
Reset USART  
bit3  
Restart dedicated Reload Counter  
read  
REST  
write  
0
1
ignored  
always 0  
Restart Counter  
bit4  
EXT  
0
External Serial Clock Source enable  
Use internal Baud Rate Generator (Reload Counter)  
Use external Serial Clock Source  
1
bit5  
OTO  
0
One-to-one external clock Input enable  
Use ext. Clock with Baud Rate Generator (Reload C.)  
Use external Clock as is  
1
bit6  
MD0  
0
bit7  
MD1  
Operation Mode Setting  
Mode 0: Asynchronous normal  
Mode 1: Asynchronous Multiprocessor  
Mode 2: Synchronous  
R/W  
W
:
:
:
Readable and writable  
Write only  
0
0
1
1
1
Initial value  
0
1
Mode 3: Asynchronous LIN  
624  
Chapter 32 USART (LIN / FIFO)  
4.USART Registers  
Table 4-4 Bit function of the Serial Mode register 04 (SMR04)  
Bit name  
Function  
These two bits sets the USART operation mode.  
bit7  
bit6  
MD1 and MD0:  
Operation mode  
selection bits  
bit5  
OTO: One-to-one  
external clock  
selection bit  
This bit sets an external clock directly to the USART’s serial clock.  
This function is used for synchronous slave mode operation  
bit4  
bit3  
EXT: External clock  
selection bit  
This bit executes internal or external clock source for the reload  
counter  
REST: Restart of  
transmission reload  
counter bit  
If a 1 is written to this bit the reload counter is restarted. Writing 0  
to it has no effect. Reading from this bit always returns 0.  
bit2  
UPCL: USART  
programmable clear  
bit (Software reset)  
Writing a 1 to this bit resets USART immediately. The register  
settings are preserved. Possible reception or transmission will cut  
off.  
All error flags are cleared and the Reception Data Register  
(RDR04) contains 00h. Writing 0 to this bit has no effect. Reading  
from it always returns 0.  
bit1  
SCKE: Serial clock  
output enable  
• This bit controls the serial clock input-output ports.  
• When this bit is 0, the SCK04 pin operates as serial clock input  
pin. When this bit is 1, the SCK04 pin operates as serial clock  
output pin.  
<Caution>  
• When using the SCK04 pin as serial clock input (SCKE=0) pin,  
set the pin as input port. Also, select external clock (EXT = 1)  
using the external clock selection bit.  
bit0  
SOE: Serial data  
output enable bit  
• This bit enables or disables the output of serial data.  
• When this bit is 0, the SOT04 pin outputs the default mark level.  
When this bit is 1, the SOT04 pin outputs the transmission data.  
4.3 Serial Status Register 04 (SSR04)  
This register checks the transmission statuts, reception status and error status, and enables and disables the  
transmission and reception interrupts.  
625  
Chapter 32 USART (LIN / FIFO)  
4.USART Registers  
Figure 4-3 Configuration of the Serial Status register 04 (SSR04)  
Initial value  
15 14 13 12 11 10  
9
8
B
0 0 0 0 1 0 0 0  
R
R
R
R
R
R/W R/W R/W  
bit8  
TIE  
Transmission Interrupt enable  
0
1
Disables Transmission Interrupt  
Enables Transmission Interrupt  
bit9  
RIE  
Reception Interrupt enable  
0
1
Disables Reception Interrupt  
Enables Reception Interrupt  
bit10  
BDS  
0
Bit direction setting  
send / receive LSB first  
send / receive MSB first  
1
bit11  
TDRE  
0
Transmission data register empty  
Transmission data register is full  
1
Transmission data register is empty  
bit12  
RDRF  
0
Reception data register full  
Reception data register is empty  
Reception data register is full  
1
bit13  
FRE  
0
Framing error  
No framing error occurred  
1
A framing error occurred during reception  
bit14  
ORE  
0
Overrun error  
No overrun error occurred  
1
An overrun error occurred during reception  
bit15  
PE  
0
Parity error  
No parity error occurred  
R/W  
:
Readable and writable  
R
:
Flag is read only, writing to it  
has no effect  
1
A parity error occurred during reception  
:
Initial value  
626  
Chapter 32 USART (LIN / FIFO)  
4.USART Registers  
Table 4-5 Functions of each bit of status register 04 (SSR04)  
Bit name  
Function  
• This bit is set to 1 when a parity error occurs during reception and is  
cleared when 0 is written to the CRE bit of the serial control register  
(SCR04).  
bit15 PE: Parity error  
flag bit  
• A reception interrupt request is output when this bit and the RIE bit are 1.  
• Data in the reception data register (RDR04) is invalid when this flag is set.  
bit14 ORE: Overrun  
error flag bit  
• This bit is set to 1 when an overrun error occurs during reception and is  
cleared when 0 is written to the CRE bit of the serial control register  
(SCR04).  
• A reception interrupt request is output when this bit and the RIE bit are 1.  
• Data in the reception data register (RDR04) is invalid when this flag is set.  
bit13 FRE: Framing  
error flag bit  
• This bit is set to 1 when a framing error occurs during reception and is  
cleared when 0 is written to the CRE bit of the serial control register 1  
(SCR04).  
• A reception interrupt request is output when this bit and the RIE bit are 1.  
• Data in the reception data register (RDR04) is invalid when this flag is set.  
bit12 RDRF: Receive  
data full flag bit  
• This flag indicates the status of the reception data register (RDR04).  
• This bit is set to 1 when reception data is loaded into RDR04 and can only  
be cleared to 0 when the reception data register (RDR04) is read.  
• A reception interrupt request is output when this bit and the RIE bit are 1.  
bit11 TDRE:  
Transmission  
data empty flag  
bit  
• This flag indicates the status of the transmission data register (TDR04).  
• This bit is cleared to 0 when transmission data is written to TDR04 and is  
set to 1 when data is loaded into the transmission shift register and  
transmission starts.  
• A transmission interrupt request is generated if this bit and the RIE bit are  
1.  
<Caution>  
This bit is set to 1 (TDR04 empty) as its initial value.  
bit10 BDS: Transfer  
direction selection  
bit  
• This bit selects whether to transfer serial data from the least significant bit  
(LSB first, BDS=0) or the most significant bit (MSB first, BDS=1).  
<Caution>  
The high-order and low-order sides of serial data are interchanged with  
each other during reading from or writing to the serial data register. If this  
bit is set to another value after the data is written to the RDR04 register,  
the data becomes invalid.  
This bit is fixed to 0 in mode 3 (LIN)  
bit9  
RIE: Reception  
interrupt request  
enable bit  
• This bit enables or disables input of a request for transmission interrupt to  
the CPU.  
• A reception interrupt request is output when this bit and the reception data  
flag bit (RDRF) are 1 or this bit and one or more error flag bits (PE, ORE,  
and FRE) are 1.  
627  
Chapter 32 USART (LIN / FIFO)  
4.USART Registers  
Table 4-5 Functions of each bit of status register 04 (SSR04)  
Bit name  
Function  
bit8  
TIE: Transmission • This bit enables or disables output of a request for transmission interrupt  
interrupt request  
enable bit  
to the CPU.  
• A transmission interrupt request is output when this bit and the TDRE bit  
are 1.  
4.4 Reception and Transmission Data Register (RDR04 / TDR04)  
The reception data register (RDR04) holds the received data. The transmission data register (TDR04) holds  
the transmission data. Both RDR04 and TDR04 registers are located at the same address.  
(Note)  
TDR04 is a write-only register and RDR04 is a read-only register. These registers are located in the  
same address, so the read value is different from the write value. Therefore, instructions that perform  
a read-modify-write (RMW) operation, such as the INC/DEC instruction, cannot be used.  
Figure 4-4 Transmission and Reception Data registers 04 (RDR04 / TDR04)  
7
6
5
4
3
2
1
0
Initial value  
B
0 0 0 0 0 0 0 0  
R/W R/W R/W R/W R/W R/W R/W R/W  
bit8-0  
R/W  
Data Registers  
Read  
Write  
Read from Reception Data Register  
Write to Transmission Data Register  
R/W  
:
Readable and writable  
■ Reception:  
RDR04 is the register that contains reception data. The serial data signal transmitted to the SIN04 pin is  
converted in the shift register and stored there. When the data length is 7 bits, the uppermost bit (D7) contains  
0. When reception is complete the data is stored in this register and the reception data full flag bit (SSR04:  
RDRF) is set to 1. If a reception interrupt request is enabled at this point, a reception interrupt occurs.  
Read RDR04 when the RDRF bit of the status register (SSR04) is 1. The RDRF bit is cleared automatically to  
0 when RDR04 is read. Also the reception interrupt is cleared if it is enabled and no error has occurred.  
Data in RDR04 is invalid when a reception error occurs (SSR04: PE, ORE, or FRE = 1).  
■ Transmission:  
When data to be transmitted is written to the transmission data register in transmission enable state, it is  
transferred to the transmission shift register, then converted to serial data, and transmitted from the serial data  
output terminal (SOT04 pin). If the data length is 7 bits, the uppermost bit (D7) is not sent.  
When transmission data is written to this register, the transmission data empty flag bit (SSR04: TDRE) is  
cleared to 0. When transfer to the transmission shift register is complete, the bit is set to 1. When the TDRE bit  
is 1, the next part of transmission data can be written. If output transmission interrupt requests have been  
628  
Chapter 32 USART (LIN / FIFO)  
4.USART Registers  
enabled, a transmission interrupt is generated. Write the next part of transmission data when a transmission  
interrupt is generated or the TDRE bit is 1.  
4.5 Extended Status/Control Register (ESCR04)  
This register provides several LIN functions, direct access to the SIN04 and SOT04 pin and setting for USART  
synchronous clock mode.  
Figure 4-5 Configuration of the Extended Status/Control Register (ESCR04)  
Initial value  
15 14 13 12 11 10  
9
8
B
0 0 0 0 0 1 0 0  
R/W R/W R/W R/W R/W R/W R/W R/W  
bit8  
SCES  
Sampling Clock Edge Selection (Mode 2)  
Sampling on rising clock edge (normal)  
0
1
Sampling on falling clock edge (inverted clock)  
bit9  
CCO  
0
Continuous Clock Output (Mode 2)  
Continuous Clock Output disabled  
Continuous Clock Output enabled  
1
bit10  
Serial Input / Output Pin Access  
SIOP  
write (if SOPE = “1”)  
SOT04 is forced to “0”  
SOT04 is forced to “1”  
read  
0
1
reading the actual value of  
SIN04  
bit11  
SOPE  
0
Enable Serial Output pin direct Access  
Serial Output pin direct access disable  
Serial Output pin direct access enable  
1
bit12  
bit 13  
LBL0  
LBL1  
LIN break length  
LIN break length 13 bit times  
LIN break length 14 bit times  
LIN break length 15 bit times  
LIN break length 16 bit times  
0
1
0
1
0
0
1
1
bit14  
LIN break detected  
read *  
LBD  
write  
0
1
Clear LIN break  
detected flag  
No LIN break detected  
ignored  
LIN break detected  
bit15  
LBIE  
0
LIN break detection Interrupt enable  
LIN break interrupt disable  
LIN break interrupt enable  
R/W  
:
:
Readable and writable  
Initial value  
1
* see table 4-6 for RMW access!  
629  
Chapter 32 USART (LIN / FIFO)  
4.USART Registers  
Table 4-6 Function of each bit of the Extended Status/Control Register (ESCR4)  
Bit name  
Function  
bit15 LBIE: LIN break  
detection interrupt  
enable bit  
This bit enables a reception interrupt, if a LIN break was detected.  
bit14 LBD: LIN break  
detected flag  
This bit goes 1 if a LIN break was detected. Writing a 0 to it clears this  
bit and the corresponding interrupt, if it is enabled.  
Note: RMW instructions always return "1". In this case, the value "1"  
does not indicate a LIN-Break.  
bit13 LBL1/0: LIN break  
bit12 length selection  
These two bits determine how many serial bit times the LIN break is  
generated by USART. Receiving a LIN break is always fixed to 13 bit  
times.  
bit11 SOPE: Serial Output  
pin direct access  
enable*  
Setting this bit to 1 enables the direct write to the SOT04 pin, if SOE  
= 1 (SMR04).*  
bit10 SIOP: Serial Input/  
Output Pin direct  
access*  
Normal read instructions always return the actual value of the SIN04  
pin. Writing to it sets the bit value to the SOT04 pin, if SOPE = 1.  
During a Read-Modify-Write instruction the bit returns the SOT04  
value in the read cycle.*  
bit9  
bit8  
CCO: Continuos  
Clock Output enable  
bit  
This bit enables a continuos serial clock at the SCK04 pin if USART  
operates in master mode 2 (synchronous) and the SCK04 pin is  
configured as a clock output.  
SCES: Serial clock  
edge selection bit  
This bit inverts the internal serial clock in mode 2 (synchronous) and  
the output clock signal, if USART operates in master mode 2  
(synchronous) and the SCK04 pin is configured as a clock output.  
In slave mode 2 the sampling time turns from rising edge to falling  
edge.  
* see table 4-7 for SOPE and SIOP interaction  
Table 4-7 * Description of the interaction of SOPE and SIOP:  
SOPE  
SIOP  
R/W  
Writing to SIOP  
Reading from SIOP  
0
has no effect on the SOT4 pin returns current value of SIN04  
but holds the written value.  
1
1
R/W  
write "0" or "1" to SOT04  
returns current value of SIN04  
RMW  
returns current value of SOT04  
and writes it back  
4.6 Extended Communication Control Register (ECCR04)  
The extended communication control register provides bus idle recognition, interrupt settings, synchronous  
clock settings, and the LIN break generation.  
630  
   
Chapter 32 USART (LIN / FIFO)  
4.USART Registers  
Figure 4-6 Configuration of the Extended Communication Control Register (ECCR04)  
7
6
5
4
3
2
1
0
Initial value  
B
0 0 0 0 0 0 X X  
R/W W R/W R/W R/W R/W  
R
R
bit0  
TBI *  
Transmission bus idle  
0
1
Transmission is ongoing  
no transmission activity  
bit1  
RBI *  
Reception bus idle  
0
1
Reception is ongoing  
no reception activity  
bit2  
BIE *  
Bus idle interrupt enable  
0
1
disable Bus idle interrupt  
enable Bus idle interrupt  
bit3  
SSM  
Synchronous start/stop bits in mode 2  
0
1
No start/stop bits in synchronous mode 2  
Enable start/stop bits in synchronous mode 2  
bit4  
SCDE  
Serial Clock Delay enable in mode 2  
disable clock delay  
0
1
enable clock delay  
bit5  
MS  
0
Master / Slave function in mode 2  
Master mode (generating serial clock)  
Slave mode (receiving external serial clock)  
1
bit6  
Set LIN break  
LBR  
write  
read  
0
1
ignored  
always read 0  
Generate LIN break  
bit7  
INV  
0
Invert Serial Data  
R/W  
:
Readable and writable  
Serial data is not inverted (NRZ format)  
Serial data is inverted (RZ format)  
1
R
W
X
:
:
:
:
Flag is read only  
Flag is write only  
Indeterminate  
Initial value  
* not useable in mode 2  
631  
Chapter 32 USART (LIN / FIFO)  
4.USART Registers  
Table 4-8 Function of each bit of the Extended Communication Control Register (ECCR04)  
Bit name  
Function  
bit7  
INV: Invert serial  
data  
This bit inverts the serial data at SIN04 and SOT04 pin. SCK04 is  
not affected (see ESCR04: SCES).  
Writing "0": The serial data format is NRZ (default)  
Writing "1": The serial data is inverted (RZ format)  
RMW instructions do not affect this bit.  
bit6  
bit5  
LBR: Set LIN break  
bit  
Writing a 1 to this bit generates a LIN break of the length selected  
by the LBL0/1 bits of the ESCR04, if operation mode 0 or 3 is  
selected.  
MS: Master/Slave  
mode selection bit  
This bit selects master or slave mode of USART in synchronous  
mode 2. If master is selected USART generates the synchronous  
clock by itself. If slave mode is selected USART receives external  
serial clock.  
<Caution>  
If slave mode is selected, the clock source must be external and  
set to “One-to-One” (SMR04: SCKE = 0, EXT = 1, OTO = 1).  
bit4  
SCDE: Serial clock  
delay enable bit  
If this bit is set, the serial output clock is delayed by 1 CLKP cycle  
(or half of its period in SPI-compliance). This only applies, if  
USART operates in master mode 2.  
bit3  
bit2  
SSM: Start/Stop bit  
mode enable  
This bit adds start and stop bits to the synchronous data format in  
operation mode 2. It is ignored in mode 0, 1, and 3.  
BIE: Bus idle  
interrupt enable  
This bit enables a reception interrupt, if there is neither reception  
nor transmission ongoing (RBI = 1, TBI = 1).  
Note: Do not use BIE in mode 2.  
bit1  
bit0  
RBI: Reception bus  
idle flag bit  
This bit is “1” if there is no reception activity on the SIN04 pin.  
Note: Do not use this flag in mode 2.  
TBI: Transmission  
bus idle flag bit  
This bit is “1” if there is no transmission activity on the SOT04 pin.  
Note: Do not use this flag in mode 2.  
4.7 Baud Rate / Reload Counter Register 0 and 1 (BGR04 / 14)  
The baud rate / reload counter registers set the division ratio for the serial clock. Also the actual count of the  
transmission reload counter can be read.  
632  
Chapter 32 USART (LIN / FIFO)  
4.USART Registers  
Figure 4-7 Baudrate Reload Counter Register 0 and 1 (BGR04 / 14)  
Initial value  
15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
B
B
0 0 0 0 0 0 0 0  
0 0 0 0 0 0 0 0  
R/W  
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W  
bit 0 - 7  
BGR0  
write  
read  
Baud rate Generator Register 1  
Write bit 0 - 7 of reload value to counter  
Read bit 0 - 7 of actual count  
bit 8 - 15  
BGR1  
write  
Baud rate Generator Register 0  
Write bit 8 - 15 of reload value to counter  
Read bit 8 - 15 of actual count  
read  
R/W  
:
Readable and writable  
The Baud Rate / Reload Counter Registers determine the division ratio for the serial clock.  
Both registers can be read or written via byte or word access.  
633  
Chapter 32 USART (LIN / FIFO)  
4.USART Registers  
4.8 FIFO Control Register (FCR04)  
Figure 4-8 Configuration of FIFO control registe  
Initial value  
7
6
5
4
3
2
1
0
B
0 0 0 0 0 0 0 0  
R/WR/W R/W R/W R R/W R/W R/W  
bit 0  
SVD  
0
select Fifo read valid date status for RX / TX  
Select reading status from RX FIFO  
1
Select reading status from TX FIFO  
bit 1  
ETX  
0
control TX FIFO (on / off)  
Disables TX FIFO  
1
Enables TX FIFO  
bit 2  
ERX  
0
control RX FIFO (on / off)  
Disables RX FIFO  
1
Enables RX FIFO  
bit 3  
not used / always read 0  
bit 4  
RXL0  
0
RX Triggerlevel  
RX Triggerlevel Bit 0  
bit 5  
RXL1  
0
RX Triggerlevel  
RX Triggerlevel Bit 1  
bit 6  
RXL2  
0
RX Triggerlevel  
RX Triggerlevel Bit 2  
bit 7  
RXL3  
0
RX Triggerleve  
RX Triggerlevel Bit 3  
R/W  
R
:
:
Readable and writable  
Flag is read only, writing to it  
has no effect  
:
Initial value  
634  
Chapter 32 USART (LIN / FIFO)  
4.USART Registers  
Table 4-9 Functions of each bit of fifo control register (FCR4)  
Bit name  
Function  
bit 0  
SVD: select Valid  
Data Fifo read  
• If this bit is set to 0 the fifo status register shows the number of valid data  
from the RX fifo  
• If this bit is set to 1 the fifo status register shows the number of valid data  
from the TX fifo  
bit 1  
bit 2  
ETX: enable TX  
fifo  
• If this bit is set to 0 the TX fifo is disabled / fifo data is cleared  
• If this bit is set to 1 the TX fifo is enabled.  
ERX: enable RX  
fifo  
• If this bit is set to 0 the RX fifo is disabled / fifo data is cleared  
• If this bit is set to 1 the RX fifo is enabled.  
bit 3  
bit 4  
reserved  
RXL0: RX  
Triggerlevel bit 0  
• Set the triggerlevel of RX Interrupt  
bit 5  
bit 6  
bit 7  
RXL1: RX  
Triggerlevel bit 1  
• Set the triggerlevel of RX Interrupt  
• Set the triggerlevel of RX Interrupt  
• Set the triggerlevel of RX Interrupt  
RXL2: RX  
Triggerlevel bit 2  
RXL3: RX  
Triggerlevel bit 3  
(Note)  
The RX triggerlevel sets the reception FIFO level where the reception interrupt is activated. E.g. if  
the triggerlevel is at its default value of RXL[3:0]=0000, the interrupt is activated if one reception is  
stored in the FIFO. If the the triggerlevel is set to RXL[3:0]=1111, the interrupt is activated if 16  
receptions are stored in the FIFO. In general: a reception interrupt is triggered if FSR[4:0] >  
FCR[3:0].  
635  
Chapter 32 USART (LIN / FIFO)  
4.USART Registers  
4.9 FIFO Status Register (FSR04)  
Figure 4-9 Configuration of FIFO status register  
Initial value  
7
6
5
4
3
2
1
0
B
0 0 0 0 0 0 0 0  
R
R
R
R
R
R
R
R
bit 0  
FIFO valid data number  
FIFO: number of valid Data Bit 0  
0
bit 1  
FIFO valid data number  
FIFO: number of valid Data Bit 1  
0
bit 2  
FIFO valid data number  
FIFO: number of valid Data Bit 2  
0
bit 3  
FIFO valid data number  
FIFO: number of valid Data Bit 3  
0
bit 4  
FIFO valid data number  
0
FIFO: number of valid Data Bit 4  
not used / always read 0  
not used / always read 0  
not used / always read 0  
bit 5  
bit 6  
bit 7  
:
R
:
Flag is read only, writing to it  
has no effect  
:
Initial value  
(Note)  
The FSR04[4:0] FIFO valid data bits indicates the number of stored receptions (SVD=0) or pending  
transmissions (SVD=1) in the FIFO buffer.  
636  
Chapter 32 USART (LIN / FIFO)  
4.USART Registers  
Table 4-10 Functions of each bit of FIFO status Register  
Bit name  
Function  
bit 0  
bit 1  
bit 2  
bit 3  
bit 4  
FIFO: number of  
valid Data  
• shows the number of valid FIFO - Data  
for RX and TX Fifo, depending on selection bit.  
FIFO: number of  
valid Data  
• shows the number of valid FIFO - Data  
for RX and TX Fifo, depending on selection bit.  
FIFO: number of  
valid Data  
• shows the number of valid FIFO - Data  
for RX and TX Fifo, depending on selection bit..  
FIFO: number of  
valid Data  
• shows the number of valid FIFO - Data  
for RX and TX Fifo, depending on selection bit..  
FIFO: number of  
valid Data  
• shows the number of valid FIFO - Data  
for RX and TX Fifo, depending on selection bit.  
637  
Chapter 32 USART (LIN / FIFO)  
5.USART Interrupts  
5. USART Interrupts  
The USART uses both reception and transmission interrupts. An interrupt request can be generated for either  
of the following causes:  
• Receive data is set in the Reception Data Register (RDR04), or a reception error occurs.  
• Transmission data is transferred from the Transmission Data Register (TDR04) to the transmission shift  
register.  
• A LIN break is detected  
• No bus activity (neither reception nor transmission)  
■ USART Interrupts  
Table 5-1 Interrupt control bits and interrupt causes of USART  
Operation  
Interrupt  
cause  
enable bit  
How to clear  
the Interrupt  
Request  
Reception/  
transmission/  
ICU  
Interrupt  
request  
flag bit  
Flag  
Register  
mode  
Interrupt  
cause  
0
1
2
3
Reception  
RDRF  
SSR04  
x
x
x
x
receive data is  
written to RDR  
SSR04 :  
RIE  
Receive data  
is read  
(FIFO level reached)  
ORE  
FRE  
PE  
SSR04  
SSR04  
SSR04  
ESCR04  
x
x
x
x
x
x
x
*
*
x
x
Overrun error  
Framing error  
Parity error  
"1" is written to  
clear rec. error  
bit (SCR04:  
CRE)  
LBD  
x
x
x
x
x
LIN synch break  
detected  
ESCR04 :  
LBIE  
"0" is written to  
ESCR04 : LBD  
TBI &  
RBI  
ESCR04  
SSR04  
IPCP4  
x
x
x
x
x
x
no bus activity  
ECCR04 :  
BIE  
Receive data /  
Send data  
Transmission TDRE  
x
Empty transmission  
register  
SSR04 :  
TIE  
Transfer data is  
written  
Input  
Capture Unit  
ICP4  
ICP4  
1st falling edge of  
LIN synch field  
IPCP4 :  
ICE4  
disable ICE4  
temporary  
IPCP4  
5th falling edge of  
LIN synch field  
IPCP4 :  
ICE4  
disable ICE4  
x
*
: Used  
: Only available if ECCR04/SSM = 1  
■ Reception Interrupt  
If one of the following events occur in reception mode, the corresponding flag bit of the Serial Status Register  
(SSR04) is set to "1":  
• - Data reception is complete, i. e. the received data was transferred from the serial input shift register to the  
Reception Data Register (RDR04) and data can be read: RDRF (if FIFO is enabled, trigger level is reached)  
• - Overrun error, i. e. RDRF = 1 and RDR04 was not read by the CPU: ORE  
638  
 
Chapter 32 USART (LIN / FIFO)  
5.USART Interrupts  
• - Framing error, i. e. a stop bit was expected, but a "0"-bit was received: FRE  
• - Parity error, i. e. a wrong parity bit was detected: PE  
If at least one of these flag bits above go "1" and the reception interrupt is enabled  
(SSR04: RIE = 1), a reception interrupt request is generated.  
If the Reception Data Register (RDR04) is read, the RDRF flag is automatically cleared to "0". Note that this is  
the only way to reset the RDRF flag. The error flags are cleared to "0", if a "1" is written to the Clear Reception  
Error (CRE) flag bit of the Serial Control Register (SCR04). The RDR04 contains only valid data if the RDRF  
flag is "1" and no error bits are set.  
Note, that the CRE flag is "write only" and by writing a "1" to it, it is internally held to "1" for one CPU clock  
cycle.  
■ Transmission Interrupt  
If transmission data is transferred from the Transmission Data Register (TDR04) to the transfer shift register  
(this happens, if the shift register (or FIFO) is empty and transmission data exists), the Transmission Data  
Register Empty flag bit (TDRE) of the Serial Status Register (SSR04) is set to "1". In this case an interrupt  
request is generated, if the Transmission Interrupt Enable (TIE) bit of the SSR04 was set to "1" before.  
Note, that the initial value of TDRE (after hardware or software reset) is "1". So an interrupt is generated  
immediately then, if the TIE flag is set to "1". Also note, that the only way to reset the TDRE flag is writing data  
to the Transmission Data Register (TDR04).  
■ LIN Synchronization Break Interrupt  
This paragraph is only relevant, if USART operates in mode 0 or 3 as a LIN slave.  
If the bus (serial input) goes "0" (dominant) for more than 11 bit times, the LIN Break Detected (LBD) flag bit of  
the Extended Status/Control Register (ESCR04) is set to "1". Note, that in this case after 9 bit times the  
reception error flags are set to "1", therefore the RIE flag has to be set to "0" or the RXE flag has to be set to  
"0", if only a LIN synch break detect is desired. In the other case a reception error interrupt would be  
generated first, and the interrupt handler routine has then to wait for LBD = 1.  
The interrupt and the LBD flag are cleared after writing a "1" to the LBD flag. This makes sure, that the CPU  
has detected the LIN synch break, because of the following procedure of adjusting the serial clock to the LIN  
master.  
■ LIN Synchronization Field Edge Detection Interrupts  
This paragraph is only relevant, if USART operates in mode 0 or 3 as a LIN slave. After a LIN break detection  
the next falling edge of the reception bus is indicated by USART. Simultaneously an internal signal connected  
to the ICU is set to "1". This signal is reset to "0" after the fifth falling edge of the LIN Synchronization Field. In  
both cases the ICU4 generates an interrupt, if "both edge detection" and the ICU1/5 interrupt are enabled. The  
difference of the ICU4 counter values is the serial clock multiplied by 8. Dividing it by 8 results in the new  
detected and calculated baud rate for the dedicated reload counter. This value - 1 has then to be written to the  
Baud Rate Generator Registers (BGR1/0).There is no need to restart the reload counter, because it is  
automatically reset if a falling edge of a start bit is detected.  
■ Bus Idle Interrupt  
If there is no reception activity on the SIN04 pin, the RBI flag bit of the ECCR04 goes "1". The TBI flag bit  
respectively goes "1", when no data is transmitted. If the Bus Idle Interrupt Enable bit (BIE) of the ECCR04 is  
set and both bus idle flag bits (TBI and RBI) are "1", an interrupt is generated.  
(Note)  
The TBI flag goes also "0" if there is no bus activity, but a "0" is written to the SIOP bit, if SOPE is  
"1".  
(Note)  
TBI nd RBI cannot be used in mode 2 (synchronous communication).  
Figure 5-1 illustrates how the bus idle interrupt is generated  
639  
Chapter 32 USART (LIN / FIFO)  
5.USART Interrupts  
Figure 5-1 Bus idle interrupt generation  
Transmission  
data  
Reception  
data  
TBI  
RBI  
Reception IRQ  
: Start bit  
: Stop bit  
: Data bit  
5.1 Reception Interrupt Generation and Flag Set Timing  
The following are the reception interrupt causes: Completion of reception (SSR04: RDRF) and occurrence of a  
reception error (SSR04: PE, ORE, or FRE).  
■ Reception Interrupt Generation and Flag Set Timing  
Generally a reception interrupt is generated, if the received data is complete (RDRF = 1) and the Reception  
Interrupt Enable (RIE) flag bit of the Serial Status Register (SSR04) was set to "1". This interrupt is generated  
if the first stop bit is detected in mode 0, 1, 2 (if SSM = 1), 3, or the last data bit was read in mode 2 (if SSM =  
0).  
(Note)  
If a reception error has occurred, the Reception Data Register (RDR04) contains invalid data in each  
mode.  
Figure 5-2 Reception operation and flag set timing  
Receive data  
(mode 0/3)  
ST  
ST  
D0  
D0  
D0  
D1  
D1  
D1  
D2  
D2  
D2  
....  
....  
D5  
D6  
D6  
D7  
D5  
D7/P SP  
A/D SP  
ST  
ST  
D0  
Receive data  
(mode 1)  
Receive data  
(mode 2)  
.... D4  
D6  
D7  
PE*, FRE  
RDRF  
ORE**  
(if RDRF = "1")  
reception interrupt occurs  
A/D: Mode 1 (multi processor) address/data selection bit  
* The PE flag will always remain “0” in mode 1 or 3  
ST: Start Bit SP: Stop Bit  
(Note)  
640  
The example in figure 5-2 does not show all possible reception options for mode 0 and 3. Here it is:  
   
Chapter 32 USART (LIN / FIFO)  
5.USART Interrupts  
"7p1" and "8N1" (p = "E" [even] or "O" [odd]), all in NRZ data format (ECCR04: INV = 0).  
(Note)  
**ORE only occurs, if the reception data is not read by the CPU (RDRF = 1) and another data frame  
is read.  
Figure 5-3 ORE set timing  
Receive  
data  
RDRF  
ORE  
5.2 Transmission Interrupt Generation and Flag Set Timing  
A transmission interrupt is generated when the next data to be sent is ready to be written to the output data  
register (TDR04).  
■ Transmission Interrupt Generation and Flag Set Timing  
A transmission interrupt is generated, when the next data to be send is ready to be written to the Transmission  
Data Register (TDR04), i. e. the TDR04 is empty, and the transmission interrupt is enabled by setting the  
Transmission Interrupt Enable (TIE) bit of the Serial Status Register (SSR04) to "1".  
The Transmission Data Register Empty (TDRE) flag bit of the SSR04 indicates an empty TDR04. Because the  
TDRE bit is "read only", it only can be cleared by writing data into TDR04.  
The following figure demonstrates the transmission operation and flag set timing for the four modes of USART.  
Figure 5-4 Transmission operation and flag set timing  
transmission interrupt occurs  
transmission interrupt occurs  
Mode 0, 1 or 3:  
write to TDR04  
TDRE  
P
AD  
P
AD  
ST D0 D1 D2 D3 D4 D5 D6 D7  
SP ST D0 D1 D2 D3 D4 D5 D6 D7  
SP  
serial output  
transmission interrupt occurs  
transmission interrupt occurs  
Mode 2 (SSM = 0):  
write to TDR04  
TDRE  
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4  
serial output  
ST: Start bit D0 ... D7: data bits P: Parity SP: Stop bit AD: Address/data selection bit (mode1)  
(Note)  
The example in figure 5-4 does not show all possible transmission options for mode 0. Here it is:  
"8p1" (p = "E" [even] or "O" [odd]), ECCR04: INV = 0. Parity is not provided in mode 3 or 2, if SSM =  
0.  
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Chapter 32 USART (LIN / FIFO)  
6.USART Baud Rates  
■ Transmission Interrupt Request Generation Timing  
If the TDRE flag is set to 1 when a transmission interrupt is enabled (SSR04: TIE=1) a transmission interrupt  
request is generated.  
A transmission completion interrupt is generated immediately after the transmission interrupt is enabled  
(TIE=1) because the TDRE bit is set to 1 as its initial value. TDRE is a read-only bit that can be cleared only  
by writing new data to the output data register (TDR04). Carefully specify the transmission interrupt enable  
timing.  
6. USART Baud Rates  
One of the following can be selected for the USART serial clock source:  
• Dedicated baud rate generator (Reload Counter)  
• External clock as it is (clock input to the SCK04 pin)  
• External clock connected to the baud rate generator (Reload Counter)  
■ USART Baud Rate Selection  
The baud rate selection circuit is designed as shown below. One of the following three types of baud rates can  
be selected:  
• Baud Rates Determined Using the Dedicated Baud Rate Generator (Reload Counter)  
USART has two independent internal reload counters for transmission and reception serial clock. The baud rate can be  
selected via the 15-bit reload value determined by the Baud Rate Generator Register 0 and 1 (BGR0/1).  
The reload counter divides the peripheral clock by the value set in the Baud Rate Generator Register 0 and 1.  
• Baud Rates determined using external clock (one-to-one mode)  
The clock input from USART clock pulse input pins (SCK04) is used as it is (synchronous). Any baud rate less than the  
peripheral clock divided by 4 and is divisible can be set externally  
• Baud Rates determined using the dedicated baud rate generator with external clock  
An external clock source can also be connected internally to the reload counter. In this mode it is used instead of the  
internal peripheral clock. This was designed to use quartz oscillators with special frequencies and having the possibility  
to divide them.  
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Chapter 32 USART (LIN / FIFO)  
6.USART Baud Rates  
Figure 6-1 Baud rate selection circuit (reload counter)  
REST  
Start bit falling  
edge detected  
Reload Value: v  
Rxc = 0?  
Reload  
set  
Reception  
Clock  
Reception  
16-bit Reload Counter  
FF  
0
1
reset  
Rxc = v/2?  
Reload Value: v  
EXT  
OTO  
Txc = 0?  
Reload  
CLK  
0
1
set  
Transmission  
16-bit Reload Counter  
FF  
0
1
SCK04  
(external  
clock  
reset  
Count Value: Txc  
Txc = v/2?  
Transmission  
Clock  
input)  
Internal data bus  
BGR7  
BGR6  
BGR5  
BGR14  
BGR13  
BGR12  
BGR11  
BGR10  
BGR9  
SMR04  
register  
BGR14  
register  
BGR04  
register  
BGR4  
EXT  
REST  
OTO  
BGR3  
BGR2  
BGR1  
BGR0  
BGR8  
6.1 Setting the Baud Rate  
This section describes how the baud rates are set and the resulting serial clock frequency is calculated.  
■ Calculating the baud rate  
The both 15-bit Reload Counters are programmed by the Baud Rate Generator Registers 1 and 0 (BGR14,  
04). The following calculation formula should be used to set the wanted baud rate:  
Reload Value:  
v = [F / b] - 1 ,  
where F is the resource clock (CLKP), b the baud rate and [ ] gaussian brackets (mathematical rounding  
function).  
■ Example of Calculation  
If the CPU clock is 16 MHz and the desired baud rate is 19200 baud then the reload value v is:  
6
v = [16 10 / 19200] - 1 = 832  
*
6
The exact baud rate can then be recalculated: b  
= F / (v + 1), here it is: 16 10 / 833 = 19207.6831  
exact  
*
(Note)  
(Note)  
Setting the reload value to 0 stops the reload counter.  
The minimum recommended division ratio is 4 (i.e. reload value is 3) due to RX oversampling filter in  
asynchronous communication modes (mode 0,1 and 3).  
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Chapter 32 USART (LIN / FIFO)  
6.USART Baud Rates  
■ Suggested Division Ratios for different machine speeds and baud rates  
The following settings are suggested for different MCU clock speeds and baud rates:  
Table 6-1 Suggested Baud Rates and reload values at different machine speeds.  
8 MHz  
10 MHz  
16 MHz  
20 MHz  
24 MHz  
32 MHz  
Baud  
rate  
%
dev.  
%
dev.  
%
dev.  
%
dev.  
%
dev.  
%
dev.  
value  
value  
value  
value  
value  
value  
2M  
3
7
0
0
4
9
0
0
7
0
0
9
0
11  
23  
0
15  
31  
0
0
1M  
15  
19  
0
0
500000  
460800  
250000  
230400  
153600  
125000  
115200  
76800  
57600  
38400  
28800  
19200  
10417  
9600  
15  
0
19  
0
31  
0
39  
0
47  
0
-0.16  
0
63  
0
-
-
-
-
-
-
-
-
51  
-
-
31  
0
39  
0
63  
0
79  
0
95  
127  
138  
207  
255  
278  
416  
555  
832  
1110  
1666  
3071  
3332  
4443  
6666  
0
-
-
-
-
-
-
86  
0.22  
-0.16  
0
103  
155  
191  
207  
311  
416  
624  
832  
1249  
2303  
2499  
3332  
4999  
9999  
-0.16  
-0.16  
0
-0.08  
0.16  
0
51  
-0.16  
0
64  
-0.16  
0
103  
127  
138  
207  
277  
416  
554  
832  
1535  
1666  
2221  
3332  
6666  
-0.16  
0
129  
159  
173  
259  
346  
520  
693  
1041  
1919  
2083  
2777  
4166  
8332  
63  
79  
-
-
86  
0.22  
-0.16  
0.22  
-0.16  
<0.01  
0.03  
<0.01  
0.03  
<0.01  
-0.02  
<0.01  
0.02  
0.08  
-0.16  
0.08  
0.08  
-0.01  
-0.03  
<0.01  
0.02  
<0.01  
<0.01  
<0.01  
0.22  
-0.16  
-0.06  
0.03  
-0.06  
0.03  
<0.01  
0.03  
<0.01  
<0.01  
<0.01  
-0.16  
-0.16  
0.08  
0
-0.08  
0.08  
0.08  
-0.04  
-0.01  
0.02  
<0.01  
0.01  
-0.01  
<0.01  
103  
138  
207  
277  
416  
767  
832  
1110  
1666  
3332  
6666  
-0.16  
0.08  
-0.16  
0.08  
0.08  
<0.01  
0.04  
<0.01  
0.02  
<0.01  
<0.01  
129  
173  
259  
346  
520  
959  
1041  
1388  
2082  
4166  
8334  
-0.03  
0
<0.01  
0
7200  
<0.01  
0
4800  
2400  
0
13332 <0.01  
26666 <0.01  
1200  
13332 <0.01 16666 <0.01 19999  
0
600  
13332 <0.01 16666 <0.01 26666 <0.01  
26666 <0.01  
-
-
-
-
-
-
-
300  
-
-
-
-
-
■ Counting Example  
Assume the reload value is 832. The figure 6-2 demonstrates the behavior of the both Reload Counters:  
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Chapter 32 USART (LIN / FIFO)  
6.USART Baud Rates  
Figure 6-2 Counting example of the reload counters  
Transmission/  
Reception Clock  
Reload  
001  
000  
832  
831  
830  
829  
828  
827  
Count  
reload count value  
Transmission/  
Reception Clock  
Reload  
417  
416  
415  
414  
413  
412  
411  
410  
Count  
(Note)  
The falling edge of the Serial Clock Signal always occurs after | (v + 1) / 2 |.  
6.2 Restarting the Reload Counter  
The Reload Counter can be restarted because of the following reasons:  
Transmission and Reception Reload Counter:  
• Global MCU Reset  
• USART programmable clear (SMR04:UPCL bit)  
• User programmable restart (SMR04: REST bit)  
Reception Reload Counter:  
• Start bit falling edge detection in asynchronous mode  
■ Programmable Restart  
If the REST bit of the Serial Mode Register (SMR04) is set by the user, both Reload Counters are restarted at  
the next clock cycle. This feature is intended to use the Transmission Reload Counter as a small timer.  
The following figure illustrates a possible usage of this feature (assume that the reload value is 100.)  
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6.USART Baud Rates  
Figure 6-3 Reload Counter Restart example  
MCU  
Clock  
Reload  
Counter  
Clock  
Outputs  
REST  
Reload  
Value  
37  
36  
35 100  
99  
98  
97  
96  
95  
94  
93  
92  
91  
90  
89  
88  
87  
Read  
BGR0/1  
Data  
Bus  
90  
: don’t care  
In this example the number of MCU clock cycles (cyc) after REST is then:  
cyc = v - c + 1 = 100 - 90 + 1 = 11,  
where v is the reload value and c is the read counter value.  
(Note)  
If USART is reset by setting SMR04:UPCL, the Reload Counters will restart too.  
■ Automatic Restart  
In asynchronous UART mode if a falling edge of a start bit is detected the Reception Reload Counter is  
restarted. This is intended to synchronize the serial input shifter to the incoming serial data stream.  
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7.USART Operation  
7. USART Operation  
USART operates in operation mode 0 for normal bidirectional serial communication, in mode 2  
and 3 in bidirectional communication as master or slave, and in mode 1 as master or slave in  
multiprocessor communication.  
■ Operation of USART  
• Operation modes  
There are four USART operation modes: modes 0 to 3. As listed in table 7-1, an operation mode can be  
selected according to the inter-CPU connection method and data transfer mode.  
Table 7-1 USART operation mode  
Operation  
mode  
Data length  
Synchroniza-  
tion of mode  
Length  
of  
stop bit  
data bit  
directio  
n*  
parity  
disabled  
parity  
enabled  
0
1
2
3
normal mode  
multiprocessor  
normal mode  
LIN mode  
7 or 8  
asynchronous  
asynchronous  
synchronous  
asynchronous  
1 or 2  
1 or 2  
0, 1 or 2  
1
L/M  
L/M  
L/M  
L
7 or 8 + 1**  
8
-
-
8
* means the data bit transfer format: LSB or MSB first  
** "+1" means the indicator bit of the address/data selection in the multiprocessor mode, instead of parity.  
(Note)  
Mode 1 operation is supported both for master or slave operation of USART in a master-slave  
connection system. In Mode 3 the USART function is locked to 8N1-Format, LSB first.  
If the mode is changed, USART cuts off all possible transmission or reception and awaits then new action.  
■ Inter-CPU Connection Method  
External Clock One-to-one connection (normal mode) and master-slave connection (multiprocessor mode) can  
be selected. For either connection method, the data length, whether to enable parity, and the synchronization  
method must be common to all CPUs. Select an operation mode as follows:  
• In the one-to-one connection method, operation mode 0 or 2 must be used in the two CPUs. Select  
operation mode 0 for asynchronous transfer mode and operation mode 2 for synchronous transfer mode.  
Note, that one CPU has to set to the master and one to the slave in synchronous mode 2.  
• Select operation mode 1 for the master-slave connection method and use it either for the master or slave  
system.  
■ Synchronization Methods  
In asynchronous operation USART reception clock is automatically synchronized to the falling edge of a  
received start bit.  
In synchronous mode the synchronization is performed either by the clock signal of the master device or by  
USART itself if operating as master.  
■ Signal Mode  
USART can treat data in non-return to zero (NRZ) and return to zero (RZ) format. For this option the ECCR:  
INV bit is provided.  
■ Operation Enable Bit  
USART controls both transmission and reception using the operation enable bit for transmission (SCR04:  
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Chapter 32 USART (LIN / FIFO)  
7.USART Operation  
TXE) and reception (SCR04: RXE). If each of the operations is disabled, stop it as follows:  
• If reception operation is disabled during reception (data is input to the reception shift register), finish frame  
reception and read the received data of the reception data register (RDR04). Then stop the reception  
operation.  
• If the transmission operation is disabled during transmission (data is output from the transmission shift  
register), wait until there is no data in the transmission data register (TDR04) before stopping the  
transmission operation.  
7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1)  
When USART is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the  
asynchronous transfer mode is selected.  
■ Transfer data format  
Generally each data transfer in the asynchronous mode operation begins with the start bit (low-level on bus)  
and ends with at least one stop bit (high-level). The direction of the bit stream (LSB first or MSB first) is  
determined by the BDS-Bit of the Serial Status Register (SSR04). The parity bit (if enabled) is always placed  
between the last data bit and the (first) stop bit.  
In operation mode 0 the length of the data frame can be 7 or 8 bits, with or without parity, and 1 or 2 stop bits.  
In operation mode 1 the length of the data frame can be 7 or 8 bits with a following address-/data-selection bit  
instead of a parity bit. 1 or 2 stop bits can be selected.  
The calculation formula for the bit length of a transfer frame is:  
Length = 1 + d + p + s  
(d = number of data bits [7 or 8], p = parity [0 or 1], s = number of stop bits [1 or 2]  
Figure 7-1 Transfer data format (operation modes 0 and 1)  
*
**  
ST D0 D1 D2 D3 D4 D5 D6 D7/P SP SP  
Operation mode 0  
Operation mode 1  
ST D0 D1 D2 D3 D4 D5 D6 D7 A/D SP  
* D7 (bit 7) if parity is not provided and data length is 8 bits  
P (parity) if parity is provided and data length is 7 bits  
** only if SBL-Bit of SCR is set to 1  
ST: Start Bit  
SP: Stop Bit  
A/D: Address/data selection bit in mode 1 (multiprocessor mode)  
(Note)  
If BDS-Bit of the Serial Status Register (SSR04) is set to "1" (MSB first), the bit stream processes as:  
D7, D6, ... , D1, D0, (P).  
During Reception both stop bits are detected, if selected. But the Reception data register full (RDRF) flag will  
go "1" at the first stop bit. The bus idle flag (RBI of ECCR04) goes "1" after the second stop bit if no further  
start bit is detected. (The second stop bit belongs to "bus activity", although it is just mark level.)  
■ Transmission Operation  
If the Transmission Data Register Empty (TDRE) flag bit of the Serial Status Register (SSR04) is "1",  
transmission data is allowed to be written to the Transmission Data Register (TDR04). When data is written,  
the TDRE flag goes "0". If the transmission operation is enabled by the TXE-Bit ("1") of the Serial Control  
Register (SCR04), the data is written next to the transmission shift register and the transmission starts at the  
next clock cycle of the serial clock, beginning with the start bit. Thereby the TDRE flag goes "1", so that new  
data can be written to the TDR04.  
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Chapter 32 USART (LIN / FIFO)  
7.USART Operation  
If transmission interrupt is enabled (TIE = 1), the interrupt is generated by the TDRE flag. Note, that the initial  
value of the TDRE flag is "1", so that in this case if TIE is set to "1" an interrupt will occur immediately.  
■ Reception Operation  
Reception operation is performed every time it is enabled by the Reception Enable (RXE) flag bit of the  
SCR04. If a start bit is detected, a data frame is received according to the format specified by the SCR04. By  
occurring errors, the corresponding error flags are set (PE, ORE, FRE). However after the reception of the  
data frame the data is transferred from the serial shift register to the Reception Data Register (RDR04) and  
the Receive Data Register Full (RDRF) flag bit of the SSR5 is set. The data then has to be read by the CPU.  
By doing so, the RDRF flag is cleared. If reception interrupt is enabled (RIE = 1), the interrupt is simply  
generated by the RDRF.  
Note: Only when the RDRF flag bit is set and no errors have occurred the Reception Data Register (RDR04)  
contains valid data.  
■ Stop Bit, Error Detection, and Parity  
For transmission, 1 or 2 stop bits can be selected. During reception, if selected, both stop bits are checked, to  
set the reception bus idle (RBI) flag of ECCR04 correctly after the second stop bit.  
In mode 0 parity, overrun, and framing errors can be detected.  
In mode 1, overrun and framing errors can be detected. Parity is not provided.  
By setting the Parity Enable (PEN) bit of the Serial Control Register (SCR04) the USART provides parity  
calculation (during transmission) and parity detection and check (during reception) in mode 0 (and mode 2 if  
the SSM bit of ECCR04 is set).  
Even parity is set, if the P bit of SCR04 is cleared, odd parity if the flag bit is set. In mode 1, overrun and  
framing errors can be detected. Parity is not provided.  
■ Signal mode NRZ and RZ  
To set USART to the NRZ data format set the ECCR04:INV bit to 0 (initial value).  
RZ data format is set, if the ECCR04:INV bit was set to 1.  
7.2 Operation in Synchronous Mode (Operation Mode 2)  
The clock synchronous transfer method is used for USART operation mode 2 (normal mode).  
■ Transfer data format (standard synchronous)  
In the synchronous mode, 8-bit data is transferred with no start or stop bits if the SSM bit of the Extended  
Communication Control Register (ECCR04) is 0. A special clock signal belongs to the data format in mode 2.  
The figure below illustrates the data format during a transmission in the synchronous operation mode  
Figure 7-2 Transfer data format (operation mode 2).  
Transmission data  
writing  
Reception data sample edge (SCES = 0)  
Transmitting or  
receiving clock  
(normal)  
Mark level  
Mark level  
Mark level  
Transmitting  
clock (SCDE = 1)  
Transmission and  
reception data  
0
1
1
0
1
0
0
1
LSB  
MSB  
Data  
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Chapter 32 USART (LIN / FIFO)  
7.USART Operation  
■ Transfer data format  
In the synchronous mode, 8-bit data is transferred with no start or stop bits if the SSM bit of the Extended  
Communication Control Register (ECCR04) is 0. A special clock signal belongs to the data format in mode 2.  
The figure below illustrates the data format during a transmission in the synchronous operation mode.  
Figure 7-3 SPI Transfer data format (operation mode 2)  
Transmission data  
writing  
Reception data sample edge (SCES = 0)  
Transmitting or  
receiving clock  
(normal)  
Mark level  
Mark level  
Mark level  
Transmitting  
clock (SCDE = 1)  
Transmission and  
reception data  
0
1
1
0
1
0
0
1
LSB  
MSB  
Data  
■ Clock inversion and start/stop bits in mode 2  
If the SCES bit of the Extended Status/Control Register (ESCR04) is set the serial clock is inverted. Therefore  
in slave mode USART samples the data bits at the falling edge of the received serial clock. Note, that in  
master mode if SCES is set the clock signal’s mark level is “0”. If the SSM04 bit of the Extended  
Communication Control Register (ECCR04) is set the data format gets additional start and stop bits like in  
asynchronous mode  
Figure 7-4 Transfer data format with clock inversion  
mark level  
reception or transmission clock  
(SCES = 0, CCO = 0):  
reception or transmission clock  
(SCES = 1, CCO = 0):  
mark level  
data stream (SSM = 1)  
(here: no parity, 1 stop bit)  
ST  
SP  
data frame  
■ Clock Supply  
In clock synchronous (normal) mode (I/O extended serial), the number of the transmission and reception bits  
has to be equal to the number of clock cycles. Note, that if start/stop bits communication is enabled, the  
number of clock cycles has to match with the quantity for the additional start and stop bit(s).  
If the internal clock (dedicated reload counter) is selected, the data receiving synchronous clock is generated  
automatically if data is transmitted.  
If external clock is selected, be sure, that the transmission side of the Transmission Data Register contains  
data and then clock cycles for each bit to sent have to be generated and supplied from outside. The mark level  
("H") must be retained before transmission starts and after it is complete if SCES is “0”.  
Setting the SCDE bit of ECCR delays the transmitting clock signal by 1 CLKP cycle (or half a clock period in  
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Chapter 32 USART (LIN / FIFO)  
7.USART Operation  
SPI). This will make sure, that the transmission data is valid and stable at any falling clock edge. (Necessary, if  
the receiving device samples the data at falling clock edge). This function is disabled when CCO is enabled.  
If the Serial Clock Edge Select (SCES) bit of the ESCR is set, the USARTs clock is inverted and thus samples  
the reception data at the falling clock edge. In this case, the sending device must make sure that the serial  
data is valid at the falling serial clock edge.  
When both the SCES and the SCDE bit are set, data is stable at the rising clock edge, as in the case of SCES  
= SCDE = 0. However, the marker value for idle state is inverted (low).  
If the CCO bit of the Extended Status/Control Register (ESCR5) is set, the serial clock on the SCK5 pin in  
master mode is continuously clocked out. It is strongly recommended to use start and stop bits in this mode to  
signalize the receiver, when a data frame begins and when it stops. Figure 7-5 illustrates this.  
Figure 7-5 Continuous clock output in mode 2  
reception or transmission clock  
(SCES = 0, CCO = 1):  
reception or transmission clock  
(SCES = 1, CCO = 1):  
data stream (SSM = 1)  
(here: no parity, 1 stop bit)  
ST  
SP  
data frame  
■ Data signal mode  
NRZ data format is selected, if ECCR04: INV = 0, otherwise the signal mode for the serial data input and  
output pin is RZ.  
■ Error Detection  
If no Start/Stop bits are selected (ECCR04: SSM = 0) only overrun errors are detected.  
■ Communication  
For initialization of the synchronous mode, the following settings have to be made:  
• Baud Rate Generator Registers (BGR0/1):  
Set the desired reload value for the dedicated Baud Rate Reload Counter  
• Serial Mode Control Register (SMR04):  
• MD1, MD0: "10b" (Mode 2)  
• SCKE:“1” for dedicated Baud Rate Reload Counter  
“0” for external clock input  
• SOE:“1” for transmission and reception  
“0” for reception only  
• Serial Control Register (SCR04):  
• RXE, TXE: one of these flag bit is set to "1"  
• PEN: no parity provided - Value: don’t care  
• P, SBL, A/D: no parity, no stop bit(s), no Address/Data selection - Value: don’t care  
• CL: automatically fixed to 8-bit data - Value: don’t care  
• CRE: "1" (the error flag is cleared for initialization, possible transmission  
or reception will cut off)  
• Serial Status Register (SSR04):  
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Chapter 32 USART (LIN / FIFO)  
7.USART Operation  
• BDS: "0" for LSB first,  
"1" for MSB first  
• RIE: "1" if interrupts are used  
"0" if not  
• TIE: "1" if interrupts are used  
"0" if not  
• Extended Communication Register (ECCR04):  
• SSM: "0" if no start/stop bits are desired (normal)  
"1" for adding start/stop bits (special)  
• MS: "0" for master mode (USART generates the serial clock);  
"1" for slave mode (USART receives serial clock from the master device)  
To start the communication, write data into the Transmission Data Register (TDR04).  
To receive data, disable the Serial Output Enable (SOE) bit of the SMR04 and write dummy data to TDR04.  
(Note)  
Setting continuous clock and start-/stop-bit mode, duplex transception is possible like in  
asynchronous modes.  
7.3 Operation with LIN Function (Operation Mode 3)  
USART can be used either for LIN-Master devices or LIN-Slave devices. For this LIN function a special mode  
(3) is provided. Setting the USART to mode 3, configure the data format to  
8N1-LSB-first format.  
■ USART as LIN master  
In LIN master mode, the master determines the baud rate of the whole sub bus. Therefore, slave devices have  
to synchronize to the master and the desired baud rate remains fixed in master operation after initialization.  
Writing a "1" into the LBR bit of the Extended Status/Communication Register (ECCR04) generates a 13 - 16  
bit times low-level on the SOT04 pin, which is the LIN synchronization break and the start of a LIN message.  
Thereby the TDRE flag of the Serial Status Register (SSR04) goes "0" and is reset to "1" after the break, and  
generates a transmission interrupt for the CPU (if TIE of SSR04 is "1").  
The length of the Synchronization break to be sent can be determined by the LBL1/0 bits of the ESCR04 as  
follows:  
Table 7-2 LIN break length  
Length of  
Break  
LBL1  
LBL0  
0
0
1
1
0
1
0
1
13 Bit times  
14 Bit times  
15 Bit times  
16 Bit times  
The Synch Field can be sent as a simple 0x55-Byte after the LIN break. To prevent a transmission interrupt,  
the 0x55 can be written to the TDR04 just after writing the "1" to the LBR bit, although the TDRE flag is "0".  
The internal transmission shifter waits until the LIN break has finished and shifts the TDR04 value out  
afterwards. In this case no interrupt is generated after the LIN break and before the start bit.  
■ USART as LIN slave  
In LIN slave mode USART has to synchronize to the master’s baud rate. If Reception is disabled (RXE = 0) but  
652  
Chapter 32 USART (LIN / FIFO)  
7.USART Operation  
LIN break Interrupt is enabled (LBIE = 1) USART will generate a reception interrupt, if a synchronization break of  
the LIN master is detected, and indicates it with the LBD flag of the ESCR04. Writing a "0" to this bit clears the  
interrupt. The next step is to analyze the baud rate of the LIN master. The first falling edge of the Synch Field is  
detected by USART. The USART signals it then to the Input Capture Unit (ICU1/5) via a rising edge of an internal  
connection. The fifth falling edge resets the ICU signal. Therefore the ICU has to be configured for the LIN input  
capture (PFR14.4=1, EPFR14.4=1) and its interrupts have to be enabled (ICS4). The values of th ICU counter  
register after the first Interrupt (a) and after the second interrupt (b) yield the BGR value:  
without timer overflow:BGR value = (b - a) / 8 ,  
with timer overflow: BGR value = (max - b + a) / 8 ,  
where max is the timer maximum value at which the overflow occurs.  
The figure 7-6 shows a typical start of a LIN message frame and the behavior of the USART.  
Figure 7-6 USART behavior as slave in LIN mode  
Serial  
clock  
Serial  
Input  
(LIN bus)  
LBR cleared  
by CPU  
LBD  
Internal  
ICU  
Signal  
Synch break (e. g. 14 Tbit)  
Synch field  
■ LIN bus timing  
653  
 
Chapter 32 USART (LIN / FIFO)  
7.USART Operation  
Figure 7-7 LIN bus timing and USART signals  
no clock used  
(calibration frame)  
ICU count  
old serial clock  
new (calibrated) serial clock  
LIN  
bus  
(SIN)  
RXE  
LBD  
(IRQ0)  
LBIE  
Internal  
Signal  
to ICU  
IRQ from  
ICU  
RDRF  
(IRQ0)  
RIE  
Read  
RDR  
by CPU  
Reception Interrupt enable  
LIN break begins  
LIN break detected and Interrupt  
IRQ cleared by CPU (LBD -> 0)  
IRQ from ICU  
IRQ cleared: Begin of Input Capture  
IRQ from ICU  
IRQ cleared: Calculate & set new baud rate  
LBIE disable  
Reception enable  
Edge of Start bit of Identifier byte  
Byte read in RDR  
RDR read by CPU  
7.4 Direct Access to Serial Pins  
USART allows the user to access directly the transmission pin (SOT04) or the reception pin (SIN04).  
■ USART Direct Pin Access  
The USART provides the ability for the user to directly access the serial input or output pin. The software can  
always monitor the incoming serial data by reading the SIOP bit of the ESCR04. If setting the Serial Output  
Pin direct access Enable (SOPE) bit of the ESCR04 the software can force the SOT04 pin to a desired value.  
Note, that this access is only possible, if the transmission shift register is empty (i. e. no transmission activity).  
In LIN mode this function can be used for reading back the own transmission and is used for error handling if  
something is physically wrong with the single-wire LIN-bus.  
(Note)  
Write the desired value to the SIOP pin before enabling the output pin access, to prevent undesired  
peaks. The peaks can occur because SIOP holds the last written value.  
During a Read-Modify-Write operation the SIOP bit returns the actual value of the SOT04 pin in the read cycle  
instead the value of SIN04 during a normal read instruction.  
654  
Chapter 32 USART (LIN / FIFO)  
7.USART Operation  
7.5 Bidirectional Communication Function (Normal Mode)  
In operation mode 0 or 2, normal serial bidirectional communication is available. Select operation mode 0 for  
asynchronous communication and operation mode 2 for synchronous communication.  
■ Bidirectional Communication Function  
The settings shown in figure 7-8 are required to operate USART in normal mode (operation mode 0 or 2).  
Figure 7-8 Settings for USART operation mode 0 and 2  
bit 15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
SCR04,SMR0  
4
PEN  
P
SBL CL  
AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE  
Mode 0  
Mode 2  
x
x
0
0
0
1
0
0
x
0
0
0
0
0
x
SSR04,  
TDR04/RDR04  
Set transmission data (during writing)  
Retain reception data (during reading)  
PE ORE FRE RDRF TDRE BDS RIE TIE  
Mode 0  
Mode 2  
ESCR04,ECCR  
04  
LBIE LBD LBL1 LBL0 SOPE SIOP CCO SECS  
-
LBR MS SCDE SSM BIE  
RBI TBI  
Mode 0  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Mode 2  
Bit is used  
x Bit is not used  
0 / 1 Set bit to 0 / 1  
Bit is used if SSM = 1 (Synchronous start-/stop-bit mode)  
■ Inter-CPU Connection  
As shown in figure 7-9, interconnect two CPUs in USART mode 2  
Figure 7-9 Connection example of USART mode 2 bidirectional communication  
SOT  
SOT  
SIN  
SIN  
Input  
Output  
SCK  
SCK  
CPU-1 (Master)  
CPU-2 (Slave)  
7.6 Master-Slave Communication Function (Multiprocessor Mode)  
USART communication with multiple CPUs connected in master-slave mode is available for both master or  
slave systems.  
655  
   
Chapter 32 USART (LIN / FIFO)  
7.USART Operation  
■ Master-slave Communication Function  
The settings shown in figure 7-10 are required to operate USART in multiprocessor mode (operation mode 1).  
Figure 7-10 Settings for USART operation mode 1  
bit 15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
SCR04,SMR0  
4
PEN  
x
P
SBL CL  
AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE  
Mode 1  
x
0
0
1
x
0
0
0
1
SSR04,  
TDR04/RDR04  
Set transmission data (during writing)  
Retain reception data (during reading)  
PE ORE FRE RDRF TDRE BDS RIE TIE  
x
Mode 1  
Bit is used  
x Bit is not used  
0 / 1 Set bit to 0 / 1  
■ Inter-CPU Connection  
As shown in figure 7-11, a communication system consists of one master CPU and multiple slave CPUs  
connected to two communication lines. USART can be used for the master or slave CPU.  
Figure 7-11 Connection example of USART master-slave communication  
SIN  
SOT  
Master CPU  
SIN SOT  
SIN SOT  
Slave CPU #1  
Slave CPU #2  
■ Function Selection  
Select the operation mode and data transfer mode for master-slave communication as shown in table 7-3.  
656  
   
Chapter 32 USART (LIN / FIFO)  
7.USART Operation  
Table 7-3 Selection of the master-slave communication function  
Operation mode  
Synchro-  
Bit  
direction  
Data  
Parity  
nization  
method  
Stop bit  
Master  
Slave CPU  
CPU  
Address  
AD="1" +  
transmis-  
7- or 8-bit  
sion and  
address  
LSB  
or  
MSB  
first  
Mode 1  
(send AD-  
bit)  
Mode 1  
(receive  
AD-bit)  
reception  
Asyn-  
chronous  
1 or 2  
bits  
None  
Data trans-  
mission  
and recep-  
tion  
AD="0" +  
7- or 8-bit  
data  
■ Communication Procedure  
When the master CPU transmits address data, communication starts. The A/D bit in the address data is set to  
1, and the communication destination slave CPU is selected. Each slave CPU checks the address data using  
a program. When the address data indicates the address assigned to a slave CPU, the slave CPU  
communicates with the master CPU (ordinary data). Figure 7-12 shows a flowchart of master-slave  
communication (multiprocessor mode)  
657  
 
Chapter 32 USART (LIN / FIFO)  
7.USART Operation  
Figure 7-12 Master-slave communication flowchart  
(Master CPU)  
(Slave CPU)  
Start  
Start  
Set operation mode 1  
Set operation mode 1  
Set SIN pin as the  
serial data input pin.  
Set SOT pin as the  
serial data output pin.  
Set SIN pin as the  
serial data input pin.  
Set SOT pin as the  
serial data output pin.  
Set 7 or 8 data bits.  
Set 1 or 2 stop bits.  
Set 7 or 8 data bits.  
Set 1 or 2 stop bits.  
Set TXE = RXE = 1.  
Receive Byte  
Set “1” in AD bit  
Set TXE = RXE = 1.  
Send Slave Address  
Set “0” in AD bit.  
NO  
NO  
Is  
AD bit = 1 ?  
YES  
Does  
Slave Address  
match?  
Communicate with  
slave CPU  
YES  
Is  
Communicate with  
master CPU  
NO  
NO  
communication  
complete?  
YES  
Is  
NO  
communication  
complete?  
Communicate  
with another  
slave CPU?  
YES  
YES  
Set TXE = RXE = 0.  
End  
658  
 
Chapter 32 USART (LIN / FIFO)  
7.USART Operation  
7.7 LIN Communication Function  
USART communication with LIN devices is available for both LIN master or LIN slave systems.  
■ LIN-Master-Slave Communication Function  
The settings shown in the figure below are required to operate USART in LIN communication mode (operation  
mode 3).  
Figure 7-13 Settings for USART  
bit 15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
SCR04,SMR04 PEN  
P
SBL CL  
AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE  
1
Mode 3  
x
x
+
+
x
0
1
x
0
0
0
1
SSR04,  
TDR04/RDR04  
Set transmission data (during writing)  
Retain reception data (during reading)  
PE ORE FRE RDRF TDRE BDS RIE TIE  
Mode 3  
x
+
ESCR04,ECCR  
04  
LBIE LBD LBL1 LBL0 SOPE SIOP CCO SECS  
-
LBR MS SCDE SSM BIE  
RBI TBI  
Mode 3  
x
x
x
x
x
x
x
x
x
Bit is used  
x Bit is not used  
0 / 1 Set bit to 0 / 1  
+ Bit is automatically set to the correct value  
■ LIN device connection  
As shown in the Figure below, a communication system of one LIN-Master device and a LIN-Slave device.  
USART can operate both as LIN-Master or LIN-Slave.  
Figure 7-14 Connection example of a small LIN-Bus system  
SOT  
SIN  
SOT  
SIN  
LIN bus  
Single-Wire-  
Transceiver  
Single-Wire-  
Transceiver  
LIN-Slave  
LIN-Master  
7.8 Sample Flowcharts for USART in LIN Communication (Operation Mode 3)  
This section contains sample flowcharts for USART in LIN communication.  
659  
Chapter 32 USART (LIN / FIFO)  
7.USART Operation  
■ USART as master device  
Figure 7-15 USART LIN master flow chart  
START  
Initialization:  
Set Operat. mode 3  
(8N1 data format)  
TIE = 0, RIE = 0  
Send Message? N  
Y
Send Sleep Mode  
TDR = 0x80  
TIE = 0  
Send Synch Break:  
write "1" to ECCR:  
LBR; TIE = 1;  
Send Synch Field:  
TDR = 0x55  
Send Wake up signal  
RIE = 0  
Wake up  
Y
TIE = 1  
from CPU?  
TDR = 0x80  
TDRE = 1  
Transm. Interrupt  
N
RIE = 1  
Send Sleep Mode?  
Y
N
0x00, 0x80,  
or 0xC0  
received?  
RIE = 0  
Y
N
Send Identify Field:  
TDR = Id  
TIE = 1  
Write data to slave  
TIE = 0  
Y
Errors occurred?  
N
Write to slave?  
N
Y
TIE = 0  
RIE = 1  
Error Handler  
Read data from slave  
RIE = 0  
660  
Chapter 32 USART (LIN / FIFO)  
7.USART Operation  
■ USART as slave device  
Figure 7-16 USART LIN slave flow chart (part1)  
START  
A
B
Initialization:  
Set Operat. mode 3  
(8N1 data format)  
Slave address  
match?  
N
N
C
Y
Errors occurred? Y  
N
E
C
RIE = 0; LBIE = 1; RXE = 0  
Master wants to  
send data?  
waiting  
(slave  
action)  
Y
LBD = 1  
LIN break interrupt  
Awaiting message  
Receive data  
+ checksum  
RIE = 0  
from LIN master.  
Write "0" to LBD  
to clear interrupt.  
TIE = 1  
Calculate  
checksum  
Send data  
Enable ICU inter-  
rupt (both edges)  
0x80 received?  
(sleep mode)  
Y
S
(on next page)  
N
TIE = 0  
waiting  
(slave  
action)  
ICU -  
Interrupt  
B
C
Errors occurred?  
N
Y
Read ICU value  
and store it.  
Clear Interrupt.  
waiting  
(slave  
action)  
C
ICU -  
Interrupt  
Read ICU value.  
Calculate new  
baud rate.  
E
Set it to Reload  
Counter.  
Clear Interrupt.  
Wait for Bus Idle  
BIE = 1  
Error handler  
waiting  
(slave  
action)  
C
RBI -  
Interrupt  
Receive Indenti-  
fier.  
RIE = 1,  
RXE = 1  
A
continued next page  
661  
Chapter 32 USART (LIN / FIFO)  
7.USART Operation  
Figure 7-17 USART LIN slave flow chart (part 2)  
continuation from previous page  
S
Send Wake up signal  
RIE = 0  
Wake up  
Y
TIE = 1  
from CPU?  
TDR = 0x80  
N
TIE = 0  
RIE = 1  
0x00, 0x80,  
or 0xC0  
received?  
RIE = 0  
N
C
Y
662  
Chapter 32 USART (LIN / FIFO)  
8.Notes on using USART  
8. Notes on using USART  
Notes on using USART are given below.  
■ Enabling Operations  
In USART, the control register (SCR04) has TXE (transmission) and RXE (reception) operation enable bits.  
Both, transmission and reception operations, must be enabled before the transfer starts because they have  
been disabled as the default value (initial value).  
In single wire bus systems like ISO 9141 (LIN bus system) because of the mono directional communication it  
is highly recommended to enable only one of these two bits at the same time. Because of the automatic  
reception the sent data by USART would be received by USART too.  
■ Cancelling Transfers  
Transfers can be cancelled by clearing their operation enable bits TXE / RXE. If RXE is cleared during an  
ongoing reception, then the USART state machines must be reset (set UPCL=1). If a transmission is ongoing  
at the same time, it will be cancelled too! In this case, wait until TDRE=1 and TBI=1 before setting UPCL.  
■ Communication Mode Setting  
Set the communication mode while the system is not operating. If the mode is changed during transmission or  
reception, the transmission or reception is stopped and possible data will be get lost.  
■ Transmission Interrupt Enabling Timing  
The default (initial value) of the transmission data empty flag bit (SSR04: TDRE) is “1” (no transmission data  
and transmission data write enable state). A transmission interrupt request is generated as soon as the  
transmission interrupt request is enabled (SSR04: TIE=1). Be sure to set the TIE flag to “1” after setting the  
transmission data to avoid an immediate interrupt.  
■ Using LIN operation mode 3  
The LIN features are also available in mode 0 (transmitting, receiving break), but using mode 3 sets the  
USART data format automatically to LIN format (8N1, LSB first). So, break features are appliable for bus  
protocols other than LIN in mode 0. Note, that the transmission time of the break is variable, but the detection  
is specified to a minimum of 11 serial bit times.  
■ Changing Operation Settings  
It is strongly recommended to reset USART after changing operation settings.  
Particularly in synchronous mode 2 if (for example) start-/stop-bits are added to or removed from the data  
format.  
<Caution>  
If settings in the Serial Mode Register (SMR04) are desired, it is not useful to set the UPCL bit at the same  
time to reset USART. The correct operation settings are not guaranteed in this case. Thus it is recommended  
to set the bits of the SMR04 and then to set them again plus the UPCL bit.  
■ LIN slave settings  
To initiate USART for LIN slave make sure to set the baudrate before receiving the first LIN synchronization  
break. This is needed to detect safely the minimum of 11 bit times of a LIN synch break.  
■ Software compatibility  
Although USART is similar to older Fujitsu-UARTs it is not software compatible to them. The programming  
models may be the same, but the structure of the registers differ. Furthermore the setting of the baud rate is  
now determined by a reload value instead of selecting a preset value.  
■ Bus Idle Function  
The Bus Idle Function cannot be used in synchronous mode 2.  
663  
 
Chapter 32 USART (LIN / FIFO)  
8.Notes on using USART  
■ Baud Rate Detection Using the Input Capture Units  
The USARTs provide the signal LSYN that can be connected to the ICU so that LSYN’s pulse length can be  
measured to derive the baud rate. The connection of the LSYN signals to the ICUs is controlled by the Port 14  
function register PFR and EPFR :  
Pin IN4  
10  
11  
S
ICU4  
IN  
LIN-UART4  
PFR[4] & EPFR[4]  
PFR[5] & EPFR[5]  
LSYN  
LSYN  
FREE RUN TIMER4  
ICU5  
Pin IN5  
10  
11  
S
IN  
LIN-UART5  
If the PFR bit equals ‘1’ and the EPFR bits equals ‘0’, the ICU is connected to its corresponding input pin IN.  
If the PFR bit equals ‘1’ and the EPFR bits equals ‘1’, the USARTs are connected to the ICU.  
The user has to take into account that:  
• ICU4 and ICU5 share one free running timer (prescaler).  
664  
Chapter 33 I2C Controller  
1.Overview  
2
Chapter 33 I C Controller  
1. Overview  
2
2
The I C interface is a serial I/O port supporting the Inter IC bus, operating as a master/slave device on the I C  
bus.  
■ Features  
• Master/slave transmitting and receiving functions  
• Arbitration function  
• Clock synchronization function  
• General call addressing support  
• Transfer direction detection function  
• Repeated start condition generation and detection function  
• Bus error detection function  
• 7 bit addressing as master and slave  
• 10 bit addressing as master and slave  
• Possibility to give the interface a seven and a ten bit slave address  
• Acknowledging upon slave address reception can be disabled (Master-only operation)  
• Address masking to give interface several slave addresses (in 7 and 10 bit mode)  
• Up to 400 kBit transfer rate  
• Possibility to use built-in noise filters for SDA and SCL  
• Can receive data at 400 kBit if R-Bus-Clock is higher than 6 MHz regardless of prescaler setting  
• Can generate MCU interrupts on transmission and bus error events  
• Supports being slowed down by a slave on bit and byte level  
2
The I C interface does not support SCL clock stretching on bit level since it can receive the full 400 kBit  
datarate if the R-Bus-Clock (CLKP) is higher than 6 MHz regardless of the prescaler setting. However, clock  
stretching on byte level is performed since SCL is pulled low during an interrupt (INT=‘1’ in IBCR2 register).  
665  
   
Chapter 33 I2C Controller  
1.Overview  
■ Block Diagram  
ICCR  
EN  
I2C enable  
R-Bus Clock (CLKP)  
ICCR  
CS4  
CS3  
CS2  
CS1  
CS0  
Clock Divider 1  
2 3 4 5 ... 32  
5
5
Clock Selector  
Sync  
Clock Divider 2 (by 12)  
SCL Duty Cycle Generator  
Shift Clock Generator  
IBSR  
BB  
Bus busy  
Repeated start  
Last Bit  
RSC  
LRB  
TRX  
ADT  
AL  
Bus Observer  
Bus Error  
Send/receive  
Address Data  
Arbitration Loss Detector  
ICCR  
NSF  
enable  
IBCR  
BER  
BEIE  
INTE  
INT  
SCL  
SDA  
Noise  
Filter  
MCU  
IRQ  
Interrupt Request  
SCL  
SDA  
IBCR  
SCC  
Start  
Start-Stop Condition  
Generator  
Master  
MSS  
ACK  
ACK enable  
GC-ACK enable  
ACK Generator  
GCAA  
8
IDAR  
8
IBSR  
AAS  
Slave  
General call  
GCA  
ISMK  
ENSB  
enable 7 bit mode  
Slave Address  
Comparator  
ITMK  
ENTB  
RAL  
enable 10 bit mode  
received ad. length  
10  
7
10  
7
ITBA  
ITMK  
ISBA  
ISMK  
10  
10  
7
7
666  
Chapter 33 I2C Controller  
2.I2C Interface Registers  
2
2. I C Interface Registers  
2
This section describes the function of the I C interface registers in detail.  
■ Bus Control Register (IBCR0)  
⇐ Bit no.  
Bus control register  
Address : 0000D0H  
15  
14  
13  
12  
11  
10  
9
8
IBCR0  
BER BEIE SCC MSS ACK GCAA INTE INT  
(R/W) (R/W) (W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
■ Bus Status Register (IBSR0)  
⇐ Bit no.  
7
6
5
4
3
2
1
0
Bus status register  
Address : 0000D1H  
IBSR0  
BB RSC AL LRB TRX AAS GCA ADT  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
■ Ten Bit slave Address register (ITBA0)  
⇐ Bit no.  
Ten Bit Address high byte  
Address : 0000D2H  
15  
---  
14  
---  
13  
---  
12  
---  
11  
---  
10  
---  
9
8
ITBAH0  
TA9 TA8  
(-)  
(0)  
(-)  
(0)  
(-)  
(0)  
(-)  
(0)  
(-)  
(0)  
(-) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(0)  
(0)  
(0)  
⇐ Bit no.  
7
6
5
4
3
2
1
0
Ten Bit Address low byte  
Address : 0000D3H  
ITBAL0  
TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
9
(0)  
8
Default value⇒  
■ Ten bit slave address MasK register (ITMK0)  
⇐ Bit no.  
Ten Bit Address Mask high byte  
Address : 0000D4H  
15  
14  
13  
---  
12  
---  
11  
---  
10  
---  
ITMKH0  
ENTB RAL  
TM9 TM8  
(R/W) (R)  
(-)  
(1)  
(-)  
(1)  
(-)  
(1)  
(-) (R/W) (R/W)  
Read/write ⇒  
(0)  
7
(0)  
6
(1)  
(1)  
(1)  
Default value⇒  
⇐ Bit no.  
5
4
3
2
1
0
Ten Bit Address Mask low byte  
Address : 0000D5H  
ITMKL0  
TM7 TM6 TM5 TM4 TM3 TM2 TM1 TM0  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
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■ Seven bit slave address MasK register (ISMK0)  
⇐ Bit no.  
Seven Bit Address Mask register  
Address : 0000D6H  
15  
14  
13  
12  
11  
10  
9
8
ISMK0  
ENSB SM6 SM5 SM4 SM3 SM2 SM1 SM0  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(0)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
■ Seven Bit slave Address register (ISBA0)  
⇐ Bit no.  
7
6
5
4
3
2
1
0
Seven Bit Address register  
Address : 0000D7H  
ISBA0  
---  
SA6 SA5 SA4 SA3 SA2 SA1 SA0  
(-) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
■ Data Register (IDAR0)  
⇐ Bit no.  
7
6
5
4
3
2
1
0
Data register  
Address : 0000D9H  
IDAR0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
■ Clock control register (ICCR0)  
⇐ Bit no.  
Clock Control register  
Address : 0000DAH  
15  
---  
14  
13  
12  
11  
10  
9
8
ICCR0  
NSF EN CS4 CS3 CS2 CS1 CS0  
(-) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(0) (0) (0) (1) (1) (1) (1) (1)  
Read/write ⇒  
Default value⇒  
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2.1 Bus Control Register (IBCR0)  
The bus control register (IBCR0) has the following functions:  
• Interrupt enabling flags  
• Interrupt generation flag  
• Bus error detection flag  
• Repeated start condition generation  
• Master / slave mode selection  
• General call acknowledge generation enabling  
• Data byte acknowledge generation enabling  
Write access to this register should only occur while the INT=‘1’ or if a transfer is to be started. The user  
should not write to this register during an ongoing transfer since changes to the ACK or GCAA bits could result  
in bus errors. All bits in this register except the BER and the BEIE bit are cleared if the interface is not enabled  
(EN=‘0’ in ICCR0).  
⇐ Bit no.  
Bus control register  
Address : 0000D0H  
15  
14  
13  
12  
11  
10  
9
8
IBCR0  
BER BEIE SCC MSS ACK GCAA INTE INT  
(R/W) (R/W) (W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
[bit 15] BER (Bus ERror)  
This bit is the bus error interrupt flag. It is set by the hardware and cleared by the user. It always reads ‘1’ in a  
Read-Modify-Write access.  
(Write access)  
0
1
Clear bus error interrupt flag.  
No effect.  
(Read access)  
0
1
No bus error detected.  
One of the error conditions described below detected.  
2
When this bit is set, the EN bit in the ICCR0 register is cleared, the I C interface goes to pause status, data  
transfer is interrupted and all bits in the IBSR0 and the IBCR0 registers except BER, BEIE and INT are  
cleared. The BER bit must be cleared before the interface may be reenabled.  
This bit is set to ‘1’ if:  
• start or stop conditions are detected at wrong places: during an address data transfer or during the transfer  
of the bits two to nine (acknowledge bit)  
• a ten bit address header with read access is received before a ten bit write access  
• a stop condition is detected while the interface is in master mode  
The detection of the first two of the above conditions is enabled after the reception of the first stop condition to  
prevent false bus error reports if the interface is being enabled during an ongoing transfer.  
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[bit 14] BEIE (Bus Error Interrupt Enable)  
This bit enables the bus error interrupt. It can only be changed by the user.  
0
1
Bus error interrupt disabled.  
Bus error interrupt enabled.  
Setting this bit to ‘1’ enables MCU interrupt generation when the BER bit is set to ‘1’.  
[bit 13] SCC (Start Condition Continue)  
This bit is used to generate a repeated start condition. It is write only - it always reads ‘0’.  
0
1
No effect.  
Generate repeated start condition during master transfer.  
A repeated start condition is generated if a ‘1’ is written to this bit while an interrupt in master mode (MSS=‘1’  
and INT=‘1’) and the INT bit is cleared automatically.  
[bit 12] MSS (Master Slave Select)  
This is the master/slave mode selection bit. It can only be set by the user, but it can be cleared by the user  
and the hardware.  
0
1
Go to slave mode.  
Go to master mode, generate start condition and send address data byte in  
IDAR0 register.  
It is cleared if an arbitration loss event occurs during master sending.  
If a ‘0’ is written to it during a master interrupt (MSS=‘1’ and INT=‘1’), the INT bit is cleared automatically, a  
stop condition will be generated and the data transfer ends. Note that the MSS bit is reset immediately, the  
generation of the stop condition can be checked by polling the BB bit in the IBSR0 register.  
If a ‘1’ is written to it while the bus is idle (MSS=‘0’ and BB=‘0’), a start condition is generated and the contents  
of the IDAR0 register (which should be address data) is sent.  
If a ‘1’ is written to the MSS bit while the bus is in use (BB=‘1’ and TRX=‘0’ in IBSR2; MSS=‘0’ in IBCR0), the  
interface waits until the bus is free and then starts sending.  
If the interface is addressed as slave with write access (data reception) in the meantime, it will start sending  
after the transfer ended and the bus is free again. If the interface is sending data as slave in the meantime  
(AAS=‘1’ and TRX=‘1’ in IBSR0), it will not start sending data if the bus is free again. It is important to check  
whether the interface was addressed as slave (AAS=‘1’ in IBSR0), sent the data byte successfully (MSS=‘1’ in  
IBCR0) or failed to send the data byte (AL=‘1’ in IBSR0) at the next interrupt!  
[bit 11] ACK (ACKnowledge)  
This is the acknowledge generation on data byte reception enable bit. It can only be changed by the user.  
0
1
The interface will not acknowledge on data byte reception.  
The interface will acknowledge on data byte reception.  
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This bit is not valid when receiving address bytes in slave mode - if the interface detects its 7 or 10 bit slave  
address, it will acknowledge if the corresponding enable bit (ENTB in ITMK0 or ENSB in ISMK0) is set.  
Write access to this bit should occur during an interrupt (INT=‘1’) or if the bus is idle (BB=‘0’ in the IBSR0  
register) write access to this bit is only possible if the interface is enabled (EN=‘1’ in ICCR0) and if there is no  
bus error (BER=‘0’ in IBCR0).  
[bit 10] GCAA (General Call Address Acknowledge)  
This bit enables acknowledge generation when a general call address is received. It can only be changed by  
the user.  
0
1
The interface will not acknowledge on general call address byte reception.  
The interface will acknowledge on general call address byte reception.  
Write access to this bit should occur during an interrupt (INT=‘1’) or if the bus is idle (BB=‘0’ in IBSR0 register)  
write access to this bit is only possible if the interface is enabled (EN=‘1’ in ICCR0) and if there is no bus error  
(BER=‘0’ in IBCR0).  
[bit 9] INTE (INTerrupt Enable)  
This bit enables the MCU interrupt generation. It can only be changed by the user.  
0
1
Interrupt disabled.  
Interrupt enabled.  
Setting this bit to ‘1’ enables MCU interrupt generation when the INT bit is set to ‘1’ (by the hardware).  
[bit 8]: INT (INTerrupt)  
This bit is the transfer end interrupt request flag. It is changed by the hardware and can be cleared by the  
user. It always reads ‘1’ in a Read-Modify-Write access.  
(Write access)  
0
1
Clear transfer end interrupt request flag.  
No effect.  
(Read access)  
0
Transfer not ended or not involved in current transfer or bus is idle.  
Set at the end of a 1-byte data transfer or reception including the acknowledge bit  
under the following conditions:  
• Device is bus master.  
• Device is addressed as slave.  
1
• General call address received.  
• Arbitration loss occurred.  
Set at the end of an address data reception (after first byte if seven bit address  
received, after second byte if ten bit address received) including the acknowledge  
bit if the device is addressed as slave.  
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While this bit is ‘1’ the SCL line will hold an ‘L’ level signal. Writing ‘0’ to this bit clears the setting, releases the  
SCL line, and executes transfer of the next byte or a repeated start or stop condition is generated.  
Additionally, this bit is cleared if a ‘1’ is written to the SCC bit or the MSS bit is being cleared.  
SCC, MSS And INT Bit Competition  
Simultaneously writing to the SCC, MSS and INT bits causes a competition to transfer the next byte, to  
generate a repeated start condition or to generate a stop condition. In these cases the order of priority is as  
follows:  
Next byte transfer and stop condition generation.  
When ‘0’ is written to the INT bit and ‘0’ is written to the MSS bit, the MSS bit takes priority and a stop  
condition is generated.  
Next byte transfer and start condition generation.  
When ‘0’ is written to the INT bit and ‘1’ is written to the SCC bit, the SCC bit takes priority. A repeated start  
condition is generated and the content of the IDAR0 register is sent.  
Repeated start condition generation and stop condition generation.  
When ‘1’ is written to the SCC bit and ‘0’ to the MSS bit, the MSS bit clearing takes priority. A stop condition is  
generated and the interface enters slave mode.  
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2.2 Bus Status Register (IBSR0)  
The bus status register (IBSR0) has the following functions:  
• Bus busy detection  
• Repeated start condition detection  
• Arbitration loss detection  
• Acknowledge detection  
• Data transfer direction indication  
• Addressing as slave detection  
• General call address detection  
• Address data transfer detection  
This register is read-only, all bits are controlled by the hardware. All bits are cleared if the interface is not  
enabled (EN=‘0’ in ICCR0).  
⇐ Bit no.  
7
6
5
4
3
2
1
0
Bus status register  
Address : 0000D1H  
IBSR0  
BB RSC AL LRB TRX AAS GCA ADT  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
[bit 7] BB (Bus Busy)  
2
This bit indicates the status of the I C bus.  
0
1
Stop condition detected (bus idle).  
Start condition detected (bus in use).  
This bit is set to ‘1’ if a start condition is detected. It is reset upon a stop condition.  
[bit 6] RSC (Repeated Start Condition)  
This bit indicates detection of a repeated start condition.  
0
1
Repeated start condition not detected.  
Bus in use, repeated start condition detected.  
This bit is cleared at the end of an address data transfer (ADT=‘0’) or detection of a stop condition.  
[bit 5] AL (Arbitration Loss)  
This bit indicates an arbitration loss.  
0
1
No arbitration loss detected.  
Arbitration loss occurred during master sending.  
This bit is cleared by writing ‘0’ to the INT bit or by writing ‘1’ to the MSS bit in the IBCR0 register.  
An arbitration loss occurs if:  
• the data sent does not match the data read on the SDA line at the rising SCL edge  
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• a repeated start condition is generated by another master in the first bit of a data byte  
• the interface could not generate a start or stop condition because another slave pulled the SCL line low  
before  
[bit 4] LRB (Last Received Bit)  
This bit is used to store the acknowledge message from the receiving side at the transmitter side.  
0
1
Receiver acknowledged.  
Receiver did not acknowledge.  
It is changed by the hardware upon reception of bit 9 (acknowledge bit) and is also cleared by a start or stop  
condition.  
[bit 3] TRX (Transferring data)  
This bit indicates data sending operation during data transfer.  
0
1
Not transmitting data.  
Transmitting data.  
It is set to ‘1’:  
• if a start condition was generated in master mode at the end of a first byte transfer and read access as slave  
or sending data as master  
It is set to ‘0’ if:  
• the bus is idle (BB=‘0’ in IBCR0)  
• an arbitration loss occured  
• a ‘1’ is written to the SCC bit during master interrupt (MSS=‘1’ and INT=‘1’)  
• the MSS bit is cleared during master interrupt (MSS=‘1’ and INT=‘1’)  
• the interface is in slave mode and the last transferred byte was not acknowledged  
• the interface is in slave mode and it is receiving data  
• the interface is in master mode and is reading data from a slave  
[bit 2] AAS (Addressed As Slave)  
This bit indicates detection of a slave addressing.  
0
1
Not addressed as slave.  
Addressed as slave.  
This bit is cleared by a (repeated-) start or stop condition. It is set if the interface detects its seven and/or ten  
bit slave address.  
[bit 1] GCA (General Call Address)  
This bit indicates detection of a general call address (0x00).  
0
General call address not received as slave.  
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1
General call address received as slave.  
This bit is cleared by a (repeated-) start or stop condition.  
[bit 0] ADT (Address Data Transfer)  
This bit indicates the detection of an address data transfer.  
0
1
Incoming data is not address data (or bus is not in use).  
Incoming data is address data.  
This bit is set to ‘1’ by a start condition. It is cleared after the second byte if a ten bit slave address header with  
write access is detected, else it is cleared after the first byte.  
"After" the first/second byte means:  
• a ‘0’ is written to the MSS bit during a master interrupt (MSS=‘1’ and INT=‘1’ in IBCR0)  
• a ‘1’ is written to the SCC bit during a master interrupt (MSS=‘1’ and INT=‘1’ in IBCR0)  
• the INT bit is being cleared  
• the beginning of every byte transfer if the interface is not involved in the current transfer as master or slave  
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2.3 Ten Bit Slave Address Register (ITBA0)  
This register (ITBAH0 / ITBAL0) designates the ten bit slave address.  
Write access to this register is only possible if the interface is disabled (EN=‘0’ in ICCR0).  
⇐ Bit no.  
Ten Bit Address high byte  
Address : 0000D2H  
15  
---  
14  
---  
13  
---  
12  
---  
11  
---  
10  
---  
9
8
ITBAH0  
TA9 TA8  
(-)  
(0)  
(-)  
(0)  
(-)  
(0)  
(-)  
(0)  
(-)  
(0)  
(-) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(0)  
(0)  
(0)  
⇐ Bit no.  
7
6
5
4
3
2
1
0
Ten Bit Address low byte  
Address : 0000D3H  
ITBAL0  
TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
[bit 15] - [bit 10] Not used.  
These bits always read ‘0’.  
[bit 9] - [bit 0] TBA - Ten Bit slave Address (TA9-TA0)  
When address data is received in slave mode, it is compared to the ITBA0 register if the ten bit address is  
enabled (ENTB=‘1’ in the ITMK0 register). An acknowledge is sent to the master after reception of a ten bit  
1
address header with write access . Then, the second incoming byte is compared to the ITBA0 register. If a  
match is detected, an acknowledge signal is sent to the master device and the AAS bit is set.  
2
Additionally, the interface acknowledges upon the the reception of a ten bit header with read access after a  
repeated start conditon.  
All bits of the slave address may be masked using the ITMK0 register. The received ten bit slave address is  
written back to the ITBA0 register, it is only valid while the AAS bit in the IBSR0 register is ‘1’.  
1.  
2.  
Note: a ten bit header (write access) consists of the following bit sequence: 11110, TA9, TA8, 0.  
Note: a ten bit header (read access) consists of the following bit sequence: 11110, TA9, TA8, 1.  
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2.4 Ten Bit Address Mask Register (ITMK0)  
This register contains the ten bit slave address mask and the ten bit slave address enable bit.  
⇐ Bit no.  
Ten Bit Address Mask high byte  
Address : 0000D4H  
15  
14  
13  
---  
12  
---  
11  
---  
10  
---  
9
8
ITMKH0  
ENTB RAL  
TM9 TM8  
(R/W) (R)  
(-)  
(1)  
(-)  
(1)  
(-)  
(1)  
(-) (R/W) (R/W)  
Read/write ⇒  
(0)  
7
(0)  
6
(1)  
(1)  
(1)  
Default value⇒  
⇐ Bit no.  
5
4
3
2
1
0
Ten Bit Address Mask low byte  
Address : 0000D5H  
ITMKL0  
TM7 TM6 TM5 TM4 TM3 TM2 TM1 TM0  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
[bit 15] ENTB - EnaBle Ten Bit slave address  
This bit enables the ten bit slave address (and the acknowleding upon its reception). Write access to this bit is  
only possible if the interface is disabled (EN=‘0’ in ICCR0).  
0
1
Ten bit slave address disabled.  
Ten bit slave address enabled.  
[bit 14] RAL - Received slave Address Length  
This bit indicates whether the interface was addressed as a seven or ten bit slave. It is read-only.  
0
1
Addressed as seven bit slave.  
Addressed as ten bit slave.  
This bit can be used to determine whether the interface was addressed as a seven or ten bit slave if both  
slave addresses are enabled (ENTB=‘1’ and ENSB=‘1’). Its contents is only valid if the AAS bit in the IBSR0  
register is ‘1’. This bit is also reset if the interface is disabled (EN=‘0’ in ICCR0).  
[bit 13] - [bit 10] Not used.  
These bits always read ‘1’.  
[bit 9] - [bit 0] TMK - Ten bit slave address MasK (TM9-TM0).  
This register is used to mask the ten bit slave address of the interface. Write access to these bits is only  
possible if the interface is disabled (EN=‘0’ in ICCR0).  
0
1
Bit is not used in slave address comparision.  
Bit is used in slave address comparision.  
This can be used to make the interface acknowledge on multiple ten bit slave addresses. Only the bits set to  
‘1’ in this register are used in the ten bit slave address comparision. The received slave address is written  
back to the ITBA0 register and thus may be determined by reading the ITBA0 register if the AAS bit in the  
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IBSR0 register is ‘1’.  
Note: If the address mask is changed after the interface had been enabled, the slave address should also be  
set again since it could have been overwritten by a previously received slave address.  
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2.5 Seven Bit Slave Address Register (ISBA0)  
This register designates the seven bit slave address.  
Write access to this register is only possible if the interface is disabled (EN=‘0’ in ICCR0).  
⇐ Bit no.  
7
6
5
4
3
2
1
0
Seven Bit Address register  
Address : 0000D7H  
ISBA0  
---  
SA6 SA5 SA4 SA3 SA2 SA1 SA0  
(-) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(0) (0) (0) (0) (0) (0) (0) (0)  
Read/write ⇒  
Default value⇒  
[bit 7] Not used.  
This bit always reads ‘0’.  
[bit 6] - [bit 0] Seven Bit slave Address (SA6-SA0)  
When address data is received in slave mode, it is compared to the ISBA0 register if the seven bit address is  
enabled (ENSB=‘1’ in the ISMK0 register). If a match is detected, an acknowledge signal is sent to the master  
device and the AAS bit is set.  
All bits of the slave address may be masked using the ISMK0 register. The received seven bit slave address is  
written back to the ISBA0 register, it is only valid while the AAS bit in the IBSR0 register is ‘1’.  
The interface does not compare the contents of this register to the incoming data if a ten bit header or a  
general call is received.  
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2.6 Seven Bit Slave Address Mask Register (ISMK0)  
This register contains the seven bit slave address mask and the seven bit mode enable bit. Write access to  
this register is only possible if the interface is disabled (EN=‘0’ in ICCR0).  
⇐ Bit no.  
Seven Bit Address Mask register  
Address : 0000D6H  
15  
14  
13  
12  
11  
10  
9
8
ISMK0  
ENSB SM6 SM5 SM4 SM3 SM2 SM1 SM0  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(0)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
[bit 15] ENSB - EnaBle Seven Bit slave address  
This bit enables the seven bit slave address (and the acknowleding upon its reception).  
0
1
Seven bit slave address disabled.  
Seven bit slave address enabled.  
[bit 14] - [bit 8] SMK - Seven bit slave address MasK (SM6-SM0)  
This register is used to mask the seven bit slave address of the interface.  
0
1
Bit is not used in slave address comparision.  
Bit is used in slave address comparision.  
This can be used to make the interface acknowledge on multiple seven bit slave addresses. Only the bits set  
to ‘1’ in this register are used in the seven bit slave address comparision. The received slave address is  
written back to the ISBA0 register and thus may be determined by reading the ISBA0 register if the AAS bit in  
the IBSR0 register is ‘1’.  
Note: If the address mask is changed after the interface had been enabled, the slave address should also be  
set again since it could have been overwritten by a previously received slave address.  
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2.7 Data Register (IDAR0)  
⇐ Bit no.  
7
6
5
4
3
2
1
0
Data register  
Address : 0000D9H  
IDAR0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(0) (0) (0) (0) (0) (0) (0) (0)  
Read/write ⇒  
Default value⇒  
[bit 15] - [bit 8] Not used.  
These bits always read ‘0’.  
[bit 7] - [bit 0] Data bits (D7-D0)  
The data register is used in serial data transfer, and transfers data MSB-first. This register is double buffered  
on the write side, so that when the bus is in use (BB=‘1’), write data can be loaded to the register for serial  
transfer. The data byte is loaded into the internal transfer register if the INT bit in the IBCR0 register is being  
cleared or the bus is idle (BB=‘0’ in IBSR0). In a read access, the internal register is read directly, therefore  
received data values in this register are only valid if INT=‘1’ in the IBCR2 register.  
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2.8 Clock Control Register (ICCR0)  
The clock control register (ICCR0) has the following functions:  
• Enable IO pad noise filters  
2
• Enable I C interface operation  
• Setting the serial clock frequency  
⇐ Bit no.  
Clock Control register  
Address : 0000DAH  
15  
---  
14  
13  
12  
11  
10  
9
8
ICCR0  
NSF EN CS4 CS3 CS2 CS1 CS0  
(-) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(0) (0) (0) (1) (1) (1) (1) (1)  
Read/write ⇒  
Default value⇒  
[bit 15] Not used.  
This bit always reads ‘0’.  
[bit 14] IO pad NoiSe Filter enable.  
This bit enables the noise filters built into the SDA and SCL IO pads.  
The noise filter will suppress single spikes with a pulse width of 0 ns (minimum) and between 1 and 1.5 cycles  
2
of R-bus (maximum). The maximum depends on the phase relationship between I C signals (SDA, SCL) and  
R-bus clock.  
It should be set to ‘1’ if the interface is transmitting or receiving at datarates above 100 kBit.  
[bit 13] EN (ENable)  
2
This bit enables the I C interface operation. It can only be set by the user but may be cleared by the user and  
the hardware.  
0
1
Interface disabled.  
Interface enabled.  
When this bit is set to ‘0’ all bits in the IBSR0 register and IBCR0 register (except the BER and BEIE bits) are  
2
cleared, the module is disabled and the I C lines are left open. It is cleared by the hardware if a bus error  
occurs (BER=‘1’ in IBCR0).  
Warning: The interface immediately stops transmitting or receiving if is it is being disabled. This might leave  
2
the I C bus in an undesired state!  
[bit 12] - [bit 8] CS4-0 (Clock preScaler)  
These bits select the serial bitrate. They can only be changed if the interface is disabled (EN=‘0’) or the EN bit  
is being cleared in the same write access.  
It is determined by the following formula:  
φ
n*12 + 18  
Noise filter disabled  
n>0; φ : R-Bus clock CLKP (set by DIVR0 register)  
Bitrate =  
682  
Chapter 33 I2C Controller  
2.I2C Interface Registers  
Noise filter enabled  
n>0; φ : R-Bus clock CLKP (set by DIVR0 register)  
(+1): Unaccurancy caused by noise filter operation  
φ
n*12 + 19 (+1)  
Bitrate =  
(Note)  
Because of the noise filter (depending on relationship between external signal and internal clock it  
will cause different delays ) the divider in the second formula can vary between (12n + 19) and (12n  
+ 20).  
■ Prescaler settings:  
Table 2-1 I2C Prescaler Settings  
n
CS4  
CS3  
CS2  
CS1  
CS0  
1
2
3
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
...  
31  
1
1
1
1
1
Do not use n=0 prescaler setting, it violates SDA/SCL timings!  
The table below shows SCL frequency measurement results for the most common R-bus clock settings and  
the recommended related pre-scaler settings for 100 Kbit and 400 Kbit operation.  
R-Bus Clock  
(CLKP) [MHz]  
100 kBit (Noise filter disabled)  
400 kBit (Noise filter enabled)  
n
Bitrate [kBit]  
n
Bitrate [kBit]  
32  
24  
16  
8
5
387.5  
352.5  
372  
19  
12  
6
97.5  
98  
4
2
1
89  
266.5  
It should be noted that the measured values have been determined by examining the last 8 cycles of a  
transfer. This was done because the first cycle of all address or data transfers is longer than the other cycles.  
To be more precise: In case of an address transfer this first cycle is 3 prescaler periods longer than the other  
cycles, in case of a data transfer it is 4 prescaler periods longer (see figure below).  
683  
Chapter 33 I2C Controller  
2.I2C Interface Registers  
■ SCL Waveforms  
Figure 2-1 SCL Waveforms  
6
7
7
5
5
7
7
5
5
7
9
9
Address sending  
Data sending  
Time unit: Prescaler cycles  
Figure 2-1 shows the SCL waveform for sending of address and data bits. The timings given in  
the figure are prescaler periods (e.g. ‘9’ means 9 times the prescaler count based on the R-Bus  
clock). The timings in the figure are only valid if no other device on the I2C bus influences the  
SCL timing.  
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Chapter 33 I2C Controller  
3.I2C Interface Operation  
2
3. I C Interface Operation  
2
The I C bus executes communication using two bi-directional bus lines, the serial data line (SDA) and serial  
2
clock line (SCL). The I C interface has two open-drain I/O pins (SDA/SCL) corresponding to these lines,  
enabling wired logic applications.  
■ Start Conditions  
2
When the bus is free (BB=‘0’ in IBSR0, MSS=‘0’ in IBCR2), writing ‘1’ to the MSS bit places the I C interface in  
master mode and generates a start condition.  
If a ‘1’ is written to it while the bus is idle (MSS=‘0’ and BB=‘0’), a start condition is generated and the contents  
of the IDAR0 register (which should be address data) is sent.  
Repeated start conditions can be generated by writing ‘1’ to the SCC bit when in bus master mode and  
interrupt status (MSS=‘1’ and INT=‘1’ in IBCR0).  
If a ‘1’ is written to the MSS bit while the bus is in use (BB=‘1’ and TRX=‘0’ in IBSR0; MSS=‘0’and INT=‘0’in  
IBCR0), the interface waits until the bus is free and then starts sending.  
If the interface is addressed as slave with write access (data reception) in the meantime, it will start sending  
after the transfer ended and the bus is free again. If the interface is sending data as slave in the meantime, it  
will not start sending data if the bus of free again. It is important to check whether the interface was addressed  
as slave (MSS=‘0’ in IBCR0 and AAS=‘1’ in IBSR0), sent the data byte successfully (MSS=‘1’ in IBCR0) or  
failed to send the data byte (AL=‘1’ in IBSR0) at the next interrupt!  
Writing ‘1’ to the MSS bit or SCC bit in any other situation has no significance.  
■ Stop Conditions  
Writing ‘0’ to the MSS bit in master mode (MSS=‘1’ and INT=‘1’ in IBCR0) generates a stop condition and  
places the device in slave mode. Writing ‘0’ to the MSS bit in any other situation has no significance.  
After clearing the MSS bit, the interface tries to generate a stop condition which might fail if another master  
pulls the SCL line low before the stop condition has been generated. This will generate an interrupt after the  
next byte has been transferred!  
■ Slave Address Detection  
In slave mode, after a start condition is generated the BB is set to ‘1’ and data sent from the master device is  
received into the IDAR0 register.  
After the reception of eight bits, the contents of the IDAR2 register is compared to the ISBA register using the  
bit mask stored in ISMK0 if the ENSB bit in the ISMK0 register is ‘1’. If a match results, the AAS bit is set to ‘1’  
and an acknowledge signal is sent to the master. Then bit 0 of the received data (bit 0 of the IDAR0 register)  
is inverted and stored in the TRX bit.  
If the ENTB bit in the ITMK0 register is ‘1’ and a ten bit address header (11110, TA1, TA0, write access) is  
detected, the interface sends an acknowledge signal to the master and stores the inverted last data bit in the  
TRX register. No interrupt is generated. Then, the next transferred byte is compared (using the bit mask stored  
in ITMK0) to the lower byte of the ITBA0 register. If a match is found, an acknowledge signal is sent to the  
master, the AAS bit is set and an interrupt is generated.  
If the interface was addressed as slave and detects a repeated start condition, the AAS bit is set after  
reception of the ten bit address header (11110, TA1, TA0, read access) and an interrupt is generated.  
Since there are seperate registers for the ten and seven bit address and their bitmasks, it is possible to make  
the interface acknowledge on both addresses by setting the ENSB (in ISMK0) and ENTB (in ITMK0) bits. The  
received slave address length (seven or ten bit) may be determined by reading the RAL bit in the ITMK0  
register (this bit is valid if the AAS bit is set only).  
It is also possible to give the interface no slave address by setting both bits to ‘0’ if it is only used as a master.  
All slave address bits may be masked with their corresponding mask register (ITMK0 or ISMK0).  
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Chapter 33 I2C Controller  
3.I2C Interface Operation  
■ Slave Address Masking  
Only the bits set to ‘1’ in the mask registers (ITMK0 / ISMK0) are used for address comparision, all other bits  
are ignored. The received slave address can be read from the ITBA0 (if ten bit address received, RAL=‘1’) or  
ISBA0 (if seven bit address received, RAL=‘0’) register if the AAS bit in the IBSR0 register is ‘1’.  
If the bitmasks are cleared, the interface can be used as a bus monitor since it will always be addressed as  
slave. Note that this is not a real bus monitor because it acknowledges upon any slave address reception,  
even if there is no other slave listening.  
■ Addressing Slaves  
In master mode, after a start condition is generated the BB and TRX bits are set to ‘1’ and the contents of the  
IDAR0 register is sent in MSB first order. After address data is sent and an acknowledge signal was received  
from the slave device, bit 0 of the sent data (bit 0 of the IDAR0 register after sending) is inverted and stored in  
the TRX bit. Acknowledgement by the slave may be checked using the LRB bit in the IBSR0 register. This  
procedure also applies to a repeated start condition.  
In order to address a ten bit slave for write access, two bytes have to be sent. The first one is the ten bit  
address header which consists of the bitsequence ‘1 1 1 1 0 A9 A8 0’, it is followed by the second byte  
containing the lower eight bits of the ten bit slave address (A7 - A0).  
A ten bit slave is accessed for reading by sending the above byte sequence and generating a repeated start  
condition (SCC bit in IBCR0) followed by a ten bit address header with read access (1 1 1 1 0 A9 A8 1).  
Summary of the address data bytes:  
7 bit slave, write access: Start condition - A6 A5 A4 A3 A2 A1 A0 0.  
7 bit slave, read access: Start condition - A6 A5 A4 A3 A2 A1 A0 1.  
10 bit slave, write access: Start condition - 1 1 1 1 0 A9 A8 0 - A7 A6 A5 A4 A3 A2 A1 A0.  
10 bit slave, read access: Start condition - 1 1 1 1 0 A9 A8 1 - A7 A6 A5 A4 A3 A2 A1 A0 - repeated start -  
1 1 1 1 0 A9 A8 1.  
■ Arbitration  
During sending in master mode, if another master device is sending data at the same time, arbitration is  
performed. If a device is sending the data value ‘1’ and the data on the SDA line has an ‘L’ level value, the  
device is considered to have lost arbitration, and the AL bit is set to ‘1.’ Also, the AL bit is set to ‘1’ if a start  
conditon is detected at the first bit of a data byte but the interface did not want to generate one or the  
generation of a start or stop condition failed by some reason.  
Arbitration loss detection clears both the MSS and TRX bit and immediately places the device in slave mode  
so it is able to acknowledge if its own slave address is being sent.  
■ Acknowledgement  
Acknowledge bits are sent from the receiver to the transmitter. The ACK bit in the IBCR0 register can be used  
to select whether to send an acknowledgment when data bytes are received.  
When data is send in slave mode (read access from another master), if no acknowledgement is received from  
the master, the TRX bit is set to ‘0’ and the device goes to receiving mode. This enables the master to  
generate a stop condition as soon as the slave has released the SCL line.  
In master mode, acknowledgement by the slave may be checked by reading the LRB bit in the IBSR0 register.  
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Chapter 33 I2C Controller  
4.Programming Flow Charts  
4. Programming Flow Charts  
■ Example Of Slave Addressing And Sending Data  
Addressing a 7 bit slave  
Sending data  
Start  
Start  
Address slave for write  
Clear BER bit (if set);  
Enable Interface EN:=1;  
IDAR0 := Data Byte;  
INT := 0  
IDAR0 := sl.address<<1+RW;  
MSS := 1; INT := 0  
N
INT=1?  
N
INT=1?  
Y
Y
Y
BER=1?  
N
Bus error  
Y
BER=1?  
N
Restart  
transfer  
Check  
if AAS  
Y
Restart  
transfer  
Check  
if AAS  
AL=1?  
N
Y
AL=1?  
N
ACK?  
(LRB=0?)  
N
ACK?  
N
(LRB=0?)  
Y
Y
Last byte  
transferred?  
Y
Ready to send data  
N
Slave did not ACK  
Generate  
repeated start  
or stop condition  
Transfer End  
Generate  
repeated start or  
stop condition  
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Chapter 33 I2C Controller  
4.Programming Flow Charts  
■ Example Of Receiving Data  
Start  
Address slave for read  
Clear ACK bit in IBCR0 if it’s the  
last byte to read from slave;  
INT := 0  
N
INT=1?  
Y
Y
Bus error  
reenable IF  
BER=1?  
N
Last byte  
N
transferred?  
Y
Transfer End  
Generate  
repeated start or  
stop condition  
688  
Chapter 33 I2C Controller  
4.Programming Flow Charts  
■ Example Of An Interrupt Handler  
Start  
Interrupt  
from other  
module  
N
Y
INT=1?  
Y
received  
Bus error  
reenable IF  
BER=1?  
Y
GCA=1?  
N
General call  
as slave  
N
Y
AAS=1?  
Arbitration  
Y
Y
Y
Y
lost  
AL=1?  
AL=1?  
N
Restart  
transfer  
Transfer failed  
N
remember to retry  
Slave did  
not ACK  
Generate  
stop or  
repeated  
start  
LRB=1?  
N
Y
ADT=1?  
New data transfer  
starts at next INT  
Change ACK bit  
if necessary  
N
TRX=1?  
N
Y
TRX=1?  
N
Read received byte  
Put next byte to be  
sent in IDAR0  
register  
Read received byte  
Put next byte  
from IDAR0 register  
Change ACK bit if  
necessary  
from IDAR0 register to be sent in  
Change ACK bit if  
necessary  
IDAR0 register  
or clear MSS  
Clear INT bit  
End ISR  
689  
Chapter 33 I2C Controller  
4.Programming Flow Charts  
690  
Chapter 34 CAN Controller  
1.Overview  
Chapter 34 CAN Controller  
1. Overview  
The CAN performs communication according to the CAN protocol version 2.0 part A and B. The bit rate can be  
programmed to values up to 1MBit/s. For the connection to the physical layer additional transceiver hardware  
is required.  
■ The CAN implements the following features:  
• Supports CAN protocol version 2.0 part A and B  
• Bit rates up to 1 MBit/s  
• 32 (up to 128) Message Objects  
• Each Message Object has its own identifier mask  
• Programmable FIFO mode (concatenation of Message Objects)  
• Maskable interrupt  
• Disabled Automatic Retransmission mode for Time Triggered CAN applications  
• Programmable loop-back mode for self-test operation  
■ This chapter uses the following terms and abbreviations.  
Term  
CAN  
BSP  
Meaning  
Controller Area Network  
Bit Stream Processor  
Bit Timing Logic  
BTL  
CRC  
DLC  
Cyclic Redundancy Check  
Data Length Code  
Error Management Logic  
Finite State Machine  
Time Triggered CAN  
EML  
FSM  
TTCAN  
691  
   
Chapter 34 CAN Controller  
2.Register Description  
2. Register Description  
This section lists the CAN registers and describes the function of each register in detail.  
2.1 Programmer’s Model  
The CAN module allocates an address space of 256 bytes (64 words). The CAN registers can be accessed  
from the CPU in byte, halfword and word.  
The two sets of interface registers (IF1 and IF2) control the CPU access to the Message RAM. They buffer the  
data to be transferred to and from the RAM, avoiding conflicts between CPU accesses and message  
reception/transmission.  
The data registers (IF1 Data and IF2 Data) are doubled in the address map, ordered both in little endian byte  
and big endian byte.  
If several CAN modules are present on a device then they are located linear in the address space with a  
constant offset of 256 bytes (64 words). The base address of each CAN module is given by the following  
table:  
• Base-address of CAN0 :0x00C000  
• Base-address of CAN1 :0x00C100  
• Base-address of CAN2 :0x00C200  
• Base-address of CAN3 :0x00C300  
• Base-address of CAN4 :0x00C400  
• Base-address of CAN5 :0x00C500  
Register  
Address  
Note  
+0  
+1  
+2  
+3  
Base-addr +  
0x00  
Control Register  
Status Register  
bit[15:8]  
reserved  
bit[7:0]  
bit[15:8]  
reserved  
bit[7:0]  
see descr. CTRLR  
Reset: 0x01  
see descr. STATR  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Base-addr +  
0x04  
Error Counter  
Bit Timing Register  
Error Counter is read  
only.  
bit[15:8]  
bit[7:0]  
TEC[7:0]  
bit[15:8]  
TSeg2[2:0],TSeg1[3:0]  
Reset: 0x23  
bit[7:0]  
Bit Timing Register  
is write enabled by  
CCE  
RP,REC[6:0]  
Reset: 0x00  
SJW[1:0],BRP[5:0]  
Reset: 0x01  
Reset: 0x00  
Base-addr +  
0x08  
Interrupt Register  
Test Register  
Interrupt Register is  
read only.  
bit[15:8]  
Int-Id[15:8]  
Reset: 0x00  
bit[7:0]  
Int-Id[7:0]  
Reset: 0x00  
bit[15:8]  
reserved  
bit[7:0]  
Test Register is write  
enabled by Test.  
r signifies the actual  
value of the  
see descr. TESTR  
Reset: 0x00  
Reset: 0x00 &  
0br0000000  
CAN_RX pin.  
Base-addr +  
0x0C  
BRP Extension Register  
Reserved  
BRP Extension Reg-  
ister is write enabled  
by CCE.  
bit[15:8]  
reserved  
bit[7:0]  
BRP[3:0]  
bit[15:8]  
reserved  
bit[7:0]  
reserved  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
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Chapter 34 CAN Controller  
2.Register Description  
Register  
Address  
Note  
+0  
+1  
+2  
+3  
Base-addr +  
0x10  
IF1 Command Request  
IF1 Command Mask  
bit[15:8]  
Busy  
bit[7:0]  
bit[15:8]  
bit[7:0]  
Mess. No. [5:0]  
Reset: 0x01  
reserved  
see descr. IF1CMSK  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Base-addr +  
0x14  
IF1 Mask 2  
IF1 Mask 1  
bit[15:8]  
bit[7:0]  
bit[15:8]  
Msk[15:8]  
Reset: 0xFF  
bit[7:0]  
Msk[7:0]  
MXtd,MDir,Msk[28:24]  
Reset: 0xFF  
Msk[23:16]  
Reset: 0xFF  
Reset: 0xFF  
Base-addr +  
0x18  
IF1 Arbitration 2  
IF1 Arbitration 1  
bit[15:8]  
MsgVal,Xtd,Dir,ID[28:24]  
Reset: 0x00  
bit[7:0]  
ID[23:16]  
bit[15:8]  
ID[15:8]  
bit[7:0]  
ID[7:0]  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Base-addr +  
0x1C  
IF1 Message Control  
Reserved  
bit[15:8]  
see descr. IF1MCTR  
Reset: 0x00  
bit[7:0]  
bit[15:8]  
reserved  
bit[7:0]  
reserved  
see descr. IF1MCTR  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Base-addr +  
0x20  
IF1 Data A1  
IF1 Data A2  
IF1 Data B2  
IF1 Data A1  
IF1 Data B1  
Big Endian byte  
ordering.  
bit[7:0]  
Data[0]  
bit[15:8]  
Data[1]  
bit[7:0]  
Data[2]  
bit[15:8]  
Data[3]  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Base-addr +  
0x24  
IF1 Data B1  
Big Endian byte  
ordering.  
bit[7:0]  
Data[4]  
bit[15:8]  
Data[5]  
bit[7:0]  
Data[6]  
bit[15:8]  
Data[7]  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Base-addr +  
0x30  
IF1 Data A2  
Little Endian byte  
ordering.  
bit[15:8]  
Data[3]  
bit[7:0]  
Data[2]  
bit[15:8]  
Data[1]  
bit[7:0]  
Data[0]  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Base-addr +  
0x34  
IF1 Data B2  
Little Endian byte  
ordering.  
bit[15:8]  
Data[7]  
bit[7:0]  
Data[6]  
bit[15:8]  
Data[5]  
bit[7:0]  
Data[4]  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
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Chapter 34 CAN Controller  
2.Register Description  
Register  
Address  
+0  
Note  
+1  
+2  
+3  
Base-addr +  
0x40  
IF2 Command Request  
IF2 Command Mask  
bit[15:8]  
bit[7:0]  
bit[15:8]  
bit[7:0]  
Busy  
Mess. No. [5:0]  
Reset: 0x01  
reserved  
see descr. IF2CMSK  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Base-addr +  
0x44  
IF2 Mask 2  
IF2 Mask 1  
bit[15:8]  
bit[7:0]  
bit[15:8]  
Msk[15:8]  
Reset: 0xFF  
bit[7:0]  
Msk[7:0]  
MXtd,MDir,Msk[28:24]  
Reset: 0xFF  
Msk[23:16]  
Reset: 0xFF  
Reset: 0xFF  
Base-addr +  
0x48  
IF2 Arbitration 2  
IF2 Arbitration 1  
bit[15:8]  
MsgVal,Xtd,Dir,ID[28:24]  
Reset: 0x00  
bit[7:0]  
ID[23:16]  
bit[15:8]  
ID[15:8]  
bit[7:0]  
ID[7:0]  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Base-addr +  
0x4C  
IF2 Message Control  
Reserved  
bit[15:8]  
see descr. IF2MCTR  
Reset: 0x00  
bit[7:0]  
bit[7:0]  
reserved  
bit[15:8]  
reserved  
see descr. IF2MCTR  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Base-addr +  
0x50  
IF2 Data A1  
IF2 Data A2  
IF2 Data B2  
IF2 Data A1  
IF2 Data B1  
Big Endian byte  
ordering.  
bit[7:0]  
Data[0]  
bit[15:8]  
Data[1]  
bit[7:0]  
Data[2]  
bit[15:8]  
Data[3]  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Base-addr +  
0x54  
IF2 Data B1  
Big Endian byte  
ordering.  
bit[7:0]  
Data[4]  
bit[15:8]  
Data[5]  
bit[7:0]  
Data[6]  
bit[15:8]  
Data[7]  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Base-addr +  
0x60  
IF2 Data A2  
Little Endian byte  
ordering.  
bit[15:8]  
Data[3]  
bit[7:0]  
Data[2]  
bit[15:8]  
Data[1]  
bit[7:0]  
Data[0]  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Base-addr +  
0x64  
IF2 Data B2  
Little Endian byte  
ordering.  
bit[15:8]  
Data[7]  
bit[7:0]  
Data[6]  
bit[15:8]  
Data[5]  
bit[7:0]  
Data[4]  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
Reset: 0x00  
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Chapter 34 CAN Controller  
2.Register Description  
Register  
Address  
Note  
+0  
+1  
+2  
+3  
Base-addr +  
0x80  
Transmission Request Register 2  
Transmission Request Register 1  
Transmission  
Request Register is  
read only.  
bit[15:8]  
bit[7:0]  
bit[15:8]  
bit[7:0]  
TxRqst[32-25]  
Reset: 0x00  
TxRqst[24-17]  
Reset: 0x00  
TxRqst[16-9]  
Reset: 0x00  
TxRqst[8-1]  
Reset: 0x00  
Base-addr +  
0x84  
Reserved ( >32..128 Message buffer)  
Base-addr +  
0x90  
New Data 2  
New Data 1  
New Data is read  
only.  
bit[15:8]  
bit[7:0]  
bit[15:8]  
bit[7:0]  
NewDat[32-25]  
Reset: 0x00  
NewDat[24-17]  
Reset: 0x00  
NewDat[16-9]  
Reset: 0x00  
NewDat[8-1]  
Reset: 0x00  
Base-addr +  
0x94  
Reserved ( >32..128 Message buffer)  
Base-addr +  
0xA0  
Interrupt Pending 2  
bit[15:8]  
Interrupt Pending 1  
bit[15:8]  
Interrupt Pending is  
read only.  
bit[7:0]  
bit[7:0]  
IntPnd[32-25]  
Reset: 0x00  
IntPnd[24-17]  
Reset: 0x00  
IntPnd[16-9]  
Reset: 0x00  
IntPnd[8-1]  
Reset: 0x00  
Base-addr +  
0xA4  
Reserved ( >32..128 Message buffer)  
Base-addr +  
0xB0  
Message Valid 2  
Message Valid 1  
Message Valid is  
read only.  
bit[15:8]  
bit[7:0]  
bit[15:8]  
bit[7:0]  
MsgVal[32-25]  
Reset: 0x00  
MsgVal[24-17]  
Reset: 0x00  
MsgVal[16-9]  
Reset: 0x00  
MsgVal[8-1]  
Reset: 0x00  
Base-addr +  
0xB4  
Reserved ( >32..128 Message buffer)  
Figure 2-1 CAN Register Summary  
Register  
Address  
Note  
+0  
+1  
+2  
+3  
0x04C0  
CANPRE  
bit[3:0]  
CANCKD  
-
-
-
-
-
-
-
-
CAN Prescaler  
bit[5:0]  
CANCKD[5:0]  
Reset: 0x00  
CANPRE[3:0]  
Reset: 0x00  
Figure 2-2 CAN Prescaler Register Summary  
2.2 Hardware Reset Description  
After hardware reset, the registers of the CAN hold the values described in Figure 2-1.  
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Chapter 34 CAN Controller  
2.Register Description  
Additionally the busoff state is reset and the output CAN_TX is set to recessive(HIGH). The value 0x0001 (Init  
= ‘1’) in the CAN Control Register enables the software initialisation. The CAN does not influence the CAN bus  
until the CPU resets Init to ‘0’.  
The data stored in the Message RAM is not affected by a hardware reset. After power-on, the contents of the  
Message RAM is undefined.  
2.3 CAN Protocol Related Registers  
These registers are related to the CAN protocol controller in the CAN Core. They control the operating modes  
and the configuration of the CAN bit timing and provide status information.  
■ CAN Control Register (CTRLR)  
⇐ Bit no.  
CTRLRH  
CAN Control Register high byte  
Address : Base + 0x00H  
15  
14  
13  
12  
11  
10  
9
8
res  
res  
res  
res  
res  
res  
res  
res  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
⇐ Bit no.  
7
6
5
4
3
2
1
0
CAN Control Register low byte  
Address : Base + 0x01H  
CTRLRL  
Test CCE DAR res  
EIE SIE  
IE  
Init  
(R/W) (R/W) (R/W) (R) (R/W) (R/W) (R/W) (R/W)  
(0) (0) (0) (0) (0) (0) (0) (1)  
Read/write ⇒  
Default value⇒  
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Chapter 34 CAN Controller  
2.Register Description  
■ Function of the CAN Control Register (CTRLR)  
[bit15 - bit8]  
Reserved Bits  
[bit7]  
Test  
Test Mode Enable  
0
1
Normal Operation.  
Test Mode.  
[bit6]  
[bit5]  
CCE  
Configuration Change Enable  
0
1
The CPU has no write access to the Bit Timing Register.  
The CPU has write access to the Bit Timing Register (while Init = 1)  
DAR  
Disable Automatic Retransmission  
0
1
Automatic Retransmission of disturbed messages enabled.  
Automatic Retransmission disabled.  
[bit4]  
[bit3]  
res  
EIE  
reserved bit  
Error Interrupt Enable  
0
1
Disabled - No Error Status Interrupt will be generated.  
Enabled - A change in the bits BOff or EWarn in the Status Register will generate  
an interrupt.  
[bit2]  
[bit1]  
[bit0]  
SIE  
Status Change Interrupt Enable  
0
1
Disabled - No Status Change Interrupt will be generated.  
Enabled - An interrupt will be generated when a message transfer is successfully  
completed or a CAN bus error is detected.  
IE  
Module Interrupt Enable  
0
1
Disabled - Module Interrupt is always inactive.  
Enabled - Interrupts will set the internal request. The request remains active until  
all pending interrupts are processed.  
Init  
Initialization  
0
1
Normal Operation  
Initialization is started.  
(Note)  
The busoff recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting or  
resetting Init. If the device goes busoff, it will set Init of its own accord, stopping all bus activities.  
Once Init has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle  
(129 * 11 consecutive recessive bits) before resuming normal operations. At the end of the busoff  
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Chapter 34 CAN Controller  
2.Register Description  
recovery sequence, the Error Management Counters will be reset.  
(Note)  
During the waiting time after the resetting of Init, each time a sequence of 11 recessive bits has  
been monitored, a Bit0Error code is written to the Status Register, enabling the CPU to readily  
check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the  
proceeding of the busoff recovery sequence.  
■ Status Register (STATR)  
⇐ Bit no.  
Status Register high byte  
15  
14  
13  
12  
11  
10  
9
8
STATRH  
res  
res  
res  
res  
res  
res  
res  
res  
Address : Base + 0x02H  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
⇐ Bit no.  
7
6
5
4
3
2
1
0
Status Register low byte  
Address : Base + 0x03H  
STATRL  
BOff EWarnEPassRxOK TxOK  
LEC  
(R)  
(0)  
(R)  
(0)  
(R) (R/W) (R/W) (R/W) (R/W) (R/W)  
(0) (0) (0) (0) (0) (0)  
Read/write ⇒  
Default value⇒  
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Chapter 34 CAN Controller  
2.Register Description  
■ Function of the Status Register (STATR)  
[bit15 - bit8]  
Reserved Bits  
[bit7]  
BOff  
Busoff Status  
0
1
The CAN module is not busoff.  
The CAN module is in busoff state.  
[bit6]  
EWarn  
Warning Status  
0
1
oth error counters are below the error warning limit of 96.  
At least one of the error counters in the EML has reached the error warning limit  
of 96.  
[bit5]  
[bit4]  
EPass  
Error Passive  
0
1
The CAN Core is error active.  
The CAN Core is in the error passive state as defined in the CANSpecification.  
RxOk  
Received a Message Successfully  
0
Since this bit was last reset by the CPU, no message has been successfully  
received. This bit is never reset by the CAN Core.  
1
Since this bit was last reset (to zero) by the CPU, a message has been success-  
fully received (independent of the result of acceptance)  
[bit3]  
TxOk  
Transmitted a Message Successfully  
0
Since this bit was reset by the CPU, no message has been successfully trans-  
mitted. This bit is never reset by the CAN Core.  
1
Since this bit was last reset by the CPU, a message has been successfully (error  
free and acknowledged by at least one other node) transmitted.  
[bit2 - bit0]  
LEC  
Last Error Code (Type of the last error to occur on the CAN bus)  
No Error  
0
1
Stuff Error  
More than 5 equal bits in a sequence have occurred in a part of a  
received message where this is not allowed.  
2
3
Form Error  
AckError  
A fixed format part of a received frame has the wrong format.  
The message this CAN Core transmitted was not acknowledged by  
another node.  
Bit1Error  
4
During the transmission of a message (with the exception of the arbi-  
tration field), the device wanted to send a recessive level (bit of logi-  
cal value ‘1’), but the monitored bus value was dominant.  
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Chapter 34 CAN Controller  
2.Register Description  
5
Bit0Error  
During the transmission of a message (or acknowledge bit or active  
error flag, or overload flag), the device wanted to send a dominant  
level (data or identifier bit logical value ‘0’), but the monitored Bus  
value was recessive. During busoff recovery this status is set each  
time a sequence of 11 recessive bits has been monitored. This  
enables the CPU to monitor the proceeding of the busoff recovery  
sequence (indicating the bus is not stuck at dominant or continuously  
disturbed).  
CRCError  
unused  
6
7
The CRC check sum was incorrect in the message received, the  
CRC received for an incoming message does not match with the cal-  
culated CRC for the received data.  
When the LEC shows the value ‘7’, no CAN bus event was detected  
since the CPU wrote this value to the LEC.  
The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be  
cleared to ‘0’ when a message has been transferred (reception or transmission) without error. The unused  
code ‘7’ may be written by the CPU to check for updates.  
■ Status Interrupts  
A Status Interrupt is generated by bits BOff and EWarn (Error Interrupt) or by RxOk, TxOk, and LEC (Status  
Change Interrupt) assumed that the corresponding enable bits in the CAN Control Register are set. A change  
of bit EPass or a write to RxOk, TxOk,or LEC will never generate a Status Interrupt.  
Reading the Status Register will clear the Status Interrupt value (8000h) in the Interrupt Register, if it is  
pending.  
■ Error Counter (ERRCNT)  
⇐ Bit no.  
ERRCNTH  
Error Counter high byte  
Address : Base + 0x04H  
15  
14  
13  
12  
11  
10  
9
8
RP  
REC6-0  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
⇐ Bit no.  
ERRCNTL  
7
6
5
4
3
2
1
0
Error Counter low byte  
Address : Base + 0x05H  
TEC7-0  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
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Chapter 34 CAN Controller  
2.Register Description  
■ Function of the Error Counter (ERRCNT)  
[bit15]  
RP  
Receive Error Passive  
0
1
The Receive Error Counter is below the error passive level.  
The Receive Error Counter has reached the error passive level as defined in the  
CAN Specification.  
[bit14 - bit8] REC6-0 Receive Error Counter  
Actual state of the Receive Error Counter. Values between 0 and 127.  
TEC7-0 Transmit Error Counter  
Actual state of the Transmit Error Counter. Values between 0 and 255.  
[bit7 - bit0]  
■ Bit Timing Register (BTR)  
⇐ Bit no.  
Bit Timimg Register high byte  
Address : Base + 0x06H  
15  
14  
13  
12  
11  
10  
9
8
BTRH  
res  
TSeg2  
TSeg1  
(R) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(0)  
(0)  
(1)  
(0)  
(0)  
(0)  
(1)  
(1)  
⇐ Bit no.  
7
6
5
4
3
2
1
0
Bit Timing Register low byte  
Address : Base + 0x07H  
BTRL  
SJW  
BRP  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W  
)
Read/write ⇒  
Default value⇒  
(0) (0) (0) (0) (0) (0) (0) (1)  
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Chapter 34 CAN Controller  
2.Register Description  
■ Function of the Bit Timing Register (BTR)  
[bit15]  
res  
Reserved bit  
[bit14 - bit12]  
TSeg2  
The time segment after the sample point  
0x0-0x7  
Valid values for TSeg2 are [ 0 … 7 ]. The actual interpretation by the hard-  
ware of this value is such that one more than the value programmed here is  
used.  
[bit11 - bit8]  
TSeg1  
The time segment before the sample point  
0x01-0x0F Valid values for TSeg1 are [ 1 … 15 ]. The actual interpretation by the hard-  
ware of this value is such that one more than the value programmed here is  
used  
[bit7 - 6]  
SJW  
(Re)Synchronisation Jump Width  
0x0-0x3  
Valid programmed values are 0-3. The actual interpretation by the hardware  
of this value is such that one more than the value programmed here is used.  
[bit5 - bit0]  
BRP  
Baud Rate Prescaler  
0x00-0x3F The value by which the oscillator frequency is divided for generating the bit  
time quanta. The bit time is built up from a multiple of this quanta. Valid val-  
ues for the Baud Rate Prescaler are[0 … 63]. The actual interpretation by  
the hardware of this value is such that one more than the value programmed  
here is used.  
(Note)  
With a module clock CAN_CLK of 8 MHz, the reset value of 0x2301 configures the CAN for a bit  
rate of 500 kBit/s. The registers are only writable if bits CCE and Init in the CAN Control Register are  
set.  
■ Test Register (TESTR)  
⇐ Bit no.  
TESTRH  
Test Register high byte  
15  
14  
13  
12  
11  
10  
9
8
res  
res  
res  
res  
res  
res  
res  
res  
Address : Base + 0x0AH  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
⇐ Bit no.  
7
6
5
4
3
2
1
0
Test Register low byte  
Address : Base + 0x0BH  
TESTRL  
Rx  
Tx1 Tx0 LBack Silent Basic res res  
(R) (R/W) (R/W) (R/W) (R/W) (R/W) (R)  
(0) (0) (0) (0) (0) (0) (0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
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Chapter 34 CAN Controller  
2.Register Description  
■ Function of the Test Register (TESTR)  
[bit15-bit8]  
[bit7]  
res  
Rx  
Reserved bits  
Monitors the actual value of the CAN_RX Pin  
0
1
The CAN bus is dominant (CAN_RX = ‘0’).  
The CAN bus is recessive (CAN_RX = ‘1’).  
[bit6-bit5]  
Tx1-0  
Control of CAN_TX pin  
00  
01  
10  
11  
Reset value, CAN_TX is controlled by the CAN Core.  
Sample Point can be monitored at CAN_TX pin.  
CAN_TX pin drives a dominant (‘0’) value.  
CAN_TX pin drives a recessive (‘1’) value.  
[bit4]  
[bit3]  
LBack  
Loop Back Mode  
0
1
Loop Back Mode is disabled.  
Loop Back Mode is enabled.  
Silent  
Silent Mode  
0
1
Normal operation.  
The module is in Silent Mode.  
[bit2]  
Basic  
Basic Mode  
0
1
Basic Mode disabled.  
IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.  
[bit1-bit0]  
res  
Reserved Bits  
Write access to the Test Register is enabled by setting bit Test in the CAN Control Register. The different test  
functions may be combined, but Tx1-0 /= “00” disturbs message transfer.  
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Chapter 34 CAN Controller  
2.Register Description  
■ BRP Extension Register (BRPER)  
⇐ Bit no.  
BRPERH  
BRP Extension Register high byte  
Address : Base + 0x0CH  
15  
14  
13  
12  
11  
10  
9
8
res  
res  
res  
res  
res  
res  
res  
res  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
⇐ Bit no.  
BRPERL  
7
6
5
4
3
2
1
0
BRP Extension Register low byte  
Address : Base + 0x0DH  
res  
res  
res res  
BRPE  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R) (R/W) (R/W) (R/W) (R/W)  
(0) (0) (0) (0) (0)  
Read/write ⇒  
Default value⇒  
■ Function of the BRP Extension Register (BRPER)  
[bit15-bit4]  
res  
Reserved Bits  
[bit3-bit0]  
BRPE  
Baud Rate Prescaler Extension  
0x00-  
0x0F  
By programming BRPE the Baud Rate Prescaler can be extended to values up to  
1023. The actual interpretation by the hardware is that one more than the value pro-  
grammed by BRPE (MSBs) and BRP (LSBs) is used.  
2.4 Message Interface Register Sets  
There are two sets of Interface Registers which are used to control the CPU access to the Message RAM. The  
Interface Registers avoid conflicts between CPU access to the Message RAM and CAN message reception  
and transmission by buffering the data to be transferred. A complete Message Object (see chapter 2.5  
“Message Object in the Message Memory” on page 711.) or parts of the Message Object may be transferred  
between the Message RAM and the IFx Message Buffer registers (see chapter 2.4 “Message Interface  
Register Sets” on page 704.) in one single transfer.  
The function of the two interface register sets is identical (except for test mode Basic). They can be used the  
way that one set of registers is used for data transfer to the Message RAM while the other set of registers is  
used for the data transfer from the Message RAM, allowing both processes to be interrupted by each other.  
Figure 2-3 gives an overview of the two Interface Register sets.  
Each set of Interface Registers consists of Message Buffer Registers controlled by their own Command  
Registers. The Command Mask Register specifies the direction of the data transfer and which parts of a  
Message Object will be transferred. The Command Request Register is used to select a Message Object in  
the Message RAM as target or source for the transfer and to start the action specified in the Command Mask  
Register.  
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Chapter 34 CAN Controller  
2.Register Description  
Address  
IF1 Register Set  
Address  
IF2 Register Set  
CAN Base + 0x10  
CAN Base + 0x12  
CAN Base + 0x14  
IF1 Command Request  
IF1 Command Mask  
IF1 Mask 2  
CAN Base + 0x40  
CAN Base + 0x42  
CAN Base + 0x44  
IF2 Command Request  
IF2 Command Mask  
IF2 Mask 2  
CAN Base + 0x16  
IF1 Mask 1  
CAN Base + 0x46  
IF2 Mask 1  
CAN Base + 0x18  
CAN Base + 0x1A  
CAN Base + 0x1C  
IF1 Arbitration 2  
IF1 Arbitration 1  
CAN Base + 0x48  
CAN Base + 0x4A  
CAN Base + 0x4C  
IF2 Arbitration 2  
IF2 Arbitration 1  
IF1 Message Control  
IF2 Message Control  
CAN Base + 0x20  
CAN Base + 0x32  
CAN Base + 0x50  
CAN Base + 0x62  
IF1 Data A1  
IF2 Data A1  
CAN Base + 0x22  
CAN Base + 0x30  
CAN Base + 0x52  
CAN Base + 0x60  
IF1 Data A2  
IF1 Data B1  
IF1 Data B2  
IF2 Data A2  
IF2 Data B1  
IF2 Data B2  
CAN Base + 0x24  
CAN Base + 0x36  
CAN Base + 0x54  
CAN Base + 0x66  
CAN Base + 0x26  
CAN Base + 0x34  
CAN Base + 0x56  
CAN Base + 0x64  
Figure 2-3 IF1 and IF2 Message Interface Register Sets  
■ IFx Command Request Registers (IFxCREQ)  
A message transfer is started as soon as the CPU has written the message number to the Command Request  
Register. With this write operation the CPU is notified that a transfer is in progress. If a CPU access to the  
CAN happens while the transfer is in progress then this access is delayed until the transfer has finished. After  
3 to 6 CAN_CLK periods, the transfer between the Interface Register and the Message RAM has completed  
and the upcoming CPU access is executed.  
⇐ Bit no.  
IFxCREQH  
IFx Command Request Register high byte  
Address : Base + 0x10H & Base + 0x40H  
15  
14  
13  
12  
11  
10  
9
8
BUSY res  
res  
res  
res  
res  
res  
res  
(R/(W)) (R)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
(0)  
7
(0)  
6
Default value⇒  
IFx Command Request Register low byte  
Address : Base + 0x11H & Base + 0x41H  
⇐ Bit no.  
IFxCREQL  
5
4
3
2
1
0
Message Number  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(0) (0) (0) (0) (0) (0) (0) (1)  
Read/write ⇒  
Default value⇒  
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Chapter 34 CAN Controller  
2.Register Description  
■ Function of the IFx Command Request Registers (IFxCREQ)  
[bit15]  
BUSY  
Busy Flag  
0
1
Reset to zero when read/write action has finished  
Set to one when writing to the IFx Command Request Register  
[bit14-bit8]  
[bit5-bit0]  
res  
Reserved Bits  
Message Number (for 32 message buffer CANs)  
Not a valid Message Number, interpreted as 0x20.  
0x00  
0x01-  
0x20  
Valid Message Number, the Message Object in the Message RAM is selected for  
data transfer.  
0x21-  
0x3F  
Not a valid Message Number, interpreted as 0x01-0x1F.  
[bit7-bit0]  
Message Number (for 128 message buffer CANs)  
Not a valid Message Number, interpreted as 0x80.  
0x00  
0x01-  
0x80  
Valid Message Number, the Message Object in the Message RAM is selected for  
data transfer.  
0x81-  
0xFF  
Not a valid Message Number, interpreted as 0x01-0x7F.  
(Note)  
Note: The Busy Flag can only be used in BASIC mode (see chapter 3.8). When using the Message  
RAM (BASIC=0) the hardware interface controls the access for read and write and this flag is always  
read as ‘0’.  
(Note)  
When a Message Number that is not valid is written into the Command Request Register, the  
Message Number will be transformed into a valid value and that Message Object will be transferred.  
■ IFx Command Mask Register (IFxCMSK)  
The control bits of the IFx Command Mask Register specify the transfer direction and select which of the IFx  
Message Buffer Registers are source or target of the data transfer.  
IFx Command Mask Register high byte  
Address : Base + 0x12H & Base + 0x42H  
15  
14  
13  
12  
11  
10  
9
8
⇐ Bit no.  
IFxCMSKH  
res  
res  
res  
res  
res  
res  
res  
res  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
IFx Command Mask Register low byte  
Address : Base + 0x13H & Base + 0x43H  
1
7
6
4
3
2
0
⇐ Bit no.  
5
TxReq/  
NewDat  
WR/RD  
Data B  
Data A  
Mask  
Arb Control CIP  
IFxCMSKL  
(R/W) (R/W) (R/W) (R/W) (R/W)  
(R/W)  
(0)  
(R/W) (R/W)  
(0) (0)  
Read/write ⇒  
Default value⇒  
(0)  
(0)  
(0)  
(0)  
(0)  
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■ Function of the IFx Command Mask Register (IFxCMSK)  
[bit15-bit8]  
[bit7]  
res  
Reserved Bits  
WR/RD Write / Read  
0
1
Read: Transfer data from the Message Object addressed by the Command Request  
Register into the selected Message Buffer Registers.  
Write: Transfer data from the selected Message Buffer Registers to the Message  
Object addressed by the Command Request Register.  
The other bits of IFx Command Mask Register have different functions depending on the transfer direction :  
• Direction = Write  
[bit6]  
[bit5]  
[bit4]  
Mask  
Access Mask Bits  
0
1
Mask bits unchanged.  
Transfer Identifier Mask + MDir + MXtd to Message Object.  
Arb  
Access Arbitration Bits  
0
1
Arbitration bits unchanged.  
Transfer Identifier + Dir + Xtd + MsgVal to Message Object.  
Control Access Control Bits  
0
1
Control Bits unchanged.  
Transfer Control Bits to Message Object.  
[bit3]  
[bit2]  
CIP  
Clear Interrupt Pending Bit  
When writing to a Message Object, this bit is ignored.  
TxReq/ Access Transmission Request Bit  
NewDat  
0
1
TxRqst bit unchanged  
set TxRqst bit  
[bit1]  
[bit0]  
Data A Access Data Bytes 0-3  
0
1
Data Bytes 0-3 unchanged.  
Transfer Data Bytes 0-3 to Message Object.  
Data B Access Data Bytes 4-7  
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0
1
Data Bytes 4-7 unchanged.  
Transfer Data Bytes 4-7 to Message Object.  
(Note)  
If a transmission is requested by programming bit TxRqst/NewDat in the IFx Command Mask  
Register, bit TxRqst in the IFx Message Control Register will be ignored.  
• Direction = Read  
[bit6]  
[bit5]  
[bit4]  
[bit3]  
[bit2]  
Mask  
Access Mask Bits  
0
1
Mask bits unchanged.  
Transfer Identifier Mask + MDir + MXtd to IFx Message Buffer Register.  
Arb  
Access Arbitration Bits  
0
1
Arbitration bits unchanged.  
Transfer Identifier + Dir + Xtd + MsgVal to IFx Message Buffer Register.  
Control Access Control Bits  
0
1
Control Bits unchanged.  
Transfer Control Bits to IFx Message Buffer Register.  
CIP  
Clear Interrupt Pending Bit  
0
1
IntPnd bit remains unchanged.  
Clear IntPnd bit in the Message Object.  
TxReq/ Access New Data Bit  
NewDat  
0
1
NewDat bit remains unchanged.  
Clear NewDat bit in the Message Object.  
[bit1]  
[bit0]  
Data A Access Data Bytes 0-3  
0
1
Data Bytes 0-3 unchanged.  
Transfer Data Bytes 0-3 to IFx Message Buffer Register.  
Data B Access Data Bytes 4-7  
0
1
Data Bytes 4-7 unchanged.  
Transfer Data Bytes 4-7 to IFx Message Buffer Register.  
(Note)  
A read access to a Message Object can be combined with the reset of the control bits IntPnd and  
NewDat. The values of these bits transferred to the IFx Message Control Register always reflect the  
status before resetting these bits.  
■ IFx Mask Registers (IFxMSK)  
The bits of the Message Buffer registers mirror the Message Objects in the Message RAM.  
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2.Register Description  
⇐ Bit no.  
IFx Mask 2 Register high byte  
15  
14  
13  
12  
11  
10  
9
8
IFxMSK2H  
MXtd MDir res  
Msk28-24  
Address : Base + 0x14H & Base + 0x44H  
(R/W) (R/W) (R) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
⇐ Bit no.  
IFxMSK2L  
7
6
5
4
3
2
1
0
IFx Mask 2 Register low byte  
Address : Base + 0x15H & Base + 0x45H  
Msk23-16  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
(1)  
⇐ Bit no.  
IFxMSK1H  
IFx Mask 1 Register high byte  
15  
14  
13  
12  
11  
10  
9
8
Msk15-8  
Address : Base + 0x16H & Base + 0x46H  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
(1)  
7
(1)  
6
(1)  
5
(1)  
4
(1)  
3
(1)  
2
(1)  
1
(1)  
0
Default value⇒  
⇐ Bit no.  
IFxMSK1L  
IFx Mask 1 Register low byte  
Address : Base + 0x17H & Base + 0x47H  
Msk7-0  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(1) (1) (1) (1) (1) (1) (1) (1)  
Read/write ⇒  
Default value⇒  
■ IFx Arbitration Registers (IFxARB)  
The bits of the Message Buffer registers mirror the Message Objects in the Message RAM.  
⇐ Bit no.  
IFxARB2H  
IFx Arbitration 2 Register high byte  
15  
14  
13  
12  
11  
10  
9
8
MsgVal Xtd  
Dir  
ID28-24  
Address : Base + 0x18H & Base + 0x48H  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
⇐ Bit no.  
7
6
5
4
3
2
1
0
IFx Arbitration 2 Register low byte  
Address : Base + 0x19H & Base + 0x49H  
IFxARB2L  
ID23-16  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(0) (0) (0) (0) (0) (0) (0) (0)  
Read/write ⇒  
Default value⇒  
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2.Register Description  
⇐ Bit no.  
IFxARB1H  
IFx Arbitration 1 Register high byte  
15  
14  
13  
12  
ID15-8  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
11  
10  
9
8
Address : Base + 0x1AH & Base + 0x4AH  
Read/write ⇒  
Default value⇒  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
⇐ Bit no.  
IFxARB1L  
7
6
5
4
3
2
1
0
IFx Arbitration 1 Register low byte  
Address : Base + 0x1BH & Base + 0x4BH  
ID7-0  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(0) (0) (0) (0) (0) (0) (0) (0)  
Read/write ⇒  
Default value⇒  
■ IFx Message Control Register (IFxMCTR)  
IFx Message Control Register high byte  
⇐ Bit no.  
IFxMCTRH  
15  
14  
13  
12  
11  
10  
9
8
Address : Base + 0x1CH & Base + 0x4CH  
NewDat MsgLst IntPnd UMask TxIE  
RxIE RmtEn TxRqst  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
IFx Message Control Register low byte  
Address : Base + 0x1DH & Base + 0x4DH  
⇐ Bit no.  
IFxMCTRL  
7
6
5
4
3
2
1
0
DLC3-0  
EoB  
res  
res  
res  
(R/W) (R)  
(0) (0)  
(R)  
(0)  
(R) (R/W) (R/W) (R/W) (R/W)  
(0) (0) (0) (0) (0)  
Read/write ⇒  
Default value⇒  
■ IFx Data A and Data B Registers (IFxDTA, IFxDTB)  
The data bytes of CAN messages are stored in the IFx Message Buffer Registers in the following order:  
addr+0  
Data(0)  
addr+1  
Data(1)  
addr+2  
Data(2)  
Data(6)  
Data(1)  
Data(5)  
addr+3  
Data(3)  
Data(7)  
Data(0)  
Data(4)  
IFxMessage Data A1 (addresses 0x20 & 0x50)  
IFx Message Data A2 (addresses 0x22 & 0x52)  
IFx Message Data B1 (addresses 0x24 & 0x54)  
IFx Message Data B2 (addresses 0x26 & 0x56)  
IFx Message Data A2 (addresses 0x30 & 0x60)  
IFx Message Data A1 (addresses 0x32 & 0x62)  
IFx Message Data B2 (addresses 0x34 & 0x64)  
IFx Message Data B1 (addresses 0x36 & 0x66)  
Data(4)  
Data(3)  
Data(7)  
Data(5)  
Data(2)  
Data(6)  
In a CAN Data Frame, Data(0) is the first, Data(7) is the last byte to be transmitted or received. In CAN’s serial  
bit stream, the MSB of each byte will be transmitted first.  
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2.Register Description  
2.5 Message Object in the Message Memory  
There are 32 Message Objects (up to 128 depending on the implementation) in the Message RAM. To avoid  
conflicts between CPU access to the Message RAM and CAN message reception and transmission, the CPU  
cannot directly access the Message Objects, these accesses are handled via the IFx Interface Registers.  
Figure 2-4 gives an overview of the two structures of a Message Object.  
Message Object  
UMask  
MsgVal  
Msk28-0  
ID28-0  
MXtd  
Xtd  
MDir  
Dir  
EoB  
NewDat  
Data0 Data1  
MsgLst  
Data2  
RxIE  
TxIE  
IntPnd  
Data5  
RmtEn  
Data6  
TxRqst  
Data7  
DLC3-0  
Data3  
Data4  
Figure 2-4 Structure of a Message Object in the Message Memory  
MsgVal Message Valid  
0
1
The Message Object is ignored by the Message Handler.  
The Message Object is configured and should be considered by the Message Handler.  
(Note)  
The CPU must reset the MsgVal bit of all unused Message Objects during the initialization before it  
resets bit Init in the CAN Control Register. This bit must also be reset before the identifier ID28-0,  
the control bits Xtd, Dir, or the Data Length Code DLC3-0 are modified, or if the Message Object is  
no longer required.  
UMask Use Acceptance Mask  
0
1
Mask ignored.  
Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.  
(Note)  
If the UMask bit is set to one, the Message Object’s mask bits have to be programmed during  
initialization of the Message Object before MsgVal is set to one.  
ID28-0  
Message Identifier  
ID28 -  
ID0  
ID28 -  
ID18  
29-bit Identifier (“Extended Frame”).  
11-bit Identifier (“Standard Frame”).  
Msk28-0 Identifier Mask  
0
1
The corresponding bit in the identifier of the message object cannot inhibit the match in the  
acceptance filtering.  
The corresponding identifier bit is used for acceptance filtering.  
Xtd  
Extended Identifier  
0
The 11-bit (“standard”) Identifier will be used for this Message Object.  
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2.Register Description  
1
The 29-bit (“extended”) Identifier will be used for this Message Object.  
MXtd  
Mask Extended Identifier  
0
1
The extended identifier bit (IDE) has no effect on the acceptance filtering  
The extended identifier bit (IDE) is used for acceptance filtering.  
(Note)  
When 11-bit (“standard”) Identifiers are used for a Message Object, the identifiers of received Data  
Frames are written into bits ID28 to ID18. For acceptance filtering, only these bits together with mask  
bits Msk28 to Msk18 are considered.  
Dir  
Message Direction  
Direction = receive: On TxRqst, a Remote Frame with the identifier of this Message Object is  
transmitted. On reception of a Data Frame with matching identifier, that message is stored in  
this Message Object.  
0
Direction = transmit: On TxRqst, the respective Message Object is transmitted as a Data  
Frame. On reception of a Remote Frame with matching identifier, the TxRqst bit of this Mes-  
sage Object is set (if RmtEn = 1).  
1
MDir  
Mask Message Direction  
0
1
The message direction bit (Dir) has no effect on the acceptance filtering.  
The message direction bit (Dir) is used for acceptance filtering.  
The Arbitration Registers ID28-0, Xtd, and Dir are used to define the identifier and type of outgoing messages  
and are used (together with the mask registers Msk28-0, MXtd, and MDir) for acceptance filtering of incoming  
messages. A received message is stored into the valid Message Object with matching identifier and Direction=  
receive (Data Frame) or Direction= transmit(Remote Frame). Extended frames can be stored only in Message  
Objects with Xtd = 1, standard frames in Message Objects with Xtd = 0. If a received message (Data Frame  
or Remote Frame) matches with more than one valid Message Object, it is stored into that with the lowest  
message number. For details see 4.5 “Acceptance Filtering of Received Messages” on page 726.  
EoB  
End of Buffer  
0
Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO  
Buffer.  
1
Single Message Object or last Message Object of a FIFO Buffer.  
(Note)  
This bit is used to concatenate two ore more Message Objects (up to 32) to build a FIFO Buffer. For  
single Message Objects (not belonging to a FIFO Buffer) this bit must always be set to 1. For  
details on the concatenation of Message Objects see chapter 4.13 “Configuration of a FIFO Buffer”  
on page 728.  
NewDat New Data  
0
1
No new data has been written into the data portion of this Message Object by the Message  
Handler since last time this flag was cleared by the CPU.  
The Message Handler or the CPU has written new data into the data portion of this Message  
Object.  
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MsgLst Message Lost (only valid for Message Objects with direction = receive)  
0
1
No message lost since last time this bit was reset by the CPU.  
The Message Handler stored a new message into this object when NewDat was still set, the  
CPU has lost a message.  
RxIE  
Receive Interrupt Enable  
0
1
IntPnd will be left unchanged after a successful reception of a frame.  
IntPnd will be set after a successful reception of a frame.  
TxIE  
Transmit Interrupt Enable  
0
1
IntPnd will be left unchanged after the successful transmission of a frame.  
IntPnd will be set after a successful transmission of a frame.  
IntPnd  
Interrupt Pending  
0
1
This message object is not the source of an interrupt.  
This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Regis-  
ter will point to this message object if there is no other interrupt source with higher priority.  
RmtEn Remote Enable  
0
1
At the reception of a Remote Frame, TxRqst is left unchanged.  
At the reception of a Remote Frame, TxRqst is set.  
TxRqst Transmit Request  
0
1
This Message Object is not waiting for transmission.  
The transmission of this Message Object is requested and is not yet done.  
DLC3-0 Data Length Code  
0-8  
Data Frame has 0-8 data bytes.  
9-15  
Data Frame has 8 data bytes.  
(Note)  
The Data Length Code of a Message Object must be defined the same as in all the corresponding  
objects with the same identifier at other nodes. When the Message Handler stores a data frame, it  
will write the DLC to the value given by the received message.  
Data 0  
Data 1  
Data 2  
Data 3  
Data 4  
Data 5  
Data 6  
Data 7  
1st data byte of a CAN Data Frame  
2nd data byte of a CAN Data Frame  
3rd data byte of a CAN Data Frame  
4th data byte of a CAN Data Frame  
5th data byte of a CAN Data Frame  
6th data byte of a CAN Data Frame  
7th data byte of a CAN Data Frame  
8th data byte of a CAN Data Frame  
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2.Register Description  
(Note)  
Byte Data 0 is the first data byte shifted into the shift register of the CAN Core during a reception,  
byte Data 7 is the last. When the Message Handler stores a Data Frame, it will write all the eight  
data bytes into a Message Object. If the Data Length Code is less than 8, the remaining bytes of the  
Message Object will be overwritten by non specified values.  
2.6 Message Handler Registers  
All Message Handler registers are read-only. Their contents (TxRqst, NewDat, IntPnd, and MsgVal bits of  
each Message Object and the Interrupt Identifier) is status information provided by the Message Handler FSM.  
■ Interrupt Register (INTR)  
⇐ Bit no.  
Interrupt Register high byte  
Address : Base + 0x08H  
15  
14  
13  
12  
11  
10  
9
8
INTRH  
IntId15-8  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
⇐ Bit no.  
7
6
5
4
3
2
1
0
Interrupt Register low byte  
Address : Base + 0x09H  
INTRL  
IntId7-0  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
■ Function of the Interrupt Register (INTR)  
• (For 32 message buffer CANs)  
IntId15-0 Interrupt Identifier (the number here indicates the source of the interrupt)  
0x0000  
No interrupt is pending.  
Number of Message Object which caused the interrupt.  
0x0001-  
0x0020  
unused.  
0x0021-  
0x7FFF  
0x8000  
Status Interrupt.  
unused.  
0x8001-  
0xFFFF  
• (For 128 message buffer CANs)  
IntId15-0 Interrupt Identifier (the number here indicates the source of the interrupt)  
0x0000  
No interrupt is pending.  
Number of Message Object which caused the interrupt.  
0x0001-  
0x0080  
0x0081-  
0x7FFF  
unused.  
0x8000  
Status Interrupt.  
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2.Register Description  
0x8001-  
0xFFFF  
unused.  
If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest  
priority, disregarding their chronological order. An interrupt remains pending until the CPU has cleared it. If  
IntId is different from 0x0000 and IE is set, the interrupt line to the CPU is active. The interrupt line remains  
active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.  
The Status Interrupt has the highest priority. Among the message interrupts, the Message Object’ s interrupt  
priority decreases with increasing message number.  
A message interrupt is cleared by clearing the Message Object’s IntPnd bit. The Status Interrupt is cleared by  
reading the Status Register.  
■ Transmission Request Registers (TREQR)  
⇐ Bit no.  
TREQR2H  
Transmission Req Register 2 high byte  
Address : Base + 0x80H  
15  
14  
13  
12  
11  
10  
9
8
TxRqst32-25  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
Transmission Req Register 2 low byte  
Address : Base + 0x81H  
⇐ Bit no.  
TREQR2L  
7
6
5
4
3
2
1
0
TxRqst24-17  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
⇐ Bit no.  
TREQR1H  
Transmission Req Register 1 high byte  
Address : Base + 0x82H  
15  
14  
13  
12  
11  
10  
9
8
TxRqst16-9  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
Transmission Req Register 1 low byte  
Address : Base + 0x83H  
⇐ Bit no.  
TREQR1L  
7
6
5
4
3
2
1
0
TxRqst8-1  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
TxRqst32-1 Transmission Request Bits (of all Message Objects)  
0
1
This Message Object is not waiting for transmission.  
The transmission of this Message Object is requested and is not yet done.  
These registers hold the TxRqst bits of the 32 Message Objects. By reading out the TxRqst bits, the CPU can  
check for which Message Object a Transmission Request is pending. The TxRqst bit of a specific Message  
Object can be set/reset by the CPU via the IFx Message Interface Registers or by the Message Handler after  
reception of a Remote Frame or after a successful transmission.  
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2.Register Description  
If more than 32 message buffers are implemented, the following table gives an overview about the additional  
flags:  
Table 2-1 Additional flags when more than 32 message buffers exist  
addr+0  
addr+1  
addr+2  
addr+3  
TREQR 4 & 3  
TREQR 6 & 5  
TxRqst 64-33 (address 0x84)  
TxRqst 96-65 (address 0x88)  
TxRqst64-57  
TxRqst96-89  
TxRqst56-49  
TxRqst88-81  
TxRqst48-41  
TxRqst80-73  
TxRqst40-33  
TxRqst72-65  
TxRqst120-  
113  
TxRqst112-  
105  
TREQR 8 & 7 TxRqst 128-97 (address 0x8C) TxRqst128-121  
TxRqst104-97  
■ New Data Registers (NEWDT)  
⇐ Bit no.  
NEWDT2H  
New Data Register 2 high byte  
Address : Base + 0x90H  
15  
14  
13  
12  
11  
10  
9
8
NewDat32-25  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
New Data Register 2 low byte  
Address : Base + 0x91H  
Read/write ⇒  
⇐ Bit no.  
NEWDT2L  
7
6
5
4
3
2
1
0
NewDat24-17  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Default value⇒  
⇐ Bit no.  
NEWDT1H  
New Data Register 1 high byte  
Address : Base + 0x92H  
Read/write ⇒  
Default value⇒  
15  
14  
13  
12  
11  
10  
9
8
NewDat16-9  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
New Data Register 1 low byte  
Address : Base + 0x93H  
Read/write ⇒  
⇐ Bit no.  
NEWDT1L  
7
6
5
4
3
2
1
0
NewDat8-1  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Default value⇒  
NewDat32-1 New Data Bits (of all Message Objects)  
No new data has been written into the data portion of this Message Object by the Message  
Handler since last time this flag was cleared by the CPU.  
The Message Handler or the CPU has written new data into the data portion of this Message  
Object.  
0
1
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Chapter 34 CAN Controller  
2.Register Description  
These registers hold the NewDat bits of the 32 Message Objects. By reading out the NewDat bits, the CPU  
can check for which Message Object the data portion was updated. The NewDat bit of a specific Message  
Object can be set/reset by the CPU via the IFx Message Interface Registers or by the Message Handler after  
reception of a Data Frame or after a successful transmission.  
If more than 32 message buffers are implemented, the following table gives an overview about the additional  
flags:  
Table 2-2 Additional flags when more than 32 message buffers exist  
addr+0  
addr+1  
addr+2  
addr+3  
NEWDT 4 & 3  
NEWDT 6 & 5  
NewDat 64-33 (address 0x94)  
NewDat 96-65 (address 0x98)  
NewDat64-57  
NewDat96-89  
NewDat56-49  
NewDat88-81  
NewDat48-41  
NewDat80-73  
NewDat40-33  
NewDat72-65  
NEWDT 8 & 7 NewDat 128-97 (address 0x9C) NewDat128-121 NewDat120-113 NewDat112-105 NewDat104-97  
■ Interrupt Pending Registers (INTPND)  
⇐ Bit no.  
INTPND2H  
Int Pending Register 2 high byte  
Address : Base + 0xA0H  
15  
14  
13  
12  
11  
10  
9
8
IntPnd32-25  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
Int Pending Register 2 low byte  
Address : Base + 0xA1H  
Read/write ⇒  
⇐ Bit no.  
INTPND2L  
7
6
5
4
3
2
1
0
IntPnd24-17  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Default value⇒  
⇐ Bit no.  
INTPND1H  
Int Pending Register 1 high byte  
Address : Base + 0xA2H  
Read/write ⇒  
Default value⇒  
15  
14  
13  
12  
11  
10  
9
8
IntPnd16-9  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Int Pending Register 1 low byte  
Address : Base + 0xA3H  
Read/write ⇒  
⇐ Bit no.  
INTPND1L  
7
6
5
4
3
2
1
0
IntPnd8-1  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Default value⇒  
IntPnd32-1 Interrupt Pending Bits (of all Message Objects)  
This message object is not the source of an interrupt.  
0
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Chapter 34 CAN Controller  
2.Register Description  
1
This message object is the source of an interrupt.  
These registers hold the IntPnd bits of the 32 Message Objects. By reading out the IntPnd bits, the CPU can  
check for which Message Object an interrupt is pending. The IntPnd bit of a specific Message Object can be  
set/reset by the CPU via the IFx Message Interface Registers or by the Message Handler after reception or  
after a successful transmission of a frame. This will also affect the value of IntId in the Interrupt Register.  
If more than 32 message buffers are implemented, the following table gives an overview about the additional  
flags:  
Table 2-3 Additional flags when more than 32 message buffers exist  
addr+0  
addr+1  
addr+2  
addr+3  
INTPND 4 & 3 IntPnd 64-33 (address 0xA4)  
INTPND 6 & 5 IntPnd 96-65 (address 0xA8)  
IntPnd64-57  
IntPnd96-89  
IntPnd56-49  
IntPnd88-81  
IntPnd48-41  
IntPnd80-73  
IntPnd40-33  
IntPnd72-65  
IntPnd128-  
121  
IntPnd120-  
113  
IntPnd112-  
105  
IntPnd104-  
97  
INTPND 8 & 7 IntPd 128-97 (address 0xAC)  
■ Message Valid Registers (MSGVAL)  
⇐ Bit no.  
MSGVAL2H  
Message Valid Register 2 high byte  
Address : Base + 0xB0H  
15  
14  
13  
12  
11  
10  
9
8
MsgVal32-25  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
Message Valid Register 2 low byte  
Address : Base + 0xB1H  
⇐ Bit no.  
MSGVAL2L  
7
6
5
4
3
2
1
0
MsgVal24-17  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
⇐ Bit no.  
MSGVAL1H  
Message Valid Register 1 high byte  
Address : Base + 0xB2H  
15  
14  
13  
12  
11  
10  
9
8
MsgVal16-9  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
Message Valid Register 1 low byte  
Address : Base + 0xB3H  
⇐ Bit no.  
MSGVAL1L  
7
6
5
4
3
2
1
0
MsgVal8-1  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
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Chapter 34 CAN Controller  
2.Register Description  
MsgVal32-1 Message Valid Bits (of all Message Objects)  
0
1
This Message Object is ignored by the Message Handler.  
This Message Object is configured and should be considered by the Message Handler.  
These registers hold the MsgVal bits of the 32 Message Objects. By reading out the MsgVal bits, the CPU  
can check which Message Object is valid. The MsgVal bit of a specific Message Object can be set/reset by  
the CPU via the IFx Message Interface Registers.  
If more than 32 message buffers are implemented then the following table gives an overview about the  
additional flags:  
Table 2-4 Additional flags when more than 32 message buffers exist  
addr+0  
addr+1  
addr+2  
addr+3  
MSGVAL 4 & 3  
MSGVAL 6 & 5  
MsgVal 64-33 (address 0xB4)  
MsgVal 96-65 (address 0xB8)  
MsgVal64-57  
MsgVal96-89  
MsgVal56-49  
MsgVal88-81  
MsgVal48-41  
MsgVal80-73  
MsgVal40-33  
MsgVal72-65  
MsgVal120-  
113  
MsgVal112-  
105  
MSGVAL 8 & 7 MsgVal 128-97 (address 0xBC) MsgVal128-121  
MsgVal104-97  
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Chapter 34 CAN Controller  
3.Functional Description  
3. Functional Description  
This chapter provides an overview of the CAN module’s operating modes and how to use them.  
3.1 Software Initialisation  
The software initialization is started by setting the bit Init in the CAN Control Register, either by software or by  
a hardware reset, or by going Bus_Off.  
While Init is set, all message transfers from and to the CAN bus are stopped, the status of the CAN bus output  
CAN_TX is recessive (HIGH). The counters of the EML are unchanged. Setting Init does not change any  
configuration register.  
To initialize the CAN Controller, the CPU has to set up the Bit Timing Register and each Message Object. If a  
Message Object is not needed, it is sufficient to set its MsgVal bit to not valid. Otherwise, the whole Message  
Object has to be initialized.  
Access to the Bit Timing Register and to the BRP Extension Register for the configuration of the bit timing is  
enabled when both bits Init and CCE in the CAN Control Register are set.  
Resetting Init (by CPU only) finishes the software initialisation. Afterwards the Bit Stream Processor BSP  
synchronizes itself to the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11  
consecutive recessive bits (= Bus Idle) before it can take part in bus activities and starts the message transfer.  
The initialization of the Message Objects is independent of Init and can be done on the fly, but the Message  
Objects should all be configured to particular identifiers or set to not valid before the BSP starts the message  
transfer.  
To change the configuration of a Message Object during normal operation, the CPU has to start by setting  
MsgVal to not valid. When the configuration is completed, MsgVal is set to valid again.  
3.2 CAN Message Transfer  
Once the CAN is initialized and Init is reset to zero, the CAN’s CAN Core synchronizes itself to the CAN bus  
and starts the message transfer.  
Received messages are stored in their appropriate Message Objects if they pass the Message Handler’s  
acceptance filtering. The whole message including all arbitration bits, DLC and eight data bytes is stored in the  
Message Object. If the Identifier Mask is used, the arbitration bits which are masked to “don’t care” may be  
overwritten in the Message Object.  
The CPU may read or write each message any time via the Interface Registers, the Message Handler  
guarantees data consistency in case of concurrent accesses.  
Messages to be transmitted are updated by the CPU. If a permanent Message Object (arbitration and control  
bits set up during configuration) exists for the message, only the data bytes are updated and then TxRqst bit  
with NewDat bit are set to start the transmission. If several transmit messages are assigned to the same  
Message Object (when the number of Message Objects is not sufficient), the whole Message Object has to be  
configured before the transmission of this message is requested.  
The transmission of any number of Message Objects may be requested at the same time, they are transmitted  
subsequently according to their internal priority. Messages may be updated or set to not valid any time, even  
when their requested transmission is still pending. The old data will be discarded when a message is updated  
before its pending transmission has started. Depending on the configuration of the Message Object, the  
transmission of a message may be requested autonomously by the reception of a remote frame with a  
matching identifier.  
3.3 Disabled Automatic Retransmission  
According to the CAN Specification (see ISO11898, 6.3.3 Recovery Management), the CAN provides means  
for automatic retransmission of frames that have lost arbitration or that have been disturbed by errors during  
transmission. The frame transmission service will not be confirmed to the user before the transmission is  
successfully completed. By default, this means for automatic retransmission is enabled. It can be disabled to  
enable the CAN to work within a Time Triggered CAN (TTCAN, see ISO11898-1) environment. The Disabled  
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Chapter 34 CAN Controller  
3.Functional Description  
Automatic Retransmission mode is enabled by setting the bit DAR in the CAN Control Register to one. In this  
operation mode the programmer has to consider the different behaviour of bits TxRqst and NewDat in the  
Control Registers of the Message Buffers:  
When a transmission starts bit TxRqst of the respective Message Buffer is reset, while bit NewDat remains  
set.  
When the transmission completed successfully bit NewDat is reset.  
When a transmission failed (lost arbitration or error) bit NewDat remains set. To restart the transmission the  
CPU has to set TxRqst back to one.  
3.4 Test Mode  
The Test Mode is entered by setting bit Test in the CAN Control Register to one. In Test Mode the bits Tx1,  
Tx0, LBack, Silent and Basic in the Test Register are writable. Bit Rx monitor the state of pin CAN_RX and  
therefore is only readable. All Test Register functions are disabled when bit Test is reset to zero.  
3.5 Silent Mode  
The CAN Core can be set in Silent Mode by programming the Test Register bit Silent to one.  
In Silent Mode, the CAN is able to receive valid data frames and valid remote frames, but it sends only  
recessive bits on the CAN bus and it cannot start a transmission. If the CAN Core is required to send a  
dominant bit (ACK bit, overload flag, active error flag), the bit is rerouted internally so that the CAN Core  
monitors this dominant bit, although the CAN bus may remain in recessive state. The Silent Mode can be used  
to analyse the traffic on a CAN bus without affecting it by the transmission of dominant bits (Acknowledge Bits,  
Error Frames). Figure 3-1 shows the connection of signals CAN_TX and CAN_RX to the CAN Core in Silent  
Mode.  
Figure 3-1 CAN Core in Silent Mode  
In ISO 11898-1, the Silent Mode is called the Bus Monitoring Mode.  
3.6 Loop Back Mode  
The CAN Core can be set in Loop Back Mode by programming the Test Register bit LBack to one. In Loop  
Back Mode, the CAN Core treats its own transmitted messages as received messages and stores them (if  
they pass acceptance filtering) into a Receive Buffer. Figure 3-2 shows the connection of signals CAN_TX and  
CAN_RX to the CAN Core in Loop Back Mode.  
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Chapter 34 CAN Controller  
3.Functional Description  
Figure 3-2 CAN Core in Loop Back Mode  
This mode is provided for self-test functions. To be independent from external stimulation, the CAN Core  
ignores acknowledge errors (recessive bit sampled in the acknowledge slot of a data/remote frame) in Loop  
Back Mode. In this mode the CAN Core performs an internal feedback from its Tx output to its Rx input. The  
actual value of the CAN_RX input pin is disregarded by the CAN Core. The transmitted messages can be  
monitored at the CAN_TX pin.  
3.7 Loop Back combined with Silent Mode  
It is also possible to combine Loop Back Mode and Silent Mode by programming bits LBack and Silent to one  
at the same time. This mode can be used for a “Hot Selftest”, meaning the CAN can be tested without  
affecting a running CAN system connected to the pins CAN_TX and CAN_RX. In this mode the CAN_RX pin  
is disconnected from the CAN Core and the CAN_TX pin is held recessive. Figure 3-3shows the connection of  
signals CAN_TX and CAN_RX to the CAN Core in case of the combination of Loop Back Mode with Silent  
Mode.  
Figure 3-3 CAN Core in Loop Back combined with Silent Mode  
3.8 Basic Mode  
The CAN Core can be set in Basic Mode by programming the Test Register bit Basic to one. In this mode the  
CAN module runs without the Message RAM.  
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Chapter 34 CAN Controller  
3.Functional Description  
The IF1 Registers are used as Transmit Buffer. The transmission of the contents of the IF1 Registers is  
requested by writing the Busy bit of the IF1 Command Request Register to ‘1’. The IF1 Registers are locked  
while the Busy bit is set. The Busy bit indicates that the transmission is pending.  
As soon as the CAN bus is idle, the IF1 Registers are loaded into the shift register of the CAN Core and the  
transmission is started. When the transmission has completed, the Busy bit is reset and the locked IF1  
Registers are released.  
A pending transmission can be aborted at any time by resetting the Busy bit in the IF1 Command Request  
Register while the IF1 Registers are locked. If the CPU has reset the Busy bit, a possible retransmission in  
case of lost arbitration or in case of an error is disabled.  
The IF2 Registers are used as Receive Buffer. After the reception of a message the content of the shift  
register is stored into the IF2 Registers, without any acceptance filtering.  
Additionally, the actual contents of the shift register can be monitored during the message transfer. Each time  
a read Message Object is initiated by writing the Busy bit of the IF2 Command Request Register to ‘1’, the  
content of the shift register is stored in the IF2 Registers.  
In Basic Mode the evaluation of all Message Object related control and status bits and of the control bits of the  
IFx Command Mask Registers is turned off. The message number of the Command request registers is not  
evaluated. The NewDat and MsgLst bits of the IF2 Message Control Register retain their function, DLC3-0  
will show the received DLC, the other control bits will be read as ‘0’.  
3.9 Software control of Pin CAN_TX  
Four output functions are available for the CAN transmit pin CAN_TX. Additionally to its default function – the  
serial data output – it can drive the CAN Sample Point signal to monitor CAN_Core’s bit timing and it can drive  
constant dominant or recessive values. The last two functions, combined with the readable CAN receive pin  
CAN_RX, can be used to check the CAN bus’ physical layer.  
The output mode of pin CAN_TX is selected by programming the Test Register bits Tx1 and Tx0 as described  
in section 2.3 “CAN Protocol Related Registers” on page 696.  
The three test functions for pin CAN_TX interfere with all CAN protocol functions. CAN_TX must be left in its  
default function when CAN message transfer or any of the test modes Loop Back Mode, Silent Mode, or Basic  
Mode are selected.  
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Chapter 34 CAN Controller  
4.CAN Application  
4. CAN Application  
This section describes how to use the CAN module in the application  
4.1 Management of Message Objects  
The configuration of the Message Objects in the Message RAM will (with the exception of the bits MsgVal,  
NewDat, IntPnd, and TxRqst) not be affected by resetting the chip. All the Message Objects must be  
initialized by the CPU or they must be not valid (MsgVal = ‘0’) and the bit timing must be configured before the  
CPU clears the Init bit in the CAN Control Register.  
The configuration of a Message Object is done by programming Mask, Arbitration, Control and Data field of  
one of the two interface register sets to the desired values. By writing to the corresponding IFx Command  
Request Register, the IFx Message Buffer Registers are loaded into the addressed Message Object in the  
Message RAM.  
When the Init bit in the CAN Control Register is cleared, the CAN Protocol Controller state machine of the  
CAN_Core and the Message Handler State Machine control the CAN’s internal data flow. Received messages  
that pass the acceptance filtering are stored into the Message RAM, messages with pending transmission  
request are loaded into the CAN_Core’s Shift Register and are transmitted via the CAN bus.  
The CPU reads received messages and updates messages to be transmitted via the IFx Interface Registers.  
Depending on the configuration, the CPU is interrupted on certain CAN message and CAN error events.  
4.2 Message Handler State Machine  
The Message Handler controls the data transfer between the Rx/Tx Shift Register of the CAN Core, the  
Message RAM and the IFx Registers.  
• The Message Handler FSM controls the following functions:  
•
•
•
•
•
•
•
•
Data Transfer from IFx Registers to the Message RAM  
Data Transfer from Message RAM to the IFx Registers  
Data Transfer from Shift Register to the Message RAM  
Data Transfer from Message RAM to Shift Register  
Data Transfer from Shift Register to the Acceptance Filtering unit  
Scanning of Message RAM for a matching Message Object  
Handling ofTxRqst flags.  
Handling of interrupts.  
4.3 Data Transfer from/to Message RAM  
When the CPU initiates a data transfer between the IFx Registers and Message RAM, the Message Handler  
sets an internal busy signal which delays a consecutive access. After the transfer has completed, the busy  
signal is set back and the consecutive access is executed.  
The respective Command Mask Register specifies whether a complete Message Object or only parts of it will  
be transferred. Due to the structure of the Message RAM it is not possible to write single bits/bytes of one  
Message Object, it is always necessary to write a complete Message Object into the Message RAM.  
Therefore the data transfer from the IFx Registers to the Message RAM requires a read-modify-write cycle.  
First parts of the Message Object that are not to be changes are read from the Message RAM and then the  
complete contents of the Message Buffer Registers are written into the Message Object.  
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Chapter 34 CAN Controller  
4.CAN Application  
Figure 4-1 Data Transfer between IFx Registers and Message RAM  
After the partial write of a Message Object, that Message Buffer Registers that are not selected in the  
Command Mask Register will set to the actual contents of the selected Message Object.  
After the partial read of a Message Object, that Message Buffer Registers that are not selected in the  
Command Mask Register will be left unchanged.  
4.4 Transmission of Messages  
If the shift register of the CAN Core cell is ready for loading and if there is no data transfer between the IFx  
Registers and Message RAM, the MsgVal bits in the Message Valid Register and the TxRqst bits in the  
Transmission Request Register are evaluated. The valid Message Object with the highest priority pending  
transmission request is loaded into the shift register by the Message Handler and the transmission is started.  
The Message Object’s NewDat bit is reset.  
After a successful transmission and if no new data was written to the Message Object (NewDat = ‘0’) since the  
start of the transmission, the TxRqst bit will be reset. If TxIE is set, IntPnd will be set after a successful  
transmission. If the CAN has lost the arbitration or if an error occurred during the transmission, the message  
will be retransmitted as soon as the CAN bus is free again. If meanwhile the transmission of a message with  
higher priority has been requested, the messages will be transmitted in the order of their priority.  
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Chapter 34 CAN Controller  
4.CAN Application  
4.5 Acceptance Filtering of Received Messages  
When the arbitration and control field (Identifier + IDE + RTR + DLC) of an incoming message is completely  
shifted into the Rx/Tx Shift Register of the CAN Core, the Message Handler FSM starts the scanning of the  
Message RAM for a matching valid Message Object.  
To scan the Message RAM for a matching Message Object, the Acceptance Filtering unit is loaded with the  
arbitration bits from the CAN Core shift register. Then the arbitration and mask fields (including MsgVal,  
UMask, NewDat, and EoB) of Message Object 1 are loaded into the Acceptance Filtering unit and compared  
with the arbitration field from the shift register. This is repeated with each following Message Object until a  
matching Message Object is found or until the end of the Message RAM is reached.  
If a match occurs, the scanning is stopped and the Message Handler FSM proceeds depending on the type of  
frame (Data Frame or Remote Frame) received.  
4.6 Reception of Data Frame  
The Message Handler FSM stores the message from the CAN Core shift register into the respective Message  
Object in the Message RAM. Not only the data bytes, but all arbitration bits and the Data Length Code are  
stored into the corresponding Message Object. This is implemented to keep the data bytes connected with the  
identifier even if arbitration mask registers are used.  
The NewDat bit is set to indicate that new data (not yet seen by the CPU) has been received. The CPU should  
reset NewDat when it reads the Message Object. If at the time of the reception the NewDat bit was already  
set, MsgLst is set to indicate that the previous data (supposedly not seen by the CPU) is lost. If the RxIE bit is  
set, the IntPnd bit is set, causing the Interrupt Register to point to this Message Object.  
The TxRqst bit of this Message Object is reset to prevent the transmission of a Remote Frame, while the  
requested Data Frame has just been received.  
4.7 Reception of Remote Frame  
When a Remote Frame is received, three different configurations of the matching Message Object have to be  
considered:  
1) Dir = ‘1’ (direction = transmit), RmtEn = ‘1’, UMask = ‘1’ or ’0’  
At the reception of a matching Remote Frame, the TxRqst bit of this Message Object is set. The rest of the  
Message Object remains unchanged.  
2) Dir = ‘1’ (direction = transmit), RmtEn = ‘0’, UMask = ’0’  
At the reception of a matching Remote Frame, the TxRqst bit of this Message Object remains unchanged; the  
Remote Frame is ignored.  
3) Dir = ‘1’ (direction = transmit), RmtEn = ‘0’, UMask = ’1’  
At the reception of a matching Remote Frame, the TxRqst bit of this Message Object is reset. The arbitration  
and control field (Identifier + IDE + RTR + DLC) from the shift register is stored into the Message Object in the  
Message RAM and the NewDat bit of this Message Object is set. The data field of the Message Object  
remains unchanged; the Remote Frame is treated similar to a received Data Frame.  
4.8 Receive / Transmit Priority  
The receive/transmit priority for the Message Objects is attached to the message number. Message Object 1  
has the highest priority, while Message Object 32 (the highest implemented message object number) has the  
lowest priority. If more than one transmission request is pending, they are serviced due to the priority of the  
corresponding Message Object.  
4.9 Configuration of a Transmit Object  
Figure 4-2 shows how a Transmit Object should be initialised.  
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Chapter 34 CAN Controller  
4.CAN Application  
Eo  
B
RxI  
E
MsgVal  
Arb  
Data Mask  
appl.  
Dir NewDat MsgLst  
TxIE IntPnd RmtEn TxRqst  
1
appl. appl.  
1
1
0
0
0
appl.  
0
appl.  
0
Figure 4-2 Initialisation of a Transmit Object  
The Arbitration Registers (ID28-0 and Xtd bit) are given by the application. They define the identifier and type  
of the outgoing message. If an 11-bit Identifier (“Standard Frame”) is used, it is programmed to ID28 - ID18,  
ID17 - ID0 can then be disregarded.  
If the TxIE bit is set, the IntPnd bit will be set after a successful transmission of the Message Object.  
If the RmtEn bit is set, a matching received Remote Frame will cause the TxRqst bit to be set; the Remote  
Frame will autonomously be answered by a Data Frame.  
The Data Registers (DLC3-0, Data0-7) are given by the application, TxRqst and RmtEn may not be set  
before the data is valid.  
The Mask Registers (Msk28-0, UMask, MXtd, and MDir bits) may be used (UMask=’1’) to allow groups of  
Remote Frames with similar identifiers to set the TxRqst bit. For details see section 4.4 “Transmission of  
Messages” on page 725., handle with care. The Dir bit should not be masked.  
4.10 Updating a Transmit Object  
The CPU may update the data bytes of a Transmit Object any time via the IFx Interface registers, neither  
MsgVal nor TxRqst have to be reset before the update.  
Even if only a part of the data bytes are to be updated, all four bytes of the corresponding IFx Data A Register  
or IFx Data B Register have to be valid before the content of that register is transferred to the Message  
Object. Either the CPU has to write all four bytes into the IFx Data Register or the Message Object is  
transferred to the IFx Data Register before the CPU writes the new data bytes.  
When only the (eight) data bytes are updated, first 0x0087 is written to the Command Mask Register and then  
the number of the Message Object is written to the Command Request Register, concurrently updating the  
data bytes and setting TxRqst.  
To prevent the reset of TxRqst at the end of a transmission that may already be in progress while the data is  
updated, NewDat has to be set together with TxRqst. For details see section section 4.4 “Transmission of  
Messages” on page 725.  
When NewDat is set together with TxRqst, NewDat will be reset as soon as the new transmission has  
started.  
4.11 Configuration of a Receive Object  
Figure 4-3 shows how a Transmit Object should be initialised.  
Eo  
B
RxI  
E
MsgVal  
Arb  
Data Mask  
appl.  
Dir NewDat MsgLst  
TxIE IntPnd RmtEn TxRqst  
1
appl. appl.  
1
0
0
0
appl.  
0
0
0
0
Figure 4-3 Initialisation of a Receive Object  
The Arbitration Registers (ID28-0 and Xtd bit) are given by the application. They define the identifier and type  
of accepted received messages. If an 11-bit Identifier (“Standard Frame”) is used, it is programmed to ID28 -  
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Chapter 34 CAN Controller  
4.CAN Application  
ID18, ID17 - ID0 can then be disregarded. When a Data Frame with an 11-bit Identifier is received, ID17 - ID0  
will be set to ‘0’.  
If the RxIE bit is set, the IntPnd bit will be set when a received Data Frame is accepted and stored in the  
Message Object.  
The Data Length Code (DLC3-0) is given by the application. When the Message Handler stores a Data Frame  
in the Message Object, it will store the received Data Length Code and eight data bytes. If the Data Length  
Code is less than 8, the remaining bytes of the Message Object will be overwritten by non specified values.  
The Mask Registers (Msk28-0, UMask, MXtd, and MDir bits) may be used (UMask=’1’) to allow groups of  
Data Frames with similar identifiers to be accepted. For details see section 4.6 “Reception of Data Frame” on  
page 726.. The Dir bit should not be masked in typical applications.  
4.12 Handling of Received Messages  
The CPU may read a received message any time via the IFx Interface registers, the data consistency is  
guaranteed by the Message Handler state machine.  
Typically the CPU will write first 0x007F to the Command Mask Register and then the number of the Message  
Object to the Command Request Register. That combination will transfer the whole received message from  
the Message RAM into the Message Buffer Register. Additionally, the bits NewDat and IntPnd are cleared in  
the Message RAM (not in the Message Buffer).  
If the Message Object uses masks for acceptance filtering, the arbitration bits show which of the matching  
messages have been received.  
The actual value of NewDat shows whether a new message has been received since last time this Message  
Object was read. The actual value of MsgLst shows whether more than one message has been received  
since last time this Message Object was read. MsgLst will not be automatically reset.  
By means of a Remote Frame, the CPU may request another CAN node to provide new data for a receive  
object. Setting the TxRqst bit of a receive object will cause the transmission of a Remote Frame with the  
receive object’s identifier. This Remote Frame triggers the other CAN node to start the transmission of the  
matching Data Frame. If the matching Data Frame is received before the Remote Frame could be transmitted,  
the TxRqst bit is automatically reset.  
4.13 Configuration of a FIFO Buffer  
With the exception of the EoB bit, the configuration of Receive Objects belonging to a FIFO Buffer is the same  
as the configuration of a (single) Receive Object, see section 4.11 “Configuration of a Receive Object” on  
page 727.  
To concatenate two or more Message Objects into a FIFO Buffer, the identifiers and masks (if used) of these  
Message Objects have to be programmed to matching values. Due to the implicit priority of the Message  
Objects, the Message Object with the lowest number will be the first Message Object of the FIFO Buffer. The  
EoB bit of all Message Objects of a FIFO Buffer except the last have to be programmed to zero. The EoB bits  
of the last Message Object of a FIFO Buffer is set to one, configuring it as the End of the Block.  
4.14 Reception of Messages with FIFO Buffers  
Received messages with identifiers matching to a FIFO Buffer are stored into a Message Object of this FIFO  
Buffer starting with the Message Object with the lowest message number.  
When a message is stored into a Message Object of a FIFO Buffer the NewDat bit of this Message Object is  
set. By setting NewDat while EoB is 0 the Message Object is locked for further write accesses by the  
Message Handler until the CPU has written the NewDat bit back to 0.  
Messages are stored into a FIFO Buffer until the last Message Object of this FIFO Buffer is reached. If none of  
the preceding Message Objects is released by writing NewDat to 0, all further messages for this FIFO Buffer  
will be written into the last Message Object of the FIFO Buffer and therefore overwrite previous messages.  
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Chapter 34 CAN Controller  
4.CAN Application  
4.15 Reading from a FIFO Buffer  
When the CPU transfers the contents of Message Object to the IFx Message Buffer registers by writing its  
number to the IFx Command Request Register, the corresponding Command Mask Register should be  
programmed the way that bits NewDat and IntPnd are reset to zero (TxRqst/NewDat = ‘1’ and ClrIntPnd =  
‘1’). The values of these bits in the Message Control Register always reflect the status before resetting the  
bits.  
To assure the correct function of a FIFO Buffer, the CPU should read out the Message Objects starting at the  
FIFO Object with the lowest message number.  
Figure 4-4 shows how a set of Message Objects which are concatenated to a FIFO Buffer can be handled by  
the CPU.  
Figure 4-4 CPU Handling of a FIFO Buffer  
4.16 Handling of Interrupts  
If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest  
priority, disregarding their chronological order. An interrupt remains pending until the CPU has cleared it.  
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Chapter 34 CAN Controller  
4.CAN Application  
The Status Interrupt has the highest priority. Among the message interrupts, the Message Object’ s interrupt  
priority decreases with increasing message number.  
A message interrupt is cleared by clearing the Message Object’s IntPnd bit. The Status Interrupt is cleared by  
reading the Status Register.  
The interrupt identifier IntId in the Interrupt Register indicates the cause of the interrupt. When no interrupt is  
pending, the register will hold the value zero. If the value of the Interrupt Register is different from zero, then  
there is an interrupt pending and, if IE is set, the interrupt line to the CPU is active. The interrupt line remains  
active until the Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset.  
The value 0x8000 indicates that an interrupt is pending because the CAN Core has updated (not necessarily  
changed) the Status Register (Error Interrupt or Status Interrupt). This interrupt has the highest priority. The  
CPU can update (reset) the status bits RxOk, TxOk and LEC, but a write access of the CPU to the Status  
Register can never generate or reset an interrupt.  
All other values indicate that the source of the interrupt is one of the Message Objects, IntId points to the  
pending message interrupt with the highest interrupt priority.  
The CPU controls whether a change of the Status Register may cause an interrupt (bits EIE and SIE in the  
CAN Control Register) and whether the interrupt line becomes active when the Interrupt Register is different  
from zero (bit IE in the CAN Control Register). The Interrupt Register will be updated even when IE is reset.  
The CPU has two possibilities to follow the source of a message interrupt. First it can follow the IntId in the  
Interrupt Register and second it can poll the Interrupt Pending Register (see section 2.6 Message Handler  
Registers (Page No.714).  
An interrupt service routine reading the message that is the source of the interrupt may read the message and  
reset the Message Object’s IntPnd at the same time (bit ClrIntPnd in the Command Mask Register). When  
IntPnd is cleared, the Interrupt Register will point to the next Message Object with a pending interrupt.  
4.17 Bit Time and Bit Rate  
The timing parameter of the bit time (i.e. the reciprocal of the bit rate) can be configured individually for each  
CAN node, creating a common bit rate even though the CAN nodes’ oscillator periods (f ) may be different.  
osc  
The frequencies of these oscillators are not absolutely stable, small variations are caused by changes in  
temperature or voltage and by deteriorating components. As long as the variations remain inside a specific  
oscillator tolerance range (df), the CAN nodes are able to compensate for the different bit rates by  
resynchronising to the bit stream.  
According to the CAN specification, the bit time is divided into four segments (see Figure 4-5). The  
Synchronisation Segment, the Propagation Time Segment, the Phase Buffer Segment 1, and the Phase  
Buffer Segment 2. Each segment consists of a specific, programmable number of time quanta (see Table 1).  
The length of the time quantum (t ) , which is the basic time unit of the bit time, is defined by the CAN  
q
controller’s system clock f  
and the Baud Rate Prescaler (BRP) : t = BRP / f . The CAN’s system clock  
sys  
sys  
q
f
is the frequency of its CAN_CLK input.  
sys  
The Synchronisation Segment Sync_Seg is that part of the bit time where edges of the CAN bus level are  
expected to occur; the distance between an edge that occurs outside of Sync_Seg and the Sync_Seg is called  
the phase error of that edge. The Propagation Time Segment Prop_Seg is intended to compensate for the  
physical delay times within the CAN network. The Phase Buffer Segments Phase_Seg1 and Phase_Seg2  
surround the Sample Point. The (Re-)Synchronisation Jump Width (SJW) defines how far a resynchronisation  
may move the Sample Point inside the limits defined by the Phase Buffer Segments to compensate for edge  
phase errors.  
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Chapter 34 CAN Controller  
4.CAN Application  
Figure 4-5 Bit Timing  
Parameter  
BRP  
Range  
[1..32]  
1 tq  
Remark  
defines the legth of the time quantum tq  
Sync_Seg  
Prop_Seg  
Phase_Seg1  
Phase_Seg2  
SJW  
fixed length, synchronisation of us into system clock  
compensates for the physical delay times  
[1..8] tq  
[1..8] tq  
[1..8] tq  
[1..4] tq  
may be lengthened temporarily by synchronisation  
may be shortened temporarily by synchronisation  
may not be longer than either Phase Buffer Segment  
Table 4-1 Parameters of the CAN Bit Time  
(Note) This table describes the minimum programmable ranges required by the CAN protocol.  
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Chapter 34 CAN Controller  
4.CAN Application  
732  
Chapter 35 Free-Run Timer  
1.Overview  
Chapter 35 Free-Run Timer  
1. Overview  
The free-run timer consists of a 16-bit timer (up counter) and control circuits.  
The free-run timer can be used with the input capture and the output compare.  
Clear  
Internal clock  
or  
Up counter  
Overflow  
External clock  
2. Features  
• Format: 16-bit up counter  
• Quantity: 8 (free-run timer 0 up to free-run timer 7)  
• Clock source: 4 internal clocks (1/4, 1/16, 1/32, and 1/64 of CLKP)  
• External clock (CK)  
• Clear factor of the count:  
• Software  
• Reset  
• Compare-match (match of the compare-register value and the count value of the free-run timer)  
• Operation start/stop: operations can be started/stopped with software.  
• Interrupt:  
• Overflow interrupt  
• An interrupt generated when the compare clear register value and the count value of the free-run timer  
match.  
• Count value: Readable/writable (write is only possible when the counting stops)  
• Others: Operates from immediately after reset.  
• Free Run Timer to ICU/OCU mapping:  
• Free-run timer 0 and input capture 0/1 co-operate  
• Free-run timer 1 and input capture 2/3 co-operate  
• Free-run timer 2 and output compare 0/1 co-operate  
• Free-run timer 3 and output compare 2/3 co-operate  
• Free-run timer 4 and input capture 4/5 co-operate  
• Free-run timer 5 and input capture 6/7 co-operate  
• Free-run timer 6 and output compare 4/5 co-operate  
• Free-run timer 7 and output compare 6/7 co-operate  
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Chapter 35 Free-Run Timer  
3.Configuration Diagram  
3. Configuration Diagram  
Figure 3-1 Configuration Diagram  
Free-run Timer  
Count clock  
CLK1-0  
TCCS: bit 1-0  
0
0
0
1
0
1
CLKP / 4  
CLKP / 16  
CLKP / 32  
1
1
STOP  
TCCS: bit 4  
Input capture  
IVFE  
TCCS: bit 5  
CLKP / 64  
0
1
Count operation  
0
1
Disable interrupts  
Enable interrupts  
Stop the count operation  
Count value  
Overflow flag  
0
0
1
Peripheral clock  
CLKP  
Timer data register  
TCDT  
Divider  
Free-run Timer  
interrupt  
IVF  
TCCS: bit 6  
0
1
No interrupt requests  
External clock  
1
Synchronization  
circuit  
Interrupt request present  
External clock  
CK /SCK/ Pxy.z  
WRITE 0: Flag clear  
Clear  
The clock selection  
ECLK  
OR  
TCCS:bit 7  
Count value  
0
1
From the divider  
From the outside  
Output compare  
1
Read of the port  
The timer clear request by the  
compare value match of the  
output compare  
0
From the port  
data register  
0
1 (Resource  
output)  
TCCS: bit 3  
CLR  
TCCS:bit 2  
MODE  
PFR/EPFR  
Function  
GP DDRxy.z  
0
0
Disable the clear by the compare-match  
Enable the clear by the compare-match  
No effect  
Clears the timer  
General-purpose port  
0
1
0
0
1
0
Input only  
1
1
1
Enable output  
SCK (USART shift clock)  
CK (FRT clock input)  
1
Notes: When using the input/output (SCK), the external clock (CK) cannot be used because the port is shared.  
Figure 3-2 Register List  
Note: See “Chapter 24 Interrupt Control (Page No.311)” about ICR register and interrupt vectors.  
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Chapter 35 Free-Run Timer  
4.Registers  
4. Registers  
4.1 TCCS: Timer Control Register  
A register for controlling the operation of the free-run timer.  
• TCCS0 (free-run timer 0): Address 01F3h (access: Byte, Half-word, Word)  
• TCCS1 (free-run timer 1): Address 01F7h (access: Byte, Half-word, Word)  
• TCCS2 (free-run timer 2): Address 01FBh (access: Byte, Half-word, Word)  
• TCCS3 (free-run timer 3): Address 01FFh (access: Byte, Half-word, Word)  
• TCCS4 (free-run timer 4): Address 02F3h (access: Byte, Half-word, Word)  
• TCCS5 (free-run timer 5): Address 02F7h (access: Byte, Half-word, Word)  
• TCCS6 (free-run timer 6): Address 02FBh (access: Byte, Half-word, Word)  
• TCCS7 (free-run timer 7): Address 02FFh (access: Byte, Half-word, Word)  
7
ECLK  
0
6
5
IVFE  
0
4
STOP  
0
3
MODE  
0
2
1
CLK1  
0
0
CLK0  
0
bit  
IVF  
0
CLR  
0
Initial value  
Attribute  
R/W  
R (RM1), W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
(About attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• bit7: Select the count clock  
ECLK  
Select the count clock  
Internal clock (the peripheral clock divided by n)  
External clock (CK pin)  
0
1
• When you change the setting of the count clock selection bit, do so when other peripheral modules (the  
output compare, input capture, etc.) using the output of the free-run timer are stopped.  
• When using the external clock, the period of the external clock must be more than double of the  
peripheral clock (CLKP). When using the output compare, in order to allow the compare-match output  
and interrupt generation, the external clock input of at least 1 clock is required after the compare-match.  
• bit6: Interrupt request flag  
Status  
IVF  
Read  
Write  
0
1
No interrupt request present  
Clear the flag (IVF).  
Interrupt request present  
(Overflow or compare-match)  
No effect on operation  
• When the count value of the free-run timer overflows, or the clear mode bit (MODE) is “1”, the interrupt  
request flag is set to “1” if the count values of the free-run timer and the compare register (OCCP) match  
and the counter is cleared.  
• To enable the interrupt request, the interrupt enabling bit must be set to do so (IVFE=“1”).  
• When the interrupt request flag is set to “1”, and “0” is written at the same time, the interrupt request flag  
is set to “1”. (Setting the flag has priority.)  
• bit5: Enable interrupt requests  
IVFE  
Operation  
0
1
Disable interrupts  
Enable interrupts  
• When the interrupt request enabling bit is set to “1”, the interrupt request (IVF) is enabled.  
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Chapter 35 Free-Run Timer  
4.Registers  
• bit4: Stop counting  
STOP  
Operation  
0
1
Enable counting  
Disable count (stop)  
• When the count stop bit is set to “1”, the free-run timer stops.  
• When the output compare is being used, if the free-run timer stops, the output compare also stops.  
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Chapter 35 Free-Run Timer  
4.Registers  
• bit3: Clear mode  
MODE  
Clear mode  
0
1
Clear the free-run timer by the reset and the clear bit (CLR).  
Clear the free-run timer by the match with the reset, the clear bit (CLR), and the compare register value  
of the output compare (OCCP).  
• Set the clear mode of the free-run timer.  
• If the clear mode bit is set to “1”, when the count value of the free-run timer and the compare-register  
value (OCCP) match, the count value of the free-run timer is cleared to “0000h”.  
• The reset and writing “1” to the clear bit (CLR) cause to clear the count value of the free-run timer to  
“0000h”, regardless of the setting of the clear mode bit.  
• The count value of the free-run timer is only cleared when the free-run timer is running. When the free-  
run timer is stopped, clear it by writing “0000h” to the timer data register (TCDT).  
• bit2: Clear  
CLR  
Operation  
0
1
No effect on operation  
Clear the free-run timer.  
• When the clear bit is set to “1”, the count value of the free-run timer is cleared to “0000h”. The clear bit is  
read as “1” until the free-run timer is completely cleared.  
When the free-run timer is completely cleared, the clear bit is also cleared to “0”.  
• When the clear operation of the free-run timer and writing “1” to the clear bit occurs at the same time, the  
clear bit keeps “1”, and after the next time the free-run timer is cleared, it is cleared.  
• bit1-bit0: Count clock division ratio selection (when the internal clock is selected)  
CLK1  
CLK0  
The division ratio of the count clock  
Peripheral clock (CLKP) divided by 4  
Peripheral clock (CLKP) divided by 16  
Peripheral clock (CLKP) divided by 32  
Peripheral clock (CLKP) divided by 64  
0
0
1
1
0
1
0
1
• Select the division ratio of the count clock of the free-run timer.  
• Change the division ratio when the setting of the count clock division ratio selection bit is changed. When  
the internal clock is selected as the count clock of the free-run timer (count clock selection bit ECLK=“0”),  
change the setting when other peripheral modules (output compare, input capture, etc.) using the output  
of the free-run timer are stopped.  
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Chapter 35 Free-Run Timer  
4.Registers  
4.2 TCDT: Timer Data Register  
This register can read 16-bit free-run timer count values.  
• TCDT0 (free-run timer 0): Address 01F0h (access: Half-word, Word)  
• TCDT1 (free-run timer 1): Address 01F4h (access: Half-word, Word)  
• TCDT2 (free-run timer 2): Address 01F8h (access: Half-word, Word)  
• TCDT3 (free-run timer 3): Address 01FCh (access: Half-word, Word)  
• TCDT4 (free-run timer 4): Address 02F0h (access: Half-word, Word)  
• TCDT5 (free-run timer 5): Address 02F4h (access: Half-word, Word)  
• TCDT6 (free-run timer 6): Address 02F8h (access: Half-word, Word)  
• TCDT7 (free-run timer 7): Address 02FCh (access: Half-word, Word)  
15  
14  
13  
12  
11  
10  
9
8
bit  
T15  
T14  
T13  
T12  
T11  
T10  
T9  
T8  
Initial  
value  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
7
6
5
4
3
2
1
0
bit  
T7  
T6  
T5  
T4  
T3  
T2  
T1  
T0  
Initial  
value  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(About attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• When the timer data register is read, the count value of the free-run timer is also obtained.  
• By writing to the timer data register, the timer value can be written in the free-run timer. When it is written,  
make sure that the free-run timer is in the idle state (the count stop bit (TCCS.STOP= 1”)).  
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Chapter 35 Free-Run Timer  
5.Operation  
5. Operation  
5.1 Count Operation of the Free-run Timer  
(Internal clock)  
FCLKP/2)  
(External clock  
External pin  
(CKI)  
Peripheral  
clock (CLKP)  
Internal clock  
(FCLKP/2)  
Count  
timing  
Count  
timing  
(7)  
The count of the  
free-run timer  
The count of the  
free-run timer  
(8)  
FFFFh  
The count of  
the free-run  
timer  
(3)  
(2)  
(5)  
0000 h  
Reset  
Time  
(1)  
Clear by software  
Clear by software  
(4)  
(5)  
The overflow and the  
interrupt request  
(2)  
Clearing the  
free-run timer  
(1) Reset  
(2) Clearing of the free-run timer by reset. (Count value “0000”)  
(3) Count-up of the free-run timer  
(4) Overflow and interrupt of the free-run timer.  
(5) Clearing of the free-run timer by overflow. (Count value “0000”)  
(6) Repeat (3) to (5)  
(7) The free-run timer counts up at the count clock (the internal clock divided by n).  
(8) The free-run timer counts up at the count clock (the external clock synchronized with the internal clock).  
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Chapter 35 Free-Run Timer  
5.Operation  
5.2 Various Clear Operations of the Free-run Timer  
The count of  
the free-run  
timer  
(2)  
(3)  
(1)  
(4)  
Time  
0000 h  
Reset  
Write "0000"  
Clear  
Clear by software or the  
compare-match.  
Operation  
stop  
The enable/disable  
of the operation  
(software)  
Operation stop  
Timing of the clear by the compare-match  
(Internal clock)  
Peripheral  
clock (CLKP)  
Count  
timing  
Count value N-1  
Compare value  
N
"0000"  
"0001"  
Compare value = N  
Compare-match  
Clearing the free-run timer  
The request of interrupt  
Clear operations of the free-run timer (4 types)  
(1) Reset  
(2) Clear by software  
(3) Clear by the compare-match  
(4) Writing “0000”  
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Chapter 35 Free-Run Timer  
6.Setting  
6. Setting  
Table 6-1 Setting Required in Order to Use the Free-run Timer  
Setting  
Procedures *  
Setting  
Setting Registers  
Setting of the initialization conditions of the timer  
See 7.4  
Setting of the count clock  
See 7.1  
Selection of the internal clock  
Timer control register (TCCS0-TCCS7)  
Selection of the external clock  
Start the count operation  
See 7.2  
See 7.3  
In the case of the external clock  
Set the clock input pin (CK) as the input.  
Port function register (PFRxy.z)  
Extra port function register (EPFRxy.z)  
See 7.2  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-2 Setting Required to Enable the Free-run Timer Interrupt  
Setting  
Procedures *  
Setting  
Setting Registers  
Setting of the free-run timer interrupt vector,  
and the free-run timer interrupt level  
See “Chapter 24 Interrupt Control (Page  
No.311)”.  
See 7.5  
See 7.7  
Setting of the free-run timer interrupt  
Clearing interrupt requests  
Timer control register (TCCS0-TCCS7)  
Enabling interrupt requests  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-3 Setting Required to Stop the Free-run Timer  
Setting  
Procedures *  
Setting  
Setting Registers  
Timer control register (TCCS0-TCCS7)  
Setting of the free-run timer stop bit  
See 7.8  
*: For the setting procedure, refer to the section indicated by the number.  
741  
 
Chapter 35 Free-Run Timer  
7.Q & A  
7. Q & A  
7.1 What are the types of the internal clock, and how do I select?  
There are 4 types of internal clocks, and these are set by the clock selection bit (TCCS.ECLK) and the count  
clock bit (TCCS.CLK [1:0]).  
Setting  
Count period  
=
F
Internal clock  
Clock selection  
Bit (ECLK)  
Count clock bit  
(CLK [1:0])  
CLKP  
F
= 16MHz  
CLKP  
32MHz  
To select F  
/4  
Set to “0”  
Set to “0”  
Set to “0”  
Set to “0”  
Sets to “00”  
Set to “01”  
Set to “10”  
Set to “11”  
125 ns  
250 ns  
CLKP  
To select F  
To select F  
To select F  
/16  
/32  
/64  
0.5 µs  
1 µs  
1 µs  
2 µs  
4 µs  
CLKP  
CLKP  
CLKP  
2 µs  
7.2 How do I select the external clock?  
Set with clock selection bits (TCCS.ECLK), data direction bits, and (extra) port function bits.  
To use the external  
clock input  
Count  
Cycle  
Over 2/F  
Setting  
Pins  
CK0-  
Free-run Timer 0-7  
The clock  
selection  
bit (ECLK)  
to “1”  
The port function bit The extra port  
(PFRxy.z)  
to “1”  
CLKP  
function bit  
(EPFRxy.z}  
to “1”  
CK7  
7.3 How do I enable / disable the count operation of the free-run timer?  
Set with count operation bits (TCCS.STOP).  
Operation  
Count operation bit (STOP)  
To enable the free-run timer  
To stop the free-run timer  
Set to “0”  
Set to “1”  
742  
   
Chapter 35 Free-Run Timer  
7.Q & A  
7.4 How do I clear the free-run timer?  
You can clear the free-run timer by performing the following operations:  
• Set with clear bit (TCCS.CLR).  
Operation  
Clear bit (CLR)  
To clear the free-run timer  
Write “1”  
• How to clear the free-run timer when the free-run timer value and the compare-register value match  
Set with the timer initialization condition bit (TCCS.MODE).  
Operation  
Timer initialization condition bit (MODE)  
To clear the free-run timer at the compare-match  
Set to “1”  
The setting of the output compare is also required. (See “Chapter 37 Output Compare (Page No.759)”.)  
• Reset.  
When you reset (the INIT pin input, the watchdog reset, the software reset), the free-run timer is cleared.  
• Write “0000 ” while the free-run timer is stopped.  
H
The count value will be set to “0000 ”, when “0000 ” is written while the free-run timer is stopped.  
H
H
• With the overflow of the free-run timer, the count value returns to “0000 ”.  
H
7.5 What interrupt registers are used?  
Setting of the free-run timer interrupt vector and the free-run timer interrupt level  
The relationship among the free-run timer number, interrupt levels and vectors is shown in the table below.  
See “Chapter 24 Interrupt Control (Page No.311)” about the details of interrupt levels and interrupt vectors.  
Number  
Interrupt Vectors (default)  
Interrupt level setting bits (ICR[4:0])  
#40  
Free-run Timer 0  
Address: 0FFF5Ch  
Interrupt level register (ICR12)  
Address: 0044Ch  
#41  
Free-run Timer 1  
Free-run Timer 2  
Free-run Timer 3  
Free-run Timer 4  
Free-run Timer 5  
Free-run Timer 6  
Free-run Timer 7  
Address: 0FFF58h  
#42  
Address: 0FFF54h  
Interrupt level register (ICR13)  
Address: 0044Dh  
#43  
Address: 0FFF50h  
#44  
Address: 0FFF4Ch  
Interrupt level register (ICR14)  
Address: 0044Eh  
#45  
Address: 0FFF48h  
#46  
Address: 0FFF44h  
Interrupt level register (ICR15)  
Address: 0044Fh  
#47  
Address: 0FFF40h  
Since the interrupt request flag (TCCS.IVF) is not cleared automatically, make sure to clear it with software  
before returning from the interrupt process. (Write “0” in the IVF bit)  
7.6 Interrupt Types  
There is only one type of interrupt, and it is generated at the overflow of the free-run timer. (Selection is not  
required)  
7.7 How do I enable interrupts?  
Enable interrupt requests, interrupt request flag  
743  
Chapter 35 Free-Run Timer  
7.Q & A  
Use interrupt request enable bit (TCCS.IVFE) to enable interrupts.  
Interrupt request permission bit (IVFE)  
Disable interrupts  
Enable interrupts  
Set to “0”  
Set to “1”  
Use interrupt request bit (TCCS.IVF) to clear interrupt requests.  
Interrupt request bit (IVF)  
Write “0”  
Clear interrupt requests  
7.8 How do I stop the free-run timer?  
Set with count operation bit (TCCS.STOP).  
See “7.3 How do I enable / disable the count operation of the free-run timer? (Page No.742)”.  
7.9 How are the free-run timer assigned to ICU and OCU?  
• The value of Free-run timer 0 can be used as capture data by ICU0 and ICU1  
• The value of Free-run timer 1 can be used as capture data by ICU2 and ICU3  
• The value of Free-run timer 2 can be used as compare data by OCU0 and OCU1  
• The value of Free-run timer 3 can be used as compare data by OCU2 and OCU3  
• The value of Free-run timer 4 can be used as capture data by ICU4 and ICU5  
• The value of Free-run timer 5 can be used as capture data by ICU6 and ICU7  
• The value of Free-run timer 6 can be used as compare data by OCU4 and OCU5  
• The value of Free-run timer 7 can be used as compare data by OCU6 and OCU7  
744  
Chapter 35 Free-Run Timer  
8.Caution  
8. Caution  
• Clearing the free-run timer  
• When you reset (the INIT pin input, the watchdog reset, the software reset), the counter is initialized to  
“0000” and the counting is stopped.  
• When the free-run timer is cleared by software, the counter is cleared and the clear request is generated  
almost at the same time. If the counter is cleared by the compare-match, it is cleared when it is counted  
up.  
• After writing “1” in the clear bit (CLR), this request (CLR=“1”) is cleared at the same clear timing of the  
free-run timer. When the clear operation of this CLR and writing “1” to the clear bit occurs at the same  
time, the clear bit (CLR) keeps “1”, and after the next time the timer is cleared, it is cleared. (As a result,  
the free-run timer is cleared twice.)  
• The counter clear operation (the software, the overflow, and the compare-match) of the free-run timer is  
enabled while the free-run timer is counting. To clear while the free-run timer is stopped, write 0000 in  
H
the timer count data register.  
• Write to the timer data register  
When writing the value in the free-run timer, make sure to do so while the free-run timer is stopped  
(STOP=“0”), and with word access.  
• External clock operation  
• The pulse width required for the external clock is 2/F  
minimum.  
CLKP  
• When using an external clock, the timing of the compare-match output and the interrupt occurrence is the  
same as the next count clock timing after the compare-match. Therefore, to allow the compare-match  
output and interrupt generation, an external clock input of at least 1 clock is required after the compare-  
match.  
• Read/modify/write  
The interrupt request flag (IVF) is always read “1” in read/modify/write.  
• Interrupt request flag  
If the interrupt request flag set timing and clear timing are simultaneous, the flag setting operation overrides  
the flag clearing operation.  
745  
 
Chapter 35 Free-Run Timer  
8.Caution  
746  
Chapter 36 Input Capture  
1.Overview  
Chapter 36 Input Capture  
1. Overview  
Input Capture records the free-run timer count value using timing detected from an external signal. It is then  
possible to calculate the time between signals using the record of the repeated count.  
Free-run timer 0  
pin  
Edge  
Capture  
detection  
circuit  
Buffer  
2. Features  
• Format: Edge detection circuit + 16 bit buffer (capture register)  
• Quantity: 4 groups = 8 channels (input capture channels 0/1, 2/3, 4/5, 6/7)  
• Compatible timers:  
Input capture channels 0/1 use free-run timer 0  
Input capture channels 2/3 use free-run timer 1  
Input capture channels 4/5 use free-run timer 4  
Input capture channels 6/7 use free-run timer 5  
• Edge Detection: Rising/falling/both edges  
• Interrupt: Edge detection  
• Capture value: Timer count value (0000 -FFFF )  
H
H
• Timer: Uses free-run timer 0  
• Precision: 4/F , 16/F  
, 32/F  
, 64/F  
(Free-run timer count clock)  
CLKP  
CLKP  
CLKP  
CLKP  
Captured signal  
Free-run  
timer  
count value  
A
t
Buffer value  
A
747  
     
Chapter 36 Input Capture  
3.Configuration  
3. Configuration  
Figure 3-1 Configuration Diagram  
Input capture 0-1  
Edge detection polarity  
EG01-00  
ICS01:bit 1-0  
0
0
1
0
1
No edge detection  
Rising edge detection  
Falling edge detection  
Both edges detection  
0
1
1
From port  
data register  
ICE0  
ICS01:bit 4  
Capture data register 0  
IPCP0 (CP15-CP0)  
0
1
Disable interrupts  
Enable interrupts  
P14 PFR: bit 0  
GP Port  
ICU input  
0
1
0
ICP0  
ICS01:bit 6  
Capture  
Input capture 0  
Edge detection circuit  
Port read  
0
1
Interrupt request not present  
Interrupt request present  
ICU0 / P14.0  
Interrupt (#92)  
1
WRITE 0: Flag clear  
Free-run timer 0  
TCDT  
Port read  
0
1
ICP1  
ICS01:bit 7  
Capture  
Input capture 1  
Interrupt (#93)  
Edge detection circuit  
0
1
Interrupt request not present  
Interrupt request present  
ICU1 / P14.1  
WRITE 0: Flag clear  
P14 PFR: bit 1  
IPCP1 (CP15-CP0)  
GP Port  
ICU input  
0
1
ICE1  
ICS01:bit 5  
Edge detection polarity  
0
1
Disable interrupts  
Enable interrupts  
Capture data register 1  
EG11-10  
ICS01: bit 3-2  
No edge detection  
From port  
data register  
0
0
1
0
1
0
1
1
Rising edge detection  
Falling edge detection  
Both edges detection  
Figure 3-2 Register List  
Note: For information about ICR registers and interrupt vectors, see “Chapter 24 Interrupt Control (Page  
No.311)”.  
748  
 
Chapter 36 Input Capture  
4.Register  
4. Register  
4.1 IPCP: Input Capture Data Register  
A register that, using changes in an external signal as a trigger, stores the free-run timer count and can read it  
out later.  
• IPCP0 (Input capture 0): Address 0184h (Access: Half-word, Word)  
• IPCP1 (Input capture 1): Address 0186h (Access: Half-word, Word)  
• IPCP2 (Input capture 2): Address 0188h (Access: Half-word, Word)  
• IPCP3 (Input capture 3): Address 018Ah (Access: Half-word, Word)  
• IPCP4 (Input capture 4): Address 02D4h (Access: Half-word, Word)  
• IPCP5 (Input capture 5): Address 02D6h (Access: Half-word, Word)  
• IPCP6 (Input capture 6): Address 02D8h (Access: Half-word, Word)  
• IPCP7 (Input capture 7): Address 02DAh (Access: Half-word, Word)  
15  
CP15  
X
14  
CP14  
X
13  
CP13  
X
12  
CP12  
X
11  
CP11  
X
10  
CP10  
X
9
CP9  
X
8
CP8  
X
bit  
Initial value  
Attribute  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
7
CP7  
X
6
CP6  
X
5
CP5  
X
4
CP4  
X
3
CP3  
X
2
CP2  
X
1
CP1  
X
0
CP0  
X
bit  
Initial value  
Attribute  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
(For information on attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• Stores the free-run timer 0 count value for the input signal from external pins (ICU0, ICU1) using the signal  
change (edge) selected by active edge selection bits (ICS01.EG[01:00]), (ICS01.EG[11:10]).  
• Input capture 0 and input capture 1 store the count value of the free-run timer.  
749  
 
Chapter 36 Input Capture  
4.Register  
4.2 ICS: Input Capture Control Register  
A register for controlling input capture  
• ICS01 (Input capture 0-1): Address 0181h (Access: Byte)  
• ICS23 (Input capture 2-3): Address 0183h (Access: Byte)  
• ICS45 (Input capture 4-5): Address 02D1h (Access: Byte)  
• ICS67 (Input capture 6-7): Address 02D3h (Access: Byte)  
7
ICP1  
6
ICP0  
5
4
3
EG11  
0
2
EG10  
0
1
EG01  
0
0
EG00  
0
bit  
ICE1  
0
ICE0  
0
0
0
Initial value  
Attribute  
R(RM1),W  
R(RM1),W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
(For information on attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• bit7: Input capture 1 interrupt request flag  
Status  
ICP1  
Read  
Write  
0
1
No interrupt request  
Interrupt request present (edge detection present)  
Clear flag  
No effect on operation  
• When the signal change (edge) selected by the active capture edge selection bit (EG[11:10]) is detected  
on the input from an external pin, the flag becomes “1”.  
• To activate the interrupt request it is necessary to set the interrupt enable bit (ICE1=“1”).  
• If the timing of the interrupt request flag becoming “1” and the writing of “0” occur simultaneously, the  
interrupt request flag will become “1”.  
• bit6: Input capture 0 interrupt request flag  
Status  
ICP0  
Read  
Write  
0
1
No interrupt request  
Interrupt request present  
Clear flag  
No effect on operation  
• When the signal change selected by the active capture edge selection bit (EG[01:00]) is detected on the  
input from an external pin (CS0), the flag becomes “1”.  
• To activate the interrupt request, the interrupt request permission setting (ICE1=“1”) is necessary.  
• If the timing of the interrupt request flag becoming “1” and the writing of “0”occur simultaneously, the  
interrupt request flag will become “1”.  
• bit5: Input capture 1 interrupt request permission  
ICE1  
Operation  
0
1
Interrupt disabled  
Interrupt enabled  
• If input capture 1 interrupt request permission bit is set to “1”, input capture 1 interrupt request ICP1 will  
be enabled.  
• bit4: Input capture 0 interrupt request permission  
ICE0  
Operation  
0
1
Interrupt disabled  
Interrupt enabled  
• If input capture 0 interrupt request permission bit is set to “1”, input capture 0 interrupt request ICP0 will  
be enabled.  
750  
Chapter 36 Input Capture  
4.Register  
• bit3-bit2: Input capture 1 active edge selection  
EG11  
EG10  
Edge selection  
0
0
1
1
0
1
0
1
Stop input capture  
Rising edge  
Falling edge  
Both edges (rising edge and falling edge)  
• Select the active capture edge for the input capture signal from external pin (ICU1)  
• If the active edge selection bit is “00”, input capture 1 is stopped.  
• bit1-bit0: Input capture 0 active edge selection  
EG01  
EG00  
Edge selection  
0
0
1
1
0
1
0
1
Stop input capture  
Rising edge  
Falling edge  
Both edges (rising edge and falling edge)  
• Select the active capture edge for the input capture signal for external pin (ICU0).  
• When the active edge selection bit is “00”, input capture 0 is stopped.  
751  
Chapter 36 Input Capture  
5.Operation  
5. Operation  
The input capture operation is described below.  
5.1 Capture Timing, Interrupt Timing  
Input capture  
(1)  
Peripheral  
clock (CLKP)  
(2)  
Active edge  
Free-run timer 0  
Capture register  
N
N+1  
(3)  
N+1  
Interrupt  
request  
(4)  
FFFFh  
Free-run  
timer 0  
count  
0000 h  
Reset  
Time  
Input  
capture  
Interrupt  
request  
(1) Rising edge of input signal  
(2) Internal signal generated by edge detection (synchronous with peripheral clock)  
(3) Store free-run timer value in capture register (capture)  
(4) Input capture interrupt generation (ICU0-ICU1=“1”)  
752  
 
Chapter 36 Input Capture  
5.Operation  
5.2 Input Capture Edge Specification and Operation  
Overflow  
(IVF)  
FFFFh  
Count value C  
Free-run  
timer 0  
count value  
Count value B  
Count value A  
Count value D  
0000 h  
Time  
Reset  
Input capture  
(1)  
(2)  
Count value A  
Capture data  
register  
Rising  
edge  
Indeterminate  
Interrupt  
request  
(3)  
Input capture  
(4)  
(5)  
Count value C  
Capture data  
register  
Falling  
edge  
Indeterminate  
Interrupt  
request  
(6)  
Input capture  
(7)  
(11)  
(8)  
Count value B  
Clearing of flags in software  
(12)  
Capture data  
register  
Both  
edges  
Indeterminate  
Count value D  
Interrupt  
request  
(9)  
(13)  
(10)  
• When specifying rising edge  
(1) Detection of rising edge of input signal  
(2) Storage of free-run timer value in capture register (capture)  
(3) Input capture interrupt generation  
• When specifying falling edge  
(4) Detection of input signal falling edge  
(5) Storage of free-run timer value in capture register (capture)  
(6) Input capture interrupt generation  
• Both edges  
(7) Detection of input signal rising edge  
(8) Storage of free-run timer value in capture register (capture)  
(9) Input capture interrupt generation  
(10) Clear interrupt request flag (ICS01.ICP0), (ICS01.ICP1) in software  
(11) Detection of input signal falling edge  
(12) Storage of free-run timer value in capture register (capture)  
(13) Input capture interrupt generation  
753  
Chapter 36 Input Capture  
6.Settings  
6. Settings  
Table 6-1 Settings Necessary for Using Input Capture  
Setting  
procedure*  
Settings  
Setting register  
Free-run timer settings  
–
See “Chapter 35 Free-Run Timer (Page No.733)”  
Free-run timer activation  
Port function register (PFR14.0 - PFR14.7)  
Extra port function register (EPFR14.0 -  
EPFR14.7)  
Input pin ICU0-ICU7 settings  
7.2  
7.1  
Input capture control register (ICS01, ICS23,  
ICS45, ICS67)  
Active edge polarity selection for external input  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-2 Required Settings for ICU Interrupt  
Setting  
procedure*  
Settings  
Settings register  
Input Capture interrupt vector,  
Input capture interrupt level settings  
See “Chapter 24 Interrupt Control (Page No.311)”  
7.3  
7.5  
Input capture interrupt settings  
Interrupt request clear  
Interrupt request permission  
Input capture control register (ICS01, ICS23,  
ICS45, ICS67)  
*: For the setting procedure, refer to the section indicated by the number.  
754  
 
Chapter 36 Input Capture  
7.Q&A  
7. Q&A  
7.1 What are the varieties of active edge polarity for external input, and how do I select  
them?  
The active edge polarity varieties consist of rising, falling, and both, for a total of 3, and are set using the  
external input active edge selection bit (ICS01.EG[01:00]) and (ICS01:EG[11:10]), (ICS23.EG[01:00]) and  
(ICS23:EG[11:10]), (ICS45.EG[01:00]) and (ICS45:EG[11:10]), (ICS67.EG[01:00]) and (ICS67:EG[11:10]).  
External input active edge polarity bit  
Operation  
(EG[01:00]), (EG[11:10])  
To select rising edge  
To select falling edge  
To select both edges  
Select “00”  
Select “10”  
Select “11”  
7.2 What about setting the external input pins (ICU0-7)?  
Use the port function register and extra port function bits (PFR14.x/EPFR14.x).  
Operation  
Port function (PFR14.x)  
Set PFR14.0 to “1”  
Set PFR14.1 to “1”  
Set PFR14.2 to “1”  
Set PFR14.3 to “1”  
Set PFR14.4 to “1”  
Set PFR14.5 to “1”  
Set PFR14.6 to “1”  
Set PFR14.7 to “1”  
Extra Port function (EPFR14.x)  
Set EPFR14.0 to “0”  
Set EPFR14.1 to “0”  
Set EPFR14.2 to “0”  
Set EPFR14.3 to “0”  
Set EPFR14.4 to “0”  
Set EPFR14.5 to “0”  
Set EPFR14.6 to “0”  
Set EPFR14.7 to “0”  
To set it to the external input pins (ICU0)  
To set it to the external input pins (ICU1)  
To set it to the external input pins (ICU2)  
To set it to the external input pins (ICU3)  
To set it to the external input pins (ICU4)  
To set it to the external input pins (ICU5)  
To set it to the external input pins (ICU6)  
To set it to the external input pins (ICU7)  
Remark: When setting the Extra port function register EPFR14.x to “1” the corresponding input capture macro  
is internally connected to the corresponding LIN-USART macro for LIN Sync Field measurement. Hence, with  
this setting the corresponding ICU channel is not available as external input.  
7.3 What about interrupt-related registers?  
Input capture interrupt vector and input capture interrupt level settings  
The relationship between input capture number, interrupt level, and vector is explained in the following table.  
For more information on interrupt level and interrupt vectors, see “Chapter 24 Interrupt Control (Page  
No.311)”.  
Number  
Interrupt vector (Default)  
Interrupt level setting bit (ICR[4:0])  
#92  
Input Capture 0  
Address: 0FFE8Ch  
Interrupt level register (ICR38)  
Address: 0466h  
#93  
Input Capture 1  
Input Capture 2  
Input Capture 3  
Input Capture 4  
Input Capture 5  
Address: 0FFE88h  
#94  
Address: 0FFE84h  
Interrupt level register (ICR39)  
Address: 0467h  
#95  
Address: 0FFE80h  
#96  
Address: 0FFE7Ch  
Interrupt level register (ICR40)  
Address: 0468h  
#97  
Address: 0FFE78h  
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Chapter 36 Input Capture  
7.Q&A  
#98  
Input Capture 6  
Input Capture 7  
Address: 0FFE74h  
Interrupt level register (ICR41)  
Address: 0469h  
#99  
Address: 0FFE70h  
Interrupt request flags (ICS01.ICP0), (ICS01.ICP1), (ICS23.ICP0), (ICS23.ICP1), (ICS45.ICP0), (ICS45.ICP1),  
(ICS67.ICP0), (ICS67.ICP1) are not automatically cleared, so please set the input capture interrupt request  
flag (ICP1, ICP0) to “0” to clear them before returning from interrupt processing.  
7.4 What are the types of interrupts?  
There is only one kind of interrupt, and it is generated by input signal edge detection.  
7.5 How do I enable interrupts?  
Interrupt request permission, interrupt request flag  
Interrupts are enabled via interrupt request permission bit (ICS01.ICE0), (ICS01.ICE1), (ICS23.ICE0),  
(ICS23.ICE1), (ICS45.ICE0), (ICS45.ICE1), (ICS67.ICE0), (ICS67.ICE1).  
Interrupt request permission bit (ICE0), (CE1)  
Disable interrupts  
Enable interrupts  
Set to “0”  
Set to “1”  
Clearing of interrupt requests is done using interrupt request bit (ICS01.ICP0), (ICS01.ICP1), (ICS23.ICP0),  
(ICS23.ICP1), (ICS45.ICP0), (ICS45.ICP1), (ICS67.ICP0), (ICS67.ICP1).  
Interrupt request bit (ICP0), (ICP1)  
Interrupt request clear  
Write “0”  
756  
Chapter 36 Input Capture  
7.Q&A  
7.6 How do I measure the pulse width of the input signal?  
• "H" Width measurement:  
Specify both edges for edge detection.  
First detect the rising edge, then detect the falling edge.  
Pulse width = {value recorded during falling (input capture register value)  
+ “10000h” x Overflow frequency  
– value recorded during rising (input capture register value)}  
x Count clock width of free-run timer  
Example: value recorded during falling = 2320h, Value recorded during rising = A635h,  
Overflow frequency = 1, count clock = 125ns  
==> pulse width = (2320h+10000h-A635h) x 125ns = 3997.375us  
• Cycle measurement:  
Specify rising (or falling) for edge detection.  
Detect edge 2 times.  
Cycle = {Second recorded value (input capture register value)  
+ “10000h” x Overflow frequency  
– First recorded value (input capture register value)}  
x Count clock width of free-run timer  
757  
Chapter 36 Input Capture  
8.Caution  
8. Caution  
• Input capture register  
The value of the input capture register during reset is indeterminate.  
Read out of the input capture register must always be done using 16 or 32 bit access.  
• Read modify write  
Input capture interrupt request bit (ICP0), (ICP1) will be read as “1” when read with read modify write.  
758  
 
Chapter 37 Output Compare  
1.Overview  
Chapter 37 Output Compare  
1. Overview  
Output compare is a feature that compares the value set to the compare register with the count value of the  
free-run timer, and reverses the level of the pins when they are equal.  
Pin 0
Match  
Compare0  
Compare  
Clear  
Latch  
Latch  
Toggle  
Output  
Free-run Timer  
Compare1  
Pin 1
Compare  
Match  
2. Features  
• Output wave form: Toggle output 4 channel  
Trigger output 4 channel  
T1 or T(max.)  
T1  
(OCU0 Pin/OCU2 Pin)  
(OCU1 Pin/OCU3 Pin)  
T2  
PWM Output  
2 channel  
(OCU1/OCU3)  
T2  
T1  
• Format:  
16 bit compare register + Compare circuit  
4 groups = 8 channels (output compare channels 0/1, 2/3, 4/5, 6/7)  
• Quantity:  
• Compatible timers:Output compare channels 0/1 use free-run timer 2  
Output compare channels 2/3 use free-run timer 3  
Output compare channels 4/5 use free-run timer 6  
Output compare channels 6/7 use free-run timer 7  
• Operation on compare match:  
• Reversal of pin output value (toggle output)  
• Free-run timer clear  
• Interrupt generation  
• Count precision: 4/F  
, 16/F  
, 32/ F  
, 64/ F  
(dependent on free-run timer)  
CLKP  
CLKP  
CLKP  
CLKP  
• Toggle change width (T): 1 x count precision - 10000 x count precision  
H
• Interrupt:  
• Others:  
Compare-match interrupt  
Setting of initial output level value is possible (“H”/“L”)  
Pins not used for OCU output can be used as general-use ports  
759  
       
Chapter 37 Output Compare  
3.Configuration Diagram  
3. Configuration Diagram  
Figure 3-1 Configuration Diagram  
Output Compare 0-1  
ICE0 OCS01: bit4  
Disable interrupts  
0
1
Enable interrupts  
ICP0  
OCS01: bit6  
0
1
Interrupt request not present  
Interrupt request present  
OCU0 Interrupt (#100)  
Write 0: Flag clear  
External clock (for free-run timer 2)  
General-use port read  
CST0 OCS01: bit0  
Disable compare operation  
OT D0  
0
1
0
OCS01: bit8  
Low fixed  
High fixed  
Compare register 0  
1
Enable compare operation  
PFR15.0  
General-use Port  
OUT0  
0
1
OCCP0  
* Compare operation only  
writable when stopped  
0
IVF  
TCCS2: bit6  
From general-use  
port register  
0
1
Overflow not present  
Overflow present  
Com-  
pare  
OCU0/TOT0/P15.0  
OCU1/TOT1/P15.1  
Latch  
1
0 0  
Match -> Latch  
reversal  
Free-run timer 2  
CMOD  
0
OCS01: bit12  
OCCP1 match alone inverts OP1 latch.  
TCDT2  
1
1
OCCP0 or OCCP1 match inverts OP1 latch.  
0
Match -> Latch reversal  
1
CLR TCCS2:bit2  
Com-  
pare  
1
OR  
0
1
No effect  
Clear  
Latch  
From general-use  
port register  
0
Compare register 0  
PFR15.1  
OT D1 OCS01: bit9  
0
1
General-use Port  
OUT1  
0
1
Low fixed 1c  
High fixed  
OCCP1  
* Compare operation only  
writable when stopped  
CST1 OCS01: bit1  
0
1
Disable compare operation  
General-use port read  
Enable compare operation  
External clock (for free-run timer 2)  
0
ICP1 OCS01: bit7  
OCU1 Interrupt (#100)  
0
1
Interrupt request not present  
Interrupt request present  
1
TCCS0 : bit 3  
MODE  
0
ICE1  
0
1
Write 0: Flag clear  
OCS01: bit5  
Disable interrupts  
Enable interrupts  
No clear on compare-match  
Clear on compare-match  
1
Figure 3-2 Register List  
Note: For information about ICR registers and interrupt vectors, see “Chapter 24 Interrupt Control (Page  
No.311)”.  
760  
 
Chapter 37 Output Compare  
4.Registers  
4. Registers  
4.1 OCS: Output Control Register  
A register for controlling the operation of output compare.  
• OCS01 (Output compare 0-1): Address 018Ch (Access: Byte, Half-word, Word)  
• OCS23 (Output compare 2-3): Address 018Eh (Access: Byte, Half-word, Word)  
• OCS45 (Output compare 4-5): Address 02DCh (Access: Byte, Half-word, Word)  
• OCS67 (Output compare 6-7): Address 02DEh (Access: Byte, Half-word, Word)  
15  
14  
13  
12  
CMOD  
0
11  
10  
9
OTD1  
0
8
bit  
–
1
–
1
–
1
–
1
–
1
OTD0  
0
Initial Value  
Attribute  
R1/W1  
R1/W1  
R1/W1  
R/W  
R1/W1  
R1/W1  
R/W  
R/W  
7
ICP1  
6
ICP0  
5
4
3
2
1
CST1  
0
0
CST0  
0
bit  
ICE1  
0
ICE0  
0
–
1
–
1
0
0
Initial Value  
Attribute  
R(RM1),W  
R(RM1),W  
R/W  
R/W  
R1/W1  
R1/W1  
R/W  
R/W  
(For information on attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• bit15-bit13: undefined Writing does not affect the operation. The read out value is “1”.  
• bit12: Reverse Mode  
CMOD  
Operation Mode  
0
Independent operation (the output level reversal operation of pins OCU0-OCU1 is independent)  
Combined operation  
1
(OCU1 output pin level is inverted when output compare 0 or output compare 1 is matched in the  
compare operation.)  
• Specifies the output level reversal operation of pin OCU1 when free-run timer count value TCDT0  
matches compare registers OCCP0, OCCP1.  
• When the reverse mode bit is set to “1”, the operation is as follows.  
OCU0 pin: output reverses when free-run timer TCDT2 matches compare register 0 (OCCP0)  
OCU1 pin: output reverses when free-run timer TCDT2 matches compare register 1 (OCCP1)  
• When the reverse mode bit is set to “0”, the operation is as follows.  
OCU0 pin: output reverses when free-run timer TCDT2 matches compare register 0(OCCP0)  
OCU1 pin: output reverses when free-run timer TCDT2 matches compare register 0 (OCCP0) or  
compare register 1 (OCCP1)  
Note: Reversal mode does not allow interrupts, even with cooperative operation (CMOD=“1”).  
• For output from pins OCU0, OCU1, registers PFR15.0, PFR15.1 must be set.  
• bit11-bit10: Undefined Writing does not affect the operation. The read value is “1”.  
• bit9: Pin-level settings (output compare 1)  
OTD1  
Operation  
0
1
Set the output level of pin OCU1 to “L”  
Set the output level of pin OCU1 to “H”  
To perform output on pin OCU1, general-purpose port settings must be performed.  
• bit8: Pin-level settings (output compare 0)  
OTD0  
Operation  
0
1
Set the output level of pin OCU0 to “L”  
Set the output level of pin OCU0 to “H”  
• To perform output on pin OCU0, general-purpose port settings must be performed.  
761  
 
Chapter 37 Output Compare  
4.Registers  
• bit7: Interrupt request flag (output compare 1)  
Status  
ICP1  
Read  
Write  
0
1
Interrupt request not present  
Interrupt request present  
Clear flag (ICP1)  
No effect on operation  
• If free-run timer count value TCDT0 matches the output compare register OCCP1, ICP1 becomes “1”.  
• Interrupt request is enabled when the interrupt permission bit (ICP1) is set to “1”.  
• If the interrupt request flag becoming “1” and writing of “0” to it happen at the same time, the interrupt  
request flag will become “1” (flag setting is given priority).  
• When using an external clock as the free-run timer operation clock, at least one external clock input is  
necessary after compare match for output compare-match output and interrupt generation.  
• bit6: Interrupt request flag (output compare 0)  
Status  
ICP0  
Read  
Interrupt request not present  
Interrupt request present  
Write  
0
1
Clear flag (ICP0)  
No effect on operation  
• If free-run timer count value TCDT0 matches output compare register OCCP0, ICP0 becomes “1”.  
• Interrupt request is enabled when the interrupt permission bit (ICP0) is “1”.  
• If the interrupt request flag becoming “1” and writing of “0” to it happen at the same time, the interrupt  
request flag will become “1” (flag setting is given priority).  
• When using an external clock as the free-run timer operation clock, at least one external clock input is  
necessary after compare match for output compare-match output and interrupt generation.  
• bit5: Interrupt request enable (output compare 1)  
ICE1  
Status  
Status  
0
1
Disable output compare 1 interrupt requests  
Enable output compare 1 interrupt requests  
• bit4: Interrupt request enable (output compare 0)  
ICE0  
0
1
Disable output compare 0 interrupt requests  
Enable output compare 0 interrupt requests  
• bit3-bit2: Undefined Writing does not affect the operation. The read value is always “1”.  
• bit1: Enable operation requests (output compare 1)  
CST1  
Operation  
0
1
Stop operation of output compare 1  
Enable operation of output compare 1  
• A bit that enables a comparison operation between the free-run timer count value and the output  
compare register (TCDT0 and OCCP1).  
• Before enabling the operation, always set a value to compare register OCCP1.  
• If you stop the free-run timer, output compare also stops.  
762  
Chapter 37 Output Compare  
4.Registers  
• bit0: Enable operation requests (output compare 0)  
CST0  
Operation  
0
1
Disable output compare 0 operation  
Enable output compare 0 operation  
• A bit that enables a comparison operation between the free-run timer count value and the output  
compare register (TCDT0 and OCCP0).  
• Before enabling the operation, always set a value to compare register OCCP0.  
• If you stop the free-run timer, output compare also stops.  
763  
Chapter 37 Output Compare  
4.Registers  
4.2 OCCP: Compare Register  
Register that sets the value to be compared to the 16 bit free-run timer count value.  
• OCCP0 (Compare 0): Address 0190h (Access: Half-word, Word)  
• OCCP1 (Compare 1): Address 0192h (Access: Half-word, Word)  
• OCCP2 (Compare 2): Address 0194h (Access: Half-word, Word)  
• OCCP3 (Compare 3): Address 0196h (Access: Half-word, Word)  
• OCCP4 (Compare 4): Address 02E0h (Access: Half-word, Word)  
• OCCP5 (Compare 5): Address 02E2h (Access: Half-word, Word)  
• OCCP6 (Compare 6): Address 02E4h (Access: Half-word, Word)  
• OCCP7 (Compare 7): Address 02E6h (Access: Half-word, Word)  
15  
14  
13  
12  
11  
10  
9
8
bit  
C15  
C14  
C13  
C12  
C11  
C10  
C9  
C8  
Initial  
Value  
X
X
X
X
X
X
X
X
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
7
6
5
4
3
2
1
0
bit  
C7  
C6  
C5  
C4  
C3  
C2  
C1  
C0  
Initial  
Value  
X
X
X
X
X
X
X
X
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(For information on attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• Compares the compare registers OCCP0, OCCP1 to free-run timer 2 count value TCD2.  
• Compares the compare registers OCCP2, OCCP3 to free-run timer 3 count value TCD3.  
• Compares the compare registers OCCP4, OCCP5 to free-run timer 6 count value TCD6.  
• Compares the compare registers OCCP6, OCCP7 to free-run timer 7 count value TCD7.  
764  
Chapter 37 Output Compare  
5.Operation  
5. Operation  
5.1 Output Compare Output (Independent Reversal) CMODE=“0”  
Peripheral  
clock (CLK)  
(6)  
Free-run timer 2  
BFFFh  
0000  
0001  
BFFEh  
Compare register value  
BFFFh  
(5)  
Compare-match signal  
OCU pin output  
(7)  
Interrupt  
request  
(8)  
BFFFh  
Free-run  
timer 0  
count  
(4)  
0000 h  
Time  
(6)  
Compare-match clear  
Compare-match clear  
Free-run timer 2 clear  
(1)  
(2)  
BFFFh  
Compare register value  
(3)  
CST  
OCU Output  
(7)  
Clear in  
software  
(8)  
Interrupt request  
(1) Free-run timer clear/reset  
(2) Compare value setting  
(3) Enable compare operation (CST=“1”)  
(4) Free-run timer count up (example of 1 clock in 4)  
(5) Compare free-run timer value and compare value and match (compare match).  
(6) Free-run timer clear from compare match (free run timer 2)  
(7) OCU output level reversal  
(8) Compare match interrupt request generation  
765  
 
Chapter 37 Output Compare  
5.Operation  
5.2 Output Compare Output (Cooperative Reversal) CMODE=“1”  
(9)  
BFFFh  
Free-run  
timer 0  
count  
(8)  
(5)  
4000h  
(4)  
0000h  
Time  
Compare-match clear  
Compare-match clear  
(1)  
(10)  
Free-run timer 2 clear  
(2)  
BFFFh  
(2)  
Compare register 0  
Compare register 1  
4000h  
(3)  
(3)  
CST 0  
CST 1  
(11)  
(11)  
OCU0 output  
CMOD=“0”  
OCU1 output  
(6)  
(6)  
OCU0 output  
CMOD=“1”  
OCU1 output  
Clear in software  
(11)  
Interrupt request 0  
Interrupt request 1  
Clear in software  
(7)  
(1) Free-run timers clear/reset  
(2) Compare 0 and compare 1 value settings  
(3) Enable compare operation  
(4) Free-run timer count up  
(5) Compare 1 match  
(6) OCU1 output level reversal  
(7) Compare 1 match interrupt  
(8) Free-run timer count up  
(9) Compare 0 match  
(10) OCU0 output level reversal  
When CMOD=“1”, OCU1 output level also reverses  
(11) Compare 0 match interrupt  
766  
Chapter 37 Output Compare  
6.Settings  
6. Settings  
Table 6-1 Settings Necessary for Using Output Compare  
Setting  
Procedure*  
Settings  
Setting Register  
Free-run timer setting  
Compare value setting  
See “Chapter 35 Free-Run Timer (Page No.733)”  
Compare register (OCCP0 - OCCP7)  
---  
See 7.1  
Compare mode setting  
See 7.2  
Output control register  
(OCS01, OCS23, OCS45, OCS67)  
Stop compare operation  
See 7.3  
See 7.4  
Set initial level of compare pin output  
Port function register (PFR15.0 - PFR15.7)  
Extra port function register (EPFR15.0 - EPFR15.7)  
Set OCU0-OCU7 pins to output  
See 7.5  
See 7.6  
See 7.7  
Timer control register  
(TCCS2, TCCS3, TCCS6, TCCS7)  
See “Chapter 35 Free-Run Timer (Page No.733)”  
Clear free-run timer  
Output control register  
(OCS01, OCS23, OCS45, OCS67)  
Enable compare operation (activate)  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-2 Item Necessary to Clear the Free-run Timer upon Compare-match.  
Setting  
Procedure*  
Setting  
Setting Register  
Timer control register  
Select free-run timer clear mode  
(TCCS2, TCCS3, TCCS6, TCCS7)  
See 7.8  
See “Chapter 35 Free-Run Timer (Page No.733)”  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-3 Item Necessary for Performing Interrupts  
Setting  
Procedure*  
Setting  
Setting register  
Output compare interrupt vector,  
output compare interrupt level setting  
See “Chapter 24 Interrupt Control (Page No.311)”  
See 7.9  
Output compare interrupt setting  
Clear interrupt request  
Enable interrupt request  
Output control register  
(OCS01, OCS23, OCS45, OCS67)  
See 7.11  
*: For the setting procedure, refer to the section indicated by the number.  
767  
 
Chapter 37 Output Compare  
7.Q & A  
7. Q & A  
7.1 How do I set the compare value?  
Write the compare value to compare registers OCCP0 - OCCP7.  
7.2 How do I set the compare mode? (for OCU1, OCU3, OCU5, OCU7 output)  
This is done using compare mode bits (OCS01.CMOD), (OCS23.CMOD), (OCS45.CMOD), (OCS67.CMOD).  
Operation  
Compare mode bit  
To reverse OCU1 output using a compare-match from only free-run timer 2  
and compare register 1  
Set (OCS01.CMOD) bit to “0”  
To reverse OCU3 output using a compare-match from only free-run timer 3  
and compare register 3  
Set (OCS23.CMOD) bit to “0”  
Set (OCS45.CMOD) bit to “0”  
Set (OCS67.CMOD) bit to “0”  
Set (OCS01.CMOD) bit to “1”  
Set (OCS23.CMOD) bit to “1”  
Set (OCS45.CMOD) bit to “1”  
Set (OCS67.CMOD) bit to “1”  
To reverse OCU5 output using a compare-match from only free-run timer 6  
and compare register 5  
To reverse OCU7 output using a compare-match from only free-run timer 7  
and compare register 7  
To reverse OCU1 output using a compare-match from free-run timer 2 and  
compare register 0, as well as free-run timer 0 and compare register 1  
To reverse OCU3 output using a compare-match from free-run timer 3 and  
compare register 2, as well as free-run timer 1 and compare register 3  
To reverse OCU5 output using a compare-match from free-run timer 6 and  
compare register 4, as well as free-run timer 4 and compare register 1  
To reverse OCU7 output using a compare-match from free-run timer 7 and  
compare register 6, as well as free-run timer 5 and compare register 3  
With no relation to CMOD bit,  
OCU0 output is reversed by a compare-match between free-run timer 2 and compare register 0 only.  
OCU2 output is reversed by a compare-match between free-run timer 3 and compare register 2 only.  
OCU4 output is reversed by a compare-match between free-run timer 6 and compare register 4 only.  
OCU6 output is reversed by a compare-match between free-run timer 7 and compare register 6 only.  
7.3 How do I enable/disable the compare operation?  
Set it via the compare operation permission bit (OCS01.CST[1:0]), (OCS23.CST[1:0]), (OCS45.CST[1:0]),  
(OCS67.CST[1:0]).  
Operation  
Compare  
Compare 0  
Compare 1  
Compare 2  
Compare 3  
Compare 4  
Compare 5  
Compare 6  
Compare 7  
Compare operation permission bit  
Set (OCS01.CST[0]) to “0”  
Set (OCS01.CST[1]) to “0”  
Set (OCS23.CST[0]) to “0”  
Set (OCS23.CST[1]) to “0”  
Set (OCS45.CST[0]) to “0”  
Set (OCS45.CST[1]) to “0”  
Set (OCS67.CST[0]) to “0”  
Set (OCS67.CST[1]) to “0”  
To stop (disable) the compare operation  
768  
 
Chapter 37 Output Compare  
7.Q & A  
Compare 0  
Compare 1  
Compare 2  
Compare 3  
Compare 4  
Compare 5  
Compare 6  
Compare 7  
Set (OCS01.CST[0]) to “1”  
Set (OCS01.CST[1]) to “1”  
Set (OCS23.CST[0]) to “1”  
Set (OCS23.CST[1]) to “1”  
Set (OCS45.CST[0]) to “1”  
Set (OCS45.CST[1]) to “1”  
Set (OCS67.CST[0]) to “1”  
Set (OCS67.CST[1]) to “1”  
To enable compare operation  
7.4 How do I set the initial level of the compare pin output?  
Set it with compare pin output specification bit (OCS01.OTD[1:0]), (OCS23.OTD[1:0]), (OCS45.OTD[1:0]),  
(OCS67.OTD[1:0]).  
Operation  
Compare pin output specification bit  
Set (OCS01.OTD0) to “0”  
Set (OCS01.OTD0) to “1”  
Set (OCS01.OTD1) to “0”  
Set (OCS01.OTD1) to “1”  
Set (OCS23.OTD0) to “0”  
Set (OCS23.OTD0) to “1”  
Set (OCS23.OTD1) to “0”  
Set (OCS23.OTD1) to “1”  
Set (OCS45.OTD0) to “0”  
Set (OCS45.OTD0) to “1”  
Set (OCS45.OTD1) to “0”  
Set (OCS45.OTD1) to “1”  
Set (OCS67.OTD0) to “0”  
Set (OCS67.OTD0) to “1”  
Set (OCS7.OTD1) to “0”  
Set (OCS67.OTD1) to “1”  
To set compare 0 pin to “L”  
To set compare 0 pin to “H”  
To set compare 1 pin to “L”  
To set compare 1 pin to “H”  
To set compare 2 pin to “L”  
To set compare 2 pin to “H”  
To set compare 3 pin to “L”  
To set compare 3 pin to “H”  
To set compare 4 pin to “L”  
To set compare 4 pin to “H”  
To set compare 5 pin to “L”  
To set compare 5 pin to “H”  
To set compare 6 pin to “L”  
To set compare 6 pin to “H”  
To set compare 7 pin to “L”  
To set compare 7 pin to “H”  
769  
 
Chapter 37 Output Compare  
7.Q & A  
7.5 How do I set the output for compare pins OCU0-OCU7?  
Set it with port function register (PFR15[7:0]).  
Operation  
Port function bit  
Extra port function bit  
Set EPFR15.0 bit to “0”  
Set EPFR15.1 bit to “0”  
Set EPFR15.2 bit to “0”  
Set EPFR15.3 bit to “0”  
Set EPFR15.4 bit to “0”  
Set EPFR15.5 bit to “0”  
Set EPFR15.6 bit to “0”  
Set EPFR15.7 bit to “0”  
To set compare 0 pin (OCU0) to output  
To set compare 1 pin (OCU1) to output  
To set compare 2 pin (OCU2) to output  
To set compare 3 pin (OCU3) to output  
To set compare 4 pin (OCU4) to output  
To set compare 5 pin (OCU5) to output  
To set compare 6 pin (OCU6) to output  
To set compare 7 pin (OCU7) to output  
Set PFR15.0 bit to “1”  
Set PFR15.1 bit to “1”  
Set PFR15.2 bit to “1”  
Set PFR15.3 bit to “1”  
Set PFR15.4 bit to “1”  
Set PFR15.5 bit to “1”  
Set PFR15.6 bit to “1”  
Set PFR15.7 bit to “1”  
7.6 How do I clear the free-run timer?  
Set it with clear bits (TCCS2.CLR), (TCCS3.CLR), (TCCS6.CLR), (TCCS7.CLR).  
Operation  
Clear Bit (CLR)  
Write “1”  
To clear the free-run timer  
For other methods, see “Chapter 35 Free-Run Timer (Page No.733)”.  
7.7 How do I enable the compare operation?  
Enable it with compare operation permission bit (OCS01.CST[1:0]), (OCS23.CST[1:0]), (OCS45.CST[1:0]),  
(OCS67.CST[1:0]).  
See “7.4 How do I set the initial level of the compare pin output? (Page No.769)”.  
7.8 How do I compare the free-run timer value with the compare register value and clear  
the free-run timer when they match?  
Do this with timer initialization condition bit (TCCS2.MODE), (TCCS3.MODE), (TCCS6.MODE),  
(TCCS7.MODE).  
Operation  
Timer initialization condition bit (MODE)  
Set (TCCS2.MODE) to “1”  
To clear free-run timer upon compare 0 match  
To clear free-run timer upon compare 2 match  
To clear free-run timer upon compare 4 match  
To clear free-run timer upon compare 6 match  
Set (TCCS3.MODE) to “1”  
Set (TCCS6.MODE) to “1”  
Set (TCCS7.MODE) to “1”  
7.9 What are the interrupt-related registers?  
Set the output compare interrupt vector and output compare interrupt level.  
The relationship between output compare number, interrupt level, and vector is shown in the following table.  
For detailed information on interrupt levels and interrupt vectors, see “Chapter 24 Interrupt Control (Page  
No.311)”.  
Number  
Interrupt vector (default)  
Interrupt level setting bit (ICR[4:0])  
Output  
#100  
Compare 0  
Address: 0FFE6Ch  
Interrupt level register (ICR42)  
Address: 046Ah  
Output  
#101  
Compare 1  
Address: 0FFE68h  
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Chapter 37 Output Compare  
7.Q & A  
Output  
#102  
Compare 2  
Address: 0FFE64h  
Interrupt level register (ICR43)  
Address: 046Bh  
Output  
#103  
Compare 3  
Address: 0FFE60h  
Output  
#104  
Compare 4  
Address: 0FFE5Ch  
Interrupt level register (ICR44)  
Address: 046Ch  
Output  
#105  
Compare 5  
Address: 0FFE58h  
Output  
#106  
Compare 6  
Address: 0FFE54h  
Interrupt level register (ICR45)  
Address: 046Dh  
Output  
#107  
Compare 7  
Address: 0FFE50h  
Interrupt request flags (OCS01. ICP[1:0]), (OCS23. ICP[1:0]), (OCS45. ICP[1:0]), (OCS67. ICP[1:0]), are not  
automatically cleared, so write “0” to the ICP[7:0] bit before returning from interrupt processing to clear them.  
7.10 What are the types of interrupts?  
There is only one type of interrupt, generated upon a compare-match.  
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Chapter 37 Output Compare  
7.Q & A  
7.11 How do I enable interrupts?  
Enabling of interrupts is done with interrupt request permission bit (OCS01. ICE[1:0]), (OCS23. ICE[1:0]),  
(OCS45. ICE[1:0]), (OCS67. ICE[1:0]).  
Interrupt request permission bit (ICE0, ICE1)  
Interrupt disabled  
Enable interrupts  
Set to “0”  
Set to “1”  
Interrupt requests are cleared with interrupt request bits (OCS01. ICP[1:0]), (OCS23. ICP[1:0]), (OCS45.  
ICP[1:0]), (OCS67. ICP[1:0]).  
Interrupt request bit (ICP0, ICP1)  
Interrupt request clear  
Write “0”  
7.12 Compare value calculation procedure  
• Toggle output pulse  
(Example) To output a period: A, phase difference 1/4 phase pulse  
A
OCU0  
OCU1  
Phase difference 1/4  
Formula: Compare 0 value = (A/2) / count clock  
Compare 1 value = (A/4) / count clock  
(Count clock: time set with free-run timer)  
Note: To clear free-run timer 2 on compare 0 match setting (TCCS2.MODE=“1”) and CMOD=“0” setting are necessary.  
Calculation example: A=1024us, count clock =125ns  
Compare 0 value = (1024000 / 2) / 125 - 1 = 4095 = FFFh  
Compare 1 value = (1024000 / 4) / 125 - 1 = 1023 = 7FFh  
• PWM output  
(Example) To output a period: A, duty 1/4 - 3/4 (“L”) PWM,  
A
OCU1  
1/4-3/4  
Formula: Compare 0 value = A / count clock  
Compare 1 value = (A/4) / count clock (when duty 1/4)  
(A x 3/4) / count clock (when duty 3/4)  
(count clock: time set with free-run timer)  
Note: To clear free-run timer 0 on compare 0 match setting (TCCS0.MODE=“1”) and CMOD=“1” setting are necessary.  
Calculation example: A=1024us, count clock =125ns  
Compare 0 value = 1024000 / 125 - 1 = 8191 = 1FFFh  
Compare 1 value = (1024000 / 4) / 125 - 1 = 1023 = 7FFh (when duty 1/4)  
(1024000 x 3 / 4) / 125 - 1 = 1023 = BFFh (when duty 3/4)  
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Chapter 37 Output Compare  
8.Caution  
8. Caution  
• Compare stop space during compare operation  
As shown below, for one count directly after the compare value is written to the compare register, the  
compare operation cannot be used.  
Compare  
timing  
Free-run timer count value  
N-2  
X
N+1  
N+2  
N-1  
N
N+3  
Write to compare register  
Compare register value  
N
Compare stop space  
In this case, a match signal  
will not be generated!  
• When CMOD=“1” and OCCP0=OCCP1 setting, if a compare match is generated, the port will only reverse  
once.  
• Compare registers (OCCP0 - OCCP7) are set to the initial values. Always set a value before activating  
them.  
• When specifying the output level of compare pins (OCU0 - OCU7), first stop the compare operation.  
• Output compare is synchronous with the free-run timer, so if you stop the free-run timer the compare  
operation also stops.  
• Even when reversal mode specification (CMOD) is set to “1” and the compare operation is in cooperative  
mode, interrupts are generated independently.  
• When using an external clock as the free-run timer, compare-matches and interrupts are generated with the  
following clock. To generate compare match output and interrupts, at least “1 clock division” must be input to  
the external clock free-run timer after the compare-match.  
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Chapter 37 Output Compare  
8.Caution  
774  
Chapter 38 Reload Timer  
1.Overview  
Chapter 38 Reload Timer  
1. Overview  
The reload timer uses a 16 bit down counter to detect the input signal trigger and perform a count down.  
The count length is 16 bits.  
Reload value  
Soft trigger  
Reload  
External event  
Reversal  
Latch  
Output value  
Underflow  
Internal clock  
or  
Down counter  
Pin  
External event  
ToPPG  
ToA/D  
2. Features  
Operation: 2 kinds of operation are possible  
• One-shot Operation  
Initial output level  
Reversed output level  
• Reload Operation  
Initial output level  
Reversed output level  
Format: 16 bit down counter with reload register  
Quantity: 8 (Output: 8 channels TOT[0-7])  
Clock mode: Select from two modes  
• Internal clock mode  
Count clock: CLKP/2, CLKP/8, CLKP/32, CLKP/64, CLKP/128  
Activation triggers (4 types)  
• External event clock mode  
Count clock  
: External event (TIN[7:0] pins)  
Count active edge: Rising/falling/both edges of external event  
Activation trigger: Software trigger  
Cycle  
: Cycle = count clock x (reload value + 1)  
(Example) When count clock = 16MHz, reload value = 15999  
Cycle = 62.5ns x (15999+1) = 1.0ms  
Count active edge: When in external event mode, choose from 3 types.  
• External trigger (rising /falling/both edges)  
Interrupt: Request generated by underflow  
Other 1: Counter stop in software/can be reopened  
Other 2: Control of other peripheral functions possible  
• PPG activation trigger source:  
Reload timer 0 : PPG0, PPG1  
Reload timer 1 : PPG2, PPG3  
775  
       
Chapter 38 Reload Timer  
3.Configuration  
Reload timer 2 : PPG4, PPG5  
Reload timer 3 : PPG6, PPG7  
Reload timer 4 : PPG8, PPG9  
Reload timer 5 : PPG10, PPG11  
Reload timer 6 : PPG12, PPG13  
Reload timer 7 : PPG14, PPG15  
• A/D converter activation trigger source (Reload timer 7 : A/D)  
3. Configuration  
Figure 3-1 Configuration Diagram  
Reload Timer 0 (Internal clock count)  
TIN0  
PFR14.0  
GP Port  
Reload Timer Input  
To general-purpose  
port input  
0
1
16 bit reload register  
From general-purpose  
port output  
OUTL RELD  
TMCSR:bit5, bit4  
TMRLR0  
"L" square wave during count  
0
0
1
1
0
1
0
TIN0/ICU0/P14.0  
One-shot mode  
"H" square wave during count  
"L" toggle output on count start  
"H" toggle output on count start  
Trigger (load + counter activation)  
Reload mode  
Reload/activation/stop  
TRG TMCSRx:bit0  
1
No effect  
0
1
control circuit  
Soft trigger  
Stop  
Reload  
Trigger selection  
MOD2-0  
Counter  
CNTE  
0
1
TMCSRx:bit1  
Stop count (disable output)  
Enable count  
TMCSRx: bit9-7  
Software trigger  
activation  
Ch01 -> PPG0-PPG1  
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
.
External trigger rising edge  
External trigger falling edge  
External trigger both edges  
Disabled  
Stop  
TOT0  
EPFR15.0  
OCU0 output  
TOT0 output  
0
1
Reload  
Clock source  
Underflow  
Latch,  
output  
change  
CLKP /2  
CLKP /23  
CLKP /25  
CLKP /26  
CLKP /27  
1
TMR0  
16 bit down counter (=timer)  
TOT0/OCU0/P15.0  
From general-purpose  
port output  
0
To general-purpose  
port input  
INTE TMCSRx:bit3  
CSL2-0  
TMCSRx: bit12-10  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
Disable interrupts  
Enable interrupts  
Internal clock CLKP/2  
Internal clock CLKP/23  
Internal clock CLKP/25  
(External event) *  
UF  
Underflow not present  
Underflow generation  
TMCSRx:bit2  
1
Disabled  
Timer interrupt  
(underflow)  
Internal clock CLKP/26  
Internal clock CLKP/27  
0
1
WRITE 0: Flag clear  
1
1
Disabled  
0
* For external events, see the next chart.  
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Chapter 38 Reload Timer  
3.Configuration  
Figure 3-2 Configuration Diagram  
Reload timer 0 (External event count)  
16 bit reload register  
TMRLR0  
Trigger (reload + counter activation)  
TRG TMCSR:bit0  
OUTL RELD  
TMCSR: bit5, bit4  
Reload/activation/stop  
control circuit  
0
1
No effect  
0
0
0
1
0
1
"L" square wave during count  
"H" square wave during count  
"L" toggle output on count start  
"H" toggle output on count start  
Soft trigger  
One-shot mode  
Reload mode  
1
1
Stop  
Counter  
CNTE TMCSR:bit1  
activation  
0
1
Stop count  
Enable count  
.
TIN0  
0
PFR14.0  
GP Port  
Reload Timer Input  
Reload  
Stop  
1
Ch01 -> PPG0-PPG1  
To general-purpose  
port input  
From general-purpose  
port output  
TOT0  
EPFR15.0  
OCU0 output  
TOT0 output  
0
1
Reload  
Underflow  
Latch,  
output  
change  
1
TIN0/ICU0/P14.0  
TMR0  
16 bit down counter  
TOT0/OCU0/P15.0  
Event source  
From general-purpose  
port output  
0
To general-purpose  
port input  
CSL2-0 TMCSR:bit12-10  
0
1
1
External event *  
INTE TMCSR:bit3  
Disable interrupts  
Enable interrupts  
0
1
* For internal clock, see the previous chart.  
Active edge  
MOD2-0 TMCSR:bit9-7  
0
0
1
1
X
0
1
0
1
X
----------  
0
0
0
0
1
1
Timer interrupt  
(underflow)  
Rising edge  
Falling edge  
Both edges  
Disabled  
UF  
TMCSRx:bit2  
0
1
Underflow not present  
Underflow generation  
0
WRITE 0: Flag clear  
Figure 3-3 Register List  
Note: For information about ICR registers and interrupt vectors, see “Chapter 24 Interrupt Control (Page  
No.311)”.  
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Chapter 38 Reload Timer  
4.Registers  
4. Registers  
4.1 TMCSR: Reload Timer Control Status Register  
The control status register controls the operation mode of the reload timer and interrupts.  
• TMCSR0 (Reload timer 0): Address: 001B6H (Access: Byte, Half-word)  
• TMCSR1 (Reload timer 1): Address: 001BEH (Access: Byte, Half-word)  
• TMCSR2 (Reload timer 2): Address: 001C6H (Access: Byte, Half-word)  
• TMCSR3 (Reload timer 3): Address: 001CEH (Access: Byte, Half-word)  
• TMCSR4 (Reload timer 4): Address: 001D6H (Access: Byte, Half-word)  
• TMCSR5 (Reload timer 5): Address: 001DEH (Access: Byte, Half-word)  
• TMCSR6 (Reload timer 6): Address: 001E6H (Access: Byte, Half-word)  
• TMCSR7 (Reload timer 7): Address: 001EEH (Access: Byte, Half-word)  
15  
–
14  
–
13  
–
12  
CSL2  
0
11  
CSL1  
0
10  
CSL0  
0
9
8
MOD1  
0
bit  
MOD2  
0
-
-
-
Initial Value  
Attribute  
RX/WX RX/WX RX/WX R0/WX  
R/W  
R/W  
R/W0  
R/W  
Rewrite during  
operation  
×
×
×
×
×
×
×
×
7
MOD0  
0
6
5
OULT  
0
4
RELD  
0
3
INTE  
0
2
1
CNTE  
0
0
TRG  
0
bit  
–
UF  
0
-
Initial Value  
Attribute  
R/W  
RX/WX  
R/W  
R/W  
R/W  
R(RM1),W  
R/W  
R0/W  
Rewrite during  
operation  
×
–
×
×
×
Ο
Ο
Ο
(O: can be rewritten, x: cannot be rewritten)  
(For information on attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• bit15-14: Undefined  
Writing has no effect on the operation. The read value is “0”.  
• bit13: Undefined (reload timer 0 - reload timer 2)  
Always write “0”. The read value is “0”.  
• bit12-10: Count clock selection  
CLKP: peripheral clock  
Remarks  
CSL2  
CSL1  
CSL0  
Count clock  
Internal clock CLKP/2  
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
0
Internal clock CLKP/8  
Internal clock CLKP/32  
External event (external clock)  
Internal clock CLKP/64  
Internal clock CLKP/128  
Notes: Depending on whether an internal clock or an external event is selected, the meaning of  
the operation mode selection bit (MOD[2:0]) changes.  
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Chapter 38 Reload Timer  
4.Registers  
• bit9-7: Operation mode selection  
Reload trigger when internal clock is selected  
MOD2  
MOD1  
MOD0  
Reload trigger  
0
0
0
0
0
0
1
1
0
1
0
1
Software trigger  
External trigger (rising edge)  
External trigger (falling edge)  
External trigger (both edges)  
When the selected reload trigger is input, the value of reload register TMRLR is loaded to the down counter and the  
count operation is started.  
Count trigger when external event is selected  
MOD2  
MOD1  
MOD0  
Count trigger  
0
0
0
0
0
0
1
1
0
1
0
1
--------  
External trigger (rising edge)  
External trigger (falling edge)  
External trigger (both edges)  
Counts an external event using the selected count trigger.  
Always set MOD2 to “0”. The read value is the written value.  
• bit6: Undefined  
Writing has no effect on the operation. The read value is “0”.  
• bit5: Output level setting  
OUTL  
One-shot mode (RELD=“0”)  
During count “H” square wave  
During count “L” square wave  
Reload mode (RELD=“1”)  
During count start “L” toggle output  
During count start “H” toggle output  
0
1
• During one-shot mode, a pulse is output during the count, and during reload mode a toggle is output.  
• For output level setting bit “0” and “1” the output level is reversed.  
• bit4: Enable reload  
RELD  
Enable reload  
0
1
One-shot mode (reload disabled)  
Reload mode (reload enabled)  
• In reload mode, down counter underflow (0000H -> FFFFH) causes the value set to reload register  
(TMRLR) to be loaded to the down counter, and the count operation continues.  
• In one-shot mode, down counter underflow (0000H -> FFFFH) causes the count operation to stop.  
• bit3: Enable timer interrupt requests  
INTE  
Enable timer interrupt requests  
0
1
Disable interrupt requests  
Enable interrupt requests  
When timer interrupt requests are enabled, the timer interrupt request flag (UF) becomes “1” and interrupt requests are  
generated.  
• bit2: Timer interrupt request flag  
Timer interrupt request flag  
UF  
When read  
When write  
Clear interrupt requests  
No effect  
0
1
Underflow not present  
Underflow present  
Upon down counter underflow (0000H -> FFFFH) generation, the timer interrupt request flag becomes “1”. If the  
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Chapter 38 Reload Timer  
4.Registers  
interrupt request is enabled (INTE=“1”) an interrupt request is generated.  
• bit1: Enable timer count  
CNTE  
Enable timer count  
0
1
Stop count operation  
Enable count operation (waiting for activation trigger)  
If timer count is enabled, it waits for an activation trigger, and when an activation trigger is generated, the count  
operation starts. The activation trigger can be a software trigger or an external trigger.  
780  
Chapter 38 Reload Timer  
4.Registers  
• bit0: Software trigger  
TRG  
Software trigger  
0
1
No effect. (The read value is “0”.)  
Start count operation after data load.  
If the count operation is enabled (CNTE=“1”) and the software trigger bit is set to “1”, the value of the reload register  
(TMRLR) is loaded to the down counter and the count operation starts.  
If the count operation is not enabled (CNTE=“0”), the software trigger has no effect.  
4.2 TMR: Timer Register  
• TMR0 (Reload timer 0): Address: 01B2H (Access: Half-word)  
• TMR1 (Reload timer 1): Address: 01BAH (Access: Half-word)  
• TMR2 (Reload timer 2): Address: 01C2H (Access: Half-word)  
• TMR3 (Reload timer 3): Address: 01CAH (Access: Half-word)  
• TMR4 (Reload timer 4): Address: 01D2H (Access: Half-word)  
• TMR5 (Reload timer 5): Address: 01DAH (Access: Half-word)  
• TMR6 (Reload timer 6): Address: 01E2H (Access: Half-word)  
• TMR7 (Reload timer 7): Address: 01EAH (Access: Half-word)  
15  
D15  
X
14  
D14  
X
13  
D13  
X
12  
D12  
X
11  
D11  
X
10  
D10  
X
9
D9  
8
D8  
bit  
X
X
Initial Value  
Attribute  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
7
D7  
6
D6  
5
D5  
4
D4  
3
D3  
2
D2  
1
D1  
0
D0  
bit  
X
X
X
X
X
X
X
X
Initial Value  
Attribute  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
(For information on attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.)  
The reload timer count value can be read out through the timer register TMR.  
Please perform the read out using half-word access.  
4.3 TMRLR: Reload register  
• TMRLR0 (Reload timer 0): Address: 01B0H (Access: Half-word)  
• TMRLR1 (Reload timer 1): Address: 01B8H (Access: Half-word)  
• TMRLR2 (Reload timer 2): Address: 01C0H (Access: Half-word)  
• TMRLR3 (Reload timer 3): Address: 01C8H (Access: Half-word)  
• TMRLR4 (Reload timer 4): Address: 01D0H (Access: Half-word)  
• TMRLR5 (Reload timer 5): Address: 01D8H (Access: Half-word)  
• TMRLR6 (Reload timer 6): Address: 01E0H (Access: Half-word)  
• TMRLR7 (Reload timer 7): Address: 01E8H (Access: Half-word)  
15  
D15  
X
14  
D14  
X
13  
D13  
X
12  
D12  
X
11  
D11  
X
10  
D10  
X
9
D9  
8
D8  
bit  
X
X
Initial Value  
Attribute  
RX/W  
RX/W  
RX/W  
RX/W  
RX/W  
RX/W  
RX/W  
RX/W  
7
6
5
4
3
2
1
0
bit  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
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Chapter 38 Reload Timer  
5.Operation  
X
X
X
X
X
X
X
X
Initial Value  
Attribute  
RX/W  
RX/W  
RX/W  
RX/W  
RX/W  
RX/W  
RX/W  
RX/W  
(For information on attributes, see “Meaning of Bit Attribute Symbols (Page No.10)”.)  
The reload value for the down counter is stored in reload register TMRLR.  
Please write using half-word access.  
5. Operation  
5.1 Internal Clock/Reload Mode  
In reload mode, a pulse with a 50% duty ratio is output.  
(1)  
TMRLR  
Reload data  
[Reload register setting value + 1] Count  
Count clock  
(5)  
Load  
data  
Count start  
-1  
(10)  
Reload  
data  
Reload  
data  
-1  
-1  
Down counter  
CNTE bit  
FFFF  
(2)  
(7)  
0000  
0000  
0 (Min)  
(4)  
Activation trigger  
(Soft or external event)  
T = CLKP  
(10)  
(5)  
(6)  
Data load  
(8)  
Underflow  
TOT output waveform  
OUTL=0  
(3)  
Toggle output  
(9)  
OUTL=1  
When RELD=1  
Repeat  
(1)  
(2)  
(3)  
(4)  
(5)  
(6)  
(7)  
(8)  
(9)  
(10)  
(11)  
Set reload value to reload register  
Enable reload timer count operation  
TOT pin output  
Generate reload trigger (activation): soft trigger or external event trigger  
Load reload value  
TOT toggle output start  
Counter count down (internal clock synchronous)  
Generate counter underflow  
TOT pin output level reversal (toggle output)  
Reload reload value  
Repeat steps (7) to (10)  
(See “8. Caution (Page No.794)”.)  
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Chapter 38 Reload Timer  
5.Operation  
5.2 Internal Clock/One-shot Mode  
In one-shot mode, a one-shot pulse is output.  
(1)  
Reload data  
TMRLR  
[Reload register setting value + 1] Count  
Count clock  
Counter  
(5)  
Reload  
data  
Count start  
(7)  
Reload  
data  
(10)  
-1  
FFFF  
-1  
FFFF  
0000  
(2)  
CNTE bit  
(4)  
Activation trigger  
(Soft or external event)  
T = CLKP  
(5)  
(6)  
Data load  
(8)  
Underflow  
(9)  
TOT output waveform  
OUTL=0  
(3)  
(10)  
OUTL=1  
Output only once  
When RELD=0  
(1)  
(2)  
(3)  
(4)  
(5)  
(6)  
(7)  
(8)  
(9)  
(10)  
Set reload value to reload register  
Enable reload timer count operation  
TOT pin output  
Generate reload trigger (activation): soft trigger or external event trigger  
Load reload value  
Square wave output (during count, “H” output/OUTL=“0”)  
Counter count down (internal clock synchronous)  
Generate counter underflow  
Return TOT pin output level  
Count stop, wait for next activation trigger  
(See “8. Caution (Page No.794)”.)  
783  
Chapter 38 Reload Timer  
5.Operation  
5.3 External Event Clock Reload Mode  
External event reload mode counts external events and outputs a pulse with a 50% duty ratio.  
(1)  
Reload data  
TMRLR  
[Reload register setting value + 1] Count  
External event (clock)  
(5) Count start  
Reload  
(10)  
Load  
data  
Reload  
data  
(7)  
Counter  
-1  
-1  
-1  
FFFF  
(2)  
0000  
0000  
data  
CNTE bit  
0 (Min)  
(4)  
Activation trigger  
(Soft only)  
T = CLKP  
(10)  
(5)  
(6)  
Data load  
(8)  
Underflow  
TOT output waveform  
OUTL=0  
(3)  
(9)  
Toggle output  
OUTL=1  
Repeat  
When RELD=1  
(1)  
(2)  
(3)  
(4)  
(5)  
(6)  
(7)  
(9)  
(10)  
(11)  
Set reload value to reload register  
Enable reload timer count operation  
TOT pin output  
Generate reload trigger (activation): software trigger only  
Load reload value  
TOT pin output (initial value)  
Counter count down (external event synchronous)  
TOT pin output level reversal  
Reload reload value  
Repeat steps (6) to (9)  
(See “8. Caution (Page No.794)”.)  
784  
Chapter 38 Reload Timer  
5.Operation  
5.4 External Event Clock/One-shot Mode  
In external event one-shot mode, external events are counted and a one-shot pulse is output.  
(1)  
Reload data  
TMRLR  
[Reload register setting value + 1] Count  
External event clock  
(5)  
Count start  
Reload  
data  
Reload  
data  
(7)  
-1  
Counter  
(10)  
FFFF  
-1  
FFFF  
(4)  
0000  
(2)  
CNTE bit  
Activation trigger  
(Soft only)  
T = CLKP  
(5)  
Data load  
(8)  
Underflow  
(6)  
(9)  
(10)  
TOT output waveform  
OUTL=0  
(3)  
OUTL=1  
When RELD=0  
Output only once  
(1)  
(2)  
(3)  
(4)  
(5)  
(6)  
(7)  
(8)  
(9)  
(10)  
Set reload value to reload register  
Enable reload timer count operation  
TOT pin output  
Generate reload trigger (activation): soft trigger only  
Load reload value  
TOT pin output (during count, output “H”/OUTL=“0”)  
Counter count down (via external events)  
Generate counter underflow  
TOT pin output reversal  
Stop counter, wait for next activation trigger  
Note: The first reload will be delayed by a maximum of 1 T (T: count clock).  
5.5 Operation during Reset  
A reset (reset on INITX signal, watchdog reset, software reset) will cause the registers in the reload timer to be  
initialized. The initial value of reload registers is indeterminate.  
For detailed information on initial values, see the explanation of registers.  
5.6 Operation during Sleep Mode  
Even after making the transition to sleep mode, the operation of the reload timer will continue.  
5.7 Operation during Stop Mode  
When the transition is made to stop mode, the operation of the reload timer stops.  
Afterwards, when returning from stop mode, it will return to the state it was in before the transition to stop  
mode.  
785  
Chapter 38 Reload Timer  
5.Operation  
5.8 Operation when Returning from Stop Mode  
When returning due to an external interrupt, the reload timer will continue operation from its stopped state.  
When returning from a reset (INITX), it will return to the initial state (down counter stopped, no TOT pin  
output).  
5.9 Status Transition  
The status of the counter is decided by the CNTE bit of the reload timer control register and the internal WAIT  
signal.  
Settable statuses are:  
STOP status: Stopped (CNTE=“0”, WAIT=“1”)  
WAIT status: Waiting for activation trigger (CNTE=“1”, WAIT=“1”)  
RUN status : Count operation running (CNTE=“1”, WAIT=“0”)  
LOAD status: Loading value to counter (from RUN/WAIT, TRG=“1” or underflow: CNTE=“1”, WAIT=“0”)  
Figure 5-1 Status Transition Diagram  
Status Transition from Hardware  
Reset  
Status Transition from Register Access  
STOP CNTE=0,WAIT=1  
Counter: Retains value  
when stopped  
Indeterminate after reset  
CNTE="1"  
TRG="0"  
CNTE="1"  
TRG="1"  
WAIT CNTE=1,WAIT=1  
RUN CNTE=1,WAIT=0  
Counter: Retains value  
when stopped  
Indeterminate until load  
after reset  
.
Counter: Operation  
RELD  
UF  
TRG="1"  
TRG="1"  
LOAD CNTE=1,WAIT=0  
RELD-UF  
Load reload register  
content to counter  
Finish load  
786  
Chapter 38 Reload Timer  
6.Setting  
6. Setting  
Table 6-1 Settings Necessary for Moving the Reload Timer (Internal Clock Operation)  
Setting  
Procedure*  
Setting  
Setting Registers  
Reload value settings  
Reload (TMRLR0-TMRLR7)  
See7.1  
See 7.2  
See 7.3  
See 7.4  
See 7.5  
Count clock selection (internal clock selection)  
Enable reload timer count operation  
Mode selection (reload /one-shot)  
Output reversal specification  
Reload timer control status  
(TMCSR0-TMCSR7)  
Reload trigger selection (activation selection)  
Soft trigger  
External trigger  
See 7.6  
See 7.8  
(Rising edge/falling edge/both edges)  
(Extra) port function register  
(PFR15.0 - PFR15.7 and EPFR15.0 -  
EPFR15.7)  
TOT0 - TOT7 pin output  
Generate activation trigger  
–
Soft trigger  
-> Software trigger bit setting  
Reload timer control status  
(TMCSR0-TMCSR7)  
See 7.10  
External trigger  
-> Input trigger to TIN pin  
External input  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-2 Settings Necessary for Moving the Reload Timer (External Event Operation)  
Setting  
Procedure*  
Setting  
Setting Registers  
Reload value setting  
Reload (TMRLR0-TMRLR7)  
See 7.1  
See 7.2  
See 7.3  
See 7.4  
See 7.5  
Count clock selection (external event clock selection)  
Enable reload timer count operation  
Mode selection (reload /one-shot)  
Reload timer control status  
(TMCSR0-TMCSR7)  
Output reversal specification  
External event clock active edge selection  
(Rising edge/falling edge/both edges)  
See 7.7  
See 7.8  
See 7.9  
See 7.10  
(Extra) port function register  
(PFR15.0 - PFR15.7 and EPFR15.0 -  
EPFR15.7)  
TOT0 - TOT7 pin output  
Port function register (PFR14.0 -  
PFR14.7)  
TIN0 - TIN7 pin external event input  
Generate activation trigger  
Soft trigger  
-> Software trigger bit setting  
Reload timer control status  
(TMCSR0-TMCSR7)  
*: For the setting procedure, refer to the section indicated by the number.  
787  
 
Chapter 38 Reload Timer  
6.Setting  
Table 6-3 Items Necessary for Performing Reload Timer Interrupts  
Setting  
Procedure*  
Setting  
Reload timer interrupt vector  
Setting Registers  
See “Chapter 24 Interrupt Control  
(Page No.311)”  
See 7.11  
See 7.12  
Reload timer interrupt level setting  
Reload timer interrupt settings  
Interrupt request clear  
Enable interrupt requests  
Reload timer control status  
(TMCSR0-TMCSR7)  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-4 Settings Necessary for Stopping the Reload Timer  
Setting  
Procedure*  
Setting  
Reload timer stop bit setting  
Setting Registers  
Reload timer control status  
(TMCSR0-TMCSR7)  
See 7.13  
*: For the setting procedure, refer to the section indicated by the number.  
788  
Chapter 38 Reload Timer  
7.Q & A  
7. Q & A  
7.1 What is the reload value setting (rewriting) procedure?  
The reload value is set by the 16 bit reload registers TMRLR0-TMRLR7.  
The equation for the values to be set is as follows.  
• Formula  
TMRLR register value = {reload interval/count clock}-1  
• Allowed Range  
TMRLR register value = 0~FFFh (65535)  
7.2 What are the kinds of count clocks and how are they selected?  
The count clock is chosen from the 4 types in the table below.  
Selection is done via the count clock selection bit.  
Table 7-1 TMCSR.CSL[2:0]  
Counter clock selection bit  
Count clock example  
Count  
Clock  
When CLKP=  
32MHz  
When CLKP=  
16MHz  
CSL2  
CSL1  
CSL0  
When CLKP= 8MHz  
CLKP/2  
CLKP/8  
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
62.5ns  
250ns  
1.0µs  
125ns  
250ns  
1.0µs  
4.0µs  
500ns  
CLKP/32  
2.0µs  
External event  
CLKP/64  
Pulse width: 2/CLKP min  
2.0µs  
4.0µs  
4.0µs  
8.0µs  
-----  
8.0µs  
16.0µs  
CLKP/128  
Disabled *  
-----  
(*: See “8. Caution (Page No.794)”.)  
7.3 How to I enable/disable the reload timer count operation?  
Use the timer count enable bit (TMCSR.CNTE).  
Control Details  
To stop the reload timer  
RLT operation permission bit (CNTE)  
Set to “0”  
Set to “1”  
To enable the reload timer’s count operation  
Cannot be reopened from the stopped state. Enable before activation or simultaneous with activation.  
7.4 How do I set the reload timer mode (reload/one-shot)?  
Use mode selection bit (TMCSR.RELD).  
Operation Mode  
To set to one-shot mode  
To set to reload  
Mode selection bit (RELD)  
Set to “0”  
Set to “1”  
7.5 How do I reverse the output level?  
The settings for the output level are detailed in the following table.  
The setting is done via timer output level bit (TMCSR.OUTL).  
Output level  
Timer output level bit (OUTL)  
789  
   
Chapter 38 Reload Timer  
7.Q & A  
Reload mode, Initial value “L” level output  
Set to “0”  
Set to “1”  
Reload mode, initial value “H” level output (reversed)  
One-shot mode, counting “H” level output  
Set to “0”  
Set to “1”  
One-shot mode, counting “L” level output (reversed)  
790  
Chapter 38 Reload Timer  
7.Q & A  
7.6 What are the kinds of triggers, and how do I select them?  
• Selection is done via the trigger selection bit (TMCSR.MOD[2:0]).  
There are 4 types of reload triggers when an internal clock is selected.  
Trigger  
Trigger specification bit (MOD[2:0])  
Software trigger (TRG bit set)  
Set to “000”  
Set to “001”  
Set to “010”  
Set to “011”  
External trigger from TINx pin (rising edge)  
External trigger from TINx pin (falling edge)  
External trigger from TINx pin (both edges)  
——————  
“100”, “101”, “110”, “111” are disabled *  
Reload is repeated on down counter underflow.  
(*: See “8. Caution (Page No.794)”.)  
• The reload trigger (activation) when an external event is selected is a software trigger.  
Reload is repeated on down counter underflow.  
7.7 What are the types of external event clock active edges and how do I select them?  
The setting is done via the trigger selection bit (TMCSR.MOD[1:0]).  
There are three types of active edges.  
Active edge  
Rising edge  
Falling edge  
Both edges  
Trigger selection bit (MOD1-MOD0)  
Set to “01”  
Set to “10”  
Set to “11”  
MOD2 settings have no meaning, no matter if they are set to “0” or “1”.  
7.8 How do I make a pin a TOT output pin?  
Write “1” to the TOT output selection bits (PFR15/EPFR15) to change the port to a TOT pin output.  
Pin  
Control bit  
TOT0 pin  
TOT1 pin  
TOT2 pin  
TOT3 pin  
TOT4 pin  
TOT5 pin  
TOT6 pin  
TOT7 pin  
PFR15.0 = ‘1’  
PFR15.1 = ‘1’  
PFR15.2 = ‘1’  
PFR15.3 = ‘1’  
PFR15.4 = ‘1’  
PFR15.5 = ‘1’  
PFR15.6 = ‘1’  
PFR15.7 = ‘1’  
EPFR15.0 = ‘1’  
EPFR15.1 = ‘1’  
EPFR15.2 = ‘1’  
EPFR15.3 = ‘1’  
EPFR15.4 = ‘1’  
EPFR15.5 = ‘1’  
EPFR15.6 = ‘1’  
EPFR15.7 = ‘1’  
7.9 How do I make the TIN pin into an external event input pin, or an external trigger  
input pin?  
Write “1” to the TIN input selection bits (PFR14) to change the port to a TIN pin input.  
Pin  
Control bit  
TIN0 pin  
TIN1 pin  
TIN2 pin  
TIN3 pin  
TIN4 pin  
TIN5 pin  
PFR14.0 = ‘1’  
PFR14.1 = ‘1’  
PFR14.2 = ‘1’  
PFR14.3 = ‘1’  
PFR14.4 = ‘1’  
PFR14.5 = ‘1’  
-
-
-
-
-
-
791  
Chapter 38 Reload Timer  
7.Q & A  
TIN6 pin  
TIN7 pin  
PFR14.6 = ‘1’  
PFR14.7 = ‘1’  
-
-
7.10 How do I generate an activation trigger?  
• Generating a soft trigger  
The setting is done via the software trigger bit (TMCSR.TRG).  
When the software trigger bit (TGR) is set to“1”, a trigger is generated.  
To enable operation and activate at the same time, set the count permission bit (TMCSR.CNTE) and the soft trigger bit  
(TMCSR.TRG) simultaneously.  
• Generating an external trigger  
By inputting the edge specified by the trigger selection bit to the trigger pin corresponding to each reload timer, a  
trigger is generated.  
Timer  
Trigger pin  
TIN0  
Reload timer 0  
Reload timer 1  
Reload timer 2  
Reload timer 3  
Reload timer 4  
Reload timer 5  
Reload timer 6  
Reload timer 7  
TIN1  
TIN2  
TIN3  
TIN4  
TIN5  
TIN6  
TIN7  
7.11 What are the interrupt-related registers?  
The relationship between reload timer numbers, interrupt level, vector, control register, etc is outlined in the  
following table.  
For details on interrupt level and interrupt vectors, see “Chapter 24 Interrupt Control (Page No.311)”.  
Interrupt level setting bit (ICR[4:0])  
Interrupt vector (default)  
#32  
Reload timer 0  
Reload timer 1  
Reload timer 2  
Reload timer 3  
Reload timer 4  
Reload timer 5  
Reload timer 6  
Reload timer 7  
Address: 0FFF7Ch  
Interrupt level register (ICR08)  
Address: 0448h  
#33  
Address: 0FFF78h  
#34  
Address: 0FFF74h  
Interrupt level register (ICR09)  
Address: 0449h  
#35  
Address: 0FFF70h  
#36  
Address: 0FFF6Ch  
Interrupt level register (ICR10)  
Address: 044Ah  
#37  
Address: 0FFF68h  
#38  
Address: 0FFF64h  
Interrupt level register (ICR11)  
Address: 044Bh  
#39  
Address: 0FFF60h  
Interrupt request flag (TMCSR0.UF) ~ (TMCSR7.UF) is not automatically cleared, so before returning from  
interrupt processing, set the UF bit to “0” to reset it.  
7.12 How do I enable interrupts?  
Enabling interrupts, interrupt request flag  
792  
Chapter 38 Reload Timer  
7.Q & A  
Enabling of interrupts is done via the interrupt request permission bit (TMCSR0.INTE) ~ (TMCSR7.INTE).  
Interrupt request permission bit (INTE)  
To disable interrupt requests  
To enable interrupt requests  
Set to “0”  
Set to “1”  
Clearing of interrupt requests is done via the interrupt request bit (TMCSR0.UF) ~ (TMCSR7.UF).  
Interrupt request bit (UF)  
To disable interrupt requests  
Set to “0”  
7.13 How do I stop the reload timer?  
This setting is done via the reload timer stop bit.  
See “7.3 How to I enable/disable the reload timer count operation? (Page No.789)”.  
793  
Chapter 38 Reload Timer  
8.Caution  
8. Caution  
• Count source select bit (TMCSR.CSL[2:0]) settings not in the table: “100”, “111” are disabled.  
If they are set, disable the reload timer operation before resetting the count source select bit.  
• Operation mode bit (TMCSR.MOD2) must be set to “0”. If it is set to “1”, disable the reload timer count  
operation before resetting it. Also the value written during read/modify/write access may be read.  
• Control bits (Count source select, operation mode, reload permission) must not be rewritten during  
operation.  
If they are set during operation, disable the reload timer count operation before resetting them.  
• From activation timing, it takes T cycle for the reload value to be loaded to the down counter. (Cycle = 1/  
CLKP, CLKP = peripheral clock)  
• About output signal internal connections  
• Reload timer TOT0-TOT7 outputs are connected to the PPG0-PPG15 internal trigger inputs.  
• Reload timer TOT7 output is connected to the A/D converter 0 trigger input.  
• Rewriting of the count clock selection bit (CSL[2:0]), operation mode selection bit (MOD[2:0]), output level  
setting bit (OUTL), reload permission bit (RELD), and timer interrupt request permission bit (INTE) should be  
done when the reload timer is stopped (TMCSR.CNTE=“0”).  
• The internal prescaler should be already set when the timer count permission bit (TMCSR.CNTE) is set to  
“1”.  
• If interrupt request flag set timing and clear timing overlap, the flag setting will be given priority and the clear  
operation will be made invalid.  
• When writing to the reload register and the reload timing overlap, the old data will be loaded to the counter.  
The new data will be loaded during the next reload timing.  
• If the loading and counting of the timer register overlap, the load (reload) operation is given priority.  
• If you want to enable the count at the same time as you start the count operation, set both the timer count  
permission bit (TMCSR.CNTE) and the software trigger bit (TMCSR.TRG) to “1”.  
794  
 
Chapter 39 Programmable Pulse Generator  
1.Overview  
Chapter 39 Programmable Pulse Generator  
1. Overview  
Programmable Pulse Generators (PPGs) are used to gain one-shot (rectangular wave) output or pulse width  
modulation (PWM) output. With their software-programmable cycle and duty capability, the PPGs comfortably  
fit into broad applications.  
Period value  
Reload  
Borrow  
Count clock  
Down counter  
Output  
value  
Pin  
Match Invert  
Latch  
Buffer  
Duty value  
2. Features  
• Output waveforms: The PPGs can generate the following six kinds of waveforms:  
• PWM waveform  
Normal polarity:  
L H  
H L  
L
L H  
H L  
Inverted polarity:  
H
• One-shot waveform (Rectangular wave)  
Normal polarity:  
L
H
L
Inverted polarity:  
H
L
H
• Clamped output  
Normal polarity: “L” Clamped output  
Inverted polarity: “H” Clamped output  
• Quantity: 4 groups (Output: 16 channels PPG0 - PPG15)  
• Count clock: Choose from four choices.  
1, 1/4, 1/16, 1/64 of the peripheral clock (CLKP)  
• Period: Setting range = Duty value ~ 65535 (specified with a 16-bit register)  
Period = Count clock (PCSR register value + 1)  
(Example) Count clock = 32MHz(31.25ns), PCSR value = 63999  
Period = 31.25ns (63999+1) = 2ms  
• Duty: Setting range = 0 ~ Period value (specified with a 16-bit register)  
Duty = Count clock (PDUT register value + 1)  
795  
     
Chapter 39 Programmable Pulse Generator  
2.Features  
• Interrupt: Choose from four choices:  
• Software trigger  
• Counter borrow (cycle match)  
• Duty match  
• Counter borrow (cycle match) or duty match  
• Activation trigger:  
• Software trigger  
• Internal triggers  
Reload timer output 0 (TOT0) available as trigger for PPG0-PPG3  
Reload timer output 1 (TOT1) available as trigger for PPG0-PPG3  
Reload timer output 2 (TOT2) available as trigger for PPG4-PPG7  
Reload timer output 3 (TOT3) available as trigger for PPG4-PPG7  
Reload timer output 4 (TOT4) available as trigger for PPG8-PPG11  
Reload timer output 5 (TOT5) available as trigger for PPG8-PPG11  
Reload timer output 6 (TOT6) available as trigger for PPG12-PPG15  
Reload timer output 7 (TOT7) available as trigger for PPG12-PPG15  
• External triggers  
Port GP14_0 (ICU0, RLT0 ext-trig) available as trigger for PPG0-PPG3/PPG8-PP11  
Port GP14_1 (ICU1, RLT1 ext-trig) available as trigger for PPG0-PPG3/PPG8-PP11  
Port GP14_2 (ICU2, RLT2 ext-trig) available as trigger for PPG0-PPG3/PPG8-PP11  
Port GP14_3 (ICU3, RLT3 ext-trig) available as trigger for PPG0-PPG3/PPG8-PP11  
Port GP14_4 (ICU4, RLT4 ext-trig) available as trigger for PPG4-PPG7/PPG12-PP15  
Port GP14_5 (ICU5, RLT5 ext-trig) available as trigger for PPG4-PPG7/PPG12-PP15  
Port GP14_6 (ICU6, RLT6 ext-trig) available as trigger for PPG4-PPG7/PPG12-PP15  
Port GP14_7 (ICU7, RLT7 ext-trig) available as trigger for PPG4-PPG7/PPG12-PP15  
796  
Chapter 39 Programmable Pulse Generator  
3.Configuration  
3. Configuration  
Figure 3-1 Configuration Diagram  
PPG (0-3)  
Only write  
enabled  
Only write  
enabled  
MDSE  
PCNH: bit13  
PWM operation  
One shot  
Duty value  
Period value  
0
1
PGMS OSEL  
PCNH: bit9,PCNL:bit0  
Normal output  
Inverted output  
Clamped L output  
Clamped H output  
PCSR  
PDUT  
0
0
1
1
0
1
0
1
Buffers  
Buffers  
Count clock  
CKS1,0 PCNH: bit11,10  
Port read  
Reload  
PPG0/P17.0  
PPG1/P17.1  
PPG2/P17.2  
PPG3/P17.3  
0
0
1
1
0
1
0
1
0
CLKP  
From Port  
Duty match  
CLKP/4  
CLKP/16  
CLKP/64  
OR  
Data register  
Output level  
(Latch)  
Compare  
Read-only  
down counter  
1
PPG0 PFR4: bit0  
PPG1 PFR4: bit1  
PPG2 PFR4: bit2  
PPG3 PFR4: bit3  
Peripheral  
clock  
(CLKP)  
Borrow  
Prescaler  
PTMR  
General-purpose port  
0
1
IREN PCNL: bit5  
Interrupt disabled  
Interrupt enabled  
Enable operation/Stop  
PPG output  
0
1
Duty  
match  
CNTE PCNH: bit15  
RTRG PCNH: bit12  
Control  
circuit  
0
1
Stop  
0
1
Restart disabled  
Restart enabled  
IRQF PCNL: bit4  
No interrupt request  
Enable operation  
1
Trigger selection  
TSEL03-00  
0
1
Borrow  
Trigger  
Interrupt request  
GCN10: bit3-0  
GCN20 EN0 bit  
GCN20 EN1 bit  
GCN20 EN2 bit  
GCN20 EN3 bit  
16-bit reload timer ch0  
16-bit reload timer ch1  
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
-
0
0
1
1
0
0
1
-
0
1
0
1
0
1
-
Trigger  
Write 0: Flag clear  
PPG0  
PPG0/1  
interrupt  
(#112/#113)  
interrupt  
request  
0
OR  
OR  
PPG1  
interrupt  
request  
OR  
Interrupt cause selection  
IRS1,0 PCNL: bit3,2  
Software trigger, or trigger input available PPG2  
Disabled  
Disabled  
-
0
0
1
1
0
1
0
1
STGR PCNH: bit14  
interrupt  
request  
0
1
Operation unaffected  
Software trigger  
Read: Always '0'  
Counter borrow  
Duty match  
Counter borrow or duty match  
PPG2/3  
interrupt  
EN0 GCN20: bit0  
EN1 GCN20: bit1  
Edge  
selection  
PPG3  
interrupt  
request  
(#114/#115)  
EN2 GCN20: bit2  
EN3 GCN20: bit3  
Reload timer ch0  
Reload timer ch1  
Register number  
Edge selection  
PCNL: bit7,6  
Operation unaffected  
Period  
setting  
Control  
status H  
EGS1,0  
Duty  
Controls  
status L  
PCNL0  
PCNL1  
PCNL2  
PCNL3  
PPG  
Timer  
Pin  
0
0
1
1
0
1
0
1
setting  
PDUT0  
PDUT1  
PDUT2  
PDUT3  
Rising edge  
Falling edge  
Both edges  
0
1
2
3
PTMR0  
PTMR1  
PTMR2  
PTMR3  
PCSR0  
PCSR1  
PCSR2  
PCSR3  
PCNH0  
PCNH1  
PCNH2  
PCNH3  
PPG0  
PPG1  
PPG2  
PPG3  
Figure 3-2 Register List  
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Chapter 39 Programmable Pulse Generator  
3.Configuration  
Note: For more information about the ICR register and interrupt vector, see “Chapter 24 Interrupt Control (Page  
No.311)”.  
798  
Chapter 39 Programmable Pulse Generator  
4.Registers  
4. Registers  
4.1 PCSR: PPG Cycle Setting Register  
Controls the cycle of the PPG.  
• PCSR00 (PPG0): Address 0112h (Access: Half-word)  
• PCSR01 (PPG1): Address 011Ah (Access: Half-word)  
• PCSR02 (PPG2): Address 0122h (Access: Half-word)  
• PCSR03 (PPG3): Address 012Ah (Access: Half-word)  
• PCSR04 (PPG4): Address 0132h (Access: Half-word)  
• PCSR05 (PPG5): Address 013Ah (Access: Half-word)  
• PCSR06 (PPG6): Address 0142h (Access: Half-word)  
• PCSR07 (PPG7): Address 014Ah (Access: Half-word)  
• PCSR08 (PPG8): Address 0152h (Access: Half-word)  
• PCSR09 (PPG9): Address 015Ah (Access: Half-word)  
• PCSR10 (PPG10): Address 0162h (Access: Half-word)  
• PCSR11 (PPG11): Address 016Ah (Access: Half-word)  
• PCSR12 (PPG12): Address 0332h (Access: Half-word)  
• PCSR13 (PPG13): Address 033Ah (Access: Half-word)  
• PCSR14 (PPG14): Address 0342h (Access: Half-word)  
• PCSR15 (PPG15): Address 034Ah (Access: Half-word)  
15  
14  
13  
12  
11  
10  
9
8
Bit  
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
Initial  
value  
X
X
X
X
X
X
X
X
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
Attribute  
7
6
5
4
3
2
1
0
Bit  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Initial  
value  
X
X
X
X
X
X
X
X
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• The PPG Period Setting registers are buffered. Transfers from the buffers to the counter take place  
automatically at counter overflow or underflow.  
• After the PPG Period Setting registers have been written, be sure to set PPG Duty Setting registers  
PDUT.  
• Always access the PPG Period Setting registers in a half-word (16-bit) format.  
(See “8. Caution (Page No.821)”.)  
799  
 
Chapter 39 Programmable Pulse Generator  
4.Registers  
4.2 PDUT: PPG Duty Setting Register  
Sets the duty of the PPG output waveform.  
• PDUT00 (PPG0): Address 0114h (Access: Half-word)  
• PDUT01 (PPG1): Address 011Ch (Access: Half-word)  
• PDUT02 (PPG2): Address 0124h (Access: Half-word)  
• PDUT03 (PPG3): Address 012Ch (Access: Half-word)  
• PDUT04 (PPG4): Address 0134h (Access: Half-word)  
• PDUT05 (PPG5): Address 013Ch (Access: Half-word)  
• PDUT06 (PPG6): Address 0144h (Access: Half-word)  
• PDUT07 (PPG7): Address 014Ch (Access: Half-word)  
• PDUT08 (PPG8): Address 0154h (Access: Half-word)  
• PDUT09 (PPG9): Address 015Ch (Access: Half-word)  
• PDUT10 (PPG10): Address 0164h (Access: Half-word)  
• PDUT11 (PPG11): Address 016Ch (Access: Half-word)  
• PDUT12 (PPG12): Address 0334h (Access: Half-word)  
• PDUT13 (PPG13): Address 033Ch (Access: Half-word)  
• PDUT14 (PPG14): Address 0344h (Access: Half-word)  
• PDUT15 (PPG15): Address 034Ch (Access: Half-word)  
15  
D15  
X
14  
D14  
X
13  
D13  
X
12  
D12  
X
11  
D11  
X
10  
D10  
X
9
D9  
8
D8  
Bit  
X
X
Initial value  
Attribute  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
7
D7  
6
D6  
5
D5  
4
D4  
3
D3  
2
D2  
1
D1  
0
D0  
Bit  
X
X
X
X
X
X
X
X
Initial value  
Attribute  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• The PPG Duty Setting registers registers are buffered. Transfers from the buffers to the counter take place  
automatically at counter overflow or underflow.  
• Set a value smaller than the setting of PPG Period Setting register PCSR in a PPG Duty Setting register.  
(See “8. Caution (Page No.821)”.)  
• If the same value as set in PPG Period Setting register PCSR is set in a PPG Duty Setting register,  
• “H” is always output to (OSEL=”0”) at normal polarity time.  
• “L” is always output to (OSEL=”1”) at inverted polarity time.  
(The OSEL bit is an output polarity specification bit of the PPG control register PCN.)  
• Always access the PPG Duty Setting registers in a half-word (16-bit) format.  
(See “8. Caution (Page No.821)”.)  
800  
Chapter 39 Programmable Pulse Generator  
4.Registers  
4.3 PCN: PPG Control Status register  
Controls the operations and status of PPGs.  
• PCN00 (PPG0): Address 0116h (Access: Byte, Half-word)  
• PCN01 (PPG1): Address 011Eh (Access: Byte, Half-word)  
• PCN02 (PPG2): Address 0126h (Access: Byte, Half-word)  
• PCN03 (PPG3): Address 012Eh (Access: Byte, Half-word)  
• PCN04 (PPG4): Address 0136h (Access: Byte, Half-word)  
• PCN05 (PPG5): Address 013Eh (Access: Byte, Half-word)  
• PCN06 (PPG6): Address 0146h (Access: Byte, Half-word)  
• PCN07 (PPG7): Address 014Eh (Access: Byte, Half-word)  
• PCN08 (PPG8): Address 0156h (Access: Byte, Half-word)  
• PCN09 (PPG9): Address 015Eh (Access: Byte, Half-word)  
• PCN10 (PPG10): Address 0166h (Access: Byte, Half-word)  
• PCN11 (PPG11): Address 016Eh (Access: Byte, Half-word)  
• PCN12 (PPG12): Address 0336h (Access: Byte, Half-word)  
• PCN13 (PPG13): Address 033Eh (Access: Byte, Half-word)  
• PCN14 (PPG14): Address 0346h (Access: Byte, Half-word)  
• PCN15 (PPG15): Address 034Eh (Access: Byte, Half-word)  
15  
CNTE  
0
14  
STGR  
0
13  
MDSE  
0
12  
RTRG  
0
11  
CKS1  
0
10  
CKS0  
0
9
PGMS  
0
8
Bit  
–
X
Initial value  
Attribute  
R/W  
R0/W  
R/W  
R/W  
R/W  
R/W  
R/W  
RX/WX  
Rewrite during  
operation  
O
O
×
×
×
×
×
–
7
EGS1  
0
6
EGS0  
0
5
IREN  
0
4
IRQF  
3
2
1
0
OSEL  
0
Bit  
IRS1  
0
IRS0  
0
–
X
0
Initial value  
Attribute  
R/W  
R/W  
R/W  
R(RM1), W  
R/W  
R/W  
RX/WX  
R/W  
Rewrite during  
operation  
×
×
O
O
×
×
–
×
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
O: Rewritable, x: Not writable (See “8. Caution (Page No.821)”.)  
• Bit 15: Timer enable operation  
CNTE  
Operation  
0
1
Stop  
Operation  
This bit enables the operation of the PPG.  
• Bit 14: Software trigger  
STGR  
Operation  
0
1
The operation is unaffected by writing (The read value always equals “0”).  
Software trigger activation  
When the Software Trigger bit is set to “1”, a software trigger is generated to activate the PPG, separately from the  
generation of an internal trigger (EN bit, reload timer output).  
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Chapter 39 Programmable Pulse Generator  
4.Registers  
• Bit 13: Mode selection  
MDSE  
Mode  
0
1
PWM operation  
One-shot operation  
• When the Mode Selection bit is set to “0”, a PWM operation is enabled to generate pulses in sequence.  
• When the Mode Selection bit is set to “1”, pulse output takes place only once.  
• Bit 12: Restart enable  
RTTG  
Operation  
0
1
Disable restart.  
Enable restart.  
When the Enable Restart bit is set to “1”, a trigger (software/internal) is generated to enable a restart.  
• Bits 11-10: Counter clock selection  
CKS1  
CKS0  
Down Counter Count Clock Selection  
0
0
1
1
0
1
0
1
Peripheral clock (CLKP)  
Peripheral clock divided by 4  
Peripheral clock divided by 16  
Peripheral clock divided by 64  
• Bit 9: PPG output mask selection  
PGMS  
Operation  
0
1
No output mask  
Output mask (Output “L” level latched:OSEL=“0”)  
• When the PPG Output Mask Selection bit is set to “1”, the PPG output can be clamped at “L” or “H”  
regardless of the mode, cycle, and duty settings.  
• The output level can be specified using the Output Polarity Specification bit (PCN.OSEL).  
• Bit 8: Undefined.The operation is unaffected by writing. The read value is indeterminate.  
• Bits 7-6: Trigger input edge selection  
EGS1 EGS0  
Selected Edge  
0
0
1
1
0
1
0
1
The operation is unaffected by writing.  
Rising edge  
Falling edge  
Both edges (rising edge, or, falling edge)  
Select an edge to trigger the activation of the trigger input selected with the Trigger Specification bits  
(GCN10[15:12]), (GCN10[11:8]), (GCN10[7:4]), and (GCN10[3:0]) of PPG3 to PPG0,  
(GCN11[15:12]), (GCN11[11:8]), (GCN11[7:4]), and (GCN11[3:0]) of PPG7 to PPG4,  
(GCN12[15:12]), (GCN12[11:8]), (GCN12[7:4]), and (GCN12[3:0]) of PPG11 to PPG8,  
(GCN13[15:12]), (GCN13[11:8]), (GCN13[7:4]), and (GCN13[3:0]) of PPG15 to PPG12,  
using the Trigger Input Edge Selection bit (EGS[1:0]).  
• Bit 5: Interrupt request enable  
IREN  
Operation  
0
1
Interrupt request disable  
Enable interrupt requests.  
• Bit 4: interrupt request flag  
IRQF  
Read Operation  
Write Operation  
Clear the Interrupt Request flag.  
0
No interrupt request  
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Chapter 39 Programmable Pulse Generator  
4.Registers  
1
Interrupt request  
The operation is unaffected by writing.  
If the Interrupt Request flag (IRQF) equals “1” and writing “0” to the flag take place at the same time, the setting of the  
Interrupt Request flag (IRQF=“1”) overrides.  
• Bit 3-2: Interrupt cause selection  
IRS1  
IRS0  
Selection  
0
0
1
1
0
1
0
1
Software trigger, or, trigger input  
Counter borrow  
The counter matches the duty value.  
Counter borrow, or the counter equals the duty value.  
• Select the operation in which to generate an interrupt request.  
• Bit 1: Undefined.The operation is unaffected by writing. The read value is indeterminate.  
• Bit 0: PPG output polarity specification  
OSEL  
Operation  
0
1
Normal polarity  
Inverted polarity  
When the PPG Output Mask Selection bit (PCN.PGMS) has been set to “1”, if the Output Polarity Specification bit  
(OSEL) is set to “0”, the output is clamped at “L”; if the Output Polarity Specification bit is set to “1”, the output is  
clamped at “H”.  
803  
Chapter 39 Programmable Pulse Generator  
4.Registers  
4.4 GCN1: General Control register 1  
Selects a trigger input to PPG0-PPG3, PPG4-PPG7, PPG8-PPG11 and PPG12-PPG15.  
• GCN10 (PPG0-PPG3): Address 0100h (Access: Half-word)  
• GCN11 (PPG4-PPG7): Address 0104h (Access: Half-word)  
• GCN12 (PPG8-PPG11): Address 0108h (Access: Half-word)  
• GCN13 (PPG12-PPG15): Address 0320h (Access: Half-word)  
15  
TSEL33  
0
14  
TSEL32  
0
13  
TSEL31  
1
12  
TSEL30  
1
11  
TSEL23  
0
10  
TSEL22  
0
9
TSEL21  
1
8
TSEL20  
0
Bit  
Initial value  
Attribute  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
7
TSEL13  
0
6
TSEL12  
0
5
TSEL11  
0
4
TSEL10  
1
3
TSEL03  
0
2
TSEL02  
0
1
TSEL01  
0
0
TSEL00  
0
Bit  
Initial value  
Attribute  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
PPG12-PPG15:  
•GCN13: Bits 15-12 (TSEL3[3:0])  
PPG15 trigger specification  
PPG14 trigger specification  
PPG13 trigger specification  
PPG12 trigger specification  
•GCN13: Bits 11-8  
•GCN13: Bits 7-4  
•GCN13: Bits 3-0  
PPG8-PPG11:  
(TSEL2[3:0])  
(TSEL1[3:0])  
(TSEL0[3:0])  
•GCN12: Bits 15-12 (TSEL3[3:0])  
PPG11 trigger specification  
PPG10 trigger specification  
PPG9 trigger specification  
PPG8 trigger specification  
•GCN12: Bits 11-8  
•GCN12: Bits 7-4  
•GCN12: Bits 3-0  
PPG4-PPG7:  
(TSEL2[3:0])  
(TSEL1[3:0])  
(TSEL0[3:0])  
•GCN11: Bits 15-12 (TSEL3[3:0])  
PPG7 trigger specification  
PPG6 trigger specification  
PPG5 trigger specification  
PPG4 trigger specification  
•GCN11: Bits 11-8  
•GCN11: Bits 7-4  
•GCN11: Bits 3-0  
PPG0-PPG3:  
(TSEL2[3:0])  
(TSEL1[3:0])  
(TSEL0[3:0])  
•GCN10: Bits 15-12 (TSEL3[3:0])  
PPG3 trigger specification  
PPG2 trigger specification  
PPG1 trigger specification  
PPG0 trigger specification  
•GCN10: Bits 11-8  
•GCN10: Bits 7-4  
•GCN10: Bits 3-0  
(TSEL2[3:0])  
(TSEL1[3:0])  
(TSEL0[3:0])  
804  
Chapter 39 Programmable Pulse Generator  
4.Registers  
TSEL  
Activation trigger specification  
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
EN0 bit (GCN2 register)  
EN1 bit (GCN2 register)  
EN2 bit (GCN2 register)  
EN3 bit (GCN2 register)  
16-bit reload timer 0/2/4/6  
16-bit reload timer 1/3/5/7  
External trigger 0/4  
External trigger 1/5  
External trigger 2/6  
External trigger 3/7  
None of the above  
Disabled (See “8. Caution (Page No.821)”.)  
• PPG0 to PPG15 as selected are activated when the edge specified by the Trigger Input Edge Selection  
bits (PCN.EGS[1:0]) are detected during the specified activation trigger.  
• For detailed setting of each channel see chapter 7.7 What activation triggers are available and how are  
they selected? (Page No.815)  
805  
Chapter 39 Programmable Pulse Generator  
4.Registers  
4.5 GCN2: General Control Register 2  
Generates PPG0-PPG3, PPG4-PPG7, PPG8-PPG11 and PPG12-PPG15 internal trigger levels using  
software.  
• GCN20 (PPG0-PPG3): Address 0103h (Access: Byte)  
• GCN21 (PPG4-PPG7): Address 0107h (Access: Byte)  
• GCN22 (PPG8-PPG11): Address 010Bh (Access: Byte)  
• GCN23 (PPG12-PPG15): Address 0323h (Access: Byte)  
7
–
6
–
5
–
4
–
3
2
1
0
bit  
EN3  
0
EN2  
0
EN1  
0
EN0  
0
0
0
0
0
Initial value  
Attribute  
R/W0  
R/W0  
R/W0  
R/W0  
R/W  
R/W  
R/W  
R/W  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bits 7-4: Undefined.Always write “0”. The read value is the value as written. (See “8. Caution (Page  
No.821)”.)  
• Bit 3: EN3 trigger input  
• Bit 2: EN2 trigger input  
• Bit 1: EN1 trigger input  
• Bit 0: EN0 trigger input  
EN0, EN1, EN2, and EN3  
Internal Triggers EN0, EN1, EN2, and EN3  
0
1
Set the level to “L”.  
Set the level to “H”.  
• Set the levels of internal triggers EN0, EN1, EN2, and EN3.  
• If any of the EN trigger inputs (EN0, EN1, EN2, EN3) is selected with the trigger specification bits  
(GCN10.TSEL0[3:0], GCN10.TSEL1[3:0], GCN10.TSEL2[3:0], and GCN10.TSEL3[3:0]) of PPG0, PPG1,  
PPG2, PPG3, then the selected EN serves as a PPG trigger input bit.  
• If any of the EN trigger inputs (EN0, EN1, EN2, EN3) is selected with the trigger specification bits  
(GCN11.TSEL0[3:0], GCN11.TSEL1[3:0], GCN11.TSEL2[3:0], and GCN11.TSEL3[3:0]) of PPG4, PPG5,  
PPG6, PPG7, then the selected EN serves as a PPG trigger input bit.  
• If any of the EN trigger inputs (EN0, EN1, EN2, EN3) is selected with the trigger specification bits  
(GCN12.TSEL0[3:0], GCN12.TSEL1[3:0], GCN12.TSEL2[3:0], and GCN12.TSEL3[3:0]) of PPG8, PPG9,  
PPG10, PPG11, then the selected EN serves as a PPG trigger input bit.  
• If any of the EN trigger inputs (EN0, EN1, EN2, EN3) is selected with the trigger specification bits  
(GCN13.TSEL0[3:0], GCN13.TSEL1[3:0], GCN13.TSEL2[3:0], and GCN13.TSEL3[3:0]) of PPG12,  
PPG13, PPG14, of PPG15, then the selected EN serves as a PPG trigger input bit.  
• If the state selected with the trigger input edge selection bit (EGS[1:0]) is generated by software using the  
trigger input bit (selected EN0, EN1, EN2, or EN3), the choice serves as an activation trigger to activate  
the PPG.  
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Chapter 39 Programmable Pulse Generator  
4.Registers  
4.6 PTMR: PPG Timer Register  
Reads the counts of PPG0-PPG3, PPG4-PPG7, PPG8-PPG11 and PPG12-PPG15.  
• PTMR00 (PPG0): Address 0110h (Access: Half-word)  
• PTMR01 (PPG1): Address 0118h (Access: Half-word)  
• PTMR02 (PPG2): Address 0120h (Access: Half-word)  
• PTMR03 (PPG3): Address 0128h (Access: Half-word)  
• PTMR04 (PPG4): Address 0130h (Access: Half-word)  
• PTMR05 (PPG5): Address 0138h (Access: Half-word)  
• PTMR06 (PPG6): Address 0140h (Access: Half-word)  
• PTMR07 (PPG7): Address 0148h (Access: Half-word)  
• PTMR08 (PPG8): Address 0150h (Access: Half-word)  
• PTMR09 (PPG9): Address 0158h (Access: Half-word)  
• PTMR10 (PPG10): Address 0160h (Access: Half-word)  
• PTMR11 (PPG11): Address 0168h (Access: Half-word)  
• PTMR12 (PPG12): Address 0330h (Access: Half-word)  
• PTMR13 (PPG13): Address 0338h (Access: Half-word)  
• PTMR14 (PPG14): Address 0340h (Access: Half-word)  
• PTMR15 (PPG15): Address 0348h (Access: Half-word)  
15  
D15  
1
14  
D14  
1
13  
D13  
1
12  
D12  
1
11  
D11  
1
10  
D10  
1
9
D9  
8
D8  
Bit  
1
1
Initial value  
Attribute  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
7
D7  
6
D6  
5
D5  
4
D4  
3
D3  
2
D2  
1
D1  
0
D0  
Bit  
1
1
1
1
1
1
1
1
Initial value  
Attribute  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• The count of the 16-bit down counter can be read.  
• Be sure to access the PPG Timer register PTMR in half words (16 bits).  
• The register would not be read correctly if it is byte-accessed.  
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Chapter 39 Programmable Pulse Generator  
5.Operation  
5. Operation  
The MB91460 series features a maximum of 16 programmable pulse generators (PPGs), which provide  
programmable pulse output independently or jointly.  
The individual modes of operation are described below.  
5.1 PWM Operation  
In PWM operation, variable-duty pulses are generated from the PPG pin.  
(3)  
Enable count  
CNTE  
(4)  
Activation trigger  
(1)  
8000  
0007  
8000  
PCSR  
0005  
PDUT  
(6) Rewrite  
(2) Write  
8000  
8000  
0007  
Buffer  
(Cycle value)  
(13) Load  
0005  
Load  
Reload  
Reload  
(5)  
(5)  
Buffer  
(Duty value)  
Load  
(13)  
Load  
Down count  
value  
(PTMR)  
(7) Down count  
Match  
0007  
0005  
(8)  
Match  
Match  
(10) Down count  
(11) Borrow  
Borrow  
(9) Invert  
(12)  
Invert  
Clear  
Invert  
Clear  
PPG pin output  
Normal  
polarity  
Duty  
Cycle  
Inverted  
polarity  
Interrupt  
cause  
Effective edge  
Duty match  
Counter borrow  
Duty match  
Counter borrow  
(1) Write a cycle value.  
(2) Write a duty value and transfer the cycle value to buffers.  
(3) Enable PPG operation.  
(4) Generate an activation trigger.  
(5) Load the cycle and duty values.  
(6) Rewrite the duty value and transfer the cycle value to buffers.  
(6) Counter down count  
(7) The down counter equals the duty value.  
(8) Inverses the PPG pin output level.  
(9) Counter down count  
(10) Counter borrow  
(11) Clear the PPG pin output level (return to normal).  
(12) Reload the cycle value.  
(13) Reload the duty value.  
(14) Steps from (6) to (13) are iterated.  
(See “8. Caution (Page No.821)”.)  
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Chapter 39 Programmable Pulse Generator  
5.Operation  
• Equation  
Period = {Period value (PCSR) + 1} x Count clock  
Duty = {Duty value (PDUT) + 1} x Count clock  
Width up to pulse output = {Period value (PCSR) – Duty value (PDUT)} x Count clock  
5.2 One-Shot Operation  
In one-shot operation, one-shot pulses are generated from the PPG pin.  
(3)  
Enable count  
CNTE  
(4)  
Activation trigger  
(1)  
8000  
PCSR  
PDUT  
0007  
(2)  
Buffer  
8000  
(Cycle value)  
(5)  
Load  
0007  
Buffer  
(Duty value)  
(5) Load  
(6) Down count  
Down count  
value  
(PTMR)  
(7)  
Match  
Down count  
0007  
(8)  
Borrow  
(10)  
Clear  
(11)  
Invert  
(9)  
PPG pin output  
Normal  
polarity  
Duty  
Cycle  
Inverted  
polarity  
Interrupt  
cause  
Effective edge  
Counter borrow  
Duty match  
(1) Write a cycle value.  
(2) Write a duty value and transfer the cycle value to buffers.  
(3) Enable PPG operation.  
(4) Generate an activation trigger.  
(5) Load the cycle and duty values.  
(6) Counter down count  
(7) Down counter value and duty value  
(8) Inverse the PPG pin output level.  
(9) Counter down count  
(10) Counter borrow  
(11) Clear the PPG pin output level (return to normal).  
(12) The operating sequence is now completed.  
(See “8. Caution (Page No.821)”.)  
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Chapter 39 Programmable Pulse Generator  
5.Operation  
5.3 Restart Operation  
The restart operation is described below.  
• Restart available in PWM operation:  
Rising edge detection  
Restarted by the trigger  
Trigger  
m
n
0
PPG  
N
T
N = duty, T = cycle  
• Restart available in one-shot operation:  
Rising edge detection  
Restarted by the trigger  
Trigger  
m
n
0
PPG  
N
T
If a restart is not available, the second and subsequent triggers have no effect in both PWM and one-shot  
operations.  
(The second and subsequent triggers following a shutdown of the down counter are functional.)  
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Chapter 39 Programmable Pulse Generator  
6.Setting  
6. Setting  
Table 6-1 Settings Needed to Start the PPG  
Setting  
Procedure*  
Setting  
Setting Registers  
PPG cycle settings (PCSR00-PCSR15)  
PPG duty settings (PDUT00-PDUT15)  
Period and duty value settings  
7.1  
Enable PPG operation.  
7.2  
7.3  
7.4  
7.5  
7.6  
Operation mode selection (PWM/one-shot)  
Enable restart.  
PPG control status (PCN00-PCN15)  
Count clock selection  
PPG output mask selection  
Trigger selection  
Software  
7.7  
General Control 1 (GCN10, GCN11, GCN12,  
GCN13)  
Internal trigger  
External trigger  
Output polarity specification  
PPG pin output setting  
7.8  
7.9  
Port functions (PFR16, PFR17)  
PPG Control Status (PCN00-PCN15)  
Trigger generation (software trigger)  
(Reload timer)  
See “Chapter 38 Reload Timer (Page  
No.775)”.  
7.10  
(GCN2.EN bit)  
General Control 2 (GCN20, GCN21, GCN22,  
GCN23)  
* For refer to the section indicated by the number.  
Table 6-2 Settings Needed to Stop the PPG  
Setting  
Procedure*  
Setting  
Setting Registers  
PPG control status (PCN00-PCN15)  
PPG stop bit setting  
7.11  
*For the setting procedure, refer to the section indicated by the number.  
Table 6-3 Settings Needed to Clamp the Output Level  
Setting  
Procedure*  
Setting  
Setting Registers  
Output polarity specification  
PPG output mask selection  
Period value = Duty value setting  
7.8  
7.6  
7.6  
PPG control status (PCN00-PCN15)  
PPG duty settings (PDUT00-PDUT15)  
*For the setting procedure, refer to the section indicated by the number.  
Table 6-4 Settings Needed to Implement PPG Interrupts  
Setting  
Procedure*  
Setting  
Setting Registers  
See “Chapter 24 Interrupt Control (Page  
No.311)”.  
PPG interrupt vector, PPG interrupt level setting  
7.12  
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Chapter 39 Programmable Pulse Generator  
6.Setting  
Table 6-4 Settings Needed to Implement PPG Interrupts  
PPG interrupt cause selection  
(Generate an activation trigger, borrow, and duty  
match)  
7.13  
7.14  
PPG control status (PCN00-PCN15)  
PPG interrupt setting  
Clear interrupt requests.  
Enable interrupt requests.  
*:For the setting procedure, refer to the section indicated by the number.  
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Chapter 39 Programmable Pulse Generator  
7.Q & A  
7. Q & A  
7.1 How do I set (rewrite) a cycle and a duty?  
Period and duty value settings  
• Set each cycle value in PPG Period Setting Register PCSR.  
• Set each duty value in PPG Duty Setting Register PDUT.  
• The PPG Period Setting and the PPG Duty Setting registers each have a buffer to allow the user to ignore  
the write timing.  
• Equation  
PCSR register value = {Cycle/Count clock} –1  
*
PDUT register value = {“H” width (duty) /Count clock} –1  
*: Normal polarity (OSEL= 0)  
• Allowed range  
PCSR register value = PCSR register value - FFFFh (65535)  
PDUT register value = 0 - PCSR register value  
Note: Be sure to set a cycle following the setting of a cycle. (See “8. Caution (Page No.821)”.)  
7.2 How do I enable or disable PPG operations?  
Enabling the PPG operation  
Use the PPG operation enable bit (PCN.CNTE).  
Control  
PPG Operation Enable Bit (CNTE)  
To stop a PPG operation  
To enable a PPG operation  
Set “0”.  
Set “1”.  
Enable PPG operation before starting the PPG.  
(See “8. Caution (Page No.821)”.)  
7.3 How do I set the PPG operation mode (PWM operation/one-shot operation)?  
Operation mode selection  
Use the mode selection bit (PCN.MDSE).  
Operation Mode  
Mode Selection Bit (MDSE)  
To implement a PWM operation  
To implement a one-shot operation  
Set “0”.  
Set “1”.  
(See “8. Caution (Page No.821)”.)  
7.4 How do I get it restarted?  
Enable restart.  
A restart of a PPG can be enabled while the PPG is in operation.  
Use the Enable Restart bit (PCN.RTRG) to set.  
(See “8. Caution (Page No.821)”.)  
813  
   
Chapter 39 Programmable Pulse Generator  
7.Q & A  
7.5 What count clocks are available and how are they selected?  
Count clock selection  
The count clock is selectable out of the four choices listed below.  
Use the count clock selection bit (PCN.CKS[1:0]).  
Count Clock Selection Bit  
(Example) CLKP = 32 MHz  
Period (1 - FFFFh)  
Count  
Clock  
CKS1  
CKS0  
Count Clock  
32MHz  
8MHz  
CLKP  
0
0
1
1
0
1
0
1
62.5ns - 2.048µs  
250ns - 8.192µs  
1µs - 32.76ms  
4µs - 131.0ms  
CLKP/4  
CLKP/16  
CLKP/64  
2MHz  
500kHz  
(See “8. Caution (Page No.821)”.)  
7.6 How do I clamp the PPG pin output level?  
PPG output mask selection  
The level of PPG pin output can be clamped.  
Use the PPG Output Mask Selection bit (PCN.PGMS) and the duty value (PDUT) to set.  
PPG Output Polarity  
PPG Pin Output  
Specification  
Bit (OSEL)  
Setting Procedure  
Set the PPG Output Mask Selection bit  
(PGMS) to “1”.  
To clamp the “L” level under normal polarity  
To clamp the “H” level under normal polarity  
To clamp the “H” level under inverted polarity  
To clamp the “L” level under inverted polarity  
When “0”  
When “0”  
When “1”  
When “1”  
Period value (PCSR) =  
Set a duty value (PDUT).  
Set the PPG Output Mask Selection bit  
(PGMS) to “1”.  
Period value (PCSR) =  
Set a duty value (PDUT).  
PPG pin output can be set to all “L”. (when OSEL=“0”)  
PPG  
Reduce  
the duty  
value  
Write "1" to PGMS (mask bit) on occurrence  
of an interrupt caused by a borrow.  
If "0" is written to PGMS on occurrence of  
an interrupt caused by a borrow, a PWM  
waveform can be generated without  
incurring hazard output.  
PPG pin output can be set to all “H”. (when OSEL=“0”)  
PPG  
Reduce  
the duty value  
Write the same value as the cycle setting  
register value to the duty setting register  
on occurrence of an interrupt caused by  
a compare match.  
PPG output will also equal all “H” if “0” is set in both the PPG Period Setting Register (PCSR) and PPG Duty  
Setting Register (PDUT). (when OSEL=“0”)  
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Chapter 39 Programmable Pulse Generator  
7.Q & A  
7.7 What activation triggers are available and how are they selected?  
• Trigger selection  
• Activation triggers are broadly grouped into software triggers, internal triggers and external triggers.  
• Software triggers work at all times.  
• Internal and external trigger availability depends on each device specification.  
An trigger is set using the trigger specification bits (GCN1.TSEL0[3:0]), (GCN1.TSEL1[3:0]),  
(GCN1.TSEL2[3:0]), and (GCN1.TSEL3[3:0]).  
Triggers are selectable for PPG0, PPG1, PPG2, and PPG3 independently.  
PPG0  
PPG1  
PPG2  
PPG3  
Internal Trigger  
Internal Trigger Specification Bit  
TSEL0[3:0]  
Set “0000”  
Set “0001”  
Set “0010”  
Set “0011”  
Set “0100”  
Set “0101”  
TSEL1[3:0]  
Set “0000”  
Set “0001”  
Set “0010”  
Set “0011”  
Set “0100”  
Set “0101”  
TSEL2[3:0]  
Set “0000”  
Set “0001”  
Set “0010”  
Set “0011”  
Set “0100”  
Set “0101”  
TSEL3[3:0]  
Set “0000”  
Set “0001”  
Set “0010”  
Set “0011”  
Set “0100”  
Set “0101”  
To select the EN0 bit of the GCN20 register  
To select the EN1 bit of the GCN20 register  
To select the EN2 bit of the GCN20 register  
To select the EN3 bit of the GCN20 register  
To select reload timer 0  
To select reload timer 1  
PPG0  
PPG1  
PPG2  
PPG3  
External Trigger  
External Trigger Specification Bit  
TSEL0[3:0]  
Set “1000”  
Set “1001”  
Set “1010”  
Set “1011”  
TSEL1[3:0]  
Set “1000”  
Set “1001”  
Set “1010”  
Set “1011”  
TSEL2[3:0]  
Set “1000”  
Set “1001”  
Set “1010”  
Set “1011”  
TSEL3[3:0]  
Set “1000”  
Set “1001”  
Set “1010”  
Set “1011”  
To select the external trigger on GP14_0  
To select the external trigger on GP14_1  
To select the external trigger on GP14_2  
To select the external trigger on GP14_3  
Triggers are selectable for PPG4, PPG5, PPG6, and PPG7 independently.  
PPG4  
PPG5  
PPG6  
PPG7  
Internal Trigger  
Internal Trigger Specification Bit  
TSEL0[3:0]  
Set “0000”  
Set “0001”  
Set “0010”  
Set “0011”  
Set “0100”  
Set “0101”  
TSEL1[3:0]  
Set “0000”  
Set “0001”  
Set “0010”  
Set “0011”  
Set “0100”  
Set “0101”  
TSEL2[3:0]  
Set “0000”  
Set “0001”  
Set “0010”  
Set “0011”  
Set “0100”  
Set “0101”  
TSEL3[3:0]  
Set “0000”  
Set “0001”  
Set “0010”  
Set “0011”  
Set “0100”  
Set “0101”  
To select the EN0 bit of the GCN21 register  
To select the EN1 bit of the GCN21 register  
To select the EN2 bit of the GCN21 register  
To select the EN3 bit of the GCN21 register  
To select reload timer 2  
To select reload timer 3  
PPG4  
PPG5  
PPG6  
PPG7  
External Trigger  
External Trigger Specification Bit  
TSEL0[3:0]  
Set “1000”  
Set “1001”  
Set “1010”  
Set “1011”  
TSEL1[3:0]  
Set “1000”  
Set “1001”  
Set “1010”  
Set “1011”  
TSEL2[3:0]  
Set “1000”  
Set “1001”  
Set “1010”  
Set “1011”  
TSEL3[3:0]  
Set “1000”  
Set “1001”  
Set “1010”  
Set “1011”  
To select the external trigger on GP14_4  
To select the external trigger on GP14_5  
To select the external trigger on GP14_6  
To select the external trigger on GP14_7  
815  
 
Chapter 39 Programmable Pulse Generator  
7.Q & A  
Triggers are selectable for PPG8, PPG9, PPG10, and PPG11 independently.  
PPG8  
PPG9  
PPG10  
PPG11  
Internal Trigger  
Internal Trigger Specification Bit  
TSEL0[3:0]  
Set “0000”  
Set “0001”  
Set “0010”  
Set “0011”  
Set “0100”  
Set “0101”  
TSEL1[3:0]  
Set “0000”  
Set “0001”  
Set “0010”  
Set “0011”  
Set “0100”  
Set “0101”  
TSEL2[3:0]  
Set “0000”  
Set “0001”  
Set “0010”  
Set “0011”  
Set “0100”  
Set “0101”  
TSEL3[3:0]  
Set “0000”  
Set “0001”  
Set “0010”  
Set “0011”  
Set “0100”  
Set “0101”  
To select the EN0 bit of the GCN22 register  
To select the EN1 bit of the GCN22 register  
To select the EN2 bit of the GCN22 register  
To select the EN3 bit of the GCN22 register  
To select reload timer 4  
To select reload timer 5  
PPG9  
PPG9  
PPG10  
PPG11  
External Trigger  
External Trigger Specification Bit  
TSEL0[3:0]  
Set “1000”  
Set “1001”  
Set “1010”  
Set “1011”  
TSEL1[3:0]  
Set “1000”  
Set “1001”  
Set “1010”  
Set “1011”  
TSEL2[3:0]  
Set “1000”  
Set “1001”  
Set “1010”  
Set “1011”  
TSEL3[3:0]  
Set “1000”  
Set “1001”  
Set “1010”  
Set “1011”  
To select the external trigger on GP14_0  
To select the external trigger on GP14_1  
To select the external trigger on GP14_2  
To select the external trigger on GP14_3  
Triggers are selectable for PPG12, PPG13, PPG14, and PPG15 independently.  
PPG12  
PPG13  
PPG14  
PPG15  
Internal Trigger  
Internal Trigger Specification Bit  
TSEL0[3:0]  
Set “0000”  
Set “0001”  
Set “0010”  
Set “0011”  
Set “0100”  
Set “0101”  
TSEL1[3:0]  
Set “0000”  
Set “0001”  
Set “0010”  
Set “0011”  
Set “0100”  
Set “0101”  
TSEL2[3:0]  
Set “0000”  
Set “0001”  
Set “0010”  
Set “0011”  
Set “0100”  
Set “0101”  
TSEL3[3:0]  
Set “0000”  
Set “0001”  
Set “0010”  
Set “0011”  
Set “0100”  
Set “0101”  
To select the EN0 bit of the GCN23 register  
To select the EN1 bit of the GCN23 register  
To select the EN2 bit of the GCN23 register  
To select the EN3 bit of the GCN23 register  
To select reload timer 6  
To select reload timer 7  
PPG12  
PPG13  
PPG14  
PPG15  
External Trigger  
External Trigger Specification Bit  
TSEL0[3:0]  
Set “1000”  
Set “1001”  
Set “1010”  
Set “1011”  
TSEL1[3:0]  
Set “1000”  
Set “1001”  
Set “1010”  
Set “1011”  
TSEL2[3:0]  
Set “1000”  
Set “1001”  
Set “1010”  
Set “1011”  
TSEL3[3:0]  
Set “1000”  
Set “1001”  
Set “1010”  
Set “1011”  
To select the external trigger on GP14_4  
To select the external trigger on GP14_5  
To select the external trigger on GP14_6  
To select the external trigger on GP14_7  
The same trigger can be specified for a group of PPGs to activate all these PPGs simultaneously. (See “8.  
Caution (Page No.821)”.)  
• Trigger edge selection  
Trigger edges are set using trigger input edge selection bits (PCN.EG[1:0]).  
Trigger Edge Selection  
Trigger Input Edge Selection Bits (EG1-EG0)  
When not detected (software trigger only)  
“L” -> “H” Trigger generated on the rising edge  
“H” -> “L” Trigger generated on the falling edge  
Trigger generated on both edges  
Set “00”.  
Set “01”.  
Set “10”.  
Set “11”.  
(See “8. Caution (Page No.821)”.)  
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Chapter 39 Programmable Pulse Generator  
7.Q & A  
7.8 How do I invert the output polarity?  
Output polarity specification  
The polarity in the normal state can be specified as follows:  
Use the PPG Output Polarity Specification bit (PCN.OSEL) to set.  
(“Normal state” means the state in which pulse output is not executed.)  
Output Level in Normal State  
PPG Output Polarity Specification Bit (OSEL)  
To enable “L” level output (normal polarity)  
Set “0”.  
Set “1”.  
To enable “H” level output (inverted polarity)  
(See “8. Caution (Page No.821)”.)  
7.9 How do I program a pin as a PPG output pin?  
-> PPG pin output setting  
Software programming allows ports to be switched to PPG pin output.  
Pin  
Control Bit Location  
Port Function register PFR17.0 = ‘1’ PPG0 Output specification bit (PPG0)  
PPG0 pin  
PPG1 pin  
PPG2 pin  
PPG3 pin  
PPG4 pin  
PPG5 pin  
PPG6 pin  
PPG7 pin  
PPG8 pin  
PPG9 pin  
PPG10 pin  
PPG11 pin  
PPG12 pin  
PPG13 pin  
PPG14 pin  
PPG15 pin  
Port Function register PFR17.1 = ‘1’  
Port Function register PFR17.2 = ‘1’  
Port Function register PFR17.3 = ‘1’  
Port Function register PFR17.4 = ‘1’  
Port Function register PFR17.5 = ‘1’  
Port Function register PFR17.6 = ‘1’  
Port Function register PFR17.7 = ‘1’  
Port Function register PFR16.0 = ‘1’  
Port Function register PFR16.1 = ‘1’  
Port Function register PFR16.2 = ‘1’  
Port Function register PFR16.3 = ‘1’  
Port Function register PFR16.4 = ‘1’  
Port Function register PFR16.5 = ‘1’  
Port Function register PFR16.6 = ‘1’  
Port Function register PFR16.7 = ‘1’  
PPG1 Output specification bit (PPG1)  
PPG2 Output specification bit (PPG2)  
PPG3 Output specification bit (PPG3)  
PPG4 Output specification bit (PPG4)  
PPG5 Output specification bit (PPG5)  
PPG6 Output specification bit (PPG6)  
PPG7 Output specification bit (PPG7)  
PPG8 Output specification bit (PPG8)  
PPG9 Output specification bit (PPG9)  
PPG10 Output specification bit (PPG10)  
PPG11 Output specification bit (PPG11)  
PPG12 Output specification bit (PPG12)  
PPG13 Output specification bit (PPG13)  
PPG14 Output specification bit (PPG14)  
PPG15 Output specification bit (PPG15)  
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Chapter 39 Programmable Pulse Generator  
7.Q & A  
7.10 How do I generate an activation trigger?  
Generating a trigger  
Methods of generating an activation trigger are described below.  
• Activating a software trigger  
Use the Software Trigger bit (PCN.STGR) to set.  
Write “1” to the Software Trigger bit (STGR) to generate an activation trigger.  
Always functional, regardless of the internal trigger.  
• Activating PPGs with reload timers  
The reload timers need to be set up and activated. For more information, see “Chapter 38 Reload Timer (Page  
No.775)”.  
An activation trigger is generated when the edge specified by the reload timer output signal is generated with the  
reload timer underflow.  
• Activating PPGs with external triggers  
An activation trigger is generated when the edge specified on the specified pin appears. There is no need for  
configuration of the port registers; the trigger is always connected to the PPGs.  
• Activating a PPG with the EN trigger input bits (GCN2.EN0) - (GCN2.EN3)  
An activation trigger can be generated by rewriting the level of the EN trigger input bits (GCN2.EN0) - (GCN2.EN3).  
Edge  
Software-Based Setting Procedure (EN0, EN1, EN2, EN3)  
First, set the EN bit to “0”, then the EN bit to “1”.  
First, set the EN bit to “1”, then to “0”.  
Rising edge  
Falling edge  
• Activating multiple PPGs concurrently  
The same trigger (trigger input bit) can be specified with the PPG trigger specification bits to activate all the PPGs  
simultaneously when the trigger is generated.  
• Even if an activation trigger is generated before the operation of a PPG is enabled, that PPG would not be  
activated. Be sure to enable the operation of a PPG before generating a trigger to activate it. (See “7.2 How  
do I enable or disable PPG operations? (Page No.813)”.)  
7.11 How do I stop a PPG operation?  
PPG stop bit setting (See “7.2 How do I enable or disable PPG operations? (Page No.813)”.)  
7.12 What interrupt registers are used?  
PPG interrupt vector, PPG interrupt level setting  
The table below summarizes the relationships among the PPG number, interrupt level and interrupt vector.  
For more information about the interrupt levels and interrupt vectors, see “Chapter 24 Interrupt Control (Page  
No.311)”.  
Interrupt Vector (Default)  
Interrupt Level Setting Bit (ICR[4:0])  
#112  
Address: 0FFE3Ch  
PPG0  
PPG1  
PPG2  
PPG3  
PPG4  
PPG5  
Interrupt Level register (ICR48)  
Address: 0470h  
#113  
Address: 0FFE38h  
#114  
Address: 0FFE34h  
Interrupt Level register (ICR49)  
Address: 0471h  
#115  
Address: 0FFE30h  
#116  
Address: 0FFE2Ch  
Interrupt Level register (ICR50)  
Address: 0472h  
#117  
Address: 0FFE28h  
818  
Chapter 39 Programmable Pulse Generator  
7.Q & A  
#118  
Address: 0FFE24h  
PPG6  
PPG7  
Interrupt Level register (ICR51)  
Address: 0473h  
#119  
Address: 0FFE20h  
#120  
Address: 0FFE1Ch  
PPG8  
Interrupt Level register (ICR52)  
Address: 0474h  
#121  
Address: 0FFE18h  
PPG9  
#122  
Address: 0FFE14h  
PPG10  
PPG11  
PPG12  
PPG13  
PPG14  
PPG15  
Interrupt Level register (ICR53)  
Address: 0475h  
#123  
Address: 0FFE10h  
#124  
Address: 0FFE0Ch  
Interrupt Level register (ICR54)  
Address: 0476h  
#125  
Address: 0FFE08h  
#126  
Address: 0FFE04h  
Interrupt Level register (ICR55)  
Address: 0477h  
#127  
Address: 0FFE00h  
The Interrupt Request flag (PCN.IRQF) does not clear itself automatically. Use software to clear it before returning from  
the interrupt handler. (Write “0” to the IRQF bit.)  
819  
Chapter 39 Programmable Pulse Generator  
7.Q & A  
7.13 What interrupts are available and how are they selected?  
Interrupt cause selection  
Four kinds of interrupts are selectable as follows:  
Use the Interrupt Cause Setting bit (PCN.IRS[1:0]) to set.  
Interrupt Cause  
Software trigger or Internal trigger generation (PPG0-PPG15)  
Down counter borrow (cycle match)  
Interrupt Cause Setting Bit (IRS[1:0])  
Set “00”.  
Set “01”.  
Set “10”.  
Set “11”.  
Duty match  
Down counter borrow (cycle match) or Duty match  
7.14 How do I enable, disable and clear interrupts?  
Interrupt Request Enable flag, Interrupt Request flag  
Use the interrupt request enable bit (PCN.IREN) to enable interrupts.  
Interrupt Request Enable Bit (IREN)  
To disable interrupt requests  
To enable interrupt requests  
Set “0”.  
Set “1”.  
Use the interrupt request bit (PCN.IRQF) to clear interrupt requests.  
Interrupt Request Bit (IRQF)  
Write “0”.  
To select interrupt request  
(See “8. Caution (Page No.821)”.)  
820  
Chapter 39 Programmable Pulse Generator  
8.Caution  
8. Caution  
• If the Interrupt Request flag (PCN.IRQF) equals “1” and the Interrupt Request flag is set to “0” at the same  
time, the setting of the Interrupt Request flag to “1” overrides the flag clear request.  
• The first load comes with a maximum delay of 2.5T after the activation trigger. (T: Count clock)  
If the down counter is loaded and counts at the same time, the load operation overrides.  
Trigger  
Maximum 2.5T  
Load  
Clock  
Count value  
PPG  
X
0003  
0002  
0001  
0000  
0003  
0002  
Interrupt  
Effective edge  
Duty match  
Counter borrow  
• Be sure to write duty value PDUT after cycle PCSR has been initialized and rewritten.  
(Always write in the order of (1)PCSR and (2)PDUT.)  
Only the PDUT can be written for rewriting the duty.  
• Set the duty value PDUT smaller than the cycle value PCSR. If any larger value has been set, disable the  
operation of the PPG before replacing the duty with a smaller value.  
• Always access PPG Period Setting registers PCSR and PPG Duty Setting registers in a half-word (16-bit)  
format. If these registers are byte-accessed, no values would be written to their upper and lower bit  
positions.  
• To activate a PPG, it is necessary to set the Timer Operation Enable bits (PCN.CNTE) to “1” before or  
concurrently with the activation to enable the PPG operation.  
• The values of mode (MDSE), restart enable (RTRG), count clock (CKS[1:0]), trigger input edge (EGS[1:0]),  
interrupt cause (IRS), internal trigger (TSEL) and output polarity specification (OSEL) may not be changed  
while the PPG is operating.  
If any of these values has been changed while the PPG was operating, disable the operation of the PPG  
before reloading the register.  
• Whenever writing a value to GCN2, be sure to write “0” to any undefined part of the upper 4 bits.  
If “1” is written, disable the operation of the PPG before reloading the register.  
• If any value outside the specified range (0110, 0111, 1100 - 1111) is set in Activation Trigger Specification  
bits (TSEL0[3:0]), (TSEL1[3:0]), (TSEL2[3:0]), (TSEL3[3:0]) has been set, disable the operation of the PPG  
and then write the specified value to let the register return to normal.  
• If the Timer Operation Enable bit (PCN.CNTE) is set to “0” to disable PPGn while it is operating, the PPG  
stops, with its status (count and output level) being latched.  
If the Timer Operation Enable bit is subsequently set to (PCN.CNTE) “1” to enable the PPG, it restarts from  
the point of interruption.  
821  
 
Chapter 39 Programmable Pulse Generator  
8.Caution  
822  
Chapter 40 Pulse Frequency Modulator  
1.PFM Overview  
Chapter 40 Pulse Frequency Modulator  
This chapter provides an overview of the 16-bit pulse frequency modulator, describes the regis-  
ter structure/functions, and describes the operation of the 16-bit pulse frequency modulator.  
1. PFM Overview  
The 16-bit pulse frequency modulator consists of two 16-bit down-counters, two 16-bit reload  
registers, prescalers for generating the internal count clocks and control registers.  
■ Functions  
• Two independent programmable 16-bit down-counters generating low and high pulses.  
• The input clock can be selected from prescaled internal clocks (the machine clock divided by 2/8/32/64/128)  
separately for each counter.  
• The mark level and output waveform can be inverted.  
823  
   
Chapter 40 Pulse Frequency Modulator  
1.PFM Overview  
■ 16-bit Reload Counter 0 Register Configuration  
Register structure  
12 11 10  
Register  
Name  
15  
–
14  
INV  
6
13  
–
9
–
1
8
MOD1  
0
CSL2 CSL1 CSL0  
7
5
4
3
2
Control status register  
P0TMCSR  
–
–
–
RELD INTE UF CNTE TRG  
0
15  
15  
16-bit counter register  
16-bit reload register  
P0TMR  
0
P0TMRLR  
■ 16-bit Reload Counter 1 Register Configuration  
Register structure  
Register  
Name  
15  
–
14  
INV  
6
13  
–
12  
11  
10  
9
–
1
8
MOD1  
0
CSL2 CSL1 CSL0  
7
5
4
3
2
Control status register  
P1TMCSR  
–
–
–
RELD INTE UF CNTE TRG  
0
15  
15  
16-bit counter register  
16-bit reload register  
P1TMR  
0
P1TMRLR  
Figure 1-1 16-bit Reload Counter Register Configuration  
824  
Chapter 40 Pulse Frequency Modulator  
1.PFM Overview  
■ Block Diagram of the 16-Bit Pulse Frequency Modulator  
16  
16-bit reload register  
8
Reload  
RELD  
–
UF  
16-bit down-counter  
16  
–
INTE  
GATE  
CSL2  
UF  
CNTE  
CSL1  
CSL0  
Clock selector  
TRG  
INV  
3
φ
φ
φ
φ
φ
Clear  
prescaler  
21 23 25 26 27  
OUT  
Internal clock  
Pulse Gen.  
16  
16-bit reload register  
IRQ  
8
Reload  
RELD  
–
UF  
16-bit down-counter  
16  
–
INTE  
GATE  
CSL2  
UF  
CNTE  
CSL1  
CSL0  
Clock selector  
TRG  
3
φ
φ
φ
φ
φ
Clear  
prescaler  
21 23 25 26 27  
Internal clock  
Figure 1-2 Block Diagram of the 16-bit Pulse Frequency Modulator  
825  
Chapter 40 Pulse Frequency Modulator  
2.Reload Counter Registers  
2. Reload Counter Registers  
This section describes the 16-bit pulse frequency modulator registers listed below.  
Control status register (P0TMCSR, P1TMCSR)  
16-bit counter register (P0TMR, P1TMR)  
16-bit reload register (P0TMRLR, P1TMRLR)  
■ Control Status Register (P0TMCSR, P1TMCSR)  
Controls the operation mode and interrupts for the 16-bit reload counter.  
Only change the value of bits other than UF and TRG when CNTE = "0".  
The bits can be written simultaneously.  
● P0TMCSR, P1TMCSR structure  
Address  
0000 0170H  
0000 0172H  
Bits  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
Reserved  
Reserved  
Reserved Reserved Reserved  
Reserved  
INV  
CSL2 CSL1 CSL0  
RELD INTE UF CNTE TRG  
MOD1  
Access  
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W  
Initial value : -0-000-0 ---00000H  
Figure 2-1 Structure of the Control Status Register  
● Functions of the P0TMCSR, P1TMCSR bits  
[Bit 15] Reserved  
Always set to "0".  
[Bit 14] INV (INVersion)  
The output signal inversion bit.  
"0" is default level (counter 0 high level, counter 1 low level).  
"1" inverts the output signal (counter 0 low level, counter 1 high level).  
Remark: Writing INV of P0TMCSR or INV of P1TMCSR or both has the same effect.  
[Bit 13] Reserved  
Always set to "0".  
[Bits 12, 10] CSL2, CSL1, CSL0 (Count clock SeLect)  
The count clock select bits.  
Table 2.1 lists the clock source selections.  
826  
 
Chapter 40 Pulse Frequency Modulator  
2.Reload Counter Registers  
Table 2-1 CSL Bit Clock Source Settings  
CSL2  
CSL1  
CSL0  
Clock source (φ : Machine clock)  
1
3
5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
φ / 2  
φ / 2  
φ / 2  
Setting disabled  
Setting disabled  
6
φ / 2  
7
φ / 2  
Setting disabled  
[Bits 9] Reserved  
Always set to "0".  
[Bits 8] MOD1  
Sets the Trigger level to Falling edge (MOD1=’1’ is necessary for PFM operation)  
[Bits 7 to 5] Reserved  
Always set to "010".  
[Bit 4] RELD  
This bit enables reload operations.  
When RELD is "1", the counter operates in reload mode. In this mode, the counter loads the  
reload register contents into the counter and continues counting whenever an underflow  
occurs (when the counter value changes from 0000H to FFFFH).  
When RELD is "0", the count operation stops when an underflow occurs due to the counter  
value changing from 0000H to FFFFH.  
[Bit 3] INTE  
The interrupt request enable bit.  
When INTE is "1", an interrupt request is generated when the UF bit changes to "1".  
When INTE is "0", no interrupt requests are generated.  
[Bit 2] UF  
The counter interrupt request flag.  
UF is set to "1" when an underflow occurs (when the counter value changes from 0000H to  
FFFFH).  
Writing "0" clears the bit. Writing "1" has no meaning. Read as "1" by read-modify-write  
instructions.  
[Bit 1] CNTE  
The counter count enable bit.  
827  
Chapter 40 Pulse Frequency Modulator  
2.Reload Counter Registers  
Writing "1" sets the counter to wait for a trigger.  
Writing "0" stops count operation.  
[Bit 0] TRG  
Software trigger bit.  
Writing "1" to TRG applies a software trigger, causing the counter to load the reload register  
contents to the counter and start counting.  
Writing "0" has no meaning. Reading always returns "0".  
Applying a trigger using this register is only valid when CNTE = "1". Writing "1" has no effect if  
CNTE = "0".  
■ 16-bit Counter Register (P0TMR, P1TMR)  
Reading this register reads the count value of the 16-bit counter.  
The initial value is indeterminate.  
Always read this register using 16-bit data transfer instructions.  
● P0TMR, P1TMR structure  
Address  
0000 0174H  
0000 0178H  
15  
0
R
R
R
R
• • •  
• • •  
R
R
R
R
R
Access  
Initial value  
×
×
×
×
×
×
×
×
×
Figure 2-2 Structure of the 16-bit Counter Register  
■ 16-bit Reload Register (P0TMRLR, P1TMRLR)  
The 16-bit reload register stores the initial count value.  
The initial value is indeterminate.  
Always write to this register using 16-bit data transfer instructions.  
828  
Chapter 40 Pulse Frequency Modulator  
2.Reload Counter Registers  
● P0TMRLR, P1TMRLR structure  
Address  
15  
0
0000 0176H  
0000 017AH  
W
W
W
W
• • •  
• • •  
W
W
W
W
W
Access  
Initial value  
×
×
×
×
×
×
×
×
×
Figure 2-3 Structure of the 16-bit Reload Register  
829  
Chapter 40 Pulse Frequency Modulator  
3.Reload Counter Operation  
3. Reload Counter Operation  
This section describes the operations of the 16-bit reload counter: Internal clock operation and  
Underflow operation  
■ Internal Clock Operation  
The machine clock divided by 2, 8, 32, 64 or 128 can be selected as the clock source when  
operating the counter from an internal clock.  
Writing "1" to both the CNTE and TRG bits in the control status register enables and starts  
counting simultaneously.  
Using the TRG bit as a trigger input is always available when the counter is enabled (CNTE =  
"1"), regardless of the operation mode.  
Figure 3-1 shows counter activation and counter operation.  
A time f (f: peripheral clock machine cycle) is required from the counter start trigger being input  
until the reload register data is loaded into counter.  
● Counter activation and operation timing  
Count clock  
Counter  
Reload data  
–1  
–1  
–1  
Data load  
CNTE (register)  
TRG (register)  
φ
Figure 3-1 Counter Activation and Operation Timing  
■ Underflow Operation  
An underflow occurs when the counter value changes from 0000H to FFFFH. Therefore, an  
underflow occurs after "reload register setting + 1" counts.  
If the RELD bit in the control register is "1" when the underflow occurs, the contents of the reload  
register are loaded into the counter and counting continues. When RELD is "0", counting stops  
with the counter at FFFFH.  
The UF bit in the control register is set when the underflow occurs. If the INTE bit is "1" at this  
time, an interrupt request is generated.  
Figure 3-2 shows the operation when an underflow occurs.  
830  
 
Chapter 40 Pulse Frequency Modulator  
3.Reload Counter Operation  
● Underflow operation timing  
• When RELD = "1"  
Count clock  
Counter  
0000H  
Reload data  
–1  
–1  
–1  
Data load  
Underflow set  
• When RELD = "0"  
Count clock  
Counter  
0000H  
FFFFH  
Underflow set  
Figure 3-2 Underflow Operation Timing  
■ Counter Operation States  
The counter state is determined by the CNTE bit in the control register and the internal WAIT  
signal. The available states are CNTE = "0" and WAIT = "1" (STOP state: operation halted),  
CNTE = "1" and WAIT = "1" (WAIT state: waiting for a trigger), and CNTE = "1" and WAIT = "0"  
(RUN state: operating).  
Figure 3-3 shows the transitions between each state.  
831  
Chapter 40 Pulse Frequency Modulator  
3.Reload Counter Operation  
● Counter state transitions  
State transitions by hardware  
State transitions by register access  
Reset  
STOP  
CNTE= "0", WAIT= "1"  
Counter: Stores the value when  
counting stopped.  
Indeterminate after a reset.  
CNTE= "0"  
CNTE= "0"  
CNTE= "1"  
TRG= "1"  
CNTE= "1"  
TRG= "0"  
RUN  
WAIT  
CNTE= "1", WAIT="1"  
CNTE= "1", WAIT= "0"  
Counter: Running  
Counter: Stores the value when  
counting stopped.  
Indeterminate after a reset  
until loaded.  
RELD•UF  
TRG= "1"  
TRG= "1"  
RELD•UF  
LOAD  
CNTE= "1", WAIT= "0"  
Load complete  
Load contents of the reload  
register to the counter.  
Figure 3-3 Counter State Transitions  
832  
Chapter 40 Pulse Frequency Modulator  
4.PFM Operation and Setting  
4. PFM Operation and Setting  
This section describes the following operations of the 16-bit pulse frequency mod (combining the  
functionality of both reload counters).  
1. The underflow output of reload counter channel 0 is connected internally to the trigger input reload  
counter channel 1. The underflow output of reload counter channel 1 is connected internally to the  
trigger input of reload counter channel 0.  
2. Both counters must be set up with RELD = “0”. Counter 0 should then be started by software  
trigger TRG = “1”. By starting counter 0 a high level is generated at the output. At the underflow  
condition of counter 0, counter 1 is automatically reloaded and started by the internal trigger (falling  
edge, set MOD1 = “1” for both counters) and a low level is generated at the output. At the underflow  
condition of counter 1, counter 0 is automatically reloaded and started by the internal trigger and a high  
level is generated at the output.  
3. Interrupts can be set up on underflow condition of counter 0, counter 1 or both. The interrupts of  
counter 0 and counter 1 are OR’ed together,  
4. The default output is low level if both CNTE = “0”, and both INV = “0”.  
833  
 
Chapter 40 Pulse Frequency Modulator  
4.PFM Operation and Setting  
834  
Chapter 41 Up/Down Counter  
1.Overview  
Chapter 41 Up/Down Counter  
1. Overview  
Triggered by an input signal, 16-bit Up/Down Counter counts up or down within the range of 0 to 65535.  
Specifically, Up/Down Counter running in the phase difference count mode is suitable for counting the encoder  
pulse of motors and other equipment. When encoder's output signals of phase A, phase B and phase Z are  
applied, the counter can achieve precise counting of rotation angles or number of revolutions.  
Reload/Compare value  
Internal clock  
Compare-match  
Underflow  
Reload  
External input  
A/B/Z  
Up/Down Counter  
Clear  
2. Feature  
• Format: 16 bit length or 8 bit x 2  
• Quantity: 2 for 16 bit (Inputs: AIN0/BIN0/ZIN0, AIN2/BIN2/ZIN2)  
4 for 8 bit (Inputs: AIN0/BIN0/ZIN0, AIN1/BIN1/ZIN1, AIN2/BIN2/ZIN2, AIN3/BIN3/ZIN3)  
• Count mode: Four types  
• Timer mode  
Count down the internal clock.  
• Up/down count mode  
Counting up is triggered by an AIN pin signal.  
Counting down is triggered by a BIN pin signal.  
• Phase difference count mode (Multiply by 2)  
Counting is triggered by the rising edge of a BIN pin signal. Up/Down Counter counts up or down,  
depending on the AIN pin signal level.  
• Phase difference count mode (Multiply by 4)  
Counting is triggered by the rising edge of AIN and BIN pin signals. Up/Down Counter counts up or  
down, depending on the ZIN pin signal level.  
• Count Source  
Internal clock (Timer mode): Peripheral clock (CLKP) divided by 2 or 8  
External trigger (Up/down count mode): Edge detection (Rising/falling/both edges/no detection)  
• Counting range: Any value between 0 and 65535 can be set.  
• Interrupt: Select from the following four types:  
(1) Compare-match interrupt  
(2) Underflow interrupt  
(3) Overflow interrupt  
(4) Count direction change interrupt  
• Others:  
Whether counting is performed or not can be controlled based on the pin input level.  
The software can activate or deactivate the counter.  
The ZIN pin has two functions: Counter clear and gate.  
The count direction flag allows identification of the previous count direction.  
835  
     
Chapter 41 Up/Down Counter  
3.Configuration  
3. Configuration  
Figure 3-1 Configuration Diagram  
Up/Down Counter 0 (8 Bit Mode)  
8 bit mode  
CFIE UDCC0: bit 13  
M16E UDCC0: bit15  
0
1
Disable interrupts  
Enable interrupts  
0
8 bit mode  
0
CDCF UDCC0: bit14  
1
0
1
No change direction  
Direction changed  
WRITE 0: Flag clear  
UDC0 interrupt  
(#128)  
OR  
UDF1-0  
UDCS0: bit 1-0  
Write: Disabled, Read only  
No input  
CMS1-0  
UDCC0: bit11 -10  
Timer mode (Countdown only)  
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
Countdown  
Up/down count mode  
CSTR  
0
1
Countup  
UDCS0: bit7  
Stop counting  
Start counting  
Phase difference count mode (Multiply by 2)  
Phase difference count mode (Multiply by 4)  
Both countdown and countup  
UDIE UDCS0: bit5  
Disable interrupts  
Activation  
0
1
OVFF UDCS0: bit3  
Enable interrupts  
0
1
No overflow  
Peripheral clock  
CLKP  
Overflowed  
Up/Down Counter (Read only)  
Prescaler  
WRITE 0: Flag clear  
1
OR  
UDCR0  
UDFF UDCS0: bit2  
0
1
No underflow  
Underflowed  
CLKS UDCC0: bit 12  
From port data  
register  
1
0
0
0
1
CLKP divided by 2  
Counter clear  
WRITE 0: Flag clear  
CLKP divided by 8  
Reload  
RLDE UDCC0: bit4  
0
UDCC0: bit6  
P20 EPFR20.0  
CTUT  
CMPF UDCS0: bit4  
Compare match  
No compare match  
Others  
Enable UDC  
0
1
0
1
No impact  
Data transfer  
Disable reload  
Enable reload  
0
1
Read from port  
Com-  
pare  
0
1
1
* Only 16 bit transfer is enabled  
while counting stops.  
WRITE 0: Flag clear  
Edge  
AIN0/SIN2/P20.0  
detection  
OR  
CITE UDCS0: bit6  
Disable interrupts  
0
1
BIN0/SOT2/P20.1  
P20 EPFR20.1  
Enable interrupts  
Gate  
UDRC0  
0
1
Others  
Enable UDC  
CES1-0 UDCC0: bit 9-8  
UCRE  
UDCC0:bit5  
0
1
Reload/compare register (Write only)  
Read  
from  
port  
0
0
1
1
0
1
0
1
Disable edge detection  
Enable falling edge detection  
Enable rising edge detection  
Disable counter clear  
Enable counter clear  
0
1
UDCLR UDCC0: bit2  
Enable both edge detection  
From port data  
register  
0
1
Clear  
Disabling  
Read from  
port  
UDCC0: bit1-0, bit 2  
CGSC  
1: Gate function  
ZIN0/SCK2/P20.2  
P20 EPFR20.2  
0
1
Edge  
detection  
0: Counter clear function  
CGE1-0  
Disable edge detection Disable level detection  
Enable falling edge detection Enable LOW level detection  
Enable rising edge detection Enable HIGH level detection  
0
0
1
1
0
1
0
1
Others  
From port data  
register  
Enable UDC  
Disable setting  
Disable setting  
836  
 
Chapter 41 Up/Down Counter  
3.Configuration  
Figure 3-2 Configuration Diagram  
Up/Down Counter 1 (8 Bit Mode)  
8 bit mode  
CFIE UDCC1: bit 13  
M16E UDCC0: bit15  
0
1
Disable interrupts  
Enable interrupts  
0
8 bit mode  
0
CDCF UDCC1: bit14  
1
0
1
No change direction  
Direction changed  
WRITE 0: Flag clear  
UDC1 interrupt  
(#129)  
OR  
UDF1-0  
UDCS1: bit 1-0  
Write: Disabled, Read only  
No input  
CMS1-0  
UDCC1: bit11-10  
Timer mode (Countdown only)  
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
Countdown  
Up/down count mode  
CSTR  
0
1
Countup  
UDCS1: bit7  
Stop counting  
Start counting  
Phase difference count mode (Multiply by 2)  
Phase difference count mode (Multiply by 4)  
Both countdown and countup  
UDIE UDCS1: bit5  
Disable interrupts  
Activation  
0
1
OVFF UDCS1: bit3  
Enable interrupts  
0
1
No overflow  
Peripheral clock  
CLKP  
Overflowed  
Up/Down Counter (Read only)  
Prescaler  
WRITE 0: Flag clear  
1
OR  
UDCR1  
UDFF UDCS1: bit2  
0
1
No underflow  
Underflowed  
CLKS UDCC1: bit 12  
From port data  
register  
1
0
0
0
1
CLKP divided by 2  
Counter clear  
WRITE 0: Flag clear  
CLKP divided by 8  
Reload  
RLDE UDCC1: bit4  
0
UDCC1: bit6  
P20 EPFR20.4  
CTUT  
CMPF UDCS1: bit4  
Compare match  
No compare match  
Others  
Enable UDC  
0
1
0
1
No impact  
Data transfer  
Disable reload  
Enable reload  
0
1
Read from port  
Com-  
pare  
0
1
1
* Only 16 bit transfer is enabled  
while counting stops.  
WRITE 0: Flag clear  
Edge  
AIN1/SIN3/P20.4  
detection  
OR  
CITE UDCS1: bit6  
Disable interrupts  
0
1
BIN1/SOT3/P20.5  
P20 EPFR20.5  
Enable interrupts  
Gate  
UDRC1  
0
1
Others  
Enable UDC  
CES1-0 UDCC1: bit 9-8  
UCRE  
UDCC1:bit5  
0
1
Reload/compare register (Write only)  
Read  
from  
port  
0
0
1
1
0
1
0
1
Disable edge detection  
Enable falling edge detection  
Enable rising edge detection  
Disable counter clear  
Enable counter clear  
0
1
UDCLR UDCC1: bit2  
Enable both edge detection  
From port data  
register  
0
1
Clear  
Disabling  
Read from  
port  
UDCC1: bit1-0, bit 2  
CGSC  
1: Gate function  
ZIN1/SCK3/P20.6  
P20 EPFR20.6  
0
1
Edge  
detection  
0: Counter clear function  
CGE1-0  
Disable edge detection Disable level detection  
Enable falling edge detection Enable LOW level detection  
Enable rising edge detection Enable HIGH level detection  
0
0
1
1
0
1
0
1
Others  
From port data  
register  
Enable UDC  
Disable setting  
Disable setting  
837  
Chapter 41 Up/Down Counter  
3.Configuration  
Figure 3-3 Configuration Diagram  
Up/Down Counter (16 Bit Mode)  
16 bit mode  
CFIE  
0
1
UDCC0: bit 13  
Disable interrupts  
Enable interrupts  
M16E UDCC0: bit15  
1
16 bit mode  
0
1
CDCF UDCC0: bit14  
0
1
No change direction  
Direction changed  
UDC0 interrupt  
(#128)  
WRITE 0: Flag clear  
OR  
UDF1-0  
UDCS0: bit 1 -0  
CMS1-0  
UDCC0: bit11-10  
Write: Disabled, Read only  
No input  
Countdown  
Countup  
Both countdown and countup  
0
0
1
1
0
1
0
1
Timer mode (Countdown only)  
Up/down count mode  
0
0
1
1
0
1
0
1
Activation  
CSTR UDCS0: bit7  
Phase difference count mode (Multiply by 2)  
Phase difference count mode (Multiply by 4)  
0
1
Stop counting  
Start counting  
UDIE UDCS0: bit5  
0
1
Disable interrupts  
OVFF UDCS0: bit3  
Enable interrupts  
0
1
No overflow  
Peripheral clock  
CLKP  
Overflowed  
Up/Down Counter (Read only)  
Prescaler  
WRITE 0: Flag clear  
1
OR  
UDCR1  
UDCR0  
UDFF UDCS0: bit2  
0
1
No underflow  
Underflowed  
From port data  
register  
0
1
CLKS UDCC0: bit 12  
CLKP divided by 2  
Counter clear  
0
WRITE 0: Flag clear  
0
1
0
Reload  
CLKP divided by 8  
CMPF UDCS0: bit4  
Com-  
pare  
P20 EPFR20.0  
CTUT UDCC0: bit6  
RLDE UDCC0: bit4  
0
1
Compare match  
0
1
Others  
Enable UDC  
No impact  
Data transfer  
0
1
0
1
Disable reload  
Enable reload  
Read from port  
1
No compare match  
WRITE 0: Flag clear  
* Only 16 bit transfer is enabled  
while counting stops.  
AIN0/SIN2/P20.0  
Edge  
detection  
CITE UDCS0: bit6  
OR  
Disable interrupts  
0
1
UDRC1  
Reload/compare register (Write only)  
UDRC0  
Enable interrupts  
BIN0/SOT2/P20.1  
P20 EPFR20.1  
Gate  
0
1
UCRE  
0
1
UDCC0:bit5  
Disable counter clear  
Enable counter clear  
0
1
Others  
Enable UDC  
CES1-0 UDCC0: bit 9 -8  
Read  
from  
port  
0
0
1
1
0
1
0
1
Disable edge detection  
Enable falling edge detection  
Enable rising edge detection  
Enable both edge detection  
UDCC0: bit2  
From port data  
register  
0
1
Counter clear  
No impact  
Read from  
port  
UDCC0: bit1-0, bit 2  
CGSC  
CGE1-0 0: Counter clear function  
ZIN0/SCK2/P20.2  
P20 EPFR20.2  
Edge  
detection  
1: Gate function  
0
0
1
1
0
1
0
1
Disable edge detection Disable level detection  
Enable falling edge detection Enable LOW level detection  
Enable rising edge detection Enable HIGH level detection  
0
1
Others  
Enable UDC  
From port data  
register  
Disable setting  
Disable setting  
Figure 3-4 Register List  
Note: For ICR registers and interrupt vectors, refer to “Chapter 24 Interrupt Control (Page No.311)”.  
838  
Chapter 41 Up/Down Counter  
3.Configuration  
Figure 3-5 Register List  
Note: For ICR registers and interrupt vectors, refer to “Chapter 24 Interrupt Control (Page No.311)”.  
Figure 3-6 Register List  
Note: For ICR registers and interrupt vectors, refer to “Chapter 24 Interrupt Control (Page No.311)”.  
839  
Chapter 41 Up/Down Counter  
4.Register  
4. Register  
4.1 UDCC: Counter Control Register  
This register is used to control behaviors of Up/Down Counter.  
• UDCC0 (Up/Down Counter 0): Address 0304 (Access: Byte, Half-word)  
H
• UDCC1 (Up/Down Counter 1): Address 0308 (Access: Byte, Half-word)  
H
• UDCC2 (Up/Down Counter 2): Address 0314 (Access: Byte, Half-word)  
H
• UDCC3 (Up/Down Counter 3): Address 0318 (Access: Byte, Half-word)  
H
15  
14  
13  
12  
11  
10  
9
8
bit  
M16E/  
Reserved  
CDCF  
CFIE  
CLKS  
CMS1  
CMS0  
CES1  
CES0  
UDCCH  
0
0
0
0
0
0
0
0
Initial value  
Attribute  
R/W *  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
7
Reserved  
0
6
5
UCRE  
0
4
3
2
1
CGE1  
0
0
CGE0  
0
bit  
CTUT  
RLDE UDCLR CGSC  
UDCCL  
Initial value  
Attribute  
0
0
1
0
R/W0  
R/W  
R/W  
R/W  
R1,W  
R/W  
R/W  
R/W  
(For attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• bit15: Enable 16 bit mode (Up/Down Counter 0 only)  
M16E  
Enable 16 bit mode  
8 bit × 2 channel operation mode (8 bit mode)  
16 bit × 1 channel operation mode (16 bit mode)  
0
1
* Reserved bit (Up/Down Counter 1 and 3). Be sure to write 0. The read value is the value written.  
• bit14: Count direction change flag (Interrupt request flag)  
Direction change detection  
CDCF  
When read:  
When written:  
0
1
A direction change has not made.  
Clear the flag.  
Writing does not affect the operation.  
Direction change has been made once or more.  
• When the count direction has been changed during count operation, the count direction change flag  
(CDCF) is set to “1”.  
• Since the count direction is set to countdown immediately after a reset, the count direction change flag  
(CDCF) is set to “1” on counting up following the reset.  
• To enable interrupt requests, the interrupt request permission bit must be set (CFIE=“1”).  
• bit13: Enable count direction change interrupt request  
CFIE  
Direction change interrupt request  
Disable direction change interrupt requests.  
Enable direction change interrupt requests.  
0
1
When the interrupt request permission bit is set to “1”, the interrupt request flag (CDCF) is enabled.  
• bit12: Select internal prescaler  
CLKS  
Internal clock frequency  
F
F
/2  
/8  
0
1
CLKP  
CLKP  
840  
 
Chapter 41 Up/Down Counter  
4.Register  
F
: Frequency of Peripheral clock (CLKP)  
CLKP  
This setting is enabled only in the timer mode, in which only countdown is performed.  
• bit11,10: Select count mode  
CMS1  
CMS0  
Count mode  
0
0
1
1
0
1
0
1
Timer mode (Countdown)  
Up/down count mode  
Phase difference count mode (Multiply by 2)  
Phase difference count mode (Multiply by 4)  
• bit9,8: Select count clock edge  
CES1  
CES0  
Edge selection  
0
0
1
1
0
1
0
1
Disable edge detection.  
Detect a falling edge.  
Detect a rising edge.  
Detect both rising and falling edges.  
This bit is used in the up/down count mode (CMS1,CMS0= “01”) to select the edge, to be detected, of an  
AIN and BIN pin signal. This setting is disabled in modes other than the up/down count.  
• bit7: Reserved.  
Be sure to write “0”. The read value is the value written.  
• bit6: Counter write  
CTUT  
Data transfer  
0
1
No impact on operation  
Transfer data from the RCR register to UDCR.  
During count operation (CSR.CSTR=“1”), the counter write bit must not be set to “1”.  
• bit5: Enable compare-match clear  
UCRE  
Compare-match counter clear  
Disable counter clear due to compare-match.  
Enable counter clear due to compare-match.  
0
1
This setting does not affect clear operations other than compare-match, such as ZIN pin clear.  
• bit4: Enable reload  
RLDE  
Reload function  
0
1
Disable reload function.  
Enable reload function.  
If the reload enable bit is set to “1”, the reload/compare value (RCR) is transferred to Up/Down Counter  
(UDCR) when Up/Down Counter is underflowed.  
• bit3: Clear UDCR  
UDCLR  
Counter clear  
Set (Clear) Up/Down Counter (UDCR) to “0000H”.  
No impact on operation  
0
1
• bit2: Select counter clear/gate  
CGSC  
ZIN pin function  
0
1
Counter clear function  
Gate function  
841  
Chapter 41 Up/Down Counter  
4.Register  
• bit1,0: Select counter clear/gate edge  
Edge detection/level selection  
CGE1  
CGE0  
When the counter clear function is selected  
(CGSC=“0”)  
Disable edge detection.  
When the gate function is selected  
(CGSC=“1”)  
0
0
1
1
0
1
0
1
Disable level detection. (Disable count.)  
Detect a “L” level.  
Detect a falling edge.  
Detect a rising edge.  
Disable setting.  
Detect a “H” level.  
Disable setting.  
842  
Chapter 41 Up/Down Counter  
4.Register  
4.2 UDCS: Count Status Register  
This register is used to control Up/Down Counter and to indicate the status of the counter.  
• UDCS0 (Up/Down Counter 0): Address 0307 (Access: Byte, Half-Word)  
H
• UDCS1 (Up/Down Counter 1): Address 030B (Access: Byte, Half-Word)  
H
• UDCS2 (Up/Down Counter 2): Address 0317 (Access: Byte, Half-Word)  
H
• UDCS3 (Up/Down Counter 3): Address 031B (Access: Byte, Half-Word)  
H
7
CSTR  
0
6
CITE  
0
5
UDIE  
0
4
3
2
1
0
bit  
CMPF  
0
OVFF  
0
UDFF  
0
UDF1  
0
UDF0  
0
Initial value  
Attribute  
R/W  
R/W  
R/W  
R/W0  
R/W0  
R/W0  
R/WX  
R/WX  
(For attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• bit7: Enable count operation  
CSTR  
Count operation  
0
1
Disable count operation.  
Enable count operation. (Activate counter.)  
• bit6: Enable compare interrupt requests  
CITE  
Compare interrupt request  
0
1
Disable compare interrupt requests.  
Enable compare interrupt requests.  
Setting the interrupt request permission bit to “1” enables the interrupt request flag (CMPF).  
• bit5: Enable overflow/underflow interrupt requests  
UDIE  
Overflow/underflow interrupt request  
Disable overflow/underflow interrupt requests.  
Enable overflow/underflow interrupt requests.  
0
1
Setting the interrupt request permission bit to “1” enables the interrupt request flag (OVFF or UDFF).  
• bit4: Compare detection flag  
Compare detection  
CMPF  
When read:  
Comparison results do not agree.  
Comparison results agree.  
When written:  
0
1
Clear the flag.  
Disable setting.  
To enable interrupt requests, the interrupt request permission bit must be set (CITE= “1”).  
• bit3: Overflow detection flag  
Overflow detection  
OVFF  
When read:  
When written:  
0
1
No overflow  
An overflow has occurred.  
Clear the flag.  
Disable setting.  
To enable interrupt requests, the interrupt request permission bit must be set (UDIE= “1”).  
• bit2: Underflow detection flag  
Underflow detection  
UDFF  
When read:  
When written:  
0
1
No Underflow  
An underflow has occurred.  
Clear the flag.  
Disable setting.  
843  
Chapter 41 Up/Down Counter  
4.Register  
To enable interrupt requests, the interrupt request permission bit must be set (UDIE= “1”).  
• bit1,0: Up/down flag  
UDF1  
UDF0  
Previous count operation  
0
0
1
1
0
1
0
1
No input  
Count down  
Count up  
Both of count up and count down  
844  
Chapter 41 Up/Down Counter  
4.Register  
4.3 UDCR: Up/Down Counter Register  
This register is used to read the count value of Up/Down Counter.  
• UDCR10 (Up/Down Counter 0/1): Address 0302 (Access: Byte, Half-Word)  
H
• UDCR32 (Up/Down Counter 2/3): Address 0312 (Access: Byte, Half-Word)  
H
Depending on the setting of the 16-bit mode enable bit (CCR.M16E), this register behaves differently.  
■ 16 Bit Mode (M16E= “1”)  
In the 16 bit mode, this register functions as 16-bit up/down counter register.  
• UDCR10 (Up/Down Counter): Address 0302 (Access: Half-word)  
H
• UDCR32 (Up/Down Counter): Address 0312 (Access: Half-word)  
H
15  
D15  
0
14  
D14  
0
13  
D13  
0
12  
D12  
0
11  
D11  
0
10  
D10  
0
9
D09  
0
8
D08  
0
bit  
Initial value  
Attribute  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
7
D07  
0
6
D06  
0
5
D05  
0
4
D04  
0
3
D03  
0
2
D02  
0
1
D01  
0
0
D00  
0
bit  
Initial value  
Attribute  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
(For attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
For the 16 bit mode, be sure to read by half-word access.  
■ 8 Bit Mode (M16E=“0”)  
In the 8 bit mode, this register functions as a 8-bit up/down counter register 0 and a 8-bit up/down counter  
register 1.  
• UDCR1 (Up/Down Counter 1): Address 00302 (Access: Byte, Half-word)  
H
• UDCR0 (Up/Down Counter 0): Address 00303 (Access: Byte, Half-word)  
H
• UDCR3 (Up/Down Counter 3): Address 00312 (Access: Byte, Half-word)  
H
• UDCR2 (Up/Down Counter 2): Address 00313 (Access: Byte, Half-word)  
H
7
6
5
4
3
2
1
0
bit  
D07  
D06  
D05  
D04  
D03  
D02  
D01  
D00  
Initial  
value  
0
0
0
0
0
0
0
0
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
R/WX  
Attribute  
(For attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
845  
Chapter 41 Up/Down Counter  
4.Register  
4.4 UDRC: Up/Down Reload/Compare Register  
This register is used to reload a value to Up/Down Counter and for comparison.  
This register is also used to write to Up/Down Counter.  
• UDRC10 (Up/Down Counter 0/1): Address 0300 (Access: Byte, Half-Word)  
H
• UDRC32 (Up/Down Counter 2/3): Address 0310 (Access: Byte, Half-Word)  
H
Depending on the setting of the 16 bit mode enable bit (CCR.M16E), this register behaves differently.  
■ 16 Bit Mode (M16E=“1”)  
In the 16 bit mode, this register functions as 16-bit reload/compare register.  
• UDCR10 (Reload compare): Address 00300 (Access: Byte, Half-word)  
H
• UDCR32 (Reload compare): Address 00310 (Access: Byte, Half-word)  
H
15  
D15  
0
14  
D14  
0
13  
D13  
0
12  
D12  
0
11  
D11  
0
10  
D10  
0
9
D09  
0
8
D08  
0
bit  
Initial value  
Attribute  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
7
D07  
0
6
D06  
0
5
D05  
0
4
D04  
0
3
D03  
0
2
D02  
0
1
D01  
0
0
D00  
0
bit  
Initial value  
Attribute  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
(For attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• The reload and compare values are same.  
When Up/Down Counter counts up, the value in RCR is used as a compare value.  
When Up/Down Counter counts down, underflow is generated and the value in RCR is used as a reload  
value for reloading.  
(Up/Down Counter counts between 0000H and the reload/compare value.)  
• In the 16 bit mode, be sure to write by half-word access.  
■ 8 Bit Mode (M16E=“0”)  
In the 8 bit mode, this register functions as 8-bit reload/compare register 0 and 8-bit reload/compare register 1.  
• UDCR1 (reload compare 1): Address 00300 (Access: Byte, Half-word)  
H
• UDCR0 (reload compare 0): Address 00301 (Access: Byte, Half-word)  
H
• UDCR3 (reload compare 3): Address 00310 (Access: Byte, Half-word)  
H
• UDCR2 (reload compare 2): Address 00311 (Access: Byte, Half-word)  
H
7
D07  
0
6
D06  
0
5
D05  
0
4
D04  
0
3
D03  
0
2
D02  
0
1
D01  
0
0
D00  
0
bit  
Initial value  
Attribute  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
RX, W  
(For attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• The reload and compare values are same.  
When Up/Down Counter counts up, the value in RCR is used as a compare value.  
When Up/Down Counter counts down, underflow is generated and the value in RCR is used as a reload  
value for reloading.  
(Up/Down Counter counts between 0000H and the reload/compare value.)  
• Perform the following procedure to write to Up/Down Counter.  
846  
Chapter 41 Up/Down Counter  
4.Register  
(1) Stop counting.  
(2) Write a value to the reload/compare register.  
(3) Write “1”to the counter write bit (CCR.CTUT).  
847  
Chapter 41 Up/Down Counter  
5.Operation  
5. Operation  
This section describes each operation mode for Up/Down Counter.  
5.1 Timer Mode CMS[1:0]=“00”  
Reload value  
Reload value  
Interrupt  
FCLKP divided by 2  
Countdown  
FCLKP divided by 8  
request  
(5)  
Reload value  
(8)  
(3)  
(9)  
CLKS, RLDE  
CGSC  
(1)  
(2)  
(3)  
CSTR  
Cleared by  
software  
Cleared by  
software  
Cleared by  
software  
(10)  
(6)  
Underflow  
(Interrupt request)  
(9)  
(4)  
Interrupt request enabled  
(7)  
(1)  
(2)  
(3)  
(4)  
(5)  
(6)  
(7)  
(8)  
(9)  
An appropriate bit (Reload enable RLDE) is set.  
Up/Down Counter is cleared (“0” is written to CGSC).  
The software activates Up/Down Counter.  
An underflow occurs.  
The reload value is reloaded to Up/Down Counter.  
The software clears the underflow flag.  
The software enables interrupts.  
Up/Down Counter counts down.  
An underflow occurs. (An interrupt request has been made.)  
(10) The software clears the underflow flag.  
(11) Repeat (8) to (10).  
848  
 
Chapter 41 Up/Down Counter  
5.Operation  
5.2 Up/Down Count Mode CMS[1:0]=“01”  
Reload value  
Reload value  
FCLKP divided by 2  
Interrupt  
request  
enabled  
Countdown  
FCLKP divided by 8  
(5)  
Reload value  
(8)  
(3)  
(9)  
CLKS, RLDE  
CGSC  
(1)  
(2)  
(3)  
CSTR  
Cleared by  
software  
Cleared by  
software  
Cleared by  
software  
(10)  
(6)  
(9)  
Underflow  
(Interrupt request)  
(4)  
Interrupt request enabled  
(7)  
Up/Down Counter clear control using the ZIN pin  
(1)  
(2)  
(3)  
(4)  
(5)  
(6)  
Appropriate bits (Counting enable CSTR, Reload enable RLDE, Clear enable UCRE) are set.  
When pulse input to the AIN pin is detected, Up/Down Counter counts up.  
The count direction change flag is set to “1”.  
When an edge is applied to the ZIN pin, Up/Down Counter is cleared.  
Continuous pulse input to the AIN pin causes Up/Down Counter to count up.  
The Up/Down Counter's count value agrees with the compare value (compare-match) and the  
compare-match flag is set to “1”.  
(7)  
(8)  
(9)  
Compare-match clears Up/Down Counter.  
Continuous pulse input to the AIN pin causes Up/Down Counter to count up.  
When pulse input to the AIN pin stops, Up/Down Counter stops counting.  
(10) When pulse input to the BIN pin is detected, Up/Down Counter counts down.  
(11) The count direction change flag is set to “1”.  
(12) Continuous pulse input to the BIN pin causes Up/Down Counter to count down.  
(13) Up/Down Counter is underflowed and the underflow flag is set to “1”.  
(14) The underflow causes the reload value to be reloaded to Up/Down Counter.  
(15) Next time when Up/Down Counter counts down, the compare-match flag is set to “1”.  
849  
Chapter 41 Up/Down Counter  
5.Operation  
5.3 Up/Down Count Mode CMS[1:0]=“01”  
ZIN=Gate control  
(12)  
(6)  
(7)  
(2)  
(11)  
(8)  
(1)  
CSTR, RLDE, UCRE  
UDCC  
(2)  
(3)  
(6)  
(12)  
(9)  
AIN  
BIN  
(7)  
CGE[1:0]=“10”  
ZIN (Gate)  
(4)  
(8)  
(10)  
“H”  
“H”  
(13)  
Countgate at the ZIN pin  
(1)  
(2)  
(3)  
Appropriate bits (Counting enable CSTR, Reload enable RLDE and Clear enable UCRE) are set.  
Up/Down Counter is cleared. (“0” is written to CGSC).  
Neither pulse input to the AIN pin nor counting at the ZIN pin being enabled, Up/Down Counter neither  
counts up nor down.  
(4)  
(5)  
(6)  
(7)  
(8)  
(9)  
Counting is enabled at the ZIN pin.  
Up/Down Counter counts up.  
When pulse input to the AIN pin stops, Up/Down Counter stops counting.  
When a pulse input to the BIN pin is detected, Up/Down Counter counts down.  
When counting is disabled at the ZIN pin, Up/Down Counter stops counting.  
Neither pulse input to the AIN pin nor counting at the ZIN pin being enabled, Up/Down Counter neither  
counts up nor down.  
(10) Counting is enabled at the ZIN pin.  
(11) Up/Down Counter counts up.  
(12) When pulse input to the AIN pin stops, Up/Down Counter stops counting.  
(13) Counting is disabled at the ZIN pin.  
850  
Chapter 41 Up/Down Counter  
5.Operation  
5.4 Phase Difference Count Mode (Multiply by 2) CMS[1:0]=“10”  
Frequency multiplied by 2 in phase difference count mode:  
On the rising and falling edges at the BIN count pin, Up/Down Counter counts up or down, depending on the  
voltage level at the AIN pin.  
Count value  
Time  
AIN  
BIN  
• Count up Conditions:  
• When the voltage level at the AIN pin detected on the rising edge at the BIN pin is “H”  
• When the voltage level at the AIN pin detected on the falling edge at the BIN pin is “L”  
• Count down Conditions:  
• When the voltage level at the AIN pin detected on the rising edge at the BIN pin is “L”  
• When the voltage level at the AIN pin detected on the falling edge at the BIN pin is “H”  
When this count mode is selected, selection of the edge to be detected using CES1 or CES0 is disabled.  
851  
Chapter 41 Up/Down Counter  
5.Operation  
5.5 Phase Difference Count Mode (Multiply by 4) CMS[1:0]=“11”  
Frequency multiplied by 4 in phase difference count mode:  
On the rising and falling edges at the BIN pin, Up/Down Counter counts up or down, depending on the voltage  
level at the AIN pin, and on the rising and falling edges at the AIN pin, Up/Down Counter counts up or down,  
depending on the voltage level at the BIN pin.  
Count value  
Time  
AIN  
BIN  
• Count up Conditions:  
• When the voltage level at the AIN pin detected on the rising edge at the BIN pin is “H”  
• When the voltage level at the AIN pin detected on the falling edge at the BIN pin is “L”  
• When the voltage level at the BIN pin detected on the rising edge at the AIN pin is “L”  
• When the voltage level at the BIN pin detected on the falling edge at the AIN pin is “H”  
• Count down Conditions:  
• When the voltage level at the AIN pin detected on the rising edge at the BIN pin is “L”  
• When the voltage level at the AIN pin detected on the falling edge at the BIN pin is “H”  
• When the voltage level at the BIN pin detected on the rising edge at the AIN pin is “H”  
• When the voltage level at the BIN pin detected on the falling edge at the AIN pin is “L”  
When Up/Down Counter is used to count encoder output, high precise counting of rotation angles and number  
of revolutions, as well as detecting of rotation directions, can be achieved by applying encoder output signals  
of phase A, phase B and phase Z to the AIN, BIN and ZIN pins, respectively.  
Note that when this count mode is selected, selection of the edge to be detected using CES1 or CES0 is  
disabled.  
852  
Chapter 41 Up/Down Counter  
5.Operation  
5.6 Clear Timing  
(1) When a clear request (Compare-match, ZIN edge detection and writing “0” to the clear bit UDCLR) is  
made, clear is performed next time when Up/Down Counter counts up.  
Compare value  
0066  
H
0065  
H
Count value  
0066  
H
0000  
H
0001  
H
Clear request  
Countup  
Clear timing  
(2) Even if a clear request (Compare-match, ZIN edge detection and writing “0” to the clear bit DCC) is made,  
clear is not performed when UP/Down Counter counts neither up nor down.  
0066  
H
Compare value  
0065  
H
Count value  
Clear request  
Countup  
0066  
H
0065  
H
Countdown  
Clear timing (None)  
(3) If Up/Down Counter does not count up after a clear request (Compare-match, ZIN edge detection and  
writing “0” to the clear bit DCC) is made, the counter is cleared when counting is disabled (CSTR=“0”).  
Compare value  
0066  
H
0065  
H
Count value  
0066  
H
0000  
H
Clear request  
Countup  
CSTR or ZIN gate function  
(4) When Up/Down Counter exceeds the maximum count, the overflow flag is set to “1” and the counter value  
is returned to “0000”.  
Count value  
Countup  
FFFEH  
FFFFH  
0000  
H
Overflow  
853  
Chapter 41 Up/Down Counter  
5.Operation  
5.7 Reload Timing  
The next time when Up/Down Counter counts down below “0000”, an underflow occurs (an interrupt request is  
made) and then reloading is performed.  
Compare value  
0066  
H
0001  
H
0000  
H
0066  
H
0065  
H
0064  
H
Count value  
Countdown  
Underflow  
Reload timing  
Note: If clear and reload operations occur at the same time, clear takes precedence.  
5.8 Writing a Value to Counter  
(2)  
RCR  
XXH  
67H  
Up/Down Counter  
CSTR  
67H  
(4)  
(3)  
(1)  
CTUT  
(1) Counting of Up/Down Counter is disabled.  
(2) A value is written to PCR.  
(3) “1” is written to the count write bit CTUT.  
(4) A value is transferred from the reload/compare register RCR to Up/Down Counter.  
854  
Chapter 41 Up/Down Counter  
6.Setting  
6. Setting  
Table 6-1 Required Settings to Run Up/Down Counter in Timer Mode  
Setting  
procedure*  
Setting  
Setting registers  
Set the reload value.  
(Optional)  
Reload/compare register (UDRC)  
Reload/compare register (UDRC)  
See 7.16.  
See 7.5.  
Set a value to Up/Down Counter  
or  
Count control register (UDCC)  
See 7.8.  
Clear the count value of Up/Down Counter.  
Set a bit length.  
See 7.1.  
See 7.2.  
See 7.3.  
See 7.7.  
Set the count mode to timer mode.  
Select a count source.  
Count control register (UDCC)  
Count status register (UDCS)  
Enable reloading at the time of underflow.  
Enable count control (clear/gate) using the ZIN pin.  
Activate Up/Down Counter.  
See  
7.9 and 7.10  
See 7.11.  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-2 Required Settings to Run Up/Down Counter in Up/Down Count Mode  
Setting  
procedure*  
Setting  
Setting registers  
Set the reload value/compare value.  
Reload/compare register (UDRC)  
Reload/compare register (UDRC)  
See 7.16.  
See 7.5.  
(Optional)  
Set a value to Up/Down Counter  
Or  
Count control register (UDCC)  
See 7.8.  
Clear the count value of Up/Down Counter.  
Set a bit length.  
See 7.1.  
See 7.2.  
See 7.4.  
Set the count mode to up/down count mode.  
Select the edge, to be detected, of a signal (AIN or BIN),  
for which counting is performed.  
Count control register (UDCC)  
Count status register (UDCS)  
Enable clearing of Up/Down Counter at the time of the  
counting following a compare-match.  
See 7.6.  
See 7.7.  
Enable reloading at the time of underflow.  
See  
7.9 and 7.10  
Enable count control (clear/gate) using the ZIN pin.  
Activate Up/Down Counter.  
See 7.11.  
*: For the setting procedure, refer to the section indicated by the number.  
855  
 
Chapter 41 Up/Down Counter  
6.Setting  
Table 6-3 Required Settings to Run Up/Down Counter in Phase Difference Count Mode (Multiply by 2 or 4)  
Setting  
procedure*  
Setting  
Setting registers  
Set the reload value/compare value.  
Reload/compare register (UDRC).  
Reload/compare register (UDRC)  
See 7.16  
(Optional)  
Set a value to Up/Down Counter  
or  
See 7.5  
See 7.8  
Count control register (UDCC)  
Clear the count value of Up/Down Counter.  
Set a bit length.  
See 7.1  
See 7.2  
Set the count mode to phase difference count mode  
(Multiply by 2 or 4).  
Enable clearing of Up/Down Counter at the time of the  
counting following a compare-match.  
Count control register (UDCC)  
Count status register (UDCS)  
See 7.6  
See 7.7  
Enable reloading at the time of underflow.  
See  
7.9 and 7.10  
Enable count control (clear/gate) using the ZIN pin.  
Activate Up/Down Counter.  
See 7.11  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-4 Required Settings for Up/Down Counter Interrupt  
Setting  
procedure*  
Setting  
Setting registers  
Set Up/Down Counter interrupt vectors and Up/Down  
Counter interrupt levels.  
Refer to “Chapter 24 Interrupt Control  
(Page No.311)”.  
See 7.17  
See 7.19  
Set Up/Down Counter interrupts.  
Clear interrupt requests.  
Count control register (UDCC)  
Count status register (UDCS)  
Enable interrupt requests.  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-5 Required Settings to Deactivate Up/Down Counter  
Setting  
procedure*  
Setting  
Deactivate Up/Down Counter  
Setting registers  
Count control register (UDCC)  
Count status register (UDCS)  
See 7.10  
See 7.11  
(Controlled through the ZIN pin)  
Deactivate Up/Down Counter.  
*: For the setting procedure, refer to the section indicated by the number.  
856  
Chapter 41 Up/Down Counter  
7.Q&A  
7. Q&A  
7.1 How do I select a bit length (8 or 16) of Up/Down Counter?  
Use the 16 bit mode enable bit (UDCC.M16E).  
Up/Down Counter's bit length  
To set the bit length to 8  
To set the bit length to 16 bit  
16 bit mode enable bit (M16E)  
Set the bit to “0”.  
Set the bit to “1”.  
7.2 What types of count modes are available and how are they set?  
There are four types of count modes:  
Timer, Up/down count, Phase difference count (Multiply by 2 or 4)  
Use the count mode selection bits (UDCC.CMS[1:0]) to set a count mode.  
Count mode  
Count mode selection bit (CMS[1:0])  
To set the count mode to timer  
To set the count mode to up/down count  
Set the bit to “00”.  
Set the bit to “01”.  
To set the count mode to phase difference count  
(Multiply by 2)  
Set the bit to “10”.  
Set the bit to “11”.  
To set the count mode to phase difference count mode  
(Multiply by 4)  
7.3 How do I select a count source for Up/Down Counter running in the timer mode?  
Use the internal prescaler select bit (UDCC.CLKS).  
Count source for timer mode  
Internal prescaler select bit (CLKS)  
Set the bit to “0”.  
To obtain the F  
To obtain the F  
divided by 2  
divided by 8  
CLKP  
CLKP  
Set the bit to “1”.  
7.4 How do I select the edge with which Up/Down Counter running in the Up/down count  
mode detects an input signal (AIN or BIN)?  
Use count clock edge select bits (UDCC.CES[1:0]).  
Edge to be detected by counter  
To disable detection  
Count clock edge select bit (CES[1:0])  
Set the bit to “00”.  
To enable detection of a falling edge  
To enable detection of a rising edge  
To enable detection of both edges  
Set the bit to “01”.  
Set the bit to “10”.  
Set the bit to “11”.  
7.5 How do I set a value to Up/Down Counter?  
A value can be set to Up/Down Counter by writing the value to the reload/compare register (RCR) and then  
writing “1” to the counter write bit (UDCC.CTUT).  
7.6 When the Up/Down Counter's count-up value agrees with the compare value  
(RCR[0:1]), how do I enable clearing of Up/Down Counter the next time when the  
counter counts up?  
Use the up/down counter clear enable bit (UDCC.UCRE).  
When the count-up value agrees with the compare  
Up/down counter clear enable bit (UCRE)  
value and then Up/Down Counter counts up:  
To disable clearing of Up/Down Counter  
To enable clearing of Up/Down Counter  
Set the bit to “0”.  
Set the bit to “1”.  
857  
 
Chapter 41 Up/Down Counter  
7.Q&A  
7.7 How do I enable reloading of the reload value (RCR[1:0]) to Up/Down Counter when  
Up/Down Counter is underflowed?  
Use the reload enable bit (UDCC.RLDE).  
When the count-up value agrees with the compare  
Reload enable bit (RLDE)  
value:  
To disable reloading of the reload value (RCR) to Up/  
Set the bit to “0”.  
Down Counter  
To enable reloading of the reload value (RCR) to Up/Down  
Set the bit to “1”.  
Counter  
7.8 How do I clear Up/Down Counter?  
Up/Down Counter can be cleared in any of the following ways:  
• Writing “0” to the up/down counter clear bit (UDCC.UDCLR).  
• Applying an edge to the ZIN pin (For details, refer to 7.9.)  
• When the compare value agrees with the Up/Down Counter's count-up value.  
• When Up/Down Counter tries to count up after reaching the maximum count.  
• Reset input (INIT pin input, watchdog reset, software reset)  
7.9 How do I clear Up/Down Counter using the ZIN pin?  
Use counter clear gate bit (UDCC.CGSC) and counter clear gate edge select bits (UDCC.CGE[1:0]). (These  
bits are enabled in the up/down count mode.)  
Counter clear gate  
edge select bit  
(CGE[1:0])  
Counter clear gate bit  
ZIN pin input  
(CGSC)  
To disable edge detection (clear)  
Set the bit to “0”.  
Set the bit to “0”.  
Set the bit to “0”.  
Set the bit to “00”.  
Set the bit to “01”.  
Set the bit to “10”.  
To clear Up/Down Counter on the falling edge  
To clear Up/Down Counter on the rising edge  
GCE[1:0]=“11” indicates that setting is disabled.  
7.10 How do I control Up/Down Counter's count operation using the ZIN pin?  
Use counter clear gate bit (UDCC.CGSC) and counter clear gate edge select bits (UDCC.CGE[1:0]). (These  
settings are enabled for all the count modes.)  
Counter clear gate  
edge select bit  
(CGE[1:0])  
Counter clear gate bit  
ZIN pin input  
(CGSC)  
To disable level detection (counting)  
Set the bit to “1”.  
Set the bit to “1”.  
Set the bit to “00”.  
To start counting up or down at the “L” level  
To stop counting up or down at the “H” level  
Set the bit to “01”.  
To stop counting up or down at the “L” level  
To start counting up or down at the “H” level  
Set the bit to “1”.  
Set the bit to “10”.  
GCE[1:0]= “11” indicates that setting is disabled.  
858  
Chapter 41 Up/Down Counter  
7.Q&A  
7.11 How do I enable/disable Up/Down Counter's count operation?  
Use the count activate bit (UDCS.CSTR).  
When the count-up value agrees with the compare value:  
Count activate bits (UDCS.CSTR)  
Set the bit to “0”.  
To disable Up/Down Counter's count operation  
To enable Up/Down Counter's count operation  
(To activate count operation)  
Set the bit to “1”.  
• How do I start counting?  
Timer mode  
Counting starts using the internal clock (See 7.3.)  
Up/down count mode  
Counting starts when the edge of an AIN or BIN pin input signal is detected.  
(See 7.4.)  
Phase difference count mode Counting starts when a phase difference between AIN and BIN pins is  
detected.  
Note that the count operation enable level must be detected, before the ZIN pin's gate function can be  
selected.  
7.12 How do I know the previous count direction (the current rotation direction)?  
Use the up/down flags (UDCS.UDF[1:0]).  
Up/down flag (UDF[1:0])  
“00” indicates that no counting is performed after resetting.  
“01” indicates that counting down is performed.  
“10” indicates that counting up is performed.  
“11” indicates that both counting up and down are performed, resulting in no change in the count value.  
This flag has nothing to do with interrupts. So, use the count direction change flag (UDCC.CDCF) for interrupt  
processing.  
7.13 How do I know count direction changes?  
Use the count direction change flag (UDCC.CDCF).  
Count direction change flag (CDCF)  
“0” indicates that no direction change has been made after clearing the flag.  
“1” indicates that a direction change has been made once or more after clearing the flag.  
7.14 How do I know that a compare-match has occurred?  
Use the compare detection flag (UDCS.CMPF).  
Compare detection flag (CMPF)  
“0” indicates that the Up/Down Counter's count value does not agree with the compare value.  
“1” indicates that the Up/Down Counter's count value agrees with the compare value.  
Regardless of counter operations (counting up/down, or a value being set or reloaded), the compare detection  
flags are set to “1” when the count value agrees with the compare value.  
859  
Chapter 41 Up/Down Counter  
7.Q&A  
7.15 How do I know that an overflow or underflow has occurred?  
Use the overflow detection flag (UDCS.OVFF) and the underflow detection flag (UDCS.UDFF).  
OVFF =“1” indicates that Up/Down Counter has been overflowed.  
UDFF =“1” indicates that Up/Down Counter has been underflowed.  
7.16 How do I set the reload/compare value?  
Set a value to the reload/compare registers (UDRC). (This value is used as a compare or reload value.)  
7.17 What are interrupt-related registers?  
Configure the up/down counter interrupt vectors and up/down counter interrupt level settings.  
The following table shows the relationship among the up/down counter number, interrupt levels and vectors:  
For details on interrupt levels and interrupt vectors, refer to “Chapter 24 Interrupt Control (Page No.311)”.  
Interrupt vector  
Interrupt level set bit (ICR[4:0])  
(Default)  
Up/Down Counter 0/1 (16 bit)  
Up/Down Counter 0 (8 bit)  
#128  
Address: 0FFDFCh  
Interrupt level register (ICR56) Address:  
0478h  
#129  
Address: 0FFDF8h  
Up/Down Counter 1 (8 bit)  
Up/Down Counter 2/3 (16 bit)  
Up/Down Counter 2 (8 bit)  
#130  
Address: 0FFDF4h  
Interrupt level register (ICR57) Address:  
0479h  
#131  
Address: 0FFDF0h  
Up/Down Counter 3 (8 bit)  
The following interrupt request flags are not automatically cleared:  
•
•
•
•
Count direction change: UDCC.CDCF  
Compare detection: UDCS.CMPF  
Overflow: UDCS.OVFF  
Underflow: UDCS.UDFF  
So, the software must write “0” to the interrupt request flag before control is returned from interrupt processing.  
7.18 What interrupts are available and how are they selected?  
There are three interrupt causes:  
• Count direction change  
• compare-match  
• overflow/underflow  
An interrupt request is made by ORing these three interrupt causes; each interrupt cause cannot be isolated.  
Use the interrupt request permission bit to enable a desired interrupt.  
860  
Chapter 41 Up/Down Counter  
7.Q&A  
7.19 How do I enable (select), disable or clear interrupts?  
Interrupt request enable and interrupt request flags  
To enable (select) interrupts, use the following interrupt request permission bits:  
• Count direction change interrupt request permission bits: UDCC.CFIE  
• Compare interrupt request permission bits  
: UDCS.CITE  
• Overflow/underflow interrupt request permission bits : UDCS.UDIE  
Interrupt request permission bits (CFIE, CITE and UDIE)  
To disable interrupt requests  
To enable interrupt requests  
Set the bit to “0”.  
Set the bit to “1”.  
To clear interrupt requests, use the following interrupt request bits:  
•
•
•
•
For count direction changes  
For compare detection  
For overflow  
: UDCC.CDCF  
: UDCS.CMPF  
: UDCS.OVFF  
: UDCS.UDFF  
For underflow  
Interrupt request bits (CDCF, CMPF, OVFF and UDFF)  
Write “0”.  
To clear interrupt requests  
861  
Chapter 41 Up/Down Counter  
8.Caution  
8. Caution  
• The count direction is set to “countdown” immediately after resetting the counter. So, when the counter  
counts up immediately after resetting, the count direction change bit (UDCC.CDCF) is set to “1” to indicate a  
direction change has been made.  
• When the up/down counter register UDCR has reached the maximum count, the overflow flag is set to 1 and  
counting continues. This time UDCR is cleared.  
• The minimum pulse width for AIN, BIN and ZIN signals is 2xT (T=1/CLKP: Period of a peripheral clock)  
• If you determine whether a change has been made to the count direction change interrupt and count  
direction flags, you must take it into consideration that when several direction changes have been made  
continuously in a short period of time, the count direction flag may be returned to the original value, which  
looks as if no change has been made.  
• The compare detection flag (UDCS.CMPF) is set to “1” when Up/Down Counter's count value agrees with  
the compare value during both counting up and down. These flags are also set to 1 when:  
• The reload value is reloaded to Up/Down Counter; or  
• The Up/Down Counter's count value agrees with the compare value when Up/Down Counter is activated.  
• The Up/Down Counter's count value is cleared by a clear request which is generated:  
• On the edge of a signal input from the ZIN pin;  
• By writing “0” to the up/down counter clear bit (UDCC.UDCLR); or  
• When the compare value agrees with the count value.  
In addition,  
• On reset input (INITX, RST and watchdog reset); or  
• When the counter counts up from the maximum account,  
the count value is also set to “0000 ”.  
H
• When Up/Down Counter clear and reload requests are made at the same time, the former takes precedence  
over the latter.  
• When Up/Down Counter is counting up, writing to the counter is disabled.  
{Writing “1” to the counter write bit (UDCC.CTUT) after writing to the UDRC register is disabled.}  
Should the software perform a reload operation during counting, the reload takes precedence and the event  
that should have taken place no longer occurs.  
• The software cannot clear the up/down flags (UDCS.UDF[1:0]) to “0”. Only reset (initialization) can clear the  
flag to “0”.  
862  
 
Chapter 42 Sound Generator  
1.Overview  
Chapter 42 Sound Generator  
1. Overview  
This Chapter provides an overview of the Sound Generator, describes the register structure and  
functions, and describe the operation of the Sound Generator.  
The Sound Generator consists of the Sound Control register, Frequency Data register, Ampli-  
tude Data register, Decrement Grade register, Tone Count register, Sound Disable register,  
PWM pulse generator, Frequency counter, Decrement counter and Tone Pulse counter.  
863  
   
Chapter 42 Sound Generator  
2.Block Diagram  
2. Block Diagram  
CLKP  
8bit PWM pulse  
Prescaler  
Frequency  
Counter  
Toggle  
flip-flop  
Generator  
CO  
EN  
CI  
CO  
EN  
D
Q
S2 S1 S0  
PWM  
EN  
reload  
reload  
1/d  
Amplitude Data  
register  
Frequency  
register  
DEC  
DEC  
Decrement  
Counter  
CI  
CO  
EN  
SGA  
Decrement  
Grade register  
Mix  
SGO  
Tone Pulse  
Counter  
TONE  
CI  
CO  
EN  
Tone Count  
register  
INTE INT ST  
IRQ  
864  
 
Chapter 42 Sound Generator  
3.Registers  
3. Registers  
Sound Control register  
15  
14  
S2  
13  
12  
S0  
11  
10  
9
8
Bit number  
SGCRH  
Address:  
000198H  
TST  
BUSY  
DEC  
S1  
Read/write  
Initial value  
(R/W) (R/W) (R/W) (R/W)  
(0) (0) (0) (0)  
(R)  
(0)  
(R/W)  
(0)  
7
6
5
4
3
2
1
0
Bit number  
SGCRL  
Address:  
000199H  
TONE  
INTE  
INT  
ST  
Read/write  
Initial value  
(R/W)  
(0)  
(R/W) (R/W) (R/W)  
(0) (0) (0)  
Frequency Data register  
Address: 00019AH  
Bit number  
SGFR  
15  
14  
13  
3
2
1
0
D15  
D14  
D13  
D3  
D2  
D1  
D0  
Read/write  
Initial value  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(X)  
(X)  
(X)  
(X)  
(X)  
(X)  
(X)  
(X)  
Amplitude Data register  
15  
14  
D6  
13  
12  
11  
D3  
10  
9
8
Bit number  
SGAR  
Address:  
00019CH  
D7  
D5  
D4  
D2  
D1  
D0  
Read/write  
Initial value  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
Tone Count register  
15  
14  
13  
12  
D4  
11  
10  
9
8
Bit number  
Address:  
00019EH  
SGTR  
D7  
D6  
D5  
D3  
D2  
D1  
D0  
Read/write  
Initial value  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(X) (X) (X) (X) (X) (X)  
(R/W) (R/W)  
(X) (X)  
Decrement Grade register  
Address: 00019FH  
Bit number  
SGDR  
7
6
5
4
3
2
1
0
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Read/write  
Initial value  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(X) (X) (X) (X) (X) (X) (X) (X)  
865  
 
Chapter 42 Sound Generator  
3.Registers  
3.1 Register Details  
■ Sound Control Register (SGCR)  
Sound Control register  
15  
14  
13  
S1  
12  
S0  
11  
10  
9
8
Bit number  
SGCRH  
Address:  
000198H  
TST  
BUSY  
DEC  
S2  
Read/write  
Initial value  
(R/W)  
(0)  
(R/W)  
(0)  
(R/W) (R/W)  
(0) (0)  
(R/W)  
(0)  
(R)  
(0)  
7
6
5
4
3
2
1
0
Bit number  
SGCRL  
Address:  
000199H  
TONE  
INTE  
INT  
ST  
Read/write  
Initial value  
(R/W)  
(0)  
(R/W) (R/W) (R/W)  
(0) (0) (0)  
[bit 15] TST : Test bit  
This bit is prepared for the device test. In any user application it should be set to "0".  
[bits14 to12] S2 to S0 : Operation clock select bits  
These bits specify the clock input signal for the Sound Generator.  
S2  
S1  
S0  
Clock input  
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
CLK  
1/2 CLK  
1/4 CLK  
1/8 CLK  
1/16 CLK  
[bit 9] BUSY : Busy bit  
This bit indicates whether the Sound Generator is in operation. This bit is set to "1" upon the  
ST bit is set to "1". It is reset to "0" when the ST bit is reset to "0" and the operation is  
completed at the end of one tone cycle. Any write instruction performed on this bit has no  
effect.  
[bit 8] DEC : Auto-decrement enable bit  
The DEC bit is prepared for an automatic decrement of the sound in conjunction with the  
Decrement Grade register.  
If this bit is set to "1", the stored value in the Amplitude Data register is decremented by  
1(one), every time when the Decrement counter counts the number of tone pulses from the  
toggle flip-flop specified by the Decrement Grade register.  
[bit 5] TONE : Tone output bit  
When this bit is set to "1", the SGO signal becomes a simple square-waveform (tone pulses)  
from the toggle flip-flop. Otherwise it is the mixed (AND logic) signal of the tone and PWM  
pulses.  
866  
Chapter 42 Sound Generator  
3.Registers  
[bit 2] INTE : Interrupt enable bit  
This bit enables the interrupt signal of the Sound Generator. When this bit is "1" and the INT  
bit is set to "1", the Sound Generator signals an interrupt.  
[bit 1] INT : Interrupt bit  
This bit is set to "1" when the Tone Pulse counter counts the number of the tone pulses  
specified by the Tone Count register and Decrement Grade register.  
This bit is reset to "0" by writing "0". Writing "1" has no effect and Read-Modify-Write  
instructions always result in reading "1".  
[bit 0] ST : Start bit  
This bit is for starting the operation of the Sound Generator. While this bit is "1", the Sound  
Generator perform its operation.  
When this bit is reset to "0", the Sound Generator stops its operation at the end of the current  
tone cycle. The BUSY bit indicates whether the Sound Generator is fully stopped.  
■ Frequency Data Register (SGFR)  
Frequency Data register  
Address: 00019AH  
Bit number  
SGFR  
15  
14  
13  
3
2
1
0
D15  
D14  
D13  
D3  
D2  
D1  
D0  
Read/write  
Initial value  
(R/W) (R/W) (R/W)  
(X) (X) (X)  
(R/W) (R/W) (R/W) (R/W)  
(X) (X) (X) (X)  
The Frequency Data register stores the reload value for the Frequency counter. The stored value  
represents the frequency of the sound (or the tone signal from the toggle flip-flop). The register  
value is reloaded into the counter at every transition of the toggle signal.  
The following figure shows the relationship between the tone signal and the register value.  
One Tone Cycle  
Tone signal  
(register value+1) x  
One PWM cycle  
(register value+1) x  
One PWM cycle  
It should be noted that modifications of the register value while operation may alter the duty cycle  
of 50% depending on the timing of the modification.  
■ Amplitude Data Register (SAGR)  
Amplitude Data register  
15  
14  
D6  
13  
12  
11  
D3  
10  
9
8
Bit number  
SGAR  
Address:  
00019CH  
D7  
D5  
D4  
D2  
D1  
D0  
Read/write  
Initial value  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(0) (0) (0) (0) (0) (0) (0) (0)  
The Amplitude Data register stores the reload value for the PWM pulse generator. The register  
867  
Chapter 42 Sound Generator  
3.Registers  
value represents the amplitude of the sound. The register value is reloaded into the PWM pulse  
generator at the end of every tone cycle.  
When the DEC bit is "1" and the Decrement counter reaches its reload value, this register value is  
decremented by 1(one). And when the register value reaches "00", further decrements are not  
performed. However the sound generator continues its operation until the ST bit is cleared.  
The following figure shows the relationship between the register value and the PWM pulse.  
One PWM Cycle  
256 input clock cycles  
Register value  
00h  
One input clock cycles  
80h  
129 input clock cycles  
FEh  
255 input clock cycles  
FFh  
256 input clock cycles  
When the register value is set to "FF", the PWM signal is always "1".  
■ Decrement Grade Register (SGDR)  
Decrement Grade register  
Address: 00019FH  
Bit number  
SGDR  
7
6
5
4
3
2
1
0
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Read/write  
Initial value  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(X) (X) (X) (X) (X) (X) (X) (X)  
The Decrement Grade register stores the reload value for the Decrement counter. They are  
prepared to automatically decrement the stored value in the Amplitude Data register.  
When the DEC bit is "1" and the Decrement counter counts the number of tone pulses up to the  
reload value, the stored value in the Amplitude Data register is decremented by 1 (one) at the  
end of the tone cycle.  
This operation realizes automatic decrement of the sound with fewer number of CPU  
interventions.  
It should be noted that the number of the tone pulses specified by this register equals to "register  
value +1". When the Decrement Grade register is set to "00", the decrement operation is  
performed every tone cycle.  
■ Tone Count Register (SGTR)  
Tone Count register  
15  
14  
13  
12  
11  
10  
9
8
Bit number  
SGTR  
Address:  
00019EH  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Read/write  
Initial value  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
(X) (X) (X) (X) (X) (X)  
(R/W) (R/W)  
(X) (X)  
The Tone Count register stores the reload value for the Tone Pulse counter. The Tone Pulse  
counter accumulate the number of tone pulses (or number of decrement operations) and when it  
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Chapter 42 Sound Generator  
3.Registers  
reaches the reload value it sets the INT bit. They are intended to reduce the frequency of  
interrupts.  
The count input of the Tone Pulse counter is connected to the carry-out signal from the  
Decrement counter. And when the Tone count register is set to "00", the Tone Pulse counter  
sets the INT bit every carry-out from the Decrement counter. Thus the number of  
accumulated tone pulses is:  
((Decrement Grade register) +1) x ((Tone Count register) +1)  
i.e. When the both registers are set to "00", the INT bit is set every tone cycle.  
869  
Chapter 42 Sound Generator  
3.Registers  
870  
Chapter 43 Stepper Motor Controller  
1.Overview  
Chapter 43 Stepper Motor Controller  
1. Overview  
The stepping motor controller consists of PWM pulse generators, motor drivers, selector logic  
circuits and A/D converter inputs.  
The four motor drivers have a high-output driving capability and two motor coils can be connect-  
ed directly to four pins. The motor rotation is designed to be controlled by a combination of the  
PWM pulse generators and selector logic circuits. The synchronization mechanism enables  
synchronous operation of two PWM pulse generators.  
■ Block Diagram of Stepping Motor Controller  
Figure 1-1 Stepping Motor Controller with A/D Converter Function  
PFR27  
PWM control register  
Output  
SC bit  
enable  
CE bit  
Selector  
PWM  
CK  
Clock  
Prescaler  
PWM1P  
PWM1M  
P27.0/AN16/SMC1P0  
PWM1 pulse generator  
EN  
PWM  
P27.1/AN17/SMC1M0  
P27.2/AN18/SMC2P0  
Peripheral  
Port 27  
clock  
PWM1 compare register  
PWM1 selection  
register  
CLKP  
Output  
enable  
CK  
PWM2P  
PWM2M  
Selector  
P27.3/AN19/SMC2M0  
PWM2 pulse generator  
PWM  
EN  
load  
PWM2 compare register  
BS PWM2 selection register  
A/D conversion  
channel setting  
register  
Decoder  
5
A/D converter  
input  
P26.x/ANx  
P27.x/ANx  
P28.x/ANx  
P29.x/ANx  
SMC channel 0 (ADC input)  
Remark: The SMC channels 0, 1, 2 and 3 are shared with ADC inputs.  
871  
     
Chapter 43 Stepper Motor Controller  
2.Registers  
Figure 1-2 Stepping Motor Controller  
PFR25  
PWM control register  
Output  
SC bit  
enable  
CE bit  
Selector  
PWM  
CK  
Clock  
Prescaler  
PWM1P  
PWM1M  
P25.0/SMC1P4  
PWM1 pulse generator  
EN  
PWM  
P25.1/SMC1M4  
P25.2/SMC2P4  
Peripheral  
Port 25  
clock  
PWM1 compare register  
PWM1 selection  
register  
CLKP  
Output  
enable  
CK  
PWM2P  
PWM2M  
Selector  
P25.3/SMC2M4  
PWM2 pulse generator  
PWM  
EN  
load  
PWM2 compare register  
BS PWM2 selection register  
SMC channel 4  
Remark: The SMC channels 4 and 5 are not shared with ADC inputs.  
2. Registers  
There are seven types of registers for the stepping motor controller:  
PWM Control register  
PWM1 Compare register  
PWM2 Compare register  
PWM1 Selection register  
PWM2 Selection register  
872  
 
Chapter 43 Stepper Motor Controller  
2.Registers  
2.1 Registers for Stepping Motor Controller  
PWM Control register (PWC0, PWC1, PWC2, PWC3, PWC4, PWC5)  
Address  
0x0C1, 0x0C3  
0x0C5, 0x0C7  
0x0C9, 0x0CB  
P2  
PWM1 Compare register (PWC10, PWC11, PWC12, PWC13, PWC14, PWC15)  
Address  
0x092, 0x09A  
0x0A2, 0x0AA  
0x0B2, 0x0BA  
Address  
0x093, 0x09B  
0x0A3, 0x0AB  
0x0B3, 0x0BB  
PWM2 Compare register (PWC20, PWC21, PWC22, PWC23, PWC24, PWC25)  
Address  
0x090, 0x098  
0x0A0, 0x0A8  
0x0B0, 0x0B8  
Address  
0x091, 0x099  
0x0A1, 0x0A9  
0x0B1, 0x0B9  
PWM2 Selection register (PWS20, PWS21, PWS22, PWS23, PWS24, PWS25)  
Address  
0x096, 0x09E  
0x0A6, 0x0AE  
0x0B6, 0x0BE  
PWM1 Selection register (PWS10, PWS11, PWS12, PWS13, PWS14, PWS15)  
Address  
0x097, 0x09F  
0x0A7, 0x0AF  
0x0B7, 0x0BF  
873  
Chapter 43 Stepper Motor Controller  
2.Registers  
2.2 PWM Control Register  
The PWM control register starts/stops the stepping motor controller, performs interrupt control  
and performs setting of external output pins, etc., for the stepping motor controller.  
■ PWM Control Register  
PWM Control register (PWC0, PWC1, PWC2, PWC3, PWC4, PWC5)  
Address  
0x0C1, 0x0C3  
0x0C5, 0x0C7  
0x0C9, 0x0CB  
P2  
[bit 7] Reserved bit  
Always set the reserved bit to "0".  
[bit 6 to 4] P2, P1, P0: Operating clock select bits (bits to select operating clock)  
The P2, P1 and P0 bits specify the clock input signal for the PWM pulse generator.  
PWM cycle (at F = 32 MHz)  
PWM cycle (at F = 40 MHz)  
cp  
cp  
P2  
P1  
P0  
Clock input  
SC=0  
8.0 us  
SC=1  
SC=0  
6.4 us  
SC=1  
F
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
32.0 us  
25.6 us  
CP  
F
F
F
F
/4  
/5  
/6  
/8  
32.0 us  
40.0 us  
48.0 us  
64.0 us  
80.0 us  
96.0 us  
128.0 us  
128.0 us  
160.0 us  
192.0 us  
256.0 us  
320.0 us  
384.0 us  
512.0 us  
25.6 us  
32.0 us  
38.4 us  
51.2 us  
64.0 us  
76.8 us  
102.4 us  
102.4 us  
128.0 us  
153.6 us  
204.8 us  
256.0 us  
307.2 us  
409.6 us  
CP  
CP  
CP  
CP  
F
/10  
/12  
/16  
CP  
CP  
CP  
F
F
F
: Peripheral clock CLKP  
CP  
Note:  
After operation clock selection, set 1 in CE.  
[bit 3] CE: Count enable bit  
The CE bit enables operation of the PWM pulse generator. When "1" is set to the CE bit, the PWM pulse  
generator starts its operating. The PWM2 pulse generator starts after the PWM1 pulse generator starts in  
order to reduce the switching noise generated by the output driver.  
When the CE bit is cleared to 0 during operation of the PWM pulse generator, the generator is initialized to  
stop operating.  
[bit 2] SC: 8/10 bits switching bit  
When "1" is set to the SC bit, the PWM pulse generator operates at 10 bit. When "0" is set to the SC bit, the  
874  
Chapter 43 Stepper Motor Controller  
2.Registers  
PWM pulse generator operates at 8 bit.  
[bit 1 to 0] Reserved bits  
Always set the reserved bits to "00".  
875  
Chapter 43 Stepper Motor Controller  
2.Registers  
2.3 PWM1&2 Compare Registers  
The value of the two 8(10) bits compare register of PWM1&2 determine the width of the PWM  
pulse. The stored "00 (000 )" value indicates that the PWM duty is 0%, and the stored "FF "  
H
H
H
("3FF ") value indicates that the PWM duty is 99.6% (99.9%).  
H
■ PWM1&2 Compare Registers  
The PWM1&2 compare registers can be accessed at any time, but the changed value is reflected in the pulse  
width at the end of the current PWM cycle after "1" is set to the BS bit of the PWM2 selection register.  
When "0" is set to SC bit of the PWM control register, and PWM performs 8-bit operation, the D9 and D8 bits are  
undefined value.  
Be sure to perform half-word access to the PWM1&2 compare registers  
PWM1 Compare register (PWC10, PWC11, PWC12, PWC13, PWC14, PWC15)  
Address  
0x092, 0x09A  
0x0A2, 0x0AA  
0x0B2, 0x0BA  
Address  
0x093, 0x09B  
0x0A3, 0x0AB  
0x0B3, 0x0BB  
PWM2 Compare register (PWC20, PWC21, PWC22, PWC23, PWC24, PWC25)  
Address  
0x090, 0x098  
0x0A0, 0x0A8  
0x0B0, 0x0B8  
Address  
0x091, 0x099  
0x0A1, 0x0A9  
0x0B1, 0x0B9  
[bit 15 to 10] Reserved bit  
Always set the reserved bit to "0".  
[bits 9 to 0] D9 to D0: Compare data  
These bits are used to set the PWM pulse width.  
876  
Chapter 43 Stepper Motor Controller  
2.Registers  
Figure 2-1 Relationship between the Compare Register Setting Value and PWM Pulse Width  
Register value  
One PWM cycle  
256 (1024) input cycles  
000H  
80H (200H)  
128 (512) input cycle  
FFH (3FFH)  
255 (1023) input cycle  
877  
Chapter 43 Stepper Motor Controller  
2.Registers  
2.4 PWM1&2 Selection Registers  
The PWM1&2 selection registers determine whether to set the output of the external pin of the  
stepping motor controller to "0", "1", PWM pulse or high impedance.  
■ PWM1&2 Selection Registers  
PWM2 Selection register (PWS20, PWS21, PWS22, PWS23, PWS24, PWS25)  
Address  
0x096, 0x09E  
0x0A6, 0x0AE  
0x0B6, 0x0BE  
PWM1 Selection register (PWS10, PWS11, PWS12, PWS13, PWS14, PWS15)  
Address  
0x097, 0x09F  
0x0A7, 0x0AF  
0x0B7, 0x0BF  
[bit 15] Reserved bit  
Always set the reserved bit to "0".  
[bit 14] BS: Rewrite bit  
The BS bit makes the setting for the PWM output match another setting. Until the BS bit is set, changes made  
to the two compare registers and two selection registers are not reflected in the output signal.  
When "1" is set to the BS bit, the PWM pulse generator and the selector load the values of the registers at the  
end of the current PWM cycle. The BS bit is cleared to “0” automatically at the beginning of the next PWM  
cycle.  
When "1" is set to the BS bit and is being cleared automatically by software simultaneously, the BS bit is set to  
“1” (no change is made to the BS bit) and the automatic clearing is cancelled.  
When "0" is set to the BS bit and is being cleared automatically by software simultaneously, the BS bit is  
cleared to “0”, however the PWM pulse generator and the selector are not load the values of the registers at  
the end of the current PWM cycle.  
Note:  
When the BS bit equals “1” when executing a read-modify-write type instruction the BS bit is "1" read as “1”  
and wrote as "1" in the BS bit again.  
When the BS bit was cleared automatically by the starting of a PWM cycle in between read and write, "1" is  
set after BS bit has cleared again.  
Therefore, values of the registers are loaded in the PWM pulse generator and selector when the BS bit is not  
set to "1" by the end of the next PWM cycle.  
878  
Chapter 43 Stepper Motor Controller  
2.Registers  
Figure 2-2 load timing of PWM compare register value  
[Automatic clear of BS bit]  
Load the values of the registers and  
reflected in the output signal.  
PWM 1 cycle  
PWM pulse  
PWM pulse generator  
counter value  
3FFh  
000h  
3FFh  
000h  
200h  
3FFh  
000h  
PWM compare  
register value  
3FFh  
XXXh  
200h  
3FFh  
Load  
Load  
PWM pulse generator  
compare register value  
200h  
BS  
When set a BS bit in "1" with automatic clear simultaneously  
PWM 1 cycle  
Load the values of the registers and  
reflected in the output signal.  
PWM pulse  
PWM pulse generator  
3FFh  
000h  
3FFh  
000h  
200h  
3FFh  
000h  
counter value  
PWM compare  
register value  
3FFh  
XXXh  
200h  
3FFh  
Load  
Load  
PWM pulse generator  
compare register value  
200h  
BS  
Automatic clear and "1" simultaneously  
write of a BS bit.  
When set a BS bit in "0" with automatic clear simultaneously  
PWM 1 cycle  
Load the values of the registers  
and reflected in the output signal.  
PWM pulse  
PWM pulse generator  
3FFh  
000h  
3FFh  
000h  
200h  
3FFh  
000h  
counter value  
PWM compare  
register value  
3FFh  
XXXh  
200h  
3FFh  
Load  
Load  
PWM pulse generator  
compare register value  
200h  
Automatic clear and "0" simultaneously  
write of a BS bit.  
BS  
When set a BS bit in "0" before the PWM cycle end  
PWM 1 cycle  
Not load the values of the registers and  
not reflected in the output signal.  
PWM pulse  
PWM pulse generator  
3FFh  
000h  
3FFh  
000h  
3FFh  
000h  
counter value  
PWM compare  
register value  
3FFh  
XXXh  
200h  
3FFh  
Not load  
Load  
PWM pulse generator  
compare register value  
BS  
"0" write of a BS bit before the 1 cycle end.  
879  
Chapter 43 Stepper Motor Controller  
2.Registers  
[bit 13 to 11] P2 to P0: Output select bits  
These bits are used to select the output signal for SMC2P.  
[bit 10 to 8] M2 to M0: Output select bits  
These bits are used to select the output signal for SMC2M.  
[bit 7 to 6] Reserved bit  
Always set the reserved bit to "0".  
[bit 5 to 3] P2 to P0: Output select bits  
These bits are used to select the output signal for SMC1P.  
[bit 2 to 0] M2 to M0: Output select bits  
These bits are used to select the output signal for SMC1M.  
The table below shows the relationship between the output levels and the select bits.  
P2  
P1  
P0  
PWMmPn  
M2  
M1  
M0  
PWMmMn  
0
0
0
1
0
0
0
1
L
H
0
0
0
1
0
0
0
1
L
H
1
X
X
PWM Pulse  
High impedance  
1
X
X
PWM Pulse  
High impedance  
X
X
m = 1 to 2 (motor coils)  
n = 0 to 5 (stepper motor channels)  
880  
Chapter 43 Stepper Motor Controller  
3.Operation  
3. Operation  
The operation of the stepping motor controller is explained.  
■ Setting Operation of Stepping Motor Controller  
Figure 3-1 Setting of Stepping Motor Controller  
PWM1 H width (compare value) is set.  
PWM2 H width (compare value) is set.  
Used bit  
Not used bit  
1 is set.  
0 is set.  
Channel No.  
■ Operation of PWM-pulse generator  
When the counter is started (PWC: CE = 1), the counter starts incrementing from 00H on the selected count  
clock rising. The PWM output pulse wave remains "H" until the value of the counter matches the value set to  
PWM compare register, and then changes to and remains "L" until the value of the counter overflows (FF -->  
H
00 ).  
H
Figure 3-2 "Examples of PWM1&2 Waveform Output" shows the PWM waveform generated by the PWM  
generator  
881  
 
Chapter 43 Stepper Motor Controller  
3.Operation  
Figure 3-2 Examples of PWM1&2 Waveform Output  
When the value of compare register is "00H"/"000H"(duty ratio is 0%):  
Value of counter:  
PWM waveform:  
When the value of compare register is "80H"/"200H"(duty ratio is 50%):  
Value of counter:  
PWM waveform:  
When the value of compare register is "FFH"/"3FFH"(duty ratio is 99.6%/99.9%):  
Value of counter:  
PWM waveform:  
One count  
■ Selection of motor drive signals  
Motor drive signals that are output to each pin related to the stepping motor controller can be selected among  
four types of signals for each pin by setting the PWM selection register.  
Table 3-1 "Selection of Motor Drive Signals and Setting of PWM Selection Registers 1&2" lists the selection of the  
motor drive signals and the settings of PWM selection registers 1&2.  
When these registers are set and "1" is written to the BS bit of the PWM selection register 2, the setting of these  
registers is enabled at the end of the current PWM cycle. The BS bit is to be cleared automatically to 0 at the  
beginning of the next PWM cycle. When "1" is written to the BS bit, and the BS bit is cleared to 0 simultaneously  
at the beginning of the next PWM cycle, "1" is written to the BS bit and clearing of the BS bit is cancelled.  
Table 3-1 Selection of Motor Drive Signals and Setting of PWM Selection Registers 1&2  
P2, P1, P0 Bits  
PWM2P Output  
PWM1P Output  
M2, M1, M0 Bits  
PWM1M Output  
PWM2M Output  
000  
001  
L
000  
L
B
B
B
B
H
001  
H
01X  
PWM Pulse  
01X  
PWM Pulse  
B
B
1XX  
High impedance  
1XX  
High impedance  
B
B
882  
   
Chapter 43 Stepper Motor Controller  
4.Caution  
4. Caution  
The caution when using the stepping motor controller are described below.  
■ Caution when Changing PWM Setting  
The PWM compare registers 1&2 (PWC1, PWC2) and the PWM selection registers 1&2 (PWS1, PWS2) can be  
accessed at any time. However, to change setting of the "H" width of PWM or to change the PWM output, "1"  
must be written to the BS bit of the PWM2 selection register after (or and at the same time) a setting is written to  
those registers (the PWM compare register 1&2 and the PWM selection register 1&2).  
When "1" is set to the BS bit, the new setting is enabled at the end of the current PWM cycle and the BS bit is  
cleared automatically.  
Also, when "1" is written to the BS bit and the BS bit is reset at the end of the PWM cycle simultaneously, "1" is  
written to the BS and resetting of the BS bit is cancelled.  
883  
 
Chapter 43 Stepper Motor Controller  
4.Caution  
884  
Chapter 44 A/D Converter  
1.Overview of A/D Converter  
Chapter 44 A/D Converter  
This chapter provides an overview of the A/D converter, describes the register structure and functions, and  
describes the operation of the A/D converter.  
• 1. Overview of A/D Converter  
• 2. Block Diagram of A/D Converter  
• 3. Registers of A/D Converter  
• 4. Operation of A/D Converter  
1. Overview of A/D Converter  
The A/D converter converts analog input voltage into digital values and provides the following features.  
Features of A/D converter:  
Conversion time: minimum 3 us per channel.  
RC type successive approximation conversion with sample & hold circuit  
10-bit or 8-bit resolution  
Program section analog input from 32 channels  
Single conversion mode: conversion of one selected channel  
Scan conversion mode: continuous conversion of multiple channels, programmable for up to 32 channels  
Single conversion mode:  
Continuous mode:  
Stop mode:  
Convert the specified channel only once.  
Repeatedly convert the specified channels.  
Convert one channel then temporarily halt until the next activation.  
(Enables synchronization of the conversion start timing.)  
A/D conversion can be followed by an A/D conversion interrupt request to CPU. This interrupt, an option that  
is ideal for continuous processing can be used to start a DMA transfer of the results of A/D conversion to  
memory.  
Startup may be by software, external trigger (falling edge) or timer (rising edge).  
■ Input impedance  
Sampling circuit of A/D converter is expressed in Figure 1-1 Input Impedance  
Rin  
Rext  
Analog  
signal  
source  
ANx  
Analog S W  
Cin
ADC  
Don•ft set Rext over maximum sampling time (Tsamp).  
Rext = Tsamp/ (7*Cin) - Rin  
Figure 1-1 Input Impedance  
885  
     
Chapter 44 A/D Converter  
2.Block Diagram of A/D Converter  
2. Block Diagram of A/D Converter  
Following figure shows block diagram of A/D converter.  
Block diagram of A/D converter  
MP X  
AN0  
AVCC  
AVRH/ L  
AN1  
AN2  
AN3  
AN4  
AN5  
AN6  
AN7  
AN8  
AN9  
AN10  
AN11  
AN12  
AVSS  
D/ A conve rte r  
S e quential  
c omparison re gister  
Comparator  
Sample & Hold  
circuit  
AN13  
AN14  
AN15  
AN16  
AN17  
AN18  
AN19  
AN20  
AN21  
AN22  
AN23  
AN24  
AN25  
AN26  
AN27  
AN28  
AN29  
AN30  
AN31  
A/ D data re giste r  
A/ D control re gister 0  
A/ D control re gister 1  
ADC S 0/ 1  
Ope rating  
Cloc k  
ATGX  
16- bit  
Re load Time r  
P re sc ale r  
CLKP  
Figure 2-1 Figure 20.2-1 "Block Diagram of A/D Converter"  
886  
 
Chapter 44 A/D Converter  
3.Registers of A/D Converter  
3. Registers of A/D Converter  
The A/D converter has the following registers.  
• • A/D enable register (ADER)  
• • A/D control status register (ADCS)  
• • Data register (ADCR)  
• • Sampling timer setting register (ADCT)  
• • Start channel setting register (ADSC)  
• • End channel setting register (ADEC)  
■ Register list  
• ADERH (ADC0): Address 01A0h (Access: Word, Half-word, Byte)  
15  
14  
13  
12  
11  
10  
9
8
Bit  
ADE31  
ADE30  
ADE29  
ADE28  
ADE27  
ADE26  
ADE25  
ADE24  
Initial  
value  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
7
6
5
4
3
2
1
0
Bit  
ADE23  
ADE22  
ADE21  
ADE20  
ADE19  
ADE18  
ADE17  
ADE16  
Initial  
value  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• ADERL (ADC0): Address 01A2h (Access: Word, Half-word, Byte)  
15  
14  
13  
12  
11  
10  
9
8
Bit  
ADE15  
ADE14  
ADE13  
ADE12  
ADE11  
ADE10  
ADE9  
ADE8  
Initial  
value  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
7
6
5
4
3
2
1
0
Bit  
ADE7  
ADE6  
ADE5  
ADE4  
ADE3  
ADE2  
ADE1  
ADE0  
Initial  
value  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• ADCS1 (ADC0): Address 01A4h (Access: Half-word, Byte)  
15  
14  
13  
12  
11  
10  
9
8
Bit  
BUSY  
INT  
INTE  
PAUS  
STS1  
STS0  
STRT  
reserved  
Initial  
value  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
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Chapter 44 A/D Converter  
3.Registers of A/D Converter  
• ADCS0 (ADC0): Address 01A5h (Access: Half-word, Byte)  
7
6
5
4
3
2
1
0
Bit  
MD1  
MD0  
S10  
ACH4  
ACH3  
ACH2  
ACH1  
ACH0  
Initial  
value  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R
R
R
R
R
Attribute  
Bit  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• ADCR1 (ADC0): Address 01A6h (Access: Word, Half-word, Byte)  
15  
-
14  
-
13  
-
12  
-
11  
-
10  
-
9
8
D9  
D8  
Initial  
value  
0
0
0
0
0
0
X
R
X
R
R0  
R0  
R0  
R0  
R0  
R0  
Attribute  
Bit  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• ADCR0 (ADC0): Address 01A7h (Access: Word, Half-word, Byte)  
7
6
5
4
3
2
1
0
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Initial  
value  
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
Attribute  
Bit  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• ADCT1 (ADC0): Address 01A8h (Access: Word, Half-word, Byte)  
15  
14  
13  
12  
11  
10  
9
8
CT5  
CT4  
CT3  
CT2  
CT1  
CT0  
ST9  
ST8  
Initial  
value  
0
0
0
1
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
Bit  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• ADCT0 (ADC0): Address 01A9h (Access: Word, Half-word, Byte)  
7
6
5
4
3
2
1
0
ST7  
ST6  
ST5  
ST4  
ST3  
ST2  
ST1  
ST0  
Initial  
value  
0
0
1
0
1
1
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
Bit  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• ADSCH (ADC0): Address 01AAh (Access: Word, Half-word, Byte)  
15  
-
14  
-
13  
-
12  
11  
10  
9
8
ANS4  
ANS3  
ANS2  
ANS1  
ANS0  
Initial  
value  
-
-
-
0
0
0
0
0
RX, W0  
RX, W0  
RX, W0  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
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Chapter 44 A/D Converter  
3.Registers of A/D Converter  
• ADECH (ADC0): Address 01ABh (Access: Word, Half-word, Byte)  
7
-
6
-
5
-
4
3
2
1
0
Bit  
ANE4  
ANE3  
ANE2  
ANE1  
ANE0  
Initial  
value  
-
-
-
0
0
0
0
0
RX, W0  
RX, W0  
RX, W0  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
3.1 A/D Enable Register (ADER)  
While a pin is used as analog input, corresponding bit in ADER register have to be set to 1.  
■ A/D enable register (ADER)  
• ADERH (ADC0): Address 01A0h (Access: Word, Half-word, Byte)  
15  
14  
13  
12  
11  
10  
9
8
Bit  
ADE31  
ADE30  
ADE29  
ADE28  
ADE27  
ADE26  
ADE25  
ADE24  
Initial  
value  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
7
6
5
4
3
2
1
0
Bit  
ADE23  
ADE22  
ADE21  
ADE20  
ADE19  
ADE18  
ADE17  
ADE16  
Initial  
value  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• ADERL (ADC0): Address 01A2h (Access: Word, Half-word, Byte)  
15  
14  
13  
12  
11  
10  
9
8
Bit  
ADE15  
ADE14  
ADE13  
ADE12  
ADE11  
ADE10  
ADE9  
ADE8  
Initial  
value  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
7
6
5
4
3
2
1
0
Bit  
ADE7  
ADE6  
ADE5  
ADE4  
ADE3  
ADE2  
ADE1  
ADE0  
Initial  
value  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
[ADE31-0]: A/D Input Enable  
ADE  
0
1
Function  
General purpose port [Initial value]  
Analog input  
RST clears them to 0.  
Be sure to set start channel and end channel to 1.  
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Chapter 44 A/D Converter  
3.Registers of A/D Converter  
3.2 A/D Control Status Register (ADCS)  
A/D control status register controls and shows the status of A/D converter. Do not overwrite ADCS0 register  
during A/D converting.  
■ A/D control status register 1 (ADCS1)  
• ADCS1 (ADC0): Address 01A4h (Access: Half-word, Byte)  
15  
14  
13  
12  
11  
10  
9
8
Bit  
BUSY  
INT  
INTE  
PAUS  
STS1  
STS0  
STRT  
reserved  
Initial  
value  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
[bit 7] BUSY (busy flag and stop)  
BUSY  
Function  
A/D converter operation indication bit. Set on activation of A/D conversion  
and cleared on completion.  
Reading  
Writing "0" to this bit during A/D conversion forcibly terminates  
conversion. Use to forcibly terminate in continuous and stop modes.  
Writing  
RMW instructions read the bit as "1".  
Cleared on the completion of A/D conversion in single conversion mode.  
In continuous and stop mode, the flag is not cleared until conversion is terminated by writing "0".  
Initialized to "0" by a reset.  
Do not specify forcible termination and software activation (BUSY="0" and STRT="1") at the same time.  
[bit 6] INT (interrupt)  
This bit is set when conversion data is stored in ADCR.  
If bit 5 (INTE) is "1" when this bit is set, an interrupt request is generated or, if activation of DMA is  
enabled, DMA is activated.  
Only clear this bit by writing "0" when A/D conversion is halted.  
Initialized to "0" by a reset.  
If DMA is used, this bit is cleared at the end of DMA transfer.  
[bit 5] INTE (Interrupt enable)  
This bit is enables or disables the conversion completion interrupt.  
INTE  
0
1
Function  
Disable interrupt [Initial value]  
Enable interrupt  
Cleared by a reset.  
[bit 4] PAUS (A/D converter pause)  
This bit is set when A/D conversion temporarily halts.  
The A/D converter has only one register to store the conversion result. Therefore, the previous  
conversion result is lost if it is not transferred by DMA when performing continuous conversion.  
To avoid this problem, the next conversion data is not stored in the data register until the previous value  
has been transferred by DMA. A/D conversion halts during this time. A/D conversion restarts when  
using DMA.  
This bit is only meaningful when using DMA.  
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Chapter 44 A/D Converter  
3.Registers of A/D Converter  
Cleared by writing "0" or by a reset. (Not cleared at the end of DMA transfer.) However when waiting  
condition of DMA transfer, this bit cannot be cleared.  
Regarding protect function of converted data, see Section “4. Operation of A/D Converter".  
[bit 3, 2] STS1, STS0 (Start source select)  
These bits initialized "00" by reset.  
These bits select the A/D activation source.  
STS1  
STS0  
Function  
0
0
1
0
1
0
Software activation [Initial value]  
External trigger pin activation and software activation  
Timer activation and software activation  
External trigger pin activation, timer activation and software  
1
1
activation  
In multiple-activation modes, the first activation to occur starts A/D conversion.  
The activation source changes immediately on writing to the register. Therefore care is required when  
switching activation mode during A/D operation.  
The A/D converter detects falling edges on the external trigger pin. When external trigger level is "L" and  
if these bits are changed to external trigger activation mode, A/D converting may starts.  
Selecting the timer selects the 16-bit reload timer 7.  
[bit 1] STRT (Start)  
Writing "1" to this bit starts A/D conversion (software activation).  
Write "1" again to restart conversion.  
Initialized to "0" by a reset.  
In continuous and stop mode, restarting is not occurred. Check BUSY bit before writing "1". (Activate  
conversion after clearing.)  
Do not specify forcible termination and software activation (BUSY="0" and STRT="1") at the same time.  
[bit 0] reserved bit  
Always write "0" to this bit.  
■ A/D control status register 0 (ADCS0)  
• ADCS0 (ADC0): Address 01A5h (Access: Half-word, Byte)  
7
6
5
4
3
2
1
0
Bit  
MD1  
MD0  
S10  
ACH4  
ACH3  
ACH2  
ACH1  
ACH0  
Initial  
value  
0
0
0
0
0
0
0
0
R/W  
R/W  
R/W  
R
R
R
R
R
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
[bit 7, 6] MD1, MD0 (A/D converter mode set)  
These bits the operation mode.  
MD1  
MD0  
Operating mode  
0
0
1
1
0
1
0
1
Single mode ; all restarts conversion during operation enabled  
Single mode ; restarts conversion during operation disabled  
Continuous mode ; restarts conversion during operation disabled  
Stop mode ; restarts conversion during operation disabled  
Single mode: Continuous A/D conversion from selected channel(s) ANS4 to ANS0 to selected channel(s)  
ANE4 to ANE0 with a pause after every conversion cycle.  
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Chapter 44 A/D Converter  
3.Registers of A/D Converter  
Continuous mode: Repeated A/D conversion cycles from selected channels ANS4 to ANS0 to selected  
channels ANE4 to ANE0.  
Stop mode: A/D conversion for each channel from selected ANS4 to ANS0 to selected channels ANE4 to  
ANE0, followed by a pause. Restart is determined by the occurrence of a start source.  
When A/D conversion is started in continuous mode or stop mode, conversion operation continued until  
stopped by the BUSY bit.  
Conversion is stopped by writing "0" to the BUSY bit.  
On activation after forcibly stopping, conversion starts from channel selected ANS4 to ANS0.  
All restarts are disabled for any of the timer, external trigger and software start sources in single,  
continuous and stop modes.  
[bit 5] S10  
This bit defines resolution of A/D conversion. If this bit set "0", the resolution is 10-bit. In the other case,  
resolution is 8-bit and the conversion result is stored to ADCR0.  
Initialized to "0" by a reset.  
[bit 4 to 0] ACH4-0 (Analog convert select channel)  
These bits show current converted channel.  
ACH4  
0
ACH3  
0
ACH2  
0
ACH1  
0
ACH0  
0
Converted channel  
AN0  
0
0
0
0
1
AN1  
0
0
0
1
0
AN2  
0
0
0
1
1
AN3  
0
0
1
0
0
AN4  
0
0
1
0
1
AN5  
0
0
1
1
0
AN6  
0
0
1
1
1
AN7  
0
1
0
0
0
AN8  
0
1
0
0
1
AN9  
0
1
0
1
0
AN10  
AN11  
AN12  
AN13  
AN14  
AN15  
AN16  
AN17  
AN18  
AN19  
AN20  
AN21  
AN22  
AN23  
AN24  
AN25  
AN26  
AN27  
AN28  
AN29  
AN30  
AN31  
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
ACH  
Function  
Current converted channel is shown during A/D converting (BUSY="1"). If  
Reading  
Writing  
conversion is halt by forcibly stopping, they shows the stopped channel.  
No effect to these bits.  
Initialized to "0000" by reset.  
3.3 Data Register (ADCR1, ADCR0)  
These registers store the conversion results of the A/D converter. ADCR0 stores lower 8-bit. ADCR1 stores upper  
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Chapter 44 A/D Converter  
3.Registers of A/D Converter  
2-bit. The register values are updated at the completion of each conversion. The registers normally store the  
results of the previous conversion.  
■ Data register (ADCR1, ADCR0)  
• ADCR1 (ADC0): Address 01A6h (Access: Word, Half-word, Byte)  
15  
-
14  
-
13  
-
12  
-
11  
-
10  
-
9
8
Bit  
D9  
D8  
Initial  
value  
-
-
-
-
-
-
X
R
X
R
RX, W0  
RX, W0  
RX, W0  
RX, W0  
RX, W0  
RX, W0  
Attribute  
Bit  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• ADCR0 (ADC0): Address 01A7h (Access: Word, Half-word, Byte)  
7
6
5
4
3
2
1
0
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Initial  
value  
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
Bit 15 to 10 of ADCR1 are read as "0".  
The A/D converter has a conversion data protection function. See the "Operation" section for further  
information.  
3.4 Sampling Timer Setting Register (ADCT)  
ADCT register controls the sampling time and conversion time of analog input. This register sets A/D conversion  
time. Do not update value of this register during A/D conversion operation.  
■ Sampling timer setting register (ADCT)  
• ADCT1 (ADC0): Address 01A8h (Access: Word, Half-word, Byte)  
15  
14  
13  
12  
11  
10  
9
8
Bit  
CT5  
CT4  
CT3  
CT2  
CT1  
CT0  
ST9  
ST8  
Initial  
value  
0
0
0
1
0
0
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
Bit  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• ADCT0 (ADC0): Address 01A9h (Access: Word, Half-word, Byte)  
7
6
5
4
3
2
1
0
ST7  
ST6  
ST5  
ST4  
ST3  
ST2  
ST1  
ST0  
Initial  
value  
0
0
1
0
1
1
0
0
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
[bit 15 to 10] CT5-0 (A/D conversion time set)  
These bits specify clock division of conversion time.  
Setting "000001" means one division (=CLKP).  
Do not set these bits "000000".  
Initialized these bits to "000100" by reset.  
893  
Chapter 44 A/D Converter  
3.Registers of A/D Converter  
Conversion time = CT value * CLKP cycle * 10 + (4 * CLKP)  
Remarks : Do not set conversion time over 500 us.  
[bit 9 to 0] ST9-0 (Analog input sampling time set)  
These bits specify sampling time of analog input.  
Initialized these bits to "0000101100" by reset.  
Sampling time = ST value * CLKP cycle  
Remarks : Do not set sampling time below 1.2 us when AVCC is below 4.5 V.  
Necessary sampling time and ST value are calculated by following.  
Necessary sampling time (Tsamp) = (Rext + Rin) * Cin * 7  
ST9 to ST0 = Tsamp / CLKP cycle  
ST has to be set that sampling time is over Tsamp.  
ex. CLKP = 32MHz, AVCC >= 4.5V, Rext = 200K  
Tsamp = ( 200 * 103 + 2.52 * 103 ) * 10.7 * 10-12 * 7 = 15.17 [us]  
ST = 15.17-6 / 31.25-9 = 485.44  
ST has to be set over 486 (111100110 ).  
D
B
Tsamp is decided by Rext. Thus conversion time should be considered together with Rext.  
3.5 A/D Channel Setting Register (ADSCH, ADECH)  
These registers specify the channels for the A/D converter to convert. Do not update these registers while the A/D  
converting is operating.  
■ A/D channel setting register (ADSCH, ADECH)  
• ADSCH (ADC0): Address 01AAh (Access: Word, Half-word, Byte)  
15  
-
14  
-
13  
-
12  
11  
10  
9
8
Bit  
ANS4  
ANS3  
ANS2  
ANS1  
ANS0  
Initial  
value  
-
-
-
0
0
0
0
0
RX, W0  
RX, W0  
RX, W0  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
894  
Chapter 44 A/D Converter  
3.Registers of A/D Converter  
• ADECH (ADC0): Address 01ABh (Access: Word, Half-word, Byte)  
7
-
6
-
5
-
4
3
2
1
0
Bit  
ANE4  
ANE3  
ANE2  
ANE1  
ANE0  
Initial  
value  
-
-
-
0
0
0
0
0
RX, W0  
RX, W0  
RX, W0  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
These bits set the start and end channel for A/D converter.  
Setting of ANE4 to ANE0 the same channel as in ANS4 to ANS0 specifies conversion for that channel  
only. (Single conversion)  
In continuous or stop mode, conversion is performed up to the channel specified by ANE4 to ANE0.  
Conversion then starts again from the start channel specified by ANS4 to ANS0.  
If ANS > ANE, conversion starts with the channel specified by ANS, continuous up to channel 31, starts  
again from channel 0, and ends with the channel specified by ANE.  
Initialized to ANS="00000", ANE="00000" by a reset.  
ex. Channel Setting ANS=30ch, ANE=3ch, single conversion mode  
Operation : Conversion channel 30ch -> 31ch -> 0ch -> 1ch -> 2ch -> 3ch end  
[bit 12 to 8] ANS4-0 (Analog start channel set)  
[bit 4 to 0] ANE4-0 (Analog end channel set)  
ANS4  
ANS3  
ANS2  
ANS1  
ANS0  
Start / End Channel  
ANE4  
ANE3  
ANE2  
ANE1  
ANE0  
0
0
0
0
0
AN0  
0
0
0
0
1
AN1  
0
0
0
1
0
AN2  
0
0
0
1
1
AN3  
0
0
1
0
0
AN4  
0
0
1
0
1
AN5  
0
0
1
1
0
AN6  
0
0
1
1
1
AN7  
0
1
0
0
0
AN8  
0
1
0
0
1
AN9  
0
1
0
1
0
AN10  
AN11  
AN12  
AN13  
AN14  
AN15  
AN16  
AN17  
AN18  
AN19  
AN20  
AN21  
AN22  
AN23  
AN24  
AN25  
AN26  
AN27  
AN28  
AN29  
AN30  
AN31  
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
895  
Chapter 44 A/D Converter  
4.Operation of A/D Converter  
4. Operation of A/D Converter  
The A/D converter operates using the successive approximation method with 10-bit or 8-bit resolution. As only  
one 16-bit register is provided to store conversion results, the conversion data register (ADCR0 and ADCR1) is  
updated each time conversion completes. Therefore, as the A/D converter on its own is not suitable for  
performing continuous conversion, it is recommended that you use the DMA service. The following describes the  
operation modes.  
■ Single Mode  
In single conversion mode, the analog input signals selected by the ANS bits and ANE bits are converted  
in order until the completion of conversion on the end channel determined by the ANE bits. A/D  
conversion then ends. If the start channel and end channel are the same (ANS=ANE), only a signal  
channel conversion is performed.  
ex.  
ANS=00000b, ANE=00011b  
Start -> AN0 -> AN1 -> AN2 -> AN3 -> End  
ANS=00010b, ANE=00010b  
Start -> AN2 -> End  
■ Continuous Mode  
In continuous mode the analog input signals selected by the ANS bits and ANE bits are converted in  
order until the completion of conversion on the end channel determined by the ANE bits, then the  
converter returns to the ANS channel for analog input and repeats the process continuously. When  
the start and end channels are the same (ANS=ANE), conversion is performed continuously for that  
channel.  
ex.  
ANS=00000b, ANE=00011b  
Start -> AN0 -> AN1 -> AN2 -> AN3 -> AN0 ... -> repeat  
ANS=00010b, ANE=00010b  
Start -> AN2 -> AN2 -> AN2 ... -> repeat  
In continuous mode, conversion is repeated until '0' is written to the BUSY bit. (Writing '0' to the BUSY bit  
forcibly stops the conversion operation.) Note that forcibly terminating operation halts the current  
conversion during mid-conversion. (If operation is forcibly terminated, the value in the conversion  
register is the result of the most recently completed conversion.)  
■ Stop Mode  
In stop mode the analog input signal selected by the ANS bits and ANE bits are converted in order, but  
conversion operation pauses for each channel. The pause is released by applying another start  
signal.  
At the completion of conversion on the end channel determined by the ANE bits, the converter returns to  
the ANS channel for analog input signal and repeats the conversion process continuously. When the  
start and end channel are the same (ANS=ANE), only a signal channel conversion is performed.  
ex.  
ANS=00000b, ANE=00011b  
Start -> AN0 -> stop -> start -> AN1 -> stop -> start -> AN2 -> stop -> start -> AN3 -> stop ->  
start -> AN0 ... -> repeat  
ANS=00010b, ANE=00010b  
Start -> AN2 -> stop -> start -> AN2 -> stop -> start -> AN2 ... -> repeat  
In stop mode the startup source is only the source determined by the STS1, STS0 bits. This mode  
enables synchronization of the conversion start signal.  
896  
 
Chapter 44 A/D Converter  
4.Operation of A/D Converter  
4.1 Single-shot conversion mode  
AN input  
(1)  
Channel  
selection  
(2)  
Activation  
(trigger)  
(4)  
(5)  
Internal level  
Sample  
hold  
Conversion Conversion  
Conversion  
a
b
c
Conversion  
value  
Conversion in progress  
Previous conversion value  
Finalized  
(7)  
Buffer  
(ADT)  
New conversion value  
Flag clear on A/D conversion activation  
(8)  
Conversion end  
(INT)  
(3)  
(6)  
Flag clear  
(A/D conversion  
activation,  
BUSY  
Conversion time  
or software)  
(1)  
(2)  
(3)  
(4)  
(5)  
(6)  
(7)  
(8)  
Channel selection  
A/D conversion activation (Trigger input: Software trigger/Reload timer/External trigger)  
INT flag clear, BUSY flag set  
Sample hold  
Conversion (Conversion a + Conversion b + Conversion c)  
Conversion end, INT flag set, BUSY flag clear  
Buffers the conversion value. Buffered data storage  
Software-based INT flag clear  
897  
Chapter 44 A/D Converter  
4.Operation of A/D Converter  
4.2 Scan conversion mode  
AN input  
(1)  
Scan start  
AN2  
AN3  
channel  
selection  
AN0  
AN1  
AN2  
(6)  
AN3  
(7)  
AN0  
(4)  
AN1  
Sample hold  
(2)  
Activation  
(trigger)  
(9)  
(5)  
a, b, c  
Buffers  
ADT0  
AN0 conversion value  
AN1 conversion value  
AN2 conversion value  
ADT1  
ADT2  
ADT3  
AN3 conversion value  
(10)  
Conversion end  
(INT)  
(3)  
(8)  
BUSY  
(1)  
(2)  
(3)  
(4)  
Activation channel selection  
A/D activation (Trigger: Software trigger/Reload timer/External trigger)  
INT flag clear, BUSY flag set  
AN0 conversion  
a. Sample hold, conversion (conversion a + conversion b + conversion c)  
b. Conversion end  
c. Buffers the conversion value.  
AN1 conversion  
(5)  
(6)  
(7)  
(8)  
(9)  
(10)  
AN2 conversion  
AN3 conversion  
INT flag set, BUSY flag clear  
Next A/D activation  
INT flag clear, BUSY flag set  
898  
Chapter 44 A/D Converter  
5.Setting  
5. Setting  
Table 5-1 Settings needed to use A/D - Single-Shot Conversion Mode  
Setting  
Procedure*  
Setting  
Setting Registers  
Mode selection (Single-shot conversion)  
Bit length selection  
See 7.1  
See 7.2  
See 7.3  
See 7.4  
A/D control (ADCS)  
Channel selection  
Conversion time setting  
Conversion time setting (ADCT)  
Port Function (PFR26-PFR29) and Extra Port  
Function (EPFR26-EPFR27)  
To program the AN pin as an input  
A/D activation trigger selection  
See 7.5  
See 7.6  
A/D activation trigger generation  
Software trigger  
A/D control (ADCS)  
-> Software trigger bit setting  
See 7.7  
Reload timer  
-> Reload timer rising output  
See “Chapter 38 Reload Timer (Page  
No.775)”.  
External trigger  
-> Inputs a trigger to the ADTG(0, 1) pin.  
External input  
Conversion end flag check  
Conversion value read  
A/D control (ADCS)  
Data buffers (ADCR)  
See 7.8  
See 7.9  
*: For the setting procedure, refer to the section indicated by the number.  
Table 5-2 Settings needed to use A/D - Scan Conversion Mode  
Setting  
Procedure*  
Setting  
Setting Registers  
Mode selection (Scan conversion)  
Bit length selection  
See 7.1  
See 7.2  
See 7.3  
See 7.4  
A/D control (ADCS)  
Starting channel selection  
Conversion time setting  
Conversion time setting (ADCT)  
Port Function (PFR26-PFR29) and Extra Port  
Function (EPFR26-EPFR27)  
Program the AN pin as an input.  
A/D activation trigger selection  
See 7.5  
See 7.6  
A/D activation trigger generation  
Software trigger  
A/D control (ADCS)  
-> Software trigger bit setting  
See 7.7  
Reload timer  
-> Reload timer falling output  
See “Chapter 38 Reload Timer (Page  
No.775)”.  
External trigger  
-> Inputs a trigger to the ATGX pin.  
External input  
Conversion end flag check  
Conversion value read  
A/D control (ADCS)  
Data buffers (ADCR)  
See 7.8  
See 7.9  
*: For the setting procedure, refer to the section indicated by the number.  
899  
 
Chapter 44 A/D Converter  
5.Setting  
Table 5-3 Forcing A/D operations to Stop  
Setting  
Forced stop  
Setting Registers  
A/D control (ADCS)  
Setting Procedure*  
See 7.10  
*: For the setting procedure, refer to the section indicated by the number.  
Table 5-4 Items needed to enable A/D Interrupts  
Setting  
Procedure*  
Setting  
Setting Registers  
See “Chapter 24 Interrupt Control (Page  
No.311)”.  
A/D interrupt vector and A/D interrupt level settings  
See 7.11.  
A/D interrupt cause selection  
(A/D conversion end)  
See 7.12  
See 7.13.  
A/D control registers (ADCS)  
A/D interrupt setting  
Clear interrupt requests.  
Enable interrupt requests.  
*: For the setting procedure, refer to the section indicated by the number.  
900  
Chapter 44 A/D Converter  
6.Q & A  
6. Q & A  
6.1 What conversion modes are available and how are they selected?  
Two modes of conversion are available:  
• Single-shot conversion mode, in which the conversion takes place only once.  
• Scan conversion mode, in which a specified sequence of channels are converted.  
Mode selection is made using the conversion mode selection bits (ADCS.MD[1:0]).  
MD1 MD0  
Operating mode  
0
0
1
1
0
1
0
1
Single mode ; all restarts conversion during operation enabled  
Single mode ; restarts conversion during operation disabled  
Continuous mode ; restarts conversion during operation disabled  
Stop mode ; restarts conversion during operation disabled  
6.2 How do I specify a bit length?  
Configure the conversion result storage bit length setting (ADCS.S10).  
Operation Mode  
Conversion Result Storage Bit Length (S10)  
To store conversion results in the ADCR register in 10 bits  
To store conversion results in the ADCR register in 8 bits  
Set “0”.  
Set “1”.  
901  
 
Chapter 44 A/D Converter  
6.Q & A  
6.3 How do I set a conversion time?  
Use Conversion Time Setting registers ADCT to set.  
[bit 15 to 10] CT5-0 (A/D conversion time set)  
These bits specify clock division of conversion time.  
Setting "000001" means one division (=CLKP).  
Do not set these bits "000000".  
Initialized these bits to "000100" by reset.  
Conversion time = CT value * CLKP cycle * 10 + (4 * CLKP)  
Remarks : Do not set conversion time over 500 us.  
[bit 9 to 0] ST9-0 (Analog input sampling time set)  
These bits specify sampling time of analog input.  
Initialized these bits to "0000101100" by reset.  
Sampling time = ST value * CLKP cycle  
Remarks : Do not set sampling time below 1.2 us when AVCC is below 4.5 V.  
Necessary sampling time and ST value are calculated by following.  
Necessary sampling time (Tsamp) = (Rext + Rin) * Cin * 7  
ST9 to ST0 = Tsamp / CLKP cycle  
ST has to be set that sampling time is over Tsamp.  
ex. CLKP = 32MHz, AVCC >= 4.5V, Rext = 200K  
Tsamp = ( 200 * 103 + 2.52 * 103 ) * 10.7 * 10-12 * 7 = 15.17 [us]  
ST = 15.17-6 / 31.25-9 = 485.44  
ST has to be set over 486 (111100110 ).  
D
B
Tsamp is decided by Rext. Thus conversion time should be considered together with Rext.  
6.4 How do I enable analog pin input?  
Use Port Function register PFR and Extra Port Function register EPFR.  
Operation  
PFR setting  
PFR29.0 = ‘1’  
PFR29.1 = ‘1’  
PFR29.2 = ‘1’  
PFR29.3 = ‘1’  
PFR29.4 = ‘1’  
PFR29.5 = ‘1’  
PFR29.6 = ‘1’  
PFR29.7 = ‘1’  
PFR28.0 = ‘1’  
PFR28.1 = ‘1’  
PFR28.2 = ‘1’  
PFR28.3 = ‘1’  
PFR28.4 = ‘1’  
PFR28.5 = ‘1’  
PFR28.6 = ‘1’  
PFR28.7 = ‘1’  
PFR27.0 = ‘1’  
PFR27.1 = ‘1’  
EPFR setting  
EPFR29.0 = ‘0’  
EPFR29.1 = ‘0’  
EPFR29.2 = ‘0’  
EPFR29.3 = ‘0’  
EPFR29.4 = ‘0’  
EPFR29.5 = ‘0’  
EPFR29.6 = ‘0’  
EPFR29.7 = ‘0’  
EPFR28.0 = ‘0’  
EPFR28.1 = ‘0’  
EPFR28.2 = ‘0’  
EPFR28.3 = ‘0’  
EPFR28.4 = ‘0’  
EPFR28.5 = ‘0’  
EPFR28.6 = ‘0’  
EPFR28.7 = ‘0’  
EPFR27.0 = ‘1’  
EPFR27.1 = ‘1’  
To program the AN0 pin as an input  
To program the AN1 pin as an input  
To program the AN2 pin as an input  
To program the AN3 pin as an input  
To program the AN4 pin as an input  
To program the AN5 pin as an input  
To program the AN6 pin as an input  
To program the AN7 pin as an input  
To program the AN8 pin as an input  
To program the AN9 pin as an input  
To program the AN10 pin as an input  
To program the AN11 pin as an input  
To program the AN12 pin as an input  
To program the AN13 pin as an input  
To program the AN14 pin as an input (*)  
To program the AN15 pin as an input (*)  
To program the AN16 pin as an input  
To program the AN17 pin as an input  
902  
Chapter 44 A/D Converter  
6.Q & A  
To program the AN18 pin as an input  
To program the AN19 pin as an input  
To program the AN20 pin as an input  
To program the AN21 pin as an input  
To program the AN22 pin as an input  
To program the AN23 pin as an input  
To program the AN24 pin as an input  
To program the AN25 pin as an input  
To program the AN26 pin as an input  
To program the AN27 pin as an input  
To program the AN28 pin as an input  
To program the AN29 pin as an input  
To program the AN30 pin as an input  
To program the AN31 pin as an input  
PFR27.2 = ‘1’  
PFR27.3 = ‘1’  
PFR27.4 = ‘1’  
PFR27.5 = ‘1’  
PFR27.6 = ‘1’  
PFR27.7 = ‘1’  
PFR26.0 = ‘1’  
PFR26.1 = ‘1’  
PFR26.2 = ‘1’  
PFR26.3 = ‘1’  
PFR26.4 = ‘1’  
PFR26.5 = ‘1’  
PFR26.6 = ‘1’  
PFR26.7 = ‘1’  
EPFR27.2 = ‘1’  
EPFR27.3 = ‘1’  
EPFR27.4 = ‘1’  
EPFR27.5 = ‘1’  
EPFR27.6 = ‘1’  
EPFR27.7 = ‘1’  
EPFR26.0 = ‘1’  
EPFR26.1 = ‘1’  
EPFR26.2 = ‘1’  
EPFR26.3 = ‘1’  
EPFR26.4 = ‘1’  
EPFR26.5 = ‘1’  
EPFR26.6 = ‘1’  
EPFR26.7 = ‘1’  
* Analogue input channels AN14 and AN15 can be also used as D/A converter outputs. In case of exclusive A/D converter  
usage do not enable the D/A converter output with DACR.DAE[1:0] since this has priority over A/D converter input. See  
chapter “D/A Converter (Page No.909)” for further information about D/A converter.  
6.5 How do I enable analog pin input for Stepper Motor Controller?  
Use Port Function register PFR and Extra Port Function register EPFR.  
Operation  
PFR setting  
PFR27.0 = ‘1’  
PFR27.1 = ‘1’  
PFR27.2 = ‘1’  
PFR27.3 = ‘1’  
PFR27.4 = ‘1’  
PFR27.5 = ‘1’  
PFR27.6 = ‘1’  
PFR27.7 = ‘1’  
PFR26.0 = ‘1’  
PFR26.1 = ‘1’  
PFR26.2 = ‘1’  
PFR26.3 = ‘1’  
PFR26.4 = ‘1’  
PFR26.5 = ‘1’  
PFR26.6 = ‘1’  
PFR26.7 = ‘1’  
EPFR setting  
EPFR27.0 = ‘0’  
EPFR27.1 = ‘0’  
EPFR27.2 = ‘0’  
EPFR27.3 = ‘0’  
EPFR27.4 = ‘0’  
EPFR27.5 = ‘0’  
EPFR27.6 = ‘0’  
EPFR27.7 = ‘0’  
EPFR26.0 = ‘0’  
EPFR26.1 = ‘0’  
EPFR26.2 = ‘0’  
EPFR26.3 = ‘0’  
EPFR26.4 = ‘0’  
EPFR26.5 = ‘0’  
EPFR26.6 = ‘0’  
EPFR26.7 = ‘0’  
To program the AN16 pin as an input for SMC1P0  
To program the AN17 pin as an input for SMC1M0  
To program the AN18 pin as an input for SMC2P0  
To program the AN19 pin as an input for SMC2M0  
To program the AN20 pin as an input for SMC1P1  
To program the AN21 pin as an input for SMC1M1  
To program the AN22 pin as an input for SMC2P1  
To program the AN23 pin as an input for SMC2M1  
To program the AN24 pin as an input for SMC1P2  
To program the AN25 pin as an input for SMC1M2  
To program the AN26 pin as an input for SMC2P2  
To program the AN27 pin as an input for SMC2M2  
To program the AN28 pin as an input for SMC1P3  
To program the AN29 pin as an input for SMC1M3  
To program the AN30 pin as an input for SMC2P3  
To program the AN31 pin as an input for SMC2M3  
See chapter “Stepper Motor Controller (Page No.871)” about using the A/D converter for SMC operation.  
6.6 To select how to activate the A/D converter  
There are three types of activation triggers:  
• Software trigger  
• Reload timer rising signal  
• External trigger input falling signal  
To set an activation trigger, use Activation Trigger Selection bits (ADCS.STS[1: 0]).  
Activation Trigger Selection bit  
A/D Activation Trigger  
(STS[1: 0])  
903  
Chapter 44 A/D Converter  
6.Q & A  
To specify a software trigger  
Set “00”.  
Set “01”.  
Set “10”.  
Set “11”.  
To specify an external trigger/software trigger  
To specify a reload timer/software trigger  
To specify an external trigger/reload timer/software trigger  
The converter A/D is activated on the first instance of any one of these causes selected.  
6.7 To activate the A/D converter  
• Generating a software trigger  
A software trigger is generated using A/D Conversion Software Trigger bits (ADCS.STRT).  
Operation  
A/D Conversion Software Trigger Bit (STRT)  
To generate a software trigger  
Write “1”.  
• Activating A/D converter with reload timer 7  
The reload timers must be setup and activated. For more information, see “Chapter 38 Reload Timer (Page  
No.775)” When an underflow of a reload timer causes the reload timer output signal to rise, an activation  
trigger is generated.  
• Activating A/D converter with an external trigger  
Use external trigger input pin ATGX to generate an external trigger.  
The external trigger input pin is set using Port Function bits (PFR16.7) and Extra Port Function Register  
(EPFR16.7).  
Operation  
Setting  
Set PFR16.7 = ‘0’ and DDR16.7 = ‘0’ (port input mode)  
Set PFR16.7 = ‘1’ and EPFR16.7 = ‘1’ (function mode)  
To program the ATGX pin as a trigger input  
6.8 To verify the end of a conversion  
There are two ways to verify the end of a conversion, as follows:  
• Checking the A/D Conversion End Interrupt Request bits (ADCS.INT)  
(INT)  
Description  
If the read value is “0”  
If the read value is “1”  
No A/D conversion end interrupt request  
A/D conversion end interrupt request  
• Checking the Operation Verification bits (ADCS.BUSY)  
(BUSY)  
Setting  
If the read value is “0”  
If the read value is “1”  
A/D conversion end (stop)  
A/D conversion in progress  
6.9 How do I read a conversion value?  
The conversion value can be read from Data Buffer register ADCR.  
6.10 How do I force an A/D conversion operation to a stop?  
Use the Forced Stop bits (ADCS.BUSY)  
Operation  
Forced Stop Bit (BUSY)  
Write “0”.  
To force an A/D conversion operation to a stop  
The operation of the A/D is unaffected by writing “1” to the Forced Stop bit (BUSY).  
904  
 
Chapter 44 A/D Converter  
6.Q & A  
6.11 What interrupt registers are used?  
A/D interrupt vector, A/D interrupt level setting  
The table below summarizes the relationships among the machine cycle, A/D number, interrupt level, and  
interrupt vector.  
For more information about the interrupt level and interrupt vector, see “Chapter 24 Interrupt Control (Page  
No.311).”  
Interrupt Vector (Default)  
Interrupt Level Setting Bit (ICR[4:0])  
#134  
Address: 0FFDE4h  
Interrupt Level register (ICR59)  
Address: 047Bh  
AD0  
6.12 What interrupts are available?  
A/D Conversion End interrupt only. No interrupt cause selection bit is available.  
6.13 How do I enable, disable, clear interrupts?  
Interrupt Request Enable flag, Interrupt Request flag  
Interrupts are enabled using the Interrupt Request Enable bits (ADCS.INTE).  
Interrupt Request Enable Bit (INTE)  
To disable interrupt requests  
To enable interrupt requests  
Set “0”.  
Set “1”.  
Interrupt request are cleared using the Interrupt Request bits (ADCS.INT).  
Interrupt Request Bit (INT)  
Write “0”  
To clear interrupt requests  
or activate A/D. (See “6.7 To activate the A/D converter (Page No.904)”.)  
(See “7. Caution (Page No.906)”.)  
905  
Chapter 44 A/D Converter  
7.Caution  
7. Caution  
Tips on using the A/D converter are summarized as follows:  
• Power-on sequence  
Be sure to turn on the MCU power (Vdd*) before turning on the power to the A/D converter (AVcc, AVRH)  
and applying a voltage to the analog input.  
• Input impedance of the analog input pin  
The A/D converter has a built-in sample hold circuit to receive the voltage present on the analog input pin in  
the sample hold capacitor after the activation of an A/D conversion. Therefore, if the analog input external  
circuit has a high output impedance, it may happen that analog input voltage fails to get stabilized within the  
sampling cycle. For this reason, keep the output impedance of the external circuit sufficiently low.  
If the output impedance of the external circuit cannot be kept sufficiently low, lengthen the sampling time  
fully.  
• As AVRH-AV decreases the error grows in proportion.  
SS  
906  
 
Chapter 44 A/D Converter  
7.Caution  
■ Definitions of A/D Converter Terms  
• Resolution  
Analog change identifiable to an A/D converter.  
• Linearity error  
Deviation between the straight line connecting zero transition point  
(00 0000 0000 <- -> 00 0000 0001) and full-scale transition point  
(11 1111 1110 <- -> 11 1111 1111) from actual conversion characteristics  
• Differential linearity error  
Deviation of the input voltage required for changing the output by one LSB, from its ideal value  
VFST - VOT  
=
1LSB  
[V]  
1022  
: Voltage at which digital output transit from (000) to (001)  
H
V
OT  
H
VV : Voltage at which digital output transit from (3FE) to (3FF)  
FST  
H
H
V
- {1LSB × (N-1) + V  
1LSB  
V(N+1)T - VNT  
}
Digital output N  
Linearity error  
Digital output N  
Differential linearity  
error  
NT  
OT  
=
=
[LSB]  
[LSB]  
-1  
1LSB  
V
: Voltage at which digital output transit from (N+1) to N  
NT  
Differentional linearity error  
Linearity error  
3FF  
3FE  
3FD  
Actual conversion characteristics  
Actual conversion characteristics  
N+1  
N
{1LSB (N-1)+VOT}  
VFST  
(Measurement  
value)  
004  
003  
002  
001  
VNT  
(Measurement  
value)  
N-1  
N-2  
VFST  
(Measurement  
value)  
Actual conversion characteristics  
VNT  
Ideal characteristics  
Actual conversion characteristics  
VOT (Measurement value)  
AVss  
AVss  
Analog input  
AVRH  
Analog input  
AVRH  
907  
Chapter 44 A/D Converter  
7.Caution  
• Overall error  
Difference between an actual vale and a theoretical value, containing a zero transition error/full transition  
error/linearity error  
AVRH - AVSS  
1LSB’(Ideal value)  
=
[V]  
1024  
VOT’ (Ideal value)  
VFST’ (Ideal value)  
=
=
AVSS + 0.5LSB’  
AVRH - 1.5LSB’  
[V]  
[V]  
VNT - {1LSB’ × (N - 1) + 0.5LSB’}  
Overall error of digital output N =  
1LSB’  
V
: Voltage at which digital output transit from (N+1) to N  
NT  
Overall error  
3FF  
1.5LSB’  
3FE  
Actual conversion characteristics  
{1LSB (N-1)+0.5LSB}  
3FD  
004  
003  
002  
001  
VNT  
(Measurement  
value)  
Actual conversion characteristics  
Ideal characteristics  
0.5LSB’  
AVss  
Analog input  
AVRH  
908  
Chapter 45 D/A Converter  
1.Overview  
Chapter 45 D/A Converter  
1. Overview  
The D/A converter converts digital values to analog output values on an R-2R type conversion basis.  
Pin  
D/A converter  
Digital value  
Analog output  
2. Features  
Method  
: R-2R type conversion  
: 2 (Output: DA0 pin and DA1 pin)  
Quantity  
Conversion time : 0.45us (Typ) (Load capacitance = 20pF)  
2.0us (Typ) (Load capacitance = 100pF)  
Resolution  
: 10-bit resolution  
Output range  
: From AV (0V) to 1023/1024 x AV  
SS  
CC  
Interrupt  
Others  
: None  
: Power-down feature available (fixed 0 V output).  
Useful for saving current consumption when in sleep mode.  
909  
       
Chapter 45 D/A Converter  
3.Configuration  
3. Configuration  
Figure 3-1 Configuration Diagram  
D/A converter (0-1)  
Register number (:bit)  
DACR: bit 0  
DACR: bit 1  
Port  
function  
D/A  
DAE  
Data  
Control  
Pin  
0
1
D/A output disable (0 V output)  
D/A output enable  
0
1
DADR0  
DADR1  
DACR.DAE0 PFR28.6  
DACR.DAE1 PFR28.7  
DA0  
DA1  
DA0  
DA1  
PFR28: bit 6  
PFR28: bit 7  
0
1
General-purpose port output  
D/A output only  
2R  
DADR0/  
DADR1  
R
2R  
1
R
2R  
DA0/P28.6  
DA1/P28.7  
From Port  
Data register  
0
2R  
R
AVcc  
AVss  
Port read  
2R  
R
For a detailed description of the D/A pin circuit, see the chapter entitled “Basic Information”.  
Figure 3-2 Register List  
910  
 
Chapter 45 D/A Converter  
4.Registers  
4. Registers  
4.1 DADR: D/A Data Register  
The D/A Data Register sets the output voltage of the D/A converter.  
• DADR0(ch0): Address 0364 (Access: Byte, Half-word)  
H
• DADR1(ch1): Address 0366 (Access: Byte, Half-word)  
H
15  
14  
13  
12  
11  
10  
9
8
Bit  
-
-
-
-
-
-
-
-
-
-
-
-
DA9  
X
DA8  
X
Initial value  
Attributes  
Bit  
RX/W0  
7
RX/W0  
6
RX/W0  
5
RX/W0  
4
RX/W0  
3
RX/W0  
2
R/W  
1
R/W  
0
DA7  
X
DA6  
X
DA5  
X
DA4  
X
DA3  
X
DA2  
X
DA1  
X
DA0  
X
Initial value  
Attributes  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
(For the attributes, refer to the “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• The D/A Data Register is not initialized on a reset.  
• The setting is “000 ” - “3FF ”.  
H
H
4.2 DACR: D/A Control Register  
The D/A Control Register controls whether D/A converter output is enabled or disabled.  
• DACR(ch0/ch1): Address 0361 (Access: Byte)  
H
7
–
–
6
–
–
5
4
3
2
MD08  
0
1
DAE1  
0
0
DAE0  
0
bit  
–
–
–
–
–
–
Initial value  
Attributes  
RX, W0 RX, W0  
RX, W0  
RX, W0  
RX, W0  
R/W  
R/W  
R/W  
(For the attributes, refer to the “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• bit7-3: Undefined  
At write, always write “0”. At read, the read value is indeterminate.  
• bit0: D/A output control  
DAE0  
Operation  
0
1
D/A output disabled  
D/A output enabled  
• Enables a converted analog level to be output from the DA pin.  
(To place the DA0 pin in the output state, it is necessary to set PFR28.6=“1”.  
• The D/A output equals 0.0 V when the D/A output control bit is “0”.  
• bit1: D/A output control  
DAE1  
Operation  
0
1
D/A output disabled  
D/A output enabled  
• Enables a converted analog level to be output from the DA pin.  
(To place the DA1 pin in the output state, it is necessary to set PFR28.7=“1”.  
• The D/A output equals 0.0 V when the D/A output control bit is “0”.  
911  
 
Chapter 45 D/A Converter  
4.Registers  
• bit2: D/A 8-/10-bit mode control  
MD08  
Operation  
0
1
D/A resolution is 10 bits  
D/A resolution is 8 bits  
• In case MD08=’1’ the 8-bit value of DA7-DA0 (DADR[7:0]) is output.  
912  
Chapter 45 D/A Converter  
5.Operation  
5. Operation  
The operations of the D/A converter are described below.  
(5)  
(1)  
DADR0/-  
DADR1  
0A0h  
060h  
(3)  
(8)  
(9)  
DAE  
(7)  
DA0/DA1  
output level  
(4)  
(2)  
(6)  
(1) Digital value setting (software-programmable)  
(2) D/A conversion in progress  
(3) Output enabled (software-programmable)  
(4) Analog value output  
(5) Digital value rewrite (software-programmable)  
(6) D/A conversion in progress  
(7) Output level finalized  
(8) Output disabled (software-programmable)  
(9) Fixed 0 V output  
913  
 
Chapter 45 D/A Converter  
6.Setting  
6. Setting  
Table 6-1 Settings Needed to Use D/A  
Setting  
Procedure*  
Setting  
Setting Registers  
D/A Data Registers (DADR)  
Digital value settings  
Pin settings  
See 7.1.  
See 7.2.  
See 7.3.  
Port Function Register (PFR28.7, PFR28.6)  
D/A Control Registers (DACR)  
Output enabled  
*:For the setting procedure, refer to the section indicated by the number.  
Table 6-2 Settings Needed to Stop D/A Output  
Setting  
Procedure*  
Setting  
Setting Registers  
Output halted  
D/A Control Registers (DACR)  
See 7.3.  
*:For the setting procedure, refer to the section indicated by the number.  
914  
 
Chapter 45 D/A Converter  
7.Q & A  
7. Q & A  
7.1 Where should I set digital values?  
Write digital values to the D/A Data Registers (DADR[7:0] for 8-bit mode, DADR[9:0] for 10-bit mode).  
Access in a byte or halfword format.  
D/A conversion begins immediately on writing.  
7.2 How do I program the D/A pins for D/A output?  
DA Pin output setting  
Setting is accomplished by writing “1” to the output specification bits (PFR28.7 for DA1), (PFR28.6 for DA0).  
(Switch the port to DA pin output by software programming.)  
Pins  
Control bit location  
DA0 Output specification bit (DA0)  
DA1 Output specification bit (DA1)  
DA0 pin  
DA1 pin  
PFR28.6 = ‘1’  
PFR28.7 = ‘1’  
7.3 How do I enable or disable D/A output?  
Use the D/A output control bits (DACR.DAE0), (DACR.DAE1).  
Operations  
D/A output control bit (DAE)  
To disable output  
To enable output  
Set “0”.  
Set “1”.  
O V (= AVss) is output when disabled. This is functional even while in a stopped state.  
7.4 How do I activate a D/A conversion?  
A conversion begins on writing a digital value. See 7.1.  
7.5 What is the formula used to work out the value necessary to produce an expected  
voltage?  
Equation  
Value = [{V (Expected analog value) x 1024} / (AV )]  
CC  
To output 2.8 V from the pin with AV = 5.0V, for example.  
CC  
(2.8V x 1024) / 5.0V = 573.44 => Value = 573  
915  
 
Chapter 45 D/A Converter  
8.Caution  
8. Caution  
• The table below lists the output voltages of the D/A converter (in 10-bit resolution mode).  
DADR Settings  
D/A Converter Output Voltage Value  
000  
0V (AVss=0.0V)  
H
1/1024 x AV  
2/1024 x AV  
~
V
V
001  
002  
~
H
H
CC  
CC  
1021/1024 x AV  
1022/1024 x AV  
1023/1024 x AV  
V
V
V
3FD  
H
H
H
CC  
CC  
CC  
3FE  
3FF  
When stopped  
0V (Avss=0.0V)  
• The table below lists the output voltages of the D/A converte (in 8-bit resolution mode)r.  
DADR Settings  
D/A Converter Output Voltage Value  
00  
0V (AVss=0.0V)  
H
1/256 x AV  
2/256 x AV  
~
V
V
01  
02  
H
H
CC  
CC  
~
253/256 x AV  
254/256 x AV  
255/256 x AV  
V
FD  
H
H
H
CC  
CC  
CC  
V
V
FE  
FF  
When stopped  
0V (Avss=0.0V)  
• The conversion speed depends on the line load capacitance.  
Indicates the conversion speed of the D/A converter.  
Load  
Conversion  
Capacitance  
Speed (TYP)  
20pF  
0.45µs  
100pF  
2.0µs  
• Power supply  
• The power supply of the analog circuit in the D /A converter is AV  
.
CC  
• Use of a power supply within the limits of “Recommended Power Supply Operation Conditions” in the  
chapter entitled “2. Instruction for Users (Page No.3)” is recommended.  
916  
 
Chapter 46 Alarm Comparator  
1.Overview  
Chapter 46 Alarm Comparator  
1. Overview  
This chapter provides an overview of the Alarm Comparator (also called Under/Overvoltage De-  
tection), describes the register structure and functions, and describes the operation of the Alarm  
Comparator.  
2. Block Diagram  
Alarm comparator - analog part  
Alarm comparator - digital part  
AVDD  
RST  
OUT1  
CLKP  
D
Q
0.8 AVDD  
ALARM  
STOP  
CK  
PD  
OUT2  
D
Q
0.4 AVDD  
CK  
CLKP  
IRQ_AC  
Interrupt logic  
Figure 2-1 Alarmcomparator (simplified circuit)  
917  
     
Chapter 46 Alarm Comparator  
3.Alarm Comparator Control/Status Register (ACSR)  
3. Alarm Comparator Control/Status Register (ACSR)  
• ACSR0 (ch0): Address 01AD (Access: Byte)  
H
• ACSR1 (ch1): Address 01AF (Access: Byte)  
H
Bits  
4
Address  
ACSR0 0000 01ADH  
ACSR1 0000 01AFH  
7
6
5
3
2
1
0
Initial value  
011XXX00  
OV_EN UV_EN  
MD  
OUT2 OUT1 IRQ IEN  
PD  
B
R/W R/W R/W  
R
R
R/W R/W R/W  
Access  
Figure 3-1 Structure of Alarm comparator control/status register  
Bit 7: MD Mode select  
1
Fast mode enabled  
Slow mode enabled  
0
[Initial value]  
[Initial value]  
Bit 6: OV_EN Overvoltage Enable  
1
0
Interrupt enabled in case of overvoltage.  
No interrupt in case of overvoltage  
Bit 5: UV_EN Undervoltage Enable  
1
0
Interrupt enabled in case of undervoltage  
No interrupt in case of undervoltage.  
[Initial value]  
Bit 4: OUT2 synchronized output of Alarm comparator UV output.  
0
1
analog input voltage < 2/5 AVDD  
analog input voltage > 2/5 AVDD  
Bit 3: OUT1 synchronized output of Alarm comparator OV output.  
1
0
analog input voltage > 4/5 AVDD  
analog input voltage < 4/5 AVDD  
Bit 2: IRQ Interrupt bit.  
1
0
Under- or overvoltage condition detected  
Normal operation  
918  
 
Chapter 46 Alarm Comparator  
4.Operation Modes  
Bit 1: IEN Interrupt enable bit.  
1
0
Interrupt assertion enabled  
Interrupt assertion disabled  
[Initial value]  
[Initial value]  
Bit 0: PD Power down bit.  
1
0
Power down (analog part)  
Runmode (analog part)  
4. Operation Modes  
The alarm comparator circuit can operate in interrupt or polling mode. The internal interrupt logic will  
detect each interrupt event independent from setting of the IEN bit.  
4.1 Interrupt Mode (IEN=1)  
The following truth table describes the valid interrupt events  
Table 4-1 Valid interrupt events  
OUT2  
OUT1  
IRQ  
analog input voltage range  
1
1
1
0
1
0
Vin > 0.8 AVDD (overvoltage)  
0.4 AVDD < Vin < 0.8 AVDD  
(normal operation)  
0
0
1
Vin < 0.4 AVDD (undervoltage)  
The interrupt Bit IRQ will be set with the next positive transition of CLKP after detecting an interrupt event.  
If IEN=1 this will create an interrupt request to the CPU. In order to determine the reason for the asserted  
interrupt - if both interrupts are enabled - it is necessary to read the ACSR register immediately inside the  
interrupt service routine. OUT2 and OUT1 always contain the actual status of the comparator outputs, i.e.  
the interrupt trigger event will not be stored.  
4.2 Polling Mode (IEN=0)  
The IRQ register bit will be set by an active interrupt event and can be reset by writing to the ACSR  
register.The ACSR can be polled continuously in order to monitor the input voltage which is feed to the AC  
comparator inputs.  
4.3 Setting and Resetting of IRQ-Flagbit  
The IRQ bit of the ACSR register can be reset to zero by writing a “0” to it. Writing an “1” to the IRQ bit of  
ACSR register has no effect. IRQ can only be set to “1” by hardware, i.e. by the outputs of the comparator  
circuits. IRQ will remain active as long as an active interrupt status is detected, even if a “0” is written to it.  
A bitset command performed on the ACSR register will result in a RMW access on the R-Bus. Every read  
access during performing a RMW command will return a “1” for the IRQ flag to the CPU. That avoids any  
loss in detecting interrupt events due to software setting of IRQ-Flag Bit.  
919  
 
Chapter 46 Alarm Comparator  
4.Operation Modes  
4.4 Power Down Modes of the Alarm Comparator  
The alarm comparator circuit has the following power down modes:  
Table 4-2 Alarm Comparator power down modes  
STOP  
PD  
analog part  
digital part  
0
0
1
1
0
1
0
1
run mode  
run mode  
run mode  
power down mode  
power down mode  
power down mode  
power down mode  
power down mode  
Precaution: The outputs of the alarm comparator (analog parts) will remain undefined for at least 3 us  
after power on and also after reentering the runmode. You have to make sure whether the IRQ is correct  
set before enabling the alarm comparator interrupt source.  
920  
Chapter 47 LCD Controller  
1.Overview  
Chapter 47 LCD Controller  
1. Overview  
LCD allows display of up to 160 cells and selection of a duty cycle from 1/2, 1/3 and 1/4.  
LCD has many applications.  
Internal Divided Resistors  
AC Circuit  
or  
External Divided Resistors  
Common  
bit 1 bit 0  
bit 3 bit 2  
bit 7  
bit 6 bit 5  
bit 4  
Peripheral  
clock  
Segment  
VRAM1  
Sub-clock  
VRAM2  
VRAM19  
2. Features  
• Quantity: 1 (4 common x 40 segment)  
• Display: Up to 160 cells (for 1/4 duty cycle)  
• Duty cycle: Selectable from options: 1/2, 1/3 and 1/4.  
• Bias: Fixed at 1/3  
• Frame period: Selectable from four options. (For clock, peripheral clock or subclock is selectable.)  
• Driver: Built-in (for internal divided resistors), or external divided resistors can be connected to the V0 - V3  
pins.  
• Data memory: Built-in 20-byte data memory for display  
• Stop mode: Enable LCD display in the sub-stop mode.  
• Blank display: Selectable.  
• Pin: The SEG0-39 of COM0-4 pin usage can be switched between general and specialized purposes.  
• Other: External divided resistors can be also used to shut off the current when LCD is deactivated.  
921  
     
Chapter 47 LCD Controller  
3.Configuration  
3. Configuration  
Figure 3-1 Configuration Diagram  
LCD Controller  
CSS  
LCR0: bit7  
1
FP1,0  
0
LCDCMR  
COM0 PFR30.0  
LCR0: bit1,0  
Subclock  
Main clock  
:
:
MS1,0 LCR0: bit3,2  
LCDCMR  
0
0
1
1
0
1
0
1
FCLKP/(213 N) FCL-SUB/(23 N)  
FCLKP/(214 N) FCL-SUB/(24 N)  
FCLKP/(215 N) FCL-SUB/(25 N)  
COM3 PFR30.3  
0
0
1
1
0
1
0
1
Deactivate  
----0000  
00001111  
Initial value  
Setting  
0
1
General-purp. ports  
COM output  
1/2 duty cycle  
1/3 duty cycle  
1/4 duty cycle  
F
CLKP/(216 N) FCL-SUB/(26 N)  
From port data  
register  
COM0  
COM1  
Peripheral  
clock  
0
1
Timing  
Control Circuit  
Prescaler  
Sub  
clock  
COM2  
COM3  
V0  
V1  
V2  
V3  
Internal  
Divided  
Resistors  
AC Circuit  
VRAM10  
VRAM11  
VRAM12  
VRAM13  
VRAM14  
VRAM15  
VRAM16  
VRAM17  
VRAM18  
VRAM19  
VRAM0  
VRAM1  
VRAM2  
VRAM3  
VRAM4  
VRAM5  
VRAM6  
VRAM7  
SEG0  
SEG1  
SEG2  
VSEL  
LCR0: bit5  
0
1
Disconnect internal divided resistors.  
Connect internal divided resistors.  
VRAM8  
VRAM9  
SEG30  
SEG39  
1
LCEN  
LCR0: bit6  
Disable display in watch mode.  
Enable display in watch mode.  
0
1
0
From  
general-purpose  
port register  
Control Section  
BK LCR0: bit4  
Display  
0
1
SEG0 PFR35.0  
SEG16 PFR33.0  
SEG32 PFR31.0  
LCR1  
00 00000000 Initial value  
Setting  
Blank  
:
:
:
:
:
:
SEG7 PFR35.7  
SEG23 PFR33.7  
SEG39 PFR31.7  
11 11111111  
SEG8 PFR34.0  
SEG24 PFR32.0  
0
1
General-purp. port  
SEG output  
:
:
:
:
SEG15 PFR34.7  
SEG31 PFR32.7  
Note: For details on ports, refer to “Chapter 30 I/O Ports (Page No.431)” and “Chapter 3 MB91460 Series Basic  
Information (Page No.23)”.  
922  
 
Chapter 47 LCD Controller  
3.Configuration  
Figure 3-2 Register List  
923  
Chapter 47 LCD Controller  
4.Registers  
4. Registers  
4.1 LCR0: LCDC Control Register 0  
This register is used to select a frame period and its clock and the display mode, to enable/disable LCD display and  
the operation in the watch mode, and to control the drive power source.  
• LCR0: Address 0E9 (Access: Byte)  
H
7
6
LCEN  
0
5
VSEL  
0
4
BK  
1
3
2
1
FP1  
0
0
FP0  
0
bit  
CSS  
0
MS1  
0
MS0  
0
Initial value  
Attribute  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
(For attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)” chapter.)  
• bit7: Select the frame period generation clock  
CSS  
Operation  
0
1
Peripheral clock (CLKP)  
Subclock  
When the peripheral clock is selected, LCD does not operate if the main clock stops (that is, LCD is in the  
subclock mode in which the main clock stops, or in the sub-stop mode).  
• bit6: Enable operation in sub-stop  
LCEN  
Operation  
0
1
Disable LCD display in the sub-stop mode.  
Enable LCD display in the sub-stop mode.  
To enable LCD display, the frame period generation clock select bit (CCS) must be also set to “1”.  
• bit5: Control LCD drive power supply  
VSEL  
Operation  
0
1
Disconnect internal divided resistors.  
Connect internal divided resistors.  
To connect external divided resistors, the LCD drive power supply control bit (VSEL) must be set to “0”.  
• bit4: Select blanking  
BK  
0
Operation  
Enable LCD display.  
1
Disable (blank) LCD display.  
• bit3-2: Select a display mode  
MS1  
MS0  
Display mode  
0
0
1
1
0
1
0
1
Deactivate LCD.  
1/2 duty cycle output mode (Time division number: N=2, COM0-COM1)  
1/3 duty cycle output mode (Time division number: N=3, COM0-COM2)  
1/4 duty cycle output mode (Time division number: N=4, COM0-COM3)  
If the display mode select bit (MS[1:0]) is set to “00”, LCD Controller ceases to operate.  
A “L” level is output through common/segment pins.  
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Chapter 47 LCD Controller  
4.Registers  
• bit1-0: Frame period  
Frame period  
When peripheral clock is selected:  
FP1  
FP0  
When subclock is selected:  
13  
3
0
0
1
1
0
1
0
1
F
F
F
F
/(2 × N)  
F
F
F
F
/(2 × N)  
CLKP  
CLKP  
CLKP  
CLKP  
CL-SUB  
CL-SUB  
CL-SUB  
CL-SUB  
14  
4
/(2 × N)  
/(2 × N)  
15  
5
/(2 × N)  
/(2 × N)  
16  
6
/(2 × N)  
/(2 × N)  
F
Peripheral clock (CLKP) frequency  
Subclock frequency  
CLKP  
F
CL-SUB  
N
Time division number (Selected with the display mode select bits, MS1 and MS0.)  
Select an appropriate value in accordance with the frame frequency of your LCD panel.  
925  
Chapter 47 LCD Controller  
4.Registers  
4.2 VRAM: Data Memory for Display  
Memory area (VRAM) for setting display data  
• VRAM0 (SEG0, SEG1): Address 0EC (Access: Byte)  
H
• VRAM1 (SEG2, SEG3): Address 0ED (Access: Byte)  
H
• VRAM2 (SEG4, SEG5): Address 0EE (Access: Byte)  
H
• VRAM3 (SEG6, SEG7): Address 0EF (Access: Byte)  
H
• VRAM4 (SEG8, SEG9): Address 0F0 (Access: Byte)  
H
• VRAM5 (SEG10, SEG11): Address 0F1 (Access: Byte)  
H
• VRAM6 (SEG12, SEG13): Address 0F2 (Access: Byte)  
H
• VRAM7 (SEG14, SEG15): Address 0F3 (Access: Byte)  
H
• VRAM8 (SEG16, SEG17): Address 0F4 (Access: Byte)  
H
• VRAM9 (SEG18, SEG19): Address 0F5 (Access: Byte)  
H
• VRAM10 (SEG20, SEG21): Address 0F6 (Access: Byte)  
H
• VRAM11 (SEG22, SEG23): Address 0F7 (Access: Byte)  
H
• VRAM12 (SEG24, SEG25): Address 0F8 (Access: Byte)  
H
• VRAM13 (SEG26, SEG27): Address 0F9 (Access: Byte)  
H
• VRAM14 (SEG28, SEG29): Address 0FA (Access: Byte)  
H
• VRAM15 (SEG30, SEG31): Address 0FB (Access: Byte)  
H
• VRAM16 (SEG32, SEG33): Address 0FC (Access: Byte)  
H
• VRAM17 (SEG34, SEG35): Address 0FD (Access: Byte)  
H
• VRAM18 (SEG36, SEG37): Address 0FE (Access: Byte)  
H
• VRAM19 (SEG38, SEG39): Address 0FF (Access: Byte)  
H
7
6
5
4
3
2
1
0
bit  
D07  
X
D06  
X
D05  
X
D04  
X
D03  
X
D02  
X
D01  
X
D00  
X
Initial value  
Attribute  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
(For attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
Regardless of the operation of LCD Controller/V driver, RAM can be read and written any time.  
926  
Chapter 47 LCD Controller  
4.Registers  
• Correspondence between VRAM and Common/Segment Pins  
927  
Chapter 47 LCD Controller  
4.Registers  
4.3 LCR1: LCDC Control Register 1  
• LCR1H: Address 0EA (Access: Byte, Half-word, Word)  
H
15  
-
14  
-
13  
-
12  
-
11  
-
10  
-
9
SEGEN9  
0
8
SEGEN8  
0
bit  
-
-
-
-
-
-
Initial value  
Attribute  
-
-
-
-
-
-
R/W  
R/W  
(For attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• bit15-10: Undefined (Read: Indeterminate, Write: “0” is always written.)  
• bit9-8: Segment driver enable.  
Always set to “11 ” when LCD is used.  
B
• LCR1L: Address 0EB (Access: Byte, Half-word, Word)  
H
7
SEGEN7  
0
6
SEGEN6  
0
5
SEGEN5  
0
4
SEGEN4  
0
3
SEGEN3  
0
2
SEGEN2  
0
1
SEGEN1  
0
0
SEGEN0  
0
bit  
Initial value  
Attribute  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
(For attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• bit7-0: Segment driver enable.  
When LCD is used, always set this register to “11111111 ”.  
B
4.4 LCDCMR: Common Pin Switching Register  
• LCDCMR: Address 0E8 (Access: Byte, Half-word, Word)  
H
7
DTCH  
0
6
5
4
3
2
1
0
bit  
–
–
–
–
–
–
COMEN3 COMEN2 COMEN1 COMEN0  
0
0
0
0
Initial value  
Attribute  
R/W  
RX/WX  
RX/WX  
RX/WX  
R/W  
R/W  
R/W  
R/W  
(For attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• bit7: Analogue macro control.  
Always set to “0 ” when LCD is used.  
B
• bit6-4: Undefined (Read: Indeterminate, Write: “0” is always written.)  
• bit3-0: Common driver enable.  
Always set to “1111 ” when LCD is used.  
B
928  
Chapter 47 LCD Controller  
5.Operation  
5. Operation  
This section describes operation.  
5.1 LCD Controller/Driver (LCDC) Operation  
(1) Set values to the display data memory (VRAM) in advance.  
(2) Make necessary settings to each register.  
(3) When the frame period generation clock oscillates, LCD drive waveform is output through common/  
segment output pins (COM0 - COM3, SEG0 - SEG39).  
(4) More detailedly,  
VRAM contents are automatically read in synchronization with common signals to be output through  
segment output pins.  
(If the bit is set to “1”, the selected waveform is output through the segment output pins.  
If the bit is set to “0”, non-selected waveform is output through the segment output pins.)  
If the display mode is set to 1/2 duty cycle, non-selected waveform is output through the COM2 and  
COM3 pins. For the 1/3 duty cycle, the COM3 pin is used to output non-selected waveform.  
(5) This output waveform is a 2-frame AC waveform in accordance with the duty cycle setting, and drives  
LCD.  
(6) When MS[1:0] = “00” is used to deactivate LCD, a “L” level is output through both common and segment  
pins.  
(7) If LCD operation is enabled in the sub-stop mode (LCEN=“1”), LCD display is displayed.  
Note that frame period generation clock signals must be supplied at this time.  
(8) LCD display can be blanked by selecting “blank” (BK=“1”) in blanking selection.  
Note that non-selected waveform continues to be output.  
(9) When LCD deactivation (MS[1:0]=“00”) is selected with the display mode, LCD ceases to operate.  
5.2 1/2 Duty Cycle Output Waveform  
Only COM0 and COM1 outputs are used for LCD display. Neither COM2 nor COM3 output is used.  
• Example of 1/3 Bias Output Waveform  
LCD cells with the maximum voltage difference between common and segment outputs are lit.  
Table 5-1 Example of Data Memory Contents for display  
Contents of data memory for display  
Segment  
COM3 output  
COM2 output  
COM1 output  
COM0 output  
SEG 2n output  
-
-
-
-
0
0
0
1
SEG2n+1 output  
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Chapter 47 LCD Controller  
5.Operation  
V3  
V2  
V1  
V0  
COM0 output  
V3  
V2  
V1  
V0  
COM1 output  
COM2 output  
V3  
V2  
V1  
V0  
V3  
V2  
V1  
V0  
COM3 output  
SEG 2n output  
V3  
V2  
V1  
V0  
V3  
V2  
V1  
V0  
SEG 2n+1 output  
ON  
LCD cell corresponding to SEG 2n, COM0 output  
LCD cell corresponding to SEG 2n, COM1 output  
LCD cell corresponding to SEG 2n+1, COM0 output  
LCD cell corresponding to SEG 2n+1, COM1 output  
OFF  
ON  
OFF  
ON  
OFF  
ON  
OFF  
930  
Chapter 47 LCD Controller  
5.Operation  
5.3 1/3 Duty Cycle Output Waveform  
In the 1/3 duty cycle output mode, COM0, COM1 and COM2 outputs are used for LCD display. COM3 output  
is not used.  
• Example of 1/3 Bias Output Waveform  
LCD cells with the maximum voltage difference between common and segment outputs are lit.  
Table 5-2 Example of Data Memory Contents for Display  
Contents of data memory for display  
Segment  
COM3 output  
COM2 output  
COM1 output  
COM0 output  
SEG 2n output  
-
-
1
1
0
0
0
1
SEG2n+1 output  
931  
Chapter 47 LCD Controller  
5.Operation  
COM0 output  
V3  
V2  
V1  
V0  
COM1 output  
COM2 output  
COM3 output  
V3  
V2  
V1  
V0  
V3  
V2  
V1  
V0  
V3  
V2  
V1  
V0  
SEG 2n output  
V3  
V2  
V1  
V0  
SEG 2n+1 output  
V3  
V2  
V1  
V0  
LCD cell corresponding to SEG 2n, COM0 output  
LCD cell corresponding to SEG 2n, COM1 output  
ON  
OFF  
ON  
OFF  
ON  
LCD cell corresponding to SEG 2n, COM2 output  
LCD cell corresponding to SEG 2n+1, COM0 output  
OFF  
ON  
OFF  
ON  
LCD cell corresponding to SEG 2n+1, COM1 output  
LCD cell corresponding to SEG 2n+1, COM2 output  
OFF  
ON  
OFF  
932  
Chapter 47 LCD Controller  
5.Operation  
5.4 1/4 Duty Cycle Output Waveform  
In the 1/4 duty cycle output mode, COM0, COM1, COM2, and COM3 outputs are all used for LCD display.  
• Example of 1/3 Bias Output Waveform  
LCD cells with the maximum voltage difference between common and segment output are lit.  
Table 5-3 Example of Data Memory Contents for Display  
Contents of data memory for display  
Segment  
COM3 output  
COM2 output  
COM1 output  
COM0 output  
SEG 2n  
output  
0
1
0
0
SEG2n+1  
output  
0
1
0
1
COM0 output  
V3  
V2  
V1  
V0  
COM1 output  
COM2 output  
COM3 output  
SEG 2n output  
SEG 2n+1 output  
V3  
V2  
V1  
V0  
V3  
V2  
V1  
V0  
V3  
V2  
V1  
V0  
V3  
V2  
V1  
V0  
V3  
V2  
V1  
V0  
LCD cell corresponding to SEG 2n, COM0 output  
LCD cell corresponding to SEG 2n, COM1 output  
ON  
OFF  
ON  
OFF  
ON  
LCD cell corresponding to SEG 2n, COM2 output  
LCD cell corresponding to SEG 2n, COM3 output  
OFF  
ON  
OFF  
ON  
LCD cell corresponding to SEG 2n+1, COM0 output  
LCD cell corresponding to SEG 2n+1, COM1 output  
OFF  
ON  
OFF  
LCD cell corresponding to SEG 2n+1, COM2 output  
LCD cell corresponding to SEG 2n+1, COM3 output  
ON  
OFF  
ON  
OFF  
933  
Chapter 47 LCD Controller  
6.Setting  
6. Setting  
Table 6-1 Required Setting to Use LCD  
Setting  
procedure  
Setting  
Setting register *  
Common pin switching register (LCDCMR)  
LCD control register 1 (LCR1)  
Presetting  
–
See  
7.8 and 7.9  
Set divided resistors.  
LCD control register 0 (LCR0)  
Set ports  
Port function register (PFR)  
See 7.1  
See 7.2  
Set display data.  
Display data memory (VRAM)  
Select the frame period generation clock.  
Set a frame period.  
See 7.3  
LCD control register 0 (LCR0)  
Select a duty cycle. (Activation)  
Enable LCD display.  
See 7.4  
See 7.6  
* :For the setting procedure, refer to the section indicated by the number.  
Table 6-2 Required Setting to Disable LCD display  
Setting  
procedure  
Setting  
Setting register *  
Disable (blank) LCD display.  
LCD control register 0 (LCR0)  
See 7.6  
* :For the setting procedure, refer to the section indicated by the number.  
Table 6-3 Required Setting to Deactivate LCD  
Setting  
procedure  
Setting  
Setting register *  
Deactivate LCD.  
LCD control register 0 (LCR0)  
See 7.5  
*:For the setting procedure, refer to the section indicated by the number.  
Table 6-4 Required Setting to Enable LCD Display in Sub-Stop Mode  
Setting  
procedure  
Setting  
Setting register *  
Enable LCD display in the sub-stop mode.  
Select the frame period generation clock.  
Switch to subclock operation.  
See 7.7  
LCD control register 0 (LCR0)  
See 7.3  
See “Chapter 13 Clock Control (Page No.189)”.  
See “Chapter 10 Standby (Page No.155)”.  
–
–
Change to the stop mode.  
* :For the setting procedure, refer to the section indicated by the number.  
934  
 
Chapter 47 LCD Controller  
7.Q&A  
7. Q&A  
7.1 How do I specify pins as COM or SEG output pins?  
Use COM and SEG output settings.  
Software can switch ports to COM or SEG output ports.  
To do so, write “1” to the output designation bit (COM[3:0], SEG[39:0]).  
Pin  
Register  
Output designation bit  
COM0  
COM1  
COM2  
COM3  
SEG0  
(COM0)  
(COM1)  
(COM2)  
(COM3)  
(SEG0)  
Port function register PFR30[3:0]  
SEG1  
(SEG1)  
SEG2  
(SEG2)  
SEG3  
(SEG3)  
Port function register PFR35[7:0]  
Port function register PFR34[7:0]  
Port function register PFR33[7:0]  
Port function register PFR32[7:0]  
SEG4  
(SEG4)  
SEG5  
(SEG5)  
SEG6  
(SEG6)  
SEG7  
(SEG7)  
SEG8  
(SEG8)  
SEG9  
(SEG9)  
SEG10  
SEG11  
SEG12  
SEG13  
SEG14  
SEG15  
SEG16  
SEG17  
SEG18  
SEG19  
SEG20  
SEG21  
SEG22  
SEG23  
SEG24  
SEG25  
SEG26  
SEG27  
SEG28  
SEG29  
SEG30  
SEG31  
(SEG10)  
(SEG11)  
(SEG12)  
(SEG13)  
(SEG14)  
(SEG15)  
(SEG16)  
(SEG17)  
(SEG18)  
(SEG19)  
(SEG20)  
(SEG21)  
(SEG22)  
(SEG23)  
(SEG24)  
(SEG25)  
(SEG26)  
(SEG27)  
(SEG28)  
(SEG29)  
(SEG30)  
(SEG31)  
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Chapter 47 LCD Controller  
7.Q&A  
SEG32  
SEG33  
SEG34  
SEG35  
SEG36  
SEG37  
SEG38  
SEG39  
(SEG32)  
(SEG33)  
(SEG34)  
(SEG35)  
(SEG36)  
(SEG37)  
(SEG38)  
(SEG39)  
Port function register PFR31[7:0]  
936  
Chapter 47 LCD Controller  
7.Q&A  
7.2 How do I set VRM?  
The following tables show the relationship between pins and the bit positions of VRAM(n). (n=0 to 19)  
Table 7-1 1/2 duty cycle  
Pin  
SEG 2n  
SEG 2n+1  
COM1  
bit 1  
Bit 5  
COM0  
bit 0  
Bit 4  
Table 7-2 1/3 duty cycle  
pin  
SEG 2n  
SEG 2n+1  
COM2  
bit 2  
Bit 6  
COM1  
COM0  
bit 0  
Bit 4  
bit 1  
Bit 5  
Table 7-3 1/4 duty cycle  
pin  
SEG 2n  
SEG 2n+1  
COM3  
bit 3  
bit 7  
COM2  
COM1  
COM0  
bit 0  
Bit 4  
bit 2  
Bit 6  
bit 1  
Bit 5  
(Non-selected waveform is output through the pins other than the above.)  
Example: 1/4 duty cycle  
When “1” is set to the bit6 of VRAMn, selected waveform is output through the SEG2n+1 of COM2.  
If a bit is set to “0”, non-selected waveform is output through the corresponding pin.  
7.3 How do I set a frame period?  
Use the frame period generation clock select bit (LCR0.CSS) and the frame period bit (LCR0.FP[1:0]). The  
following settings are available:  
Selected value  
Frame period  
Frame period generation clock  
select bit (CSS)  
Frame period bit  
(FP[1:0])  
13  
Set to “0”.  
Set to “0”.  
Set to “0”.  
Set to “0”.  
Set to “1”.  
Set to “1”.  
Set to “1”.  
Set to “1”.  
Set to “00”.  
Set to “01”.  
Set to “10”.  
Set to “11”.  
Set to “00”.  
Set to “01”.  
Set to “10”.  
Set to “11”.  
Peripheral clock (F  
)/(2 × N)  
CLKP  
CLKP  
CLKP  
CLKP  
14  
Peripheral clock (F  
Peripheral clock (F  
Peripheral clock (F  
Subclock (F  
)/(2 × N)  
15  
)/(2 × N)  
16  
)/(2 × N)  
3
)/(2 × N)  
CL-SUB  
4
Subclock (F  
Subclock (F  
Subclock (F  
)/(2 × N)  
CL-SUB  
CL-SUB  
CL-SUB  
5
)/(2 × N)  
6
)/(2 × N)  
N (Time division number) = MS[1:0] value + “1”  
Set an appropriate frame period that corresponds to the frame frequency of your LCD panel.  
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Chapter 47 LCD Controller  
7.Q&A  
7.4 How do I set a duty cycle?  
Use the display mode select bit (LCR0.MS[1:0]).  
Display mode select bit  
(MS[1:0])  
Controlled operation  
N (Time division number)  
To deactivate LCD (Pin output: “L”)  
To set the 1/2 duty cycle output mode  
To set the 1/3 duty cycle output mode  
To set the 1/4 duty cycle output mode  
Set to “00”.  
Set to “01”.  
Set to “10”.  
Set to “11”.  
N/A  
2
3
4
The display mode select bit also serves as an operation start/stop control bit.  
7.5 How do I control starting and stopping of LCD?  
Use the display mode select bit (LCR0. MS[1:0]) to control start and stop of operation.  
See (4).  
7.6 How do I enable or disable LCD display?  
Use either of the following methods:  
• Use the blanking select bit (LCR0. BK).  
Controlled operation  
To enable LCD display  
Blanking select bit (BK)  
Set to “0”.  
Set to “1”.  
To disable (blank) LCD display  
(Non-selected waveform is output through segment pins.)  
• The LCD display can be blanked by using the display mode select bit (LCR0. MS[1:0]) to select LCD  
deactivation.  
Controlled operation  
Display mode select bit (MS[1:0])  
Set to “00”.  
To deactivate LCD  
(A “L” level is output through common and segment pins.)  
7.7 How do I enable LCD display even in the sub-stop mode?  
Use the sub-stop operation enable bit (LCR0. LCEN).  
Frame period  
generation clock  
select bit (CSS)  
Sub-stop operation enable bit  
(LCEN)  
Controlled operation  
To disable LCD display during sub-stop  
To enable LCD display during sub-stop  
–
Set to “0”.  
Set to “1”.  
Set to “1”.  
To enable LCD display when the main clock stops and the  
subclock operates  
Set to “1”.  
–
7.8 How do I select internal or external divided resistors?  
Use the LCD drive power supply control bit (LCR0. VSEL).  
Controlled operation  
To use external divided resistors  
(Internal divided resistors disconnected)  
LCD drive power supply control bit (VSEL).  
Set to “0”.  
To use internal divided resistors  
(Internal divided resistors connected)  
Set to “1”.  
938  
Chapter 47 LCD Controller  
7.Q&A  
7.9 How do I select internal or external divided resistors?  
• When using internal divided resistors:  
V3  
V
V
V
V
3
2
1
0
R
R
R
V2  
V1  
V0  
N-ch  
LCDC operation  
enabled  
• When using external divided resistors:  
The LCD driving voltage can be generated by connecting external divided resistors to the LCD drive power  
supply pins (V0 to V3).  
VR  
V3  
V
V
V
V
3
2
1
0
RX  
RX  
RX  
R
R
R
V2  
V1  
V0  
N-ch  
LCDC operation  
enabled  
To avoid the effect of internal divided resistors, the resistors must be disconnected by setting “0” to the LCD  
drive power supply control bit (LCR0.VSEL).  
7.10 How do I use external divided resistors to shut off the current when LCD is  
deactivated?  
The V0 pin is internally connected to Vss (GND) via a transistor. For this reason, the current generated on  
deactivating LCD controller can be shut off by connecting external divided resistors to the V0 pin on the Vss  
side. To shut off the current, use the display mode select bit (MS[1:0]= “00”).  
939  
Chapter 47 LCD Controller  
8.Caution  
8. Caution  
• To access VRAM, be sure to use byte-by-byte access.  
• Switching the frame period generation clocks:  
Frame period generation clocks (LCR0:CSS) can be switched even during LCD display. However, switching  
may cause some screen flicker. To avoid such flicker, be sure to set the blanking select bit (LCR0:BK) to “1”  
(blank display) before switching.  
• Depending on your LCD, different external divided resistors are used. Use appropriate resistor values.  
• When the display mode is set to 1/2 duty cycle, non-selected waveform is output through the COM2 and  
COM3 pins. For 1/3 duty cycle, the COM3 pin is used to output non-selected waveform.  
• Inappropriate selection or setting of frame period generation clock (CSS), LCD drive power supply control  
(VSEL), duty cycle (MS[1:0]) and frame period (FP[1:0]) results in inappropriate LCD display.  
• LCD display is disabled in the main stop mode. To enable LCD display in the stop mode, use the sub-stop  
mode. (See 6 “Setting procedure”.)  
940  
 
Chapter 48 Clock Monitor  
1.Overview  
Chapter 48 Clock Monitor  
1. Overview  
The Clock Monitor is a macro that outputs internal clock signals to a terminal to externally monitor them. The Clock  
Monitor provides a function to divide the frequency of a clock signal before it outputs to the terminal, thus allowing the  
clock signal to be used as an event at which external circuits act in synchronization with a MCU function.  
MONCLK  
Terminal  
Internal clocks  
Prescaler  
Selector  
2. Features  
• Format: Divide an internal clock signal to output it to a terminal (MONCLK).  
• Channel: 1  
• Division ratios: CLK/1, CLK/2, CLK/3, ..., CLK/16  
• Glitch free output enable  
• Programmable mark level (output “L” or “H” before enabling the clock output)  
• Interrupt: None  
941  
       
Chapter 48 Clock Monitor  
3.Configuration  
3. Configuration  
Figure 3-1 Configuration Diagram  
Clock Monitor  
CMCFG  
CMSEL3:0  
0000 Disable clock monitor output  
Others  
Enable clock monitor output  
Prescaler  
Selector  
MONCLK  
Internal clocks  
CMCFG  
CMSEL3:0  
0000 Disable clock monitor output  
CMCFG bit 7-4  
Clock Output  
Frequency  
Clock Output  
Frequency  
Main oscillation before CSV  
Sub oscillation before CSV  
RC oscillation  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
CMPRE3:0  
CMPRE3:0  
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
φ/1  
φ/2  
φ/3  
φ/4  
φ/5  
φ/6  
φ/7  
φ/8  
φ/9  
φ/10  
φ/11  
φ/12  
φ/13  
φ/14  
φ/15  
φ/16  
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
1
0
1
0
1
Sub clock (after SCKS)  
Main oscillation after CSV  
Sub oscillation after CSV  
Clock modulator output to C-Unit  
Clock modulator observer output  
PLL output after 1/g  
PLL output after 1/m  
PLL output after 1/c  
PLL input after 1/n  
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
0
1
1
CLKB  
CLKP  
CLKT  
Figure 3-2 Register List  
942  
 
Chapter 48 Clock Monitor  
4.Register  
4. Register  
4.1 Clock Monitor Configuration Register  
A register for output settings of an internal clock signal  
• CMCFG: Address 04AF (Access: Byte)  
H
7
CMPRE3  
0
6
CMPRE2  
0
5
CMPRE1  
0
4
CMPRE0  
0
3
CMSEL3  
0
2
CMSEL2  
0
1
CMSEL1  
0
0
CMSEL0  
0
bit  
Initial value  
Attributes  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
(For attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• bit7-4: Select an output frequency prescaler  
CMPRE3  
CMPRE2  
CMPRE1  
CMPRE0  
Clock Frequency Output to the MONCLK pin  
Source clock (selected by CMSEL) divided by 1 (Initial)  
Source clock (selected by CMSEL) divided by 2  
Source clock (selected by CMSEL) divided by 3  
Source clock (selected by CMSEL) divided by 4  
Source clock (selected by CMSEL) divided by 5  
Source clock (selected by CMSEL) divided by 6  
Source clock (selected by CMSEL) divided by 7  
Source clock (selected by CMSEL) divided by 8  
Source clock (selected by CMSEL) divided by 9  
Source clock (selected by CMSEL) divided by 10  
Source clock (selected by CMSEL) divided by 11  
Source clock (selected by CMSEL) divided by 12  
Source clock (selected by CMSEL) divided by 13  
Source clock (selected by CMSEL) divided by 14  
Source clock (selected by CMSEL) divided by 15  
Source clock (selected by CMSEL) divided by 16  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Specifies the frequency of a clock signal output to a clock monitor terminal.  
• bit3-0: Select an output frequency prescaler  
CMSEL  
CMSEL2  
CMSEL1  
CMSEL0  
Clock Source Output to the MONCLK pin  
MONCLK output disabled (high impedance) (Initial)  
Main oscillation before clock supervisor  
Sub oscillation before clock supervisor  
RC oscillation  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Sub clock (after sub clock selector SCKS)  
Main oscillation after clock supervisor (MCLK_OUT)  
Sub oscillation after clock supervisor (SCLK_OUT)  
Clock modulator output to Clock Control  
Clock modulator observer output  
PLL output after 1/g divider (Auto Gear)  
PLL output after 1/m divider (PLL output)  
PLL output after 1/c divider (CAN clock)  
PLL input after 1/n divider (PLL feedback)  
CLKB  
CLKP  
CLKT  
943  
   
Chapter 48 Clock Monitor  
4.Register  
• CSCFG: Address 04AEh (Access: Byte)  
7
6
5
4
3
2
1
0
bit  
EDSUEN PLLLOCK RCSEL MONCKI  
CSC3  
CSC2  
CSC1  
CSC0  
Initial value (INIT pin  
input, watchdog reset)  
0
X
0
0
0
0
0
0
Initial value  
(software reset)  
X
X
R
X
X
X
X
X
X
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• bit4: Clock Monitor MONCLK inverter  
MONCKI  
Function  
MONCLK mark level is low [Initial value]  
MONCLK mark level is high  
0
1
• Other bits7-5, bits3-0  
Not belonging to clock monitor operation. See chapter “CSCFG: Clock Source Configuration Register (Page No.196)”  
about information on the additional functions of this register.  
944  
Chapter 48 Clock Monitor  
5.Operation  
5. Operation  
The following diagram shows the output waveforms of the Clock Monitor.  
(1) The MONCLK pin is in high impedance state.  
(2) CMSEL is set from “0000” (no clock selected) to the selected (and prescaled) clock.  
(3) The MONCLK pin changes to output “L” status (output “H” if MONCKI is set to ‘1’) for one period of the  
internal (prescaled) clock.  
(4) After one period of the selected (and prescaled) internal clock MONCLK outputs the selected (and  
prescaled) internal clock.  
(5) CMSEL is set from the selected clock to “0000” (no clock selected).  
(6) The MONCLK pin changes to output “L” status (output “H” if MONCKI is set to ‘1’) for one period of the  
internal (prescaled) clock.  
(7) The MONCLK pin switches to high impedance state.  
945  
 
Chapter 48 Clock Monitor  
6.Settings  
6. Settings  
Table 6-1 Settings for Using Clock Monitor  
Setting  
Procedure*  
Settings  
Set a prescaler value  
Setting Registers  
Clock Monitor Prescaler  
(CMCFG.CMPRE[3:0])  
See 7.1  
See 7.1  
See 7.1  
Clock Monitor Selection  
(CMCFG.CMSEL[3:0])  
Set a source clock  
Clock Monitor Inverter  
(CSCFG.MONCKI)  
Change the mark level  
See 7.2  
Clock Monitor Selection  
(CMCFG.CMSEL[3:0])  
Enable clock monitor output.(MONCLK)  
See 7.3  
*:For each setting procedure, refer to an appropriate section.  
7. Q&A  
7.1 How do I set an output terminal (MONCLK)?  
Use the Clock Monitor Selection bits (CMCFG.CMSEL[3:0])  
Operation  
CMCFG.CMSEL[3:0]  
Set to the appropriate clock (!= “0000”)  
To set an output terminal (MONCLK)  
7.2 How do I select an output frequency?  
Use the Output Frequency Select bit (CMCFG.CMPRE[3:0]).  
Output Frequency (Example)  
CLKP=32MHz CLKP=40MHz  
Clock Division  
Ratio  
Frequency Prescaler  
(CMCFG.CMPRE[3:0])  
1/2  
1/3  
16.0 MHz  
10.7 MHz  
8.0 MHz  
4.0 MHz  
2.1 MHz  
2.0 MHz  
20.0 MHz  
13.3 MHz  
10.0 MHz  
5.0 MHz  
2.7 MHz  
2.5 MHz  
Set to “0001”.  
Set to “0010”.  
Set to “0011”.  
Set to “0111”.  
Set to “1110”.  
Set to “1111”.  
1/4  
1/8  
1/15  
1/16  
7.3 How do I enable/disable clock monitor output?  
Use the Output Enable bit (CMCFG.CMSEL[3:0]).  
Operation  
Output Enable Bit (CMCFG.CMSEL[3:0])  
Set to “0000”.  
To disable clock monitor output  
(To set the terminal to the Hi-z status)  
Enable clock monitor output.  
Set to “0001”-”1111”.  
946  
   
Chapter 48 Clock Monitor  
8.Caution  
8. Caution  
Due to the glitch free switching mechanism it is necessary to follow these rules when switching the clock  
source (CMCFG3:0) or the prescaler ratio (CMPRE3:0):  
- The CMPRE3:0 registers can only be written if the CMCFG3:0 registers are currently 0x0.  
- The CMPRE3:0 registers can only be written if the CMCFG3:0 registers are written to 0x0 within the same  
write access.  
- Between 2 write accesses to CMPRE/CMCFG there must be at least 2 cycles of the divided monitor clock.  
947  
 
Chapter 48 Clock Monitor  
8.Caution  
948  
Chapter 49 Real-Time Clock  
1.Overview  
Chapter 49 Real-Time Clock  
1. Overview  
Real-time Clock (RTC) continues to count elapsed time even in the STOP mode to provide the current real  
time (HH/MM/SS) based on main oscillation (4MHz), sub oscillation (32kHz) or RC oscillation (~100kHz).  
This allows precise time counting without a return from an interrupt during stand by periods.  
Sub-Second  
Registers  
Reload  
Counter  
1/2  
21 Bit  
Down Counter  
Second Minute Hour  
Oscillation  
clock  
Update  
Second Minute Hour  
2. Features  
• Information: Time count (HH/MM/SS). (This clock continues to operate even in the STOP mode.)  
• Operational on main clock (4MHz), sub clock (32kHz) or RC clock (~100kHz)  
• Quantity: 1  
• Time unit: Clock divided by 2  
• Operation clock:  
•
•
For register access: CLKP  
For time count: Mainclock, Subclock, RC clock  
• Time: Initial setting and adjustment are possible.  
• Interrupt: Interrupts can be generated at any of the five intervals: 1 half-second, 1 second, 1 minute, 1 hour  
and 1 day.  
• Others: By changing the value of the sub-second register, interrupts can be generated at any interval (from  
short to long).  
949  
     
Chapter 49 Real-Time Clock  
3.Configuration  
3. Configuration  
Figure 3-1 Configuration Diagram  
Real-Time Clock  
WTBR value = 1/2 second  
(Initial value indeterminate)  
WTBR  
INTE4 WTCER: bit9  
RUN WTCR: bit 3  
Read only  
Disable interrupts  
0
1
Enable interrupts  
0
RTC inactive  
Reload  
1
RTC active  
Every half second  
INT4 WTCER: bit0  
0
1
Clear interrupt requests  
0
Prescaler: 1/2  
21 Bit Counter  
Disable  
1
Oscillation  
Read: 1=Interrupt request has been made  
Every second  
0
1
INT0 WTCR: bit8  
Clear interrupt requests  
0
1
Disable  
Read: 1=Interrupt request has been made  
ST WTCR: bit 0  
INTE0 WTCR: bit9  
0
Stop after reset  
Start  
Disable interrupts  
0
1
1
Enable interrupts  
Every minute  
INT1 bbit100  
0
RTC  
interrupt  
(#132)  
W
T
C
C
R
:
1
OR  
Clear interrupt requests  
0
1
Disable  
Read: 1=Interrupt request has been made  
Every hour  
INT2  
0
1
T
C
R
:
bit122  
INTE1
T
C
R
:
bit111  
Clear interrupt requests  
0
1
0
0
1
Disable interrupts  
Enable interrupts  
Disable  
Every 24 hour (Everyday)  
INT3  
Read: 1=Interrupt request has been made  
1
T
C
R
:
bit144  
0
1
Clear interrupt requests  
INTE2
T
C
C
R
:
bbit133  
Disable  
Read: 1=Interrupt request has been made  
0
1
Disable interrupts  
Enable interrupts  
INTE3 WTCR: bit15  
Hour Counter  
Minute Counter  
0
1
Disable interrupts  
Second Counter  
Enable interrupts  
Overflow  
Overflow  
Overflow  
OR  
WTHR (W)  
WTHR (R)  
Hour  
WTMR (W)  
WTSR(W)  
UPDT WTCR: bit 2  
WTMR (R)  
Minute  
WTSR(R)  
Second  
0
1
No impact on operation  
Update  
Figure 3-2 Register List  
Note: For ICR registers and interrupt vectors, refer to “Chapter 24 Interrupt Control (Page No.311)”.  
950  
 
Chapter 49 Real-Time Clock  
4.Registers  
4. Registers  
4.1 WTCR: RTC Control Register  
This register is used to control behavior of the Real-time Clock module.  
• WTCR: Address 04A2  
(Access: Byte, Half-word)  
H
15  
14  
13  
12  
11  
10  
9
8
bit  
INTE3  
INT3  
INTE2  
INT2  
INTE1  
INT1  
INTE0  
INT0  
Initial  
value  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
When reset  
Attribute  
R/W  
R(R1),W  
R/W  
R(R1),W  
R/W  
R(R1),W  
R/W  
R(R1),W  
7
6
5
4
–
3
2
1
–
0
bit  
Reserved  
Reserved  
Reserved  
RUN  
UPDT  
ST  
Initial  
value  
0
0
0
–
0
0
–
X
0
0
0
–
0
0
–
X
When reset  
Attribute  
R/W0  
R/W0  
R/W0  
RX/WX  
R/WX  
R(R0)/W  
RX/WX  
R/W  
(For attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• bit15: Enable interrupt requests at 1-day intervals  
INTE3  
Operation  
0
1
No interrupt requests  
Generate interrupt requests at 1-day (24 hour) intervals.  
When the hour counter overflows, this flag is set to “1”.  
• bit14: 1-day interrupt request flag  
Status  
INT3  
Read  
Write  
0
1
No interrupt requests  
Clear the flag.  
Generate interrupt requests at 1-day (24 hour)  
intervals.  
Writing does not affect the operation.  
• bit13: Enable interrupt requests at 1-hour intervals  
INTE2  
Operation  
0
1
No interrupt requests  
Generate interrupt requests at 1-hour intervals.  
When the minute counter overflows, this flag is set to “1”.  
• bit12: 1-hour interrupt request flag  
Status  
INT2  
Read  
Write  
0
1
No interrupt requests  
Clear the flag.  
Writing does not affect the operation.  
Generate interrupt requests at 1-hour intervals.  
• bit11: Enable interrupt requests at 1-minute intervals  
INTE1  
Operation  
0
1
No interrupt requests  
Generate interrupt requests at 1-minute intervals.  
951  
 
Chapter 49 Real-Time Clock  
4.Registers  
When the minute counter overflows, this flag is set to “1”.  
• bit10: 1-minute interrupt request flag  
Operation  
INT1  
Read  
Write  
0
1
No interrupt requests  
Clear the flag.  
Writing does not affect the operation.  
Generate interrupt requests at 1-minute intervals.  
• bit9: Enable interrupt requests at 1-second intervals  
INTE0  
Operation  
0
1
No interrupt requests  
Generate interrupt requests at 1-second intervals.  
When the 21 bit down counter is set to “0”, this flag is set to “1”.  
• bit8: 1-second interrupt request flag  
Status  
INT0  
Read  
Write  
0
1
No interrupt requests  
Clear the flag.  
Writing does not affect the operation.  
Generate interrupt requests at 1-second intervals.  
• bit7-5: Reserved  
Be sure to write “0”. The read value is the value written.  
• bit4: Undefined  
Writing does not affect the operation. The read value is indeterminate.  
• bit3: Operation status  
RUN  
Status  
0
1
The Real-time Clock module is inactive.  
The Real-time Clock module is active.  
• bit2: Update  
UPDT  
Status/Operation  
0
The update has been completed. (Writing “0” does not affect the operation.)  
Update the hour/minute/second counters with the values of the hour/minute/second registers,  
respectively.  
1
Before writing “1” to the update bit (UPDT), the hour/minute/second registers must be set to the values with  
which to update the hour/minute/second counters. The hour/minute/second registers are updated on  
reloading to the 21 bit down counter.  
• bit1: Undefined  
Writing does not affect the operation. The read value is indeterminate.  
• bit0: Start  
ST  
Operation  
The Real-time Clock module stops to operate, and the 21 bit down counter and the hour/minute/second  
counters are cleared.  
0
The settings of the hour/minute/second registers are loaded to the hour/minute/second counters, and the  
Real-time Clock module starts to operate.  
1
Application Note: The Sub-second register of the RTC module stores the reload value for the 21bit  
prescaler. This value is reloaded after the reload counter reaches "0". When modifying all three bytes, make  
sure the reload operation will not be performed in between the write instructions. Otherwise the 21-bit  
prescaler loads the incorrect value of the combination of new data and old data bytes. It is generally  
952  
Chapter 49 Real-Time Clock  
4.Registers  
recommended that the Sub-Second register is updated while the ST bit is "0".  
However, if this update is done immediately after an RTC second interrupt there should be enough time to  
securely modify the registers until the next reload operation (next second interrupt) even if ST is not set to  
"0" and the module is in operation.  
When updating the registers by using the ST bit the following must be taken into account:  
The new value is written into the registers with the rising edge of the RUN bit. This RUN bit is clocked by the  
RTC clock (32 kHz, 100kHz or 4 MHz depending on device and mode). To make sure that the update is  
done properly, write the new values into the registers, set ST to 0, wait for the RUN bit to go low and then  
start the circuit again by setting ST to 1. RUN will go low at the second rising edge of the RTC clock after ST  
has been set to 0. It will rise again at the half second rising edge of RTC clock after ST has been set to 1. If  
this operation is to be done several times directly after each other, wait for RUN to go to high before setting  
ST to low again.  
• WTCER: Address 04A1  
(Access: Byte)  
H
7
–
6
–
5
–
4
–
3
–
2
–
1
0
bit  
INTE4  
INT4  
Initial  
value  
–
–
–
–
–
–
–
–
0
0
–
–
–
–
0
0
When reset  
Attribute  
RX/WX  
RX/WX  
RX/WX  
RX/WX  
RX/WX  
RX/WX  
R/W  
R(R1),W  
(For attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
• bit7-2: Undefined  
Writing does not affect the operation. The read value is indeterminate.  
• bit1: Enable interrupt requests at half-second (500ms) intervals  
INTE4  
Operation  
0
1
No interrupt requests  
Generate interrupt requests at half-second (500 ms) intervals.  
When the hour counter overflows, this flag is set to “1”.  
• bit0: half-second (500ms) interrupt request flag  
Status  
Clear the flag.  
INT4  
Read  
Write  
0
1
No interrupt requests  
Generate interrupt requests at half-second (500 ms)  
intervals.  
Writing does not affect the operation.  
953  
Chapter 49 Real-Time Clock  
4.Registers  
4.2 WTBR: Sub-Second Registers  
These registers are used to hold values to be reloaded to the 21 bit down counter.  
• WTBR0: Address 04A5 (Access: Byte, Half-word, Word)  
H
• WTBR1: Address 04A6 (Access: Byte, Half-word, Word)  
H
• WTBR2: Address 04A7 (Access: Byte, Half-word, Word)  
H
WTBR0  
7
6
5
4
D20  
X
3
D19  
X
2
D18  
X
1
D17  
X
0
D16  
X
bit  
–
–
–
–
–
–
–
–
–
Initial value  
Unchanged Unchanged Unchanged Unchanged Unchanged When reset  
RX/WX  
RX/WX  
RX/WX  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
WTBR1  
7
D15  
X
6
D14  
X
5
D13  
X
4
D12  
X
3
D11  
X
2
D10  
X
1
D9  
X
0
D8  
X
bit  
Initial value  
Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged When reset  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
WTBR2  
7
D7  
X
6
D6  
X
5
D5  
X
4
D4  
X
3
D3  
X
2
D2  
X
1
D1  
X
0
D0  
X
bit  
Initial value  
Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged When reset  
R/W R/W R/W R/W R/W R/W R/W R/W Attribute  
(For attributes, refer to “Meaning of Bit Attribute Symbols (Page No.10)”.)  
The sub-second registers, WTBR, holds values to be reloaded to the 21 bit down counter. When the 21 bit  
down counter value becomes “0”, the settings of WTBR are reloaded to the 21 bit down counter.  
(See “8. Caution (Page No.961)”.)  
Remark: The reload value to be set in the sub-second registers corresponds to the time for half a second. One  
second is reached after counting twice the reload value set in WTBR.  
(See “7.1 How do I set the count period of 1 second? (Page No.959)”.)  
954  
Chapter 49 Real-Time Clock  
4.Registers  
4.3 WTHR/WTMR/WTSR: Hour/Minute/Second Registers  
These registers hold time information (HH/MM/SS) for Real-time Clock.  
• WTHR (Hour register): Address 04A8  
(Access: Byte, Half-word)  
H
• WTMR (Minute register): Address 04A9  
(Access: Byte, Half-word)  
H
• WTSR (Second register): Address 04AA (Access: Byte, Half-word)  
H
WTHR  
7
6
5
4
H4  
X
3
H3  
X
2
H2  
X
1
H1  
X
0
H0  
X
bit  
–
–
–
–
–
–
–
–
–
Initial value  
Unchanged Unchanged Unchanged Unchanged Unchanged When reset  
RX/WX  
RX/WX  
RX/WX  
R,W  
R,W  
R,W  
R,W  
R,W  
Attribute  
WTMR  
7
6
5
M5  
X
4
M4  
X
3
M3  
X
2
M2  
X
1
M1  
X
0
M0  
X
bit  
–
–
–
–
–
–
Initial value  
Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged When reset  
RX/WX  
RX/WX  
R,W  
R,W  
R,W  
R,W  
R,W  
R,W  
Attribute  
WTSR  
7
6
5
S5  
X
4
S4  
X
3
S3  
X
2
S2  
X
1
S1  
X
0
S0  
X
bit  
–
–
–
–
–
–
Initial value  
Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged When reset  
R,W R,W R,W R,W R,W R,W Attribute  
RX/WX  
RX/WX  
• The values written to the hour/minute/second registers are the initial values to be loaded to the hour/  
minute/second counters.  
By setting “1” to the update bit (WTCR.UPDT) or the start bit (WTCR.ST), the hour/minute/second  
register values are written to the hour/minute/second counters.  
• The hour/minute/second counter values are saved to the hour/minute/second registers every time when  
the second counter overflows, that is, at intervals of one minute. When the hour/minute/second counters  
are read, the saved count values, not written ones, are read.  
• The hour/minute/second registers consist of two separate sets of registers: one for reading and the other  
for writing.  
(See “8. Caution (Page No.961)”.)  
955  
Chapter 49 Real-Time Clock  
5.Operation  
5. Operation  
This section describes Real-time Clock operation.  
(1) (4)  
(19)  
(20)  
ST  
reload value  
0000 h  
21 bit down counter  
(8)  
(9)  
(6)  
(2)  
Clear  
(10)  
Half  
Second  
59S  
S
(5)  
Second  
(10)  
(11)  
(2)  
Clear  
(20)  
Hour/  
Minute/  
Second  
counters  
59M  
23H  
Minute  
M
(5)  
(11)  
(20)  
(20)  
(2)  
(2)  
Clear  
Clear  
(12)  
H
Hour  
(5)  
WTSR  
WTMR  
WTHR  
(3) Hour/Minute/Second register values  
(3) Sub-second values  
(7)  
WTBR(0-2)  
RUN  
(20)  
Other circuits are stopped  
(14)  
STOP  
(17)  
(1)  
(2)  
(3)  
The start bit (ST) is set to “1” and then “0”. (Register initialization operation)  
This (ST=“0”) resets to 0 and stops the 21 bit down counter and the hour/minute/second timers.  
• The software writes hour, minute, and second values to the hour/minute/second registers, WTHR/  
WTMR/WTSR.  
• The software writes the appropriate values to the sub-second registers, WTBR0/WTBR1/WTBR2.  
• The interrupt request bits (INT0, INT1, INT2, INT3 and INT4) are initialized, and the interrupt request  
enable bits (INTE0, INTE1, INTE2, INT3 and INTE4) are set to “interrupts enabled”.  
(4)  
(5)  
The start bit (ST) is set to “1”.  
This (ST=“1”) causes the values of the hour/minute/second registers, WTHR/WTMR/WTSR, to be  
loaded to the hour/minute/second timers.  
(6)  
The values of the sub-second registers, WTBR0/WTBR1/WTBR2, are loaded to the 21 bit down  
counter.  
(7)  
(8)  
The run flag (RUN) is set to “1”.  
The 21 bit down counter begins counting at the mainclock divided by 2 (4/2 MHz), subclock divided by  
2 (32.768/2 KHz) or RC clock divided by 2 (100/2 kHz).  
(9)  
When the 21 bit down counter reaches “000000 ”, the value of the sub-second registers is loaded to  
H
the 21 bit down counter, generating a half-second interrupt request. Each second half-second interrupt  
a second interrupt will be generated.  
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Chapter 49 Real-Time Clock  
5.Operation  
(10)  
(11)  
(12)  
(14)  
When the second counter counts up to “59”, the counter is cleared next time when the counter counts  
up, at which the minute counter counts up, generating a 1-minute interrupt request.  
When the minute counter counts up to “59”, the counter is cleared next time when the counter counts  
up, at which the hour counter counts up, generating a 1-hour interrupt request.  
When the hour counter counts up to “23”, the counter is cleared next time when the counter counts up,  
at which a 1-day interrupt request is generated.  
The software changes the status of Real-time Clock to STOP. (Set the stop bit (STCR.STOP) to “1”.)  
Real-time Clock continues to operate in the STOP state.  
(17)  
(20)  
The device recovers from STOP mode (by interrupt request).  
This (ST=“0”) resets and stops the 21 bit down counter and the hour/minute/second counters.  
957  
Chapter 49 Real-Time Clock  
6.Setting  
6. Setting  
Table 6-1 Required Settings to Run Real-time Clock  
Setting  
Procedure *  
Setting  
Setting Registers  
Sub-second registers  
(WTBR0,WTBR1 and WTBR2)  
Set a reload value to the sub-second registers.  
Initialize Real-time Clock.  
See 7.1.  
See 7.2.  
See 7.3.  
See 7.4.  
RTC control register (WTCR)  
Hour/minute/second registers  
(WTHR/WTMR/WTSR)  
Set time (hour/minute/second).  
Activate Real-time Clock.  
RTC control register (WTCR)  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-2 Required Settings to Know Time  
Setting  
Procedure *  
Setting  
Setting Registers  
Hour/minute/second registers  
(WTHR/WTMR/WTSR)  
Read time.  
See 7.6.  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-3 Required Settings to Stop Real-Time Clock  
Setting  
Procedure *  
Setting  
Stop Real-time Clock.  
Setting Registers  
RTC control register (WTCR)  
See 7.7.  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-4 Required Settings to Generate Interrupts to Real-time Clock  
Setting  
Procedure *  
Setting  
Setting Registers  
See “Chapter 24 Interrupt Control (Page  
No.311)”.  
Set a RTC interrupt vector and RTC interrupt level.  
See 7.10.  
See 7.10.  
Enable RTC interrupts.  
Clear interrupt requests.  
Enable interrupt requests.  
RTC control register (WTCR)  
*: For the setting procedure, refer to the section indicated by the number.  
Table 6-5 Required Settings to select clock source to Real-time Clock  
Setting  
Procedure *  
Setting  
Set a RTC clock source.  
Setting Registers  
See “4.4 CSCFG: Clock Source Configuration  
Register (Page No.196)”.  
*: For the setting procedure, refer to the section indicated by the number.  
958  
 
Chapter 49 Real-Time Clock  
7.Q&A  
7. Q&A  
7.1 How do I set the count period of 1 second?  
Stop Real-time Clock and then set the sub-second register WTBR. The reload value corresponds to the time  
needed for half a second, i.e.  
• At 32 kHz RTC operation set WTBR to “001FFF ”.  
H
• At 100 kHz RTC operation set WTBR to “0061A7 ”.  
H
• At 4 MHz RTC operation set WTBR to “0F423F ”.  
H
7.2 How do I initialize Real-time Clock?  
Use the start bit (WTCR.ST).  
Changing the start bit from “1” to “0” resets the hour/minute/second counters and the 21 bit down counter  
to “0” (initialization), and stops count operation.  
7.3 How do I set or update time (hour/minute/second)?  
Write values to the hour/minute/second registers, WTHR/WTMR/WTSR, and set the update bit (UPDT).  
Operation  
Update bit (UPDT)  
To update the hour/minute/second counters  
Set the bit to “1”.  
7.4 How do I start or stop Real-time Clock's counting?  
Use the start bit (WTCR.ST).  
Operation  
To stop Real-time Clock's counting  
To start Real-time Clock's counting  
Start bit (ST)  
Set the bit to “0”.  
Set the bit to “1”.  
7.5 How do I confirm that Real-time Clock is active?  
Use the run flag (WTCR.RUN).  
Operation  
Real-time Clock is inactive.  
Run flag (RUN)  
The flag is set to “0”.  
The flag is set to “1”.  
Real-time Clock is active.  
7.6 How do I know time?  
Read the hour/minute/second registers, WTHR/WTMR/WTSR.  
Note that only byte-access is allowed to these register. So, when these registers are read at the very timing of  
changing over the hour or minute boundary as shown below, there is a possibility of misjudging the time. So,  
read several times to get a logically consistent value.  
Example: Read begins at the second register: 02:59:59 (SS) => 03:59:59 (SS) => 03:00:00  
Read begins at the hour register: 02:59:59 => 02:00:00 => 03:00:00  
7.7 How do I stop Real-time Clock?  
See 7.4.  
959  
   
Chapter 49 Real-Time Clock  
7.Q&A  
7.8 What are interrupt-related registers?  
RTC interrupt vector and level settings.  
The following table shows the relationship between interrupt levels and vectors.  
For details on interrupt levels and vectors, refer to “Chapter 24 Interrupt Control (Page No.311)”.  
Interrupt vectors (Default)  
Interrupt level set bit (ICR[4.0])  
#132 (0FFDECh)  
Interrupt level register ICR58 (047Ah)  
The interrupt request flags (INT0,INT1,INT2,INT3 and INT4) are not automatically cleared, so the software  
must clear them by writing “0” to these flags before control is returned from interrupt processing.  
7.9 What interrupts are available and how are they selected?  
There are four interrupt causes:  
Interrupt request enable  
Interrupt cause  
Interrupt request bit  
bits  
On counting seconds  
On counting minutes  
On counting hours  
INT0  
INT1  
INT2  
INT3  
INT4  
INTE0  
INTE1  
INTE2  
INTE3  
INTE4  
On counting days  
On counting half-seconds  
An interrupt request is made by ORing these four interrupt causes. Each cause can be selected with the  
corresponding interrupt request enable bit.  
7.10 How do I enable interrupts?  
Use the interrupt request enable bits (WTCR.INTE0, WTCR.INTE1, WTCR.INTE2, WTCR.INTE3 and  
WTCER.INTE4).  
Setting Procedure  
Interrupt request enable bits (INTE0, INTE1, INTE2, INTE3 and INTE4)  
To disable interrupts  
To enable interrupts  
Set the bit to “0”.  
Set the bit to “1”.  
To clear interrupt requests,  
Use the interrupt request bits (WTCR.INT0, WTCR.INT1, WTCR.INT2, WTCR.INT3 and WTCER.INT4).  
Setting Procedure  
Interrupt request bits (INT0, INT1, INT2, INT3 and INT4)  
To clear interrupt requests  
Write “0”.  
960  
Chapter 49 Real-Time Clock  
8.Caution  
8. Caution  
• Setting the interrupt request flags (WTCR.INT0, WTCR.INT1, WTCR.INT2, WTCR.INT4 and WTCER.INT4)  
to “1” due to overflow, and writing “0” to that bit have occurred at the same time, the flag is set to “1”. (Flag  
setting takes precedence.)  
• Writing “1” to the update bit (ETCR.UPDT) and update completion have occurred at the same time, the  
update bit (UPDT) is set to “0”.  
• When the second counter holds the value of 59, even if “1” is written to the update bit (WTCR.UPDT), the  
hour/minute/second counters are not updated, leaving the update bit to remain “0”.  
In order to update the hour/minute/second counters, it is recommended that “0” should be written to the start  
bit (WTCR.ST), the hour/minute/second counters be cleared to “0”, and then “1” be written to the start bit  
(ST).  
• If you stop the peripheral clock (CLKP) after updating the hour/minute/second counters using the update bit  
(WTCR.UPDT), read the hour/minute/second registers to confirm that they have been updated before  
stopping the peripheral clock.  
• When you start to use the Real-time Clock module, change the start bit (ST) from “1” to “0”, and clear the  
hour/minute/second counters and the 21 bit down counter to “0”.  
• The Sub-second register of the RTC module stores the reload value for the 21bit prescaler. This value is  
reloaded after the reload counter reaches "0". When modifying all three bytes, make sure the reload  
operation will not be performed in between the write instructions. Otherwise the 21-bit prescaler loads the  
incorrect value of the combination of new data and old data bytes. It is generally recommended that the Sub-  
Second register is updated while the ST bit is "0".  
However, if this update is done immediately after an RTC second interrupt there should be enough time to  
securely modify the registers until the next reload operation (next second interrupt) even if ST is not set to  
"0" and the module is in operation.  
When updating the registers by using the ST bit the following must be taken into account:  
The new value is written into the registers with the rising edge of the RUN bit. This RUN bit is clocked by the  
RTC clock (32 kHz, 100kHz or 4 MHz depending on device and mode). To make sure that the update is  
done properly, write the new values into the registers, set ST to 0, wait for the RUN bit to go low and then  
start the circuit again by setting ST to 1. RUN will go low at the second rising edge of the RTC clock after ST  
has been set to 0. It will rise again at the half second rising edge of RTC clock after ST has been set to 1. If  
this operation is to be done several times directly after each other, wait for RUN to go to high before setting  
ST to low again.  
• If a reload has occurred during updating the sub-second registers, WTBR0 to WTBR2, an unexpected value  
may be reloaded to the 21 bit down counter. Therefore, it is recommended that the sub-second register,  
WTBR, should be updated with the start bit (WTCR.ST) set to “0”.  
• If all the sub-second registers, WTBR0 to WTBR2, are set to “0”, the 21 bit down counter does not operate,  
resulting in the Real-time Clock module to be inoperational.  
• If a carry has occurred during reading from the hour/minute/second registers, WTHR/WTMR/WTSR,  
inappropriate values may be read. To avoid this, it is recommended that interrupts (INT0-4) should be used  
to read time (HH/MM/SS).  
• In order for the Real-time Clock module to function properly, the frequency of the subclock must be much  
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Chapter 49 Real-Time Clock  
8.Caution  
lower than that of the peripheral clock (CLKP). If not, correct values cannot be read from WTHR/WTMR/  
WTSR.  
• Note that only byte-access is allowed to these register. So, when these registers are read at the very timing  
of changing over the hour or minute boundary as shown below, there is a possibility of misjudging the time.  
So, read several times to get a logically consistent value.  
Example: Read begins at the second register: 02:59:59=> 03:59:59 => 03:00:00  
Read begins at the hour register: 02:59:59 => 02:00:00 => 03:00:00  
In this case, the current time should be interpreted as 3 o'clock.  
962  
Chapter 50 Subclock Calibration Unit  
1.Overview  
Chapter 50 Subclock Calibration Unit  
1. Overview  
The Clock Calibration Module provides possibilities to calibrate the 32kHz oscillation clock or  
100kHz RC oscillation clock with respect to the 4MHz oscillation clock. This chapter gives an  
overview of the calibration unit, describes the registers and provides some application notes.  
1.1 Description  
This hardware allows the software to measure time generated by the 32kHz clock (or 100kHz RC clock) with  
the 4MHz clock.  
By utilizing this hardware in conjunction with software processing, the accuracy of the 32kHz clock (or 100kHz  
RC clock) can come closer to that of the 4MHz clock. The measurement result from the Clock Calibration  
Module can be processed by the software and the setting required for the Real Time Clock Module can be  
obtained.  
This module consists of two timers, one operating with the 32kHz clock (or 100kHz RC clock) and the other  
operating with the 4MHz clock. The 32kHz (100kHz) timer triggers the 4MHz timer and resulting 4MHz timer  
value is stored in a register. The value stored in this register can be used for the subsequent software  
processing to calculate the desired Real Time Clock module’s setting.  
963  
   
Chapter 50 Subclock Calibration Unit  
2.Block Diagram  
2. Block Diagram  
UC18CLK  
CLK4G = OSC4 | ~STRT | (READY & ~RUNS);  
CLK4G  
OSC4  
gate  
STRT  
READY  
RUNS  
OSC32  
CLKP  
gate  
STRT  
CLKPG  
gate  
gate  
32kHz  
TIMER  
UC18TRD  
4MHz  
TIMER  
CLK32G  
CUTD  
RSLEEPB  
RUN  
CLKPG2  
CUTR  
counter (16 bit)  
CUTR (24 bit)  
sync  
RUNS  
async  
RST  
STRTS  
32->4  
RSLEEPB  
STRT  
RUN  
UC18TRR  
&
CLKPG2 = CLKP | (~STRT & RSLEEPB);  
READY  
READY  
STRT  
sync  
CLKP->32  
async  
RST  
STRT  
STRT  
reset  
STRT  
set / reset  
READY  
RB  
RUNSS1  
RUNSS  
&
INTEN  
set / reset  
sync  
4->CLKP  
RBB  
RB  
RSLEEP  
RMW  
RSLEEPB  
RMWB  
set  
INT  
READYPULSE  
reset  
UC18BUS  
CUCR (3 bit)  
CUTR (24 bit)  
&
INT_INT  
INT_I  
INT  
*_RDB  
*_WRB  
*_RD  
*_WR  
CUTD  
CUTD (16 bit)  
RSTB  
RST  
UC18IO  
UC18RBI  
FC18  
Figure 2-1 Block Diagram of the calibration unit  
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Chapter 50 Subclock Calibration Unit  
3.Timing  
3. Timing  
32 kHz  
STRT (CLKP)  
STRTS (32 kHz)  
RUN (32 kHz)  
RUNS (4 MHz)  
32 kHz counter (16 bit)  
4 MHz counter (24 bit)  
READY (32 kHz)  
CUTD  
0
CUTD-1  
2
1
0
CUTD  
old CUTR  
new CUTR  
READYPULSE (CLKP)  
INT (CLKP)  
Figure 3-1 Timing of the measurement process  
965  
 
Chapter 50 Subclock Calibration Unit  
4.Clocks  
4. Clocks  
The module operates with 3 different clocks: The 4 MHz clock OSC4, the 32 kHz clock OSC32 (ot the 100kHz  
clock OSC100) and the peripheral clock CLKP. Synchronization circuits adapt the different domains.  
The clock frequencies have to fulfill the following requirements:  
● Clock ratio  
T
T
T
> 2 x T  
+ 3 x T  
OSC4 CLKP  
OSC32/OSC100  
< 1/2 x T  
- 3/2 x T  
OSC4  
CLKP  
OSC32/OSC100  
OSC32/OSC100  
CLKP  
OSC4  
< 1/3 x T  
- 2/3 x T  
● The input frequencies must not exceed the values given in Table 4-1 .  
Table 4-1 Maximum operation frequencies  
OSC32/OSC100  
OSC4  
CLKP  
maximum 2 MHz 500 ns 10 MHz 100 ns 50 MHz 20 ns  
Table 4-2 Example of valid clock ratios which fulfill requirements 1 and 2  
OSC32  
2 MHz 500 ns  
32 kHz 31.25 us 100 kHz  
OSC100  
OSC4  
10 MHz 100 ns 50 MHz  
4 MHz 250 ns >2 MHz  
CLKP  
maximum operation  
speed  
2 MHz  
500 ns  
10 us  
20 ns  
normal operation  
500 ns  
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Chapter 50 Subclock Calibration Unit  
5.Register Description  
5. Register Description  
This section lists the registers of the calibration unit and describes the function of each register  
in detail.  
■ Calibration Unit Control Register (CUCR)  
⇐ Bit no.  
7
-
6
5
-
4
3
-
2
-
1
0
Control Register low byte  
Address : 0004B0H  
CUCRL  
-
STRT  
INT INTEN  
(R)  
(0)  
(R)  
(0)  
(R) (R/W) (R) (R/W) (R/W) (R/W)  
(0) (0) (0) (0) (0) (0)  
Read/write ⇒  
Default value⇒  
■ 32kHz/100kHz Timer Data Register (CUTD)  
⇐ Bit no.  
32/100kHz Timer Register high byte  
Address : 0004B2H  
15  
14  
13  
12  
11  
10  
9
8
CUTDH  
TDD15TDD14 TDD13 TDD12 TDD11TDD10 TDD9 TDD8  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
(1)  
7
(0)  
6
(0)  
5
(0)  
4
(0)  
3
(0)  
2
(0)  
1
(0)  
0
Default value⇒  
⇐ Bit no.  
32/100kHz Timer Register low byte  
Address : 0004B3H  
CUTDL  
TDD7 TDD6 TDD5 TDD4 TDD3 TDD2 TDD1 TDD0  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
See also 4.4 CSCFG: Clock Source Configuration Register (Page No.196) for the configuration  
of the Calibration Unit clock sources.  
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Chapter 50 Subclock Calibration Unit  
5.Register Description  
■ 4MHz Timer Data Register (CUTR1/CUTR2)  
⇐ Bit no.  
CUTR1H  
4MHz Timer Register1 high byte  
Address : 0004B4H  
15  
-
14  
-
13  
-
12  
-
11  
-
10  
-
9
-
8
-
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
⇐ Bit no.  
7
6
5
4
3
2
1
0
4MHz Timer Register1 low byte  
Address : 0004B5H  
CUTR1L  
TDR23 TDR22 TDR21TDR20 TDR19 TDR18 TDR17TDR16  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
⇐ Bit no.  
4MHz Timer Register2 high byte  
Address : 0004B6H  
15  
14  
13  
12  
11  
10  
9
8
CUTR2H  
TDR15TDR14 TDR13 TDR12 TDR11TDR10 TDR9 TDR8  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
⇐ Bit no.  
7
6
5
4
3
2
1
0
4MHz Timer Register2 low byte  
Address : 0004B7H  
CUTR2L  
TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
Register  
Address  
+0  
Block  
+1  
+2  
+3  
0004B0  
CUCR [R/W]  
-------- ---0--00  
CUTD [R/W]  
10000000 00000000  
Calibration  
Unit of 32kHz  
and 100kHz  
oscillator  
H
0004B4  
CUTR1 [R]  
-------- 00000000  
CUTR2 [R]  
00000000 00000000  
H
5.1 Calibration Unit Control Register (CUCR)  
The Control Register (CUCR) has the following functions:  
start / stop calibration measurement  
enable / disable interrupt  
indicates the end of the calibration measurement  
⇐ Bit no.  
CUCRL  
7
-
6
5
-
4
3
-
2
-
1
0
Control Register low byte  
Address : 0004B1H  
-
STRT  
INT INTEN  
(R)  
(0)  
(R)  
(0)  
(R) (R/W) (R) (R/W) (R/W) (R/W)  
(0) (0) (0) (0) (0) (0)  
Read/write ⇒  
Default value⇒  
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Chapter 50 Subclock Calibration Unit  
5.Register Description  
BIT[0]: INTEN - Interrupt enable  
0
1
interrupt disabled (default)  
interrupt enabled  
This is the interrupt enable bit corresponding to the INT bit. When this bit is set to 1 and the  
INT bit is set by the hardware, the calibration module signals an interrupt to the CPU. The  
INT-bit itself is not affected by the INTEN bit and is set by hardware even if interrupts are  
disabled (INTEN=0).  
BIT[1]: INT - Interrupt  
0
1
calibration ongoing / module inactive (default)  
calibration completed  
This bit indicates the end of the calibration. When the 32KHz/100kHz timer reaches zero after  
the start of calibration, the 4MHz Timer Data Register stores the last 4MHz timer value and  
the INT bit is set to 1.  
The read-modify-write operation to this bit results in reading 1 and writing 0 to this bit clears  
this flag(INT=0). Writing 1 to this bit has no effect.  
The interrupt flag INT is not reset by hardware. Therefor it must be reset by software before  
starting a new calibration. Otherwise the end of the calibration process is only signalized by  
the STRT bit (the INT flag stays 1 also during calibration).  
BIT[4]: STRT - Calibration Start  
0
1
calibration stopped, module switched off (default)  
start calibration  
When the STRT bit is set to 1 by the software, the calibration starts. The 32kHz/100kHz  
Timer  
starts counting down from the value stored in the 32KHz/100kHz Timer Data Register  
MHz Timer starts counting up from zero.  
and the 4  
When the 32KHz/100kHz Timer reaches zero, this bit is reset to 0 by the hardware.  
If 0 is written into this bit by the software during the calibration process, the calibration is  
immediately stopped. If writing 0 by the software and reset to 0 by the hardware happens at  
the same time, the hardware operation supersede the software operation. This means the  
calibration is properly completed and the INT bit is set to “1”. Writing 1 to this bit during the  
calibration has no effect.  
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Chapter 50 Subclock Calibration Unit  
5.Register Description  
5.2 32 kHz / 100 kHz Timer Data Register (16 bit) (CUTD)  
The 32kHz/100kHz Timer Data Register (CUTD) holds the value which determines the duration of calibration  
(32kHz/100kHz reload value)  
⇐ Bit no.  
32/100kHz Timer Register high byte  
Address : 0004B2H  
15  
14  
13  
12  
11  
10  
9
8
CUTDH  
TDD15TDD14 TDD13 TDD12 TDD11TDD10 TDD9 TDD8  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
(1)  
7
(0)  
6
(0)  
5
(0)  
4
(0)  
3
(0)  
2
(0)  
1
(0)  
0
Default value⇒  
⇐ Bit no.  
32/100kHz Timer Register low byte  
Address : 0004B3H  
CUTDL  
TDD7 TDD6 TDD5 TDD4 TDD3 TDD2 TDD1 TDD0  
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)  
Read/write ⇒  
Default value⇒  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
Default value is 0x8000 which corresponds to a measurement duration of 1 second, if a 32.768  
kHz crystal is used.  
This register should be written only when the calibration is inactive (STRT=0).  
The 32kHz/100kHz Timer Register stores the value to specify the duration of the calibration.  
When the calibration is started, the stored value is loaded into the 32kHz/100kHz Timer and the  
timer starts counting down until it reaches zero.  
If CUTD is initialized with 0000 an underflow will occur and the measurement will take (FFFF hex  
+ 1) * T  
osc32/osc100  
The 32kHz/100kHz timer operates with the 32kHz or with the 100kHz oscillation clock (see  
chapter “4.4 CSCFG: Clock Source Configuration Register (Page No.196)” how to select  
between those clocks.  
In order to achieve a measurement duration of 1 second at a 32kHz oscillation, the CUTD register  
has to be load with 0x8000 = 32768 dec. This number results from the exact oscillation frequency  
of the crystal, which is F =32768 Hz. The ideal values of the measurement results (if a 4.00  
osc  
MHz crystal is used) are shown in the following table.  
In order to achieve a measurement duration of half a second at a 100kHz oscillation, the CUTD  
register has to be load with 0xC350 = 50000 dec. This number results from the exact oscillation  
frequency of the crystal, which is F =100000 Hz. The ideal values of the measurement results  
osc  
(if a 4.00 MHz crystal is used) are shown in the following table.  
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Chapter 50 Subclock Calibration Unit  
5.Register Description  
Table 5-1 32kHz : Ideal measurement results depending on measurement duration  
duration of  
calibration  
CUTD  
value  
CUTR  
value  
2 sec  
1.75 sec  
1.5 sec  
1.25 sec  
1 sec  
0x0000  
0xE000  
0xC000  
0xA000  
0x8000  
0x6000  
0x4000  
0x2000  
0x7A1200  
0x6ACFC0  
0x5B8D80  
0x4C4B40  
0x3D0900  
0x2DC6C0  
0x1E8480  
0x0F4240  
0.75 sec  
0.5 sec  
0.25 sec  
The duration of the whole process from writing a 1 into the STRT bit until STRT is reset by  
hardware is longer than the actual calibration measurement time, due to synchronization between  
the different clock domains. Process Duration < (CUTD + 3)*T  
.
osc32  
The calibration measurement time is exact CUTD * T  
.
osc32  
Table 5-2 100kHz : Ideal measurement results depending on measurement duration  
duration of  
calibration  
CUTD  
value  
CUTR  
value  
0.5 sec  
0.25 sec  
0.125 sec  
0.1 sec  
0xC350  
0x61A8  
0x30D4  
0x2710  
0x1E8480  
0x0F4240  
0x07A120  
0x061A80  
The duration of the whole process from writing a 1 into the STRT bit until STRT is reset by  
hardware is longer than the actual calibration measurement time, due to synchronization between  
the different clock domains. Process Duration < (CUTD + 3)*T  
.
osc100  
The calibration measurement time is exact CUTD * T  
.
osc100  
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Chapter 50 Subclock Calibration Unit  
5.Register Description  
5.3 4 MHz Timer Data Register (24 bits) (CUTR)  
The Timer Data Register (CUTR) holds the value of the calibration result (4MHz counter)  
Precaution: Reading this register during calibration, results in random values.  
The end of calibration is indicated by the INT-bit and the STRT-bit  
in the CUCR-register.  
After INT has changed from 0 to 1 / STRT has changed from 1 to 0,  
the value of CUTR is valid.  
⇐ Bit no.  
CUTR1H  
4MHz Timer Register1 high byte  
Address : 0004B4H  
15  
-
14  
-
13  
-
12  
-
11  
-
10  
-
9
-
8
-
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
⇐ Bit no.  
7
6
5
4
3
2
1
0
4MHz Timer Register1 low byte  
Address : 0004B5H  
CUTR1L  
TDR23 TDR22 TDR21TDR20 TDR19 TDR18 TDR17TDR16  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
⇐ Bit no.  
4MHz Timer Register2 high byte  
Address : 0004B6H  
15  
14  
13  
12  
11  
10  
9
8
CUTR2H  
TDR15TDR14 TDR13 TDR12 TDR11TDR10 TDR9 TDR8  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
⇐ Bit no.  
7
6
5
4
3
2
1
0
4MHz Timer Register2 low byte  
Address : 0004B7H  
CUTR2L  
TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
(R)  
(0)  
Read/write ⇒  
Default value⇒  
The 4MHz Timer Data Register stores the result of the calibration. When the calibration is started,  
the 4MHz Timer starts counting up from zero. When the 32kHz/100kHz Timer reaches zero, the  
4MHz Timer stops counting and the register holds the calibration result until the next calibration is  
triggered by software.  
Reading this register during calibration, results in random values.  
The end of calibration is indicated by the INT-bit and the STRT-bit in CUCR-register. After these  
bits changed from 0 to 1, resp. 1 to 0, the value of CUTR is valid.  
Writing into this register by software has no effect.  
The 4MHz Timer operates with the 4MHz oscillation clock.  
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Chapter 50 Subclock Calibration Unit  
6.Application Note  
6. Application Note  
This section lists application notes concerning accuracy of the calibration, power dissipation and  
measurement duration.  
● 32kHz  
The setting of the 32KHz Timer Data Register can be calculated in the following way.  
If the duration of 1 second is desired for the calibration, 8000Hex = 32768Dec should be set in  
the 32kHz Timer Data Register and it represents 32,768 pulses of the 32.768kHz oscillation  
clock.  
This setting should result in the stored value of approximately 3D0900Hex in the 4MHz Time Data  
Register. This value represents 4,000,000 pulses of the 4MHz oscillator.  
● 100kHz  
The setting of the 100KHz Timer Data Register can be calculated in the following way.  
If the duration of 0.5 second is desired for the calibration, C350Hex = 50000Dec should be set in  
the 100kHz Timer Data Register and it represents 50,000 pulses of the 100kHz oscillation clock.  
This setting should result in the stored value of approximately 1E8480Hex in the 4MHz Time Data  
Register. This value represents 2,000,000 pulses of the 4MHz oscillator.  
Table 6-1 Ideal measurement results (CUTR) with 32.768kHz and 4.0MHz oscillators  
duration of  
calibration  
CUTD  
value  
CUTR  
value  
2 sec  
1.75 sec  
1.5 sec  
1.25 sec  
1 sec  
0x0000  
0xE000  
0xC000  
0xA000  
0x8000  
0x6000  
0x4000  
0x2000  
0x7A1200  
0x6ACFC0  
0x5B8D80  
0x4C4B40  
0x3D0900  
0x2DC6C0  
0x1E8480  
0x0F4240  
0.75 sec  
0.5 sec  
0.25 sec  
The key to the use of the calibration module is power dissipation as well as accuracy of the  
calibration.  
Table 6-2 Ideal measurement results (CUTR) with 100kHz and 4.0MHz oscillators  
duration of  
calibration  
CUTD  
value  
CUTR  
value  
0.5 sec  
0.25 sec  
0.125 sec  
0.1 sec  
0xC350  
0x61A8  
0x30D4  
0x2710  
0x1E8480  
0x0F4240  
0x07A120  
0x061A80  
The key to the use of the calibration module is power dissipation as well as accuracy of the  
calibration.  
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Chapter 50 Subclock Calibration Unit  
6.Application Note  
■ Accuracy:  
The accuracy of the calibration is dependent on the clock frequency used by the 4MHz Timer and  
duration of the calibration. The maximum error of the 4MHz timer is +/- 1 digit. If the clock  
frequency is 4MHz and duration of the calibration is 1 second, the achieved accuracy is  
calculated in the following way:  
0.25us (Clock cycle time) / 1 second (duration)=0.25 ppm.  
In general:  
Accuracy = (Clock cycle time of 4MHz Timer) / (Duration of calibration)  
■ Power dissipation:  
Suppose the current consumption I  
in run mode is 20 times the consumption I  
in RTC  
RTC  
RUN  
mode ( I  
= 20 x I  
).  
RTC  
RUN  
If the MCU is woken up from RTC mode by software to trigger the calibration measurement every  
minute and the duration of the calibration is set to 1 second, the increase in the power dissipation  
can be 20xI  
/60= 1/3 * I  
.
RTC  
RTC  
Therefore the software has to make sure that the increase should not affect the hardware  
limitations coming from the system requirements. For example, the software has to be designed  
to trigger the calibration least frequently.  
It is generally recommended that the theoretical increase in power dissipation is not more than  
5% particularly in the RTC mode of the MCU.  
■ Measurement limits:  
The limit to the duration of the calibration is roughly 2 seconds if the 32kHz/100kHz Timer is  
operating with 32kHz clock (0.5 seconds if operating with 100kHz). On the other hand, the 4MHz  
Timer can measure time up to 4 seconds if it is working with a 4MHz clock.  
974  
Chapter 51 Low Voltage Reset/Interrupt  
1.Overview  
Chapter 51 Low Voltage Reset/Interrupt  
1. Overview  
• Module for generating a low voltage reset or interrupt depending on the supply state of either the internal or  
external supply voltage.  
2. Features  
• Generates a low voltage reset or a low voltage interrupt  
• Interrupt activation source can be selected between external supply (VDD5) detection and internal supply  
(VDD) detection  
• Selectable trigger levels for external and internal supply levels  
• Power down function  
975  
     
Chapter 51 Low Voltage Reset/Interrupt  
3.Registers  
3. Registers  
3.1 LV Detection Control Registers  
Controls the low voltage detection function.  
• LVDET: Address 04C5h (Access: Byte, Halfword, Word)  
7
-
6
5
4
3
2
-
1
0
bit  
LVSEL  
LVEPD  
LVIPD  
LVREN  
LVIEN  
LVIRQ  
Initial value (INIT pin input,  
watchdog reset)  
-
0
0
0
0
-
0
0
Initial value  
(Software reset)  
-
X
X
X
X
-
0
0
R0/W0  
R/W  
R/W  
R/W  
R/W  
R0/W0  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7: Reserved bit. The read value is always ‘0’.  
• Bit6: Low-Voltage Interrupt Source selection.  
LVSEL  
Function  
0
1
Internal (VDD) LV detection used for LV-Int and LV-Reset [Initial value]  
External (VDD5) LV detection used for LV-Int and LV-Reset  
• Bit5: External Low-Voltage Detection Power-Down.  
LVEPD  
Function  
0
1
External (VDD5) LV detection active [Initial value]  
External (VDD5) LV detection power down  
• Bit4: Internal Low-Voltage Detection Power-Down.  
LVIPD  
Function  
0
1
Internal (VDD) LV detection active [Initial value]  
Internal (VDD) LV detection power down  
• Bit3: Low-Voltage Reset Enable.  
LVREN  
Function  
0
1
Low Voltage Reset Disabled [Initial value]  
Low Voltage Reset Enabled  
• Bit2: Reserved bit.  
• Bit1: Low-Voltage Interrupt Enable.  
LVIEN  
Function  
0
1
Low Voltage Interrupt Disabled [Initial value]  
Low Voltage Interrupt Enabled  
• Bit0: Low-Voltage Interrupt Flag.  
LVIRQ  
Function  
0
1
Low Voltage Interrupt Flag (no interrupt request) [Initial value]  
Low Voltage Interrupt Flag (interrupt requested)  
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Chapter 51 Low Voltage Reset/Interrupt  
3.Registers  
• LVSEL: Address 04C4h (Access: Byte, Halfword, Word)  
7
6
5
4
3
2
1
0
bit  
LVESEL3 LVESEL2 LVESEL1 LVESEL0 LVISEL3 LVISEL2 LVISEL1 LVISEL0  
Initial value (INIT pin input,  
watchdog reset)  
0
0
0
0
0
1
1
1
Initial value  
(Software reset)  
X
X
X
X
X
X
X
X
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7-4: External LV detection voltage level  
LVESEL3-LVESEL0  
Trigger level  
4.2V +/- 0.1V  
4.1V +/- 0.1V  
4.0V +/- 0.1V  
3.9V +/- 0.1V  
3.8V +/- 0.1V  
3.7V +/- 0.1V  
3.6V +/- 0.1V  
3.2V +/- 0.1V  
3.0V +/- 0.1V  
2.8V +/- 0.1V (initial)  
1001  
1000  
0111  
0110  
0101  
0100  
0011  
0010  
0001  
0000  
• Bit3-0: Internal LV detection voltage level  
LVISEL3-LVISEL0  
Trigger level  
1.6V +/- 0.1V (initial)  
1.5V +/- 0.1V  
1.4V +/- 0.1V  
0111  
0110  
0101  
0100  
0011  
0010  
0001  
0000  
1.3V +/- 0.1V  
1.2V +/- 0.1V  
1.1V +/- 0.1V  
1.0V +/- 0.1V  
0.9V +/- 0.1V  
Note: The set level of the Internal Low Voltage Detection is only effective in case of Main Regulator is  
switched off (for decreasing the trigger level when decreasing the sub regulator voltage). Otherwise (with  
main regulator on) the default level is applied internally by hardware to the low voltage detection module  
(the register setting is not changed in this case and will be applied next time the main regulator is switched  
off).  
977  
Chapter 51 Low Voltage Reset/Interrupt  
3.Registers  
978  
Chapter 52 Regulator Control  
1.Overview  
Chapter 52 Regulator Control  
1. Overview  
• Module for controlling the behaviour of the MAIN-Regulator and SUB-Regulator in the device modes.  
2. Features  
• Main Regulator enable and disable independently for Sub-run and STOP/RTC  
• Main regulator standby flag output  
• Selectable Sub regulator output voltage for Sub-run and STOP/RTC  
979  
     
Chapter 52 Regulator Control  
3.Registers  
3. Registers  
3.1 Regulator Control Registers  
Controls the regulator function.  
• REGCTR: Address 04CFh (Access: Byte, Halfword, Word)  
7
-
6
-
5
-
4
3
-
2
-
1
0
bit  
MSTBO  
MAINKPEN MAINDSBL  
Initial value (INIT pin input,  
watchdog reset)  
X
X
X
X
X
X
0
0
Initial value  
(Software reset)  
X
X
X
X
R
X
X
X
X
R0/WX  
R0/WX  
R0/WX  
R0/WX  
R0/WX  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7-5: Reserved bit. The read value is always “0”.  
• Bit4: Main regulator Standby output flag.  
MSTBO  
Function  
Function  
0
1
Main regulator is in RUN mode  
Main regulator is in STANDBY mode  
• Bit3-2: Reserved bit. The read value is always “0”.  
• Bit1: Main Regulator enable in STOP/RTC mode.  
MAINKPEN  
0
1
Main regulator disabled in STOP/RTC mode [Initial value]  
Main regulator enabled in STOP/RTC mode  
• Bit0: Main Regulator disable in Subrun Mode.  
MAINDSBL  
Function  
0
1
Main regulator enabled in Subrun mode [Initial value]  
Main regulator disabled in Subrun mode  
980  
 
Chapter 52 Regulator Control  
3.Registers  
• REGSEL: Address 04CEh (Access: Byte, Halfword, Word)  
7
-
6
-
5
4
3
2
1
0
bit  
FLASHSEL MAINSEL SUBSEL3 SUBSEL2 SUBSEL1 SUBSEL0  
Initial value (INIT pin input,  
watchdog reset)  
0
0
0
0
0
1
1
0
Initial value  
(Software reset)  
X
X
X
X
X
X
X
X
R0/WX  
R0/WX  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit7-6: Reserved bit. The read value is always “0”.  
• Bit5: Flash memory supply mode.  
FLASHSEL  
Function  
Flash memory operation mode is 1.8V [Initial value]  
Flash memory operation mode is 1.9V  
0
1
Note: Please check with the related device datasheet if this setting is supported.  
• Bit4: Main Regulator supply mode.  
MAINSEL  
Function  
Main regulator operation mode is 1.8V [Initial value]  
Main regulator operation mode is 1.9V  
0
1
Note: Please check with the related device datasheet if this setting is supported.  
• Bit3-0: Sub-regulator voltage level  
SUBSEL3-SUBSEL0  
Voltage level  
1.9V +/- 0.1V  
1.8V +/- 0.1V (initial)  
1.7V +/- 0.1V  
1.6V +/- 0.1V  
1.5V +/- 0.1V  
1.4V +/- 0.1V  
1.3V +/- 0.1V  
1.2V +/- 0.1V  
0111  
0110  
0101  
0100  
0011  
0010  
0001  
0000  
Note: The set level of the Sub-regulator voltage is only be effective in case of Main Regulator is switched  
off. Otherwise (with main regulator on) the default level is applied internally by hardware to the Sub-Reg-  
ulator (the register setting is not changed in this case and will be applied next time the main regulator is  
switched off).  
981  
Chapter 52 Regulator Control  
3.Registers  
982  
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM  
1.Overview  
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM  
1. Overview  
The Boot ROM is a fixed start-up routine, which is located at memory addresses 0xB000 to 0xBFFF. The entry  
point 0xBFF8 is determined by the Fixed Reset Vector if the device is configured with the mode pins set to  
MD[2:0]=”000” (internal ROM/vector mode). In this mode MB91460 series devices use the Fixed Mode Vector data  
(FMV, address 0x0F:FFF8, data 0x06000000) and Fixed Reset Vector data (FRV, address 0x0F:FFFC, data  
0x0000BFF8). The data of both these vectors are independent from the flash content at these two addresses.  
The purpose of the Boot ROM is to configure the device after a reset and to provide a simple serial bootloader for  
programming the embedded flash memories.  
Therefore it is executed always after the Reset Cancellation Sequence (see chapter 5.6 Reset Cancellation  
Sequence (Page No.147) or 7.6 Reset Cancellation Sequence (Page No.149)) of every INIT or RST reset.  
2. Check for Boot Conditions  
The check for boot conditions is slightly different for the evaluation chip MB91V460 (A-version) and the flash  
derivates (e.g. MB91F467DA).  
2.1 Evaluation Chip MB91V460  
After the chip initialization and saving the RSRR (Reset Cause Register) to CPU register R4, the Boot Security  
Vector (BSV: Vector #144, 0x0F:FDBC) will be checked. This check is performed as follows: if the data of this  
vector represents a valid address in the specified address range, the Boot Security Vector itself becomes valid.  
Device  
Valid Boot Security Vector address range  
MB91V460  
0x04:0000 – 0x13:FFFF  
If the Boot Security Vector is valid, the Boot ROM is left and the user application is started at the address given by  
this vector.  
The purpose of this feature is to disable the execution of the internal bootloader due to security reasons or to  
minimize startup time of the application. Only if the user sets the Boot Security Vector to an address outside the  
given address range or leaves this vector at default content after erase (0xFFFF:FFFF) the internal bootloader can  
be entered.  
If the Boot Security Vector is not valid, the reset cause will be checked as second boot condition. Only if the reset  
cause was an INIT reset (external INITX pin input, RSRR=0x80), the check for boot conditions will go on.  
Otherwise Boot ROM is left and application is started at default user program entry address 0x0F:4000.  
If the reset cause was an INIT reset, UART0 is initialized: 2400 baud, 8 data bits, 1 stop bit, no parity. UART-  
reception is checked for about 100 ms. If during this time period the ASCII-character “V” (0x56) is received, the  
internal bootloader is entered. Otherwise Boot ROM is left and application is started at default user program entry  
address 0x0F:4000.  
983  
       
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM  
2.Check for Boot Conditions  
*1) Boot-Security-Vector points to address in valid address  
range (0x04:000 – 0x13:FFFF)?  
*2) Start user application at address given by Boot Security Vector  
*3) Start user application at default user program entry address  
*4) Timeout about 100 ms  
Flow Chart of checking boot conditions on MB91V460  
984  
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM  
2.Check for Boot Conditions  
2.2 Flash devices of MB91460 series (MB91F46x)  
After the chip initialization and saving the RSRR (Reset Cause Register) to CPU register R4, there is a check for  
boot conditions.  
All Flash devices have two Boot Security Vectors (BSV1: 0x14:8004, BSV2: 0x14:800C). These vectors are  
located in parallel sector to the Flash Security Vectors (FSV1, FSV2):  
Sector SA4  
(8kB)  
Sector SA5  
(8kB)  
…
…
0x14:8008  
0x14:8000  
FSV2  
FSV1  
BSV2  
BSV1  
64bit width  
The Flash Security Vectors are used for configuring the protection mode of the flash memory sectors and do no  
influence startup of Boot ROM. Refer to Chapter 55 Flash Security (Page No.1009).  
At first, BSV1 is checked: if the data of this vector represents a valid address in the specified address range  
(depending on Flash-ROM size), the Boot Security Vector itself becomes valid.  
Device  
Valid Boot Security Vector address range  
0x04:0000 – 0x14:FFFF  
MB91F467DA  
MB91F469GA  
MB91F464AA  
MB91F465KA  
0x04:0000 – 0x24:FFFF  
0x0A:0000 – 0x0F:FFFF  
0x14:8000 – 0x14:FFFF  
0x08:0000 – 0x0F:FFFF  
0x14:8000 – 0x14:FFFF  
If BSV1 is valid, there will be an additional check before entering user program at the entry address given by BSV1  
(1). Otherwise checks for entering the internal bootloader will be done (2).  
The purpose of this feature is to disable the execution of the internal bootloader due to security reasons or to  
minimize startup time of application. If the user sets BSV1 to a valid address range, this bootloader cannot be  
entered any more.  
(1) If the check for BSV1 is valid, the Magic Number, which should be located on the four bytes before the address  
BSV1 points to, is compared to 0x000A897A. If the Magic Number matches this value, the user application is  
entered at the address given by BSV1.  
The Magic Number is used as flag for a valid user application, or especially for a user bootloader. If you want to re-  
program this user bootloader, a second user bootloader, which handles the re-programming of the first user  
bootloader, has to be located at the address BSV2 points to. If BSV2 does not point to a valid address range, then  
application is started at default user program entry address 0x0F:4000. For more information on this bootloader  
update strategy refer to chapter 5. Bootloader Update Strategy (Page No.990).  
(2) If the check for BSV1 is not valid, the reset cause will be checked as second boot condition. Only if the reset  
cause was an INIT reset (external INITX input, RSRR=0x80), the check for boot conditions will go on. Otherwise  
Boot ROM is left and application is started at default user program entry address 0x0F:4000.  
If the reset cause was an INIT reset, serial clock pin SCK4 is checked for an external clock signal. Therefore logic  
level at this pin is monitored for about 1ms. If port level is constant, UART4 is initialized to asynchronous mode:  
9600 baud, 8 data bits, 1 stop bit, no parity. If port level changes, UART4 is initialized to synchronous slave mode.  
UART-reception is checked for about 100 ms. If during this time period the ASCII-character “V” (0x56) is received,  
985  
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM  
2.Check for Boot Conditions  
the internal bootloader is entered. Otherwise Boot ROM is left and application is also started at default user  
program entry address 0x0F:4000.  
*1) Boot Security Vector points to address in Flash-ROM  
*2) Magic Number = 0x0A897A?  
*3) Start user application at address given by Boot Security Vector 1/2  
*4) Start user application at default user program entry address  
*5) Timeout about 100 ms  
Flow Chart of checking boot conditions on flash derivates of MB91460 series  
986  
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM  
2.Check for Boot Conditions  
2.3 Internal Bootloader Description  
If a valid boot condition for entering the internal bootloader was met, the ASCII-character “F” (0x46) will be  
transmitted via UART0 (MB91V460) or UART4 (MB91460 series flash derivatives) to indicate that the bootloader is  
ready to accept commands.  
There are five different commands supported by the internal bootloader. See the table below for serial protocol of  
these commands.  
(Note) Software to transfer data using this protocol is available from Fujitsu.  
Command  
PC to MCU  
1 (0x01)  
MCU to PC  
241 (0xF1)  
Remark  
130 (0x82)  
2 (0x02)  
Address (4 bytes)  
Size (2 bytes)  
Lo, MidLo, MidHi, Hi  
Lo, Hi  
READ  
Direct read and dump  
Binary Dump  
Bootloader sends 16bit  
checksum  
CheckSum (2 bytes)  
1 (0x01)  
241 (0xF1)  
131 (0x83)  
3 (0x03)  
Address (4 bytes)  
Size (2 bytes)  
Binary Dump  
Lo, MidLo, MidHi, Hi  
Lo, Hi  
WRITE  
Receive and store dump in  
RAM  
Bootloader sends 16bit  
checksum  
CheckSum (2 bytes)  
1 (0x01)  
241 (0xF1)  
132 (0x84)  
4 (0x04)  
Address (4 bytes)  
Lo, MidLo, MidHi, Hi  
CALL  
Calls specified Address and  
waits for a return  
The returned parameter in R4  
will be echoed to the PC  
Return Parameter  
241 (0xF1)  
1 (0x01)  
5 (0x05)  
133 (0x85)  
CHECKSUM  
BAUDRATE  
CheckSum (2 bytes)  
MCU re-dumps 16bit  
checksum (Lo, Hi) calculated  
at last write or read operation  
1 (0x01)  
241 (0xF1)  
134 (0x86)  
6 (0x06)  
Baudrate (4 bytes)  
Lo, MidLo, MidHi, Hi  
Initializes UART with new  
baudrate value  
987  
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM  
3.Registers modified by Boot ROM  
3. Registers modified by Boot ROM  
The Boot ROM initializes the chip and changes the settings of some registers (see table below).  
(Note) The RSRR register can only be read once. After reading the RSRR-register, the contents will be present in  
R4 (C-Compiler convention for parameters) after a branch to application start or the address specified by the Boot-  
Security-Vector.  
3.1 Evaluation Chip MB91V460  
Register  
TBCR  
RSRR  
TBR  
SP*  
PFR21*  
SMR00*  
SCR00*  
SSR00*  
RDR00*  
TRD00*  
BGR00*  
TMCSR0*  
TMRLR0*  
TMR0*  
Value  
0x03  
0 (see note)  
0x0FFC00  
0x0203F8  
0x07  
Address  
0x482  
0x480  
-
Description  
Time-Base Counter/Sync-RST Register  
Reset Source Register (visible in R4)  
Table Base Register  
Stack Pointer  
Port Function Register Port 21 (UART0)  
UART0 Mode Register  
-
0xD95  
0x041  
0x040  
0x042  
0x043  
0x043  
0x080  
0x1B6  
0x1B0  
0x1B2  
0x05  
0x17  
UART0 Control Register  
UART0 Serial Status Register  
UART0 Reception Data Register  
UART0 Transmission Data Register  
UART0 Baud Rate/Reload Counter Register  
Reload Timer 0 Control Status Register  
Reload Timer 0 Reload Register  
Reload Timer 0 Timer Register  
0x0CF  
0x0003  
0x03E8  
(Note) * these registers will only be modified if a check for valid boot condition is performed  
3.2 Flash devices of MB91460 series  
Register  
TBCR  
RSRR  
TBR  
Value  
0x03  
0 (see note)  
0x0FFC00  
Address  
0x482  
0x480  
-
-
Description  
Time-Base Counter/Sync-RST Register  
Reset Source Register (visible in R4)  
Table Base Register  
SP*  
Stack Pointer (depends on RAM size)  
(Note) * these registers will only be modified if a check for valid boot condition is performed  
988  
 
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM  
4.Flash Access Mode Switching  
4. Flash Access Mode Switching  
On MB91460 series flash devices it is possible to switch between different flash access modes. These modes are  
depending on device type.  
Device  
16bit access  
read/write  
read/write  
read/write  
read/write  
32bit access  
read/write  
read/write  
read  
64bit access  
MB91F467DA  
MB91F469GA  
MB91F464AA  
MB91F465KA  
read  
read  
-
-
read  
The 16bit mode is intended basically for flash programming, so program execution from flash is prohibited anyway.  
The 32bit and 64bit modes, however, are intended for program execution from flash. Since switching between  
these modes directly from an application located in the flash is prohibited it is necessary to locate the switching  
routine either in RAM or use the available routine in the Boot ROM:  
This routine is located at address 0xBF60 for all MB91F46x devices. To call this function two parameters are  
expected in CPU registers R4 and R5:  
R4: 2bits (LSB of register) for setting the flash access mode  
b’00: 32bit read/write mode  
b’01: 16bit read/write mode  
b’1x: 64bit read only mode  
R5: 16bits for setting wait time  
The wait time should be in the range of some 100ns after switching the flash access mode for stabilization of the  
Flash-ROM. The wait function is a simple delay loop that needs about 3 CPU cycles for one run. The value in R5  
represents the number of runs through this delay loop.  
Example (time for 1 run through delay loop):  
30 ns @ 100MHz CPU clock  
47 ns @ 64MHz CPU clock  
94 ns @ 32MHz CPU clock  
500 ns @ 2MHz CPU clock  
min. 4-5 runs  
min. 3 runs  
min. 2 runs  
min. 1 runs  
After leaving this delay loop, the switching function will return to the application.  
989  
 
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM  
5.Bootloader Update Strategy  
5. Bootloader Update Strategy  
Some applications require the possibility of software updates in the final product without great effort. To be able to  
program an updated application to the microcontroller, all connected busses (I2C, CAN, LIN, K-Line etc.) can be  
used, so that the microcontroller can remain ‘embedded’ in a bigger system.  
But therefore a user bootloader has to be integrated to the application software, which handles the startup of the  
application, the requests for new programming and the application update itself.  
This user bootloader should be executed after every reset command, so the Boot Security Vector should point to  
the starting address of this bootloader. The request for re-programming the application has to be done by a defined  
communication protocol.  
If the Boot Security Vector feature is used, there is also no possibility to enter the internal bootloader of the  
microcontroller. So the code is secured from read-out or manipulation.  
If there is a request for updating an application, the user bootloader causes the erase of flash sectors where the  
application is located. Flash section, where the Boot Security Vector is located and the section of the bootloader  
itself may not be erased. After erasing, the bootloader has to handle the programming of the application.  
If during this procedure problems like reset or power-down occur, the program-ming can be started again without  
problems because user bootloader and Boot Security Vector are not changed.  
This system brings along some problems if the user bootloader has to be updated. Therefore also the user  
bootloader sector has to be erased and re-programmed. If there is a reset or power-down before ending the  
programming, there is no valid bootloader anymore and there will be no access to the microcontroller via the above  
mentioned busses.  
All MB91460 series flash devices therefore offer the possibility of a safe bootloader update by use of two Boot  
Security Vectors and a Magic Number.  
If user bootloader 1 is valid, set the Magic Number, which has to be located on the four bytes before the address  
defined by BSV1, to 0x000A897A. So after every reset this bootloader is executed. If there is no request for a re-  
programming, the application is started normally.  
990  
 
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM  
5.Bootloader Update Strategy  
By use of this bootloader the application as well as user bootloader 2 can be re-programmed.  
If you want to re-program user bootloader 1, then functions in user bootloader 2 have to be called to erase the  
sector where user bootloader 1 and the Magic Number are located. After erasing, program the new user  
bootloader to the section. As last step, the Magic Number should be set to 0x000A897A.  
This procedure guarantees that there is started always a valid bootloader. If after erasing or during programming  
user bootloader 1 a reset or a power-down occurs, user bootloader 2 is started and the programming can be  
resumed.  
991  
Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM  
5.Bootloader Update Strategy  
992  
Chapter 54 Flash Memory  
1.Overview  
Chapter 54 Flash Memory  
This chapter describes the use of the built-in flash memory.  
1. Overview  
The MB91F46x devices have built-in Flash memory with a variety of capacities, capable of batch-erasing all  
sectors or erasing on the sector level via single +3.0V-5.5V power supply, and writing by the FR-CPU at the  
half-word (16-bit) and word (32-bit) level.  
2. Features  
• Power: Single +3.0-5.5V supply  
• Basic specification: Same as MBM29LV400TC (except size and part of sector configuration)  
• Faster device operation by enabling commands/data reads at D-word (64-bit) level (not all devices)  
• External writers: Interface for Parallel Flash Programmer available.  
• Operation modes:  
(1) 64-bit CPU mode (not all devices)  
CPU reads and executes programs in word (32-bit) length units.  
Flash writing is not possible.  
Actual Flash Memory access is performed in d-word (64-bit) length units.  
(2) 32-bit CPU mode  
CPU reads, writes and executes programs in word (32-bit) length units.  
Actual Flash Memory access is performed in word (32-bit) length units.  
(3) 16-bit CPU mode:  
CPU reads and writes in half-word (16-bit) length units.  
Program exectuion from the Flash is not possible.  
Actual Flash Memory access is performed in word (16-bit) length units.  
(4) Flash memory mode (external access to Flash memory enabled)  
• Features (Through combination of Flash memory macro and FR-CPU interface circuit):  
• Functions as CPU program/data storage memory.  
• Enables access to 32-bit bus width.  
*
• Enables read/write/erase by CPU (auto program algorithm ).  
• Functions equivalent to MBM29LV400TC stand-alone Flash-memory product.  
*
• Enables read/write/erase by parallel Flash programmer (auto program algorithm ).  
*: Auto program algorithm = Embedded Algorithm TM  
993  
       
Chapter 54 Flash Memory  
3.Configuration  
3. Configuration  
Figure 3-1 Block Diagram (32bit flash)  
CPU  
FLASH interface  
FLASH memory  
Control signal  
CPU core  
Control signal  
Control signal  
A0 to A20  
A0 to A20  
Address  
DQ0 to DQ31  
32-bit  
DQ0 to DQ31  
Data  
32-bit  
Control  
signal  
Interface  
with  
FLASH  
writer  
(when in  
FLASH  
mode)  
Address  
Data  
16-bit  
Figure 3-2 Block Diagram (64bit flash)  
CPU  
FLASH interface  
FLASH memory  
Control signal  
CPU core  
Control signal  
Control signal  
A0 to A20  
A0 to A20  
Address  
DQ0 to DQ63  
64-bit  
DQ0 to DQ63  
Data  
32-bit  
Control  
signal  
Interface  
with  
FLASH  
writer  
(when in  
FLASH  
mode)  
Address  
Data  
16-bit  
994  
 
Chapter 54 Flash Memory  
3.Configuration  
3.1 Address conversion from CPU Mode to Flash Programming Mode  
Flash memory's address mapping is different depending on whether it is being accessed from the FR-CPU or  
parallel Flash programmer  
The following equations are an example to calculate a Flash programming mode address (FA) from a CPU  
mode address (addr) for the 64bit flash type with a memory size of 1088kB (16x64kB + 8x8kB), as used on  
MB91F467DA:  
SA0, SA2, SA4, SA6 (14:0000h ≤ addr ≤ 14:FFFFh; addr[2]=0):  
FA = addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 05:0000h  
SA1, SA3, SA5, SA7 (14:0000h ≤ addr ≤ 14:FFFFh; addr[2]=1):  
FA = addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 04:E000h  
SA8, SA10, SA12, SA14, SA16, SA18, SA20, SA22 (04:0000h ≤ addr ≤ 13:FFFFh; addr[2]=0):  
FA = addr - addr%02:0000h + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 + 0C:0000h  
SA9, SA11, SA13, SA15, SA17, SA19, SA21, SA23 (04:0000h ≤ addr ≤ 13:FFFFh; addr[2]=1):  
FA = addr - addr%02:0000h + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 + 0D:0000h  
For other flash memory sizes or types please see the related datasheets.  
995  
 
Chapter 54 Flash Memory  
4.Registers  
4. Registers  
For the description of the Flash related registers, refer to Chapter 11 Memory Controller (Page No.167).  
5. Access Modes  
This section describes the Flash memory access modes.  
5.1 Access from the FR-CPU  
The following three types of access mode are available:  
■ 64-bit CPU mode (read/execute), not for all devices  
This mode does not allow data erase/write. Data can only be accessed by the CPU in lengths of words (32  
bits) but is actually read from the Flash Memory in lengths of d-words (64 bits).  
Programs can be executed in Flash memory while this mode is enabled.  
• Specifying the mode  
Use the Flash setting procedure located in the Boot-ROM at address 0000:BF60 with R4 (2 bits) set to 1X to set this  
H
B
mode. Refer to Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM (Page No.983).  
• Description of operation  
When reading or executing code from the Flash memory area, data is read by the CPU in word (32-bit) length units but  
is actually read from memory in d-word (64-bit) length units.  
Running Auto Algorithms is not possible.  
■ 32-bit CPU mode (read/write/execute), write not for all devices  
This mode allows data erase/write. Data can only be accessed in lengths of words (32 bits).  
Programs cannot be executed in Flash memory while the Flash is being written/erased.  
• Specifying the mode  
Use the Flash setting procedure located in the Boot-ROM at address 0000:BF60 with R4 (2 bits) set to 00 to set this  
H
B
mode. Refer to Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM (Page No.983).  
Flash memory always goes to 32-bit mode after a reset is cleared, when the CPU is running.  
• Description of operation  
When reading or executing code from the Flash memory area, data is read from memory in word (32-bit) length units.  
Auto Algorithms can be run by writing commands to Flash memory. It is possible to erase/write to Flash memory by  
running an Auto Algorithm. See “7. Auto Algorithms (Page No.999)” for details about Auto Algorithms.  
■ 16-bit CPU mode (read/write)  
This mode allows data erase/write. Data can only be accessed in lengths of half-words (16 bits).  
Programs cannot be executed in Flash memory while this mode is enabled.  
• Specifying the mode  
Use the Flash setting procedure located in the Boot-ROM at address 0000:BF60 with R4 (2 bits) set to 01 to set this  
H
B
mode. Refer to Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM (Page No.983).  
• Description of operation  
When reading from the Flash memory area, data is read from memory in half-word (16-bit) length units.  
Auto Algorithms can be run by writing commands to Flash memory. It is possible to erase/write the Flash memory by  
running an Auto Algorithm. See “7. Auto Algorithms (Page No.999)” for details about Auto Algorithms.  
996  
   
Chapter 54 Flash Memory  
6.Flash Access Mode Switching  
6. Flash Access Mode Switching  
On MB91460 series flash devices it is possible to switch between different flash access modes. These modes are  
depending on device type.  
Device  
16bit access  
read/write  
read/write  
read/write  
read/write  
32bit access  
read/write  
read/write  
read  
64bit access  
MB91F467DA  
MB91F469GA  
MB91F464AA  
MB91F465KA  
read  
read  
-
-
read  
The 16bit mode is intended basically for flash programming, so program execution from flash is prohibited anyway.  
The 32bit and 64bit modes, however, are intended for program execution from flash. Since switching between  
these modes directly from an application located in the flash is prohibited it is necessary to locate the switching  
routine either in RAM or use the available routine in the Boot ROM:  
This routine is located at address 0xBF60 for all MB91F46x devices. To call this function two parameters are  
expected in CPU registers R4 and R5:  
R4: 2bits (LSB of register) for setting the flash access mode  
b’00: 32bit read/write mode  
b’01: 16bit read/write mode  
b’1x: 64bit read only mode  
R5: 16bits for setting wait time  
The wait time should be in the range of some 100ns after switching the flash access mode for stabilization of the  
Flash-ROM. The wait function is a simple delay loop that needs about 3 CPU cycles for one run. The value in R5  
represents the number of runs through this delay loop.  
Example (time for 1 run through delay loop):  
30 ns @ 100MHz CPU clock  
47 ns @ 64MHz CPU clock  
94 ns @ 32MHz CPU clock  
500 ns @ 2MHz CPU clock  
min. 4-5 runs  
min. 3 runs  
min. 2 runs  
min. 1 runs  
After leaving this delay loop, the switching function will return to the application.  
997  
 
Chapter 54 Flash Memory  
6.Flash Access Mode Switching  
6.1 Flash Memory Mode  
Resetting after setting the MD2, MD1 and MD0 pins to “1”, “1” and “1” will halt the MCU functions. At this time,  
the Flash memory's interface circuit functions are emabled for direct control of the Flash memory unit from  
external pins, by directly linking some of the signals to the Flash memory unit's control signal. In this mode, the  
Flash memory appears to the external pins as a stand-alone unit. This mode is generally set when writing/  
erasing using the parallel Flash programmer. In this mode, all operations of the Flash memory's Auto  
Algorithms are available.  
For correspondence between the MCU pins and Flash memory’s interface circuit in the flash parallel  
programming mode please check the related datasheets of each product.  
998  
Chapter 54 Flash Memory  
7.Auto Algorithms  
7. Auto Algorithms  
Writes and erases to Flash memory are performed by launching the Flash memory's own Auto Algorithms.  
7.1 Command Operation  
Auto Algorithms are launched by writing one to six half words (16 bits) to the Flash memory in succession.  
This is called a “command.” Writing an illegal address or data, or writing them in the incorrect order, will reset  
the Flash memory to read mode.  
Table 7-1 List of Commands in CPU mode  
4th Bus  
Read/write  
cycle  
1st Bus  
Write cycle  
2nd Bus  
Write cycle  
3rd Bus  
Write cycle  
5th Bus  
Write cycle  
6th Bus  
Write cycle  
Bus  
Write  
Cycle  
Command  
Sequence  
Address  
Data  
Address  
Data  
Address  
Data  
Address  
Data  
Address  
Data  
Address  
Data  
Read/  
reset  
*XXXX  
F0  
H
1
4
---  
---  
55  
---  
---  
F0  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
H
Read/  
Reset  
*x557  
H
AA  
*yAAF  
*x557  
RA  
RD  
H
H
H
H
H
*x557  
H
AA  
AA  
AA  
*yAAF  
*yAAF  
*yAAF  
55  
55  
55  
*x557  
*x557  
*x557  
A0  
80  
Writing  
4
6
6
PA  
PD  
AA  
AA  
---  
---  
55  
55  
---  
---  
10  
H
H
H
H
H
H
H
H
H
H
H
H
H
*x557  
H
*x557  
*x557  
*yAAF  
*x557  
H
Chip erase  
Sector erase  
H
H
H
H
H
H
H
H
H
*x557  
H
80  
H
*yAAF  
30  
SA  
H
”
H
Suspend erase during sector erase with input of Address= “*XXXX ”, data = “B0  
Sector erase suspend  
Sector erase resume  
H
H
Resume erase after Sector erase suspend, with input of Address= “*XXXX ”, data = “30  
”
H
H
Continuous  
mode  
*x557  
AA  
A0  
*yAAF  
PA  
55  
*x557  
20  
3
---  
---  
---  
---  
---  
---  
H
H
H
H
H
H
Continuous  
2
*XXXX  
*XXXX  
PD  
F0  
or  
00  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
---  
H
H
H
writing  
Continuous  
mode  
Reset  
H
90  
*XXXX  
H
2
H
H
Both word mode and half-word mode are the same for commands. Any data can be set in the non-specified bits.  
RA: Read address  
PA: Write address  
SA: Sector address (Specify any address in the sector)  
RD: Read data  
PD: Write data  
*: “0004”, “0005”, “0006”, “0007”, “0008”, “0009”, “000A”, “000B”, “000C”, “000D”, “000E”, “000F”, “0010”, “0011”, “0012”, “0013” or “0014”  
x: Any odd hex digit: “1“, “3“, “5“, “7“, “9“, “B“, “D“ or “F“  
y: Any even hex digit: “0“, “2“, “4“, “6“, “8“, “A“, “C“ or “E“  
• Auto Algorithm Execution Status  
If an Auto Algorithm is started in CPU mode, it is possible to learn the operational state of the Auto  
Algorithm via the internal ready signal (RDY). The level of the ready signal can be read from the “RDY” bit  
of the FLASH Memory Control Status Register.  
While the “RDY” bit is set to “0”, data read is the hardware sequence flag indicating Flash memory status  
(see Hardware sequence flag in (3) and (4)).  
999  
 
Chapter 54 Flash Memory  
7.Auto Algorithms  
7.2 Auto Algorithm Commands  
■ Read/reset command  
Issue a Read/reset command sequence to recover to read mode after a timing limit has been exceeded. Data  
is read from Flash memory via the read cycle. Flash memory stays in a read state until another command is  
input.  
When powered up, Flash memory is automatically set to read/reset. In this case, commands are not required  
for data reading.  
■ Program (write)  
In CPU programming mode, writes are performed in basic units of half words. Writes are performed in 4 bus  
operations. The command sequence as two “unlock” cycles, followed by a write setup command and write  
data cycle. Then, in the final write cycle, writing to memory starts.  
After the auto write algorithm command sequence is executed, Flash memory no longer requires external  
control. Flash memory generates appropriate write pulses that it has automatically created internally, and  
validates the margins of written cells. Auto write operation ends when the bit 7 data matches the data written  
to this bit via data polling (see (3) Hardware sequence flag). Flash memory then returns to read mode, and no  
longer accepts write addresses. As a result, at this time Flash memory requests the next valid address. Thus,  
data polling indicates that writing is ongoing.  
During writing, all commands written to Flash memory are ignored. If a hardware reset is started during writing,  
the data in addresses that have been written is not guaranteed. Data can be written to addresses in any order,  
and may also cross sector boundaries. Writing cannot return data “0” to data “1”. If data “1” is written to data  
“0”, then either the data polling algorithm will determine that the device is bad, or it will appear that data “1”  
has been written, but in reset/read mode, when the data is read, it will still be read as “0”. Only erase operation  
can change “0” data to “1” data.  
Figure 7-1 The Writing Sequence Using Write Commands  
Start write  
Write command sequence  
Device data polling  
No  
Last address?  
Next address  
YES  
Write finished  
1000  
Chapter 54 Flash Memory  
7.Auto Algorithms  
■ Chip erase  
Chip erase (erase all sectors at once) is performed via six accesses. First, there are two “unlock” cycles, after  
which a setup command is written. This is then followed by two more “unlock” commands before the chip  
erase command.  
The user does not have to write to Flash memory before a chip erase can be performed. While the auto erase  
algorithm is executing, Flash memory automatically validates each cell before erasing it by writing a “0” pattern  
(preprogram). During this operation, the Flash memory does not require external control.  
Auto erase begins with a write during the command sequence, and ends when “1” is written to bit 7, at which  
point the Flash memory returns to read mode. The time for chip erase is equal to [sector erase time] x [number  
of sectors] + [chip write time (preprogram)].  
The figure below shows the chip erase sequence using the chip erase command.  
■ Sector erase  
Sector erase is performed via six accesses. There are two “unlock” cycles, after which a “setup” command is  
written, followed by another two “unlock” cycles. On the sixth cycle, a sector erase command is input, starting  
the sector erase. From the time that the last sector-erase command is written until the timeout of 50us, the  
next sector-erase command will be accepted.  
It is possible to submit multiple sector erases simultaneously by writing the six bus cycles described above.  
This sequence is performed by writing the addresses of sectors to erase in succession after the sector-erase  
command (30H). After a timeout of 50us since the last sector-erase command was written, sector erase  
begins. In other words, to erase multiple sectors simultaneously, each sector must be entered within 50us of  
the other, after which commands may no longer be accepted. It is possible to monitor whether successive  
sector-erase commands are valid via bit 3 (see (3) Hardware sequence flag). After finishing, Flash memory  
returns to read mode. Other commands are ignored. Data polling works on any address in an erased sector.  
The time for multiple-sector erase is equal to ([sector erase time] + [sector write time (preprogram)]) x [number  
of sectors erased].  
Figure 7-2 Chip Erase Sequence Using the Chip erase Command  
Start erase  
Chip/sector erase  
command sequence  
Device data polling or  
toggle bit complete  
Write finished  
■ Erase suspend  
The erase suspend command allows the user to pause the Flash memory’s Auto Algorithm during sector  
erase, and read data from/write data to sectors not being erased. This command is only valid during sector  
erase. It is ignored during chip erase and write operations. The erase suspend command (B0H) is only valid  
during sector-erase operation, including the timeout period after a sector-erase command (30H). Entering this  
command during the timeout period immediately ends the timeout, and interrupts the erase operation. When  
the erase resume command is written, the erase operation resumes. Any address can be used for erase  
suspend and erase resume command input.  
If a erase suspend command is input during sector-erase operation, it will take up to 20us for the Flash  
memory to halt the erase operation. When the Flash memory goes into erase suspend mode, it outputs ready/  
busy and bit 7 outputs “1”, and bit-6 toggling is halted. It is possible to confirm whether the erase operation  
1001  
Chapter 54 Flash Memory  
7.Auto Algorithms  
has halted, by entering the address of an erased sector, and monitoring the values read from bits 6 and 7.  
Additionally, writes of erase-suspend commands are ignored. When erasing is halted, the Flash memory goes  
into erase-suspend read mode. In this mode, data reads from sectors where erase has not been paused are  
enabled, but for other sectors, it is the same as standard reading. While in erase-suspend read mode, when  
data is read sequentially from an erase-suspended sector, bit 2 is toggled (see (3) Hardware sequence flag for  
details).  
After entering erase-suspend read mode, the user can write to the Flash memory by writing a write command  
sequence. This mode is called “erase-suspend write mode”. In this mode, data writes to sectors where erase  
has not been paused are enabled, but for other sectors, it is the same as normal byte writing. While in erase-  
suspend write mode, when data is read sequentially from an erase-suspended sector, bit 2 is toggled. This  
mode can be detected via the erase-suspend bit (bit 6).  
A word of caution is required for using this mode: Although bit 6 can be read from any address, bit 7 must be  
read from a write address. To resume sector erase, a resume command must be entered (30H). At this point,  
further resume commands will be ignored. Conversely, it is possible to enter a erase-suspend command after  
the Flash memory resumes erasing.  
1002  
Chapter 54 Flash Memory  
7.Auto Algorithms  
7.3 Hardware Sequence Flag  
This Flash memory performs the write/erase sequence via Auto Algorithms. It thus has hardware for informing  
the outside world when it has finished internal operations.  
Hardware sequence flag  
The hardware sequence flag can be obtained as data by reading any address (an odd address during byte  
access) from the Flash memory while an Auto Algorithm is executing. Five of the retrieved bits of data are  
valid, each indicating the status of its corresponding Auto Algorithm.  
Figure 7-3 Hardware Sequence Flag Format  
bit 15  
When reading from hardware  
8 7  
0
0
(Indeterminate)  
Hardware sequence flag  
Hardware sequence flag  
bit  
7
When reading from byte (Odd address only)  
bit  
7
6
5
4
3
2
1
0
During  
(Indeterminate)  
(Indeterminate)  
(Indeterminate)  
DPOLL TOGGLE TLOVER  
SETIMR TOGGL2  
half-word  
byte access  
Note that these flags are meaningless in FR-CPU ROM mode. Read this data as a half-word or byte, and only  
in FR-CPU programming mode.  
Table 7-2 List of Hardware Sequence Flag States  
DPOLL  
(Bit 7)  
TOGGLE  
(Bit 6)  
TLOVER  
(Bit 5)  
SETIMR  
(Bit 3)  
TOGGL2  
(Bit 2)  
Status  
Auto write  
Inverted data Toggles  
0
0
0
1
1
Write/erase during auto-erase  
0
Toggles  
Toggles  
Read (sectors being  
erased)  
Executing  
1
1
0
0
Toggles  
Erase  
suspended  
(paused)  
Read (sectors not  
being erased)  
Data  
Data  
Data  
Data  
Data  
Write (sectors not  
being erased)  
Inverted data Toggles  
Inverted data Toggles  
0
1
1
0
0
1
1 (*1)  
1
Time  
limit  
exceeded  
Auto write  
Write/erase during auto-erase  
0
Toggles  
(*2)  
*1:During erase-suspend write mode, when an address that has been written to is read, bit 2 outputs logical  
“1”.  
When data is read sequentially from an erase-suspended sector, however, bit 2 is toggled.  
*2:When bit 5 is set to “1” (time limit exceeded), sequential reads of sectors being written to/erased toggle  
bit 2, while reads from other sectors will not toggle bit 2.  
• Ready/busy signal (RDY/BUSYX)  
In addition to the hardware sequence flag, the Flash memory has a ready/busy signal for indicating  
whether an internal Auto Algorithm is executing. This ready/busy signal can be connected to the Flash  
memory interface circuit, and read as the “RDY” bit of the FLASH Memory Control Status Register.  
Additionally, by starting up the ready/busy signal, it is possible to issue interrupt requests to the CPU  
(See “4. Registers (Page No.996)” for more information).  
Value “0” read from “RDY” bit: Flash memory is currently writing or erasing. At this time, write and  
erase commands are not accepted.  
Value “1” read from “RDY” bit: Flash memory is currently on standby for read/write or erase.  
1003  
Chapter 54 Flash Memory  
7.Auto Algorithms  
7.4 FLCR: Hardware Sequence Flag  
• FLCR: Address. Any address in Flash memory. (Access: Byte or half-word)  
7
6
5
4
-
3
2
1
-
0
-
bit  
DPOLL TOGGLE TLOVER  
SETIMR  
TOGGL2  
-
-
-
-
-
-
-
-
Initial value  
Attribute  
R
R
R
RX  
R
R
RX  
RX  
• bit 7: Data polling (DPOLL)  
• Auto write under way  
If data is read while the auto write algorithm is executing, the Flash memory outputs the data with the last  
value written to bit 7 inverted. If a read access is performed after the auto-write algorithm finishes, the  
Flash memory outputs the bit 7 of the address indicated by the address signal for the read data.  
• Auto erase under way  
If a read is performed while the auto-erase algorithm is executing, the Flash memory outputs “0”,  
regardless of the address indicated by the address signal. Similarly, upon termination it outputs “1”.  
• Sector erase suspend mode  
If a read is performed while in sector erase suspend mode, the Flash memory outputs “1” if the address  
indicated by the address signal belongs to a sector being erased. If it does not belong to the sector being  
erased, bit 7 of the value read from the address indicated by the address signal is output. Referring to  
this value while toggling bit 6 (described below) makes it possible to determine whether the current sector  
is in sector erase-suspend state, and which sectors are being erased.  
• Note that when the operation of an Auto Algorithm approaches termination, the value of bit 7 (data  
polling) changes asynchronously. This means that Flash memory sends the operating status to bit 7, then  
sends this data next. When the Flash memory terminates the Auto Algorithm, and also when it outputs  
data set in bit 7, the other bits are still undefined.  
• The defined data for other bits can be read by successfully executing reads.  
• bit 6: Toggle bit (TOGGLE)  
• Auto write/erase under way  
If successive reads are performed while the auto-write or erase algorithm is executing, the Flash memory  
outputs the result of toggling between “1” and “0” to bit 6. After the auto write or erase algorithm  
terminates, bit 6 stops toggling in response to successive reads, and outputs valid data.  
The toggle bit becomes effective after the final write cycle of the command sequence in question.  
Note that when writing, if an attempt is made to write to an overwrite-protected sector, toggling is  
performed for about 2us, after which toggling ends; the data is not overwritten. When erasing, if all  
selected sectors are write-protected, the toggle bit toggles for about 100us, the returns to read mode; the  
data is not overwritten.  
• Sector erase suspend mode  
If a read is performed while in sector erase suspend mode, the Flash memory outputs “1” if the address  
indicated by the address signal belongs to a sector being erased. If it does not belong to the sector being  
erased, bit 6 of the value read from the address indicated by the address signal is output.  
• bit 5: Timing limit exceeded (TLOVER)  
• Auto write/erase under way  
Bit 5 indicates that the Auto Algorithm has exceeded the length of time stipulated internally by the Flash  
memory (internal pulse count). In this state, bit 5 outputs “1”. In other words, if this flag outputs “1” while  
an Auto Algorithm is running, it means that the write or erase has failed.  
Attempts to write to bit 5, or an unerased non-flag area, will fail. When this happens, it will not be possible  
to read set data from bit 7 (data polling), and bit 6 (toggle bit) will remain toggled. If the time limit is  
exceeded while in this state, bit 5 outputs “1”. Note that this means that the Flash memory was not used  
properly; it does not mean that something is wrong with the Flash memory. If the Flash memory reaches  
this state, execute the reset command.  
1004  
Chapter 54 Flash Memory  
7.Auto Algorithms  
• bit 4: Undefined:  
The read value is indeterminate.  
• bit 3: Sector erase timer (SETIMR)  
• During sector erase  
After executing the first sector-erase command sequence, Flash memory goes into standby for sector  
erase. During this time, bit 3 is “0”. After the sector-erase wait period ends, it outputs “1”. The data-polling  
and toggle bits become enabled after the first sector-erase command sequence is executed.  
If the data-polling and toggle-bit functions set this flag to “1” while the erase algorithm is executing, it  
indicates that internally controlled erasing has begun. Until the data-polling or toggle bit indicates that the  
erase is finished, subsequent command writes are ignored (only the erase-suspend code is accepted). If  
this flag is “0”, the Flash memory will accept additional sector erase-code writes. It is recommended that  
you check this flag via the software before writing subsequent sector-erase codes, in order to confirm  
this. If the flag is “1” on the second status check, it is possible that additional sector-erase codes will not  
be accepted. If a read is performed while in sector erase suspend mode, the Flash memory outputs “1” if  
the address indicated by the address signal belongs to an erased sector. If it does not belong to an  
erased sector, bit 3 of the value read from the address indicated by the address signal is output.  
• bit 2: Toggle bit 2 (TOGGL2)  
• During sector erase  
This toggle bit is used in addition to the bit-6 toggle bit, in order to detect whether the Flash memory is  
performing auto erase, or erase is suspended. Bit 2 toggles if data is read repeatedly from an erased  
sector during auto erase. If Flash memory is in erase-suspend read mode, bit 2 will toggle if data is read  
repeatedly from a sector for which erase is suspended.  
If Flash memory is in erase-suspend write mode, “1” will be read from bit 2 if addresses are read  
repeatedly from a sector for which erase is not suspended. Unlike bit 2, bit 6 only toggles during normal  
writing and erasing, and erase-suspend write mode.  
For example, bits 2 and 6 are used together in order to detect erase-suspend read mode (bit 2 toggles,  
but bit 6 does not). Bit 2 is also used to detect erased sectors. When Flash memory is performing erase  
operation, this bit toggles if data is read from an erased sector.  
• bit 1-0: Undefined  
The read value is indeterminate.  
1005  
Chapter 54 Flash Memory  
7.Auto Algorithms  
7.5 Sample Use of Hardware Sequence Flag  
It is possible to determine the state of the Flash memory’s internal Auto Algorithms using the hardware  
sequence flag mentioned above. As an example, the figures below show the write/erase determination  
sequence when the data-polling function is used, and when the toggle-bit function is used.  
Figure 7-4 Write/erase Determination Sequence Using Data-polling Function  
Start write/erase  
VA = write address  
= Erased sector address during  
Read (D0 to D7)  
sector erase  
address = VA  
= Non-protected sector address  
during chip erase  
* : Since D7 changes at the same time  
as D5, even if D5 = "1", D7 must  
be rechecked.  
YES  
D7 = Data?  
NO  
NO  
D5 = 1?  
YES  
Read (D0 to D7)  
address = VA  
YES  
D7 = Data?  
*
NO  
Write/erase Pass  
Write/erase Fail  
Figure 7-5 Write/erase Determination Sequence Using Toggle-bit Function  
Start write/erase  
Read (D0 to D7)  
address = "H" or "L"  
NO  
D6 = Toggle?  
YES  
NO  
D5=1 ?  
YES  
Read (D0 to D7)  
address = "H" or "L"  
NO  
D6 = Toggle?  
*
YES  
Write/erase Fail  
Write/erase Pass  
* When D5 changes to "1", D6 stops toggling, so even if  
D5 = "1", D6 must be rechecked.  
1006  
Chapter 54 Flash Memory  
8.Caution  
8. Caution  
• Please review the MBM29LV400TC data sheet in conjunction with this document.  
• CPU mode  
When in CPU mode, the address-allocation method is different than when writing via a parallel Flash  
programmer. Refer to “3.1 Address conversion from CPU Mode to Flash Programming Mode (Page  
No.995)”.  
• Flash memory mode (writing via parallel Flash programmer)  
This Flash memory allows writing via an external device, by means of the parallel Flash programmer. In this  
state, pin functions equivalent to the stand-alone product MBM29LV400TC are assigned to the device's  
external pins, and operation of the CPU halts.  
In Flash memory mode, the address line connections are changed from CPU mode, to mapping within the  
memory area.  
• See the section in your parallel Flash programmer manual concerning the MBM29LV400TC or MB91460 for  
details about using Flash memory from a parallel Flash programmer.  
1007  
 
Chapter 54 Flash Memory  
8.Caution  
1008  
Chapter 55 Flash Security  
1.Overview  
Chapter 55 Flash Security  
1. Overview  
• Module for controlling the read and write access protection to the embedded Flash memory  
2. Features  
• Common read protection for all flash sectors depending on device mode  
• Individual write protection for each flash sector depending on device mode  
• Write protection level depending on device mode  
• Security vector re-fetch sequence (for security status update after chip erase)  
• CRC checksum calculation (CRC32/AAL5 algorithm)  
• CRC polygon is x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1  
1009  
       
Chapter 55 Flash Security  
3.Flash Security Vectors  
3. Flash Security Vectors  
3.1 Vector addresses  
Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1, BSV2)  
controlling the protection functions of the flash security module:  
FSV1: 0x14:8000 BSV1: 0x14:8004  
FSV2: 0x14:8008 BSV2: 0x14:800C  
Remark: The addresses of both boot security vectors and flash security vectors depend on the size and the  
data width configuration of the embedded flash memory. Therefore always check the appropriate datasheet if  
the addresses shown here are valid for the product you are using.  
3.2 Security Vector FSV1  
The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes and the  
individual write protection of the 8 kByte sectors.  
■ FSV1 (bits 31 to 16)  
The setting of the Flash Security Vector FSV1 bits [31:16] is responsible for the read and write protection  
modes.  
Explanation of the bits in the Flash Security Vector FSV1[31:16]:  
FSV1[31:19]  
FSV1[18]  
Write  
FSV1[17]  
Write  
FSV1[16]  
Read  
Flash Security Mode  
Protection  
Level  
Protection  
Protection  
set all to ‘0’  
set all to ‘0’  
set all to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘0’  
set to ‘1’  
Read Protection (all device modes, except  
INTVEC mode MD[2:0]=”000”)  
Write Protection (all device modes, without  
exception)  
Read Protection (all device modes, except  
INTVEC mode MD[2:0]=”000”) and Write  
Protection (all device modes)  
set all to ‘0’  
set all to ‘0’  
set all to ‘0’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘0’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘0’  
set to ‘1’  
Read Protection (all device modes, except  
INTVEC mode MD[2:0]=”000”)  
Write Protection (all device modes, except  
INTVEC mode MD[2:0]=”000”)  
Read Protection (all device modes, except  
INTVEC mode MD[2:0]=”000”) and Write  
Protection (all device modes except INTVEC  
mode MD[2:0]=”000”)  
1010  
 
Chapter 55 Flash Security  
3.Flash Security Vectors  
■ FSV1 (bits 15 to 0)  
The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write protection of the  
8 kByte sectors. It is only evaluated if write protection bit FSV1[17] is set.  
Explanation of the bits in the Flash Security Vector FSV1[15:0] (valid for MB91F467DA):  
FSV1 bit  
Sector  
Enable  
Write  
Disable  
Write  
Comment  
Protection  
Protection  
FSV1[0]  
FSV1[1]  
FSV1[2]  
FSV1[3]  
FSV1[4]  
FSV1[5]  
FSV1[6]  
FSV1[7]  
FSV1[8]  
FSV1[9]  
FSV1[10]  
FSV1[11]  
FSV1[12]  
FSV1[13]  
FSV1[14]  
FSV1[15]  
SA0  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
-
SA1  
SA2  
SA3  
SA4  
Write protection is mandatory !  
SA5  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
SA6  
SA7  
-
-
-
-
-
-
-
-
not available  
not available  
not available  
not available  
not available  
not available  
not available  
not available  
Remark: It is mandatory to always set the sector where the Flash Security Vectors FSV1 and FSV2 are  
located to write protected (here sector SA4). Otherwise it is possible to overwrite the Security Vector  
to a setting where it is possible to either read out the flash content or manipulate data by writing.  
Remark: The content of the security vector FSV1[15:0] depends on the size and the data width configuration  
of the embedded flash memory. Therefore always check the appropriate datasheet if the data shown here are  
valid for the product you are using.  
See Chapter 54 Flash Memory (Page No.993) for an overview about the sector organisation of the Flash  
Memory.  
1011  
Chapter 55 Flash Security  
3.Flash Security Vectors  
3.3 Security Vector FSV2  
The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write protection of the  
64 kByte sectors. It is only evaluated if write protection bit FSV1[17] is set.  
Explanation of the bits in the Flash Security Vector FSV2[31:0] (valid for MB91F467DA):  
FSV1 bit  
Sector  
Enable  
Write  
Disable  
Write  
Comment  
Protection  
Protection  
FSV2[0]  
SA8  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘0’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
set to ‘1’  
FSV2[1]  
SA9  
FSV2[2]  
SA10  
FSV2[3]  
SA11  
FSV2[4]  
SA12  
FSV2[5]  
SA13  
FSV2[6]  
SA14  
FSV2[7]  
SA15  
FSV2[8]  
SA16  
FSV2[9]  
SA17  
FSV2[10]  
FSV2[11]  
FSV2[12]  
FSV2[13]  
FSV2[14]  
FSV2[15]  
FSV2[16]  
FSV2[17]  
FSV2[18]  
FSV2[19]  
FSV2[20]  
FSV2[21]  
FSV2[22]  
FSV2[23]  
FSV2[24]  
FSV2[25]  
FSV2[26]  
FSV2[27]  
FSV2[28]  
FSV2[29]  
FSV2[30]  
FSV2[31]  
SA18  
SA19  
SA20  
SA21  
SA22  
SA23  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
not available  
not available  
not available  
not available  
not available  
not available  
not available  
not available  
not available  
not available  
not available  
not available  
not available  
not available  
not available  
not available  
Remark: The content of the security vector FSV2[31:0] depends on the size and the data width configuration  
of the embedded flash memory. Therefore always check the appropriate datasheet if the data shown here are  
valid for the product you are using.  
See Chapter 54 Flash Memory (Page No.993) for an overview about the sector organisation of the Flash  
Memory.  
1012  
Chapter 55 Flash Security  
4.Register  
4. Register  
4.1 Flash Security Control Register  
■ FSCR0: Address 7100h (Access: Byte (write), Word (read))  
31  
30  
29  
28  
27  
26  
25  
24  
bit  
CRC31/  
S7  
CRC30/  
S6  
CRC29/  
S5  
CRC28/  
S4  
CRC27/  
S3  
CRC26/  
S2  
CRC25/  
S1  
CRC24/  
S0  
Initial value (INIT pin input,  
watchdog reset)  
1
1
1
1
1
1
1
1
Initial value  
(Software reset)  
X
X
X
X
X
X
X
X
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
23  
22  
21  
20  
19  
18  
17  
16  
bit  
CRC23  
CRC22  
CRC21  
CRC20  
CRC19  
CRC18  
CRC17  
CRC16  
Initial value (INIT pin input,  
watchdog reset)  
1
1
1
1
1
1
1
1
Initial value  
(Software reset)  
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
Attribute  
15  
14  
13  
12  
11  
10  
9
8
bit  
CRC15  
CRC14  
CRC13  
CRC12  
CRC11  
CRC10  
CRC9  
CRC8  
Initial value (INIT pin input,  
watchdog reset)  
1
1
1
1
1
1
1
1
Initial value  
(Software reset)  
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
Attribute  
7
6
5
4
3
2
1
0
bit  
CRC7  
CRC6  
CRC5  
CRC4  
CRC3  
CRC2  
CRC1  
CRC0  
Initial value (INIT pin input,  
watchdog reset)  
1
1
1
1
1
1
1
1
Initial value  
(Software reset)  
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
• Bit31-24: Sequence activation  
S7-S0  
Function  
0xA5 -> 0x5A  
0xF0 -> 0X0F  
Start of a Flash Security Vector Re-Fetch Sequence (write only)  
Start of a Flash Memory CRC32 Checksum Sequence (write only)  
Continuously writing “A5 ”, “5A ” in the FSCR0[31:24] register will start a Flash Security Vector Re-fetch  
H
H
sequence immediately after writing “5A ”. There is no time restrictions between “A5 ” and “5A ”, but if “A5 ” is  
H
H
H
H
written followed by the one other than “5A ”, you should write “A5 ” again. If not, the Re-Fetch sequence  
H
H
cannot be started even if “5A ” is written.  
H
Continuously writing “F0 ”, “0F ” in the FSCR0[31:24] register will start a CRC32 checksum sequence  
H
H
immediately after writing “0F ”. There is no time restrictions between “F0 ” and “0F ”, but if “F0 ” is written  
H
H
H
H
followed by the one other than “0F ”, you should write “F0 ” again. If not, the CRC checksum sequence  
H
H
cannot be started even if “0F ” is written.  
H
1013  
 
Chapter 55 Flash Security  
4.Register  
Remark: The Flash Security Vector Re-Fetch sequence is especially intented to be used after a chip erase  
command to update the security status without the need of applying an external INITX reset or after changing  
the status of the FSV1 security vector.  
Remark: For both Security Vector Re-Fetch and CRC32 it is not recommended to start these sequences from  
programs located in the Flash Memory itself.  
Remark: Before starting the CRC32 checksum it is recommended to set the RC oscillation in the 2MHz  
operation mode to avoid long runtimes. See the RCSEL bit in Chapter 4.1 Clock Monitor Configuration  
Register (Page No.943).  
• Bit31-0: CRC32 checksum result  
CRC31-CRC0  
Function  
CRC32 Checksum (read only)  
This register contains the CRC32 checksum result after completion of the CRC32 checksum sequence (the  
sequence completion is indicated by FSCR1.RDY). The CRC checksum is calculated in a standard CRC32/  
AAL5 algorithm with the polygon x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1.  
■ FSCR1: Address 7104h (Access: Byte (read), Word (write))  
31  
-
30  
-
29  
-
28  
-
27  
-
26  
-
25  
-
24  
bit  
RDY  
Initial value (INIT pin input,  
watchdog reset)  
0
0
0
0
0
0
0
0
Initial value  
(Software reset)  
X
X
X
X
X
X
X
X
R
R0/WX  
R0/WX  
R0/WX  
R0/WX  
R0/WX  
R0/WX  
R0/WX  
Attribute  
23  
-
22  
-
21  
-
20  
-
19  
18  
17  
16  
bit  
CSZ3  
CSZ2  
CSZ1  
CSZ0  
Initial value (INIT pin input,  
watchdog reset)  
0
0
0
0
0
0
0
0
Initial value  
(Software reset)  
X
X
X
X
X
X
X
X
R0/WX  
R0/WX  
R0/WX  
R0/WX  
R/W  
R/W  
R/W  
R/W  
Attribute  
15  
14  
13  
12  
11  
10  
9
8
bit  
CSA15  
CSA14  
CSA13  
CSA12  
CSA11  
CSA10  
CSA9  
CSA8  
Initial value (INIT pin input,  
watchdog reset)  
0
0
0
0
0
0
0
0
Initial value  
(Software reset)  
X
X
X
X
X
X
X
X
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
7
6
5
4
3
2
1
0
bit  
CSA7  
CSA6  
CSA5  
CSA4  
CSA3  
CSA2  
CSA1  
CSA0  
Initial value (INIT pin input,  
watchdog reset)  
0
0
0
0
0
0
0
0
Initial value  
(Software reset)  
X
X
X
X
X
X
X
X
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Attribute  
(See “Meaning of Bit Attribute Symbols (Page No.10)” for details of the attributes.)  
1014  
Chapter 55 Flash Security  
4.Register  
• Bit31-25: Reserved bit. The read value is always “0”.  
• Bit24: RDY: CRC32 Sequence Ready  
RDY  
Function  
CRC32 sequence running or not yet started  
CRC32 sequence ready (data in the FSCR0 register is valid)  
0
1
• Bit23-20: Reserved bit. The read value is always “0”.  
• Bit19-16: CSZ3-0: CRC32 Size Mask  
CSZ3-0  
Function  
0000  
0001  
CRC32 sequence size mask is 4 kByte  
CRC32 sequence size mask is 8 kByte  
CRC32 sequence size mask is 16 kByte  
CRC32 sequence size mask is 32 kByte  
CRC32 sequence size mask is 64 kByte  
CRC32 sequence size mask is 128 kByte  
CRC32 sequence size mask is 256 kByte  
CRC32 sequence size mask is 512 kByte  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
CRC32 sequence size mask is 1024 kByte  
CRC32 sequence size mask is 2048 kByte  
CRC32 sequence size mask is 4096 kByte  
Not supported  
1001  
1010  
1011-1111  
Remark: CSZ3-0 is used as an OR-mask for the address given by CSA15-0. See address calculation below.  
• Bit15-0: CSA15-0: CRC32 Start Address  
This register contains the CRC32 startaddress which is aligned to 4kByte addresses. It is only possible to  
calculate the CRC32 checksum over addresses located in the Flash Memory address space. Other addresses  
are invalid and might lead to wrong checksums.  
Remark: The addresses to be written in this register are flash memory addresses like used in the flash parallel  
programming mode and not the mapped addresses which are used in CPU mode.  
■ Calculation of the CRC32 start- and end-address:  
The CSZ3-0 setting is first translated into a mask value:  
CSZ3-0  
0000  
MASK  
0000_0000_0000_0000  
0000_0000_0000_0001  
0000_0000_0000_0011  
0000_0000_0000_0111  
0000_0000_0000_1111  
0000_0000_0001_1111  
0000_0000_0011_1111  
0000_0000_0111_1111  
0000_0000_1111_1111  
and so on...  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001-1111  
CRC32 Startaddress = CSA[15:0] << 12 + 0x000  
CRC32 Endaddress = (CSA[15:0] or MASK ) << 12 + 0xFFF  
1015  
Chapter 55 Flash Security  
4.Register  
1016  
Chapter 56 Electrical Specification  
Chapter 56 Electrical Specification  
See the appropriate data sheet for the electrical specification of each device.  
1017  
 
Chapter 56 Electrical Specification  
1018  
FR60  
MB91460 Series Hardware Manual  
European Microcontroller Design Centre  
Author : MBo  
CM71-xxxxx-1E  
FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL  
FR60  
32-BIT MICROCONTROLLER  
MB91460 Series  
User's Manual  
Jan 2005 the zero edition  
Published FUJITSU LIMITED Electronic Devices  
Edited  
European Microcontroller Design Centre  

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