Application Note 42
Implementing the RC5040 and RC5042
DC-DC Converters on Pentium® Pro Motherboards
Introduction
PentiumPro and OverDrive®
Processor Power Requirements
This document describes how to implement a switching volt-
age regulator using an RC5040 or an RC5042 high speed
controller, a power inductor, a Schottky diode, appropriate
capacitors, and external power MOSFETs. This regulator
forms a step down DC-DC converter that can deliver up to
14.5A of continuous load current at voltages ranging from
2.1V to 3.5V. A specific application circuit, design consider-
ations, component selection, PCB layout guidelines and per-
formance evaluation procedures are covered in detail.
Use Intel’s AP-523 Application Note, Pentium® Pro
Processor Power Distribution Guidelines, November 1995
(order number 242764-001), as a basic reference. The speci-
fications contained in this document have been modified
slightly from the original Intel document to include updated
specifications for Pentium Pro microprocessors. Please con-
tact Intel Corporation for specific details.
Input Voltages
In the past 10 years, microprocessors have evolved at such an
exponential rate that a modern chip can rival the computing
power of a mainframe computer. Such evolution has been
possible because of the increasing numbers of transistors that
processors integrate. Pentium CPUs, for example, integrate
well over 5 million transistors on a single piece of silicon.
Available inputs are +5V ±5% and +12V ±5%. Raytheon
Electronics’ DC-DC converters may use either or both
inputs. Their input voltage requirements are listed in Table 1.
Table 1. Input Voltage Requirements
Controller
MOSFET
Drain
MOSFET
Gate Bias
To integrate so many transistors on a piece of silicon, their
physical geometry has been reduced to the sub-micron level.
As a result of each geometry reduction, the corresponding
operational voltage for each transistor has also been reduced.
This changing voltage for the CPU demands the design of a
programmable power supply—a design that is not com-
pletely re-engineered with every change in CPU voltage.
Part #
V
CC
RC5040
RC5042
+5V ±5%
+5V ±5%
+5V ±5% or
12V ±5%
RC5043
+5V ±5%
12V ±5%
12V ±5%
Pentium Pro DC Power Requirements
Refer to Table 2 for the power supply specifications for
Pentium Pro and Overdrive Processors. For a motherboard
design without a standard Voltage Regulator Module (VRM)
socket, the on-board DC-DC converter must supply a mini-
mum I P current of 13.9A at 2.5V and 12.4A at 3.3V. For a
CC
flexible motherboard design, the on-board converter must be
The operational voltage of CPUs has shown a downwards
trend for the past 5 years: from 5V for the x386 and x486, to
3.3V for Pentium, and 3.1V for Pentium Pro. Furthermore,
emerging chip technologies may require operating voltages
as low as 2.5V. With this trend in mind, Raytheon Electron-
ics has designed the RC5040 and RC5042 controllers. These
controllers integrate the necessary programmability to
address the changing power supply requirements of lower
voltage CPUs.
able to supply 14.5A maximum I P.
CC
DC Voltage Regulation
As indicated in Table 2, the voltage level supplied to the
CPU must be within ±5% of its nominal setting. Voltage
regulation limits must include:
Previous generations of DC-DC converter controllers were
designed with fixed output voltages adjustable only with a
set of external resistors. In a high volume production envi-
ronment (such as with personal computers), however, a CPU
voltage change requires a CPU board re-design to accommo-
date the new voltage requirement. The integrated 4-bit DAC
in the RC5040 and the RC5042 reads the voltage ID code
from the Pentium Pro microprocessor and configures the sys-
tem to provide the appropriate voltage. In this manner, the
PC board does not have to be re-designed each time the CPU
voltage changes. The CPU can thus automatically configure
its own required voltage.
• Output load ranges specified in Table 2
• Output ripple/noise
• DC output initial voltage set point
• Temperature and warm up drift (Ambient +10°C to +60°C
at full load with a maximum rate of change of 5°C per 10
minutes minimum but no more than 10°C per hour)
• Output load transient with:
Slew rate >30A/µs at the converter pins
Range: 0.3A – I P Max (as defined in Table 2).
CC
Rev. 1.1.0
APPLICATION NOTE
AN42
The RC5040 and RC5042 Controllers
RC5040 and RC5042 Description
The RC5040 is a programmable synchronous-mode DC-DC
converter controller. The RC5042 is a non-synchronous ver-
sion of the RC5040. When designed with the appropriate
external components, either device can be configured to
deliver more than 14.5A of output current. During heavy
loading conditions, these controllers function as current-
mode PWM step-down regulators. Under light loads, they
function in PFM (pulse frequency modulation) or pulse skip-
ping mode. The controllers sense the load level and switch
between the two operating modes automatically, thus opti-
mizing efficiency under all loads. The key differences
between the RC5040 and RC5042 are listed in Table 4.
Simple Step-Down Converter
S1
L1
+
VIN
D1
C1
RL Vout
–
65-AP42-01
Figure 1. Simple Buck DC-DC Converter
Figure 1 illustrates a step-down DC-DC converter with no
feedback control. The basic step-down converter serves as
the basis for deriving the design equations for the RC5040
and RC5042. From Figure 1, the basic operation begins by
closing the switch S1, so that the input voltage V is
IN
impressed across inductor L1. The current flowing through
this inductor is given by the following equation:
Table 4. RC5040 and RC5042 Differences
RC5040
RC5042
Operation
Package
Synchronous Non-Synchronous
20-pin SOIC
Yes
16-pin SOIC
No
Output Enable/
Disable
(V – V
)T
OUT ON
IN
I
= -----------------------------------------------
L
L1
Refer to the RC5040 Block Diagram illustrated in Figure 2.
The control loop of the regulator contains two main sections:
the analog control block and the digital control block. The
analog block consists of signal conditioning amplifiers feed-
ing into a set of comparators which provide the inputs to the
digital block. The signal conditioning section accepts inputs
from the IFB (current feedback) and VFB (voltage feedback)
pins and sets two controlling signal paths. The voltage con-
trol path amplifies the VFB signal and presents the output to
one of the summing amplifier inputs. The current control
path takes the difference between the IFB and VFB and pre-
sents the result to another input of the summing amplifier.
These two signals are then summed together with the slope
compensation input from the oscillator. This output is then
presented to a comparator, which provides the main PWM
control signal to the digital control block.
where T is the duty cycle (the time when S1 is closed).
ON
When S1 opens, the diode D1 conducts the inductor
current and the output current is delivered to the load accord-
ing to the following equation:
V
(T – T
L1
)
ON
OUT
S
I
= -------------------------------------------
L
where T is the overall switching period and (T – T ) is
S
S
ON
the time during which S1 is open.
By solving these equations you can obtain the basic relation-
ship for the output voltage of a step-down converter:
T
ON
----------
V
= V
IN
OUT
T
The additional comparators in the analog control section sets
the threshold for when the RC5040 enters PFM mode during
light loads and the point when the current limit comparator
disables the output drive signals to the MOSFETs.
S
In order to obtain a more accurate approximation for V
,
OUT
we must also include the forward voltage V across diode
D
D1 and the switching loss, V . After taking into account
SW
these factors, the new relationship becomes:
The digital control block is designed to take the comparator
inputs along with the main clock signal from the oscillator
and provide the appropriate pulses to the HIDRV and
LODRV pins that control the external power MOSFETs. The
digital section was designed utilizing high speed Schottky
transistor logic, thus allowing the RC5040 to operate at clock
speeds as high as 1MHz.
T
ON
----------
V
= (V + V – V
)
– V
D
OUT
IN
D
SW
T
S
Where V
SW
= I • R .
DS,ON
L
3
AN42
APPLICATION NOTE
Main Control Loop
RC5040
+5V
VIN
OSCILLATOR
–
+
–
+
–
+
VO
–
+
DIGITAL
CONTROL
1.24V
REFERENCE
4-BIT
DAC
VREF
POWER
GOOD
PWRGD
65-5040-01
VID0
VID1
VID2
VID3
Figure 2. RC5040 Block Diagram
High Current Output Drivers
Power Good (PWRGD)
The RC5040 contains two identical high current output
drivers that use high speed bipolar transistors in a push-pull
configuration. Each driver is capable of delivering 1A of cur-
rent in less than 100ns. Each driver’s power and ground are
separated from the chip power and ground for additional
switching noise immunity. The HIDRV driver’s power sup-
ply, VCCQP, is boot-strapped from a flying capacitor as
illustrated in Figure 3. Using this configuration, C12 is
charged from VCC via the Schottky diode DS2 and boosted
when the FET is turned on. This scheme provides a VCCQP
voltage equal to 2•VCC – VDS(DS2), or approximately 9.5V
when VCC = 5V. This voltage is sufficient to provide the 9V
gate drive to the MOSFET that is required to achieve a low
RDS(ON). Since the low side synchronous FET is referenced to
ground (see Figure 4), boosting the gate drive voltage is not
needed and the VCCP power pin can be tied to VCC.
Refer to Typical Operating Characteristics of the RC5040
data sheet for a full load VCCQP waveform.
The RC5040 and RC5042 Power Good function has been
designed according to Intel’s Pentium Pro DC-DC converter
specification. The Power Good function provides a constant
voltage monitor on the VFB pin. The internal circuitry of the
converter compares the VFB signal to the VREF voltage and
outputs an active-low interrupt signal to the CPU when the
power supply voltage exceeds ±7% of its nominal setpoint.
The Power Good flag provides no other control function to
the RC5040.
Output Enable (OUTEN)
Intel specifications state that the DC-DC converter should
accept an open collector signal for controlling the output
voltage. A logic LOW for this signal disables the output volt-
age. When disabled, the PWRGD output is in the low state.
This feature is available for the RC5040 only.
Upgrade Present (UP#)
Intel specifications state that the DC-DC converter must
accept an open collector signal that indicates the presence of
an upgrade processor. The typical state is high (for a stan-
dard P6 processor). When the signal is low or in theground
state (for the OverDrive processor), the output voltage must
be disabled unless the converter can supply the OverDrive
processor’s power requirements. When disabled, the
PWRGD output must be in the low state. Because the
RC5040 and RC5042 can supply the OverDrive processor
requirements, the UP# signal is not required.
Internal Voltage Reference
The reference used in the RC5040 is a precision band-gap
voltage reference, with internal resistors precisely trimmed
to provide a near zero temperature coefficient, TC. Added to
the reference voltage is the output from a 4-bit DAC. The
DAC is provided meet Pentium Pro specifications, requiring
a programmable converter output via a 4-bit voltage identifi-
cation (VID) code. This code scales the output voltage from
2.0V (no CPU) to 3.5V in 100mV increments. To guarantee
stable operation under all loads, a 10KΩ pull-up resistor and
0.1µF of decoupling capacitance should be connected to the
VREF pin. No load should be imposed on this pin.
4
APPLICATION NOTE
AN42
In general, a lower operating frequency increases the peak
Over-Voltage Protection
ripple current flowing through the output inductor, allowing
the use of a larger inductor value. Operation at lower fre-
quencies increases the amount of energy storage that the
bulk output capacitors must provide during load transients
that occur due to the slower loop response of the controller.
The RC5040 and RC5042 constantly monitor the output
voltage for protection against over voltage. If the voltage at
the VFB pin exceeds 20% of the selected program voltage,
an over-voltage condition is assumed, and the controller dis-
ables the output drive signal to the external MOSFET(s).
In addition, note that the efficiency losses due to switching
are relatively fixed per switching cycle. Therefore, as the
switching frequency increases, the contribution toward effi-
ciency due to switching losses also increases.
Short Circuit Protection
A current sense methodology is implemented to disable the
output drive signal to the MOSFET(s) when an over-current
condition is detected. The voltage drop created by the output
current flowing across a sense resistor is presented to an
internal comparator. When the voltage developed across the
sense resistor exceeds the comparator threshold voltage,
the controller disables the output drive signal to the
MOSFET(s).
RC5040 has an optimal operating frequency of 650KHz.
This frequency allows the use of smaller inductive and
capacitive components while optimizing peak efficiency
under all operating conditions.
Design Considerations and
Component Selection
The DC-DC converter returns to normal operation after the
fault has been removed, for either an over voltage or a short
circuit condition.
Application Circuits
Oscillator
Figure 3 illustrates a typical non-synchronous application
using the RC5040. Figure 4 shows a typical synchronous
application using the RC5040, and Figure 5 shows a typical
non-synchronous application using the RC5042.
The RC5040 oscillator section is implemented using a
fixed current capacitor charging configuration. An external
capacitor (CEXT) is used to preset the oscillator frequency
between 200KHz and 1MHz. This allows maximum flexibil-
ity in setting the switching frequency and in choosing exter-
nal components.
L2
VCC
2.6µH
C5
C4
C3
C1
C2
0.1µF
0.1µF
1000µF 1000µF
1000µF
DS2
C9
C8
1N5817
0.1µF
0.1µF
M1
M2
C12
2SK1388
11
12
10
9
8
7
6
5
4
3
2
1
1µF
2SK1388
L1
R
13
14
15
SENSE
R7
VO
10K
1.3µH
8mΩ
C6
RC5040
4.7µF
16
17
18
19
20
VREF
GND
C7
DS1
MBR1545CT
0.1µF
C
EXT
39pF
10K
10K
10K
10K
R1
VID3
VID2
VCC
R2
R3
R4
R6
10K
PWRGD
VID1
VID0
65-AP42-03
C11
0.22µF
VCC
R5
10K
OUTEN
C10
0.1µF
Figure 3. Non-Synchronous DC-DC Converter Application Schematic Using RC5040
5
AN42
APPLICATION NOTE
L2
VCC
2.6µH
C4
C1
C2
C5
C3
0.1µF
0.1µF
1000µF
1000µF
1000µF
DS2
C9
C8
1N5817
0.1µF
0.1µF
M1
M2
C12
2SK1388
11
12
13
14
15
10
9
8
7
6
5
1µF
2SK1388
L1
R
SENSE
R7
VO
10K
1.3µH
8mΩ
C6
4.7µF
RC5040
16
17
18
19
20
VREF
4
3
2
1
M3
2SK1388
C7
DS1
1N5817
0.1µF
GND
C
EXT
39pF
10K
10K
10K
10K
R1
VID3
VCC
R2
R3
R4
R6
VID2
10K
PWRGD
VID1
VID0
65-AP42-04
C11
VCC
0.22µF
R5
10K
OUTEN
C10
0.1µF
Figure 4. Synchronous DC-DC Converter Application Schematic Using RC5040
L2
2.6µH
VCC
C4
C5
C3
C1
C2
0.1µF
0.1µF
1000µF 1000µF
1000µF
DS2
C9
C8
1N5817
0.1µF
0.1µF
M2
C12
2SK1388
M1
1µF
2SK1388
L1
R
9
10
11
12
8
7
6
5
SENSE
R7
VO
1.3µH
10K
8mΩ
C6
4.7µF
VREF
GND
RC5042
4
3
2
1
13
14
15
16
DS1
C7
MBR1545CT
0.1µF
C
EXT
39pF
10K
10K
10K
10K
R1
R2
R3
R4
VID3
VCC
R6
10K
VID2
65-AP42-05
PWRGD
VID1
VID0
C11
0.22µF
VCC
C10
0.1µF
Figure 5. Non-Synchronous DC-DC Converter Application Schematic Using RC5042
6
APPLICATION NOTE
AN42
• Power package with low thermal resistance
• Drain current rating of 20A minimum
• Drain-Source voltage > 15V.
MOSFET Selection
This application requires the use of N-channel, Logic Level
Enhancement Mode Field Effect Transistors. The desired
characteristics of these components are:
The on-resistance (R ) is the main parameter for MOS-
DS,ON
FET selection. It determines the MOSFET’s power dissipa-
tion, thus significantly affecting the efficiency of the
converter. Several suitable MOSFETs are shown in Table 5.
• Low Static Drain-Source On-Resistance
R
< 37 mΩ (lower is better)
DS,ON
• Low gate drive voltage, V ≤ 4.5V
GS
Table 5. MOSFET Selection Table
R
DS,ON
(mΩ)
Thermal
1
Manufacturer & Model #
Conditions
T = 25°C
Typ.
25
Max.
P ackage Resistance
Fuji
2SK1388
V
D
= 4V
37
—
20
34
15
TO-220
Φ
Φ
= 75
= 50
GS
I = 17.5A
J
JA
JA
T = 125°C
J
37
Siliconix
SI4410DY
V
= 4.5V
T = 25°C
J
16.5
28
SO-8
(SMD)
GS
I = 5A
D
T = 125°C
J
National Semiconductor
NDP706AL
V
= 5V
T = 25°C
J
13
TO-220
Φ
= 62.5
JA
GS
I = 40A
Φ
= 1.5
D
JC
NDP706AEL
National Semiconductor
NDP603AL
T = 125°C
20
31
42
22
33
6
24
40
54
25
40
9
J
V
D
= 4.5V
T = 25°C
J
TO-220
TO-220
TO-263
Φ
= 62.5
JA
GS
I = 10A
T = 125°C
J
Φ
= 2.5
JC
National Semiconductor
NDP606AL
V
= 5V
T = 25°C
J
Φ
JA
= 62.5
GS
I = 24A
D
T = 125°C
J
Φ
= 1.5
JC
Motorola
V
= 5V
T = 25°C
J
Φ
JA
= 62.5
GS
I = 37.5A
D
2
MTB75N03HDL
Int. Rectifier
T = 125°C
J
9.3
—
—
—
14
28
46
19
31
(D PAK)
Φ
= 1.0
JC
V
= 5V
T = 25°C
J
TO-220
TO-220
Φ
JA
= 62.5
GS
I = 31A
D
IRLZ44
T = 125°C
J
Φ
= 1.0
JC
Int. Rectifier
V
= 4.5V
T = 25°C
J
Φ
JA
= 62.5
GS
I = 28A
D
IRL3103S
T = 125°C
J
Φ
= 1.0
JC
Note:
1. R
) values at Tj = 125°C for most devices were extrapolated from the typical operating curves supplied by the manufac-
DS(ON
turers and are approximations only.
Two MOSFETs in Parallel
We recommend two MOSFETs used in parallel instead of a
single MOSFET. The following significant advantages are
realized using two MOSFETs in parallel:
• No added heat sink required.
With the power dissipation down to around one watt and
with MOSFETs mounted flat on the motherboard, no
external heat sink is required. The junction-to-case
thermal resistance for the MOSFET package (TO-220) is
typically at 2°C/W and the motherboard serves as an
excellent heat sink.
• Significant reduction of power dissipation.
Maximum current of 14A with one MOSFET:
2
P
= (I R
)(Duty Cycle) =
DS,ON
MOSFET
2
• Higher current capability.
(14) (0.050*)(3.3+0.4)/(5+0.4-0.35) = 7.2 W
With thermal management under control, this on-board
DC-DC converter can deliver load currents up to 14.5A
with no performance or reliability concerns.
With two MOSFETs in parallel:
2
P
= (I R
)(Duty Cycle) =
DS,ON
MOSFET
2
(14/2) (0.037*)(3.3+0.4)/(5+0.4-0.35) = 1.3W/FET
*
Note: R
increases with temperature. Assume R
= 25mΩ
can easily increase to 50mΩ at high temperature
DS,ON
DS,ON
at 25°C. R
DS,ON
when using a single MOSFET. When using two MOSFETs in
parallel, the temperature effects should not cause the R
to rise
DS,ON
above the listed maximum value of 37mΩ.
7
AN42
APPLICATION NOTE
12V Gate Bias
MOSFET Gate Bias
Figure 7 illustrates how an external 12V source can be used
to bias VCCQP. A 47 Ω resistor is used to limit the transient
current into the VCCQP pin, and a 1µF capacitor filter is
used to filter the VCCQP supply. This method provides a
The MOSFET(s) can be biased using one of two methods:
Charge Pump or 12V Gate Bias.
Charge Pump (or Bootstrap)
higher gate bias voltage (V ) to the MOSFET, and there-
GS
Figure 6 employs a charge pump to provide the MOSFET
gate bias. The charge pump capacitor, CP, is used as a flying
capacitor to boost the voltage of the RC5040 or RC5042 out-
put driver. When the MOSFET switches off, the source of the
MOSFET is at -0.6V. VCCQP is charged through the Schot-
tky diode to 4.5V. Thus, the capacitor CP is charged to 5V.
When the MOSFET turns on, the source of the MOSFET is
at approximately 5V. The capacitor voltage follows, and
hence provides a voltage at VCCQP equal to 10V. The Schot-
tky is required to provide the charge path when the MOSFET
is off, and then reverses bias when the VCCQP goes to 10V.
The capacitor CP needs to be a high Q and high frequency
capacitor. A 1µF ceramic capacitor is recommended here.
fore reduces the R
DS,ON
MOSFET. Figure 8 illustrates how R
and resulting power loss within the
decreases dra-
DS,ON
matically as V increases. A 6.2V Zener (DS2) is used to
GS
clamp the voltage at V
CCQP
to a maximum of 12V and
ensure that the absolute maximum voltage of the IC is not
exceeded.
Warning: The 12V Gate Bias method applies only to the
RC5042. The RC5040 has not been designed to accept an
external 12V gate bias voltage, and may be damaged if
this method is used.
+5V
+5V
47Ω
+12V
D1
DS2
6.2V
VCCQP
M1
VCCQP
M1
HIDRV
HIDRV
CP
L1
RS
L1
RS
VO
PWM/PFM
Control
VO
PWM/PFM
Control
CB
DS1
CB
DS1
65-AP42-06
65-AP42-07
Figure 6. Charge Pump Configuration
Figure 7. 12V Gate Bias Configuration
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
R(DS)Fuji
R(DS)Fuji
R(DS)706A
R(DS)-706AEL
1.5
2
2.5
3
3.5
4
5
6
7
8
9
10
11
Gate-Source Voltage, V
(V)
GS
Figure 8. R
DS,ON
vs. V for Selected MOSFETs
GS
8
APPLICATION NOTE
AN42
Converter Efficiency
Losses due to parasitic resistance in the switches, inductor,
and sense resistor dominate at high load-current levels. The
major loss mechanisms under heavy loads, in order of
importance, are:
• Sense Resistor Losses
• Gate-Charge Losses
• Diode-Conduction Losses
• Transition Losses
• Input Capacitor Losses
• Losses Due to the Operating Supply Current of the IC.
2
• MOSFET I R Losses
• Inductor Losses
Efficiency of the converter under heavy loads can be calculated as follows:
× V
P
I
OUT
OUT
OUT
Efficiency = ------------- = -------------------------------------------------------- ,
p
I
× V
+ P
OUT LOSS
IN
OUT
where P
= PD
+ PD
+ PD
+ PD
+ PD
+ PD
+ PD
+ PD
CAP IC
LOSS
MOSFET
INDUCTOR
RSENSE
GATE
DIODE
TRAN
Design Equations:
V
+ V
D
2
OUT
(1) PD
(2) PD
= I
× R
× DutyCycle , whereDutyCycle = -----------------------------------------
DS,ON
MOSFET
OUT
V
+ V – V
SW
IN
D
2
= I
× R
INDUCTOR
INDUCTOR
OUT
2
(3) PD
(4) PD
= I
× R
OUT SENSE
RSENSE
= q
× f × 5V , where q
is the gate charge and f is the switching frequency
GATE
GATE
GATE
(5) PD
= V × I (1 – DutyCycle)
DIODE
f
D
2
IN
V
× C
× I
× f
LOAD
RSS
(6) PD
(7) PD
= ------------------------------------------------------------- , where C
is the reverse transfer capacitance of the high-side MOSFET.
RSS
TRAN
CAP
I
DRIVE
2
= I
× ESR
RMS
(8) PD = V × I
IC
CC
CC
Example:
3.3 + 0.5
DutyCycle = ----------------------------- = 0.73
5 + 0.5 – 0.3
2
PD
PD
= 10 × 0.030 × 0.73 = 2.19W
MOSFET
2
= 10 × 0.010 = 1W
INDUCTOR
2
PD
PD
PD
= 10 × 0.0065 = 0.65W
RSENSE
= CV × f × 5V = 1.75nf × (9 – 1)V × 650Khz × 5V = 0.045W
GATE
= 0.5 × 10(1 – 0.73) = 1.35W
DIODE
2
5 × 400pf × 10 × 650khz
----------------------------------------------------------------
0.7A
PD
PD
=
∼ 0.010W
TRAN
2
= (7.5 – 2.5) × 0.015 = 0.37W
CAP
PD = 0.2W
IC
9
AN42
APPLICATION NOTE
PD
= 2.19W + 1.0W + 0.65W + 0.045W + 1.35W + 0.010W + 0.37W + 0.2W = 5.815W
LOSS
3.3 × 10
---------------------------------------
∴ Efficiency =
≈ 85%
3.3 × 10 + 5.815
Table 6. RC5040 and RC5042 Short Circuit Comparator
Threshold Voltage
Selecting the Inductor
Selecting the right inductor component is critical in the
DC-DC converter application. The inductor’s critical param-
eters to consider are inductance (L), maximum DC current
Short Circuit Comparator
V
(mV)
threshold
(I ), and coil resistance (R ).
O
l
Typical
Minimum
Maximum
120
100
The inductor core material is crucial in determining the
amount of current it can withstand. As with all engineering
designs, tradeoffs exist between various types of core mate-
rials. In general, Ferrites are popular due to their low cost,
low EMI properties, and high frequency (>500KHz) charac-
teristics. Molypermalloy powder (MPP) materials exhibit
good saturation characteristics, low EMI, and low hysteresis
losses; however, they tend to be expensive and more effec-
tively utilized at operating frequencies below 400KHz.
140
When designing the external current sense circuitry, pay
careful attention to the output limitations during normal
operation and during a fault condition. If the short circuit
protection threshold current is set too low, the converter may
not be able to continuously deliver the maximum CPU load
current. If the threshold level is too high, the output driver
may not be disabled at a safe limit and the resulting power
dissipation within the MOSFET(s) may rise to destructive
levels.
Another critical parameter is the DC winding resistance of
the inductor. This value should typically be as low as possi-
ble because the power loss in DC resistance degrades the
The design equation used to set the short circuit threshold
limit is as follows:
2
efficiency of the converter by P
LOSS
= I x R . The value
O
l
of the inductor is a function of the oscillator duty cycle
(T ) and the maximum inductor current (I ). I can be
V
th
ON
PK PK
--------
R
=
, where: I = output short circuit current
SENSE
SC
calculated from the relationship:
I
SC
(I – I
)
min
pk
V
– V
– V
SW D
I
≥ I
= I
+ ----------------------------
Load, max
IN
SC
inductor
-----------------------------------------
I
= I
+
T
ON
2
PK
MIN
L
where I and I
are peak ripple currents and
is the maximum output load current.
pk min
Where T
ON
forward voltage of diode DS1.
is the maximum duty cycle and V is the
D
I
load, max
You must also take into account the current (I –I ), or
pk min
The inductor value can be calculated using the following
relationship:
the ripple current flowing through the inductor under normal
operation. Figure 9 illustrates the inductor current waveform
for the RC5040 and RC5042 DC-DC converters at maxi-
mum load.
V
– V
– V
SW O
IN
-----------------------------------------
L =
T
ON
I
– I
MIN
PK
I
pk
Where V
(R x I ) is the drain-to-source voltage of
SW DS,ON
O
M1 when it is turned on.
I
(I – I
pk
)/2
min
Implementing Short Circuit Protection
ILOAD, MAX
t
I
min
Intel currently requires all power supply manufacturers
to provide continuous protection against short circuit
conditions that may damage the CPU. To address this
requirement, Raytheon Electronics has implemented a cur-
rent sense methodology on the RC5040 and RC5042 con-
trollers. This methodology limits the power delivered to the
load during an overcurrent condition. The voltage drop cre-
ated by the output current flowing across a sense resistor is
presented to one terminal of an internal comparator with
hysterisis. The other comparator terminal has a threshold
voltage, nominally 120mV. Table 6 states the limits for the
comparator threshold of the switching regulator:
TON
TOFF
T = 1/f
s
Figure 9. Typical DC-DC Converter
Inductor Current Waveform
The calculation of this ripple current is as follows:
(V –V – V (V + V )
)
(I – I
)
min
IN
SW
OUT
OUT
D
pk
------------------------------------------------ ---------------------------------------------
T
---------------------------- =
×
L
(V – V + V )
IN SW
2
D
10
APPLICATION NOTE
AN42
(IPK – Imin
)
where:
ISC ≥ Iinductor = ILoad, max + ----------------------------- = 14.5 + 1 = 15.5A
2
•
•
•
•
V
V
V
= Input Voltage to the Converter
= Voltage Across the MOSFET = I
LOAD
= Forward Voltage of the Schottky Diode
IN
SW
D
For continuous operation at 14.5A, the short circuit detection
threshold must be at least 15.5A.
x R
DS,ON
T = The Switching Period of the Converter = 1/fS,
Where f = Switching Frequency.
The next step is to determine the value of the sense resistor.
Including tolerance, the sense resistor value can be approxi-
mated as follows:
S
For an input voltage of 5V, an output voltage of 3.3V, an
Vth,min
Vth,min
inductor value of 1.3µH, and a switching frequency of
----------------
ISC
----------------------------------
1.0 + ILoad,max
RSENSE
=
× (1 – TF) =
× (1 – TF)
650KHz (using C
EXT
= 39pF), the inductor current can be
calculated as follows:
where TF = Tolerance Factor for the sense resistor.
(I – I
)
min
(5.0 – 14.5 × 0.037 – 3.3)
pk
-------------------------------------------------------------
---------------------------- =
×
–6
2
Several different types of sense resistors exist. Table 7
describes tolerance, size, power capability, temperature
coefficient and cost of various sense resistors.
1.3 × 10
(3.3 + 0.5)
1
-------------------------------------------------------------- -----------------------
×
= 1.048A
3
(5.0 – 14.5 × 0.037 + 0.5)
650 × 10
Therefore, for a continued load current of 14.5A, the peak
current through the inductor, I , is found to be:
pk
Table 7. Comparison of Sense Resistors
Discrete Metal
Strip Surface
Mount Resistor
(Dale)
Discrete
CuNi Alloy
Wire Resistor
(Copel)
Discrete Iron
Alloy
Resistor (IRC)
Discrete MnCu
Alloy Wire
Resistor
Motherboard
Trace Resistor
Description
Tolerance
Factor (TF)
±29%
±5%
(±1% available)
±1%
±10%
±10%
Size
(L x W x H)
2" x 0.2" x 0.001" 0.45" x 0.065" x 0.25" x 0.125" x 0.200" x 0.04" x
0.200" x 0.04" x
0.100"
(1 oz Cu trace)
0.200"
0.025"
0.160"
Power capability
> 50A/in
1 watt
1 watt
1 watt
1 watt
(3W and 5W
available)
Temperature
Coefficient
+4,000 ppm
+30 ppm
±75 ppm
±30 ppm
±20 ppm
Cost
Low
$0.31
$0.47
$0.09
$0.09
@10,000 piece
included in
motherboard
Refer to Appendix A for Directory of component suppliers
Based on the Tolerance in the above table, for embedded PC
V
th,min
----------------------------------------
× (1 – TF) =
R
=
trace resistor and for I
= 14.5A:
load,max
SENSE
1.0A + I
Load, max
V
th,min
----------------------------------------
R
=
× (1 – TF) =
SENSE
1.0A + I
Load, max
100mV
---------------------------------
× (1 – 5%) = 6.1mΩ
1.0A + 14.5A
100mV
---------------------------------
1.0A + 14.5A
× (1 – 29%) = 4.6mΩ
For user convenience, Table 8 lists the recommended values
for sense resistor at various load currents using an embedded
PC trace resistor or discrete resistor.
For a discrete resistor and I
= 14.5A:
load, max
11
AN42
APPLICATION NOTE
Table 8. R
for various load currents
Table 9 is a summary of tolerances for the Embedded PC
Trace Resistor.
sense
R
R
SENSE
SENSE
I
PC Trace
Resistor (mΩ)
Discrete
Resistor (mΩ)
Load,max
Table 9. Summary PC Trace Resistor Tolerance
(A)
Tolerance due to sheet resistivity variation
Tolerance due to L/W error
16%
1%
10.0
11.2
12.4
13.9
14.0
14.5
6.5
5.8
5.3
4.8
4.7
4.6
8.6
7.8
7.1
6.4
6.3
6.1
Tolerance due to temperature variation
Total Tolerance for PC Trace Resistor
12%
29%
Design rules for using an embedded resistor
The basic equation for laying an embedded resistor is:
L
L
W × t
W
-------------
R = ρ ×
t
Discrete Sense Resistor
Discrete iron alloy resistors come in a variety of tolerances
and power ratings, and are ideal for precision implementa-
tions. Either an MnCu alloy wire resistor or an CuNi alloy
wire resistor is ideal for a low cost implementation.
where ρ is the Resistivity (W-mil), L is the Length (mils), W
is the Width (mils), and t is the Thickness (mils).
For 1oz copper, t = 1.35 mils, ρ = 717.86 µΩ-mil,
1 L/1 W = 1 Square ( ■ ).
For example, you can layout a 5.30mΩ embedded sense
Embedded Sense Resistor (PC Trace Resistor)
resistor. From Equations above,
Embedded PC trace resistors have the advantage of almost
zero cost implementation. However, the value of the PC
trace resistors have large variations. Embedded resistors
have 3 major error sources: the sheet resistivity of the inner
layer, the mismatch due to L/W, and the temperature varia-
tion of the resistor. When laying out embedded sense resis-
tors, consider all error sources described as follows:
I
10
0.05
L
W = --------- = --------- = 200mil
0.05
R × W × t
0.00530 × 200 × 1.35
L = ----------------------- = --------------------------------------------------- = 2000mi
ρ
717.86
L/W = 10 ■.
Therefore, to model 5.30mΩ enbedded resistor, you need
• Sheet resistivity.
W = 200 mils, and L = 2000 mils. See Figure 10.
For 1 ounce copper, the thickness variation is typically
between 1.15 mil and 1.35 mil. Therefore, the error due to
sheet resistivity is (1.35 – 1.15)/1.25 = 16%.
1
1
1
1
1
1
1
1
1
1
W = 200 mils
• Mismatch due to L/W.
The error in L/W is dictated by the geometry and the
power dissipation capability of the sense resistor. The
sense resistor must be able to handle the load current and,
therefore, requires a minimum width, calculated as
follows:
L = 2000
Figure 10. 5.30mΩ Sense Resistor (10 ■)
You can also implement the sense resistor in the following
manner. Each corner square is counted as 0.6 square since
the current flowing through the corner square does not flow
uniformly, concentrated towards the inside edge. This is
shown in Figure 11.
I
L
W = ---------
0.05
where W is the minimum width required for proper power
dissipation (mils), and I is the load current in Amps.
L
1
1
1
1
1
1
.6
.6
1
For a load current of 15A, the minimum width required is
300mils, which reflects a 1% L/W error.
1
.8
• Thermal Considerations.
2
The I R power losses cause the surface temperature of the
Figure 11. 5.30mΩ Sense Resistor (10 ■)
resistor to increase along with its resistance value. In
addition, ambient temperature variations add the change
in resistor value:
A Resign Example Combining an Embedded Resistor
with a Discrete Resistor
R = R [1 + α (T – 20)]
20
20
For low cost implementation, the embedded PC trace resistor
is the most desirable alternative, but, as discussed earlier, the
wide tolerance (±29%) presents a challenge. In addition,
changing CPU requirements may force the maximum load
where R is the resistance at 20°C, α = 0.00393/ °C,T
20
20
is the operating temperature, andR is the desired value.
For temperature T = 50°C, the %R change = 12%.
12
APPLICATION NOTE
AN42
Embedded Sense Resistor
IFBH
MnCu Discrete
Resistor
R21
R22
IFBL
Output Power
Plane (Vout)
R-∆r
R
R+∆r
Figure 12. Short Circuit Sense Resistor Design Using PC Trace Resistor and Optional Discrete Sense Resistor
currents to change. Therefore, combining an embedded
resistor with a discrete resistor may be a desirable option.
This section discusses a design that provides flexibility and
addresses wide tolerances. Refer to Figure 12.
The converter exhibits at normal load regulation until the
voltage across the resistor reaches the internal short circuit
threshold of 120mV. At this point, the internal
comparator trips and signals the controller to turn off the
gate drive to the power MOSFET. This causes a drastic
reduction in the output voltage as the load regulation col-
lapses into the short circuit control mode. The output voltage
does not return to its nominal value until the output short cir-
cuit current is reduced to within the safe range for the DC-
DC converter.
In this design, the user has the option to choose either an
embedded or a discrete MnCu sense resistor. To use the dis-
crete sense resistor, populate R21 with a shorting bar (zero
Ohm resistor) for a proper Kelvin connection and add the
MnCu sense resistor. To use the embedded sense resistor,
populate R22 with a shorting bar for a Kelvin connection.
The embedded sense resistor allows you to choose a plus or a
minus delta resistance tap to offset any large sheet resistivity
change.
Power Dissipation Consideration During a
Short Circuit Condition
The RC5040 and RC5042 controllers respond to an output
short circuit by drastically changing the duty cycle of the
gate drive signal to the power MOSFET. In doing this, the
power MOSFET is protected from over-stress and eventual
destruction. Figure 14A shows the gate drive signal of a typ-
ical RC5040 operating in continuous mode with a load cur-
rent of 10A. The duty cycle is then set by the ratio of the
input voltage to the output voltage. If the input voltage is 5V
and the output voltage is 3.1V, the ratio of Vout/ Vin is 62%.
Figure 14B shows the result of the RC5040 going into its
short circuit mode when the duty cycle is around 20%. Cal-
culating the power on the MOSFET at each condition on the
graph in Figure 13 shows how the protection scheme works.
The power dissipated in the MOSFET at normal operation
for a load current of 14.5A, is given by:
In this design, the center tap yields 6mΩ, and the left or the
right tap yield 6.7 or 5.3 mΩ, respectively.
RC5040 and RC5042 Short Circuit Current
Characteristics
The RC5040 and RC5042 have a short circuit current char-
acteristic that includes a hysteresis function. This function
prevents the DC-DC converter from oscillating in the event
of a short circuit. Figure 13 shows the typical characteristic
of the DC-DC converter using a 6.5 mΩ sense resistor.
3.5
˙
2 × .037 × .62 = 1.2W
3.0
2.5
2.0
1.5
1.0
14.5
2
PD = I2 × RON × DutyCycle =
---------
for each MOSFET.
The power dissipated in the MOSFET at short circuit
condition for a peak short current of 20A, is given by:
0.5
0
2
20
2
-----
P
=
× .037 × .2 = 0.74W
D
0
5
10
15
20
25
for each MOSFET.
Output Current
Figure 13. RC5040/RC5042 Short Circuit Characteristic
Thus, the MOSFET is not being over-stressed during a short
circuit condition.
13
AN42
APPLICATION NOTE
P
= I
× V × (1 – DutyCycle) =
F, ave
D, Diode
F
14 × 0.45 × 0.8 ≈ 5W
Thus for the Schottky diode, the thermal dissipation during
a short circuit is greatly magnified and requires that the
thermal dissipation of the diode be properly managed by the
appropriate choice of a heat sink. In order to protect the
Schottky from being destroyed in the event of a short, we
should limit the junction temperature to less than 130°C.
Using the equation for maximum junction temperature,
we can arrive at the thermal resistance required below:
T
– T
A
J(max)
R
P
= -------------------------------
D
ΘJA
Figure 14A. V
CCQP
Output Waveform for Normal
= 3.3V@10A
Operation Condition with V
Assuming that the ambient temperature is 50°C, we get:
– T
out
T
130 – 50
J(max)
A
R
= ------------------------------- = -------------------- = 16°C ⁄ W
ΘJA
P
5
D
Thus we need to provide for a heat sink that will give the
Schottky diode a thermal resistance of at least 16°C/W or
lower in order to protect the device during an indefinite
short.
In summary, with proper heat sink, the Schottky diode is not
being over stressed during a short circuit condition.
Schottky Diode Selection
The application circuits of Figures 3, 4, and 5 show two
Schottky diodes, DS1 and DS2. In synchronous mode, DS1
is used in parallel with M3 to prevent the lossy diode in the
FET from turning on. In non-synchronous mode, DS1 is
used as a flyback diode to provide a constant current path for
the inductor when M1 is turned off.
Figure 14B. V
CCQP
Output Waveform for
Output Shorted to Ground
The Schottky diode has a power dissipation consideration
during the short circuit condition. During normal operation,
the diode dissipates power when the power MOSFET is off.
The power dissipation is given by:
The Schottky diode DS2 serves a dual purpose. As config-
ured in Figures 3, 4, and 5, DS2 allows the VCCQP pin on
the RC5040 to be bootstrapped up to 9V using capacitor
C12. When the lower MOSFET M3 is turned on, one side of
capacitor C12 is connected to ground while the other side of
the capacitor is being charged up to voltage VIN – VD
through DS2. The voltage that is then applied to the gate of
the MOSFET is VCCQP – VSAT, or typically around 9V.
DS2 also provides correct sequencing of the various supply
voltages by assuring that VCCQP is not enabled before the
other supplies.
P
= I × V × (1 – DutyCycle) =
D, Diode
F
F
14.5 × 0.5V × (1 – 0.62) = 2.75W
In short circuit mode, the duty cycle is dramatically reduced
to approximately 20%. The forward current during a short
circuit condition decays exponentially through the inductor.
The power dissipated on the diode during the short circuit
condition, is approximated by:
A vital selection criteria for DS1 and DS2 is that they exhibit
a very low forward voltage drop, as this parameter can
directly affect the regulator efficiency. Table 10 lists several
suitable Schottky diodes. Note that the MBR2015CTL has a
very low forward voltage drop. This diode is ideal for appli-
cations where output voltages less than 2.8V are required.
1
1.5us
– -------------
1.3us
– -----------
L ⁄ R
I
I
= I × e
= 20A × e
≈ 7.9A
F, ending
sc
≈ (20A + 7.9A) ⁄ 2 ≈ 14A
F, ave
14
APPLICATION NOTE
AN42
With this in mind, correct calculation of the output capaci-
Table 10. Schottky Diode Selection Table
tance is crucial to the performance of the DC-DC converter.
The output capacitor determines the overall loop stability,
output voltage ripple, and load transient response. The calcu-
lation is as follows:
Manufacturer
Model #
Forward Voltage
Conditions
VF
Philips
PBYR1035
IF = 20A; Tj=25°C
IF = 20A; Tj=125°C
< 0.84v
< 0.72v
I × ∆T
O
Motorola
MBR2035CT IF = 20A; Tj=125°C
IF = 20A; Tj=25°C
< 0.84v
< 0.72v
C(µF) = -------------------------------------
∆V – I × ESR
O
Motorola
MBR1545CT IF = 15A; Tj=125°C
IF = 15A; Tj=25°C
< 0.84v
< 0.72v
where ∆V is the maximum voltage deviation due to load
transients, ∆T is the reaction time of the power source, and
I
O
is the output load current. ∆V is the loop response time of
Motorola
MBR2015CTL IF = 20A; Tj=150°C
IF = 20A; Tj=25°C
< 0.58v
< 0.48v
the RC5040 and RC5042, approximately 8µs.
For I = 10A and ∆V = 165mV, the bulk capacitance
O
Output Filter Capacitors
required can be approximated as follows:
Output ripple performance and transient response are
functions of the filter capacitors. Since the 5V supply of a PC
motherboard may be located several inches away from the
DC-DC converter, the input capacitance can play an impor-
tant role in the load transient response of the RC5040.
The higher the input capacitance, the more charge storage is
available for improving the current transfer through the
FET(s). Capacitors with low Equivalent Series Resistance
(ESR) are best for this type of application and can influence
the converter's efficiency if not chosen carefully. The input
capacitor should be placed as close to the drain of the FET as
possible to reduce the effect of ringing caused by long trace
lengths.
IO × ∆T
C(µF) = ------------------------------------- = --------------------------------------------------------- = 1454µF
∆V – IO × ESR 165mV – 10A × 11mΩ
10A × 8µs
Input filter
The DC-DC converter design should include an input induc-
tor between the system +5V supply and the converter input
as described below. This inductor will serve to isolate the
+5V supply from noise occurring in the switching portion of
the DC-DC converter and also to limit the inrush current into
the input capacitors during power up. An inductor value of
around 2.5µH is recommended, as illustrated in Figure 15.
2.5µH
5V
Vin
ESR is the resonant impedance of the capacitor, and it is dif-
ficult to quantify. Since the capacitor is actually a complex
impedance device having resistance, inductance, and capaci-
tance, it is natural for it to have a resonant frequency. As a
rule, the lower the ESR, the better suited the capacitor is for
use in switching power supply applications. Many manufac-
turers do not supply ESR data, but a useful estimate can be
obtained using the following equation:
1000µF, 10V
0.1µF
Electrolytic
65-AP42-17
Figure 15. Input Filter
DF
ESR = ------------
2πfC
Bill of Materials
where DF is the dissipation factor of the capacitor, f is the
operating frequency, and C is the capacitance in farads.
The Bill of Materials for the application circuits of Figures 2
through 4 is presented in Table 11.
Table 11. Bill of Materials for a 14.5A Pentium Pro Motherboard Application
C4, C5, C7, C8, C9,
C10
Panasonic
ECU-V1H104ZFX
0.1µF 50V capacitor
4.7µF 16V capacitor
39pF capacitor
C6
Panasonic
ECSH1CY475R
Cext
Panasonic
ECU-V1H121JCG
C12
C1, C2, C3
United Chemicon
LXF16VB102M
1000µF 6.3V electrolytic
capacitor 10mm x 20mm
ESR<0.047Ω
C11
Panasonic
ECU-V1H224ZFX
0.22µF 50V capacitor
15
AN42
APPLICATION NOTE
Table 11. Bill of Materials for a 14.5A Pentium Pro Motherboard Application
C13, C14, C15
Sanyo
6MV1500GX
1500µF 6.3V electrolytic
ESR < 0.047 Ω
Vf<0.72V @ If = 15A
1A, 20V
capacitor 10mm x 20mm
DS1
(note 1)
Motorola
MBR1545CT
Shottky Diode
DS2
L1
General Instruments 1N5817
Skynet 320-8107
Schottky Diode
1.3µH inductor
2.5µH inductor
L2*
Skynet
320-6110
*Optional – will help re-
duce ripple on 5v line
M1, M2, M3
(note 2)
Fuji
2SK1388
N-Channel Logic Level
Enhancement Mode MOSFET
R
V
< 37m ohm
DS(ON)
< 4V, I > 20A
GS
D
Rsense
COPEL
A.W.G. #18
6 milliohm CuNi Alloy Wire
resistor
R1, R2, R3, R4, R6,
R7
Panasonic ERJ-6ENF10.0KV
10K 5% Resistors
U1
Raytheon
RC5042M or RC5040M
DC-DC Converter for Pentium
Pro
Refer to Appendix A for Directory of component suppliers.
Notes:
1. In synchronous mode using the RC5040, a 1A schottky diode (1N5817) may be substituted for the MBR1545CT.
2. MOSFET M3 is only required for the RC5040 synchronous application.
PCB Layout Guidelines and Considerations
PCB Layout Guidelines
• The CEXT timing capacitor should be surrounded with a
• Placement of the MOSFETs relative to the RC5040 is
ground trace. The placement of a ground or power plane
critical. The MOSFETs (M1 & M2), should be placed
underneath the capacitor provides further noise isolation,
such that the trace length of the HIDRV pin to the FET
and helps to shield the oscillator from the noise on the
gate is minimized. A long lead length causes high
PCB. This capacitor should be placed as close to pin 1 as
amounts of ringing due to the inductance of the trace and
possible.
the large gate capacitance of the FET. This noise radiates
all over the board, and because it is switching at a high
• Group the MOSFETs, inductor, and Schottky diode as
voltage and frequency, it is very difficult to suppress.
close together as possible. This minimizes ringing derived
from the inductance of the trace and the large gate
Figure 16 shows an example of proper MOSFET
capacitance of the FET. Place the input bulk capacitors as
placement in relation to the RC5040. It also shows an
close to the drains of MOSFETs as possible. In addition,
example of problematic placement for the MOSFETs.
place the 0.1µF decoupling capacitors right on the drain
of each MOSFET. This helps to suppress some of the high
In general, noisy switching lines should be kept away
frequency switching noise on the DC-DC converter input.
from the quiet analog section of the RC5040. That is,
traces that connect to pins 12 and 13 (HIDRV and
• The traces that run from the RC5040 IFB (pin 4) and VFB
VCCQP) should be kept far away from the traces that
(pin 5) pins should be run next to each other and be Kelvin
connect to pins 1 through 5, and pin 16.
connected to the sense resistor. Running these lines
together helps to reject some of the common mode noise
to the RC5040 feedback input. Run the noisy switching
• Place the 0.1µF decoupling capacitors as close to the
RC5040 and RC5042 pins as possible. Extra lead length
signals (HIDRV & VCCQP) on one layer, and use the
negates their ability to suppress noise.
inner layers for power and ground only. If the top layer is
being used to route all of the noisy switching signals, use
• Each VCC and GND pin should have its own via to the
the bottom layer to route the analog sensing signals VFB
appropriate plane on the board to add isolation between
and IFB.
pins
16
APPLICATION NOTE
AN42
Good layout
Bad layout
10
9
10
9
11 RC5040
11 RC5040
12
13
12
13
8
7
8
7
14
15
16
17
14
15
16
17
6
6
5
4
5
4
18
19
18
19
20
3
2
3
2
20
1
1
= “Quiet” Pins
Figure 16. Example of Proper MOSFETs Placements
File can be obtained from Raytheon Electronics Semicon-
ductor Division’s Marketing Department at (415) 966-7819.
PC Motherboard Layout and Gerber File
A reference design for motherboard implementation of the
RC5040 and RC5042 along with the Layout Gerber File and
Silk Screen are presented below. The actual PCAD Gerber
17
AN42
APPLICATION NOTE
18
APPLICATION NOTE
AN42
5. Apply load at 1A increments; an active load (HP6060B
or equivalent) is suggested.
Guidelines for Debugging and
Performance Evaluations
6. In case of poor regulation, refer to the procedures in the
DebuggingYour First Design Implementation
Troubleshooting section.
Use the following procedure to help you debug your design
implementation:
Troubleshooting
1. If no voltage is registered at the output and the circuit is
not drawing current, look for openings in the connec-
tions. Check the circuitry versus the schematic, and the
power supply pins at the device to ascertain that volt-
age(s) had been applied.
1. Note the VID pins settings. They tell you what voltage is
to be expected.
2. Do not connect any load to the circuit. While monitoring
the output voltage, apply power to the part with current
limiting at the power supply. Do this to make sure that
no catastrophic shorts occur.
2. If no voltage is registered at the output and the circuit is
drawing excessive current (>100mA) with no load,
check for possible shorts. Trace the path of the excessive
current to determine if the controller is at fault or if the
excessive current is due to peripheral components.
3. Ιf proper voltage is not achieved, follow the procedures
in the Troubleshooting section.
3. If the output voltage comes near to, but is not, what is
expected, check the VID inputs at the device pins. The
part is factory set to correspond to the VID inputs.
4. After there is proper voltage, increase the current limit-
ing of the power supply to 16A.
19
AN42
APPLICATION NOTE
Load Regulation
4. Premature shut down can be caused by an inappropriate
value of sense resistor. See the Sense Resistor section.
VID
Iload (A)
0.5
Vout (V)
3.0904
3.0825
3.0786
3.0730
3.0695
3.0693
3.0695
3.0695
3.0694
3.0694
3.0691
0.70%
5. A poor load regulation can have many causes. You
should first check the voltages and signals at the critical
pins.
0100
1.0
2.0
6. The VREF pin should be at the voltage set by the VID
pins. If the power supply pins are correct and the VID
pins are correct, the VREF should be at the correct volt-
age.
3.0
4.0
5.0
7. Next check the oscillator pin. A saw tooth wave at the
frequency set by the external capacitor should be seen.
6.0
7.0
8. When the VREF and CEXT pins are determined to be
correct and the output voltage is still incorrect look at
the waveform at VCCQP. This pin should be swinging
from ground to +12V (in the +12V application) and
from slightly below +5V to about +10V (charge pump
application). If the VCCQP pin is noisy, with ripples and
overshoots, then the noise may cause the converter to
function improperly.
8.0
9.0
9.9
Load Regulation 0.5A – 9.9A
VID
Iload (A)
0.5
Vout (V)
3.2805
3.2741
3.2701
3.2642
3.2595
3.2597
3.2606
3.2611
3.2613
3.2611
3.2607
3.2599
3.2596
3.2596
0.64%
0010
9. Next, look at the HIDRV pin. This pin directly drives the
gate of the FET. It should provide a gate drive (Vgs) of
about 5V when turning the FET on. A careful study of
the layout is recommended. See the PCB Layout Guide-
lines and Considerations section.
1.0
2.0
3.0
4.0
10. Experience shows that the most frequent errors are using
incorrect components, improper connections, and poor
layout.
5.0
6.0
7.0
Performance Evaluation
8.0
This section shows the results of a random sample evalua-
tion. Use these results as a reference guide for evaluating the
RC5040 DC-DC converter for Pentium Pro motherboards.
9.0
10.0
11.0
12.0
12.4
Load Regulation 0.5A – 12.4A
20
APPLICATION NOTE
AN42
VID
I
(A)
V
(V)
Low to High 0.5A-9.9A
Current Step
- 76.0mV
+ 70mV
Refer to
load
out
Attachment
A for Scope
Picture
1010
0.5
2.505
2.504
2.501
2.496
2.493
2.493
2.492
2.492
2.491
2.490
2.489
2.488
2.486
2.485
2.484
0.84%
1.0
2.0
High to Low 9.9A-0.5A
Current Step
Refer to
Attachment
B for Scope
Picture
3.0
4.0
5.0
Low to High 0.5A-12.4A - 97.6mV
Current Step
Refer to
6.0
Attachment
C for Scope
Picture
7.0
8.0
High to Low 12.4A-0.5A + 80.0mV
Current Step
Refer to
9.0
Attachment
D for Scope
Picture
10.0
11.0
12.0
13.0
13.9
Low to High 0.5A-13.9A - 99.2mV
Current Step
Refer to
Attachment
E for Scope
Picture
High to Low 13.9A-0.5A + 105.2mV Refer to
Current Step
Load Regulation 0.5 - 13.9A
Attachment
Note:
F for Scope
Picture
Load regulation is expected to be typically around 0.8%. The
load regulation performance for this device under evaluation is
excellent.
Note:
Excellent transient voltage response. Transient voltage is rec-
ommended to be less than 4% of the output voltage. The per-
formance of the device under evaluation is significantly better
than a typical VRM.
Output Voltage LoadTransients Due to Load Current Step
This test is performed using Intel P6.0/P6S/P6T Voltage
Transient Tester.
Input Ripple and Power on Input Rush Current
Iload = 9.9A Input Ripple
Refer to Attachment
Voltage = 15mV G for Scope Picture
Power on Input Rush Current is not measured on the mother-
board because we did not want to cut the 5V trace and insert
current probe in series with the supply. However, with the
input filter design, the Input Rush Current will be well within
specification.
21
AN42
APPLICATION NOTE
Component Case Temperature
Case Temperature Case Temperature Case Temperature
(°C)
Iload= 9.9A
(°C)
Iload= 12.4A
(°C)
Iload =13.9A
Device
Description
Q3A
MOSFET
K1388
57
58
53
66
63
64
56
70
56.3
66.6
61.2
87
Q3B
L1
MOSFET
K1388
Inductor,
Unknown
Q2
Schottky Diode
2048CT
IC
Raytheon RC5040
52
38.2
35
54
58
39
Cin
Cout
Input Capacitor 1000µF
36.8
34.8
Output Capacitor
38.2
1500µF
Note:
Case temperatures are all within guidelines. Our guideline is that case temperatures for all components should be below 105°C
@25°C Ambient.
Comments:
Excellent input ripple voltage. Input ripple voltage is recommended to be less than 5% of the output voltage.
Evaluation Summary:
The on-board DC-DC converter is fully functional. It has
excellent load regulation, transient response, and input
voltage ripple.
Attachment A
Attachment B
22
APPLICATION NOTE
AN42
Attachment E
Attachment C
Attachment F
Attachment D
Attachment G
Summary
RC5040/RC5042 Evaluation Board
This application note covers for implementation of a DC-DC
converter on a Pentium Pro motherboard using the RC5040
and RC5042. The detailed discussion includes Pentium Pro
processor power requirements, RC5040 and RC5042
description, design considerationsn and component selec-
tions, layout guidelines and considerations, guidelines for
debugging, and performance evaluations.
Raytheon Electronics provides an evaluation board for the
purpose of verifying system level performance of the
RC5040 and RC5042. The evaluation board serves as a guide
as to what can be expected in performance with the supplied
external components and PCB layout. Please call Raytheon
Electronics Marketing Department at (415) 966-7819 for an
evaluation board.
23
AN42
APPLICATION NOTE
Appendix A: Directory of Component Suppliers
Dale Electronics, Inc.
E. Hwy. 50, PO Box 180
Yankton, SD 57078-0180
PH: (605) 665-9301
National Semiconductor
2900 Semiconductor Drive
Santa Clara, CA 95052-8090
PH: (800) 272-9959
Fuji Electric
Nihon Inter Electronics Corp.
Quantum Marketing Int’l, Inc.
12900 Rolling Oaks Rd.
Caliente, CA 93518
Collmer Semiconductor Inc.
14368 Proton Rd.
Dallas, Texas 75244
PH: (214)233-1589
PH: (805) 867-2555
General Instrument
Panasonic Industrial Co.
6550 Katella Avenue
Cypress, CA 90630
PH: (714) 373-7366
Power Semiconductor Division
10 Melville Park Road
Melville, NY 11747
PH: (516) 847-3000
Pulse Engineering
Hoskins Manufacturing Co.
(Copel Resistor Wire)
10776 Hall Road
12220 World Trade Drive
San Diego, CA 92128
PH: (619) 674-8100
Hamburg, MI 48139-0218
PH: (313) 231-1900
Sanyo Energy USA
2001 Sanyo Avenue
San Diego, CA 92173
PH: (619) 661-6620
Intel Corp.
5200 NE Elam Young Pkwy.
Hillsboro, OR. 97123
PH: (800) 843-4481 Tech. Support
for Power Validator
Siliconix
Temic Semiconductors
2201 Laurelwood Road
Santa Clara, CA 95056-1595
PH: (800) 554-5565
International Rectifier
233 Kansas St.
El Segundo, CA 90245
PH: (310) 322-3331
Sumida Electric USA
5999 New Wilke Road Suite #110
Rolling Meadows, IL 60008
PH: (708) 956-0702
IRC Inc.
PO Box 1860
Boone, NC 28607
PH: (704) 264-8861
Xicon Capacitors
PO Box 170537
Motorola Semiconductors
PO Box 20912
Arlington, Texas 76003
PH:(800) 628-0544
Phoenix, Arizona 85036
PH:(602) 897-5056
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device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
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