RUBY-MM-1612
16-Channel 12-Bit Analog Output
PC/104 Module
User Manual V1.1
ã Copyright 2001
Diamond Systems Corporation
8430-D Central Ave.
Newark, CA 94560
Tel (510) 456-7800
Fax (510) 45-7878
RUBY-MM-1612
16-Channel Analog Output PC/104 Module
1. DESCRIPTION
Ruby-MM-1612 is a PC/104-format data acquisition board that provides analog outputs and digital I/O for
process control and other applications. Below is a summary of key features:
Analog Outputs
Ruby-MM-1612 has 16 analog voltage outputs with 12-bit resolution (1 part in 4096).
Þ Note: Analog output, D/A, and DAC are all used interchangeably in this manual.
Multiple Full-Scale Output Ranges
Six different preset ranges are available, including both bipolar and unipolar ranges.
Adjustable Full-Scale Output Range
One of the preset ranges (2.5V full-scale) can be adjusted by the user to any voltage between
approximately 1V and 2.5V.
Simultaneous Update
All 16 analog outputs are updated simultaneously. This prevents time skew errors which can
result from updating outputs sequentially on a system which requires two or more control signals
to change simultaneously.
External Trigger
An external trigger signal can be connected to the board. This trigger can be used to update the
analog outputs. The trigger is enabled in software.
Digital I/O
An 82C55 chip is included to provide 24 lines of digital I/O. Each line has a 10KW pull-up resistor.
Each line is CMOS / TTL compatible and can supply up to ±2.5mA of current.
+5V Operation
Ruby-MM-1612 requires only +5VDC from the system power supply for operation. It generates its
own ±15V supplies for the analog circuitry on board using four miniature DC/DC converters.
Copyright 2001 Diamond Systems Corp.
Ruby-MM-1612 User Manual V1.1 P. 3
2. I/O HEADER PINOUT
Ruby-MM-1612 provides a 50-pin right-angle header labeled J3 for all user I/O. This header is located on
the right side of the board. Pins 1, 2, 49, and 50 are marked to aid in proper orientation. A standard 50-pin
cable-mount IDC (insulation displacement contact) connector will mate with this header.
J3
(Top of board)
Agnd
Agnd
Agnd
Agnd
Agnd
1
3
5
7
9
2
4
6
8
10
Vout 0
Vout 1
Vout 2
Vout 3
Vout 4
Agnd
Agnd
Agnd
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
Vout 5
Vout 6
Vout 7
Vout 9
Vout 8
Vout 10
Vout 12
Vout 14
DIO A7
DIO A5
DIO A3
DIO A1
DIO B7
DIO B5
DIO B3
DIO B1
DIO C7
DIO C5
DIO C3
DIO C1
+5V
Vout 11
Vout 13
Vout 15
DIO A6
DIO A4
DIO A2
DIO A0
DIO B6
DIO B4
DIO B2
DIO B0
DIO C6
DIO C4
DIO C2
DIO C0 / Ext Trig
Dgnd
Signal Name
Definition
Vout15 - 0
Agnd
Analog output channels
Analog ground
DIO A7-0, B7-0, C7-0
Ext Trig
+5V
Dgnd
Digital I/O lines (programmable direction)
Digital I/O line C0 can be used as an external D/A update signal
Connected to PC/104 bus +5V power supply
Digital ground
Þ Note: The +5V and Dgnd lines do not need to be connected to a power supply to use this board. They
are provided as connection points for convenience purposes only.
Copyright 2001 Diamond Systems Corp.
Ruby-MM-1612 User Manual V1.1 P. 4
3. BOARD CONFIGURATION
Refer to the Drawing of Ruby-MM-1612 on Page 8 for locations of headers described in Chapters 3 and
4.
Base Address
Each board in the system must have a different base address. Use the pin header labeled J5, base
address. The numbers above the jumpers correspond to the I/O address bits; bit 9 is the MSB and bit 0 is
the LSB. Only bits 9 – 4 are used for the base address decoding. The remaining 4 bits 3-0 are assumed
to be 0 for the base address. When a jumper is in, the corresponding base address bit is a 0, and when it
is out, the bit is a 1.
The default address is 300 Hex = 1 1 0 0 0 0 0 0 0 0, so 9 8 are out and 7 6 5 4 are in. Any address
above 100 Hex is a valid I/O address. However, there are many other circuits and boards sharing the I/O
space, so you should check the documentation for your other boards to avoid conflicts. Below are some
recommended I/O addresses for Ruby-MM-1612. Although the Base addresses can only be selected on
16-byte boundaries, Ruby-MM-1612 only uses the first 8 addresses.
Table 3.1: Base Address Configuration
Base Address
Header J5 Position
Hex
Decimal
544
9
8
7
6
5
4
220
240
250
260
280
290
2A0
2B0
2C0
2D0
2E0
300
330
340
350
360
380
390
3A0
3C0
3E0
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
Out
In
In
576
In
In
Out
Out
Out
In
In
592
In
In
In
Out
In
608
In
In
Out
In
640
In
Out
Out
Out
Out
Out
Out
Out
In
In
656
In
In
In
Out
In
672
In
In
Out
Out
In
688
In
In
Out
In
704
In
Out
Out
Out
In
720
In
In
Out
In
736
In
Out
In
768 (Default) Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
In
816
832
848
864
896
912
928
960
992
Out
Out
Out
Out
Out
Out
Out
Out
Out
In
In
Out
In
Out
In
In
Out
Out
Out
In
In
In
Out
In
In
Out
In
Out
Out
Out
Out
Out
In
In
In
Out
In
In
Out
In
Out
Out
In
Out
In
Copyright 2001 Diamond Systems Corp.
Ruby-MM-1612 User Manual V1.1 P. 5
4. ANALOG OUTPUT RANGE CONFIGURATION
Refer to the Drawing of Ruby-MM-1612 on Page 8 for locations of headers described in Sections 3 and 4.
Refer to Figure 4.1 on Page for an explanation of the voltage reference circuitry. Also refer to Table 4.1
for a quick guide to output range configuration and jumper settings.
Header J4 is used to configure the analog outputs. Four items are configurable: (1) On-board reference
full-scale voltage, (2) D/A full-scale voltage, (3) unipolar / bipolar select, and (4) adjustable reference
voltage. Items 2 and 3 in turn are configured separately for each bank of 8 analog output channels.
On-Board Reference Full-Scale Voltage Selection
An on-board reference voltage generator provides a +5.000V full-scale voltage output. This voltage is
used as the basis for all on-board full-scale output ranges. This +5 reference drives an operational
amplifier, from which the fixed references are derived. The gain of this amplifier is normally set to 1, so
that its output is also +5.000V. However, you can change the gain to 2 so that the output is +10.00V. For
an output of +5V, install a jumper in location 5 in header J4. For an output of +10V, remove the jumper
from this location. The output of this amplifier is used to generate the full-scale voltages for both bipolar
and unipolar output ranges.
D/A Full-Scale Voltage
The full-scale voltage defines the full output range capability of the analog outputs. Locations F A on
header J4 are used to select the full-scale voltage. Each bank of eight channels has its own selection
pins for full-scale voltage. Thus each bank of eight channels may be configured differently. Install only
one jumper in these locations for each bank of channels. Position F is for the Full-scale voltage (5V or
10V depending on the jumper in position 2, explained above). This is the default setting. Position A is for
the Adjustable reference voltage (see section 4.4).
Unipolar / Bipolar Output Range
Unipolar output ranges are positive voltages only (for example 0 - 5V), while bipolar output ranges include
both positive and negative voltages (for example ±5V). To select unipolar outputs, install a jumper in
position U on J4. to select bipolar outputs, install a jumper in position B. Install only one jumper in these
locations for each bank of channels.
Adjustable Reference Voltage
One full-scale voltage range is adjustable by the user. It is preset to 2.5V (for both 0-2.5V and ±2.5V
ranges), but may be set anywhere between 0V and 2.5V. To adjust this voltage, apply a voltmeter to the
top pin of header J4 underneath either A mark and turn the screw on potentiometer R4 (the fourth from
the left / second from the right in the row of blue potentiometers at the top of the board) until the voltmeter
reads the desired voltage.
Copyright 2001 Diamond Systems Corp.
Ruby-MM-1612 User Manual V1.1 P. 6
Table 4.1: Analog Output Configuration (Header J4)
Range
5
F
A
B
U
0-5V:
0-10V:
+/-5V:
+/-10V:
0-2.5V:
or
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
+/-2.5V:
or
X
X
An X means that a jumper is installed in that location. Only one half of pin header J4 is shown.
Positions F A B U are repeated for each bank of 8 channels.
Þ Note: Each bank of eight channels (0 - 7 and 8 - 15) can have a different output range setting.
However, all eight channels within a bank will always have the same output range.
Copyright 2001 Diamond Systems Corp.
Ruby-MM-1612 User Manual V1.1 P. 7
5. RUBY-MM-1612 BOARD DRAWING
J1:
J2:
J3:
J4:
J5:
J6:
PC/104 8-bit bus header
PC/104 16-bit bus header (not used)
User I/O header
Analog output range configuration header
Base address selection header
ISP header for factory use only; do not connect
Copyright 2001 Diamond Systems Corp.
Ruby-MM-1612 User Manual V1.1 P. 8
6. I/O MAP
Ruby-MM-1612 occupies 8 consecutive 8-bit locations in I/O space. For example, the default base
address is 300 Hex (768 Decimal); in this case the board occupies addresses 300 - 307 (768 - 775).
The first 2 locations are used individually for each analog output channel. Since analog output data is 12
bits wide, it is broken into two bytes. The first byte contains the 8 least significant bits (called the LSB) of
the D/A data, and the 4 lowest bits of the second byte contain the 4 most significant bits (called the MSB)
of the D/A data. The 4 highest bits of the second byte are not used.
The DACs are updated all at once when Base or Base+1 is read. The value read from these locations is
not predictable and not meaningful. Only the act of reading from the board is required to perform the
update.
Ruby-MM-1612 I/O Map
Base +
Write Function
Read Function
0
1
2
3
4
5
6
7
DAC LSB (all DACs)
DAC MSB (all DACs)
DAC channel register
External trigger enable
Digital I/O port A data
Digital I/O port B data
Digital I/O port C data
Digital I/O control register
Update all DACs simultaneously
Update all DACs simultaneously
NA
NA
Digital I/O port A data
Digital I/O port B data
Digital I/O port C data
Digital I/O control register
Reset information:
A system hardware reset will also reset the board.
During a reset, the following occurs:
·
All analog outputs are set to mid-scale (0V for bipolar ranges and 1/2 full-scale for unipolar
ranges).
·
·
The external trigger register is set to 0, disabling external trigger.
All digital I/O lines are set to input mode.
The next chapter describes all registers on the board. You should familiarize yourself with these registers
in order to get a complete understanding of the board’s operation.
Copyright 2001 Diamond Systems Corp.
Ruby-MM-1612 User Manual V1.1 P. 9
7. REGISTER DEFINITIONS
Base + 0, Write: DAC LSB register
Bit No.
Name
7
6
5
4
3
2
1
0
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
DA7-0
D/A data bits 7-0. DA0 is the LSB (least significant bit).
Base + 1, Write: DAC MSB register
Bit No.
Name
7
6
5
4
3
2
1
0
X
X
X
X
DA11
DA10
DA9
DA8
X
Bit not used. These bits will be ignored.
D/A data bits 11-8. DA11 is the MSB (most significant bit).
DA11-8
Base + 0 or 1, Read: Update DACs
Reading from these locations updates all DACs to the values written to them. Only DACs with new data
written to them will change. The remaining channels will retain their current values.
Base + 2, Write: DAC channel register
Bit No.
Name
7
6
5
4
3
2
1
0
X
X
X
X
CH3
CH2
CH1
CH0
X
Bit not used. These bits will be ignored.
D/A Channel no. There are 16 channels numbered 0 to 15.
CH3-0
Copyright 2001 Diamond Systems Corp.
Ruby-MM-1612 User Manual V1.1 P. 10
Base + 3, Write: External trigger register
Bit No.
Name
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
TRIGEN
X
Bit not used. These bits will be ignored.
TRIGEN
External trigger enable. 1 = enable, 0 = disable. When external trigger is enabled, digital
I/O line C0 will update all DACs simultaneously when it is brought low. This can be done
either by an external signal, when C0 is in input mode, or in software, when C0 is in
output mode.
If using an external trigger, make sure that the lower half of Port C is in input mode.
Base + 4 through Base + 7
Read/Write
82C55 Digital I/O Registers
These registers map directly to the 82C55 digital I/O chip. The definitions of these registers can be found
in the 82C55 datasheet appended to the back of this manual. A short form description is on the next
page.
These lines power up in input mode. Each line has a 10KW pull-up resistor, so on power-up or system
reset, all lines will indicate a logic high.
Copyright 2001 Diamond Systems Corp.
Ruby-MM-1612 User Manual V1.1 P. 11
8. 82C55 DIGITAL I/O CHIP OPERATION
This is a short form description of the 82C55 digital I/O chip on the board. A full datasheet is included at
the back of this manual.
82C55 Register Map
Base + n, Dir, Function
4, R/W, Port A
D7
A7
B7
C7
1
D6
A6
B6
C6
D5
A5
B5
C5
D4
A4
D3
A3
D2
A2
D1
A1
D0
A0
5, R/W, Port B
B4
B3
B2
B1
B0
6, R/W, Port C
C4
C3
C2
C1
C0
7, W, Config Register
ModeC ModeA
DirA
DirCH
ModeB
DirB
DirCL
Configuration Register
The configuration register is programmed by writing to Base + 7 using the format below. Once you have
set the port directions with this register, you can read and write to the ports as desired.
Bit No.
Name
7
1
6
5
4
3
2
1
0
ModeC ModeA
DirA
DirCH
ModeB
DirB
DirCL
Definitions:
1
Bit 7 must be set to 1 to indicate port mode set operation.
Direction control for bits A7 – A0: 0 = output, 1 = input
Direction control for bits B7 – B0: 0 = output, 1 = input
Direction control for bits C3 – C0: 0 = output, 1 = input
Direction control for bits C7 – C4: 0 = output, 1 = input
DirA
DirB
DirCL
DirCH
ModeA, ModeB, ModeC
I/O Mode for each port, 0 or 1
Here is a list of common configuration register values (others are possible):
Configuration Byte
Hex
Decimal
Port A
Port B
Port C (both halves)
9B
92
99
90
8B
82
89
80
155
146
153
144
139
130
137
128
Input
Input
Input
Input
Output
Output
Output
Output
Input
Input
Output
Output
Input
Input
Output
Output
Input
Output
Input
Output
Input
Output
Input
Output (all ports output)
(all ports input)
Copyright 2001 Diamond Systems Corp.
Ruby-MM-1612 User Manual V1.1 P. 12
9. ANALOG OUTPUT RANGES AND RESOLUTION
The table below lists the available fixed full-scale output ranges and their corresponding actual full-scale
voltage ranges and resolution.
For any output range, the resolution is equal to the maximum possible range of output voltages divided by
the maximum number of possible steps. For a 12-bit D/A converter as is used on the Ruby-MM-1612, the
maximum number of steps is 212 = 4096 (the actual output codes range from 0 to 4095, which is the full
range of possible 12-bit binary numbers). Thus the resolution is equal to 1/4096 times the full-scale
range. This is the smallest possible change in the output and corresponds to a change of 1 in the output
code. Because of this fact the resolution is often referred to as the value of 1 LSB, or 1 least significant
bit.
Table 10.1: Analog Output Ranges and Resolution
Full-Scale
Voltage
10V
Unipolar
or Bipolar
Unipolar
Unipolar
Unipolar
Bipolar
Negative
Range Name Full Scale
Positive
Full Scale
+9.9976V
+4.9988V
+2.4994V
+9.9951V
+4.9963V
+2.4988V
Resolution
(1LSB)
0-10V
0-5V
0-2.5V
±10V
±5V
0V
0V
0V
2.44mV
1.22mV
0.61mV
4.88mV
2.44mV
1.22mV
5V
2.5V
10V
5V
-10V
-5V
-2.5V
Bipolar
Bipolar
2.5V
±2.5V
In the table above, negative full scale refers to the output voltage for a code of 0, and positive full scale
refers to the output voltage for a code of 4095.
Copyright 2001 Diamond Systems Corp.
Ruby-MM-1612 User Manual V1.1 P. 13
10. D/A CODE COMPUTATION
Two different methods are used to compute the 12-bit D/A code used for analog output operations.
For unipolar output ranges (positive voltages only), straight binary coding is used.
For bipolar output ranges (both positive and negative voltages), offset binary coding is used.
For any output range, the resolution is equal to the maximum possible range of output voltages divided by
the maximum number of possible steps. For a 12-bit D/A converter as is used on the Ruby-MM-1612, the
12
maximum number of steps is 2 = 4096 (the actual output codes range from 0 to 4095, which is the full
range of possible 12-bit binary numbers). Thus the resolution is equal to 1/4096 times the full-scale
range. This is the smallest possible change in the output and corresponds to a change of 1 in the output
code. Because of this fact the resolution is often referred to as the value of 1 LSB, or 1 least significant
bit.
Straight Binary Coding (for unipolar output ranges)
This is the simplest form of binary coding. The output voltage is given by:
Output Voltage = (Output Code / 4096) x Full-Scale Voltage
Example:
Output code = 1024, full-scale voltage = 5V
Output voltage = (1024 / 4096) x 5 = .25 x 5 = 1.250V
Conversely, the output code for a desired output voltage is given by:
Output Code = (Desired Output Voltage / Full-Scale Voltage) x 4096
Example:
Desired output voltage = 0.485V, Full-scale voltage = 2.5V
Output Code = (0.485 / 2.5) x 4096 = 0.194 x 4096 = 795 (rounded up)
The relationship between D/A resolution and Full-scale voltage is:
1 LSB = 1/4096 x Full-Scale Voltage
Example: Full-scale voltage = 5V; 1 LSB = 5V / 4096 = 1.22mV
Here is a brief overview of the relationship between output code and output voltage:
Output Code
Explanation
0V
1 LSB
1/2 positive full scale
Positive full scale - 1 LSB
Output Voltage for 0-5V Range
0V
.0024V (2.44mV)
2.5V
4.9988V
0
1
2048
4095
Þ Note: In order to generate an output voltage of positive full scale, you would have to output a code of
4096 (4096 / 4096 x full-scale = full-scale). However, 4096 is a 13-bit number which cannot be
reproduced on a 12-bit D/A converter. The highest number that can be output is 4095, which is 4096 - 1.
This results in a maximum output voltage of full scale minus 1 LSB for any analog output range. This
phenomenon is true for all D/A and A/D converters.
Copyright 2001 Diamond Systems Corp.
Ruby-MM-1612 User Manual V1.1 P. 14
Offset Binary Coding (for bipolar output ranges)
This method takes into account the fact that the lowest output voltage is not zero but a negative value.
The output voltage is given by:
Output Voltage = (Output Code / 2048) x Full-Scale Voltage - Full-Scale Voltage
Example:
Output code = 1024, full-scale voltage = 5V
Output voltage = (1024 / 2048) x 5 - 5 = (0.5 x 5) - 5 = -2.500V
Note the difference between this output voltage to the output voltage using straight binary coding shown
above using the same output code.
Conversely, the output code for a desired output voltage is given by:
Output Code = (Desired Output Voltage / Full-Scale Voltage) x 2048 + 2048
Example:
Desired output voltage = 0.485V, Full-scale voltage = 2.5V
Output Code = (0.485 / 2.5) x 2048 + 2048 = 0.194 x 2048 + 2048 = 2445
(rounded down)
The relationship between D/A resolution and Full-scale voltage is:
1 LSB = 1/2048 x Full-Scale Voltage
Example: Full-scale voltage = 5V; 1 LSB = 5V / 2048 = 2.44mV
The reason that 1 LSB for a bipolar range is twice the magnitude of 1 LSB for a unipolar range with the
same full-scale voltage is that for the bipolar range, the full voltage span is twice the magnitude. For
example, a unipolar range with a full-scale voltage of 5V has a range of 0V to 5V, for a total span of 5V.
However, a bipolar range with a full-scale voltage of 5V has a range of ±5V, for a total span of 10V.
Here is a brief overview of the relationship between output code and output voltage:
Output Code Explanation
Output Voltage for ±5V Range
0
1
Negative full scale
Negative full scale + 1 LSB
-5V
-4.9976V
2047
2048
2049
4095
-1 LSB
0V
+1 LSB
Positive full scale - 1 LSB
-.0024V (-2.44mV)
0V
+.0024V (+2.44mV)
+4.9976V
Þ Note: Again, an output code of 4096 would be required to generate the positive-full-scale output
voltage, but since that is impossible, the maximum output voltage is 1 LSB less then positive full scale.
Copyright 2001 Diamond Systems Corp.
Ruby-MM-1612 User Manual V1.1 P. 15
11. HOW TO GENERATE AN ANALOG OUTPUT
This chapter describes how to generate an analog output directly (without the use of the driver software).
Ruby-MM-1612 has 12-bit resolution analog outputs. However, data is written to the board in 8-bit bytes.
Therefore two bytes must be written to the board to generate a single analog output. In addition, many
applications require several channels to be updated simultaneously. In order to provide this ability, the
update operation is separate from the data write operation.
Thus there are three steps required to generate an analog output. Each step is described in detail. The
steps must be completed in the sequence shown below.
To generate an analog output on one or more channels:
1. Write the LSB (least significant byte) to the board at register Base + 0.
2. Write the channel number to the board at register Base + 2..
3. Write the MSB (most significant byte) to the board.
4. Repeat steps 1-3 for each channel to be changed
5. Update all changed channels by reading Base + 0 or Base + 1.
Hardware Update Command
A hardware update command can occur with a falling edge on the external trigger, pin 48 of J3.
To use hardware updating, or triggering, you must program the TRIGEN bit at Base + 3. See Chapter 3
for details.
Þ Note: When a channel is updated, its output will change only if new data has been written to it since
the last update. For example, if you do a simultaneous update on all channels but you only wrote data to
channel 0, then only channel 0 will change, and channels 1 - 15 will stay the same.
Þ Note: If hardware updating is enabled, software updating will still work.
Copyright 2001 Diamond Systems Corp.
Ruby-MM-1612 User Manual V1.1 P. 16
Examples
Single channel output
Assume channels 0 - 7 are configured for 0-5V. To set channel 0 to 3V, do the following:
D/A code is 3V / 5V x 4096 = 2458 (value is rounded to nearest integer)
LSB = 2458 AND 255 = 154
MSB = (2458 AND 3840) / 256 = 9
Step 1. Write 154 to base + 0 (LSB register).
Step 2. Write 0 to base + 2 (Channel register).
Step 3. Write 9 to base + 1 (MSB register). The value 2458 is written to DAC 0.
Step 4. Read from base + 0. DAC 0 now outputs 3.000V.
Two channel output
Assume channels 0 - 7 are configured for 0-5V. To set channel 0 to 3.8V and channel 3 to 1.5V, do the
following:
D/A code for channel 0 = 3.8 / 5 x 4096 = 3113
LSB = 3113 AND 255 = 41
MSB = (3113 AND 3840) / 256 = 12
D/A code for channel 1 = 1.5 / 5 x 4096 = 1229
LSB = 1229 AND 255 = 205
MSB = (1229 AND 3840) / 256 = 4
Step 1. Write 41 to base + 0 (LSB register).
Step 2. Write 0 to base + 2 (Channel register).
Step 3. Write 12 to base + 1 (MSB register). The value 3113 is written to DAC 0.
Step 4. Write 205 to base + 0 (LSB register).
Step 5. Write 0 to base + 2 (Channel register).
Step 6. Write 4 to base + 1 (MSB register). The value 1229 is written to DAC 1.
Step 7. Read from base + 0. DAC 0 and DAC3 are both updated to their new output voltages. All
other channels remain at their existing output voltages.
Copyright 2001 Diamond Systems Corp.
Ruby-MM-1612 User Manual V1.1 P. 17
12. CALIBRATION PROCEDURE
Calibration requires a voltmeter (at least 5 digits of precision is preferred) and a miniature screwdriver to
turn the potentiometer screws. The common lead of the voltmeter must be connected to analog ground
(not digital ground). The best source for this connection is any of the analog ground pins on the user I/O
header J3.
Þ Note: All steps should be completed in the sequence shown, since each step affects the following
steps. (Steps 4 and 5 may be interchanged since they do not depend on each other.)
+5.000V Reference Voltage Adjust
Install a jumper in position “5” on J4. Connect the high side lead of the voltmeter to the upper pin of J4
under either location marked “F”. Adjust R1 so that the voltmeter reads +5.000V.
+10.00V Reference Voltage Adjust
Keep the voltmeter connected to as described above. Remove the jumper in position “5” on J4 and
adjust R2 so that the voltmeter reads +10.000V.
Adjustable Reference Adjust
This step can be skipped if you are not using the adjustable reference.
Connect the voltmeter to the upper pin of J4 below either location marked “A” on J4. Adjust R3 so that
the voltmeter reads the desired full-scale voltage range. This voltage is factory-preset to 2.500V. Any
adjustment from about 1V to slightly over 2.5V is achievable.
Negative Full-Scale Reference Adjust, Channels 0 - 7
Install jumpers in positions “5” and the leftmost “F” on J4. Connect the voltmeter to the upper pin on J4
under the leftmost “B”. Adjust R4 so that the voltmeter reads –4.999V. With this setting, the D/A will
actually output closer to –5.000V when it is loaded with all zeros. This value can be adjusted later if
desired by measuring the actual D/A output.
Negative Full-Scale Reference Adjust, Channels 8-15
Install jumpers in positions “5” and the rightmost “F” on J4. Connect the voltmeter to the upper pin on J4
under the rightmost “B”. Adjust R5 so that the voltmeter reads –4.999V.
Copyright 2001 Diamond Systems Corp.
Ruby-MM-1612 User Manual V1.1 P. 18
13. SPECIFICATIONS
Analog Outputs
No. of outputs
Resolution
16 voltage outputs
12 bits (1 part in 4096)
Fixed output ranges
0 - 5V, 0 - 10V unipolar, ±5V, ±10V bipolar
Adjustable output range Preset to 2.5V for 0 - 2.5V, ±2.5V output ranges
Can be adjusted anywhere between approx. 1V and 2.5V
External reference
Settling time
0V min, 10V max
6ms max to ±.01%
Accuracy
±1LSB
Integral nonlinearity
Differential nonlinearity
Output current
Minimum output load
Update method
Reset
±1LSB max
-1LSB max, guaranteed monotonic
±5mA max per channel
2KW
Simultaneous, software command or external trigger
All DACs reset to mid-scale
(0V for bipolar ranges, 1/2 full-scale for unipolar ranges)
Digital I/O
No. of lines
Compatibility
Input voltage
24
CMOS / TTL
Logic 0:
Logic 1:
-0.5V min, 0.8V max
2.0V min, 5.5V max
Output voltage
Logic 0:
Logic 1:
0.0V min, 0.4V max
3.0V min, Vcc - 0.4V max
Output current
Pull-up resistor
External trigger
Reset
±2.5mA max per line
10KW resistor on each I/O line
TTL / CMOS compatible, 10KW pull-up resistor, active low edge
All digital output lines are set to 0
Miscellaneous
Power supply (Vcc)
Current requirement
Operating temperature
Operating humidity
Size
+5VDC ±10%
430mA, all outputs unloaded
-40 to +85oC
5 to 95% non-condensing
3.55” x 3.775”
Data bus
8 bits
(16-bit header can be installed for
pass-through function but is not used on board)
Copyright 2001 Diamond Systems Corp.
Ruby-MM-1612 User Manual V1.1 P. 19
82C55A
CMOS Programmable
Peripheral Interface
June 1998
Features
Description
• Pin Compatible with NMOS 8255A
• 24 Programmable I/O Pins
• Fully TTL Compatible
The Intersil 82C55A is a high performance CMOS version of
the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may be
used with many different microprocessors. There are 24 I/O
pins which may be individually programmed in 2 groups of
12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.
• High Speed, No “Wait State” Operation with 5MHz and
8MHz 80C86 and 80C88
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• L7 Process
Static CMOS circuit design insures low operating power. TTL
compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
Intersil advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.
• 2.5mA Drive Capability on All I/O Ports
• Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . .10µA
Ordering Information
PART NUMBERS
TEMPERATURE PKG.
5MHz
8MHz
PACKAGE
RANGE
NO.
E40.6
E40.6
N44.65
N44.65
F40.6
F40.6
F40.6
F40.6
o
o
CP82C55A-5
IP82C55A-5
CS82C55A-5
IS82C55A-5
CD82C55A-5
ID82C55A-5
CP82C55A
IP82C55A
CS82C55A
IS82C55A
CD82C55A
ID82C55A
0 C to 70 C
40 Ld PDIP
o
o
-40 C to 85 C
o
o
0 C to 70 C
44 Ld PLCC
o
o
-40 C to 85 C
o
o
0 C to 70 C
40 Ld
CERDIP
o
o
-40 C to 85 C
o
o
MD82C55A-5/B MD82C55A/B
8406601QA 8406602QA
-55 C to 125 C
SMD#
44 Pad
CLCC
o
o
MR82C55A-5/B MR82C55A/B
-55 C to 125 C
J44.A
J44.A
8406601XA
8406602XA
SMD#
Pinouts
82C55A (DIP)
TOP VIEW
82C55A (CLCC)
82C55A (PLCC)
TOP VIEW
TOP VIEW
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
PA3
PA2
PA1
PA0
RD
PA4
6
5
4
3
2
1
44 43 42 41 40
PA5
PA6
PA7
WR
RESET
D0
6
5
4
3
2
1 44 43 42 41 40
3
39
38
7
8
GND
NC
NC
RESET
D0
4
CS
GND
A1
A0
PC7
NC
7
8
9
39
38
37 D1
RESET
D0
5
37
36
35
34
33
32
31
9
A1
6
CS
10
11
12
13
14
15
16
17
A0
D1
10
11
12
13
14
15
16
17
D2
D3
NC
D4
D5
D6
D7
V
36
35
34
33
32
31
30
29
7
GND
A1
PC7
PC6
PC5
PC4
PC0
PC1
PC2
D2
8
D1
D3
9
A0
D2
D4
PC6
PC5
PC4
PC0
PC1
10
11
12
13
14
15
16
17
18
19
20
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
D3
D5
D4
D6
D5
30 D7
29 NC
D6
CC
D7
18 1920 21 22 23 24 25 26 27 28
18 19 20 21 22 23 24 25 26 27 28
26 V
CC
PB7
25
24
23
22
21
PB6
PB5
PB4
PB3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 2969.2
1
82C55A
Pin Description
PIN
SYMBOL
NUMBER
TYPE
DESCRIPTION
: The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is
V
26
V
CC
CC
recommended for decoupling.
GND
7
GROUND
D0-D7
27-34
I/O
DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the
system data bus.
RESET
CS
35
6
I
I
I
I
I
RESET: A high on this input clears the control register and all ports (A, B, C) are set
to the input mode with the “Bus Hold” circuitry turned on.
CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the
Data Bus for CPU communications.
RD
5
READ: Read is an active low input control signal used by the CPU to read status
information or data via the data bus.
WR
36
8, 9
WRITE: Write is an active low input control signal used by the CPU to load control
words and data into the 82C55A.
A0-A1
ADDRESS: These input signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word register. A0 and A1 are
normally connected to the least significant bits of the Address Bus A0, A1.
PA0-PA7
1-4, 37-40
I/O
PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are
present on this port.
PB0-PB7
PC0-PC7
18-25
10-17
I/O
I/O
PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.
PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.
Functional Diagram
I/O
PA7-PA0
+5V
GROUP A
PORT A
(8)
POWER
SUPPLIES
GND
GROUP A
CONTROL
GROUP A
PORT C
UPPER
(4)
I/O
PC7-PC4
BI-DIRECTIONAL
DATA BUS
DATA BUS
BUFFER
D7-D0
GROUP B
PORT C
LOWER
(4)
8-BIT
INTERNAL
DATA BUS
I/O
PC3-PC0
RD
WR
A1
READ
WRITE
CONTROL
LOGIC
GROUP B
CONTROL
GROUP B
PORT B
(8)
I/O
PB7-PB0
A0
RESET
CS
2
82C55A
Functional Description
I/O
PA7-
PA0
+5V
GND
GROUP A
PORT A
(8)
POWER
SUPPLIES
Data Bus Buffer
GROUP A
CONTROL
This three-state bi-directional 8-bit buffer is used to interface
the 82C55A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status informa-
tion are also transferred through the data bus buffer.
I/O
PC7-
PC4
GROUP A
PORT C
UPPER
(4)
BI-DIRECTIONAL
DATA BUS
I/O
DATA
PC3-
PC0
BUS
BUFFER
GROUP B
PORT C
LOWER
(4)
D7-D0
8-BIT
INTERNAL
DATA BUS
Read/Write and Control Logic
The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words.
It accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of the Control Groups.
I/O
PB7-
PB0
RD
WR
A1
READ
WRITE
CONTROL
LOGIC
GROUP B
CONTROL
GROUP B
PORT B
(8)
A0
RESET
(CS) Chip Select. A “low” on this input pin enables the
communcation between the 82C55A and the CPU.
CS
(RD) Read. A “low” on this input pin enables 82C55A to send
the data or status information to the CPU on the data bus. In
essence, it allows the CPU to “read from” the 82C55A.
FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,
READ/WRITE, GROUP A & B CONTROL LOGIC
FUNCTIONS
(WR) Write. A “low” on this input pin enables the CPU to
write data or control words into the 82C55A.
(RESET) Reset. A “high” on this input initializes the control
register to 9Bh and all ports (A, B, C) are set to the input
mode. “Bus hold” devices internal to the 82C55A will hold
the I/O port inputs to a logic “1” state with a maximum hold
current of 400µA.
(A0 and A1) Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word
register. They are normally connected to the least significant
bits of the address bus (A0 and A1).
Group A and Group B Controls
82C55A BASIC OPERATION
The functional configuration of each port is programmed by
the systems software. In essence, the CPU “outputs” a con-
trol word to the 82C55A. The control word contains
information such as “mode”, “bit set”, “bit reset”, etc., that ini-
tializes the functional configuration of the 82C55A.
INPUT OPERATION
A1
0
A0
0
RD WR CS
(READ)
Port A → Data Bus
Port B → Data Bus
Port C → Data Bus
Control Word → Data Bus
0
0
0
0
1
1
1
1
0
0
0
0
Each of the Control blocks (Group A and Group B) accepts
“commands” from the Read/Write Control logic, receives
“control words” from the internal data bus and issues the
proper commands to its associated ports.
0
1
1
0
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
1
1
OUTPUT OPERATION
(WRITE)
The control word register can be both written and read as
shown in the “Basic Operation” table. Figure 4 shows the
control word format for both Read and Write operations.
When the control word is read, bit D7 will always be a logic
“1”, as this implies control word mode information.
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
Data Bus → Port A
Data Bus → Port B
Data Bus → Port C
Data Bus → Control
DISABLE FUNCTION
Data Bus → Three-State
Data Bus → Three-State
X
X
X
X
X
1
X
1
1
0
3
82C55A
Ports A, B, and C
register will contain 9Bh. During the execution of the system
program, any of the other modes may be selected using a
single output instruction. This allows a single 82C55A to
service a variety of peripheral devices with a simple software
maintenance routine. Any port programmed as an output
port is initialized to all zeros when the control word is written.
The 82C55A contains three 8-bit ports (A, B, and C). All can
be configured to a wide variety of functional characteristics
by the system software but each has its own special features
or “personality” to further enhance the power and flexibility of
the 82C55A.
ADDRESS BUS
CONTROL BUS
DATA BUS
Port A One 8-bit data output latch/buffer and one 8-bit data
input latch. Both “pull-up” and “pull-down” bus-hold devices
are present on Port A. See Figure 2A.
Port B One 8-bit data input/output latch/buffer and one 8-bit
data input buffer. See Figure 2B.
Port C One 8-bit data output latch/buffer and one 8-bit data
input buffer (no latch for input). This port can be divided into
two 4-bit ports under the mode control. Each 4-bit port con-
tains a 4-bit latch and it can be used for the control signal
output and status signal inputs in conjunction with ports A
and B. See Figure 2B.
RD, WR
D7-D0
A0-A1
CS
82C55A
C
MODE 0
MODE 1
B
8
A
8
I/O
4
I/O
4
I/O
I/O
PB7-PB0 PC3-PC0 PC7-PC4 PA7-PA0
C
INPUT MODE
MASTER
RESET
B
A
OR MODE
CHANGE
8
I/O
8
I/O
INTERNAL
DATA IN
EXTERNAL
PORT A PIN
PB7-PB0 CONTROL CONTROL PA7-PA0
OR I/O OR I/O
INTERNAL
DATA OUT
(LATCHED)
MODE 2
C
B
8
A
OUTPUT MODE
BI-
I/O
FIGURE 2A. PORT A BUS-HOLD CONFIGURATION
DIRECTIONAL
V
CC
PB7-PB0
PA7-PA0
RESET
OR MODE
CHANGE
CONTROL
P
FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
GROUP B
INTERNAL
DATA IN
EXTERNAL
PORT B, C
PIN
INTERNAL
DATA OUT
(LATCHED)
PORT C (LOWER)
1 = INPUT
0 = OUTPUT
OUTPUT MODE
PORT B
1 = INPUT
0 = OUTPUT
FIGURE 2B. PORT B AND C BUS-HOLD CONFIGURATION
FIGURE 2. BUS-HOLD CONFIGURATION
MODE SELECTION
0 = MODE 0
1 = MODE 1
Operational Description
GROUP A
Mode Selection
PORT C (UPPER)
1 = INPUT
There are three basic modes of operation than can be
selected by the system software:
Mode 0 - Basic Input/Output
0 = OUTPUT
PORT A
1 = INPUT
0 = OUTPUT
Mode 1 - Strobed Input/Output
Mode 2 - Bi-directional Bus
MODE SELECTION
00 = MODE 0
When the reset input goes “high”, all ports will be set to the
input mode with all 24 port lines held at a logic “one” level by
internal bus hold devices. After the reset is removed, the
82C55A can remain in the input mode with no additional ini-
tialization required. This eliminates the need to pullup or pull-
down resistors in all-CMOS designs. The control word
01 = MODE 1
1X = MODE 2
MODE SET FLAG
1 = ACTIVE
FIGURE 4. MODE DEFINITION FORMAT
4
82C55A
The modes for Port A and Port B can be separately defined, This function allows the programmer to enable or disable a
while Port C is divided into two portions as required by the CPU interrupt by a specific I/O device without affecting any
Port A and Port B definitions. All of the output registers, other device in the interrupt structure.
including the status flip-flops, will be reset whenever the
INTE Flip-Flop Definition
mode is changed. Modes may be combined so that their
functional definition can be “tailored” to almost any I/O
structure. For instance: Group B can be programmed in
Mode 0 to monitor simple switch closings or display compu-
tational results, Group A could be programmed in Mode 1 to
monitor a keyboard or tape reader on an interrupt-driven
basis.
(BIT-SET)-INTE is SET - Interrupt Enable
(BIT-RESET)-INTE is Reset - Interrupt Disable
NOTE: All Mask flip-flops are automatically reset during mode se-
lection and device Reset.
The mode definitions and possible mode combinations may Operating Modes
seem confusing at first, but after a cursory review of the
Mode 0 (Basic Input/Output). This functional configuration
complete device operation a simple, logical I/O approach will
surface. The design of the 82C55A has taken into account
things such as efficient PC board layout, control signal defi-
nition vs. PC layout and complete functional flexibility to sup-
port almost any peripheral device with no external logic.
Such design represents the maximum use of the available
pins.
provides simple input and output operations for each of the
three ports. No handshaking is required, data is simply writ-
ten to or read from a specific port.
Mode 0 Basic Functional Definitions:
• Two 8-bit ports and two 4-bit ports
• Any Port can be input or output
• Outputs are latched
Single Bit Set/Reset Feature (Figure 5)
Any of the eight bits of Port C can be Set or Reset using a
single Output instruction. This feature reduces software • Input are not latched
requirements in control-based applications.
• 16 different Input/Output configurations possible
When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit Set/Reset
operation just as if they were output ports.
MODE 0 PORT DEFINITION
A
B
GROUP A
PORTC
GROUP B
PORTC
CONTROL WORD
D4 D3
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D0 PORT A (Upper)
#
0
1
2
3
4
5
6
7
8
9
PORT B (Lower)
D7 D6 D5 D4 D3 D2 D1 D0
BIT SET/RESET
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output Output
Output Output
Output Output
Output Output
Output Output
Output
Input
Input
Output
Input
X
X
X
1 = SET
0 = RESET
DON’T
CARE
Input
BIT SELECT
0 1 2 3 4 5 6 7
0 1 0 1 0 1 0 1 B0
0 0 1 1 0 0 1 1 B1
0 0 0 0 1 1 1 1 B2
Output
Output
Output
Output
Input
Input
Input
Output Output
Output
Input
Input
Output
Input
Input
Input
Input
BIT SET/RESET FLAG
0 = ACTIVE
Output
Output
Output Output
Input
Output
Input
Input
Output
Input
FIGURE 5. BIT SET/RESET FORMAT
Input
Output 10
Output 11
Interrupt Control Functions
Input
Input
When the 82C55A is programmed to operate in mode 1 or
mode 2, control signals are provided that can be used as
interrupt request inputs to the CPU. The interrupt request
signals, generated from port C, can be inhibited or enabled
by setting or resetting the associated INTE flip-flop, using the
bit set/reset function of port C.
Input
Input
Input
Input
Input
12 Output Output
Input
13 Output
Input
Output
Input
Input
14
15
Input
Input
Input
5
82C55A
Mode 0 (Basic Input)
tRR
RD
tIR
tHR
INPUT
CS, A1, A0
D7-D0
tAR
tRA
tRD
tDF
Mode 0 (Basic Output)
tWW
WR
tWD
tDW
D7-D0
CS, A1, A0
OUTPUT
tAW
tWA
tWB
Mode 0 Configurations
CONTROL WORD #0
CONTROL WORD #2
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
8
4
8
4
PA7 - PA0
PC7 - PC4
PA7 - PA0
PC7 - PC4
A
A
82C55A
C
82C55A
C
D7 - D0
D7 - D0
4
8
4
8
PC3 - PC0
PB7 - PB0
PC3 - PC0
PB7 - PB0
B
B
CONTROL WORD #1
CONTROL WORD #3
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
8
4
8
4
PA7 - PA0
PC7 - PC4
PA7 - PA0
PC7 - PC4
A
A
82C55A
C
82C55A
C
D7 - D0
D7 - D0
4
8
4
8
PC3 - PC0
PB7 - PB0
PC3 - PC0
PB7 - PB0
B
B
6
82C55A
Mode 0 Configurations (Continued)
CONTROL WORD #4
CONTROL WORD #8
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
8
4
8
4
PA7 - PA0
PC7 - PC4
PA7 - PA0
PC7 - PC4
A
A
82C55A
C
82C55A
C
D7 - D0
D7 - D0
4
8
4
8
PC3 - PC0
PB7 - PB0
PC3 - PC0
PB7 - PB0
B
B
CONTROL WORD #5
CONTROL WORD #9
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
1
0
0
1
1
0
0
1
0
0
0
1
8
4
8
4
PA7 - PA0
PC7 - PC4
PA7 - PA0
PC7 - PC4
A
A
82C55A
C
82C55A
C
D7 - D0
D7 - D0
4
8
4
8
PC3 - PC0
PB7 - PB0
PC3 - PC0
PB7 - PB0
B
B
CONTROL WORD #6
CONTROL WORD #10
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
1
0
1
0
1
0
0
1
0
0
1
0
8
4
8
4
PA7 - PA0
PC7 - PC4
PA7 - PA0
PC7 - PC4
A
A
82C55A
C
82C55A
C
D7 - D0
D7 - D0
4
8
4
8
PC3 - PC0
PB7 - PB0
PC3 - PC0
PB7 - PB0
B
B
CONTROL WORD #7
CONTROL WORD #11
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
1
0
1
1
1
0
0
1
0
0
1
1
8
4
8
4
PA7 - PA0
PC7 - PC4
PA7 - PA0
PC7 - PC4
A
A
82C55A
C
82C55A
C
D7 - D0
D7 - D0
4
8
4
8
PC3 - PC0
PB7 - PB0
PC3 - PC0
PB7 - PB0
B
B
7
82C55A
Mode 0 Configurations (Continued)
CONTROL WORD #12
CONTROL WORD #14
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
1
0
0
0
1
0
0
1
1
0
1
0
8
4
8
4
PA7 - PA0
PC7 - PC4
PA7 - PA0
PC7 - PC4
A
A
82C55A
C
82C55A
C
D7 - D0
D7 - D0
4
8
4
8
PC3 - PC0
PB7 - PB0
PC3 - PC0
PB7 - PB0
B
B
CONTROL WORD #13
CONTROL WORD #15
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
8
4
8
4
PA7 - PA0
PC7 - PC4
PA7 - PA0
PC7 - PC4
A
A
82C55A
C
82C55A
C
D7 - D0
D7 - D0
4
8
4
8
PC3 - PC0
PB7 - PB0
PC3 - PC0
PB7 - PB0
B
B
Operating Modes
MODE 1 (PORT A)
PA7-PA0
Mode 1 - (Strobed Input/Output). This functional configura-
tion provides a means for transferring I/O data to or from a
specified port in conjunction with strobes or “hand shaking”
signals. In mode 1, port A and port B use the lines on port C
to generate or accept these “hand shaking” signals.
8
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1/0
INTE
PC4
STBA
A
1
0
1
1
PC5
IBFA
PC6, PC7
1 = INPUT
0 = OUTPUT
Mode 1 Basic Function Definitions:
• Two Groups (Group A and Group B)
INTRA
I/O
PC3
2
RD
• Each group contains one 8-bit port and one 4-bit
control/data port
PC6, PC7
• The 8-bit data port can be either input or output. Both
inputs and outputs are latched.
MODE 1 (PORT B)
PB7-PB0
• The 4-bit port is used for control and status of the 8-bit
port.
8
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
INTE
PC2
Input Control Signal Definition
B
STBB
IBFB
1
1
1
PC1
(Figures 6 and 7)
STB (Strobe Input)
INTRB
PC0
A “low” on this input loads data into the input latch.
RD
IBF (Input Buffer Full F/F)
FIGURE 6. MODE 1 INPUT
A “high” on this output indicates that the data has been
loaded into the input latch: in essence, and acknowledg-
ment. IBF is set by STB input being low and is reset by the
rising edge of the RD input.
8
82C55A
tST
STB
IBF
tSIB
tSIT
tRIB
INTR
RD
tRIT
tPH
INPUT FROM
PERIPHERAL
tPS
FIGURE 7. MODE 1 (STROBED INPUT)
INTE A
INTR (Interrupt Request)
A “high” on this output can be used to interrupt the CPU Controlled by Bit Set/Reset of PC6.
when and input device is requesting service. INTR is set by
INTE B
the condition: STB is a “one”, IBF is a “one” and INTE is a
“one”. It is reset by the falling edge of RD. This procedure
allows an input device to request service from the CPU by
simply strobing its data into the port.
Controlled by Bit Set/Reset of PC2.
NOTE:
1. To strobe data into the peripheral device, the user must operate
the strobe line in a hand shaking mode. The user needs to send
OBF to the peripheral device, generates an ACK from the pe-
ripheral device and then latch data into the peripheral device on
the rising edge of OBF.
INTE A
Controlled by bit set/reset of PC4.
INTE B
MODE 1 (PORT A)
Controlled by bit set/reset of PC2.
8
PA7-PA0
PC7
CONTROL WORD
Output Control Signal Definition
D7 D6 D5 D4 D3 D2 D1 D0
OBFA
ACKA
(Figure 8 and 9)
1
0
1
1
1/0
INTE
A
PC6
OBF - Output Buffer Full F/F). The OBF output will go “low”
to indicate that the CPU has written data out to be specified
port. This does not mean valid data is sent out of the part at
this time since OBF can go true before data is available.
Data is guaranteed valid at the rising edge of OBF, (See
Note 1). The OBF F/F will be set by the rising edge of the
WR input and reset by ACK input being low.
PC4, PC5
1 = INPUT
0 = OUTPUT
INTRA
PC3
2
WR
PC4, PC5
ACK - Acknowledge Input). A “low” on this input informs the
82C55A that the data from Port A or Port B is ready to be
accepted. In essence, a response from the peripheral device
indicating that it is ready to accept data, (See Note 1).
MODE 1 (PORT B)
PB7-PB0
8
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
OBFB
ACKB
PC1
INTR - (Interrupt Request). A “high” on this output can be
used to interrupt the CPU when an output device has
accepted data transmitted by the CPU. INTR is set when
ACK is a “one”, OBF is a “one” and INTE is a “one”. It is
reset by the falling edge of WR.
1
1
0
INTE
PC2
B
INTRB
PC0
WR
FIGURE 8. MODE 1 OUTPUT
9
82C55A
tWOB
WR
tAOB
OBF
INTR
tWIT
ACK
tAK
tAIT
OUTPUT
tWB
FIGURE 9. MODE 1 (STROBED OUTPUT)
8
8
PA7-PA0
PC4
PA7-PA0
PC7
STBA
IIBFA
INTRA
I/O
OBFA
ACKA
INTRA
I/O
RD
WR
CONTROL WORD
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
PC5
PC3
PC6
PC3
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
1
1/0
1
0
1
0
1
0
1/0
1
1
2
2
PC6, PC7
PC4, PC5
PC6, PC7
PC4, PC5
1 = INPUT
0 = OUTPUT
1 = INPUT
0 = OUTPUT
8
PB7, PB0
PB7, PB0
8
PC1
PC2
PC0
PC2
PC1
PC0
OBFB
ACKB
INTRB
STBB
IBFB
WR
RD
INTRB
PORT A - (STROBED INPUT)
PORT B - (STROBED OUTPUT)
PORT A - (STROBED OUTPUT)
PORT B - (STROBED INPUT)
Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O
applications.
FIGURE 10. COMBINATIONS OF MODE 1
Operating Modes
Mode 2 (Strobed Bi-Directional Bus I/O)
Output Operations
The functional configuration provides a means for communi-
cating with a peripheral device or structure on a single 8-bit
bus for both transmitting and receiving data (bi-directional
bus I/O). “Hand shaking” signals are provided to maintain
proper bus flow discipline similar to Mode 1. Interrupt gener-
ation and enable/disable functions are also available.
OBF - (Output Buffer Full). The OBF output will go “low” to
indicate that the CPU has written data out to port A.
ACK - (Acknowledge). A “low” on this input enables the
three-state output buffer of port A to send out the data. Oth-
erwise, the output buffer will be in the high impedance state.
INTE 1 - (The INTE flip-flop associated with OBF). Con-
trolled by bit set/reset of PC4.
Mode 2 Basic Functional Definitions:
• Used in Group A only
• One 8-bit, bi-directional bus Port (Port A) and a 5-bit
control Port (Port C)
Input Operations
STB - (Strobe Input). A “low” on this input loads data into the
input latch.
• Both inputs and outputs are latched
• The 5-bit control port (Port C) is used for control and
status for the 8-bit, bi-directional bus port (Port A)
IBF - (Input Buffer Full F/F). A “high” on this output indicates
that data has been loaded into the input latch.
Bi-Directional Bus I/O Control Signal Definition
INTE 2 - (The INTE flip-flop associated with IBF). Controlled
(Figures 11, 12, 13, 14)
by bit set/reset of PC4.
INTR - (Interrupt Request). A high on this output can be
used to interrupt the CPU for both input or output operations.
10
82C55A
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
INTRA
PC3
1
1
1/0 1/0 1/0
PA7-PA0
PC7
8
OBFA
ACKA
INTE
PC6
PC2-PC0
1 = INPUT
0 = OUTPUT
1
INTE
2
STBA
IBFA
PC4
PC5
PORT B
1 = INPUT
0 = OUTPUT
WR
RD
GROUP B MODE
0 = MODE 0
1 = MODE 1
3
PC2-PC0
I/O
FIGURE 11. MODE CONTROL WORD
FIGURE 12. MODE 2
DATA FROM
CPU TO 82C55A
WR
tAOB
OBF
INTR
ACK
tWOB
tAK
tST
STB
IBF
tSIB
tPS
tAD
tKD
PERIPHERAL
BUS
tRIB
tPH
RD
DATA FROM
PERIPHERAL TO 82C55A
DATA FROM
82C55A TO PERIPHERAL
DATA FROM
82C55A TO CPU
NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF • MASK • STB • RD ÷ OBF •
MASK • ACK • WR)
FIGURE 13. MODE 2 (BI-DIRECTIONAL)
11
82C55A
MODE 2 AND MODE 0 (INPUT)
MODE 2 AND MODE 0 (OUTPUT)
PC3
PC3
INTRA
INTRA
PA7-PA0
PA7-PA0
8
8
OBFA
ACKA
OBFA
ACKA
PC7
PC6
PC4
PC7
PC6
PC4
CONTROL WORD
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
1
0
1
1/0
1
1
0
0
1/0
STBA
IBFA
STBA
IBFA
I/O
PC2-PC0
1 = INPUT
0 = OUTPUT
PC2-PC0
1 = INPUT
0 = OUTPUT
PC5
PC5
3
3
8
PC2-PC0
I/O
PC2-PC0
RD
RD
PB7-PB0
PB7, PB0
8
WR
WR
MODE 2 AND MODE 1 (OUTPUT)
MODE 2 AND MODE 1 (INPUT)
PC3
PC3
INTRA
INTRA
PA7-PA0
PA7-PA0
8
8
OBFA
ACKA
OBFA
ACKA
PC7
PC6
PC4
PC7
PC6
PC4
CONTROL WORD
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
STBA
IBFA
STBA
IBFA
1
1
1
0
1
1
1
1
PC5
PC5
PB7-PB0
PB7-PB0
8
8
OBFB
ACKB
STBB
IBFB
PC1
PC2
PC0
PC2
PC1
PC0
RD
RD
INTRB
INTRB
WR
WR
FIGURE 14. MODE 2 COMBINATIONS
12
82C55A
MODE DEFINITION SUMMARY
MODE 1
MODE 0
MODE 2
IN
OUT
IN
OUT
GROUP A ONLY
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
Mode 0
or Mode 1
Only
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
In
In
In
In
In
In
In
In
Out
Out
Out
Out
Out
Out
Out
Out
INTRB
IBFB
STBB
INTRA
STBA
IBFA
I/O
INTRB
OBFB
ACKB
INTRA
I/O
I/O
ACKA
OBFA
I/O
I/O
I/O
INTRA
STBA
IBFA
ACKA
OBFA
I/O
Special Mode Combination Considerations
INPUT CONFIGURATION
D5 D4 D3 D2
There are several combinations of modes possible. For any
combination, some or all of Port C lines are used for control
or status. The remaining bits are either inputs or outputs as
defined by a “Set Mode” command.
D7
D6
D1
D0
I/O
I/O
IBFA INTEA INTRA INTEB IBFB INTRB
GROUP A
OUTPUT CONFIGURATION
GROUP B
During a read of Port C, the state of all the Port C lines,
except the ACK and STB lines, will be placed on the data
bus. In place of the ACK and STB line states, flag status will
appear on the data bus in the PC2, PC4, and PC6 bit
positions as illustrated by Figure 17.
D7
D6
D5
D4
D3
D2
D1
D0
OBFA INTEA
I/O
I/O
INTRA INTEB OBFB INTRB
GROUP B
Through a “Write Port C” command, only the Port C pins
programmed as outputs in a Mode 0 group can be written.
No other pins can be affected by a “Write Port C” command,
nor can the interrupt enable flags be accessed. To write to
any Port C output programmed as an output in Mode 1 group
or to change an interrupt enable flag, the “Set/Reset Port C
Bit” command must be used.
GROUP A
FIGURE 15. MODE 1 STATUS WORD FORMAT
D7
D6
D5
D4
D3
D2
D1
D0
OBFA INTE1 IBFA INTE2 INTRA
X
X
X
GROUP A
GROUP B
With a “Set/Reset Port Cea Bit” command, any Port C line
programmed as an output (including IBF and OBF) can be
written, or an interrupt enable flag can be either set or reset.
Port C lines programmed as inputs, including ACK and STB
lines, associated with Port C fare not affected by a
“Set/Reset Port C Bit” command. Writing to the correspond-
ing Port C bit positions of the ACK and STB lines with the
“Set Reset Port C Bit” command will affect the Group A and
Group B interrupt enable flags, as illustrated in Figure 17.
(Defined by Mode 0 or Mode 1 Selection)
FIGURE 16. MODE 2 STATUS WORD FORMAT
Current Drive Capability
Any output on Port A, B or C can sink or source 2.5mA. This
feature allows the 82C55A to directly drive Darlington type
drivers and high-voltage displays that require such sink or
source current.
13
82C55A
Reading Port C Status (Figures 15 and 16)
Applications of the 82C55A
In Mode 0, Port C transfers data to or from the peripheral
device. When the 82C55A is programmed to function in
Modes 1 or 2, Port C generates or accepts “hand shaking”
signals with the peripheral device. Reading the contents of
Port C allows the programmer to test or verify the “status” of
each peripheral device and change the program flow
accordingly.
The 82C55A is a very powerful tool for interfacing peripheral
equipment to the microcomputer system. It represents the
optimum use of available pins and flexible enough to inter-
face almost any I/O device without the need for additional
external logic.
Each peripheral device in a microcomputer system usually
has a “service routine” associated with it. The routine
manages the software interface between the device and the
CPU. The functional definition of the 82C55A is programmed
by the I/O service routine and becomes an extension of the
system software. By examining the I/O devices interface
characteristics for both data transfer and timing, and
matching this information to the examples and tables in the
detailed operational description, a control word can easily be
developed to initialize the 82C55A to exactly “fit” the
application. Figures 18 through 24 present a few examples
of typical applications of the 82C55A.
There is not special instruction to read the status information
from Port C. A normal read operation of Port C is executed to
perform this function.
INTERRUPT
ENABLE FLAG
ALTERNATE PORT C
PIN SIGNAL (MODE)
POSITION
INTE B
INTE A2
INTE A1
PC2
ACKB (Output Mode 1)
or STBB (Input Mode 1)
PC4
PC6
STBA (Input Mode 1 or
Mode 2)
ACKA (Output Mode 1 or
Mode 2)
FIGURE 17. INTERRUPT ENABLE FLAGS IN MODES 1 AND 2
INTERRUPT
REQUEST
PC3 PA0
PA1
HIGH SPEED
PRINTER
PA2
PA3
PA4
PA5
PA6
PA7
MODE 1
(OUTPUT)
HAMMER
RELAYS
PC7
PC6
PC5
DATA READY
ACK
PAPER FEED
FORWARD/REV.
PC4
82C55A
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PAPER FEED
FORWARD/REV.
RIBBON
MODE 1
(OUTPUT)
CARRIAGE SEN.
PC1
PC2
DATA READY
ACK
PC0
INTERRUPT
REQUEST
CONTROL LOGIC
AND DRIVERS
FIGURE 18. PRINTER INTERFACE
14
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