Cypress enCoRe CY7C604XX User Manual

CY7C604XX  
enCoRe™ V Low Voltage Microcontroller  
Features  
Powerful Harvard Architecture Processor  
Programmable Pin Configurations  
M8C processor speeds running up to 24 MHz  
Low power at high processing speeds  
Interrupt controller  
25 mA sink current on all GPIO  
Pull Up, High Z, Open Drain, CMOS drive modes on all GPIO  
Configurable inputs on all GPIO  
1.71V to 3.6V operating voltage  
Temperature range: 0°C to 70°C  
Low dropout voltage regulator for Port 1 pins. Programmable  
to output 3.0, 2.5, or 1.8V at the I/O pins  
Selectable, regulated digital I/O on Port 1  
• Configurable input threshold for Port 1  
• 3.0V, 20 mA total Port 1 source current  
• Hot-swappable  
Flexible On-Chip Memory  
Up to 32K Flash program storage  
• 50,000 Erase and write cycles  
• Flexible protection modes  
Up to 2048 bytes SRAM data storage  
In-System Serial Programming (ISSP)  
5 mA strong drive mode on Ports 0 and 1  
Additional System Resources  
Configurable communication speeds  
I C Slave  
• Selectable to 50 kHz, 100 kHz, or 400 kHz  
• Implementation requires no clock stretching  
• Implementation during sleep modes with less than 100 mA  
• Hardware address detection  
SPI master and SPI slave  
• Configurable between 93.75 kHz and 12 MHz  
Three 16-bit timers  
Complete Development Tools  
Free development tool (PSoC Designer™)  
Full featured, in-circuit emulator and programmer  
Full speed emulation  
Complex breakpoint structure  
128K trace memory  
2
Precision, Programmable Clocking  
Crystal-less oscillator with support for an external crystal or  
resonator  
8-bit ADC used to monitor battery voltage or other signals -  
with external components  
Watchdog and sleep timers  
Integrated supervisory circuit  
Internal ±5.0% 6, 12, or 24 MHz main oscillator  
Internal low speed oscillator at 32 kHz for watchdog and  
sleep.The frequency range is 19 to 50 kHz with a 32 kHz  
typical value  
enCoRe V LV Block Diagram  
Port 4 Port 3 Port 2 Port 1 Port 0 Prog. LDO  
enCoRe V  
Low Voltage  
CORE  
System Bus  
SRAM  
2048 Bytes  
SROM  
Flash 32K  
CPU Core  
(M8C)  
Sleep and  
Watchdog  
Interrupt  
Controller  
6/12/24 MHz Internal Main Oscillator  
POR and LVD  
System Resets  
I2C Slave/SPI  
Master-Slave  
3 16-Bit  
Timers  
SYSTEM RESOURCES  
Cypress Semiconductor Corporation  
Document Number: 001-12395 Rev *H  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 30, 2009  
 
CY7C604XX  
Development Tools  
PSoC Designer is a Microsoft® Windows-based, integrated  
Assemblers. The assemblers allow assembly code to be  
merged seamlessly with C code. Link libraries automatically use  
absolute addressing or are compiled in relative mode, and linked  
with other software modules to get absolute addressing.  
development  
environment  
for  
the  
Programmable  
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs  
on Windows XP or Windows Vista.  
This system provides design database management by project,  
an integrated debugger with In-Circuit Emulator, in-system  
programming support, and built-in support for third-party assem-  
blers and C compilers.  
C Language Compilers. C language compilers are available  
that support the enCoRe and PSoC families of devices. The  
products allow you to create complete C programs for the PSoC  
family devices.  
PSoC Designer also supports C language compilers developed  
specifically for the devices in the enCoRe and PSoC families.  
The optimizing C compilers provide all the features of C tailored  
to the PSoC architecture. They come complete with embedded  
libraries providing port and bus operations, standard keypad and  
display support, and extended math functionality.  
PSoC Designer Software Subsystems  
Chip-Level View  
Debugger  
The chip-level view is a traditional integrated development  
environment (IDE) based on PSoC Designer 4.4. Choose a base  
device to work with and then select different onboard analog and  
digital components called user modules that use the PSoC  
blocks. Examples of user modules are ADCs, DACs, Amplifiers,  
and Filters. Configure the user modules for the chosen appli-  
cation and connect them to each other and to the proper pins.  
Then generate your project. This prepopulates your project with  
APIs and libraries that you can use to program your application.  
PSoC Designer has a debug environment that provides  
hardware in-circuit emulation, allowing you to test the program in  
a physical system while providing an internal view of the PSoC  
device. Debugger commands allow the designer to read and  
program flash, read and write data memory, read and write I/O  
registers, read and write CPU registers, set and clear break-  
points, and provide program run, halt, and step control. The  
debugger also allows the designer to create a trace buffer of  
registers and memory locations of interest.  
The tool also supports easy development of multiple configura-  
tions and dynamic reconfiguration. Dynamic reconfiguration  
enables changing configurations at run time.  
Online Help System  
The online help system displays online, context-sensitive help  
for the user. Designed for procedural help and quick reference,  
each functional subsystem has its own context-sensitive help.  
This system also provides tutorials and links to FAQs and an  
Online Support Forum to aid the designer in getting started.  
System-Level View  
The system-level view is a drag-and-drop visual embedded  
system design environment based on PSoC Designer.  
Hybrid Designs  
In-Circuit Emulator  
You can begin in the system-level view, allow it to choose and  
configure your user modules, routing, and generate code, then  
switch to the chip-level view to gain complete control over  
on-chip resources. All views of the project share common code  
editor, builder, and common debug, emulation, and programming  
tools.  
A low cost, high functionality ICE (In-Circuit Emulator) is  
available for development support. This hardware has the  
capability to program single devices.  
The emulator consists of a base unit that connects to the PC by  
way of a USB port. The base unit is universal and operates with  
all enCoRe and PSoC devices. Emulation pods for each device  
family are available separately. The emulation pod takes the  
place of the PSoC device in the target board and performs full  
speed (24 MHz) operation.  
Code Generation Tools  
PSoC Designer supports multiple third-party C compilers and  
assemblers. The code generation tools work seamlessly within  
the PSoC Designer interface and have been tested with a full  
range of debugging tools. The choice is yours.  
Document Number: 001-12395 Rev *H  
Page 3 of 30  
CY7C604XX  
Designing with PSoC Designer  
The development process for the enCoRe V device differs from  
that of a traditional fixed function microprocessor. Powerful  
PSoC Designer tools get the core of your design up and running  
in minutes instead of hours.  
valuator functions. In the chip-level view, you perform the  
selection, configuration, and routing so that you have complete  
control over the use of all on-chip resources.  
Generate, Verify, and Debug  
The development process can be summarized in the following  
four steps:  
When you are ready to test the hardware configuration or move  
on to developing code for the project, you perform the “Generate  
Configuration Files” step. This causes PSoC Designer to  
generate source code that automatically configures the device to  
your specification and provides the software for the system.  
1. Select Components  
2. Configure Components  
3. Organize and Connect  
4. Generate, Verify, and Debug  
Both system-level and chip-level designs generate software  
based on your design. The chip-level design provides application  
programming interfaces (APIs) with high-level functions to  
control and respond to hardware events at run time and interrupt  
service routines that you can adapt as needed. The system-level  
design also generates a C main() program that completely  
controls the chosen application and contains placeholders for  
custom code at strategic positions allowing you to further refine  
the software without disrupting the generated code.  
Select Components  
The chip-level views provide a library of pre-built, pre-tested  
hardware peripheral components. These components are called  
“user modules.” User modules make selecting and implementing  
peripheral devices simple, and come in analog, digital, and  
mixed-signal varieties.  
Configure Components  
A complete code development environment allows you to  
develop and customize your applications in C, assembly  
language, or both.  
Each of the components you select establishes the basic register  
settings that implement the selected function. They also provide  
parameters and properties that allow you to tailor their precise  
configuration to your particular application.  
The last step in the development process takes place inside  
PSoC Designer’s Debugger (access by clicking the Connect  
icon). PSoC Designer downloads the HEX image to the In-Circuit  
Emulator (ICE) where it runs at full speed. PSoC Designer  
debugging capabilities rival those of systems costing many times  
more. In addition to traditional single-step, run-to-breakpoint and  
watch-variable features, the debug interface provides a large  
trace buffer and allows you to define complex breakpoint events  
that include monitoring address and data bus values, memory  
locations and external signals.  
The chip-level user modules are documented in data sheets that  
are viewed directly in PSoC Designer. These data sheets explain  
the internal operation of the component and provide perfor-  
mance specifications. Each data sheet describes the use of each  
user module parameter and contains other information you may  
need to successfully implement your design.  
Organize and Connect  
You build signal chains at the chip level by interconnecting user  
modules to each other and the I/O pins, or connect system-level  
inputs, outputs, and communication interfaces to each other with  
Document Number: 001-12395 Rev *H  
Page 4 of 30  
CY7C604XX  
Document Conventions  
Acronyms Used  
Units of Measure  
The following table lists the acronyms that are used in this  
document.  
A units of measure table is located in the Electrical Specifications  
section. Table 7 on page 14 lists all the abbreviations used to  
measure the enCoRe V LV devices.  
Acronym  
API  
Description  
application programming interface  
central processing unit  
general purpose IO  
Numeric Naming  
Hexadecimal numbers are represented with all letters in  
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or  
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’  
prefix, the C coding convention. Binary numbers have an  
appended lowercase ‘b’ (for example, 01010100b’ or  
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are  
decimal.  
CPU  
GPIO  
ICE  
in-circuit emulator  
ILO  
internal low speed oscillator  
internal main oscillator  
input/output  
IMO  
IO  
LSb  
least significant bit  
LVD  
low voltage detect  
MSb  
POR  
PPOR  
PSoC®  
SLIMO  
SRAM  
most significant bit  
power on reset  
precision power on reset  
Programmable System-on-Chip™  
slow IMO  
static random access memory  
Document Number: 001-12395 Rev *H  
Page 5 of 30  
CY7C604XX  
Pin Configuration  
16-Pin Part Pinout  
Figure 1. CY7C60413 16-Pin enCoRe V LV Device  
Table 1. 16-Pin Part Pinout (QFN)  
Pin No.  
Type  
I/O  
Name  
Description  
Digital I/O, Crystal Out (Xout)  
1
2
P2[5]  
P2[3]  
P1[7]  
P1[5]  
P1[3]  
P1[1]  
Vss  
I/O  
Digital I/O, Crystal In (Xin)  
Digital I/O, I2C SCL, SPI SS  
Digital I/O, I2C SDA, SPI MISO  
Digital I/O, SPI CLK  
3
IOHR  
IOHR  
IOHR  
IOHR  
Power  
IOHR  
IOHR  
IOHR  
Input  
IOHR  
Power  
IOHR  
IOHR  
IOHR  
4
5
6
Digital I/O, ISSP CLK, I2C SCL, SPI MOSI  
Ground Pin  
7
8
P1[0]  
P1[2]  
P1[4]  
XRES  
P0[4]  
Vdd  
Digital I/O, ISSP DATA, I2C SDA, SPI CLK  
Digital I/O  
9
10  
11  
12  
13  
14  
15  
16  
Digital I/O, optional external clock input (EXTCLK)  
Active high external reset with internal pull down  
Digital I/O  
Power Pin  
P0[7]  
P0[3]  
P0[1]  
Digital I/O  
Digital I/O  
Digital I/O  
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.  
Document Number: 001-12395 Rev *H  
Page 6 of 30  
CY7C604XX  
32-Pin Part Pinout  
Figure 2. CY7C60445 32-Pin enCoRe V LV Device  
P0[1]  
P2[7]  
1
2
24  
23  
P0[0]  
P2[6]  
P2[5]  
P2[3]  
P2[1]  
P3[3]  
3
4
5
6
7
8
22  
21  
20  
P2[4]  
P2[2]  
P2[0]  
P3[2]  
QFN  
(Top View)  
19  
18  
17  
P3[1]  
P1[7]  
P3[0]  
XRES  
Table 2. 32-Pin Part Pinout (QFN)  
Pin No.  
Type  
IOH  
Name  
P0[1]  
Description  
1
2
Digital I/O  
Digital I/O  
I/O  
P2[7]  
P2[5]  
P2[3]  
P2[1]  
P3[3]  
P3[1]  
P1[7]  
P1[5]  
P1[3]  
P1[1]  
Vss  
3
I/O  
Digital I/O, Crystal Out (Xout)  
Digital I/O, Crystal In (Xin)  
Digital I/O  
4
I/O  
5
I/O  
6
I/O  
Digital I/O  
7
I/O  
Digital I/O  
8
IOHR  
IOHR  
IOHR  
IOHR  
Power  
IOHR  
IOHR  
IOHR  
IOHR  
Digital I/O, I2C SCL, SPI SS  
Digital I/O, I2C SDA, SPI MISO  
Digital I/O, SPI CLK  
9
10  
11  
12  
13  
14  
15  
16  
Digital I/O, ISSP CLK, I2C SCL, SPI MOSI  
Ground connection  
P1[0]  
P1[2]  
P1[4]  
P1[6]  
Digital I/O, ISSP DATA, I2C SDA, SPI CLK  
Digital I/O  
Digital I/O, optional external clock input (EXTCLK)  
Digital I/O  
Notes  
1. During power up or reset event, device P1[0] and P1[1] may disturb the I2C bus. Use alternate pins if issues are encountered.  
2. These are the in-system serial programming (ISSP) pins, that are not High Z at power on reset (POR)  
Document Number: 001-12395 Rev *H  
Page 7 of 30  
CY7C604XX  
Table 2. 32-Pin Part Pinout (QFN) (continued)  
Pin No.  
17  
Type  
Reset Input  
I/O  
Name  
XRES  
Description  
Active high external reset with internal pull down  
18  
P3[0]  
P3[2]  
P2[0]  
P2[2]  
P2[4]  
P2[6]  
P0[0]  
P0[2]  
P0[4]  
P0[6]  
Vdd  
Digital I/O  
19  
I/O  
Digital I/O  
20  
I/O  
Digital I/O  
21  
I/O  
Digital I/O  
22  
I/O  
Digital I/O  
23  
I/O  
Digital I/O  
24  
IOH  
Digital I/O  
25  
IOH  
Digital I/O  
26  
IOH  
Digital I/O  
27  
IOH  
Digital I/O  
28  
Power  
IOH  
Supply voltage  
Digital I/O  
29  
P0[7]  
P0[5]  
P0[3]  
Vss  
30  
IOH  
Digital I/O  
31  
IOH  
Digital I/O  
32  
Power  
Power  
Ground connection  
Center pad must be connected to ground  
CP  
Vss  
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.  
Notes  
3. During power up or reset event, device P1[0] and P1[1] may disturb the I2C bus. Use alternate pins if issues are encountered.  
4. These are the in-system serial programming (ISSP) pins, that are not High Z at power on reset (POR)  
Document Number: 001-12395 Rev *H  
Page 8 of 30  
   
CY7C604XX  
48-Pin Part Pinout  
Figure 3. CY7C60455/CY7C60456 48-Pin enCoRe V LV Device  
P2[6]  
P2[4]  
P2[2]  
P2[0]  
P4[2]  
P4[0]  
P3[6]  
36  
35  
34  
33  
32  
31  
30  
NC  
P2[7]  
P2[5]  
1
2
3
4
P2[3]  
P2[1]  
P4[3]  
5
6
QFN  
(Top View)  
P4[1]  
P3[7]  
P3[5]  
P3[3]  
7
P3[4]  
P3[2]  
P3[0]  
XRES  
29  
28  
27  
8
9
10  
P3[1]  
P1[7]  
26  
25  
11  
12  
P1[6]  
Table 3. 48-Pin Part Pinout (QFN)  
Pin No.  
Type  
NC  
Name  
Description  
1
2
NC  
No connection  
Digital I/O  
I/O  
P2[7]  
P2[5]  
P2[3]  
P2[1]  
P4[3]  
P4[1]  
P3[7]  
P3[5]  
P3[3]  
P3[1]  
P1[7]  
P1[5]  
NC  
3
I/O  
Digital I/O, Crystal Out (Xout)  
Digital I/O, Crystal In (Xin)  
Digital I/O  
4
I/O  
5
I/O  
6
I/O  
Digital I/O  
7
I/O  
Digital I/O  
8
I/O  
Digital I/O  
9
I/O  
Digital I/O  
10  
11  
12  
13  
14  
15  
16  
17  
I/O  
Digital I/O  
I/O  
Digital I/O  
IOHR  
IOHR  
NC  
Digital I/O, I2C SCL, SPI SS  
Digital I/O, I2C SDA, SPI MISO  
No connection  
NC  
NC  
No connection  
IOHR  
IOHR  
P1[3]  
P1[1]  
Digital I/O, SPI CLK  
Digital I/O, ISSP CLK, I2C SCL, SPI MOSI  
Document Number: 001-12395 Rev *H  
Page 9 of 30  
CY7C604XX  
Table 3. 48-Pin Part Pinout (QFN) (continued)  
Pin No.  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
CP  
Type  
Power  
NC  
Name  
Description  
Vss  
NC  
NC  
Supply ground  
No connection  
No connection  
Supply voltage  
NC  
Power  
IOHR  
IOHR  
IOHR  
IOHR  
XRES  
I/O  
Vdd  
P1[0]  
P1[2]  
P1[4]  
P1[6]  
Digital I/O, ISSP DATA, I2C SDA, SPI CLK  
Digital I/O  
Digital I/O, optional external clock input (EXTCLK)  
Digital I/O  
Ext Reset  
P3[0]  
P3[2]  
P3[4]  
P3[6]  
P4[0]  
P4[2]  
P2[0]  
P2[2]  
P2[4]  
P2[6]  
P0[0]  
P0[2]  
P0[4]  
P0[6]  
Vdd  
Active high external reset with internal pull down  
Digital I/O  
I/O  
Digital I/O  
I/O  
Digital I/O  
I/O  
Digital I/O  
I/O  
Digital I/O  
I/O  
Digital I/O  
I/O  
Digital I/O  
I/O  
Digital I/O  
I/O  
Digital I/O  
I/O  
Digital I/O  
IOH  
IOH  
IOH  
IOH  
Power  
NC  
Digital I/O  
Digital I/O  
Digital I/O  
Digital I/O  
Supply voltage  
No connection  
No connection  
Digital I/O  
NC  
NC  
NC  
IOH  
IOH  
IOH  
Power  
IOH  
Power  
P0[7]  
P0[5]  
P0[3]  
Vss  
Digital I/O  
Digital I/O  
Supply ground  
Digital I/O  
P0[1]  
Vss  
Center pad must be connected to ground  
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output  
Document Number: 001-12395 Rev *H  
Page 10 of 30  
CY7C604XX  
Register Reference  
The section discusses the registers of the enCoRe V LV device. It lists all the registers in mapping tables, in address order.  
Register Conventions  
Register Mapping Tables  
The register conventions specific to this section are listed in the  
following table.  
The enCoRe V LV device has a total register address space of  
512 bytes. The register space is also referred to as IO space and  
is broken into two parts: Bank 0 (user space) and Bank 1 (config-  
uration space). The XIO bit in the Flag register (CPU_F) deter-  
mines which bank the user is currently in. When the XIO bit is  
set, the user is said to be in the “extended” address space or the  
“configuration” registers.  
Table 4. Register Conventions  
Convention  
Description  
Read register or bits  
R
W
L
Write register or bits  
Logical register or bits  
Clearable register or bits  
Access is bit specific  
C
#
Document Number: 001-12395 Rev *H  
Page 11 of 30  
CY7C604XX  
Table 5. Register Map Bank 0 Table: User Space  
Name  
Addr (0,Hex) Access  
Name  
Addr (0,Hex) Access  
Name  
Addr (0,Hex) Access  
Name  
Addr (0,Hex) Access  
PRT0DR  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
0E  
0F  
10  
11  
RW  
RW  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
4A  
4B  
4C  
4D  
4E  
4F  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
5A  
5B  
5C  
5D  
5E  
5F  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
6A  
6B  
6C  
6D  
6E  
6F  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
7A  
7B  
7C  
7D  
7E  
7F  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
8A  
8B  
8C  
8D  
8E  
8F  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
9A  
9B  
9C  
9D  
9E  
9F  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
AA  
AB  
AC  
AD  
AE  
AF  
C0  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
PRT0IE  
PRT1DR  
PRT1IE  
RW  
RW  
PRT2DR  
PRT2IE  
RW  
RW  
I2C_XCFG  
I2C_XSTAT  
I2C_ADDR  
I2C_BP  
C8  
C9  
CA  
CB  
CC  
CD  
CE  
CF  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
DA  
DB  
DC  
DD  
DE  
DF  
E0  
E1  
E2  
E3  
E4  
E5  
E6  
E7  
E8  
E9  
EA  
EB  
EC  
ED  
EE  
EF  
F0  
F1  
F2  
F3  
F4  
F5  
F6  
F7  
F8  
F9  
FA  
FB  
FC  
FD  
FE  
FF  
RW  
R
RW  
R
PRT3DR  
PRT3IE  
RW  
RW  
I2C_CP  
R
CPU_BP  
CPU_CP  
I2C_BUF  
CUR_PP  
STK_PP  
RW  
R
RW  
RW  
RW  
PRT4DR  
PRT4IE  
RW  
RW  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
2A  
2B  
2C  
2D  
2E  
2F  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
3A  
3B  
3C  
3D  
3E  
3F  
IDX_PP  
RW  
RW  
RW  
RW  
#
MVR_PP  
MVW_PP  
I2C_CFG  
I2C_SCR  
I2C_DR  
RW  
INT_CLR0  
INT_CLR1  
INT_CLR2  
INT_CLR3  
INT_MSK2  
INT_MSK1  
INT_MSK0  
INT_SW_EN  
INT_VC  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RC  
W
RES_WDT  
INT_MSK3  
RW  
SPI_TXR  
SPI_RXR  
SPI_CR  
W
R
#
PT0_CFG  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
BA  
BB  
BC  
BD  
BE  
BF  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
PT0_DATA1  
PT0_DATA0  
PT1_CFG  
PT1_DATA1  
PT1_DATA0  
PT2_CFG  
PT2_DATA1  
PT2_DATA0  
CPU_F  
RL  
CPU_SCR1  
CPU_SCR0  
#
#
Gray fields are reserved and should not be accessed.  
# Access is bit specific.  
Document Number: 001-12395 Rev *H  
Page 12 of 30  
CY7C604XX  
Table 6. Register Map Bank 1 Table: Configuration Space  
Name  
Addr (1,Hex) Access  
Name  
Addr (1,Hex) Access  
Name  
Addr (1,Hex) Access  
Name  
Addr (1,Hex) Access  
PRT0DM0  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
0E  
0F  
10  
11  
RW  
40  
80  
C0  
PRT0DM1  
RW  
41  
42  
43  
44  
45  
46  
47  
48  
49  
4A  
4B  
4C  
4D  
4E  
4F  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
5A  
5B  
5C  
5D  
5E  
5F  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
6A  
6B  
81  
82  
83  
84  
85  
86  
87  
88  
89  
8A  
8B  
8C  
8D  
8E  
8F  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
9A  
9B  
9C  
9D  
9E  
9F  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
AA  
AB  
AC  
AD  
AE  
AF  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
B9  
BA  
BB  
BC  
BD  
BE  
BF  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
CA  
CB  
CC  
CD  
CE  
CF  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
DA  
DB  
PRT1DM0  
PRT1DM1  
RW  
RW  
PRT2DM0  
PRT2DM1  
RW  
RW  
PRT3DM0  
PRT3DM1  
RW  
RW  
PRT4DM0  
PRT4DM1  
RW  
RW  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
2A  
2B  
2C  
2D  
2E  
2F  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
3A  
3B  
3C  
3D  
3E  
3F  
IO_CFG  
DC  
DD  
DE  
DF  
E0  
E1  
E2  
E3  
E4  
E5  
E6  
E7  
E8  
E9  
EA  
EB  
EC  
ED  
EE  
EF  
F0  
F1  
F2  
F3  
F4  
F5  
F6  
F7  
F8  
F9  
FA  
FB  
FC  
FD  
FE  
FF  
RW  
RW  
OUT_P1  
OSC_CR0  
ECO_CFG  
OSC_CR2  
VLT_CR  
RW  
#
RW  
RW  
R
VLT_CMP  
IMO_TR  
ILO_TR  
W
W
SPI_CFG  
RW  
SLP_CFG  
SLP_CFG2  
SLP_CFG3  
RW  
RW  
RW  
TMP_DR0  
TMP_DR1  
TMP_DR2  
TMP_DR3  
6C  
RW  
RW  
RW  
RW  
6D  
6E  
6F  
70  
71  
72  
73  
74  
75  
76  
77  
CPU_F  
RL  
78  
79  
7A  
7B  
7C  
7D  
7E  
7F  
Gray fields are reserved and should not be accessed.  
# Access is bit specific.  
Document Number: 001-12395 Rev *H  
Page 13 of 30  
CY7C604XX  
Electrical Specifications  
This section presents the DC and AC electrical specifications of the enCoRe V LV devices. For the most up to date electrical  
specifications, verify that you have the most recent data sheet available by visiting the company web site at http://www.cypress.com.  
Figure 4. Voltage versus CPU Frequency  
Figure 5. IMO Frequency Trim Options  
3.6V  
3.6V  
SLIMO SLIMO  
SLIMO  
Mode  
Mode  
= 00  
Mode  
= 01  
= 10  
1.71V  
1.71V  
750 kHz  
3 MHz  
CPU Frequency  
24 MHz  
750 kHz  
3 MHz  
6 MHz 12 MHz 24 MHz  
IMO Frequency  
The following table lists the units of measure that are used in this chapter.  
Table 7. Units of Measure  
Symbol  
Unit of Measure  
Symbol  
μW  
mA  
ms  
mV  
nA  
Unit of Measure  
o
C
degree Celsius  
decibels  
microwatts  
dB  
fF  
milli-ampere  
milli-second  
milli-volts  
femto farad  
hertz  
Hz  
KB  
1024 bytes  
1024 bits  
nanoampere  
nanosecond  
nanovolts  
Kbit  
kHz  
kΩ  
ns  
kilohertz  
nV  
kilohm  
Ω
ohm  
MHz  
MΩ  
μA  
μF  
μH  
μs  
μV  
μVrms  
megahertz  
megaohm  
microampere  
microfarad  
microhenry  
microsecond  
microvolts  
pA  
picoampere  
picofarad  
pF  
pp  
peak-to-peak  
ppm  
ps  
parts per million  
picosecond  
sps  
s
samples per second  
sigma: one standard deviation  
volts  
microvolts root-mean-square  
V
Document Number: 001-12395 Rev *H  
Page 14 of 30  
 
CY7C604XX  
ADC Electrical Specifications  
Table 8. ADC Electrical Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
Conditions  
This gives 72% of maximum code  
Input  
Input Voltage Range  
Input Capacitance  
Vss  
1.3  
5
V
pF  
Resolution  
8-Bit Sample Rate  
8
Bits  
23.4375  
ksps Data Clock set to 6 MHz. Sample Rate  
= 0.001/(2^Resolution/Data clock)  
DC Accuracy  
DNL  
-1  
-2  
0
+2  
+2  
LSb For any configuration  
INL  
LSb For any configuration  
Offset Error  
15  
90  
mV  
Operating Current  
Data Clock  
275  
350  
12  
μA  
2.25  
MHz Source is chip’s internal main oscillator.  
See AC Chip Level Specifications for  
accuracy.  
Monotonicity  
Not guaranteed. See DNL  
Power Supply Rejection Ratio  
PSRR (Vdd>3.0V)  
PSRR (2.2 < Vdd < 3.0)  
PSRR (2.0 < Vdd < 2.2)  
PSRR (Vdd < 2.0)  
Gain Error  
24  
30  
12  
0
dB  
dB  
dB  
dB  
1
5
%FSR For any resolution  
Input Resistance  
1/(500fF*D 1/(400fF*D 1/(300fF*D  
ata-Clock) ata-Clock) ata-Clock)  
Ω
Equivalent switched cap input resis-  
tance for 8-, 9-, or 10-bit resolution.  
Document Number: 001-12395 Rev *H  
Page 15 of 30  
CY7C604XX  
(6)  
Electro Static Discharge Voltage (ESD) .................. 2000V  
Maximum Ratings  
(7)  
Latch-up Current (LU) ........................................... 200 mA  
(5)  
o
o
o
Storage Temperature (T  
)
-55 C to 125 C (Typical +25 C)  
STG  
Operating Conditions  
Supply Voltage Relative to Vss (Vdd)............. -0.5V to +4.0V  
DC Input Voltage (V )....................Vss - 0.5V to Vdd + 0.5V  
o
o
IO  
Ambient Temperature (T ).................................. 0 C to 70 C  
A
DC Voltage Applied to Tri-state (V )Vss - 0.5V to Vdd + 0.5V  
o
o
IOZ  
Operational Die Temperature (T ) ................... 0 C to 85 C  
J
Maximum Current into any Port Pin (I  
). -25mA to +50 mA  
MIO  
DC Electrical Characteristics  
DC Chip Level Specifications  
Table 9 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.  
Table 9. DC Chip Level Specifications  
Parameter  
Description  
Supply Voltage  
Conditions  
Min  
Typ  
Max  
Units  
Vdd  
See table titled DC POR and LVD  
1.71  
3.6  
V
o
I
I
I
Supply Current, IMO = 24 MHz  
Supply Current, IMO = 12 MHz  
Supply Current, IMO = 6 MHz  
Deep Sleep Current  
Conditions are Vdd = 3.0V, T = 25 C,  
CPU = 24 MHz  
No I2C/SPI  
3.1  
2.0  
1.5  
mA  
mA  
mA  
DD24  
DD12  
DD6  
A
o
Conditions are Vdd = 3.0V, T = 25 C,  
A
CPU = 12 MHz  
No I2C/SPI  
o
Conditions are Vdd = 3.0V, T = 25 C,  
A
CPU = 6 MHz  
No I2C/SPI  
o
I
I
Vdd = 3.0V, T = 25 C, IO regulator  
0.1  
μA  
SB0  
A
turned off  
o
Standby Current with POR, LVD, and  
Sleep Timer  
Vdd = 3.0V, T = 25 C, IO regulator  
1.5  
μA  
SB1  
A
turned off  
Notes  
5. Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Extended duration storage temperatures above 85°C  
degrade reliability.  
6. Human Body Model ESD.  
7. According to JESD78 standard.  
8. The temperature rise from ambient to junction is package specific. See on page 27. The user must limit the power consumption to comply with this requirement.  
Document Number: 001-12395 Rev *H  
Page 16 of 30  
         
CY7C604XX  
DC General Purpose I/O Specifications  
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 1.71V to 3.6V and  
0°C T 70°C. Typical parameters apply to 3.3V at 25°C. These are for design guidance only.  
A
Table 10. 3.0V to 3.6V DC GPIO Specifications  
Symbol  
Description  
Pull Up Resistor  
Conditions  
Min  
Typ  
5.6  
Max  
8
Units  
kΩ  
R
4
PU  
V
High Output Voltage  
Port 2 or 3 Pins  
IOH < 10 μA, maximum of 10 mA source Vdd - 0.2  
current in all I/Os  
V
OH1  
V
V
High Output Voltage  
Port 2 or 3 Pins  
IOH = 1 mA, maximum of 20 mA source Vdd - 0.9  
current in all I/Os  
V
V
OH2  
OH3  
High Output Voltage  
Port 0 or 1 Pins with LDO Regulator current in all I/Os  
Disabled for Port 1  
IOH < 10 μA, maximum of 10 mA source Vdd - 0.2  
V
V
V
V
V
V
V
V
High Output Voltage  
Port 0 or 1 Pins with LDO Regulator current in all I/Os  
Disabled for Port 1  
IOH = 5 mA, maximum of 20 mA source Vdd - 0.9  
3.00  
3.3  
V
V
V
V
V
V
V
V
OH4  
OH5  
OH6  
OH7  
OH8  
OH9  
OH10  
OL  
High Output Voltage  
Port 1 Pins with LDO Regulator  
Enabled for 3V Out  
IOH < 10 μA, Vdd > 3.1V, maximum of 4  
2.85  
2.20  
2.35  
1.90  
1.60  
1.20  
I/Os all sourcing 5 mA  
High Output Voltage  
Port 1 Pins with LDO Regulator  
Enabled for 3V Out  
IOH = 5 mA, Vdd > 3.1V, maximum of 20  
mA source current in all I/Os  
High Output Voltage  
Port 1 Pins with LDO Enabled for 2.5V mA source current in all I/Os  
Out  
IOH < 10 μA, Vdd > 2.7V, maximum of 20  
2.50  
2.75  
High Output Voltage  
Port 1 Pins with LDO Enabled for 2.5V mA source current in all I/Os  
Out  
IOH = 2 mA, Vdd > 2.7V, maximum of 20  
High Output Voltage  
Port 1 Pins with LDO Enabled for 1.8V mA source current in all I/Os  
Out  
IOH < 10 μA, Vdd > 2.7V, maximum of 20  
1.80  
2.1  
High Output Voltage  
Port 1 Pins with LDO Enabled for 1.8V mA source current in all I/Os  
Out  
IOH = 1 mA, Vdd > 2.7V, maximum of 20  
Low Output Voltage  
IOL = 25 mA, Vdd > 3.3V, maximum of 60  
0.75  
mA sink current on even port pins (for  
example, P0[2] and P1[4]) and 60 mA sink  
current on odd port pins (for example,  
P0[3] and P1[5])  
V
V
V
Input Low Voltage  
2.00  
0.80  
V
V
IL  
IH  
H
Input High Voltage  
Input Hysteresis Voltage  
Input Leakage (Absolute Value)  
Pin Capacitance  
80  
1
5
mV  
µA  
pF  
I
0.001  
1.7  
IL  
C
Package and pin dependent  
Temp = 25 C  
0.5  
PIN  
o
Document Number: 001-12395 Rev *H  
Page 17 of 30  
   
CY7C604XX  
Table 11. 2.4V to 3.0V DC GPIO Specifications  
Symbol Description  
Pull Up Resistor  
Conditions  
Min  
Typ  
5.6  
Max  
8
Units  
kΩ  
V
R
4
PU  
V
V
V
High Output Voltage  
Port 2 or 3 Pins  
IOH < 10 μA, maximum of 10 mA source Vdd - 0.2  
current in all I/Os  
OH1  
High Output Voltage  
Port 2 or 3 Pins  
IOH = 0.2 mA, maximum of 10 mA source Vdd - 0.4  
current in all I/Os  
V
V
OH2  
OH3  
High Output Voltage  
Port 0 or 1 Pins with LDO Regulator  
Disabled for Port 1  
IOH < 10 μA, maximum of 10 mA source Vdd - 0.2  
current in all I/Os  
V
V
V
V
High Output Voltage  
Port 0 or 1 Pins with LDO Regulator  
Disabled for Port 1  
IOH = 2 mA, maximum of 10 mA source Vdd - 0.5  
current in all I/Os  
1.80  
V
V
V
V
OH4  
OH5A  
OH6A  
OL  
High Output Voltage  
Port 1 Pins with LDO Enabled for 1.8V mA source current in all I/Os.  
Out  
IOH < 10 μA, Vdd > 2.4V, maximum of 20  
1.50  
1.20  
2.10  
High Output Voltage  
Port 1 Pins with LDO Enabled for 1.8V mA source current in all I/Os  
Out  
IOH = 1 mA, Vdd > 2.4V, maximum of 20  
Low Output Voltage  
IOL = 10 mA, maximum of 30 mA sink  
0.75  
current on even port pins (for example,  
P0[2] and P1[4]) and 30 mA sink current  
on odd port pins (for example, P0[3] and  
P1[5])  
V
V
V
Input Low Voltage  
1.6  
0.72  
V
V
IL  
IH  
H
Input High Voltage  
Input Hysteresis Voltage  
Input Leakage (Absolute Value)  
Capacitive Load on Pins  
80  
1
5
mV  
µA  
pF  
I
0.001  
1.7  
IL  
C
Package and pin dependent  
Temp = 25 C  
0.5  
PIN  
o
Document Number: 001-12395 Rev *H  
Page 18 of 30  
CY7C604XX  
Table 12. 1.71V to 2.4V DC GPIO Specifications  
Symbol  
Description  
Pull Up Resistor  
Conditions  
Min  
4
Typ  
5.6  
Max  
8
Units  
kΩ  
R
PU  
V
High Output Voltage  
Port 2 or 3 Pins  
IOH = 10 μA, maximum of 10 mA  
source current in all I/Os  
Vdd - 0.2  
V
OH1  
V
V
High Output Voltage  
Port 2 or 3 Pins  
IOH = 0.5 mA, maximum of 10 mA  
source current in all I/Os  
Vdd - 0.5  
Vdd - 0.2  
V
V
OH2  
OH3  
High Output Voltage  
Port 0 or 1 Pins with LDO Regulator  
IOH = 100 μA, maximum of 10 mA  
source current in all I/Os  
Disabled for Port 1  
V
V
High Output Voltage  
Port 0 or 1 Pins with LDO Regulator  
Disabled for Port 1  
IOH = 2 mA, maximum of 10 mA  
source current in all I/Os  
Vdd - 0.5  
V
V
OH4  
Low Output Voltage  
IOL = 5 mA, maximum of 20 mA sink  
current on even port pins (for  
0.4  
OL  
example, P0[2] and P1[4]) and 30 mA  
sink current on odd port pins (for  
example, P0[3] and P1[5])  
V
V
V
Input Low Voltage  
0.3 x Vdd  
V
V
IL  
IH  
H
Input High Voltage  
0.65 x Vdd  
Input Hysteresis Voltage  
Input Leakage (Absolute Value)  
Capacitive Load on Pins  
80  
1
5
mV  
µA  
pF  
I
0.001  
1.7  
IL  
C
Package and pin dependent.  
Temp = 25 C  
0.5  
PIN  
o
Document Number: 001-12395 Rev *H  
Page 19 of 30  
CY7C604XX  
DC POR and LVD Specifications  
Table 13 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.  
Table 13. DC POR and LVD Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
(9)  
Vdd Value for PPOR Trip  
V
V
V
V
PORLEV[1:0] = 00b, HPOR = 0  
PORLEV[1:0] = 00b, HPOR = 1  
PORLEV[1:0] = 01b, HPOR = 1  
PORLEV[1:0] = 10b, HPOR = 1  
1.61  
1.66  
2.36  
2.60  
2.82  
1.71  
2.41  
2.66  
2.95  
V
V
V
V
PPOR0  
PPOR1  
PPOR2  
PPOR3  
Vdd Value for LVD Trip  
(10)  
V
V
V
V
V
V
V
VM[2:0] = 000b  
VM[2:0] = 001b  
VM[2:0] = 010b  
2.40  
2.64  
2.85  
2.95  
3.06  
1.84  
1.75  
2.45  
2.71  
2.92  
3.02  
3.13  
1.9  
2.51  
2.78  
2.99  
3.09  
3.20  
2.32  
1.84  
V
V
V
V
LVD0  
LVD1  
LVD2  
LVD3  
LVD4  
LVD5  
LVD6  
(11)  
(12)  
VM[2:0] = 011b  
VM[2:0] = 100b  
VM[2:0] = 101b  
(13)  
VM[2:0] = 110b  
1.8  
DC Programming Specifications  
Table 14 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.  
Table 14. DC Programming Specifications  
Symbol  
Vdd  
Description  
Min  
1.71  
Typ  
Max  
Units  
V
Supply Voltage for Flash Write Operations  
Supply Current During Programming or Verify  
Input Low Voltage During Programming or Verify  
Input High Voltage During Programming or Verify  
Input Current when Applying Vilp to P1[0] or P1[1] During  
IWRITE  
DDP  
I
5
25  
mA  
V
V
V
V
IL  
ILP  
V
V
IHP  
IH  
I
0.2  
mA  
ILP  
(14)  
Programming or Verify  
I
Input Current when Applying Vihp to P1[0] or P1[1]  
During Programming or Verify  
1.5  
mA  
IHP  
V
V
Output Low Voltage During Programming or Verify  
Output High Voltage During Programming or Verify  
Vss + 0.75  
V
V
OLV  
(13)  
V
Vdd  
OHV  
OH  
Flash  
Flash  
Flash Write Endurance  
50,000  
10  
Cycles  
Years  
ENPB  
DR  
Flash Data Retention  
20  
Notes  
9. Vdd must be greater than or equal to 1.71V during startup, reset from the XRES pin, or reset from watchdog.  
10. Always greater than 50 mV above V  
11. Always greater than 50 mV above V  
12. Always greater than 50 mV above V  
13. Always greater than 50 mV above V  
14. Driving internal pull down resistor.  
for falling supply.  
for falling supply.  
for falling supply.  
voltage for falling supply.  
PPOR1  
PPOR2  
PPOR3  
PPOR0  
15. See appropriate DC General Purpose I/O Specifications table. For Vdd > 3V use V  
16. Erase/write cycles per block.  
OH4  
17. Following maximum Flash write cycles at Tamb = 55C and Tj = 70C.  
Document Number: 001-12395 Rev *H  
Page 20 of 30  
                   
CY7C604XX  
AC Electrical Characteristics  
AC Chip Level Specifications  
Table 15 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.  
Table 15. AC Chip Level Specifications  
Symbol  
Description  
Min  
24  
Typ  
Max  
Units  
MHz  
MHz  
kHz  
MHz  
MHz  
MHz  
%
(18)  
F
F
F
F
F
F
Maximum Operating Frequency  
MAX  
(19)  
Maximum Processing Frequency  
24  
CPU  
Internal Low Speed Oscillator Frequency  
Internal Main Oscillator Stability for 24 MHz ± 5%  
19  
32  
24  
12  
6.0  
50  
50  
32K1  
IMO24  
IMO12  
IMO6  
(20)  
22.8  
11.4  
5.7  
40  
25.2  
12.6  
6.3  
60  
(20)  
Internal Main Oscillator Stability for 12 MHz  
Internal Main Oscillator Stability for 6 MHz  
DC  
T
Duty Cycle of IMO  
Supply Ramp Time  
IMO  
0
μs  
RAMP  
AC General Purpose IO Specifications  
Table 16 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.  
Table 16. AC GPIO Specifications  
Symbol  
Description  
Conditions  
Min  
Typ  
Max  
Units  
F
GPIO Operating Frequency  
Normal Strong Mode, Port 0, 1  
0
6 MHz for  
1.71V<Vdd<2.4V  
MHz  
GPIO  
0
0
-
12 MHz for  
2.4V<Vdd<3.6V  
Normal Strong Mode, Port 2, 3  
3 MHz for  
1.71V<Vdd<2.4V  
MHz  
6 MHz for  
3.0V<Vdd<3.6V  
TRise23  
Rise Time, Strong Mode, Cload Vdd = 3.0 to 3.6V, 10% – 90%  
= 50 pF  
15  
80  
ns  
ns  
ns  
Ports 2 or 3  
Vdd = 2.4 to 3.0V, 10% – 90%  
15  
15  
100  
100  
TRise23L Rise Time, Strong Mode Low  
Supply, Cload = 50 pF  
Vdd = 1.71 to 3.0V, 10% – 90%  
Ports 2 or 3  
TRise01  
Rise Time, Strong Mode, Cload Vdd = 3.0 to 3.6V, 10% – 90%  
10  
50  
= 50 pF  
LDO enabled or disabled  
Ports 0 or 1  
Vdd = 2.4 to 3.0V, 10% – 90%  
LDO enabled or disabled  
10  
15  
70  
TRise01L Rise Time, Strong Mode Low  
Supply, Cload = 50 pF  
Vdd = 1.71 to 3.0V, 10% – 90%  
LDO enabled or disabled  
100  
ns  
ns  
Ports 0 or 1  
TFall  
Fall Time, Strong Mode, Cload = Vdd = 3.0 to 3.6V, 10% – 90%  
50 pF  
All Ports  
10  
10  
80  
80  
Vdd = 1.71 to 3.0V, 10% - 90%  
Notes  
18. Digital clocking functions.  
19. CPU speed.  
20. Trimmed using factory trim values.  
Document Number: 001-12395 Rev *H  
Page 21 of 30  
         
CY7C604XX  
Figure 6. GPIO Timing Diagram  
90%  
GPIO Pin  
Output  
Voltage  
10%  
TRise23  
TRise01  
TFall  
AC External Clock Specifications  
Table 17 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.  
Table 17. AC External Clock Specifications  
Symbol  
Description  
Min  
0.750  
20.6  
20.6  
150  
Typ  
Max  
Units  
MHz  
ns  
F
Frequency  
High Period  
Low Period  
25.2  
5300  
OSCEXT  
ns  
Power Up IMO to Switch  
μs  
AC Programming Specifications  
Table 18 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.  
Table 18. AC Programming Specifications  
Symbol  
Description  
Min  
1
Typ  
Max  
20  
20  
Units  
ns  
T
T
T
T
F
T
T
T
Rise Time of SCLK  
Fall Time of SCLK  
RSCLK  
FSCLK  
SSCLK  
HSCLK  
SCLK  
1
ns  
Data Set up Time to Falling Edge of SCLK  
Data Hold Time from Falling Edge of SCLK  
Frequency of SCLK  
40  
40  
0
ns  
ns  
8
MHz  
ms  
ms  
ns  
Flash Erase Time (Block)  
18  
25  
85  
ERASEB  
WRITE  
DSCLK1  
Flash Block Write Time  
Data Out Delay from Falling Edge of SCLK,  
3.0V<Vdd<3.6V  
T
Data Out Delay from Falling Edge of SCLK,  
1.71V<Vdd<3.0V  
130  
ns  
DSCLK2  
Document Number: 001-12395 Rev *H  
Page 22 of 30  
   
CY7C604XX  
Figure 7. Timing Diagram - AC Programming Cycle  
AC SPI Specifications  
Table 19 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.  
Table 19. AC SPI Specifications  
Symbol  
Description  
Min  
Typ  
Max  
Units  
(21)  
(21)  
F
F
T
Maximum Input Clock Frequency Selection, Master  
2.4V<Vdd<3.6V  
12  
SPIM  
MHz  
Maximum Input Clock Frequency Selection, Master  
1.71V<Vdd<2.4V  
-
-
6
Maximum Input Clock Frequency Selection, Slave  
2.4V<Vdd<3.6V  
12  
6
SPIS  
SS  
MHz  
ns  
Maximum Input Clock Frequency Selection, Slave  
1.71V<Vdd<2.4V  
Width of SS_ Negated Between Transmissions  
50  
Notes  
21. Output clock frequency is half of input clock rate.  
Document Number: 001-12395 Rev *H  
Page 23 of 30  
   
CY7C604XX  
2
AC I C Specifications  
Table 20 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.  
2
Table 20. AC Characteristics of the I C SDA and SCL Pins  
Standard Mode  
Fast Mode  
Symbol  
Description  
Units  
Min  
0
Max  
100  
Min  
0
Max  
400  
F
T
SCL Clock Frequency  
kHz  
SCLI2C  
Hold Time (repeated) START Condition. After this period,  
the first clock pulse is generated.  
4.0  
0.6  
μs  
HDSTAI2C  
T
T
T
T
T
T
T
T
LOW Period of the SCL Clock  
4.7  
4.0  
4.7  
0
1.3  
0.6  
0.6  
0
μs  
μs  
μs  
μs  
ns  
μs  
μs  
ns  
LOWI2C  
HIGH Period of the SCL Clock  
HIGHI2C  
SUSTAI2C  
HDDATI2C  
SUDATI2C  
SUSTOI2C  
BUFI2C  
Setup Time for a Repeated START Condition  
Data Hold Time  
Data Setup Time  
250  
4.0  
4.7  
100  
Setup Time for STOP Condition  
0.6  
1.3  
0
Bus Free Time Between a STOP and START Condition  
Pulse Width of Spikes are Suppressed by the Input Filter  
50  
SPI2C  
2
Figure 8. Definition of Timing for Fast/Standard Mode on the I C Bus  
SDA  
SCL  
TSPI2C  
T
LOWI2C  
TSUDATI2C  
THDSTAI2C  
TBUFI2C  
TSUSTOI2C  
TSUSTAI2C  
THDDATI2C  
THDSTAI2C  
THIGHI2C  
S
Sr  
P
S
Notes  
22. A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement t  
Š 250 ns must then be met. This is automatically the case  
SU;DAT  
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the  
SDA line t + t = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is released.  
rmax  
SU;DAT  
Document Number: 001-12395 Rev *H  
Page 24 of 30  
   
CY7C604XX  
Package Diagram  
This section illustrates the packaging specifications for the enCoRe V LV device, along with the thermal impedances for each package.  
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of  
the enCoRe V LV emulation tools and their dimensions, refer to the development kit.  
Packaging Dimensions  
Figure 9. 16-Pin (3 x 3 mm) QFN (001-09116)  
001-09116 *D  
Document Number: 001-12395 Rev *H  
Page 25 of 30  
CY7C604XX  
Figure 10. 32-Pin (5 x 5 x 0.55 mm) QFN (001-42168)  
001-42168 *C  
Document Number: 001-12395 Rev *H  
Page 26 of 30  
CY7C604XX  
Figure 11. 48-Pin (7 x 7 x 0.9 mm) QFN (001-13191)  
001-13191 *C  
Package Handling  
Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving  
the factory. A label on the package has details about the actual bake temperature and the minimum bake time to remove this moisture.  
The maximum bake time is the aggregate time that the parts exposed to the bake temperature. Exceeding this exposure may degrade  
device reliability.  
Table 21.Package Handling  
Parameter  
TBAKETEMP  
TBAKETIME  
Description  
Bake Temperature  
Bake Time  
Minimum  
Typical  
Maximum  
See package label  
72  
Unit  
o
125  
C
See package label  
hours  
Document Number: 001-12395 Rev *H  
Page 27 of 30  
 
CY7C604XX  
Thermal Impedances  
(23)  
Package  
Typical θ  
JA  
o
16 QFN  
32.69 C/W  
o
32 QFN  
19.51 C/W  
o
48 QFN  
17.68 C/W  
Solder Reflow Peak Temperature  
Following is the minimum solder reflow peak temperature to achieve good solderability.  
Package  
16 QFN  
32 QFN  
48 QFN  
Minimum Peak Temperature  
Maximum Peak Temperature  
o
o
240 C  
260 C  
o
o
240 C  
260 C  
o
o
240 C  
260 C  
Ordering Information  
Ordering Code  
Package Information  
16-Pin QFN (3x3 mm)  
Flash  
8K  
SRAM  
No. of GPIOs  
Target Applications  
CY7C60413-16LKXC  
1K  
1K  
1K  
13  
13  
28  
Feature-rich Wireless Mouse  
Feature-rich Wireless Mouse  
Feature-Rich Wireless Mouse  
CY7C64013-16LKXCT 16-Pin QFN (3X3 mm)  
8K  
CY7C60445-32LQXC 32-Pin QFN  
(5x5x0.55 mm)  
16K  
CY7C60445-32LQXCT 32-Pin QFN - (Tape and Reel)  
(5x5x0.55 mm)  
16K  
16K  
16K  
32K  
32K  
1K  
1K  
1K  
2K  
2K  
28  
36  
36  
36  
36  
Feature-Rich Wireless Mouse  
Mid-Tier Wireless Keyboard  
Mid-Tier Wireless Keyboard  
CY7C60455-48LTXC  
48-Pin QFN  
(7x7x0.9 mm)  
CY7C60455-48LTXCT 48-Pin QFN - (Tape and Reel)  
(7x7x0.9 mm)  
CY7C60456-48LTXC  
48-Pin QFN  
(7x7x0.9 mm)  
Feature-Rich Wireless  
Keyboard  
CY7C60456-48LTXCT 48-Pin QFN - (Tape and Reel)  
(7x7x0.9 mm)  
Feature-Rich Wireless  
Keyboard  
Notes  
23. T = T + Power x θ  
J
A
JA.  
24. To achieve the thermal impedance specified for the package, solder the center thermal pad to the PCB ground plane.  
25. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5°C with Sn-Pb or 245 ± 5°C with Sn-Ag-Cu paste.  
Refer to the solder manufacturer specifications.  
Document Number: 001-12395 Rev *H  
Page 28 of 30  
     
CY7C604XX  
Document History Page  
Document Title: CY7C604XX, enCoRe™ V Low Voltage Microcontroller  
Document Number: 001-12395  
Orig. of  
Change  
Submission  
Date  
Rev.  
ECN No.  
Description of Change  
**  
626516  
735721  
TYJ  
See ECN New data sheet  
*A  
TYJ/ARI  
See ECN Added new block diagram, replaced TBDs, corrected values, updated pinout infor-  
mation, changed part number to reflect new specifications.  
*B  
1120504  
ARI  
See ECN Corrected the description to pin 29 on Table 1, the Typ/Max values for I  
on the  
SB0  
DC chip-level specifications, and the Min voltage value for Vdd  
Programming Specifications table.  
in the DC  
IWRITE  
Corrected Flash Write Endurance minimum value in the DC Programming Speci-  
fications table.  
Corrected the Flash Erase Time max value and the Flash Block Write Time max  
value in the AC Programming Specifications table.  
Implemented new latest template.  
*C  
*D  
1225864  
1446763  
AESA/ARI  
AESA  
See ECN Corrected the description to pin 13, 29 on Table 1 and 22,44 on Table 2.  
Added sections Register Reference, Register Conventions and Register Mapping  
Tables. Corrected Max values on the DC Chip-Level Specifications table.  
See ECN Changed T  
parameter, max value to 18ms in Table 13, AC Programming  
ERASEB  
Specification.  
*E  
*F  
1639963  
2138889  
AESA  
TYJ/PYRS  
See ECN Updated Ordering Code table:  
- Ordering code changed for 32-QFN package: From -32LKXC to -32LTXC  
- Added a new package type – “LTXC” for 48-QFN  
- Included Tape and Reel ordering code for 32-QFN and 48-QFN packages  
Changed active current values at 24, 12 and 6MHz in table “DC Chip-Level Speci-  
fications”  
- IDD24: 2.15 to 3.1mA  
- IDD12: 1.45 to 2.0mA  
- IDD6: 1.1 to 1.5mA  
Added information on using P1[0] and P1[1] as the I2C interface during POR or  
reset events  
*G  
2583853 TYJ/PYRS/  
HMT  
10/10/08  
Converted from Preliminary to Final  
ADC resolution changed from 10-bit to 8-bit  
On Page1, SPI Master and Slave – speeds changed  
Rephrased battery monitoring clause in page 1 to include “with external compo-  
nents”  
Included ADC specifications table  
Voh5, Voh7, Voh9 specs changed  
Flash data retention – condition added to Note [15]  
Input leakage spec changed to 25 nA max  
Under AC Char, Frequency accuracy of ILO corrected  
GPIO rise time for ports 0,1 and ports 2,3 made common  
AC Programming specifications updated  
Included AC Programming cycle timing diagram  
AC SPI specification updated  
Spec change for 32-QFN package  
Input Leakage Current maximum value changed to 1 uA  
Maximum specification for V  
parameter changed from 2.0 to 2.1V  
OH5A  
Minimum voltages for F  
(Table 18)  
and F  
specifications changed from 1.8V to 1.71V  
SPIM  
SPIS  
Updated V  
parameter in Table 13  
OHV  
Updated Thermal impedance values for the packages - Table 20.  
Update Development Tools, add Designing with PSoC Designer. Edit, fix links and  
table format. Update TMs. Update maximum data in Table 12. DC POR and LVD  
Specifications.  
Document Number: 001-12395 Rev *H  
Page 29 of 30  
CY7C604XX  
Document Title: CY7C604XX, enCoRe™ V Low Voltage Microcontroller  
Document Number: 001-12395  
*H  
2653717 DVJA/PYRS  
02/04/09  
Changed master page from CY7C60445, CY7C6045X to CY7C604XX.  
Updated Features, Functional Overview, Development Tools, and Designing with  
PSoC Designer sections.  
Removed ‘GUI - graphical user interface’ from Document Conventions acronym  
table.  
Added Figure 1 and Table 1 (16-pin part information) to Pin Configurations section.  
Removed ‘O - Only a read/write register or bits’ in Table 4  
Edited Table 8: removed 10-bit resolution information and corrected units column.  
Added Figure 9 (16-pin part information) to Package Dimensions section.  
Added ‘Package Handling’ section.  
Added 8K part ‘CY7C60413-16LKXC’ to Ordering Information.  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Clocks & Buffers  
Wireless  
Memories  
CAN 2.0b  
Image Sensors  
USB  
© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-12395 Rev *H  
Revised January 30, 2009  
Page 30 of 30  
enCoRe™, PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corporation. All other trademarks or registered  
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the  
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names  
mentioned in this document may be the trademarks of their respective holders.  

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