Cypress Perform STK12C68 User Manual

STK12C68  
64 Kbit (8K x 8) AutoStore nvSRAM  
Features  
Functional Description  
25 ns, 35 ns, and 45 ns access times  
The Cypress STK12C68 is a fast static RAM with a nonvolatile  
element in each memory cell. The embedded nonvolatile  
Hands off automatic STORE on power down with external 68  
µF capacitor  
elements incorporate QuantumTrap technology producing the  
world’s most reliable nonvolatile memory. The SRAM provides  
unlimited read and write cycles, while independent nonvolatile  
data resides in the highly reliable QuantumTrap cell. Data  
transfers from the SRAM to the nonvolatile elements (the  
STORE operation) takes place automatically at power down. On  
power up, data is restored to the SRAM (the RECALL operation)  
from the nonvolatile memory. Both the STORE and RECALL  
operations are also available under software control. A hardware  
STORE is initiated with the HSB pin.  
STORE to QuantumTrap™ nonvolatile elements is initiated by  
software, hardware, or AutoStore™ on power down  
RECALL to SRAM initiated by software or power up  
Unlimited Read, Write, and Recall cycles  
1,000,000 STORE cycles to QuantumTrap  
100 year data retention to QuantumTrap  
Single 5V+10% operation  
Commercial and industrial temperatures  
228-pin (330mil) SOIC, 28-pin (300mil) PDIP, 28-pin (600mil)  
PDIP packages  
28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages  
RoHS compliance  
Logic Block Diagram  
V
CC  
V
CAP  
Quantum Trap  
128 X 512  
A5  
A6  
POWER  
CONTROL  
STORE  
A7  
RECALL  
STORE/  
RECALL  
CONTROL  
STATIC RAM  
ARRAY  
128 X 512  
A8  
HSB  
A9  
A11  
A12  
SOFTWARE  
DETECT  
A0  
-
A12  
DQ0  
COLUMN I/O  
DQ1  
DQ2  
DQ3  
COLUMN DEC  
DQ4  
DQ5  
DQ6  
DQ7  
A0  
A4  
A10  
A1  
A3  
A2  
OE  
CE  
WE  
Cypress Semiconductor Corporation  
Document Number: 001-51027 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 30, 2009  
STK12C68  
During normal operation, the device draws current from VCC to  
charge a capacitor connected to the VCAP pin. This stored  
charge is used by the chip to perform a single STORE operation.  
If the voltage on the VCC pin drops below VSWITCH, the part  
automatically disconnects the VCAP pin from VCC. A STORE  
operation is initiated with power provided by the VCAP capacitor.  
Device Operation  
The STK12C68 nvSRAM is made up of two functional compo-  
nents paired in the same physical cell. These are an SRAM  
memory cell and a nonvolatile QuantumTrap cell. The SRAM  
memory cell operates as a standard fast static RAM. Data in the  
SRAM is transferred to the nonvolatile cell (the STORE  
operation) or from the nonvolatile cell to SRAM (the RECALL  
operation). This unique architecture enables the storage and  
recall of all cells in parallel. During the STORE and RECALL  
operations, SRAM Read and Write operations are inhibited. The  
STK12C68 supports unlimited reads and writes similar to a  
typical SRAM. In addition, it provides unlimited RECALL opera-  
tions from the nonvolatile cells and up to one million STORE  
operations.  
Figure 2 shows the proper connection of the storage capacitor  
(VCAP) for automatic store operation. A charge storage capacitor  
between 68 µF and 220 µF (+20%) rated at 6V should be  
provided. The voltage on the VCAP pin is driven to 5V by a charge  
pump internal to the chip. A pull up is placed on WE to hold it  
inactive during power up.  
Figure 2. AutoStore Mode  
SRAM Read  
The STK12C68 performs a Read cycle whenever CE and OE are  
LOW while WE and HSB are HIGH. The address specified on  
pins A0–12 determines the 8,192 data bytes accessed. When the  
Read is initiated by an address transition, the outputs are valid  
after a delay of tAA (Read cycle 1). If the Read is initiated by CE  
or OE, the outputs are valid at tACE or at tDOE, whichever is later  
(Read cycle 2). The data outputs repeatedly respond to address  
changes within the tAA access time without the need for transi-  
tions on any control input pins, and remains valid until another  
address change or until CE or OE is brought HIGH, or WE or  
HSB is brought LOW.  
9&$3  
9FF  
:(  
+6%  
SRAM Write  
A Write cycle is performed whenever CE and WE are LOW and  
HSB is HIGH. The address inputs must be stable prior to entering  
the Write cycle and must remain stable until either CE or WE  
goes HIGH at the end of the cycle. The data on the common IO  
pins DQ0–7 are written into the memory if it has valid tSD, before  
the end of a WE controlled Write or before the end of an CE  
controlled Write. Keep OE HIGH during the entire Write cycle to  
avoid data bus contention on common IO lines. If OE is left LOW,  
internal circuitry turns off the output buffers tHZWE after WE goes  
LOW.  
9VV  
In system power mode, both VCC and VCAP are connected to the  
+5V power supply without the 68 μF capacitor. In this mode, the  
AutoStore function of the STK12C68 operates on the stored  
system charge as power goes down. The user must, however,  
guarantee that VCC does not drop below 3.6V during the 10 ms  
STORE cycle.  
AutoStore Operation  
The STK12C68 stores data to nvSRAM using one of three  
storage operations:  
To reduce unnecessary nonvolatile stores, AutoStore, and  
Hardware Store operations are ignored, unless at least one Write  
operation has taken place since the most recent STORE or  
RECALL cycle. Software initiated STORE cycles are performed  
regardless of whether a Write operation has taken place. An  
optional pull up resistor is shown connected to HSB. The HSB  
signal is monitored by the system to detect if an AutoStore cycle  
is in progress.  
1. Hardware store activated by HSB  
2. Software store activated by an address sequence  
3. AutoStore on device power down  
AutoStore operation is a unique feature of QuantumTrap  
technology and is enabled by default on the STK12C68.  
Document Number: 001-51027 Rev. **  
Page 3 of 20  
 
STK12C68  
Figure 3. AutoStore Inhibit Mode  
During any STORE operation, regardless of how it is initiated,  
the STK12C68 continues to drive the HSB pin LOW, releasing it  
only when the STORE is complete. After completing the STORE  
operation, the STK12C68 remains disabled until the HSB pin  
returns HIGH.  
9&$3  
9FF  
:(  
If HSB is not used, it is left unconnected.  
Hardware RECALL (Power Up)  
+6%  
During power up or after any low power condition (VCC  
<
V
RESET), an internal RECALL request is latched. When VCC  
once again exceeds the sense voltage of VSWITCH, a RECALL  
cycle is automatically initiated and takes tHRECALL to complete.  
If the STK12C68 is in a Write state at the end of power up  
RECALL, the SRAM data is corrupted. To help avoid this  
situation, a 10 Kohm resistor is connected either between WE  
and system VCC or between CE and system VCC  
.
Software STORE  
Data is transferred from the SRAM to the nonvolatile memory by  
a software address sequence. The STK12C68 software STORE  
cycle is initiated by executing sequential CE controlled Read  
cycles from six specific address locations in exact order. During  
the STORE cycle, an erase of the previous nonvolatile data is  
first performed followed by a program of the nonvolatile  
elements. When a STORE cycle is initiated, input and output are  
disabled until the cycle is completed.  
9VV  
If the power supply drops faster than 20 us/volt before Vcc  
reaches VSWITCH, then a 2.2 ohm resistor should be connected  
between VCC and the system supply to avoid momentary excess  
Because a sequence of Reads from specific addresses is used  
for STORE initiation, it is important that no other Read or Write  
accesses intervene in the sequence. If they intervene, the  
sequence is aborted and no STORE or RECALL takes place.  
of current between VCC and VCAP  
.
AutoStore Inhibit Mode  
If an automatic STORE on power loss is not required, then VCC  
is tied to ground and +5V is applied to VCAP (Figure 3). This is  
the AutoStore Inhibit mode, where the AutoStore function is  
disabled. If the STK12C68 is operated in this configuration, refer-  
ences to VCC are changed to VCAP throughout this data sheet.  
In this mode, STORE operations are triggered through software  
control or the HSB pin. To enable or disable Autostore using an  
I/O port pin see Preventing Store on page 5. It is not permissible  
to change between these three options “on the fly”.  
To initiate the software STORE cycle, the following Read  
sequence is performed:  
1. Read address 0x0000, Valid READ  
2. Read address 0x1555, Valid READ  
3. Read address 0x0AAA, Valid READ  
4. Read address 0x1FFF, Valid READ  
5. Read address 0x10F0, Valid READ  
6. Read address 0x0F0F, Initiate STORE cycle  
Hardware STORE (HSB) Operation  
The software sequence is clocked with CE controlled Reads or  
OE controlled Reads. When the sixth address in the sequence  
is entered, the STORE cycle commences and the chip is  
disabled. It is important that Read cycles and not Write cycles  
are used in the sequence. It is not necessary that OE is LOW for  
a valid sequence. After the tSTORE cycle time is fulfilled, the  
SRAM is again activated for Read and Write operation.  
The STK12C68 provides the HSB pin for controlling and  
acknowledging the STORE operations. The HSB pin is used to  
request a hardware STORE cycle. When the HSB pin is driven  
LOW, the STK12C68 conditionally initiates a STORE operation  
after tDELAY. An actual STORE cycle only begins if a Write to the  
SRAM takes place since the last STORE or RECALL cycle. The  
HSB pin also acts as an open drain driver that is internally driven  
LOW to indicate a busy condition, while the STORE (initiated by  
any means) is in progress.  
Software RECALL  
Data is transferred from the nonvolatile memory to the SRAM by  
a software address sequence. A software RECALL cycle is  
initiated with a sequence of Read operations in a manner similar  
to the software STORE initiation. To initiate the RECALL cycle,  
the following sequence of CE controlled Read operations is  
performed:  
SRAM Read and Write operations, that are in progress when  
HSB is driven LOW by any means, are given time to complete  
before the STORE operation is initiated. After HSB goes LOW,  
the STK12C68 continues SRAM operations for tDELAY. During  
tDELAY, multiple SRAM Read operations take place. If a Write is  
in progress when HSB is pulled LOW, it allows a time, tDELAY to  
complete. However, any SRAM Write cycles requested after  
HSB goes LOW are inhibited until HSB returns HIGH.  
1. Read address 0x0000, Valid READ  
2. Read address 0x1555, Valid READ  
Document Number: 001-51027 Rev. **  
Page 4 of 20  
 
STK12C68  
3. Read address 0x0AAA, Valid READ  
4. Read address 0x1FFF, Valid READ  
5. Read address 0x10F0, Valid READ  
6. Read address 0x0F0E, Initiate RECALL cycle  
The VCC level  
IO loading  
Figure 4. Current Versus Cycle Time (Read)  
Internally, RECALL is a two step procedure. First, the SRAM data  
is cleared; then, the nonvolatile information is transferred into the  
SRAM cells. After the tRECALL cycle time, the SRAM is again  
ready for Read and Write operations. The RECALL operation  
does not alter the data in the nonvolatile elements. The nonvol-  
atile data can be recalled an unlimited number of times.  
Data Protection  
The STK12C68 protects data from corruption during low voltage  
conditions by inhibiting all externally initiated STORE and Write  
operations. The low voltage condition is detected when VCC is  
less than VSWITCH. If the STK12C68 is in a Write mode (both CE  
and WE are low) at power up after a RECALL or after a STORE,  
the Write is inhibited until a negative transition on CE or WE is  
detected. This protects against inadvertent writes during power  
up or brown out conditions.  
Figure 5. Current Versus Cycle Time (Write)  
Noise Considerations  
The STK12C68 is a high speed memory. It must have a high  
frequency bypass capacitor of approximately 0.1 µF connected  
between VCC and VSS, using leads and traces that are as short  
as possible. As with all high speed CMOS ICs, careful routing of  
power, ground, and signals reduce circuit noise.  
Hardware Protect  
The STK12C68 offers hardware protection against inadvertent  
STORE operation and SRAM Writes during low voltage condi-  
tions. When VCAP<VSWITCH, all externally initiated STORE  
operations and SRAM Writes are inhibited. AutoStore can be  
completely disabled by tying VCC to ground and applying +5V to  
V
CAP. This is the AutoStore Inhibit mode; in this mode, STOREs  
are only initiated by explicit request using either the software  
sequence or the HSB pin.  
Preventing Store  
Low Average Active Power  
The STORE function is disabled by holding HSB high with a  
driver capable of sourcing 30 mA at a VOH of at least 2.2V,  
because it must overpower the internal pull down device. This  
device drives HSB LOW for 20 μs at the onset of a STORE.  
When the STK12C68 is connected for AutoStore operation  
CMOS technology provides the STK12C68 the benefit of  
drawing significantly less current when it is cycled at times longer  
than 50 ns. Figure 4 shows the relationship between ICC and  
Read or Write cycle time. Worst case current consumption is  
shown for both CMOS and TTL input levels (commercial temper-  
ature range, VCC = 5.5V, 100% duty cycle on chip enable). Only  
standby current is drawn when the chip is disabled. The overall  
average current drawn by the STK12C68 depends on the  
following items:  
(system VCC connected to VCC and a 68 μF capacitor on VCAP  
)
and VCC crosses VSWITCH on the way down, the STK12C68  
attempts to pull HSB LOW. If HSB does not actually get below  
VIL, the part stops trying to pull HSB LOW and abort the STORE  
attempt.  
The duty cycle of chip enable  
The overall cycle rate for accesses  
The ratio of Reads to Writes  
CMOS versus TTL input levels  
The operating temperature  
Document Number: 001-51027 Rev. **  
Page 5 of 20  
   
STK12C68  
manufacturing test to ensure these system routines work  
consistently.  
Best Practices  
nvSRAM products have been used effectively for over 15 years.  
While ease-of-use is one of the product’s main system values,  
experience gained working with hundreds of applications has  
resulted in the following suggestions as best practices:  
Power up boot firmware routines should rewrite the nvSRAM  
into the desired state. While the nvSRAM is shipped in a preset  
state, best practice is to again rewrite the nvSRAM into the  
desired state as a safeguard against events that might flip the  
bit inadvertently (program bugs, incoming inspection routines,  
and so on).  
The nonvolatile cells in an nvSRAM are programmed on the  
test floor during final test and quality assurance. Incoming  
inspection routines at customer or contract manufacturer’s  
sites sometimes reprograms these values. Final NV patterns  
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.  
Theendproduct’sfirmwareshouldnotassumethatanNVarray  
is in a set programmed state. Routines that check memory  
content values to determine first time system configuration,  
cold or warm boot status, and so on must always program a  
unique NV pattern (for example, complex 4-byte pattern of 46  
E6 49 53 hex or more random bytes) as part of the final system  
The Vcap value specified in this data sheet includesa minimum  
and a maximum value size. The best practice is to meet this  
requirementandnotexceedthemaximumVcapvaluebecause  
the higher inrush currents may reduce the reliability of the  
internal pass transistor. Customers who want to use a larger  
Vcap value to make sure there is extra store charge should  
discuss their Vcap size selection with Cypress.  
Table 1. Hardware Mode Selection  
CE  
H
L
WE  
X
HSB  
H
A12–A0  
Mode  
IO  
Power  
Standby  
Active[3]  
Active  
X
X
X
X
Not Selected  
Read SRAM  
Write SRAM  
Output High Z  
Output Data  
Input Data  
H
H
L
L
H
X
X
L
Nonvolatile STORE Output High Z  
ICC2  
[2, 3]  
L
H
H
0x0000  
0x1555  
0x0AAA  
0x1FFF  
0x10F0  
0x0F0F  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active ICC2  
Nonvolatile STORE Output High Z  
L
H
H
0x0000  
0x1555  
0x0AAA  
0x1FFF  
0x10F0  
0x0F0E  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active[2, 3]  
Nonvolatile RECALL Output High Z  
Notes  
1. HSB STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle. After the STORE (If any) completes, the part goes into standby  
mode, inhibiting all operations until HSB rises.  
2. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.  
3. I/O state assumes OE < V . Activation of nonvolatile cycles does not depend on state of OE.  
IL  
Document Number: 001-51027 Rev. **  
Page 6 of 20  
       
STK12C68  
Voltage on DQ0-7 or HSB .......................–0.5V to Vcc + 0.5V  
Power Dissipation.......................................................... 1.0W  
DC output Current (1 output at a time, 1s duration) .... 15 mA  
Maximum Ratings  
Exceeding maximum ratings may shorten the useful life of the  
device. These user guidelines are not tested.  
Storage Temperature ................................. –65°C to +150°C  
Temperature under Bias ............................. –55°C to +125°C  
Voltage on Input Relative to GND.....................–0.5V to 7.0V  
Voltage on Input Relative to Vss............0.6V to VCC + 0.5V  
Operating Range  
Range  
Commercial  
Industrial  
Ambient Temperature  
0°C to +70°C  
VCC  
4.5V to 5.5V  
4.5V to 5.5V  
-40°C to +85°C  
DC Electrical Characteristics  
Over the operating range (VCC = 4.5V to 5.5V) [4]  
Parameter  
Description  
Test Conditions  
Min  
Max  
Unit  
ICC1  
Average VCC Current tRC = 25 ns  
85  
75  
65  
mA  
mA  
mA  
t
RC = 35 ns  
tRC = 45 ns  
Dependent on output loading and cycle rate. Values obtained  
without output loads.  
I
OUT = 0 mA.  
Average VCC Current All Inputs Do Not Care, VCC = Max  
during STORE Average current for duration tSTORE  
Average VCC Current at WE > (VCC – 0.2V). All other inputs cycling.  
RC= 200 ns, 5V, 25°C Dependent on output loading and cycle rate. Values obtained  
Typical without output loads.  
ICC2  
ICC3  
3
mA  
mA  
10  
t
ICC4  
Average VCAP Current All Inputs Do Not Care, VCC = Max  
during AutoStore Cycle Average current for duration tSTORE  
2
mA  
[5]  
ISB1  
VCC Standby Current  
(Standby, Cycling TTL tRC = 35 ns, CE > VIH  
Input Levels)  
tRC = 25 ns, CE > VIH  
27  
24  
20  
mA  
mA  
mA  
tRC = 45 ns, CE > VIH  
[5]  
ISB2  
VCC Standby Current  
CE > (VCC – 0.2V). All others VIN < 0.2V or > Commercial  
(VCC – 0.2V). Standby current level after  
1.5  
mA  
nonvolatile cycle is complete.  
Inputs are static. f = 0 MHz.  
Industrial  
2.5  
mA  
IIX  
Input Leakage Current VCC = Max, VSS < VIN < VCC  
Input Leakage Current VCC = Max, VSS < VIN < VCC  
-1  
-1  
-5  
+1  
+1  
+5  
μA  
μA  
μA  
IIX  
IOZ  
Off State Output  
Leakage Current  
VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL  
VIH  
Input HIGH Voltage  
2.2  
VCC  
0.5  
+
V
VIL  
Input LOW Voltage  
VSS – 0.5  
2.4  
0.8  
V
V
V
V
VOH  
VOL  
VBL  
Output HIGH Voltage IOUT = –4 mA  
Output LOW Voltage  
IOUT = 8 mA  
OUT = 3 mA  
0.4  
0.4  
Logic ‘0’ Voltage on  
HSB Output  
I
VCAP  
Storage Capacitor  
Between Vcap pin and Vss, 6V rated. 68 µF +20% nom.  
54  
260  
µF  
Notes  
4.  
V
reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or V  
if VCC is connected to ground.  
CC  
CAP  
5. CE > V does not produce standby current levels until any nonvolatile cycle in progress has timed out.  
IH  
Document Number: 001-51027 Rev. **  
Page 7 of 20  
   
STK12C68  
Data Retention and Endurance  
Parameter  
DATAR  
Description  
Data Retention  
Nonvolatile STORE Operations  
Min  
100  
Unit  
Years  
K
NVC  
1,000  
Capacitance  
In the following table, the capacitance parameters are listed.[6]  
Parameter  
CIN  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max  
8
Unit  
pF  
TA = 25°C, f = 1 MHz,  
CC = 0 to 3.0 V  
V
COUT  
7
pF  
Thermal Resistance  
In the following table, the thermal resistance parameters are listed.[6]  
28-PDIP 28-PDIP  
(300 mil) (600 mil)  
Parameter  
Description  
Test Conditions  
28-SOIC  
28-CDIP  
28-LCC  
Unit  
ΘJA  
Thermal Resis-  
tance  
(Junction to  
Ambient)  
Test conditions follow  
standard test methods and  
procedures for measuring  
thermal impedance, per EIA /  
JESD51.  
46.55  
45.16  
55.84  
46.1  
95.31  
°C/W  
ΘJC  
Thermal Resis-  
tance  
27.95  
31.62  
25.74  
5.01  
9.01  
°C/W  
(Junction to Case)  
Figure 6. AC Test Loads  
R1 963Ω  
R1 963Ω  
For Tri-state Specs  
5.0V  
5.0V  
Output  
Output  
R2  
R2  
512  
30 pF  
5 pF  
512Ω  
Ω
AC Test Conditions  
Input Pulse Levels..................................................0 V to 3 V  
Input Rise and Fall Times (10% to 90%)...................... <5 ns  
Input and Output Timing Reference Levels.......................1.5  
Note  
6. These parameters are guaranteed by design and are not tested.  
Document Number: 001-51027 Rev. **  
Page 8 of 20  
 
STK12C68  
AC Switching Characteristics  
SRAM Read Cycle  
Parameter  
25 ns  
35 ns  
45 ns  
Unit  
Description  
Cypress  
Alt  
Min  
Max  
Min  
Max  
Min  
Max  
Parameter  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time  
Read Cycle Time  
25  
35  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ACE  
ELQV  
t
25  
35  
45  
RC  
AA  
AVAV, ELEH  
[8]  
Address Access Time  
25  
10  
35  
15  
45  
20  
AVQV  
Output Enable to Data Valid  
Output Hold After Address Change  
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
DOE  
OHA  
GLQV  
[8]  
5
5
5
5
5
5
AXQX  
[9]  
[9]  
[9]  
[9]  
LZCE  
HZCE  
LZOE  
HZOE  
ELQX  
10  
10  
25  
10  
10  
35  
12  
12  
45  
EHQZ  
0
0
0
0
0
0
GLQX  
GHQZ  
[6]  
PU  
ELICCH  
EHICCL  
[6]  
PD  
Switching Waveforms  
Figure 7. SRAM Read Cycle 1: Address Controlled [7, 8]  
W5&  
$''5(66  
W$$  
W2+$  
'4ꢀꢊ'$7$ꢀ287ꢋ  
'$7$ꢀ9$/,'  
Figure 8. SRAM Read Cycle 2: CE and OE Controlled [7]  
W5&  
$''5(66  
&(  
W$&(  
W3'  
W+=&(  
W/=&(  
2(  
W+=2(  
W'2(  
W/=2(  
'4ꢀꢊ'$7$ꢀ287ꢋ  
'$7$ꢀ9$/,'  
$&7,9(  
W38  
67$1'%<  
,&&  
Notes  
7. WE and HSB must be High during SRAM Read cycles.  
8. Device is continuously selected with CE and OE both Low.  
9. Measured ±200 mV from steady state output voltage.  
Document Number: 001-51027 Rev. **  
Page 9 of 20  
     
STK12C68  
SRAM Write Cycle  
Parameter  
25 ns  
35 ns  
45 ns  
Unit  
Description  
Write Cycle Time  
Cypress  
Parameter  
Alt  
Min  
Max  
Min  
Max  
Min  
Max  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
25  
20  
20  
10  
0
35  
25  
25  
12  
0
45  
30  
30  
15  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
AVAV  
WLWH, WLEH  
t
Write Pulse Width  
PWE  
SCE  
SD  
t
Chip Enable To End of Write  
Data Setup to End of Write  
Data Hold After End of Write  
Address Setup to End of Write  
Address Setup to Start of Write  
Address Hold After End of Write  
Write Enable to Output Disable  
Output Active After End of Write  
ELWH, ELEH  
t
DVWH, DVEH  
t
HD  
WHDX, EHDX  
t
20  
0
25  
0
30  
0
AW  
AVWH, AVEH  
t
SA  
AVWL, AVEL  
t
0
0
0
HA  
WHAX, EHAX  
[9]  
10  
13  
14  
HZWE  
LZWE  
WLQZ  
WHQX  
5
5
5
Switching Waveforms  
Figure 9. SRAM Write Cycle 1: WE Controlled [11, 12]  
tWC  
ADDRESS  
CE  
tHA  
tSCE  
tAW  
tSA  
tPWE  
WE  
tHD  
tSD  
DATA VALID  
DATA IN  
tHZWE  
tLZWE  
HIGH IMPEDANCE  
PREVIOUS DATA  
DATA OUT  
Figure 10. SRAM Write Cycle 2: CE Controlled [11, 12]  
tWC  
ADDRESS  
tHA  
tSCE  
tSA  
CE  
WE  
tAW  
tPWE  
tSD  
tHD  
DATA IN  
DATA VALID  
HIGH IMPEDANCE  
DATA OUT  
Notes  
10. If WE is Low when CE goes Low, the outputs remain in the high impedance state.  
11. HSB must be high during SRAM Write cycles.  
12.  
CE or WE must be greater than V during address transitions.  
IH  
Document Number: 001-51027 Rev. **  
Page 10 of 20  
     
STK12C68  
AutoStore or Power Up RECALL  
STK12C68  
Max  
Parameter  
Alt  
Description  
Unit  
Min  
t
t
t
t
t
t
Power up RECALL Duration  
STORE Cycle Duration  
550  
10  
μs  
ms  
HRECALL  
RESTORE  
HLHZ  
STORE  
DELAY  
[9, 15]  
t
Time Allowed to Complete SRAM Cycle  
Low Voltage Trigger Level  
Low Voltage Reset Level  
1
μs  
V
HLQZ , BLQZ  
V
V
t
4.0  
4.5  
3.9  
SWITCH  
RESET  
V
V
Rise Time  
150  
μs  
ns  
VCCRISE  
CC  
t
Low Voltage Trigger (V  
) to HSB Low  
300  
VSBL  
SWITCH  
Switching Waveform  
Figure 11. AutoStore/Power Up RECALL  
WE  
Notes  
13. t  
starts from the time V rises above V  
.
SWITCH  
HRECALL  
CC  
14. CE and OE low for output behavior.  
15. CE and OE low and WE high for output behavior.  
16. HSB is asserted low for 1us when V  
takes place.  
drops through V  
. If an SRAM Write has not taken place since the last nonvolatile cycle, HSB is released and no store  
CAP  
SWITCH  
Document Number: 001-51027 Rev. **  
Page 11 of 20  
       
STK12C68  
Software Controlled STORE/RECALL Cycle  
The software controlled STORE/RECALL cycle follows.  
25 ns  
35 ns  
45 ns  
Unit  
Parameter  
Alt  
Description  
Min  
Max  
Min  
Max  
Min  
Max  
RC  
t
t
t
t
t
t
t
t
t
STORE/RECALL Initiation Cycle Time  
Address Setup Time  
25  
0
35  
0
45  
0
ns  
ns  
ns  
ns  
AVAV  
AVEL  
ELEH  
ELAX  
SA  
CW  
Clock Pulse Width  
20  
20  
25  
20  
30  
20  
Address Hold Time  
HACE  
RECALL Duration  
20  
20  
20  
μs  
RECALL  
Switching Waveform  
Figure 12. CE Controlled Software STORE/RECALL Cycle [18]  
tRC  
tRC  
ADDRESS # 1  
ADDRESS # 6  
ADDRESS  
tSA  
tSCE  
CE  
tHACE  
OE  
t
STORE / tRECALL  
HIGH IMPEDANCE  
DATA VALID  
DATA VALID  
DQ (DATA)  
Notes  
17. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).  
18. The six consecutive addresses must be read in the order listed in Table 1 on page 6. WE must be HIGH during all six consecutive cycles.  
Document Number: 001-51027 Rev. **  
Page 12 of 20  
   
STK12C68  
Hardware STORE Cycle  
STK12C68  
Parameter  
Alt  
Description  
STORE Cycle Duration  
Unit  
Min  
Max  
10  
[9, 14]  
t
t
t
t
t
t
t
ms  
ns  
ns  
ns  
STORE  
HLHZ  
t
Hardware STORE High to Inhibit Off  
Hardware STORE Pulse Width  
700  
DHSB  
PHSB  
HLBL  
RECOVER, HHQX  
15  
HLHX  
Hardware STORE Low to STORE Busy  
300  
Switching Waveform  
Figure 13. Hardware STORE Cycle  
Note  
19. t  
is only applicable after t  
is complete.  
STORE  
DHSB  
Document Number: 001-51027 Rev. **  
Page 13 of 20  
 
STK12C68  
Part Numbering nomenclature  
STK12C68 - S F 45 I TR  
Packaging Option:  
TR = Tape and Reel  
Blank = Tube  
Temperature Range:  
C - Commercial (0 to 70°C)  
I - Industrial (-40 to 85°C)  
Speed:  
25 - 25 ns  
35 - 35 ns  
45 - 45 ns  
Lead Finish  
F = 100% Sn (Matte Tin)  
Package:  
S = Plastic 28-pin 330 mil SOIC  
P = Plastic 28-pin 300 mil DIP  
W = Plastic 28-pin 600 mil DIP  
C = Ceramic 28-pin 300 mil DIP  
L = Ceramic 28-pin LLC  
Ordering Information  
Speed (ns)  
Ordering Code  
STK12C68-SF25TR  
STK12C68-SF25  
STK12C68-PF25  
STK12C68-WF25  
STK12C68-SF25ITR  
STK12C68-SF25I  
STK12C68-PF25I  
STK12C68-WF25I  
STK12C68-C35  
Package Diagram  
001-85058  
001-85058  
001-85014  
001-85017  
001-85058  
001-85058  
001-85014  
001-85017  
001-51695  
001-51696  
001-51695  
001-51696  
Package Type  
28-pin SOIC (330 mil)  
28-pin SOIC (330 mil)  
28-pin PDIP (300 mil)  
28-pin PDIP (600 mil)  
28-pin SOIC (330 mil)  
28-pin SOIC (330 mil)  
28-pin PDIP (300 mil)  
28-pin PDIP (600 mil)  
28-pin CDIP (300 mil)  
28-pin LCC (350 mil)  
28-pin CDIP (300 mil)  
28-pin LCC (350 mil)  
Operating Range  
Commercial  
25  
Industrial  
35  
Commercial  
Industrial  
STK12C68-L35  
STK12C68-C35I  
STK12C68-L35I  
Document Number: 001-51027 Rev. **  
Page 14 of 20  
STK12C68  
Ordering Information (continued)  
Speed (ns)  
Ordering Code  
STK12C68-SF45TR  
STK12C68-SF45  
STK12C68-PF45  
STK12C68-WF45  
STK12C68-C45  
Package Diagram  
001-85058  
001-85058  
001-85014  
001-85017  
001-51695  
001-51696  
001-85058  
001-85058  
001-85014  
001-85017  
001-51695  
001-51696  
Package Type  
28-pin SOIC (330 mil)  
28-pin SOIC (330 mil)  
28-pin PDIP (300 mil)  
28-pin PDIP (600 mil)  
28-pin CDIP (300 mil)  
28-pin LCC (350 mil)  
28-pin SOIC (330 mil)  
28-pin SOIC (330 mil)  
28-pin PDIP (300 mil)  
28-pin PDIP (600 mil)  
28-pin CDIP (300 mil)  
28-pin LCC (350 mil)  
Operating Range  
Commercial  
45  
STK12C68-L45  
STK12C68-SF45ITR  
STK12C68-SF45I  
STK12C68-PF45I  
STK12C68-WF45I  
STK12C68-C45I  
STK12C68-L45I  
Industrial  
All parts are Pb-free. The above table contains Final information. Contact your local Cypress sales representative for availability of these parts  
Document Number: 001-51027 Rev. **  
Page 15 of 20  
STK12C68  
Package Diagrams  
Figure 14. 28-Pin (330 Mil) SOIC (51-85058)  
51-85058 *A  
Figure 15. 28-Pin (300 Mil) PDIP (51-85014)  
51-85014 *D  
Document Number: 001-51027 Rev. **  
Page 16 of 20  
STK12C68  
Package Diagrams (continued)  
Figure 16. 28-Pin (600 Mil) PDIP (51-85017)  
51-85017 *B  
Document Number: 001-51027 Rev. **  
Page 17 of 20  
STK12C68  
Package Diagrams (continued)  
Figure 17. 28-Pin (300 Mil) Side Braze DIL (001-51695)  
001-51695 **  
Document Number: 001-51027 Rev. **  
Page 18 of 20  
STK12C68  
Package Diagrams (continued)  
Figure 18. 28-Pad (350 Mil) LCC (001-51696)  
1. ALL DIMENSION ARE IN INCHES AND MILLIMETERS [MIN/MAX]  
2. JEDEC 95 OUTLINE# MO-041  
3. PACKAGE WEIGHT : TBD  
001-51696 **  
Document Number: 001-51027 Rev. **  
Page 19 of 20  
STK12C68  
Document History Page  
Document Title: STK12C68 64 Kbit (8K x 8) AutoStore nvSRAM  
Document Number: 001-51027  
Orig. of  
Change  
Submission  
Date  
Rev.  
ECN No.  
Description of Change  
**  
2606744  
GVCH  
01/30/2009 New data sheet  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-51027 Rev. **  
Revised January 30, 2009  
Page 20 of 20  
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective  
holders.  

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