CY7C68000A
MoBL-USB™ TX2 USB 2.0 UTMI
Transceiver
■ Supports transmission of Resume Signaling
■ 3.3V Operation
MoBL-USB™TX2 Features
■ UTMI-compliant and USB 2.0 certified for device operation
■ Two package options: 56-pin QFN and 56-pin VFBGA
■ Operates in both USB 2.0 High Speed (HS), 480 Mbits/second,
and Full Speed (FS), 12 Mbits/second
■ All required terminations, including 1.5 Kohm pull up on
DPLUS, are internal to chip
®
■ Optimized for Seamless Interface with Intel Monahans Appli-
cations Processors
■ Supports USB 2.0 Test Modes
The Cypress MoBL-USB TX2 is a Universal Serial Bus (USB)
specification revision 2.0 transceiver, serial and deserializer, to a
parallel interface of either 16 bits at 30 MHz or eight bits at 60
MHz. The MoBL-USB TX2 provides a high speed physical layer
interface that operates at the maximum allowable USB 2.0
bandwidth. This enables the system designer to keep the
complex high speed analog USB components external to the
digital ASIC. This decreases development time and associated
risk. A standard USB 2.0-certified interface is provided and is
compliant with Transceiver Macrocell Interface (UTMI) specifi-
cation version 1.05 dated 3/29/2001.
■ Tri-state Mode enables sharing of UTMI Bus with other devices
■ Serial-to-Parallel and Parallel-to-Serial Conversions
■ 8-bit Unidirectional, 8-bit Bidirectional, or 16-bit Bidirectional
External Data Interface
■ Synchronous Field and EOP Detection on Receive Packets
■ Synchronous Field and EOP Generation on Transmit Packets
■ Data and Clock Recovery from the USB Serial Stream
■ Bit stuffing and unstuffing; Bit Stuff Error Detection
This product is also optimized to seamlessly interface with
Monahans -P & -L applications processors. It has been charac-
terized by Intel and is recommended as the USB 2.0 UTMI trans-
ceiver of choice for its Monahans processors. It is also capable
of tri-stating the UTMI bus, while suspended, to enable the bus
to be shared with other devices.
■ Staging Register to manage Data Rate variation due to Bit
stuffing and unstuffing
■ 16-bit 30 MHz and 8-bit 60 MHz Parallel Interface
■ Ability to switch between FS and HS terminations and signaling
■ Supports detection of USB Reset, Suspend, and Resume
Two packages are defined for the family: 56-pin QFN and 56-pin
VFBGA.
■ Supports HSidentification and detection as defined bythe USB
2.0 Specification
The functional block diagram follows.
Logic Block Diagram
Tri_state
Cypress Semiconductor Corporation
Document #: 38-08052 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 5, 2008
CY7C68000A
Mode 0 enables the transceiver to operate with normal USB data
decoding and encoding.
Operational Modes
The operational modes are controlled by the OpMode signals.
The OpMode signals are capable of inhibiting normal operation
of the transceiver and evoking special test modes. These modes
take effect immediately and take precedence over any pending
data operations. The transmission data rate when in OpMode
depends on the state of the XcvrSelect input.
Mode 1 enables the transceiver logic to support a soft disconnect
feature that tri-states both the HS and FS transmitters, and
removes any termination from the USB, making it appear to an
upstream port that the device is disconnected from the bus.
Mode 2 disables Bit Stuff and NRZI encoding logic so ‘1’s loaded
from the data bus becomes ‘J’s on the DPLUS/DMINUS lines
and ‘0’s become ‘K’s.
OpMode[1:0]
Mode
Description
Normal operation
00
01
10
0
1
2
DPLUS/DMINUS Impedance Termination
Non-driving
The CY7C68000A does not require external resistors for USB
data line impedance termination or an external pull up resistor on
the DPLUS line. These resistors are incorporated into the part.
They are factory trimmed to meet the requirements of USB 2.0.
Incorporating these resistors also reduces the pin count on the
part.
Disable Bit Stuffing and NRZI
encoding
11
3
Reserved
Document #: 38-08052 Rev. *G
Page 3 of 15
CY7C68000A
Pin Configurations
The following pages illustrate the individual pin diagrams that are available in the 56-pin QFN and 56-pin VFBGA packages.
The packages offered use either an 8-bit (60 MHz) or 16-bit (30 MHz) bus interface.
Figure 1. CY7C68000A 56-pin QFN Pin Assignment
GND
D5
TXReady
Suspend
Reset
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Reserved
D6
3
AV
4
CC
D7
XTALOUT
XTALIN
AGND
5
D8
6
CY7C68000A
56-pin QFN
D9
7
Reserved
D10
AV
8
CC
DPLUS
DMINUS
9
D11
10
11
12
13
14
V
AGND
CC
D12
GND
D13
XcvrSelect
TermSelect
OpMode0
Document #: 38-08052 Rev. *G
Page 4 of 15
CY7C68000A
Figure 2. CY7C68000A 56-pin VFBGA Pin Assignment
1
2
3
4
5
6
7
8
1A
1B
1C
2A
2B
2C
3A
3B
3C
4A
4B
4C
5A
5B
5C
6A
6B
6C
7A
7B
7C
8A
8B
8C
A
B
C
D
1D
2D
7D
8D
1E
1F
1G
1H
2E
2F
2G
2H
7E
7F
7G
7H
8E
8F
8G
8H
E
3F
4F
5F
6F
F
G
H
3G
3H
4G
4H
5G
5H
6G
6H
Document #: 38-08052 Rev. *G
Page 5 of 15
CY7C68000A
Pin Descriptions
Table 1. Pin Descriptions
QFN VFBGA
Name
AVCC
Type
Power
Power
Power
Power
I/O/Z
I/O/Z
I/O
Default
N/A
N/A
N/A
N/A
Z
Description
Analog V This signal provides power to the analog section of the chip.
4
H1
H5
H4
H8
H6
H7
G8
G7
G5
G3
G2
F8
F6
F5
F4
F3
F1
G4
E1
D8
G1
E2
A1
CC
8
AVCC
AGND
AGND
DPLUS
DMINUS
D0
Analog V This signal provides power to the analog section of the chip.
CC
7
Analog Ground Connect to ground with as short a path as possible.
Analog Ground Connect to ground with as short a path as possible.
USB DPLUS Signal Connect to the USB DPLUS signal.
11
9
10
49
48
46
44
43
41
39
38
37
36
34
33
31
29
27
26
50
Z
USB DMINUS Signal Connect to the USB DMINUS signal.
Bidirectional Data Bus This bidirectional bus is used as the entire data
bus in the 8-bit bidirectional mode or the least significant eight bits in the
16-bit mode. Under the 8-bit unidirectional mode, these bits are used as
inputs for data, selected by the RxValid signal.
D1
I/O
D2
I/O
D3
I/O
D4
I/O
D5
I/O
D6
I/O
D7
I/O
D8
I/O
Bidirectional Data Bus This bidirectional bus is used as the upper eight
bits of the data bus when in the 16-bit mode, and not used when in the
8-bit bidirectional mode. Under the 8-bit unidirectional mode these bits
are used as outputs for data, selected by the TxValid signal.
D9
I/O
D10
D11
D12
D13
D14
D15
CLK
I/O
I/O
I/O
I/O
I/O
I/O
Output
Clock This output is used for clocking the receive and transmit parallel
data on the D[15:0] bus.
3
B2
B3
Reset
Input
Input
N/A
N/A
Active HIGH Reset Resets the entire chip. This pin can be tied to V
CC
through a 0.1-μF capacitor and to GND through a 100 K resistor for a
10-ms RC time constant.
12
XcvrSelect
Transceiver Select This signal selects between the Full Speed (FS) and
the High Speed (HS) transceivers:
0: HS transceiver enabled
1: FS transceiver enabled
13
2
B4
B1
TermSelect
Suspend
Input
Input
N/A
N/A
Termination Select This signal selects between the Full Speed (FS) and
the High Speed (HS) terminations:
0: HS termination
1: FS termination
Suspend Places the CY7C68000A in a mode that draws minimal power
from supplies. Shuts down all blocks not necessary for Suspend/Resume
operations. While suspended, TermSelect must always be in FS mode
to ensure that the 1.5 Kohm pull up on DPLUS remains powered.
0: CY7C68000A circuitry drawing suspend current
1: CY7C68000A circuitry drawing normal current
Note
1. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs that are three-statable should only be pulled up or down to ensure
signals at power-up and in standby.
Document #: 38-08052 Rev. *G
Page 6 of 15
CY7C68000A
Table 1. Pin Descriptions (continued)
[1]
QFN VFBGA
Name
Tri_state
Type
Default
Description (continued)
24
B8
Input
Tri-state Mode Enable Places the CY7C68000A into Tri-state mode
which tri-states all outputs and IOs. Tri-state Mode can only be enabled
while suspended.
0: Disables Tri-state Mode
1: Enables Tri-state Mode
19
C2
LineState1
Output
Line State These signals reflect the current state of the single-ended
receivers. They are combinatorial until a “usable” CLK is available then
they are synchronized to CLK. They directly reflect the current state of the
DPLUS (LineState0) and DMINUS (LineState1).
D– D+ Description
0 0 0: SE0
0 1 1: ‘J’ State
1 0 2: ‘K’ State
1 1 3: SE1
18
C1
LineState0
Output
Line State These signals reflect the current state of the single-ended
receivers. They are combinatorial until a ‘usable’ CLK is available then
they are synchronized to CLK. They directly reflect the current state of the
DPLUS (LineState0) and DMINUS (LineState1).
D– D+ Description
00–0: SE0
01–1: ‘J’ State
10–2: ‘K’ State
11–3: SE1
15
14
54
B6
B5
A5
OpMode1
OpMode0
TXValid
Input
Input
Input
Operational Mode These signals select among various operational
modes.
10 Description
00–0: Normal Operation
01–1: Non-driving
10–2: Disable Bit Stuffing and NRZI encoding
11–3: Reserved
Operational Mode These signals select among various operational
modes.
10 Description
00–0: Normal Operation
01–1: Non-driving
10–2: Disable Bit Stuffing and NRZI encoding
11–3: Reserved
Transmit Valid This signal indicates that the data bus is valid. The asser-
tion of Transmit Valid initiates SYNC on the USB. The negation of Trans-
mit Valid initiates EOP on the USB. The start of SYNC must be initiated
on the USB no less than one or no more that two CLKs after the assertion
of TXValid.
In HS (XcvrSelect = 0) mode, the SYNC pattern must be asserted on the
USB between 8- and 16-bit times after the assertion of TXValid is detected
by the Transmit State Machine.
In FS (Xcvr = 1), the SYNC pattern must be asserted on the USB no less
than one or more than two CLKs after the assertion of TXValid is detected
by the Transmit State Machine.
1
A8
TXReady
Output
Transmit Data Ready If TXValid is asserted, the SIE must always have
data available for clocking in to the TX Holding Register on the rising edge
of CLK. If TXValid is TRUE and TXReady is asserted at the rising edge
of CLK, the CY7C68000A loads the data on the data bus into the TX
Holding Register on the next rising edge of CLK. At that time, the SIE
should immediately present the data for the next transfer on the data bus.
Document #: 38-08052 Rev. *G
Page 7 of 15
CY7C68000A
Table 1. Pin Descriptions (continued)
[1]
QFN VFBGA
Name
RXValid
Type
Default
Description (continued)
21
A4
Output
Receive Data Valid This signal indicates that the DataOut bus has valid
data. The Receive Data Holding Register is full and ready to be unloaded.
The SIE is expected to latch the DataOut bus on the clock edge.
22
B7
RXActive
Output
Receive Active This signal indicates that the receive state machine has
detected SYNC and is active.
RXActive is negated after a bit stuff error or an EOP is detected.
23
56
A6
A7
RXError
ValidH
Output
I/O
Receive Error
0 Indicates no error.
1 Indicates that a receive error has been detected.
ValidH This signal indicates that the high-order eight bits of a 16-bit data
word presented on the Data bus are valid. When DataBus16_8 = 1 and
TXValid = 0, ValidH is an output, indicating that the high-order receive
data byte on the Data bus is valid. When DataBus16_8 = 1 and TXValid
= 1, ValidH is an input and indicates that the high-order transmit data byte,
presented on the Data bus by the transceiver, is valid. When
DataBus16_8 = 0, ValidH is undefined. The status of the receive
low-order data byte is determined by RXValid and are present on D0–D7.
51
A2
H3
DataBus16_8
Input
Input
Data Bus 16_8 This signal selects between 8- and 16-bit data transfers.
1–16-bit data path operation enabled. CLK = 30 MHz.
0–8-bit data path operation enabled. When Uni_Bidi = 0, D[8:15] are un-
defined. When Uni_Bidi =1, D[0:7] are valid on TxValid and D[8:15] are
valid on RxValid. CLK = 60 MHz
Note: DataBus16_8 is static after Power-on Reset (POR) and is only
sampled at the end of Reset.
6
XTALIN
N/A
N/A
Crystal Input Connect this signal to a 24 MHz parallel-resonant, funda-
mental mode crystal and 30 pF capacitor to GND.
It is also correct to drive XTALIN with an external 24 MHz square wave
derived from another clock source.
5
H2
A3
XTALOUT
Uni_Bidi
Output
Input
Crystal Output Connect this signal to a 24 MHz parallel-resonant, funda-
mental mode crystal and 30 pF (nominal) capacitor to GND. If an external
clock is used to drive XTALIN, leave this pin open.
52
Driving this pin HIGH enables the unidirectional mode when the 8-bit
interface is selected. Uni_Bidi is static after power-on reset (POR).
55
17
28
32
45
53
16
20
30
42
47
40
35
25
C6
C7
D7
E7
E8
C4
C5
C3
D1
D2
G6
F7
F2
C8
V
V
V
V
V
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
Ground
INPUT
INPUT
INPUT
INPUT
V
V
V
V
V
. Connect to 3.3V power source.
. Connect to 3.3V power source.
. Connect to 3.3V power source.
. Connect to 3.3V power source.
. Connect to 3.3V power source.
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
Ground.
GND
Ground.
GND
Ground.
GND
Ground.
GND
Ground.
Reserved
Reserved
Reserved
Reserved
Connect pin to Ground.
Connect pin to Ground.
Connect pin to Ground.
Connect pin to Ground.
Document #: 38-08052 Rev. *G
Page 8 of 15
CY7C68000A
Absolute Maximum Ratings
Operating Conditions
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Supplied ..... 0°C to +70°C
Supply Voltage to Ground Potential ...............–0.5V to +4.0V
DC Input Voltage to Any Input Pin ............................. 5.25 V
DC Voltage Applied to Outputs
T (Ambient Temperature Under Bias) ............ 0°C to +70°C
A
Supply Voltage ...............................................+3.0V to +3.6V
Ground Voltage ................................................................. 0V
F
(Oscillator or Crystal Frequency) ... 24 MHz ± 100 ppm
OSC
................................................................... Parallel Resonant
in High-Z State ..................................... –0.5V to V + 0.5V
CC
Power Dissipation .................................................... 630 mW
Static Discharge Voltage ..........................................>2000V
Max Output Current, per IO pin ................................... 4 mA
Max Output Current, all 21–IO pins ............................ 84 mA
DC Characteristics
Table 2. DC Characteristics
Parameter
Description
Supply Voltage
Conditions
Min
3.0
2
Typ
Max
3.6
Unit
V
V
3.3
CC
IH
IL
V
V
Input High Voltage
Input Low Voltage
5.25
0.8
V
–0.5
V
I
Input Leakage Current
Output Voltage High
Output Low Voltage
Output Current High
Output Current Low
Input Pin Capacitance
0< V < V
CC
±10
μA
V
I
IN
V
V
I
I
= 4 mA
2.4
OH
OUT
OUT
= –4 mA
0.4
4
V
OL
I
I
mA
mA
pF
pF
pF
μA
μA
mA
mA
ms
OH
OL
4
C
Except DPLUS/DMINUS/CLK
DPLUS/DMINUS/CLK
Output pins
10
15
30
273
35
175
90
IN
C
I
Maximum Output Capacitance
Suspend Current
LOAD
[2]
Connected
228
8
SUSP
[2]
Disconnected
I
I
t
Supply Current HS Mode
Supply Current FS Mode
Minimum Reset time
Normal operation OPMOD[1:0] = 00
Normal operation OPMOD[1:0] = 00
CC
CC
1.9
RESET
Note
2. Connected to the USB includes 1.5 Kohm internal pull up. Disconnected has the 1.5 Kohm internal pull up excluded.
Document #: 38-08052 Rev. *G
Page 9 of 15
CY7C68000A
AC Electrical Characteristics
USB 2.0 Transceiver
USB 2.0-compliant in FS and HS modes.
Timing Diagram
HS/FS Interface Timing - 60 MHz
Figure 3. 60 MHz Interface Timing Constraints
CLK
TCH_MIN
TCSU_MIN
TDSU_MIN
Control_In
TDH_MIN
DataIn
TCCO
TCDO
Control_Out
DataOut
Table 3. 60 MHz Interface Timing Constraints Parameters
Parameter
Description
Min
4
Typ
Max
Unit
Notes
T
T
T
T
T
Minimum setup time for TXValid
ns
ns
ns
ns
ns
CSU_MIN
CH_MIN
DSU_MIN
DH_MIN
CCO
Minimum hold time for TXValid
1
Minimum setup time for Data (transmit direction)
Minimum hold time for Data (transmit direction)
4
1
Clock to Control out time for TXReady, RXValid,
RXActive and RXError
1
8
8
T
Clock to Data out time (Receive direction)
1
ns
CDO
Document #: 38-08052 Rev. *G
Page 10 of 15
CY7C68000A
HS/FS Interface Timing - 30 MHz
Figure 4. 30 MHz Timing Interface Timing Constraints
CLK
TCH_MIN
TCSU_MIN
Control_In
TDH_MIN
TDSU_MIN
DataIn
Control_Out
DataOut
TCDO
TCCO
TCVO
TVH_MIN
TVSU_MIN
Table 4. 30 MHz Timing Interface Timing Constraints Parameters
Parameter
Description
Min
16
1
Typ
Max
Unit
Notes
T
T
T
T
T
Minimum setup time for TXValid
ns
ns
ns
ns
ns
CSU_MIN
CH_MIN
DSU_MIN
DH_MIN
CCO
Minimum hold time for TXValid
Minimum setup time for Data (Transmit direction)
Minimum hold time for Data (Transmit direction)
16
1
Clock to Control Out time for TXReady, RXValid,
RXActive and RXError
1
20
20
T
T
T
T
Clock to Data out time (Receive direction)
1
16
1
ns
ns
ns
ns
CDO
Minimum setup time for ValidH (transmit Direction)
Minimum hold time for ValidH (Transmit direction)
Clock to ValidH out time (Receive direction)
VSU_MIN
VH_MIN
CVO
1
20
Figure 5. Tri-state Mode Timing Constraints
Ttspd
Ttssu Ttspd
Suspend
Tri-state
Output / IO
XXXX
Hi-Z
Table 5. Tri-state Mode Timing Constraints Parameters
Parameter
Description
Minimum setup time for Tri-state
Propagation Delay for Tri-State mode
Min
Typ
Max
Unit
ns
Notes
T
T
0
tssu
tspd
50
ns
Document #: 38-08052 Rev. *G
Page 11 of 15
CY7C68000A
Ordering Information
Ordering Code
Package Type
CY7C68000A-56LFXC
CY7C68000A-56BAXC
CY3683
56 QFN
56 VFBGA
MoBL-USB TX2 Development Board
Package Diagrams
The MoBL-USB TX2 is available in two packages:
■ 56-pin QFN
■ 56-pin VFBGA
Figure 6. 56-Pin Quad Flatpack No Lead Package 8 x 8 mm (Sawn Version) LS56B
51-85187 *C
Document #: 38-08052 Rev. *G
Page 12 of 15
CY7C68000A
Package Diagrams (continued)
Figure 7. 56 VFBGA (5 x 5 x 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56
TOP VIEW
BOTTOM VIEW
Ø0.05 M C
Ø0.15 M C A B
Ø0.30 0.05(56X)
A1 CORNER
PIN A1 CORNER
1
2
3
4
5
6
6
8
8
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
G
H
0.50
3.50
-B-
-A-
5.00 0.10
SIDE VIEW
5.00 0.10
0.10(4X)
REFERENCE JEDEC: MO-195C
PACKAGE WEIGHT: 0.02 grams
-C-
SEATING PLANE
001-03901-*B
■ Connections between the USB connector shell and signal
ground must be done near the USB connector
PCB Layout Recommendations
Follow these recommendations to ensure reliable, high-perfor-
■ Bypass and flyback capacitors on VBus, near the connector,
are recommended
mance operation
.
■ Afour-layer impedance controlled board is required to maintain
signal quality
■ Keep DPLUS and DMINUS trace lengths within 2 mm of each
other in length, with preferred length of 20 to 30 mm
■ Specify impedance targets (ask your board vendor what they
can achieve)
■ Maintain a solid ground plane under the DPLUS and DMINUS
traces. Do not split the plane under these traces
■ To control impedance, maintain trace widths and trace spacing
to within written specifications
■ Do not place vias on the DPLUS or DMINUS trace routing
■ Isolate the DPLUS and DMINUS traces from all other signal
traces by no less than 10 mm
■ Minimize stubs to minimize reflected signals
Note
3. Source for recommendations: EZ-USB FX2™ PCB Design Recommendations, http:///www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf
High-Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.
Document #: 38-08052 Rev. *G
Page 13 of 15
CY7C68000A
For further information on this package design, refer to the appli-
cation note “Surface Mount Assembly of AMKOR’s MicroLead-
Quad Flat Package No Leads (QFN) Package
Design Notes
AMKOR’s
website,
by
following
this
link:
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. Hence, special attention is required to the
heat transfer area below the package to provide a good thermal
bond to the circuit board. A Copper (Cu) fill is to be designed into
the PCB as a thermal pad under the package. Heat is transferred
from the MoBL-USB TX2 through the device’s metal paddle on
the package bottom. From here, heat is conducted to the PCB at
the thermal pad. It is then conducted from the thermal pad to the
PCB inner ground plane by an array of via. A via is a plated
through-hole in the PCB with a finished diameter of 13 mil. The
QFN’s metal die paddle must be soldered to the PCB’s thermal
pad. Solder mask is placed on the board top, over each via, to
resist solder flow into the via. The mask on the top side also
minimizes outgassing during the solder reflow process.
Note.pdf. The application note provides detailed information on
board mounting guidelines, soldering flow, and rework process.
Figure 8 displays a cross-sectional area under the package. The
cross section is of only one via. The solder paste template needs
to be designed to enable at least 50 percent solder coverage.
The thickness of the solder paste template should be 5 mil. It is
recommended that ‘No Clean’, type 3 solder paste be used for
mounting the part. Nitrogen purge is recommended during
reflow.
assembly (darker areas indicate solder).
Figure 8. Cross section of the Area Underneath the QFN Package
0.017” dia
Solder Mask
Cu Fill
Cu Fill
0.013” dia
PCB Material
PCB Material
Via hole for thermally connecting the
This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and
the Ground Plane
QFN to the circuit board ground plane.
Figure 9. Plot of the Solder Mask (White Area)
Document #: 38-08052 Rev. *G
Page 14 of 15
CY7C68000A
Document History Page
Document Title: CY7C68000A MoBL-USB™ TX2 USB 2.0 UTMI Transceiver
Document Number: 38-08052
Orig. of
Change
Submission
Date
REV.
ECN NO.
Description of Change
**
285592
427959
KKU
TEH
See ECN
See ECN
New data sheet
*A
Addition of VFBGA Package information and Pinout, Removal of SSOP
Package. Edited text and moved figure titles to the top per new template
*B
470121
TEH
See ECN
Change from preliminary to final data sheet. Grammatical and formatting
changes
*C
*D
*E
*F
*G
476107
491668
498415
567869
TEH
TEH
TEH
TEH
See ECN
See ECN
See ECN
See ECN
10/13/08
This data sheet needs to be posted to the web site under NDA
Addition of Tri-state Mode
Update power consumption numbers
Remove NDA requirement
2587010 KKU/PYRS
Update Pin 6 description on Page 8
Update template
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© Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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Document #: 38-08052 Rev. *G
Revised October 5, 2008
Page 15 of 15
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