CY62157EV30 MoBL®
8-Mbit (512K x 16) Static RAM
reduces power consumption when addresses are not toggling.
Features
Place the device into standby mode when deselected (CE
1
• TSOP I package configurable as 512K x 16 or as 1M x 8
SRAM
HIGH or CE LOW or both BHE and BLE are HIGH). The input
2
or output pins (IO through IO ) are placed in a high
0
15
impedance state when:
• High speed: 45 ns
• Deselected (CE HIGH or CE LOW)
1
2
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62157DV30
• Ultra low standby power
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
— Typical Standby current: 2 µA
— Maximum Standby current: 8 µA (Industrial)
• Ultra low active power
• Write operation is active (CE LOW, CE HIGH and WE
1
2
LOW)
To write to the device, take Chip Enable (CE LOW and CE
1
2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO through IO ) is
— Typical active current: 1.8 mA @ f = 1 MHz
0
7
• Easy memory expansion with CE , CE , and OE features
1
2
written into the location specified on the address pins (A
0
• Automatic power down when deselected
• CMOS for optimum speed and power
through A ). If Byte High Enable (BHE) is LOW, then data
18
from IO pins (IO through IO ) is written into the location
8
15
specified on the address pins (A through A ).
0
18
• Available in both Pb-free and non Pb-free 48-ball VFBGA,
Pb-free 44-pin TSOP II and 48-pin TSOP I packages
To read from the device, take Chip Enable (CE LOW and CE
1
2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
Functional Description[1]
The CY62157EV30 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL ) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
appear on IO to IO . If Byte High Enable (BHE) is LOW, then
0
7
8
15
modes.
®
Logic Block Diagram
DATA IN DRIVERS
A
A
A
A
A
A
A
A
A
A
A
10
9
8
7
6
512K × 16 / 1M x 8
5
4
3
2
1
0
RAM Array
IO –IO
0
7
IO –IO
8
15
COLUMN DECODER
BYTE
CE2
CE
BHE
WE
1
PowerDown
Circuit
CE
CE
2
BHE
BLE
1
OE
BLE
Notes
1. For best practice recommendations, please refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 38-05445 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 07, 2007
CY62157EV30 MoBL®
Pin Configuration (continued)
The following picture shows the 48-ball VFBGA pinout.
48-Ball VFBGA
Top View
1
3
4
5
6
2
A2
CE2
A0
A3
A5
A1
A4
A6
BLE OE
A
B
C
IO8
IO0
IO2
BHE
CE1
IO1
IO9
IO10
V
IO11 A17
D
V
A7
IO3
IO4
IO5
CC
SS
V
SS
IO12
A16
A15
A13
A10
V
CC
NC
A14
A12
A9
E
F
IO14 IO13
IO6
IO7
NC
G
H
IO15
A18
NC
A8
WE
A11
Document #: 38-05445 Rev. *E
Page 3 of 14
CY62157EV30 MoBL®
DC Input Voltage
........... –0.3V to 3.9V (V
+ 0.3V)
Maximum Ratings
CC max
Output Current into Outputs (LOW) ............................ 20 mA
Exceeding maximum ratings may shorten the battery life of the
device. User guidelines are not tested.
Static Discharge Voltage ..........................................> 2001V
(MIL-STD-883, Method 3015)
Storage Temperature ................................–65°C to + 150°C
Latch up Current ....................................................> 200 mA
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Operating Range
Supply Voltage to Ground
Ambient
Potential ................................–0.3V to 3.9V (V
+ 0.3V)
+ 0.3V)
Device
Range
V
CC
CCmax
CCmax
Temperature
DC Voltage Applied to Outputs
CY62157EV30LL Ind’l/Auto-A –40°Cto+85°C
2.20V to
3.60V
in High-Z State
................–0.3V to 3.9V (V
Electrical Characteristics
Over the Operating Range
45 ns (Ind’l/Auto-A)
Parameter
Description
Test Conditions
Unit
Min Typ
2.0
Max
V
V
V
V
I
Output HIGH Voltage
I
I
I
I
= –0.1 mA
V
V
OH
OL
IH
OH
OH
OL
OL
= –1.0 mA, V > 2.70V
2.4
CC
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
= 0.1 mA
0.4
0.4
V
= 2.1mA, V > 2.70V
V
CC
V
V
V
V
= 2.2V to 2.7V
= 2.7V to 3.6V
= 2.2V to 2.7V
= 2.7V to 3.6V
1.8
2.2
V
V
+ 0.3
V
CC
CC
CC
CC
CC
CC
+ 0.3
V
–0.3
–0.3
–1
0.6
V
IL
0.8
+1
+1
25
3
V
Input Leakage Current
Output Leakage Current
GND < V < V
CC
µA
µA
IX
I
I
GND < V < V , Output Disabled
–1
OZ
O
CC
I
V
OperatingSupplyCurrent f = f
= 1/t
V
= V
CCmax
18
CC
CC
max
RC
CC
I
= 0 mA
mA
OUT
f = 1 MHz
1.8
CMOS levels
I
Automatic CE Power Down
Current — CMOS Inputs
2
8
µA
CE > V − 0.2V, CE < 0.2V
SB1
1
CC
2
V
> V – 0.2V, V < 0.2V)
CC IN
IN
f = f
(Address and Data Only),
max
f = 0 (OE, BHE, BLE and WE), V = 3.60V
CC
I
Automatic CE Power Down
Current — CMOS Inputs
2
8
µA
CE > V – 0.2V or CE < 0.2V,
SB2
1
CC
2
V
> V – 0.2V or V < 0.2V, f = 0, V = 3.60V
IN
CC
IN
CC
Capacitance [10]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max
10
Unit
C
C
T = 25°C, f = 1 MHz,
pF
pF
IN
A
V
= V
CC
CC(typ)
10
OUT
Notes
6.
7.
V
= –2.0V for pulse durations less than 20 ns.
IL(min)
V
= V + 0.75V for pulse durations less than 20 ns.
IH(max)
CC
8. Full device AC operation assumes a 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.
cc
CC
9. Only chip enables (CE and CE ), byte enables (BHE and BLE) and BYTE (48 TSOP I only) need to be tied to CMOS levels to meet the I
/ I
spec. Other
1
2
SB2 CCDR
inputs can be left floating.
10. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05445 Rev. *E
Page 4 of 14
CY62157EV30 MoBL®
Thermal Resistance [10]
Parameter
Description
Test Conditions
BGA
TSOP I
TSOP II
Unit
Θ
Thermal Resistance Still Air, soldered on a 3 × 4.5 inch,
(Junction to Ambient) two-layer printed circuit board
72
74.88
76.88
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
8.86
8.6
13.52
°C/W
JC
AC Test Loads and Waveforms
Figure 1. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
V
V
CC
CC
90%
10%
90%
OUTPUT
10%
GND
Fall Time = 1 V/ns
Rise Time = 1 V/ns
R2
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
Parameters
2.5V
16667
15385
8000
1.20
3.0V
1103
1554
645
Unit
Ω
Ω
Ω
V
R1
R2
R
TH
TH
V
1.75
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min Typ
Max Unit
V
V
for Data Retention
1.5
V
DR
CC
V
= 1.5V, CE > V – 0.2V,
Ind’l/Auto-A
2
5
µA
I
Data Retention Current
CC
1
CC
CCDR
CE < 0.2V V > V – 0.2V or V < 0.2V
,
2
IN
CC
IN
t
t
Chip Deselect to Data
Retention Time
0
ns
ns
CDR
Operation Recovery Time
t
RC
R
Data Retention Waveform[12]
Figure 2. Data Retention Waveform
DATA RETENTION MODE
V
V
> 1.5V
V
CC(min)
CC(min)
VCC
DR
t
t
CDR
R
CE1 or
BHE.BLE
or
CE2
Notes
11. Full device operation requires linear V ramp from V to V
12. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
> 100 µs or stable at V
> 100 µs.
CC(min)
CC
DR
CC(min)
Document #: 38-05445 Rev. *E
Page 5 of 14
CY62157EV30 MoBL®
Switching Characteristics
Over the Operating Range
45 ns (Ind’l/Auto-A)
Unit
Parameter
Description
Min
Max
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
45
AA
Data Hold from Address Change
CE LOW and CE HIGH to Data Valid
10
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
45
22
1
2
OE LOW to Data Valid
OE LOW to LOW-Z
5
10
0
OE HIGH to High-Z
CE LOW and CE HIGH to Low-Z
18
18
1
2
CE HIGH and CE LOW to High-Z
1
2
CE LOW and CE HIGH to Power Up
1
2
CE HIGH and CE LOW to Power Down
45
45
PD
1
2
BLE/BHE LOW to Data Valid
DBE
LZBE
HZBE
BLE/BHE LOW to Low-Z
BLE/BHE HIGH to HIGH-Z
5
18
Write Cycle
t
Write Cycle Time
45
ns
WC
t
t
CE LOW and CE HIGH to Write End
35
35
ns
ns
SCE
1
2
Address Setup to Write End
AW
t
t
Address Hold from Write End
Address Setup to Write Start
0
0
ns
ns
HA
SA
t
t
t
t
WE Pulse Width
35
35
25
0
ns
ns
ns
ns
PWE
BW
SD
BLE/BHE LOW to Write End
Data Setup to Write End
Data Hold from Write End
HD
t
t
WE LOW to High-Z
18
ns
ns
HZWE
WE HIGH to Low-Z
10
LZWE
Notes
13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of V
/2, input pulse
CC(typ)
levels of 0 to V
CC(typ)
OL OH
14. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
15. At any temperature and voltage condition, t is less than t , t is less than t , t is less than t , and t is less than t for any device.
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
16. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
HZOE HZCE HZBE
HZWE
17. If both byte enables are toggled together, this value is 10 ns.
18. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V , and CE = V . All signals must be active to initiate a
IL
IL
2
IH
write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
Document #: 38-05445 Rev. *E
Page 6 of 14
CY62157EV30 MoBL®
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
Figure 3. Read Cycle No. 1
t
RC
ADDRESS
DATA OUT
t
AA
t
OHA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
Figure 4. Read Cycle No. 2
ADDRESS
tRC
CE1
CE2
tPD
t
HZCE
tACE
BHE/BLE
tDBE
tHZBE
tLZBE
OE
tHZOE
tDOE
tLZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
tLZCE
ICC
ISB
tPU
50%
50%
Notes
19. The device is continuously selected. OE, CE = V , BHE, BLE, or both = V , and CE = V .
IH
1
IL
IL
2
20. WE is HIGH for read cycle.
21. Address valid before or similar to CE , BHE, BLE transition LOW and CE transition HIGH.
1
2
Document #: 38-05445 Rev. *E
Page 7 of 14
CY62157EV30 MoBL®
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)
Figure 5. Write Cycle No. 1
tWC
ADDRESS
CE1
tSCE
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
NOTE 24
DATA IO
VALID DATA
tHZOE
Write Cycle No. 2 (CE or CE Controlled)
1
2
Figure 6. Write Cycle No. 1
tWC
ADDRESS
CE1
tSCE
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
DATA IO
VALID DATA
tHZOE
Notes
22. Data IO is high impedance if OE = V
.
IH
23. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
24. During this period, the IOs are in output state. Do not apply input signals.
Document #: 38-05445 Rev. *E
Page 8 of 14
CY62157EV30 MoBL®
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
Figure 7. Write Cycle No. 3
tWC
ADDRESS
CE1
tSCE
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
tHD
DATA IO
VALID DATA
tLZWE
t
HZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
Figure 8. Write Cycle No. 4
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
WE
tSA
tPWE
tSD
VALID DATA
tHD
NOTE 24
DATA IO
Document #: 38-05445 Rev. *E
Page 9 of 14
CY62157EV30 MoBL®
Truth Table
CE
H
X
CE
X
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High-Z
Mode
Deselect/Power Down
Deselect/Power Down
Deselect/Power Down
Read
Power
Standby (I
Standby (I
Standby (I
1
2
)
)
)
SB
SB
SB
L
X
X
X
X
High-Z
High-Z
X
X
X
X
H
H
L
H
H
H
L
L
L
Data Out (IO –IO
)
Active (I
Active (I
)
)
0
15
CC
CC
L
H
L
H
L
Data Out (IO –IO );
Read
0
7
High-Z (IO –IO
)
8
15
L
H
H
L
L
H
High-Z (IO –IO );
Read
Active (I
)
0
7
CC
Data Out (IO –IO
)
8
15
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High-Z
High-Z
High-Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (I
Active (I
Active (I
Active (I
Active (I
)
)
)
)
)
CC
CC
CC
CC
CC
L
Data In (IO –IO
)
15
0
L
H
Data In (IO –IO );
High-Z (IO –IO )
Write
0
7
8
15
L
H
L
X
L
H
High-Z (IO –IO );
Write
Active (I
)
0
7
CC
Data In (IO –IO )
8
15
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Package Type
Ordering Code
45
CY62157EV30LL-45BVI
CY62157EV30LL-45BVXI
CY62157EV30LL-45ZSXI
CY62157EV30LL-45ZXI
CY62157EV30LL-45BVXA
CY62157EV30LL-45ZSXA
51-85150 48-ball Very Fine Pitch Ball Grid Array
Industrial
51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
51-85087 44-pin Thin Small Outline Package Type II (Pb-free)
51-85183 48-pin Thin Small Outline Package Type I (Pb-free)
51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
51-85087 44-pin Thin Small Outline Package Type II (Pb-free)
45
Automotive-A
Contact your local Cypress sales representative for availability of these parts.
Document #: 38-05445 Rev. *E
Page 10 of 14
CY62157EV30 MoBL®
Package Diagrams
Figure 9. 48-Pin VFBGA (6 x 8 x 1 mm), 51-85150
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30 0.05(48X)
A1 CORNER
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15(4X)
SEATING PLANE
C
51-85150-*D
Document #: 38-05445 Rev. *E
Page 11 of 14
CY62157EV30 MoBL®
Package Diagrams (continued)
Figure 10. 44-Pin TSOP II, 51-85087
51-85087-*A
Document #: 38-05445 Rev. *E
Page 12 of 14
CY62157EV30 MoBL®
Package Diagrams (continued)
Figure 11. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183
DIMENSIONS IN INCHES[MM] MIN.
MAX.
JEDEC # MO-142
0.037[0.95]
0.041[1.05]
N
1
0.020[0.50]
TYP.
0.472[12.00]
0.007[0.17]
0.011[0.27]
0.002[0.05]
0.006[0.15]
0.724 [18.40]
0.787[20.00]
0.047[1.20]
MAX.
0.004[0.10]
0.008[0.21]
0.010[0.25]
GAUGE PLANE
51-85183-*A
0.020[0.50]
0.028[0.70]
0°-5°
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05445 Rev. *E
Page 13 of 14
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62157EV30 MoBL®
Document History Page
®
Document Title: CY62157EV30 MoBL , 8-Mbit (512K x 16) Static RAM
Document Number: 38-05445
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
202940
291272
See ECN
See ECN
AJU
New Data Sheet
*A
SYT
Converted from Advance Information to Preliminary
Removed 48-TSOP I Package and the associated footnote
Added footnote stating 44 TSOP II Package has only one CE on Page # 2
Changed V stabilization time in footnote #7 from 100 µs to 200 µs
CC
Changed I
Changed t
Changed t
Changed t
from 4 to 4.5 µA
CCDR
from 6 to 10 ns for both 35 and 45 ns Speed Bins
from 15 to 18 ns for 35 ns Speed Bin
OHA
DOE
, t
and t
from 12 and 15 ns to 15 and 18 ns for 35
HZOE HZBE
HZWE
and 45 ns Speed Bins respectively
Changed t from 12 and 15 ns to 18 and 22 ns for 35 and 45 ns Speed
HZCE
Bins respectively
Changed t , t and t
from 25 and 40 ns to 30 and 35 ns for 35 and 45 ns
BW
SCE AW
Speed Bins respectively
Changed t from 15 and 20 ns to 18 and 22 ns for 35 and 45 ns Speed Bins
SD
respectively
Added Lead-Free Package Information
*B
444306
See ECN
NXR
Converted from Preliminary to Final.
Changed ball E3 from DNU to NC
Removed redundant footnote on DNU.
Removed 35 ns speed bin
Removed “L” bin
Added 48 pin TSOP I package
Added Automotive product information.
Changed the I Typ value from 16 mA to 18 mA and I Max value from 28
CC
CC
mA to 25 mA for test condition f = fax = 1/t
RC.
Changed the I Max value from 2.3 mA to 3 mA for test condition f = 1MHz.
CC
Changed the I
and I
Max value from 4.5 µA to 8 µA and Typ value from
SB1
SB2
0.9 µA to 2 µA respectively.
Modified ISB test condition to include BHE, BLE
1
Updated Thermal Resistance table.
Changed Test Load Capacitance from 50 pF to 30 pF.
Added Typ value for I
CCDR .
Changed the I
Max value from 4.5 µA to 5 µA
CCDR
Corrected t in Data Retention Characteristics from 100 µs to t ns.
R
RC
Changed t
Changed t
Changed t
Changed t
Changed t
from 3 to 5
from 6 to 10
from 22 to 18
from 6 to 5
LZOE
LZCE
HZCE
LZBE
PWE
from 30 to 35
Changed t from 22 to 25
SD
Changed t
from 6 to 10
LZWE
Added footnote #15
Updated the ordering Information and replaced the Package Name column
with Package Diagram.
*C
*D
467052
925501
See ECN
See ECN
NXR
VKN
Modified Data sheet to include x8 configurability.
Updated the Ordering Information table
Removed Automotive-E information
Added Preliminary Automotive-A information
Added footnote #10 related to I
and I
SB2
CCDR
Added footnote #15 related AC timing parameters
*E
1045801
See ECN
VKN
Converted Automotive-A specs from preliminary to final
Updated footnote #9
Document #: 38-05445 Rev. *E
Page 14 of 14
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