CY8C24123A
CY8C24223A, CY8C24423A
®
PSoC Programmable System-on-Chip™
■ New CY8C24x23A PSoC Device
❐ Derived From the CY8C24x23 Device
❐ Low Power and Low Voltage (2.4V)
Features
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ 2.4 to 5.25V Operating Voltage
❐ Operating Voltages Down to 1.0V Using On-Chip Switch
Mode Pump (SMP)
■ Additional System Resources
2
❐ I C™ Slave, Master, and MultiMaster to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
❐ Industrial Temperature Range: -40°C to +85°C
■ Complete Development Tools
■ Advanced Peripherals (PSoC Blocks)
❐ Six Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
❐ Free Development Software (PSoC Designer™)
❐ Full-Featured, In-Circuit Emulator, and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Trace Memory
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
Logic Block Diagram
Analog
Port 2 Port 1 Port 0
Drivers
• Full-Duplex UART
PSoC CORE
• Multiple SPI™ Masters or Slaves
• Connectable to All GPIO Pins
❐ Complex Peripherals by Combining Blocks
System Bus
■ Precision, Programmable Clocking
Global Digital Interconnect
Global Analog Interconnect
❐ Internal ±2.5% 24/48 MHz Oscillator
SRAM
256 Bytes
SROM
Flash 4K
❐ High accuracy 24 MHz with optional 32 kHz Crystal and PLL
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
Controller
■ Flexible On-Chip Memory
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
❐ 4K Flash Program Storage 50,000 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref
Digital
Block
Array
Analog
Block
Array
Analog
Input
Muxing
■ Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
❐ Up to Ten Analog Inputs on GPIO
❐ Two 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on All GPIO
Internal
Voltage
Ref.
Switch
Mode
Pump
Digital
Clocks Accum.
Multiply
POR and LVD
System Resets
I2C
Decimator
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 38-12028 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 11, 2008
CY8C24123A
CY8C24223A, CY8C24423A
Figure 2. Analog System Block Diagram
Analog System
The Analog System consists of six configurable blocks, each
consisting of an opamp circuit that allows the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are:
P0[7]
P0[6]
P0[4]
P0[5]
P0[3]
P0[1]
P0[2]
P0[0]
■ Analog-to-digital converters (up to two, with 6 to 14-bit
resolution, selectable as Incremental, Delta Sigma, and SAR)
P2[6]
P2[4]
P2[3]
P2[1]
■ Filters (two and four pole band-pass, low-pass, and notch)
■ Amplifiers (up to two, with selectable gain to 48x)
■ Instrumentation amplifiers (one with selectable gain to 93x)
■ Comparators (up to two, with 16 selectable thresholds)
■ DACs (up to two, with 6 to 9-bit resolution)
P2[2]
P2[0]
Array Input Configuration
■ Multiplying DACs (up to two, with 6 to 9-bit resolution)
■ High current output drivers (two with 30 mA drive as a PSoC
ACI0[1:0]
ACI1[1:0]
Core resource)
■ 1.3V reference (as a System Resource)
■ DTMF Dialer
Block Array
ACB00
ASC10
ASD20
ACB01
■ Modulators
ASD11
ASC21
■ Correlators
■ Peak Detectors
■ Many other topologies possible
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
Analog Reference
Interface to
Digital System
Reference
Generators
RefHi
RefLo
AGND
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 38-12028 Rev. *I
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CY8C24123A
CY8C24223A, CY8C24423A
Additional System Resources
Getting Started
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a multiplier, decimator,
switch mode pump, low voltage detection, and power on reset.
Statements describing the merits of each system resource
follow:
The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in-depth information, along with
detailed programming information, refer the PSoC Program-
mable Sytem-on-Chip Technical Reference Manual.
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks may
be generated using digital PSoC blocks as clock dividers.
For up-to-date Ordering, Packaging, and Electrical Specification
information, refer the latest PSoC device data sheets on the web
■ A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math and
digital filters.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com, click the Online Store shopping cart
icon at the bottom of the web page, and click PSoC (Program-
mable System-on-Chip) to view a current list of available items.
■ The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■ TheI2Cmoduleprovides100and400kHzcommunicationover
two wires. Slave, master, and multi-master are supported.
■ Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltagelevels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
Technical Training
Free PSoC technical training is available for beginners and is
taught by a marketing or application engineer over the phone.
PSoC training classes cover designing, debugging, advanced
analog, and application-specific classes covering topics, such as
Design Support located on the left side of the web page, and
select Technical Training for more details.
■ An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■ An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
PSoC Device Characteristics
Consultants
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or
PSoC device groups. The PSoC device covered by this data
sheet is highlighted in this table.
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
Support located on the left side of the web page, and select
CYPros Consultants.
Table 1. PSoC Device Characteristics
Technical Support
PSoC application engineers take pride in fast and accurate
response. They can be reached with a 4-hour guaranteed
PSoC Part
Number
Application Notes
CY8C29x66
CY8C27x43
up to 4
64
16 12
4
4
4
4
12 2K
32K
16K
A long list of application notes can assist you in every aspect of
your design effort. To view the PSoC application notes, go to the
http://www.cypress.com web site and select Application Notes
under the Design Resources list located in the center of the web
page. Application notes are listed by date as default.
up to 2
44
8
12
12 256
Bytes
CY8C24x94
CY8C24x23
49
1
4
4
48
12
2
2
2
2
6
6
1K
16K
4K
up to 1
24
256
Bytes
CY8C24x23A up to 1
24
4
4
4
0
12
28
8
2
0
0
0
2
2
2
0
6
256
4K
8K
4K
8K
Bytes
CY8C21x34
CY8C21x23
CY8C20x34
up to
28
1
4a
4a
3b
512
Bytes
16
1
256
Bytes
up to 0
28
28
512
Bytes
a. Limited analog functionality.
b. Two analog blocks and one CapSense.
Document Number: 38-12028 Rev. *I
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CY8C24123A
CY8C24223A, CY8C24423A
PSoC Designer Software Subsystems
Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
Device Editor
development
environment
for
the
Programmable
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Windows 2000, Windows
PSoC Designer helps the customer to select an operating config-
uration for the PSoC, write application code that uses the PSoC,
and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
The device editor also supports the easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows changing configurations at run time.
PSoC Designer sets up power on initialization tables for selected
PSoC block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components and, if the project uses more
than one operating configuration, contains routines to switch
between different sets of PSoC block configurations at run time.
PSoC Designer can print out a configuration sheet for a given
project configuration for use during application programming, in
conjunction with the device data sheet. After the framework is
generated, the user can add application-specific code to flesh
out the framework. It is also possible to change the selected
components and regenerate the framework.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Figure 3. PSoC Designer Subsystems
Context
Graphical Designer
PSoC
Sensitive
Interface
Help
Designer
Design Browser
The Design Browser allows users to select and import
preconfigured designs into the user’s project. Users can easily
browse
a
catalog of preconfigured designs to facilitate
Importable
Design
Database
time-to-design. Examples provided in the tools include a
300-baud modem, LIN Bus master and slave, fan controller, and
magnetic card reader.
PSoC
Configuration
Sheet
Device
Database
Application Editor
PSoC
Designer
Core
In the Application Editor you can edit C language and Assembly
language source code. You can also assemble, compile, link,
and build.
Application
Database
Manufacturing
Information
File
Engine
Assembler. The macro assembler allows the seamless merging
of the assembly code with C code. The link libraries automatically
use absolute addressing or can be compiled in relative mode,
and linked with other software modules to get absolute
addressing.
Project
Database
User
Modules
C Language Compiler. A C language compiler is available that
supports PSoC family devices. Even if you have never worked in
the C language before, the product helps you to quickly create
complete C programs for the PSoC family devices.
Library
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Emulation
Pod
In-Circuit
Emulator
Device
Programmer
Document Number: 38-12028 Rev. *I
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CY8C24123A
CY8C24223A, CY8C24423A
Debugger
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides
high-level functions to control and respond to hardware events
at run-time. The API also provides optional interrupt service
routines that you can adapt as needed.
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear
breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. Pick the user modules you need for
your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, build signal chains by
interconnecting user modules to each other and the IO pins. At
this stage, you can also configure the clock source connections
and enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to developing code for the project,
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides high-level user
module API functions.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC
through the parallel or USB port. The base unit is universal and
operates with all PSoC devices. Emulation pods for each device
family are available separately. The emulation pod takes the
place of the PSoC device in the target board and performs full
speed (24 MHz) operation.
Figure 4. User Module and Source Code Development Flows
Device Editor
Placement
Designing with User Modules
User
Module
Selection
Source
Code
Generator
and
Parameter-
ization
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, can
implement a wide variety of user-selectable functions. Each
block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative development cycles permit you to adapt the
hardware and the software. This substantially lowers the risk of
having to select a different part to meet the final design
requirements.
Generate
Application
Application Editor
Source
Code
Editor
Project
Manager
Build
Manager
To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library
contains over 50 common peripherals such as ADCs, DACs
Timers, Counters, UARTs, and other uncommon peripherals,
such as DTMF Generators and Bi-Quad analog filter sections.
Build
All
Debugger
Event &
Breakpoint
Manager
Interface
to ICE
Storage
Inspector
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more digital PSoC blocks, one for each 8 bits
of resolution. The user module parameters permit you to
Document Number: 38-12028 Rev. *I
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CY8C24223A, CY8C24423A
The next step is to write your main program, and any sub-routine
using PSoC Designer’s Application Editor subsystem. The
Application Editor includes a Project Manager that allows you to
open the project source code files (including all generated code
files) from a hierarchal view. The source code editor provides
syntax coloring and advanced edit features for both C and
assembly language. File search capabilities include simple string
searches and recursive “grep-style” patterns. A single mouse
Table 2. Acronyms Used (continued)
Acronym Description
LSb least-significant bit
LVD
low voltage detect
MSb
most-significant bit
program counter
PC
click invokes the Build Manager. It employs
a
PLL
phase-locked loop
professional-strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in a
console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
POR
PPOR
PSoC®
PWM
SC
power on reset
precision power on reset
Programmable System-on-Chip™
pulse width modulator
switched capacitor
slow IMO
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
SLIMO
SMP
SRAM
switch mode pump
static random access memory
Units of Measure
A unit of measure table is located in the section
the abbreviations used to measure the PSoC devices.
Document Conventions
Numeric Naming
Acronyms Used
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
The following table lists the acronyms that are used in this
document.
Table 2. Acronyms Used
Acronym
AC
Description
alternating current
ADC
API
analog-to-digital converter
application programming interface
central processing unit
continuous time
CPU
CT
DAC
DC
digital-to-analog converter
direct current
ECO
EEPROM
external crystal oscillator
electrically erasable programmable read-only
memory
FSR
GPIO
GUI
HBM
ICE
full scale range
general purpose IO
graphical user interface
human body model
in-circuit emulator
ILO
internal low speed oscillator
internal main oscillator
input/output
IMO
IO
IPOR
imprecise power on reset
Document Number: 38-12028 Rev. *I
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CY8C24123A
CY8C24223A, CY8C24423A
Pinouts
This section describes, lists, and illustrates the CY8C24x23A PSoC device pins and pinout configurations. Every port pin (labeled
with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
8-Pin Part Pinoutt
Table 3. Pin Definitions - 8-Pin PDIP and SOIC
Type
Figure 5. CY8C24123A 8-Pin PSoC Device
Pin
No.
Pin
Name
Description
Digital Analog
A, IO,P0[5]
A,IO, P0[3]
I2CSCL,XTALin,P1[1]
Vss
1
2
3
4
8
7
6
5
Vdd
P0[4], A,I
P0[2], A,I
1
IO
IO
IO
IO
P0[5] Analog Column Mux Input and
Column Output
PDIP
SOIC
2
3
IO
P0[3] Analog Column Mux Input and
Column Output
P1[0],XTALout,I2CSDA
P1[1] Crystal Input (XTALin), I2C Serial
Clock (SCL), ISSP-SCLK*
4
5
Power
IO
Vss
Ground Connection
P1[0] CrystalOutput(XTALout), I2CSerial
Data (SDA), ISSP-SDATA*
6
7
8
IO
I
I
P0[2] Analog Column Mux Input
P0[4] Analog Column Mux Input
IO
Power
Vdd
Supply Voltage
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details.
Document Number: 38-12028 Rev. *I
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CY8C24123A
CY8C24223A, CY8C24423A
20-Pin Part Pinout
Table 4. Pin Definitions - 20-Pin PDIP, SSOP, and SOIC
Type
Figure 6. CY8C24223A 20-Pin PSoC Device
Pin
No.
Pin
Description
Name
Digital Analog
A, I,P0[7]
A,IO, P0[5]
A,IO, P0[3]
A,I, P0[1]
Vdd
1
2
3
20
19
18
17
16
15
14
13
12
11
1
IO
IO
I
P0[7] Analog Column Mux Input
P0[6], A,I
2
IO
P0[5] Analog Column Mux Input and Column
Output
P0[4], A,I
P0[2], A,I
4
PDIP
SSOP
SOIC
SMP
P0[0], A,I
5
3
IO
IO
I
P0[3] Analog Column Mux Input and Column
Output
I2CSCL,P1[7]
I2C SDA,P1[5]
P1[3]
XRES
P1[6]
6
7
8
9
4
5
IO
P0[1] Analog Column Mux Input
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
Power
SMP Switch Mode Pump (SMP) Connection to
External Components required
I2CSCL,XTALin,P1[1]
Vss
10
6
7
8
9
IO
IO
IO
IO
P1[7] I2C Serial Clock (SCL)
P1[5] I2C Serial Data (SDA)
P1[3]
P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*
10 Power
11 IO
Vss
Ground Connection.
P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*
12 IO
13 IO
14 IO
15 Input
P1[2]
P1[4] Optional External Clock Input (EXTCLK)
P1[6]
XRES Active High External Reset with Internal
Pull Down
16 IO
17 IO
18 IO
19 IO
20 Power
I
I
I
I
P0[0] Analog Column Mux Input
P0[2] Analog Column Mux Input
P0[4] Analog Column Mux Input
P0[6] Analog Column Mux Input
Vdd
Supply Voltage
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details.
Document Number: 38-12028 Rev. *I
Page 9 of 56
CY8C24123A
CY8C24223A, CY8C24423A
28-Pin Part Pinout
Table 5. Pin Definitions - 28-Pin PDIP, SSOP, and SOIC
Type
Figure 7. CY8C24423A 28-Pin PSoC Device
Pin
No.
Pin
Name
Description
Digital Analog
A, I,P0[7]
A,IO, P0[5]
A,IO, P0[3]
A,I, P0[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Vdd
P0[6], A, I
P0[4], A, I
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
IO
IO
I
P0[7] Analog Column Mux Input
2
IO
P0[5] Analog Column Mux Input and column
output
P0[2], A, I
P0[0], A, I
P2[6],Ex ternalVRef
P2[4],Ex ternalAGND
P2[2], A, I
3
IO
IO
I
P0[3] Analog Column Mux Input and Column
Output
P2[7]
P2[5]
PDIP
SSOP
SOIC
A,I, P2[3]
A, I,P2[1]
4
5
6
7
8
9
IO
P0[1] Analog Column Mux Input
IO
P2[7]
SMP
P2[0], A, I
XRES
P1[6]
IO
P2[5]
I2CSCL,P1[7]
I2CSDA,P1[5]
P1[3]
IO
I
I
P2[3] Direct Switched Capacitor Block Input
P2[1] Direct Switched Capacitor Block Input
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
IO
I2CSCL,XTALin,P1[1]
Vss
Power
SMP Switch Mode Pump (SMP) Connection to
External Components required
10
11
12
13
IO
IO
IO
IO
P1[7] I2C Serial Clock (SCL)
P1[5] I2C Serial Data (SDA)
P1[3]
P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*
14
15
Power
IO
Vss
Ground connection.
P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*
16
17
18
19
IO
P1[2]
IO
P1[4] Optional External Clock Input (EXTCLK)
P1[6]
IO
Input
XRES Active High External Reset with Internal
Pull Down
20
21
22
23
24
25
26
27
28
IO
I
I
P2[0] Direct Switched Capacitor Block Input
P2[2] Direct Switched Capacitor Block Input
P2[4] External Analog Ground (AGND)
P2[6] External Voltage Reference (VRef)
P0[0] Analog Column Mux Input
IO
IO
IO
IO
I
I
I
I
IO
P0[2] Analog Column Mux Input
IO
P0[4] Analog Column Mux Input
IO
P0[6] Analog Column Mux Input
Power
Vdd
Supply Voltage
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Pro-
grammable Sytem-on-Chip Technical Reference Manual for details.
Document Number: 38-12028 Rev. *I
Page 10 of 56
CY8C24123A
CY8C24223A, CY8C24423A
32-Pin Part Pinout
Table 6. Pin Definitions - 32-Pin QFN**
Type
Figure 8. CY8C24423A 32-Pin PSoC Device
Pin
No.
Pin
Name
Description
Digital Analog
1
2
3
4
5
6
IO
P2[7]
P2[5]
IO
IO
I
I
P2[3] Direct Switched Capacitor Block Input
P2[1] Direct Switched Capacitor Block Input
P2[7]
P2[5]
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
P0[2], A,I
P0[0], A,I
IO
A, I,P2[3]
A, I,P2[1]
Vss
P2[6],ExternalVRef
P2[4],ExternalAGND
P2[2], A,I
P2[0], A,I
XRES
Power
Power
Vss
Ground Connection
QFN
(Top View)
SMP Switch Mode Pump (SMP) Connection
to External Components required
SMP
I2CSCL,P1[7]
I2CSDA,P1[5]
7
8
9
IO
IO
P1[7] I2C Serial Clock (SCL).
P1[5] I2C Serial Data (SDA).
P1[6]
NC
No Connection
10
11
IO
IO
P1[3]
P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*
12
13
Power
IO
Vss
Ground Connection
P1[0] Crystal Output (XTALout), I2C Serial
Data (SDA), ISSP-SDATA*
14
15
IO
IO
P1[2]
Figure 9. CY8C24423A 32-Pin Sawn PSoC Device
P1[4] Optional External Clock Input
(EXTCLK)
16
17
18
NC
No Connection
IO
P1[6]
Input
XRES Active High External Reset with Internal
Pull Down
P2[7]
P2[5]
1
2
3
4
5
6
7
8
P0[2], A, I
24
19
20
21
22
23
24
25
26
27
28
29
30
IO
IO
IO
IO
IO
IO
I
I
P2[0] Direct Switched Capacitor Block Input
P2[2] Direct Switched Capacitor Block Input
P2[4] External Analog Ground (AGND)
P2[6] External Voltage Reference (VRef)
P0[0] Analog Column Mux Input
23 P0[0], A, I
A, I, P2[3]
A, I, P2[1]
Vss
22 P2[6], ExternalVRef
P2[4], ExternalA GND
21
20 P2[2], A, I
QFN
(Top View)
SMP
P2[0], A, I
19
12 CS CL, P1[7]
12 CS DA, P1[5]
18 XRES
17 P1[6]
I
I
P0[2] Analog Column Mux Input
NC
No Connection
IO
I
I
P0[4] Analog Column Mux Input
P0[6] Analog Column Mux Input
IO
Power
IO
Vdd
Supply Voltage
I
P0[7] Analog Column Mux Input
IO
IO
P0[5] Analog Column Mux Input and Column
Output
31
IO
IO
P0[3] Analog Column Mux Input and Column
Output
32
IO
I
P0[1] Analog Column Mux Input
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details.
** The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it must
be electrically floated and not connected to any other signal.
Document Number: 38-12028 Rev. *I
Page 11 of 56
CY8C24123A
CY8C24223A, CY8C24423A
56-Pin Part Pinout
The 56-pin SSOP part is for the CY8C24000A On-Chip Debug (OCD) PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Table 7. Pin Definitions - 56-Pin SSOP
Type
Pin
No.
Pin
Description
No Connection
Name
Digital Analog
1
2
3
NC
Figure 10. CY8C24000A 56-Pin PSoC Device
IO
IO
I
I
P0[7] Analog Column Mux Input
NC
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[7]
56
55
54
53
1
2
3
4
5
6
Vdd
P0[5] Analog Column Mux Input and
Column Output
P0[6], AI
P0[4], AIO
P0[2], AIO
P0[0], AI
4
IO
I
I
P0[3] Analog Column Mux Input and
Column Output
52
51
P2[6], External VRef
P2[4], External AGND
P2[2], AI
P2[0], AI
P4[6]
P2[5]
AI, P2[3]
AI, P2[1]
P4[7]
7
8
9
50
49
48
5
6
7
8
IO
IO
IO
IO
P0[1] Analog Column Mux Input
P2[7]
P2[5]
10
47
46
45
44
43
42
41
40
39
38
37
36
35
34
P4[5]
P4[3]
P4[4]
11
12
13
P4[2]
P4[0]
I
I
P2[3] Direct Switched Capacitor Block
Input
P4[1]
OCDE
OCDO
SMP
14
CCLK
HCLK
XRES
P3[6]
SSOP
15
16
9
IO
P2[1] Direct sWitched Capacitor Block
Input
P3[7]
17
P3[5]
P3[3]
P3[4]
P3[2]
P3[0]
P5[2]
18
19
20
10
11
12
13
14
IO
P4[7]
P4[5]
P4[3]
P4[1]
P3[1]
P5[3]
IO
21
22
23
P5[1]
P5[0]
P1[6]
IO
I
I
I2C SCL, P1[7]
I2C SDA, P1[5]
NC
P1[4], EXTCLK
24
25
33
32
IO
P1[2]
P1[3]
SCLK, I2C SCL, XTALIn, P1[1]
Vss
26
27
28
31
30
P1[0], XTALOut, I2C SDA, SDATA
NC
NC
OCD
OCD OCD Even Data IO.
E
29
15
16
OCD
OCD OCD Odd Data Output
O
Power
SMP Switch Mode Pump (SMP)
Connection to required External
Components
Not for Production
17
18
19
20
21
22
23
24
25
26
27
IO
IO
IO
IO
IO
IO
IO
IO
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
P1[7] I2C Serial Clock (SCL)
P1[5] I2C Serial Data (SDA)
NC
No Connection
IO
IO
P1[3]
P1[1] Crystal Input (XTALin), I2C Serial
Clock (SCL), ISSP-SCLK*
28
29
30
31
Power
Vdd
NC
NC
Supply Voltage
No Connection
No Connection
IO
P1[0] Crystal Output (XTALout), I2C
Serial Data (SDA), ISSP-SDATA*
32
33
IO
IO
P1[2]
P1[4] Optional External Clock Input
(EXTCLK)
Document Number: 38-12028 Rev. *I
Page 12 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Table 7. Pin Definitions - 56-Pin SSOP (continued)
Type
Pin
No.
Pin
Name
Description
Digital Analog
34
IO
P1[6]
P5[0]
P5[2]
P3[0]
P3[2]
P3[4]
P3[6]
35
36
37
38
39
40
41
IO
IO
IO
IO
IO
IO
Input
XRES Active high external reset with
internal pull down.
42
43
44
45
46
47
48
OCD
OCD
IO
HCLK OCD high-speed clock output.
CCLK OCD CPU clock output.
P4[0]
P4[2]
P4[4]
P4[6]
IO
IO
IO
IO
I
I
P2[0] Direct switched capacitor block
input.
49
IO
P2[2] Direct switched capacitor block
input.
50
51
IO
IO
P2[4] External Analog Ground (AGND).
P2[6] External Voltage Reference
(VRef).
52
53
IO
IO
I
I
P0[0] Analog column mux input.
P0[2] Analog column mux input and
column output.
54
IO
I
I
P0[4] Analog column mux input and
column output.
55
56
IO
P0[6] Analog column mux input.
Power
Vdd
Supply voltage.
LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable Sytem-on-Chip Technical Reference Manual for details.
Document Number: 38-12028 Rev. *I
Page 13 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Register Mapping Tables
Register Reference
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
This section lists the registers of the CY8C24x23A PSoC device.
For detailed register information, refer the PSoC Programmable
Sytem-on-Chip Reference Manual.
Register Conventions
Note In the following register mapping tables, blank fields are
reserved and must not be accessed.
Abbreviations Used
The register conventions specific to this section are listed in the
following table.
Table 8. Abbreviations
Convention
Description
Read register or bit(s)
R
W
L
Write register or bit(s)
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
C
#
Document Number: 38-12028 Rev. *I
Page 14 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Table 9. Register Map Bank 0 Table: User Space
Addr
(0,Hex)
00
Addr
Addr
(0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
Addr
(0,Hex)
C0
Name
Access Name
Access Name
ASC10CR0
Access Name
Access
(0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
RW
RW
RW
RW
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
RW
RW
I2C_CFG
I2C_SCR
I2C_DR
RW
#
RW
#
RW
RW
99
I2C_MSCR
INT_CLR0
INT_CLR1
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
INT_CLR3
INT_MSK3
RW
RW
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
#
AMX_IN
RW
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL_X
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
W
RW
#
ARF_CR
CMP_CR0
ASY_CR
CMP_CR1
RW
#
#
#
W
RW
#
RW
#
W
RW
#
MUL_Y
MUL_DH
MUL_DL
ACC_DR1
ACC_DR0
ACC_DR3
ACC_DR2
#
W
RW
#
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RW
RW
RW
RW
RW
RW
RW
CPU_F
RL
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 38-12028 Rev. *I
Page 15 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Table 9. Register Map Bank 0 Table: User Space (continued)
Addr
(0,Hex)
3E
Addr
(0,Hex)
7E
Addr
(0,Hex)
BE
BF
Addr
(0,Hex)
FE
Name
Access Name
Access Name
Access Name
CPU_SCR1
CPU_SCR0
Access
#
#
3F
7F
FF
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Table 10. Register Map Bank 1 Table: Configuration Space
Addr
(1,Hex)
00
Addr
(1,Hex)
40
Addr
(1,Hex)
80
Addr
(1,Hex)
C0
Name
Access Name
Access Name
ASC10CR0
Access Name
Access
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
RW
RW
RW
RW
RW
RW
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
RW
RW
RW
RW
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
RW
RW
RW
RW
RW
RW
RW
R
DBB00FN
DBB00IN
DBB00OU
RW
RW
RW
CLK_CR0
RW
RW
RW
RW
CLK_CR1
ABF_CR0
AMD_CR0
DBB01FN
DBB01IN
DBB01OU
RW
RW
RW
VLT_CMP
AMD_CR1
ALT_CR0
RW
RW
DCB02FN
DCB02IN
DCB02OU
RW
RW
RW
IMO_TR
ILO_TR
BDG_TR
ECO_TR
W
W
RW
W
DCB03FN
DCB03IN
DCB03OU
RW
RW
RW
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RW
RW
RW
RW
RW
RW
RW
F1
F2
F3
F4
F5
F6
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 38-12028 Rev. *I
Page 16 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Table 10. Register Map Bank 1 Table: Configuration Space (continued)
Addr
(1,Hex)
37
Addr
(1,Hex)
77
Addr
(1,Hex)
B7
Addr
(1,Hex)
F7
Name
Access Name
ACB01CR2
Access Name
Access Name
Access
RW
CPU_F
RL
38
39
3A
3B
3C
3D
3E
3F
78
79
7A
7B
7C
7D
7E
7F
B8
B9
BA
BB
BC
BD
BE
F8
F9
FA
FB
FC
FD
FE
FF
CPU_SCR1
CPU_SCR0
#
#
BF
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 38-12028 Rev. *I
Page 17 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C24x23A PSoC device. For the latest electrical specifications,
Specifications are valid for -40°C ≤ T ≤ 85°C and T ≤ 100°C, except where noted.
A
J
Refer to Table 31 on page 32 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
Figure 11. Voltage versus CPU Frequency
Figure 12. IMO Frequency Trim Options
5.25
4.75
5.25
4.75
SLIMO
Mode=1
SLIMO
Mode=0
3.60
3.00
2.40
SLIMO
Mode=1
SLIMO
Mode=0
3.00
2.40
SLIMO SLIMO
Mode=1 Mode=1
93 kHz
12 MHz
24 MHz
3 MHz
CPUFrequency
93 kHz
6 MHz
12 MHz
24 MHz
IMOFrequency
The following table lists the units of measure that are used in this section.
Table 11. Units of Measure
Symbol
Unit of Measure
degree Celsius
Symbol
Unit of Measure
°C
μW
mA
ms
mV
nA
ns
microwatts
dB
fF
decibels
milli-ampere
milli-second
milli-volts
femto farad
hertz
Hz
KB
Kbit
kHz
kΩ
MHz
MΩ
μA
μF
1024 bytes
1024 bits
nanoampere
nanosecond
nanovolts
kilohertz
nV
W
kilohm
ohm
megahertz
megaohm
pA
pF
pp
ppm
ps
picoampere
picofarad
microampere
microfarad
microhenry
microsecond
microvolts
peak-to-peak
parts per million
picosecond
μH
μs
μV
sps
s
samples per second
sigma: one standard deviation
volts
μVrms
microvolts root-mean-square
V
Document Number: 38-12028 Rev. *I
Page 18 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 12. Absolute Maximum Ratings
Symbol
Description
Storage Temperature
Min
Typ
Max
Units
Notes
T
-55
25
+100
°C Higher storage temperatures
reduce data retention time.
Recommended storage
STG
temperature is +25°C ± 25°C.
Extended duration storage
temperatures above 65°C
degrades reliability.
T
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
-40
-0.5
–
–
–
+85
°C
V
A
Vdd
+6.0
V
Vss - 0.5
Vdd +
0.5
V
IO
V
DC Voltage Applied to Tri-state
Vss - 0.5
–
Vdd +
0.5
V
IOZ
I
Maximum Current into any Port Pin
Electro Static Discharge Voltage
Latch-up Current
-25
2000
–
–
–
–
+50
–
mA
MIO
ESD
LU
V
Human Body Model ESD.
200
mA
Operating Temperature
Table 13. Operating Temperature
Symbol
Description
Min
-40
-40
Typ
–
Max
+85
Units
Notes
T
Ambient Temperature
Junction Temperature
°C
A
T
–
+100
°C The temperature rise from ambient
to junction is package specific. See
limit the power consumption to
J
comply with this requirement.
Document Number: 38-12028 Rev. *I
Page 19 of 56
CY8C24123A
CY8C24223A, CY8C24423A
DC Electrical Characteristics
DC Chip-Level Specifications
Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 14. DC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd
Supply Voltage
Supply Current
2.4
–
5.25
V
See DC POR and LVD specifications,
I
I
I
–
–
–
5
3.3
2
8
6.0
4
mA Conditions are Vdd = 5.0V, T = 25°C,
DD
A
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75 kHz,
analog power = off.
SLIMO mode = 0. IMO = 24 MHz.
Supply Current
Supply Current
mA Conditions are Vdd = 3.3V, T = 25 °C,
DD3
DD27
A
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75 kHz,
analog power = off. SLIMO mode = 0.
IMO = 24 MHz.
mA Conditions are Vdd = 2.7V, T = 25°C,
A
CPU = 0.75 MHz, SYSCLK doubler
disabled, VC1 = 0.375 MHz,
VC2 = 23.44 kHz, VC3 = 0.09 kHz,
analog power = off. SLIMO mode = 1.
IMO = 6 MHz.
I
I
I
Sleep (Mode) Current with POR, LVD, Sleep
Timer, and WDT.
–
–
–
3
4
4
6.5
25
μA Conditions are with internal slow
SB
a
speed oscillator, Vdd = 3.3V, -40°C ≤
T ≤ 55°C, analog power = off.
A
Sleep (Mode) Current with POR, LVD, Sleep
μA Conditions are with internal slow
SBH
SBXTL
a
Timer, and WDT at high temperature.
speedoscillator, Vdd=3.3V, 55°C<T
A
≤ 85°C, analog power = off.
Sleep (Mode) Current with POR, LVD, Sleep
7.5
μA Conditions are with properly loaded,
a
Timer, WDT, and external crystal.
1 μW max, 32.768 kHz crystal.
Vdd = 3.3V, -40°C ≤ T ≤ 55°C, analog
A
power = off.
I
Sleep (Mode) Current with POR, LVD, Sleep
Timer, WDT, and external crystal at high
temperature.
–
5
26
μA Conditions are with properly loaded,
SBXTLH
1μW max, 32.768 kHz crystal.
a
Vdd = 3.3 V, 55°C < T ≤ 85°C, analog
A
power = off.
V
V
Reference Voltage (Bandgap)
Reference Voltage (Bandgap)
1.28
1.16
1.30
1.30
1.33
1.33
V
V
Trimmed for appropriate Vdd.
Vdd > 3.0V
REF
Trimmed for appropriate Vdd.
Vdd = 2.4V to 3.0V
REF27
a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar
functions enabled.
Document Number: 38-12028 Rev. *I
Page 20 of 56
CY8C24123A
CY8C24223A, CY8C24423A
DC General Purpose IO Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 15. 5V and 3.3V DC GPIO Specifications
Symbol
Description
Min
Typ
5.6
5.6
–
Max
Units
kΩ
kΩ
Notes
R
Pull up Resistor
4
4
8
8
–
PU
R
Pull down Resistor
High Output Level
PD
V
Vdd - 1.0
V
IOH = 10 mA, Vdd = 4.75 to 5.25V
(maximum 40 mA on even port pins
(for example, P0[2], P1[4]),
OH
maximum 40 mA on odd port pins
(for example, P0[3], P1[5])). 80 mA
maximum combined IOH budget.
V
Low Output Level
–
–
0.75
V
IOL = 25 mA, Vdd = 4.75 to 5.25V
(maximum 100 mA on even port
pins (for example, P0[2], P1[4]),
maximum 100 mA on odd port pins
(for example, P0[3], P1[5])). 150
mA maximum combined IOL
budget.
OL
V
V
V
I
Input Low Level
–
2.1
–
–
–
0.8
V
V
Vdd = 3.0 to 5.25
Vdd = 3.0 to 5.25
IL
IH
H
Input High Level
Input Hysterisis
60
1
–
–
mV
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
nA Gross tested to 1 μA
pF Package and pin dependent.
Temp = 25°C
IL
C
–
3.5
10
IN
C
Capacitive Load on Pins as Output
–
3.5
10
pF Package and pin dependent.
Temp = 25°C
OUT
Table 16. 2.7V DC GPIO Specifications
Symbol
Description
Min
Typ
5.6
5.6
–
Max
Units
Notes
R
Pull up Resistor
4
4
8
8
–
kΩ
kΩ
V
PU
R
Pull down Resistor
High Output Level
PD
V
Vdd - 0.4
IOH = 2 mA (6.25 Typ), Vdd = 2.4
to 3.0V (16 mA maximum, 50 mA
Typ combined IOH budget).
OH
V
Low Output Level
–
–
0.75
V
IOL = 11.25 mA, Vdd = 2.4 to 3.0V
(90 mA maximum combined IOL
budget).
OL
V
V
V
I
Input Low Level
–
2.0
–
–
–
0.75
–
V
V
Vdd = 2.4 to 3.0
Vdd = 2.4 to 3.0
IL
IH
H
Input High Level
Input Hysteresis
90
1
–
mV
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
–
–
nA Gross tested to 1 μA
pF Package and pin dependent.
IL
C
–
3.5
10
IN
o
Temp = 25 C
C
Capacitive Load on Pins as Output
–
3.5
10
pF Package and pin dependent.
OUT
o
Temp = 25 C
Document Number: 38-12028 Rev. *I
Page 21 of 56
CY8C24123A
CY8C24223A, CY8C24423A
DC Operational Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at
25°C and are for design guidance only.
Table 17. 5V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
V
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
OSOA
–
–
–
–
–
–
1.6
1.3
1.2
10
8
7.5
mV
mV
mV
TCV
Average Input Offset Voltage Drift
7.0
20
35.0
–
μV/°C
OSOA
I
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
pA Gross tested to 1 μA
pF Package and pin dependent.
Temp = 25°C
EBOA
C
4.5
9.5
INOA
V
Common Mode Voltage Range
Common Mode Voltage Range (high power or
high opamp bias)
0.0
0.5
–
–
Vdd
Vdd - 0.5
V
The common-mode input voltage
range is measured through an
analog output buffer. The
specification includes the
limitations imposed by the
characteristics of the analog
output buffer.
CMOA
G
Open Loop Gain
–
–
dB Specification is applicable at high
power. For all other bias modes
(except high power, high opamp
bias), minimum is 60 dB.
OLOA
OHIGHOA
OLOWOA
SOA
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
60
60
80
V
V
High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Vdd - 0.2
Vdd - 0.2
Vdd - 0.5
–
–
–
–
–
–
V
V
V
Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
Power = High, Opamp Bias = High
I
Supply Current (including associated AGND
buffer)
Power = Low, Opamp Bias = High
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
μA
μA
μA
μA
μA
μA
PSRR
Supply Voltage Rejection Ratio
64
80
–
dB Vss ≤ VIN ≤ (Vdd - 2.25) or
OA
(Vdd - 1.25V) ≤ VIN ≤ Vdd
Document Number: 38-12028 Rev. *I
Page 22 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Table 18. 3.3V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
V
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5 Volts Only
OSOA
–
–
1.65
1.32
10
8
mV
mV
TCV
Average Input Offset Voltage Drift
–
–
–
7.0
20
35.0
–
μV/°C
OSOA
I
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
pA Gross tested to 1 μA
EBOA
C
4.5
9.5
pF Package and pin dependent.
Temp = 25°C
INOA
V
Common Mode Voltage Range
0.2
–
Vdd - 0.2
V
The common-mode input voltage
range is measured through an
analog output buffer. The
specification includes the
limitations imposed by the
characteristics of the analog
output buffer.
CMOA
G
Open Loop Gain
–
–
dB Specification is applicable at high
power. For all other bias modes
(except high power, high opamp
bias), minimum is 60 dB.
OLOA
OHIGHOA
OLOWOA
SOA
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High, Opamp Bias = Low
60
60
80
V
V
High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High is 5V only
Vdd - 0.2
Vdd - 0.2
Vdd - 0.2
–
–
–
–
–
–
V
V
V
Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
Power = High, Opamp Bias = Low
I
Supply Current (including associated AGND
buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
μA
μA
μA
μA
μA
μA
PSRR
Supply Voltage Rejection Ratio
64
80
–
dB Vss ≤ VIN ≤ (Vdd - 2.25) or
OA
(Vdd - 1.25V) ≤ VIN ≤ Vdd
Document Number: 38-12028 Rev. *I
Page 23 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Table 19. 2.7V DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
V
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5 Volts Only
OSOA
–
–
1.65
1.32
10
8
mV
mV
TCV
Average Input Offset Voltage Drift
–
–
–
7.0
20
35.0
–
μV/°C
OSOA
I
Input Leakage Current (Port 0 Analog Pins)
Input Capacitance (Port 0 Analog Pins)
pA Gross tested to 1 μA
EBOA
C
4.5
9.5
pF Package and pin dependent.
Temp = 25°C
INOA
V
Common Mode Voltage Range
0.2
–
Vdd - 0.2
V
The common-mode input voltage
range is measured through an
analog output buffer. The
specification includes the
limitations imposed by the
characteristics of the analog output
buffer.
CMOA
G
Open Loop Gain
–
–
dB Specification is applicable at high
power. For all other bias modes
(except high power, high opamp
bias), minimum is 60 dB.
OLOA
OHIGHOA
OLOWOA
SOA
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High
60
60
80
V
V
High Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
Power = High is 5V only
Vdd - 0.2
Vdd - 0.2
Vdd - 0.2
–
–
–
–
–
–
V
V
V
Low Output Voltage Swing (internal signals)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = Low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
Power = High, Opamp Bias = Low
I
Supply Current (including associated AGND
buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
–
150
300
600
1200
2400
4600
200
400
800
1600
3200
6400
μA
μA
μA
μA
μA
μA
PSRR
Supply Voltage Rejection Ratio
64
80
–
dB Vss ≤ VIN ≤ (Vdd - 2.25) or
OA
(Vdd - 1.25V) ≤ VIN ≤ Vdd
DC Low Power Comparator Specifications
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V at 25°C and are for design guidance only.
Table 20. DC Low Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
V
Low power comparator (LPC) reference
voltage range
0.2
–
Vdd - 1
V
REFLPC
I
LPC supply current
LPC voltage offset
–
–
10
40
30
μA
mV
SLPC
V
2.5
OSLPC
Document Number: 38-12028 Rev. *I
Page 24 of 56
CY8C24123A
CY8C24223A, CY8C24423A
DC Analog Output Buffer Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 21. 5V DC Analog Output Buffer Specifications
Symbol
Description
Min
–
Typ
3
Max
12
Units
mV
Notes
V
Input Offset Voltage (Absolute Value)
Average Input Offset Voltage Drift
Common-Mode Input Voltage Range
OSOB
TCV
–
+6
–
–
μV/°C
V
OSOB
CMOB
V
0.5
Vdd - 1.0
R
Output Resistance
Power = Low
Power = High
OUTOB
–
–
1
1
–
–
W
W
V
V
High Output Voltage Swing (Load = 32 ohms
to Vdd/2)
Power = Low
Power = High
OHIGHOB
OLOWOB
SOB
0.5 x Vdd + 1.1
0.5 x Vdd + 1.1
–
–
–
–
V
V
Low Output Voltage Swing (Load = 32 ohms
to Vdd/2)
Power = Low
Power = High
–
–
–
–
.5 x Vdd - 1.3
0.5 x Vdd - 1.3
V
V
I
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
–
–
1.1
2.6
5.1
8.8
mA
mA
PSRR
Supply Voltage Rejection Ratio
52
64
–
dB
V
> (Vdd - 1.25).
OB
OUT
Table 22. 3.3V DC Analog Output Buffer Specifications
Symbol
Description
Min
–
Typ
3
Max
12
Units
mV
Notes
V
Input Offset Voltage (Absolute Value)
Average Input Offset Voltage Drift
Common-Mode Input Voltage Range
OSOB
TCV
–
+6
-
–
μV/°C
V
OSOB
V
0.5
Vdd - 1.0
CMOB
R
Output Resistance
Power = Low
Power = High
OUTOB
–
–
1
1
–
–
W
W
V
High Output Voltage Swing (Load = 1k ohms
to Vdd/2)
Power = Low
Power = High
OHIGHOB
OLOWOB
SOB
0.5 x Vdd + 1.0
0.5 x Vdd + 1.0
–
–
–
–
V
V
V
Low Output Voltage Swing (Load = 1k ohms
to Vdd/2)
Power = Low
Power = High
–
–
–
–
0.5 x Vdd - 1.0
0.5 x Vdd - 1.0
V
V
I
Supply Current Including Bias Cell (No Load)
Power = Low
0.8
2.0
2.0
4.3
mA
mA
Power = High
–
PSRR
Supply Voltage Rejection Ratio
52
64
–
dB
V
> (Vdd - 1.25)
OB
OUT
Document Number: 38-12028 Rev. *I
Page 25 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Table 23. 2.7V DC Analog Output Buffer Specifications
Symbol
Description
Min
–
Typ
3
Max
12
Units
mV
Notes
V
Input Offset Voltage (Absolute Value)
Average Input Offset Voltage Drift
Common-Mode Input Voltage Range
OSOB
TCV
–
+6
-
–
μV/°C
V
OSOB
CMOB
V
0.5
Vdd - 1.0
R
Output Resistance
Power = Low
Power = High
OUTOB
–
–
1
1
–
–
W
W
V
V
High Output Voltage Swing (Load = 1k ohms
to Vdd/2)
Power = Low
Power = High
OHIGHOB
OLOWOB
SOB
V
V
0.5 x Vdd + 0.2
0.5 x Vdd + 0.2
–
–
–
–
Low Output Voltage Swing (Load = 1k ohms
to Vdd/2)
Power = Low
Power = High
V
V
–
–
–
–
0.5 x Vdd - 0.7
0.5 x Vdd - 0.7
I
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
0.8
2.0
2.0
4.3
mA
mA
–
PSRR
Supply Voltage Rejection Ratio
52
64
–
dB
V
> (Vdd - 1.25).
OB
OUT
DC Switch Mode Pump Specifications
Table 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 24. DC Switch Mode Pump (SMP) Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
a
V
V
V
5V
3V
2V
5V Output Voltage from Pump
4.75
5.0
5.25
V
Configuration listed in footnote.
PUMP
PUMP
PUMP
PUMP
Average, neglecting ripple. SMP
trip voltage is set to 5.0V.
a
3.3V Output Voltage from Pump
2.6V Output Voltage from Pump
Available Output Current
3.00
2.45
3.25
2.55
3.60
2.80
V
V
Configuration listed in footnote.
Average, neglecting ripple. SMP
trip voltage is set to 3.25V.
a
Configuration listed in footnote.
Average, neglecting ripple. SMP
trip voltage is set to 2.55V.
a
I
Configuration listed in footnote.
V
V
V
= 1.8V, V
= 1.5V, V
= 1.3V, V
= 5.0V
= 3.25V
= 2.55V
5
8
8
–
–
–
–
–
–
mA
mA
mA
SMP trip voltage is set to 5.0V.
SMP trip voltage is set to 3.25V.
SMP trip voltage is set to 2.55V.
BAT
BAT
BAT
PUMP
PUMP
PUMP
a
V
V
V
V
5V
Input Voltage Range from Battery
Input Voltage Range from Battery
Input Voltage Range from Battery
1.8
1.0
1.0
1.2
–
–
–
–
5.0
3.3
3.0
–
V
V
V
V
Configuration listed in footnote.
SMP trip voltage is set to 5.0V.
BAT
BAT
BAT
a
3V
2V
Configuration listed in footnote.
SMP trip voltage is set to 3.25V.
a
Configuration listed in footnote.
SMP trip voltage is set to 2.55V.
a
Minimum Input Voltage from Battery to
Start Pump
Configuration listed in footnote.
BATSTART
0°C ≤ T ≤ 100. 1.25V at
A
T = -40°C
A
Document Number: 38-12028 Rev. *I
Page 26 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Table 24. DC Switch Mode Pump (SMP) Specifications (continued)
Symbol
Description
Line Regulation (over V
Min
Typ
Max
Units
Notes
a
ΔV
ΔV
ΔV
range)
–
5
–
%V
Configuration listed in footnote.
PUMP_Line
BAT
O
V
is the “Vdd Value for PUMP
O
Trip” specified by the VM[2:0]
setting in the DC POR and LVD
a
Load Regulation
–
5
–
%V
Configuration listed in footnote.
PUMP_Load
O
V
is the “Vdd Value for PUMP
O
Trip” specified by the VM[2:0]
setting in the DC POR and LVD
a
Output Voltage Ripple (depends on
capacitor/load)
–
100
50
–
–
mVpp Configuration listed in footnote.
Load is 5 mA.
PUMP_Ripple
a
E
Efficiency
35
%
Configuration listed in footnote.
3
2
Load is 5 mA. SMP trip voltage is
set to 3.25V.
E
Efficiency
F
Switching Frequency
Switching Duty Cycle
–
–
1.3
50
–
–
MHz
%
PUMP
DC
PUMP
a.
L
1
1
1
Figure 13. Basic Switch Mode Pump Circuit
D1
Vdd
VPUMP
L1
SMP
+
VBAT
Battery
PSoC
C1
Vss
Document Number: 38-12028 Rev. *I
Page 27 of 56
CY8C24123A
CY8C24223A, CY8C24423A
DC Analog Reference Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling
of the digital signal may appear on the AGND.
Table 25. 5V DC Analog Reference Specifications
Symbol
Description
Bandgap Voltage Reference
AGND = Vdd/2
Min
1.28
Typ
1.30
Max
1.33
Units
BG
–
V
V
V
V
V
V
V
Vdd/2 - 0.04
2 x BG - 0.048
P2[4] - 0.011
BG - 0.009
1.6 x BG - 0.022
-0.034
Vdd/2 - 0.01
2 x BG - 0.030
P2[4]
Vdd/2 + 0.007
2 x BG + 0.024
P2[4] + 0.011
BG + 0.016
1.6 x BG + 0.018
0.034
–
AGND = 2 x BandGap
AGND = P2[4] (P2[4] = Vdd/2)
AGND = BandGap
–
–
BG + 0.008
1.6 x BG - 0.010
0.000
–
AGND = 1.6 x BandGap
–
AGND Block to Block Variation
(AGND = Vdd/2)
–
–
–
–
–
RefHi = Vdd/2 + BandGap
RefHi = 3 x BandGap
Vdd/2 + BG - 0.10
3 x BG - 0.06
Vdd/2 + BG
3 x BG
Vdd/2 + BG + 0.10
3 x BG + 0.06
V
V
V
V
V
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) 2 x BG + P2[6] - 0.113 2 x BG + P2[6] - 0.018 2 x BG + P2[6] + 0.077
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
P2[4] + BG - 0.130
P2[4] + BG - 0.016
P2[4] + BG + 0.098
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2
P2[6] = 1.3V)
P2[4] + P2[6] - 0.133 P2[4] + P2[6] - 0.016 P2[4] + P2[6]+ 0.100
–
–
–
–
–
–
RefHi = 3.2 x BandGap
RefLo = Vdd/2 – BandGap
RefLo = BandGap
3.2 x BG - 0.112
Vdd/2 - BG - 0.04
BG - 0.06
3.2 x BG
Vdd/2 - BG + 0.024
BG
3.2 x BG + 0.076
Vdd/2 - BG + 0.04
BG + 0.06
V
V
V
V
V
V
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) 2 x BG - P2[6] - 0.084 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
P2[4] - BG - 0.056
P2[4] - BG + 0.026
P2[4] - BG + 0.107
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,
P2[6] = 1.3V)
P2[4] - P2[6] - 0.057 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110
Table 26. 3.3V DC Analog Reference Specifications
Symbol
Description
Bandgap Voltage Reference
AGND = Vdd/2
Min
1.28
Typ
1.30
Max
1.33
Units
BG
–
V
V
Vdd/2 - 0.03
Vdd/2 - 0.01
Vdd/2 + 0.005
–
AGND = 2 x BandGap
AGND = P2[4] (P2[4] = Vdd/2)
AGND = BandGap
Not Allowed
–
P2[4] - 0.008
BG - 0.009
P2[4] + 0.001
BG + 0.005
1.6 x BG - 0.010
0.000
P2[4] + 0.009
BG + 0.015
1.6 x BG + 0.018
0.034
V
V
–
–
AGND = 1.6 x BandGap
1.6 x BG - 0.027
-0.034
V
–
AGND Column to Column Variation
(AGND = Vdd/2)
mV
–
–
–
–
RefHi = Vdd/2 + BandGap
Not Allowed
Not Allowed
Not Allowed
Not Allowed
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
Document Number: 38-12028 Rev. *I
Page 28 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Table 26. 3.3V DC Analog Reference Specifications (continued)
Symbol
Description
Min
Typ
Max
Units
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,
P2[6] = 0.5V)
P2[4] + P2[6] - 0.075 P2[4] + P2[6] - 0.009 P2[4] + P2[6] + 0.057
V
–
–
–
–
–
–
RefHi = 3.2 x BandGap
Not Allowed
RefLo = Vdd/2 - BandGap
Not Allowed
RefLo = BandGap
Not Allowed
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
Not Allowed
Not Allowed
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,
P2[6] = 0.5V)
P2[4] - P2[6] - 0.048 P2[4]- P2[6] + 0.022 P2[4] - P2[6] + 0.092
V
Table 27. 2.7V DC Analog Reference Specifications
Symbol
Description
Bandgap Voltage Reference
AGND = Vdd/2
Min
1.16
Typ
1.30
Max
1.33
Units
BG
–
V
V
Vdd/2 - 0.03
Vdd/2 - 0.01
Vdd/2 + 0.01
–
AGND = 2 x BandGap
AGND = P2[4] (P2[4] = Vdd/2)
AGND = BandGap
Not Allowed
–
P2[4] - 0.01
BG - 0.01
P2[4]
P2[4] + 0.01
BG + 0.015
V
V
–
BG
–
AGND = 1.6 x BandGap
Not Allowed
0.000
–
AGND Column to Column Variation
(AGND = Vdd/2)
-0.034
0.034
mV
–
–
–
–
–
RefHi = Vdd/2 + BandGap
Not Allowed
Not Allowed
Not Allowed
Not Allowed
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2,
P2[6] = 0.5V)
P2[4] + P2[6] - 0.08 P2[4] + P2[6] - 0.01 P2[4] + P2[6] + 0.06
V
–
–
–
–
–
–
RefHi = 3.2 x BandGap
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
RefLo = Vdd/2 - BandGap
RefLo = BandGap
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2,
P2[6] = 0.5V)
P2[4] - P2[6] - 0.05
P2[4]- P2[6] + 0.01
P2[4] - P2[6] + 0.09
V
Document Number: 38-12028 Rev. *I
Page 29 of 56
CY8C24123A
CY8C24223A, CY8C24423A
DC Analog PSoC Block Specifications
Table 29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 28. DC Analog PSoC Block Specifications
Symbol
Description
Min
–
Typ
Max
–
Units
kΩ
fF
Notes
R
Resistor Unit Value (Continuous Time)
Capacitor Unit Value (Switched Capacitor)
12.2
80
CT
SC
C
–
–
DC POR, SMP, and LVD Specifications
Table 30 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Programmable Sytem-on-Chip
Technical Reference Manual for more information on the VLT_CR register.
Table 29. DC POR and LVD Specifications
Symbol
Description
Vdd Value for PPOR Trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
Min
Typ
Max
Units
Notes
Vdd must be greater than
or equal to 2.5V during
startup, reset from the
XRES pin, or reset from
Watchdog.
V
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
PPOR0
PPOR1
PPOR2
V
V
–
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
0
a
0
V
V
V
V
V
V
V
V
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.45
2.92
2.51
2.99
V
LVD0
LVD1
LVD2
LVD3
LVD4
LVD5
LVD6
LVD7
0
b
0
V
0
3.02
3.13
4.48
4.64
4.73
4.81
3.09
3.20
4.55
4.75
4.83
4.95
V
0
V
0
V
V
V
V
Vdd Value for SMP Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
0
0
c
V
V
V
V
V
V
V
V
2.50
2.96
3.03
3.18
4.54
4.62
4.71
4.89
2.55
3.02
3.10
2.62
3.09
3.16
V
PUMP0
PUMP1
PUMP2
PUMP3
PUMP4
PUMP5
PUMP6
PUMP7
0
V
0
V
0
d
0
3.25
4.64
4.73
4.82
5.00
3.32
4.74
4.83
4.92
5.12
V
0
V
V
V
V
a. Always greater than 50 mV above V
b. Always greater than 50 mV above V
c. Always greater than 50 mV above V
d. Always greater than 50 mV above V
(PORLEV=00) for falling supply.
(PORLEV=01) for falling supply.
PPOR
PPOR
.
LVD0
.
LVD3
Document Number: 38-12028 Rev. *I
Page 30 of 56
CY8C24123A
CY8C24223A, CY8C24423A
DC Programming Specifications
Table 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 30. DC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd
Supply Voltage for Flash Write Operations
2.70
–
–
V
IWRIT
E
I
Supply Current During Programming or Verify
Input Low Voltage During Programming or Verify
Input High Voltage During Programming or Verify
–
–
5
–
–
–
25
0.8
–
mA
V
DDP
V
V
ILP
2.1
–
V
IHP
I
Input Current when Applying Vilp to P1[0] or P1[1]
During Programming or Verify
0.2
mA
Drivinginternalpulldown
resistor.
ILP
I
InputCurrentwhenApplyingVihptoP1[0]orP1[1]
During Programming or Verify
–
–
1.5
mA
Drivinginternalpulldown
resistor.
IHP
V
V
Output Low Voltage During Programming or Verify
–
–
–
Vss + 0.75
Vdd
V
V
OLV
Output High Voltage During Programming or
Verify
Vdd - 1.0
OHV
Flash
Flash Endurance (per block)
50,000
–
–
–
Erase/write cycles per
block
ENP
B
a
Flash
Flash Endurance (total)
1,800,000
10
–
–
–
–
–
Erase/write cycles
ENT
DR
Flash
Flash Data Retention
Years
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum
cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles
to 36x50,000 and that no single block ever sees more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature
argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more
information.
Document Number: 38-12028 Rev. *I
Page 31 of 56
CY8C24123A
CY8C24223A, CY8C24423A
AC Electrical Characteristics
AC Chip-Level Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 31. 5V and 3.3V AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
a,b,c
F
F
Internal Main Oscillator Frequency for
24 MHz
23.4
24
24.6
MHz Trimmed for 5V or 3.3V operation
using factory trim values. See Figure
IMO24
a,b,c
Internal Main Oscillator Frequency for
6 MHz
5.75
6
6.35
MHz Trimmed for 5V or 3.3V operation
using factory trim values. See Figure
IMO6
a,b
F
F
F
CPU Frequency (5V Nominal)
CPU Frequency (3.3V Nominal)
Digital PSoC Block Frequency
0.93
0.93
0
24
12
48
24.6
12.3
MHz
MHz
CPU1
CPU2
48M
b,c
a,b,d
49.2
MHz Refer to the AC Digital Block
Specifications.
b, d
F
F
Digital PSoC Block Frequency
0
24
32
24.6
64
MHz
kHz
24M
Internal Low Speed Oscillator
Frequency
15
32K1
F
F
External Crystal Oscillator
–
–
32.768
23.986
–
–
kHz Accuracy is capacitor and crystal
dependent. 50% duty cycle.
32K2
PLL
PLL Frequency
MHz Is a multiple (x732) of crystal
frequency.
Jitter24M2
24 MHz Period Jitter (PLL)
PLL Lock Time
–
0.5
0.5
–
–
–
600
10
ps
ms
ms
ms
T
T
T
T
PLLSLEW
PLLSLEWSLOW
OS
PLL Lock Time for Low Gain Setting
External Crystal Oscillator Startup to 1%
–
50
1700
2800
2620
3800
External Crystal Oscillator Startup to
100 ppm
–
ms The crystal oscillator frequency is
within100ppmofitsfinal valuebythe
OSACC
end of the T
period. Correct
osacc
operationassumesaproperlyloaded
1 uW maximum drive level 32.768
o
kHz crystal. 3.0V ≤ Vdd ≤ 5.5V, -40 C
o
≤ T ≤ 85 C.
A
Jitter32k
32 kHz Period Jitter
–
10
40
–
100
–
ns
μs
%
T
External Reset Pulse Width
24 MHz Duty Cycle
–
60
–
XRST
DC24M
50
Step24M
Fout48M
Jitter24M1P
24 MHz Trim Step Size
48 MHz Output Frequency
50
kHz
a,c
46.8
–
48.0
300
49.2
MHz Trimmed. Using factory trim values.
ps
24 MHz Period Jitter (IMO)
Peak-to-Peak
Jitter24M1R
24 MHz Period Jitter (IMO) Root Mean
Squared
–
–
0
–
–
–
600
12.3
–
ps
MHz
μs
F
T
Maximum frequency of signal on row
input or row output.
MAX
Supply Ramp Time
RAMP
a. 4.75V < Vdd < 5.25V.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
c. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for
operation at 3.3V.
d. See the individual user module data sheets for information on maximum frequencies for user modules.
Document Number: 38-12028 Rev. *I
Page 32 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Table 32. 2.7V AC Chip-Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
a,b,c
F
F
Internal Main Oscillator Frequency for
12 MHz
11.5
12
12.7
MHz Trimmed for 2.7V operation using
page 18. SLIMO mode = 1.
IMO12
a,b,c
a,b
Internal Main Oscillator Frequency for 6
MHz
5.75
6
6.35
MHz Trimmed for 2.7V operation using
page 18. SLIMO mode = 1.
IMO6
0
0
0
0
F
F
CPU Frequency (2.7V Nominal)
0.93
0
3
3.15
MHz
CPU1
a,b,c
0
Digital PSoC Block Frequency (2.7V
Nominal)
12
12.7
MHz Refer to the AC Digital Block
BLK27
Specifications.
F
Internal Low Speed Oscillator
Frequency
8
32
96
kHz
32K1
Jitter32k
32 kHz Period Jitter
–
10
40
–
150
–
ns
μs
%
T
External Reset Pulse Width
12 MHz Duty Cycle
–
XRST
DC12M
50
60
Jitter12M1P
12 MHz Period Jitter (IMO)
Peak-to-Peak
340
ps
Jitter12M1R
12 MHz Period Jitter (IMO) Root Mean
Squared
–
–
0
–
–
–
600
12.7
–
ps
MHz
μs
F
T
Maximum frequency of signal on row
input or row output.
MAX
Supply Ramp Time
RAMP
a. 2.4V < Vdd < 3.0V.
b. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
c. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum frequency for User Modules.
Document Number: 38-12028 Rev. *I
Page 33 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Figure 14. PLL Lock Timing Diagram
PLL
Enable
T
24 MHz
PLLSLEW
FPLL
PLL
Gain
0
Figure 15. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
T
24 MHz
PLLSLEWLOW
FPLL
PLL
Gain
1
Figure 16. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
T
OS
F32K2
Figure 17. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
Figure 18. 32 kHz Period Jitter (ECO) Timing Diagram
Jitter32k
F32K2
Document Number: 38-12028 Rev. *I
Page 34 of 56
CY8C24123A
CY8C24223A, CY8C24423A
AC General Purpose IO Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 33. 5V and 3.3V AC GPIO Specifications
Symbol
Description
Min
0
Typ
–
Max
12
18
18
–
Units
Notes
F
GPIO Operating Frequency
MHz Normal Strong Mode
GPIO
TRiseF
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
3
–
ns
ns
ns
ns
Vdd = 4.5 to 5.25V, 10% - 90%
TFallF
TRiseS
TFallS
2
–
Vdd = 4.5 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
10
10
27
22
–
Table 34. 2.7V AC GPIO Specifications
Symbol
Description
Min
0
Typ
–
Max
3
Units
Notes
F
GPIO Operating Frequency
MHz Normal Strong Mode
GPIO
TRiseF
Rise Time, Normal Strong Mode, Cload = 50 pF
Fall Time, Normal Strong Mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
6
–
50
ns
ns
ns
ns
Vdd = 2.4 to 3.0V, 10% - 90%
TFallF
TRiseS
TFallS
6
–
50
Vdd = 2.4 to 3.0V, 10% - 90%
Vdd = 2.4 to 3.0V, 10% - 90%
Vdd = 2.4 to 3.0V, 10% - 90%
18
18
40
40
120
120
Figure 19. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
Document Number: 38-12028 Rev. *I
Page 35 of 56
CY8C24123A
CY8C24223A, CY8C24423A
AC Operational Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V and 2.7V.
Table 35. 5V AC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
T
T
Rising Settling Time from 80% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
ROA
–
–
–
–
–
–
3.9
0.72
0.62
μs
μs
μs
Falling Settling Time from 20% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
SOA
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
–
–
–
–
–
–
5.9
0.92
0.72
μs
μs
μs
SR
SR
Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
ROA
0.15
1.7
6.5
–
–
–
–
–
–
V/μs
V/μs
V/μs
Falling Slew Rate (20% to 80%) (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
FOA
0.01
0.5
4.0
–
–
–
–
–
–
V/μs
V/μs
V/μs
Power = High, Opamp Bias = High
BW
Gain Bandwidth Product
OA
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
0.75
3.1
5.4
–
–
–
–
–
–
MHz
MHz
MHz
E
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
NOA
Table 36. 3.3V AC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
T
T
Rising Settling Time from 80% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
ROA
–
–
–
–
3.92
0.72
μs
μs
Power = Medium, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
SOA
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
–
–
–
–
5.41
0.72
μs
μs
SR
SR
Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
ROA
0.31
2.7
–
–
–
–
V/μs
V/μs
Falling Slew Rate (20% to 80%) (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
FOA
0.24
1.8
–
–
–
–
V/μs
V/μs
BW
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
OA
0.67
2.8
–
–
–
–
MHz
MHz
E
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
NOA
Document Number: 38-12028 Rev. *I
Page 36 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Table 37. 2.7V AC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
T
T
Rising Settling Time from 80% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
ROA
–
–
–
–
3.92
0.72
μs
μs
Power = Medium, Opamp Bias = High
Falling Settling Time from 20% of ΔV to 0.1% of ΔV
(10 pF load, Unity Gain)
SOA
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
–
–
–
–
5.41
0.72
μs
μs
SR
SR
Rising Slew Rate (20% to 80%) (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
ROA
0.31
2.7
–
–
–
–
V/μs
V/μs
Falling Slew Rate (20% to 80%) (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
FOA
0.24
1.8
–
–
–
–
V/μs
V/μs
BW
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
OA
0.67
2.8
–
–
–
–
MHz
MHz
E
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
–
100
–
nV/rt-Hz
NOA
Document Number: 38-12028 Rev. *I
Page 37 of 56
CY8C24123A
CY8C24223A, CY8C24423A
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 20. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 21. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
0.01
0.1
1
10
100
Freq (kHz)
Document Number: 38-12028 Rev. *I
Page 38 of 56
CY8C24123A
CY8C24223A, CY8C24423A
AC Low Power Comparator Specifications
Table 38 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V at 25°C and are for design guidance only.
Table 38. AC Low Power Comparator Specifications
Symbol
Description
LPC response time
Min
Typ
Max
Units
Notes
T
–
–
50
μs
≥ 50 mV overdrive comparator
reference set within V
RLPC
REFLPC
AC Digital Block Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 39. 5V and 3.3V AC Digital Block Specifications
Function
Timer
Description
Capture Pulse Width
Min
Typ
–
Max
–
Units
Notes
a
50
ns
Maximum Frequency, No Capture
Maximum Frequency, With Capture
Enable Pulse Width
–
–
–
49.2
24.6
–
MHz 4.75V < Vdd < 5.25V
–
MHz
a
Counter
50
–
ns
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
Kill Pulse Width:
–
–
–
49.2
24.6
MHz 4.75V < Vdd < 5.25V
MHz
–
Dead Band
Asynchronous Restart Mode
Synchronous Restart Mode
Disable Mode
20
–
–
–
–
–
–
–
ns
a
50
ns
a
50
–
ns
Maximum Frequency
–
–
49.2
49.2
MHz 4.75V < Vdd < 5.25V
MHz 4.75V < Vdd < 5.25V
CRCPRS
(PRS Mode)
Maximum Input Clock Frequency
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
Maximum Input Clock Frequency
–
–
–
–
–
24.6
8.2
MHz
SPIM
MHz Maximum data rate at 4.1 MHz
due to 2 x over clocking.
SPIS
Maximum Input Clock Frequency
–
–
–
4.1
–
ns
ns
a
Width of SS_ Negated Between Transmissions
Maximum Input Clock Frequency
50
Transmitter
Receiver
–
–
–
–
24.6
MHz Maximum data rate at 3.08
MHz due to 8 x over clocking.
Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
–
–
–
49.2
24.6
49.2
MHz Maximum data rate at 6.15
MHz due to 8 x over clocking.
Maximum Input Clock Frequency
MHz Maximum data rate at 3.08
MHz due to 8 x over clocking.
Maximum Input Clock Frequency with Vdd ≥
4.75V, 2 Stop Bits
MHz Maximum data rate at 6.15
MHz due to 8 x over clocking.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 38-12028 Rev. *I
Page 39 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Table 40. 2.7V AC Digital Block Specifications
Function
Description
Min
Typ
Max
Units
Notes
All
Maximum Block Clocking Frequency
12.7
MHz 2.4V < Vdd < 3.0V
Functions
a
0
0
Timer
Capture Pulse Width
100
–
–
–
ns
Maximum Frequency, With or Without Capture
–
12.7
0
MHz
ns
a
0
Counter Enable Pulse Width
Maximum Frequency, No Enable Input
100
–
–
–
–
–
12.7
12.7
MHz
MHz
Maximum Frequency, Enable Input
Kill Pulse Width:
–
Dead
Band
Asynchronous Restart Mode
Synchronous Restart Mode
20
100
100
–
–
–
0
ns
ns
a
a
0
–
–
0
0
0
Disable Mode
–
–
ns
Maximum Frequency
–
–
12.7
12.7
MHz
MHz
CRCPRS Maximum Input Clock Frequency
–
(PRS
Mode)
CRCPRS Maximum Input Clock Frequency
–
–
12.7
MHz
(CRC
Mode)
SPIM
Maximum Input Clock Frequency
Maximum Input Clock Frequency
–
–
–
–
6.35
4.23
MHz Maximum data rate at 3.17 MHz
due to 2 x over clocking.
SPIS
ns
ns
a
0
0
Width of SS_ Negated Between Transmissions 100
–
–
Trans-
mitter
Maximum Input Clock Frequency
–
–
–
12.7
12.7
MHz Maximum data rate at 1.59 MHz
due to 8 x over clocking.
Receiver Maximum Input Clock Frequency
–
MHz Maximum data rate at 1.59 MHz
due to 8 x over clocking.
a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Document Number: 38-12028 Rev. *I
Page 40 of 56
CY8C24123A
CY8C24223A, CY8C24423A
AC Analog Output Buffer Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 41. 5V AC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
T
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
ROB
–
–
–
–
2.5
2.5
μs
μs
T
Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
SOB
–
–
–
–
2.2
2.2
μs
μs
SR
SR
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High
ROB
0.65
0.65
–
–
–
–
V/μs
V/μs
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High
FOB
0.65
0.65
–
–
–
–
V/μs
V/μs
BW
BW
Small Signal Bandwidth, 20mV , 3dB BW, 100 pF Load
Power = Low
Power = High
OB
pp
0.8
0.8
–
–
–
–
MHz
MHz
Large Signal Bandwidth, 1V , 3dB BW, 100 pF Load
OB
pp
Power = Low
Power = High
300
300
–
–
–
–
kHz
kHz
Table 42. 3.3V AC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
T
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
ROB
–
–
–
–
3.8
3.8
μs
μs
T
Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
SOB
–
–
–
–
2.6
2.6
μs
μs
SR
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High
ROB
FOB
0.5
0.5
–
–
–
–
V/μs
V/μs
SR
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High
0.5
0.5
–
–
–
–
V/μs
V/μs
BW
BW
Small Signal Bandwidth, 20mV , 3dB BW, 100 pF Load
Power = Low
Power = High
OB
OB
pp
0.7
0.7
–
–
–
–
MHz
MHz
Large Signal Bandwidth, 1V , 3dB BW, 100 pF Load
pp
Power = Low
Power = High
200
200
–
–
–
–
kHz
kHz
Document Number: 38-12028 Rev. *I
Page 41 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Table 43. 2.7V AC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
T
Rising Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
ROB
–
–
–
–
4
4
μs
μs
T
Falling Settling Time to 0.1%, 1V Step, 100 pF Load
Power = Low
Power = High
SOB
–
–
–
–
3
3
μs
μs
SR
SR
Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
Power = Low
Power = High
ROB
0.4
0.4
–
–
–
–
V/μs
V/μs
Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
Power = Low
Power = High
FOB
0.4
0.4
–
–
–
–
V/μs
V/μs
BW
Small Signal Bandwidth, 20mV , 3dB BW, 100 pF Load
Power = Low
Power = High
OB
OB
pp
0.6
0.6
–
–
–
–
MHz
MHz
BW
Large Signal Bandwidth, 1V , 3dB BW, 100 pF Load
pp
Power = Low
Power = High
180
180
–
–
–
–
kHz
kHz
AC External Clock Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 44. 5V AC External Clock Specifications
Symbol
Description
Min
0.093
20.6
20.6
150
Typ
–
Max
24.6
5300
–
Units
MHz
ns
F
Frequency
OSCEXT
–
–
–
High Period
–
Low Period
–
ns
Power Up IMO to Switch
–
–
μs
Table 45. 3.3V AC External Clock Specifications
Symbol
Description
Min
0.093
0.186
41.7
41.7
150
Typ
–
Max
12.3
24.6
5300
–
Units
MHz
MHz
ns
a
F
Frequency with CPU Clock divide by 1
OSCEXT
OSCEXT
b
F
–
–
–
Frequency with CPU Clock divide by 2 or greater
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
–
–
–
ns
–
–
μs
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle
requirements.
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the
fifty percent duty cycle requirement is met.
Document Number: 38-12028 Rev. *I
Page 42 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Table 46. 2.7V AC External Clock Specifications
Symbol
Description
Min
0.093
0.186
41.7
41.7
150
Typ
–
Max
12.3
12.3
5300
–
Units
MHz
MHz
ns
a
F
Frequency with CPU Clock divide by 1
OSCEXT
OSCEXT
b
F
–
–
–
Frequency with CPU Clock divide by 2 or greater
High Period with CPU Clock divide by 1
Low Period with CPU Clock divide by 1
Power Up IMO to Switch
–
–
–
ns
–
–
μs
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle
requirements.
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the
fifty percent duty cycle requirement is met.
AC Programming Specifications
Table 47 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to
A
A
A
5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 47. AC Programming Specifications
Symbol
Description
Rise Time of SCLK
Min
1
Typ
–
Max
20
20
–
Units
ns
Notes
T
RSCLK
FSCLK
SSCLK
HSCLK
SCLK
T
T
T
F
T
T
T
T
T
Fall Time of SCLK
1
–
ns
Data Setup Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
–
8
MHz
ms
ms
ns
Flash Erase Time (Block)
–
20
20
–
–
ERASEB
WRITE
DSCLK
DSCLK3
DSCLK2
Flash Block Write Time
–
–
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
–
45
50
70
Vdd > 3.6
–
–
ns
3.0 ≤ Vdd ≤ 3.6
–
–
ns
2.4 ≤ Vdd ≤ 3.0
2
AC I C Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
2
Table 48. AC Characteristics of the I C SDA and SCL Pins for Vdd > 3.0V
Standard Mode
Fast Mode
Symbol
Description
SCL Clock Frequency
Units
Min
0
Max
100
–
Min
Max
400
–
F
T
0
kHz
SCLI2C
Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated.
4.0
0.6
μs
HDSTAI2C
T
T
T
T
T
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for a Repeated START Condition
Data Hold Time
4.7
4.0
4.7
0
–
–
–
–
–
1.3
0.6
0.6
0
–
–
–
–
–
μs
μs
μs
μs
ns
LOWI2C
HIGHI2C
SUSTAI2C
HDDATI2C
SUDATI2C
a
Data Setup Time
250
100
Document Number: 38-12028 Rev. *I
Page 43 of 56
CY8C24123A
CY8C24223A, CY8C24423A
2
Table 48. AC Characteristics of the I C SDA and SCL Pins for Vdd > 3.0V (continued)
Standard Mode
Fast Mode
Symbol
Description
Units
Min
4.0
4.7
Max
–
Min
Max
–
T
T
Setup Time for STOP Condition
0.6
1.3
μs
SUSTOI2C
Bus Free Time Between a STOP and START
Condition
–
–
μs
BUFI2C
T
Pulse Width of spikes are suppressed by the
input filter.
–
–
0
50
ns
SPI2C
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t
Š 250 ns must then be met. This is
SU;DAT
automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL
signal, it must output the next data bit to the SDA line t
tion) before the SCL line is released.
+ t
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specifica-
rmax
SU;DAT
2
Table 49. AC Characteristics of the I C SDA and SCL Pins for Vdd < 3.0V (Fast Mode Not Supported)
Standard Mode
Fast Mode
Symbol
Description
SCL Clock Frequency
Units
Min
0
Max
100
–
Min
Max
–
F
T
–
–
kHz
SCLI2C
Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated.
4.0
–
μs
HDSTAI2C
T
T
T
T
T
T
T
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for a Repeated START Condition
Data Hold Time
4.7
4.0
4.7
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
μs
μs
μs
μs
ns
μs
μs
LOWI2C
HIGHI2C
SUSTAI2C
HDDATI2C
SUDATI2C
SUSTOI2C
BUFI2C
Data Setup Time
250
4.0
4.7
Setup Time for STOP Condition
Bus Free Time Between a STOP and START
Condition
T
Pulse Width of spikes are suppressed by the
input filter
–
–
–
–
ns
SPI2C
2
Figure 22. Definition for Timing for Fast/Standard Mode on the I C Bus
SDA
SCL
TSPI2C
T
LOWI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
TSUSTOI2C
TSUSTAI2C
THDDATI2C
THDSTAI2C
THIGHI2C
S
Sr
P
S
Document Number: 38-12028 Rev. *I
Page 44 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Packaging Information
This section illustrates the packaging specifications for the CY8C24x23A PSoC device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
Packaging Dimensions
Figure 23. 8-Pin (300-Mil) PDIP
0.380
0.390
PIN 1 ID
4
1
DIMENSIONS IN INCHES MIN.
MAX.
0.240
0.260
5
8
0.300
0.325
0.100 BSC.
SEATING
PLANE
0.115
0.145
0.180 MAX.
0.008
0.015
0.015 MIN.
0.125
0.140
0°-10°
0.055
0.070
0.430 MAX.
0.014
0.022
51-85075 *A
Document Number: 38-12028 Rev. *I
Page 45 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Figure 24. 8-Pin (150-Mil) SOIC
PIN 1 ID
1
4
1. DIMENSIONS IN INCHES[MM] MIN.
2. PIN 1 ID IS OPTIONAL,
MAX.
ROUND ON SINGLE LEADFRAME
0.150[3.810]
0.157[3.987]
RECTANGULAR ON MATRIX LEADFRAME
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0138[0.350]
0.0192[0.487]
51-85066 *C
Figure 25. 20-Pin (300-Mil) Molded DIP
20-Lead (300-Mil) Molded DIP P5
51-85011 *A
Document Number: 38-12028 Rev. *I
Page 46 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Figure 26. 20-Pin (210-Mil) SSOP
51-85077 *C
Figure 27. 20-Pin (300-Mil) Molded SOIC
51-85024 *C
Document Number: 38-12028 Rev. *I
Page 47 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Figure 30. 28-Pin (300-Mil) Molded SOIC
51-85026 *D
Figure 31. 32-Pin (5x5 mm) QFN
CHANGED SPEC. TITLE, CORRECTED EPAD DIMENSION
SIDE VIEW
TOP VIEW
BOTTOM VIEW
3.50
PIN1 ID
0.20 R.
Ø
N
N
1
2
1
2
0.45
SOLDERABLE
EXPOSED
PAD
3.50
3.50
-0.20
0°-12°
0.50
0.42±0.18
[4X]
SEATING
C
3.50
PLANE
A
NOTES:
1. HATCH AREA IS SOLDERABLE EXPOSED PAD.
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.054g
4. ALL DIMENSIONS ARE IN MM [MIN/MAX]
5. PACKAGE CODE
51-85188 *B
PART #
DESCRIPTION
)
LF32
LY32
STANDARD
PB-FREE
V
B
Document Number: 38-12028 Rev. *I
Page 49 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Figure 32. 32-Pin Sawn QFN Package
SOLDERABLE
EXPOSED
PAD
NOTES:
1. HATCH AREA IS SOLDERABLE EXPOSED PAD
2. BASED ON REF JEDEC # MO-220
3. PACKAGE W EIGHT: 0.058g
001-30999 *A
4. DIMENSIONS ARE IN MILLIMETERS
Important Note For information on the preferred dimensions for mounting QFN packages, see the following application note at
Figure 33. 56-Pin (300-Mil) SSOP
51-85062 *C
Document Number: 38-12028 Rev. *I
Page 50 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Thermal Impedances
Capacitance on Crystal Pins
Table 50. Thermal Impedances per Package
Table 51. Typical Package Capacitance on Crystal Pins
Package Package Capacitance
2.8 pF
Package
Typical θ
*
JA
8 PDIP
123°C/W
185°C/W
109°C/W
117 °C/W
81°C/W
8 PDIP
8 SOIC
8 SOIC
2.0 pF
3.0 pF
2.6 pF
2.5 pF
3.5 pF
2.8 pF
2.7 pF
2.0 pF
20 PDIP
20 SSOP
20 SOIC
28 PDIP
28 SSOP
28 SOIC
32 QFN
20 PDIP
20 SSOP
20 SOIC
28 PDIP
28 SSOP
28 SOIC
32 QFN
69 °C/W
101°C/W
74 °C/W
22°C/W
* T = T + POWER x θJA
J
A
Solder Reflow Peak Temperature
The following table lists the minimum solder reflow peak temperatures to achieve good solderability.
Table 52. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature* Maximum Peak Temperature
8 PDIP
240°C
260°C
260°C
260°C
260°C
260°C
260°C
260°C
260°C
260°C
8 SOIC
240°C
240°C
240°C
220°C
240°C
240°C
220°C
240°C
20 PDIP
20 SSOP
20 SOIC
28 PDIP
28 SSOP
28 SOIC
32 QFN
o
*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 C with
o
Sn-Pb or 245 ± 5 C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
Document Number: 38-12028 Rev. *I
Page 51 of 56
CY8C24123A
CY8C24223A, CY8C24423A
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
Development Tool Selection
■ iMAGEcraft C Compiler (Registration Required)
■ ISSP Cable
This section presents the development tools available for all
current PSoC device families including the CY8C24x23A family.
■ USB 2.0 Cable and Blue Cat-5 Cable
■ 2 CY8C29466-24PXI 28-PDIP Chip Samples
Software
PSoC Designer™
At the core of the PSoC development software suite is PSoC
Designer. Used by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for half a decade.
PSoC Designer is available free of charge at
http://www.cypress.com under DESIGN RESOURCES >>
Software and Drivers.
CY3210-ExpressDK PSoC Express Development Kit
The CY3210-ExpressDK is for advanced prototyping and
development with PSoC Express (may be used with ICE-Cube
2
In-Circuit Emulator). It provides access to I C buses, voltage
reference, switches, upgradeable modules and more. The kit
includes:
PSoC Express™
■ PSoC Express Software CD
■ Express Development Board
■ 4 Fan Modules
As the newest addition to the PSoC development software suite,
PSoC Express is the first visual embedded system design tool
that allows a user to create an entire PSoC project and generate
a schematic, BOM, and data sheet without writing a single line
of code. Users work directly with application objects such as
LEDs, switches, sensors, and fans. PSoC Express is available
■ 2 Proto Modules
■ MiniProg In-System Serial Programmer
■ MiniEval PCB Evaluation Board
■ Jumper Wire Kit
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer or PSoC Express. PSoC
Programmer software is compatible with both PSoC ICE-Cube
In-Circuit Emulator and PSoC MiniProg. PSoC programmer is
available free ofcharge at http://www.cypress.com/psocpro-
grammer.
■ USB 2.0 Cable
■ Serial Cable (DB9)
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ 2 CY8C24423A-24PXI 28-PDIP Chip Samples
■ 2 CY8C27443-24PXI 28-PDIP Chip Samples
■ 2 CY8C29466-24PXI 28-PDIP Chip Samples
CY3202-C iMAGEcraft C Compiler
CY3202 is the optional upgrade to PSoC Designer that enables
the iMAGEcraft C compiler. It can be purchased from the
Online Store shopping cart icon at the bottom of the web page,
and click PSoC (Programmable System-on-Chip) to view a
current list of available items.
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online
Store.
CY3210-MiniProg1
The CY3210-MiniProg1 kit allows a user to program PSoC
devices through the MiniProg1 programming unit. The MiniProg
is a small, compact prototyping programmer that connects to the
PC through a provided USB 2.0 cable. The kit includes:
Development Kits
All development kits can be purchased from the Cypress Online
Store.
■ MiniProg Programming Unit
CY3215-DK Basic Development Kit
■ MiniEval Socket Programming and Evaluation Board
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■ PSoC Designer Software CD
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface allows users to run, halt, and single step the processor
and view the content of specific memory locations. Advance
emulation features also supported through PSoC Designer. The
kit includes:
■ Getting Started Guide
■ PSoC Designer Software CD
■ ICE-Cube In-Circuit Emulator
■ ICE Flex-Pod for CY8C29x66 Family
■ Cat-5 Adapter
■ USB 2.0 Cable
■ Mini-Eval Programming Board
Document Number: 38-12028 Rev. *I
Page 52 of 56
CY8C24123A
CY8C24223A, CY8C24423A
CY3210-PSoCEval1
Device Programmers
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit
includes:
All device programmers can be purchased from the Cypress
Online Store.
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■ Evaluation Board with LCD Module
■ MiniProg Programming Unit
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■ PSoC Designer Software CD
■ Getting Started Guide
■ Modular Programmer Base
■ 3 Programming Module Cards
■ MiniProg Programming Unit
■ PSoC Designer Software CD
■ Getting Started Guide
■ USB 2.0 Cable
CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features
a
■ USB 2.0 Cable
development board for the CY8C24794-24LFXI PSoC device.
Special features of the board include both USB and capacitive
sensing development and debugging support. This evaluation
board also includes an LCD module, potentiometer, LEDs, an
enunciator and plenty of bread boarding space to meet all of your
evaluation needs. The kit includes:
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note CY3207ISSP needs special software and is not compatible
with PSoC Programmer. The kit includes:
■ PSoCEvalUSB Board
■ LCD Module
■ CY3207 Programmer Unit
■ PSoC ISSP Software CD
■ MIniProg Programming Unit
■ Mini USB Cable
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ USB 2.0 Cable
■ PSoC Designer and Example Projects CD
■ Getting Started Guide
■ Wire Pack
Accessories (Emulation and Programming)
Table 53. Emulation and Programming Accessories
a
b
c
Part #
All non-QFN
Pin Package
Flex-Pod Kit
Foot Kit
Adapter
All non QFN
CY3250-24X23A
CY3250-8DIP-FK,
CY3250-8SOIC-FK,
CY3250-20DIP-FK,
CY3250-20SOIC-FK,
CY3250-20SSOP-FK,
CY3250-28DIP-FK,
CY3250-28SOIC-FK,
CY3250-28SSOP-FK
CY8C24423A-24LFXI
32 QFN
CY3250-24X23AQFN
CY3250-32QFN-FK
a. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
b. Foot kit includes surface mount feet that can be soldered to the target PCB.
c. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
Third Party Tools
Build a PSoC Emulator into Your Board
Several tools have been specially designed by the following
3rd-party vendors to accompany PSoC devices during devel-
opment and production. Specific details for each of these tools
RESOURCES >> Evaluation Boards.
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
Emulator into Your Board”.
Document Number: 38-12028 Rev. *I
Page 53 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Ordering Information
The following table lists the CY8C24x23A PSoC device’s key package features and ordering codes.
Table 54. CY8C24x23A PSoC Device Key Features and Ordering Information
8 Pin (300 Mil) DIP
8 Pin (150 Mil) SOIC
CY8C24123A-24PXI
CY8C24123A-24SXI
4K
4K
256 No
256 No
-40C to +85C
-40C to +85C
4
4
6
6
6
6
4
4
2
2
No
No
8 Pin (150 Mil) SOIC
(Tape and Reel)
CY8C24123A-24SXIT
4K
256 No
-40C to +85C
4
6
6
4
2
No
20 Pin (300 Mil) DIP
CY8C24223A-24PXI
CY8C24223A-24PVXI
4K
4K
256 Yes -40C to +85C
256 Yes -40C to +85C
4
4
6
6
16
16
8
8
2
2
Yes
Yes
20 Pin (210 Mil) SSOP
20 Pin (210 Mil) SSOP
(Tape and Reel)
CY8C24223A-24PVXIT 4K
256 Yes -40C to +85C
256 Yes -40C to +85C
256 Yes -40C to +85C
4
4
4
6
6
6
16
16
16
8
8
8
2
2
2
Yes
Yes
Yes
20 Pin (300 Mil) SOIC
CY8C24223A-24SXI
CY8C24223A-24SXIT
4K
4K
20 Pin (300 Mil) SOIC
(Tape and Reel)
28 Pin (300 Mil) DIP
CY8C24423A-24PXI
CY8C24423A-24PVXI
4K
4K
256 Yes -40C to +85C
256 Yes -40C to +85C
4
4
6
6
24
24
10
10
2
2
Yes
Yes
28 Pin (210 Mil) SSOP
28 Pin (210 Mil) SSOP
(Tape and Reel)
CY8C24423A-24PVXIT 4K
256 Yes -40C to +85C
256 Yes -40C to +85C
256 Yes -40C to +85C
256 Yes -40C to +85C
256 Yes -40C to +85C
4
4
4
4
4
6
6
6
6
6
24
24
24
24
24
10
10
10
10
10
2
2
2
2
2
Yes
Yes
Yes
Yes
Yes
Yes
28 Pin (300 Mil) SOIC
CY8C24423A-24SXI
CY8C24423A-24SXIT
CY8C24423A-24LFXI
CY8C24423A-24LTXI
4K
4K
4K
4K
28 Pin (300 Mil) SOIC
(Tape and Reel)
32 Pin (5x5 mm) QFN
32 Pin (5x5 mm 0.93 MAX)
SAWN QFN
32 Pin (5x5 mm 0.93 MAX)
SAWN QFN (Tape and Reel)
CY8C24423A-24LTXIT 4K
256 Yes -40C to +85C
256 Yes -40C to +85C
4
4
6
6
24
24
10
10
2
2
a
56 Pin OCD SSOP
CY8C24000A-24PVXI
4K
Yes
a. This part may be used for in-circuit debugging. It is NOT available for production
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Ordering Code Definitions
CY 8 C 24 xxx-SPxx
Package Type:
Thermal Rating:
C = Commercial
I = Industrial
PX = PDIP Pb-Free
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
LFX/LKX = QFN Pb-Free
AX = TQFP Pb-Free
E = Extended
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 38-12028 Rev. *I
Page 54 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Document History Page
®
Document Title: CY8C24123A, CY8C24223A, CY8C24423A PSoC Programmable System-on-Chip™
Document Number: 38-12028
Orig. of
Change
Submission
Date
Rev.
**
ECN
Description of Change
236409
247589
SFV
See ECN
See ECN
New silicon and new document – Preliminary Data Sheet.
*A
SFV
Changed the title to read “Final” data sheet. Updated Electrical Specifications
chapter.
*B
*C
261711
279731
HMT
HMT
See ECN
See ECN
Input all SFV memo changes. Updated Electrical Specifications chapter.
Update Electrical Specifications chapter, including 2.7 VIL DC GPIO spec. Add
Solder Reflow Peak Temperature table. Clean up pinouts and fine tune wording and
format throughout.
*D
*E
*F
352614
424036
521439
HMT
HMT
HMT
See ECN
See ECN
See ECN
Add new color and CY logo. Add URL to preferred dimensions for mounting MLF
packages. Update Transmitter and Receiver AC Digital Block Electrical Specifica-
tions. Re-add ISSP pinout identifier. Delete Electrical Specification sentence re:
devices running at greater than 12 MHz. Update Solder Reflow Peak Temperature
table. Fix CY.com URLs. Update CY copyright.
Fix SMP 8-pin SOIC error in Feature and Order table. Update 32-pin QFN E-Pad
dimensions and rev. *A. Add ISSP note to pinout tables. Update typical and recom-
mended Storage Temperature per industrial specs. Add OCD non-production pinout
and package diagram. Update CY branding and QFN convention. Update package
diagram revisions.
Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add new Dev.
Tool section. Add CY8C20x34 to PSoC Device Characteristics table.
*G
*H
2256806 UVS/PYRS See ECN
2425586 DSO/AESA See ECN
Added Sawn pin information.
Corrected Ordering Information to include CY8C24423A-24LTXI and
CY8C24423A-24LTXIT
®
*I
2619935 OGNE/AESA 12/11/2008
Changed title to “CY8C24123A, CY8C24223A, CY8C24423A PSoC
Programmable System-on-Chip™”
Updated package diagram 001-30999 to *A.
Document Number: 38-12028 Rev. *I
Page 55 of 56
CY8C24123A
CY8C24223A, CY8C24423A
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
PSoC Solutions
General
Clocks & Buffers
Wireless
Low Power/Low Voltage
Precision Analog
LCD Drive
Memories
Image Sensors
CAN 2.0b
USB
© Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-12028 Rev. *I
Revised December 11, 2008
Page 56 of 56
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names
mentioned in this document may be the trademarks of their respective holders.
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