Cypress CY8C24094 User Manual

latest signal-to-noise signal level requirements Application

CY8C24094, CY8C24794

CY8C24894, CY8C24994

Figure 3-2. Analog System Block Diagram

3.1 The Analog System

A ll IO

(E x c e p t P o rt 7 )

The Analog System is composed of 6 configurable blocks, each

comprised of an opamp circuit allowing the creation of complex

analog signal flows. Analog peripherals are very flexible and can

be customized to support specific application requirements.

Some of the more common PSoC analog functions (most

available as user modules) are listed below.

P 0 [7 ]

P 0 [5 ]

P 0 [6 ]

P 0 [4 ]

P 0 [3 ]

P 0 [1 ]

P 0 [2 ]

P 0 [0 ]

■ Analog-to-digital converters (up to 2, with 6 to 14-bit resolution,

selectable as Incremental, Delta Sigma, and SAR)

P 2 [6 ]

P 2 [4 ]

P 2 [3 ]

P 2 [1 ]

■ Filters (2 and 4 pole band-pass, low-pass, and notch)

■ Amplifiers (up to 2, with selectable gain to 48x)

■ Instrumentation amplifiers (1 with selectable gain to 93x)

■ Comparators (up to 2, with 16 selectable thresholds)

■ DACs (up to 2, with 6- to 9-bit resolution)

P 2 [2 ]

P 2 [0 ]

■ Multiplying DACs (up to 2, with 6- to 9-bit resolution)

A C I0 [1 :0 ]

A rra y In p u t

A C I1 [1 :0 ]

■ High current output drivers (two with 30 mA drive as a PSoC

Core Resource)

C o n fig u ra tio n

■ 1.3V reference (as a System Resource)

■ DTMF Dialer

B lo c k

A rray

A C B 0 0

A S C 1 0

A S D 2 0

A C B 0 1

■ Modulators

A S D 1 1

A S C 2 1

■ Correlators

■ Peak Detectors

A n a lo g R e fe re n c e

■ Many other topologies possible

In te rfa c e to

D ig ita l S y s te m

R e fe re n c e

G e n e ra to rs

Analog blocks are arranged in a column of three, which includes

one CT (Continuous Time) and two SC (Switched Capacitor)

blocks, as shown in Figure 3-2.

R e fH i

R e fL o

A G N D

A G N D In

R e fIn

B a n d g a p

M 8 C In te rfa c e (A d d re s s B u s , D a ta B u s , E tc .)

3.0.1 The Analog Multiplexer System

The Analog Mux Bus can connect to every GPI/O pin in ports 0-5.

Pins are connected to the bus individually or in any combination.

The bus also connects to the analog system for analysis with

comparators and analog-to-digital converters. It is split into two

sections for simultaneous dual-channel processing. An

additional 8:1 analog input multiplexer provides a second path to

bring Port 0 pins to the analog array.

Switch control logic enables selected pins to precharge continu-

ously under hardware control. This enables capacitive

measurement for applications such as touch sensing. Other

multiplexer applications include:

■ Track pad, finger sensing.

■ Chip-wide mux that allows analog input from up to 48 I/O pins.

■ Crosspoint connection between any I/O pin combinations.

When designing capacitive sensing applications, refer to the

Notes, which are found under http://www.cypress.com > Design

Resources > Application Notes. In general, and unless otherwise

noted in the relevant Application Notes, the minimum

signal-to-noise ratio (SNR) for CapSense applications is 5:1.

Document Number: 38-12018 Rev. *M

Page 3 of 47

information, see the latest PSoC device data sheets on the web

CY8C24094, CY8C24794

CY8C24894, CY8C24994

3.1 Additional System Resources

4. Getting Started

System Resources, provide additional capability useful to

complete systems. Additional resources include a multiplier,

decimator, low voltage detection, and power on reset. Brief state-

ments describing the merits of each resource follow.

The quickest way to understand PSoC silicon is to read this data

sheet and then use the PSoC Designer Integrated Development

Environment (IDE). This data sheet is an overview of the PSoC

integrated circuit and presents specific pin, register, and

electrical specifications.

■ Full-Speed USB (12 Mbps) with 5 configurable endpoints and

256 bytes of RAM. No external components required except

two series resistors. Wider than commercial temperature USB

operation (-10°C to +85°C).

For in depth information, along with detailed programming

details, see the PSoC® Programmable System-on-Chip

Technical Reference Manual for CY8C28xxx PSoC devices.

■ Digital clock dividers provide three customizable clock

frequencies for use in applications. The clocks can be routed

to both the digital and analog systems. Additional clocks are

generated using digital PSoC blocks as clock dividers.

For up-to-date ordering, packaging, and electrical specification

at www.cypress.com/psoc.

4.1 Application Notes

■ Two multiply accumulates (MACs) provide fast 8-bit multipliers

with 32-bit accumulate, to assist in both general math and

digital filters.

Application notes are an excellent introduction to the wide variety

of possible PSoC designs. They are located here:

www.cypress.com/psoc. Select Application Notes under the

Documentation tab.

■ Decimator provides a custom hardware filter for digital signal

processing applications including creation of Delta Sigma

ADCs.

4.2 Development Kits

■ TheI2Cmoduleprovides100and400kHzcommunicationover

two wires. Slave, master, multi-master are supported.

PSoC Development Kits are available online from Cypress at

www.cypress.com/shop and through a growing number of

regional and global distributors, which include Arrow, Avnet,

Digi-Key, Farnell, Future Electronics, and Newark.

■ Low Voltage Detection (LVD) interrupts signal the application

of falling voltage levels, while the advanced POR (Power On

Reset) circuit eliminates the need for a system supervisor.

4.3 Training

■ An internal 1.3V reference provides an absolute reference for

the analog system, including ADCs and DACs.

Free PSoC technical training (on demand, webinars, and

workshops) is available online at www.cypress.com/training. The

training covers a wide variety of topics and skill levels to assist

you in your designs.

■ Versatile analog multiplexer system.

3.2 PSoC Device Characteristics

4.4 CyPros Consultants

Depending on your PSoC device characteristics, the digital and

analog systems can have 16, 8, or 4 digital blocks and 12, 6, or

4 analog blocks. The following table lists the resources available

for specific PSoC device groups. The device covered by this data

sheet is shown in the highlighted row of the table

Certified PSoC Consultants offer everything from technical

assistance to completed PSoC designs. T o c ontact or become a

PSoC Consultant go to www.cypress.com/cypros.

4.5 Solutions Library

Visit our growing library of solution focused designs at

www.cypress.com/solutions. Here you can find various appli-

cation designs that include firmware and hardware design files

that enable you to complete your designs quickly.

Table 3-1. PSoC Device Characteristics

PSoC Part

Number

4.6 Technical Support

CY8C29x66

CY8C27x43

up to

32K

16K

For assistance with technical issues, search KnowledgeBase

articles and forums at www.cypress.com/support. If you cannot

find an answer to your question, call technical support at

1-800-541-4736.

up to

256

Bytes

CY8C24x94

16K

CY8C24x23A

up to

256

Bytes

[1]

CY8C21x34

CY8C21x23

CY8C20x34

up to

512

Bytes

[1]

[2]

256

Bytes

up to

512

Bytes

Document Number: 38-12018 Rev. *M

Page 4 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

5.1.4 Code Generation Tools

5. Development Tools

PSoC Designer supports multiple third party C compilers and

assemblers. The code generation tools work seamlessly within

the PSoC Designer interface and have been tested with a full

range of debugging tools. The choice is yours.

PSoC Designer is a Microsoft^®Windows-based, integrated

development

environment

for

the

Programmable

System-on-Chip (PSoC) devices. The PSoC Designer IDE runs

on Windows XP or Windows Vista.

This system provides design database management by project,

an integrated debugger with In-Circuit Emulator, in-system

programming support, and built-in support for third-party

assemblers and C compilers.

Assemblers. The assemblers allow assembly code to merge

seamlessly with C code. Link libraries automatically use absolute

addressing or are compiled in relative mode, and linked with

other software modules to get absolute addressing.

PSoC Designer also supports C language compilers developed

specifically for the devices in the PSoC family.

C Language Compilers. C language compilers are available

that support the PSoC family of devices. The products allow you

to create complete C programs for the PSoC family devices.

5.1 PSoC Designer Software Subsystems

The optimizing C compilers provide all the features of C tailored

to the PSoC architecture. They come complete with embedded

libraries providing port and bus operations, standard keypad and

display support, and extended math functionality.

5.1.1 System-Level View

A drag-and-drop visual embedded system design environment

based on PSoC Express. In the system level view you create a

model of your system inputs, outputs, and communication inter-

faces. You define when and how an output device changes state

based upon any or all other system devices. Based upon the

design, PSoC Designer automatically selects one or more PSoC

Mixed-Signal Controllers that match your system requirements.

5.1.5 Debugger

The PSoC Designer Debugger subsystem provides hardware

in-circuit emulation, allowing you to test the program in a physical

system while providing an internal view of the PSoC device.

Debugger commands allow the designer to read and program

and read and write data memory, read and write I/O registers,

read and write CPU registers, set and clear breakpoints, and

provide program run, halt, and step control. The debugger also

allows the designer to create a trace buffer of registers and

memory locations of interest.

PSoC Designer generates all embedded code, then compiles

and links it into a programming file for a specific PSoC device.

5.1.2 Chip-Level View

The chip-level view is a more traditional integrated development

environment (IDE) based on PSoC Designer 4.4. Choose a base

device to work with and then select different onboard analog and

digital components called user modules that use the PSoC

blocks. Examples of user modules are ADCs, DACs, Amplifiers,

and Filters. Configure the user modules for your chosen

application and connect them to each other and to the proper

pins. Then generate your project. This prepopulates your project

with APIs and libraries that you can use to program your

application.

5.1.6 Online Help System

The online help system displays online, context-sensitive help

for the user. Designed for procedural and quick reference, each

functional subsystem has its own context-sensitive help. This

system also provides tutorials and links to FAQs and an Online

Support Forum to aid the designer in getting started.

5.2 In-Circuit Emulator

The device editor also supports easy development of multiple

configurations and dynamic reconfiguration. Dynamic

configuration allows for changing configurations at run time.

A low cost, high functionality ICE (In-Circuit Emulator) is

available for development support. This hardware has the

capability to program single devices.

5.1.3 Hybrid Designs

The emulator consists of a base unit that connects to the PC by

way of a USB port. The base unit is universal and operates with

all PSoC devices. Emulation pods for each device family are

available separately. The emulation pod takes the place of the

PSoC device in the target board and performs full speed (24

MHz) operation.

You can begin in the system-level view, allow it to choose and

configure your user modules, routing, and generate code, then

switch to the chip-level view to gain complete control over

on-chip resources. All views of the project share a common code

editor, builder, and common debug, emulation, and programming

tools.

Document Number: 38-12018 Rev. *M

Page 5 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

6.3 Organize and Connect

6. Designing with PSoC Designer

You can build signal chains at the chip level by interconnecting

user modules to each other and the I/O pins, or connect system

level inputs, outputs, and communication interfaces to each

other with valuator functions.

The development process for the PSoC device differs from that

of a traditional fixed function microprocessor. The configurable

analog and digital hardware blocks give the PSoC architecture a

unique flexibility that pays dividends in managing specification

change during development and by lowering inventory costs.

These configurable resources, called PSoC Blocks, have the

ability to implement a wide variety of user-selectable functions.

In the system-level view, selecting a potentiometer driver to

control a variable speed fan driver and setting up the valuators

to control the fan speed based on input from the pot selects,

places, routes, and configures a programmable gain amplifier

(PGA) to buffer the input from the potentiometer, an analog to

digital converter (ADC) to convert the potentiometer’s output to

a digital signal, and a PWM to control the fan.

The PSoC development process can be summarized in the

following four steps:

1. Select components

2. Configure components

3. Organize and Connect

4. Generate, Verify, and Debug

In the chip-level view, perform the selection, configuration, and

routing so that you have complete control over the use of all

on-chip resources.

6.4 Generate, Verify, and Debug

6.1 Select Components

When you are ready to test the hardware configuration or move

on to developing code for the project, perform the “Generate

Application” step. This causes PSoC Designer to generate

source code that automatically configures the device to your

specification and provides the software for the system.

Both the system-level and chip-level views provide a library of

prebuilt, pretested hardware peripheral components. In the

system-level view, these components are called “drivers” and

correspond to inputs (a thermistor, for example), outputs (a

brushless DC fan, for example), communication interfaces

(I C-bus, for example), and the logic to control how they interact

with one another (called valuators).

Both system-level and chip-level designs generate software

based on your design. The chip-level design provides application

programming interfaces (APIs) with high level functions to

control and respond to hardware events at run-time and interrupt

service routines that you can adapt as needed. The system-level

design also generates a C main() program that completely

controls the chosen application and contains placeholders for

custom code at strategic positions allowing you to further refine

the software without disrupting the generated code.

In the chip-level view, the components are called “user modules”.

User modules make selecting and implementing peripheral

devices simple, and come in analog, digital, and mixed signal

varieties.

6.2 Configure Components

Each of the components you select establishes the basic register

settings that implement the selected function. They also provide

parameters and properties that allow you to tailor their precise

configuration to your particular application. For example, a Pulse

Width Modulator (PWM) User Module configures one or more

digital PSoC blocks, one for each 8 bits of resolution. The user

module parameters permit you to establish the pulse width and

duty cycle. Configure the parameters and properties to

correspond to your chosen application. Enter values directly or

by selecting values from drop-down menus.

A complete code development environment allows you to

develop and customize your applications in C, assembly

language, or both.

The last step in the development process takes place inside the

PSoC Designer’s Debugger subsystem. The Debugger

downloads the HEX image to the In-Circuit Emulator (ICE) where

it runs at full speed. Debugger capabilities rival those of systems

costing many times more. In addition to traditional single-step,

run-to-breakpoint and watch-variable features, the Debugger

provides a large trace buffer and allows you define complex

breakpoint events that include monitoring address and data bus

values, memory locations and external signals.

Both the system-level drivers and chip-level user modules are

documented in data sheets that are viewed directly in the PSoC

Designer. These data sheets explain the internal operation of the

component and provide performance specifications. Each data

sheet describes the use of each user module parameter or driver

property, and other information you may need to successfully

implement your design.

Document Number: 38-12018 Rev. *M

Page 6 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

7.2 Units of Measure

7. Document Conventions

A units of measure table is located in the Electrical Specifications

section. T a ble 10-1 on page 20 lists all the abbreviations used to

measure the PSoC devices.

7.1 Acronyms Used

The following table lists the acronyms that are used in this

document.

7.3 Numeric Naming

Acronym

Description

alternating current

Hexadecimal numbers are represented with all letters in

uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or

‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’

prefix, the C coding convention. Binary numbers have an

appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).

Numbers not indicated by an ‘h’ or ‘b’ are decimal.

ADC

API

analog-to-digital converter

application programming interface

central processing unit

continuous time

CPU

DAC

digital-to-analog converter

direct current

ECO

external crystal oscillator

EEPROM electrically erasable programmable read-only

memory

FSR

GPI/O

GUI

full scale range

general purpose I/O

graphical user interface

human body model

in-circuit emulator

HBM

ICE

ILO

internal low speed oscillator

internal main oscillator

input/output

IMO

I/O

IPOR

LSb

imprecise power on reset

least-significant bit

LVD

low voltage detect

MSb

most-significant bit

program counter

PLL

phase-locked loop

POR

PPOR

PSoC®

PWM

power on reset

precision power on reset

Programmable System-on-Chip™

pulse width modulator

switched capacitor

SRAM

static random access memory

Document Number: 38-12018 Rev. *M

Page 7 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

8. Pin Information

This section describes, lists, and illustrates the CY8C24x94 PSoC device family pins and pinout configuration.

The CY8C24x94 PSoC devices are available in the following packages, all of which are shown on the following pages. Every port pin

(labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.

8.1 56-Pin Part Pinout

Table 8-1. 56-Pin Part Pinout (QFN^[2]) See LEGEND details and footnotes in T a ble 8-2 on page 9.

Type

Digital Analog

No.

Figure 8-1. CY8C24794 56-Pin PSoC Device

Name

Description

I/O

I, M

P2[3] Direct switched capacitor block input.

P2[1] Direct switched capacitor block input.

P4[7]

P4[5]

P4[3]

P4[1]

P3[7]

A,I, M,P2[3]

A,I, M,P2[1]

M,P4[7]

P2[2], A, I,M

P2[0], A, I,M

P4[6],M

P4[4],M

P4[2],M

P4[0],M

P3[6],M

P3[4],M

P3[2],M

P3[0],M

P5[6],M

P5[4],M

P5[2],M

P5[0],M

P3[5]

P3[3]

P3[1]

M,P4[5]

M,P4[3]

M,P4[1]

M,P3[7]

P5[7]

P5[5]

P5[3]

QFN

(Top View )

M,P3[5]

M,P3[3]

M,P3[1]

P5[1]

M,P5[7]

M,P5[5]

M,P5[3]

M,P5[1]

P1[7] I2C Serial Clock (SCL).

P1[5] I2C Serial Data (SDA).

P1[3]

P1[1] I2C Serial Clock (SCL), ISSP SCLK

Power

Vss Ground connection.

USB

D+

D-

Power

Vdd Supply voltage.

I/O

P7[7]

P7[0]

P1[0] I2C Serial Data (SDA), ISSP SDATA

P1[2]

P1[4] Optional External Clock Input (EXTCLK).

P1[6]

P5[0]

Type

No.

Name

Description

I/O

P5[2]

Digital Analog

P5[4]

I/O

P2[6] External Voltage Reference (VREF) input.

P0[0] Analog column mux input.

P0[2] Analog column mux input.

P0[4] Analog column mux input VREF.

P0[6] Analog column mux input.

Vdd Supply voltage.

P5[6]

I, M

P3[0]

P3[2]

P3[4]

P3[6]

Power

I, M

P4[0]

Vss Ground connectI/On.

P4[2]

I/O

P0[7] Analog column mux input,.

P4[4]

I/O, M P0[5] Analog column mux input and column output.

I/O, M P0[3] Analog column mux input and column output.

P4[6]

I, M

P2[0] Direct switched capacitor block input.

P2[2] Direct switched capacitor block input.

P2[4] External Analog Ground (AGND) input.

I, M

P0[1] Analog column mux input.

P2[7]

P2[5]

Document Number: 38-12018 Rev. *M

Page 8 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

8.1 56-Pin Part Pinout (with XRES)

Table 8-2. 56-Pin Part Pinout (QFN^[2])

Type

Figure 8-2. CY8C24894 56-Pin PSoC Device

Name

Description

No.

Digital Analog

I/O

I, M

P2[3] Direct switched capacitor block input.

P2[1] Direct switched capacitor block input.

P4[7]

P4[5]

P4[3]

P4[1]

P3[7]

A, I, M, P2[3]

A, I, M, P2[1]

P2[2], A, I, M

P2[0], A, I, M

P3[5]

P3[3]

P3[1]

M, P4[7]

M, P4[5]

M, P4[3]

M, P4[1]

M, P3[7]

P4[6], M

P4[4], M

P4[2], M

P4[0], M

XRES

P5[7]

P5[5]

P5[3]

QFN

(Top View)

M, P3[5]

M, P3[3]

M, P3[1]

P3[4], M

P3[2], M

P3[0], M

P5[1]

P1[7] I2C Serial Clock (SCL).

P1[5] I2C Serial Data (SDA).

P1[3]

M, P5[7]

M, P5[5]

M, P5[3]

M, P5[1]

P5[6], M

P5[4], M

P5[2], M

P5[0], M

[1].

P1[1] I2C Serial Clock (SCL), ISSP SCLK

Power

Vss Ground connection.

USB

D+

D-

Power

Vdd Supply voltage.

I/O

P7[7]

P7[0]

P1[0] I2C Serial Data (SDA), ISSP SDATA

P1[2]

P1[4] Optional External Clock Input (EXTCLK).

P1[6]

I/O

P5[0]

P5[2]

P5[4]

P5[6]

P3[0]

P3[2]

P3[4]

Type

No.

Name

Description

Digital Analog

I/O

P2[6] External Voltage Reference (VREF) input.

P0[0] Analog column mux input.

P0[2] Analog column mux input.

P0[4] Analog column mux input VREF.

P0[6] Analog column mux input.

Vdd Supply voltage.

I, M

Input

XRES Active high external reset with internal

pull down.

Power

I/O

P4[0]

Power

I, M

Vss Ground connection.

P4[2]

I/O

P0[7] Analog column mux input,.

P4[4]

I/O, M P0[5] Analog column mux input and column output.

I/O, M P0[3] Analog column mux input and column output.

P4[6]

I, M

P2[0] Direct switched capacitor block input.

P2[2] Direct switched capacitor block input.

P2[4] External Analog Ground (AGND) input.

I, M

P0[1] Analog column mux input.

P2[7]

P2[5]

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

Notes

1. These are the ISSP pins, which are not High Z at POR. See the PSoC Programmable System-on-Chip Technical Reference Manual for details.

2. The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it

should be electrically floated and not connected to any other signal.

Document Number: 38-12018 Rev. *M

Page 9 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

8.1 68-Pin Part Pinout

The 68-pin QFN part table and drawing below is for the CY8C24994 PSoC device.

Table 8-3. 68-Pin Part Pinout (QFN^[2])

Type

Figure 8-3. CY8C24994 68-Pin PSoC Device

No.

Name

Description

Digital Analog

I/O

P4[7]

P4[5]

P4[3]

P4[1]

No connection.

Power

I/O

Vss

Ground connection.

M, P4[7]

M, P4[5]

M, P4[3]

P2[0], M, AI

P3[7]

P3[5]

P3[3]

P3[1]

P5[7]

P5[5]

P5[3]

P5[1]

P1[7]

P1[5]

P1[3]

P1[1]

Vss

P4[6], M

P4[4], M

P4[2], M

I/O

M, P4[1]

10 I/O

11 I/O

P4[0], M

XRES

12 I/O

13 I/O

14 I/O

15 I/O

16 I/O

17 I/O

18 I/O

19 I/O

20 Power

21 USB

22 USB

23 Power

24 I/O

25 I/O

26 I/O

27 I/O

28 I/O

29 I/O

30 I/O

31 I/O

32 I/O

33 I/O

34 I/O

35 I/O

36 I/O

37 I/O

38 I/O

39 I/O

40 I/O

41 I/O

42 I/O

43 I/O

Vss

M, P3[7]

M, P3[5]

P3[6], M

P3[4], M

QFN

(Top View)

M, P3[3]

M, P3[1]

M, P5[7]

P3[2], M

P3[0], M

I2C Serial Clock (SCL).

I2C Serial Data (SDA).

M, P5[5]

P5[6], M

P5[4], M

M, P5[3]

M, P5[1]

I2C SCL, M, P1[7]

I2C SDA, M, P1[5]

P5[2], M

P5[0], M

[1]

I2C Serial Clock (SCL) ISSP SCLK

Ground connection.

P1[6], M

D+

D-

Vdd

Supply voltage.

P7[7]

P7[6]

P7[5]

P7[4]

P7[3]

P7[2]

P7[1]

P7[0]

P1[0]

P1[2]

P1[4]

P1[6]

P5[0]

P5[2]

P5[4]

P5[6]

P3[0]

P3[2]

P3[4]

P3[6]

Type

No.

Name

Description

Digital Analog

50 I/O

51 I/O

52 I/O

P4[6]

I2C Serial Data (SDA), ISSP SDATA

I,M

P2[0] Direct switched capacitor block input.

P2[2] Direct switched capacitor block input.

P2[4] External Analog Ground (AGND) input.

P2[6] External Voltage Reference (VREF) input.

P0[0] Analog column mux input.

Optional External Clock Input (EXTCLK). 53 I/O

54 I/O

55 I/O

56 I/O

57 I/O

58 I/O

I,M

P0[2] Analog column mux input and column output.

P0[4] Analog column mux input and column output.

P0[6] Analog column mux input.

59 Power

Vdd

Vss

Supply voltage.

60 Power

61 I/O

Ground connection.

I,M

P0[7] Analog column mux input, integration input #1

62 I/O

I/O,M

P0[5] Analog column mux input and column output, integration

input #2.

No connection.

63 I/O

64 I/O

65 I/O

I/O,M

I,M

P0[3] Analog column mux input and column output.

P0[1] Analog column mux input.

P2[7]

46 Input

XRES Active high pin reset with internal pull

down.

47 I/O

48 I/O

49 I/O

P4[0]

P4[2]

P4[4]

66 I/O

67 I/O

68 I/O

P2[5]

I,M

P2[3] Direct switched capacitor block input.

P2[1] Direct switched capacitor block input.

LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.

Document Number: 38-12018 Rev. *M

Page 10 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

8.1 68-Pin Part Pinout (On-Chip Debug)

The 68-pin QFN part table and drawing below is for the CY8C24094 On-Chip Debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production.

Table 8-4. 68-Pin Part Pinout (QFN^[2])

Type

No.

Figure 8-4. CY8C24094 68-Pin OCD PSoC Device

Name

Description

Digital Analog

I/O

P4[7]

P4[5]

P4[3]

P4[1]

OCDE OCD even data I/O.

OCDO OCD odd data output.

Power

I/O

Vss

Ground connection.

M, P4[7]

M, P4[5]

M, P4[3]

P2[0], M, AI

P4[6], M

P3[7]

P3[5]

P3[3]

P3[1]

P5[7]

P5[5]

P5[3]

P5[1]

P1[7]

P1[5]

P1[3]

P1[1]

Vss

P4[4], M

P4[2], M

I/O

M, P4[1]

OCDE

OCDO

10 I/O

11 I/O

P4[0], M

XRES

CCLK

Vss

M, P3[7]

M, P3[5]

12 I/O

13 I/O

14 I/O

15 I/O

16 I/O

17 I/O

18 I/O

19 I/O

20 Power

21 USB

22 USB

23 Power

24 I/O

25 I/O

26 I/O

27 I/O

28 I/O

29 I/O

30 I/O

31 I/O

32 I/O

33 I/O

34 I/O

35 I/O

36 I/O

37 I/O

38 I/O

39 I/O

40 I/O

41 I/O

42 I/O

43 I/O

HCLK

P3[6], M

P3[4], M

QFN

(Top View)

M, P3[3]

M, P3[1]

M, P5[7]

M, P5[5]

P3[2], M

P3[0], M

I2C Serial Clock (SCL).

I2C Serial Data (SDA).

P5[6], M

P5[4], M

M, P5[3]

M, P5[1]

I2C SCL, M, P1[7]

I2C SDA, M, P1[5]

P5[2], M

P5[0], M

P1[6], M

I2C Serial Clock (SCL), ISSP SCLK

Ground connection.

D+

D-

Vdd

Supply voltage.

P7[7]

P7[6]

P7[5]

P7[4]

P7[3]

P7[2]

P7[1]

P7[0]

P1[0]

P1[2]

P1[4]

P1[6]

P5[0]

P5[2]

P5[4]

P5[6]

P3[0]

P3[2]

P3[4]

P3[6]

Type

Digital Analog

No.

Name

Description

50 I/O

51 I/O

52 I/O

P4[6]

I2C Serial Data (SDA), ISSP SDATA

I,M

P2[0] Direct switched capacitor block input.

P2[2] Direct switched capacitor block input.

Optional External Clock Input (EXTCLK). 53 I/O

P2[4] External Analog Ground (AGND) input.

P2[6] External Voltage Reference (VREF) input.

P0[0] Analog column mux input.

54 I/O

55 I/O

56 I/O

57 I/O

58 I/O

I,M

P0[2] Analog column mux input and column output.

P0[4] Analog column mux input and column output.

P0[6] Analog column mux input.

59 Power

Vdd

Vss

Supply voltage.

60 Power

61 I/O

Ground connection.

I,M

P0[7] Analog column mux input, integration input #1

62 I/O

I/O,M

P0[5] Analog column mux input and column output,

integration input #2.

HCLK OCD high-speed clock output.

CCLK OCD CPU clock output.

63 I/O

64 I/O

65 I/O

I/O,M

I,M

P0[3] Analog column mux input and column output.

P0[1] Analog column mux input.

P2[7]

46 Input

XRES Active high pin reset with internal pull

down.

47 I/O

48 I/O

49 I/O

P4[0]

P4[2]

P4[4]

66 I/O

67 I/O

68 I/O

P2[5]

I,M

P2[3] Direct switched capacitor block input.

P2[1] Direct switched capacitor block input.

LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, OCD = On-Chip Debugger.

Document Number: 38-12018 Rev. *M

Page 11 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

8.1 100-Ball VFBGA Part Pinout

The 100-ball VFBGA part is for the CY8C24994 PSoC device.

Table 8-5. 100-Ball Part Pinout (VFBGA)

No.

Name

Description

Name

Description

A1 Power

A2 Power

Vss

Vdd

Vss

Ground connection.

No connection.

Ground connection.

No connection.

F2 I/O

F3 I/O

F4 I/O

P5[7]

P3[5]

P5[1]

Vss

No connection.

F5 Power

F6 Power

Ground connection.

A6 Power

Supply voltage.

Vss

No connection.

F7 I/O

F8 I/O

P5[0]

P3[0]

No connection.

A9 Power

A10 Power

B1 Power

B2 Power

B3 I/O I,M

B4 I/O I,M

B5 I/O I,M

B6 Power

B7 I/O I,M

B8 I/O I,M

B9 Power

B10 Power

Ground connection.

XRES Active high pin reset with internal pull down.

P7[1]

F10 I/O

No connection.

G2 I/O

G3 I/O

G4 I/O

G5 I/O

G6 I/O

G7 I/O

G8 I/O

G9 I/O

G10 I/O

P5[5]

P3[3]

P2[1] Direct switched capacitor block input.

P0[1] Analog column mux input.

P1[7] I2C Serial Clock (SCL).

P0[7] Analog column mux input.

P1[1] I2C Serial Clock (SCL), ISSP SCLK

Vdd

Supply voltage.

P1[0] I2C Serial Data (SDA), ISSP SDATA

P0[2] Analog column mux input.

P1[6]

P3[4]

P5[6]

P7[2]

P2[2] Direct switched capacitor block input.

Vss

Ground connection.

No connection.

Vss

No connection.

C2 I/O

C3 I/O

C4 I/O

P4[1]

P4[7]

P2[7]

H2 I/O

H3 I/O

H4 I/O

P5[3]

P3[1]

P1[5] I2C Serial Data (SDA).

C5 I/O I/O,M P0[5] Analog column mux input and column output. H5 I/O

P1[3]

P1[2]

C6 I/O I,M

C7 I/O I,M

C8 I/O I,M

P0[6] Analog column mux input.

P0[0] Analog column mux input.

P2[0] Direct switched capacitor block input.

P4[2]

H6 I/O

H7 I/O

H8 I/O

H9 I/O

H10 I/O

P1[4] Optional External Clock Input (EXTCLK).

P3[2]

P5[4]

P7[3]

C9 I/O

C10

No connection.

Power

Vss

D+

Ground connection.

D2 I/O

D3 I/O

D4 I/O

P3[7]

P4[5]

P2[5]

USB

Power

I/O

D-

D5 I/O I/O,M P0[3] Analog column mux input and column output. J5

Vdd

P7[7]

P7[0]

P5[2]

Vss

Supply voltage.

D6 I/O I,M

P0[4] Analog column mux input.

D7 I/O

D8 I/O

D9 I/O

D10

P2[6] External Voltage Reference (VREF) input.

I/O

P4[6]

P4[0]

I/O

Power

Ground connection.

No connection.

J10 Power

K1 Power

K2 Power

E3 I/O

P4[3]

E4 I/O I,M

E5 Power

E6 Power

P2[3] Direct switched capacitor block input.

No connection.

Vss

Ground connection.

K5 Power

K6 I/O

K7 I/O

K8 I/O

K9 Power

K10 Power

Vdd

P7[6]

P7[5]

P7[4]

Vss

Supply voltage.

E7 I/O

E8 I/O

E9 I/O

E10

P2[4] External Analog Ground (AGND) input.

P4[4]

P3[6]

Ground connection.

No connection.

LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection.

Document Number: 38-12018 Rev. *M

Page 12 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

Figure 8-5. CY8C24094 OCD (Not for Production)

Vss

Vdd

Vss

Vss P2[1] P0[1] P0[7] Vdd P0[2] P2[2] Vss

P4[1] P4[7] P2[7] P0[5] P0[6] P0[0] P2[0] P4[2]

P3[7] P4[5] P2[5] P0[3] P0[4] P2[6] P4[6] P4[0]

NC P4[3] P2[3] Vss

P5[7] P3[5] P5[1] Vss

Vss P2[4] P4[4] P3[6]

Vss P5[0] P3[0] XRES P7[1]

P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2]

P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3]

Vss

D +

D -

Vdd P7[7] P7[0] P5[2] Vss

Vdd P7[6] P7[5] P7[4] Vss

Vss

BGA (Top View)

8.1 100-Ball VFBGA Part Pinout (On-Chip Debug)

The 100-pin VFBGA part table and drawing below is for the CY8C24094 On-Chip Debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production.

Table 8-6. 100-Ball Part Pinout (VFBGA)

No.

Name

Description

Name

Description

A1 Power

A2 Power

Vss

Vdd

Vss

Ground connection.

OCDE OCD even data I/O.

Ground connection.

No connection.

F2 I/O

F3 I/O

F4 I/O

P5[7]

P3[5]

P5[1]

No connection.

F5 Power

F6 Power

Vss

Ground connection.

A6 Power

Supply voltage.

Vss

No connection.

F7 I/O

F8 I/O

P5[0]

P3[0]

No connection.

A9 Power

A10 Power

B1 Power

B2 Power

Ground connection.

XRES Active high pin reset with internal pull down.

F10 I/O

P7[1]

OCDO OCD odd data output.

G2 I/O

G3 I/O

G4 I/O

G5 I/O

G6 I/O

G7 I/O

G8 I/O

G9 I/O

G10 I/O

P5[5]

P3[3]

B3 I/O I,M P2[1] Direct switched capacitor block input.

B4 I/O I,M P0[1] Analog column mux input.

B5 I/O I,M P0[7] Analog column mux input.

P1[7] I2C Serial Clock (SCL).

P1[1] I2C Serial Clock (SCL), ISSP SCLK

B6 Power

Vdd

Supply voltage.

P1[0] I2C Serial Data (SDA), ISSP SDATA

B7 I/O I,M P0[2] Analog column mux input.

P1[6]

P3[4]

P5[6]

P7[2]

B8 I/O I,M P2[2] Direct switched capacitor block input.

B9 Power

B10 Power

Vss

Ground connection.

No connection.

Vss

No connection.

C2 I/O

C3 I/O

C4 I/O

P4[1]

P4[7]

P2[7]

H2 I/O

H3 I/O

H4 I/O

P5[3]

P3[1]

P1[5] I2C Serial Data (SDA).

P1[3]

C5 I/O I/O, P0[5] Analog column mux input and column output. H5 I/O

C6 I/O I,M P0[6] Analog column mux input.

C7 I/O I,M P0[0] Analog column mux input.

H6 I/O

H7 I/O

P1[2]

P1[4] Optional External Clock Input (EXTCLK).

Document Number: 38-12018 Rev. *M

Page 13 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

Table 8-6. 100-Ball Part Pinout (VFBGA) (continued)

C8 I/O I,M P2[0] Direct switched capacitor block input.

H8 I/O

H9 I/O

H10 I/O

P3[2]

P5[4]

P7[3]

Vss

D+

C9 I/O

C10

P4[2]

No connection.

Power

Ground connection.

D2 I/O

D3 I/O

D4 I/O

P3[7]

P4[5]

P2[5]

Ground connection.

USB

D-

D5 I/O I/O, P0[3] Analog column mux input and column output. J5

Power

Vdd

Supply voltage.

D6 I/O I,M P0[4] Analog column mux input.

I/O

P7[7]

P7[0]

P5[2]

Vss

D7 I/O

D8 I/O

D9 I/O

D10

P2[6] External Voltage Reference (VREF) input.

P4[6]

I/O

P4[0]

Power

Ground connection.

No connection.

CCLK OCD CPU clock output.

J10 Power

K1 Power

K2 Power

Vss

No connection.

Vss

E3 I/O

P4[3]

E4 I/O I,M P2[3] Direct switched capacitor block input.

No connection.

E5 Power

E6 Power

Vss

Ground connection.

K5 Power

K6 I/O

K7 I/O

K8 I/O

K9 Power

K10 Power

Vdd

P7[6]

P7[5]

P7[4]

Vss

Supply voltage.

E7 I/O

E8 I/O

E9 I/O

E10

P2[4] External Analog Ground (AGND) input.

P4[4]

P3[6]

Ground connection.

HCLK OCD high-speed clock output.

Vss

LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection, OCD = On-Chip Debugger.

Figure 8-6. CY8C24094 OCD (Not for Production)

Vss

Vdd

Vss

Vss P2[1] P0[1] P0[7] Vdd P0[2] P2[2] Vss

P4[1] P4[7] P2[7] P0[5] P0[6] P0[0] P2[0] P4[2]

P3[7] P4[5] P2[5] P0[3] P0[4] P2[6] P4[6] P4[0] CClk

NC P4[3] P2[3] Vss

Vss P2[4] P4[4] P3[6] HClk

Vss P5[0] P3[0] XRES P7[1]

ocde P5[7] P3[5] P5[1] Vss

ocdo P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2]

Vss

P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3]

Vss

D +

D -

Vdd P7[7] P7[0] P5[2] Vss

Vdd P7[6] P7[5] P7[4] Vss

Vss

BGA (Top View)

Document Number: 38-12018 Rev. *M

Page 14 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

8.1 100-Pin Part Pinout (On-Chip Debug)

The 100-pin TQFP part is for the CY8C24094 On-Chip Debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production.

Table 8-7. 100-Pin Part Pinout (TQFP)

No.

Name

Description

Name

Description

No connection.

51 I/O

52 I/O

53 I/O

54 I/O

55 I/O

56 I/O

57 I/O

58 I/O

59 I/O

P1[6]

P5[0]

P5[2]

P5[4]

P5[6]

P3[0]

P3[2]

P3[4]

P3[6]

I/O I, M P0[1] Analog column mux input.

I/O

P2[7]

P2[5]

I/O I, M P2[3] Direct switched capacitor block input.

I/O I, M P2[1] Direct switched capacitor block input.

I/O

P4[7]

P4[5]

10 I/O

P4[3]

HCLK OCD high-speed clock output.

I/O

P4[1]

CCLK OCD CPU clock output.

OCDE OCD even data I/O.

OCDO OCD odd data output.

62 Input

63 I/O

64 I/O

XRES Active high pin reset with internal pull down.

P4[0]

P4[2]

No connection.

15 Power

Vss

Ground connection.

65 Power

Vss

Ground connection.

16 I/O

17 I/O

18 I/O

19 I/O

20 I/O

21 I/O

22 I/O

23 I/O

24 I/O

P3[7]

P3[5]

P3[3]

P3[1]

P5[7]

P5[5]

P5[3]

P5[1]

66 I/O

67 I/O

P4[4]

P4[6]

68 I/O I, M P2[0] Direct switched capacitor block input.

69 I/O I, M P2[2] Direct switched capacitor block input.

70 I/O

P2[4] External Analog Ground (AGND) input.

NC No connection.

P2[6] External Voltage Reference (VREF) input.

NC No connection.

P0[0] Analog column mux input.

72 I/O

P1[7] I2C Serial Clock (SCL).

74 I/O

No connection.

77 I/O I, M P0[2] Analog column mux input and column output.

78 NC No connection.

79 I/O I, M P0[4] Analog column mux input and column output.

80 NC No connection.

28 I/O

29 I/O

30 I/O

P1[5] I2C Serial Data (SDA)

P1[3]

P1[1] Crystal (XTALin), I2C Serial Clock (SCL),

ISSP SCLK

No connection.

81 I/O I, M P0[6] Analog column mux input.

32 Power

33 USB

34 USB

35 Power

36 I/O

37 I/O

38 I/O

39 I/O

40 I/O

41 I/O

42 I/O

43 I/O

Vss

Ground connection.

82 Power

Vdd

Vss

Supply voltage.

No connection.

Ground connection.

No connection.

D+

D-

84 Power

Vdd

P7[7]

P7[6]

P7[5]

P7[4]

P7[3]

P7[2]

P7[1]

P7[0]

Supply voltage.

No connection.

95 I/O I, M P0[7] Analog column mux input.

96 NC No connection.

97 I/O I/O, P0[5] Analog column mux input and column output.

48 I/O

49 I/O

50 I/O

P1[0] Crystal (XTALout), I2C Serial Data (SDA),

No connection.

ISSP SDATA

P1[2]

99 I/O I/O, P0[3] Analog column mux input and column output.

P1[4] Optional External Clock Input (EXTCLK).

100

No connection.

Document Number: 38-12018 Rev. *M

Page 15 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

Table 8-7. 100-Pin Part Pinout (TQFP) (continued)

LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input, OCD = On-Chip Debugger.

Figure 8-7. CY8C24094 OCD (Not for Production)

P0[0],M,AI

AI, M,P0[1]

M,P2[7]

M,P2[5]

AI, M,P2[3]

AI, M,P2[1]

M,P4[7]

M,P4[5]

M,P4[3]

M,P4[1]

OCDE

P2[6],M,External VREF

P2[4],M,External AGND

P2[2],M,AI

P2[0],M,AI

P4[6],M

P4[4],M

Vss

P4[2],M

OCDO

TQFP

P4[0],M

XRES

Vss

M,P3[7]

M,P3[5]

CCLK

HCLK

P3[6],M

P3[4],M

P3[2],M

P3[0],M

P5[6],M

M,P3[3]

M,P3[1]

M,P5[7]

M,P5[5]

P5[4],M

P5[2],M

P5[0],M

M,P5[3]

M,P5[1]

I2C SCL,P1[7]

P1[6],M

Document Number: 38-12018 Rev. *M

Page 16 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

9. Register Reference

This section lists the registers of the CY8C24x94 PSoC device family. For detailed register information, reference the

PSoC Programmable System-on-Chip Technical Reference Manual.

9.1 Register Conventions

9.2 Register Mapping Tables

The register conventions specific to this section are listed in the

following table.

The PSoC device has a total register address space of 512

bytes. The register space is referred to as I/O space and is

divided into two banks. The XOI bit in the Flag register (CPU_F)

determines which bank the user is currently in. When the XOI bit

is set the user is in Bank 1.

Convention

Description

Read register or bit(s)

Note In the following register mapping tables, blank fields are

Reserved and should not be accessed.

Write register or bit(s)

Logical register or bit(s)

Clearable register or bit(s)

Access is bit specific

Document Number: 38-12018 Rev. *M

Page 17 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

9.3 Register Map Bank 0 Table: User Space

Name

PRT0DR

Addr (0,Hex) Access

Name

Addr (0,Hex) Access

Name

ASC10CR0

Addr (0,Hex) Access

Name

Addr (0,Hex)

Access

PMA0_DR

PRT0IE

PMA1_DR

PMA2_DR

PMA3_DR

PMA4_DR

PMA5_DR

PMA6_DR

PMA7_DR

USB_SOF0

USB_SOF1

USB_CR0

USBI/O_CR0

USBI/O_CR1

ASC10CR1

ASC10CR2

ASC10CR3

ASD11CR0

ASD11CR1

ASD11CR2

ASD11CR3

PRT0GS

PRT0DM2

PRT1DR

PRT1IE

PRT1GS

PRT1DM2

PRT2DR

PRT2IE

PRT2GS

PRT2DM2

PRT3DR

PRT3IE

PRT3GS

PRT3DM2

PRT4DR

PRT4IE

EP1_CNT1

EP1_CNT

EP2_CNT1

EP2_CNT

EP3_CNT1

EP3_CNT

EP4_CNT1

EP4_CNT

EP0_CR

ASD20CR0

ASD20CR1

ASD20CR2

ASD20CR3

ASC21CR0

ASC21CR1

ASC21CR2

ASC21CR3

CUR_PP

STK_PP

PRT4GS

PRT4DM2

PRT5DR

PRT5IE

IDX_PP

MVR_PP

MVW_PP

I2C_CFG

I2C_SCR

I2C_DR

PRT5GS

PRT5DM2

EP0_CNT

EP0_DR0

EP0_DR1

EP0_DR2

EP0_DR3

EP0_DR4

EP0_DR5

EP0_DR6

EP0_DR7

AMX_IN

I2C_MSCR

INT_CLR0

INT_CLR1

INT_CLR2

INT_CLR3

INT_MSK3

INT_MSK2

INT_MSK0

INT_MSK1

INT_VC

PRT7DR

PRT7IE

PRT7GS

PRT7DM2

DBB00DR0

DBB00DR1

DBB00DR2

DBB00CR0

DBB01DR0

DBB01DR1

DBB01DR2

DBB01CR0

DCB02DR0

DCB02DR1

DCB02DR2

DCB02CR0

DCB03DR0

DCB03DR1

DCB03DR2

DCB03CR0

AMUXCFG

ARF_CR

CMP_CR0

ASY_CR

CMP_CR1

RES_WDT

DEC_DH

DEC_DL

DEC_CR0

DEC_CR1

MUL0_X

MUL1_X

MUL1_Y

MUL0_Y

MUL1_DH

MUL1_DL

ACC1_DR1

ACC1_DR0

ACC1_DR3

ACC1_DR2

RDI0RI

MUL0_DH

MUL0_DL

ACC0_DR1

ACC0_DR0

ACC0_DR3

ACC0_DR2

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

ACB00CR3

ACB00CR0

ACB00CR1

ACB00CR2

ACB01CR3

ACB01CR0

ACB01CR1

ACB01CR2

RDI0SYN

RDI0IS

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

CPU_F

DAC_D

CPU_SCR1

CPU_SCR0

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

Document Number: 38-12018 Rev. *M

Page 18 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

9.4 Register Map Bank 1 Table: Configuration Space

Name

PRT0DM0

PRT0DM1

PRT0IC0

PRT0IC1

PRT1DM0

PRT1DM1

PRT1IC0

PRT1IC1

PRT2DM0

PRT2DM1

PRT2IC0

PRT2IC1

PRT3DM0

PRT3DM1

PRT3IC0

PRT3IC1

PRT4DM0

PRT4DM1

PRT4IC0

PRT4IC1

PRT5DM0

PRT5DM1

PRT5IC0

PRT5IC1

Addr (1,Hex) Access

Name

Addr (1,Hex) Access

Name

ASC10CR0

ASC10CR1

ASC10CR2

ASC10CR3

ASD11CR0

ASD11CR1

ASD11CR2

ASD11CR3

Addr (1,Hex) Access

Name

USBI/O_CR2

USB_CR1

Addr(1,Hex) Access

PMA0_WA

PMA1_WA

PMA2_WA

PMA3_WA

PMA4_WA

PMA5_WA

PMA6_WA

PMA7_WA

EP1_CR0

EP2_CR0

EP3_CR0

EP4_CR0

PMA0_RA

PMA1_RA

PMA2_RA

PMA3_RA

PMA4_RA

PMA5_RA

PMA6_RA

PMA7_RA

GDI_O_IN

GDI_E_IN

GDI_O_OU

GDI_E_OU

ASD20CR1

ASD20CR2

ASD20CR3

ASC21CR0

ASC21CR1

ASC21CR2

ASC21CR3

MUX_CR0

MUX_CR1

MUX_CR2

MUX_CR3

PRT7DM0

PRT7DM1

PRT7IC0

PRT7IC1

DBB00FN

DBB00IN

DBB00OU

OSC_GO_EN

OSC_CR4

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

CLK_CR0

CLK_CR1

ABF_CR0

AMD_CR0

CMP_GO_EN

DBB01FN

DBB01IN

DBB01OU

VLT_CMP

AMD_CR1

ALT_CR0

DCB02FN

DCB02IN

DCB02OU

IMO_TR

ILO_TR

BDG_TR

ECO_TR

MUX_CR4

MUX_CR5

DCB03FN

DCB03IN

DCB03OU

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

ACB00CR3

ACB00CR0

ACB00CR1

ACB00CR2

ACB01CR3

ACB01CR0

ACB01CR1

ACB01CR2

RDI0RI

RDI0SYN

RDI0IS

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

CPU_F

DAC_CR

CPU_SCR1

CPU_SCR0

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

Document Number: 38-12018 Rev. *M

Page 19 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

10. Electrical Specifications

This section presents the DC and AC electrical specifications of the CY8C24x94 PSoC device family. For the most up to date electrical

specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.

Specifications are valid for -40 C ≤ T ≤ 85 C and T ≤ 100 C, except where noted. Specifications for devices running at greater than

12 MHz are valid for -40 C ≤ T ≤ 70 C and T ≤ 82 C.

Figure 10-1. Voltage versus CPU Frequency

5.25

4.75

3.00

93 kHz

12 MHz

24 MHz

CPU Frequency

The following table lists the units of measure that are used in this chapter.

Table 10-1. Units of Measure

Symbol

Unit of Measure

degree Celsius

Symbol

μW

Unit of Measure

microwatts

decibels

milli-ampere

milli-second

milli-volts

femto farad

hertz

Kbit

kHz

kΩ

1024 bytes

1024 bits

nanoampere

nanosecond

nanovolts

kilohertz

kilohm

ohm

MHz

MΩ

μA

μF

μH

μs

μV

μVrms

megahertz

megaohm

ppm

picoampere

picofarad

microampere

microfarad

microhenry

microsecond

microvolts

peak-to-peak

parts per million

picosecond

sps

samples per second

sigma: one standard deviation

volts

microvolts root-mean-square

Document Number: 38-12018 Rev. *M

Page 20 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

10.1 Absolute Maximum Ratings

Table 10-2. Absolute Maximum Ratings

Symbol

Description

Storage Temperature

Min

-55

Typ

Max

+100

Units

Notes

Higher storage temperatures

STG

reduces data retention time. Recom-

mended storage temperature is

+25 C ± 25 C. Extended duration

storage temperatures above 65 C

degrades reliability.

Ambient Temperature with Power Applied

Supply Voltage on Vdd Relative to Vss

DC Input Voltage

-40

–

+85

Vdd

-0.5

+6.0

Vss -

0.5

Vdd +

0.5

I/O

DC Voltage Applied to Tri-state

Vss -

0.5

–

Vdd +

0.5

I/O2

Maximum Current into any Port Pin

-25

-50

–

+50

MI/O

Maximum Current into any Port Pin

Configured as Analog Driver

MAI/O

ESD

Electro Static Discharge Voltage

Latch-up Current

2000

–

Human Body Model ESD.

200

10.2 Operating Temperature

Table 10-3. Operating Temperature

Symbol

Description

Ambient Temperature

Min

-40

Typ

Max

+85

Units

Notes

–

Ambient Temperature using USB

Junction Temperature

-10

–

+85

AUSB

-40

+100

The temperature rise from ambient to

junction is package specific. See

Thermal Impedance on page 41. The

user must limit the power

consumption to comply with this

requirement.

Document Number: 38-12018 Rev. *M

Page 21 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

10.3 DC Electrical Characteristics

10.3.1 DC Chip Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 10-4. DC Chip-Level Specifications

Symbol

Vdd

Description

Min

3.0

Typ

Max

5.25

Units

Notes

Supply Voltage

–

See DC POR and LVD specifications,

T a ble 10-14 on page 28.

Conditions are Vdd = 5.0V, T = 25 C,

Supply Current, IMO = 24 MHz (5V)

Supply Current, IMO = 24 MHz (3.3V)

–

DD5

DD3

CPU = 3 MHz, SYSCLK doubler

disabled, VC1 = 1.5 MHz, VC2 = 93.75

kHz, VC3 = 93.75 kHz, analog power =

off.

–

Conditions are Vdd = 3.3V, T = 25 C,

CPU = 3 MHz, SYSCLK doubler

disabled, VC1 = 1.5 MHz, VC2 = 93.75

kHz, VC3 = 0.367 kHz, analog power =

off.

Sleep (Mode) Current with POR, LVD, Sleep –

Timer, and WDT.

6.5

μA

Conditions are with internal slow speed

[3]

oscillator, Vdd = 3.3V, -40 C ≤ T ≤ 55

C, analog power = off.

Sleep (Mode) Current with POR, LVD, Sleep –

μA

Conditions are with internal slow speed

SBH

[3]

Timer, and WDT at high temperature.

oscillator, Vdd = 3.3V, 55 C < T ≤ 85

C, analog power = off.

10.3.2 DC General Purpose I/O Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 10-5. DC GPI/O Specifications

Symbol

Description

Pull-Up Resistor

Pull-Down Resistor

High Output Level

Min

Typ

5.6

–

Max

Units

kΩ

Notes

–

Vdd -

1.0

I/OH = 10 mA, Vdd = 4.75 to 5.25V (8

total loads, 4 on even port pins (for

example, P0[2], P1[4]), 4 on odd port

pins (for example, P0[3], P1[5])). 80

mA maximum combined I/OH budget.

Low Output Level

–

0.75

0.8

I/OL = 25 mA, Vdd = 4.75 to 5.25V (8

total loads, 4 on even port pins (for

example, P0[2], P1[4]), 4 on odd port

pins (for example, P0[3], P1[5])). 200

mA maximum combined I/OL budget.

Vdd = 3.0 to 5.25.

Input Low Level

Input High Level

Input Hysterisis

Input Leakage (Absolute Value)

Capacitive Load on Pins as Input

–

2.1

–

3.5

–

Gross tested to 1 μA.

Package and pin dependent.

Temp = 25 C.

Capacitive Load on Pins as Output

–

3.5

Package and pin dependent.

Temp = 25 C.

OUT

Note

3. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar

functions enabled.

Document Number: 38-12018 Rev. *M

Page 22 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

10.3.3 DC Full-Speed USB Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -10°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -10°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 10-6. DC Full-Speed (12 Mbps) USB Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

USB Interface

Differential Input Sensitivity

0.2

–

| (D+) - (D-) |

Differential Input Common Mode Range

Single Ended Receiver Threshold

Transceiver Capacitance

0.8

–

2.5

2.0

μA

High-Z State Data Line Leakage

External USB Series Resistor

Static Output High, Driven

-10

2.8

0V < V < 3.3V.

I/O

In series with each USB pin.

EXT

3.6

15 kΩ ± 5% to Ground. Internal pull-up

enabled.

UOH

Static Output High, Idle

Static Output Low

2.7

–

3.6

0.3

15 kΩ ± 5% to Ground. Internal pull-up

enabled.

UOHI

UOL

15 kΩ ± 5% to Ground. Internal pull-up

enabled.

USB Driver Output Impedance

D+/D- Crossover Voltage

–

Including R

Resistor.

EXT

1.3

2.0

CRS

10.3.4 DC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC

blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.

Table 10-7. 5V DC Operational Amplifier Specifications

Symbol

Description

Min

Typ

1.6

1.3

1.2

Max

7.5

Units

Notes

Input Offset Voltage (absolute value)

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

OSOA

–

TCV

Average Input Offset Voltage Drift

7.0

35.0

–

μV/ C

OSOA

Input Leakage Current (Port 0 Analog Pins)

Input Capacitance (Port 0 Analog Pins)

Gross tested to 1 μA.

Package and pin dependent. Temp =

EBOA

4.5

9.5

INOA

25 C.

Common Mode Voltage Range

Common Mode Voltage Range (high power

or high opamp bias)

0.0

0.5

–

Vdd

Vdd -

0.5

The common-mode input voltage

range is measured through an analog

output buffer. The specification

includes the limitations imposed by

the characteristics of the analog

output buffer.

CMOA

Open Loop Gain

–

OLOA

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

Document Number: 38-12018 Rev. *M

Page 23 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

Table 10-7. 5V DC Operational Amplifier Specifications (continued)

Symbol

Description

Min

Typ

Max

Units

Notes

High Output Voltage Swing (internal signals)

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

OHIGHO

Vdd -

0.2

Vdd -

–

0.2

Vdd -

0.5

Low Output Voltage Swing (internal signals)

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = High

OLOWOA

–

0.2

0.5

Power = High, Opamp Bias = High

Supply Current (including associated AGND

buffer)

SOA

–

400

500

800

1200

2400

4600

800

900

1000

1600

3200

6400

μA

Power = Low, Opamp Bias = Low

Power = Low, Opamp Bias = High

Power = Medium, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = Low

Power = High, Opamp Bias = High

PSRR

Supply Voltage Rejection Ratio

–

Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd -

1.25V) ≤ VIN ≤ Vdd.

10.3.5 DC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters

apply to 5V at 25°C and are for design guidance only.

Table 10-8. DC Low Power Comparator Specifications

Symbol

Description

Min

0.2

Typ

Max

Units

Notes

Low power comparator (LPC) reference

voltage range

–

Vdd - 1 V

REFLPC

LPC supply current

LPC voltage offset

–

μA

SLPC

2.5

OSLPC

Document Number: 38-12018 Rev. *M

Page 24 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

10.3.6 DC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 10-9. 5V DC Analog Output Buffer Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

Input Offset Voltage (Absolute Value)

Average Input Offset Voltage Drift

–

OSOB

TCV

μV/°C

OSO

Common-Mode Input Voltage Range

0.5

–

Vdd - 1.0

CMOB

Output Resistance

Power = Low

Power = High

OUTOB

–

0.6

–

High Output Voltage Swing (Load = 32 ohms

to Vdd/2)

Power = Low

Power = High

OHIGHO

0.5 x Vdd +

1.1

0.5 x Vdd +

1.1

–

Low Output Voltage Swing (Load = 32 ohms

to Vdd/2)

Power = Low

OLOWOB

–

0.5 x Vdd -

1.3

Power = High

0.5 x Vdd -

1.3

Supply Current Including Bias Cell (No Load)

Power = Low

Power = High

SOB

–

1.1

2.6

5.1

8.8

PSRR

Supply Voltage Rejection Ratio

–

(0.5 x Vdd - 1.3) ≤ V

(Vdd - 2.3).

≤

OUT

Table 10-10. 3.3V DC Analog Output Buffer Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

Input Offset Voltage (Absolute Value)

Average Input Offset Voltage Drift

Common-Mode Input Voltage Range

–

OSOB

TCV

–

μV/°C

OSOB

0.5

Vdd - 1.0

CMOB

Output Resistance

Power = Low

Power = High

OUTOB

–

High Output Voltage Swing (Load = 1K ohms

to Vdd/2)

Power = Low

Power = High

OHIGHO

OLOWOB

SOB

0.5 x Vdd +

1.0

0.5 x Vdd +

1.0

–

Low Output Voltage Swing (Load = 1K ohms

to Vdd/2)

Power = Low

Power = High

–

0.5 x Vdd -

1.0

0.5 x Vdd -

1.0

Supply Current Including Bias Cell (No Load)

Power = Low

Power = High

0.8

2.0

4.3

–

PSRR

Supply Voltage Rejection Ratio

–

(0.5 x Vdd - 1.0) ≤ V

(0.5 x Vdd + 0.9).

≤

OUT

Document Number: 38-12018 Rev. *M

Page 25 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

10.3.7 DC Analog Reference Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to

the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control

register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.

Reference control power is high.

Table 10-11. 5V DC Analog Reference Specifications

Symbol

Description

Min

Typ

Max

Units

–

Bandgap Voltage Reference

1.28

1.30

1.32

AGND = Vdd/2

Vdd/2 - 0.04

2 x BG - 0.048

P2[4] - 0.011

BG - 0.009

Vdd/2 - 0.01

2 x BG - 0.030

P2[4]

Vdd/2 + 0.007

2 x BG + 0.024

P2[4] + 0.011

BG + 0.016

–

AGND = 2 x BandGap

[4 , 5]

–

AGND = P2[4] (P2[4] = Vdd/2)

[4, 5]

–

AGND = BandGap

BG + 0.008

1.6 x BG - 0.010

0.000

–

AGND = 1.6 x BandGap

1.6 x BG - 0.022

-0.034

1.6 x BG + 0.018

0.034

–

AGND Block to Block Variation (AGND = Vdd/2)

RefHi = Vdd/2 + BandGap

–

Vdd/2 + BG - 0.10 Vdd/2 + BG

Vdd/2 + BG + 0.10

3 x BG + 0.06

–

RefHi = 3 x BandGap

3 x BG - 0.06

3 x BG

–

RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)

2 x BG + P2[6] -

0.113

2 x BG + P2[6] -

0.018

2 x BG + P2[6] +

0.077

–

RefHi = P2[4] + BandGap (P2[4] = Vdd/2)

P2[4] + BG - 0.130 P2[4] + BG - 0.016 P2[4] + BG + 0.098 V

RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] -

0.133

P2[4] + P2[6] -

0.016

P2[4] + P2[6]+

0.100

–

RefHi = 3.2 x BandGap

3.2 x BG - 0.112

3.2 x BG

3.2 x BG + 0.076

RefLo = Vdd/2 – BandGap

RefLo = BandGap

Vdd/2 - BG - 0.04 Vdd/2 - BG + 0.024 Vdd/2 - BG + 0.04

BG - 0.06

BG + 0.06

RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)

2 x BG - P2[6] -

0.084

2 x BG - P2[6] +

0.025

2 x BG - P2[6] +

0.134

–

RefLo = P2[4] – BandGap (P2[4] = Vdd/2)

P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107 V

RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] -

0.057

P2[4] - P2[6] +

0.026

P2[4] - P2[6] +

0.110

Table 10-12. 3.3V DC Analog Reference Specifications

Symbol

Description

Bandgap Voltage Reference

Min

Typ

1.30

Max

1.32

Units

–

1.28

[4 , 5]

AGND = Vdd/2

AGND = 2 x BandGap

Vdd/2 - 0.03

Not Allowed

P2[4] - 0.008

BG - 0.009

1.6 x BG - 0.027

-0.034

Vdd/2 - 0.01

Vdd/2 + 0.005

[4, 5]

–

AGND = P2[4] (P2[4] = Vdd/2)

P2[4] + 0.001

BG + 0.005

1.6 x BG - 0.010

0.000

P2[4] + 0.009

BG + 0.015

1.6 x BG + 0.018

0.034

–

AGND = BandGap

–

AGND = 1.6 x BandGap

–

AGND Column to Column Variation (AGND =

Vdd/2)

–

RefHi = Vdd/2 + BandGap

Not Allowed

RefHi = 3 x BandGap

RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)

RefHi = P2[4] + BandGap (P2[4] = Vdd/2)

RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + P2[6] -

0.075

P2[4] + P2[6] -

0.009

P2[4] + P2[6] +

0.057

Document Number: 38-12018 Rev. *M

Page 26 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

Table 10-12. 3.3V DC Analog Reference Specifications (continued)

Symbol

Description

RefHi = 3.2 x BandGap

Min

Not Allowed

Typ

Max

Units

–

RefLo = Vdd/2 - BandGap

RefLo = BandGap

RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)

RefLo = P2[4] – BandGap (P2[4] = Vdd/2)

RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] -

0.048

P2[4]- P2[6] +

0.022

P2[4] - P2[6] +

0.092

10.3.8 DC Analog PSoC Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 10-13. DC Analog PSoC Block Specifications

Symbol

Description

Min

Typ

12.2

Max

Units

kΩ

Notes

Resistor Unit Value (Continuous Time)

Capacitor Unit Value (Switched Capacitor)

–

Note

4. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.

5. Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling of the digital signal may appear on the

AGND.

Document Number: 38-12018 Rev. *M

Page 27 of 47

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CY8C24894, CY8C24994

10.3.9 DC POR and LVD Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V or 3.3V at 25°C and are

for design guidance only.

Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Programmable System-on-Chip

Technical Reference Manual for more information on the VLT_CR register.

Table 10-14. DC POR and LVD Specifications

Symbol

Description

Min

Typ

2.91

4.39

4.55

Max

Units

Notes

Vdd Value for PPOR Trip (positive ramp)

PORLEV[1:0] = 00b

PORLEV[1:0] = 01b

PPOR0R

PPOR1R

PPOR2R

–

PORLEV[1:0] = 10b

Vdd Value for PPOR Trip (negative ramp)

PORLEV[1:0] = 00b

PORLEV[1:0] = 01b

2.82

4.39

4.55

PPOR0

PPOR1

PPOR2

PORLEV[1:0] = 10b

PPOR Hysteresis

PORLEV[1:0] = 00b

PORLEV[1:0] = 01b

PORLEV[1:0] = 10b

–

PH0

PH1

PH2

Vdd Value for LVD Trip

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

[6]

[7]

2.86

2.96

3.07

3.92

4.39

4.55

4.63

4.72

2.92

3.02

3.13

4.00

4.48

4.64

4.73

4.81

2.98

3.08

3.20

4.08

4.57

4.74

4.82

4.91

LVD0

LVD1

LVD2

LVD3

LVD4

LVD5

LVD6

LVD7

Notes

6. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.

7. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.

Document Number: 38-12018 Rev. *M

Page 28 of 47

Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.

CY8C24094, CY8C24794

CY8C24894, CY8C24994

10.3.10 DC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 10-15. DC Programming Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

Supply Current During Programming or Verify

–

DDP

Input Low Voltage During Programming or

Verify

–

0.8

ILP

Input High Voltage During Programming or

Verify

2.1

–

IHP

Input Current when Applying Vilp to P1[0] or

P1[1] During Programming or Verify

0.2

1.5

Driving internal pull-down

resistor.

ILP

Input Current when Applying Vihp to P1[0] or

P1[1] During Programming or Verify

–

Driving internal pull-down

resistor.

IHP

Output Low Voltage During Programming or

Verify

–

Vss +

0.75

OLV

Output High Voltage During Programming or Vdd- 1.0 –

Verify

Vdd

OHV

Flash

Flash Endurance (per block)

50,000

–

Erase/write cycles per block.

Erase/write cycles.

ENP

ENT

[8]

Flash

Flash Endurance (total)

1,800,0

–

Flash

Flash Data Retention

–

Years

Note

8. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks

of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees

more than 50,000 cycles).

For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.

Document Number: 38-12018 Rev. *M

Page 29 of 47

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10.4 AC Electrical Characteristics

10.4.1 AC Chip-Level Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 10-16. AC Chip-Level Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

[9,10]

Internal Main Oscillator Frequency for 24 MHz 23.04 24

(5V)

24.96

MHz

Trimmed for 5V operation

using factory trim values.

IMO245V

IMO243V

IMOUSB5

[10,1 1]

Internal Main Oscillator Frequency for 24 MHz 22.08 24

(3.3V)

25.92

24.06

MHz

Trimmed for 3.3V operation

using factory trim values.

[10]

Internal Main Oscillator Frequency with USB 23.94 24

-10°C ≤ T ≤ 85°C

4.35 ≤ Vdd ≤ 5.15

(5V)

Frequency locking enabled and USB traffic

present.

[10]

Internal Main Oscillator Frequency with USB 23.94 24

24.06

MHz

-0°C ≤ T ≤ 70°C

3.15 ≤ Vdd ≤ 3.45

IMOUSB3

(3.3V)

Frequency locking enabled and USB traffic

present.

[9,10]

CPU Frequency (5V Nominal)

0.93

24.96

12.96

49.92

MHz

CPU1

CPU2

BLK5

[10,1 1]

[9,10,12]

CPU Frequency (3.3V Nominal)

Digital PSoC Block Frequency (5V Nominal)

Refer to the AC Digital Block

Specifications.

[10,12]

Digital PSoC Block Frequency (3.3V Nominal) 0

Internal Low Speed Oscillator Frequency 15

25.92

MHz

kHz

BLK3

32K1

Jitter32k 32 kHz Period Jitter

–

100

Step24M 24 MHz Trim Step Size

Fout48M 48 MHz Output Frequency

–

kHz

MHz

[9,1 1]

46.08 48.0

49.92

Trimmed. Utilizing factory

trim values.

Jitter24M 24 MHz Period Jitter (IMO) Peak-to-Peak

–

300

–

Maximum frequency of signal on row input or

row output.

12.96

–

MHz

μs

MAX

Supply Ramp Time

–

RAMP

Figure 10-2. 24 MHz Period Jitter (IMO) Timing Diagram

Jitter24M1

F_24M

Notes

9. 4.75V < Vdd < 5.25V.

10. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.

11. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation

at 3.3V.

12. See the individual user module data sheets for information on maximum frequencies for user modules

Document Number: 38-12018 Rev. *M

Page 30 of 47

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10.0.1 AC General Purpose I/O Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 10-17. AC GPI/O Specifications

Symbol

Description

Min

Typ

Max

Units

MHz

Notes

GPI/O Operating Frequency

–

Normal Strong Mode

GPI/O

TRiseF

Rise Time, Normal Strong Mode, Cload = 50 pF 3

Fall Time, Normal Strong Mode, Cload = 50 pF 2

–

Vdd = 4.5 to 5.25V, 10% - 90%

Vdd = 3 to 5.25V, 10% - 90%

TFallF

TRiseS

TFallS

Rise Time, Slow Strong Mode, Cload = 50 pF 10

Fall Time, Slow Strong Mode, Cload = 50 pF 10

–

Figure 10-3. GPI/O Timing Diagram

90%

GPIO

Output

Voltage

10%

TRiseF

TRiseS

TFallF

TFallS

10.0.1 AC Full-Speed USB Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -10°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -10°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 10-18. AC Full-Speed (12 Mbps) USB Specifications

Symbol Description Min

Transition Rise Time

Transition Fall Time

Rise/Fall Time Matching: (T /T )

Typ

Max

Units

Notes

For 50 pF load.

–

RFS

For 50 pF load.

FSS

111

RFMFS

DRATEFS

Full-Speed Data Rate

12 -

12 +

Mbps

0.25%

Document Number: 38-12018 Rev. *M

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10.0.2 AC Operational Amplifier Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.

Power = High and Opamp Bias = High is not supported at 3.3V.

Table 10-19. 5V AC Operational Amplifier Specifications

Symbol

Description

Min

Typ

Max

Units

Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10

pF load, Unity Gain)

ROA

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

–

3.9

0.72

0.62

μs

Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10

pF load, Unity Gain)

SOA

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

–

5.9

0.92

0.72

μs

Rising Slew Rate (20% to 80%)(10 pF load, Unity

Gain)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

ROA

0.15

1.7

6.5

–

V/μs

Falling Slew Rate (20% to 80%)(10 pF load, Unity

Gain)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

FOA

0.01

0.5

4.0

–

V/μs

Gain Bandwidth Product

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

Power = High, Opamp Bias = High

0.75

3.1

5.4

–

MHz

Noise at 1 kHz (Power = Medium, Opamp Bias = High) –

100

–

nV/rt-Hz

NOA

Table 10-20. 3.3V AC Operational Amplifier Specifications

Symbol

Description

Min

Typ

Max

Units

Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10

pF load, Unity Gain)

ROA

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

–

3.92

0.72

μs

Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10

pF load, Unity Gain)

SOA

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

–

5.41

0.72

μs

Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain)

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

ROA

0.31

2.7

–

V/μs

Falling Slew Rate (20% to 80%)(10 pF load, Unity

Gain)

Power = Low, Opamp Bias = Low

FOA

0.24

1.8

–

V/μs

Power = Medium, Opamp Bias = High

Gain Bandwidth Product

Power = Low, Opamp Bias = Low

Power = Medium, Opamp Bias = High

0.67

2.8

–

MHz

Noise at 1 kHz (Power = Medium, Opamp Bias = High) –

100

–

nV/rt-Hz

NOA

Document Number: 38-12018 Rev. *M

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When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up

to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.

Figure 10-4. Typical AGND Noise with P2[4] Bypass

dBV/rtHz

10000

0.01

0.1

1.0

1000

100

0.001

0.01

0.1 Freq (kHz)

100

At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high

frequencies, increased power level reduces the noise spectrum level.

Figure 10-5. Typical Opamp Noise

nV/rtHz

10000

PH_BH

PH_BL

PM_BL

PL_BL

1000

100

0.001

0.01

0.1

100

Freq (kHz)

Document Number: 38-12018 Rev. *M

Page 33 of 47

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10.0.1 AC Low Power Comparator Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters

apply to 5V at 25°C and are for design guidance only.

Table 10-21. AC Low Power Comparator Specifications

Symbol

Description

LPC response time

Min

Typ

Max

Units

Notes

–

μs

≥ 50 mV overdrive comparator

reference set within V

RLPC

REFLPC

10.0.2 AC Digital Block Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 10-22. AC Digital Block Specifications

Function

Description

Capture Pulse Width

Min

Typ

Max

Units

Notes

Timer

–

Maximum Frequency, No Capture

Maximum Frequency, With Capture

–

49.92 MHz

25.92 MHz

4.75V < Vdd < 5.25V.

–

Counter Enable Pulse Width

Maximum Frequency, No Enable Input

–

49.92 MHz

25.92 MHz

4.75V < Vdd < 5.25V.

Maximum Frequency, Enable Input

Kill Pulse Width:

–

Dead

Band

Asynchronous Restart Mode

Synchronous Restart Mode

Disable Mode

–

Maximum Frequency

49.92 MHz

4.75V < Vdd < 5.25V.

CRCPRS Maximum Input Clock Frequency

–

(PRS

Mode)

CRCPRS Maximum Input Clock Frequency

(CRC

Mode)

–

24.6

8.2

MHz

SPIM

Maximum Input Clock Frequency

–

Maximum data rate at 4.1 MHz due

to 2 x over clocking.

SPIS

–

4.1

–

MHz

Width of SS_ Negated Between Transmissions 50

Trans-

mitter

Maximum Input Clock Frequency

–

24.6

MHz

Maximum data rate at 3.08 MHz

due to 8 x over clocking.

Receiver Maximum Input Clock Frequency

–

24.6

MHz

Maximum data rate at 3.08 MHz

due to 8 x over clocking.

Note

13. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

Document Number: 38-12018 Rev. *M

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10.0.3 AC External Clock Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 10-23. AC External Clock Specifications

Symbol

Description

Frequency for USB Applications

Duty Cycle

Min

23.94

Typ

Max

24.06

Units

MHz

Notes

OSCEXT

–

Power up to IMO Switch

150

–

μs

10.0.4 AC Analog Output Buffer Specifications

The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 10-24. 5V AC Analog Output Buffer Specifications

Symbol

Description

Min

Typ

Max

2.5

Units

Notes

Rising Settling Time to 0.1%, 1V Step, 100pF

ROB

Load

Power = Low

Power = High

–

μs

2.5

Falling Settling Time to 0.1%, 1V Step, 100pF

Load

Power = Low

Power = High

SOB

–

2.2

μs

Rising Slew Rate (20% to 80%), 1V Step, 100

pF Load

Power = Low

Power = High

ROB

0.65

–

V/μs

Falling Slew Rate (80% to 20%), 1V Step, 100

pF Load

Power = Low

Power = High

FOB

0.65

–

V/μs

Small Signal Bandwidth, 20mV , 3dB BW,

OBSS

OBLS

100 pF Load

Power = Low

Power = High

0.8

–

MHz

Large Signal Bandwidth, 1V , 3dB BW, 100

pF Load

300

–

kHz

Power = Low

Power = High

Document Number: 38-12018 Rev. *M

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Table 10-25. 3.3V AC Analog Output Buffer Specifications

Symbol

Description

Min

Typ

Max

3.8

Units

Notes

Rising Settling Time to 0.1%, 1V Step, 100 pF

ROB

Load

Power = Low

Power = High

–

μs

3.8

Falling Settling Time to 0.1%, 1V Step, 100 pF

Load

Power = Low

Power = High

SOB

–

2.6

μs

Rising Slew Rate (20% to 80%), 1V Step, 100

pF Load

Power = Low

Power = High

ROB

0.5

–

V/μs

Falling Slew Rate (80% to 20%), 1V Step, 100

pF Load

Power = Low

Power = High

FOB

0.5

–

V/μs

Small Signal Bandwidth, 20mV , 3dB BW,

OBSS

OBLS

100 pF Load

Power = Low

Power = High

0.7

–

MHz

Large Signal Bandwidth, 1V , 3dB BW, 100

pF Load

200

–

kHz

Power = Low

Power = High

10.0.5 AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 10-26. AC Programming Specifications

Symbol

Description

Rise Time of SCLK

Min

Typ

Max

Units

Notes

–

RSCLK

FSCLK

SSCLK

HSCLK

SCLK

Fall Time of SCLK

–

Data Set up Time to Falling Edge of SCLK

Data Hold Time from Falling Edge of SCLK 40

–

Frequency of SCLK

–

MHz

Flash Erase Time (Block)

–

ERASEB

WRITE

DSCLK

DSCLK3

Flash Block Write Time

–

Data Out Delay from Falling Edge of SCLK

Vdd > 3.6

3.0 ≤ Vdd ≤ 3.6

–

Document Number: 38-12018 Rev. *M

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10.0.6 AC I C Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and

are for design guidance only.

Table 10-27. AC Characteristics of the I C SDA and SCL Pins for Vdd

Standard Mode

Fast Mode

Min Max

Symbol

Description

Units

kHz

Notes

Min

Max

100

SCL Clock Frequency

400

–

SCLI2C

Hold Time (repeated) START Condition. After 4.0

this period, the first clock pulse is generated.

–

0.6

μs

HDSTAI2

LOW Period of the SCL Clock

HIGH Period of the SCL Clock

4.7

4.0

–

1.3

0.6

–

μs

LOWI2C

HIGHI2C

SUSTAI2

Set-up Time for a Repeated START Condition 4.7

Data Hold Time

–

μs

HDDATI2

SUDATI2

SUSTOI2

BUFI2C

SPI2C

[14]

Data Set-up Time

250

4.0

100

0.6

1.3

–

Set-up Time for STOP Condition

–

Bus Free Time Between a STOP and START 4.7

Condition

–

Pulse Width of spikes are suppressed by the

input filter.

–

Figure 10-6. Definition for Timing for Fast/Standard Mode on the I C Bus

SDA

SCL

T_SPI2C

T_LOWI2C

T_SUDATI2C

T_HDSTAI2C

T_BUFI2C

T_SUSTOI2C

T_SUSTAI2C

T_HDDATI2C

T_HDSTAI2C

T_HIGHI2C

Note

14. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t

Š 250 ns must then be met. This automatically is the case

SU;DAT

if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the

SDA line t + t = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

rmax

SU;DAT

Document Number: 38-12018 Rev. *M

Page 37 of 47

http://www.cypress.com/design/MR10161.

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CY8C24894, CY8C24994

11. Packaging Dimensions

This section illustrates the package specification for the CY8C24x94 PSoC devices, along with the thermal impedance for the package

and solder reflow peak temperatures.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of

the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at

Figure 11-1. 56-Pin (8x8 mm) QFN

001-12921 **

Document Number: 38-12018 Rev. *M

Page 38 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

Figure 11-2. 68-Pin (8x8 mm x 0.89 mm) QFN

51-85214 *C

Important Note

■ For information on the preferred dimensions for mounting QFN packages, see the following Application Note at

http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.

■ Pinned vias for thermal conduction are not required for the low-power PSoC device.

Figure 11-3. 68-Pin SAWN QFN (8X8 mm X 0.90 mm)

001-09618 *A

Document Number: 38-12018 Rev. *M

Page 39 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

Figure 11-4. 100-Ball (6x6 mm) VFBGA

51-85209 *B

Figure 11-5. 100-Pin (14x14 x 1.4 mm) TQFP

51-85048 *C

Document Number: 38-12018 Rev. *M

Page 40 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

11.1 Thermal Impedance

Table 11-1. Thermal Impedance for the Package

[15]

Package

Typical θ

[16]

56 QFN

68 QFN

12.93 C/W

[16]

13.05 C/W

100 VFBGA

100 TQFP

65 C/W

51 C/W

11.2 Solder Reflow Peak Temperature

Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 11-2. Solder Reflow Peak Temperature

[17]

Package

Minimum Peak Temperature

Maximum Peak Temperature

56 QFN

68 QFN

240 C

260 C

240 C

260 C

100 VFBGA

240 C

260 C

Notes

15. T = T + POWER x θ

16. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.

17. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 C with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu paste.

Refer to the solder manufacturer specifications

Document Number: 38-12018 Rev. *M

Page 41 of 47

■ ImageCraft Cypress Edition Compiler is available from

CY8C24094, CY8C24794

CY8C24894, CY8C24994

12. Development Tool Selection

12.1 Software

■ iMAGEcraft C Compiler (Registration Required)

■ ISSP Cable

12.1.1 PSoC Designer™

■ USB 2.0 Cable and Blue Cat-5 Cable

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

At the core of the PSoC development software suite is PSoC

Designer. Used by thousands of PSoC developers, this robust

software has been facilitating PSoC designs for half a decade.

PSoC Designer is available free of charge at

http://www.cypress.com under DESIGN RESOURCES >>

Software and Drivers.

12.2.2 CY3210-ExpressDK PSoC Express Development Kit

The CY3210-ExpressDK is for advanced prototyping and devel-

opment with PSoC Express (may be used with ICE-Cube

In-Circuit Emulator). It provides access to I C buses, voltage

12.1.2 PSoC Programmer

reference, switches, upgradeable modules and more. The kit

includes:

Flexible enough to be used on the bench in development, yet

suitable for factory programming, PSoC Programmer works

either as a standalone programming application or it can operate

directly from PSoC Designer or PSoC Express. PSoC

Programmer software is compatible with both PSoC ICE-Cube

In-Circuit Emulator and PSoC MiniProg. PSoC programmer is

available free of charge at http://www.cypress.com/psocpro-

grammer.

■ PSoC Express Software CD

■ Express Development Board

■ 4 Fan Modules

■ 2 Proto Modules

■ MiniProg In-System Serial Programmer

■ MiniEval PCB Evaluation Board

■ Jumper Wire Kit

12.1.3 C Compilers

PSoC Designer comes with a free HI-TECH C Lite C compiler.

The HI-TECH C Lite compiler is free, supports all PSoC devices,

integrates fully with PSoC Designer and PSoC Express, and

runs on Windows versions up to 32-bit Vista. Compilers with

additional features are available at additional cost from their

manufactures.

■ USB 2.0 Cable

■ Serial Cable (DB9)

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ 2 CY8C24423A-24PXI 28-PDIP Chip Samples

■ 2 CY8C27443-24PXI 28-PDIP Chip Samples

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

■ HI-TECH C PRO for the PSoC is available from

http://www.htsoft.com.

http://www.imagecraft.com.

12.2 Development Kits

12.3 Evaluation Tools

All development kits can be purchased from the Cypress Online

Store.

All evaluation tools can be purchased from the Cypress Online

Store.

12.2.1 CY3215-DK Basic Development Kit

12.3.1 CY3210-MiniProg1

The CY3215-DK is for prototyping and development with PSoC

Designer. This kit supports in-circuit emulation and the software

interface allows users to run, halt, and single step the processor

and view the content of specific memory locations. Advance

emulation features also supported through PSoC Designer. The

kit includes:

The CY3210-MiniProg1 kit allows a user to program PSoC

devices via the MiniProg1 programming unit. The MiniProg is a

small, compact prototyping programmer that connects to the PC

via a provided USB 2.0 cable. The kit includes:

■ MiniProg Programming Unit

■ PSoC Designer Software CD

■ ICE-Cube In-Circuit Emulator

■ ICE Flex-Pod for CY8C29x66 Family

■ Cat-5 Adapter

■ MiniEval Socket Programming and Evaluation Board

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample

■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample

■ PSoC Designer Software CD

■ Mini-Eval Programming Board

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ Getting Started Guide

■ USB 2.0 Cable

Document Number: 38-12018 Rev. *M

Page 42 of 47

http://www.emulation.com.

CY8C24094, CY8C24794

CY8C24894, CY8C24994

12.3.2 CY3210-PSoCEval1

12.4 Device Programmers

The CY3210-PSoCEval1 kit features an evaluation board and

the MiniProg1 programming unit. The evaluation board includes

an LCD module, potentiometer, LEDs, and plenty of bread-

boarding space to meet all of your evaluation needs. The kit

includes:

All device programmers can be purchased from the Cypress

Online Store.

12.4.1 CY3216 Modular Programmer

The CY3216 Modular Programmer kit features a modular

programmer and the MiniProg1 programming unit. The modular

programmer includes three programming module cards and

supports multiple Cypress products. The kit includes:

■ Evaluation Board with LCD Module

■ MiniProg Programming Unit

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)

■ PSoC Designer Software CD

■ Getting Started Guide

■ Modular Programmer Base

■ 3 Programming Module Cards

■ MiniProg Programming Unit

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

12.3.3 CY3214-PSoCEvalUSB

The CY3214-PSoCEvalUSB evaluation kit features a devel-

opment board for the CY8C24794-24LFXI PSoC device. Special

features of the board include both USB and capacitive sensing

development and debugging support. This evaluation board also

includes an LCD module, potentiometer, LEDs, an enunciator

and plenty of bread boarding space to meet all of your evaluation

needs. The kit includes:

■ USB 2.0 Cable

12.4.2 CY3207ISSP In-System Serial Programmer (ISSP)

The CY3207ISSP is a production programmer. It includes

protection circuitry and an industrial case that is more robust than

the MiniProg in a production-programming environment.

Note: CY3207ISSP needs special software and is not

■ PSoCEvalUSB Board

■ LCD Module

compatible with PSoC Programmer. The kit includes:

■ CY3207 Programmer Unit

■ PSoC ISSP Software CD

■ MIniProg Programming Unit

■ Mini USB Cable

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ USB 2.0 Cable

■ PSoC Designer and Example Projects CD

■ Getting Started Guide

■ Wire Pack

12.5 Accessories (Emulation and Programming)

Table 12-1. Emulation and Programming Accessories

[18]

[19]

[20]

Part #

Pin Package

56 QFN

Flex-Pod Kit

Foot Kit

Adapter

CY8C24794-24LFXI

CY8C24894-24LFXI

CY3250-24X94QFN

CY3250-56QFN-FK

AS-56-28

AS-28-28-02SS-6ENG-GANG

12.5.1 3rd-Party Tools

12.5.2 Build a PSoC Emulator into Your Board

Several tools have been specially designed by the following

3rd-party vendors to accompany PSoC devices during devel-

opment and production. Specific details for each of these tools

are found at http://www.cypress.com under Design Resources >

Evaluation Boards.

For details on how to emulate your circuit before going to volume

production using an on-chip debug (OCD) non-production PSoC

device, see Application Note “Debugging - Build a PSoC

Emulator

into

Your

Board

AN2323”

http://www.cypress.com/an2323.

Notes

18. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.

19. Foot kit includes surface mount feet that are soldered to the target PCB.

20. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters are found at

Document Number: 38-12018 Rev. *M

Page 43 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

13. Ordering Information

Table 13-1. CY8C24x94 PSoC Device’s Key Features and Ordering Information

56 Pin (8x8 mm) QFN

CY8C24794-24LFXI

CY8C24794-24LFXIT

16K 1K

-40°C to +85°C

56 Pin (8x8 mm) QFN

(Tape and Reel)

-40°C to +85°C

56 Pin (8x8 mm) QFN

CY8C24894-24LFXI

CY8C24894-24LFXIT

16K 1K

-40°C to +85°C

Yes

56 Pin (8x8 mm) QFN

(Tape and Reel)

-40°C to +85°C

[21]

68 Pin OCD (8x8 mm) QFN

68 Pin (8x8 mm) QFN

CY8C24094-24LFXI

CY8C24994-24LFXI

CY8C24994-24LFXIT

16K 1K

-40°C to +85°C

Yes

68 Pin (8x8 mm) QFN

(Tape and Reel)

68-Pin QFN (Sawn)

100 Ball OCD (6x6 mm)

CY8C24994-24LTXI

CY8C24994-24LTXIT

CY8C24094-24BVXI

16K 1K

-40°C to +85°C

Yes

[21]

VFBGA

100 Ball (6x6 mm) VFBGA

CY8C24994-24BVXI

CY8C24094-24AXI

CY8C24094-24LTXI

CY8C24094-24LTXIT

16K 1K

-40°C to +85°C

Yes

[21]

100 Pin OCD TQFP

68-Pin QFN (Sawn)

Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).

Document Number: 38-12018 Rev. *M

Page 44 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

13.1 Ordering Code Definitions

CY 8 C 24 XXX-SP XX

Package Type:

Thermal Rating:

C = Commercial

I = Industrial

PX = PDIP Pb-Free

SX = SOIC Pb-Free

PVX = SSOP Pb-Free

LFX/LKX/LTX = QFN Pb-Free

AX = TQFP Pb-Free

E = Extended

BVX = VFBGA Pb-Free

Speed: 24 MHz

Part Number

Family Code

Technology Code: C = CMOS

Marketing Code: 8 = Cypress PSoC

Company ID: CY = Cypress

Note

21. This part may be used for in-circuit debugging. It is NOT available for production.

Document Number: 38-12018 Rev. *M

Page 45 of 47

CY8C24094, CY8C24794

CY8C24894, CY8C24994

14. Document History Page

Document Title: CY8C24094, CY8C24794, CY8C24894 and CY8C24994 PSoC® Programmable System-on-Chip™

Document Number: 38-12018

Submission

Date

Orig. of

Change

Rev. ECN No.

Description of Change

133189 01.27.2004

251672 See ECN

NWJ

New silicon and new document – Advance Data Sheet.

SFV

First Preliminary Data Sheet. Changed title to encompass only the CY8C24794

because the CY8C24494 and CY8C24694 are not being offered by Cypress.

289742 See ECN

335236 See ECN

HMT

Add standard DS items from SFV memo. Add Analog Input Mux on pinouts. 2

MACs. Change 512 bytes of SRAM to 1K. Add dimension key to package. Remove

HAPI. Update diagrams, registers and specs.

HMT

Add CY logo. Update CY copyright. Update new CY.com URLs. Re-add ISSP

programming pinout notation. Add Reflow Temp. table. Update features (MAC,

Oscillator, and voltage range), registers (INT_CLR2/MSK2, second MAC), and

specs. (Rext, IMO, analog output buffer...).

344318 See ECN

HMT

Add new color and logo. Expand analog arch. diagram. Fix I/O #. Update Electrical

Specifications.

346774 See ECN

349566 See ECN

HMT

Add USB temperature specifications. Make data sheet Final.

Remove USB logo. Add URL to preferred dimensions for mounting MLF

packages.

393164 See ECN

469243 See ECN

HMT

Add new device, CY8C24894 56-pin MLF with XRES pin. Add Fimousb3v char. to

specs. Upgrade to CY Perform logo and update corporate address and copyright.

Add ISSP note to pinout tables. Update typical and recommended Storage

Temperature per industrial specs. Update Low Output Level maximum I/OL

budget. Add FLS_PR1 to Register Map Bank 1 for users to specify which Flash

bank should be used for SROM operations. Add two new devices for a 68-pin QFN

and 100-ball VFBGA under RPNs: CY8C24094 and CY8C24994. Add two

packages for 68-pin QFN. Add OCD non-production pinouts and package

diagrams. Update CY branding and QFN convention. Add new Dev. Tool section.

Update copyright and trademarks.

561158

See ECN

HMT

Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add

CY8C20x34 to PSoC Device Characteristics table. Add detailed dimensions to

56-pin QFN package diagram and update revision. Secure one package

diagram/manufacturing per QFN. Update emulation pod/feet kit part numbers. Fix

pinout type-o per TestTrack.

728238 See ECN

2552459 08/14/08

HMT

Add CapSense SNR requirement reference. Update figure standards. Update

Technical Training paragraphs. Add QFN package clarifications and dimensions.

Update ECN-ed Amkor dimensioned QFN package diagram revisions. Reword

SNR reference. Add new 56-pin QFN spec.

AZIE/PYRS

Add footnote on AGND descriptions to avoid using P2[4] for digital signaling as it

may add noise to AGND. Remove reference to CMP_GO_EN1 in Map Bank 1

Table on Address 65; this register has no functionality on 24xxx. Add footnote on

die sales. Add description 'Optional External Clock Input’ on P1[4] to match

description of P1[4].

2616550 12/05/08

2657956 02/11/09

OGNE/PYRS Updated Programmable Pin Configuration detail.

Changed title from PSoC® Mixed-Signal Array to PSoC® Programmable

System-on-Chip™

DPT/PYRS

Added package diagram 001-09618 and updated Ordering Information table

Document Number: 38-12018 Rev. *M

Page 46 of 47

psoc.cypress.com/solutions

CY8C24094, CY8C24794

CY8C24894, CY8C24994

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at cypress.com/sales.

Products

PSoC

PSoC Solutions

General

psoc.cypress.com/low-power

psoc.cypress.com/precision-analog

psoc.cypress.com/lcd-drive

psoc.cypress.com/can

Clocks & Buffers

Wireless

Low Power/Low Voltage

Precision Analog

LCD Drive

Memories

Image Sensors

CAN 2.0b

USB

psoc.cypress.com/usb

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medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 38-12018 Rev. *M

Revised February 10, 2009

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PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced

herein are property of the respective corporations.