Cypress CY8C21234 User Manual

signal-to-noise system level requirement found in Application

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

The Analog Multiplexer System

The Analog System

The Analog Mux Bus can connect to every GPIO pin. Pins may

be connected to the bus individually or in any combination. The

bus also connects to the analog system for analysis with

comparators and analog-to-digital converters. An additional 8:1

analog input multiplexer provides a second path to bring Port 0

pins to the analog array.

The Analog System consists of 4 configurable blocks that allow

the creation of complex analog signal flows. Analog peripherals

are very flexible and may be customized to support specific

application requirements. Some of the common PSoC analog

functions for this device (most available as user modules) are:

■ Analog-to-digital converters (single or dual, with 8-bit or 10-bit

resolution)

Switch control logic enables selected pins to precharge

continuously under hardware control. This enables capacitive

measurement for applications such as touch sensing. Other

multiplexer applications include:

■ Pin-to-pin comparator

■ Single-ended comparators (up to 2) with absolute (1.3V)

reference or 8-bit DAC reference

■ Track pad, finger sensing.

■ 1.3V reference (as a System Resource)

■ Chip-wide mux that allows analog input from any IO pin.

■ Crosspoint connection between any IO pin combinations.

In most PSoC devices, analog blocks are provided in columns of

three, which includes one CT (Continuous Time) and two SC

(Switched Capacitor) blocks. The CY8C21x34 devices provide

limited functionality Type “E” analog blocks. Each column

contains one CT Type E block and one SC Type E block. Refer

to the PSoC Programmable System-on-Chip™ Technical

Reference Manual for detailed information on the CY8C21x34’s

Type E analog blocks.

When designing capacitive sensing applications, refer to the

Note

AN2403

the

Cypress

web

site

http://www.cypress.com.

Additional System Resources

System Resources, some of which are listed in the previous

sections, provide additional capability useful to complete

systems. Additional resources include a switch mode pump, low

voltage detection, and power on reset. Brief statements

describing the merits of each system resource follow.

Figure 2. Analog System Block Diagram

Array Input

■ Digital clock dividers provide three customizable clock

frequencies for use in applications. The clocks may be routed

to both the digital and analog systems. Additional clocks can

be generated using digital PSoC blocks as clock dividers.

Configuration

■ TheI2Cmoduleprovides100and400kHzcommunicationover

two wires. Slave, master, and multi-master modes are all

supported.

ACI0[1:0]

ACI1[1:0]

■ Low Voltage Detection (LVD) interrupts can signal the

application of falling voltage levels, while the advanced POR

(Power On Reset) circuit eliminates the need for a system

supervisor.

All IO

AC OL 1MU X

An al o g MuxBus

■ An internal 1.3 voltage reference provides an absolute

reference for the analog system, including ADCs and DACs.

Array

■ An integrated switch mode pump (SMP) generates normal

operating voltages from a single 1.2V battery cell, providing a

low cost boost converter.

ACE00

ACE01

ASE11

■ Versatile analog multiplexer system.

ASE10

Document Number: 38-12025 Rev. *O

Page 3 of 45

information, see the latest PSoC device data sheets on the web

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

For up-to-date ordering, packaging, and electrical specification

at www.cypress.com/psoc.

PSoC Device Characteristics

Depending on your PSoC device characteristics, the digital and

analog systems can have 16, 8, or 4 digital blocks and 12, 6, or

4 analog blocks. T a ble 1 lists the resources available for specific

PSoC device groups. The PSoC device covered by this data

sheet is highlighted in this table.

Application Notes

Application notes are an excellent introduction to the wide variety

of possible PSoC designs. They are located here:

www.cypress.com/psoc. Select Application Notes under the

Documentation tab.

Table 1. PSoC Device Characteristics

PSoC Part

Number

Development Kits

PSoC Development Kits are available online from Cypress at

www.cypress.com/shop and through a growing number of

regional and global distributors, which include Arrow, Avnet,

Digi-Key, Farnell, Future Electronics, and Newark.

CY8C29x66 upto 4

16 12

12 2K

32K

CY8C27x43 upto 2

12 256 16K

Bytes

Training

CY8C24x94 56

16K

Free PSoC technical training (on demand, webinars, and

workshops) is available online at www.cypress.com/training. The

training covers a wide variety of topics and skill levels to assist

you in your designs.

CY8C24x23A upto 1

256 4K

Bytes

[1]

[2]

CY8C21x34 upto 1

512 8K

Bytes

Cypros Consultants

CY8C21x23 16

256 4K

Bytes

Certified PSoC Consultants offer everything from technical

assistance to completed PSoC designs. T o c ontact or become a

PSoC Consultant go to www.cypress.com/cypros.

CY8C20x34 upto 0

512 8K

Bytes

Solutions Library

Visit our growing library of solution focused designs at

www.cypress.com/solutions. Here you can find various appli-

cation designs that include firmware and hardware design files

that enable you to complete your designs quickly.

Getting Started

The quickest way to understand PSoC silicon is to read this data

sheet and then use the PSoC Designer Integrated Development

Environment (IDE). This data sheet is an overview of the PSoC

integrated circuit and presents specific pin, register, and

electrical specifications.

Technical Support

For assistance with technical issues, search KnowledgeBase

articles and forums at www.cypress.com/support. If you cannot

find an answer to your question, call technical support at

1-800-541-4736.

For in depth information, along with detailed programming

details, see the PSoC® Programmable System-on-Chip

Technical Reference Manual for CY8C28xxx PSoC devices.

Notes

1. Limited analog functionality.

2. Two analog blocks and one CapSense.

Document Number: 38-12025 Rev. *O

Page 4 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Code Generation Tools

Development Tools

PSoC Designer supports multiple third party C compilers and

assemblers. The code generation tools work seamlessly within

the PSoC Designer interface and have been tested with a full

range of debugging tools. The choice is yours.

PSoC Designer is a Microsoft^®Windows-based, integrated

development

environment

for

the

Programmable

System-on-Chip (PSoC) devices. The PSoC Designer IDE runs

on Windows XP or Windows Vista.

This system provides design database management by project,

an integrated debugger with In-Circuit Emulator, in-system

programming support, and built-in support for third-party

assemblers and C compilers.

Assemblers. The assemblers allow assembly code to merge

seamlessly with C code. Link libraries automatically use absolute

addressing or are compiled in relative mode, and linked with

other software modules to get absolute addressing.

PSoC Designer also supports C language compilers developed

specifically for the devices in the PSoC family.

C Language Compilers. C language compilers are available

that support the PSoC family of devices. The products allow you

to create complete C programs for the PSoC family devices.

PSoC Designer Software Subsystems

The optimizing C compilers provide all the features of C tailored

to the PSoC architecture. They come complete with embedded

libraries providing port and bus operations, standard keypad and

display support, and extended math functionality.

System-Level View

A drag-and-drop visual embedded system design environment

based on PSoC Express. In the system level view you create a

model of your system inputs, outputs, and communication inter-

faces. You define when and how an output device changes state

based upon any or all other system devices. Based upon the

design, PSoC Designer automatically selects one or more PSoC

Mixed-Signal Controllers that match your system requirements.

Debugger

The PSoC Designer Debugger subsystem provides hardware

in-circuit emulation, allowing you to test the program in a physical

system while providing an internal view of the PSoC device.

Debugger commands allow the designer to read and program

and read and write data memory, read and write IO registers,

read and write CPU registers, set and clear breakpoints, and

provide program run, halt, and step control. The debugger also

allows the designer to create a trace buffer of registers and

memory locations of interest.

PSoC Designer generates all embedded code, then compiles

and links it into a programming file for a specific PSoC device.

Chip-Level View

The chip-level view is a more traditional Integrated Development

Environment (IDE) based on PSoC Designer 4.4. Choose a base

device to work with and then select different onboard analog and

digital components called user modules that use the PSoC

blocks. Examples of user modules are ADCs, DACs, Amplifiers,

and Filters. Configure the user modules for your chosen

application and connect them to each other and to the proper

pins. Then generate your project. This prepopulates your project

with APIs and libraries that you can use to program your

application.

Online Help System

The online help system displays online, context-sensitive help

for the user. Designed for procedural and quick reference, each

functional subsystem has its own context-sensitive help. This

system also provides tutorials and links to FAQs and an Online

Support Forum to aid the designer in getting started.

In-Circuit Emulator

The device editor also supports easy development of multiple

configurations and dynamic reconfiguration. Dynamic

configuration allows for changing configurations at run time.

A low cost, high functionality In-Circuit Emulator (ICE) is

available for development support. This hardware has the

capability to program single devices.

Hybrid Designs

The emulator consists of a base unit that connects to the PC by

way of a USB port. The base unit is universal and operates with

all PSoC devices. Emulation pods for each device family are

available separately. The emulation pod takes the place of the

PSoC device in the target board and performs full speed (24

MHz) operation.

You can begin in the system-level view, allow it to choose and

configure your user modules, routing, and generate code, then

switch to the chip-level view to gain complete control over

on-chip resources. All views of the project share a common code

editor, builder, and common debug, emulation, and programming

tools.

Document Number: 38-12025 Rev. *O

Page 5 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

property, and other information you may need to successfully

implement your design.

Designing with PSoC Designer

The development process for the PSoC device differs from that

of a traditional fixed function microprocessor. The configurable

analog and digital hardware blocks give the PSoC architecture a

unique flexibility that pays dividends in managing specification

change during development and by lowering inventory costs.

These configurable resources, called PSoC Blocks, have the

ability to implement a wide variety of user-selectable functions.

Organize and Connect

You can build signal chains at the chip level by interconnecting

user modules to each other and the IO pins, or connect system

level inputs, outputs, and communication interfaces to each

other with valuator functions.

In the system-level view, selecting a potentiometer driver to

control a variable speed fan driver and setting up the valuators

to control the fan speed based on input from the pot selects,

places, routes, and configures a programmable gain amplifier

(PGA) to buffer the input from the potentiometer, an analog to

digital converter (ADC) to convert the potentiometer’s output to

a digital signal, and a PWM to control the fan.

The PSoC development process can be summarized in the

following four steps:

1. Select components

2. Configure components

3. Organize and Connect

4. Generate, Verify, and Debug

In the chip-level view, perform the selection, configuration, and

routing so that you have complete control over the use of all

on-chip resources.

Select Components

Both the system-level and chip-level views provide a library of

prebuilt, pretested hardware peripheral components. In the

system-level view, these components are called “drivers” and

correspond to inputs (a thermistor, for example), outputs (a

brushless DC fan, for example), communication interfaces

(I C-bus, for example), and the logic to control how they interact

with one another (called valuators).

Generate, Verify, and Debug

When you are ready to test the hardware configuration or move

on to developing code for the project, perform the “Generate

Application” step. This causes PSoC Designer to generate

source code that automatically configures the device to your

specification and provides the software for the system.

In the chip-level view, the components are called “user modules”.

User modules make selecting and implementing peripheral

devices simple, and come in analog, digital, and mixed signal

varieties.

Both system-level and chip-level designs generate software

based on your design. The chip-level design provides application

programming interfaces (APIs) with high level functions to

control and respond to hardware events at run-time and interrupt

service routines that you can adapt as needed. The system-level

design also generates a C main() program that completely

controls the chosen application and contains placeholders for

custom code at strategic positions allowing you to further refine

the software without disrupting the generated code.

Configure Components

Each of the components you select establishes the basic register

settings that implement the selected function. They also provide

parameters and properties that allow you to tailor their precise

configuration to your particular application. For example, a Pulse

Width Modulator (PWM) User Module configures one or more

digital PSoC blocks, one for each 8 bits of resolution. The user

module parameters permit you to establish the pulse width and

duty cycle. Configure the parameters and properties to

correspond to your chosen application. Enter values directly or

by selecting values from drop-down menus.

A complete code development environment allows you to

develop and customize your applications in C, assembly

language, or both.

The last step in the development process takes place inside the

PSoC Designer’s Debugger subsystem. The Debugger

downloads the HEX image to the ICE where it runs at full speed.

Debugger capabilities rival those of systems costing many times

more. In addition to traditional single-step, run-to-breakpoint and

watch-variable features, the Debugger provides a large trace

buffer and allows you define complex breakpoint events that

include monitoring address and data bus values, memory

locations and external signals.

Both the system-level drivers and chip-level user modules are

documented in data sheets that are viewed directly in the PSoC

Designer. These data sheets explain the internal operation of the

component and provide performance specifications. Each data

sheet describes the use of each user module parameter or driver

Document Number: 38-12025 Rev. *O

Page 6 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Units of Measure

Document Conventions

A units of measure table is located in the Electrical Specifications

section. T a ble 2 on page 7 lists all the abbreviations used to

measure the PSoC devices.

Acronyms Used

The following table lists the acronyms that are used in this

document.

Numeric Naming

Table 2. Acronyms Used

Hexadecimal numbers are represented with all letters in

uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or

‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’

prefix, the C coding convention. Binary numbers have an

appended lowercase ‘b’ (for example, 01010100b’ or

‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are

decimal.

Acronym

Description

alternating current

ADC

API

analog-to-digital converter

application programming interface

central processing unit

continuous time

CPU

DAC

digital-to-analog converter

direct current

ECO

EEPROM

external crystal oscillator

electrically erasable programmable read-only

memory

FSR

GPIO

GUI

full scale range

general purpose IO

graphical user interface

human body model

in-circuit emulator

HBM

ICE

ILO

internal low speed oscillator

internal main oscillator

input/output

IMO

IPOR

LSb

imprecise power on reset

least-significant bit

low voltage detect

LVD

MSb

most-significant bit

program counter

PLL

phase-locked loop

POR

PPOR

PSoC®

PWM

power on reset

precision power on reset

Programmable System-on-Chip™

pulse width modulator

switched capacitor

slow IMO

SLIMO

SMP

SRAM

switch mode pump

static random access memory

Document Number: 38-12025 Rev. *O

Page 7 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Pin Information

The CY8C21x34 PSoC device is available in a variety of packages which are listed in the following tables. Every port pin (labeled with

a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, SMP, and XRES are not capable of

Digital IO.

16-Pin Part Pinout

Figure 3. CY8C21234 16-Pin PSoC Device

A, I,M, P0[7]

A, I,M, P0[5]

A, I,M, P0[3]

A, I,M, P0[1]

SMP

Vdd

P0[6], A,I, M

P0[4], A,I, M

P0[2], A,I, M

P0[0], A,I, M

P1[4],EXTCLK,M

P1[2],M

SOIC

Vss

M,I2C SCL,P1[1]

Vss

P1[0],I2CSDA,M

Table 3. Pin Definitions - CY8C21234 16-Pin (SOIC)

Type

Pin No.

Name

Description

Digital

Analog

I, M

P0[7]

Analog column mux input.

I, M

P0[5]

P0[3]

P0[1]

SMP

Vss

Analog column mux input, integrating input.

Power

Switch Mode Pump (SMP) connection to required external components.

Ground connection.

[3]

P1[1]

Vss

I2C Serial Clock (SCL), ISSP-SCLK

Ground connection.

Power

P1[0]

P1[2]

P1[4]

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

I2C Serial Data (SDA), ISSP-SDATA ..

Optional External Clock Input (EXTCLK).

Analog column mux input.

Supply voltage.

I, M

Power

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

Note

3. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details.

Document Number: 38-12025 Rev. *O

Page 8 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

20-Pin Part Pinout

Figure 4. CY8C21334 20-Pin PSoC Device

A, I,M, P0[7]

A, I,M, P0[5]

A, I,M, P0[3]

A, I,M, P0[1]

Vss

Vdd

P0[6], A,I, M

P0[4], A,I, M

P0[2], A,I, M

P0[0], A,I, M

XRES

P1[6],M

P1[4],EXTCLK,M

P1[2],M

SSOP

M,I2C SCL,P1[7]

M,I2C SDA,P1[5]

M,P1[3]

M,I2C

SCL,P1[1]

Vss

P1[0],I2C SDA,M

Table 4. Pin Definitions - CY8C21334 20-Pin (SSOP)

Type

Pin No.

Name

Description

Digital

Analog

I, M

P0[7]

P0[5]

P0[3]

P0[1]

Vss

Analog column mux input.

I, M

Analog column mux input, integrating input.

Ground connection.

Power

P1[7]

P1[5]

P1[3]

P1[1]

Vss

I2C Serial Clock (SCL).

I2C Serial Data (SDA).

[3]

I2C Serial Clock (SCL), ISSP-SCLK

Ground connection.

Power

P1[0]

P1[2]

P1[4]

P1[6]

I2C Serial Data (SDA), ISSP-SDATA

Optional External Clock Input (EXTCLK).

Input

XRES Active high external reset with internal pull down.

I, M

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

Analog column mux input.

Supply voltage.

Power

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

Document Number: 38-12025 Rev. *O

Page 9 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

28-Pin Part Pinout

Figure 5. CY8C21534 28-Pin PSoC Device

A, I,M, P0[7]

A, I,M, P0[5]

A, I,M, P0[3]

A, I,M, P0[1]

M,P2[7]

Vdd

P0[6], A,I, M

P0[4], A,I, M

P0[2], A,I, M

P0[0], A,I, M

P2[6],M

M,P2[5]

M, P2[3]

M, P2[1]

P2[4],M

P2[2],M

SSOP

Vss

P2[0],M

XRES

P1[6],M

M,I2C SCL,P1[7]

M,I2C SDA,P1[5]

M,P1[3]

P1[4],EXTCLK,M

P1[2],M

P1[0],I2CSDA,M

M,I2C SCL,P1[1]

Vss

Table 5. Pin Definitions - CY8C21534 28-Pin (SSOP)

Type

Pin No.

Name

Description

Digital

Analog

I, M

P0[7]

Analog column mux input.

I, M

P0[5]

P0[3]

P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

Vss

Analog column mux input and column output.

Analog column mux input and column output, integrating input.

Analog column mux input, integrating input.

I, M

Direct switched capacitor block input.

Ground connection.

Power

P1[7]

P1[5]

P1[3]

P1[1]

Vss

I2C Serial Clock (SCL).

I2C Serial Data (SDA).

[3]

I2C Serial Clock (SCL), ISSP-SCLK

Ground connection.

Power

P1[0]

P1[2]

P1[4]

P1[6]

XRES

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

I2C Serial Data (SDA), ISSP-SDATA

Optional External Clock Input (EXTCLK).

Input

Active high external reset with internal pull down.

Direct switched capacitor block input.

I, M

Direct switched capacitor block input.

I, M

Analog column mux input.

Analog column mux input

Analog column mux input.

Supply voltage.

Power

LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input.

Document Number: 38-12025 Rev. *O

Page 10 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

32-Pin Part Pinout

Figure 9. CY8C21634 32-Pin PSoC Device

Figure 6. CY8C21434 32-Pin PSoC Device

Figure 10. CY8C21434 32-Pin Sawn PSoC Device

Figure 11. CY8C21634 32-Pin Sawn PSoC Device

A, I, M, P0[1]

M, P2[7]

M, P2[5]

M, P2[3]

M, P2[1]

M, P3[3]

A, I, M, P0[1]

M, P2[7]

M, P2[5]

M, P2[3]

M, P2[1]

SMP

P0[0], A, I, M

23 P2[6], M

22 P2[4], M

P2[2], M

20 P2[0], M

P3[2], M

23 P2[6], M

22 P2[4], M

P2[2], M

20 P2[0], M

P3[2], M

QFN

(Top View)

QFN

(Top View)

M, P3[1]

M, 12C SCL, P1[7]

Vss

18 P3[0], M

17 XRES

18 P3[0], M

17 XRES

M, 12C SCL, P1[7]

Document Number: 38-12025 Rev. *O

Page 11 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

[4]

Table 6. Pin Definitions - CY8C21434/CY8C21634 32-Pin (QFN)

Type

Analog

I, M

No.

Name

P0[1]

Description

Digital

Analog column mux input, integrating input.

P2[7]

P2[5]

P2[3]

P2[1]

P3[3]

SMP

In CY8C21434 part.

Power

Switch Mode Pump (SMP) connection to required external components in

CY8C21634 part.

P3[1]

Vss

In CY8C21434 part.

Power

Ground connection in CY8C21634 part.

I2C Serial Clock (SCL).

P1[7]

P1[5]

P1[3]

P1[1]

Vss

I2C Serial Data (SDA).

I2C Serial Clock (SCL), ISSP-SCLK

Ground connection.

Power

[3]

P1[0]

P1[2]

P1[4]

P1[6]

XRES

P3[0]

P3[2]

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

I2C Serial Data (SDA), ISSP-SDATA

Optional External Clock Input (EXTCLK).

Input

Active high external reset with internal pull down.

I, M

Analog column mux input.

Supply voltage.

Power

I, M

P0[7]

P0[5]

P0[3]

Vss

Analog column mux input.

Analog column mux input, integrating input.

Ground connection.

Power

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.

Note

4. The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it

must be electrically floated and not connected to any other signal.

Document Number: 38-12025 Rev. *O

Page 12 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

56-Pin Part Pinout

The 56-pin SSOP part is for the CY8C21001 On-Chip Debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production.

Figure 12. CY8C21001 56-Pin PSoC Device

Vss

Vdd

AI, P0[7]

AI, P0[5]

AI, P0[3]

P0[6], AI

P0[4], AI

P0[2], AI

AI, P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

P0[0], AI

P2[6]

P2[4]

P2[2]

P2[0]

P3[2]

P3[0]

CCLK

HCLK

XRES

OCDE

OCDO

SMP

SSOP

Vss

P3[3]

P3[1]

P1[6]

I2C SCL, P1[7]

P1[4], EXTCLK

P1[2]

I2C SDA, P1[5]

P1[3]

P1[0], I2C

SDA, SDATA

SCLK, I2C SCL, P1[1]

Vss

Table 7. Pin Definitions - CY8C21001 56-Pin (SSOP)

Type

Pin No.

Pin Name

Description

Digital

Power

Analog

Vss

Ground connection.

Analog column mux input.

P0[7]

P0[5]

P0[3]

P0[1]

P2[7]

P2[5]

P2[3]

P2[1]

Analog column mux input and column output.

Analog column mux input.

Direct switched capacitor block input.

No connection.

OCD

OCDE

OCDO

SMP

Vss

OCD even data IO.

OCD

OCD odd data output.

Power

Switch Mode Pump (SMP) connection to required external components.

Ground connection.

Vss

Ground connection.

Document Number: 38-12025 Rev. *O

Page 13 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Table 7. Pin Definitions - CY8C21001 56-Pin (SSOP) (continued)

Type

Pin No.

Pin Name

Description

Digital

Analog

P3[3]

P3[1]

No connection.

P1[7]

P1[5]

I2C Serial Clock (SCL).

I2C Serial Data (SDA).

No connection.

P1[3]

P1[1]

Vss

FMTEST

[3]

Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK ..

Power

Ground connection.

No connection.

P1[0]

P1[2]

P1[4]

P1[6]

Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA ..

FMTEST

Optional External Clock Input (EXTCLK).

No connection.

Input

OCD

XRES

HCLK

CCLK

P3[0]

P3[2]

Active high external reset with internal pull down.

OCD high-speed clock output.

OCD CPU clock output.

No connection.

P2[0]

P2[2]

P2[4]

P2[6]

P0[0]

P0[2]

P0[4]

P0[6]

Vdd

Analog column mux input.

Analog column mux input and column output.

Analog column mux input.

Power

Supply voltage.

LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.

Document Number: 38-12025 Rev. *O

Page 14 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

This chapter lists the registers of the CY8C21x34 PSoC device. For detailed register information, refer the PSoC Programmable

System-on-Chip Technical Reference Manual.

The register conventions specific to this section are listed in T a ble 8.

Table 8. Register Conventions

Convention

Description

Read register or bit(s)

Write register or bit(s)

Logical register or bit(s)

Clearable register or bit(s)

Access is bit specific

The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into

two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user

is in Bank 1.

Note In the following register mapping tables, blank fields are Reserved and must not be accessed.

Table 9. Register Map 0 Table: User Space

PRT0DR

PRT0IE

PRT0GS

PRT0DM2

PRT1DR

PRT1IE

PRT1GS

PRT1DM2

PRT2DR

PRT2IE

PRT2GS

PRT2DM2

PRT3DR

PRT3IE

ASE10CR0

ASE11CR0

PRT3GS

PRT3DM2

CUR_PP

STK_PP

IDX_PP

MVR_PP

MVW_PP

I2C_CFG

I2C_SCR

I2C_DR

I2C_MSCR

INT_CLR0

INT_CLR1

INT_CLR3

INT_MSK3

Blank fields are Reserved and must not be accessed.

# Access is bit specific.

Document Number: 38-12025 Rev. *O

Page 15 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Table 9. Register Map 0 Table: User Space (continued)

DBB00DR0

DBB00DR1

DBB00DR2

DBB00CR0

DBB01DR0

DBB01DR1

DBB01DR2

DBB01CR0

DCB02DR0

DCB02DR1

DCB02DR2

DCB02CR0

DCB03DR0

DCB03DR1

DCB03DR2

DCB03CR0

AMX_IN

AMUXCFG

PWM_CR

INT_MSK0

INT_MSK1

INT_VC

RES_WDT

CMP_CR0

CMP_CR1

DEC_CR0

DEC_CR1

ADC0_CR

ADC1_CR

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

RDI0RI

RDI0SYN

RDI0IS

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

ACE00CR1

ACE00CR2

ACE01CR1

ACE01CR2

CPU_F

DAC_D

CPU_SCR1

CPU_SCR0

Blank fields are Reserved and must not be accessed.

# Access is bit specific.

Table 10. Register Map 1 Table: Configuration Space

PRT0DM0

PRT0DM1

PRT0IC0

PRT0IC1

PRT1DM0

PRT1DM1

PRT1IC0

PRT1IC1

PRT2DM0

PRT2DM1

PRT2IC0

PRT2IC1

PRT3DM0

PRT3DM1

PRT3IC0

PRT3IC1

ASE10CR0

ASE11CR0

GDI_O_IN

GDI_E_IN

GDI_O_OU

GDI_E_OU

Blank fields are Reserved and must not be accessed.

# Access is bit specific.

Document Number: 38-12025 Rev. *O

Page 16 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Table 10. Register Map 1 Table: Configuration Space (continued)

MUX_CR0

MUX_CR1

MUX_CR2

MUX_CR3

OSC_GO_EN DD

OSC_CR4

OSC_CR3

OSC_CR0

OSC_CR1

OSC_CR2

VLT_CR

VLT_CMP

ADC0_TR

ADC1_TR

DBB00FN

DBB00IN

DBB00OU

CLK_CR0

CLK_CR1

ABF_CR0

AMD_CR0

DBB01FN

DBB01IN

DBB01OU

CMP_GO_EN 64

AMD_CR1

ALT_CR0

DCB02FN

DCB02IN

DCB02OU

IMO_TR

ILO_TR

BDG_TR

ECO_TR

CLK_CR3

TMP_DR0

TMP_DR1

TMP_DR2

TMP_DR3

DCB03FN

DCB03IN

DCB03OU

RDI0RI

RDI0SYN

RDI0IS

RDI0LT0

RDI0LT1

RDI0RO0

RDI0RO1

ACE00CR1

ACE00CR2

ACE01CR1

ACE01CR2

CPU_F

FLS_PR1

DAC_CR

CPU_SCR1

CPU_SCR0

Blank fields are Reserved and must not be accessed.

# Access is bit specific.

Document Number: 38-12025 Rev. *O

Page 17 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Electrical Specifications

This section presents the DC and AC electrical specifications of the CY8C21x34 PSoC device. For up to date electrical specifications,

visit the web site http://www.cypress.com/psoc.

Specifications are valid for -40 C ≤ T ≤ 85 C and T ≤ 100 C as specified, except where noted.

Refer T a ble 25 on page 26 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.

Figure 13. Voltage versus CPU Frequency

Figure 14. IMO Frequency Trim Options

5.25

4.75

5.25

4.75

SLIMO

Mode=1

SLIMO

Mode=0

3.60

3.00

2.40

SLIMO

Mode=1

SLIMO

Mode=0

3.00

2.40

SLIMO SLIMO

Mode=1 Mode=1

93 kHz

12 MHz

CPUFrequency

24 MHz

3 MHz

93 kHz

6 MHz

12 MHz

24 MHz

IMOFrequency

T a ble 11 lists the units of measure that are used in this section.

Table 11. Units of Measure

Symbol

Unit of Measure

degree Celsius

Symbol

μW

Unit of Measure

microwatts

decibels

milli-ampere

milli-second

milli-volts

femto farad

hertz

1024 bytes

1024 bits

nanoampere

nanosecond

nanovolts

Kbit

kHz

kΩ

kilohertz

kilohm

ohm

MHz

MΩ

μA

μF

μH

μs

μV

μVrms

megahertz

megaohm

picoampere

picofarad

microampere

microfarad

microhenry

microsecond

microvolts

peak-to-peak

parts per million

picosecond

samples per second

ppm

sps

sigma: one standard deviation

volts

microvolts root-mean-square

Document Number: 38-12025 Rev. *O

Page 18 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Absolute Maximum Ratings

Table 12. Absolute Maximum Ratings

Symbol

Description

Storage Temperature

Min

Typ

Max

Units

Notes

-55

+100

Higher storage temperatures

STG

reduce data retention time. Recom-

mended storage temperature is

+25 C ± 25 C. Extended duration

storage temperatures above 65 C

degrade reliability.

Ambient Temperature with Power Applied

Supply Voltage on Vdd Relative to Vss

DC Input Voltage

-40

–

+85

Vdd

-0.5

+6.0

Vss -

0.5

Vdd +

0.5

DC Voltage Applied to Tri-state

Vss -

0.5

–

Vdd +

0.5

IOZ

Maximum Current into any Port Pin

Electro Static Discharge Voltage

Latch-up Current

-25

2000

–

+50

–

MIO

ESD

Human Body Model ESD.

200

Operating Temperature

Table 13. Operating Temperature

Symbol

Description

Ambient Temperature

Junction Temperature

Min

-40

Typ

–

Max

+85

Units

Notes

–

+100

The temperature rise from ambient

to junction is package specific. See

T a ble 40 on page 38. The user must

limit the power consumption to

comply with this requirement.

DC Electrical Characteristics

DC Chip-Level Specifications

T a ble 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to

5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 14. DC Chip-Level Specifications

Symbol

Description

Min

2.40

–

Typ

–

Max

5.25

Units

Notes

Vdd

Supply Voltage

See T a ble 23 on page 24.

Supply Current, IMO = 24 MHz

mA Conditions are Vdd = 5.0V,

T = 25 C, CPU = 3 MHz, 48 MHz

disabled. VC1 = 1.5 MHz,

VC2 = 93.75 kHz, VC3 = 0.366 kHz.

Supply Current, IMO = 6 MHz using SLIMO

mode.

–

1.2

1.1

mA Conditions are Vdd = 3.3V,

DD3

DD27

T = 25 C, CPU = 3 MHz, clock

doubler disabled. VC1 = 375 kHz,

VC2 = 23.4 kHz, VC3 = 0.091 kHz.

Supply Current, IMO = 6 MHz using SLIMO

mode.

1.5

mA Conditions are Vdd = 2.55V,

T = 25 C, CPU = 3 MHz, clock

doubler disabled. VC1 = 375 kHz,

VC2 = 23.4 kHz, VC3 = 0.091 kHz.

Document Number: 38-12025 Rev. *O

Page 19 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Table 14. DC Chip-Level Specifications (continued)

Symbol

Description

Min

Typ

Max

Units

Notes

Sleep (Mode) Current with POR, LVD, Sleep

Timer, WDT, and internal slow oscillator active.

Mid temperature range.

–

2.6

μA

Vdd = 2.55V, 0 C ≤ T ≤ 40 C.

SB27

Sleep (Mode) Current with POR, LVD, Sleep

Timer, WDT, and internal slow oscillator active.

–

2.8

μA

Vdd = 3.3V, -40 C ≤ T ≤ 85 C.

Reference Voltage (Bandgap)

Analog Ground

1.28

1.16

1.30

1.32

1.33

Trimmed for appropriate Vdd.

Vdd = 3.0V to 5.25V.

REF

Trimmed for appropriate Vdd. Vdd =

2.4V to 3.0V.

REF27

AGND

REF

- 0.003

+ 0.003

DC General Purpose IO Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.

Table 15. 5V and 3.3V DC GPIO Specifications

Symbol

Description

Min

Typ

5.6

–

Max

Units

kΩ

Notes

Pull up Resistor

–

Pull down Resistor

High Output Level

kΩ

Vdd -

1.0

IOH = 10 mA, Vdd = 4.75 to 5.25V (8

total loads, 4 on even port pins (for

example, P0[2], P1[4]), 4 on odd port

pins (for example, P0[3], P1[5])).

Low Output Level

–

0.75

0.8

IOL = 25 mA, Vdd = 4.75 to 5.25V (8

total loads, 4 on even port pins (for

example, P0[2], P1[4]), 4 on odd port

pins (for example, P0[3], P1[5])).

Input Low Level

–

2.1

–

Vdd = 3.0 to 5.25.

Input High Level

Input Hysteresis

–

Input Leakage (Absolute Value)

Capacitive Load on Pins as Input

–

nA Gross tested to 1 μA.

–

3.5

Package and pin dependent.

Temp = 25 C.

Capacitive Load on Pins as Output

–

3.5

Package and pin dependent.

Temp = 25 C.

OUT

Table 16. 2.7V DC GPIO Specifications

Symbol Description

Min

Typ

5.6

–

Max

Units

kΩ

Notes

Pull up Resistor

–

Pull down Resistor

High Output Level

kΩ

Vdd -

0.4

IOH = 2.5 mA (6.25 Typ), Vdd = 2.4

to 3.0V (16 mA maximum, 50 mA Typ

combined IOH budget).

Low Output Level

Input Low Level

–

0.75

IOL = 10 mA, Vdd = 2.4 to 3.0V (90

mA maximum combined IOL

budget).

Vdd = 2.4 to 3.0.

Document Number: 38-12025 Rev. *O

Page 20 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Table 16. 2.7V DC GPIO Specifications (continued)

Symbol Description

Min

2.0

–

Typ

–

Max

–

Units

Notes

Vdd = 2.4 to 3.0.

Input High Level

Input Hysteresis

–

Input Leakage (Absolute Value)

Capacitive Load on Pins as Input

–

nA Gross tested to 1 μA.

–

3.5

Package and pin dependent.

Temp = 25 C.

Capacitive Load on Pins as Output

–

3.5

Package and pin dependent.

Temp = 25 C.

OUT

DC Operational Amplifier Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 17. 5V DC Operational Amplifier Specifications

Symbol

Description

Min

–

Typ

2.5

Max

–

Units

Notes

Input Offset Voltage (absolute value)

Average Input Offset Voltage Drift

Input Leakage Current (Port 0 Analog Pins)

Input Capacitance (Port 0 Analog Pins)

OSOA

TCV

–

μV/ C

OSOA

[5]

–

200

4.5

–

Gross tested to 1 μA.

EBOA

–

9.5

Package and pin dependent.

Temp = 25 C.

INOA

Common Mode Voltage Range

0.0

–

Vdd - 1

CMOA

Open Loop Gain

–

OLOA

Amplifier Supply Current

μA

SOA

Table 18. 3.3V DC Operational Amplifier Specifications

Symbol

Description

Min

–

Typ

2.5

Max

–

Units

Notes

Input Offset Voltage (absolute value)

Average Input Offset Voltage Drift

Input Leakage Current (Port 0 Analog Pins)

Input Capacitance (Port 0 Analog Pins)

OSOA

TCV

–

μV/ C

OSOA

[5]

–

200

4.5

–

Gross tested to 1 μA.

EBOA

–

9.5

Package and pin dependent.

Temp = 25 C.

INOA

Common Mode Voltage Range

Open Loop Gain

–

Vdd - 1

CMOA

–

μA

OLOA

Amplifier Supply Current

SOA

Note

5. Atypical behavior: I_EBOAof Port 0 Pin 0 is below 1 nA at 25°C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA.

Document Number: 38-12025 Rev. *O

Page 21 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Table 19. 2.7V DC Operational Amplifier Specifications

Symbol

Description

Min

–

Typ

2.5

Max

–

Units

Notes

Input Offset Voltage (absolute value)

Average Input Offset Voltage Drift

Input Leakage Current (Port 0 Analog Pins)

Input Capacitance (Port 0 Analog Pins)

OSOA

TCV

–

μV/ C

OSOA

[5]

–

200

4.5

–

Gross tested to 1 μA.

EBOA

–

9.5

Package and pin dependent.

Temp = 25 C.

INOA

Common Mode Voltage Range

Open Loop Gain

–

Vdd - 1

CMOA

–

μA

OLOA

Amplifier Supply Current

SOA

DC Low Power Comparator Specifications

T a ble 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to

5V at 25°C and are for design guidance only.

Table 20. DC Low Power Comparator Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

Low power comparator (LPC) reference

voltage range

0.2

–

Vdd - 1

REFLPC

LPC supply current

LPC voltage offset

–

μA

SLPC

2.5

OSLPC

DC Switch Mode Pump Specifications

T a ble 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to

5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 21. DC Switch Mode Pump (SMP) Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

5V Output Voltage from Pump

4.75

5.0

5.25

Configuration of footnote.

PUMP5V

PUMP3V

PUMP2V

PUMP

Average, neglecting ripple.

SMP trip voltage is set to 5.0V.

3.3V Output Voltage from Pump

2.6V Output Voltage from Pump

Available Output Current

3.00

2.45

3.25

2.55

3.60

2.80

Configuration of footnote.

Average, neglecting ripple.

SMP trip voltage is set to 3.25V.

Configuration of footnote.

Average, neglecting ripple.

SMP trip voltage is set to 2.55V.

Configuration of footnote.

= 1.8V, V

= 1.5V, V

= 1.3V, V

= 5.0V

= 3.25V

= 2.55V

–

SMP trip voltage is set to 5.0V.

SMP trip voltage is set to 3.25V.

SMP trip voltage is set to 2.55V.

BAT

PUMP

Input Voltage Range from Battery

1.8

1.0

1.2

–

5.0

3.3

2.8

–

Configuration of footnote.

BAT5V

BAT3V

BAT2V

BATSTA

SMP trip voltage is set to 5.0V.

Configuration of footnote.

SMP trip voltage is set to 3.25V.

Configuration of footnote.

SMP trip voltage is set to 2.55V.

Minimum Input Voltage from Battery to Start

Pump

Configuration of footnote.

0 C ≤ T ≤ 100. 1.25V at T =

-40 C.

Document Number: 38-12025 Rev. *O

Page 22 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Table 21. DC Switch Mode Pump (SMP) Specifications (continued)

Symbol

Description

Min

Typ

Max

Units

Notes

ΔV

Line

Line Regulation (over Vi range)

–

Configuration of footnote.

PUMP_

is the “Vdd Value for PUMP

Trip” specified by the VM[2:0]

setting in the DC POR and LVD

Specification, T a ble 23 on page

24.

ΔV

Load

Load Regulation

–

Configuration of footnote.

PUMP_

is the “Vdd Value for PUMP

Trip” specified by the VM[2:0]

setting in the DC POR and LVD

Specification, T a ble 23 on page

24.

ΔV

Ripple

Output Voltage Ripple (depends on cap/load)

Efficiency

–

100

–

mVpp Configuration of footnote.

Load is 5 mA.

PUMP_

Configuration of footnote.

Load is 5 mA. SMP trip voltage

is set to 3.25V.

Efficiency

–

For I load = 1mA, V

PUMP

2.55V, V

= 1.3V,

BAT

10 uH inductor, 1 uF capacitor,

and Schottky diode.

Switching Frequency

Switching Duty Cycle

–

1.3

–

MHz

PUMP

Figure 15. Basic Switch Mode Pump Circuit

Vdd

V_PUMP

L₁

SMP

Vss

V_BAT

Battery

PSoC

Note

6. L₁= 2 mH inductor, C₁= 10 mF capacitor, D₁= Schottky diode. See Figure 15.

Document Number: 38-12025 Rev. *O

Page 23 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

DC Analog Mux Bus Specifications

T a ble 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to

5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 22. DC Analog Mux Bus Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

Switch Resistance to Common Analog Bus

–

400

800

Vdd ≥ 2.7V

2.4V ≤ Vdd ≤ 2.7V

Resistance of Initialization Switch to Vdd

–

800

VDD

DC POR and LVD Specifications

T a ble 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to

5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 23. DC POR and LVD Specifications

Symbol

Description

Vdd Value for PPOR Trip

PORLEV[1:0] = 00b

PORLEV[1:0] = 01b

PORLEV[1:0] = 10b

Min

Typ

Max

Units

Notes

Vdd must be greater than or equal

to 2.5V during startup, reset from

the XRES pin, or reset from

Watchdog.

2.36

2.82

4.55

2.40

2.95

4.70

PPOR0

PPOR1

PPOR2

–

Vdd Value for LVD Trip

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

[7]

2.40

2.85

2.95

3.06

4.37

4.50

4.62

4.71

2.45

2.92

3.02

3.13

4.48

4.64

4.73

4.81

2.51

2.99

LVD0

LVD1

LVD2

LVD3

LVD4

LVD5

LVD6

LVD7

[8]

3.09

3.20

4.55

4.75

4.83

4.95

Vdd Value for PUMP Trip

VM[2:0] = 000b

VM[2:0] = 001b

VM[2:0] = 010b

VM[2:0] = 011b

VM[2:0] = 100b

VM[2:0] = 101b

VM[2:0] = 110b

VM[2:0] = 111b

[9]

2.45

2.96

3.03

3.18

4.54

4.62

4.71

4.89

2.55

3.02

3.10

2.62

3.09

3.16

PUMP0

PUMP1

PUMP2

PUMP3

PUMP4

PUMP5

PUMP6

PUMP7

[10]

3.25 3.32

4.64

4.73

4.82

5.00

4.74

4.83

4.92

5.12

Notes

7. Always greater than 50 mV above V_PPOR(PORLEV = 00) for falling supply.

8. Always greater than 50 mV above V_PPOR(PORLEV = 01) for falling supply.

9. Always greater than 50 mV above V_LVD0

10. Always greater than 50 mV above V_LVD3

Document Number: 38-12025 Rev. *O

Page 24 of 45

11. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

DC Programming Specifications

T a ble 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to

5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 24. DC Programming Specifications

Symbol

Vdd

Description

Min

2.70

–

Typ

–

Max

–

Units

Notes

Supply Voltage for Flash Write Operations

Supply Current During Programming or Verify

IWRITE

DDP

Input Low Voltage During Programming or

Verify

–

0.8

ILP

Input High Voltage During Programming or

Verify

2.2

–

IHP

Input Current when Applying Vilp to P1[0] or

P1[1] During Programming or Verify

0.2

1.5

Driving internal pull down resistor.

ILP

Input Current when Applying Vihp to P1[0] or

P1[1] During Programming or Verify

–

IHP

Output Low Voltage During Programming or

Verify

–

Vss +

0.75

OLV

Output High Voltage During Programming or

Verify

Vdd -

1.0

Vdd

OHV

Flash

Flash Endurance (per block)

50,000

–

Erase/write cycles per block.

Erase/write cycles.

ENPB

ENT

[11]

Flash Endurance (total)

1,800,

000

Flash

Flash Data Retention

–

Years

Note

blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block

ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (Flash T e mp) and feed the result to

the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more

information.

Document Number: 38-12025 Rev. *O

Page 25 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

AC Electrical Characteristics

AC Chip-Level Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 25. 5V and 3.3V AC Chip-Level Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

[12,13,14]

[12,13]

Internal Main Oscillator Frequency for 24 MHz 23.4

24.6

MHz Trimmed for 5V or 3.3V

operation using factory trim

values. See Figure 14 on

page 18. SLIMO mode = 0.

IMO24

Internal Main Oscillator Frequency for 6 MHz

5.75

0.93

6.35

MHz Trimmed for 5V or 3.3V

operation using factory trim

values. See Figure 14 on

page 18. SLIMO mode = 1.

IMO6

CPU1

CPU Frequency (5V Nominal)

CPU Frequency (3.3V Nominal)

24.6

MHz 24 MHz only for SLIMO

mode = 0.

[13,14]

0.93

12.3

MHz

CPU2

BLK5

[12,13,15]

Digital PSoC Block Frequency (5V Nominal)

49.2

MHz Refer to the AC Digital Block

Specifications.

[13,15]

Digital PSoC Block Frequency (3.3V Nominal)

Internal Low Speed Oscillator Frequency

32 kHz RMS Period Jitter

–

24.6

MHz

kHz

BLK33

32K1

200

–

Jitter32k

100

1400

–

32 kHz Peak-to-Peak Period Jitter

External Reset Pulse Width

–

μs

XRST

DC24M

24 MHz Duty Cycle

–

Step24M

Fout48M

24 MHz Trim Step Size

kHz

[12,14]

48 MHz Output Frequency

46.8

48.0

49.2

MHz Trimmed. Using factory trim

values.

Jitter24M1 24 MHz Peak-to-Peak Period Jitter (IMO)

–

600

–

Maximum frequency of signal on row input or

row output.

12.3

–

MHz

MAX

Supply Ramp Time

–

μs

RAMP

Notes

12. 4.75V < Vdd < 5.25V.

13. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.

14. 3.0V < Vdd < 3.6 V . S ee Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for

operation at 3.3V.

15. See the individual user module data sheets for information on maximum frequencies for user modules.

Document Number: 38-12025 Rev. *O

Page 26 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Table 26. 2.7V AC Chip-Level Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

[16,17,18]

Internal Main Oscillator Frequency for 12 MHz 11.5

12.7

MHz Trimmed for 2.7V operation

using factory trim values.

See Figure 14 on page 18.

SLIMO mode = 1.

IMO12

[16,17,18]

[16,17]

Internal Main Oscillator Frequency for 6 MHz

5.75

6.35

MHz Trimmed for 2.7V operation

using factory trim values.

See Figure 14 on page 18.

SLIMO mode = 1.

IMO6

CPU Frequency (2.7V Nominal)

0.093

3.15

MHz 24 MHz only for SLIMO

mode = 0.

CPU1

BLK27

32K1

[16,17,18]

Digital PSoC Block Frequency (2.7V Nominal)

12.5

MHz RefertotheACDigitalBlock

Specifications.

Internal Low Speed Oscillator Frequency

32 kHz RMS Period Jitter

–

150

1400

–

200

–

kHz

Jitter32k

32 kHz Peak-to-Peak Period Jitter

External Reset Pulse Width

–

μs

MHz

XRST

Maximum frequency of signal on row input or

row output.

–

12.3

MAX

Supply Ramp Time

–

μs

RAMP

Figure 16. 24 MHz Period Jitter (IMO) Timing Diagram

Jitter24M1

F_24M

Figure 17. 32 kHz Period Jitter (ILO) Timing Diagram

Jitter32k

F_32K1

Notes

16. 2.4V < Vdd < 3.0V.

17. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.

18. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on maximum frequency for user modules.

Document Number: 38-12025 Rev. *O

Page 27 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

AC General Purpose IO Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 27. 5V and 3.3V AC GPIO Specifications

Symbol

Description

Min

Typ

–

Max

–

Units

Notes

GPIO Operating Frequency

MHz Normal Strong Mode

GPIO

TRiseF

TFallF

TRiseS

TFallS

Rise Time, Normal Strong Mode, Cload = 50 pF

Fall Time, Normal Strong Mode, Cload = 50 pF

Rise Time, Slow Strong Mode, Cload = 50 pF

Fall Time, Slow Strong Mode, Cload = 50 pF

–

Vdd = 4.5 to 5.25V, 10% - 90%

–

Vdd = 4.5 to 5.25V, 10% - 90%

Vdd = 3 to 5.25V, 10% - 90%

–

Table 28. 2.7V AC GPIO Specifications

Symbol

Description

Min

Typ

–

Max

Units

Notes

GPIO Operating Frequency

MHz Normal Strong Mode

GPIO

TRiseF

TFallF

TRiseS

TFallS

Rise Time, Normal Strong Mode, Cload = 50 pF

Fall Time, Normal Strong Mode, Cload = 50 pF

Rise Time, Slow Strong Mode, Cload = 50 pF

Fall Time, Slow Strong Mode, Cload = 50 pF

–

Vdd = 2.4 to 3.0V, 10% - 90%

–

Vdd = 2.4 to 3.0V, 10% - 90%

120

Figure 18. GPIO Timing Diagram

90%

GPIO

Output

Voltage

10%

TRiseF

TRiseS

TFallF

TFallS

AC Operational Amplifier Specifications

T a ble 29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to

5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 29. AC Operational Amplifier Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

Comparator Mode Response Time, 50 mV

Overdrive

100

200

Vdd ≥ 3.0V.

2.4V < Vcc < 3.0V.

COMP

AC Low Power Comparator Specifications

T a ble 30 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to

5V at 25°C and are for design guidance only.

Table 30. AC Low Power Comparator Specifications

Symbol

Description

LPC response time

Min

Typ

Max

Units

Notes

–

μs

≥ 50 mV overdrive comparator

reference set within V

RLPC

REFLPC

Document Number: 38-12025 Rev. *O

Page 28 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

AC Analog Mux Bus Specifications

T a ble 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to

5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 31. AC Analog Mux Bus Specifications

Symbol

Description

Min

Typ

Max

3.17

Units

Notes

Switch Rate

–

MHz

AC Digital Block Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 32. 5V and 3.3V AC Digital Block Specifications

Function

All

Functions

Description

Min

Typ

Max

49.2

24.6

–

Units

Notes

Maximum Block Clocking Frequency (> 4.75V)

Maximum Block Clocking Frequency (< 4.75V)

Capture Pulse Width

MHz 4.75V < Vdd < 5.25V.

MHz 3.0V < Vdd < 4.75V.

[19]

Timer

–

Maximum Frequency, No Capture

Maximum Frequency, With or Without Capture

Enable Pulse Width

–

49.2

24.6

–

MHz 4.75V < Vdd < 5.25V.

MHz

Counter

–

Maximum Frequency, No Enable Input

Maximum Frequency, Enable Input

49.2

24.6

MHz 4.75V < Vdd < 5.25V.

MHz

–

Dead Band Kill Pulse Width:

Asynchronous Restart Mode

–

Synchronous Restart Mode

Disable Mode

–

Maximum Frequency

49.2

MHz 4.75V < Vdd < 5.25V.

CRCPRS Maximum Input Clock Frequency

–

(PRS

Mode)

CRCPRS Maximum Input Clock Frequency

(CRC

Mode)

–

24.6

8.2

MHz

SPIM

Maximum Input Clock Frequency

MHz Maximum data rate at 4.1 MHz

due to 2 x over clocking.

SPIS

Maximum Input Clock Frequency

–

4.1

–

MHz

Width of SS_ Negated Between Transmissions

Transmitter Maximum Input Clock Frequency

24.6

MHz Maximum data rate at 3.08 MHz

due to 8 x over clocking.

Maximum Input Clock Frequency with Vdd ≥

4.75V, 2 Stop Bits

–

49.2

MHz Maximum data rate at 6.15 MHz

due to 8 x over clocking.

Receiver

Maximum Input Clock Frequency

–

24.6

49.2

MHz Maximum data rate at 3.08 MHz

due to 8 x over clocking.

MHz Maximum data rate at 6.15 MHz

due to 8 x over clocking.

Maximum Input Clock Frequency with Vdd ≥

4.75V, 2 Stop Bits

Note

19. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).

Document Number: 38-12025 Rev. *O

Page 29 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Table 33. 2.7V AC Digital Block Specifications

Function

All

Description

Min

Typ

Max

Units

Notes

Maximum Block Clocking Frequency

12.7

MHz 2.4V < Vdd < 3.0V.

Functions

[20]

Timer

Capture Pulse Width

100

–

Maximum Frequency, With or Without Capture

Enable Pulse Width

–

100

–

12.7

–

MHz

Counter

Maximum Frequency, No Enable Input

Maximum Frequency, Enable Input

12.7

MHz

–

Dead Band Kill Pulse Width:

Asynchronous Restart Mode

100

–

Synchronous Restart Mode

Disable Mode

–

Maximum Frequency

12.7

MHz

CRCPRS Maximum Input Clock Frequency

–

(PRS

Mode)

CRCPRS Maximum Input Clock Frequency

(CRC

Mode)

–

12.7

6.35

MHz

SPIM

Maximum Input Clock Frequency

MHz Maximum data rate at 3.17 MHz

due to 2 x over clocking.

SPIS

Maximum Input Clock Frequency

–

100

–

4.1

–

MHz

Width of SS_ Negated Between Transmissions

Transmitter Maximum Input Clock Frequency

12.7

MHz Maximum data rate at 1.59 MHz

due to 8 x over clocking.

Receiver Maximum Input Clock Frequency

–

12.7

MHz Maximum data rate at 1.59 MHz

due to 8 x over clocking.

AC External Clock Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C

and are for design guidance only.

Table 34. 5V AC External Clock Specifications

Symbol

Description

Min

0.093

20.6

150

Typ

–

Max

24.6

5300

–

Units

MHz

–

Frequency

High Period

Low Period

OSCEXT

–

Power Up IMO to Switch

–

μs

Note

20. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).

Document Number: 38-12025 Rev. *O

Page 30 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Table 35. 3.3V AC External Clock Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

Frequency with CPU Clock divide by 1

0.093

–

12.3

MHz Maximum CPU frequency is 12

MHz at 3.3V. With the CPU clock

divider set to 1, the external clock

must adhere to the maximum

frequency and duty cycle

OSCEXT

requirements.

Frequency with CPU Clock divide by 2 or

greater

0.186

–

24.6

MHz Ifthefrequencyoftheexternalclock

is greater than 12 MHz, the CPU

clock divider must be set to 2 or

greater. In this case, the CPU clock

divider ensures that the fifty percent

duty cycle requirement is met.

OSCEXT

–

High Period with CPU Clock divide by 1

Low Period with CPU Clock divide by 1

Power Up IMO to Switch

41.7

150

–

5300

μs

–

Table 36. 2.7V AC External Clock Specifications

Symbol

Description

Min

Typ

Max

Units

Notes

Frequency with CPU Clock divide by 1

0.093

–

3.08

MHz Maximum CPU frequency is 3 MHz

at 2.7V. With the CPU clock divider

set to 1, the external clock must

adhere to the maximum frequency

and duty cycle requirements.

OSCEXT

Frequency with CPU Clock divide by 2 or

greater

0.186

–

6.35

MHz Ifthefrequencyoftheexternalclock

is greater than 3 MHz, the CPU

clock divider must be set to 2 or

greater. In this case, the CPU clock

divider ensures that the fifty percent

duty cycle requirement is met.

OSCEXT

–

High Period with CPU Clock divide by 1

Low Period with CPU Clock divide by 1

Power Up IMO to Switch

160

150

–

5300

μs

–

AC Programming Specifications

T a ble 37 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C

≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for

design guidance only.

Table 37. AC Programming Specifications

Symbol

Description

Rise Time of SCLK

Min

Typ

–

Max

–

Units

Notes

RSCLK

FSCLK

SSCLK

HSCLK

SCLK

Fall Time of SCLK

–

Data Set up Time to Falling Edge of SCLK

Data Hold Time from Falling Edge of SCLK

Frequency of SCLK

–

MHz

Flash Erase Time (Block)

–

ERASEB

Document Number: 38-12025 Rev. *O

Page 31 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Table 37. AC Programming Specifications (continued)

Symbol

Description

Flash Block Write Time

Min

–

Typ

–

Max

–

Units

Notes

WRITE

Data Out Delay from Falling Edge of SCLK

–

3.6 < Vdd

DSCLK

DSCLK3

DSCLK2

–

3.0 ≤ Vdd ≤ 3.6

2.4 ≤ Vdd ≤ 3.0

–

AC I C Specifications

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C ≤ T ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 38. AC Characteristics of the I C SDA and SCL Pins for Vdd ≥ 3.0V

Standard Mode

Fast Mode

Symbol

Description

SCL Clock Frequency

Units

Min

Max

100

–

Min

Max

400

–

kHz

SCLI2C

Hold Time (repeated) START Condition.

After this period, the first clock pulse is

generated.

4.0

0.6

μs

HDSTAI2C

LOW Period of the SCL Clock

HIGH Period of the SCL Clock

4.7

4.0

4.7

–

1.3

0.6

–

μs

LOWI2C

HIGHI2C

SUSTAI2C

Set-up Time for a Repeated START

Condition

Data Hold Time

–

μs

HDDATI2C

SUDATI2C

SUSTOI2C

BUFI2C

[21]

Data Set-up Time

250

4.0

4.7

100

Set-up Time for STOP Condition

0.6

1.3

Bus Free Time Between a STOP and START

Condition

Pulse Width of spikes are suppressed by the

input filter.

–

SPI2C

Note

21. A Fast-Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but the requirement t_SU;DAT≥ 250 ns must then be met. This is automatically

the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next

data bit to the SDA line t_rmax+ t_SU;DAT= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

Document Number: 38-12025 Rev. *O

Page 32 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Table 39. 2.7V AC Characteristics of the I C SDA and SCL Pins (Fast Mode not Supported)

Standard Mode

Fast Mode

Symbol

Description

Units

Min

Max

100

–

Min

–

Max

–

SCL Clock Frequency

kHz

SCLI2C

Hold Time (repeated) START Condition.

After this period, the first clock pulse is

generated.

4.0

–

μs

HDSTAI2C

LOW Period of the SCL Clock

HIGH Period of the SCL Clock

4.7

4.0

4.7

–

μs

LOWI2C

HIGHI2C

SUSTAI2C

Set up Time for a Repeated START

Condition

Data Hold Time

–

μs

HDDATI2C

SUDATI2C

SUSTOI2C

BUFI2C

Data Set-up Time

250

4.0

4.7

Set up Time for STOP Condition

Bus Free Time Between a STOP and START

Condition

Pulse Width of spikes are suppressed by the

input filter.

–

SPI2C

Figure 19. Definition for Timing for Fast/Standard Mode on the I C Bus

SDA

SCL

T_SPI2C

LOWI2C

T_SUDATI2C

T_HDSTAI2C

T_BUFI2C

T_SUSTOI2C

T_SUSTAI2C

T_HDDATI2C

T_HDSTAI2C

T_HIGHI2C

Document Number: 38-12025 Rev. *O

Page 33 of 45

http://www.cypress.com/design/MR10161.

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Packaging Information

This section shows the packaging specifications for the CY8C21x34 PSoC device with the thermal impedances for each package.

Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of

the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at

Packaging Dimensions

Figure 20. 16-Pin (150-Mil) SOIC

PIN 1 ID

DIMENSIONS IN INCHES[MM] MIN.

MAX.

REFERENCE JEDEC MS-012

PACKAGE WEIGHT 0.15gms

0.150[3.810]

0.157[3.987]

0.230[5.842]

0.244[6.197]

PART #

S16.15 STANDARD PKG.

SZ16.15 LEAD FREE PKG.

0.010[0.254]

0.016[0.406]

X 45°

0.386[9.804]

0.393[9.982]

SEATING PLANE

0.061[1.549]

0.068[1.727]

0.004[0.102]

0.050[1.270]

BSC

0.0075[0.190]

0.0098[0.249]

0.016[0.406]

0.035[0.889]

0°~8°

0.0138[0.350]

0.0192[0.487]

0.004[0.102]

0.0098[0.249]

51-85068 *B

Figure 21. 20-Pin (210-MIL) SSOP

51-85077 *C

Document Number: 38-12025 Rev. *O

Page 34 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Figure 22. 28-Pin (210-Mil) SSOP

51-85079 *C

Figure 23. 32-Pin (5x5 mm 0.93 MAX) QFN

E-PAD X, Y for this product is 3.53 mm, 3.53 mm (+/-0.11 mm)

51-85188 *B

Document Number: 38-12025 Rev. *O

Page 35 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Figure 24. 32-Pin (5x5 mm 0.60 MAX) QFN

E-PAD X, Y for this product is 3.53 mm, 3.53 mm (+/-0.11 mm)

001-06392 *A

Figure 25. 32-Pin (5 X 5 X 0.4MM) QFN (SAWN 1.85 X 2.85 EPAD

001-44368 *A

Document Number: 38-12025 Rev. *O

Page 36 of 45

http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Figure 26. 32-Pin Sawn QFN Package

001-30999 *A

Figure 27. 32-Pin Thin Sawn QFN Package

001-42168 *C

Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at

Document Number: 38-12025 Rev. *O

Page 37 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Figure 28. 56-Pin (300-Mil) SSOP

51-85062 *C

Thermal Impedances

Table 40. Thermal Impedances per Package

[22]

Package

Typical θ

16 SOIC

20 SSOP

28 SSOP

123 C/W

55 C/W

117 C/W

41 C/W

96 C/W

39 C/W

[23]

32 QFN

5x5 mm 0.60 MAX

5x5 mm 0.93 MAX

27 C/W

15 C/W

[23]

22 C/W

12 C/W

Document Number: 38-12025 Rev. *O

Page 38 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Solder Reflow Peak Temperature

Following is the minimum solder reflow peak temperature to achieve good solderability.

Table 41. Solder Reflow Peak Temperature

[24]

Package

Minimum Peak Temperature

Maximum Peak Temperature

16 SOIC

20 SSOP

28 SSOP

32 QFN

240 C

260 C

240 C

260 C

240 C

260 C

240 C

260 C

Notes

22. T_J= T_A+ Power x θ

23. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane

24. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5^oC with Sn-Pb or 245 ± 5^oC with Sn-Ag-Cu

paste. Refer to the solder manufacturer specifications.

Document Number: 38-12025 Rev. *O

Page 39 of 45

■ ImageCraft Cypress Edition Compiler is available from

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ iMAGEcraft C Compiler (Registration Required)

■ ISSP Cable

Development Tool Selection

This section presents the development tools available for all

current PSoC device families including the CY8C21x34 family.

■ USB 2.0 Cable and Blue Cat-5 Cable

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

Software

PSoC Designer™

At the core of the PSoC development software suite is PSoC

Designer. Used by thousands of PSoC developers, this robust

software has been facilitating PSoC designs for half a decade.

PSoC Designer is available free of charge at

http://www.cypress.com under DESIGN RESOURCES >>

Software and Drivers.

CY3210-ExpressDK PSoC Express Development Kit

The CY3210-ExpressDK is for advanced prototyping and

development with PSoC Express (may be used with ICE-Cube

In-Circuit Emulator). It provides access to I C buses, voltage

reference, switches, upgradeable modules and more. The kit

includes:

PSoC Programmer

■ PSoC Express Software CD

■ Express Development Board

■ 4 Fan Modules

Flexible enough to be used on the bench in development, yet

suitable for factory programming, PSoC Programmer works

either as a standalone programming application or operates

directly from PSoC Designer or PSoC Express. PSoC

Programmer software is compatible with both PSoC ICE-Cube

In-Circuit Emulator and PSoC MiniProg. PSoC programmer is

available free ofcharge at http://www.cypress.com/psocpro-

grammer.

■ 2 Proto Modules

■ MiniProg In-System Serial Programmer

■ MiniEval PCB Evaluation Board

■ Jumper Wire Kit

C Compilers

■ USB 2.0 Cable

PSoC Designer comes with a free HI-TECH C Lite C compiler.

The HI-TECH C Lite compiler is free, supports all PSoC devices,

integrates fully with PSoC Designer and PSoC Express, and

runs on Windows versions up to 32-bit Vista. Compilers with

additional features are available at additional cost from their

manufactures.

■ Serial Cable (DB9)

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ 2 CY8C24423A-24PXI 28-PDIP Chip Samples

■ 2 CY8C27443-24PXI 28-PDIP Chip Samples

■ 2 CY8C29466-24PXI 28-PDIP Chip Samples

■ HI-TECH C PRO for the PSoC is available from

http://www.htsoft.com.

http://www.imagecraft.com.

Evaluation Tools

All evaluation tools can be purchased from the Cypress Online

Store.

Development Kits

All development kits can be purchased from the Cypress Online

Store.

CY3210-MiniProg1

The CY3210-MiniProg1 kit allows a user to program PSoC

devices through the MiniProg1 programming unit. The MiniProg

is a small, compact prototyping programmer that connects to the

PC through a provided USB 2.0 cable. The kit includes:

CY3215-DK Basic Development Kit

The CY3215-DK is for prototyping and development with PSoC

Designer. This kit supports in-circuit emulation and the software

interface allows users to run, halt, and single step the processor

and view the content of specific memory locations. Advance

emulation features also supported through PSoC Designer. The

kit includes:

■ MiniProg Programming Unit

■ MiniEval Socket Programming and Evaluation Board

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample

■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample

■ PSoC Designer Software CD

■ ICE-Cube In-Circuit Emulator

■ ICE Flex-Pod for CY8C29x66 Family

■ Cat-5 Adapter

■ Getting Started Guide

■ USB 2.0 Cable

■ Mini-Eval Programming Board

Document Number: 38-12025 Rev. *O

Page 40 of 45

production using an on-chip debug (OCD) non-production PSoC

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

CY3210-PSoCEval1

Device Programmers

The CY3210-PSoCEval1 kit features an evaluation board and

the MiniProg1 programming unit. The evaluation board includes

an LCD module, potentiometer, LEDs, and plenty of bread-

boarding space to meet all of your evaluation needs. The kit

includes:

All device programmers can be purchased from the Cypress

Online Store.

CY3216 Modular Programmer

The CY3216 Modular Programmer kit features a modular

programmer and the MiniProg1 programming unit. The modular

programmer includes three programming module cards and

supports multiple Cypress products. The kit includes:

■ Evaluation Board with LCD Module

■ MiniProg Programming Unit

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)

■ PSoC Designer Software CD

■ Getting Started Guide

■ Modular Programmer Base

■ 3 Programming Module Cards

■ MiniProg Programming Unit

■ PSoC Designer Software CD

■ Getting Started Guide

■ USB 2.0 Cable

CY3214-PSoCEvalUSB

The CY3214-PSoCEvalUSB evaluation kit features

■ USB 2.0 Cable

development board for the CY8C24794-24LFXI PSoC device.

Special features of the board include both USB and capacitive

sensing development and debugging support. This evaluation

board also includes an LCD module, potentiometer, LEDs, an

enunciator and plenty of bread boarding space to meet all of your

evaluation needs. The kit includes:

CY3207ISSP In-System Serial Programmer (ISSP)

The CY3207ISSP is a production programmer. It includes

protection circuitry and an industrial case that is more robust than

the MiniProg in a production-programming environment.

Note CY3207ISSP needs special software and is not compatible

with PSoC Programmer. The kit includes:

■ PSoCEvalUSB Board

■ CY3207 Programmer Unit

■ PSoC ISSP Software CD

■ LCD Module

■ MIniProg Programming Unit

■ Mini USB Cable

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ USB 2.0 Cable

■ PSoC Designer and Example Projects CD

■ Getting Started Guide

■ Wire Pack

Accessories (Emulation and Programming)

Table 42. Emulation and Programming Accessories

[25]

[26]

Part #

Pin Package

16 SOIC

Flex-Pod Kit

CY3250-21X34

Foot Kit

Adapter

CY8C21234-24S

CY3250-16SOIC-FK

CY3250-20SSOP-FK

CY3250-32QFN-FK

CY3250-28SSOP-FK

CY3250-32QFN-FK

Programmingadapterconverts

non-DIP package to DIP

footprint. Specific details and

orderinginformationforeachof

the adapters can be found at

http://www.emulation.com.

CY8C21334-24PVXI

CY8C21434-24LFXI

CY8C21534-24PVXI

CY8C21634-24LFXI

20 SSOP

32 QFN

28 SSOP

32 QFN

CY3250-21X34

CY3250-21X34QFN

CY3250-21X34

CY3250-21X34QFN

Third-Party Tools

Build a PSoC Emulator into Your Board

Several tools have been specially designed by the following

3rd-party vendors to accompany PSoC devices during devel-

opment and production. Specific details for each of these tools

can be found at http://www.cypress.com under DESIGN

RESOURCES >> Evaluation Boards.

For details on how to emulate your circuit before going to volume

device, see Application Note AN2323 “Debugging - Build a PSoC

Emulator into Your Board”.

Notes

25. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.

26. Foot kit includes surface mount feet that can be soldered to the target PCB.

Document Number: 38-12025 Rev. *O

Page 41 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Ordering Information

16 Pin (150-Mil) SOIC

CY8C21234-24SXI

CY8C21234-24SXIT

512 Yes -40°C to +85°C

16 Pin (150-Mil) SOIC

(Tape and Reel)

20 Pin (210-Mil) SSOP

CY8C21334-24PVXI

CY8C21334-24PVXIT

512 No

-40°C to +85°C

Yes

20 Pin (210-Mil) SSOP

(Tape and Reel)

28 Pin (210-Mil) SSOP

CY8C21534-24PVXI

CY8C21534-24PVXIT

512 No

-40°Cto +85°C

-40°C to +85°C

Yes

28 Pin (210-Mil) SSOP

(Tape and Reel)

32 Pin (5x5 mm 0.93 MAX)

CY8C21434-24LFXI

512 No

-40°C to +85°C

Yes

QFN

32Pin(5x5mm0.93MAX)QFN CY8C21434-24LFXIT

b (Tape and Reel)

32Pin(5x5mm0.60MAX)QFN CY8C21434-24LKXI

32Pin(5x5mm0.60MAX)QFN CY8C21434-24LKXIT

(Tape and Reel)

32Pin(5x5mm0.93MAX)QFN CY8C21634-24LFXI

512 Yes -40°C to +85°C

32Pin(5x5mm0.93MAX)QFN CY8C21634-24LFXIT

(Tape and Reel)

32 Pin (5x5 mm 1.00 MAX)

SAWN QFN

CY8C21434-24LTXI

CY8C21434-24LTXIT

512 No

-40°C to +85°C

32 Pin (5x5 mm 1.00 MAX)

SAWN QFN

Reel)

(Tape and

32 Pin (5x5 mm 0.40 MAX)

CY8C21434-24LCXI

CY8C21434-24LCXIT

512 No

-40°C to +85°C

Yes

SAWN QFN

32 Pin (5x5 mm 0.40 MAX)

SAWN QFN

(Tape and Reel)

32 Pin (5x5 mm 0.60 MAX)

THIN SAWN QFN

CY8C21434-24LQXI

CY8C21434-24LQXIT

512 No

-40°C to +85°C

Yes

32 Pin (5x5 mm 0.60 MAX)

THIN SAWN QFN

(Tape and Reel)

32 Pin (5x5 mm 0.93 MAX)

CY8C21634-24LTXI

CY8C21634-24LTXIT

512 Yes -40°C to +85°C

Yes

SAWN QFN

32 Pin (5x5 mm 0.93 MAX)

SAWN QFN

(Tape and Reel)

56 Pin OCD SSOP

CY8C21001-24PVXI

512 Yes -40°C to +85°C

Yes

Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).

Notes

27. All Digital IO Pins also connect to the common analog mux.

28. Refer to the section 32-Pin Part Pinout on page 11 for pin differences.

Document Number: 38-12025 Rev. *O

Page 42 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Ordering Code Definitions

CY 8 C 21 xxx-24xx

Package Type:

Thermal Rating:

C = Commercial

I = Industrial

PX = PDIP Pb-Free

SX = SOIC Pb-Free

PVX = SSOP Pb-Free

LFX/LKX = QFN Pb-Free

AX = TQFP Pb-Free

E = Extended

Speed: 24 MHz

Part Number

Family Code

Technology Code: C = CMOS

Marketing Code: 8 = Cypress PSoC

Company ID: CY = Cypress

Document Number: 38-12025 Rev. *O

Page 43 of 45

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Document History Page

Document Title: CY8C21234/CY8C21334/CY8C21434/CY8C21534/CY8C21634 PSoC Programmable System-on-Chip™

Document Number: 38-12025

Orig. of

Change

Submission

Date

Revision ECN No.

Description of Change

New silicon and document (Revision **).

227340

235992

HMT

See ECN

SFV

Updated Overview and Electrical Spec. chapters, along with revisions to the

24-pin pinout part. Revised the register mapping tables. Added a SSOP

28-pin part.

248572

277832

SFV

See ECN

Changed title to include all part #s. Changed 28-pin SSOP from CY8C21434

to CY8C21534. Changed pin 9 on the 28-pin SSOP from SMP pin to Vss pin.

Added SMP block to architecture diagram. Update Electrical Specifications.

Added another 32-pin MLF part: CY8C21634.

HMT

Verify data sheet standards from SFV memo. Add Analog Input Mux to appli-

cable pin outs. Update PSoC Characteristics table. Update diagrams and

specs. Final.

285293

301739

329104

HMT

See ECN

Update 2.7V DC GPIO spec. Add Reflow Peak Temp. table.

DC Chip-Level Specification changes. Update links to new CY.com Portal.

Re-add pinout ISSP notation. Fix TMP register names. Clarify ADC feature.

Update Electrical Specifications. Update Reflow Peak Temp. table. Add 32

MLF E-PAD dimensions. Add ThetaJC to Thermal Impedance table. Fix

20-pin package order number. Add CY logo. Update CY copyright.

352736

HMT

See ECN

Add new color and logo. Add URL to preferred dimensions for mounting MLF

packages. Update Transmitter and Receiver AC Digital Block Electrical

Specifications.

390152

413404

430185

HMT

See ECN

Clarify MLF thermal pad connection info. Replace 16-pin 300-MIL SOIC with

correct 150-MIL.

Update 32-pin QFN E-Pad dimensions and rev. *A. Update CY branding and

QFN convention.

Add new 32-pin 5x5 mm 0.60 thickness QFN package and diagram,

CY8C21434-24LKXI. Update thermal resistance data. Add 56-pin SSOP

on-chip debug non-production part, CY8C21001-24PVXI. Update typical and

recommended Storage Temperature per industrial specs. Update copyright

and trademarks.

677717

HMT

See ECN

Add CapSense SNR requirement reference. Add new Dev. Tool section. Add

CY8C20x34 to PSoC Device Characteristics table. Add Low Power

Comparator (LPC) AC/DC electrical spec. tables. Update rev. of32-Lead (5x5

mm 0.60 MAX) QFN package diagram.

2147847 UVS/PYRS

2273246 UVS/AESA

02/27/08

04/01/08

Added 32-Pin QFN Sawn pin diagram, package diagram, and ordering infor-

mation.

Added 32 pin thin sawn package diagram.

2618124 OGNE/PYRS 12/09/08

Added Note in Ordering Information section.

Changed title from PSoC Mixed-Signal Array to PSoC

Programmable System-on-Chip

2684145 SNV/AESA

04/06/2009

Updated 32-Pin Sawn QFN package dimension for CY8C21434-24LTXIT

Updated Getting Started, Development Tools, and Designing with PSoC

Designer Sections

Document Number: 38-12025 Rev. *O

Page 44 of 45

psoc.cypress.com/solutions

CY8C21634, CY8C21534

CY8C21434, CY8C21334, CY8C21234

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at cypress.com/sales.

Products

PSoC

PSoC Solutions

General

psoc.cypress.com/low-power

psoc.cypress.com/precision-analog

psoc.cypress.com/lcd-drive

psoc.cypress.com/can

Clocks & Buffers

Wireless

Low Power/Low Voltage

Precision Analog

LCD Drive

Memories

Image Sensors

CAN 2.0b

USB

psoc.cypress.com/usb

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 38-12025 Rev. *O

Revised April 06, 2009

Page 45 of 45

PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced

herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights

to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document

may be the trademarks of their respective holders.