CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
72-Mbit DDR-II+ SRAM 2-Word Burst
Architecture (2.0 Cycle Read Latency)
Features
Functional Description
■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
■ 375 MHz clock for high bandwidth
The CY7C1546V18, CY7C1557V18, CY7C1548V18, and
CY7C1550V18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of both K and K. Each address location is associated with two
8-bit words (CY7C1546V18), 9-bit words (CY7C1557V18),
18-bit words (CY7C1548V18), or 36-bit words (CY7C1550V18)
that burst sequentially into or out of the device.
■ 2-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces
(data transferred at 750 MHz) at 375 MHz
■ Available in 2.0 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
Asynchronous inputs include an output impedance matching
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ Core V = 1.8V ± 0.1V; IO V
= 1.4V to V
DD
DD
DDQ
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1546V18 – 8M x 8
CY7C1557V18 – 8M x 9
CY7C1548V18 – 4M x 18
CY7C1550V18 – 2M x 36
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
375 MHz
375
333 MHz
333
300 MHz
300
Unit
MHz
mA
x8
x9
1300
1300
1300
1300
1200
1200
1200
1200
1100
1100
x18
x36
1100
1100
Note
1. The QDR consortium specification for V
is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V
DDQ
DDQ
= 1.4V to V
.
DD
Cypress Semiconductor Corporation
Document Number: 001-06550 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 11, 2008
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Logic Block Diagram (CY7C1548V18)
Write
Reg
Write
Reg
21
A
(20:0)
Address
Register
LD
18
K
K
Output
Logic
Control
CLK
Gen.
R/W
DOFF
Read Data Reg.
36
CQ
CQ
V
18
REF
18
18
Reg.
Reg.
Reg.
Control
Logic
R/W
DQ
[17:0]
18
BWS
18
[1:0]
QVLD
Logic Block Diagram (CY7C1550V18)
Write
Reg
Write
Reg
20
A
(19:0)
Address
Register
LD
36
K
Output
Logic
Control
CLK
Gen.
K
R/W
DOFF
Read Data Reg.
72
36
CQ
CQ
V
REF
36
36
Reg.
Reg.
Reg.
Control
Logic
R/W
DQ
[35:0]
36
BWS
36
[3:0]
QVLD
Document Number: 001-06550 Rev. *E
Page 3 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Pin Configuration
The pin configuration for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follow.
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1546V18 (8M x 8)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
3
4
R/W
A
5
6
K
K
A
7
8
LD
A
9
10
A
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
A
B
C
D
E
F
A
A
NWS
NC/144M
A
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQ4
NC
DQ5
NC/288M
A
NWS
A
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0
V
V
V
SS
SS
SS
SS
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
G
H
J
V
V
V
V
REF
REF
DDQ
DDQ
NC
NC
NC
DQ1
NC
NC
DQ0
NC
NC
NC
TDI
K
L
NC
DQ6
NC
NC
NC
NC
NC
DQ7
A
NC
NC
NC
NC
NC
A
NC
NC
V
V
V
V
SS
SS
SS
SS
M
N
P
R
V
V
NC
SS
SS
SS
NC
V
A
A
A
A
A
A
A
V
NC
SS
NC
A
A
QVLD
NC
A
A
NC
TCK
TMS
CY7C1557V18 (8M x 9)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
3
4
5
NC
6
K
K
A
7
8
9
10
A
11
CQ
DQ3
NC
A
B
C
D
E
F
A
A
R/W
A
NC/144M
LD
A
A
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQ4
NC
DQ5
NC/288M
A
BWS
A
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0
V
V
V
SS
SS
SS
SS
V
V
V
V
V
V
NC
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQ2
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
G
H
J
NC
V
V
V
V
REF
ZQ
REF
DDQ
DDQ
NC
NC
NC
NC
DQ1
NC
NC
K
L
NC
NC
NC
NC
DQ7
A
NC
NC
NC
NC
NC
A
NC
DQ6
NC
V
V
NC
DQ0
NC
SS
SS
SS
SS
M
N
P
R
V
V
V
V
NC
SS
SS
SS
NC
V
A
A
A
A
A
A
A
V
NC
NC
SS
NC
A
A
QVLD
NC
A
A
NC
DQ8
TDI
TCK
TMS
Note
2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-06550 Rev. *E
Page 4 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Pin Configuration (continued)
[2]
The pin configuration for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follow.
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1548V18 (4M x 18)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
A
3
4
R/W
A
5
6
K
7
8
LD
A
9
10
A
11
CQ
A
B
C
D
E
F
A
BWS
NC/144M
A
1
DQ9
NC
NC
NC
DQ12
NC
NC
NC/288M
A
K
BWS
A
NC
NC
NC
NC
NC
NC
NC
DQ7
NC
NC
NC
NC
DQ8
NC
0
NC
V
V
NC
V
SS
SS
SS
SS
DQ10
DQ11
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NC
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQ6
DQ5
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
G
H
J
DQ13
V
V
V
V
REF
ZQ
REF
DDQ
DDQ
NC
NC
NC
DQ14
NC
NC
DQ4
NC
NC
K
L
NC
NC
NC
NC
NC
A
DQ3
DQ2
NC
DQ15
NC
V
V
V
V
NC
SS
SS
SS
SS
M
N
P
R
NC
V
V
DQ1
NC
SS
SS
SS
NC
DQ16
DQ17
A
V
A
A
A
A
A
A
A
V
NC
SS
NC
A
A
QVLD
NC
A
A
NC
DQ0
TDI
TCK
TMS
CY7C1550V18 (2M x 36)
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/144M
DQ27
NC
3
4
5
BWS
BWS
A
6
K
7
BWS
BWS
A
8
9
10
A
11
A
B
C
D
E
F
A
R/W
A
LD
A
A
CQ
2
3
1
0
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
K
NC
NC
NC
NC
NC
NC
NC
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
V
V
NC
V
DQ17
NC
SS
SS
SS
SS
DQ29
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DQ15
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DQ30
DQ31
V
V
V
V
V
V
V
V
V
V
G
H
J
NC
V
V
V
V
REF
REF
DDQ
DDQ
NC
NC
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
A
NC
DQ13
DQ12
NC
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
K
L
NC
NC
NC
NC
NC
A
DQ33
NC
V
V
SS
SS
SS
SS
M
N
P
R
V
V
V
V
DQ11
NC
SS
SS
SS
DQ35
NC
V
A
A
A
A
A
A
A
V
SS
A
A
QVLD
NC
A
A
DQ9
TMS
TCK
Document Number: 001-06550 Rev. *E
Page 5 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Pin Definitions
Pin Name
IO
Pin Description
Data Input or Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid
write operations. These pins drive out the requested data during a read operation. Valid data is driven
out on the rising edge of both the K and K clocks during read operations. When read access is
DQ
Input and
Output
Synchronous
[x:0]
deselected, Q
are automatically tri-stated.
[x:0]
CY7C1546V18 − DQ
CY7C1557V18 − DQ
CY7C1548V18 − DQ
CY7C1550V18 − DQ
[7:0]
[8:0]
[17:0]
[35:0]
LD
Input
Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when a
Synchronous bus cycle sequence is defined. This definition includes address and read or write direction. All trans-
actions operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.
NWS , NWS Input
Nibble Write Select 0, 1 − Active LOW (CY7C1546V18 only). Sampled on the rising edge of the K
Synchronous and K clocks during write operations. Used to select the nibble that is written into the device during
the current portion of the write operations. Nibbles not written remain unaltered.
0
1
NWS controls D
and NWS controls D
.
0
[3:0]
1
[7:4]
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write
Select ignores the corresponding nibble of data and does not write into the device.
BWS BWS
Input
Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks
,
,
1
3
0
Synchronous during write operations. Used to select the byte written into the device during the current portion of
the write operations. Bytes not written remain unaltered.
BWS , BWS
2
CY7C1557V18 − BWS controls D
0
[8:0]
[8:0]
[8:0]
CY7C1548V18 − BWS controls D
and BWS controls D
0
1
[17:9].
, BWS controls D
CY7C1550V18 − BWS controls D
, BWS controls D
and BWS
[26:18] 3
0
1
[17:9]
2
controls D
.
[35:27]
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and does not write into the device.
A
Input
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.
Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 8M x 8 (2 arrays each of 4M x 8) for CY7C1546V18, 8M x 9 (2 arrays each of 4M x 9)
for CY7C1557V18, 4M x 18 (2 arrays each of 2M x 18) for CY7C1548V18, and 2M x 36 (2 arrays
each of 1M x 36) for CY7C1550V18.
R/W
Input
Synchronous Read or Write Input. When LD is LOW, this input designates the access type (read
Synchronous when R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold
times around edge of K.
QVLD
K
Valid output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and
indicator
CQ.
Input
Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
when in single clock mode. All accesses are initiated on the rising
[x:0]
edge of K.
K
Input
Clock
Negative Input Clock Input. K is used to capture synchronous data presented to the device and to
drive out data through Q when in single clock mode.
[x:0]
CQ
Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
CQ
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
Clock Output
Document Number: 001-06550 Rev. *E
Page 6 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Pin Definitions (continued)
Pin Name
ZQ
IO
Pin Description
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q output impedance are set to 0.2 x RQ, where RQ is a resistor
[x:0]
connected between ZQ and ground. Alternatively, this pin is connected directly to V
and enables
DDQ
the minimum impedance mode. This pin is not connected directly to GND or left unconnected.
DOFF
Input
DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
timing in the DLL turned off operation is different from that listed in this datasheet. For normal
operation, this pin is connected to a pull up through a 10 Kohm or less pull up resistor. The device
behaves in DDR-I mode when the DLL is turned off. In this mode, the device is operated at a
frequency of up to 167 MHz with DDR-I timing.
TDO
Output
Input
Input
Input
N/A
TDO for JTAG.
TCK
TCK Pin for JTAG.
TDI
TDI Pin for JTAG.
TMS
TMS Pin for JTAG.
NC
Not Connected to the Die. Is tied to any voltage level.
Not Connected to the Die. Is tied to any voltage level.
Not Connected to the Die. Is tied to any voltage level.
Not Connected to the Die. Is tied to any voltage level.
Reference Voltage Input. Static input is used to set the reference level for HSTL inputs, outputs,
NC/72M
NC/144M
NC/288M
N/A
N/A
N/A
V
Input
REF
Reference and AC measurement points.
V
V
V
Power Supply Power Supply Inputs to the Core of the Device.
DD
Ground
Ground for the Device.
SS
Power Supply Power Supply Inputs for the Outputs of the Device.
DDQ
Document Number: 001-06550 Rev. *E
Page 7 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
the positive input clock (K). Doing so pipelines the data flow such
that 18 bits of data is transferred into the device on every rising
edge of the input clocks (K and K).
Functional Overview
The CY7C1546V18, CY7C1557V18, CY7C1548V18, and
CY7C1550V18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface.
When the write access is deselected, the device ignores all
inputs after the pending write operations are completed.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input and output timing is referenced
from the rising edge of the input clocks (K and K).
Byte Write Operations
Byte write operations are supported by the CY7C1548V18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS and
All synchronous data inputs (D
) pass through input registers
[x:0]
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q ) pass through output registers
0
BWS , which are sampled with each set of 18-bit data words.
1
[x:0]
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read, modify, or write operations to a byte write
operation.
controlled by the rising edge of the input clocks (K and K).
All synchronous control (R/W, LD, NWS , BWS ) inputs
[x:0]
[x:0]
pass through input registers controlled by the rising edge of the
input clock (K).
CY7C1548V18 is described in the following sections. The same
basic descriptions apply to CY7C1546V18, CY7C1557V18, and
CY7C1550V18.
Double Date Rate Operation
Read Operations
The CY7C1548V18 enables high-performance operation
through high clock frequencies (achieved through pipelining) and
DDR mode of operation. The CY7C1548V18 requires a
minimum of two No Operation (NOP) cycle during transition from
a read to a write cycle. At higher frequencies, some applications
require third NOP cycle to avoid contention.
The CY7C1548V18 is organized internally as two arrays of 2M x
18. Accesses are completed in a burst of two sequential 18-bit
data words. Read operations are initiated by asserting R/W
HIGH and LD LOW at the rising edge of the positive input clock
(K). The address presented to the address inputs is stored in the
read address register. Following the next two K clock rise, the
corresponding 18-bit word of data from this address location is
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information is stored because
the SRAM cannot perform the last word write to the array without
conflicting with the read. The data stays in this register until the
next write cycle occurs. On the first write cycle after the read(s),
the stored data from the earlier write is written into the SRAM
array. This is called a Posted write.
driven onto the Q
using K as the output timing reference. On
[17:0]
the subsequent rising edge of K, the next 18-bit data word is
driven onto the Q . The requested data is valid 0.45 ns from
[17:0]
the rising edge of the input clock (K and K). To maintain the
internal logic, each read access must be allowed to complete.
Read accesses can be initiated on every rising edge of the
positive input clock (K).
If a read is performed on the same address on which a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.
When read access is deselected, the CY7C1548V18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the output following the next
rising edge of the positive input clock (K). This enables a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register. On the following K clock rise, the data
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V to allow the SRAM to adjust its output
SS
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω, with V
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
presented to D
data register, provided BWS
is latched and stored into the 18-bit write
[17:0]
are both asserted active. On the
[1:0]
subsequent rising edge of the negative input clock (K), the infor-
mation presented to D is also stored into the write data
= 1.5V. The
DDQ
[17:0]
register, provided BWS
are both asserted active. The 36 bits
[1:0]
of data are then written into the memory array at the specified
location. Write accesses can be initiated on every rising edge of
Document Number: 001-06550 Rev. *E
Page 8 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Echo Clocks
DLL
Echo clocks are provided on the DDR-II+ to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR-II+. CQ is referenced with respect to K and CQ is refer-
enced with respect to K. These are free-running clocks and are
synchronized to the input clock of the DDR-II+. The timing for the
These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF pin. When the DLL is turned off, the device behaves in
DDR-I mode (with 1.0 cycle latency and a longer access time).
For more information, refer to the application note, “DLL Consid-
erations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be
reset by slowing or stopping the input clocks K and K for a
minimum of 30ns. However, it is not necessary to reset the DLL
to lock to the desired frequency. During Power-up, when the
DOFF is tied HIGH, the DLL gets locked after 2048 cycles of
stable clock.
Valid Data Indicator (QVLD)
QVLD is provided on the DDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the DDR-II+ device
along with data output. This signal is also edge aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
Application Example
Figure 1 shows two DDR-II+ used in an application.
Figure 1. Application Example
ZQ
CQ/CQ
K
K
ZQ
CQ/CQ
K
K
SRAM#1
LD R/W
SRAM#2
DQ
DQ
R = 250ohms
R = 250ohms
LD R/W
A
A
DQ
Addresses
Cycle Start
R/W
Source CLK
Source CLK
BUS
MASTER
(CPU or ASIC)
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
Document Number: 001-06550 Rev. *E
Page 9 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Truth Table
The truth table for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follows.
Operation
K
LD
R/W
DQ
DQ
Write Cycle:
Load address; wait one cycle;
L-H
L
L
D(A) at K(t + 1) ↑
D(A+1) at K(t + 1) ↑
input write data on consecutive K and K rising edges.
Read Cycle: (2.0 cycle Latency)
Load address; wait two cycle;
L-H
L
H
Q(A) at K(t + 2) ↑
Q(A+1) at K(t + 2) ↑
read data on consecutive K and K rising edges.
NOP: No Operation
L-H
H
X
X
X
High Z
High Z
Standby: Clock Stopped
Stopped
Previous State
Previous State
Write Cycle Descriptions
The write cycle description table for CY7C1546V18 and CY7C1548V18 follows.
BWS / BWS /
0
1
K
Comments
K
NWS
NWS
1
0
L
L
L
L
L–H
–
During the data portion of a write sequence:
CY7C1546V18 − both nibbles (D
) are written into the device.
[7:0]
CY7C1548V18 − both bytes (D
) are written into the device.
[17:0]
–
L–H
–
L-H During the data portion of a write sequence:
CY7C1546V18 − both nibbles (D
) are written into the device.
) are written into the device.
[7:0]
CY7C1548V18 − both bytes (D
[17:0]
L
H
H
L
–
During the data portion of a write sequence:
CY7C1546V18 − only the lower nibble (D
) is written into the device, D
remains unaltered.
remains unaltered.
[3:0]
[7:4]
CY7C1548V18 − only the lower byte (D
) is written into the device, D
[8:0]
[17:9]
L
L–H During the data portion of a write sequence:
CY7C1546V18 − only the lower nibble (D
) is written into the device, D
remains unaltered.
remains unaltered.
[3:0]
[7:4]
CY7C1548V18 − only the lower byte (D
) is written into the device, D
[8:0]
[17:9]
H
H
L–H
–
–
During the data portion of a write sequence:
CY7C1546V18 − only the upper nibble (D
) is written into the device, D
) is written into the device, D
remains unaltered.
[3:0]
[7:4]
CY7C1548V18 − only the upper byte (D
remains unaltered.
[17:9]
[8:0]
L
L–H During the data portion of a write sequence:
CY7C1546V18 − only the upper nibble (D
) is written into the device, D
) is written into the device, D
remains unaltered.
remains unaltered.
[7:4]
[3:0]
[8:0]
CY7C1548V18 − only the upper byte (D
[17:9]
H
H
H
H
L–H
–
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Notes
3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
4. Device powers up deselected with the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
8. Cypress recommends that K = K = HIGH when clock is stopped. This is not essential but permits most rapid restart by overcoming transmission line charging
symmetrically.
9. Is based on a write cycle is initiated as per the Write Cycle Descriptions table. NWS , NWS , BWS , BWS , BWS , and BWS is altered on different portions of a write
0
1
0
1
2
3
cycle, as long as the setup and hold requirements are met.
Document Number: 001-06550 Rev. *E
Page 10 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Write Cycle Descriptions
The write cycle description table for CY7C1557V18 follows.
BWS
K
L–H
–
K
Comments
0
L
L
–
During the data portion of a write sequence, the single byte (D
) is written into the device.
) is written into the device.
[8:0]
L–H During the data portion of a write sequence, the single byte (D
[8:0]
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1550V18 follows.
BWS
BWS
BWS
BWS
3
K
K
Comments
0
1
2
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D
the device.
) are written into
) are written into
[35:0]
L
L
L
H
H
L
L
H
H
H
H
L
L
H
H
H
H
H
H
L
–
L–H
–
L–H During the data portion of a write sequence, all four bytes (D
the device.
[35:0]
–
During the data portion of a write sequence, only the lower byte (D
) is written
) is written
[8:0]
[8:0]
into the device. D
remains unaltered.
[35:9]
L
L–H During the data portion of a write sequence, only the lower byte (D
into the device. D remains unaltered.
[35:9]
H
H
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D
) is written into
[17:9]
the device. D
and D
remain unaltered.
[8:0]
[35:18]
L
L–H During the data portion of a write sequence, only the byte (D
the device. D and D remain unaltered.
) is written into
[17:9]
[8:0]
[35:18]
H
H
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D
) is written into
) is written into
) is written into
) is written into
[26:18]
[26:18]
[35:27]
[35:27]
the device. D
and D
remain unaltered.
[17:0]
[35:27]
L
L–H During the data portion of a write sequence, only the byte (D
the device. D and D remain unaltered.
[17:0]
[35:27]
H
H
L–H
–
–
During the data portion of a write sequence, only the byte (D
the device. D remains unaltered.
[26:0]
L
L–H During the data portion of a write sequence, only the byte (D
the device. D remains unaltered.
[26:0]
H
H
H
H
H
H
H
H
L–H
–
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Document Number: 001-06550 Rev. *E
Page 11 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
page 15. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
(V ) to prevent clocking of the device. TDI and TMS are inter-
SS
nally pulled up and may be unconnected. They may alternatively
be connected to V through a pull up resistor. TDO must be left
unconnected. Upon power up, the device comes up in a reset
state, which does not interfere with the operation of the device.
Bypass Register
DD
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (V ) when
the BYPASS instruction is executed.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
SS
Boundary Scan Register
Test Mode Select (TMS)
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up inter-
nally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
Test Data-Out (TDO)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (V ) for five rising
TAP Instruction Set
DD
edges of TCK. This Reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high-Z state.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
RESERVED and must not be used. The other five instructions
are described in this section in detail.
TAP Registers
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction once it is shifted in, the TAP controller must be
moved into the Update-IR state.
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document Number: 001-06550 Rev. *E
Page 12 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
IDCODE
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High-Z state until the next command is supplied during the
Update IR state.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
SAMPLE/PRELOAD
EXTEST OUTPUT BUS TRI-STATE
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High-Z condition.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is pre-set HIGH to enable
the output when the device is powered up, and also when the
TAP controller is in the Test-Logic-Reset state.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (t and t ). The SRAM clock input might not be captured
CS
CH
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
Document Number: 001-06550 Rev. *E
Page 13 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
TAP Controller State Diagram
The state diagram for the TAP controller follows.
TEST-LOGIC
1
RESET
0
1
1
1
SELECT
TEST-LOGIC/
SELECT
0
IR-SCAN
IDLE
DR-SCAN
0
0
1
1
CAPTURE-DR
0
CAPTURE-IR
0
0
0
SHIFT-DR
1
SHIFT-IR
1
1
0
1
EXIT1-DR
0
EXIT1-IR
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-IR
UPDATE-DR
1
1
0
0
Note
10. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-06550 Rev. *E
Page 14 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
TAP Controller Block Diagram
0
Bypass Register
2
1
1
1
0
0
0
Selection
TDI
Selection
Circuitry
TDO
Instruction Register
Circuitry
31 30
29
.
.
2
Identification Register
.
108
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the Operating Range
Parameter
Description
Output HIGH Voltage
Test Conditions
= −2.0 mA
Min
1.4
1.6
Max
Unit
V
V
V
V
V
V
I
I
I
I
I
V
V
OH1
OH2
OL1
OL2
IH
OH
OH
OL
OL
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
= −100 μA
= 2.0 mA
0.4
0.2
V
= 100 μA
V
0.65V
V
+ 0.3
V
DD
DD
Input LOW Voltage
–0.3
–5
0.35V
5
V
IL
DD
Input and Output Load Current
GND ≤ V ≤ V
DD
μA
X
I
Notes
11. These characteristics apply to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in Electrical Characteristics on page 20.
12. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
13. All voltage refers to ground.
Document Number: 001-06550 Rev. *E
Page 15 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
TAP AC Switching Characteristics
Over the Operating Range
Parameter
Description
Min
Max
Unit
ns
t
t
t
t
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
50
TCYC
TF
20
MHz
ns
20
20
TH
TCK Clock LOW
ns
TL
Setup Times
t
t
t
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
ns
TMSS
TDIS
CS
Hold Times
t
t
t
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
TMSH
TDIH
CH
Capture Hold after Clock Rise
Output Times
t
t
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
TDOV
TDOX
0
TAP Timing and Test Conditions
Figure 2. TAP Timing and Test Conditions
0.9V
ALL INPUT PULSES
0.9V
50Ω
1.8V
TDO
0V
Z = 50Ω
0
C = 20 pF
L
GND
(a)
t
TL
t
TH
Test Clock
TCK
t
TCYC
t
TMSH
t
TMSS
Test Mode Select
TMS
t
TDIS
t
TDIH
Test Data In
TDI
Test Data Out
TDO
t
TDOV
t
TDOX
Note
14. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
Document Number: 001-06550 Rev. *E
Page 16 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Identification Register Definitions
Value
Instruction Field
Description
CY7C1546V18
CY7C1557V18
000
CY7C1548V18
000
CY7C1550V18
Revision Number
(31:29)
000
000
Version number.
Cypress Device ID 11010111100000100 11010111100001100 11010111100010100 11010111100100100 Defines the type of
(28:12)
SRAM.
Cypress JEDEC ID
(11:1)
00000110100
1
00000110100
1
00000110100
1
00000110100
1
Enables unique
identification of
SRAM vendor.
ID Register
Presence (0)
Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
Bypass
3
1
ID
32
109
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-06550 Rev. *E
Page 17 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Boundary Scan Order
Bit Number
Bump ID
6R
Bit Number
28
Bump ID
10G
9G
Bit Number
56
Bump ID
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
3D
3C
1D
2C
3E
2D
2E
1E
2F
Bit Number
84
Bump ID
1J
0
1
6P
29
57
85
2J
2
6N
30
11F
11G
9F
58
86
3K
3
7P
31
59
87
3J
4
7N
32
60
88
2K
5
7R
33
10F
11E
10E
10D
9E
61
89
1K
6
8R
34
62
90
2L
7
8P
35
63
91
3L
8
9R
36
64
92
1M
1L
9
11P
10P
10N
9P
37
65
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
38
10C
11D
9C
66
94
3N
39
67
95
3M
1N
40
68
96
10M
11N
9M
41
9D
69
97
2M
3P
42
11B
11C
9B
70
98
43
71
99
2N
9N
44
72
100
101
102
103
104
105
106
107
108
2P
11L
11M
9L
45
10B
11A
10A
9A
73
1P
46
74
3R
47
75
4R
10L
11K
10K
9J
48
76
4P
49
8B
77
5P
50
7C
78
3F
5N
51
6C
79
1G
1F
5R
9K
52
8A
80
Internal
10J
11J
11H
53
7A
81
3G
2G
1H
54
7B
82
55
6B
83
Document Number: 001-06550 Rev. *E
Page 18 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
DLL Constraints
Power Up Sequence in DDR-II+ SRAM
■ DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
DDR-II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations. During
power up, when the DOFF is tied HIGH, the DLL is locked after
2048 cycles of stable clock.
.
KC Var
■ The DLL functions at frequencies down to 120 MHz.
■ If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency causing unstable
SRAM behavior. To avoid this, provide 2048 cycles stable clock
to relock to the desired clock frequency.
Power Up Sequence
■ Apply power with DOFF tied HIGH (All other inputs can be
HIGH or LOW)
❐ Apply V before V
DD
DDQ
❐ Apply V
before V
or at the same time as V
DDQ
REF REF
■ Provide stable power and clock (K, K) for 2048 cycles to lock
the DLL.
Power Up Waveforms
Figure 3. Power Up Waveforms
K
K
Start Normal
Operation
Unstable Clock
> 2048 Stable Clock
Clock Start (Clock Starts after V /V
DD DDQ
is Stable)
V
/V
+
V
/V Stable (< 0.1V DC per 50 ns)
DD DDQ
DD DDQ
Fix HIGH (tie to V
DDQ
)
DOFF
Document Number: 001-06550 Rev. *E
Page 19 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V
Latch up Current..................................................... >200 mA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied.. –55°C to +125°C
Operating Range
Ambient
Range
V
V
DDQ
DD
Temperature (T )
Supply Voltage on V Relative to GND........–0.5V to +2.9V
A
DD
Commercial
Industrial
0°C to +70°C
1.8 ± 0.1V
1.4V to
Supply Voltage on V
Relative to GND.......–0.5V to +V
DD
DDQ
V
DD
–40°C to +85°C
DC Applied to Outputs in High-Z ........ –0.5V to V
+ 0.3V
DDQ
DC Input Voltage
.............................. –0.5V to V + 0.3V
DD
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Parameter
Description
Power Supply Voltage
IO Supply Voltage
Test Conditions
Min
1.7
1.4
Typ
Max
Unit
V
1.8
1.5
1.9
V
V
DD
V
V
V
V
V
V
V
I
V
DD
DDQ
OH
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Note 17
Note 18
V
V
/2 – 0.12
/2 – 0.12
V
V
/2 + 0.12
/2 + 0.12
V
DDQ
DDQ
DDQ
DDQ
V
OL
I
I
= –0.1 mA, Nominal Impedance
= 0.1 mA, Nominal Impedance
V
– 0.2
V
V
OH(LOW)
OL(LOW)
IH
OH
OL
DDQ
DDQ
V
0.2
V
SS
V
+ 0.1
V
+ 0.15
DDQ
V
REF
–0.15
V
– 0.1
REF
V
IL
Input Leakage Current
Output Leakage Current
Input Reference Voltage
GND ≤ V ≤ V
–2
–2
2
μA
μA
V
X
I
DDQ
I
GND ≤ V ≤ V
Output Disabled
2
OZ
I
DDQ,
V
Typical Value = 0.75V
0.68
0.75
0.95
1300
1300
1300
1300
1200
1200
1200
1200
1100
1100
1100
1100
REF
I
V
Operating Supply
V
= Max,
375MHz
333MHz
300MHz
(x8)
(x9)
mA
DD
DD
DD
I
= 0 mA,
OUT
f = f
= 1/t
MAX
CYC
(x18)
(x36)
(x8)
mA
mA
(x9)
(x18)
(x36)
(x8)
(x9)
(x18)
(x36)
Notes
15. Overshoot: V (AC) < V
16. Power up: assumes a linear ramp from 0V to V (min) within 200 ms. During this time V < V and V
+ 0.3V (pulse width less than t
/2). Undershoot: V (AC) > − 0.3V (pulse width less than t
/2).
IH
DDQ
CYC
IL
CYC
< V
.
DD
IH
DD
DDQ
DD
17. Outputs are impedance controlled. I = –(V
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
OH
DDQ
18. Outputs are impedance controlled. I = (V
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
OL
DDQ
19. V
(min) = 0.68V or 0.46V
, whichever is larger. V
(max) = 0.95V or 0.54V
, whichever is smaller.
DDQ
REF
DDQ
REF
20. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-06550 Rev. *E
Page 20 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Electrical Characteristics
[13]
Over the Operating Range
DC Electrical Characteristics
Parameter
Description
Test Conditions
Min
Typ
Max
525
525
525
525
500
500
500
500
450
450
450
450
Unit
I
Automatic Power down
Current
Max V
,
375MHz
333MHz
300MHz
(x8)
(x9)
mA
SB1
DD
Both Ports Deselected,
V
≥ V or V ≤ V
IN
IH
IN
IL
(x18)
(x36)
(x8)
f = f
= 1/t
,
MAX
CYC
Inputs Static
mA
mA
(x9)
(x18)
(x36)
(x8)
(x9)
(x18)
(x36)
AC Electrical Characteristics
Over the Operating Range
Parameter
Description
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min
+ 0.2
Typ
–
Max
Unit
V
V
V
V
+ 0.24
DDQ
IH
IL
REF
V
–0.24
–
V
– 0.2
V
REF
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Input Capacitance
Test Conditions
Max
Unit
C
T = 25°C, f = 1 MHz, V = 1.8V, V = 1.5V
DDQ
5.5
8.5
8
pF
pF
pF
IN
A
DD
C
C
Clock Input Capacitance
Output Capacitance
CLK
O
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
Θ
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
11.82
°C/W
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
2.33
JC
Document Number: 001-06550 Rev. *E
Page 21 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
VREF = 0.75V
0.75V
VREF
VREF
0.75V
R = 50Ω
OUTPUT
ALL INPUT PULSES
1.25V
Z = 50Ω
0
OUTPUT
Device
R = 50Ω
L
0.75V
Under
Device
Under
0.25V
Test
5 pF
VREF = 0.75V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250Ω
250Ω
INCLUDING
JIG AND
SCOPE
(a)
(b)
Note
21. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V
= 0.75V, RQ = 250Ω, V
= 1.5V, input pulse
DDQ
REF
levels of 0.25V to 1.25V, output loading of the specified I /I
OL OH,
Document Number: 001-06550 Rev. *E
Page 22 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Switching Characteristics
Over the Operating Range
375 MHz
333 MHz
300 MHz
Cypress Consortium
Parameter Parameter
Description
Unit
Min Max Min Max Min Max
t
t
t
t
t
V
(Typical) to the First Access
1
–
1
–
1
–
ms
POWER
CYC
KH
DD
t
t
t
t
K Clock Cycle Time
2.66 8.40 3.0 8.40 3.3 8.40 ns
KHKH
KHKL
KLKH
KHKH
Input Clock (K/K) HIGH
Input Clock (K/K) LOW
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
t
t
CYC
KL
CYC
K Clock Rise to K Clock Rise (rising edge to rising edge)
1.13
1.28
1.40
ns
KHKH
Setup Times
t
t
t
t
t
t
Address Setup to K Clock Rise
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
ns
ns
ns
SA
AVKH
IVKH
IVKH
Control Setup to K Clock Rise (LD, R/W)
Double Data Rate Control Setup to Clock (K/K) Rise
SC
0.28
0.28
0.28
SCDDR
(BWS , BWS , BWS , BWS )
0
1
2
3
t
t
D Setup to Clock (K/K) Rise
[X:0]
0.28
–
0.28
–
0.28
–
ns
SD
DVKH
Hold Times
t
t
t
t
t
t
0.4
0.4
–
–
–
0.4
0.4
–
–
–
0.4
0.4
–
–
–
ns
ns
ns
Address Hold After K Clock Rise
HA
KHAX
KHIX
KHIX
Control Hold After K Clock Rise (LD, R/W)
Double Data Rate Control Hold After Clock (K/K) Rise
HC
0.28
0.28
0.28
HCDDR
(BWS , BWS , BWS , BWS )
0
1
2
3
t
t
D Hold After Clock (K/K) Rise
[X:0]
0.28
–
0.28
–
0.28
–
ns
HD
KHDX
Output Times
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
K/K Clock Rise to Data Valid
–
–0.45
–
0.45
–
–
–0.45
–
0.45
–
–
–0.45
–
0.45 ns
ns
0.45 ns
CO
CHQV
Data Output Hold After K/K Clock Rise (Active to Active)
K/K Clock Rise to Echo Clock Valid
Echo Clock Hold After K/K Clock Rise
Echo Clock High to Data Valid
–
DOH
CHQX
0.45
–
0.45
–
CCQO
CQOH
CQD
CHCQV
CHCQX
CQHQV
CQHQX
CQHCQL
CQHCQH
–0.45
–
–0.45
–
–0.45
–
–
0.2
–
ns
ns
ns
ns
ns
0.2
–
0.2
–
Echo Clock High to Data Invalid
–0.2
0.88
0.88
–0.2
1.03
1.03
–0.2
1.15
1.15
CQDOH
CQH
Output Clock (CQ/CQ) HIGH
–
–
–
CQ Clock Rise to CQ Clock Rise
–
–
–
CQHCQH
(rising edge to rising edge)
t
t
t
t
t
t
Clock (K/K) Rise to High Z (Active to High Z)
–
0.45
–
–
0.45
–
–
0.45 ns
ns
CHZ
CLZ
CHQZ
CHQX1
QVLD
Clock (K/K) Rise to Low Z
–0.45
–0.45
–0.45
–
Echo Clock High to QVLD Valid
–0.20 0.20 –0.20 0.20 –0.20 0.20 ns
QVLD
DLL Timing
t
t
t
t
t
t
Clock Phase Jitter
DLL Lock Time (K)
–
0.20
–
–
0.20
–
–
0.20 ns
KC Var
KC Var
2048
30
2048
30
2048
30
–
–
Cycles
ns
KC lock
KC Reset
KC lock
KC Reset
K Static to DLL Reset
–
–
Notes
22. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated
and outputs data with the output timings of that frequency range.
23. This part has a voltage regulator internally; t
is the time that the power is supplied above V minimum initially before a read or write operation is initiated.
DD
POWER
24. These parameters are extrapolated from the input timing parameters (t
- 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t
) is already
KHKH
KC Var
included in the t
). These parameters are only guaranteed by design and are not tested in production
KHKH
25. t
, t
, are specified with a load capacitance of 5 pF as in (b) of “AC Test Loads and Waveforms” on page 22. Transition is measured ±100 mV from steady-state
CHZ CLZ
voltage.
26. At any given voltage and temperature, t
is less than t
and t
less than t
.
CO
CHZ
CLZ
CHZ
27. t
specification is applicable for both rising and falling edges of QVLD signal.
QVLD
28. Hold to >V or <V .
IH
IL
Document Number: 001-06550 Rev. *E
Page 23 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Switching Waveforms
Figure 5. Waveform for 2.0 Cycle Read Latency
WRITE
7
READ
9
NOP
11
NOP
1
READ
2
READ
3
NOP
4
NOP
5
NOP
6
WRITE
8
NOP
10
12
K
t
t
t
t
KH
KL
CYC
KHKH
K
LD
t
t
HC
SC
R/W
A
A1
A2
A3
A4
A0
t
QVLD
t
t
t
SA HA
QVLD
t
QVLD
QVLD
t
t
HD
HD
SD
t
SD
D21 D30 D31
t
Q00 Q01 Q10 Q11
D20
Q40 Q41
DQ
t
t
t
CHZ
CLZ
DOH
t
t
CO
CQD
(Read Latency = 2.0 Cycles)
t
t
CQDOH
t
CCQO
t
CQOH
CQ
CQ
t
t
CQH
CQHCQH
CCQO
t
CQOH
DON’T CARE
UNDEFINED
Notes
29. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
30. Outputs are disabled (High-Z) one clock cycle after a NOP.
31. The third NOP cycle between read to write transition is not necessary for correct device operation when Read Latency = 2.0 cycles; however at high frequency operation,
it is required to avoid bus contention.
32. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 001-06550 Rev. *E
Page 24 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Ordering Information
Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
375 CY7C1546V18-375BZC
CY7C1557V18-375BZC
CY7C1548V18-375BZC
CY7C1550V18-375BZC
CY7C1546V18-375BZXC
CY7C1557V18-375BZXC
CY7C1548V18-375BZXC
CY7C1550V18-375BZXC
CY7C1546V18-375BZI
CY7C1557V18-375BZI
CY7C1548V18-375BZI
CY7C1550V18-375BZI
CY7C1546V18-375BZXI
CY7C1557V18-375BZXI
CY7C1548V18-375BZXI
CY7C1550V18-375BZXI
333 CY7C1546V18-333BZC
CY7C1557V18-333BZC
CY7C1548V18-333BZC
CY7C1550V18-333BZC
CY7C1546V18-333BZXC
CY7C1557V18-333BZXC
CY7C1548V18-333BZXC
CY7C1550V18-333BZXC
CY7C1546V18-333BZI
CY7C1557V18-333BZI
CY7C1548V18-333BZI
CY7C1550V18-333BZI
CY7C1546V18-333BZXI
CY7C1557V18-333BZXI
CY7C1548V18-333BZXI
CY7C1550V18-333BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
Commercial
Industrial
Commercial
Industrial
Document Number: 001-06550 Rev. *E
Page 25 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Ordering Information (continued)
Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
300 CY7C1546V18-300BZC
CY7C1557V18-300BZC
CY7C1548V18-300BZC
CY7C1550V18-300BZC
CY7C1546V18-300BZXC
CY7C1557V18-300BZXC
CY7C1548V18-300BZXC
CY7C1550V18-300BZXC
CY7C1546V18-300BZI
CY7C1557V18-300BZI
CY7C1548V18-300BZI
CY7C1550V18-300BZI
CY7C1546V18-300BZXI
CY7C1557V18-300BZXI
CY7C1548V18-300BZXI
CY7C1550V18-300BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
Commercial
Industrial
Document Number: 001-06550 Rev. *E
Page 26 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Package Diagram
Figure 6. 165-Ball FBGA (15 x 17 x 1.4 mm)
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Document Number: 001-06550 Rev. *E
Page 27 of 28
CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Document History Page
Document Title: CY7C1546V18/CY7C1557V18/CY7C1548V18/CY7C1550V18, 72-Mbit DDR-II+ SRAM 2-Word Burst Architec-
ture (2.0 Cycle Read Latency)
Document Number: 001-06550
Issue
Date
Orig. of
Change
REV. ECN No.
Description of Change
**
432718 See ECN
437000 See ECN
461934 See ECN
NXR
IGS
New datasheet
*A
*B
ECN for show on web
NXR
Changed t and t from 40 ns to 20 ns, changed t
, t
, t , t
, t
, t
TH
TL
TMSS TDIS CS TMSH TDIH CH
from 10 ns to 5 ns and changed t
from 20 ns to 10 ns in TAP AC Switching
TDOV
Characteristics table
Modified Power up waveform
*C
497567 See ECN
NXR
Changed the V
Range table, and the DC Electrical Characteristics table
Added foot note in page 1
operating voltage to 1.4V to V in the Features section, Operating
DDQ DD
Changed the Maximum rating of ambient temperature with power applied from –10°C
to +85°C to –55°C to +125°C
Changed V
(Max) specification from 0.85V to 0.95V in the DC Electrical Character-
REF
istics table and in the note below the table
Updated footnote 18 to specify overshoot and undershoot specifications
Updated I and I values
DD
SB
Updated Θ and Θ values
JA
JC
Removed x9 part and its related information
Updated footnote 25
*D
*E
1351504 See ECN VKN/AESA Converted from preliminary to final
Added x8 and x9 parts
Updated logic block diagram for x18 and x36 parts
Changed t max spec to 8.4 ns for all speed bins
CYC
Updated footnote# 21
Updated Ordering Information table
2193266 See ECN VKN/AESA Added footnote# 20 related to I
DD
© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
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Document Number: 001-06550 Rev. *E
Revised March 11, 2008
Page 28 of 28
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
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