Cypress CY7C1364C User Manual

CY7C1364C

9-Mbit (256K x 32) Pipelined Sync SRAM

Features

Functional Description^[1]

• Registered inputs and outputs for pipelined operation

• 256K × 32 common I/O architecture

The CY7C1364C SRAM integrates 256K x 32 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

• 3.3V core power supply (V

)

• 2.5V/3.3V I/O power supply (V

• Fast clock-to-output times

)

DDQ

addresses, all data inputs, address-pipelining Chip Enable

[2]

(CE ), depth-expansion Chip Enables (CE and CE ), Burst

— 2.8 ns (for 250-MHz device)

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW , and BWE), and Global Write (GW). Asynchronous

[A:D]

• Provide high-performance 3-1-1-1 access rate

inputs include the Output Enable (OE) and the ZZ pin.

• User-selectable burst counter supporting Intel

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

controlled by the Byte Write control inputs. GW when active

• Available in JEDEC-standard lead-free 100-Pin TQFP

package

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• “ZZ” Sleep Mode Option

causes all bytes to be written.

LOW

The CY7C1364C operates from a +3.3V core power supply

while all outputs may operate with either a +2.5 or +3.3V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Logic Block Diagram-CY7C1364C (256K x 32)

A0, A1, A

ADDRESS

A[1:0]

MODE

ADV

CLK

BURST

COUNTER

AND

LOGIC

CLR

ADSC

ADSP

DQ^D

BYTE

WRITE REGISTER

DQ^D

BYTE

WRITE DRIVER

BWD

BWC

DQ^C

BYTE

WRITE DRIVER

DQ^C

BYTE

WRITE REGISTER

OUTPUT

BUFFERS

OUTPUT

REGISTERS

MEMORY

ARRAY

SENSE

AMPS

DQ s

DQ^B

BYTE

WRITE DRIVER

DQ^B

BYTE

WRITE REGISTER

BWB

DQ^A

BYTE

WRITE DRIVER

DQA

BYTE

WRITE REGISTER

BWA

BWE

INPUT

REGISTERS

CE1

CE2

CE3

ENABLE

PIPELINED

ENABLE

SLEEP

CONTROL

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2. CE is not available on 2 Chip Enable TQFP package.

Cypress Semiconductor Corporation

Document #: 38-05689 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 14, 2006

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CY7C1364C

Pin Configuration (continued)

100-Pin TQFP Pinout (3 Chip Enables) (A version)

DQ_C

V_DDQ

V_SSQ

DQ_C

V_SSQ

V_DDQ

DQ_C

DQ_B

V_DDQ

V_SSQ

DQ_B

V_SSQ

V_DDQ

DQ_B

V_SS

BYTE C

BYTE B

V_DD

V_SS

CY7C1364C

V_DD

DQ_D

V_DDQ

V_SSQ

DQ_D

V_SSQ

V_DDQ

DQ_D

DQ_A

V_DDQ

V_SSQ

DQ_A

V_SSQ

V_DDQ

DQ_A

BYTE D

BYTE A

Document #: 38-05689 Rev. *E

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CY7C1364C

Pin Definitions

Name

TQFP

I/O

Description

Address Inputs used to select one of the 256K address locations.

A , A , A

37, 36, 32, 33, 34, 35, 43,

Input-

44, 45, 46, 47, 48, 49, 50, Synchronous Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW,

81, 82, 99, 100

and CE , CE , and CE are sampled active. A

feed the 2-bit counter.

[1:0]

BW , BW

93, 94, 95, 96

Input-

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct

BW , BW

Synchronous byte writes to the SRAM. Sampled on the rising edge of CLK.

Input- Global Write Enable Input, active LOW. When asserted LOW on the

Synchronous rising edge of CLK, a global Write is conducted (ALL bytes are written,

regardless of the values on BW and BWE).

[A:D]

BWE

CLK

Input-

Byte Write Enable Input, active LOW. Sampled on the rising edge of

Synchronous CLK. This signal must be asserted LOW to conduct a Byte Write.

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. Also

used to increment the burst counter when ADV is asserted LOW, during

a burst operation.

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK.

Synchronous Used in conjunction with CE and CE to select/deselect the device.

ADSP is ignored if CE is HIGH. CE is sampled only when a new

external address is loaded.

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK.

and to select/deselect the device.

Synchronous Used in conjunction with

CE is sampled only when a new external address is loaded.

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK.

(for 3 Chip Enable Version) Synchronous Used in conjunction with CE and CE to select/deselect the

device.CE is assumed active throughout this document for BGA. CE

is sampled only when a new external address is loaded.

Input-

Output Enable, asynchronous input, active LOW. Controls the

Asynchronous direction of the I/O pins. When LOW, the I/O pins behave as outputs.

When deasserted HIGH, I/O pins are tri-stated, and act as input data

pins. OEis masked during the first clock of a Read cycle when emerging

from a deselected state.

ADV

Input-

Advance Input signal, sampled on the rising edge of CLK, active

Synchronous LOW. Whenasserted, itautomatically increments the address in a burst

cycle.

ADSP

Input-

Synchronous CLK, active LOW. When asserted LOW, A is captured in the address

registers. A are also loaded into the burst counter. When and

Address Strobe from Processor, sampled on the rising edge of

ADSP

ADSC are both asserted, only ADSP is recognized. ASDP is ignored

[1:0]

when CE is deasserted HIGH.

ADSC

Input-

Address Strobe from Controller, sampled on the rising edge of

Synchronous CLK, active LOW. When asserted LOW, A is captured in the address

registers. A are also loaded into the burst counter. When ADSP and

[1:0]

ADSC are both asserted, only ADSP is recognized.

Input-

ZZ “sleep” Input, active HIGH. This input, when High places the

Asynchronous device in a non-time-critical “sleep” condition with data integrity

preserved. For normal operation, this pin has to be LOW or left floating.

ZZ pin has an internal pull-down.

DQs

52, 53, 56, 57, 58, 59, 62,

I/O-

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data

63, 68, 69, 72, 73, 74, 75, Synchronous register that is triggered by the rising edge of CLK. As outputs, they

78, 79, 2, 3, 6, 7, 8, 9, 12,

13, 18, 19, 22, 23, 24, 25,

28, 29

deliver the data contained in the memory location specified by “A”

during the previous clock rise of the Read cycle. The direction of the

pins is controlled by OE. When OE is asserted LOW, the pins behave

as outputs. When HIGH, DQ are placed in a tri-state condition.

15, 41, 65, 91

17, 40, 67, 90

Power Supply Power supply inputs to the core of the device.

Ground

Ground for the core of the device.

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CY7C1364C

Pin Definitions (continued)

Name

TQFP

I/O

Description

4, 11, 20, 27, 54, 61, 70, 77 I/O Power Power supply for the I/O circuitry.

DDQ

Supply

5, 10, 21, 26, 55, 60, 71, 76 I/O Ground Ground for the I/O circuitry.

SSQ

MODE

Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence.

When tied to V or left floating selects interleaved burst sequence.

This is a strap pin and should remain static during device operation.

Mode pin has an internal pull-up.

1, 14, 16, 30, 38, 39, 42,

51, 66, 80

No Connects. Not internally connected to the die

Single Write Accesses Initiated by ADSP

Functional Overview

This access is initiated when both of the following conditions

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) CE , CE , CE are all asserted active. The address

presented to A is loaded into the address register and the

The CY7C1364C supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium and i486™

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is user

selectable, and is determined by sampling the MODE input.

Accesses can be initiated with either the Processor Address

Strobe (ADSP) or the Controller Address Strobe (ADSC).

Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

address advancement logic while being delivered to the RAM

array. The Write signals (GW, BWE, and BW

inputs are ignored during this first cycle.

) and ADV

[A:D]

ADSP-triggered Write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQ inputs is written into the corre-

sponding address location in the memory array. If GW is HIGH,

then the Write operation is controlled by BWE and BW

[A:D]

signals. The CY7C1364C provides Byte Write capability that

is described in the Write Cycle Descriptions table. Asserting

the Byte Write Enable input (BWE) with the selected Byte

Write (BW

) input, will selectively write to only the desired

[A:D]

bytes. Bytes not selected during a Byte Write operation will

remain unaltered. A synchronous self-timed Write mechanism

has been provided to simplify the Write operations.

Byte Write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW

) inputs. A Global Write

[A:D]

Enable (GW) overrides all Byte Write inputs and writes data to

all four bytes. All writes are simplified with on-chip

synchronous self-timed Write circuitry.

Because the CY7C1364C is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQ inputs. Doing so will tri-state the output drivers. As

a safety precaution, DQ are automatically tri-stated whenever

a Write cycle is detected, regardless of the state of OE.

Three synchronous Chip Selects (CE , CE , CE ) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. ADSP is ignored if CE

is HIGH.

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,

deasserted HIGH, (3) CE , CE , CE are all asserted active,

and (4) the appropriate combination of the Write inputs (GW,

(2) CE , CE , CE are all asserted active, and (3) the Write

signals (GW, BWE) are all deasserted HIGH. ADSP is ignored

BWE, and BW ) are asserted active to conduct a Write to

[A:D]

the desired byte(s). ADSC-triggered Write accesses require a

single clock cycle to complete. The address presented to A is

loaded into the address register and the address

advancement logic while being delivered to the memory array.

The ADV input is ignored during this cycle. If a global Write is

conducted, the data presented to the DQ is written into the

corresponding address location in the memory core. If a Byte

Write is conducted, only the selected bytes are written. Bytes

not selected during a Byte Write operation will remain

unaltered. A synchronous self-timed Write mechanism has

been provided to simplify the Write operations.

if CE is HIGH. The address presented to the address inputs

(A) is stored into the address advancement logic and the

address register while being presented to the memory array.

The corresponding data is allowed to propagate to the input of

the output registers. At the rising edge of the next clock the

data is allowed to propagate through the output register and

onto the data bus within t

if OE is active LOW. The only

exception occurs when the SRAM is emerging from a

deselected state to a selected state, its outputs are always

tri-stated during the first cycle of the access. After the first cycle

of the access, the outputs are controlled by the OE signal.

Consecutive single Read cycles are supported. Once the

SRAM is deselected at clock rise by the chip select and either

ADSP or ADSC signals, its output will tri-state immediately.

Because the CY7C1364C is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQ inputs. Doing so will tri-state the output drivers. As

a safety precaution, DQs are automatically tri-stated whenever

a Write cycle is detected, regardless of the state of OE.

Document #: 38-05689 Rev. *E

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CY7C1364C

Burst Sequences

Interleaved Burst Address Table

(MODE = Floating or V_DD

)

The CY7C1364C provides a two-bit wraparound counter, fed

by A

, that implements either an interleaved or linear burst

[1:0]

First

Second

Third

Address

Fourth

sequence. The interleaved burst sequence is designed specif-

ically to support Intel Pentium applications. The linear burst

sequence is designed to support processors that follow a

linear burst sequence. The burst sequence is user selectable

through the MODE input.

Address

[1:0]

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both Read and Write burst operations are supported.

Linear Burst Address Table (MODE = GND)

Sleep Mode

First

Second

Third

Fourth

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CE , CE , CE , ADSP, and ADSC must

Address

[1:0]

remain inactive for the duration of t

after the ZZ input

ZZREC

returns LOW

ZZ Mode Electrical Characteristics

Parameter

Description

Sleep mode standby current

Device operation to ZZ

Test Conditions

Min.

Max.

Unit

ZZ > V – 0.2V

DDZZ

ZZ > V – 0.2V

ZZS

CYC

ZZ recovery time

ZZ < 0.2V

CYC

ZZREC

ZZI

ZZ Active to Sleep current

ZZ Inactive to exit Sleep current

This parameter is sampled

RZZI

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CY7C1364C

Truth Table^{[3, 4, 5, 6, 7, 8]}

Address

Next Cycle

Unselected

Used

ADSP

ADSC

ADV

Write

None

Tri-State

Unselected

None

Unselected

None

Unselected

None

Unselected

None

Begin Read

External

Begin Read

Read

Write

Continue Read

Suspend Read

Begin Write

Tri-State

Current

External

Tri-State

Begin Write

Continue Write

Suspend Write

ZZ “Sleep”

Current

None

Notes:

3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

4. WRITE = L when any one or more Byte Write Enable signals (BW ,BW ,BW ,BW and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals

)

(BW ,BW ,BW ,BW

5. The DQ pins are controlled by the current cycle and the

BWE

signal.

is asynchronous and is not sampled with the clock.

6. CE , CE , and CE are available only in the TQFP package.

7. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW

. Writes may occur only on subsequent clocks

[A:D]

after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a

don't care for the remainder of the Write cycle.

8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are tri-state when OE is

inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

Document #: 38-05689 Rev. *E

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CY7C1364C

Truth Table for Read/Write^{[3, 4]}

Function

BWE

Read

Write Byte A – DQ

Write Byte B – DQ

Write Bytes B, A

Write Byte C – DQ

Write Bytes C, A

Write Bytes C, B

Write Bytes C, B, A

Write Byte D – DQ

Write Bytes D, A

Write Bytes D, B

Write Bytes D, B, A

Write Bytes D, C

Write Bytes D, C, A

Write Bytes D, C, B

Write All Bytes

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CY7C1364C

DC Input Voltage................................... –0.5V to V + 0.5V

Maximum Ratings

Current into Outputs (LOW) .........................................20 mA

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Static Discharge Voltage .......................................... >2001V

(per MIL-STD-883, Method 3015)

Storage Temperature ................................. –65°C to +150°C

Latch-up Current ..................................................... >200 mA

Ambient Temperature with

Power Applied ............................................ –55°C to +125°C

Operating Range

Supply Voltage on V Relative to GND........–0.5V to +4.6V

Ambient

Range

Commercial

Industrial

Temperature

0°C to +70°C

–40°C to +85°C

DDQ

Supply Voltage on V

Relative to GND...... –0.5V to +V

DDQ

3.3V –

5%/+10%

2.5V – 5% to

DC Voltage Applied to Outputs

in tri-state.............................................–0.5V to V

+ 0.5V

DDQ

[9, 10]

Electrical Characteristics Over the Operating Range

Parameter

Description

Power Supply Voltage

I/O Supply Voltage

Test Conditions

Min.

Max.

3.6

Unit

3.135

2.375

2.4

for 3.3 V I/O

for 2.5V I/O

DDQ

2.625

Output HIGH Voltage

Output LOW Voltage

for 3.3 V I/O, I = –4.0 mA

for 2.5V I/O, I = –1.0 mA

2.0

for 3.3 V I/O, I = 8.0 mA

0.4

for 2.5V I/O, I = 1.0 mA

[9]

Input HIGH Voltage

for 3.3 V I/O

for 2.5V I/O

for 3.3 V I/O

for 2.5V I/O

2.0

1.7

+ 0.3V

[9]

Input LOW Voltage

–0.3

–5

0.8

0.7

Input Leakage Current GND ≤ V ≤ V

except ZZ and MODE

µA

DDQ

Input Current of MODE Input = V

–30

–5

µA

Input = V

Input Current of ZZ

Input = V

µA

Output Leakage Current GND ≤ V ≤ V

Output Disabled

–5

µA

DDQ,

Operating Supply

f = f

= Max., I

= 0 mA,

4-ns cycle, 250 MHz

5-ns cycle, 200 MHz

6-ns cycle, 166 MHz

250

220

180

130

120

110

OUT

= 1/t

MAX CYC

Current

Automatic CE

Power-down

Current—TTL Inputs

= Max., Device Deselected, 4-ns cycle, 250 MHz

SB1

≥ V or V ≤ V ,

5-ns cycle, 200 MHz

6-ns cycle, 166 MHz

f = f

= 1/t

MAX CYC

Automatic CE

Power-down

Current—CMOS Inputs f = 0

V = Max., Device Deselected, All speeds

SB2

≤ 0.3V or V > V – 0.3V,

DDQ

Automatic CE

Power-down

Current—CMOS Inputs f = f

= Max., Device Deselected, 4-ns cycle, 250 MHz

120

110

100

SB3

or V ≤ 0.3V or V > V

– 0.3V,

DDQ

5-ns cycle, 200 MHz

6-ns cycle, 166 MHz

= 1/t

MAX

CYC

Automatic CE

V = Max., Device Deselected, All speeds

SB4

Power-down

Current—TTL Inputs

f = 0

≥ V or V ≤ V ,

IH IN IL

Notes:

9. Overshoot: V (AC) < V +1.5V (Pulse width less than t

/2), undershoot: V (AC) > –2V (Pulse width less than t /2).

CYC

10. T

: Assumes a linear ramp from 0Vv to V (min.) within 200 ms. During this time V < V and V

< V

Power-up

DDQ

Document #: 38-05689 Rev. *E

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CY7C1364C

Capacitance^[11]

100 TQFP

Parameter

Description

Input Capacitance

Test Conditions

T = 25°C, f = 1 MHz,

Max.

Unit

= 3.3V

= 2.5V

Clock Input Capacitance

Input/Output Capacitance

CLK

I/O

DDQ

Thermal Resistance^[11]

Parameter

Description

Test Conditions

Test conditions follow standard test

methods and procedures for measuring

100 TQFP Package

Unit

Thermal Resistance

(Junction to Ambient)

29.41

°C/W

thermal impedance, per EIA/JESD51

Thermal Resistance

(Junction to Case)

6.13

°C/W

AC Test Loads and Waveforms

3.3V I/O Test Load

OUTPUT

R = 317Ω

3.3V

OUTPUT

ALL INPUT PULSES

90%

V_DDQ

90%

10%

Z = 50Ω

R = 50Ω

10%

GND

5 pF

INCLUDING

R = 351Ω

≤ 1 ns

V = 1.5V

(a)

JIG AND

SCOPE

(b)

(c)

2.5V I/O Test Load

R = 1667Ω

2.5V

OUTPUT

R = 50Ω

OUTPUT

ALL INPUT PULSES

90%

V_DDQ

GND

90%

10%

Z = 50Ω

10%

5 pF

R =1538Ω

≤ 1 ns

INCLUDING

V = 1.25V

JIG AND

SCOPE

(a)

(b)

(c)

Note:

11. Tested initially and after any design or process change that may affect these parameters

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CY7C1364C

[12,13]

Switching Characteristics Over the Operating Range

–250

Min.

–200

Min.

–166

Parameter

Description

Max.

Min.

Max.

Unit

[14]

(Typical) to the First Access

POWER

Clock

Clock Cycle Time

Clock HIGH

4.0

1.8

5.0

2.0

6.0

2.4

CYC

Clock LOW

Output Times

Data Output Valid after CLK Rise

Data Output Hold after CLK Rise

2.8

3.0

3.5

1.25

DOH

CLZ

[15, 16, 17]

Clock to Low-Z

[15, 16, 17]

Clock to High-Z

2.8

3.0

3.5

CHZ

OEV

OELZ

OEHZ

OE LOW to Output Valid

[15, 16, 17]

OE LOW to Output Low-Z

[15, 16, 17]

OE HIGH to Output High-Z

2.8

3.0

3.5

Set-up Times

Address Set-up before CLK Rise

ADSC, ADSP Set-up before CLK Rise

ADV Set-up before CLK Rise

1.25

1.5

ADS

ADVS

WES

GW, BWE, BW

Set-up before CLK Rise

[A:D]

Data Input Set-up before CLK Rise

Chip Enable Set-up before CLK Rise

CES

Hold Times

Address Hold after CLK Rise

ADSP, ADSC Hold after CLK Rise

ADV Hold after CLK Rise

0.4

0.5

ADH

ADVH

WEH

GW, BWE, BW

Hold after CLK Rise

[A:D]

Data Input Hold after CLK Rise

Chip Enable Hold after CLK Rise

CEH

Notes:

12. Timing reference level is 1.5V when V

= 3.3V and is 1.25V when V

= 2.5V.

DDQ

13. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

14. This part has a voltage regulator internally; t

is the time that the power needs to be supplied above V minimum initially before a Read or Write operation

POWER

can be initiated.

15. t

, t

, and t

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

CHZ CLZ OELZ

OEHZ

16. At any given voltage and temperature, t

is less than t

and t

is less than t

to eliminate bus contention between SRAMs when sharing the same

CLZ

OEHZ

OELZ

CHZ

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

17. This parameter is sampled and not 100% tested.

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CY7C1364C

Switching Waveforms

[18]

Read Cycle Timing

CYC

CLK

ADH

ADS

ADSP

ADSC

ADH

ADS

ADDRESS

Burst continued with

new base address

WEH

WES

GW, BWE,

BW[A:D]

Deselect

cycle

CEH

CES

ADVH

ADVS

ADV

suspends

burst.

OEV

OEHZ

CHZ

OELZ

DOH

CLZ

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

Q(A2)

Q(A2 + 1)

Q(A1)

Data Out (Q)

High-Z

Burst wraps around

Note:

18. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.

Document #: 38-05689 Rev. *E

Page 12 of 18

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CY7C1364C

Switching Waveforms (continued)

[18,19]

Write Cycle Timing

CYC

CLK

ADH

ADS

ADSP

ADSC extends burst

ADH

ADS

ADH

ADS

ADSC

ADDRESS

Byte write signals are

ignored for first cycle when

ADSP initiates burst

WEH

WES

BWE,

BW[A :D]

WEH

WES

CEH

CES

ADVH

ADVS

ADV

ADV suspends burst

Data In (D)

D(A2)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A1)

High-Z

OEHZ

Data Out (Q)

BURST READ

Single WRITE

BURST WRITE

Extended BURST WRITE

DON’T CARE

UNDEFINED

Note:

19.

Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW

LOW.

[A:D]

Document #: 38-05689 Rev. *E

Page 13 of 18

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CY7C1364C

Switching Waveforms (continued)

[18,20, 21]

Read/Write Cycle Timing

CYC

CLK

ADH

ADS

ADSP

ADSC

ADDRESS

WEH

WES

BWE,

BW[A:D]

CEH

CES

ADV

OELZ

Data In (D)

High-Z

D(A3)

D(A5)

D(A6)

OEHZ

CLZ

Data Out (Q)

Q(A1)

Q(A2)

Q(A4)

Q(A4+1)

Q(A4+2)

Q(A4+3)

Back-to-Back READs

Single WRITE

BURST READ

Back-to-Back

WRITEs

DON’T CARE

UNDEFINED

Notes:

20. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.

21. GW is HIGH.

Document #: 38-05689 Rev. *E

Page 14 of 18

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CY7C1364C

Switching Waveforms (continued)

[22, 23]

ZZ Mode Timing

CLK

ZZREC

ZZI

SUPPLY

DDZZ

RZZI

ALL INPUTS

(except ZZ)

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

Notes:

22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

23. DQs are in High-Z when exiting ZZ sleep mode.

Document #: 38-05689 Rev. *E

Page 15 of 18

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CY7C1364C

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz)

Package

Diagram

Operating

Range

Ordering Code

Part and Package Type

166

200

250

CY7C1364C-166AXC

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

(3 Chip Enable)

Commercial

CY7C1364C-166AJXC

CY7C1364C-166AXI

CY7C1364C-166AJXI

CY7C1364C-200AXC

CY7C1364C-200AJXC

CY7C1364C-200AXI

CY7C1364C-200AJXI

CY7C1364C-250AXC

CY7C1364C-250AJXC

CY7C1364C-250AXI

CY7C1364C-250AJXI