Cypress CY7C1360C User Manual

CY7C1360C  
CY7C1362C  
9-Mbit (256K x 36/512K x 18) Pipelined SRAM  
Features  
Functional Description[1]  
• Supports bus operation up to 250 MHz  
The CY7C1360C/CY7C1362C SRAM integrates 256K x 36  
and 512K x 18 SRAM cells with advanced synchronous  
peripheral circuitry and a two-bit counter for internal burst  
operation. All synchronous inputs are gated by registers  
controlled by a positive-edge-triggered Clock Input (CLK). The  
synchronous inputs include all addresses, all data inputs,  
• Available speed grades are 250, 200, and 166 MHz  
• Registered inputs and outputs for pipelined operation  
• 3.3V core power supply (V  
)
DD  
• 2.5V/3.3V I/O operation (V  
)
DDQ  
address-pipelining Chip Enable (CE ), depth-expansion Chip  
1
• Fast clock-to-output times  
[2]  
Enables (CE and CE ), Burst Control inputs (ADSC, ADSP,  
2
3
ADV), Write Enables (BW , and BWE), and Global Write  
(GW). Asynchronous inputs include the Output Enable (OE)  
and the ZZ pin.  
and  
— 2.8 ns (for 250-MHz device)  
X
• Provide high-performance 3-1-1-1 access rate  
®
User-selectable burst counter supporting Intel  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
®
Pentium interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous output enable  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to two or four bytes wide as  
controlled by the Byte Write control inputs. GW when active  
• Single Cycle Chip Deselect  
• Available in lead-free 100-Pin TQFP package, lead-free  
and non lead-free 119-Ball BGA package and 165-Ball  
FBGA package  
LOW cause  
s all bytes to be written.  
• TQFP Available with 3-Chip Enable and 2-Chip Enable  
• IEEE 1149.1 JTAG-Compatible Boundary Scan  
The CY7C1360C/CY7C1362C operates from a +3.3V core  
power supply while all outputs may operate with either a +2.5  
or +3.3V supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Logic Block Diagram – CY7C1362C (512K x 18)  
ADDRESS  
A0, A1, A  
REGISTER  
A[1:0]  
2
MODE  
Q1  
ADV  
CLK  
BURST  
COUNTER AND  
LOGIC  
CLR  
Q0  
ADSC  
ADSP  
DQB,DQPB  
DQB,DQPB  
WRITE REGISTER  
WRITE DRIVER  
OUTPUT  
BUFFERS  
BWB  
DQs  
DQPA  
DQPB  
OUTPUT  
REGISTERS  
SENSE  
AMPS  
MEMORY  
ARRAY  
DQA,DQPA  
E
DQA,DQPA  
WRITE REGISTER  
WRITE DRIVER  
BWA  
BWE  
INPUT  
REGISTERS  
GW  
ENABLE  
REGISTER  
CE1  
CE2  
PIPELINED  
ENABLE  
CE3  
OE  
SLEEP  
CONTROL  
ZZ  
Notes:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
2. CE is for A version of TQFP (3 Chip Enable option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.  
3
Cypress Semiconductor Corporation  
Document #: 38-05540 Rev. *H  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised September 14, 2006  
CY7C1360C  
CY7C1362C  
Pin Configurations  
100-Pin TQFP Pinout (3 Chip Enables) (A Version)  
DQPC  
1
DQPB  
DQB  
DQB  
VDDQ  
VSSQ  
DQB  
DQB  
DQB  
DQB  
VSSQ  
VDDQ  
DQB  
DQB  
VSS  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
NC  
NC  
NC  
VDDQ  
VSSQ  
NC  
A
NC  
NC  
VDDQ  
VSSQ  
NC  
DQPA  
DQA  
DQA  
VSSQ  
VDDQ  
DQA  
DQA  
VSS  
NC  
1
2
3
4
5
6
7
8
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
DQC  
2
DQc  
VDDQ  
VSSQ  
DQC  
3
4
5
6
DQC  
7
NC  
DQC  
8
DQB  
DQB  
VSSQ  
VDDQ  
DQB  
DQB  
NC  
VDD  
NC  
VSS  
DQB  
DQB  
VDDQ  
VSSQ  
DQB  
DQB  
DQPB  
NC  
DQC  
9
10  
11  
9
VSSQ  
VDDQ  
DQC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
12  
DQC  
13  
NC  
14  
VDD  
15  
NC  
VDD  
ZZ  
CY7C1362C  
(512K x 18)  
CY7C1360C  
(256K X 36)  
NC  
16  
VDD  
ZZ  
VSS  
17  
DQD  
18  
DQA  
DQA  
VDDQ  
VSSQ  
DQA  
DQA  
DQA  
DQA  
VSSQ  
VDDQ  
DQA  
DQA  
DQPA  
DQA  
DQA  
VDDQ  
VSSQ  
DQA  
DQA  
NC  
DQD  
19  
20  
21  
VDDQ  
VSSQ  
DQD  
22  
DQD  
23  
DQD  
24  
DQD  
25  
26  
27  
NC  
VSSQ  
VDDQ  
DQD  
DQD  
29  
VSSQ  
VDDQ  
NC  
NC  
NC  
VSSQ  
VDDQ  
NC  
NC  
NC  
28  
DQPD  
30  
Document #: 38-05540 Rev. *H  
Page 3 of 31  
CY7C1360C  
CY7C1362C  
Pin Configurations (continued)  
100-Pin TQFP Pinout (2 Chip Enables) (AJ Version)  
DQPC  
DQC  
DQC  
VDDQ  
VSSQ  
DQC  
DQC  
DQC  
DQC  
VSSQ  
VDDQ  
DQC  
DQC  
NC  
DQPB  
DQB  
DQB  
VDDQ  
VSSQ  
DQB  
DQB  
DQB  
DQB  
VSSQ  
VDDQ  
DQB  
DQB  
VSS  
1
2
3
4
5
6
7
8
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
NC  
NC  
NC  
VDDQ  
VSSQ  
NC  
A
NC  
NC  
VDDQ  
VSSQ  
NC  
DQPA  
DQA  
DQA  
VSSQ  
VDDQ  
DQA  
DQA  
VSS  
NC  
1
2
3
4
5
6
7
8
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
NC  
DQB  
DQB  
VSSQ  
VDDQ  
DQB  
DQB  
NC  
VDD  
NC  
VSS  
DQB  
DQB  
VDDQ  
VSSQ  
DQB  
DQB  
DQPB  
NC  
9
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
VDD  
NC  
VSS  
NC  
VDD  
ZZ  
CY7C1362C  
(512K x 18)  
CY7C1360C  
(256K X 36)  
VDD  
ZZ  
DQD  
DQD  
VDDQ  
VSSQ  
DQD  
DQD  
DQD  
DQD  
VSSQ  
VDDQ  
DQD  
DQD  
DQPD  
DQA  
DQA  
VDDQ  
VSSQ  
DQA  
DQA  
DQA  
DQA  
VSSQ  
VDDQ  
DQA  
DQA  
DQPA  
DQA  
DQA  
VDDQ  
VSSQ  
DQA  
DQA  
NC  
NC  
VSSQ  
VDDQ  
NC  
NC  
NC  
VSSQ  
VDDQ  
NC  
NC  
NC  
Document #: 38-05540 Rev. *H  
Page 4 of 31  
CY7C1360C  
CY7C1362C  
Pin Configurations (continued)  
119-Ball BGA Pinout (2 Chip Enables with JTAG)  
CY7C1360C (256K x 36)  
1
2
3
4
5
6
7
A
V
A
A
A
A
V
DDQ  
ADSP  
ADSC  
DDQ  
B
C
NC/288M  
NC/144M  
CE  
A
A
A
A
A
A
A
NC/576M  
NC/1G  
2
V
DD  
D
E
F
DQ  
DQ  
DQP  
DQ  
V
NC  
CE  
V
DQP  
DQ  
DQ  
DQ  
C
C
SS  
SS  
SS  
SS  
SS  
SS  
B
B
V
V
V
V
C
C
1
B
B
V
DQ  
DQ  
V
DDQ  
OE  
ADV  
GW  
DDQ  
C
B
G
H
J
DQ  
DQ  
DQ  
BW  
V
BW  
V
DQ  
DQ  
DQ  
C
C
C
C
B
B
B
B
DQ  
DQ  
C
SS  
SS  
B
V
V
NC  
V
NC  
V
V
DDQ  
DDQ  
DD  
DD  
DD  
K
DQ  
DQ  
DQ  
DQ  
DQ  
V
CLK  
NC  
V
DQ  
DQ  
DQ  
DQ  
DQ  
D
D
D
SS  
SS  
A
A
A
L
M
N
DQ  
DQ  
BW  
V
BW  
A
D
D
D
A
A
A
D
V
V
V
V
DDQ  
BWE  
A1  
DDQ  
SS  
SS  
SS  
DQ  
V
V
DQ  
D
SS  
A
DQ  
DQP  
A
A0  
V
DQP  
A
DQ  
P
R
D
D
SS  
SS  
A
NC  
NC  
MODE  
V
NC  
A
NC  
DD  
T
NC/72M  
TMS  
A
A
A
NC/36M  
NC  
ZZ  
V
TDI  
TCK  
TDO  
V
DDQ  
U
DDQ  
CY7C1362C (512K x 18)  
2
A
1
3
A
A
A
4
5
A
A
A
6
A
A
A
7
V
V
DDQ  
A
B
C
D
E
F
ADSP  
ADSC  
DDQ  
NC/288M  
CE  
A
NC/576M  
2
NC/144M  
V
NC/1G  
NC  
DD  
DQ  
NC  
DQ  
V
NC  
CE  
V
DQP  
B
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
A
NC  
V
V
V
V
V
V
NC  
DQ  
B
A
1
V
NC  
DQ  
DQ  
V
OE  
ADV  
GW  
DDQ  
A
DDQ  
NC  
NC  
DQ  
G
H
J
BW  
V
B
A
B
DQ  
NC  
DQ  
NC  
B
SS  
A
V
V
NC  
V
NC  
V
V
DDQ  
DDQ  
DD  
DD  
DD  
K
NC  
DQ  
DQ  
V
CLK  
NC  
V
NC  
DQ  
DQ  
B
SS  
SS  
A
L
M
N
P
NC  
DQ  
V
V
V
V
NC  
BW  
B
SS  
SS  
SS  
SS  
A
A
V
V
V
V
NC  
DQ  
V
DDQ  
BWE  
A1  
DDQ  
B
SS  
SS  
SS  
DQ  
NC  
NC  
DQ  
B
A
NC  
DQP  
A0  
NC  
B
A
R
T
NC  
A
A
MODE  
A
V
NC  
A
A
A
NC  
ZZ  
DD  
NC/72M  
NC/36M  
TCK  
V
TMS  
TDI  
TDO  
NC  
V
DDQ  
U
DDQ  
Document #: 38-05540 Rev. *H  
Page 5 of 31  
CY7C1360C  
CY7C1362C  
Pin Configurations (continued)  
165-Ball FBGA Pinout (3 Chip Enable with JTAG)  
CY7C1360C (256K x 36)  
1
2
3
4
5
6
7
8
9
10  
A
11  
NC  
NC/288M  
NC/144M  
DQPC  
A
B
C
D
CE1  
BWC  
BWD  
VSS  
VDD  
BWB  
BWA  
VSS  
VSS  
CE  
ADSC  
OE  
A
BWE  
GW  
VSS  
VSS  
ADV  
ADSP  
VDDQ  
VDDQ  
3
A
CE2  
VDDQ  
VDDQ  
CLK  
VSS  
VSS  
A
NC/576M  
DQPB  
DQB  
NC  
VSS  
VDD  
NC/1G  
DQB  
DQC  
DQC  
DQC  
DQC  
DQC  
NC  
DQC  
DQC  
DQC  
VSS  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDDQ  
VDDQ  
NC  
DQB  
DQB  
DQB  
NC  
DQB  
DQB  
DQB  
ZZ  
E
F
G
H
J
DQD  
DQD  
DQD  
DQD  
DQD  
DQD  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQA  
DQA  
DQA  
DQA  
DQA  
DQA  
K
L
DQD  
DQPD  
NC  
DQD  
NC  
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
NC/18M  
A1  
VSS  
NC  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQA  
NC  
A
DQA  
DQPA  
A
M
N
P
NC/72M  
TDI  
TDO  
A0  
MODE NC/36M  
A
A
TMS  
TCK  
A
A
A
A
R
CY7C1362C (512K x 18)  
1
2
A
3
4
5
NC  
6
7
8
9
10  
A
11  
A
NC/288M  
NC/144M  
NC  
A
B
C
D
BWB  
NC  
CE  
CE1  
CE2  
BWE  
GW  
VSS  
VSS  
ADSC  
OE  
ADV  
ADSP  
VDDQ  
VDDQ  
3
A
BWA  
VSS  
VSS  
CLK  
VSS  
VSS  
A
NC/576M  
DQPA  
DQA  
NC  
VDDQ  
VDDQ  
VSS  
VDD  
VSS  
NC/1G  
NC  
NC  
DQB  
VDD  
NC  
NC  
DQB  
DQB  
DQB  
VSS  
NC  
VDDQ  
VDDQ  
VDDQ  
NC  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDDQ  
VDDQ  
VDDQ  
NC  
NC  
NC  
DQA  
DQA  
DQA  
ZZ  
E
F
NC  
NC  
G
H
J
NC  
NC  
DQB  
DQB  
DQB  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
DQA  
DQA  
DQA  
NC  
NC  
NC  
K
L
NC  
NC  
DQB  
DQPB  
NC  
NC  
NC  
VDDQ  
VDDQ  
A
VDD  
VSS  
A
VSS  
NC  
VSS  
NC/18M  
A1  
VSS  
NC  
VDD  
VSS  
A
VDDQ  
VDDQ  
A
DQA  
NC  
A
NC  
NC  
A
M
N
P
NC/72M  
TDI  
TDO  
MODE NC/36M  
A
A
TMS  
A0  
TCK  
A
A
A
A
R
Document #: 38-05540 Rev. *H  
Page 6 of 31  
CY7C1360C  
CY7C1362C  
Pin Definitions  
Name  
I/O  
Description  
Address Inputs used to select one of the address locations. Sampled at the rising edge of  
A , A , A  
Input-  
0
1
[2]  
Synchronous the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active. A , A  
1
2
3
1
0
are fed to the two-bit counter.  
.
BW , BW  
Input-  
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the  
A
B
BW , BW  
Synchronous SRAM. Sampled on the rising edge of CLK.  
C
D
GW  
Input- Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a  
Synchronous global Write is conducted (ALL bytes are written, regardless of the values on BW and BWE).  
X
BWE  
CLK  
Input-  
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must  
Synchronous be asserted LOW to conduct a Byte Write.  
Input-  
Clock  
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the  
burst counter when ADV is asserted LOW, during a burst operation.  
CE  
CE  
CE  
Input-  
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction  
1
2
3
[2]  
Synchronous with CE and CE  
to select/deselect the device. ADSP is ignored if CE is HIGH. CE is  
2
3
1
1
sampled only when a new external address is loaded.  
Input-  
Synchronous with CE and CE  
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction  
[2]  
to select/deselect the device. CE is sampled only when a new external  
1
3
2
address is loaded.  
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction  
Synchronous with CE and CE to select/deselect the device. Not available for AJ package version. Not  
[2]  
Input-  
1
2
[2]  
connected for BGA. Where referenced, CE  
is assumed active throughout this document for  
3
BGA. CE is sampled only when a new external address is loaded.  
3
OE  
Input-  
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.  
Asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,  
and act as input data pins. OE is masked during the first clock of a read cycle when emerging  
from a deselected state.  
ADV  
Input-  
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it  
Synchronous automatically increments the address in a burst cycle.  
ADSP  
Input- Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When  
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A ,  
1
A are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP  
0
is recognized. ASDP is ignored when CE is deasserted HIGH.  
1
ADSC  
ZZ  
Input-  
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When  
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A ,  
1
A are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP  
0
is recognized.  
Input-  
ZZ “Sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical  
Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or  
left floating. ZZ pin has an internal pull-down.  
I/O-  
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered  
DQs, DQP  
X
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location  
specified by the addresses presented during the previous clock rise of the read cycle. The  
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.  
When HIGH, DQs and DQP are placed in a tri-state condition.  
X
V
V
V
V
Power Supply Power supply inputs to the core of the device.  
DD  
Ground  
Ground for the core of the device.  
SS  
I/O Ground  
Ground for the I/O circuitry.  
SSQ  
DDQ  
I/O Power Supply Power supply for the I/O circuitry.  
MODE  
Input-  
Static  
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V or  
DD  
left floating selects interleaved burst sequence. This is a strap pin and should remain static  
during device operation. Mode pin has an internal pull-up.  
TDO  
JTAG serial  
output  
Synchronous  
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG  
feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP  
packages.  
Document #: 38-05540 Rev. *H  
Page 7 of 31  
CY7C1360C  
CY7C1362C  
Pin Definitions (continued)  
Name  
TDI  
I/O  
Description  
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is  
Synchronous not being utilized, this pin can be disconnected or connected to V . This pin is not available  
DD  
on TQFP packages.  
TMS  
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is  
Synchronous not being utilized, this pin can be disconnected or connected to V . This pin is not available  
DD  
on TQFP packages.  
TCK  
NC  
JTAG-  
Clock  
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be  
connected to V . This pin is not available on TQFP packages.  
SS  
No Connects. Not internally connected to the die  
NC (18,36,  
72, 144, 288,  
576, 1G)  
These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M  
288M, 576M, and 1G densities.  
access. After the first cycle of the access, the outputs are  
controlled by the OE signal. Consecutive single Read cycles  
are supported. Once the SRAM is deselected at clock rise by  
the chip select and either ADSP or ADSC signals, its output  
will tri-state immediately.  
Functional Overview  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock.  
Maximum access delay from the clock rise (t ) is 2.8 ns  
(250-MHz device).  
CO  
Single Write Accesses Initiated by ADSP  
This access is initiated when both of the following conditions  
The CY7C1360C/CY7C1362C supports secondary cache in  
systems utilizing either a linear or interleaved burst sequence.  
The interleaved burst order supports Pentium and i486™  
processors. The linear burst sequence is suited for processors  
that utilize a linear burst sequence. The burst order is user  
selectable, and is determined by sampling the MODE input.  
Accesses can be initiated with either the Processor Address  
Strobe (ADSP) or the Controller Address Strobe (ADSC).  
Address advancement through the burst sequence is  
controlled by the ADV input. A two-bit on-chip wraparound  
burst counter captures the first address in a burst sequence  
and automatically increments the address for the rest of the  
burst access.  
are satisfied at clock rise: (1) ADSP is asserted LOW, and  
[2]  
(2) CE , CE , CE  
are all asserted active. The address  
1
2
3
presented to A is loaded into the address register and the  
address advancement logic while being delivered to the  
memory array. The Write signals (GW, BWE, and BW ) and  
X
ADV inputs are ignored during this first cycle.  
ADSP-triggered Write accesses require two clock cycles to  
complete. If GW is asserted LOW on the second clock rise, the  
data presented to the DQs inputs is written into the corre-  
sponding address location in the memory array. If GW is HIGH,  
then the Write operation is controlled by BWE and BW  
X
signals. The CY7C1360C/CY7C1362C provides Byte Write  
capability that is described in the Write Cycle Descriptions  
table. Asserting the Byte Write Enable input (BWE) with the  
Byte Write operations are qualified with the Byte Write Enable  
(BWE) and Byte Write Select (BW ) inputs. A Global Write  
X
selected Byte Write (BW ) input, will selectively write to only  
Enable (GW) overrides all Byte Write inputs and writes data to  
all four bytes. All writes are simplified with on-chip  
synchronous self-timed Write circuitry.  
[2]  
X
the desired bytes. Bytes not selected during a Byte Write  
operation will remain unaltered. A synchronous self-timed  
Write mechanism has been provided to simplify the Write  
operations.  
Three synchronous Chip Selects (CE , CE , CE ) and an  
1
2
3
asynchronous Output Enable (OE) provide for easy bank  
Because the CY7C1360C/CY7C1362C is a common I/O  
device, the Output Enable (OE) must be deasserted HIGH  
before presenting data to the DQs inputs. Doing so will tri-state  
the output drivers. As a safety precaution, DQs are automati-  
cally tri-stated whenever a Write cycle is detected, regardless  
of the state of OE.  
selection and output tri-state control. ADSP is ignored if CE  
is HIGH.  
1
Single Read Accesses  
This access is initiated when the following conditions are  
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)  
[2]  
CE , CE , CE  
are all asserted active, and (3) the Write  
1
2
3
Single Write Accesses Initiated by ADSC  
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored  
ADSC Write accesses are initiated when the following condi-  
if CE is HIGH. The address presented to the address inputs  
1
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is  
(A) is stored into the address advancement logic and the  
address register while being presented to the memory array.  
The corresponding data is allowed to propagate to the input of  
the output registers. At the rising edge of the next clock the  
data is allowed to propagate through the output register and  
onto the data bus within 2.8 ns (250-MHz device) if OE is  
active LOW. The only exception occurs when the SRAM is  
emerging from a deselected state to a selected state, its  
outputs are always tri-stated during the first cycle of the  
[2]  
deasserted HIGH, (3) CE , CE , CE  
are all asserted active,  
1
2
3
and (4) the appropriate combination of the Write inputs (GW,  
BWE, and BW ) are asserted active to conduct a Write to the  
X
desired byte(s). ADSC-triggered Write accesses require a  
single clock cycle to complete. The address presented to A is  
loaded into the address register and the address  
advancement logic while being delivered to the memory array.  
The ADV input is ignored during this cycle. If a global Write is  
Document #: 38-05540 Rev. *H  
Page 8 of 31  
CY7C1360C  
CY7C1362C  
conducted, the data presented to the DQs is written into the  
corresponding address location in the memory core. If a Byte  
Write is conducted, only the selected bytes are written. Bytes  
not selected during a Byte Write operation will remain  
unaltered. A synchronous self-timed Write mechanism has  
been provided to simplify the Write operations.  
clock cycles are required to enter into or exit from this “sleep”  
mode. While in this mode, data integrity is guaranteed.  
Accesses pending when entering the “sleep” mode are not  
considered valid nor is the completion of the operation  
guaranteed. The device must be deselected prior to entering  
[2]  
the “sleep” mode. CE , CE , CE , ADSP, and ADSC must  
1
2
3
remain inactive for the duration of t  
returns LOW.  
after the ZZ input  
ZZREC  
Because the CY7C1360C/CY7C1362C is a common I/O  
device, the Output Enable (OE) must be deasserted HIGH  
before presenting data to the DQs inputs. Doing so will tri-state  
the output drivers. As a safety precaution, DQs are automati-  
cally tri-stated whenever a Write cycle is detected, regardless  
of the state of OE.  
Interleaved Burst Address Table  
(MODE = Floating or VDD  
)
First  
Second  
Third  
Fourth  
Address  
Address  
Address  
Address  
Burst Sequences  
A , A  
A , A  
A , A  
A , A  
1
0
1
0
1
0
1
0
The CY7C1360C/CY7C1362C provides a two-bit wraparound  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
counter, fed by A , A , that implements either an interleaved  
1
0
or linear burst sequence. The interleaved burst sequence is  
designed specifically to support Intel Pentium applications.  
The linear burst sequence is designed to support processors  
that follow a linear burst sequence. The burst sequence is user  
selectable through the MODE input.  
Linear Burst Address Table (MODE = GND)  
Asserting ADV LOW at clock rise will automatically increment  
the burst counter to the next address in the burst sequence.  
Both Read and Write burst operations are supported.  
First  
Second  
Third  
Fourth  
Address  
Address  
Address  
Address  
A , A  
A , A  
A , A  
A , A  
1
0
1
0
1
0
1
0
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
Sleep Mode  
The ZZ input pin is an asynchronous input. Asserting ZZ  
places the SRAM in a power conservation “sleep” mode. Two  
ZZ Mode Electrical Characteristics  
Parameter  
Description  
Sleep mode standby current  
Device operation to ZZ  
Test Conditions  
ZZ > V – 0.2V  
Min.  
Max.  
Unit  
mA  
ns  
I
t
t
t
t
50  
DDZZ  
DD  
ZZ > V – 0.2V  
2t  
ZZS  
DD  
CYC  
CYC  
ZZ recovery time  
ZZ < 0.2V  
2t  
ns  
ZZREC  
ZZI  
CYC  
ZZ Active to sleep current  
ZZ Inactive to exit sleep current  
This parameter is sampled  
This parameter is sampled  
2t  
ns  
0
ns  
RZZI  
Truth Table[3, 4, 5, 6, 7, 8]  
Address  
Used  
Operation  
CE  
H
L
CE  
X
L
CE ZZ ADSP ADSC ADV WRITE OE CLK  
DQ  
1
2
3
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Deselect Cycle, Power Down  
Sleep Mode, Power Down  
READ Cycle, Begin Burst  
READ Cycle, Begin Burst  
None  
None  
X
X
H
X
H
X
L
L
L
L
L
L
H
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H  
L-H  
L-H  
L-H  
L-H  
X
Tri-State  
Tri-State  
Tri-State  
Tri-State  
Tri-State  
Tri-State  
Q
None  
L
X
L
L
None  
L
H
H
X
L
None  
L
X
X
H
H
H
L
None  
X
L
X
X
X
L
External  
External  
External  
L-H  
L-H  
L-H  
L
L
L
H
X
Tri-State  
D
WRITE Cycle, Begin Burst  
L
L
H
Notes:  
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.  
4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.  
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.  
6. CE , CE , and CE are available only in the TQFP package. BGA package has only two chip selects CE and CE .  
1
2
3
1
2
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks  
X
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a  
don't care for the remainder of the Write cycle.  
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE  
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).  
Document #: 38-05540 Rev. *H  
Page 9 of 31  
CY7C1360C  
CY7C1362C  
Truth Table[3, 4, 5, 6, 7, 8] (continued)  
Address  
Operation  
Used  
External  
External  
Next  
CE  
L
CE  
H
H
X
X
X
X
X
X
X
X
X
X
X
X
CE ZZ ADSP ADSC ADV WRITE OE CLK  
DQ  
1
2
3
READ Cycle, Begin Burst  
READ Cycle, Begin Burst  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
READ Cycle, Continue Burst  
WRITE Cycle, Continue Burst  
WRITE Cycle, Continue Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
READ Cycle, Suspend Burst  
WRITE Cycle, Suspend Burst  
WRITE Cycle, Suspend Burst  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
L
H
H
H
H
H
H
L
L
H
L
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
Q
L
L
Tri-State  
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next  
L
H
L
Tri-State  
Next  
L
Q
Next  
L
H
X
X
L
Tri-State  
Next  
L
D
Next  
L
L
D
Current  
Current  
Current  
Current  
Current  
Current  
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
Tri-State  
Q
H
X
X
Tri-State  
D
D
L
Partial Truth Table for Read/Write[5, 9]  
Function (CY7C1360C)  
GW  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE  
H
L
BW  
X
H
H
H
H
H
H
H
H
L
BW  
X
H
H
H
H
L
BW  
BW  
A
D
C
B
Read  
Read  
X
H
H
L
X
H
L
Write Byte A – (DQ and DQP )  
L
A
A
Write Byte B – (DQ and DQP )  
L
H
L
B
B
Write Bytes B, A  
Write Byte C – (DQ and DQP )  
L
L
L
H
H
L
H
L
C
C
Write Bytes C, A  
Write Bytes C, B  
Write Bytes C, B, A  
L
L
L
L
H
L
L
L
L
Write Byte D – (DQ and DQP )  
L
H
H
H
H
L
H
H
L
H
L
D
D
Write Bytes D, A  
Write Bytes D, B  
Write Bytes D, B, A  
Write Bytes D, C  
L
L
L
L
H
L
L
L
L
L
L
H
H
L
H
L
Write Bytes D, C, A  
Write Bytes D, C, B  
Write All Bytes  
L
L
L
L
L
L
H
L
L
L
L
L
Write All Bytes  
X
X
X
X
X
Note:  
9. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.  
X
Document #: 38-05540 Rev. *H  
Page 10 of 31  
CY7C1360C  
CY7C1362C  
Truth Table for Read/Write[5, 9]  
Function (CY7C1362C)  
GW  
H
BWE  
BW  
X
BW  
A
B
Read  
Read  
H
L
L
L
L
L
X
X
H
L
H
H
H
L
Write Byte A – (DQ and DQP )  
H
A
A
Write Byte B – (DQ and DQP )  
H
H
L
B
B
Write Bytes B, A  
Write All Bytes  
Write All Bytes  
H
L
H
L
L
L
X
X
Test Access Port (TAP)  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
The CY7C1360C/CY7C1362C incorporates a serial boundary  
scan test access port (TAP) in the BGA package only. The  
TQFP package does not offer this functionality. This part  
operates in accordance with IEEE Standard 1149.1-1900, but  
doesn’t have the set of functions required for full 1149.1  
compliance. These functions from the IEEE specification are  
excluded because their inclusion places an added delay in the  
critical speed path of the SRAM. Note the TAP controller  
functions in a manner that does not conflict with the operation  
of other devices using 1149.1 fully compliant TAPs. The TAP  
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.  
Test Clock (TCK)  
The test clock is used only with the TAP controller. All inputs  
are captured on the rising edge of TCK. All outputs are driven  
from the falling edge of TCK.  
Test MODE SELECT (TMS)  
The TMS input is used to give commands to the TAP controller  
and is sampled on the rising edge of TCK. It is allowable to  
leave this ball unconnected if the TAP is not used. The ball is  
pulled up internally, resulting in a logic HIGH level.  
The CY7C1360C/CY7C1362C contains a TAP controller,  
instruction register, boundary scan register, bypass register,  
and ID register.  
Test Data-In (TDI)  
The TDI ball is used to serially input information into the  
registers and can be connected to the input of any of the  
registers. The register between TDI and TDO is chosen by the  
instruction that is loaded into the TAP instruction register. For  
information on loading the instruction register, see TAP  
Controller State Diagram. TDI is internally pulled up and can  
be unconnected if the TAP is unused in an application. TDI is  
connected to the most significant bit (MSB) of any register.  
(See Tap Controller Block Diagram.)  
Disabling the JTAG Feature  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
(V ) to prevent clocking of the device. TDI and TMS are inter-  
SS  
nally pulled up and may be unconnected. They may alternately  
be connected to V through a pull-up resistor. TDO should be  
DD  
left unconnected. Upon power-up, the device will come up in  
a reset state which will not interfere with the operation of the  
device.TAP Controller State Diagram  
Test Data-Out (TDO)  
The 0/1 next to each state represents the value of TMS at the  
The TDO output ball is used to serially clock data-out from the  
registers. The output is active depending upon the current  
state of the TAP state machine. The output changes on the  
falling edge of TCK. TDO is connected to the least significant  
bit (LSB) of any register. (See Tap Controller State Diagram.)  
TEST-LOGIC  
1
RESET  
0
1
1
1
RUN-TEST/  
IDLE  
SELECT  
DR-SCAN  
SELECT  
IR-SCAN  
0
0
0
1
1
CAPTURE-DR  
CAPTURE-IR  
0
0
SHIFT-DR  
0
SHIFT-IR  
0
1
1
1
1
EXIT1-DR  
EXIT1-IR  
0
0
PAUSE-DR  
0
PAUSE-IR  
0
1
1
0
0
EXIT2-DR  
1
EXIT2-IR  
1
UPDATE-DR  
UPDATE-IR  
1
0
1
0
rising edge of TCK.  
Document #: 38-05540 Rev. *H  
Page 11 of 31  
CY7C1360C  
CY7C1362C  
Boundary Scan Register  
TAP Controller Block Diagram  
0
The boundary scan register is connected to all the input and  
bidirectional balls on the SRAM.  
Bypass Register  
The boundary scan register is loaded with the contents of the  
RAM I/O ring when the TAP controller is in the Capture-DR  
state and is then placed between the TDI and TDO balls when  
the controller is moved to the Shift-DR state. The EXTEST,  
SAMPLE/PRELOAD and SAMPLE Z instructions can be used  
to capture the contents of the I/O ring.  
2
1
0
0
0
Selection  
Circuitry  
Instruction Register  
31 30 29  
Identification Register  
Selection  
Circuitry  
TDI  
TDO  
.
.
.
2
1
The Boundary Scan Order tables show the order in which the  
bits are connected. Each bit corresponds to one of the bumps  
on the SRAM package. The MSB of the register is connected  
to TDI and the LSB is connected to TDO.  
x
.
.
.
.
.
2
1
Boundary Scan Register  
Identification (ID) Register  
The ID register is loaded with a vendor-specific, 32-bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired  
into the SRAM and can be shifted out when the TAP controller  
is in the Shift-DR state. The ID register has a vendor code and  
other information described in the Identification Register  
Definitions table.  
TCK  
TMS  
TAP CONTROLLER  
Performing a TAP Reset  
TAP Instruction Set  
A RESET is performed by forcing TMS HIGH (V ) for five  
DD  
Overview  
rising edges of TCK. This RESET does not affect the operation  
of the SRAM and may be performed while the SRAM is  
operating.  
Eight different instructions are possible with the three-bit  
instruction register. All combinations are listed in the  
Instruction Codes table. Three of these instructions are listed  
as RESERVED and should not be used. The other five instruc-  
tions are described in detail below.  
At power-up, the TAP is reset internally to ensure that TDO  
comes up in a High-Z state.  
TAP Registers  
The TAP controller used in this SRAM is not fully compliant to  
the 1149.1 convention because some of the mandatory 1149.1  
instructions are not fully implemented.  
Registers are connected between the TDI and TDO balls and  
allow data to be scanned into and out of the SRAM test  
circuitry. Only one register can be selected at a time through  
the instruction register. Data is serially loaded into the TDI ball  
on the rising edge of TCK. Data is output on the TDO ball on  
the falling edge of TCK.  
The TAP controller cannot be used to load address data or  
control signals into the SRAM and cannot preload the I/O  
buffers. The SRAM does not implement the 1149.1 commands  
EXTEST or INTEST or the PRELOAD portion of  
SAMPLE/PRELOAD; rather, it performs a capture of the I/O  
ring when these instructions are executed.  
Instruction Register  
Three-bit instructions can be serially loaded into the instruction  
register. This register is loaded when it is placed between the  
TDI and TDO balls as shown in the Tap Controller Block  
Diagram. Upon power-up, the instruction register is loaded  
with the IDCODE instruction. It is also loaded with the IDCODE  
instruction if the controller is placed in a reset state as  
described in the previous section.  
Instructions are loaded into the TAP controller during the  
Shift-IR state when the instruction register is placed between  
TDI and TDO. During this state, instructions are shifted  
through the instruction register through the TDI and TDO balls.  
To execute the instruction once it is shifted in, the TAP  
controller needs to be moved into the Update-IR state.  
EXTEST  
When the TAP controller is in the Capture-IR state, the two  
least significant bits are loaded with a binary “01” pattern to  
allow for fault isolation of the board-level serial test data path.  
EXTEST is a mandatory 1149.1 instruction which is to be  
executed whenever the instruction register is loaded with all  
0s. EXTEST is not implemented in this SRAM TAP controller,  
and therefore this device is not compliant to 1149.1. The TAP  
controller does recognize an all-0 instruction.  
Bypass Register  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain chips. The bypass  
register is a single-bit register that can be placed between the  
TDI and TDO balls. This allows data to be shifted through the  
SRAM with minimal delay. The bypass register is set LOW  
When an EXTEST instruction is loaded into the instruction  
register, the SRAM responds as if a SAMPLE/PRELOAD  
instruction has been loaded. There is one difference between  
the two instructions. Unlike the SAMPLE/PRELOAD  
instruction, EXTEST places the SRAM outputs in a High-Z  
state.  
(V ) when the BYPASS instruction is executed.  
SS  
Document #: 38-05540 Rev. *H  
Page 12 of 31  
CY7C1360C  
CY7C1362C  
IDCODE  
To guarantee that the boundary scan register will capture the  
correct value of a signal, the SRAM signal must be stabilized  
long enough to meet the TAP controller's capture set-up plus  
The IDCODE instruction causes a vendor-specific, 32-bit code  
to be loaded into the instruction register. It also places the  
instruction register between the TDI and TDO balls and allows  
the IDCODE to be shifted out of the device when the TAP  
controller enters the Shift-DR state.  
hold times (t and t ). The SRAM clock input might not be  
CS  
CH  
captured correctly if there is no way in a design to stop (or  
slow) the clock during a SAMPLE/PRELOAD instruction. If this  
is an issue, it is still possible to capture all other signals and  
simply ignore the value of the CK and CK captured in the  
boundary scan register.  
The IDCODE instruction is loaded into the instruction register  
upon power-up or whenever the TAP controller is given a test  
logic reset state.  
Once the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the  
boundary scan register between the TDI and TDO pins.  
SAMPLE Z  
The SAMPLE Z instruction causes the boundary scan register  
to be connected between the TDI and TDO balls when the TAP  
controller is in a Shift-DR state. It also places all SRAM outputs  
into a High-Z state.  
PRELOAD allows an initial data pattern to be placed at the  
latched parallel outputs of the boundary scan register cells  
prior to the selection of another boundary scan test operation.  
The shifting of data for the SAMPLE and PRELOAD phases  
can occur concurrently when required—that is, while data  
captured is shifted out, the preloaded data can be shifted in.  
SAMPLE/PRELOAD  
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When  
the SAMPLE/PRELOAD instructions are loaded into the  
instruction register and the TAP controller is in the Capture-DR  
state, a snapshot of data on the inputs and output pins is  
captured in the boundary scan register.  
BYPASS  
When the BYPASS instruction is loaded in the instruction  
register and the TAP is placed in a Shift-DR state, the bypass  
register is placed between the TDI and TDO balls. The  
advantage of the BYPASS instruction is that it shortens the  
boundary scan path when multiple devices are connected  
together on a board.  
The user must be aware that the TAP controller clock can only  
operate at a frequency up to 20 MHz, while the SRAM clock  
operates more than an order of magnitude faster. Because  
there is a large difference in the clock frequencies, it is  
possible that during the Capture-DR state, an input or output  
will undergo a transition. The TAP may then try to capture a  
signal while in transition (metastable state). This will not harm  
the device, but there is no guarantee as to the value that will  
be captured. Repeatable results may not be possible.  
Reserved  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
TAP Timing  
1
2
3
4
5
6
Test Clock  
(TCK)  
t
t
t
TH  
CYC  
TL  
t
t
t
t
TMSS  
TDIS  
TMSH  
Test Mode Select  
(TMS)  
TDIH  
Test Data-In  
(TDI)  
t
TDOV  
t
TDOX  
Test Data-Out  
(TDO)  
DON’T CARE  
UNDEFINED  
Document #: 38-05540 Rev. *H  
Page 13 of 31  
CY7C1360C  
CY7C1362C  
[10, 11]  
TAP AC Switching Characteristics Over the Operating Range  
Parameter  
Clock  
Description  
Min.  
Max.  
Unit  
t
t
t
t
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH time  
TCK Clock LOW time  
50  
ns  
MHz  
ns  
TCYC  
TF  
20  
10  
20  
20  
TH  
ns  
TL  
Output Times  
t
t
TCK Clock LOW to TDO Valid  
TCK Clock LOW to TDO Invalid  
ns  
ns  
TDOV  
TDOX  
0
Set-up Times  
t
t
t
TMS Set-up to TCK Clock Rise  
TDI Set-up to TCK Clock Rise  
Capture Set-up to TCK Rise  
5
5
5
ns  
ns  
ns  
TMSS  
TDIS  
CS  
Hold Times  
t
t
t
TMS Hold after TCK Clock Rise  
TDI Hold after Clock Rise  
5
5
5
ns  
ns  
ns  
TMSH  
TDIH  
CH  
Capture Hold after Clock Rise  
3.3V TAP AC Test Conditions  
2.5V TAP AC Test Conditions  
Input pulse levels ................................................ V to 3.3V  
Input pulse levels.................................................V to 2.5V  
SS  
SS  
Input rise and fall times................................................... 1 ns  
Input timing reference levels...........................................1.5V  
Output reference levels...................................................1.5V  
Test load termination supply voltage...............................1.5V  
Input rise and fall time .....................................................1 ns  
Input timing reference levels......................................... 1.25V  
Output reference levels ................................................ 1.25V  
Test load termination supply voltage ............................ 1.25V  
3.3V TAP AC Output Load Equivalent  
2.5V TAP AC Output Load Equivalent  
1.5V  
1.25V  
50  
50  
TDO  
TDO  
ZO= 50Ω  
ZO= 50Ω  
20pF  
20pF  
TAP DC Electrical Characteristics And Operating Conditions  
[12]  
(0°C < T < +70°C; V = 3.3V ±0.165V unless otherwise noted)  
A
DD  
Parameter  
Description  
Conditions  
Min.  
2.4  
2.0  
2.9  
2.1  
Max.  
Unit  
V
V
V
V
Output HIGH Voltage  
Output HIGH Voltage  
Output LOW Voltage  
I
I
I
= –4.0 mA  
= –1.0 mA  
= –100 µA  
V
V
V
V
V
V
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
OH1  
OH  
OH  
OH  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
V
V
OH2  
OL1  
V
I
I
= 8.0 mA  
= 8.0 mA  
0.4  
0.4  
V
OL  
V
OL  
Notes:  
10. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.  
CS  
CH  
11. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.  
R
F
12. All voltages referenced to V (GND).  
SS  
Document #: 38-05540 Rev. *H  
Page 14 of 31  
CY7C1360C  
CY7C1362C  
TAP DC Electrical Characteristics And Operating Conditions  
[12]  
(0°C < T < +70°C; V = 3.3V ±0.165V unless otherwise noted)  
(continued)  
A
DD  
Parameter  
Description  
Conditions  
Min.  
Max.  
0.2  
Unit  
V
V
V
V
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Input Load Current  
I
= 100 µA  
V
V
V
V
V
V
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
= 3.3V  
= 2.5V  
OL2  
OL  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
DDQ  
0.2  
V
2.0  
1.7  
V
V
+ 0.3  
V
IH  
IL  
DD  
DD  
+ 0.3  
V
–0.5  
–0.3  
–5  
0.7  
V
0.7  
5
V
I
GND < V < V  
DDQ  
µA  
X
IN  
Identification Register Definitions  
CY7C1360C  
(256KX36)  
CY7C1362C  
(512KX18)  
Instruction Field  
Description  
Revision Number (31:29)  
000  
01011  
000  
Describes the version number  
Reserved for Internal Use  
[13]  
Device Depth (28:24)  
01011  
Device Width (23:18) 119-BGA  
Device Width (23:18) 165- FBGA  
Cypress Device ID (17:12)  
101000  
000000  
100110  
00000110100  
1
101000  
000000  
010110  
Defines memory type and architecture  
Defines memory type and architecture  
Defines width and density  
Cypress JEDEC ID Code (11:1)  
ID Register Presence Indicator (0)  
00000110100 Allows unique identification of SRAM vendor  
1
Indicates the presence of an ID register  
Scan Register Sizes  
Register Name  
Bit Size (x36)  
Bit Size (x18)  
Instruction  
Bypass  
ID  
3
3
1
1
32  
71  
71  
32  
71  
71  
Boundary Scan Order (119-ball BGA package)  
Boundary Scan Order (165-ball FBGA package)  
Identification Codes  
Instruction  
EXTEST  
Code  
Description  
000  
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM outputs to High-Z state.  
IDCODE  
001  
010  
Loads the ID register with the vendor ID code and places the register between TDI and  
TDO. This operation does not affect SRAM operations.  
SAMPLE Z  
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Forces all SRAM output drivers to a High-Z state.  
RESERVED  
011  
100  
Do Not Use: This instruction is reserved for future use.  
SAMPLE/PRELOAD  
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.  
Does not affect SRAM operation.  
RESERVED  
RESERVED  
BYPASS  
101  
110  
111  
Do Not Use: This instruction is reserved for future use.  
Do Not Use: This instruction is reserved for future use.  
Places the bypass register between TDI and TDO. This operation does not affect SRAM  
operations.  
Note:  
13. Bit #24 is “1” in the Register Definitions for both 2.5V and 3.3V versions of this device.  
Document #: 38-05540 Rev. *H  
Page 15 of 31  
CY7C1360C  
CY7C1362C  
165-ball FBGA Boundary Scan Order  
CY7C1360C (256K x 36)  
CY7C1362C (512K x 18)  
Signal  
Signal  
Name  
Signal  
Name  
Signal  
Name  
Bit#  
1
ball ID  
B6  
Name  
CLK  
GW  
Bit#  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
ball ID  
R6  
P6  
Bit#  
1
ball ID  
B6  
Bit#  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
ball ID  
R6  
A0  
CLK  
GW  
A0  
A1  
2
B7  
A1  
2
B7  
P6  
3
A7  
BWE  
OE  
R4  
P4  
R3  
P3  
A
3
A7  
BWE  
OE  
R4  
A
4
B8  
A
A
4
B8  
P4  
A
5
A8  
ADSC  
ADSP  
ADV  
A
5
A8  
ADSC  
ADSP  
ADV  
A
R3  
A
6
B9  
A
6
B9  
P3  
A
7
A9  
R1  
N1  
L2  
MODE  
7
A9  
R1  
MODE  
Internal  
Internal  
Internal  
Internal  
8
B10  
A10  
C11  
E10  
F10  
G10  
D10  
D11  
E11  
F11  
G11  
H11  
J10  
K10  
L10  
M10  
J11  
K11  
L11  
M11  
N11  
R11  
R10  
P10  
R9  
DQP  
8
B10  
Internal  
Internal  
Internal  
Internal  
N1  
D
9
A
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
9
A10  
A
D
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
DQP  
K2  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
A11  
A
B
D
D
D
D
D
D
D
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
J2  
Internal  
Internal  
Internal  
C11  
Internal  
Internal  
Internal  
B
M2  
M1  
L1  
DQP  
B
B
B
B
B
B
B
B
M1  
DQ  
DQ  
DQ  
DQ  
B
DQP  
L1  
A
B
B
B
K1  
D11  
DQ  
DQ  
DQ  
DQ  
K1  
A
A
A
A
J1  
E11  
J1  
Internal  
G2  
F2  
Internal  
F11  
Internal  
G2  
Internal  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
G11  
H11  
DQ  
DQ  
DQ  
DQ  
C
C
C
C
C
C
C
C
B
B
B
B
ZZ  
ZZ  
F2  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
E2  
J10  
DQ  
DQ  
DQ  
DQ  
E2  
A
A
A
A
A
A
A
A
A
A
A
A
D2  
G1  
F1  
K10  
D2  
L10  
Internal  
Internal  
Internal  
Internal  
Internal  
B2  
Internal  
Internal  
Internal  
Internal  
Internal  
A
M10  
Internal  
Internal  
Internal  
Internal  
Internal  
R11  
E1  
Internal  
D1  
C1  
B2  
A2  
A3  
Internal  
DQP  
A
Internal  
C
Internal  
DQP  
A
Internal  
A2  
A
A
A
A
A
A
A
A
A
A
CE  
CE  
A
A
A
A
A
A
A
A
A3  
CE  
CE  
1
1
2
B3  
R10  
P10  
B3  
2
B4  
BW  
BW  
BW  
Internal  
Internal  
A4  
Internal  
Internal  
D
C
B
A4  
A5  
B5  
A6  
R9  
P9  
P9  
BW  
B
A
3
R8  
BW  
R8  
B5  
BW  
A
P8  
CE  
P8  
A6  
CE  
3
P11  
P11  
Document #: 38-05540 Rev. *H  
Page 16 of 31  
CY7C1360C  
CY7C1362C  
119-ball BGA Boundary Scan Order  
CY7C1360C (256K x 36)  
CY7C1362C (512K x 18)  
Signal  
Signal  
Signal  
Name  
Signal  
Name  
Bit# ball ID  
Name  
CLK  
GW  
Bit#  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
ball ID  
P4  
Bit#  
1
ball ID  
Name  
CLK  
GW  
Bit#  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
ball ID  
1
A0  
P4  
A0  
K4  
H4  
M4  
F4  
B4  
A4  
G4  
C3  
B3  
D6  
H7  
G6  
E6  
D7  
E7  
F6  
G7  
H6  
T7  
K7  
L6  
K4  
H4  
2
N4  
A1  
2
N4  
A1  
3
BWE  
OE  
R6  
A
3
M4  
BWE  
OE  
R6  
A
4
T5  
A
A
4
F4  
T5  
A
5
ADSC  
ADSP  
ADV  
A
T3  
5
B4  
ADSC  
ADSP  
ADV  
A
T3  
A
6
R2  
A
6
A4  
R2  
A
7
R3  
MODE  
7
G4  
R3  
MODE  
Internal  
Internal  
Internal  
Internal  
8
P2  
DQP  
8
C3  
Internal  
Internal  
Internal  
Internal  
P2  
D
9
A
P1  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
9
B3  
A
D
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
DQP  
L2  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
T2  
A
B
D
D
D
D
D
D
D
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
K1  
Internal  
Internal  
Internal  
D6  
Internal  
Internal  
Internal  
B
N2  
DQP  
B
B
B
B
B
B
B
B
N1  
N1  
DQ  
DQ  
DQ  
DQ  
B
M2  
L1  
DQP  
M2  
A
B
B
B
E7  
DQ  
DQ  
DQ  
DQ  
L1  
A
A
A
A
K2  
F6  
K2  
Internal  
H1  
Internal  
G7  
Internal  
H1  
Internal  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
H6  
DQ  
DQ  
DQ  
DQ  
C
C
C
C
C
C
C
C
B
B
B
B
ZZ  
G2  
E2  
T7  
ZZ  
G2  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
K7  
DQ  
DQ  
DQ  
DQ  
E2  
A
A
A
A
A
A
A
A
A
A
A
A
D1  
L6  
D1  
N6  
P7  
N7  
M6  
L7  
H2  
N6  
Internal  
Internal  
Internal  
Internal  
Internal  
C2  
Internal  
Internal  
Internal  
Internal  
Internal  
A
G1  
F2  
P7  
Internal  
Internal  
Internal  
Internal  
Internal  
T6  
Internal  
E1  
Internal  
D2  
DQP  
A
Internal  
C
K6  
P6  
T4  
A3  
C5  
B5  
A5  
C6  
A6  
B6  
C2  
Internal  
DQP  
A2  
A
Internal  
A2  
A
A
A
A
A
A
A
A
A
A
E4  
CE  
CE  
A
A
A
A
A
A
A
A
E4  
CE  
CE  
1
1
2
B2  
A3  
B2  
2
L3  
BWD  
C5  
Internal  
Internal  
G3  
Internal  
Internal  
G3  
G5  
L5  
BW  
BW  
B5  
C
B
A5  
BW  
B
BW  
C6  
L5  
BW  
A
A
Internal  
Internal  
A6  
Internal  
Internal  
B6  
Document #: 38-05540 Rev. *H  
Page 17 of 31  
CY7C1360C  
CY7C1362C  
DC Input Voltage ..................................0.5V to VDD + 0.5V  
Current into Outputs (LOW)......................................... 20 mA  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature .................................65°C to +150°C  
Latch-up Current.....................................................> 200 mA  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Supply Voltage on V Relative to GND........ –0.5V to +4.6V  
DD  
Ambient  
Supply Voltage on V  
Relative to GND ......0.5V to +V  
Range  
Temperature  
V
V
DDQ  
DDQ  
DD  
DD  
DC Voltage Applied to Outputs  
in Tri-State..........................................–0.5V to VDDQ + 0.5V  
Commercial 0°C to +70°C  
Industrial –40°C to +85°C  
3.3V –  
5%/+10%  
2.5V – 5% to  
V
DD  
[14, 15]  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Power Supply Voltage  
I/O Supply Voltage  
Test Conditions  
Min.  
3.135  
3.135  
2.375  
2.4  
Max.  
Unit  
V
V
3.6  
V
V
DD  
for 3.3V I/O  
for 2.5V I/O  
V
DD  
DDQ  
2.625  
V
V
V
V
V
I
Output HIGH Voltage  
Output LOW Voltage  
for 3.3V I/O, I = –4.0 mA  
V
OH  
OL  
IH  
OH  
for 2.5V I/O, I = –1.0 mA  
2.0  
V
OH  
for 3.3V I/O, I = 8.0 mA  
0.4  
0.4  
V
OL  
for 2.5V I/O, I = 1.0 mA  
V
OL  
[14]  
Input HIGH Voltage  
for 3.3V I/O  
for 2.5V I/O  
for 3.3V I/O  
for 2.5V I/O  
GND V V  
2.0  
1.7  
V
V
+ 0.3V  
V
DD  
DD  
+ 0.3V  
V
[14]  
Input LOW Voltage  
–0.3  
–0.3  
–5  
0.8  
0.7  
5
V
IL  
V
Input Leakage Current  
except ZZ and MODE  
µA  
X
I
DDQ  
Input Current of MODE Input = V  
Input = V  
–30  
–5  
µA  
µA  
SS  
DD  
SS  
DD  
5
Input Current of ZZ  
Input = V  
Input = V  
µA  
30  
5
µA  
I
I
Output Leakage Current GND V V  
Output Disabled  
–5  
µA  
OZ  
I
DDQ,  
V
Operating Supply  
V
f = f  
= Max., I  
= 0 mA,  
4-ns cycle, 250 MHz  
5-ns cycle, 200 MHz  
6-ns cycle, 166 MHz  
4-ns cycle, 250 MHz  
5-ns cycle, 200 MHz  
6-ns cycle, 166 MHz  
250  
220  
180  
130  
120  
110  
40  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
DD  
DD  
DD  
OUT  
CYC  
Current  
= 1/t  
MAX  
I
Automatic CE  
Power-down  
Current—TTL Inputs  
V = Max, Device Deselected,  
DD  
SB1  
V
V or V V  
IN  
IH  
IN  
IL  
f = f  
= 1/t  
MAX CYC  
I
I
Automatic CE  
Power-down  
Current—CMOS Inputs f = 0  
V = Max, Device Deselected, All speeds  
DD  
SB2  
V
0.3V or V > V – 0.3V,  
IN  
IN  
DDQ  
Automatic CE  
Power-down  
Current—CMOS Inputs f = f  
V
V
= Max, Device Deselected, or 4-ns cycle, 250 MHz  
120  
110  
100  
40  
mA  
mA  
mA  
mA  
SB3  
DD  
0.3V or V > V  
– 0.3V  
IN  
IN  
DDQ  
5-ns cycle, 200 MHz  
6-ns cycle, 166 MHz  
= 1/t  
MAX  
CYC  
I
Automatic CE  
V = Max, Device Deselected, All Speeds  
DD  
SB4  
Power-down  
Current—TTL Inputs  
V
V or V V , f = 0  
IN  
IH IN IL  
Notes:  
14. Overshoot: V (AC) < V +1.5V (Pulse width less than t  
/2), undershoot: V (AC) > –2V (Pulse width less than t /2).  
CYC  
IH  
DD  
CYC  
IL  
15. T  
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V  
< V  
.
Power-up  
DD  
IH  
DD  
DDQ  
DD  
Document #: 38-05540 Rev. *H  
Page 18 of 31  
CY7C1360C  
CY7C1362C  
Capacitance[16]  
100 TQFP  
Max.  
119 BGA  
Max.  
165 FBGA  
Parameter  
Description  
Input Capacitance  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max.  
Unit  
pF  
C
C
C
5
5
5
5
5
7
5
5
7
IN  
A
V
= 3.3V  
= 2.5V  
DD  
Clock Input Capacitance  
Input/Output Capacitance  
pF  
CLK  
I/O  
V
DDQ  
pF  
Thermal Resistance[16]  
100 TQFP  
Package  
119 BGA  
Package  
165 FBGA  
Package  
Parameter  
Description  
Test Conditions  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient) methods and procedures for  
Test conditions follow standard test  
29.41  
34.1  
16.8  
°C/W  
JA  
measuring thermal impedance, per  
EIA/JESD51.  
Θ
Thermal Resistance  
(Junction to Case)  
6.13  
14.0  
3
°C/W  
JC  
AC Test Loads and Waveforms  
3.3V I/O Test Load  
OUTPUT  
R = 317Ω  
3.3V  
ALL INPUT PULSES  
90%  
VDDQ  
OUTPUT  
90%  
10%  
Z = 50Ω  
0
R = 50Ω  
10%  
L
GND  
5 pF  
INCLUDING  
R = 351Ω  
1 ns  
1 ns  
V = 1.5V  
T
(a)  
JIG AND  
SCOPE  
(b)  
(c)  
2.5V I/O Test Load  
R = 1667Ω  
2.5V  
OUTPUT  
R = 50Ω  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
90%  
10%  
Z = 50Ω  
0
10%  
L
5 pF  
R =1538Ω  
1 ns  
1 ns  
INCLUDING  
V = 1.25V  
T
JIG AND  
SCOPE  
(a)  
(b)  
(c)  
Note:  
16. Tested initially and after any design or process change that may affect these parameters.  
Document #: 38-05540 Rev. *H  
Page 19 of 31  
CY7C1360C  
CY7C1362C  
[17, 18]  
Switching Characteristics Over the Operating Range  
–250  
–200  
–166  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
[19]  
t
V
(Typical) to the First Access  
1
1
1
ms  
POWER  
DD  
Clock  
t
t
t
Clock Cycle Time  
Clock HIGH  
4.0  
1.8  
1.8  
5.0  
2.0  
2.0  
6.0  
2.4  
2.4  
ns  
ns  
ns  
CYC  
CH  
Clock LOW  
CL  
Output Times  
t
t
t
t
t
t
t
Data Output Valid after CLK Rise  
Data Output Hold after CLK Rise  
2.8  
3.0  
3.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CO  
1.25  
1.25  
1.25  
1.25  
1.25  
1.25  
1.25  
1.25  
1.25  
DOH  
CLZ  
[20, 21, 22]  
Clock to Low-Z  
[20, 21, 22]  
Clock to High-Z  
2.8  
2.8  
3.0  
3.0  
3.5  
3.5  
CHZ  
OEV  
OELZ  
OEHZ  
OE LOW to Output Valid  
[20, 21, 22]  
OE LOW to Output Low-Z  
0
0
0
[20, 21, 22]  
OE HIGH to Output High-Z  
2.8  
3.0  
3.5  
Set-up Times  
t
t
t
t
t
t
Address Set-up before CLK Rise  
ADSC, ADSP Set-up before CLK Rise  
ADV Set-up before CLK Rise  
1.4  
1.4  
1.4  
1.4  
1.4  
1.4  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
ns  
ns  
ns  
ns  
AS  
ADS  
ADVS  
WES  
DS  
GW, BWE, BW Set-up before CLK Rise  
X
Data Input Set-up before CLK Rise  
Chip Enable Set-up before CLK Rise  
CES  
Hold Times  
t
t
t
t
t
t
Address Hold after CLK Rise  
ADSP, ADSC Hold after CLK Rise  
ADV Hold after CLK Rise  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
AH  
ADH  
ADVH  
WEH  
DH  
GW, BWE, BW Hold after CLK Rise  
X
Data Input Hold after CLK Rise  
Chip Enable Hold after CLK Rise  
CEH  
Notes:  
17. Timing reference level is 1.5V when V  
= 3.3V and is 1.25V when V  
= 2.5V.  
DDQ  
DDQ  
18. Test conditions shown in (a) of AC Test Loads unless otherwise noted.  
19. This part has a voltage regulator internally; t  
is the time that the power needs to be supplied above V (minimum) initially before a Read or Write operation  
POWER  
DD  
can be initiated.  
20. t  
, t  
,t  
, and t  
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.  
CHZ CLZ OELZ  
OEHZ  
21. At any given voltage and temperature, t  
is less than t  
and t  
is less than t  
to eliminate bus contention between SRAMs when sharing the same  
CLZ  
OEHZ  
OELZ  
CHZ  
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed  
to achieve High-Z prior to Low-Z under the same system conditions.  
22. This parameter is sampled and not 100% tested.  
Document #: 38-05540 Rev. *H  
Page 20 of 31  
CY7C1360C  
CY7C1362C  
Switching Waveforms  
[23]  
Read Cycle Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
ADH  
ADS  
t
t
AH  
AS  
A1  
A2  
A3  
ADDRESS  
Burst continued with  
new base address  
t
t
WEH  
WES  
GW, BWE,  
BWx  
Deselect  
cycle  
t
t
CEH  
CES  
CE  
t
t
ADVH  
ADVS  
ADV  
OE  
ADV  
suspends  
burst.  
t
t
OEV  
CO  
t
t
OEHZ  
t
t
CHZ  
OELZ  
DOH  
t
CLZ  
t
Q(A2)  
Q(A2 + 1)  
Q(A2 + 2)  
Q(A2 + 3)  
Q(A2)  
Q(A2 + 1)  
Q(A1)  
Data Out (Q)  
High-Z  
CO  
Burst wraps around  
to its initial state  
Single READ  
BURST READ  
DON’T CARE  
UNDEFINED  
Note:  
23. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.  
1
2
3
1
2
3
Document #: 38-05540 Rev. *H  
Page 21 of 31  
CY7C1360C  
CY7C1362C  
Switching Waveforms (continued)  
[23, 24]  
Write Cycle Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC extends burst  
t
t
ADH  
ADS  
t
t
ADH  
ADS  
ADSC  
t
t
AH  
AS  
A1  
A2  
A3  
ADDRESS  
Byte write signals are  
ignored for first cycle when  
ADSP initiates burst  
t
t
WEH  
WES  
BWE,  
BWX  
t
t
WEH  
WES  
GW  
CE  
t
t
CEH  
CES  
t
t
ADVH  
ADVS  
ADV  
OE  
ADV suspends burst  
t
t
DH  
DS  
Data In (D)  
D(A2)  
D(A2 + 1)  
D(A2 + 1)  
D(A2 + 2)  
D(A2 + 3)  
D(A3)  
D(A3 + 1)  
D(A3 + 2)  
D(A1)  
High-Z  
t
OEHZ  
Data Out (Q)  
BURST READ  
Single WRITE  
BURST WRITE  
Extended BURST WRITE  
DON’T CARE  
UNDEFINED  
Note:  
24.  
Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.  
X
Document #: 38-05540 Rev. *H  
Page 22 of 31  
CY7C1360C  
CY7C1362C  
Switching Waveforms (continued)  
[23, 25, 26]  
Read/Write Cycle Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
AH  
AS  
A1  
A2  
A3  
A4  
A5  
A6  
ADDRESS  
t
t
WEH  
WES  
BWE,  
BWX  
t
t
CEH  
CES  
CE  
ADV  
OE  
t
t
DH  
t
CO  
DS  
t
OELZ  
Data In (D)  
High-Z  
High-Z  
D(A3)  
D(A5)  
D(A6)  
t
t
OEHZ  
CLZ  
Data Out (Q)  
Q(A1)  
Q(A2)  
Q(A4)  
Q(A4+1)  
Q(A4+2)  
Q(A4+3)  
Back-to-Back READs  
Single WRITE  
BURST READ  
Back-to-Back  
WRITEs  
DON’T CARE  
UNDEFINED  
Notes:  
25. The data bus (Q) remains in high-Z following a Write cycle, unless a new Read access is initiated by ADSP or ADSC.  
26. GW is HIGH.  
Document #: 38-05540 Rev. *H  
Page 23 of 31  
CY7C1360C  
CY7C1362C  
Switching Waveforms (continued)  
[27, 28]  
ZZ Mode Timing  
CLK  
t
t
ZZ  
ZZREC  
ZZ  
t
ZZI  
I
SUPPLY  
I
DDZZ  
t
RZZI  
ALL INPUTS  
(except ZZ)  
DESELECT or READ Only  
Outputs (Q)  
High-Z  
DON’T CARE  
Notes:  
27. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.  
28. DQs are in High-Z when exiting ZZ sleep mode.  
Document #: 38-05540 Rev. *H  
Page 24 of 31  
CY7C1360C  
CY7C1362C  
Ordering Information  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
CY7C1360C-166AXC  
CY7C1362C-166AXC  
Part and Package Type  
166  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
(3 Chip Enable)  
Commercial  
CY7C1360C-166AJXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
(2 Chip Enable)  
CY7C1362C-166AJXC  
CY7C1360C-166BGC  
CY7C1362C-166BGC  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1360C-166BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1362C-166BGXC  
CY7C1360C-166BZC  
CY7C1362C-166BZC  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1360C-166BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
CY7C1362C-166BZXC  
CY7C1360C-166AXI  
CY7C1362C-166AXI  
CY7C1360C-166AJXI  
CY7C1362C-166AJXI  
CY7C1360C-166BGI  
CY7C1362C-166BGI  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
(3 Chip Enable)  
Industrial  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
(2 Chip Enable)  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1360C-166BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1362C-166BGXI  
CY7C1360C-166BZI  
CY7C1362C-166BZI  
CY7C1360C-166BZXI  
CY7C1362C-166BZXI  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
Document #: 38-05540 Rev. *H  
Page 25 of 31  
CY7C1360C  
CY7C1362C  
Ordering Information (continued)  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
200  
CY7C1360C-200AXC  
CY7C1362C-200AXC  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
(3 Chip Enable)  
Commercial  
CY7C1360C-200AJXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
(2 Chip Enable)  
CY7C1362C-200AJXC  
CY7C1360C-200BGC  
CY7C1362C-200BGC  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1360C-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1362C-200BGXC  
CY7C1360C-200BZC  
CY7C1362C-200BZC  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1360C-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
CY7C1362C-200BZXC  
CY7C1360C-200AXI  
CY7C1362C-200AXI  
CY7C1360C-200AJXI  
CY7C1362C-200AJXI  
CY7C1360C-200BGI  
CY7C1362C-200BGI  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
(3 Chip Enable)  
Industrial  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
(2 Chip Enable)  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1360C-200BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1362C-200BGXI  
CY7C1360C-200BZI  
CY7C1362C-200BZI  
CY7C1360C-200BZXI  
CY7C1362C-200BZXI  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
Document #: 38-05540 Rev. *H  
Page 26 of 31  
CY7C1360C  
CY7C1362C  
Ordering Information (continued)  
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered.  
250  
CY7C1360C-250AXC  
CY7C1362C-250AXC  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
(3 Chip Enable)  
Commercial  
CY7C1360C-250AJXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
(2 Chip Enable)  
CY7C1362C-250AJXC  
CY7C1360C-250BGC  
CY7C1362C-250BGC  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1360C-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1362C-250BGXC  
CY7C1360C-250BZC  
CY7C1362C-250BZC  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
CY7C1360C-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
CY7C1362C-250BZXC  
CY7C1360C-250AXI  
CY7C1362C-250AXI  
CY7C1360C-250AJXI  
CY7C1362C-250AJXI  
CY7C1360C-250BGI  
CY7C1362C-250BGI  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
(3 Chip Enable)  
Industrial  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
(2 Chip Enable)  
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)  
CY7C1360C-250BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free  
CY7C1362C-250BGXI  
CY7C1360C-250BZI  
CY7C1362C-250BZI  
CY7C1360C-250BZXI  
CY7C1362C-250BZXI  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free  
Document #: 38-05540 Rev. *H  
Page 27 of 31  
CY7C1360C  
CY7C1362C  
Package Diagrams  
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)  
16.00 0.20  
14.00 0.10  
1.40 0.05  
100  
81  
80  
1
0.30 0.08  
0.65  
TYP.  
12° 1°  
(8X)  
SEE DETAIL  
A
30  
51  
31  
50  
0.20 MAX.  
1.60 MAX.  
R 0.08 MIN.  
0.20 MAX.  
0° MIN.  
SEATING PLANE  
STAND-OFF  
0.05 MIN.  
0.15 MAX.  
NOTE:  
1. JEDEC STD REF MS-026  
0.25  
GAUGE PLANE  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE  
R 0.08 MIN.  
0.20 MAX.  
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH  
3. DIMENSIONS IN MILLIMETERS  
0°-7°  
0.60 0.15  
0.20 MIN.  
51-85050-*B  
1.00 REF.  
DETAIL  
A
Document #: 38-05540 Rev. *H  
Page 28 of 31  
CY7C1360C  
CY7C1362C  
Package Diagrams (continued)  
119-Ball PBGA (14 x 22 x 2.4 mm) (51-85115)  
Ø0.05 M C  
Ø0.25 M C A B  
A1 CORNER  
Ø0.75 0.15(119X)  
Ø1.00(3X) REF.  
1
2
3
4
5
6
7
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
G
H
J
K
L
J
K
L
M
N
P
R
T
M
N
P
R
T
U
U
1.27  
0.70 REF.  
A
3.81  
12.00  
7.62  
B
14.00 0.20  
0.15(4X)  
30° TYP.  
51-85115-*B  
SEATING PLANE  
C
Document #: 38-05540 Rev. *H  
Page 29 of 31  
CY7C1360C  
CY7C1362C  
Package Diagrams (continued)  
165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)  
BOTTOM VIEW  
PIN 1 CORNER  
TOP VIEW  
Ø0.05 M C  
PIN 1 CORNER  
Ø0.25 M C A B  
-0.06  
Ø0.50
(165X)  
+0.14  
1
2
3
4
5
6
7
8
9
10  
11  
11 10  
9
8
7
6
5
4
3
2
1
A
A
B
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00  
5.00  
10.00  
13.00 0.10  
B
B
13.00 0.10  
0.15(4X)  
NOTES :  
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)  
PACKAGE WEIGHT : 0.475g  
JEDECREFERENCE: MO-216 / DESIGN 4.6C  
PACKAGE CODE : BB0AC  
SEATING PLANE  
C
51-85180-*A  
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM  
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05540 Rev. *H  
Page 30 of 31  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C1360C  
CY7C1362C  
Document History Page  
Document Title: CY7C1360C/CY7C1362C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM  
Document Number: 38-05540  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
241690  
278130  
See ECN  
See ECN  
RKF  
RKF  
New data sheet  
*A  
Changed Boundary Scan order to match the B rev of these devices  
Changed TQFP pkg to Lead-free TQFP in Ordering Information section  
Added comment of Lead-free BG and BZ packages availability  
*B  
*C  
248929  
323636  
See ECN  
See ECN  
VBL  
PCI  
Changed ISB1 and ISB3 from DC Characteristics table as follows:  
ISB1: 225 MHz -> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA  
ISB3: 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA  
Changed IDDZZ to 50 mA  
Added BG and BZ pkg lead-free part numbers to ordering info section  
Changed frequency of 225 MHz into 250 MHz  
Added t  
of 4.0 ns for 250 MHz  
CYC  
Changed Θ and Θ for TQFP Package from 25 and 9 °C/W to 29.41 and  
JA  
JC  
6.13 °C/W respectively  
Changed Θ and Θ for BGA Package from 25 and 6 °C/W to 34.1 and  
JA  
JC  
14.0 °C/W respectively  
Changed Θ and Θ for FBGA Package from 27 and 6 °C/W to 16.8 and  
JA  
JC  
3.0 °C/W respectively  
Modified address expansion as per JEDEC Standard  
Removed comment of Lead-free BG and BZ packages availability  
*D  
*E  
332879  
357258  
See ECN  
See ECN  
PCI  
PCI  
Unshaded 200 and 166 MHz speed bins in the AC/DC Table and Selection  
Guide  
Added Address Expansion pins in the Pin Definition Table  
Changed Device Width (23:18) for 119-BGA from 000000 to 101000  
Added separate row for 165 -FBGA Device Width (23:18)  
Modified V , V test conditions  
OL  
OH  
Updated Ordering Information Table  
Changed from Preliminary to Final  
Removed Shading on 250MHz Speed Bin in Selection Guide and AC/DC  
Table  
Changed I  
from 30 to 40 mA  
SB2  
Updated Ordering Information Table  
*F  
377095  
408298  
See ECN  
See ECN  
PCI  
Modified test condition in note# 16 from V  
< V to V  
V  
DDQ  
DD  
DDQ DD  
*G  
RXU  
Changed address of Cypress Semiconductor Corporation on Page# 1 from  
“3901 North First Street” to “198 Champion Court”  
Changed three-state to tri-state on page# 9 & page# 10  
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in  
the Electrical Characteristics Table  
Replaced Package Name column with Package Diagram in the Ordering  
Information table  
Updated Ordering Information Table  
*H  
501793  
See ECN  
VKN  
Added the Maximum Rating for Supply Voltage on V  
Relative to GND  
DDQ  
Changed t , t from 25 ns to 20 ns and t  
from 5 ns to 10 ns in TAP  
TH TL  
TDOV  
AC Switching Characteristics table.  
Updated the Ordering Information table.  
Document #: 38-05540 Rev. *H  
Page 31 of 31  

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