Cypress CY7C1354CV25 User Manual

CY7C1354CV25

CY7C1356CV25

9-Mbit (256K x 36/512K x 18)

Pipelined SRAM with NoBL™ Architecture

Functional Description^[1]

Features

• Pin-compatible with and functionally equivalent to

ZBT™

The CY7C1354CV25 and CY7C1356CV25 are 2.5V, 256K x

36 and 512K x 18 Synchronous pipelined burst SRAMs with

No Bus Latency™ (NoBL™) logic, respectively. They are

designed to support unlimited true back-to-back Read/Write

operations with no wait states. The CY7C1354CV25 and

CY7C1356CV25 are equipped with the advanced (NoBL) logic

required to enable consecutive Read/Write operations with

data being transferred on every clock cycle. This feature

dramatically improves the throughput of data in systems that

require frequent Write/Read transitions. The CY7C1354CV25

and CY7C1356CV25 are pin-compatible with and functionally

equivalent to ZBT devices.

• Supports 250-MHz bus operations with zero wait states

• Available speed grades are 250, 200, and 166 MHz

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

• Single 2.5V power supply (V

• Fast clock-to-output times

)

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which when deasserted suspends operation and extends the

previous clock cycle.

— 2.8 ns (for 250-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Available in lead-free 100-Pin TQFP package, lead-free

and non lead-free 119-Ball BGA package and 165-Ball

FBGA package

Write operations are controlled by the Byte Write Selects

(BW –BW

for CY7C1354CV25 and BW –BW

for

CY7C1356CV25) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst capability–linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Three synchronous Chip Enables (CE , CE , CE ) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Logic Block Diagram–CY7C1354CV25 (256K x 36)

ADDRESS

A0, A1, A

A1'

A0'

BURST

LOGIC

MODE

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

BWa

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

MEMORY

ARRAY

DQs

WRITE

DRIVERS

DQPa

DQPb

DQPc

DQPd

BWb

BWc

BWd

INPUT

READ LOGIC

CE1

CE2

CE3

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05537 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 14, 2006

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CY7C1354CV25

CY7C1356CV25

Pin Configurations

100-pin TQFP Pinout

DQPc

DQc

DDQ

DQPb

DQb

DDQ

DQPa

DQa

DDQ

DQc

DQb

DQc

DQb

DDQ

DQa

DDQ

DQc

DQb

CY7C1354CV25

(256K × 36)

CY7C1356CV25

(512K × 18)

DQa

DQd

DQb

DQa

DQd

DQb

DDQ

DQa

DDQ

DQd

DQa

DQb

DQa DQPb

DQa

DDQ

DQd

DQPd

DQa

DQPa

Document #: 38-05537 Rev. *H

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CY7C1354CV25

CY7C1356CV25

Pin Configurations (continued)

119-Ball BGA Pinout

CY7C1354CV25 (256K × 36)

NC/18M

DDQ

NC/576M

NC/1G

ADV/LD

DQP

DDQ

CLK

DDQ

CEN

DDQ

DQP

NC/144M

MODE

NC/288M

NC/72M

TMS

NC/36M

TDI

TCK

TDO

DDQ

CY7C1356CV25 (512K x 18)

NC/18M

DDQ

NC/576M

NC/1G

ADV/LD

DQP

DDQ

CLK

CEN

DDQ

DQP

NC/144M

NC/72M

MODE

NC/288M

NC/36M

TCK

TMS

TDI

TDO

DDQ

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CY7C1354CV25

CY7C1356CV25

Pin Configurations (continued)

165-Ball FBGA Pinout

CY7C1354CV25 (256K × 36)

NC/576M

NC/1G

DQP_c

ADV/LD

CE₁

BW_c

BW_d

V_SS

V_DD

BW_b

BW_a

V_SS

CEN

CE2

V_DDQ

V_SS

V_DD

NC/18M

V_DDQ

CLK

V_SS

DQ_c

V_SS

DQ_b

DQP_b

DQ_b

DQ_c

V_DDQ

V_DD

V_SS

V_DD

DQ_b

DQ_d

V_DDQ

DQ_a

V_DDQ

DQ_d

V_DDQ

V_DD

V_SS

V_DD

V_SS

DQ_a

DQP_a

DQP_d

NC/144M NC/72M

MODE NC/36M

TDI

TDO

NC/288M

TMS

TCK

CY7C1356CV25 (512K × 18)

NC/576M

NC/1G

CE₁

BW_b

CEN

ADV/LD

CE2

V_DDQ

BW_a

V_SS

CLK

V_SS

NC/18M

V_DDQ

V_SS

V_DD

V_SS

V_DD

DQP_a

DQ_a

DQ_b

V_DDQ

V_DD

V_SS

V_DD

DQ_a

DQ_b

V_DDQ

DQ_a

V_DDQ

DQ_b

V_DDQ

V_DD

V_SS

V_DD

V_SS

DQ_a

DQP_b

NC/144M NC/72M

MODE NC/36M

TDI

TDO

NC/288M

TMS

TCK

Document #: 38-05537 Rev. *H

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CY7C1354CV25

CY7C1356CV25

Pin Definitions

Pin Name

I/O Type

Pin Description

Input-

Synchronous

Address Inputs used to select one of the address locations. Sampled at the rising edge of

the CLK.

BW BW

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.

BW BW

Sampled on the rising edge of CLK. BW controls DQ and DQP , BW controls DQ and DQP ,

BW controls DQ and DQP , BW controls DQ and DQP .

Input-

Synchronous

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This

signal must be asserted LOW to initiate a write sequence.

ADV/LD

Input-

Synchronous

Advance/Load Input used to advance the on-chip address counter or load a new address.

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a

new address can be loaded into the device for an access. After being deselected, ADV/LD should

be driven LOW in order to load a new address.

CLK

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.

CLK is only recognized if CEN is active LOW.

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE and CE to select/deselect the device.

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

CE and CE to select/deselect the device.

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE and CE to select/deselect the device.

Input-

Output Enable, active LOW. Combined with the synchronous logic block inside the device to

Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.

When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during

the data portion of a Write sequence, during the first clock when emerging from a deselected state

and when the device has been deselected.

CEN

Input-

Synchronous

Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the

SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not

deselect the device, CEN can be used to extend the previous cycle when required.

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by addresses during the previous clock rise of the Read cycle. The direction of the pins

is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave

as outputs. When HIGH, DQ –DQ are placed in a tri-state condition. The outputs are automati-

cally tri-stated during the data portion of a write sequence, during the first clock when emerging

from a deselected state, and when the device is deselected, regardless of the state of OE.

DQP

I/O-

Synchronous

Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ

During

[a:d].

write sequences, DQP is controlled by BW , DQP is controlled by BW , DQP is controlled by

BW , and DQP is controlled by BW .

MODE

Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.

Pulled LOW selects the linear burst order. MODE should not change states during operation.

When left floating MODE will default HIGH, to an interleaved burst order.

TDO

TDI

JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

Synchronous

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.

Synchronous

TMS

TCK

Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.

Synchronous

JTAG-Clock

Clock input to the JTAG circuitry.

Power Supply Power supply inputs to the core of the device.

I/O Power Supply Power supply for the I/O circuitry.

DDQ

Ground

Ground for the device. Should be connected to ground of the system.

Document #: 38-05537 Rev. *H

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CY7C1354CV25

CY7C1356CV25

Pin Definitions (continued)

Pin Name

I/O Type

Pin Description

No connects. This pin is not connected to the die.

–

NC (18,

36, 72,

These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M

288M, 576M, and 1G densities.

144, 288,

576, 1G

Input-

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition

Asynchronous with data integrity preserved. For normal operation, this pin has to be LOW or left floating.

ZZ pin has an internal pull-down.

of the chip enable signals, its output will tri-state following the

next clock rise.

Functional Overview

The

CY7C1354CV25

and

CY7C1356CV25

are

Burst Read Accesses

synchronous-pipelined Burst NoBL SRAMs designed specifi-

cally to eliminate wait states during Write/Read transitions. All

synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock signal is qualified with

the Clock Enable input signal (CEN). If CEN is HIGH, the clock

signal is not recognized and all internal states are maintained.

All synchronous operations are qualified with CEN. All data

outputs pass through output registers controlled by the rising

edge of the clock. Maximum access delay from the clock rise

The CY7C1354CV25 and CY7C1356CV25 have an on-chip

burst counter that allows the user the ability to supply a single

address and conduct up to four Reads without reasserting the

address inputs. ADV/LD must be driven LOW in order to load

a new address into the SRAM, as described in the Single Read

Access section above. The sequence of the burst counter is

determined by the MODE input signal. A LOW input on MODE

selects a linear burst mode, a HIGH selects an interleaved

burst sequence. Both burst counters use A0 and A1 in the

burst sequence, and will wrap around when incremented suffi-

ciently. A HIGH input on ADV/LD will increment the internal

burst counter regardless of the state of chip enables inputs or

WE. WE is latched at the beginning of a burst cycle. Therefore,

the type of access (Read or Write) is maintained throughout

the burst sequence.

(t ) is 2.8 ns (250-MHz device).

Accesses can be initiated by asserting all three Chip Enables

(CE , CE , CE ) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,

the address presented to the device will be latched. The

access can either be a Read or Write operation, depending on

the status of the Write Enable (WE). BW

conduct Byte Write operations.

can be used to

[d:a]

Single Write Accesses

Write operations are qualified by the Write Enable (WE). All

Writes are simplified with on-chip synchronous self-timed

Write circuitry.

Write access are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,

and CE are ALL asserted active, and (3) the Write signal WE

Three synchronous Chip Enables (CE , CE , CE ) and an

is asserted LOW. The address presented to A ∠A is loaded

into the Address Register. The write signals are latched into

the Control Logic block.

asynchronous Output Enable (OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW once the device has been

deselected in order to load a new address for the next

operation.

On the subsequent clock rise the data lines are automatically

tri-stated regardless of the state of the OE input signal. This

allows the external logic to present the data on DQ and DQP

(DQ

/DQP

for CY7C1354CV25 and DQ /DQP

Single Read Accesses

a,b,c,d

a,b,c,d a,b a,b

for CY7C1356CV25). In addition, the address for the subse-

quent access (Read/Write/Deselect) is latched into the

address register (provided the appropriate control signals are

asserted).

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,

and CE are ALL asserted active, (3) the Write Enable input

signal WE is deasserted HIGH, and (4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the address register and presented to the memory core

and control logic. The control logic determines that a read

access is in progress and allows the requested data to

propagate to the input of the output register. At the rising edge

of the next clock the requested data is allowed to propagate

through the output register and onto the data bus within 2.8 ns

(250-MHz device) provided OE is active LOW. After the first

clock of the read access the output buffers are controlled by

OE and the internal control logic. OE must be driven LOW in

order for the device to drive out the requested data. During the

second clock, a subsequent operation (Read/Write/Deselect)

can be initiated. Deselecting the device is also pipelined.

Therefore, when the SRAM is deselected at clock rise by one

On the next clock rise the data presented to DQ

and DQP

(DQ

/DQP

for CY7C1354CV25 and DQ /DQP

a,b,c,d

a,b,c,d a,b a,b

for CY7C1356CV25) (or a subset for byte write operations,

see Write Cycle Description table for details) inputs is latched

into the device and the Write is complete.

The data written during the Write operation is controlled by BW

(BW

for

CY7C1354CV25

and

for

a,b,c,d

a,b

CY7C1356CV25) signals. The CY7C1354CV25/56CV25

provides Byte Write capability that is described in the Write

Cycle Description table. Asserting the Write Enable input (WE)

with the selected Byte Write Select (BW) input will selectively

write to only the desired bytes. Bytes not selected during a

Byte Write operation will remain unaltered. A synchronous

self-timed write mechanism has been provided to simplify the

Write operations. Byte Write capability has been included in

Document #: 38-05537 Rev. *H

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CY7C1354CV25

CY7C1356CV25

order to greatly simplify Read/Modify/Write sequences, which

can be reduced to simple Byte Write operations.

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

Because the CY7C1354CV25 and CY7C1356CV25 are

common I/O devices, data should not be driven into the device

while the outputs are active. The Output Enable (OE) can be

deasserted HIGH before presenting data to the DQ and DQP

the “sleep” mode. CE , CE , and CE must remain inactive for

the duration of t

after the ZZ input returns LOW.

ZZREC

(DQ

/DQP

for CY7C1354CV25 and DQ /DQP

a,b,c,d

a,b,c,d a,b a,b

for CY7C1356CV25) inputs. Doing so will tri-state the output

Interleaved Burst Address Table

(MODE = Floating or V_DD

drivers. As

(DQ /DQP

safety precaution, DQ

for CY7C1354CV25 and DQ /DQP

and DQP

)

a,b,c,d

a,b a,b

First

Second

Address

Third

Address

Fourth

Address

for CY7C1356CV25) are automatically tri-stated during the

data portion of a write cycle, regardless of the state of OE.

Address

A1,A0

Burst Write Accesses

The CY7C1354CV25/56CV25 has an on-chip burst counter

that allows the user the ability to supply a single address and

conduct up to four WRITE operations without reasserting the

address inputs. ADV/LD must be driven LOW in order to load

the initial address, as described in the Single Write Access

section above. When ADV/LD is driven HIGH on the subse-

quent clock rise, the chip enables (CE , CE , and CE ) and

Linear Burst Address Table (MODE = GND)

First

Address

Second

Address

Third

Address

Fourth

Address

WE inputs are ignored and the burst counter is incremented.

The correct BW (BW for CY7C1354CV25 and BW for

a,b,c,d

a,b

A1,A0

CY7C1356CV25) inputs must be driven in each cycle of the

burst write in order to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

ZZ Mode Electrical Characteristics

Parameter

Description

Sleep mode standby current

Device operation to ZZ

ZZ recovery time

Test Conditions

Min.

Max.

Unit

ZZ > V − 0.2V

DDZZ

ZZS

CYC

ZZ < 0.2V

ZZREC

ZZI

CYC

ZZ active to sleep current

This parameter is sampled

CYC

ZZ Inactive to exit sleep current

RZZI

Truth Table^{[2, 3, 4, 5, 6, 7, 8]}

Address

Used

Operation

Deselect Cycle

CE ZZ ADV/LD WE BWx

CEN CLK

None

L-H

Tri-State

Continue Deselect Cycle

Read Cycle (Begin Burst)

Read Cycle (Continue Burst)

NOP/Dummy Read (Begin Burst)

Dummy Read (Continue Burst)

Write Cycle (Begin Burst)

Write Cycle (Continue Burst)

External

L-H Data Out (Q)

External

L-H

Tri-State

External

Data In (D)

Notes:

2. X = “Don’t Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx =

Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.

3. Write is defined by WE and BW . See Write Cycle Description table for details.

4. When a write cycle is detected, all I/Os are tri-stated, even during Byte Writes.

5. The DQ and DQP pins are controlled by the current cycle and the OE signal.

6. CEN = H inserts wait states.

7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.

8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP = Tri-state when OE

is inactive or when the device is deselected, and DQs = data when OE is active.

Document #: 38-05537 Rev. *H

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CY7C1354CV25

CY7C1356CV25

Truth Table^{[2, 3, 4, 5, 6, 7, 8]}

Address

Used

Operation

CE ZZ ADV/LD WE BWx

CEN CLK

Tri-State

–

NOP/WRITE ABORT (Begin Burst)

WRITE ABORT (Continue Burst)

IGNORE CLOCK EDGE (Stall)

SLEEP MODE

None

L-H

Current

None

Tri-State

Partial Write Cycle Description^{[2, 3, 4, 9]}

Function (CY7C1354CV25)

Read

Write –No bytes written

Write Byte a– (DQ and DQP

Write Byte b – (DQ and DQP

Write Bytes b, a

Write Byte c – (DQ and DQP

Write Bytes c, a

Write Bytes c, b

Write Bytes c, b, a

Write Byte d – (DQ and DQP

Write Bytes d, a

Write Bytes d, b

Write Bytes d, b, a

Write Bytes d, c

Write Bytes d, c, a

Write Bytes d, c, b

Write All Bytes

Partial Write Cycle Description^{[2, 3, 4, 9]}

Function (CY7C1356CV25)

Read

Write – No Bytes Written

Write Byte a − (DQ and DQP

Write Byte b – (DQ and DQP

Write Both Bytes

Note:

9. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.

Document #: 38-05537 Rev. *H

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CY7C1354CV25

CY7C1356CV25

The ball is pulled up internally, resulting in a logic HIGH level.

IEEE 1149.1 Serial Boundary Scan (JTAG)

Test Data-In (TDI)

The CY7C1354CV25/CY7C1356CV25 incorporates a serial

boundary scan test access port (TAP) in the BGA package

only. The TQFP package does not offer this functionality. This

part operates in accordance with IEEE Standard 1149.1-1900,

but doesn’t have the set of functions required for full 1149.1

compliance. These functions from the IEEE specification are

excluded because their inclusion places an added delay in the

critical speed path of the SRAM. Note the TAP controller

functions in a manner that does not conflict with the operation

of other devices using 1149.1 fully compliant TAPs. The TAP

operates using JEDEC-standard 2.5V I/O logic levels.

The TDI ball is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. For

information on loading the instruction register, see TAP

Controller State Diagram. TDI is internally pulled up and can

be unconnected if the TAP is unused in an application. TDI is

connected to the most significant bit (MSB) of any register.

(See Tap Controller Block Diagram.)

Test Data-Out (TDO)

The CY7C1354CV25/CY7C1356CV25 contains

TAP

controller, instruction register, boundary scan register, bypass

The TDO output ball is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine. The output changes on the

falling edge of TCK. TDO is connected to the least significant

bit (LSB) of any register. (See Tap Controller State Diagram.)

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

TAP Controller Block Diagram

(V ) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to V through a pull-up resistor. TDO should be

left unconnected. Upon power-up, the device will come up in

a reset state which will not interfere with the operation of the

device.

Bypass Register

Selection

Circuitry

Instruction Register

31 30 29

Identification Register

Selection

Circuitry

TDI

TDO

TAP Controller State Diagram^[10]

TEST-LOGIC

RESET

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

Boundary Scan Register

CAPTURE-DR

CAPTURE-IR

TCK

TMS

TAP CONTROLLER

SHIFT-DR

SHIFT-IR

EXIT1-DR

EXIT1-IR

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (V ) for five

PAUSE-DR

PAUSE-IR

rising edges of TCK. This RESET does not affect the operation

of the SRAM and may be performed while the SRAM is

operating.

EXIT2-DR

EXIT2-IR

At power-up, the TAP is reset internally to ensure that TDO

comes up in a High-Z state.

UPDATE-DR

UPDATE-IR

TAP Registers

Registers are connected between the TDI and TDO balls and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction register. Data is serially loaded into the TDI ball

on the rising edge of TCK. Data is output on the TDO ball on

the falling edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.Test MODE SELECT (TMS)

Instruction Register

Three-bit instructions can be serially loaded into the instruction

TDI and TDO balls as shown in the Tap Controller Block

Diagram. Upon power-up, the instruction register is loaded

with the IDCODE instruction.

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this ball unconnected if the TAP is not used.

Note:

10. The 0/1 next to each state represents the value of TMS at the rising edge of the TCK.

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CY7C1354CV25

CY7C1356CV25

It is also loaded with the IDCODE instruction if the controller is

placed in a reset state as described in the previous section.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state. The SAMPLE Z command puts

the output bus into a High-Z state until the next command is

given during the “Update IR” state.

When the TAP controller is in the Capture-IR state, the two

least significant bits are loaded with a binary “01” pattern to

allow for fault isolation of the board-level serial test data path.

Bypass Register

SAMPLE/PRELOAD

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

TDI and TDO balls. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

(V ) when the BYPASS instruction is executed.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is

possible that during the Capture-DR state, an input or output

will undergo a transition. The TAP may then try to capture a

signal while in transition (metastable state). This will not harm

the device, but there is no guarantee as to the value that will

be captured. Repeatable results may not be possible.

Boundary Scan Register

The boundary scan register is connected to all the input and

bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the

RAM I/O ring when the TAP controller is in the Capture-DR

state and is then placed between the TDI and TDO balls when

the controller is moved to the Shift-DR state. The EXTEST,

SAMPLE/PRELOAD and SAMPLE Z instructions can be used

to capture the contents of the I/O ring.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture set-up plus

hold times (t and t ). The SRAM clock input might not be

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI, and the LSB is connected to TDO.

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK# captured in the

boundary scan register.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the

boundary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells

prior to the selection of another boundary scan test operation.

TAP Instruction Set

The shifting of data for the SAMPLE and PRELOAD phases

can occur concurrently when required—that is, while data

captured is shifted out, the preloaded data can be shifted in.

Overview

Eight different instructions are possible with the three bit

instruction register. All combinations are listed in the

Instruction Codes table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

BYPASS

When the BYPASS instruction is loaded in the instruction

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO balls.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

EXTEST

The EXTEST instruction enables the preloaded data to be

driven out through the system output pins. This instruction also

selects the boundary scan register to be connected for serial

access between the TDI and TDO in the shift-DR controller

state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO balls and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

The IDCODE instruction is loaded into the instruction register

upon power-up or whenever the TAP controller is given a test

logic reset state.

Document #: 38-05537 Rev. *H

Page 11 of 28

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CY7C1354CV25

CY7C1356CV25

TAP Timing

Test Clock

(TCK)

CYC

TMSS

TDIS

TMSH

Test Mode Select

(TMS)

TDIH

Test Data-In

(TDI)

TDOV

TDOX

Test Data-Out

(TDO)

DON’T CARE

UNDEFINED

[11, 12]

TAP AC Switching Characteristics Over the Operating Range

Parameter

Clock

Description

Min.

Max.

Unit

TCK Clock Cycle Time

TCK Clock Frequency

TCK Clock HIGH Time

TCK Clock LOW Time

MHz

TCYC

Output Times

TCK Clock LOW to TDO Valid

TCK Clock LOW to TDO Invalid

TDOV

TDOX

Set-up Times

TMS Set-up to TCK Clock Rise

TDI Set-up to TCK Clock Rise

Capture Set-up to TCK Rise

TMSS

TDIS

Hold Times

TMS Hold after TCK Clock Rise

TDI Hold after Clock Rise

TMSH

TDIH

Capture Hold after Clock Rise

Notes:

11. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.

12. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.

Document #: 38-05537 Rev. *H

Page 12 of 28

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CY7C1354CV25

CY7C1356CV25

2.5V TAP AC Test Conditions

2.5V TAP AC Output Load Equivalent

1.25V

Input pulse levels ............................................... V to 2.5V

Input rise and fall time .................................................... 1 ns

Input timing reference levels ........................................1.25V

Output reference levels ................................................1.25V

Test load termination supply voltage.............................1.25V

50Ω

TDO

Z_O= 50Ω

20pF

TAP DC Electrical Characteristics And Operating Conditions

[13]

(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)

Parameter

Description

Test Conditions

Min.

2.0

Max.

Unit

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Input Load Current

= –1.0 mA, V

= 2.5V

OH1

DDQ

= –100 µA,V

2.1

OH2

OL1

OL2

= 8.0 mA, V

= 100 µA

= 2.5V

0.4

0.2

DDQ

= 2.5V

DDQ

1.7

–0.3

–5

+ 0.3

0.7

GND < V < V

µA

DDQ

Identification Register Definitions

Instruction Field

Revision Number (31:29)

Cypress Device ID (28:12)

Cypress JEDEC ID (11:1)

ID Register Presence (0)

CY7C1354CV25

000

CY7C1356CV25

Description

000

Reserved for version number.

01011001000100110 01011001000010110 Reserved for future use.

00000110100

Allows unique identification of SRAM vendor.

Indicate the presence of an ID register.

Scan Register Sizes

Bit Size (x36)

Bit Size (x18)

Instruction

Bypass

Boundary Scan Order (119-ball BGA

package)

Boundary Scan Order (165-ball FBGA

package)

Identification Codes

Instruction

EXTEST

Code

Description

000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and

TDO. Forces all SRAM outputs to High-Z state.

IDCODE

001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This

operation does not affect SRAM operation.

SAMPLE Z

010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scanregister between TDI and TDO.

Does not affect the SRAM operation.

RESERVED

101 Do Not Use: This instruction is reserved for future use.

110

111

Do Not Use: This instruction is reserved for future use.

BYPASS

Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.

Note:

13. All voltages referenced to V (GND).

Document #: 38-05537 Rev. *H

Page 13 of 28

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CY7C1354CV25

CY7C1356CV25

Boundary Scan Exit Order (256K × 36) (continued)

Boundary Scan Exit Order (256K × 36)

Bit #

119-ball ID

165-ball ID

Bit #

119-ball ID

165-ball ID

Not Bonded

(Preset to 1)

Not Bonded

(Preset to 1)

B10

A10

C11

E10

F10

G10

D10

D11

E11

F11

G11

H11

J10

K10

L10

M10

J11

K11

L11

M11

N11

R11

R10

P10

Document #: 38-05537 Rev. *H

Page 14 of 28

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CY7C1354CV25

CY7C1356CV25

Boundary Scan Exit Order (512K × 18) (continued)

Boundary Scan Exit Order (512K × 18)

Bit #

119-ball ID

165-ball ID

Bit #

119-ball ID

165-ball ID

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

B10

A10

A11

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 1)

Not Bonded

(Preset to 1)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

C11

D11

E11

F11

G11

H11

J10

K10

L10

M10

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

R11

R10

P10

Not Bonded

(Preset to 0

Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0

Document #: 38-05537 Rev. *H

Page 15 of 28

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CY7C1354CV25

CY7C1356CV25

Maximum Ratings

Current into Outputs (LOW)......................................... 20 mA

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Storage Temperature .................................–65°C to +150°C

Latch-up Current.................................................... > 200 mA

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Operating Range

Supply Voltage on V Relative to GND........ –0.5V to +3.6V

Range

Commercial

Industrial

Ambient Temperature

0°C to +70°C

DD DDQ

Supply Voltage on V

Relative to GND ......–0.5V to +V

DDQ

2.5V ±5%

DC to Outputs in Tri-State................... –0.5V to V

+ 0.5V

DDQ

–40°C to +85°C

DC Input Voltage....................................–0.5V to V + 0.5V

[14, 15]

Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

Min.

2.375

2.0

Max.

2.625

Unit

Power Supply Voltage

I/O Supply Voltage

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

DDQ

for 2.5V I/O

for 2.5V I/O, I = −1.0 mA

for 2.5V I/O, I = 1.0 mA

0.4

for 2.5V I/O

1.7

–0.3

–5

+ 0.3V

0.7

[14]

Input LOW Voltage

Input Leakage Current GND ≤ V ≤ V

except ZZ and MODE

µA

DDQ

Input Current of MODE Input = V

–30

–5

µA

Input = V

Input Current of ZZ

Input = V

µA

Output Leakage Current GND ≤ V ≤ V

Output Disabled

–5

µA

DDQ,

Operating Supply

f = f

= Max., I

= 0 mA,

4-ns cycle, 250 MHz

250

220

180

130

120

110

OUT

= 1/t

CYC

MAX

5-ns cycle, 200 MHz

6-ns cycle, 166 MHz

Automatic CE

Power-down

Current—TTL Inputs

Max. V , Device Deselected, 4-ns cycle, 250 MHz

SB1

≥ V or V ≤ V , f = f

MAX

5-ns cycle, 200 MHz

6-ns cycle, 166 MHz

1/t

CYC

Automatic CE

Power-down

Current—CMOS Inputs f = 0

Max. V , Device Deselected, All speed grades

SB2

≤ 0.3V or V > V

− 0.3V,

DDQ

Automatic CE

Power-down

Current—CMOS Inputs f = f

Max. V , Device Deselected, 4-ns cycle, 250 MHz

120

110

100

SB3

≤ 0.3V or V > V

− 0.3V,

DDQ

5-ns cycle, 200 MHz

6-ns cycle, 166 MHz

= 1/t

MAX

CYC

Automatic CE

Max. V , Device Deselected, All speed grades

SB4

Power-down

Current—TTL Inputs

≥ V or V ≤ V , f = 0

Notes:

14. Overshoot: V (AC) < V +1.5V (Pulse width less than t

/2), undershoot: V (AC)> –2V (Pulse width less than t /2).

CYC

15. T

: Assumes a linear ramp from 0V to V

(min.) within 200 ms. During this time V < V and V

< V

Power-up

DDQ

Document #: 38-05537 Rev. *H

Page 16 of 28

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CY7C1354CV25

CY7C1356CV25

Capacitance^[16]

100 TQFP

Max.

119 BGA

Max.

165 FBGA

Parameter

Description

Test Conditions

T = 25°C, f = 1 MHz,

Max.

Unit

Input Capacitance

= 2.5V, V

= 2.5V

DDQ

Clock Input Capacitance

Input/Output Capacitance

CLK

I/O

Thermal Resistance^[16]

100 TQFP

Package

119 BGA

Package

165 FBGA

Package

Parameters

Description

Test Conditions

Unit

Thermal Resistance Test conditions follow standard

29.41

34.1

16.8

°C/W

(Junction to

Ambient)

test methods and procedures

for measuring thermal

impedance, per EIA/JESD51.

Thermal Resistance

(Junction to Case)

6.13

3.0

°C/W

AC Test Loads and Waveforms

2.5V I/O Test Load

R = 1667Ω

2.5V

OUTPUT

ALL INPUT PULSES

90%

V_DDQ

OUTPUT

90%

10%

Z = 50Ω

R = 50Ω

10%

GND

5 pF

INCLUDING

R = 1538Ω

≤ 1 ns

V_T= 1.25V

JIG AND

SCOPE

(a)

(b)

(c)

Note:

16. Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05537 Rev. *H

Page 17 of 28

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CY7C1354CV25

CY7C1356CV25

[18, 19]

Switching Characteristics Over the Operating Range

–250

Max.

–200

Max.

–166

Parameter

Description

(typical) to the First Access Read or Write

Min.

Max.

Unit

[17]

Power

Clock

Clock Cycle Time

Maximum Operating Frequency

Clock HIGH

4.0

MHz

CYC

250

200

166

MAX

1.8

2.0

2.4

Clock LOW

Output Times

Data Output Valid after CLK Rise

OE LOW to Output Valid

2.8

3.2

3.5

EOV

DOH

CHZ

CLZ

Data Output Hold after CLK Rise

1.25

1.5

[20, 21, 22]

Clock to High-Z

2.8

3.2

3.5

[20, 21, 22]

Clock to Low-Z

[20, 21, 22]

OE HIGH to Output High-Z

EOHZ

EOLZ

[20, 21, 22]

OE LOW to Output Low-Z

Set-up Times

Address Set-up before CLK Rise

Data Input Set-up before CLK Rise

CEN Set-up before CLK Rise

1.4

1.5

CENS

WES

ALS

CES

WE, BW Set-up before CLK Rise

ADV/LD Set-up before CLK Rise

Chip Select Set-up

Hold Times

Address Hold after CLK Rise

Data Input Hold after CLK Rise

CEN Hold after CLK Rise

0.4

0.5

CENH

WEH

ALH

CEH

WE, BW Hold after CLK Rise

ADV/LD Hold after CLK Rise

Chip Select Hold after CLK Rise

Notes:

17. This part has a voltage regulator internally; t

is the time power needs to be supplied above V minimum initially, before a Read or Write operation can be

power

initiated.

18. Timing reference level is when V

= 2.5V.

DDQ

19. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

20. t , t , t , and t are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

CHZ CLZ EOLZ

EOHZ

21. At any given voltage and temperature, t

is less than t

and t

is less than t

to eliminate bus contention between SRAMs when sharing the same

CLZ

EOHZ

EOLZ

CHZ

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

22. This parameter is sampled and not 100% tested.

Document #: 38-05537 Rev. *H

Page 18 of 28

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CY7C1354CV25

CY7C1356CV25

Switching Waveforms

[23, 24, 25]

Read/Write Timing

CYC

CLK

CENS CENH

CEN

CES

CEH

ADV/LD

BWX

ADDRESS

DOH

OEV

CLZ

CHZ

Data

D(A1)

D(A2)

D(A2+1)

Q(A3)

Q(A4)

Q(A4+1)

D(A5)

Q(A6

-Out (DQ)

OEHZ

DOH

OELZ

WRITE

D(A1)

WRITE

D(A2)

BURST

WRITE

READ

Q(A3)

READ

Q(A4)

BURST

READ

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

D(A2+1)

Q(A4+1)

DON’T CARE

UNDEFINED

Notes:

23. For this waveform ZZ is tied LOW.

24. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH,CE is HIGH or CE is LOW or CE is HIGH.

25. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

Document #: 38-05537 Rev. *H

Page 19 of 28

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CY7C1354CV25

CY7C1356CV25

Switching Waveforms (continued)

[23, 24, 26]

NOP, STALL and DESELECT CYCLES

CLK

CEN

ADV/LD

BWX

ADDRESS

CHZ

D(A4)

D(A1)

Q(A2)

Q(A3)

Q(A5)

Data

In-Out (DQ)

WRITE

D(A1)

READ

Q(A2)

STALL

READ

Q(A3)

WRITE

D(A4)

STALL

NOP

READ

Q(A5)

DESELECT

CONTINUE

DESELECT

DON’T CARE

UNDEFINED

Note:

26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.

Document #: 38-05537 Rev. *H

Page 20 of 28

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CY7C1354CV25

CY7C1356CV25

Switching Waveforms (continued)

[27, 28]

ZZ Mode Timing

CLK

ZZREC

ZZI

SUPPLY

DDZZ

RZZI

ALL INPUTS

(except ZZ)

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

Notes:

27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.

28. I/Os are in High-Z when exiting ZZ sleep mode.

Document #: 38-05537 Rev. *H

Page 21 of 28

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CY7C1354CV25

CY7C1356CV25

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz)

Package

Diagram

Operating

Range

Ordering Code

Part and Package Type

166 CY7C1354CV25-166AXC

CY7C1356CV25-166AXC

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

CY7C1354CV25-166BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1356CV25-166BGC

CY7C1354CV25-166BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1356CV25-166BGXC

CY7C1354CV25-166BZC

CY7C1356CV25-166BZC

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1354CV25-166BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1356CV25-166BZXC

CY7C1354CV25-166AXI

CY7C1356CV25-166AXI

CY7C1354CV25-166BGI

CY7C1356CV25-166BGI

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1354CV25-166BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1356CV25-166BGXI

CY7C1354CV25-166BZI

CY7C1356CV25-166BZI

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1354CV25-166BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1356CV25-166BZXI

Document #: 38-05537 Rev. *H

Page 22 of 28

[+] Feedback

CY7C1354CV25

CY7C1356CV25

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

200 CY7C1354CV25-200AXC

CY7C1356CV25-200AXC

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

CY7C1354CV25-200BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1356CV25-200BGC

CY7C1354CV25-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1356CV25-200BGXC

CY7C1354CV25-200BZC

CY7C1356CV25-200BZC

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1354CV25-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1356CV25-200BZXC

CY7C1354CV25-200AXI

CY7C1356CV25-200AXI

CY7C1354CV25-200BGI

CY7C1356CV25-200BGI

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1354CV25-200BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1356CV25-200BGXI

CY7C1354CV25-200BZI

CY7C1356CV25-200BZI

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1354CV25-200BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1356CV25-200BZXI

Document #: 38-05537 Rev. *H

Page 23 of 28

[+] Feedback

CY7C1354CV25

CY7C1356CV25

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

250 CY7C1354CV25-250AXC

CY7C1356CV25-250AXC

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

CY7C1354CV25-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1356CV25-250BGC

CY7C1354CV25-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1356CV25-250BGXC

CY7C1354CV25-250BZC

CY7C1356CV25-250BZC

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1354CV25-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1356CV25-250BZXC

CY7C1354CV25-250AXI

CY7C1356CV25-250AXI

CY7C1354CV25-250BGI

CY7C1356CV25-250BGI

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1354CV25-250BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1356CV25-250BGXI

CY7C1354CV25-250BZI

CY7C1356CV25-250BZI

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1354CV25-250BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

CY7C1356CV25-250BZXI

Document #: 38-05537 Rev. *H

Page 24 of 28

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CY7C1354CV25

CY7C1356CV25

Package Diagrams

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)

16.00 0.20

14.00 0.10

1.40 0.05

100

0.30 0.08

0.65

TYP.

12° 1°

(8X)

SEE DETAIL

0.20 MAX.

1.60 MAX.

R 0.08 MIN.

0.20 MAX.

0° MIN.

SEATING PLANE

STAND-OFF

0.05 MIN.

0.15 MAX.

NOTE:

1. JEDEC STD REF MS-026

0.25

GAUGE PLANE

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

R 0.08 MIN.

0.20 MAX.

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

0°-7°

0.60 0.15

0.20 MIN.

51-85050-*B

1.00 REF.

DETAIL

Document #: 38-05537 Rev. *H

Page 25 of 28

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CY7C1354CV25

CY7C1356CV25

Package Diagrams (continued)

119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)

Ø0.05 M C

Ø0.25 M C A B

A1 CORNER

Ø0.75 0.15(119X)

Ø1.00(3X) REF.

1.27

0.70 REF.

3.81

12.00

7.62

14.00 0.20

0.15(4X)

30° TYP.

51-85115-*B

SEATING PLANE

Document #: 38-05537 Rev. *H

Page 26 of 28

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CY7C1354CV25

CY7C1356CV25

Package Diagrams (continued)

165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)

BOTTOM VIEW

PIN 1 CORNER

TOP VIEW

Ø0.05 M C

Ø0.25 M C A B

-0.06

PIN 1 CORNER

Ø0.50

(165X)

+0.14

11 10

1.00

5.00

10.00

13.00 0.10

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

SEATING PLANE

51-85180-*A

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device

Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders

Document #: 38-05537 Rev. *H

Page 27 of 28

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C1354CV25

CY7C1356CV25

Document History Page

Document Title: CY7C1354CV25/CY7C1356CV25 9-Mbit (256K x 36/512K x 18)

Pipelined SRAM with NoBL™ Architecture

Document Number: 38-05537

Orig. of

REV.

ECN No. Issue Date Change

Description of Change

242032

278969

284929

See ECN

RKF

New data sheet

Changed Boundary Scan order to match the B Rev of these devices

RKF

VBL

Included DC Characteristics Table

Changed ISB1 and ISB3 from DC Characteristic table as follows:

ISB1: 225 MHz -> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA

ISB3: 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA

Changed IDDZZ to 50mA.

Added BG and BZ pkg lead-free part numbers to ordering info section.

323636

See ECN

PCI

Changed frequency of 225 MHz into 250 MHz

Added t

of 4.0 ns for 250 MHz

CYC

Changed Θ and Θ for TQFP Package from 25 and 9 °C/W to 29.41 and

6.13 °C/W respectively

Changed Θ and Θ for BGA Package from 25 and 6 °C/W to 34.1 and

14.0 °C/W respectively

Changed Θ and Θ for FBGA Package from 27 and 6 °C/W to 16.8 and

3.0 °C/W respectively

Modified address expansion as per JEDEC Standard

Removed comment of Lead-free BG and BZ packages availability

332879

357258

See ECN

PCI

Unshaded 200 and 166 MHz speed bin in the AC/DC Table and Selection

Guide

Added Address Expansion pins in the Pin Definition Table

Removed description of Extest Output Bus Tri-state on page # 11

Modified V , V test conditions

Updated Ordering Information Table

Changed from Preliminary to Final

Changed I

from 35 to 40 mA

SB2

Removed Shading on 250MHz Speed Bin in Selection Guide and AC/DC

Table

Updated Ordering Information Table

377095

408298

See ECN

PCI

Modified test condition in note# 15 from V

< V to V

≤ V

DDQ

DDQ DD

RXU

Changed address of Cypress Semiconductor Corporation on Page# 1 from

“3901 North First Street” to “198 Champion Court”

Changed three-state to tri-state.

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in

the Electrical Characteristics Table.

Replaced Package Name column with Package Diagram in the Ordering

Information table.

Updated the Ordering Information Table.

501793

See ECN

VKN

Added the Maximum Rating for Supply Voltage on V

Relative to GND

DDQ

Changed t , t from 25 ns to 20 ns and t

from 5 ns to 10 ns in TAP

TH TL

TDOV

AC Switching Characteristics table.

Updated the Ordering Information table.

Document #: 38-05537 Rev. *H

Page 28 of 28

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