CY7C1330AV25
CY7C1332AV25
PRELIMINARY
18-Mbit (512K x 36/1Mbit x 18)
Pipelined Register-Register Late Write
Functional Description
Features
• Fast clock speed: 250, 200 MHz
• Fast access time: 2.0, 2.25 ns
The CY7C1330AV25 and CY7C1332AV25 are high perfor-
mance, Synchronous Pipelined SRAMs designed with late
write operation. These SRAMs can achieve speeds up to 250
• Synchronous Pipelined Operation with Self-timed Late
Write
MHz. Each memory cell consists of six transistors.
Late write feature avoids an idle cycle required during the
turnaround of the bus from a read to a write.
• Internally synchronized registered outputs eliminate
the need to control OE
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (K). The synchronous
• 2.5V core supply voltage
inputs include all addresses (A), all data inputs (DQ
), Chip
• 1.4–1.9V V
supply with V
of 0.68–0.95V
[a:d]
DDQ
REF
Enable (CE), Byte Write Selects (BWS
), and read-write
[a:d]
— Wide range HSTL I/O Levels
control (WE). Read or Write Operations can be initiated with
the chip enable pin (CE). This signal allows the user to
select/deselect the device when desired.
• Single Differential HSTL clock Input K and K
• Single WE (READ/WRITE) control pin
Power down feature is accomplished by pulling the
Synchronous signal ZZ HIGH.
• Individual byte write (BWS
LOW)
) control (may be tied
[a:d]
Output Enable (OE) is an asynchronous input signal. OE can
be used to disable the outputs at any given time.
• Common I/O
• Asynchronous Output Enable Input
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
• Programmable Impedance Output Drivers
• JTAG boundary scan for BGA packaging version
• Available in a 119-ball BGA package (CY7C1330AV25
and CY7C1332AV25)
Configuration
CY7C1330AV25 – 512K x 36
CY7C1332AV25 – 1M x 18
Logic Block Diagram
Clock
Buffer
K,K
D
CE
Data-In REG.
(2stage)
Q
Ax
512Kx36
1Mx18
CONTROL
and WRITE
LOGIC
CE
DQx
MEMORY
ARRAY
WE
BWSx
ZZ
OE
DQ
A
BWS
X
X
X
X = 18:0
512Kx36
1Mx18
X = a, b, c, d X = a, b, c, d
X = 19:0
X = a, b
X = a, b
Cypress Semiconductor Corporation
Document No: 001-07844 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 20, 2006
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
Pin Definitions
Name
I/O Type
Description
A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the K.
BWS
BWS
BWS
BWS
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
a
b
c
d
SRAM. Sampled on the rising edge of CLK. BWS controls DQ , BWS controls DQ ,
a
a
b
b
BWS controls DQ , BWS controls DQ .
c
c
d
d
WE
K,K
CE
OE
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to initiate a write sequence and high to initiate a read sequence.
Input-
Differential Clock
Clock Inputs. Used to capture all synchronous inputs to the device.
Input-
Synchronous
Chip Enable Input, active LOW. Sampled on the rising edge of CLK. Used to
select/deselect the device.
Input-
Asynchronous
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input
data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state and when the device has been
deselected.
DQ
DQ
DQ
DQ
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
a
b
c
d
memory location specified by A
during the previous clock rise of the read cycle. The
[x:0]
direction of the pins is controlled by OE and the internal control logic. When OE is
asserted LOW, the pins can behave as outputs. When HIGH, DQ –DQ are placed in
a
d
a tri-state condition. The outputs are automatically tri-stated during the data portion of
a write sequence, during the first clock when emerging from a deselected state, and
when the device is deselected, regardless of the state of OE. DQ a,b,c,d are 9 bits wide
M
M
Read Protocol Mode Mode control pins, used to set the proper read protocol. For specified device
1,
2
Pins
operation, M must be connected to V , and M must be connected to V or V
.
1
SS
2
DD
DDQ
These mode pins must be set at power-up and cannot be changed during device
operation.
ZZ
Input-
Asynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to
the system data bus impedance. Q
output impedance are set to 0.2 x RQ, where
[x:0]
RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to V , which enables the minimum impedance mode. This pin
DDQ
cannot be connected directly to GND or left unconnected.
V
V
V
Power Supply
Power supply inputs to the core of the device. For this device, the V is 2.5V.
DD
DD
I/O Power Supply
Power supply for the I/O circuitry. For this device, the V
is 1.5V.
DDQ
REF
DDQ
Input-
Reference Voltage
Reference Voltage Input. Static input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.
V
Ground
Ground for the device. Should be connected to ground of the system.
SS
TDO
JTAG serial output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
TDI
JTAG serial input
Synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
TMS
Test Mode Select
Synchronous
This pin controls the Test Access Port state machine. Sampled on the rising edge
of TCK.
TCK
NC
JTAG serial clock
–
Serial clock to the JTAG circuit.
No connects.
Document No: 001-07844 Rev. *A
Page 3 of 19
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
A is loaded into the Address Register. The write signals are
latched into the Control Logic block.
Introduction
x
Functional Overview
The data lines are automatically tri-stated regardless of the
state of the OE input signal when a write is detected. This
allows the external logic to present the data on DQ and DQP
The CY7C1330AV25 and CY7C1332AV25 are synchronous-
pipelined Late Write SRAMs running at speeds up to 250 MHz.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
(DQ
for CY7C1332AV25 and DQ
for CY7C1330AV25).
[a:b]
[a:d]
In addition, the address for the subsequent access
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).
Maximum access delay from the clock rise (t ) is 2.0 ns
CO
(250-MHz device).
On the next clock rise the data presented to DQ (or a subset
for byte write operations, see Write Cycle Description table for
details) inputs is latched into the device and the write is
complete.
Accesses can be initiated by asserting Chip Enable (CE) on
the rising edge of the clock. The address presented to the
device will be latched on this edge of the clock. The access
can either be a read or write operation, depending on the
status of the Write Enable (WE). BWS
conduct individual byte write operations.
The data written during the Write operation is controlled by
can be used to
[d:a]
BWS (BWS
for CY7C1330AV25 and BWS
for
[a:d]
[a:b]
CY7C1332AV25) signals. The CY7C1330AV25 and
CY7C1332AV25 provide byte write capability that is described
in the Write Cycle Description table. Asserting the Write
Enable input (WE) with the selected Byte Write Select (BWS)
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
Synchronous self-timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write opera-
tions.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed late
write circuitry.
All operations (Reads, Writes, and Deselects) are pipelined.
Pipelined Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) Chip Enable (CE) is asserted active
and (2) the Write Enable input signal (WE) is asserted HIGH.
The address presented to the address inputs is latched into
the Address Register and presented to the memory core and
control logic. The control logic determines that a read access
is in progress and allows the requested data to propagate to
the input of the output register. At the rising edge of the next
clock the requested data is allowed to propagate through the
output register and onto the data bus within 2.0 ns (250-MHz
device) provided OE is active LOW. After the first clock of the
read access the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
device to drive out the requested data. During the second
clock, a subsequent operation (Read/Write/Deselect) can be
initiated. Deselecting the device is also pipelined. Therefore,
when the SRAM is deselected at clock rise by one of the chip
enable signals, its output will tri-state following the next clock
rise.
Because the CY7C1330AV25/CY7C1332AV25 is a common
I/O device, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQ inputs. Doing so will
tri-state the output drivers. As a safety precaution, DQ is
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Power-up/Power-down Supply Voltage Sequencing
The power-up and power-down supply voltage application
recommendations are as follows:
Power-up: V , V , V
, V , V .
SS
DD
DDQ
REF IN
Power-down: V , V , V
, V , V
.
IN
REF DDQ
DD
SS
V
can be applied/removed simultaneously with V
as
DD
DDQ
long as V
does not exceed V by more than 0.5V.
DDQ
DD
Bypass Read Operation
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
Bypass read operation occurs when the last write operation is
followed by a read operation where write and read addresses
are identical. The data outputs are provided from the data in
registers rather than the memory array. This operation occurs
on a byte to byte basis. If only one byte is written during a write
operation and a read operation is performed on the same
address; then a partial bypass read operation is performed
since the new byte data will be from the datain registers while
the remaining bytes are from the memory array.
pin on the SRAM and V to allow the SRAM to adjust its
SS
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±10% is between 175Ω and 350Ω, with
V
=1.5V. The output impedance is adjusted every 1024
DDQ
cycles to adjust for drifts in supply voltage and temper-
ature.The output buffers can also be programmed in a
Late Write Accesses
minimum impedance configuration by connecting ZQ to V
.
DD
The Late Write feature allows for the write data to be presented
one cycle later after the access is started. This feature elimi-
nates one bus-turnaround cycle which is necessary when
going from a read to a write in an ordinary pipelined
Synchronous Burst SRAM.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
Write access is initiated when the following conditions are
satisfied at clock rise: (1) CE is asserted active and (2) the
write signal WE is asserted LOW. The address presented to
Document No: 001-07844 Rev. *A
Page 4 of 19
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE must remain inactive for the duration of
after the ZZ input returns LOW.
t
ZZREC
Cycle Description Truth Table[1, 2, 3, 4, 5]
Operation Address Used CE WE BWS CLK ZZ
Comments
x
Deselected External
Begin Read External
Begin Write External
1
0
0
X
1
0
X
X
L-H
L-H
0
0
0
I/Os tri-state following next recognized clock.
Address latched. Data driven out on the next rising edge of the clock.
Valid L-H
Address latched, data presented to the SRAM on the next rising
edge of the clock.
Sleep Mode
-
X
X
X
X
1
Power down mode.
ZZ Mode Electrical Characteristics
Parameter
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min.
Max.
Unit
mA
ns
I
t
t
ZZ > V
128
DDZZ
IH
IH
IL
ZZ > V
ZZ < V
2t
CYC
ZZS
2t
ns
ZZREC
CYC
Write Cycle Descriptions[1, 2]
Function (CY7C1330AV25)
WE
1
BW
BW
X
1
BW
X
1
BW
a
d
c
b
Read
X
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Write Byte 0 – DQ
Write Byte 1 – DQ
Write Bytes 1, 0
Write Byte 2 – DQ
Write Bytes 2, 0
Write Bytes 2, 1
0
a
0
1
0
b
0
1
0
0
0
1
c
0
0
1
0
0
0
Write Bytes 2, 1, 0
0
0
0
Write Byte 3 – DQ
Write Bytes 3, 0
Write Bytes 3, 1
0
1
1
d
0
1
1
0
1
0
Write Bytes 3, 1, 0
Write Bytes 3, 2
0
1
0
0
0
1
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
0
0
1
0
0
0
0
0
0
Abort Write All Bytes
0
1
1
Write Cycle Descriptions[1, 2]
Function (CY7C1332AV25)
WE
BW
X
BW
a
b
Read
1
0
0
0
0
X
0
1
0
1
Write Byte 0 – DQ
Write Byte 1 – DQ
Write All Bytes
1
a
0
b
0
Abort Write All Bytes
1
Notes:
1. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW. BWS = 0 signifies at least one Byte Write Select is active, BWS = Valid signifies that the desired byte write
x
x
selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWS . See Write Cycle Description table for details.
x
3. The DQ pins are controlled by the current cycle and the OE signal.
4. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
5. OE assumed LOW.
Document No: 001-07844 Rev. *A
Page 5 of 19
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
Instruction Register
IEEE 1149.1 Serial Boundary Scan (JTAG)
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This port operates in accor-
dance with IEEE Standard 1149.1-1900 but does not have the
set of functions required for full 1149.1 compliance. The TAP
operates using JEDEC standard 1.8V I/O logic levels.
Disabling the JTAG Feature
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V ) to prevent clocking of the device. TDI and TMS are inter-
SS
nally pulled up and may be unconnected. They may alternately
Bypass Register
be connected to V
through a pull-up resistor. TDO should
DD
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Test Access Port—Test Clock
(V ) when the BYPASS instruction is executed.
SS
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
Test Data-Out (TDO)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
TAP Registers
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Document No: 001-07844 Rev. *A
Page 6 of 19
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
EXTEST
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
hold times (t and t ). The SRAM clock input might not be
CS
CH
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
Document No: 001-07844 Rev. *A
Page 7 of 19
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
TAP Controller State Diagram[6]
TEST-LOGIC
1
RESET
0
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
6. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document No: 001-07844 Rev. *A
Page 8 of 19
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
TDI
Selection
Circuitry
2
1
0
0
0
TDO
Circuitry
Instruction Register
29
31 30
.
.
2
1
Identification Register
.
106 .
.
.
2
1
Boundary Scan Register
TCK
TMS
TAP Controller
[7, 8, 9]
TAP Electrical Characteristics Over the Operating Range
Parameter
Description
Output HIGH Voltage
Test Conditions
= −2.0 mA
= −100 µA
= 2.0 mA
Min.
1.7
Max.
Unit
V
V
V
V
V
V
V
I
I
I
I
I
OH1
OH2
OL1
OL2
IH
OH
OH
OL
OL
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
2.1
V
0.7
0.2
V
= 100 µA
V
1.7
–0.3
–5
V
+ 0.3
V
DD
Input LOW Voltage
0.7
5
V
IL
Input and Output Load Current
GND ≤ V ≤ V
µA
X
I
DD
[10, 11]
TAP AC Switching Characteristics Over the Operating Range
Parameter
Description
Min.
Max.
Unit
ns
t
t
t
t
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
50
TCYC
20
MHz
ns
TF
TH
TL
20
20
TCK Clock LOW
ns
Set-up Times
t
t
t
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
5
5
5
ns
ns
ns
TMSS
TDIS
CS
Hold Times
t
t
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
ns
ns
TMSH
TDIH
Notes:
7. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
8. Input waveform should have a slew rate of > 1 V/ns.
9. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
10. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
11. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document No: 001-07844 Rev. *A
Page 9 of 19
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
[10, 11]
TAP AC Switching Characteristics Over the Operating Range (continued)
Parameter
Description
Min.
Max.
Unit
t
Capture Hold after Clock Rise
5
ns
CH
Output Times
t
t
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
TDOV
TDOX
0
TAP Timing and Test Conditions[11]
1.25V
ALL INPUT PULSES
1.25V
2.5V
50Ω
0V
TDO
Z = 50Ω
0
C = 20 pF
L
GND
t
t
TL
TH
(a)
Test Clock
TCK
t
TCYC
t
TMSS
t
TMSH
Test Mode Select
TMS
t
TDIS
t
TDIH
Test Data-In
TDI
Test Data-Out
TDO
t
TDOV
t
TDOX
Identification Register Definitions
Value
CY7C1330AV25
000
Instruction Field
Revision Number (31:29)
Cypress Device ID (28:12)
CY7C1332AV25
Description
000
Version number.
01011110101100101 01011110101010101 Defines the type of SRAM.
Cypress JEDEC ID (11:1)
ID Register Presence (0)
00000110100
1
00000110100
1
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Document No: 001-07844 Rev. *A
Page 10 of 19
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
Scan Register Sizes
Register Name
Instruction
Bit Size—CY7C1330AV25
Bit Size—CY7C1332AV25
3
1
3
1
Bypass
ID
32
70
32
51
Boundary Scan
Instruction Codes
Instruction
EXTEST
Code
000
Description
Captures the Input/Output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.
Boundary Scan Order (1 Mbit x 18)
Bit #
1
Bump ID
5R
6T
Bit #
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Bump ID
7E
Bit #
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Bump ID
1H
2
6D
3G
4D
3
4P
6A
4
6R
5T
6C
4E
5
5C
4G
4H
6
7T
5A
7
7P
6B
4M
2K
8
6N
6L
5B
9
3B
1L
10
11
12
13
14
15
16
17
7K
2B
2M
1N
5L
3A
4L
3C
2P
4K
2C
3T
4F
2A
2R
6H
7G
6F
1D
4N
2E
2T
2G
3R
Document No: 001-07844 Rev. *A
Page 11 of 19
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
Boundary Scan Order (512K x 36)
Bit #
1
Bump ID
5R
4P
Bit #
Bump ID
6F
Bit #
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Bump ID
2H
1H
3G
4D
4E
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
2
7E
3
4T
6E
4
6R
5T
7D
6D
6A
5
6
7T
4G
4H
4M
3L
7
6P
6C
5C
5A
8
7P
9
6N
7N
6M
6L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
6B
1K
5B
2K
3B
1L
7L
2B
2L
6K
3A
2M
1N
2N
1P
7K
3C
2C
2A
5L
4L
4K
2D
1D
2E
2P
4F
3T
5G
7H
6H
7G
6G
2R
4N
3R
1E
2F
2G
1G
Document No: 001-07844 Rev. *A
Page 12 of 19
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
[7]
DC Input Voltage ................................ –0.5V to V + 0.5V
Maximum Ratings
DD
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage...........................................> 1500V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current.....................................................> 200 mA
Ambient Temperature with
Power Applied........................................... –55°C to +125°°C
Operating Range
Supply Voltage on V Relative to GND........ –0.5V to +2.9V
DD
Ambient
Supply Voltage on V
Relative to GND ......–0.5V to +V
Range
Temperature
V
V
DDQ
DDQ
DD
DD
DC Voltage Applied to Outputs
in High-Z State ................................. –0.5V to V
Com’l
0°C to +70°C
2.37V to 2.63V 1.4V to 1.9V
[7]
+ 0.5V
DDQ
Electrical Characteristics Over the Operating Range
DC Electrical Characteristics Over the Operating Range
Parameter
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
2.37
1.4
Max.
2.63
1.9
Unit
V
V
DD
V
V
V
V
V
V
V
V
V
I
V
DDQ
OH1
OL1
OH2
OL2
OH3
OL3
IH
[12]
[14]
Output HIGH Voltage
Programmable Impedance Mode
Programmable Impedance Mode
V
/2
V
V
DDQ
DD
[13]
[14]
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
V
V
/2
V
SS
DDQ
[15]
I
I
I
I
= –0.1 mA, Minimum Impedance Mode
V
V
V
– 0.2
V
V
OH
OL
OH
OL
DDQ
DDQ
[15]
= 0.1 mA, Minimum Impedance Mode
= –6.0 mA, Minimum Impedance Mode
V
0.2
V
SS
[15]
[15]
– 0.4
V
V
DDQ
DDQ
= 6.0 mA, Minimum Impedance Mode
V
0.4
V
SS
+ 0.1
V
+ 0.3
– 0.1
V
REF
DDQ
[7]
Input LOW Voltage
–0.3
V
V
IL
REF
Input Leakage Current
Output Leakage Current
Input Reference Voltage
GND ≤ V ≤ V
–1
–1
1
mA
mA
V
X
I
DDQ
I
GND ≤ V ≤ V
Output Disabled
1
OZ
I
DDQ,
V
Typical value = 0.75V
0.68
–0.3
0.95
REF
V –CLK
Clock Input Reference
Voltage
V
V
+ 0.3
V
IN
DDQ
V
V
–CLK
–CLK
Clock Input Differential
Voltage
0.1
+ 0.3
V
V
DIF
DDQ
Clock Common Mode
Voltage
Typical Value =0.75V
0.55
0.95
CM
I
V
Operating Supply
V
f = f
= Max., I
= 0 mA,
250 MHz
600
550
280
260
mA
mA
mA
mA
DD
DD
DD
OUT
= 1/t
CYC
MAX
200 MHz
250 MHz
200 MHz
I
Automatic CE
Power-Down
Current—TTL Inputs
Max. V , Device Deselected,
DD
V
f = f
SB1
> V or V < V
IN
IH
IN
IL
= 1/t
MAX CYC
AC Electrical Characteristics Over the Operating Range
Parameter
Description
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min.
Max.
Unit
V
V
V
+ 0.2
–
IH
IL
REF
V
–
V
– 0.2
V
REF
Notes:
12. I = (V
/2)/(RQ/5)+15% for 175Ω < RQ < 350Ω.
OH
DDQ
13. I = (V
/2)/(RQ/5)+15% for 175Ω < RQ < 350Ω.
OL
DDQ
14. Programmable Impedance Output Buffer Mode. The ZQ pin is connected to V through RQ.
SS
15. Minimum Impedance Output Buffer Mode: The ZQ pin is connected directly to V or V
.
SS
DD
16. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
DD
Power-up
DD
IH
DD
DDQ
Document No: 001-07844 Rev. *A
Page 13 of 19
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
Capacitance[17]
Parameter
Description
Input Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
pF
C
C
C
5
6
7
IN
A
V
= 2.5V
= 1.5V
DD
Clock Input Capacitance
Input/Output Capacitance
pF
CLK
I/O
V
DDQ
pF
Thermal Resistance[17]
Parameter
Description
Test Conditions
BGA Typ.
Unit
Θ
Thermal Resistance
(Junction to Ambient)
Still Air, solderedon a 4.25x 1.125 inch, 4-layerprinted
circuit board
19.7
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
6.0
°C/W
JC
AC Test Loads and Waveforms
V
REF = 0.75V
0.75V
VREF
VREF
0.75V
R = 50Ω
OUTPUT
[18]
ALL INPUT PULSES
1.25V
Z = 50Ω
0
OUTPUT
Device
Under
Test
R = 50Ω
L
0.75V
Device
Under
0.25V
5 pF
VREF = 0.75V
Slew Rate = 2 V/ns
ZQ
Test
ZQ
RQ =
RQ =
250
250Ω
Ω
(a)
(b)
Notes:
17. Tested initially and after any design or process change that may affect these parameters.
18. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75V, V
= 0.75V, RQ = 250Ω, V
= 1.5V, input
DDQ
REF
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads.
OL OH
Document No: 001-07844 Rev. *A
Page 14 of 19
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
Switching Characteristics[18, 19, 20, 21]
250
200
Parameter
Description
(typical) to the First Access Read or Write
CC
Min.
Max.
Min.
Max.
Unit
[22]
t
V
1
1
ms
Power
Clock
t
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
4.0
5.0
ns
MHz
ns
CYC
F
250
200
MAX
t
t
1.5
1.5
1.5
1.5
CH
CL
Clock LOW
ns
Output Times
t
t
t
t
t
t
t
Data Output Valid After CLK Rise
2.0
2.0
2.25
2.25
ns
ns
ns
ns
ns
ns
ns
CO
[17, 19, 21]
OE LOW to Output Valid
EOV
DOH
CHZ
CLZ
Data Output Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
[17, 18, 19, 20, 21]
Clock to High-Z
2.0
2.0
2.25
2.25
[17, 18, 19, 20, 21]
Clock to Low-Z
[18, 19, 21]
OE HIGH to Output High-Z
EOHZ
EOLZ
[18, 19, 21]
OE LOW to Output Low-Z
Set-Up Times
t
t
t
t
Address Set-Up Before CLK Rise
Data Input Set-Up Before CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
ns
ns
ns
ns
AS
DS
WE, BWS Set-Up Before CLK Rise
WES
CES
x
Chip Select Set-Up
Hold Times
t
t
t
t
Address Hold After CLK Rise
Data Input Hold After CLK Rise
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
ns
ns
ns
ns
AH
DH
WE, BW Hold After CLK Rise
WEH
CEH
x
Chip Select Hold After CLK Rise
Notes:
19. t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
CHZ CLZ
20. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
EOHZ
EOLZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
22. This part has a voltage regulator that steps down the voltage internally; t
is the time power needs to be supplied above V minimum initially before a read
DD
Power
or write operation can be initiated.
Document No: 001-07844 Rev. *A
Page 15 of 19
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
Switching Waveforms
[23, 24, 25, 26]
READ/WRITE/DESELECT Sequence (OE Controlled)
K
t
t
t
CYC
CL
CH
t
t
AH
AS
RA3
WA5
RA1
WA2
RA6
ADDRESS
WE
WA7
WA8
t
t
WES
WEH
BWS
OE/
x
t
t
WES
WEH
t
EOHZ
t
EOLZ
t
t
EOV
t
DS
DH
t
t
DOH
DOH
t
t
EOHZ
CLZ
Q1
Out
D2
In
Data
In/Out
Q3
Out
D5
In
Q6
Out
D7
D8
In
In
Device
originally
t
CHZ
t
t
CO
DH
deselected
t
DS
= UNDEFINED
= DON’T CARE
Notes:
23. The combination of WE and BWS (x = a, b, c, d for x36 and x = a, b for x18) define a write cycle (see Write Cycle Description table).
x
24. All chip enables need to be active in order to select the device. Any chip enable can deselect the device.
25. RAx stands for Read Address X, WAx Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X.
26. CE held LOW.
Document No: 001-07844 Rev. *A
Page 16 of 19
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
Switching Waveforms (continued)
READ/WRITE/DESELECT Sequence (CE Controlled)
CLK
t
t
t
CYC
CL
CH
t
t
CEH
CES
CE
t
t
AH
AS
RA3
WA5
RA1
WA2
RA6
ADDRESS
WE
WA7
WA8
t
t
WES
WEH
BWS
x
t
t
t
WES
WEH
t
t
DS
DH
t
DOH
DOH
t
CLZ
Q1
Out
D2
In
Data
In/Out
Q3
Out
D5
In
Q6
Out
D7
In
D8
In
Device
originally
t
CHZ
t
CO
deselected
= UNDEFINED
= DON’T CARE
Document No: 001-07844 Rev. *A
Page 17 of 19
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Package Type
250 CY7C1330AV25-250BGC 51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1332AV25-250BGC
Commercial
CY7C1330AV25-250BGXC 51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1332AV25-250BGXC
200 CY7C1330AV25-200BGC 51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1332AV25-200BGC
CY7C1330AV25-200BGXC 51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1332AV25-200BGXC
Package Diagram
119-ball PBGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
All product and company names mentioned in this document are trademarks of their respective holders.
Document No: 001-07844 Rev. *A
Page 18 of 19
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
Document History Page
Document Title: CY7C1330AV25/CY7C1332AV25 18-Mbit (512K x 36/1Mbit x 18)
Pipelined Register-Register Late Write SRAM
Document Number: 001-07844
Orig. of
REV.
**
ECN No. Issue Date Change
Description of Change
469811
503690
See ECN
See ECN
NXR New data sheet
VKN Minor change: Moved data sheet to web
*A
Document No: 001-07844 Rev. *A
Page 19 of 19
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