CY62146EV30 MoBL®
4-Mbit (256K x 16) Static RAM
reduces power consumption by 80% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption by more than 99% when
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62146DV30
• Ultra low standby power
deselected (CE HIGH). The input and output pins (IO through
0
IO ) are placed in a high impedance state when:
15
• Deselected (CE HIGH)
• Outputs are disabled (OE HIGH)
— Typical standby current: 1 µA
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
— Maximum standby current: 7 µA
• Ultra low active power
• Write operation is active (CE LOW and WE LOW)
— Typical active current: 2 mA @ f = 1 MHz
• Easy memory expansion with CE, and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW,
then data from IO pins (IO through IO ), is written into the
0
7
location specified on the address pins (A through A ). If Byte
0
17
High Enable (BHE) is LOW, then data from IO pins (IO
8
• Available in a Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
through IO ) is written into the location specified on the
15
address pins (A through A ).
0
17
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte Low Enable (BLE) is LOW, then data from the memory
Functional Description [1]
The CY62146EV30 is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
location specified by the address pins appear on IO to IO . If
0
7
Byte High Enable (BHE) is LOW, then data from memory
®
This is ideal for providing More Battery Life™ (MoBL ) in
8
15
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
complete description of read and write modes.
Product Portfolio
Power Dissipation
Speed
(ns)
Product
V
Range (V)
Operating I (mA)
CC
CC
Standby I
(µA)
SB2
f = 1 MHz
f = f
max
[2]
[2]
[2]
Min
Typ
Max
Typ
Max
Typ
15
Max
20
Typ
Max
CY62146EV30LL
2.2
3.0
3.6
45 ns
2
2.5
1
7
Notes:
1. For best practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V , T = 25°C.
CC
CC(typ)
A
Cypress Semiconductor Corporation
Document #: 38-05567 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 26, 2007
CY62146EV30 MoBL®
DC Input Voltage
........... –0.3V to 3.9V (V
+ 0.3V)
Maximum Ratings
CC max
Output Current into Outputs (LOW) ............................ 20 mA
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Static Discharge Voltage ......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................–65°C to + 150°C
Latch-up Current ..................................................... >200 mA
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Operating Range
Supply Voltage to Ground
Ambient
Potential .............................–0.3V to + 3.9V (V
+ 0.3V)
+ 0.3V)
CCmax
Device
Range
Temperature
V
CC
DC Voltage Applied to Outputs
CY62146EV30 Industrial –40°C to +85°C 2.2V to 3.6V
in High-Z State
................–0.3V to 3.9V (V
CCmax
Electrical Characteristics (Over the Operating Range)
45 ns
Parameter
Description
Test Conditions
= –0.1 mA
Min
2.0
2.4
Typ
Max
Unit
V
V
Output HIGH Voltage
I
I
I
I
OH
OL
IH
OH
OH
OL
OL
= –1.0 mA, V > 2.70V
V
CC
V
V
V
I
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
= 0.1 mA
0.4
0.4
V
= 2.1 mA, V > 2.70V
V
CC
V
V
V
V
= 2.2V to 2.7V
= 2.7V to 3.6V
= 2.2V to 2.7V
= 2.7V to 3.6V
1.8
2.2
V
V
+ 0.3
V
CC
CC
CC
CC
CC
CC
+ 0.3
V
–0.3
–0.3
–1
0.6
V
IL
0.8
+1
+1
20
V
Input Leakage Current
Output Leakage Current
GND < V < V
CC
µA
µA
mA
IX
I
I
I
GND < V < V , Output Disabled
–1
OZ
O
CC
V
Operating Supply Current f = f
= 1/t
V
= V
CC(max),
15
CC
CC
max
RC
CC
I
= 0 mA
OUT
f = 1 MHz
2
1
2.5
CMOS levels
I
Automatic CE Power down
Current — CMOS Inputs
7
µA
SB1
CE > V −0.2V,
CC
V
> V –0.2V or V < 0.2V
CC IN
IN
f = f
(Address and Data Only),
max
f = 0 (OE, BHE, BLE and WE), V = 3.60V
CC
I
Automatic CE Power down
Current — CMOS Inputs
1
7
µA
CE > V – 0.2V,
SB2
CC
V
> V – 0.2V or V < 0.2V,
CC IN
IN
f = 0, V = 3.60V
CC
Notes:
5. V
= –2.0V for pulse durations less than 20 ns.
IL(min)
6. V
= V + 0.75V for pulse durations less than 20 ns.
IH(max)
CC
7. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.
cc
cc
8. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
/ I
spec. Other inputs can be left floating.
SB2 CCDR
Document #: 38-05567 Rev. *C
Page 3 of 12
CY62146EV30 MoBL®
[9]
Capacitance (For All Packages)
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max
10
Unit
pF
C
IN
A
V
= V
CC
CC(typ)
C
10
pF
OUT
VFBGA
Package
TSOP II
Package
Parameter
Description
Test Conditions
Unit
Θ
Thermal Resistance Still Air, soldered on a 3 × 4.5 inch,
(Junction to Ambient) two-layer printed circuit board
75
10
77
13
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
°C/W
JC
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
10%
V
CC
V
CC
OUTPUT
90%
10%
GND
R2
30 pF
Rise Time = 1 V/ns
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THEVENIN EQUIVALENT
R
TH
OUTPUT
V
Parameters
2.50V
16667
15385
8000
3.0V
Unit
Ω
R1
R2
1103
1554
645
Ω
R
Ω
TH
V
1.20
1.75
V
TH
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
for Data Retention
CC
Conditions
Min
Typ
Max
Unit
V
V
V
1.5
DR
I
Data Retention Current
V
V
= 1.5V, CE > V – 0.2V,
0.8
7
µA
CCDR
CC
IN
CC
> V – 0.2V or V < 0.2V
CC
IN
t
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
CDR
R
t
RC
Data Retention Waveform
DATA RETENTION MODE
> 1.5V
V
V
V
VCC
CE
CC(min)
CC(min)
DR
t
t
R
CDR
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.
10. Full device operation requires linear V ramp from V to V > 100 µs or stable at V > 100 µs.
CC(min)
CC
DR
CC(min)
Document #: 38-05567 Rev. *C
Page 4 of 12
CY62146EV30 MoBL®
Switching Characteristics (Over the Operating Range)
45 ns
Parameter
Read Cycle
Description
Min
45
Max
Unit
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
45
AA
Data Hold from Address Change
10
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
45
22
CE LOW to Data Valid
OE LOW to Data Valid
5
10
0
OE LOW to Low-Z
18
18
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power Up
45
22
CE HIGH to Power Down
BLE / BHE LOW to Data Valid
PD
DBE
LZBE
HZBE
5
BLE / BHE LOW to Low-Z
18
BLE / BHE HIGH to High-Z
[15]
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
45
35
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
HA
0
SA
35
35
25
0
WE Pulse Width
PWE
BW
BLE / BHE LOW to Write End
Data Setup to Write End
SD
Data Hold from Write End
HD
18
WE LOW to High-Z
HZWE
LZWE
10
WE HIGH to Low-Z
Notes:
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
/2, input
CC(typ)
pulse levels of 0 to V
CC(typ)
OL OH
12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further
clarification.
13. At any given temperature and voltage condition, t
given device.
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
14. t
, t
, t
, and t
transitions are measured when the outputs enter a high impedence state.
HZOE HZCE HZBE
HZWE
15. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any of
IL
IL
these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 38-05567 Rev. *C
Page 5 of 12
CY62146EV30 MoBL®
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)
t
RC
ADDRESS
t
AA
t
OHA
PREVIOUS DATA VALID
DATA VALID
DATA OUT
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE/BLE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGHIMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PU
V
50%
50%
CC
I
SUPPLY
SB
CURRENT
Notes:
16. The device is continuously selected. OE, CE = V , BHE and/or BLE = V .
IL
IL
17. WE is HIGH for read cycle.
18. Address valid before or similar to CE and BHE, BLE transition LOW.
Document #: 38-05567 Rev. *C
Page 6 of 12
CY62146EV30 MoBL®
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
HD
t
SD
NOTE 21
DATA IO
DATAIN
t
HZOE
Write Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA IO
t
HZOE
Notes:
19. Data IO is high impedance if OE = V
.
IH
20. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance state.
IH
21. During this period, the IOs are in output state and input signals must not be applied.
Document #: 38-05567 Rev. *C
Page 7 of 12
CY62146EV30 MoBL®
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
HD
t
SD
DATA IO
DATAIN
t
LZWE
t
HZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
t
SA
tPWE
WE
tHZWE
t
HD
t
SD
NOTE 21
DATAIN
DATA IO
tLZWE
Document #: 38-05567 Rev. *C
Page 8 of 12
CY62146EV30 MoBL®
Truth Table
CE
H
L
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High-Z
High-Z
Data Out (IO –IO
Mode
Power
Standby (I
Deselect/Power down
Output Disabled
Read
)
SB
X
X
H
H
Active (I
Active (I
Active (I
)
CC
L
H
L
L
L
)
)
CC
0
15
L
H
L
H
L
Data Out (IO –IO );
Read
)
CC
0
7
IO –IO in High-Z
8
15
L
H
L
L
H
Data Out (IO –IO );
Read
Active (I
)
8
15
CC
IO –IO in High-Z
0
7
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High-Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (I
Active (I
Active (I
Active (I
Active (I
)
CC
High-Z
High-Z
)
CC
)
CC
L
Data In (IO –IO
)
)
CC
0
15
L
H
Data In (IO –IO );
Write
)
CC
0
7
IO –IO in High-Z
8
15
L
L
X
L
H
Data In (IO –IO );
Write
Active (I
)
CC
8
15
IO –IO in High-Z
0
7
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
45
CY62146EV30LL-45BVXI 51-85150 48-ball VFBGA (Pb-free)
CY62146EV30LL-45ZSXI 51-85087 44-pin TSOP II (Pb-free)
Industrial
Please contact your local Cypress sales representative for availability of other parts
Document #: 38-05567 Rev. *C
Page 9 of 12
CY62146EV30 MoBL®
Package Diagrams
Figure 1. 48-ball VFBGA (6 x 8 x 1 mm), 51-85150
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30 0.05(48X)
A1 CORNER
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15(4X)
SEATING PLANE
C
51-85150-*D
Document #: 38-05567 Rev. *C
Page 10 of 12
CY62146EV30 MoBL®
Package Diagrams (continued)
Figure 2. 44-pin TSOP II, 51-85087
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05567 Rev. *C
Page 11 of 12
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62146EV30 MoBL®
Document History Page
®
Document Title:CY62146EV30 MoBL , 4-Mbit (256K x 16) Static RAM
Document Number: 38-05567
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
223225
247373
See ECN
See ECN
AJU
SYT
New Data Sheet
*A
Changed Advance Information to Preliminary
Moved Product Portfolio to Page 2
Changed V stabilization time in footnote #8 from 100 µs to 200 µs
CC
Removed Footnote #14(t
) from Previous revision
LZBE
Changed I
from 2.0 µA to 2.5 µA
CCDR
Changed typo in Data Retention Characteristics(t ) from 100 µs to t ns
R
RC
Changed t
Changed t
from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin
OHA
, t
, t
from 12 to 15 ns for 35 ns Speed Bin and 15 to
HZOE HZBE HZWE
18 ns for 45 ns Speed Bin
Changed t and t from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns
SCE
BW
for 45 ns Speed Bin
Changed t from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45
HZCE
ns Speed Bin
Changed t from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for
SD
45 ns Speed Bin
Changed t
Changed t
from 15 to 18 ns for 35 ns Speed Bin
from 15 to 18 ns for 35 ns Speed Bin
DOE
DBE
Changed Ordering Information to include Pb-Free Packages
*B
414807
See ECN
ZSD
Changed from Preliminary information to Final
Changed the address of Cypress Semiconductor Corporation on Page #1
from “3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin
Removed “L” version of CY62146EV30
Changed ball E3 from DNU to NC
Removed the redundant foot note on DNU.
Changed I (Max) value from 2 mA to 2.5 mA and I (Typ) value from
CC
CC
1.5 mA to 2 mA at f=1 MHz
Changed I (Typ) value from 12 mA to 15 mA at f = f
CC
max
Changed I
and I
Typ values from 0.7 µA to 1 µA and Max values from
SB1
SB2
2.5 µA to 7 µA.
Changed the AC test load capacitance from 50pF to 30pF on Page# 4
Changed I from 2.5 µA to 7 µA.
CCDR
Added I
typical value.
CCDR
Changed t
Changed t
Changed t
Changed t
Changed t
from 3 ns to 5 ns
LZOE
LZCE
LZBE
HZCE
PWE
and t
from 6 ns to 10 ns
LZWE
from 6 ns to 5 ns
from 22 ns to 18 ns
from 30 ns to 35 ns.
Changed t from 22 ns to 25 ns.
SD
Updated the package diagram 48-ball VFBGA from *B to *D
Updated the ordering information table and replaced the Package Name
column with Package Diagram.
*C
925501
See ECN
VKN
Added footnote #8 related to I
Added footnote #12 related AC timing parameters
and I
SB2 CCDR
Document #: 38-05567 Rev. *C
Page 12 of 12
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