Cypress CY14E102N User Manual

ADVANCE  
CY14E102L, CY14E102N  
2-Mbit (256K x 8/128K x 16) nvSRAM  
Features  
Functional Description  
15 ns, 20 ns, 25 ns, and 45 ns access times  
The Cypress CY14E102L/CY14E102N is a fast static RAM, with  
a nonvolatile element in each memory cell. The memory is  
Internally organized as 256K x 8 (CY14E102L) or 128K x 16  
(CY14E102N)  
organized as 256K words of 8 bits each or 128K words of 16 bits  
each. The embedded nonvolatile elements incorporate  
QuantumTrap technology, producing the world’s most reliable  
nonvolatile memory. The SRAM provides infinite read and write  
cycles, while independent nonvolatile data reside in the highly  
reliable QuantumTrap cell. Data transfers from the SRAM to the  
nonvolatile elements (the STORE operation) takes place  
automatically at power down. On power up, data is restored to  
the SRAM (the RECALL operation) from the nonvolatile memory.  
Both the STORE and RECALL operations are also available  
under software control.  
Hands off automatic STORE on power down with only a small  
capacitor  
STORE to QuantumTrap nonvolatile elements initiated by  
software, device pin, or AutoStore on power down  
RECALL to SRAM initiated by software or power up  
Infinite read, write, and recall cycles  
200,000 STORE cycles to QuantumTrap  
20 year data retention  
Single 5V +10% operation  
Commercial and Industrial temperatures  
48-pin FBGA, 44 and 54-pin TSOP II packages  
Pb-free and RoHS compliance  
Logic Block Diagram  
V
V
CC  
CAP  
[1]  
A - A  
Address  
0
17  
[1]  
DQ0 - DQ7  
CE  
OE  
CY14E102L  
CY14E102N  
WE  
HSB  
BHE  
BLE  
V
SS  
Note  
1. Address A - A and Data DQ0 - DQ7 for x8 configuration, Address A - A and Data DQ0 - DQ15 for x16 configuration.  
0
17  
0
16  
Cypress Semiconductor Corporation  
Document Number: 001-45755 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 27, 2008  
 
CY14E102L, CY14E102N  
ADVANCE  
Pinouts (continued)  
Figure 3. Pin Diagram - 54 TSOP II (Top View)  
NC  
NC  
A
0
54  
53  
52  
51  
50  
49  
HSB  
[3]  
NC  
1
2
3
[2]  
NC  
A
16  
A
1
4
A
2
A
15  
5
A
3
OE  
6
48  
47  
46  
45  
A
BHE  
7
8
4
CE  
DQ0  
DQ1  
BLE  
DQ15  
DQ14  
DQ13  
DQ12  
9
10  
11  
12  
13  
14  
DQ2  
DQ3  
44  
43  
42  
41  
40  
39  
(x16)  
(Not to Scale)  
V
CC  
V
SS  
V
SS  
V
CC  
DQ4  
DQ5  
DQ11  
DQ10  
DQ9  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
38  
37  
36  
35  
DQ6  
DQ7  
WE  
DQ8  
V
CAP  
A
5
A
14  
34  
33  
32  
31  
30  
29  
28  
A
6
A
13  
A
A
7
A
8
12  
A
11  
A
10  
A
9
NC  
NC  
NC  
25  
26  
27  
NC  
NC  
NC  
Pin Definitions  
Pin Name  
IO Type  
Description  
A – A  
Input  
Address Inputs. Used to select one of the 262, 144 bytes of the nvSRAM for x8 Configuration.  
0
17  
16  
A – A  
Address Inputs. Used to select one of the 131, 072 bytes of the nvSRAM for x16 Configuration.  
0
DQ0 – DQ7 Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on  
operation.  
DQ0 – DQ15  
WE  
Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on  
operation.  
Input  
Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the address  
location latched by the falling edge of CE.  
Input  
Input  
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.  
CE  
OE  
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read  
cycles. IO pins are tri-stated on deasserting OE high.  
Input  
Input  
Byte High Enable, Active LOW. Controls DQ15 - DQ8.  
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.  
BHE  
BLE  
V
Ground  
Ground for the Device. Must be connected to the ground of the system.  
SS  
V
Power Supply Power Supply Inputs to the Device.  
CC  
Input/Output  
HSB  
Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress.  
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull  
up resistor keeps this pin HIGH if not connected (connection is optional).  
V
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from the SRAM  
CAP  
to nonvolatile elements.  
NC  
No Connect No Connect. Do not connect this pin to the die.  
Document Number: 001-45755 Rev. *A  
Page 3 of 21  
CY14E102L, CY14E102N  
ADVANCE  
To reduce unnecessary nonvolatile stores, AutoStore and  
Hardware Store operations are ignored unless at least one  
WRITE operation has taken place since the most recent STORE  
or RECALL cycle. Software initiated STORE cycles are  
performed regardless of whether a WRITE operation has taken  
place. Monitor the HSB signal by the system to detect if an  
AutoStore cycle is in progress.  
Device Operation  
The CY14E102L/CY14E102N nvSRAM is made up of two  
functional components paired in the same physical cell. They are  
an SRAM memory cell and a nonvolatile QuantumTrap cell. The  
SRAM memory cell operates as a standard fast static RAM. Data  
in the SRAM is transferred to the nonvolatile cell (the STORE  
operation), or from the nonvolatile cell to the SRAM (the RECALL  
operation). Using this unique architecture all cells are stored and  
recalled in parallel. During the STORE and RECALL operations  
SRAM read and write operations are inhibited. The  
CY14E102L/CY14E102N supports infinite reads and writes  
similar to a typical SRAM. In addition, it provides infinite RECALL  
operations from the nonvolatile cells and up to 200K STORE  
operations.  
Figure 4. AutoStore Mode  
Vcc  
0.1uF  
Vcc  
SRAM Read  
The CY14E102L/CY14E102N performs a READ cycle when CE  
and OE are LOW, and WE and HSB are HIGH. The address  
WE  
VCAP  
specified on pins A  
or A  
determines which of the 262, 144  
0-17  
0-16  
data bytes or 131, 072 words of 16 bits each is accessed. When  
the read is initiated by an address transition, the outputs are valid  
VCAP  
after a delay of t . If the read is initiated by CE or OE, the  
AA  
VSS  
outputs are valid at t  
or at t  
, whichever is later. The data  
ACE  
DOE  
outputs repeatedly respond to address changes within the t  
AA  
access time without the need for transitions on any control input  
pins. This remains valid until another address change or until CE  
or OE is brought HIGH, or WE or HSB is brought LOW.  
SRAM Write  
Hardware STORE Operation  
A WRITE cycle is performed whenever CE and WE are LOW and  
HSB is HIGH. The address inputs must be stable before entering  
the WRITE cycle and must remain stable until either CE or WE  
goes high at the end of the cycle. The data on the common IO  
The CY14E102L/CY14E102N provides the HSB pin for  
controlling and acknowledging the STORE operations. Use the  
HSB pin to request a hardware STORE cycle. When the HSB pin  
is driven LOW, the CY14E102L/CY14E102N conditionally  
pins DQ  
are written into the memory if the data is valid t  
initiates a STORE operation after t  
. An actual STORE cycle  
0–15  
SD  
DELAY  
before the end of a WE controlled WRITE or before the end of  
an CE controlled WRITE. It is recommended that OE be kept  
HIGH during the entire WRITE cycle to avoid data bus contention  
on common IO lines. If OE is left LOW, internal circuitry turns off  
only begins if a WRITE to the SRAM took place since the last  
STORE or RECALL cycle. The HSB pin also acts as an open  
drain driver that is internally driven LOW to indicate a busy  
condition while the STORE (initiated by any means) is in  
progress.  
the output buffers t  
after WE goes LOW.  
HZWE  
SRAM READ and WRITE operations that are in progress when  
HSB is driven LOW by any means are given time to complete  
before the STORE operation is initiated. After HSB goes LOW,  
the CY14E102LL/CY14E102N continues SRAM operations for  
AutoStore Operation  
The CY14E102L/CY14E102N stores data to the nvSRAM using  
one of the following three storage operations: Hardware Store  
activated by HSB, Software Store activated by an address  
sequence, and AutoStore on device power down. The AutoStore  
operation is a unique feature of QuantumTrap technology and is  
enabled by default on the CY14E102L/CY14E102N.  
t
. During t  
, multiple SRAM READ operations may take  
DELAY  
DELAY  
place. If a WRITE is in progress when HSB is pulled low it is  
allowed a time, t to complete. However, any SRAM WRITE  
DELAY  
cycles requested after HSB goes LOW is inhibited until HSB  
returns HIGH.  
During a normal operation, the device draws current from V to  
CC  
charge a capacitor connected to the V  
charge is used by the chip to perform a single STORE operation.  
pin. This stored  
During any STORE operation, regardless of how it was initiated,  
the CY14E102L/CY14E102N continues to drive the HSB pin  
LOW, releasing it only when the STORE is complete. Upon  
CAP  
If the voltage on the V pin drops below V , the part  
CC  
SWITCH  
automatically disconnects the V  
pin from V . A STORE  
completion  
of  
the  
STORE  
operation,  
the  
CAP  
CC  
operation is initiated with power provided by the V  
capacitor.  
CY14E102L/CY14E102N remains disabled until the HSB pin  
returns HIGH. Leave the HSB unconnected if it is not used.  
CAP  
Figure 4 shows the proper connection of the storage capacitor  
(V ) for automatic store operation. Refer to the section DC  
CAP  
.
CAP  
Document Number: 001-45755 Rev. *A  
Page 4 of 21  
 
CY14E102L, CY14E102N  
ADVANCE  
The software sequence may be clocked with CE controlled  
READs or OE controlled READs. After the sixth address in the  
sequence is entered, the STORE cycle commences and the chip  
is disabled. It is important to use READ cycles and not WRITE  
cycles in the sequence, although it is not necessary that OE be  
Hardware RECALL (Power Up)  
During power up or after any low power condition  
(V < V  
), an internal RECALL request is latched. When  
CC  
SWITCH  
V
again exceeds the sense voltage of V  
, a RECALL  
SWITCH  
CC  
LOW for a valid sequence. After the t  
cycle time is fulfilled,  
cycle is automatically initiated and takes t  
to complete.  
STORE  
HRECALL  
the SRAM is activated again for the READ and WRITE operation.  
Software STORE  
Software RECALL  
Transfer data from the SRAM to the nonvolatile memory with a  
software address sequence. The CY14E102L/CY14E102N  
software STORE cycle is initiated by executing sequential  
CE-controlled READ cycles from six specific address locations  
in exact order. During the STORE cycle an erase of the previous  
nonvolatile data is first performed, followed by a program of the  
nonvolatile elements. After a STORE cycle is initiated, further  
input and output are disabled until the cycle is completed.  
Transfer the data from the nonvolatile memory to the SRAM with  
a software address sequence. A software RECALL cycle is  
initiated with a sequence of READ operations in a manner similar  
to the software STORE initiation. To initiate the RECALL cycle,  
the following sequence of CE controlled READ operations must  
be performed:  
1. Read Address 0x4E38 Valid READ  
2. Read Address 0xB1C7 Valid READ  
3. Read Address 0x83E0 Valid READ  
4. Read Address 0x7C1F Valid READ  
5. Read Address 0x703F Valid READ  
6. Read Address 0x4C63 Initiate RECALL Cycle  
Because a sequence of READs from specific addresses is used  
for STORE initiation, it is important that no other READ or WRITE  
accesses intervene in the sequence. If there are intervening  
READ or WRITE accesses, the sequence is aborted and no  
STORE or RECALL takes place.  
To initiate the software STORE cycle, the following READ  
sequence must be performed.  
Internally, RECALL is a two step procedure. First, the SRAM data  
is cleared and then, the nonvolatile information is transferred into  
the SRAM cells. After the t  
ready for READ and WRITE operations. The RECALL operation  
does not alter the data in the nonvolatile elements.  
1. Read Address 0x4E38 Valid READ  
2. Read Address 0xB1C7 Valid READ  
3. Read Address 0x83E0 Valid READ  
4. Read Address 0x7C1F Valid READ  
5. Read Address 0x703F Valid READ  
6. Read Address 0x8FC0 Initiate STORE Cycle  
cycle time, the SRAM is again  
RECALL  
Table 1. Mode Selection  
A15 - A0  
Mode  
IO  
Power  
CE  
WE  
OE  
H
X
X
X
Not Selected  
Output High Z  
Standby  
L
L
L
H
L
L
X
L
X
X
Read SRAM  
Write SRAM  
Output Data  
Input Data  
Active  
Active  
[5,6,7]  
H
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x8B45  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
AutoStore  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active  
Disable  
[5,6,7]  
L
H
L
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x4B46  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
AutoStore Enable  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active  
Notes  
5. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.  
6. While there are 18/17 address lines on the CY14E102L/CY14E102N, only the lower 16 lines are used to control software modes.  
7. IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.  
Document Number: 001-45755 Rev. *A  
Page 5 of 21  
     
CY14E102L, CY14E102N  
ADVANCE  
Table 1. Mode Selection (continued)  
A15 - A0  
Mode  
IO  
Power  
CE  
WE  
OE  
L
H
L
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x8FC0  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active I  
CC2  
Nonvolatile Store Output High Z  
[5,6,7]  
L
H
L
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x4C63  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Nonvolatile  
Recall  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
Active  
If the AutoStore function is disabled or re-enabled a manual  
STORE operation (hardware or software) must be issued to save  
the AutoStore state through subsequent power down cycles. The  
part comes from the factory with AutoStore enabled.  
Preventing AutoStore  
The AutoStore function is disabled by initiating an AutoStore  
disable sequence. A sequence of read operations is performed  
in a manner similar to the software STORE initiation. To initiate  
the AutoStore disable sequence, the following sequence of CE  
controlled read operations must be performed:  
Data Protection  
The CY14E102L/CY14E102N protects data from corruption  
during low voltage conditions by inhibiting all externally initiated  
STORE and write operations. The low voltage condition is  
1. Read address 0x4E38 Valid READ  
2. Read address 0xB1C7 Valid READ  
3. Read address 0x83E0 Valid READ  
4. Read address 0x7C1F Valid READ  
5. Read address 0x703F Valid READ  
6. Read address 0x8B45 AutoStore Disable  
detected when V < V  
. If the CY14E102L/CY14E102N  
CC  
SWITCH  
is in a write mode (both CE and WE LOW) at power up, after a  
RECALL or STORE, the write is inhibited until a negative  
transition on CE or WE is detected. This protects against  
inadvertent writes during power up or brown out conditions.  
The AutoStore is re-enabled by initiating an AutoStore enable  
sequence. A sequence of read operations is performed in a  
manner similar to the software RECALL initiation. To initiate the  
AutoStore enable sequence, the following sequence of CE  
controlled read operations must be performed:  
Noise Considerations  
1. Read address 0x4E38 Valid READ  
2. Read address 0xB1C7 Valid READ  
3. Read address 0x83E0 Valid READ  
4. Read address 0x7C1F Valid READ  
5. Read address 0x703F Valid READ  
6. Read address 0x4B46 AutoStore Enable  
Document Number: 001-45755 Rev. *A  
Page 6 of 21  
CY14E102L, CY14E102N  
ADVANCE  
Package Power Dissipation  
Maximum Ratings  
Capability (T = 25°C) ................................................... 1.0W  
A
Exceeding maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Surface Mount Pb Soldering  
Temperature (3 Seconds).......................................... +260°C  
Storage Temperature ................................. –65°C to +150°C  
Output Short Circuit Current .................................... 15 mA  
Ambient Temperature with  
Power Applied ............................................ –55°C to +150°C  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Supply Voltage on V Relative to GND ..........–0.5V to 7.0V  
CC  
Latch-Up Current................................................... > 200 mA  
Voltage Applied to Outputs  
in High-Z State.......................................0.5V to V + 0.5V  
Operating Range  
CC  
Range  
Commercial  
Industrial  
Ambient Temperature  
0°C to +70°C  
V
CC  
Input Voltage.............................................–0.5V to Vcc+0.5V  
Transient Voltage (<20 ns) on  
4.5V to 5.5V  
4.5V to 5.5V  
Any Pin to Ground Potential ..................2.0V to V + 2.0V  
CC  
–40°C to +85°C  
DC Electrical Characteristics  
Over the Operating Range (V = 4.5V to 5.5V)  
CC  
Parameter  
Description  
Average V Current  
Test Conditions  
Min  
Max  
Unit  
I
t
t
t
t
= 15 ns  
= 20 ns  
= 25 ns  
= 45 ns  
Commercial  
70  
65  
65  
50  
mA  
mA  
mA  
CC1  
CC  
RC  
RC  
RC  
RC  
Dependent on output loading and cycle  
rate.Values obtained without output loads.  
Industrial  
75  
70  
70  
52  
mA  
mA  
mA  
I
= 0 mA  
OUT  
I
I
Average V Current All Inputs Don’t Care, V = Max  
6
mA  
mA  
CC2  
CC  
CC  
during STORE  
Average current for duration t  
STORE  
AverageV Currentat WE > (V – 0.2). All other I/P cycling.  
35  
CC3  
CC  
CC  
t
= 200 ns, 5V, 25°C Dependent on output loading and cycle rate. Values obtained  
RC  
typical  
without output loads.  
I
I
Average V  
Current All Inputs Don’t Care, V = Max  
6
3
mA  
mA  
CC4  
CAP  
CC  
during AutoStore Cycle Average current for duration t  
STORE  
V
Standby Current CE > (V – 0.2). All others V < 0.2V or > (V – 0.2V).  
CC IN CC  
SB  
CC  
Standby current level after nonvolatile cycle is complete.  
Inputs are static. f = 0 MHz.  
I
Input Leakage Current V = Max, V < V < V  
(except HSB)  
–1  
–100  
–1  
+1  
+1  
+1  
μA  
μA  
μA  
IX  
CC  
SS  
IN  
CC  
Input Leakage Current V = Max, V < V < V  
(For HSB)  
CC  
CC  
SS  
IN  
CC  
I
Off-State Output  
Leakage Current  
V
= Max, V < V < V , CE or OE > V  
SS IN CC IH  
OZ  
V
V
V
V
V
Input HIGH Voltage  
Input LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Storage Capacitor  
2.0  
V
+ 0.5  
V
V
IH  
CC  
V
– 0.5  
ss  
0.8  
IL  
I
I
= –2 mA  
= 4 mA  
2.4  
V
OH  
OL  
OUT  
0.4  
82  
V
OUT  
Between V  
pin and V , 5V Rated  
61  
μF  
CAP  
CAP  
SS  
Notes  
8. Outputs shorted for no more than one second. No more than one output shorted at a time.  
9. Typical conditions for the active current shown on the front page of the data sheet are average values at 25°C (room temperature), and V = 5V. Not 100% tested.  
CC  
10. The HSB pin has I  
=-10 uA for V of 2.4V.This parameter is characterized but not tested.  
OUT  
OH  
Document Number: 001-45755 Rev. *A  
Page 7 of 21  
       
CY14E102L, CY14E102N  
ADVANCE  
Capacitance  
The following table lists the capacitance parameters.  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max  
7
Unit  
pF  
C
IN  
A
V
= 0 to 3.0V  
CC  
C
7
pF  
OUT  
Thermal Resistance  
The following table lists the thermal resistance parameters.  
Parameter  
Description  
Test Conditions  
48-FBGA 44-TSOP II 54-TSOP II Unit  
ΘJA  
Thermal Resistance  
(Junction to Ambient) procedures for measuring thermal impedance, in  
Test conditions follow standard test methods and  
28.82  
31.11  
30.73  
°C/W  
accordance with EIA/JESD51.  
ΘJC  
Thermal Resistance  
(Junction to Case)  
7.84  
5.56  
6.08  
°C/W  
AC Test Loads  
963Ω  
R1  
for tri-state specs  
963Ω  
5.0V  
OUTPUT  
5.0V  
R1  
OUTPUT  
R2  
512Ω  
R2  
512Ω  
5 pF  
30 pF  
AC Test Conditions  
Input Pulse Levels ....................................................0V to 3V  
Input Rise and Fall Times (10% - 90%)........................ <5 ns  
Input and Output Timing Reference Levels .................... 1.5V  
Note  
11. These parameters are guaranteed but not tested.  
Document Number: 001-45755 Rev. *A  
Page 8 of 21  
 
CY14E102L, CY14E102N  
ADVANCE  
AC Switching Characteristics  
The following table lists the AC switching characteristics.  
Parameters  
Description  
Parameters Parameters  
15 ns  
20 ns  
25 ns  
45 ns  
Unit  
Cypress  
Alt  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
SRAM Read Cycle  
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time  
Read Cycle Time  
15  
20  
25  
45  
ns  
ns  
ns  
ns  
ns  
ACE  
ACS  
RC  
AA  
15  
20  
25  
45  
RC  
Address Access Time  
Output Enable to Data Valid  
15  
10  
20  
10  
25  
12  
45  
20  
AA  
DOE  
OHA  
OE  
OH  
Output Hold After Address  
Change  
3
3
3
3
3
3
3
3
t
t
t
t
t
t
t
t
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
ns  
ns  
ns  
ns  
LZCE  
LZ  
7
7
8
8
10  
10  
15  
15  
HZCE  
HZ  
0
0
0
0
0
0
0
0
LZOE  
HZOE  
OLZ  
OHZ  
Output Disable to Output  
Inactive  
t
t
t
t
t
t
t
Chip Enable to Power Active  
Chip Disable to Power Standby  
Byte Enable to Data Valid  
ns  
ns  
ns  
ns  
ns  
PU  
PA  
15  
10  
20  
10  
25  
12  
45  
20  
PD  
PS  
-
-
-
DBE  
Byte Enable to Output Active  
Byte Disable to Output Inactive  
0
0
0
0
LZBE  
HZBE  
7
8
10  
15  
SRAM Write Cycle  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
15  
10  
15  
5
20  
15  
15  
8
25  
20  
20  
10  
0
45  
30  
30  
15  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
PWE  
SCE  
SD  
WC  
WP  
CW  
DW  
DH  
AW  
AS  
Write Pulse Width  
Chip Enable To End of Write  
Data Setup to End of Write  
Data Hold After End of Write  
Address Setup to End of Write  
Address Setup to Start of Write  
Address Hold After End of Write  
Write Enable to Output Disable  
Output Active after End of Write  
Byte Enable to End of Write  
0
0
HD  
10  
0
15  
0
20  
0
30  
0
AW  
SA  
0
0
0
0
HA  
WR  
WZ  
OW  
[14,15]  
7
8
10  
15  
HZWE  
3
3
3
3
LZWE  
BW  
-
15  
15  
20  
30  
Notes  
12. WE must be HIGH during SRAM read cycles.  
13. Device is continuously selected with CE and OE both LOW.  
14. Measured ±200 mV from steady state output voltage.  
15. If WE is LOW when CE goes LOW, the output goes into high impedance state.  
Document Number: 001-45755 Rev. *A  
Page 9 of 21  
       
CY14E102L, CY14E102N  
ADVANCE  
AutoStore and Power Up RECALL  
CY14E102L/CY14E102N  
Unit  
Parameters  
Description  
Min  
Max  
t
Power Up RECALL Duration  
20  
ms  
ms  
V
HRECALL  
t
STORE Cycle Duration  
Low Voltage Trigger Level  
VCC Rise Time  
15  
STORE  
V
t
4.4  
SWITCH  
150  
μs  
VCCRISE  
Software Controlled STORE and RECALL Cycle  
The following table lists the software controlled STORE and RECALL cycle parameters.  
15ns  
20 ns  
25ns  
45ns  
Parameters  
Description  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
45  
0
Max  
t
STORE and RECALL Initiation Cycle Time  
Address Setup Time  
15  
0
20  
0
25  
0
ns  
ns  
ns  
ns  
μs  
μs  
RC  
t
t
t
t
t
AS  
Clock Pulse Width  
12  
1
15  
1
20  
1
30  
1
CW  
Address Hold Time  
GHAX  
RECALL Duration  
200  
70  
200  
70  
200  
70  
200  
70  
RECALL  
Soft Sequence Processing Time  
SS  
Hardware STORE Cycle  
CY14E102L/CY14E102N  
Min Max  
70  
Parameters  
Description  
Unit  
t
t
Time allowed to complete SRAM cycle  
Hardware STORE pulse width  
1
μs  
DELAY  
15  
ns  
HLHX  
Notes  
16. t  
starts from the time V rises above V  
SWITCH.  
HRECALL  
CC  
17. If an SRAM Write has not taken place since the last nonvolatile cycle, no STORE takes place.  
18. The software sequence is clocked with CE controlled or OE controlled reads.  
19. The six consecutive addresses must be read in the order listed in the mode selection table. WE must be HIGH during all six consecutive cycles.  
20. This is the amount of time it takes to take action on a soft sequence command.Vcc power must remain HIGH to effectively register command.  
21. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.  
22. On a hardware STORE initiation, SRAM operation continues to be enabled for time t  
to allow read and write cycles to complete.  
DELAY  
Document Number: 001-45755 Rev. *A  
Page 10 of 21  
             
CY14E102L, CY14E102N  
ADVANCE  
Switching Waveforms  
Figure 5. SRAM Read Cycle #1: Address Controlled  
tRC  
ADDRESS  
tAA  
tOHA  
DQ (DATA OUT)  
DATA VALID  
[12, 23, 25]  
Figure 6. SRAM Read Cycle #2: CE and OE Controlled  
tRC  
ADDRESS  
CE  
tACE  
tPD  
tLZCE  
tHZCE  
OE  
tHZOE  
tDOE  
tLZOE  
BHE , BLE  
tHZCE  
tHZBE  
tDBE  
tLZBE  
DQ (DATA OUT)  
DATA VALID  
ACTIVE  
tPU  
STANDBY  
ICC  
Notes  
23. HSB must remain HIGH during READ and WRITE cycles.  
24. CE or WE must be >V during address transitions.  
IH  
25. BHE and BLE are applicable for x16 configuration only.  
Document Number: 001-45755 Rev. *A  
Page 11 of 21  
   
CY14E102L, CY14E102N  
ADVANCE  
Switching Waveforms (continued)  
[13, 21, 22, 23]  
Figure 7. SRAM Write Cycle #1: WE Controlled  
tWC  
ADDRESS  
CE  
tHA  
tSCE  
tAW  
tSA  
tPWE  
WE  
tBW  
BHE , BLE  
tHD  
tSD  
DATA VALID  
DATA IN  
tHZWE  
tLZWE  
HIGH IMPEDANCE  
PREVIOUS DATA  
DATA OUT  
Figure 8. SRAM Write Cycle #2: CE Controlled  
tWC  
ADDRESS  
CE  
tSA  
tSCE  
tHA  
tAW  
tPWE  
WE  
tBW  
tSD  
BHE , BLE  
tHD  
DATA IN  
DATA VALID  
HIGH IMPEDANCE  
DATA OUT  
Document Number: 001-45755 Rev. *A  
Page 12 of 21  
CY14E102L, CY14E102N  
ADVANCE  
Switching Waveforms (continued)  
Figure 9. AutoStore or Power Up RECALL  
No STORE occurs  
without atleast one  
SRAM write  
STORE occurs only  
if a SRAM write  
has happened  
V
CC  
V
SWITCH  
tVCCRISE  
AutoStore  
tSTORE  
tSTORE  
POWER-UP RECALL  
tHRECALL  
tHRECALL  
Read & Write Inhibited  
Figure 10. CE Controlled Software STORE/RECALL Cycle  
Note  
26. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V  
.
SWITCH  
Document Number: 001-45755 Rev. *A  
Page 13 of 21  
 
CY14E102L, CY14E102N  
ADVANCE  
Switching Waveforms (continued)  
Figure 11. OE Controlled Software STORE/RECALL Cycle  
tRC  
tRC  
ADDRESS # 1  
ADDRESS # 6  
ADDRESS  
CE  
OE  
tAS  
tCW  
tGHAX  
t
STORE / tRECALL  
HIGH IMPEDANCE  
DATA VALID  
DQ (DATA)  
DATA VALID  
Figure 12. Hardware STORE Cycle  
Figure 13. Soft Sequence Processing  
tSS  
tSS  
Document Number: 001-45755 Rev. *A  
Page 14 of 21  
CY14E102L, CY14E102N  
ADVANCE  
Ordering Information  
Speed  
Package  
Diagram  
Operating  
Ordering Code  
Package Type  
(ns)  
Range  
Commercial  
Industrial  
15  
CY14B102L-ZS15XCT  
CY14E102L-ZS15XIT  
CY14E102L-ZS15XI  
51-85087  
51-85087  
51-85087  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
51-85087  
51-85087  
51-85087  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
44-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
CY14E102L-BA15XCT  
CY14E102L-BA15XIT  
CY14E102L-BA15XI  
CY14E102L-ZSP15XCT  
CY14E102L-ZSP15XIT  
CY14E102L-ZSP15XI  
CY14E102N-BA115XCT  
CY14E102N-BA15XIT  
CY14E102N-BA15XI  
CY14E102N-ZSP15XCT  
CY14E102N-ZSP15XIT  
CY14E102N-ZSP15XI  
CY14B102L-ZS20XCT  
CY14E102L-ZS20XIT  
CY14E102L-ZS20XI  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
20  
Commercial  
Industrial  
CY14E102L-BA20XCT  
CY14E102L-BA20XIT  
CY14E102L-BA20XI  
CY14E102L-ZSP20XCT  
CY14E102L-ZSP20XIT  
CY14E102L-ZSP20XI  
CY14E102N-BA20XCT  
CY14E102N-BA20XIT  
CY14E102N-BA20XI  
CY14E102N-ZSP20XCT  
CY14E102N-ZSP20XIT  
CY14E102N-ZSP20XI  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Document Number: 001-45755 Rev. *A  
Page 15 of 21  
CY14E102L, CY14E102N  
ADVANCE  
Ordering Information (continued)  
Speed  
Package  
Diagram  
Operating  
Ordering Code  
(ns)  
Package Type  
Range  
Commercial  
Industrial  
25  
CY14E102L-ZS25XCT  
CY14E102L-ZS25XIT  
CY14E102L-ZS25XI  
51-85087  
51-85087  
51-85087  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
51-85087  
51-85087  
51-85087  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
44-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
CY14E102N-BA25XCT  
CY14E102L-BA25XIT  
CY14E102L-BA25XI  
CY14E102L-ZSP25XCT  
CY14E102L-ZSP25XIT  
CY14E102L-ZSP25XI  
CY14E102N-BA25XCT  
CY14E102N-BA25XIT  
CY14E102N-BA25XI  
CY14E102N-ZSP25XCT  
CY14E102N-ZSP25XIT  
CY14E102N-ZSP25XI  
CY14E102L-ZS45XCT  
CY14E102L-ZS45XIT  
CY14E102L-ZS45XI  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
45  
Commercial  
Industrial  
CY14E102L-BA45XCT  
CY14E102L-BA45XIT  
CY14E102L-BA45XI  
CY14E102L-ZSP45XCT  
CY14E102L-ZSP45XIT  
CY14E102L-ZSP45XI  
CY14E102N-BA45XCT  
CY14E102N-BA45XIT  
CY14E102N-BA45XI  
CY14E102N-ZSP45XCT  
CY14E102N-ZSP45XIT  
CY14E102N-ZSP45XI  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
All parts are Pb-free. The above table contains Advance information. Please contact your local Cypress sales representative for availability of these parts.  
Document Number: 001-45755 Rev. *A  
Page 16 of 21  
CY14E102L, CY14E102N  
ADVANCE  
Part Numbering Nomenclature  
CY 14 E 102 L - ZS P 15 X C T  
Option:  
T - Tape & Reel  
Blank - Std.  
Temperature:  
C - Commercial (0 to 70°C)  
I - Industrial (–40 to 85°C)  
Speed:  
Pb-Free  
15 - 15 ns  
20 - 20 ns  
25 - 25 ns  
45 - 45 ns  
Package:  
P - 54 Pin  
Blank - 44 Pin  
BA - 48 FBGA  
ZS - TSOP II  
Data Bus:  
L - x8  
N - x16  
Density:  
102 - 2 Mb  
Voltage:  
E - 5.0V  
NVSRAM  
14 - Auto Store + Software Store + Hardware Store  
Cypress  
Document Number: 001-45755 Rev. *A  
Page 17 of 21  
CY14E102L, CY14E102N  
ADVANCE  
Package Diagrams  
Figure 14. 44-Pin TSOP II  
DIMENSION IN MM (INCH)  
MAX  
MIN.  
PIN 1 I.D.  
22  
1
R
O
E
K
A
X
S G  
EJECTOR PIN  
23  
44  
TOP VIEW  
BOTTOM VIEW  
10.262 (0.404)  
10.058 (0.396)  
0.400(0.016)  
0.300 (0.012)  
0.800 BSC  
(0.0315)  
BASE PLANE  
0.10 (.004)  
0.210 (0.0083)  
0.120 (0.0047)  
0°-5°  
18.517 (0.729)  
18.313 (0.721)  
0.597 (0.0235)  
0.406 (0.0160)  
SEATING  
PLANE  
51-85087-*A  
Document Number: 001-45755 Rev. *A  
Page 18 of 21  
CY14E102L, CY14E102N  
ADVANCE  
Package Diagrams (continued)  
Figure 15. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
A1 CORNER  
Ø0.30 0.05(48X)  
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875  
A
A
0.75  
B
6.00 0.10  
3.75  
B
6.00 0.10  
0.15(4X)  
SEATING PLANE  
C
51-85128-*D  
Document Number: 001-45755 Rev. *A  
Page 19 of 21  
CY14E102L, CY14E102N  
ADVANCE  
Package Diagrams (continued)  
Figure 16. 54-Pin TSOP II  
51-85160-**  
Document Number: 001-45755 Rev. *A  
Page 20 of 21  
ADVANCE  
CY14E102L, CY14E102N  
Document History Page  
Document Title: CY14E102L/CY14E102N 2-Mbit (256K x 8/128K x 16) nvSRAM  
Document Number: 001- 45755  
Orig. of Submission  
REV. ECN NO.  
Description of Change  
Change  
Date  
**  
2470086  
GVCH  
New Data Sheet  
06/27/2008 Added 20 ns access speed information in “Features”.  
Added I for t =20 ns for both industrial and Commercial temperature Grade.  
*A  
2522209 GVCH/  
AESA  
CC1  
RC  
Updated Thermal resistance values for 48-FBGA, 44-TSOP II and 54-TSOP II  
Packages.  
Added AC Switching Characteristics specs for 20 ns access speed.  
Added software controlled STORE/RECALL cycle specs for 20 ns access speed.  
Updated ordering information and part numbering nomenclature.  
Updated data sheet template.  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any  
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,  
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical  
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-45755 Rev. *A  
Revised June 27, 2008  
Page 21 of 21  
AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.  

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