AMD Geode™ LX Processors
Data Book
February 2009
Publication ID: 33234H
AMD Geode™ LX Processors Data Book
Contents
33234H
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.0 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.0 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 GeodeLink™ Control Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 GeodeLink™ Interface Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4 GeodeLink™ Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5 Graphics Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6 Display Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.7 Video Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.8 Video Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.9 GeodeLink™ PCI Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.10 Security Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.0 Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Bootstrap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3 Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.0 GeodeLink™ Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1 MSR Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2 GLIU Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.0 CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1 Core Processor Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.2 Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.3 Application Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.4 System Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.5 CPU Core Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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6.0 Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
6.1 GeodeLink™ Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
6.2 GeodeLink™ Memory Controller Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
6.3 Graphics Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
6.4 Graphics Processor Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
6.5 Display Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
6.6 Display Controller Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
6.7 Video Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
6.8 Video Processor Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
6.9 Video Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
6.10 Video Input Port Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
6.11 Security Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
6.12 Security Block Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
6.13 GeodeLink™ Control Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
6.14 GeodeLink™ Control Processor Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
6.15 GeodeLink™ PCI Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
6.16 GeodeLink™ PCI Bridge Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
7.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
7.1 Electrical Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
7.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
7.3 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
7.4 DC Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
7.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
7.6 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
8.0 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
8.1 General Instruction Set Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
8.2 CPUID Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
8.3 Processor Core Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
8.4 MMX™, FPU, and AMD 3DNow!™ Technology Instructions Sets . . . . . . . . . . . . . . . . . . . . . . 658
9.0 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
9.1 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
Appendix A Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
Order Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
Data Book Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
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List of Figures
Signal Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
BGU481 Ball Assignment Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
GeodeLink™ Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Integrated Functions Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
GLMC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
HOI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
LOI Addressing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
LOI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Request Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
DDR Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
DDR Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
14-Bit Repeated Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Display Controller High-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
GUI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
VGA Frame Buffer Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Graphics Controller High-level Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Write Mode Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Read Mode Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Color Compare Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Graphics Filter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Flicker Filter and Line Buffer Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Interlaced Timing Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Video Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Video Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Downscaler Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Linear Interpolation Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Mixer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Color Key and Alpha-Blending Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
VOP Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
525-Line NTSC Video Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
HBLANK and VBLANK for Lines 20-262, 283-524 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
HBLANK and VBLANK for Lines 1-18, 264-281 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
BT.656 8/16 Bit Line Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Dithered 8x8 Pixel Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
525 line, 60 Hz Digital Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
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Message Passing Data Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
Data Streaming Data Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
BT.601 Mode Default Field Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
BT.601 Mode Programmable Field Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
BT.601 Mode Horizontal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
YUV 4:2:2 to YUV 4:2:0 Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
Dual Buffer for Message Passing and Data Streaming Modes . . . . . . . . . . . . . . . . . . . . . . 476
Security Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Processor Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
GLPCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
Atomic MSR Accesses Across the PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
Simple Round-Robin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
Weighted Round-Robin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
VMEMLX Power Split . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
Drive Level and Measurement Points for Switching Characteristics . . . . . . . . . . . . . . . . . . 607
Drive Level and Measurement Points for Switching Characteristics . . . . . . . . . . . . . . . . . . 608
Power Up Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Drive Level and Measurement Points for Switching Characteristics . . . . . . . . . . . . . . . . . . 609
Drive Level and Measurement Points for Switching Characteristics . . . . . . . . . . . . . . . . . . 610
Drive Level and Measurement Points for Switching Characteristics . . . . . . . . . . . . . . . . . . 611
DDR Write Timing Measurement Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
DDR Read Timing Measurement Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
BGU481 Top/Side View/Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
BGU481 Bottom View/Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
AMD Geode™ LX Processors OPN Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
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Graphics Processor Feature Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Video Signal Definitions Per Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Buffer Type Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Bootstrap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Ball Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Ball Assignments - Sorted by Ball Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Ball Assignments - Sorted Alphabetically by Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Signal Behavior During and After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
MSR Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MSR Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
GLIU Memory Descriptor Address Hit and Routing Description . . . . . . . . . . . . . . . . . . . . . . 48
GLIU I/O Descriptor Address Hit and Routing Description . . . . . . . . . . . . . . . . . . . . . . . . . . 49
GeodeLink™ Device Standard MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
GLIU Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
GLIU P2D Descriptor MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Initialized Core Register Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Segment Register Selection Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
System Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Control Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
CR4 Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
CR3 Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
CR2 Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
CR0 Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Effects of Various Combinations of EM, TS, and MP Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
CPU Core Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
XC_HIST_MSR Exception Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Region Properties Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Read Operations vs. Region Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
LOI - 2 DIMMs, Same Size, 1 DIMM Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Non-Auto LOI - 1 or 2 DIMMs, Different Sizes, 2 DIMM Banks . . . . . . . . . . . . . . . . . . . . . . 214
Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
GLMC Specific MSR Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Graphics Processor Feature Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
LUT (Lookup Table) Load Command Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
AMD Geode™ LX Processors Data Book
7
33234H
List of Tables
Data Only Command Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Pixel Ordering for 4-Bit Pixels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Example Vector Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Example of Monochrome Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
32-bpp 8:8:8:8 Color Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
16-bpp Color Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
8-bpp 3:3:2 Color Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Common Raster Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Graphics Processor Configuration Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
PAT_DATA Usage for Color Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Cursor Display Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Icon Display Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Cursor/Color Key/Alpha Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Video Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
VGA Text Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
VGA Graphics Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Vertical Timing in Number of Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Timing Register Settings for Interlaced Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
DC Configuration Control Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
VGA Block Configuration Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
VGA Block Standard Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
VGA Sequencer Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Font Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
CRTC Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
CRTC Memory Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Graphics Controller Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Attribute Controller Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Extended Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Truth Table for Alpha-Blending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
VOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
SAV/EAV Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Protection Bit Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
SAV VIP Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
8
AMD Geode™ LX Processors Data Book -
List of Tables
33234H
Panel Output Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Register Settings for Dither Enable/Disable Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Video Processor Module Configuration Control Registers Summary . . . . . . . . . . . . . . . . . 412
VIP Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
SAV/EAV Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
VIP Data Types / Memory Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
VIP Configuration/Control Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
EEPROM Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Security Block Specific MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
TAP Instruction Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
GLCP Specific MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
Format for Accessing the Internal PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . 569
Standard GeodeLink™ Device MSRs Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
GLPCI Specific Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Region Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
AMD Geode LX [email protected] Processor DC Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
AMD Geode LX [email protected] Processor DC Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
AMD Geode LX [email protected] Processor DC Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
AMD Geode LX [email protected] Processor DC Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
PCI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
VIP Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
CRT Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
JTAG Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
General Instruction Set Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
Instruction Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
Instruction Prefix Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
w Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
d Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
s Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
eee Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
General Registers Selected by mod r/m Fields and w Field . . . . . . . . . . . . . . . . . . . . . . . . 623
sreg2 Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
AMD Geode™ LX Processors Data Book
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33234H
List of Tables
sreg3 Field (FS and GS Segment Register Selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
index Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
mod base Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
CPUID Instruction with EAX = 00000000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
CPUID Instruction with EAX = 00000001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
CPUID Instruction with EAX = 80000000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
CPUID Instruction with EAX = 80000001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
CPUID Instruction with EAX = 80000005h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
CPUID Instruction with EAX = 80000006h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Processor Core Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
FPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
AMD 3DNow!™ Technology Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
Valid OPN Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
Edits to Current Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
10
AMD Geode™ LX Processors Data Book -
Overview
33234H
1.0Overview
1
1.1
General Description
AMD Geode™ LX processors are integrated x86 proces-
sors specifically designed to power embedded devices for
entertainment, education, and business. Serving the needs
of consumers and business professionals alike, it’s an
excellent solution for embedded applications, such as thin
clients, interactive set-top boxes, single board computers,
and mobile computing devices.
While the processor core provides maximum compatibility
with the vast amount of Internet content available, the intel-
ligent integration of several other functions, including
graphics and video datapaths, offers a true system-level
multimedia solution.
For implementation details and suggestions for this device,
see the supporting documentation (i.e., application notes,
schematics, etc.) on the AMD Embedded Developer Sup-
Available with a core voltage of 1.2V, 1.25V, or 1.4V it offers
extremely low typical power consumption leading to longer
battery life and enabling small form-factor, fanless designs.
Clock Module
CPU Core
Graphics Processor (GP)
SYSREF
64 KB L1 I-cache
System PLL
BLT Engine
Integer
MMU
1 KB
LUT
FPU
Unit
Load/Store
64 KB L1 D-cache
ROP Unit
CPU PLL
DOTREF
SDCLKs
TLB
Bus Controller
Alpha Compositing
Rotation BLT
DOTCLK PLL
128 KB L2 cache
GeodeLink™
Memory
Controller (GLMC)
GeodeLink™ Interface Unit 0
(GLIU0)
64-Bit
DDR
64-bit DDR SDRAM
Display Controller (DC)
Compression Buffer
GeodeLink™
Control
Processor (GLCP)
GeodeLink™ Interface Unit 1
(GLIU1)
Palette RAM
Timing
Test/Reset
Interface
Power Mgmnt
Graphics Filter/Scaling
HW VGA
Test
Diagnostic
Companion I/F
AMD Geode™
Companion
Device
RGB
YUV
Video Processor (VP)
Security Block
TFT
Controller/
Video
Output
Port (VOP)
GeodeLink™
PCI Bridge
(GLPCI)
Video Scalar
Video Input
Port (VIP)
128-bit AES
(CBC/ECB)
Video Mixer
True
Random Number
Generator
Alpha Blender
3x8-Bit DAC
CRT
TFT/VOP
VIP
PCI
EEPROM on package
(optional)
Figure 1-1. Internal Block Diagram
AMD Geode™ LX Processors Data Book
11
33234H
Overview
■ Power Management:
1.2
Features
— LX [email protected] processor* (Unterminated):
Total Dissipated Power (TDP) 5.1W,
2.6W typical @ 600 MHz max power
— LX [email protected] processor* (Unterminated):
Total Dissipated Power (TDP) 3.6W,
1.8W typical @ 500 MHz max power
— LX [email protected] processor* (Unterminated):
Total Dissipated Power (TDP) 3.1W,
1.3W typical @ 433 MHz max power
— LX [email protected] processor* (Unterminated):
Total Dissipated Power (TDP) 2.8W,
1.2W typical @ 366 MHz max power
General Features
■ Functional blocks include:
— CPU Core
— GeodeLink™ Control Processor
— GeodeLink Interface Units
— GeodeLink Memory Controller
— Graphics Processor
— Display Controller
— Video Processor
– TFT Controller/Video Output Port
— Video Input Port
— GeodeLink active hardware power management
— Hardware support for standard ACPI software power
management
— GeodeLink PCI Bridge
— Security Block
— I/O companion SUSP/SUSPA power controls
— Lower power I/O
— Wakeup on SMI/INTR
■ 0.13 micron process
■ Packaging:
— 481-Terminal BGU (Ball Grid Array Cavity Up) with
internal heatspreader
■ Works in conjunction with the AMD Geode™ CS5536
(USB 2.0) or CS5535 (USB 1.1) companion device
■ Single packaging option supports all features
GeodeLink™ Architecture
■ Industrial temperature range available for the
LX [email protected] processor*
■ High bandwidth packetized uni-directional bus for
internal peripherals
CPU Processor Features
■ Standardized protocol to allow variants of products to be
■ x86/x87-compatible CPU core
developed by adding or removing modules
■ Performance:
■ GeodeLink Control Processor (GLCP) for diagnostics
— Processor frequency: up to 600 MHz
— Dhrystone 2.1 MIPs: 150 to 450
— Fully pipelined FPU
and scan control
■ Dual GeodeLink Interface Units (GLIUs) for device inter-
connect
■ Split I/D cache/TLB (Translation Look-aside Buffer):
— 64 KB I-cache/64 KB D-cache
GeodeLink™ Memory Controller
— 128 KB L2 cache configurable as I-cache, D-cache,
or both
■ Integrated memory controller for low latency to CPU and
on-chip peripherals
■ Efficient prefetch and branch prediction
■ 64-bit wide DDR SDRAM bus operating frequency:
■ Integrated FPU that supports the MMX™ and
— 200 MHz, 400 MT/S
AMD 3DNow!™ instruction sets
■ Supports unbuffered DDR DIMMS using up to 2 GB
■ Fully pipelined single precision FPU hardware with
DRAM technology
microcode support for higher precisions
■ Supports up to 2 DIMMS (16 devices max)
GeodeLink™ Control Processor
2D Graphics Processor
■ High performance 2D graphics controller
■ Alpha BLT
■ JTAG interface:
— ATPG, Full Scan, BIST on all arrays
— 1149.1 Boundary Scan compliant
®
■ ICE (in-circuit emulator) interface
■ Windows GDI GUI acceleration:
— Hardware support for all Microsoft RDP codes
■ Command buffer interface for asynchronous BLTs
■ Second pattern channel support
■ Reset and clock control
■ Designed for improved software debug methods and
performance analysis
■ Hardware screen rotation
*The AMD Geode LX [email protected] processor operates at 600 MHz, the AMD Geode LX [email protected] processor operates at 500 MHz, the
AMD Geode LX [email protected] processor operates at 433 MHz and the AMD Geode LX [email protected] processor operates at 366 MHz. Model
numbers reflect performance as described here: http://www.amd.com/connectivitysolutions/geodelxbenchmark.
12
AMD Geode™ LX Processors Data Book
Overview
33234H
Display Controller
GeodeLink™ PCI Bridge
■ Hardware frame buffer compression improves Unified
■ PCI 2.2 compliant
Memory Architecture (UMA) memory efficiency
■ 3.3V signaling and 3.3V I/Os
■ 33 to 66 MHz operation
■ CRT resolutions supported:
— Supports up to 1920x1440x32 bpp at 85 Hz
— Supports up to 1600x1200x32 bpp at 100 Hz
■ 32-bit interface
■ Supports up to 1600x1200x32 bpp at 60 Hz for TFT
■ Supports virtual PCI headers for GeodeLink devices
■ Standard Definition (SD) resolution for Video Output
Port (VOP):
Video Input Port (VIP)
— 720x482 at 59.94 Hz interlaced for NTSC
— 768x576 at 50 Hz interlaced for PAL
■ VESA 1.1 and 2.0 compliant, 8 or 16-bit
■ Video Blanking Interval (VBI) support
■ 8 or 16-bit 80 MHz SD or HD capable
■ High Definition (HD) resolution for Video Output Port
(VOP):
— Up to 1920x1080 at 30 Hz interlaced (1080i HD)
(74.25 MHz)
Security Block
— Up to 1280x720 at 60 Hz progressive (720p HD)
(74.25 MHz)
■ Serial EEPROM interface for 2K bit unique ID and AES
(Advanced Encryption Standard) hidden key storage
(EEPROM optional inside package)
■ Supports down to 7.652 MHz Dot Clock (320x240
QVGA)
■ Electronic Code Book (ECB) or Cipher Block Chaining
(CBC)128-bit AES hardware support
■ Hardware VGA
■ True random number generator (TRNG)
■ Hardware supported 48x64 32-bit cursor with alpha
blending
Video Processor
■ Supports video scaling, mixing and VOP
■ Hardware video up/down scalar
■ Graphics/video alpha blending and color key muxing
■ Digital VOP (SD and HD) or TFT outputs
■ Legacy RGB mode
■ VOP supports SD and HD 480p, 480i, 720p, and 1080i
■ VESA 1.1, 2.0 and BT.601 24-bit (out only), BT.656
compliant
Integrated Analog CRT DAC, System Clock PLLs and
Dot Clock PLL
■ Integrated Dot Clock PLL with up to 350 MHz clock
■ Integrated 3x8-bit DAC with up to 350 MHz sampling
■ Integrated x86 core PLL
■ Memory PLL
AMD Geode™ LX Processors Data Book
13
33234H
Overview
14
AMD Geode™ LX Processors Data Book
Architecture Overview
33234H
2.0Architecture Overview
2
The CPU Core provides maximum compatibility with the
vast amount of Internet content available while the intelli-
gent integration of several other functions, including graph-
ics, makes the AMD Geode™ LX processor a true system-
level multimedia solution.
2.1.1
Integer Unit
The Integer Unit consists of a single issue 8-stage pipeline
and all the necessary support hardware to keep the pipe-
line running efficiently.
The instruction pipeline in the integer unit consists of eight
stages:
The AMD Geode LX processor can be divided into major
1) Instruction Prefetch - Raw instruction data is fetched
• CPU Core
from the instruction memory cache.
• GeodeLink™ Control Processor
• GeodeLink Interface Units
• GeodeLink Memory Controller
• Graphics Processor
• Display Controller
2) Instruction Pre-decode - Prefix bytes are extracted
from raw instruction data. This decode looks-ahead to
the next instruction and the bubble can be squashed if
the pipeline stalls down stream.
• Video Processor
— TFT Controller/Video Output Port
• Video Input Port
• GeodeLink PCI Bridge
• Security Block
3) Instruction Decode - Performs full decode of instruc-
tion data. Indicates instruction length back to the
Prefetch Unit, allowing the Prefetch Unit to shift the
appropriate number of bytes to the beginning of the
next instruction.
4) Instruction Queue - FIFO containing decoded x86
instructions. Allows Instruction Decode to proceed
even if the pipeline is stalled downstream. Register
reads for data operand address calculations are per-
formed during this stage.
2.1
CPU Core
The x86 core consists of an Integer Unit, cache memory
subsystem, and an x87 compatible FPU (Floating Point
Unit). The Integer Unit contains the instruction pipeline and
associated logic. The memory subsystem contains the
instruction and data caches, translation look-aside buffers
(TLBs), and an interface to the GeodeLink Interface Units
(GLIUs).
5) Address Calculation #1 - Computes linear address of
operand data (if required) and issues request to the
Data Memory Cache. Microcode can take over the
pipeline and inject a micro-box here if multi-box
instructions require additional data operands.
The instruction set supported by the core is a combination
of Intel Pentium processor, AMD Athlon™ processor, and
AMD Geode LX processor specific instructions. Specifi-
cally, it supports the Pentium, Pentium Pro, AMD 3DNow!™
technology and MMX™ instructions for the AMD Athlon
®
6) Address Calculation #2 - Operand data (if required)
is returned and set up to the Execution stage with no
bubbles if there was a data cache hit. Segment limit
checking is performed on the data operand address.
The µROM is read for setup to Execution Unit.
processor. It supports
a
subset of the specialized
AMD Geode LX processor instructions including special
SMM instructions. The CPU Core does not support the
entire Katmai New Instruction (KNI) set as implemented in
the Pentium 3. It does support the MMX instructions for the
7) Execution Unit - Register and/or data memory fetch
fed through the Arithmetic Logic Unit (ALU) for arith-
metic or logical operations. µROM always fires for the
first instruction box down the pipeline. Microcode can
take over the pipeline and insert additional boxes here
if the instruction requires multiple Execution Unit
stages to complete.
AMD Athlon processor, which are
Pentium 3 KNI instructions.
a
subset of the
8) Writeback - Results of the Execution Unit stages are
written to the register file or to data memory.
AMD Geode™ LX Processors Data Book
15
33234H
Architecture Overview
integer core. The datapath is optimized for single precision
arithmetic. Extended precision instructions are handled in
microcode and require multiple passes through the pipe-
line. There is an execution pipeline and a load/store pipe-
line. This allows load/store operations to execute in parallel
with arithmetic instructions.
2.1.2
Memory Management Unit
The memory management unit (MMU) translates the linear
address supplied by the integer unit into a physical address
to be used by the cache unit and the internal bus interface
unit. Memory management procedures are x86-compati-
ble, adhering to standard paging mechanisms.
The MMU also contains a load/store unit that is responsible
for scheduling cache and external memory accesses. The
load/store unit incorporates two performance-enhancing
features:
2.2
GeodeLink™ Control Processor
The GeodeLink Control Processor (GLCP) is responsible
for reset control, macro clock management, and debug
support provided in the Geode LX processor. It contains
the JTAG interface and the scan chain control logic. It sup-
ports chip reset, including initial PLL control and program-
ming and runtime power management macro clock control.
• Load-store reordering gives memory reads required by
the integer unit a priority over writes to external memory.
• Memory-read bypassing eliminates unnecessary
memory reads by using valid data from the execution
unit.
The JTAG support includes a TAP Controller that is IEEE
1149.1 compliant. CPU control can be obtained through
the JTAG interface into the TAP Controller, and all internal
registers, including CPU Core registers, can be accessed.
In-circuit emulation (ICE) capabilities are supported
through this JTAG and TAP Controller interface.
2.1.3
Cache and TLB Subsystem
The cache and TLB subsystem of the CPU Core supplies
the integer pipeline with instructions, data, and translated
addresses (when necessary). To support the efficient deliv-
ery of instructions, the cache and TLB subsystem has a
single clock access 64 KB 16-way set associative instruc-
tion cache and a 16-entry fully associative TLB. The TLB
performs necessary address translations when in protected
mode. For data, there is a 64 KB 16-way set associative
writeback cache, and a 16-entry fully associative TLB.
When there is a miss to the instruction or data TLBs, there
is a second level unified (instruction and data) 64-entry 2-
way set associative TLB that takes an additional clock to
access. When there is a miss to the instruction or data
caches or the TLB, the access must go to the GeodeLink
Memory Controller (GLMC) for processing. Having both an
instruction and a data cache and their associated TLBs
improves overall efficiency of the integer unit by enabling
simultaneous access to both caches.
The GLCP also includes the companion device interface.
The companion device has several unique signals con-
nected to this module that support Geode LX processor
reset, interrupts, and system power management.
2.3
GeodeLink™ Interface Units
Together, the two GeodeLink Interface Units (GLIU0 and
GLIU1) make up the internal bus derived from the
GeodeLink architecture. GLIU0 connects five high band-
width modules together with a seventh link to GLIU1 that
connects to the five low bandwidth modules.
2.4
GeodeLink™ Memory Controller
The GeodeLink Memory Controller (GLMC) is the source
for all memory needs in a typical Geode LX processor sys-
tem. The GLMC supports a memory data bus width of 64
bits and supports 200 MHz, 400 MT/S for DDR (Double
Data Rate).
The L1 caches are supported by a 128 KB unified L2 victim
cache. The L2 cache can be configured to hold data,
instructions, or both. The L2 cache is 4-way set associa-
tive.
The modules that need memory are the CPU Core, Graph-
ics Processor, Display Controller, Video Input Port, and
Security Block. Because the GLMC supports memory
needs for both the CPU Core and the display subsystem,
the GLMC is classically called a UMA (Unified Memory
Architecture) subsystem. PCI accesses to main memory
are also supported.
2.1.4
Bus Controller Unit
The bus controller unit provides a bridge from the proces-
sor to the GLIUs. When external memory access is
required, due to a cache miss, the physical address is
passed to the bus controller unit, that translates the cycle
to a GeodeLink cycle.
Up to four banks, with eight devices maximum in each bank
of SDRAM, are supported with up to 512 MB in each bank.
Four banks means that one or two DIMM or SODIMM mod-
ules can be used in a AMD Geode LX processor system.
Some memory configurations have additional restrictions
on maximum device quantity.
2.1.5
Floating Point Unit
The Floating Point Unit (FPU) is a pipelined arithmetic unit
that performs floating point operations as per the IEEE 754
standard. The instruction sets supported are x87, MMX,
and AMD 3DNow! technology. The FPU is a pipelined
machine with dynamic scheduling of instructions to mini-
mize stalls due to data dependencies. It performs out of
order execution and register renaming. It is designed to
support an instruction issue rate of one per clock from the
16
AMD Geode™ LX Processors Data Book
Architecture Overview
33234H
• Hardware accelerated rotation BLTs
• Color depth conversion
2.5
Graphics Processor
The Graphics Processor is based on the graphics proces-
sor used in the AMD Geode GX processor with several fea-
tures added to enhance performance and functionality. Like
its predecessor, the AMD Geode LX processor’s Graphics
Processor is a BitBLT/vector engine that supports pattern
generation, source expansion, pattern/source transpar-
ency, 256 ternary raster operations, alpha blenders to sup-
port alpha-BLTs, incorporated BLT FIFOs, a GeodeLink
interface and the ability to throttle BLTs according to video
timing. Features added to the Graphics Processor include:
• Paletized color
• Full 8x8 color pattern buffer
• Channel 3 - third DMA channel
• Monochrome inversion
Processor features of the AMD Geode GX and LX proces-
sors.
• Command buffer interface
Table 2-1. Graphics Processor Feature Comparison
Feature
AMD Geode™ GX Processor
AMD Geode™ LX Processor
Color Depth
8, 16, 32 bpp
8, 16, 32 bpp (A) RGB 4 and 8-bit indexed
ROPs
256 (src, dest, pattern)
256 (2-src, dest and pattern)
BLT Buffers
FIFOs in Graphics Processor
FIFOs in Graphics Processor
BLT Splitting
Managed by hardware
Managed by hardware
Video Synchronized BLT/Vector
Bresenham Lines
Patterned (stippled) Lines
Screen to Screen BLT
Throttle by VBLANK
Throttle by VBLANK
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Screen to Screen BLT with
mono expansion
Memory to Screen BLT
Accelerated Text
Yes (through CPU writes)
Yes (throttled rep movs writes)
No
No
Pattern Size (Mono)
Pattern Size (Color)
8x8 pixels
8x8 pixels
8x8 pixels
8x1 (32 pixels)
8x2 (16 pixels)
8x4 (8 pixels)
Monochrome Pattern
Dithered Pattern (4 color)
Color Pattern
Yes
Yes (with inversion)
No
No
8, 16, 32 bpp
8, 16, 32 bpp
Transparent Pattern
Solid Fill
Monochrome
Monochrome
Yes
Yes
Pattern Fill
Yes
Yes
Transparent Source
Color Key Source Transparency
Variable Source Stride
Variable Destination Stride
Destination Write Bursting
Selectable BLT Direction
Alpha BLT
Monochrome
Monochrome
Y with mask
Y with mask
Yes
Yes
Yes
Yes
Yes
Yes
Vertical and Horizontal
Vertical and Horizontal
Yes (constant α, α/pix, or sep. α channel)
Decodes VGA Register
Unlimited
Yes (constant α or α/pix)
VGA Support
Decodes VGA Register
Pipeline Depth
2 ops
No
Accelerated Rotation BLT
Color Depth Conversion
8, 16, 32 bpp
No
5:6:5, 1:5:5:5, 4:4:4:4, 8:8:8:8
AMD Geode™ LX Processors Data Book
17
33234H
Architecture Overview
2.7.2
TFT Controller
2.6
Display Controller
The TFT Controller converts the digital RGB output of a
Video Mixer block to the digital output suitable for driving a
TFT flat panel LCD.
The Display Controller performs the following functions:
1) Retrieves graphics, video, and cursor data.
2) Serializes the streams.
The flat panel connects to the RGB port of the Video Mixer.
It interfaces directly to industry standard 18-bit or 24-bit
active matrix thin film transistor (TFT). The digital RGB or
video data that is supplied by the video logic is converted
into a suitable format to drive a wide range of panels with
variable bits. The LCD interface includes dithering logic to
increase the apparent number of colors displayed for use
on panels with less than 6 bits per color. The LCD interface
also supports automatic power sequencing of panel power
supplies.
3) Performs any necessary color lookups and output for-
matting.
4) Interfaces to the Video Processor for driving the dis-
play device(s).
The Display Controller consists of a memory retrieval sys-
tem for rasterized graphics data, a VGA, and a back-end fil-
ter. The AMD Geode LX processor’s Display Controller
corresponds to the Display Controller function found in the
AMD Geode GX processor with additional hardware for
graphics filter functions. The VGA provides full hardware
compatibility with the VGA graphics standard. The raster-
ized graphics and the VGA share a single display FIFO and
display refresh memory interface to the GeodeLink Mem-
ory Controller (GLMC). The VGA uses 8 bpp and syncs,
that are expanded to 24 bpp via the color lookup table, and
passes the information to the graphics filter for scaling and
interlaced display support. The stream is then passed to
the Video Processor, which is used for video overlay. The
Video Processor forwards this information to the DAC (Dig-
ital-to-Analog Converter), that generates the analog red,
green, and blue signals, and buffers the sync signals that
are then sent to the display. The Video Processor output
can also be rendered as YUV data, and can be output on
the Video Output Port (VOP).
It supports panels up to a 24-bit interface and up to
1600x1200 resolution.
The TFT Controller interfaces with the CPU Core via a
GLIU master/slave interface. The TFT Controller is both a
GLIU master and slave.
2.7.3
Video Output Port
The VOP receives YUV 4:4:4 encoded data from the Video
Processor and formats the data into a video stream that is
BT.656 compliant. Output from the VOP goes to either a
VIP or a TV encoder. The VOP is BT.656/601 compliant
since its output may go directly (or indirectly) to a display.
2.8
Video Input Port
The Video Input Port (VIP) receives 8- or 16-bit video or
ancillary data, 8-bit message data, or 8-bit raw video and
passes it to data buffers located in system memory. The
VIP is a DMA engine. The primary operational mode is as a
compliant VESA 2.0 slave. The VESA 2.0 specification
defines the protocol for receiving video, VBI, and ancillary
data. The addition of the message passing and data
streaming modes provides additional flexibility in receiving
non-VESA 2.0 compliant data streams. Input data is
packed into QWORDS, buffered into a FIFO, and sent to
system memory over the GLIU. The VIP masters the inter-
nal GLIU and transfers the data from the FIFO to system
memory. The maximum input data rate (8- or 16-bits) is 150
MHz.
2.7
Video Processor
The Video Processor mixes the graphics and video
streams, and outputs either digital RGB data to the internal
DACs or the flat panel interface, or digital YUV data via the
VOP interface.
The Video Processor delivers high-resolution and true-
color graphics. It can also overlay or blend a scaled true-
color video image on the graphic background.
The Video Processor interfaces with the CPU Core via a
GLIU master/slave interface. The Video Processor is a
slave only, as it has no memory requirements.
2.7.1
CRT Interface
2.9
GeodeLink™ PCI Bridge
The internal high performance DACs support CRT resolu-
tions up to:
The GeodeLink PCI Bridge (GLPCI) contains all the neces-
sary logic to support an external PCI interface. The PCI
interface is PCI v2.2 specification compliant. The logic
includes the PCI and GLIU interface control, read and write
FIFOs, and a PCI arbiter.
— 1920x1440x32 bpp at 85 Hz
— 1600x1200x32 bpp at 100 Hz
18
AMD Geode™ LX Processors Data Book
Architecture Overview
33234H
set of interrupt registers. The AES module has two key
sources: one hidden 128-bit key stored in the “on-package”
EEPROM, and a write only 128-bit key (reads as all zeros).
The hidden key is loaded automatically by the hardware
after reset and is not visible to the processor. The
EEPROM can be locked. The initialization vector for the
CBC mode can be generated by the True Random Number
Generator (TRNG). The TRNG is addressable separately
and generates a 32-bit random number.
2.10 Security Block
The AMD Geode LX processor has an on-chip AES 128-bit
crypto acceleration block capable of 44 Mbps throughput
on either encryption or decryption at a processor speed of
500 MHz. The AES block runs asynchronously to the pro-
cessor core and is DMA based. The AES block supports
both EBC and CBC modes and has an interface for
accessing the optional EEPROM memory for storing
unique IDs and/or security keys. The AES and EEPROM
sections have separate control registers but share a single
AMD Geode™ LX Processors Data Book
19
33234H
Architecture Overview
20
AMD Geode™ LX Processors Data Book
Signal Definitions
33234H
3.0Signal Definitions
3
This chapter defines the signals and describes the external interface of the AMD Geode™ LX processor. Figure 3-1 shows
the pins organized by their functional groupings. Where signals are multiplexed, the default signal name is listed first and is
AD[31:0]
CBE[3:0]#
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
SYSREF
DOTREF
INTA#
IRQ13 (STRAP)
CIS
AMD Geode™
LX Processor
PCI
System
Interface
Signals
Interface
Signals
SUSPA# (STRAP)
PW[1:0] (STRAP)
TDP
PAR
REQ[2:0]#
(STRAP) GNT[2:0]#
TDN
RESET#
(Total of 32) VCORE
(Total of 30) VIO
(Total of 33) VMEM
(Total of 128) VSS
Power/Ground
Interface
Signals
SDCLK[5:0]P
SDCLK[5:0]N
MVREF
CKE[1:0]
CS[3:0]#
RAS[1:0]#
CAS[1:0]#
WE[1:0]#
BA[1:0]
MA[13:0]
TLA[1:0]
DQS[7:0]
DQM[7:0]
DQ[63:0]
DOTCLK+VOPCLK
DRGB[31:26]+VID[15:10]
Memory
Interface
Signals
DRGB[25:24]+VID[9:8]+
MSGSTART+MSGSTOP
DRGB[23:16]
DRBG[15:8]+VOP[15:8]
DRGB[7:0]+VOP[7:0]
HSYNC+VOP_HSYNC
VSYNC+VOP_VSYNC
VDDEN+VIP_HSYNC
LDEMOD+VIP_VSYNC
DISPEN+VOP_BLANK
Display (TFT Option)
Interface
Signals
VAVDD, CAVDD, MAVDD
VAVSS, CAVSS, MAVSS
PLL
Interface
Signals
CLPF
MLPF
VLPF
VIPCLK
VID[7:0]
VIPSYNC
VIP
Interface
Signals
DVREF
DRSET
(Total of 4) DAVDD
(Total of 4) DAVSS
RED
Internal Test
and
Measurement
Interface
Signals
TCLK
TMS
TDI
Display (CRT Option)
Interface
Signals
TDO
TDBGI
TDBGO
GREEN
BLUE
HSYNC
VSYNC
Figure 3-1. Signal Groups
AMD Geode™ LX Processors Data Book
21
33234H
Signal Definitions
Table 3-1. Video Signal Definitions Per Mode
RGB w/16-bit
VIP
ARGB (Note 1)
w/8-bit VIP
TFT w/16-bit VIP
(not 601)
8- or 16-bit VOP
w/16-bit VIP
Signal Name
CRT w/16-bit VIP
RED
RED
GREEN
GREEN
BLUE
BLUE
DRGB[31:24] (I/O)
DRGB[23:16] (O)
DRGB[15:8] (O)
DRGB[7:0] (O)
DOTCLK (O)
HSYNC (O)
VSYNC (O)
DISPEN (O)
VDDEN (I/O)
LDEMOD (I/O)
VID[7:0] (I)
VID[15:8] (I)
R[7:0]
VID[15:8] (I)
R[7:0]
Alpha
R[7:0]
VID[15:8] (I)
R[7:0] (Note 2)
G[7:0] (Note 2)
B[7:0] (Note 2)
DOTCLK (O)
VOP_HSYNC (O)
VSYNC (O)
DISPEN (O)
VDDEN (O)
LDEMOD (O)
VID[7:0]
VID[15:8] (I)
Driven low
G[7:0]
G[7:0]
G[7:0]
VOP[15:8] (O)
VOP[7:0] (O)
VOPCLK (O)
VOP_HSYNC (O)
VOP_VSYNC (O)
VOP_BLANK (O)
VIP_HSYNC (I)
VIP_VSYNC (I)
VID[7:0]
B[7:0]
B[7:0]
B[7:0]
DOTCLK (O)
HSYNC (O)
VSYNC (O)
DOTCLK (O)
HSYNC (O)
VSYNC (O)
DOTCLK (O)
HSYNC (O)
VSYNC (O)
VIP_HSYNC (I)
VIP_VSYNC (I)
VID[7:0]
VIP_HSYNC (I)
VIP_VSYNC (I)
VID[7:0]
VIP_HSYNC (I)
VIP_VSYNC (I)
VID[7:0]
VIPCLK (I)
VIPCLK
VIPCLK
VIPCLK
VIPCLK
VIPCLK
VIPSYNC (I)
VIPSYNC
VIPSYNC
VIPSYNC
VIPSYNC
VIPSYNC
Note 1. Alpha RED/GREEN/BLUE: Useful for off-chip graphics digital interfaces.
Note 2. Pin usage depends on TFT mode. See Section 6.7.7 "Flat Panel Display Controller" on page 405 for details.
22
AMD Geode™ LX Processors Data Book
Signal Definitions
33234H
PU/PD: Indicates if an internal, programmable pull-up or
pull-down resistor may be present.
3.1
Buffer Types
column labeled “Buffer Type”. The details of each buffer
Current High/Low (mA): This column gives the current
source/sink capacities when the voltage at the pin is high,
and low. The high and low values are separated by a “/”
and values given are in milli-amps (mA).
TS: Indicates whether the buffer may be put into the TRI-
STATE mode. Note some pins that have buffer types that
allow TRI-STATE may never actually enter the TRI-STATE
mode in practice, since they may be inputs or provide other
signals that are always driven. To determine if a particular
signal can be put in the TRI-STATE mode, consult the indi-
vidual signal descriptions in Section 3.4 "Signal Descrip-
Rise/Fall @ Load: This column indicates the rise and fall
times for the different buffer types at the load capacitance
indicated. These measurements are given in two ways:
rise/fall time between the 20%-80% voltage levels, or, the
rate of change the buffer is capable of, in volts-per-nano-
second (V/ns).
Note the presence of “Wire” type buffer in this table. Sig-
nals identified as a wire-type are not driven by a buffer,
hence no rise/fall time or other measurements are given;
tion indicates a direct connection to internal circuits such
as power, ground, and analog signals.
OD: Indicates if the buffer is open-drain, or not. Open-drain
outputs may be wire ORed together and require a discrete
pull-up resistor to operate properly.
5VT: Indicates if the buffer is 5-volt tolerant, or not. If it is 5-
volt tolerant, then 5 volt TTL signals may be safely applied
to this pin.
Table 3-2. Buffer Type Characteristics
Current
High/Low
(mA)
Name
TS
OD
5VT
PU/PD
Rise/Fall @ Load
24/Q3
24/Q5
24/Q7
5V
X
X
X
X
X
X
X
X
24/24
24/24
24/24
16/16
0.5/1.5
10/10
3 ns @ 50 pF
5 ns @ 50 pF
7 ns @ 50 pF
1.25V/ns @ 40 pF
1-4V/ns @ 10 pF
8.5V/ns @ 15 pF
2.4V/ns @ 50 pF
NA
X
PCI
DDRCLK
DDR
Wire
NA
NA
NA
NA
AMD Geode™ LX Processors Data Book
23
33234H
Signal Definitions
3.2
Bootstrap Options
3.3
Ball Assignments
The tables in this chapter use several common abbrevia-
the AMD Geode LX processor for configuring the system.
Table 3-3. Bootstrap Options
Table 3-4. Ball Type Definitions
Pins
Description
Mnemonic
Definition
IRQ13
0: Normal boot operation, TAP reset
active during PCI reset
A
Analog
I
Input ball
1: Debug stall of CPU after CPU
I/O
Bidirectional ball
Core PLL Ground ball: Analog
reset, TAP reset active until V valid
IO
CAV
CAV
DAV
DAV
SS
DD
SS
DD
PW1
0: PCI (SYSREF) is 33 MHz
1: PCI (SYSREF) is 66 MHz
Core PLL Power ball: Analog
DAC PLL Ground ball: Analog
DAC PLL Power ball: Analog
GLIU PLL Ground ball: Analog
GLIU PLL Power ball: Analog
PW0,
SUSPA#,
GNT[2:0]#
Select CPU and GeodeLink system
MHz options including a PLL bypass
556 for programming.
MAV
MAV
O
SS
DD
Output ball
VAV
VAV
Video PLL Ground ball: Analog
SS
DD
Video PLL Power ball: Analog
Power ball: 1.2V (Nominal)
I/O Power ball: 3.3V (Nominal)
Power ball: 2.5V
V
V
V
V
#
CORE
IO
MEM
SS
Ground ball
The “#” symbol at the end of a signal
name indicates that the active, or
asserted state, occurs when the sig-
nal is at a low voltage level. When “#”
is not present after the signal name,
the signal is asserted when at a high
voltage level.
24
AMD Geode™ LX Processors Data Book
Signal Definitions
33234H
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A
B
A
VSS VMEM VSS DQ21 VSS DQM2 DQ22 VSS DQ28 DQS3 VSS DQ26 DQ31 VMEM DQ32 VSS DQ37 VMEM DQM4 DQ39 VSS DQ40 DQ41 VSS DQ42 DQ43 VSS WE1# VSS VMEM VSS
VMEM VSS VSS DQ17 VMEM DQ18 DQ23 VMEM DQ24 DQM3 VMEM DQ27 TLA1 VSS TLA0 DQ36 DQ33 VSS DQ34 DQ38 VMEM DQ35 DQS5 VMEM DQ46 DQ47 VMEM CS0# VSS VSS VMEM
B
C
C
VSS VSS VMEM VSS MA12 DQS2 VMEM DQ19 DQ29 DQ25 DQ30 VSS
MA3 VMEM MA2 MA0 MA1 VMEM DQS4 BA1 VSS DQ44 DQ45 DQM5 VMEM RAS0# WE0# VSS VMEM VSS VSS
D
D
DQ20 DQ16 VSS VMEM MA11 MA9 VSS MA7 MA8 VSS MA5 MA6 MA4 VSS VCORE VSS VCORE VSS MA10 SDK5P SDK5N VSS SDK4P SDK4N VSS BA0 RAS1# VMEM VSS CS3# DQ48
E
E
VSS VMEM DQ11 CKE0
DQ15 DQ14 DQ10 CKE1
DQ13 DQM1 VMEM VSS
CAS0# CAS1# VMEM VSS
CS1# CS2# MA13 DQ49
VSS VMEM DQ52 DQ53
SDK3N DQM6 VSS VMEM
SDK3P DQS6 DQ55 DQ54
VSS VMEM DQ50 DQ51
SDK2N DQ60 VSS VMEM
SDK2P DQ61 DQ57 DQ56
VSS VMEM DQM7 DQS7
VSS VMEM DQ62 VSS
VCORE DQ63 DQ58 DQ59
VSS VSS VSS VSS
VCORE VCORE VCOREVCORE
VCORE MLPF MAVSS MAVDD
VSS CLPF CAVSS CAVDD
F
F
G
G
H
H
VMEM VSS DQS1 SDK1N
DQ9 DQ8 DQ12 SDK1P
J
J
K
K
DQ7 DQ3 VMEM VSS
VMEM VSS DQ6 SDK0N
AMD Geode™
L
L
M
M
N
DQM0 DQS0 DQ2 SDK0P
DQ5 DQ1 VSS VMEM
MVREF DQ0 DQ4 VSS
VSS VSS VSS VSS
VCORE VCORE VCORE VCORE
DAVDD BLUE DAVSS VCORE
DAVDD GREEN DAVSS DAVDD
DVREF DAVSS RED DAVDD
N
VCORE VCORE VSS VSS VSS VCORE VCORE
VCORE VCORE VSS VSS VSS VCORE VCORE
VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS
VCORE VCORE VSS VSS VSS VCORE VCORE
VCORE VCORE VSS VSS VSS VCORE VCORE
P
P
R
R
T
T
U
U
V
V
W
Y
W
Y
DRSET DAVSS VIO
VSS
VCORE VSS RESET# SYREF
s
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
GNT0# REQ0# VSS
VIO
VAVDD VAVSS VLPF TMS
DOTREF TDBGI TDI TDBGO
LX Processor
s
REQ2# IRQ13 GNT1# REQ1#
s
s
s
TDO TCLK VIO
VIO VSS VSYNC LDEMOD
DOTCLK VDEN HSYNC DISPEN
DRB17 DRB16 VIO VSS
VIO VSS DRB18 DRB19
DRB20 DRB21 DRB22 VSS DRB11 VSS DRB0 DRB6 VSS DRB29 DRB24 VSS VID3 VSS VCORE VSS VCORE VSS AD1 VSS AD5 AD11 VSS AD14 IRDY# VSS CBE2# VSS AD23 AD22 CBE3#
VSS
VSS
INTA# AD31 VSS
AD27 CIS AD29 AD30
VSS VIO AD26 AD28
AD25 AD24 VSS VIO
VIO GNT2# SUPA#
(Top View)
VIO
s
DRB23 DRB8 VIO DRB12 DRB15 VIO DRB3 DRB7 VIO DRB28 DRB25 VIO VID4 VIO VID0 VSS PW1 VIO AD0 VIO AD6 CBE0# VIO AD15 STOP# VIO
PAR AD16 VIO AD19 AD21
VIO
VSS
1
VSS DRB9 DRB14 VSS DRB1 DRB4 VSS DRB31 DRB26 VSS VID7 VID5 VSS VID1 VSS TDN VSS AD4 AD3 VSS AD8 AD10 VSS DEVSL# TRDY# VSS AD17 AD20 VSS
VIO
s
VIO DRB10 DRB13 VIO DRB2 DRB5 VIO DRB30 DRB27 VIO VIPCLK VID6 VIPSYNC VID2 VSS TDP PW0 AD7 AD2 VIO AD9 AD12 VIO AD13 CBE1# VIO FRAME# AD18 VIO
VSS
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Note: Signal names have been abbreviated in this figure due to space constraints.
= GND Ball
= PWR Ball
= Strap Option Ball
S
= Multiplexed Ball
Figure 3-2. BGU481 Ball Assignment Diagram
AMD Geode™ LX Processors Data Book
25
33234H
Table 3-5. Ball Assignments - Sorted by Ball Number
Ball Signal Name
Type
(PD)
Buffer
Type
Ball Signal Name
Type
(PD)
Buffer
Type
Ball Signal Name
Type
(PD)
Buffer
Type
No.
A1
A2
A3
(Note 1)
No.
(Note 1)
No.
(Note 1)
V
V
V
GND
PWR
GND
---
---
---
B19
B20
B21
DQ34
DQ38
I/O
I/O
DDR
DDR
---
D7
V
GND
---
SS
SS
D8
D9
MA7
MA8
I/O
I/O
DDR
DDR
---
MEM
SS
V
PWR
MEM
B22
B23
B24
DQ35
DQS5
I/O
I/O
DDR
DDR
---
D10
V
GND
SS
A4
A5
DQ21
I/O
DDR
---
D11 MA5
D12 MA6
D13 MA4
I/O
I/O
DDR
DDR
DDR
---
V
GND
SS
V
PWR
MEM
A6
A7
A8
DQM2
DQ22
I/O
I/O
DDR
DDR
---
B25
B26
B27
DQ46
DQ47
I/O
I/O
DDR
DDR
---
I/O
D14
D15
D16
D17
D18
V
V
V
V
V
GND
SS
V
GND
SS
V
PWR
PWR
GND
PWR
GND
---
---
---
---
MEM
CORE
SS
A9
DQ28
DQS3
I/O
I/O
DDR
DDR
---
B28
B29
CS0#
I/O
DDR
---
A10
A11
V
V
V
V
V
V
V
GND
SS
V
GND
SS
CORE
SS
B30
B31
C1
GND
PWR
GND
GND
PWR
GND
---
---
---
---
---
---
SS
A12
A13
A14
DQ26
DQ31
I/O
I/O
DDR
DDR
---
MEM
SS
D19 MA10
I/O
O
DDR
DDRCLK
DDRCLK
---
V
PWR
D20 SDCLK5P
D21 SDCLK5N
MEM
A15
A16
DQ32
I/O
DDR
---
C2
O
SS
V
GND
D22
V
GND
C3
SS
SS
MEM
SS
A17
A18
DQ37
I/O
DDR
---
D23 SDCLK4P
D24 SDCLK4N
O
O
DDRCLK
DDRCLK
---
C4
V
PWR
MEM
C5
C6
C7
MA12
DQS2
I/O
I/O
DDR
DDR
---
D25
V
GND
A19
A20
A21
DQM4
DQ39
I/O
I/O
DDR
DDR
---
SS
D26 BA0
I/O
I/O
DDR
DDR
---
V
PWR
MEM
V
GND
D27 RAS1#
SS
C8
C9
DQ19
DQ29
I/O
I/O
DDR
DDR
DDR
DDR
---
D28
D29
V
V
PWR
A22
A23
A24
DQ40
DQ41
I/O
I/O
DDR
DDR
---
MEM
SS
GND
---
C10 DQ25
C11 DQ30
I/O
V
GND
I/O
D30 CS3#
D31 DQ48
I/O
I/O
DDR
DDR
---
SS
A25
A26
A27
DQ42
DQ43
I/O
I/O
DDR
DDR
---
C12
C13 MA3
C14
V
GND
SS
E1
E2
V
V
GND
I/O
DDR
---
SS
V
GND
V
PWR
PWR
---
SS
MEM
MEM
A28
A29
WE1#
I/O
DDR
---
C15 MA2
C16 MA0
C17 MA1
I/O
I/O
DDR
DDR
DDR
---
E3
E4
DQ11
I/O
I/O
DDR
DDR
DDR
DDR
---
V
GND
CKE0
SS
A30
A31
B1
V
V
V
V
V
PWR
GND
PWR
GND
GND
---
---
---
---
---
I/O
E28
E29
E30
CAS0#
CAS1#
I/O
MEM
SS
C18
V
PWR
I/O
MEM
V
PWR
C19 DQS4
C20 BA1
I/O
I/O
DDR
DDR
---
MEM
MEM
SS
E31
V
GND
---
SS
B2
C21
V
GND
F1
F2
DQ15
DQ14
DQ10
CKE1
CS1#
CS2#
MA13
DQ49
DQ13
DQM1
I/O
I/O
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
---
SS
B3
SS
C22 DQ44
C23 DQ45
C24 DQM5
I/O
I/O
DDR
DDR
DDR
---
B4
B5
DQ17
I/O
DDR
---
F3
I/O
V
PWR
MEM
I/O
F4
I/O
B6
B7
B8
DQ18
DQ23
I/O
I/O
DDR
DDR
---
C25
V
PWR
F28
F29
F30
F31
G1
G2
G3
I/O
MEM
I/O
C26 RAS0#
C27 WE0#
I/O
I/O
DDR
DDR
---
V
PWR
MEM
I/O
B9
DQ24
I/O
I/O
DDR
DDR
---
I/O
C28
C29
C30
C31
V
V
V
V
GND
SS
B10
B11
DQM3
I/O
PWR
GND
GND
---
---
---
MEM
SS
V
PWR
MEM
I/O
B12
B13
B14
DQ27
TLA1
I/O
I/O
DDR
DDR
---
V
V
V
V
PWR
MEM
SS
SS
G4
GND
GND
PWR
---
---
---
D1
D2
D3
DQ20
DQ16
I/O
I/O
DDR
DDR
---
V
GND
SS
G28
G29
SS
B15
B16
B17
B18
TLA0
DQ36
DQ33
I/O
I/O
DDR
DDR
DDR
---
MEM
V
V
GND
SS
G30 DQ52
G31 DQ53
I/O
I/O
DDR
DDR
---
D4
PWR
---
I/O
MEM
V
GND
D5
D6
MA11
MA9
I/O
I/O
DDR
DDR
SS
H1
V
PWR
MEM
26
AMD Geode™ LX Processors Data Book
Ball Signal Name
33234H
Type
(PD)
Buffer
Type
Ball Signal Name
Type
(PD)
Buffer
Type
Ball Signal Name
Type
(PD)
Buffer
Type
No.
(Note 1)
No.
N28
N29
(Note 1)
No.
T31
U1
(Note 1)
H2
V
GND
---
V
V
GND
PWR
---
---
V
SS
GND
---
---
SS
SS
H3
H4
DQS1
I/O
O
DDR
DDRCLK
DDRCLK
DDR
DAV
APWR
MEM
DD
SDCLK1N
N30 DQM7
N31 DQS7
I/O
I/O
I
DDR
DDR
---
U2
U3
BLUE
A
---
---
H28 SDCLK3N
H29 DQM6
O
DAV
AGND
SS
CORE
SS
I/O
GND
P1
P2
P3
P4
MVREF
DQ0
U4
V
V
V
V
V
V
V
V
V
V
V
V
PWR
GND
GND
GND
GND
GND
GND
GND
PWR
PWR
PWR
PWR
APWR
---
---
---
---
---
---
---
---
---
---
---
---
---
H30
H31
V
V
---
I/O
I/O
GND
DDR
DDR
---
SS
U13
U14
U15
U16
U17
U18
U19
U28
U29
U30
U31
V1
PWR
---
DQ4
MEM
SS
V
J1
J2
DQ9
I/O
I/O
I/O
O
DDR
DDR
SS
SS
DQ8
P13
P14
P15
P16
P17
P18
P19
P28
P29
V
V
V
V
V
V
V
V
V
PWR
PWR
GND
GND
GND
PWR
PWR
GND
PWR
---
---
---
---
---
---
---
---
---
CORE
CORE
SS
SS
J3
DQ12
SDCLK1P
SDCLK3P
DQS6
DQ55
DQ54
DQ7
DDR
SS
J4
DDRCLK
DDRCLK
DDR
SS
J28
J29
J30
J31
K1
K2
K3
O
SS
SS
I/O
I/O
I/O
I/O
I/O
PWR
SS
DDR
CORE
CORE
CORE
CORE
CORE
CORE
SS
DDR
DDR
DQ3
DDR
V
V
V
V
---
MEM
MEM
DAV
DD
P30
P31
DQ62
I/O
DDR
---
K4
GND
GND
PWR
---
---
---
SS
V2
V3
GREEN
A
---
---
V
V
V
V
V
V
V
V
V
V
V
V
V
GND
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
CORE
K28
K29
SS
DAV
DAV
AGND
SS
DD
R1
R2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PWR
---
---
---
---
---
---
---
---
---
---
---
---
MEM
V4
APWR
PWR
PWR
GND
GND
GND
PWR
PWR
PWR
---
---
---
---
---
---
---
---
---
K30
K31
L1
DQ50
DQ51
I/O
I/O
DDR
DDR
---
V13
V14
V15
V16
V17
V18
V19
V28
V
V
V
V
V
V
V
V
CORE
CORE
SS
R3
R4
V
PWR
MEM
R13
R14
R15
R16
R17
R18
R19
R28
L2
V
GND
---
SS
SS
L3
L4
DQ6
I/O
O
DDR
DDRCLK
DDRCLK
DDR
SS
SDCLK0N
SDCLK2N
DQ60
CORE
CORE
CORE
L28
L29
L30
O
I/O
GND
V
---
SS
V29
V30
MLPF
A
---
---
L31
V
PWR
---
MEM
MAV
MAV
AGND
SS
M1
M2
M3
M4
DQM0
DQS0
I/O
I/O
I/O
O
DDR
DDR
V31
APWR
---
DD
R29 DQ63
R30 DQ58
R31 DQ59
I/O
I/O
DDR
DDR
DDR
---
W1
W2
DVREF
DAV
A
---
---
DQ2
DDR
AGND
SS
SDCLK0P
DDRCLK
DDRCLK
DDR
I/O
W3
W4
RED
DAV
A
---
---
M28 SDCLK2P
M29 DQ61
M30 DQ57
M31 DQ56
O
T1
T2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
PWR
CORE
CORE
CORE
CORE
SS
APWR
I/O
I/O
I/O
I/O
I/O
GND
DD
PWR
PWR
PWR
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
---
---
---
---
---
---
---
---
---
---
---
---
---
DDR
W13
W14
W15
W16
W17
W18
W19
W28
V
V
V
V
V
V
V
V
PWR
PWR
GND
GND
GND
PWR
PWR
GND
---
---
CORE
CORE
SS
T3
DDR
T4
N1
N2
N3
DQ5
DQ1
DDR
---
T13
T14
T15
T16
T17
T18
T19
T28
T29
T30
DDR
---
SS
V
---
SS
SS
---
SS
N4
V
PWR
PWR
PWR
GND
GND
GND
PWR
PWR
---
---
---
---
---
---
---
---
MEM
SS
---
CORE
CORE
SS
N13
N14
N15
N16
N17
N18
N19
V
V
V
V
V
V
V
CORE
CORE
SS
SS
DDR
---
SS
SS
W29 CLPF
A
---
---
SS
SS
W30 CAV
W31 CAV
AGND
SS
SS
SS
APWR
A
---
---
DD
CORE
CORE
SS
Y1
DRSET
SS
AMD Geode™ LX Processors Data Book
27
33234H
Ball Signal Name
Type
(PD)
Buffer
Type
Ball Signal Name
No. (Note 1)
Type
(PD)
Buffer
Type
Ball Signal Name
Type
(PD)
Buffer
Type
No.
(Note 1)
No.
(Note 1)
Y2
DAV
AGND
PWR
GND
PWR
GND
---
---
---
---
---
AE29 CIS
I/O
I/O
24/Q7
PCI
AH26
V
GND
---
SS
SS
AE30 AD29
AE31 AD30
AF1 DRGB17
AF2 DRGB16
Y3
V
V
V
V
AH27 CBE2#
AH28
I/O
PCI
---
IO
I/O
PCI
V
GND
Y4
SS
SS
O (PD)
O (PD)
PWR
24/Q5
24/Q5
---
AH29 AD23
AH30 AD22
AH31 CBE3#
I/O
I/O
PCI
PCI
Y28
Y29
CORE
SS
AF3
AF4
V
V
V
V
IO
I/O
PCI
Y30
Y31
RESET#
SYSREF
I
PCI
PCI
---
GND
GND
PWR
---
---
---
AJ1
AJ2
DRGB23
DRGB8
VOP15
O (PD)
O (PD)
O
24/Q5
24/Q5
SS
SS
IO
I
AF28
AF29
AA1 VAV
AA2 VAV
APWR
DD
AGND
---
SS
AJ3
AJ4
V
PWR
---
IO
AF30 AD26
AF31 AD28
I/O
I/O
PCI
PCI
---
AA3 VLPF
AA4 TMS
A
---
24/Q7
PCI
PCI
---
DRGB12
VOP11
DRGB15
VOP8
O (PD)
O
24/Q5
I
I/O
I
AG1
AG2
V
V
PWR
IO
AA28 GNT0#
AA29 REQ0#
AJ5
O (PD)
O
24/Q5
GND
---
SS
AG3 DRGB18
AG4 DRGB19
AG28 AD25
O (PD)
O (PD)
I/O
24/Q5
24/Q5
PCI
AA30
AA31
V
GND
SS
IO
AJ6
AJ7
V
PWR
---
IO
V
PWR
---
DRGB3
VOP4
O (PD)
O
24/Q5
AB1 DOTREF
AB2 TDBGI
AB3 TDI
I
PCI
24/Q7
24/Q7
24/Q3
PCI
AG29 AD24
I/O
PCI
I
I
AJ8
DRGB7
VOP0
O (PD)
O
24/Q5
AG30
AG31
V
V
GND
---
SS
IO
PWR
---
AB4 TDBGO
AB28 REQ2#
AB29 IRQ13
AB30 GNT1#
AB31 REQ1#
AC1 TDO
O (PD)
I/O
AJ9
V
PWR
---
IO
AH1 DRGB20
AH2 DRGB21
AH3 DRGB22
O (PD)
O (PD)
O (PD)
GND
24/Q5
24/Q5
24/Q5
---
AJ10 DRGB28
VID12
I/O (PD) 24/Q5
I/O (PD) 24/Q5
O
I/O
I/O
O
PCI
PCI
AJ11 DRGB25
MSGSTOP
VID9
I/O (PD) 24/Q5
AH4
V
SS
I
I
24/Q5
24/Q7
---
AH5 DRGB11
VOP12
O (PD)
O
24/Q5
AC2 TCLK
I
AJ12
AJ13 VID4
AJ14
AJ15 VID0
AJ16
AJ17 PW1
AJ18
AJ19 AD0
AJ20
V
PWR
I/O (PD) 24/Q7
PWR ---
I/O (PD) 24/Q7
---
IO
AC3
AC4
V
V
V
V
PWR
AH6
V
GND
---
IO
SS
GND
GND
PWR
---
---
---
AH7 DRGB0
VOP7
O (PD)
O
24/Q5
SS
SS
IO
V
IO
AC28
AC29
AH8 DRGB6
VOP1
O (PD)
O
24/Q5
V
GND
---
SS
AC30 GNT2#
AC31 SUSPA#
I/O
I/O
PCI
24/Q5
---
I/O
24/Q7
---
AH9
V
GND
---
SS
V
PWR
IO
AH10 DRGB29
VID13
I/O (PD) 24/Q5
AD1
AD2
V
V
PWR
IO
I/O
PCI
---
I
GND
---
SS
V
PWR
IO
AH11 DRGB24
I/O (PD) 24/Q5
AD3 VSYNC
VOP_VSYNC
O (PD)
O
5V
AJ21 AD6
I/O
I/O
PCI
PCI
---
MSGSTART
I
I
AJ22 CBE0#
VID8
AD4 LDEMOD
VIP_VSYNC
I/O (PD) 24/Q5
AJ23
V
PWR
AH12
V
GND
---
IO
SS
I
AJ24 AD15
I/O
I/O
PCI
PCI
---
AH13 VID3
I/O (PD) 24/Q7
AD28 INTA#
AD29 AD31
I/O (PD) 24/Q5
AJ25 STOP#
AH14
AH15
AH16
AH17
AH18
V
V
V
V
V
GND
PWR
GND
PWR
GND
---
---
---
---
---
SS
I/O
PCI
---
AJ26
V
PWR
IO
CORE
SS
AD30
AD31
V
V
GND
SS
AJ27 PAR
I/O
I/O
PCI
PCI
---
PWR
---
IO
AJ28 AD16
CORE
SS
AE1 DOTCLK
VOPCLK
O (PD)
O
24/Q3
AJ29
V
PWR
IO
AJ30 AD19
AJ31 AD21
I/O
I/O
PCI
PCI
---
AE2 VDDEN
I/O (PD) 24/Q5
I
AH19 AD1
AH20
I/O
PCI
---
VIP_HSYNC
AE3 HSYNC
VOP_HSYNC
AE4 DISPEN
VOP_BLANK
AE28 AD27
V
GND
SS
AK1
AK2
V
V
PWR
IO
O (PD)
O
5V
24/Q5
PCI
AH21 AD5
AH22 AD11
I/O
I/O
PCI
PCI
---
GND
---
SS
AK3 DRGB9
VOP14
O (PD)
O
24/Q5
O (PD)
O
AH23
V
GND
SS
AH24 AD14
AH25 IRDY#
I/O
I/O
PCI
PCI
I/O
28
AMD Geode™ LX Processors Data Book
Ball Signal Name
33234H
Type
(PD)
Buffer
Type
Ball Signal Name
Type
(PD)
Buffer
Type
Ball Signal Name
Type
(PD)
Buffer
Type
No.
(Note 1)
No.
(Note 1)
No.
(Note 1)
AK4 DRGB14
VOP9
O (PD)
O
24/Q5
AK24
V
GND
---
AL11
V
PWR
---
SS
IO
AK25 DEVSEL#
AK26 TRDY#
I/O
I/O
PCI
PCI
---
AL12 VIPCLK
AL13 VID6
I/O (PD)
5V
AK5
V
GND
---
I/O (PD) 24/Q7
I/O (PD) 5V
I/O (PD) 24/Q7
SS
AK6 DRGB1
VOP6
O (PD)
O
24/Q5
AK27
V
GND
AL14 VIPSYNC
AL15 VID2
SS
AK28 AD17
AK29 AD20
I/O
I/O
PCI
PCI
---
AK7 DRGB4
VOP3
O (PD)
O
24/Q5
AL16
V
GND
---
SS
AK30
AK31
AL1
V
V
V
V
GND
AL17 TDP
AL18 PW0
AL19 AD7
AL20 AD2
A
I/O
---
24/Q7
PCI
PCI
---
SS
IO
AK8
V
GND
---
SS
PWR
GND
PWR
---
---
AK9 DRGB31
VID15
I/O (PD) 24/Q5
I/O
SS
IO
I
I/O
AL2
---
AK10 DRGB26
VID10
I/O (PD) 24/Q5
I
AL21
V
PWR
IO
AL3
DRGB10
VOP13
O (PD)
O
24/Q5
AL22 AD9
AL23 AD12
I/O
I/O
PCI
PCI
---
AK11
V
GND
---
SS
AL4
DRGB13
VOP10
O (PD)
O
24/Q5
AK12 VID7
AK13 VID5
I/O (PD) 24/Q7
I/O (PD) 24/Q7
AL24
V
PWR
IO
AL25 AD13
I/O
I/O
PCI
PCI
---
AL5
AL6
V
PWR
---
IO
AK14
AK15 VID1
AK16
AK17 TDN
AK18
V
GND
---
AL26 CBE1#
SS
DRGB2
VOP5
O (PD)
O
24/Q5
I/O (PD) 24/Q7
AL27
V
PWR
IO
V
GND
---
AL28 FRAME#
AL29 AD18
I/O
I/O
PCI
PCI
---
SS
AL7
DRGB5
VOP2
O (PD)
O
24/Q5
A
A
V
GND
---
AL30
AL31
V
V
PWR
SS
IO
AL8
AL9
V
PWR
---
IO
AK19 AD4
AK20 AD3
I/O
I/O
PCI
PCI
---
GND
---
SS
DRGB30
VID14
I/O (PD) 24/Q5
I
Note 1.The primary signal name is listed first.
AK21
V
GND
SS
AL10 DRGB27
VID11
I/O (PD) 24/Q5
I
AK22 AD8
AK23 AD10
I/O
I/O
PCI
PCI
AMD Geode™ LX Processors Data Book
29
33234H
Ball No.
Table 3-6. Ball Assignments - Sorted Alphabetically by Signal Name
Signal Name
Ball No.
Signal Name
Ball No.
Signal Name
AD0
AJ19
AH19
AL20
AK20
AK19
AH21
AJ21
AL19
AK22
AL22
AK23
AH22
AL23
AL25
AH24
AJ24
AJ28
AK28
AL29
AJ30
AK29
AJ31
AH30
AH29
AG29
AG28
AF30
AE28
AF31
AE30
AE31
AD29
D26
CS1#
CS2#
CS3#
DAVDD
DAVSS
DEVSEL#
DISPEN
DOTCLK
DOTREF
DQ0
F28
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DRGB0
DRGB1
DRGB2
DRGB3
DRGB4
DRGB5
DRGB6
A20
A22
A23
A25
A26
C22
C23
B25
B26
D31
F31
K30
K31
G30
G31
J31
J30
M31
M30
R30
R31
L29
M29
P30
R29
M1
AD1
F29
AD2
D30
AD3
U1, V1, V4, W4
AD4
U3, V3, Y2, W2
AK25
AE4
AE1
AB1
P2
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
BA0
DQ1
N2
DQ2
M3
DQ3
K2
DQ4
P3
DQ5
N1
DQ6
L3
DQ7
K1
DQ8
J2
DQ9
J1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
F3
E3
J3
G1
F2
F1
D2
B4
G2
B6
A6
C8
B10
A19
C24
H29
N30
M2
D1
A4
A7
B7
BA1
C20
B9
BLUE
CAS0#
CAS1#
CAVDD
CAVSS
CBE0#
CBE1#
CBE2#
CBE3#
CIS
U2
C10
A12
B12
A9
H3
E28
C6
E29
A10
C19
B23
J29
N31
AH7
AK6
AL6
AJ7
AK7
AL7
AH8
W31
W30
AJ22
AL26
AH27
AH31
AE29
E4
C9
C11
A13
A15
B17
B19
B22
B16
A17
B20
CKE0
CKE1
CLPF
CS0#
F4
W29
B28
30
AMD Geode™ LX Processors Data Book
33234H
Signal Name
Ball No.
Signal Name
Ball No.
Signal Name
Ball No.
DRGB7
DRGB8
DRGB9
DRGB10
DRGB11
DRGB12
DRGB13
DRGB14
DRGB15
DRGB16
DRGB17
DRGB18
DRGB19
DRGB20
DRGB21
DRGB22
DRGB23
DRGB24
DRGB25
DRGB26
DRGB27
DRGB28
DRGB29
DRGB30
DRGB31
DRSET
DVREF
FRAME#
GNT0#
GNT1#
GNT2#
GREEN
HSYNC
INTA#
AJ8
AJ2
MA11
D5
C5
VCORE (Total
of 32)
D15, D17, N13, N14,
N18, N19, P13, P14,
P18, P19, R28, T1, T2,
T3, T4, U4, V13, V14,
V18, V19, U28, U29,
U30, U31, V28, W13,
W14, W18, W19, Y28,
AH15, AH17
MA12
AK3
AL3
AH5
AJ4
MA13
F30
MAVDD
MAVSS
MLPF
V31
V30
V29
AH11
AJ11
P1
AL4
AK4
AJ5
MSGSTART
MSGSTOP
MVREF
PAR
VDDEN
AE2
V
IO (Total of Y3, AA31, AJ3, AJ6, AJ9,
30)
AJ12, AJ14, AJ18, AJ20,
AJ23, AJ26, AJ29, AC3,
AK1, AK31, AL2, AL5,
AL8, AL11, AL21, AL24,
AL27, AL30, AC29, AD1,
AD31, AF3, AF29, AG1,
AG31
AF2
AF1
AG3
AG4
AH1
AH2
AH3
AJ1
AJ27
AL18
AJ17
C26
D27
W3
PW0
PW1
RAS0#
RAS1#
RED
VID0
AJ15
AK15
AL15
AH13
AJ13
AK13
AL13
AK12
AH11
AJ11
AK10
AL10
AJ10
AH10
AL9
VID1
REQ0#
REQ1#
REQ2#
RESET#
SDCLK0N
SDCLK0P
SDCLK1N
SDCLK1P
SDCLK2N
SDCLK2P
SDCLK3N
SDCLK3P
SDCLK4N
SDCLK4P
SDCLK5N
SDCLK5P
STOP#
SUSPA#
SYSREF
TCLK
AA29
AB31
AB28
Y30
L4
VID2
VID3
AH11
AJ11
AK10
AL10
AJ10
AH10
AL9
AK9
Y1
VID4
VID5
VID6
M4
VID7
H4
VID8
J4
VID9
L28
VID10
VID11
VID12
VID13
VID14
VID15
VIPCLK
VIP_HSYNC
VIPSYNC
VIP_VSYNC
VLPF
M28
H28
J28
W1
AL28
AA28
AB30
AC30
V2
D24
D23
D21
D20
AJ25
AC31
Y31
AC2
AB2
AB4
AB3
AK17
AC1
AL17
B15
B13
AA4
AK26
AA1
AA2
AK9
AL12
AE2
AL14
AD4
AA3
AE3
AD28
AH25
AB29
AD4
C16
C17
C15
C13
D13
D11
D12
D8
IRDY#
VOP0
VOP1
VOP2
VOP3
VOP4
VOP5
VOP6
VOP7
VOP8
VOP9
VOP10
VOP11
VOP12
AJ8
IRQ13
TDBGI
AH8
AL7
LDEMOD
MA0
TDBGO
TDI
AK7
MA1
TDN
AJ7
MA2
TDO
AL6
MA3
TDP
AK6
MA4
TLA0
AH7
AJ5
MA5
TLA1
MA6
TMS
AK4
MA7
TRDY#
VAVDD
AL4
MA8
D9
AJ4
MA9
D6
VAVSS
AH5
MA10
D19
AMD Geode™ LX Processors Data Book
31
33234H
Signal Name
Ball No.
Signal Name
Ball No.
Signal Name
Ball No.
VOP13
AL3
AK3
AJ2
AE4
AE1
AE3
AD3
VSS (Total of A1, A3, A29, A31, AA30,
VSYNC
WE0#
WE1#
AD3
C27
A28
128)
AC4, AC28, AD2, AD30,
AF4, AF28, AG2, AG30,
AH4, AH6, AH9, AH12,
AH14, AH16, AH18,
VOP14
VOP15
VOP_BLANK
VOPCLK
AH20, B2, AH23, AH26,
AH28, AJ16, AK2, AK5,
AK8, AK11, AK14, AK16,
B3, AK18, AK21, AK24,
AK27, AK30, AL1, AL16,
AL31, B14, B18, B29,
B30, C1, C2, C4, A5,
C12, C21, C28, C30,
C31, D3, D7, D10, D14,
D16, A8, D18, D22, D25,
D29, E1, E31, G4, G28,
H2, H30, A11, K4, K28,
L2, L30, N3, N15, N16,
N17, N28, P4, A16, P15,
P16, P17, P28, P31, R1,
R2, R3, R4, R13, A21,
R14, R15, R16, R17,
VOP_HSYNC
VOP_VSYNC
VMEM (Total
of 33)
A2, A14, B1, B5, B8,
B11, B21. B24, B27, B31,
C3, C7, C14, C18, C25,
C29, D4, D28, A18, E2,
E30, G3, G29, H1, H31,
K3, K29, L1, L31, A30,
N4, N29, P29
R18, R19, T13, T14, T15,
T16, A24, T17, T18, T19,
T28, T29, T30, T31, U13,
U14, U15, A27, U16,
U17, U18, U19, V15,
V16, V17, W15, W16,
W17, W28, Y4, Y29
32
AMD Geode™ LX Processors Data Book
33234H
3.4
Signal Descriptions
3.4.1
System Interface Signals
Ball
Signal Name
No.
Type
f
V
Description
SYSREF
Y31
I
33, 66 MHz
3.3
System Reference. PCI input clock; typically 33 or
66 MHz.
DOTREF
INTA#
AB1
I
48 MHz
3.3
3.3
Dot Clock Reference. Input clock for DOTCLK PLL.
AD28
I/O
0-66 Mb/s
Interrupt. Interrupt from the AMD Geode LX proces-
(PD)
sor to the CS5536 companion device (open drain).
IRQ13
AB29
(Strap)
I/O
(PD)
0-66 Mb/s
3.3
Interrupt Request Level 13. When a floating point
error occurs, the AMD Geode LX processor asserts
IRQ13. The floating point interrupt handler then per-
forms an OUT instruction to I/O address F0h or F1h.
The AMD Geode LX processor accepts either of
these cycles and clears IRQ13.
IRQ13 is an output during normal operation. It is an
input at reset and functions as a boot strap for tester
features on a board. It must be pulled low for normal
operation.
CIS
AE29
I/O
I/O
0-66 Mb/s
0-66 Mb/s
3.3
3.3
CPU Interface Serial. The GLCP I/O companion
interface uses the CIS signal to create a serial bus. It
contains INTR#, SUSP#, NMI#, INPUT_DIS#,
OUTPUT_DIS#, and SMI#. For details see
SUSPA#
AC31
(Strap)
Suspend Acknowledge. Suspend Acknowledge
indicates that the AMD Geode LX processor has
entered low-power Suspend mode as a result of
SUSP# assertion (as part of the packet asserted on
the CIS signal) or execution of a HLT instruction.
(The AMD Geode LX processor enters Suspend
mode following execution of a HLT instruction if the
SUSPONHLT bit, MSR 00001210h[0], is set.)
The SYSREF input may be stopped after SUSPA#
has been asserted to further reduce power con-
sumption if the system is configured for 3 Volt Sus-
pend mode.
SUSPA# is an output during normal operation. It is
an input at reset and functions as a boot strap for fre-
quency selection on a board. It must be pulled high
or low to invoke the strap.
PW0, PW1
AL18,
AJ17
(Strap)
I/O
0-300 Mb/s
3.3
PowerWise Controls. Used for debug.
PWx is an output during normal operation. It is an
input at reset and functions as a boot strap for fre-
quency selection on a board. It must be pulled high
or low to invoke the strap.
AMD Geode™ LX Processors Data Book
33
33234H
3.4.1
System Interface Signals (Continued)
Ball
Signal Name
No.
Type
f
V
Description
TDP
AL17
A
Analog
N/A
Thermal Diode Positive (TDP). TDP is the positive
terminal of the thermal diode on the die. The diode is
used to do thermal characterization of the device in
a system. This signal works in conjunction with TDN.
For accurate die temperature measurements, a dual
current source remote sensor, such as the National
Semiconductor LM82, should be used. Single cur-
rent source sensors may not yield the desired level
of accuracy.
If reading the CPU temperature is required while the
system is off, then a small bias (<0.25V) on V is
IO
required for the thermal diode to operate properly.
TDN
AK17
A
Analog
N/A
Thermal Diode Negative (TDN). TDN is the nega-
tive terminal of the thermal diode on the die. The
diode is used to do thermal characterization of the
device in a system. This signal works in conjunction
with TDP.
For accurate die temperature measurements, a dual
current source remote sensor, such as the National
Semiconductor LM82, should be used. Single cur-
rent source sensors may not yield the desired level
of accuracy.
If reading the CPU temperature is required while the
system is off, then a small bias (<0.25V) on V is
IO
required for the thermal diode to operate properly.
3.4.2
PLL Interface Signals
Ball
Signal Name
No.
W31
W30
V31
V30
AA1
AA2
W29
V29
AA3
Type
APWR
APWR
APWR
APWR
APWR
APWR
A
f
V
3.3
0
Description
CAV
CAV
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Core PLL Analog Power. Connect to 3.3V.
Core PLL Analog Ground. Connect to ground.
GLIU PLL Analog Power. Connect to 3.3V.
GLIU PLL Analog Ground. Connect to ground.
Video PLL Analog Power. Connect to 3.3V.
Video PLL Analog Ground. Connect to ground.
DD
SS
MAV
MAV
3.3
0
DD
SS
DD
SS
VAV
VAV
3.3
0
CLPF
MLPF
VLPF
N/A
N/A
N/A
Core PLL Low Pass Filter. 220 pF to CAV
.
SS
A
GLIU PLL Low Pass Filter. 220 pF to MAV
SS.
A
Video PLL Low Pass Filter. 220 pF to VAV
SS.
34
AMD Geode™ LX Processors Data Book
33234H
3.4.3
Memory Interface Signals (DDR)
Signal Name
Ball No.
Type
f
V
Description
SDCLK[5:0]P,
SDCLK[5:0]N
D20, D21,
D23, D24,
J28, H28,
M28, L28,
J4, H4,
O
up to 200 MHz
2.5
SDRAM Clock Differential Pairs. The SDRAM
devices sample all the control, address, and
data based on these clocks. All clocks are dif-
ferential clock outputs.
M4, L4
MVREF
P1
I
Analog
V
Memory Voltage Reference. This input oper-
MEM
ates at half the V
voltage.
MEM
CKE[1:0]
F4, E4
I/O
up to 200 Mb/s
2.5
Clock Enable. For normal operation, CKE is
held high. CKE goes low during Suspend.
CKE0 is used with CS0# and CS1#. CKE1 is
used with CS2# and CS3#.
CS[3:0]#
D30, F29,
F28, B28
I/O
up to 200 Mb/s
2.5
Chip Selects. The chip selects are used to
select the module bank within the system mem-
ory. Each chip select corresponds to a specific
module bank.
If CS# is high, the bank(s) do not respond to
RAS#, CAS#, or WE# until the bank is selected
again.
RAS[1:0]#
CAS[1:0]#
WE[1:0]#
D27, C26
E29, E28
I/O
I/O
I/O
up to 200 Mb/s
up to 200 Mb/s
up to 200 Mb/s
2.5
2.5
2.5
Row Address Strobe. RAS#, CAS#, WE#, and
CKE are encoded to support the different
SDRAM commands. RAS0# is used with CS0#
and CS1#. RAS1# is used with CS2# and
CS3#.
Column Address Strobe. RAS#, CAS#, WE#,
and CKE are encoded to support the different
SDRAM commands. CAS0# is used with CS0#
and CS1#. CAS1# is used with CS2# and
CS3#.
A28, C27
C20, D26
Write Enable. RAS#, CAS#, WE#, and CKE
are encoded to support the different SDRAM
commands. WE0# is used with CS0# and
CS1#. WE1# is used with CS2# and CS3#.
BA[1:0]
I/O
I/O
up to 200 Mb/s
up to 200 Mb/s
2.5
2.5
Bank Address Bits. These bits are used to
select the component bank within the SDRAM.
MA[13:0]
Memory Address Bus. The multiplexed row/
column address lines driven to the system
memory.
Supports 256-Mbit SDRAM.
TLA[1:0]
DQS[7:0]
B13, B15
I/O
I/O
up to 200 Mb/s
up to 200 MHz
2.5
2.5
Memory Debug Pins. These pins provide use-
ful memory interface debug timing signals.
(Should be wired to DIMM slot.)
TLA[0] is wired to DQS[8] on the DIMM
TLA[1] is wired to CB[0] on the DIMM
N31, J29,
B23, C19,
A10, C6,
H3, M2
DDR Data Strobe.
AMD Geode™ LX Processors Data Book
35
33234H
3.4.3
Memory Interface Signals (DDR) (Continued)
Signal Name
DQM[7:0]
Ball No.
Type
f
V
Description
N30, H29,
C24, A19,
B10, A6,
G2, M1
I/O
166-400 Mb/s
2.5
Data Mask Control Bits. During memory read
cycles, these outputs control whether the
SDRAM output buffers are driven on the Mem-
ory Data Bus or not. All DQM signals are
asserted during read cycles.
During memory write cycles, these outputs con-
trol whether or not memory data is written into
the SDRAM.
DQM[0] is associated with MD[7:0].
DQM[7] is associated with MD[63:56].
DQ[63:0]
I/O
166-400 Mb/s
2.5
Memory Data Bus.
3.4.4
Internal Test and Measurement Interface Signals
Signal Name
Ball No.
Type
f
V
Description
TCLK
TMS
TDI
AC2
AA4
AB3
AC1
AB2
I
I
0-66 MHz
0-66 Mb/s
0-66 Mb/s
0-66 Mb/s
0-400 Mb/s
3.3
3.3
3.3
3.3
3.3
Test Clock. JTAG test clock.
Test Mode Select. JTAG test mode select.
Test Data Input. JTAG serial test data input.
Test Data Output. JTAG serial test data output.
I
TDO
TDBGI
O
I
Test Debug Input. The Debug Management
Interrupt (DMI) is input via TDBGI. The selects
for TDBGI are MSR programmable via the GLCP
module. When using TDBGI for DMI, it cannot be
used for other debug purposes. DMI can be
setup via the GLCP module to be edge sensitive
or level sensitive
TDBGO
AB4
O
(PD)
0-400 Mb/s
3.3
Test Debug Output. The AMD Geode LX pro-
cessor can output internal clocks on TDBGO.
The selects for TDBGO are MSR programmable
via the GLCP module. The internal clock can be
selected from any clock domain and may be
divided down by 2 or 3 before output. This
enables tester and board level visibility of the
internal clock quality.
36
AMD Geode™ LX Processors Data Book
33234H
3.4.5
PCI Interface Signals
Signal Name
Ball No.
Type
f
V
Description
AD[31:0]
I/O
33-66 Mb/s
3.3
Multiplexed Address and Data. Addresses and
data are multiplexed together on the same pins.
A bus transaction consists of an address phase
in the cycle in which FRAME# is asserted fol-
lowed by one or more data phases. During the
address phase, AD[31:0] contain a physical 32-
bit address. During data phases, AD[7:0] contain
the least significant byte (LSB) and AD[31:24]
contain the most significant byte (MSB). Write
data is stable and valid when IRDY# is asserted
and read data is stable and valid when TRDY# is
asserted. Data is transferred during the SYSREF
when both IRDY# and TRDY# are asserted.
CBE[3:0]#
AH31,
AH27,
AL26,
AJ22
I/O
33-66 Mb/s
3.3
Multiplexed Command and Byte Enables. C/
BE# are the bus commands and byte enables.
During the address phase of a transaction when
FRAME# is active, C/BE# define the bus com-
mand. During the data phase C/BE# are used as
byte enables. The byte enables are valid for the
entire data phase and determine which byte
lanes carry meaningful data. C/BE0# applies to
byte 0 (LSB) and C/BE3# applies to byte 3
(MSB). The command encoding and types are
listed below:
0000: Interrupt Acknowledge
0001: Special Cycle
0010: I/O Read
0011: I/O Write
0100: Reserved
0101: Reserved
0110: Memory Read
0111: Memory Write
1000: Reserved
1001: Reserved
1010: Configuration Read
1011: Configuration Write
1100: Memory Read Multiple
1101: Dual Address Cycle (RSVD)
1110: Memory Read Line
1111: Memory Write and Invalidate
PAR
AJ27
I/O
33-66 Mb/s
3.3
Parity. PAR is used with AD[31:0] and C/BE# to
generate even parity. Parity generation is
required by all PCI agents: the master drives PAR
for address and write-data phases and the target
drives PAR for read-data phases.
For address phases, PAR is stable and valid one
SYSREF after the address phase.
For data phases, PAR is stable and valid one
SYSREF after either IRDY# is asserted on a
write transaction or after TRDY# is asserted on a
read transaction. Once PAR is valid, it remains
valid until one SYSREF after the completion of
the data phase.
AMD Geode™ LX Processors Data Book
37
33234H
3.4.5
PCI Interface Signals (Continued)
Signal Name
RESET#
Ball No.
Type
f
V
Description
Y30
I
0-1 Mb/s
3.3
PCI Reset. RESET# aborts all operations in
progress and places the AMD Geode LX proces-
sor into a reset state. RESET# forces the CPU
and peripheral functions to begin executing at a
known state. All data in the on-chip cache is
invalidated upon a reset.
RESET# is an asynchronous input, but must
meet specified setup and hold times to guarantee
recognition at a particular clock edge. This input
is typically generated during the power-on-reset
(POR) sequence.
STOP#
AJ25
I/O
33-66 Mb/s
3.3
Target Stop. STOP# is asserted to indicate that
the current target is requesting the master to stop
the current transaction. This signal is used with
DEVSEL# to indicate retry, disconnect, or target
abort. If STOP# is sampled active while a master,
FRAME# is de-asserted and the cycle is stopped
within three SYSREFs. STOP# can be asserted
when the PCI write buffers are full or a previously
buffered cycle has not completed.
FRAME#
AL28
AH25
I/O
I/O
33-66 Mb/s
33-66 Mb/s
3.3
3.3
Frame. FRAME# is driven by the current master
to indicate the beginning and duration of an
access. FRAME# is asserted to indicate a bus
transaction is beginning. While FRAME# is
asserted, data transfers continue. When
FRAME# is de-asserted, the transaction is in the
final data phase.
IRDY#
Initiator Ready. IRDY# is asserted to indicate
that the bus master is able to complete the cur-
rent data phase of the transaction. IRDY# is used
in conjunction with TRDY#. A data phase is com-
pleted on any SYSREF in which both IRDY# and
TRDY# are sampled asserted. During a write,
IRDY# indicates valid data is present on
AD[31:0]. During a read, it indicates the master is
prepared to accept data. Wait cycles are inserted
until both IRDY# and TRDY# are asserted
together.
TRDY#
AK26
I/O
33-66 Mb/s
3.3
Target Ready. TRDY# is asserted to indicate that
the target agent is able to complete the current
data phase of the transaction. TRDY# is used in
conjunction with IRDY#. A data phase is com-
plete on any SYSREF in which both TRDY# and
IRDY# are sampled asserted. During a read,
TRDY# indicates that valid data is present on
AD[31:0]. During a write, it indicates the target is
prepared to accept data. Wait cycles are inserted
until both IRDY# and TRDY# are asserted
together.
38
AMD Geode™ LX Processors Data Book
33234H
3.4.5
PCI Interface Signals (Continued)
Signal Name
Ball No.
Type
f
V
Description
DEVSEL#
AK25
I/O
33-66 Mb/s
3.3
Device Select. DEVSEL# indicates that the driv-
ing device has decoded its address as the target
of the current access. As an input, DEVSEL#
indicates whether any device on the bus has
been selected. DEVSEL# is also driven by any
agent that has the ability to accept cycles on a
subtractive decode basis. As a master, if no
DEVSEL# is detected within and up to the sub-
tractive decode clock, a master abort cycle
results, except for special cycles that do not
expect a DEVSEL# returned.
REQ[2:0]#
GNT[2:0]#
AB28,
AB31,
AA29
I
33-66 Mb/s
33-66 Mb/s
3.3
3.3
Request Lines. REQ# indicates to the arbiter
that an agent desires use of the bus. Each mas-
ter has its own REQ# line. REQ# priorities are
based on the arbitration scheme chosen.
REQ2# is reserved for the interface with the
AMD Geode CS5536 companion device.
AC30,
AB30,
AA28
I/O
Grant Lines. GNT# indicates to the requesting
master that it has been granted access to the
bus. Each master has its own GNT# line. GNT#
can be pulled away any time a higher REQ# is
received or if the master does not begin a cycle
within a set period of time.
(Strap)
GNT# is an output during normal operation. It is
an input at reset and functions as a boot strap for
frequency selection on a board. It must be pulled
high or low to invoke the strap.
GNT2# is reserved for the interface with the
AMD Geode CS5536 companion device.
AMD Geode™ LX Processors Data Book
39
33234H
3.4.6
TFT Display Interface Signals
Signal Name
Ball No.
Type
f
V
Description
DRGB[31:24]
DRGB[23:0]
I/O
0-162 Mb/s
3.3
Display Data Bus.
O
(PD)
DOTCLK
HSYNC
AE1
AE3
O
(PD)
0-162 MHz
0-162 Mb/s
3.3
Dot Clock. Output clock from DOTCLK PLL.
O
(PD)
3.3
(5vt)
Horizontal Sync. Horizontal Sync establishes
the line rate and horizontal retrace interval for an
attached flat panel. The polarity is programmable
(See Section 6.8.3.43 on page 451, VP Memory
Offset 400h[29]).
VSYNC
AD3
O
(PD)
0-162 Mb/s
3.3
(5vt)
Vertical Sync. Vertical Sync establishes the
screen refresh rate and vertical retrace interval
for an attached flat panel. The polarity is pro-
VP Memory Offset 400h[30]).
DISPEN
VDDEN
AE4
AE2
O
(PD)
0-162 Mb/s
0-162 Mb/s
3.3
3.3
Flat Panel Backlight Enable.
I/O
LCD VDD FET Control. When this output is
(PD)
asserted high, V voltage is applied to the
DD
panel. This signal is intended to control a power
FET to the LCD panel. The FET may be internal
to the panel or not, depending on the panel man-
ufacturer.
LDEMOD
AD4
AH11
AJ11
I/O
(PD)
0-162 Mb/s
0-75 Mb/s
0-75 Mb/s
0-75 Mb/s
3.3
3.3
3.3
3.3
Flat Panel Display Enable (TFT Panels).
MSGSTART
MSGSTOP
VID[15:8]
I
I
Message Start. Used in VIP message passing
mode to indicate start of message.
Message Stop. Used in VIP message passing
mode to indicate end of message.
I
Video Input Port Data. When in 16 bit VIP
mode, these are the eight MSBs of the VIP data.
(PD)
VOP[15:0]
O
0-75 Mb/s
3.3
Video Output Port Data. VOP output data.
VOPCLK
AE1
AE4
AE3
AD3
O
O
O
O
0-75 MHz
0-75 Mb/s
0-75 Mb/s
0-75 Mb/s
3.3
3.3
3.3
3.3
Video Output Port Clock.
VOP_BLANK
VOP_HSYNC
VOP_VSYNC
Video Output Port Blank.
Video Output Port Horizontal Sync.
Video Output Port Vertical Sync.
40
AMD Geode™ LX Processors Data Book
33234H
3.4.7
CRT Display Interface Signals
Signal Name
Ball No.
Type
f
V
Description
HSYNC
VSYNC
AE3
I/O
0-350 Mb/s
3.3
(5vt)
Horizontal Sync. Horizontal Sync establishes
the line rate and horizontal retrace interval for an
attached CRT. The polarity is programmable
Offset 008h[8]).
AD3
I/O
0-350 Mb/s
3.3
(5vt)
Vertical Sync. Vertical Sync establishes the
screen refresh rate and vertical retrace interval
for an attached CRT. The polarity is programma-
ory Offset 008h[9]).
DVREF
DRSET
W1
Y1
A
Analog
Analog
Analog
Analog
1.235
N/A
3.3
0
Video DAC Voltage Reference. Connect this
pin to a 1.235V voltage reference.
A
DAC Current Setting Resistor. 1.21K, 1% to
DAV
.
SS
DAV [3:0]
W4, V4,
V1, U1
APWR
AGND
DAC Analog Power Connection.
DAC Analog Ground Connection.
DD
DAV [3:0]
W2, Y2,
V3, U3
SS
RED
W3
V2
U2
A
A
A
Analog
Analog
Analog
N/A
N/A
N/A
Red DAC Output. Red analog output.
Green DAC Output. Green analog output.
Blue DAC Output. Blue analog output.
GREEN
BLUE
3.4.8
Signal Name
VIPCLK
VIP Interface Signals
Ball No.
Type
f
V
Description
AL12
I/O
0-75 MHz
3.3
Video Input Port Clock.
(PD)
VID[7:0]
AK12,
AL13,
AK13,
AJ13,
AH13,
AL15,
AK15,
AJ15
I/O
(PD)
0-150 Mb/s
3.3
Video Input Port Data.
VIPSYNC
AL14
I/O
0-150 Mb/s
3.3
Video Input Port Sync Signal.
(PD)
VIP_HSYNC
VIP_VSYNC
AE2
AD4
I
I
0-150 Mb/s
0-150 Mb/s
3.3
3.3
Video Input Port Horizontal Sync.
Video Input Port Vertical Sync.
AMD Geode™ LX Processors Data Book
41
33234H
3.4.9
Power and Ground Interface Signals
Signal Name
(Note 1)
Ball No.
Type
f
V
Description
V
V
V
V
PWR
N/A
1.2
Core Power Connection (Total of 32).
I/O Power Connection (Total of 30)
Memory Power Connection (Total of 33).
Ground Connection (Total of 128).
CORE
PWR
PWR
GND
N/A
N/A
N/A
3.3
2.5
0
IO
MEM
SS
Note 1.For module specific power and ground signals see:
For additional electrical details on pins, refer to Section 7.0 "Electrical Specifications" on page 597.
42
AMD Geode™ LX Processors Data Book
Signal Name
33234H
Table 3-7. Signal Behavior During and After Reset
Type
Behavior
Signal Name
Type
Behavior
Inputs during RESET# low
AD[31:0]
INTA#
PCI
TRI-STATE during RESET#
low
VID[7:0] (PD)
VIPCLK
CIS
Video
PAR
System
Debug
REQ#
TDBGI
TMS
IRDY#
FRAME#
GNT#
TDI
TCLK
SYREF
DOTREF
DEVSEL#
TRDY#
System
STOP#
Power-up states after RESET#
BA[1:0]
DDR
DRGB[31:24]
Video
TRI-STATE with pin PD:
CAS[1:0]#
CBE[3:0]#
CS[3:0]#
DQ[63:0]
DQM[7:0]
DQS[7:0]
MA[13:0]
RAS[1:0]#
SDCLK[5:0]P
SDCLK[5:0]N
TLA[1:0]
WE[1:0]#
TDO
—Display filter can enable
outputs to drive alpha
(disables PDs).
—VIP can enable as inputs
(disables PDs).
DRGB[23:0]
DOTCLK
HSYNC
Driven
VSYNC
DISPEN
VDDEN
Input with PD
Input with PD:
LDEMOD
VID[7:0]
VIPCLK
Debug
TDBGO
VIPSYNC
VIPSYNC (PD)
IRQ13
VIP
—PD remains if pin is used
as input.
—PD disables if VIP drives
pin.
System
SUSPA#
DRGB[31:24]
VSYNC
Video
Video
PD during reset.
PW[1:0]
System
TRI-STATE
Driven low during RESET# low
HSYNC
DISPEN
DOTCLK
DRGB[23:0]
LDEMOD
VDDEN
CKE[1:0]#
DDR
AMD Geode™ LX Processors Data Book
43
GeodeLink™ Interface Unit
33234H
4.0GeodeLink™ Interface Unit
4
Many traditional architectures use buses to connect mod-
ules together, which usually requires unique addressing for
each register in every module. This requires that some kind
of house-keeping be done as new modules are designed
and new devices are created from the module set. Using
module select signals to create the unique addresses can
get cumbersome and requires that the module selects be
sourced from some centralized location.
4.1
MSR Set
The AMD Geode™ LX processor incorporates two GLIUs
into its device architecture. Except for the configuration
registers that are required for x86 compatibility, all internal
registers are accessed through a Model Specific Register
(MSR) set. MSRs have a 32-bit address space and a 64-bit
data space. The full 64-bit data space is always read or
written when accessed.
To alleviate this issue, AMD developed an internal bus
architecture based on GeodeLink™ technology. The
GeodeLink architecture connects the internal modules of a
device using the data ports provided by GeodeLink Inter-
face Units (GLIUs). Using GLIUs, all internal module port
addresses are derived from the distinct port that the mod-
ule is connected to. In this way, a module’s Model Specific
Registers (MSRs) do not have unique addresses until a
device is defined. Also, as defined by the GeodeLink archi-
tecture, a module’s port address depends on the location of
the module sourcing the cycle, or source module (e.g.,
source module can be CPU Core, GLCP, and GLPCI; how-
ever, under normal operating conditions, accessing MSRs
is from the CPU Core).
An MSR can be read using the RDMSR instruction, opcode
0F32h. During an MSR read, the contents of the particular
MSR, specified by the ECX register, are loaded into the
EDX:EAX registers. An MSR can be written using the
WRMSR instruction, opcode 0F30h. During an MSR write,
the contents of EDX:EAX are loaded into the MSR speci-
fied in the ECX register. The RDMSR and WRMSR instruc-
tions are privileged instructions.
ules within the AMD Geode LX processor with the CPU
Core as the source module.
Table 4-1. MSR Addressing
MSR Address
Module Name
GLIU
Port
(Relative to CPU Core)
GeodeLink™ Interface Unit 0 (GLIU0)
GeodeLink Memory Controller (GLMC)
CPU Core (CPU Core)
0
0
0
0
0
1
1
1
1
1
1
0
1
3
4
5
0
2
3
4
5
6
1000xxxxh
2000xxxxh
0000xxxxh
8000xxxxh
A000xxxxh
4000xxxxh
4800xxxxh
4C00xxxxh
5000xxxxh
5400xxxxh
5800xxxxh
Display Controller (DC)
Graphics Processor (GP)
GeodeLink Interface Unit 1 (GLIU1)
Video Processor (VP)
GeodeLink Control Processor (GLCP)
GeodeLink PCI Bridge (GLPCI)
Video Input Port (VIP)
Security Block (SB)
AMD Geode™ LX Processors Data Book
45
33234H
GeodeLink™ Interface Unit
4.1.1
Port Address
Each GLIU has seven channels with Channel 0 being the
GLIU itself and therefore not considered a physical port.
Figure 4-1 illustrates the GeodeLink architecture in a
AMD Geode LX processor, showing how the modules are
connected to the two GLIUs. GLIU0 has five channels con-
nected, and GLIU1 has six channels connected. To get
MSR address/data across the PCI bus, the GLPCI converts
the MSR address into PCI cycles and back again.
GLMC
1
CPU Core
3
0
7
4
Not Used
DC
GLIU0
An MSR address is parsed into two fields, the port address
(18 bits) and the index (14 bits). The port address is further
parsed into six 3-bit channel address fields. Each 3-bit field
represents, from the perspective of the source module, the
GLIU channels that are used to get to the destination mod-
ule, starting from the closest GLIU to the source (left most
3-bit field) to the farthest GLIU (right most 3-bit field).
6
5
Not Used
GP
2
GLIU0
GLIU1
In aN AMD Geode LX processor/CS5536 system, the com-
panion device is connected to the processor via the PCI
bus. The internal architecture of the companion device
uses the same GeodeLink architecture with one GLIU
being in that device. Hence, in a AMD Geode LX proces-
sor/CS5536 system there are a total of three GLIUs: two in
the processor and one in the companion device. Therefore
at most, only the two left most 3-bit fields of the base
address field should be needed to access any module in
the system. There are exceptions that require more; see
For the CPU Core to access MSR Index 300h in the
GeodeLink Control Processor (GLCP) module, the address
is 010_011_000_000_000_000b (six channel fields of the
port address) + 300h (Index), or 4C000300h. The 010b
points to Channel 2 of GLIU0, which is the channel con-
nected to GLIU1. The 011b points to the GLIU1 Channel 3,
which is the channel to the GLCP module. From this point
on, the port address is abbreviated by noting each channel
address followed by a dot. From the above example, this is
represented by 2.3.0.0.0.0. It is important to repeat here
that the port address is derived from the perspective of the
source module.
1
VP
3
2
0
7
Not Used
GLCP
GLIU1
5
6
SB
(AES)
4
VIP
GLPCI
GLPCI
PCI Bus
Figure 4-1. GeodeLink™ Architecture
For a module to access an MSR within itself, the port
address is zero.
46
AMD Geode™ LX Processors Data Book
GeodeLink™ Interface Unit
33234H
4.1.2
Port Addressing Exceptions
Table 4-2. MSR Mapping
There are some exceptions to the port addressing rules.
Source (Note 1)
If a module accesses an MSR from within its closest GLIU
(e.g., CPU Core accessing a GLIU0 MSR), then, by con-
vention, the port address should be 0.0.0.0.0.0. But this
port address accesses an MSR within the source module
and not the GLIU as desired. To get around this, if the port
address contains a 0 in the first channel field and then con-
tains a 1 in any of the other channel fields, the access goes
to the GLIU nearest the module sourcing the cycle. By con-
vention, set the MSB of the second channel field,
0.4.0.0.0.0. If the MSR access is to a GLIU farther removed
from the module sourcing the cycle, then there is no con-
vention conflict, so no exception is required for that situa-
tion.
Destination
CPU Core
GLCP
GLPCI
CPU Core
GLIU0
GLMC
GLIU1
GLCP
GLPCI
DC
0000xxxxh
1000xxxxh
2000xxxxh
4000xxxxh
4C00xxxxh
5000xxxxh
8000xxxxh
A000xxxxh
4800xxxxh
5400xxxxh
5800xxxxh
2C00xxxxh
2000xxxxh
2400xxxxh
1000xxxxh
0000xxxxh
8000xxxxh
3000xxxxh
3400xxxxh
4000xxxxh
2C00xxxxh
2000xxxxh
2400xxxxh
1000xxxxh
6000xxxxh
0000xxxxh
3000xxxxh
3400xxxxh
3800xxxxh
GP
If a module attempts to access an MSR to the channel that
it is connected to, a GLIU error results. This is called a
reflective address attempt. An example of this case is the
CPU Core accessing 3.0.0.0.0.0. Since the CPU Core is
connected to Channel 3 of GLIU0, the access causes a
reflective address error. This exception is continued to the
next GLIU in the chain. The CPU Core accessing
2.1.0.0.0.0 also causes a reflective address error.
VP
VIP
Security Block
Companion
Device
51Y0xxxxh
(Note 2)
8ZK0xxxxh
(Note 3)
NA
Note 1. The xxxx contains the lower two bits of the 18 bits from
the port fields plus the 14-bit MSR offset.
To access modules in the AMD Geode companion device,
the port address must go through the GLPCI (PCI control-
ler) in the processor and through the GLPCI in the compan-
ion device. The port address of the MSRs in the
processor’s GLPCI when accessed from the CPU Core is
2.4.0.0.0.0. To get the port address to go through the
GLPCI, the third field needs a non-zero value. By conven-
tion, this is a 2. We now have a port address of 2.4.2.0.0.0.
But this accesses the MSRs in the GLPCI in the compan-
ion device. The port to be accessed must be added in the
fourth field, 2.4.2.5.0.0, to access the AC97 audio bus mas-
ter, for example.
Note 2. Y is the hex value obtained from one bit (always a 0) plus
the port number (#) of the six port field addresses [0+#].
Example: # = 5, therefore the Y value is [0+101] which is
5h, thus the address = 5150xxxxh.
Note 3. ZK are the hex values obtained from the concatenation
of [10+#+000], where # is the port number from the six
port field address. Example # = 5, the ZK value is
[10+101+000] which is [1010,1000]. In hex. it is A8h; thus
the address is 8A80xxxxh.
4.1.3
Memory and I/O Mapping
The GLIU decodes the destination ID of memory requests
using a series of physical to device (P2D) descriptors.
There can be up to 32 descriptors in each GLIU. The GLIU
decodes the destination ID of I/O requests using a series of
I/O descriptors (IOD).
To access the GLIU in the companion device, the same
addressing exception occurs as with GLIU0 due to the
GLPCI’s address. A port address of 2.4.2.0.0.0 accesses
the companion device’s GLPCI, not the GLIU. To solve this,
a non-zero value must be in at least one of the two right-
most port fields. By convention, a 4 in the left-most port
field is used. To access the companion device’s GLIU from
the CPU Core, the port address is 2.4.2.0.0.4.
4.1.3.1 Memory Routing and Translation
Memory addresses are routed and optionally translated
from physical space to device space. Physical space is the
32-bit memory address space that is shared between all
GeodeLink devices. Device space is the unique address
space within a given device. For example, a memory con-
troller may implement a 4 MB frame buffer region in the 12-
16 MB range of main memory. However, the 4 MB region
may exist in the 4 GB region of physical space. The actual
location of the frame buffer in the memory controller with
respect to itself is a device address, while the address that
all the devices see in the region of memory is in physical
space.
modules in a AMD Geode LX processor/CS5536 system
with the CPU Core as the source module. Included in the
table is the MSR port address for module access using the
GLCP and GLPCI as the source module. However, under
normal operating conditions, accessing MSRs is from the
CPU Core. Therefore, all MSR addresses in the following
chapters of this data book are documented using the CPU
Core as the source.
Memory request routing and translation is performed with a
choice of five descriptor types. Each GLIU may have any
number of each descriptor type up to a total of 32. The P2D
descriptor types satisfy different needs for various software
models.
AMD Geode™ LX Processors Data Book
47
33234H
GeodeLink™ Interface Unit
Each memory request is compared against all the P2D
descriptors. If the memory request does not hit in any of
the descriptors, the request is sent to the subtractive port. If
the memory requests hit more than one descriptor, the
results are undefined. The software must provide a consis-
tent non-overlapping address map.
P2D Range Descriptor (P2D_R)
P2D_R maps a range of addresses to a device that is NOT
a power of 2 size aligned. There is no address translation
P2D Range Offset Descriptor (P2D_RO)
P2D_RO has the same address routing as P2D_R with the
addition of address translation with a 2s complement off-
set.
The way each descriptor checks if the request address hits
its descriptor and how to route the request address to the
P2D Swiss Cheese Descriptor (P2D_SC)
P2D Base Mask Descriptor (P2D_BM)
The P2D_SC maps a 256 KB region of memory in 16 KB
chunks to a device or the subtractive decode port. The
descriptor type is useful for legacy address mapping. The
Swiss cheese feature implies that the descriptor is used to
“poke holes” in memory.
P2D_BM is the simplest descriptor. It usually maps a power
of two size aligned region of memory to a destination ID.
P2D_BM performs no address translation.
P2D Base Mask Offset Descriptor (P2D_BMO)
P2D_BMO has the same routing features as P2D_BM with
the addition of a 2s complement address translation to the
most-significant bits of the address.
Note: Only one P2D can hit at a time for a given port. If
the P2D descriptors are overlapping, the results
are undefined.
Table 4-3. GLIU Memory Descriptor Address Hit and Routing Description
Descriptor
Function Description
P2D_BM,
P2D_BMO
Checks that the physical address supplied by the device’s request on address bits [31:12] with a logical AND with
PMASK bits of the descriptor register bits [19:0] are equal to the PBASE bits on the descriptor register (bits [39:20]).
Also checks that the BIZZARO bit of the request is equal to the PCMP_BIZ bit of the descriptor register bit [60].
If the above matches, then the descriptor has a hit condition and it routes the received address to the programmed des-
tination PDID1 of the descriptor register (bits [63:61]).
For P2D_BM:
DEVICE_ADDR = request address
For P2D_BMO:
DEVICE_ADDR [31:12] = [request address [31:12] + descriptor POFFSET]
DEVICE_ADDR [11:0] = request address [11:0]
P2D_R,
P2D_RO
Checks that the physical address supplied by the device’s request on address bits [31:12] are within the range speci-
fied by PMIN and PMASK field bits [39:20] and [19:0], respective of the descriptor register. PMIN is the minimum
address range and PMAX is the maximum address range.The condition is: PMAX > physical address [31:12] > PMIN.
Also checks that the BIZZARO bit of the request is equal to the PCMP_BIZ bit of the descriptor register bit [60].
If the above matches, then the descriptor has a hit condition and routes the received address to the programmed des-
tination ID, PDID1 of the descriptor register (bits [63:61]).
For P2D_R:
DEVICE_ADDR = request address
For P2D_RO:
DEVICE_ADDR [31:12] = [request address [31:12] + descriptor POFFSET]
DEVICE_ADDR [11:0] = request address [11:0]
P2D_SC
Checks that the physical address supplied by the device’s request on address bits [31:18] are equal to the PBASE field
of descriptor register bits [13:0] and that the enable write or read conditions given by the descriptor register fields WEN
and REN in bits [47:32] and [31:16], respectively matches the request type and enable fields given on the physical
address bits [17:14] of the device’s request.
If the above matches, then the descriptor has a hit condition and routes the received address to the programmed des-
tination ID, PDID1 field of the descriptor register bits [63:61].
DEVICE_ADDR = request address
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GeodeLink™ Interface Unit
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4.1.3.2 I/O Routing and Translation
for legacy address mapping. The Swiss cheese feature
implies that the descriptor is used to “poke holes” in I/O.
I/O addresses are routed and are never translated. I/O
request routing is performed with a choice of two descriptor
types. Each GLIU may have any number of each descriptor
type. The IOD types satisfy different needs for various soft-
ware models.
4.1.3.3 Special Cycles
PCI special cycles are performed using I/O writes and set-
ting the BIZARRO flag in the write request. The BIZARRO
flag is treated as an additional address bit, providing
unaliased I/O address. The I/O descriptors are set up to
route the special cycles to the appropriate device (i.e.,
GLCP, GLPCI, etc.). The I/O descriptors are configured to
default to the appropriate device on reset. The PCI special
cycles are mapped as:
Each I/O request is compared against all the IOD. If the I/O
request does not hit in any of the descriptors, the request is
sent to the subtractive port. If the I/O request hits more
than one descriptor, the results are undefined. Software
must provide a consistent non-overlapping I/O address
map. The methods of check and routing are described in
Name
BIZZARO
Address
Shutdown
Halt
x86 specific
0003h-FFFFh
1
1
1
1
00000000h
00000001h
00000002h
00000002h-0000FFFFh
IOD Base Mask Descriptors (IOD_BM)
IOD_BM is the simplest descriptor. It usually maps a power
of two size aligned region of I/O to a destination ID.
IOD Swiss Cheese Descriptors (IOD_SC)
The IOD_SC maps an 8-byte region of memory in 1 byte
chunks to one of two devices. The descriptor type is useful
Table 4-4. GLIU I/O Descriptor Address Hit and Routing Description
Descriptor
Function Description
IOD_BM
Checks that the physical address supplied by the device on address bits [31:12] with a logic AND with PMASK bits of
the register bits [19:0] are equal to the PBASE bits of the descriptor register bits [39:20].
Also checks that the BIZZARO bit of the request is equal to the PCMP_PIZ bit of the descriptor register bit [60].
If the above matches, then the descriptor has a hit condition and routes the received address to the programmed des-
tination of the P2D_BM register bit [63:61].
DEVICE_ADDR = request address
IOD_SC
Checks that the physical address supplied by the device’s request on address bits [31:18] are equal to the PBASE field
of descriptor register bits [13:0] and that the enable write or read conditions given by the descriptor register fields WEN
and REN in bits [47:32] and [31:16], respectively matches the request type and enable fields given on the physical
address bits [17:14] of the device’s request.
If the above matches, then the descriptor has a hit condition and routes the received address to the programmed des-
tination ID, PDID1 field of the descriptor register bits [63:61].
DEVICE_ADDR = request address
AMD Geode™ LX Processors Data Book
49
33234H
GLIU Register Descriptions
4.2
GLIU Register Descriptions
All GeodeLink™ Interface Unit (GLIU) registers are Model
Specific Registers (MSRs) and are accessed through the
RDMSR and WRMSR instructions.
register summary tables that include reset values and page
references where the bit descriptions are provided.
Note: The MSR address is derived from the perspective
of the CPU Core. See Section 4.1 "MSR Set" on
page 45 for more details on MSR addressing.
The registers associated with the GLIU are the Standard
GeodeLink Device (GLD) MSRs, GLIU Specific MSRs.
GLIU Statistic and Comparator MSRs, P2D Descriptor
MSRs, and I/O Descriptor MSRs. The tables that follow are
Reserved (RSVD) fields do not have any meaningful stor-
age elements. They always return 0.
Table 4-5. GeodeLink™ Device Standard MSRs Summary
Type Register Name Reset Value
MSR Address
Reference
GLIU0: 10002000h
GLIU1: 40002000h
00000000_000014xxh
Page 55
GLIU0: 10002001h
GLIU1: 40002001h
GLIU0:
00000000_00000002h
GLIU1:
Page 55
00000000_00000004h
GLIU0: 10002002h
GLIU1: 40002002h
00000000_00000001h
00000000_00000000h
00000000_00000000h
00000000_00000000h
Page 56
Page 57
Page 59
Page 60
GLIU0: 10002003h
GLIU1: 40002003h
GLIU0: 10002004h
GLIU1: 40002004h
GLIU0: 10002005h
GLIU1: 40002005h
Table 4-6. GLIU Specific MSRs Summary
Type Register Name
MSR Address
Reset Value
Reference
GLIU0: 10000080h
GLIU1: 40000080h
GLIU0: 10000081h
GLIU1: 40000081h
Page 65
GLIU0: 10000082h
GLIU1: 40000082h
GLIU0: 10000083h
GLIU1: 40000083h
GLIU0: 10000084h
GLIU1: 40000084h
GLIU0: 10000086h
GLIU1: 40000086h
GLIU0:
20291830_010C1086h
GLIU1:
20311030_0100400Ah
GLIU0: 10000087h
GLIU1: 40000087h
GLIU0: 10000088h
GLIU1: 40000088h
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GLIU Register Descriptions
33234H
Table 4-6. GLIU Specific MSRs Summary (Continued)
MSR Address
Type Register Name
Reset Value
Reference
GLIU0: 10000089h
GLIU1: 40000089h
00000000_00000010h
GLIU1:
GLIU0: 1000008Ah
GLIU1: 4000008Ah
RO
Reserved
---
---
GLIU0: 1000008Bh
GLIU1: 4000008Bh
GLIU0: 1000008Ch
GLIU1: 4000008Ch
GLIU0: 1000008Dh
GLIU1: 4000008Dh
Table 4-7. GLIU Statistic and Comparator MSRs Summary
Type Register Reset Value
WO Descriptor Statistic Counter
MSR Address
Reference
GLIU0: 100000A0h
GLIU1: 400000A0h
00000000_00000000h
00000000_00000000h
00000000_00000000h
--
Page 71
(STATISTIC_CNT[0])
GLIU0: 100000A1h
GLIU1: 400000A1h
R/W Descriptor Statistic Mask
(STATISTIC_MASK[0])
Page 72
Page 73
--
GLIU0: 100000A2h
GLIU1: 400000A2h
R/W Descriptor Statistic Action
(STATISTIC_ACTION[0])
GLIU0: 100000A3h
GLIU1: 400000A3h
--
Reserved
GLIU0: 100000A4h
GLIU1: 400000A4h
WO
Descriptor Statistic Counter
(STATISTIC_CNT[1])
00000000_00000000h
00000000_00000000h
00000000_00000000h
--
Page 71
Page 72
Page 73
--
GLIU0: 100000A5h
GLIU1: 400000A5h
R/W Descriptor Statistic Mask
(STATISTIC_MASK[1])
GLIU0: 100000A6h
GLIU1: 400000A6h
R/W Descriptor Statistic Action
(STATISTIC_ACTION[1])
GLIU0: 100000A7h
GLIU1: 400000A7h
--
Reserved
GLIU0: 100000A8h
GLIU1: 400000A8h
WO
Descriptor Statistic Counter
(STATISTIC_CNT[2])
00000000_00000000h
00000000_00000000h
00000000_00000000h
--
Page 71
Page 72
Page 73
--
GLIU0: 100000A9h
GLIU1: 400000A9h
R/W Descriptor Statistic Mask
(STATISTIC_MASK[2])
GLIU0: 100000AAh
GLIU1: 400000AAh
R/W Descriptor Statistic Action
(STATISTIC_ACTION[2])
GLIU0: 100000ABh
GLIU1: 40000ABh
--
Reserved
GLIU0: 100000ACh
GLIU1: 400000ACh
WO
Descriptor Statistic Counter
(STATISTIC_CNT[3])
00000000_00000000h
00000000_00000000h
00000000_00000000h
Page 71
Page 72
Page 73
GLIU0: 100000ADh
GLIU1: 400000ADh
R/W Descriptor Statistic Mask
(STATISTIC_MASK[3])
GLIU0: 100000AEh
GLIU1: 400000AEh
R/W Descriptor Statistic Action
(STATISTIC_ACTION[3])
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GLIU Register Descriptions
Table 4-7. GLIU Statistic and Comparator MSRs Summary (Continued)
MSR Address
Type Register
Reset Value
Reference
GLIU0: 100000C0h
GLIU1: 400000C0h
R/W Request Compare Value
(RQ_COMPARE_VAL[0])
001FFFFF_FFFFFFFFh
Page 74
GLIU0: 100000C1h
GLIU1: 400000C1h
R/W Request Compare Mask
(RQ_COMPARE_MASK[0])
00000000_00000000h
001FFFFF_FFFFFFFFh
00000000_00000000h
001FFFFF_FFFFFFFFh
00000000_00000000h
001FFFFF_FFFFFFFFh
00000000_00000000h
--
Page 75
Page 74
Page 75
Page 74
Page 75
Page 74
Page 75
--
GLIU0: 100000C2h
GLIU1: 400000C2h
R/W Request Compare Value
(RQ_COMPARE_VAL[1])
GLIU0: 100000C3h
GLIU1: 400000C3h
R/W Request Compare Mask
(RQ_COMPARE_MASK[1])
GLIU0: 100000C4h
GLIU1: 400000C4h
R/W Request Compare Value
(RQ_COMPARE_VAL[2])
GLIU0: 100000C5h
GLIU1: 400000C5h
R/W Request Compare Mask
(RQ_COMPARE_MASK[2])
GLIU0: 100000C6h
GLIU1: 400000C6h
R/W Request Compare Value
(RQ_COMPARE_VAL[3])
GLIU0: 100000C7h
GLIU1: 400000C7h
R/W Request Compare Mask
(RQ_COMPARE_MASK[3])
GLIU0: 100000C9h
GLIU1: 400000CFh
--
Reserved
GLIU0: 100000D0h
GLIU1: 400000D0h
R/W Data Compare Value Low
(DA_COMPARE_VAL_LO[0])
00001FFF_FFFFFFFFh
0000000F_FFFFFFFFh
00000000_00000000h
00000000_00000000h
00001FFF_FFFFFFFFh
0000000F_FFFFFFFFh
00000000_00000000h
00000000_00000000h
00000000_00000000h
0000000F_FFFFFFFFh
00000000_00000000h
00000000_00000000h
00001FFF_FFFFFFFFh
0000000F_FFFFFFFFh
Page 76
Page 77
Page 78
Page 79
Page 76
Page 77
Page 78
Page 79
Page 79
Page 77
Page 78
Page 79
Page 76
Page 77
GLIU0: 100000D1h
GLIU1: 400000D1h
R/W Data Compare Value High
(DA_COMPARE_VAL_HI[0])
GLIU0: 100000D2h
GLIU1: 400000D2h
R/W Data Compare Mask Low
(DA_COMPARE_MASK_LO[0])
GLIU0: 100000D3h
GLIU1: 400000D3h
R/W Data Compare Mask High
(DA_COMPARE_MASK_HI[0])
GLIU0: 100000D4h
GLIU1: 400000D4h
R/W Data Compare Value Low
(DA_COMPARE_VAL_LO[1])
GLIU0: 100000D5h
GLIU1: 400000D5h
R/W Data Compare Value High
(DA_COMPARE_VAL_HI[1])
GLIU0: 100000D6h
GLIU1: 400000D6h
R/W Data Compare Mask Low
(DA_COMPARE_MASK_LO[1])
GLIU0: 100000D7h
GLIU1: 400000D7h
R/W Data Compare Mask High
(DA_COMPARE_MASK_HI[1])
GLIU0: 100000DBh
GLIU1: 400000DBh
R/W Data Compare Value Low
(DA_COMPARE_VAL_LO[2])
GLIU0: 100000D9h
GLIU1: 400000D9h
R/W Data Compare Value High
(DA_COMPARE_VAL_HI[2])
GLIU0: 100000DAh
GLIU1: 400000DAh
R/W Data Compare Mask Low
(DA_COMPARE_MASK_LO[2])
GLIU0: 100000DBh
GLIU1: 400000DBh
R/W Data Compare Mask High
(DA_COMPARE_MASK_HI[2])
GLIU0: 100000DCh
GLIU1: 400000DCh
R/W Data Compare Value Low
(DA_COMPARE_VAL_LO[3])
GLIU0: 100000DDh
GLIU1: 400000DDh
R/W Data Compare Value High
(DA_COMPARE_VAL_HI[3])
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AMD Geode™ LX Processors Data Book
GLIU Register Descriptions
33234H
Table 4-7. GLIU Statistic and Comparator MSRs Summary (Continued)
MSR Address
Type Register
Reset Value
Reference
GLIU0: 100000DEh
GLIU1: 400000DEh
R/W Data Compare Mask Low
(DA_COMPARE_MASK_LO[3])
00000000_00000000h
Page 78
GLIU0: 100000DFh
GLIU1: 400000DFh
R/W Data Compare Mask High
(DA_COMPARE_MASK_HI[3])
00000000_00000000h
Page 79
Table 4-8. GLIU P2D Descriptor MSRs Summary
MSR Address
GLIU0
Type
Register
Reset Value
Reference
R/W
P2D Base Mask Descriptor
(P2D_BM): P2D_BM[5:0]
---
---
P2D Base Mask Offset Descriptor
(P2D_BMO): P2D_BMO[1:0]
P2D Range Descriptor (P2D_R:
P2D_R[0]
P2D Range Offset Descriptor
(P2D_RO): P2D_RO[2:0]
P2D Swiss Cheese Descriptor
(P2D_SC): P2D_SC[0]
1000002Dh-
1000003Fh
P2D Reserved Descriptors
GLIU1
R/W
P2D Base Mask Descriptor
(P2D_BM): P2D_BM[9:0]
00000000_00000000h
---
P2D Range Descriptor (P2D_R):
P2D_R[3:0]
P2D Swiss Cheese Descriptor
(P2D_SC): P2D_SC[0]
4000002Fh-
4000003Fh
P2D Reserved Descriptor
(P2D_RSVD)
Table 4-9. GLIU Reserved MSRs Summary
Register
MSR Address
Type
Reset Value
Reference
GLIU0:10000006h-
1000000Fh
GLIU1:40000006h-
4000000Fh
R/W
Reserved for future use by AMD.
Reserved for future use by AMD.
Reserved for future use by AMD.
00000000_00000000h
00000000_00000000h
00000000_00000000h
---
GLIU0:10000040h-
1000004Fh
GLIU1:40000040h-
4000004Fh
R/W
R/W
---
---
GLIU0:10000050h-
1000007Fh
GLIU1:40000050h-
4000007Fh
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GLIU Register Descriptions
Table 4-10. GLIU IOD Descriptor MSRs Summary
Register
MSR Address
GLIU0
Type
Reset Value
Reference
100000E0h-
100000E2h
R/W
R/W
R/W
IOD Reserved Descriptors
000000FF_FFF00000h
Page 86
Page 87
---
100000E3h-
100000E8h
00000000_00000000h
---
100000E9h-
100000FFh
GLIU1
400000E0h-
400000E2h
R/W
R/W
R/W
IOD Reserved Descriptors
000000FF_FFF00000h
00000000_00000000h
---
Page 86
Page 87
---
400000E3h-
400000E6h
400000E7h-
400000FFh
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GLIU Register Descriptions
33234H
4.2.1
Standard GeodeLink™ Device (GLD) MSRs
4.2.1.1 GLD Capabilities MSR (GLD_MSR_CAP)
MSR Address
GLIU0: 10002000h
GLIU1: 40002000h
RO
Type
Reset Value
00000000_000014xxh
GLD_MSR_CAP Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
DEV_ID
REV_ID
GLD_MSR_CAP Bit Descriptions
Bit
Name
Description
63:24
23:8
7:0
RSVD
Reserved.
DEV_ID
REV_ID
Device ID. Identifies device (0014h).
Revision ID. Identifies device revision. See AMD Geode™ LX Processors Specification
Update document for value
4.2.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)
MSR Address
GLIU0: 10002001h
GLIU1: 40002001h
R/W
Type
Reset Value
GLIU0: 00000000_00000002h
GLIU1: 00000000_00000004h
GLD_MSR_CONFIG Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SUBP
GLD_MSR_CONFIG Bit Descriptions
Bit
Name
Description
Reserved.
63:3
2:0
RSVD
SUBP
Subtractive Port. Subtractive port assignment for all negative decode requests.
000: Port 0 (GLIU0 = GLIU; GLIU1 = GLIU)
001: Port 1 (GLIU0 = GLMC; GLIU1 = Interface to GLIU0)
010: Port 2 (GLIU0 = Interface to GLIU1; GLIU1 = VP)
011: Port 3 (GLIU0 = CPU Core; GLIU1 = GLCP)
100: Port 4 (GLIU0 = DC; GLIU1 = GLPCI)
101: Port 5 (GLIU0 = GP; GLIU1 = VIP)
110: Port 6 (GLIU0 = Not Used; GLIU1 = SB)
111: Port 7 (GLIU0 = Not Used; GLIU1 = Not Used)
AMD Geode™ LX Processors Data Book
55
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GLIU Register Descriptions
4.2.1.3 GLD SMI MSR (GLD_MSR_SMI)
MSR Address
GLIU0: 10002002h
GLIU1: 40002002h
R/W
Type
Reset Value
00000000_00000001h
The flags are set with internal conditions. The internal conditions are always capable of setting the flag, but if the mask is 1,
the flagged condition will not trigger the SMI signal. Reads to the flags return the value. Write = 1 to the flag, clears the
value. Write = 0 has no effect on the flag.
GLD_MSR_SMI Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
GLD_MSR_SMI Bit Descriptions
Bit
Name
Description
Reserved.
63:37
36
RSVD
SFLAG4
SMI Flag4. If high, records that an SMI was generated due to a Statistic Counter 3
(GLIU0 MSR 100000ACh, GLIU1 MSR 400000ACh) event. Write 1 to clear; writing 0 has
no effect. SMASK4 (bit 4) must be low to generate SMI and set flag.
35
34
33
SFLAG3
SFLAG2
SFLAG1
SMI Flag3. If high, records that an SMI was generated due to a Statistic Counter 2
(GLIU0 MSR 100000A8h, GLIU1 MSR 400000A8h) event. Write 1 to clear; writing 0 has
no effect. SMASK3 (bit 3) must be low to generate SMI and set flag.
SMI Flag2. If high, records that an SMI was generated due to a Statistic Counter 1
(GLIU0 MSR 100000A4h, GLIU1 MSR 400000A4h) event. Write 1 to clear; writing 0 has
no effect. SMASK2 (bit 2) must be low to generate SMI and set flag.
SMI Flag1. If high, records that an SMI was generated due to a Statistic Counter 0
(GLIU0 MSR 100000A0h, GLIU1 MSR 400000A0h) event. Write 1 to clear; writing 0 has
no effect. SMASK1 (bit 1) must be low to generate SMI and set flag.
32
31:5
4
SFLAG0
RSVD
SMI Flag0. Unexpected Type (HW Emulation).
Reserved.
SMASK4
SMI Mask4. Write 0 to enable SFLAG4 (bit 37) and to allow a Statistic Counter 3 (GLIU0
MSR 100000ACh, GLIU1 MSR 400000ACh) event to generate an SMI.
3
2
1
0
SMASK3
SMASK2
SMASK1
SMASK0
SMI Mask3. Write 0 to enable SFLAG3 (bit 36) and to allow a Statistic Counter 2 (GLIU0
MSR 100000A8h, GLIU1 MSR 400000A8h) event to generate an SMI.
SMI Mask2. Write 0 to enable SFLAG2 (bit 34) and to allow a Statistic Counter 1 (GLIU0
MSR 100000A4h, GLIU1 MSR 400000A4h) event to generate an SMI.
SMI Mask1. Write 0 to enable SFLAG1 (bit 33) and to allow a Statistic Counter 0 (GLIU0
MSR 100000A0h, GLIU1 MSR 400000A0h) event to generate an SMI.
SMI Mask0. Unexpected Type (HW Emulation).
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AMD Geode™ LX Processors Data Book
GLIU Register Descriptions
33234H
4.2.1.4 GLD Error MSR (GLD_MSR_ERROR)
MSR Address
GLIU0: 10002003h
GLIU1: 40002003h
R/W
Type
Reset Value
00000000_00000000h
The flags are set with internal conditions. The internal conditions are always capable of setting the flag, but if the mask is 1,
the flagged condition will not trigger the ERR signal. Reads to the flags return the value. Write = 1 to the flag, clears the
value. Write = 0 has no effect on the flag.
GLD_MSR_ERROR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
GLD_MSR_ERROR Bit Descriptions
Bit
Name
Description
Reserved.
63:47
46
RSVD
EFLAG14
Data Comparator Error Flag 3. If high, records that an ERR was generated due to a
Data Comparator 3 (DA_COMPARE_VAL_LO3/DA_COMPARE_VAL_HI3, GLIU0 MSR
100000DCh/100000DDh, GLIU1 MSR 400000DCh/400000DDh) event. Write 1 to clear;
writing 0 has no effect. EMASK14 (bit 14) must be low to generate ERR and set flag.
45
44
43
42
41
40
EFLAG13
EFLAG12
EFLAG11
EFLAG10
EFLAG9
EFLAG8
Data Comparator Error Flag 2. If high, records that an ERR was generated due to a
Data Comparator 2 (DA_COMPARE_VAL_LO2/DA_COMPARE_VAL_HI2, GLIU0 MSR
100000D8h/100000D9h, GLIU1 MSR 400000D8h/400000D9h) event. Write 1 to clear;
writing 0 has no effect. EMASK13 (bit 13) must be low to generate ERR and set flag.
Data Comparator Error Flag 1. If high, records that an ERR was generated due to a
Data Comparator 1 (DA_COMPARE_VAL_LO1/DA_COMPARE_VAL_HI1, GLIU0 MSR
100000D4h/100000D5h, GLIU1 MSR 400000D4h/400000D5h) event. Write 1 to clear;
writing 0 has no effect. EMASK12 (bit 12) must be low to generate ERR and set flag.
Data Comparator Error Flag 0. If high, records that an ERR was generated due to a
Data Comparator 0 (DA_COMPARE_VAL_LO0/DA_COMPARE_VAL_HI0, GLIU0 MSR
100000D0h/100000D1h, GLIU1 MSR 400000D0h/400000D1h) event. Write 1 to clear;
writing 0 has no effect. EMASK11(bit 11) must be low to generate ERR and set flag.
Request Comparator Error Flag 3. If high, records that an ERR was generated due to a
Request Comparator 3 (RQ_COMPARE_VAL3, GLIU0 MSR 100000C6h, GLIU1 MSR
400000C6h) event. Write 1 to clear; writing 0 has no effect. EMASK10 (bit 10) must be
low to generate ERR and set flag.
Request Comparator Error Flag 2. If high, records that an ERR was generated due to a
Request Comparator 2 (RQ_COMPARE_VAL2, GLIU0 MSR 100000C4h, GLIU1 MSR
400000C4h) event. Write 1 to clear; writing 0 has no effect. EMASK9 (bit 9) must be low
to generate ERR and set flag.
Request Comparator Error Flag 1. If high, records that an ERR was generated due to a
Request Comparator 1 (RQ_COMPARE_VAL1, GLIU0 MSR 100000C2h, GLIU1 MSR
400000C2h) event. Write 1 to clear; writing 0 has no effect. EMASK8 (bit 8) must be low
to generate ERR and set flag.
AMD Geode™ LX Processors Data Book
57
33234H
GLIU Register Descriptions
GLD_MSR_ERROR Bit Descriptions (Continued)
Description
Bit
Name
39
EFLAG7
Request Comparator Error Flag 0. If high, records that an ERR was generated due to a
Request Comparator 0 (RQ_COMPARE_VAL0, GLIU0 MSR 100000C0h, GLIU1 MSR
400000C0h) event. Write 1 to clear; writing 0 has no effect. EMASK7 (bit 7) must be low
to generate ERR and set flag.
38
37
36
35
34
33
32
EFLAG6
EFLAG5
EFLAG4
EFLAG3
EFLAG2
EFLAG1
EFLAG0
Statistic Counter Error Flag 3. If high, records that an ERR was generated due to a
Statistic Counter 3 (GLIU0 MSR 100000ACh, GLIU1 MSR 400000ACh) event. Write 1 to
clear; writing 0 has no effect. EMASK6 (bit 6) must be low to generate ERR and set flag.
Statistic Counter Error Flag 2. If high, records that an ERR was generated due to a
Statistic Counter 2 (GLIU0 MSR 100000A8h, GLIU1 MSR 400000A8h) event. Write 1 to
clear; writing 0 has no effect. EMASK5 (bit 5) must be low to generate ERR and set flag.
Statistic Counter Error Flag 1. If high, records that an ERR was generated due to a
Statistic Counter 1 (GLIU0 MSR 100000A4h, GLIU1 MSR 400000A4h) event. Write 1 to
clear; writing 0 has no effect. EMASK4 (bit 4) must be low to generate ERR and set flag.
Statistic Counter Error Flag 0. If high, records that an ERR was generated due to a
Statistic Counter 0 (GLIU0 MSR 100000A0h, GLIU1 MSR 400000A0h) event. Write 1 to
clear; writing 0 has no effect. EMASK3 (bit 3) must be low to generate ERR and set flag.
Unhandled SMI Error Flag. If high, records that an ERR was generated due an unhan-
dled SSMI (synchronous error). Write 1 to clear; writing 0 has no effect. EMASK2 (bit 2)
must be low to generate ERR and set flag Unhandled SMI.
Unexpected Address Error Flag. If high, records that an ERR was generated due an
unexpected address (synchronous error). Write 1 to clear; writing 0 has no effect.
EMASK1 (bit 1) must be low to generate ERR and set flag.
Unexpected Type Error Flag. If high, records that an ERR was generated due an unex-
pected type (synchronous error). Write 1 to clear; writing 0 has no effect. EMASK0 (bit 0)
must be low to generate ERR and set flag.
31:15
14
RSVD
Reserved.
EMASK14
Data Comparator Error Mask 3. Write 0 to enable EFLAG14 (bit 46) and to allow a Data
Comparator 3 (DA_COMPARE_VAL_LO3/DA_COMPARE_VAL_HI3, GLIU0 MSR
100000DCh/100000DDh, GLIU1 MSR 400000DCh/400000DDh) event to generate an
ERR and set flag.
13
12
11
EMASK13
EMASK12
EMASK11
Data Comparator Error Mask 2. Write 0 to enable EFLAG13 (bit 45) and to allow a Data
Comparator 2 (DA_COMPARE_VAL_LO2/DA_COMPARE_VAL_HI2, GLIU0 MSR
100000D8h/100000D9h, GLIU1 MSR 400000D8h/400000D9h) event to generate an
ERR and set flag.
Data Comparator Error Mask 1. Write 0 to enable EFLAG12 (bit 44) and to allow a Data
Comparator 1 (DA_COMPARE_VAL_LO1/DA_COMPARE_VAL_HI1, GLIU0 MSR
100000D4h/100000D5h, GLIU1 MSR 400000D4h/400000D5h) event to generate an
ERR and set flag.
Data Comparator Error Mask 0. Write 0 to enable EFLAG11 (bit 43) and to allow a Data
Comparator 0 (DA_COMPARE_VAL_LO0/DA_COMPARE_VAL_HI0, GLIU0 MSR
100000D4h/100000D5h, GLIU1 MSR 400000D4h/400000D5h) event to generate an
ERR and set flag.
10
9
EMASK10
EMASK9
Request Comparator Error Mask 3. Write 0 to enable EFLAG10 (bit 42) and to allow a
Request Comparator 3 (RQ_COMPARE_VAL3, GLIU0 MSR 100000C6h, GLIU1 MSR
400000C6h) event to generate an ERR
Request Comparator Error Mask 2. Write 0 to enable EFLAG9 (bit 41) and to allow a
Request Comparator 2 (RQ_COMPARE_VAL2, GLIU0 MSR 100000C4h, GLIU1 MSR
400000C4h) event to generate an ERR.
58
AMD Geode™ LX Processors Data Book
GLIU Register Descriptions
33234H
GLD_MSR_ERROR Bit Descriptions (Continued)
Description
Bit
Name
8
EMASK8
Request Comparator Error Mask 1. Write 0 to enable EFLAG8 (bit 40) and to allow a
Request Comparator 1 (RQ_COMPARE_VAL1, GLIU0 MSR 100000C2h, GLIU1 MSR
400000C2h) event to generate an ERR
7
6
5
4
3
EMASK7
EMASK6
EMASK5
EMASK4
EMASK3
Request Comparator Error Mask 0. Write 0 to enable EFLAG7 (bit 39) and to allow a
Request Comparator 0 (RQ_COMPARE_VAL0, GLIU0 MSR 100000C0h, GLIU1 MSR
400000C0h) event to generate an ERR
Statistic Counter Error Mask 3. Write 0 to enable EFLAG6 (bit 38) and to allow a Statis-
tic Counter 3 (GLIU0 MSR 100000ACh, GLIU1 MSR 400000ACh) event to generate an
ERR.
Statistic Counter Error Mask 2. Write 0 to enable EFLAG5 (bit 37) and to allow a Statis-
tic Counter 2 (GLIU0 MSR 100000A8h, GLIU1 MSR 400000A8h) event to generate an
ERR.
Statistic Counter Error Mask 1. Write 0 to enable EFLAG4 (bit 36) and to allow a Statis-
tic Counter 1 (GLIU0 MSR 100000A4h, GLIU1 MSR 400000A4h) event to generate an
ERR.
Statistic Counter Error Mask 0. Write 0 to enable EFLAG3 (bit 35) and to allow a Statis-
tic Counter 0 (GLIU0 MSR 100000A0h, GLIU1 MSR 400000A0h) event to generate an
ERR.
2
1
0
EMASK2
EMASK1
EMASK0
Unhandled SMI Error Mask 2. Write 0 to enable EFLAG2 (bit 34) and to allow the
unhandled SSMI (synchronous error) event to generate an ERR.
Unexpected Address Error Mask 1. as Write 0 to enable EFLAG1 (bit 33) and to allow
the unexpected address (synchronous error) event to generate an ERR.
Unexpected Type Error Mask 0. Write 0 to enable EFLAG0 (bit 32) and to allow the
unexpected type (synchronous error) event to generate an ERR.
4.2.1.5 GLD Power Management MSR (GLD_MSR_PM)
MSR Address
GLIU0: 10002004h
GLIU1: 40002004h
R/W
Type
Reset Value
00000000_00000000h
GLD_MSR_PM Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
AMD Geode™ LX Processors Data Book
59
33234H
GLIU Register Descriptions
GLD_MSR_PM Bit Descriptions
Description
Bit
Name
63:4
3:2
RSVD
Reserved.
PMODE_1
Power Mode 1. Statistics and Time Slice Counters.
00: Disable clock gating. Clocks are always on.
01: Enable hardware clock gating. Clock goes off whenever this module’s circuits are not
busy.
10, 11: Reserved.
1:0
PMODE_0
Power Mode 0. Online GLIU logic.
00: Disable clock gating. Clocks are always on.
01: Enable hardware clock gating. Clock goes off whenever this module’s circuits are not
busy.
10, 11: Reserved.
4.2.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)
MSR Address
GLIU0: 10002005h
GLIU1: 40002005h
R/W
Type
Reset Value
00000000_00000000h
This register is reserved for internal use by AMD and should not be written to.
4.2.2 GLIU Specific Registers
4.2.2.1 Coherency (COH)
MSR Address
GLIU0: 10000080h
GLIU1: 40000080h
R/W
Type
Reset Value
Configuration Dependent
COH Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
COHP
COH Bit Descriptions
Bit
Name
Description
Reserved.
63:3
2:0
RSVD
COHP
Coherent Device Port. The port that coherents snoops are routed to. If the coherent
device is on the other side of a bridge, the COHP points to the bridge.
60
AMD Geode™ LX Processors Data Book
GLIU Register Descriptions
33234H
4.2.2.2 Port Active Enable (PAE)
MSR Address
GLIU0: 10000081h
GLIU1: 40000081h
R/W
Type
Reset Value
Boot Strap Dependent
Ports that are not implemented return 00 (RSVD). Ports that are slave only return 11. Master/Slave ports return the values
as stated.
GLIU0 will reset all PAE to 11 (ON) except that GLIU0 PAE3 resets to 00 when the debug stall bootstrap is active (CPU port
resets inactive for debug stall).
PAE Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD PAE0 PAE7 PAE6 PAE5 PAE4 PAE3 PAE2 PAE1
PAE Bit Descriptions
Bit
Name
Description
Reserved.
63:16
15:14
RSVD
PAE0
Port Active Enable for Port 0. (GLIU0 = GLIU; GLIU1 = GLIU.)
00: OFF - Master transactions are disabled.
01: LOW - Master transactions limited to 1 outstanding transaction.
10: Reserved.
11: ON - Master transactions enabled with no limitations.
13:12
11:10
9:8
PAE7
PAE6
PAE5
PAE4
PAE3
PAE2
PAE1
Port Active Enable for Port 7. (GLIU0 = Not Used; GLIU1 = Not Used.)
See bits [15:14] for decode.
Port Active Enable for Port 6. (GLIU0 = Not Used; GLIU1 = SB.)
See bits [15:14] for decode.
Port Active Enable for Port 5. (GLIU0 = GP; GLIU1 = VIP.)
See bits [15:14] for decode.
7:6
Port Active Enable for Port 4. (GLIU0 = DC; GLIU1 = GLPCI.)
See bits [15:14] for decode.
5:4
Port Active Enable for Port 3. (GLIU0 = CPU Core; GLIU1 = GLCP.)
See bits [15:14] for decode.
3:2
Port Active Enable for Port 2. (GLIU0 = Interface to GLIU1; GLIU1 = VP.)
See bits [15:14] for decode.
1:0
Port Active Enable for Port 1. (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
See bits [15:14] for decode.
AMD Geode™ LX Processors Data Book
61
33234H
GLIU Register Descriptions
4.2.2.3 Arbitration (ARB)
MSR Address
GLIU0: 10000082h
GLIU1: 40000082h
R/W
Type
Reset Value
10000000_00000000h
ARB Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RSVD
ARB Bit Descriptions
Bit
Name
Description
63
QUACK_EN
Quadruple Acknowledge Enabled. Allow four acknowledgements in a row before
advancing round-robin arbitration. Only applies when arbitrating matching priorities.
0: Disable.
1: Enable.
62
PIPE_DIS
Pipelined Arbitration Disabled.
0: Pipelined arbitration enabled and GLIU is not limited to one outstanding transaction.
1: Limit the entire GLIU to one outstanding transaction.
61
60
RSVD
Reserved.
DACK_EN
Double Acknowledge Enabled. Allow two acknowledgements in a row before advanc-
ing round-robin arbitration. Only applies when arbitrating matching priorities.
0: Disable.
1: Enable.
59:0
RSVD
Reserved.
4.2.2.4 Asynchronous SMI (ASMI)
MSR Address
GLIU0: 10000083h
GLIU1: 40000083h
R/W
Type
Reset Value
00000000_00000000h
ASMI is a condensed version of the port ASMI signals. The MASK bits can be used to prevent a device from issuing an
ASMI. If the MASK = 1, the device’s ASMI is disabled.
ASMI Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
62
AMD Geode™ LX Processors Data Book
GLIU Register Descriptions
33234H
ASMI Bit Descriptions
Bit
Name
Description
Reserved.
63:16
15
RSVD
ASMI_MASK7
Asynchronous SMI Mask for Port 7. (GLIU0 = Not Used; GLIU1 = Not Used.) Write 0 to
allow Port 7 to generate an ASMI. ASMI status is reported in bit 7.
14
13
12
11
10
9
ASMI_MASK6
ASMI_MASK5
ASMI_MASK4
ASMI_MASK3
ASMI_MASK2
ASMI_MASK1
ASMI_MASK0
Asynchronous SMI Mask for Port 6. (GLIU0 = Not Used; GLIU1 = SB.) Write 0 to allow
Port 6 to generate an ASMI. ASMI status is reported in bit 6.
Asynchronous SMI Mask for Port 5. (GLIU0 = GP; GLIU1 = VIP.) Write 0 to allow Port 5
to generate an ASMI. ASMI status is reported in bit 5.
Asynchronous SMI Mask for Port 4. (GLIU0 = DC; GLIU1 = GLPCI.) Write 0 to allow
Port 4 to generate an ASMI. ASMI status is reported in bit 4.
Asynchronous SMI Mask for Port 3. (GLIU0 = CPU Core; GLIU1 = GLCP.) Write 0 to
allow Port 3 to generate an ASMI. ASMI status is reported in bit 3.
Asynchronous SMI Mask for Port 2. (GLIU0 = Interface to GLIU1; GLIU1 = VP.) Write 0
to allow Port 2 to generate an ASMI. ASMI status is reported in bit 2.
Asynchronous SMI Mask for Port 1. (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
Write 0 to allow Port 1 to generate an ASMI. ASMI status is reported in bit 1.
8
Asynchronous SMI Mask for Port 0. (GLIU0 = GLIU; GLIU1 = GLIU.) Write 0 to allow
Port 0 to generate an ASMI. ASMI status is reported in bit 0.
7
ASMI_FLAG7
(RO)
Asynchronous SMI Flag for Port 7 (Read Only). (GLIU0 = Not Used; GLIU1 = Not
Used.). If 1, this bit indicates that an ASMI was generated by Port 7. Cleared by source.
6
ASMI_FLAG6
(RO)
Asynchronous SMI Flag for Port 6 (Read Only). (GLIU0 = Not Used; GLIU1 = SB.) If 1,
this bit indicates that an ASMI was generated by Port 6. Cleared by source.
5
ASMI_FLAG5
(RO)
Asynchronous SMI Flag for Port 5 (Read Only). (GLIU0 = GP; GLIU1 = VIP.) If 1, this
bit indicates that an ASMI was generated by Port 5. Cleared by source.
4
ASMI_FLAG4
(RO)
Asynchronous SMI Flag for Port 4 (Read Only). (GLIU0 = DC; GLIU1 = GLPCI.) If 1,
this bit indicates that an ASMI was generated by Port 4. Cleared by source.
3
ASMI_FLAG3
(RO)
Asynchronous SMI Flag for Port 3 (Read Only). (GLIU0 = CPU Core; GLIU1 = GLCP.)
If 1, this bit indicates that an ASMI was generated by Port37. Cleared by source.
2
ASMI_FLAG2
(RO)
Asynchronous SMI Flag for Port 2 (Read Only). (GLIU0 = Interface to GLIU1; GLIU1 =
VP.) If 1, this bit indicates that an ASMI was generated by Port 2. Cleared by source.
1
ASMI_FLAG1
(RO)
Asynchronous SMI Flag for Port 1 (Read Only). (GLIU0 = GLMC; GLIU1 = Interface to
GLIU0.) If 1, this bit indicates that an ASMI was generated by Port 1. Cleared by source.
0
ASMI_FLAG0
(RO)
Asynchronous SMI Flag for Port 0 (Read Only). (GLIU0 = GLIU; GLIU1 = GLIU.) If 1,
this bit indicates that an ASMI was generated by Port 0. Cleared by source.
4.2.2.5 Asynchronous ERR (AERR)
MSR Address
GLIU0: 10000084h
GLIU1: 40000084h
R/W
Type
Reset Value
00000000_00000000h
AERR is a condensed version of the port ERR signals. The MASK bits can be used to prevent a device from issuing an
AERR. If the MASK = 1, the device’s AERR is disabled.
AMD Geode™ LX Processors Data Book
63
33234H
GLIU Register Descriptions
AERR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
AERR Bit Descriptions
Bit
Name
Description
63:16
15
RSVD
Reserved.
AERR_MASK7
Asynchronous Error Mask for Port 7. (GLIU0 = Not Used; GLIU1 = Not Used.) Write 0
to allow Port 7 to generate an AERR. AERR status is reported in bit 7.
14
13
12
11
10
9
AERR_MASK6
AERR_MASK5
AERR_MASK4
AERR_MASK3
AERR_MASK2
AERR_MASK1
AERR_MASK0
Asynchronous Error Mask for Port 6. (GLIU0 = Not Used; GLIU1 = SB.) Write 0 to
allow Port 6 to generate an AERR. AERR status is reported in bit 6.
Asynchronous Error Mask for Port 5. (GLIU0 = GP; GLIU1 = VIP.) Write 0 to allow Port
5 to generate an AERR. AERR status is reported in bit 5.
Asynchronous Error Mask for Port 4. (GLIU0 = DC; GLIU1 = GLPCI.) Write 0 to allow
Port 4 to generate an AERR. AERR status is reported in bit 4.
Asynchronous Error Mask for Port 3. (GLIU0 = CPU Core; GLIU1 = GLCP.) Write 0 to
allow Port 3 to generate an AERR. AERR status is reported in bit 3.
Asynchronous Error Mask for Port 2. (GLIU0 = Interface to GLIU1; GLIU1 = VP.) Write
0 to allow Port 2 to generate an AERR. AERR status is reported in bit 2.
Asynchronous Error Mask for Port 1. (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
Write 0 to allow Port 1 to generate an AERR. AERR status is reported in bit 1.
8
Asynchronous Error Mask for Port 0. (GLIU0 = GLIU; GLIU1 = GLIU.) Write 0 to allow
Port 0 to generate an AERR. AERR status is reported in bit 0.
7
AERR_FLAG7
(RO)
Asynchronous Error for Port 7 (Read Only). (GLIU0 = Not Used; GLIU1 = Not Used.) If
1, indicates that an AERR was generated by Port 7. Cleared by source.
6
AERR_FLAG6
(RO)
Asynchronous Error for Port 6 (Read Only). (GLIU0 = Not Used; GLIU1 = SB.) If 1,
indicates that an AERR was generated by Port 6. Cleared by source.
5
AERR_FLAG5
(RO)
Asynchronous Error for Port 5 (Read Only). (GLIU0 = GP; GLIU1 = VIP.) If 1, indicates
that an AERR was generated by Port 5. Cleared by source.
4
AERR_FLAG4
(RO)
Asynchronous Error for Port 4 (Read Only). (GLIU0 = DC; GLIU1 = GLPCI.) If 1, indi-
cates that an AERR was generated by Port 4. Cleared by source.
3
AERR_FLAG3
(RO)
Asynchronous Error for Port 3 (Read Only). (GLIU0 = CPU Core; GLIU1 = GLCP.) If 1,
indicates that an AERR was generated by Port 3. Cleared by source.
2
AERR_FLAG2
(RO)
Asynchronous Error for Port 2 (Read Only). (GLIU0 = Interface to GLIU1; GLIU1 =
VP.) If 1, indicates that an AERR was generated by Port 2. Cleared by source.
1
AERR_FLAG1
(RO)
Asynchronous Error for Port 1 (Read Only). (GLIU0 = GLMC; GLIU1 = Interface to
GLIU0.) If 1, indicates that an AERR was generated by Port 1. Cleared by source.
0
AERR_FLAG0
(RO)
Asynchronous Error for Port 0 (Read Only). (GLIU0 = GLIU; GLIU1 = GLIU.) If 1, indi-
cates that an AERR was generated by Port 0. Cleared by source.
64
AMD Geode™ LX Processors Data Book
GLIU Register Descriptions
33234H
4.2.2.6 GLIU Physical Capabilities (PHY_CAP)
MSR Address
GLIU0: 10000086h
GLIU1: 40000086h
R/W
Type
Reset Value
GLIU0: 20291830_010C1086h
GLIU1: 20311030_0100400Ah
PHY_CAP Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
NPORTS NCOH NIOD_SC NIOD_BM NP2D_BMK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
NP2D_SC NP2D_RO NP2D_R NP2D_BMO
NP2D_BM
PHY_CAP Bit Descriptions
Description
Bit
Name
63
RSVD
Reserved.
62:60
59:57
56:54
53:51
50:48
47:42
41:36
35:30
29:24
23:18
17:12
11:6
NSTAT_CNT
NDBG_DA_CMP
NDBG_RQ_CMP
NPORTS
Number Of Statistic Counters.
Number Of Data Comparators.
Number Of Request Comparators.
Number of Ports on the GLIU.
Number of Coherent Devices.
Number of IOD_SC Descriptors.
Number of IOD_BM Descriptors.
Number of P2D_BMK Descriptors.
Number of P2D_SC Descriptors.
Number of P2D_RO Descriptors.
Number of P2D_R Descriptors.
Number of P2D_BMO Descriptors.
Number of P2D_BM Descriptors.
NCOH
NIOD_SC
NIOD_BM
NP2D_BMK
NP2D_SC
NP2D_RO
NP2D_R
NP2D_BMO
NP2D_BM
5:0
AMD Geode™ LX Processors Data Book
65
33234H
GLIU Register Descriptions
4.2.2.7 N Outstanding Response (NOUT_RESP)
MSR Address
GLIU0: 10000087h
GLIU1: 40000087h
RO
Type
Reset Value
00000000_00000000h
NOUT_RESP Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
NOUT_RESP7 NOUT_RESP6 NOUT_RESP5 NOUT_RESP4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
NOUT_RESP3
NOUT_RESP2
NOUT_RESP1
NOUT_RESP9
NOUT_RESP Bit Descriptions
Description
Bit
Name
63:56
NOOUT_RESP7
Number of Outstanding Responses on Port 7. (GLIU0 = Not Used; GLIU1 = Not
Used.)
55:48
47:40
39:32
31:24
23:16
NOOUT_RESP6
NOOUT_RESP5
NOOUT_RESP4
NOOUT_RESP3
NOOUT_RESP2
Number of Outstanding Responses on Port 6. (GLIU0 = Not Used; GLIU1 = SB.)
Number of Outstanding Responses on Port 5. (GLIU0 = GP; GLIU1 = VIP.)
Number of Outstanding Responses on Port 4. (GLIU0 = DC; GLIU1 = GLPCI.)
Number of Outstanding Responses on Port 3. (GLIU0 = CPU Core; GLIU1 = GLCP.)
Number of Outstanding Responses on Port 2. (GLIU0 = Interface to GLIU1; GLIU1 =
VP.)
15:8
7:0
NOOUT_RESP1
NOOUT_RESP0
Number of Outstanding Responses on Port 1. (GLIU0 = GLMC; GLIU1 = Interface to
GLIU0.)
Number of Outstanding Responses on Port 0. (GLIU0 = GLIU; GLIU1 = GLIU.)
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AMD Geode™ LX Processors Data Book
GLIU Register Descriptions
33234H
4.2.2.8 N Outstanding Write Data (NOUT_WDATA)
MSR Address
GLIU0: 10000088h
GLIU1: 40000088h
RO
Type
Reset Value
00000000_00000000h
NOUT_WDATA Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
NOUT_WDATA7 NOUT_WDATA6 NOUT_WDATA5 NOUT_WDATA4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
NOUT_WDATA3
NOUT_WDATA2
NOUT_WDATA1
NOUT_WDATA0
NOUT_WDATA Bit Descriptions
Description
Bit
Name
63:56
NOOUT_WDATA7
Number of Outstanding Write Data on Port 7. (GLIU0 = Not Used; GLIU1 = Not
Used.)
55:48
47:40
39:32
31:24
NOOUT_WDATA6
NOOUT_WDATA5
NOOUT_WDATA4
NOOUT_WDATA3
Number of Outstanding Write Data on Port 6. (GLIU0 = Not Used; GLIU1 = SB.)
Number of Outstanding Write Data on Port 5. (GLIU0 = GP; GLIU1 = VIP.)
Number of Outstanding Write Data on Port 4. (GLIU0 = DC; GLIU1 = GLPCI.)
Number of Outstanding Write Data on Port 3. (GLIU0 = CPU Core; GLIU1 =
GLCP.)
23:16
15:8
7:0
NOOUT_WDATA2
NOOUT_WDATA1
NOOUT_WDATA0
Number of Outstanding Write Data on Port 2. (GLIU0 = Interface to GLIU1; GLIU1
= VP.)
Number of Outstanding Write Data on Port 1. (GLIU0 = GLMC; GLIU1 = Interface
to GLIU0.)
Number of Outstanding Write Data on Port 0. (GLIU0 = GLIU; GLIU1 = GLIU.)
4.2.2.9 SLAVE_ONLY
MSR Address
GLIU0: 10000089h
GLIU1: 40000089h
Type
RO
Reset Value
GLIU0: 00000000_00000010h
GLIU1: 00000000_00000100h
SLAVE_ONLY Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
SLAVE_ONLY
SLAVE_ONLY Bit Descriptions
Bit
Name
Description
Reserved.
63:8
7
RSVD
P7_SLAVE_ONLY
Port 7 Slave Only. (GLIU0 = Not Used; GLIU1 = Not Used.) If high, indicates that Port
7 is a slave port. If low, Port 7 is a master/slave port.
AMD Geode™ LX Processors Data Book
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33234H
GLIU Register Descriptions
SLAVE_ONLY Bit Descriptions (Continued)
Description
Bit
Name
6
P6_SLAVE_ONLY
P5_SLAVE_ONLY
P4_SLAVE_ONLY
P3_SLAVE_ONLY
P2_SLAVE_ONLY
P1_SLAVE_ONLY
P0_SLAVE_ONLY
Port 6 Slave Only. (GLIU0 = Not Used; GLIU1 = SB.) If high, indicates that Port 6 is a
slave port. If low, Port 6 is a master/slave port.
5
4
3
2
1
0
Port 5 Slave Only. (GLIU0 = GP; GLIU1 = VIP.) If high, indicates that Port 5 is a slave
port. If low, Port 5 is a master/slave port.
Port 4 Slave Only. (GLIU0 = DC; GLIU1 = GLPCI.) If high, indicates that Port 4 is a
slave port. If low, Port 4 is a master/slave port.
Port 3 Slave Only. (GLIU0 = CPU Core; GLIU1 = GLCP.) If high, indicates that Port 3
is a slave port. If low, Port 3 is a master/slave port.
Port 2 Slave Only. (GLIU0 = Interface to GLIU1; GLIU1 = VP.) If high, indicates that
Port 2 is a slave port. If low, Port 2 is a master/slave port.
Port 1 Slave Only. (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.) If high, indicates
that Port 1 is a slave port. If low, Port 1 is a master/slave port.
Port 0 Slave Only. (GLIU0 = GLIU; GLIU1 = GLIU.) If high, indicates that Port 0 is a
slave port. If low, Port 0 is a master/slave port.
4.2.2.10 WHO AM I (WHOAMI)
MSR Address
GLIU0: 1000008Bh
GLIU1: 4000008Bh
Type
RO
Reset Value
Configuration Dependent
WHO AM I Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
DSID
WHO AM I Bit Descriptions
Bit
Name
Description
Reserved.
63:3
2:0
RSVD
DSID
Source ID of the Initiating Device. Used to prevent self referencing transactions.
000: Port 0 (GLIU0 = GLIU; GLIU1 = GLIU.)
001: Port 1 (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
010: Port 2 (GLIU0 = Interface to GLIU1; GLIU1 = VP.)
011: Port 3 (GLIU0 = CPU Core; GLIU1 = GLCP.)
100: Port 4 (GLIU0 = DC; GLIU1 = GLPCI.)
101: Port 5 (GLIU0 = GP; GLIU1 = VIP.)
110: Port 6 (GLIU0 = Not Used; GLIU1 = SB.)
111: Port 7 (GLIU0 = Not Used; GLIU1 = Not Used.)
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AMD Geode™ LX Processors Data Book
GLIU Register Descriptions
33234H
4.2.2.11 GLIU Slave Disable (GLIU_SLV)
MSR Address
GLIU0: 1000008Ch
GLIU1: 4000008Ch
R/W
Type
Reset Value
00000000_00000000h
The slave disable registers are available for the number of ports on the GLIU. The unused ports return 0.
GLIU_SLV Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
GLIU_SLV Bit Descriptions
Bit
Name
Description
Reserved.
63:8
7
RSVD
SLAVE_DIS7
Slave Transactions Disable for Port 7. (GLIU0 = Not Used; GLIU1 = Not Used.) Write
1 to disable slave transactions to Port 7.
6
5
4
3
2
1
0
SLAVE_DIS6
SLAVE_DIS5
SLAVE_DIS4
SLAVE_DIS3
SLAVE_DIS2
SLAVE_DIS1
SLAVE_DIS0
Slave Transactions Disable for Port 6. (GLIU0 = Not Used; GLIU1 = SB.) Write 1 to
disable slave transactions to Port 6.
Slave Transactions Disable for Port 5. (GLIU0 = GP; GLIU1 = VIP.) Write 1 to disable
slave transactions to Port 5.
Slave Transactions Disable for Port 4. (GLIU0 = DC; GLIU1 = GLPCI.) Write 1 to dis-
able slave transactions to Port 4.
Slave Transactions Disable for Port 3. (GLIU0 = CPU Core; GLIU1 = GLCP.) Write 1
to disable slave transactions to Port 3.
Slave Transactions Disable for Port 2. (GLIU0 = Interface to GLIU1; GLIU1 = VP.)
Write 1 to disable slave transactions to Port 2.
Slave Transactions Disable for Port 1. (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
Write 1 to disable slave transactions to Port 1.
Slave Transactions Disable for Port 0. (GLIU0 = GLIU; GLIU1 = GLIU.) Write 1 to dis-
able slave transactions to Port 0.
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33234H
GLIU Register Descriptions
4.2.2.12 Arbitration2 (ARB2)
MSR Address
GLIU0: 1000008Dh
GLIU1: 4000008Dh
R/W
Type
Reset Value
00000000_00000000h
ARB2 Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
THRESH
ARB2 Bit Descriptions
Bit
Name
Description
Reserved.
63:4
3
RSVD
THROT_EN
Arbitration Throttling Enable. When set, arbitration is prevented in this GLIU if the
other GLIU is retreating a priority above the THRESH priority.
2:0
THRESH
Priority Threshold. See THROT_EN description. Priority threshold value must be 4 or
less.
0: Disable.
1: Enable.
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GLIU Register Descriptions
33234H
4.2.3
GLIU Statistic and Comparator MSRs
4.2.3.1 Descriptor Statistic Counter (STATISTIC_CNT[0:3])
Descriptor Statistic Counter (STATISTIC_CNT[0])
Descriptor Statistic Counter (STATISTIC_CNT[2])
MSR Address
GLIU0: 100000A0h
GLIU1: 400000A0h
R/W
MSR Address
GLIU0: 100000A8h
GLIU1: 400000A8h
R/W
Type
Type
Reset Value
00000000_00000000h
Reset Value
00000000_00000000h
Descriptor Statistic Counter (STATISTIC_CNT[1])
Descriptor Statistic Counter (STATISTIC_CNT[3])
MSR Address
GLIU0: 100000A4h
GLIU1: 400000A4h
R/W
MSR Address
GLIU0: 100000ACh
GLIU1: 400000ACh
R/W
Type
Type
Reset Value
00000000_00000000h
Reset Value
00000000_00000000h
STATISTIC_CNT[0:3] Registers Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
LOAD_VAL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CNT
STATISTIC_CNT[0:3] Bit Descriptions
Bit
Name
Description
63:32
LOAD_VAL
Counter Load Value. The value loaded here is used as the initial Statistics Counter
value when a LOAD action occurs or is commanded.
31:0
CNT
Counter Value. These bits provide the current counter value when read.
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33234H
GLIU Register Descriptions
4.2.3.2 Statistic Mask (STATISTIC_MASK[0:3]
Descriptor Statistic Mask (STATISTIC_MASK[0])
Descriptor Statistic Mask (STATISTIC_MASK[2])
MSR Address
GLIU0: 100000A1h
GLIU1: 400000A1h
R/W
MSR Address
GLIU0: 100000A9h
GLIU1: 400000A9h
R/W
Type
Type
Reset Value
00000000_00000000h
Reset Value
00000000_00000000h
Descriptor Statistic Mask (STATISTIC_MASK[1])
Descriptor Statistic Mask (STATISTIC_MASK[3])
MSR Address
GLIU0: 100000A5h
GLIU1: 400000A5h
R/W
MSR Address
GLIU0: 100000ADh
GLIU1: 400000ADh
R/W
Type
Type
Reset Value
00000000_00000000h
Reset Value
00000000_00000000h
STATISTIC_MASK[0:3] Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
IOD_MASK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
P2D MASK
STATISTIC_MASK[0:3] Bit Descriptions
Bit
Name
Description
63:32
IOD_MASK
Mask for Hits to Each IOD. Hits are determined after the request is arbitrated. A hit is
determined by the following logical equation: Hit = |(IOD_MASK[n-1:0] &
RQ_DESC_HIT[n-1:0] && is_io) | |(P2D_MASK[n-1:0] & RQ_DESC_HIT[n-1:0] &&
is_mem).
31:0
P2D_MASK
Mask for Hits to Each P2D. A hit is determined by the following logical equation: Hit =
|(IOD_MASK[n-1:0] & RQ_DESC_HIT[n-1:0] && is_io) | |(P2D_MASK[n-1:0] &
RQ_DESC_HIT[n-1:0] && is_mem).
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AMD Geode™ LX Processors Data Book
GLIU Register Descriptions
33234H
4.2.3.3 Statistic Action (STATISTIC_ACTION[0:3]
Descriptor Statistic Action (STATISTIC_ACTION[0])
Descriptor Statistic Action (STATISTIC_ACTION[2])
MSR Address
GLIU0: 100000A2h
GLIU1: 400000A2h
R/W
MSR Address
GLIU0: 100000AAh
GLIU1: 400000AAh
R/W
Type
Type
Reset Value
00000000_00000000h
Reset Value
00000000_00000000h
Descriptor Statistic Action (STATISTIC_ACTION[1])
Descriptor Statistic Action (STATISTIC_ACTION[3])
MSR Address
GLIU0: 100000A6h
GLIU1: 400000A6h
R/W
MSR Address
GLIU0: 100000AEh
GLIU1: 400000AEh
R/W
Type
Type
Reset Value
00000000_00000000h
Reset Value
00000000_00000000h
STATISTIC_ACTION[0:3] Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
PREDIV
STATISTIC_ACTION[0:3] Bit Descriptions
Bit
Name
Description
Reserved.
63:24
23:8
RSVD
PREDIV
Pre Divider. Used if ALWAYS_DEC (bit 4) is set. The predivider is free running and
extends the depth of the counter.
7
6
5
4
WRAP
Decrement Counter Beyond Zero and Wrap.
0: Disable wrap; counter stops when it reaches zero.
1: Enable wrap; counter decrements through 0 to all ones.
ZERO_AERR
ZERO_ASMI
ALWAYS_DEC
Assert AERR on cnt = 0. Assert AERR when STATISTIC_CNT[x] reaches 0.
0: Disable.
1: Enable.
Assert ASMI on cnt = 0. Assert ASMI when STATISTIC_CNT[x] reaches 0.
0: Disable.
1: Enable.
Always Decrement Counter. If enabled, the counter decrements on every memory
clock subject to the prescaler value PREDIV (bits [23:8]). Decrementing continues unless
loading is occurring due to another action, or if the counter reaches zero and WRAP is
disabled (bit 7).
0: Disable.
1: Enable
3
HIT_AERR
Assert AERR on Descirptor Hit. The descriptor hits are ANDed with the masks and
then all ORed together.
0: Disable.
1: Enable
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33234H
GLIU Register Descriptions
STATISTIC_ACTION[0:3] Bit Descriptions
Description
Bit
Name
2
HIT_ASMI
Assert ASMI on Descriptor Hit. The descriptor hits are ANDed with the masks and then
all ORed together.
0: Disable.
1: Enable.
1
0
HIT_DEC
Decrement Counter on Descriptor Hit. The descriptor hits are ANDed with the masks
and then all ORed together.
0: Disable.
1: Enable.
HIT_LDEN
Load Counter on Descriptor Hit. The descriptor hits are ANDed with the masks and
then all ORed together.
0: Disable.
1: Enable.
4.2.3.4 Request Compare Value (RQ_COMPARE_VAL[0:3]
The RQ Compare Value and the RQ Compare Mask enable traps on specific transactions. A hit to the RQ Compare is
determined by hit = (RQ_IN & RQ_COMPARE_MASK) == RQ_COMPARE_VAL). A hit can trigger the RQ_CMP error
sources when they are enabled. The value is compared only after the packet is arbitrated.
Request Compare Value (RQ_COMPARE_VAL[0])
Request Compare Value (RQ_COMPARE_VAL[2])
MSR Address
GLIU0: 100000C0h
GLIU1: 400000C0h
R/W
MSR Address
GLIU0: 100000C4h
GLIU1: 400000C4h
R/W
Type
Type
Reset Value
001FFFFF_FFFFFFFFh
Reset Value
001FFFFF_FFFFFFFFh
Request Compare Value (RQ_COMPARE_VAL[1])
Request Compare Value (RQ_COMPARE_VAL[3])
MSR Address
GLIU0: 100000C2h
GLIU1: 400000C2h
R/W
MSR Address
GLIU0: 100000C6h
GLIU1: 400000C6h
R/W
Type
Type
Reset Value
001FFFFF_FFFFFFFFh
Reset Value
001FFFFF_FFFFFFFFh
RQ_COMPARE_VAL[0:3] Register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD RQ_VAL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RQ_VAL
RQ_COMPARE_VAL[0:3] Bit Descriptions
Description
Reserved.
Bit
Name
63:53
52:0
RSVD
RQ_VAL
Request Packet Value. This is the value compared against the logical bit-wise AND of
the incoming request packet and the RQ_COMPMASK in order to determine a ‘hit”.
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GLIU Register Descriptions
33234H
4.2.3.5 Request Compare Mask (RQ_COMPARE_MASK[0:3]
The RQ Compare Value and the RQ Compare Mask enable traps on specific transactions. A hit to the RQ Compare is
determined by hit = (RQ_IN & RQ_COMPARE_MASK) == RQ_COMPARE_VAL). A hit can trigger the RQ_CMP error
sources when they are enabled. The value is compared only after the packet is arbitrated.
Request Compare Mask (RQ_COMPARE_MASK[0])
Request Compare Mask (RQ_COMPARE_MASK[2])
MSR Address
GLIU0: 100000C1h
GLIU1: 400000C1h
R/W
MSR Address
GLIU0: 100000C5h
GLIU1: 400000C5h
R/W
Type
Type
Reset Value
00000000_00000000h
Reset Value
00000000_00000000h
Request Compare Mask (RQ_COMPARE_MASK[1])
Request Compare Mask (RQ_COMPARE_MASK[3])
MSR Address
GLIU0: 100000C3h
GLIU1: 400000C3h
R/W
MSR Address
GLIU0: 100000C7h
GLIU1: 400000C7h
R/W
Type
Type
Reset Value
00000000_00000000h
Reset Value
00000000_00000000h
RQ_COMPARE_MASK[0:3] Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD RQ_MASK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RQ_MASK
RQ_COMPARE_MASK[0:3] Bit Descriptions
Bit
Name
Description
Reserved.
63:53
52:0
RSVD
RQ_MASK
Request Packet Mask. This field is bit-wise logically ANDed with the incoming request
packet before it is compared to the RQ_COMPVAL.
AMD Geode™ LX Processors Data Book
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33234H
GLIU Register Descriptions
4.2.3.6 DA Compare Value Low (DA_COMPARE_VAL_LO[0:3]
The DA Compare Value and the DA Compare Mask enable traps on specific transactions. A hit to the DA Compare is deter-
mined by hit = (DA_IN & DA_COMPARE_MASK) == DA_COMPARE_VAL). A hit can trigger the DA_CMP error sources
when they are enabled. The value is compared only after the packet is arbitrated.
Data Compare Value Low (DA_COMPARE_VAL_LO[0])
Data Compare Value Low (DA_COMPARE_VAL_LO[2])
MSR Address
GLIU0: 100000D0h
GLIU1: 400000D0h
R/W
MSR Address
GLIU0: 100000D8h
GLIU1: 400000D8h
R/W
Type
Type
Reset Value
00001FFF_FFFFFFFFh
Reset Value
00001FFF_FFFFFFFFh
Data Compare Value Low (DA_COMPARE_VAL_LO[1])
Data Compare Value Low (DA_COMPARE_VAL_LO[3])
MSR Address
GLIU0: 100000D4h
GLIU1: 400000D4h
R/W
MSR Address
GLIU0: 100000DCh
GLIU1: 400000DCh
R/W
Type
Type
Reset Value
00001FFF_FFFFFFFFh
Reset Value
00001FFF_FFFFFFFFh
DA_COMPARE_VAL_LO[0:3] Register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
DALO_VAL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DALO_VAL
DA_COMPARE_VAL_LO[0:3] Bit Descriptions
Bit
Name
Description
Reserved.
63:45
44:0
RSVD
DALO_VAL
DA Packet Compare Value [44:0]. This field forms the lower portion of the data value,
which is compared to the logical bit-wise AND of the incoming data value and the data
value compare mask in order to determine a ‘hit’. The “HI” and “LO” portions of the
incoming data, the compare value, and the compare mask, are assembled into complete
bit patterns before these operations occur.
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AMD Geode™ LX Processors Data Book
GLIU Register Descriptions
33234H
4.2.3.7 DA Compare Value High (DA_COMPARE_VAL_HI[0:3]
The DA Compare Value and the DA Compare Mask enable traps on specific transactions. A hit to the DA Compare is deter-
mined by hit = (DA_IN & DA_COMPARE_MASK) == DA_COMPARE_VAL). A hit can trigger the DA_CMP error sources
when they are enabled. The value is compared only after the packet is arbitrated.
Data Compare Value High (DA_COMPARE_VAL_HI[0])
Data Compare Value High (DA_COMPARE_VAL_HI[2])
MSR Address
GLIU0: 100000D1h
GLIU1: 400000D1h
R/W
MSR Address
GLIU0: 100000D9h
GLIU1: 400000D9h
R/W
Type
Type
Reset Value
0000000F_FFFFFFFFh
Reset Value
0000000F_FFFFFFFFh
Data Compare Value High (DA_COMPARE_VAL_HI[1])
Data Compare Value High (DA_COMPARE_VAL_HI[3])
MSR Address
GLIU0: 100000D5h
GLIU1: 400000D5h
R/W
MSR Address
GLIU0: 100000DDh
GLIU1: 400000DDh
R/W
Type
Type
Reset Value
0000000F_FFFFFFFFh
Reset Value
0000000F_FFFFFFFFh
DA_COMPARE_VAL_HI[0:3] Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DAHI_VAL
DAHI_VAL
9
8
7
6
5
4
3
2
1
0
DA_COMPARE_VAL_HI[0:3] Bit Descriptions
Bit
Name
Description
Reserved.
63:36
35:0
RSVD
DAHI_VAL
DA Packet Compare Value [80:45]. This field forms the upper portion of the data value
which is compared to the logical bit-wise AND of the incoming data value AND the data
value compare mask in order to determine a ‘hit’. The “HI” and “LO” portions of the
incoming data, the compare value, and the compare mask, are assembled into complete
bit patterns before these operations occur.
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GLIU Register Descriptions
4.2.3.8 DA Compare Mask Low (DA_COMPARE_MASK_LO[0:3])
Data Compare Mask Low
(DA_COMPARE_MASK_LO[0])
Data Compare Mask Low
(DA_COMPARE_MASK_LO[2])
MSR Address
GLIU0: 100000D2h
GLIU1: 400000D2h
R/W
MSR Address
GLIU0: 100000DAh
GLIU1: 400000DAh
R/W
Type
Type
Reset Value
00000000_00000000h
Reset Value
00000000_00000000h
Data Compare Mask Low
Data Compare Mask Low
(DA_COMPARE_MASK_LO[1])
(DA_COMPARE_MASK_LO[3])
MSR Address
GLIU0: 100000D6h
MSR Address
GLIU0: 100000DEh
GLIU1: 400000D6h
R/W
GLIU1: 400000DEh
R/W
Type
Type
Reset Value
00000000_00000000h
Reset Value
00000000_00000000h
The DA Compare Value and the DA Compare Mask enable traps on specific transactions. A hit to the DA Compare is deter-
mined by hit = (DA_IN & DA_COMPARE_MASK) == DA_COMPARE_VAL). A hit can trigger the DA_CMP error sources
when they are enabled. The value is compared only after the packet is arbitrated.
DA_COMPARE_VAL_HI[0:3] Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
DALO_MASK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DALO_MASK
DA_COMPARE_MASK_LO[0:3] Bit Descriptions
Bit
Name
Description
Reserved.
63:45
44:0
RSVD
DALO_MASK
DA Packet Compare Value [44:0]. This field forms the lower portion of the data COMP-
MASK value, which is then bit-wise logically ANDed with the incoming data value before
it is compared to the DA_COMPVAL. The “HI” and “LO” portions of the incoming data,
the compare value, and the compare mask, are assembled into complete bit patterns
before these operations occur.
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33234H
4.2.3.9 DA Compare Mask High (DA_COMPARE_MASK_HI[0:3])
Data Compare Mask High
(DA_COMPARE_MASK_HI[0])
Data Compare Mask High
(DA_COMPARE_MASK_HI[2])
MSR Address
GLIU0: 100000D3h
GLIU1: 400000D3h
R/W
MSR Address
GLIU0: 100000DBh
GLIU1: 400000DBh
R/W
Type
Type
Reset Value
00000000_00000000h
Reset Value
00000000_00000000h
Data Compare Mask High
Data Compare Mask High
(DA_COMPARE_MASK_HI[1])
(DA_COMPARE_MASK_HI[3])
MSR Address
GLIU0: 100000D7h
MSR Address
GLIU0: 100000DFh
GLIU1: 400000D7h
R/W
GLIU1: 400000DFh
R/W
Type
Type
Reset Value
00000000_00000000h
Reset Value
00000000_00000000h
DA_COMPARE_MASK_HI[0:3] Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DAHI_MASK
DAHI_MASK
9
8
7
6
5
4
3
2
1
0
DA_COMPARE_MASK_HI[0:3] Bit Descriptions
Bit
Name
Description
Reserved.
63:36
35:0
RSVD
DAHI_MASK
DA Packet Compare Mask [80:45]. This field forms the upper portion of the data
COMPMASK value, which is then bit-wise logically ANDed with the incoming data value
before it is compared to the DA_COMPVAL.The “HI” and “LO” portions of the incoming
data. the compare value, and the compare mask, are assembled into complete bit pat-
terns before these operations occur.
AMD Geode™ LX Processors Data Book
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GLIU Register Descriptions
4.2.4
P2D Descriptor Registers
P2D descriptors are ordered P2D_BM, P2D_BMO, P2D_R, P2D_RO, P2D_SC, P2D_BMK. For example if NP2D_BM=3
and NP2D_BM0=2, IMSR EO = P2D_BM[0], MSR E3 = P2D_SC[0].
4.2.4.1 P2D Base Mask Descriptor (P2D_BM)
GLIU0
P2D_BM[5:0]
GLIU1
P2D_BM[9:0]
MSR Address
Type
10000020h-10000025h
R/W
MSR Address
Type
40000020h-40000029h
R/W
Reset Value
000000FF_FFF00000h
Reset Value
000000FF_FFF00000h
P2D_BM Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
PDID1
RSVD
PBASE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PBASE PMASK
P2D_BM Bit Descriptions
Bit
Name
Description
63:61
PDID1
Descriptor Destination ID. These bits define which Port to route the request to, if it is a
‘hit’ based on the other settings in this register.
000: Port 0 (GLIU0 = GLIU; GLIU1 = GLIU.)
001: Port 1 (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
010: Port 2 (GLIU0 = Interface to GLIU1; GLIU1 = VP.)
011: Port 3 (GLIU0 = CPU Core; GLIU1 = GLCP.)
100: Port 4 (GLIU0 = DC; GLIU1 = GLPCI.)
101: Port 5 (GLIU0 = GP; GLIU1 = VIP.)
110: Port 6 (GLIU0 = Not Used; GLIU1 = SB.)
111: Port 7 (GLIU0 = Not Used; GLIU1 = Not Used.)
60
PCMP_BIZ
Compare Bizzaro Flag.
0: Consider only transactions whose Bizzaro flag is low as a potentially valid address hit.
A low Bizzaro flag indicates a normal transaction cycle such as a memory or I/O.
1: Consider only transactions whose Bizzaro flag is high as a potentially valid address
hit. A high Bizzaro flag indicates a ‘special’ transaction, such as a PCI Shutdown or
Halt cycle.
59:40
39:20
RSVD
Reserved.
PBASE
Physical Memory Address Base. These bits form the matching value against which the
masked value of the physical address, bits [31:12] are directly compared. If a match is
found, then a “hit’ is declared, depending on the setting of the Bizzaro flag comparator.
19:0
PMASK
Physical Memory Address Mask. These bits are used to mask address bits [31:12] for
the purposes of this ‘hit’ detection.
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GLIU Register Descriptions
33234H
4.2.4.2 P2D Base Mask Offset Descriptor (P2D_BMO)
GLIU0
MSR Address
Type
P2D_BMO[1:0]
10000026h-10000027h
R/W
Reset Value
00000FF0_FFF00000h
P2D_BMO Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
PDID1
POFFSET
PBASE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PBASE PMASK
P2D_BMO Bit Descriptions
Bit
Name
Description
63:61
PDID1
Descriptor Destination ID. These bits define which Port to route the request to, if it is a
‘hit’ based on the other settings in this register.
000: Port 0 (GLIU0 = GLIU; GLIU1 = GLIU.)
001: Port 1 (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
010: Port 2 (GLIU0 = Interface to GLIU1; GLIU1 = VP.)
011: Port 3 (GLIU0 = CPU Core; GLIU1 = GLCP.)
100: Port 4 (GLIU0 = DC; GLIU1 = GLPCI.)
101: Port 5 (GLIU0 = GP; GLIU1 = VIP.)
110: Port 6 (GLIU0 = Not Used; GLIU1 = SB.)
111: Port 7 (GLIU0 = Not Used; GLIU1 = Not Used.)
60
PCMP_BIZ
Compare Bizzaro Flag.
0: Consider only transactions whose Bizzaro flag is low as a potentially valid address hit.
A low Bizzaro flag indicates a normal transaction cycle such as a memory or I/O.
1: Consider only transactions whose Bizzaro flag is high as a potentially valid address
hit. A high Bizzaro flag indicates a ‘special’ transaction, such as a PCI Shutdown or
Halt cycle.
59:40
39:20
POFFSET
PBASE
Physical Memory Address 2s Comp Offset. 2s complement offset that is added to
physical address on a hit.
Physical Memory Address Base. These bits form the matching value against which the
masked value of the physical address, bits [31:12] are directly compared. If a match is
found, then a “hit’ is declared, depending on the setting of the Bizzaro flag comparator.
19:0
PMASK
Physical Memory Address Mask. These bits are used to mask address bits [31:12] for
the purposes of this ‘hit’ detection.
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GLIU Register Descriptions
4.2.4.3 P2D Range Descriptor (P2D_R)
GLIU0
P2D_R[0]
GLIU1
P2D_R[3:0]
MSR Address
10000028h
MSR Address
4000002Ah-4000002Dh
Type
R/W
Type
R/W
Reset Value
00000000_000FFFFFh
Reset Value
00000000_000FFFFFh
P2D_R Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
PDID1
RSVD
PMAX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PMAX PMIN
P2D_R Bit Descriptions
Bit
Name
Description
63:61
PDID1
Descriptor Destination ID. These bits define which Port to route the request to, if it is a
‘hit’ based on the other settings in this register.
000: Port 0 (GLIU0 = GLIU; GLIU1 = GLIU.)
001: Port 1 (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
010: Port 2 (GLIU0 = Interface to GLIU1; GLIU1 = VP.)
011: Port 3 (GLIU0 = CPU Core; GLIU1 = GLCP.)
100: Port 4 (GLIU0 = DC; GLIU1 = GLPCI.)
101: Port 5 (GLIU0 = GP; GLIU1 = VIP.)
110: Port 6 (GLIU0 = Not Used; GLIU1 = SB.)
111: Port 7 (GLIU0 = Not Used; GLIU1 = Not Used.)
60
PCMP_BIZ
Compare Bizzaro Flag.
0: Consider only transactions whose Bizzaro flag is low as a potentially valid address hit.
A low Bizzaro flag indicates a normal transaction cycle such as a memory or I/O.
1: Consider only transactions whose Bizzaro flag is high as a potentially valid address
hit. A high Bizzaro flag indicates a ‘special’ transaction, such as a PCI Shutdown or
Halt cycle.
59:40
39:20
RSVD
PMAX
Reserved.
Physical Memory Address Max. These bits form the value denoting the upper (ending)
address of the physical memory, which is compared to determine a hit.
19:0
PMIN
Physical Memory Address Min. These bits form the value denoting the lower (starting)
address of the physical memory, which is compared to determine a hit. Hence, a hit
occurs if the physical address [31:12] >= PMIN and <= PMAX.
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GLIU Register Descriptions
33234H
4.2.4.4 P2D Range Offset Descriptor (P2D_RO)
GLIU0
P2D_RO[2:0]
MSR Address
10000029h-1000002Bh
Type
R/W
Reset Value
00000000_000FFFFFh
P2D_RO Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
PDID1
OFFSET
PMAX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PMAX PMIN
P2D_RO Bit Descriptions
Bit
Name
Description
63:61
PDID1
Descriptor Destination ID. These bits define which Port to route the request to, if it is a
‘hit’ based on the other settings in this register.
000: Port 0 (GLIU0 = GLIU; GLIU1 = GLIU.)
001: Port 1 (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
010: Port 2 (GLIU0 = Interface to GLIU1; GLIU1 = VP.)
011: Port 3 (GLIU0 = CPU Core; GLIU1 = GLCP.)
100: Port 4 (GLIU0 = DC; GLIU1 = GLPCI.)
101: Port 5 (GLIU0 = GP; GLIU1 = VIP.)
110: Port 6 (GLIU0 = Not Used; GLIU1 = SB.)
111: Port 7 (GLIU0 = Not Used; GLIU1 = Not Used.)
60
PCMP_BIZ
Compare Bizzaro Flag.
0: Consider only transactions whose Bizzaro flag is low as a potentially valid address hit.
A low Bizzaro flag indicates a normal transaction cycle such as a memory or I/O.
1: Consider only transactions whose Bizzaro flag is high as a potentially valid address
hit. A high Bizzaro flag indicates a ‘special’ transaction, such as a PCI Shutdown or
Halt cycle.
59:40
39:20
19:0
POFFSET
PMAX
Physical Memory Address 2’s Comp Offset. 2s complement offset that is added to
physical address on a hit.
Physical Memory Address Max. These bits form the value denoting the upper (ending)
address of the physical memory, which is compared to determine a hit.
PMIN
Physical Memory Address Min. These bits form the value denoting the lower (starting)
address of the physical memory, which is compared to determine a hit. Hence, a hit
occurs if the physical address [31:12] >= PMIN and <= PMAX.
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GLIU Register Descriptions
4.2.4.5 P2D Swiss Cheese Descriptor (P2D_SC)
GLIU0
MSR Address
Type
P2D_SC[0]
1000002Ch
R/W
GLIU1
MSR Address
Type
P2D_SC[0]
4000002Eh
R/W
Reset Value
00000000_00000000h
Reset Value
00000000_00000000h
P2D_SC Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
PDID1
RSVD
WEN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
REN
PSCBASE
P2D_SC Bit Descriptions
Bit
Name
Description
63:61
PDID1
Descriptor Destination ID 1. These bits define which Port to route the request to, if it is
a ‘hit’ based on the other settings in this register.
000: Port 0 (GLIU0 = GLIU; GLIU1 = GLIU.)
001: Port 1 (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
010: Port 2 (GLIU0 = Interface to GLIU1; GLIU1 = VP.)
011: Port 3 (GLIU0 = CPU Core; GLIU1 = GLCP.)
100: Port 4 (GLIU0 = DC; GLIU1 = GLPCI.)
101: Port 5 (GLIU0 = GP; GLIU1 = VIP.)
110: Port 6 (GLIU0 = Not Used; GLIU1 = SB.)
111: Port 7 (GLIU0 = Not Used; GLIU1 = Not Used.)
60
PCMP_BIZ
Compare Bizzaro Flag.
0: Consider only transactions whose Bizzaro flag is low as a potentially valid address hit.
A low Bizzaro flag indicates a normal transaction cycle such as a memory or I/O.
1: Consider only transactions whose Bizzaro flag is high as a potentially valid address
hit. A high Bizzaro flag indicates a ‘special’ transaction, such as a PCI Shutdown or
Halt cycle.
59:48
47:32
RSVD
WEN
Reserved.
Enable hits to the base for the ith 16K page for writes. When set to 1, causes the
incoming request to be routed to the port specified in PDID1 if the incoming request is a
write type.
31:16
REN
Enable hits to the base for the ith 16K page for reads. When set to 1, causes the
incoming request to be routed to the port specified in PDID1 if the incoming request is a
read type.
15:14
13:0
RSVD
Reserved.
PBASE
Physical Memory Address Base for Hit. These bits form the basis of comparison with
incoming checks that the physical address supplied by the device’s request on address
bits [31:18] are equal to PBASE. Bits [17:14] of the physical address are used to choose
the ith 16K region of WEN/REN for a hit.
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33234H
4.2.5
SPARE MSRs (SPARE_MSR[0:9], A:F)
MSR Address
GLIU0: 10000040h-1000004Fh
GLIU1: 40000040h-4000004Fh
R/W
Type
Reset Value
00000000_00000000h
SPARE_MSR[x] Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
SPARE_MSR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SPARE_MSR
SPARE_MSR[x] Bit Descriptions
Bit
Name
Description
Spare MSR.
63:0
SPARE_MSR
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GLIU Register Descriptions
4.2.6
I/O Descriptors
I/O descriptors are ordered IOD_BM, IOD_SC. For example if NIOD_BM = 3 and NIOD_SC = 2, MSR 100000EOh =
IOD_BM[0] and MSR 100000E3h = IOD_SC[0].
4.2.6.1 IOD Base Mask Descriptors (IOD_BM)
GLIU0
IOD_BM[0:3]
GLIU1
IOD_BM[0:3]
MSR Address
Type
100000E0h-100000E2h
R/W
MSR Address
Type
400000E0h-400000E2h
R/W
Reset Value
000000FF_FFF00000h
Reset Value
000000FF_FFF00000h
IOD_BM[x] Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
IDID
RSVD
IBASE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IBASE IMASK
IOD_BM[x] Bit Descriptions
Description
Bit
Name
63:61
IDID
I/O Descriptor Destination ID. These bits define which Port to route the request to, if it
is a ‘hit’ based on the other settings in this register.
000: Port 0 (GLIU0 = GLIU; GLIU1 = GLIU.)
001: Port 1 (GLIU0 = GLMC; GLIU1 = Interface to GLIU0.)
010: Port 2 (GLIU0 = Interface to GLIU1; GLIU1 = VP.)
011: Port 3 (GLIU0 = CPU Core; GLIU1 = GLCP.)
100: Port 4 (GLIU0 = DC; GLIU1 = GLPCI.)
101: Port 5 (GLIU0 = GP; GLIU1 = VIP.)
110: Port 6 (GLIU0 = Not Used; GLIU1 = SB.)
111: Port 7 (GLIU0 = Not Used; GLIU1 = Not Used.)
60
ICMP_BIZ
Compare Bizzaro Flag.
0: Consider only transactions whose Bizzaro flag is low as a potentially valid address hit.
A low Bizzaro flag indicates a normal transaction cycle such as a memory or I/O.
1: Consider only transactions whose Bizzaro flag is high as a potentially valid address
hit. A high Bizzaro flag indicates a ‘special’ transaction, such as a PCI Shutdown or
Halt cycle.
59:40
39:20
RSVD
IBASE
Reserved.
Physical I/O Address Base. These bits form the matching value against which the
masked value of the physical address, bits [19:0] are directly compared. If a match is
found, then a “hit’ is declared, depending on the setting of the Bizzaro flag comparator.
19:0
IMASK
Physical I/O Address Mask. These bits are used to mask address bits [31:12] for the
purposes of this ‘hit’ detection.
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GLIU Register Descriptions
33234H
4.2.6.2 IOD Swiss Cheese Descriptors (IOD_SC)
GLIU0
IOD_SC[0:5]
GLIU1
IOD_SC[0:3]
MSR Address
100000E3h-100000E8h
MSR Address
400000E3h-400000E6h
Type
R/W
Type
R/W
Reset Value
00000000_00000000h
Reset Value
00000000_00000000h
IOD_SC[x] Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
IDID1
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
EN
RSVD
IBASE
RSVD
IOD_SC[x] Bit Descriptions
Bit
Name
Description
63:61
IDID1
Descriptor Destination ID 1. Encoded port number of the destination of addresses
which produce a ‘hit’ based on the other fields in this descriptor.
60
ICMP_BIZ
Compare Bizzaro Flag. Used to check that the Bizzaro flag of the request is equal to
the PICMP_BIZ_SC bit (this bit). If a match does not occur, then the incoming request
cannot generate a hit. The Bizzaro flag, if set in the incoming request, signifies a “spe-
cial’ cycle such as a PCI Shutdown or Halt.
59:32
31:24
RSVD
EN
Reserved. Write as read.
Enable for Hits to IDID1 or else SUBP. Setting these bits enables hits to IDID1. If not
enabled, subtractive port is selected per GLD_MSR_CONFIG, bits [2:0] (MSR GLIU0:
10002001h; GLIU1: 40002001h). (See Section 4.2.1.2 "GLD Master Configuration MSR
(GLD_MSR_CONFIG)" on page 55 for bit descriptions).
23:22
21
RSVD
WEN
Reserved.
Descriptor Hits IDID1 on Write Request Types else SUBP. If set, causes the incom-
ing request to be routed to the port specified in IDID1 if the incoming request is a Write
type. If not set, subtractive port is selected per GLD_MSR_CONFIG, bits [2:0] (MSR
GLIU0: 10002001h; GLIU1: 40002001h). (See Section 4.2.1.2 "GLD Master Configura-
tion MSR (GLD_MSR_CONFIG)" on page 55 for bit descriptions).
20
REN
Descriptors Hit IDID1 on Read Request Types else SUBP. If set, causes the incom-
ing request to be routed to the port specified in IDID1 if the incoming request is a Read
type. If not set, subtractive port is selected per GLD_MSR_CONFIG, bits [2:0] (MSR
GLIU0: 10002001h; GLIU1: 40002001h). (See Section 4.2.1.2 "GLD Master Configura-
tion MSR (GLD_MSR_CONFIG)" on page 55 for bit descriptions).
19:3
2:0
IBASE
RSVD
I/O Memory Base. This field forms the basis of comparison with the incoming checks
that the physical address supplied by the device’s request on address bits [31:18] are
equal to the PBASE field of descriptor register bits [13:0].
Reserved. Write as read.
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GLIU Register Descriptions
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CPU Core
33234H
5.0CPU Core
5
This section describes the internal operations of the
AMD Geode™ LX processor’s CPU Core from a program-
mer’s point of view. It includes a description of the tradi-
tional “core” processing and FPU operations. The
integrated function registers are described in the next
chapter.
and turns off paging. When RESET# is asserted, the CPU
terminates all local bus activity and all internal execution.
While RESET# is asserted, the internal pipeline is flushed
and no instruction execution or bus activity occurs.
Approximately 150 to 250 external clock cycles after
RESET# is de-asserted, the processor begins executing
instructions at the top of physical memory (address location
FFFFFFF0h). The actual number of clock cycles depends
on the clock scaling in use. Also, before execution begins,
The primary register sets within the processor core include:
• Application Register Set
• System Register Set
20
an additional 2 clock cycles are needed when self-test is
requested.
5.1
Core Processor Initialization
Typically, an intersegment jump is placed at FFFFFFF0h.
This instruction forces the processor to begin execution in
Core registers and illustrates how they are initialized.
The CPU Core is initialized when the RESET# (Reset) sig-
nal is asserted. The CPU Core is placed in real mode and
values. RESET# invalidates and disables the CPU cache,
Table 5-1. Initialized Core Register Controls
Initialized Contents
(Note 1)
Register Register Name
Comments
EAX
EBX
ECX
EDX
EBP
ESI
Accumulator
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxx 04 [DIR0]h
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
00000002h
0000FFF0h
0000h
00000000h indicates self-test passed.
Base
Count
Data
DIR0 = Device ID
Base Pointer
Source Index
EDI
Destination Index
Stack Pointer
ESP
EFLAGS
EIP
Extended Flags
Instruction Pointer
Extra Segment
Code Segment
Stack Segment
Data Segment
ES
Base address set to 00000000h. Limit set to FFFFh.
Base address set to FFFF0000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
CS
F000h
SS
0000h
DS
0000h
FS
Extra Segment
Extra Segment
Interrupt Descriptor Table Register
Global Descriptor Table Register
Local Descriptor Table Register
Task Register
0000h
GS
0000h
IDTR
GDTR
LDTR
TR
Base = 0, Limit = 3FFh
xxxxxxxxh
xxxxh
xxxxh
CR0
CR2
CR3
CR4
Control Register 0
Control Register 2
Control Register 3
Control Register 4
60000010h
xxxxxxxxh
xxxxxxxxh
00000000h
Note 1.
x = Undefined value.
AMD Geode™ LX Processors Data Book
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33234H
CPU Core
page 634) contains the clock count table that lists each
instruction in the CPU instruction set. Included in the table
are the associated opcodes, execution clock counts, and
effects on the EFLAGS register.
5.2
Instruction Set Overview
The CPU Core instruction set can be divided into nine
types of operations:
• Arithmetic
• Bit Manipulation
• Shift/Rotate
5.2.1
Lock Prefix
The LOCK prefix may be placed before certain instructions
that read, modify, then write back to memory. The PCI will
not be granted access in the middle of locked instructions.
The LOCK prefix can be used with the following instructions
only when the result is a write operation to memory.
• String Manipulation
• Control Transfer
• Data Transfer
• Bit Test Instructions (BTS, BTR, BTC)
• Floating Point
• Exchange Instructions (XADD, XCHG, CMPXCHG)
• High-Level Language Support
• Operating System Support
• One-Operand Arithmetic and Logical Instructions (DEC,
INC, NEG, NOT)
The instructions operate on as few as zero operands and
as many as three operands. A NOP (no operation) instruc-
tion is an example of a zero-operand instruction. Two-oper-
and instructions allow the specification of an explicit source
and destination pair as part of the instruction. These two-
operand instructions can be divided into ten groups accord-
ing to operand types:
• Two-Operand Arithmetic and Logical Instructions (ADC,
ADD, AND, OR, SBB, SUB, XOR).
An invalid opcode exception is generated if the LOCK pre-
fix is used with any other instruction or with one of the
instructions above when no write operation to memory
occurs (for example, when the destination is a register).
• Register to Register
• Register to Memory
• Memory to Register
• Memory to Memory
• Register to I/O
5.2.2
Register Sets
The accessible registers in the processor are grouped into
two sets:
1) The Application Register Set contains the registers
on page 91 shows the General Purpose, Segment,
Instruction Pointer and EFLAGS registers.
• I/O to Register
• Memory to I/O
2) The System Register Set contains the registers typi-
cally reserved for operating systems programmers:
Control, System Address, Debug, Configuration, and
Test registers. All accesses to the these registers use
special CPU instructions.
• I/O to Memory
• Immediate Data to Register
• Immediate Data to Memory
Both of these register sets are discussed in detail in the
subsections that follow.
An operand can be held in the instruction itself (as in the
case of an immediate operand), in one of the processor’s
registers or I/O ports, or in memory. An immediate operand
is fetched as part of the opcode for the instruction.
Operand lengths of 8, 16, 32 or 48 bits are supported as
well as 64 or 80 bits associated with floating-point instruc-
tions. Operand lengths of 8 or 32 bits are generally used
when executing code written for 386- or 486-class (32-bit
code) processors. Operand lengths of 8 or 16 bits are gen-
erally used when executing existing 8086 or 80286 code
(16-bit code). The default length of an operand can be
overridden by placing one or more instruction prefixes in
front of the opcode. For example, the use of prefixes allows
a 32-bit operand to be used with 16-bit code or a 16-bit
operand to be used with 32-bit code.
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5.3
Application Register Set
The Application Register Set consists of the registers most
often used by the applications programmer. These regis-
ters are generally accessible, although some bits in the
EFLAGS registers are protected.
that contain the base address for each segment, as well as
other memory addressing information.
The Instruction Pointer register points to the next instruc-
tion that the processor will execute. This register is auto-
matically incremented by the processor as execution
progresses.
The General Purpose register contents are frequently
modified by instructions and typically contain arithmetic
and logical instruction operands.
The EFLAGS register contains control bits used to reflect
the status of previously executed instructions. This register
also contains control bits that affect the operation of some
instructions.
In real mode, Segment registers contain the base
address for each segment. In protected mode, the Seg-
ment registers contain segment selectors. The segment
selectors provide indexing for tables (located in memory)
Table 5-2. Application Register Set
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
General Purpose Registers
8
7
6
5
4
3
2
1
0
AX
AH
AL
EAX (Extended A Register)
BX
CX
DX
BH
BL
EBX (Extended B Register)
CH
CL
DL
ECX (Extended C Register)
DH
EDX (Extended D Register)
SI (Source Index)
ESI (Extended Source Index)
EDI (Extended Destination Index)
EBP (Extended Base Pointer)
ESP (Extended Stack Pointer)
DI (Destination Index)
BP (Base Pointer)
SP (Stack Pointer)
Segment (Selector) Registers
CS (Code Segment)
SS (Stack Segment)
DS (D Data Segment)
ES (E Data Segment)
FS (F Data Segment)
GS (G Data Segment)
Instruction Pointer and EFLAGS Registers
EIP (Extended Instruction Pointer)
ESP (Extended EFLAGS Register)
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The EBP register may be used to refer to data passed on
the stack during procedure calls. Local data may also be
placed on the stack and accessed with BP. This register
provides a mechanism to access stack data in high-level
languages.
5.3.1
General Purpose Registers
The General Purpose registers are divided into four data
registers, two pointer registers, and two index registers as
The Data registers are used by the applications program-
mer to manipulate data structures and to hold the results of
logical and arithmetic operations. Different portions of gen-
eral data registers can be addressed by using different
names.
5.3.2
Segment Registers
The 16-bit Segment registers are part of the main memory
addressing mechanism. The six segment registers are:
CS - Code Segment
DS - Data Segment
SS - Stack Segment
An “E” prefix identifies the complete 32-bit register. An “X”
suffix without the “E” prefix identifies the lower 16 bits of the
register.
ES - Extra Segment
FS - Additional Data Segment
GS - Additional Data Segment
The lower two bytes of a data register are addressed with
an “H” suffix (identifies the upper byte) or an “L” suffix (identi-
fies the lower byte). These _L and _H portions of the data
registers act as independent registers. For example, if the
AH register is written to by an instruction, the AL register
bits remain unchanged.
The Segment registers are used to select segments in
main memory. A segment acts as private memory for differ-
ent elements of a program such as code space, data space
and stack space. There are two segment mechanisms, one
for real and virtual 8086 operating modes and one for pro-
tected mode.
The Pointer and Index registers are listed below.
SI or ESI
DI or EDI
Source Index
Destination Index
The active Segment register is selected according to the
currently processed. In general, the DS register selector is
used for data references. Stack references use the SS reg-
ister, and instruction fetches use the CS register. While
some selections may be overridden, instruction fetches,
stack operations, and the destination write operation of
string operations cannot be overridden. Special segment-
override instruction prefixes allow the use of alternate seg-
ment registers. These segment registers include the ES,
FS, and GS registers.
SP or ESP Stack Pointer
BP or EBP Base Pointer
These registers can be addressed as 16- or 32-bit registers,
with the “E” prefix indicating 32 bits. The Pointer and Index
registers can be used as general purpose registers; how-
ever, some instructions use a fixed assignment of these
registers. For example, repeated string operations always
use ESI as the source pointer, EDI as the destination
pointer, and ECX as a counter. The instructions that use
fixed registers include multiply and divide, I/O access,
string operations, stack operations, loop, variable shift and
rotate, and translate instructions.
5.3.3
Instruction Pointer Register
The Instruction Pointer (EIP) register contains the offset
into the current code segment of the next instruction to be
executed. The register is normally incremented by the
length of the current instruction with each instruction exe-
cution unless it is implicitly modified through an interrupt,
exception, or an instruction that changes the sequential
execution flow (for example JMP and CALL).
The CPU Core implements a stack using the ESP register.
This stack is accessed during the PUSH and POP instruc-
tions, procedure calls, procedure returns, interrupts, excep-
tions, and interrupt/exception returns. The Geode LX
processor automatically adjusts the value of the ESP dur-
ing operations that result from these instructions.
Table 5-3. Segment Register Selection Rules
Implied (Default)
Segment-Override
Prefix
Type of Memory Reference
Segment
Code Fetch
CS
SS
SS
ES
None
None
None
None
Destination of PUSH, PUSHF, INT, CALL, PUSHA instructions
Source of POP, POPA, POPF, IRET, RET instructions
Destination of STOS, MOVS, REP STOS, REP MOVS instructions
Other data references with effective address using base registers of:
EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP
DS
SS
CS, ES, FS, GS, SS
CS, DS, ES, FS, GS
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lower 16 bits of this register are used when executing 8086
EFLAGS register.
5.3.4
EFLAGS Register
The EFLAGS register contains status information and con-
trols certain operations on the Geode LX processor. The
Table 5-4. EFLAGS Register
Bit
Name
Flag Type
Description
Reserved. Set to 0.
31:22
21
RSVD
ID
--
System
Identification Bit. The ability to set and clear this bit indicates that the CPUID instruction is sup-
ported. The ID can be modified only if the CPUID bit in CCR4 (Index E8h[7]) is set.
20:19
18
RSVD
AC
--
Reserved. Set to 0.
System
Alignment Check Enable. In conjunction with the AM flag (bit 18) in CR0, the AC flag deter-
mines whether or not misaligned accesses to memory cause a fault. If AC is set, alignment
faults are enabled.
17
16
VM
RF
System
Debug
Virtual 8086 Mode. If set while in protected mode, the processor switches to virtual 8086 oper-
ation handling segment loads as the 8086 does, but generating exception 13 faults on privileged
opcodes. The VM bit can be set by the IRET instruction (if current privilege level is 0) or by task
switches at any privilege level.
Resume Flag. Used in conjunction with debug register breakpoints. RF is checked at instruction
boundaries before breakpoint exception processing. If set, any debug fault is ignored on the next
instruction.
15
14
RSVD
NT
--
Reserved. Set to 0.
System
Nested Task. While executing in protected mode, NT indicates that the execution of the current
task is nested within another task.
13:12
IOPL
System
Arithmetic
Control
I/O Privilege Level. While executing in protected mode, IOPL indicates the maximum current
privilege level (CPL) permitted to execute I/O instructions without generating an exception 13
fault or consulting the I/O permission bit map. IOPL also indicates the maximum CPL allowing
alteration of the IF bit when new values are popped into the EFLAGS register.
11
OF
Overflow Flag. Set if the operation resulted in a carry or borrow into the sign bit of the result but
did not result in a carry or borrow out of the high-order bit. Also set if the operation resulted in a
carry or borrow out of the high-order bit but did not result in a carry or borrow into the sign bit of
the result.
10
DF
Direction Flag. When cleared, DF causes string instructions to auto-increment (default) the
appropriate index registers (ESI and/or EDI). Setting DF causes auto-decrement of the index
registers to occur.
9
8
IF
System
Debug
Interrupt Enable Flag. When set, maskable interrupts (INTR input pin) are acknowledged and
serviced by the CPU.
TF
Trap Enable Flag. Once set, a single-step interrupt occurs after the next instruction completes
execution. TF is cleared by the single-step interrupt.
7
6
5
4
SF
ZF
Arithmetic
Arithmetic
--
Sign Flag. Set equal to high-order bit of result (0 indicates positive, 1 indicates negative).
Zero Flag. Set if result is zero; cleared otherwise.
Reserved. Set to 0.
RSVD
AF
Arithmetic
Auxiliary Carry Flag. Set when a carry out of (addition) or borrow into (subtraction) bit position
3 of the result occurs; cleared otherwise.
3
2
RSVD
PF
--
Reserved. Set to 0.
Arithmetic
Parity Flag. Set when the low-order 8 bits of the result contain an even number of ones; other-
wise PF is cleared.
1
0
RSVD
CF
Reserved. Set to 1.
Arithmetic
Carry Flag. Set when a carry out of (addition) or borrow into (subtraction) the most significant
bit of the result occurs; cleared otherwise.
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5.4
System Register Set
registers not generally used by application programmers.
These registers are either initialized by the system BIOS or
employed by system level programmers who generate
operating systems and memory management programs.
Associated with the System Register Set are certain tables
Table 5-5. System Register Set
Width
(Bits)
Group
Name
Function
Control
Registers
CR0
System Control
Register
32
32
32
CR2
CR3
Page Fault Linear
Address Register
The Control registers control certain aspects of the CPU
Core such as paging, coprocessor functions, and segment
protection.
Page Directory Base
Register
CR4
PLn
Feature Enables
32
64
The CPU Core Configuration registers are used to initial-
ize, provide for, test or define most of the features of the
CPU Core. The attributes of these registers include:
CPU Core
Configuration
Registers
Pipeline
Control Registers
IMn
Instruction Memory
Control Registers
64
64
64
64
• CPU setup - Enable cache, features, operating modes.
• Debug support - Provide debugging facilities for the
Geode™ LX processor and enable the use of data
access breakpoints and code execution breakpoints.
DMn
BCn
FPUn
Data Memory Con-
trol Registers
Bus Controller Con-
trol Registers
• Built-in Self-test (BIST) support.
• Test - Support a mechanism to test the contents of the
on-chip caches and the Translation Lookaside Buffers
(TLBs).
Floating Point Unit
Shadow Registers
Descriptor
Table
Registers
GDTR
IDTR
LDTR
TR
GDT Register
IDT Register
LDT Register
Task Register
32
32
16
16
8
• In-Circuit Emulation (ICE) - Provide for a alternative
accessing path to support an ICE.
• CPU identification - Allow the BIOS and other software
Task Register
to identify the specific CPU and stepping.
Performance
Registers
PCRn
Performance
Control Registers
• Power Management.
• Performance Monitoring - Enables test software to
measure the performance of application software.
The Descriptor Table registers point to tables used to
manage memory segments and interrupts.
The Task State register points to the Task State Segment,
which is used to save and load the processor state when
switching tasks.
size and function.
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The CD bit (Cache Disable, bit 30) in CR0 globally controls
the operating mode of the L1 and L2 caches. LCD and
LWT, Local Cache Disable and Local Write-through bits in
the Translation Lookaside Buffer, control the mode on a
page-by-page basis. Additionally, memory configuration
control can specify certain memory regions as non-cache-
able.
5.4.1
Control Registers
A map of the Control registers (CR0, CR1, CR2, CR3, and
the tables that follow. (These registers should not be con-
fused with the CRRn registers.) CR0 contains system con-
trol bits that configure operating modes and indicate the
general state of the CPU. The lower 16 bits of CR0 are
referred to as the Machine Status Word (MSW).
If the cache is disabled, no further cache line fills occur.
However, data already present in the cache continues to be
used. For the cache to be completely disabled, the cache
must be invalidated with a WBINVD instruction after the
cache has been disabled.
When operating in real mode, any program can read and
write the control registers. In protected mode, however,
only privilege level 0 (most-privileged) programs can read
and write these registers.
Write-back caching improves performance by relieving con-
gestion on slower external buses.
L1 Cache Controller
The Geode LX processor contains an on-board 64 KB L1
instruction cache, a 64 KB L1 write-back data cache, and a
128 KB unified L2 victim cache. With the memory controller
on-board, the L1 cache requires no external logic to main-
tain coherency. All DMA cycles automatically snoop the L1
and L2 caches.
The Geode LX processor caches SMM regions, reducing
system management overhead to allow for hardware emu-
lation such as VGA.
Table 5-6. Control Registers Map
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CR4 Register
Control Register 4 (R/W)
RSVD
RSVD
RSVD
CR3 Register
CR2 Register
CR1 Register
CR0 Register
Control Register 3 (R/W)
PDBR (Page Directory Base Register)
Control Register 2 (R/W)
RSVD
0
0
RSVD
PFLA (Page Fault Linear Address)
Control Register 1 (R/W)
RSVD
Control Register 0 (R/W)
RSVD
RSVD
Machine Status Word (MSW)
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Table 5-7. CR4 Bit Descriptions
Description
Reserved. Set to 0 (always returns 0 when read).
Bit
Name
31:9
8
RSVD
PCE
Performance Counter Enable. Set PCE = 1 to make RDPMC available at nonzero privi-
lege levels.
7
PGE
Page Global Enable. Set PGE = 1 to make global pages immune to INVLPG instruc-
tions.
6:5
4
RSVD
PSE
DE
Reserved. Set to 0 (always returns 0 when read).
Page Size Extensions. Set PSE = 1 to enable 4 MB pages.
3
Debug Extensions. Set DE = 1 to enable debug extensions (i.e., DR4, DR5, and I/O
breakpoints).
2
TSC
Time Stamp Counter Instruction.
0: RDTSC instruction enabled for all CPL states.
1: RDTSC instruction enabled for CPL = 0 only.
1:0
RSVD
Reserved. Set to 0 (always returns 0 when read).
Table 5-8. CR3 Bit Descriptions
Description
Bit
Name
31:12
PDBR
Page Directory Base Register. Identifies page directory base address on a 4 KB page
boundary.
11:0
RSVD
Reserved. Set to 0.
Table 5-9. CR2 Bit Descriptions
Description
Bit
Name
31:0
PFLA
Page Fault Linear Address. With paging enabled and after a page fault, PFLA contains
the linear address of the address that caused the page fault.
Table 5-10. CR0 Bit Descriptions
Description
Bit
Name
31
PG
Paging Enable Bit. If PG = 1 and protected mode is enabled (PE = 1), paging is
enabled. After changing the state of PG, software must execute an unconditional branch
instruction (e.g., JMP, CALL) to have the change take effect.
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Table 5-10. CR0 Bit Descriptions (Continued)
Description
Name
30
29
CD
Cache Disable/Not Write-Through (Snoop). Cache behavior is based on the CR0 CD
and NW bits.
NW
CD
0
NW
0
Normal Cache operation, coherency maintained.
Read hits access the cache,
Write hits update the cache,
Read/write misses may cause line allocations based on memory
region configuration settings.
0
1
1
0
Invalid, causes a General Protection Fault (GPF).
Cache off, coherency maintained (i.e., snooping enabled).
Read hits access the cache,
Write hits update the cache,
Read/write misses do not cause line allocations.
1
1
Cache off, coherency not maintained (i.e., snooping disabled).
Read hits access the cache,
Write hits update the cache,
Read/write misses do not cause line allocations.
28:19
18
RSVD
AM
Reserved.
Alignment Check Mask. If AM = 1, the AC bit in the EFLAGS register is unmasked and
allowed to enable alignment check faults. Setting AM = 0 prevents AC faults from occur-
ring.
17
16
RSVD
WP
Reserved
Write Protect. Protects read only pages from supervisor write access. WP = 0 allows a
read only page to be written from privilege level 0-2. WP = 1 forces a fault on a write to a
read only page from any privilege level.
15:6
5
RSVD
NE
Reserved.
Numerics Exception. NE = 1 to allow FPU exceptions to be handled by interrupt 16.
NE = 0 if FPU exceptions are to be handled by external interrupts.
4
3
ET (RO)
TS
Extension Type (Read Only). (Default = 1)
Task Switched. Set whenever a task switch operation is performed. Execution of a float-
ing point instruction with TS = 1 causes a Device Not Available (DNA) fault. If MP = 1 and
TS = 1, a WAIT instruction also causes a DNA fault. (Note 1)
2
1
EM
MP
Emulate Processor Extension. If EM = 1, all floating point instructions cause a DNA
fault 7. (Note 1)
Monitor Processor Extension. If MP = 1 and TS = 1, a WAIT instruction causes DNA
fault 7. The TS bit is set to 1 on task switches by the CPU. Floating point instructions are
not affected by the state of the MP bit. The MP bit should be set to 1 during normal oper-
0
PE
Protected Mode Enable. Enables the segment based protection mechanism. If PE = 1,
protected mode is enabled. If PE = 0, the CPU operates in real mode and addresses are
formed as in an 8086-style CPU.
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Table 5-11. Effects of Various Combinations of EM, TS, and MP Bits
CR0[3:1]
EM
Instruction Type
TS
MP
WAIT
ESC
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
Execute
Execute
Execute
Fault 7
Execute
Execute
Fault 7
Fault 7
Fault 7
Fault 7
Fault 7
Fault 7
Execute
Execute
Execute
Fault 7
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5.5
CPU Core Register Descriptions
All CPU Core registers are Model Specific Registers
(MSRs) and are accessed via the RDMSR and WRMSR
instructions.
meaning a RDMSR/WRMSR instruction attempting to use
the address generates a General Protection Fault.
The registers associated with the CPU Core are the Stan-
dard GeodeLink™ Device MSRs and CPU Core Specific
tables that include reset values and page references where
the bit descriptions are provided. Note that the standard
GLD MSRs for the CPU Core start at 00002000h.
Each module inside the processor is assigned a 256 regis-
ter section of the address space. The module responds to
any reads or writes in that range. Unused addresses within
a module’s address space are reserved, meaning the mod-
ule returns zeroes on a read and ignores writes. Addresses
that are outside all the module address spaces are invalid,
Table 5-12. Standard GeodeLink™ Device MSRs Summary
MSR
Address
Type
Register Name
Reset Value
Reference
00002000h
00002001h
RO
00000000_000864xxh
00000000_00000320h
R/W
00002002h
00002003h
00002004h
R/W
R/W
R/W
GLD SMI MSR (GLD_MSR_SMI) - Not Used
00000000_00000000h
00000000_00000000h
00000000_00000000h
GLD Error MSR (GLD_MSR_ERROR) - Not Used
Not Used
00002005h
R/W
00000000_00000000h
Table 5-13. CPU Core Specific MSRs Summary
Register Name
MSR
Address
Type
Reset Value
Reference
00000010h
00000186h
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CPU Core Register Descriptions
Table 5-13. CPU Core Specific MSRs Summary (Continued)
MSR
Address
Type
Register Name
Reset Value
Reference
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Table 5-13. CPU Core Specific MSRs Summary (Continued)
MSR
Address
Type
Register Name
Reset Value
Reference
00001353h
R/W
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CPU Core Register Descriptions
Table 5-13. CPU Core Specific MSRs Summary (Continued)
MSR
Address
Type
Register Name
Reset Value
Reference
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Table 5-13. CPU Core Specific MSRs Summary (Continued)
MSR
Address
Type
Register Name
Reset Value
Reference
Warm Start Value:
Warm Start Value:
Warm Start Value:
Warm Start Value:
Warm Start Value:
Warm Start Value:
Warm Start Value:
Warm Start Value:
Warm Start Value:
Warm Start Value:
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CPU Core Register Descriptions
Table 5-13. CPU Core Specific MSRs Summary (Continued)
MSR
Address
Type
Register Name
Reset Value
Reference
Warm Start Value:
Warm Start Value:
Warm Start Value:
Warm Start Value:
Warm Start Value:
00001882h
00001883h
00001884h
00001890h
R/W
R/W
R/W
R/W
x86 Control Register 2 MSR (CR2_MSR)
x86 Control Register 3 MSR (CR3_MSR)
x86 Control Register 4 MSR (CR4_MSR)
00000000_xxxxxxxxh
00000000_xxxxxxxxh
00000000_xxxxxxxxh
00000000_00000000h
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Table 5-13. CPU Core Specific MSRs Summary (Continued)
MSR
Address
Type
Register Name
Reset Value
Reference
00001904h
RO
00000000_00000000h
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CPU Core Register Descriptions
Table 5-13. CPU Core Specific MSRs Summary (Continued)
MSR
Address
Type
Register Name
Reset Value
Reference
xxxxxxxx_xxxxxxxxh
R/W
00001A60h-
00001A6Fh
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Table 5-13. CPU Core Specific MSRs Summary (Continued)
MSR
Address
Type
Register Name
Reset Value
Reference
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CPU Core Register Descriptions
5.5.1
Standard GeodeLink™ Device MSRs
5.5.1.1 GLD Capabilities MSR (GLD_MSR_CAP)
MSR Address
Type
00002000h
RO
Reset Value
00000000_000864xxh
GLD_MSR_CAP Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
DEV_ID
REV_ID
GLD_MSR_CAP Bit Descriptions
Bit
Name
Description
63:24
23:8
7:0
RSVD
Reserved. Reads as 0.
DEV_ID
REV_ID
Device ID. Identifies device (0864h).
Revision ID. Identifies device revision. See AMD Geode™ LX Processors Specification
Update document for value.
5.5.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG)
MSR Address
Type
00002001h
R/W
Reset Value
00000000_00000320h
GLD_MSR_CONFIG Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
RSVD
PRI0
PID
GLD_MSR_CONFIG Bit Descriptions
Bit
Name
Description
63:11
10:7
6:4
RSVD
RSVD
PRI0
RSVD
PID
Reserved. Write as read.
Reserved. (Default = 3)
Priority Level. Priority value used for CPU Core GLIU requests. (Default = 2)
3
Reserved. Write as read.
2:0
Priority ID Value. Priority ID value used for CPU Core GLIU requests. Always write to 0.
(Default = 0)
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5.5.1.3 GLD SMI MSR (GLD_MSR_SMI)
MSR Address
Type
00002002h
R/W
Reset Value
00000000_00000000h
This register is not used in the CPU Core module.
5.5.1.4 GLD Error MSR (GLD_MSR_ERROR)
MSR Address
Type
00002003h
R/W
Reset Value
00000000_00000000h
This register is not used in the CPU Core module.
5.5.1.5 GLD Power Management MSR (GLD_MSR_PM)
MSR Address
Type
00002004h
R/W
Reset Value
00000000_00000000h
This register is not used in the CPU Core module.
5.5.1.6 GLD Diagnostic Bus Control MSR (GLD_MSR_DIAG)
MSR Address
Type
00002005h
R/W
Reset Value
00000000_00000000h
This register is reserved for internal use by AMD and should not be written to.
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CPU Core Register Descriptions
5.5.2
CPU Core Specific MSRs
5.5.2.1 Time Stamp Counter MSR (TSC_MSR)
MSR Address
Type
00000010h
R/W
Reset Value
00000000_00000000h
TSC_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
TSC (High DWORD)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TSC (Low DWORD)
TSC_MSR Bit Descriptions
Bit
Name
Description
63:0
TSC
Time Stamp Counter. This register is the 64-bit time stamp counter, also readable via
the RDTSC instruction.
Bus Controller Configuration 0 Register (MSR 00001900h) contains configuration bits
that determine if TSC counts during SMM, DMM, or Suspend modes.
Writes to this register clears the upper DWORD to 0. The lower DWORD is written nor-
mally.
5.5.2.2 Performance Event Counter 0 MSR (PERF_CNT0_MSR)
MSR Address
Type
000000C1h
R/W
Reset Value
00000000_00000000h
PERF_CNT0_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PERF_CNT0 (Low DWORD)
PERF_CNT0 (High Byte)
9
8
7
6
5
4
3
2
1
0
PERF_CNT0_MSR Bit Descriptions
Bit
Name
Description
63:40
39:0
RSVD
Reserved. Write as read.
PERF_CNT0
Performance Event Counter 0. This register is a 40-bit event counter used to count
events or conditions inside of the CPU Core. This counter is controlled by Performance
Event Counter 0 Select MSR (MSR 00000186h).
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5.5.2.3 Performance Event Counter 1 MSR (PERF_CNT1_MSR)
MSR Address
Type
000000C2h
R/W
Reset Value
00000000_00000000h
PERF_CNT1_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
PERF_CNT1 (Low DWORD)
PERF_CNT1 (High Byte)
9
8
7
6
5
4
3
2
1
0
PERF_CNT1_MSR Bit Descriptions
Bit
Name
Description
63:40
39:0
RSVD
Reserved. Write as read.
PERF_CNT1
Performance Event Counter 1. This register is a 40-bit event counter used to count
events or conditions inside the CPU Core. This counter is controlled by Performance
Event Counter 1 Select MSR (MSR 00000187h).
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CPU Core Register Descriptions
5.5.2.4 SYSENTER/SYSEXIT Code Segment Selector MSR (SYS_CS_MSR)
MSR Address
Type
00000174h
R/W
Reset Value
00000000_C09B0000h
SYS_CS_MSR is used by the SYSENTER instruction (fast system call) as the selector of the most privileged code seg-
ment. SYS_CS plus 8 is used by SYSENTER as the selector of the most privileged stack segment. SYS_CS plus 16 is
used by SYSEXIT as the selector of the least privileged code segment. SYS_CS plus 24 is used by SYSEXIT as the selec-
tor of the least privileged stack segment.
SYS_CS_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
G
D
RSVD
P
DPL
S
X
C
R
A
CS_SEL
TI RPL
SYS_CS_MSR Bit Descriptions
Bit
Name
Description
Reserved.
63:32
31
RSVD
G (RO)
Granularity (Read Only). Code segment limit granularity is 4 KB. (Default = 1)
Default (Read Only). Code segment default size is 32 bits. (Default = 1)
Reserved (Read Only).
30
D (RO)
29:24
23
RSVD (RO)
P (RO)
Present (Read Only). Code segment descriptor is present. (Default = 1)
22:21
DPL (RO)
Descriptor Privilege Level (Read Only). Code segment descriptor privilege level.
(Default = 11)
20
19
S (RO)
X (RO)
C (RO)
R (RO)
A (RO)
CS_SEL
TI
Segment (Read Only). Code segment is not a system segment. (Default = 1)
Executable (Read Only). Code segment is executable. (Default = 1)
Conforming (Read Only). Code segment is conforming. (Default = 0)
Readable (Read Only). Code segment is readable. (Default = 1)
Accessed (Read Only). Code segment was accessed. (Default = 1)
Code Segment Selector. (Default = 0)
18
17
16
15:3
2
Descriptor Table Indicator. (Default = 0)
1:0
RPL (RO)
Requestor Privilege Level (Read Only). (Default = 0)
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5.5.2.5 SYSENTER/SYSEXIT Stack Pointer MSR (SYS_SP_MSR)
MSR Address
Type
00000175h
R/W
Reset Value
00000000_00000000h
SYS_SP MSR is used by the SYSENTER instruction (fast system call) as the most privileged stack pointer.
SYS_SP_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ESP
SYS_SP_MSR Bit Descriptions
Bit
Name
Description
Reserved.
63:32
31:0
RSVD
ESP
Enter Stack Pointer. Stack pointer to be used after SYSENTER in most privileged code.
(Default = 0)
5.5.2.6 SYSENTER/SYSEXIT Instruction Pointer MSR (SYS_IP_MSR)
MSR Address
Type
00000176h
R/W
Reset Value
00000000_00000000h
SYS_IP MSR is used by the SYSENTER instruction (fast system call) as the offset into the most privileged code segment.
SYS_IP_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
EIP
SYS_IP_MSR Bit Descriptions
Bit
Name
Description
Reserved.
63:32
31:0
RSVD
EIP
Enter Instruction Pointer. Offset into the most privileged code segment. (Default = 0)
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CPU Core Register Descriptions
5.5.2.7 Performance Event Counter 0 Select MSR (PERF_SEL0_MSR
MSR Address
Type
00000186h
R/W
Reset Value
00000000_00000000h
PERF_SEL0_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RSVD RSVD PC0_UMASK
9
8
7
6
5
4
3
2
1
0
PC0_EVENT
PERF_SEL0_MSR Bit Descriptions
Description
Bit
Name
63:23
22
RSVD
Reserved. Write as read.
PC_EN
Performance Event Counters 0 and 1 Enable.
0: Disable counters.
1: Enable counters.
21:16
15:8
RSVD
Reserved. Write as read.
PC0_UMASK
Performance Event Counter 0 Unit Mask. Selects sub-events.
00h: All sub-events counted.
7:0
PC0_EVENT
Performance Event Counter 0 Event Select Value. See individual module chapters for
performance event selections.
5.5.2.8 Performance Event Counter 1 Select MSR (PERF_SEL1_MSR)
MSR Address
Type
00000187h
R/W
Reset Value
00000000_00000000h
PERF_SEL1_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
PC1_UMASK
PC1_EVENT
PERF_SEL1_MSR Bit Descriptions
Bit
Name
Description
Reserved. Write as read.
63:16
15:8
RSVD
PC1_UMASK
Performance Event Counter 1 Unit Mask. Selects sub-events.
00h: All sub-events counted.
7:0
PC1_EVENT
Performance Event Counter 1 Event Select Value. See individual module chapters for
performance event selections.
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5.5.2.9 Instruction Fetch Configuration MSR (IF_CONFIG_MSR)
MSR Address
Type
00001100h
R/W
Reset Value
00000000_00005051h
IF_CONFG_MSR controls the operation of the Instruction Fetch (IF). The Level-0 COF cache (Change of Flow (COF)
cache), L1 COF cache, return stack, and power saving mode may be turned on or off. The WRMSR instruction can access
IF_CONFIG MSR at any time. Devices external to the CPU should issue writes to IF_CONFIG MSR only if the CPU is sus-
pended or stalled.
IF_CONFIG_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
RSVD
BSP
W_DIS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
RSVD
RSVD
RSVD
IF_CONFIG_MSR Bit Descriptions
Bit
Name
Description
Reserved.
63:48
47
RSVD
BETD
Branch Tree Messaging (BTM) Exception Type. Allow the BTM stream to contain
exception type records.
0: Enable. (Default)
1: Disable.
46
BIVD
Branch Tree Messaging Interrupt Vector. Allow the BTM stream to contain interrupt
vector records.
0: Enable. (Default)
1: Disable.
45
44
LSNPD
PSNPD
Linear Snooping.
0: Enable. (Default)
1: Disable.
Physical Snooping.
0: Enable. (Default)
1: Disable.
43:41
40:37
RSVD
BSP
Reserved.
Branch Tree Messaging Sync Period. Specifies the maximum period between BTM
synchronization records. If BSP is non-zero, the IF will insert a synchronization record
into the BTM stream whenever it sees a series of 32*BSP non-synchronization records.
(Default = 0)
36
RSVD
Reserved.
35:32
W_DIS
Branch Target Buffer (BTB) Way. Each bit is used to disable one Way of the BTB. Bit
32 = Way 0, bit 33 = Way 1, bit 34 = Way 2, and bit 35 = Way 3.
0: Enable Way. (Default)
1: Disable Way.
31:29
RSVD
Reserved.
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CPU Core Register Descriptions
IF_CONFIG_MSR Bit Descriptions (Continued)
Description
Bit
Name
28
II_NS
Instruction Pipeline (IP) Empty Mode.
0: IM Interface may make requests to Instruction Memory (IM) when the IP is not empty.
(Default)
1: IM Interface only makes requests to IM after the IP is empty.
Note: Enabling this mode reduces performance.
Reserved.
27:25
24
RSVD
CC_SER
COF Cache Serialization.
0: Allow more than one outstanding request in COF cache. (Default)
1: Allow only one request in the COF cache.
Note: Enabling COF cache serialization may reduce performance.
Reserved.
23:21
20
RSVD
RQ_SER
Request Queue Serialization.
0: Allow more than one request in the Request Queue. (Default)
1: Only one request is allowed in the Request Queue.
Note: Enabling RQ serialization reduces performance.
Reserved.
19:17
16
RSVD
II_SER
Instruction Memory Request Serialization.
0: IM requests are not serialized. (Default)
1: IM Interface waits until IM responds to a request before IM Interface issues the next
request.
Note: Enabling IM Interface serialization reduces performance.
Reserved.
15
14
RSVD
II_IMFLSH
Instruction Memory Flush.
0: IF never issues flush requests to IM.
1: IF may issue flush requests to IM. (Default)
Note: Enabling IM flushing usually increases performance.
13
12
RSVD
Reserved.
CC_L0
Level-0 COF Cache.
0: Disable.
1: Enable. (Default)
Note: Enabling the L0 COF cache increases performance. Unless CC_L1 is enabled
(bit 0 = 1), then CC_L0 has no effect.
11
10
RSVD
Reserved.
DMM_DIS
Debug Management Mode (DMM).
0: The COF cache and return stack is neither used nor updated during DMM. (Default)
1: The COF cache and return stack may be used and updated during DMM.
Note: Disabling the COF cache and return stack during DMM may reduce performance
but make debug easier.
9
8
RSVD
Reserved.
CC_PS
Power Saving Mode.
0: Disable. (Default)
1: Enable.
Note: CC_L1 must be disabled (bit 0 = 0) to enable power saving.
7
RSVD
Reserved.
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IF_CONFIG_MSR Bit Descriptions (Continued)
Description
Bit
Name
6
STRONG
Strong Prediction. Allow the IF to make strong predictions.
0: Disable.
1: Enable. (Default)
Note: Enabling strong predictions may improve performance.
5
4
RSVD
RS
Reserved.
Return Stack.
0: Disable.
1: Enable. (Default)
Note: Enabling the return stack increases performance unless CC_L1 is enabled (bit 0
= 1), then the return stack has no effect.
3
2
RSVD
Reserved.
CC_INVL
COF Cache Invalidation.
0: Translation Look-aside Buffer (TLB) invalidations do not invalidate the COF cache.
(Default)
1: Whenever the TLB is invalidated, the COF cache is also invalidated.
Note: Invalidating the COF cache whenever the TLB is invalidated may reduce perfor-
mance.
1
0
RSVD
Reserved.
CC_L1
Level-1 COF Cache.
0: Disable.
1: Enable. (Default)
Note: Enabling the L1 COF cache increases performance.
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CPU Core Register Descriptions
5.5.2.10 IF Invalidate MSR (IF_INVALIDATE_MSR)
MSR Address
Type
00001102h
W
Reset Value
00000000_00000000h
IF_INVALIDATE MSR may be used to invalidate the contents of the Tag RAMs (Level-1 COF cache), Level-0 COF cache,
and the return stack. Devices external to the CPU should issue writes to IF_INVALIDATE_MSR only if the CPU is sus-
pended or stalled.
IF_INVALIDATE_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
RS CC
IF_INVALIDATE_MSR Bit Descriptions
Bit
Name
Description
63:2
1
RSVD
RS
Reserved.
Invalidate Return Stack.
0: Do not alter the return stack. (Default)
1: Empty the return stack.
0
CC
Invalidate L0 and L1 COF Cache.
0: Do not alter the COF cache. (Default)
1: Empty the COF cache.
5.5.2.11 IF Test Address MSR (IF_TEST_ADDR_MSR)
MSR Address
Type
00001108h
R/W
Reset Value
00000000_00000000h
IF_TEST_ADDR_MSR is used to indirectly address the IF state elements, while IF_TEST_DATA_MSR (MSR 0000109h) is
used to read/write the elements. The format of the data written to, or read from IF_TEST_DATA_MSR depends on the value
in IF_TEST_ADDR MSR.
IF_TEST_ADDR_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD BLOCK
INDEX
IF_TEST_ADDR_MSR Bit Descriptions
Bit
Name
Description
Reserved.
63:13
RSVD
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IF_TEST_ADDR_MSR Bit Descriptions (Continued)
Bit
Name
Description
12:8
BLOCK
Block Identifier.
00h: Target RAM 0 (Way 0). (Default)
01h: Target RAM 1 (Way 0).
02h: Target RAM 2 (Way 0).
03h: Target RAM 3 (Way 0).
04h: Target RAM 4 (Way 1).
05h: Target RAM 5 (Way 1).
06h: Target RAM 6 (Way 1).
07h: Target RAM 7 (Way 1).
08h: Target RAM 8 (Way 2).
09h: Target RAM 9 (Way 2).
0Ah: Target RAM 10 (Way 2).
0Bh: Target RAM 11 (Way 2).
0Ch: Target RAM 12 (Way 3).
0Dh: Target RAM 13 (Way 3).
0Eh: Target RAM 14 (Way 3).
0Fh: Target RAM 15 (Way 3).
10h: Tag RAM 0 (Way 0).
11h: Tag RAM 1 (Way 1).
12h: Tag RAM 2 (Way 2).
13h: Tag RAM 3 (Way 3).
14h: L0 COF cache.
15h: Return stack.
7:0
INDEX
Block Index. (Default = 00h)
When accessing a Tag RAM or a Target RAM, the index is the address of the RAM loca-
tion (0-255).
When accessing the L0 COF cache, indexes 0-1 refer to the 2 tag entries, 4-5 refer to the
2 source addresses, 8-9 refer to the 2 target addresses, and 12-13 refer to the 2 return
addresses.
When accessing the return stack, indexes 0-7 refer to the 8 non-speculative return
addresses, indexes 8-15 refer to the IF speculative return addresses, and address 16
refers to the valid bits, indexes 17-24 refer to the ID speculative return addresses.
5.5.2.12 IF Test Data MSR (IF_TEST_DATA_MSR)
MSR Address
Type
00001109h
R/W
Reset Value
00000000_xxxxxxxxh
IF_TEST_DATA_MSR Register Map for Target RAMs
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TGT
IF_TEST_DATA_MSR Bit Descriptions for Target RAMs
Description
Bit
Name
63:32
31:0
RSVD
TGT
Reserved.
COF Target.
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IF_TEST_DATA_MSR Register Map for Tag RAMs
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
LIP RSVD STRENGTH TYPE
9
8
7
6
5
4
3
2
1
0
V
END
IF_TEST_DATA_MSR Bit Descriptions for Tag RAMs
Description
Bit
Name
63:32
31
RSVD
V
Reserved.
Tag is Valid. (Default = 0)
Linear Address Bits [19:11].
Reserved.
30:22
21:20
19:16
LIP
RSVD
STRENGTH
Prediction Strength. Bit 19 = STRENGTH3, bit 18 = STRENGTH2, bit 17 =
STRENGTH1, and bit 16 = STRENGTH0.
0: Weakly predicted.
1: Strongly predicted.
15:8
7:0
TYPE
END
COF Type. Bits [15:14] = TYPE3, bits [13:12] = TYPE2, bits [11:10] = TYPE1, and bits
[9:8] = TYPE0.
Predicted Taken COF End Markers.
IF_TEST_DATA_MSR Register Map for Level-0 COF Cache Tag
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RSVD RSVD LEN RSVD
9
8
7
6
5
4
3
2
1
0
RSVD TYPE
RSVD
IF_TEST_DATA_MSR Bit Descriptions for Level-0 COF Cache Tag
Bit
Name
Description
Reserved.
63:21
20
RSVD
PNTKN
RSVD
VLD
Predicted Not Taken. Entry ends with a predicted not-taken change of flow.
19:17
16
Reserved.
Valid. If an entry is valid, then all the tag information as well as the entry’s address and
target must also be valid. (Default = 0)
15:12
LEN
Number of Bytes. Number of bytes from address to either end of QWORD or end of pre-
dicted taken change of flow (0-8).
11:9
8
RSVD
PTKEN
RSVD
TYPE
RSVD
LRU
Reserved.
Predicted Taken. Entry ends with a predicted taken change of flow.
7:6
5:4
3:1
0
Reserved.
Change of Flow Type.
Reserved.
Next Entry. Indicates that entry is the next entry to be written. Exactly one of the four
entries should have this bit set.
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IF_TEST_DATA_MSR Register Map for Level-0 COF Cache Address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ADDR[31:0]
IF_TEST_DATA_MSR Bit Descriptions for Level-0 COF Cache Address
Bit
Name
Description
Reserved.
63:32
31:0
RSVD
ADDR[31:0]
Address Bits [31:0]. Linear address for which the entry contains data.
IF_TEST_DATA_MSR Register Map for Level-0 COF Cache Target
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TARGET[31:0]
IF_TEST_DATA_MSR Bit Descriptions for Level-0 COF Cache Target
Bit
Name
Description
Reserved.
63:32
31:0
RSVD
TARGET[31:0]
Target Bits [31:0]. If an entry is valid and contains a predicted taken change of flow,
then this is the predicted target for the change of flow.
IF_TEST_DATA_MSR Register Map for Return Stack Addresses
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ADDR[31:0]
IF_TEST_DATA_MSR Bit Descriptions for Return Stack Addresses
Bit
Name
Description
Reserved.
63:32
31:0
RSVD
ADDR[31:0]
Address Bits [31:0]. Linear address to which a Return instruction should return.
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CPU Core Register Descriptions
IF_TEST_DATA_MSR Register Map for Return Stack Valids
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
ID_SPEC_VLD
IF_SPEC_VLD[7:0]
NONSPEC_VLD[7:0]
IF_TEST_DATA_MSR Bit Descriptions for Return Stack Valids
Bit
Name
Description
Reserved.
63:24
23:16
RSVD
ID_SPEC_VLD
Valid Instruction Decode Speculative. ID speculative return stack entries that are
valid. The lease significant entry is the next to be popped from the stack. (Default = 0)
15:8
7:0
IF_SPEC_VLD
Valid Instruction Fetch Speculative. IF speculative return stack entries that are valid.
The least significant entry is the next to be popped from the stack. (Default = 0)
NONSPEC_VLD Valid Non-Speculative. Non-speculative return stack entries that are valid. The least
significant entry the next to be popped from the stack. (Default = 0)
5.5.2.13 IF Sequential Count MRS (IF_SEQCOUNT_MSR)
MSR Address
Type
00001110h
RO
Reset Value
00000000_00000000h
IF SEQCOUNT MSR is a read only MSR containing the number of sequential instructions executed since the last change of
flow. This is useful when the CPU is halted, since it helps determine the instructions executed since the last record of the
BTM stream.
IF_SEQCOUNT_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
SEQCOUNT
IF_SEQCOUNT_MSR Bit Descriptions
Bit
Name
Description
Reserved.
63:5
4:0
RSVD
SEQCOUNT
Sequential Count. Number of sequential instructions executed since the last change of
flow.
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5.5.2.14 IF Built-In Self-Test MSR (IF_BIST_MSR)
MSR Address
Type
00001140h
RO
Reset Value
00000000_00000000h
IF_BIST_MSR may be used to run built-in self-test (BIST) on the IF Tag and Target RAMs, and to get an indication of
whether the BIST run passed or failed. There are separate BIST controllers for the Tag RAM and for the Target RAMs. A
MSR read of IF_BIST_MSR causes BIST to be run.
IF_BIST_MSR can only be run when the level-1 COF cache, the level-0 COF cache, and the return stack is disabled in the
IF_CONFIG MSR. If the COF cache is enabled, reading IF_BIST_MSR does not cause BIST to be run, and returns zero.
After BIST has been run by reading IF_BIST_MSR, the contents of the IF Tag RAMs is invalidated (cleared).
IF_BIST_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
IF_BIST_MSR Bit Descriptions
Bit
Name
Description
63:2
1
RSVD
Reserved.
TGT_PASS
Target RAM BIST Status.
0: Target RAM BIST did not pass. (Default)
1: Target RAM BIST passed.
0
TAG_PASS
Tag RAM BIST Status.
0: Tag RAM BIST did not pass. (Default)
1: Tar RAM BIST passed.
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5.5.2.15 Exception Unit (XC) Configuration MSR (XC_CONFIG_MSR)
MSR Address
Type
00001210h
R/W
Reset Value
00000000_00000000h
XC_CONFIG_MSR allows the processor to be configured so that when the processor is in its HALT state, it can request
that its clocks be turned off. It also allows the processor to be configured so that the processor is suspended when a
PAUSE instruction is executed.
XC_CONFIG_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
XC_CONFIG_MSR Bit Descriptions
Bit
Name
Description
Reserved.
63:2
1
RSVD
SUSPONPAUSE
Suspend on Pause. When set, if a pause instruction is executed, the processor is sus-
pended for the number of clocks specified in the PAUSEDLY field of
BC_CONFIG0_MSR (MSR 00001900h[27:24]). (Default = 0)
0
SUSPONHLT
Suspend on Halt. When set, if the processor is halted, then it requests that its clocks
be turned off. (Default = 0)
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5.5.2.16 XC Mode MSR (XC_MODE_MSR)
MSR Address
Type
00001211h
R/W
Reset Value
00000000_00000000h
XC_MODE_MSR contains information about the current status of the processor.
XC_MODE_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
XC_MODE_MSR Bit Descriptions
Bit
Name
Description
63:16
15
RSVD (RO)
Reserved (Read Only).
DM_AC_STALL
(RO)
Data Memory Subsystem Stall Address Calculation Unit (Read Only). DM wants no
more requests from AC.
14
13
FP_STALL (RO)
Floating Point Stall (Read Only). FP is stalling the pipeline.
FP_ERROR
(RO)
Floating Point Error (Read Only). FP is reporting an error.
12
11
10
9
FP_BUSY (RO)
IP_BUSY (RO)
DM_BUSY (RO)
IF_BUSY (RO)
Floating Point Busy (Read Only). FP is reporting that it is not idle.
Instruction Pipeline Busy (Read Only). IP is reporting that it is not idle.
Data Memory Subsystem Busy (Read Only). DM is reporting that it is not idle.
Instruction Fetch Busy (Ready Only). IF is reporting that it is not idle.
8
DM_EX_DELAY
(RO)
Data Memory Subsystem Execution Delay (Read Only). Pipeline is waiting for DM to
provide instruction data.
7
6
IQ_EMPTY (RO) Instruction Queue Empty (Read Only). Instruction Queue is empty.
WAIT_FPINTR
(RO)
Wait for Floating Point Interrupt (Read Only). Processor is waiting for an external
Descriptions" on page 96). (Default = 0)
5
4
3
FLUSHING (RO) Flushing (Read Only). Processor is flushing the pipeline while waiting for DM to empty.
HALTED (RO)
Halted (Read Only). Processor is halted. (Default = 0)
SUSPENDED
(RO)
Suspended (Read Only). Processor is suspended. (Default = 0)
2
1
0
NMI_ACTIVE
DMM_ACTIVE
SMM_ACTIVE
Non-Maskable Interrupt Active. Processor is in a NMI handler. (Default = 0)
Debug Management Mode. Processor is in debug management mode. (Default = 0)
System Management Mode. Processor is in system management mode. (Default = 0)
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CPU Core Register Descriptions
5.5.2.17 XC History MSR (XC_HIST_MSR)
MSR Address
Type
00001212h
RO
Reset Value
00000000_00000000h
XC_HIST_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
TYPE11
TYPE10
TYPE9
TYPE8
TYPE7
7
TYPE6
2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
6
5
4
3
1
0
RSVD
TYPE5
TYPE4
TYPE3
TYPE2
TYPE1
TYPE0
XC_HIST_MSR Bit Descriptions
Bit
Name
Description (Note 1)
63:62
61:57
56:52
51:47
46:42
41:37
36:32
31:30
29:25
24:20
19:15
14:10
9:5
RSVD
Reserved.
TYPE11
TYPE10
TYPE9
TYPE8
TYPE7
TYPE6
RSVD
Exception Type 11.
Exception Type 10.
Exception Type 9.
Exception Type 8.
Exception Type 7.
Exception Type 6.
Reserved.
TYPE5
TYPE4
TYPE3
TYPE2
TYPE1
TYPE0
Exception Type 5.
Exception Type 4.
Exception Type 3.
Exception Type 2.
Exception Type 1.
Exception Type 0.
4:0
Table 5-14. XC_HIST_MSR Exception Types
Value Description
Value Description
Value Description
00h
Divide error
0Bh
Segment not present
16h
External system management
during I/O instruction
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
Debug
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
Stack fault
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
--
External system management
Init
External non-maskable interrupt
Breakpoint
General protection fault
Page fault
Reset
Overflow
Reserved
Internal suspend/stall
External suspend/stall
Unsuspend/unstall
Triple fault shutdown
External maskable interrupt
No exception
Bound
FPU error trap
Invalid operation code
FPU unavailable
Double fault
Alignment fault
FPU error interrupt
Internal debug management
External debug management
I/O-initiated system management
Self-modified code fault
Invalid task-state segment
--
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33234H
5.5.2.18 XC Microcode Address MSR (XC_UADDR_MSR)
MSR Address
Type
00001213h
RO
Reset Value
00000000_00000000h
XC_UADDR_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD UADDR4 UADDR3 UADDR2[11:8]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
UADDR2[7:0]
UADDR1
UADDR0
XC_UADDR_MSR Bit Descriptions
Bit
Name
Description
63:60
59:48
47:36
35:24
23:12
11:0
RSVD
Reserved.
UADDR4
UADDR3
UADDR2
UADDR1
UADDR0
Microcode Address for Exception 4.
Microcode Address for Exception 3.
Microcode Address for Exception 2.
Microcode Address for Exception 1.
Microcode Address for Exception 0. Most recent exception.
5.5.2.19 ID Configuration MSR (ID_CONFIG_MSR)
MSR Address
Type
00001250h
R/W
Reset Value
00000000_00000002h
ID_CONFIG_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
ID_CONFIG_MSR Bit Descriptions
Bit
Name
Description
63:3
2
RSVD (RO)
GPF_TR
Reserved (Read Only).
General Protection Faults on Test Register Accesses. Generate general protection
faults on accesses to Test Registers.
0: Disable. (Default)
1: Enable.
1
0
INV_3DNOW
SERIAL
Inverse 3DNow!™. Inverse AMD 3DNow!™ instructions PFRCPV and RFRSQRTV.
0: Disable.
1: Enable. (Default)
Serialize. Serialize the CPU integer pipeline by only allowing one instruction in the pipe-
line at a time.
0: Integer pipeline is not serialized. (Default)
1: Integer pipeline is serialized.
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5.5.2.20 SMM Control MSR (SMM_CTL_MSR)
MSR Address
Type
00001301h
R/W
Reset Value
00000000_00000000h
SMM_CTL_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
SMM_CTL_MSR Bit Descriptions
Bit
Name
Description
63:6
5
RSVD (RO)
SMI_EXTL
Reserved (Read Only).
Enable External ASMI Pin. Enable external asynchronous SMIs.
0: Disable.
1: Enable.
4
3
SMI_IO
Enable I/O Generated SMI. Enable SMIs caused by an I/O instruction.
0: Disable.
1: Enable.
SMI_INST
Enable SMI Instructions. Enable SMI instructions: SMINT, RSM, SVDC, RSDC,
SVLDT, RSLDT, SVTS, RSTS. If not enabled, executing an SMI instruction causes an
invalid operation fault.
0: Disable.
1: Enable.
2
1
0
SMM_NEST
SMM_SUSP
SMM_NMI
Enable SMI Nesting. Enable non-software SMIs during SMM mode.
0: Disable.
1: Enable.
Enable Suspend during SMM. Enable Suspend during SMM mode.
0: Disable.
1: Enable.
Enable Non-Maskable Interrupts during SMM. Enable NMI during SMM mode.
0: Disable.
1: Enable.
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33234H
5.5.2.21 Debug Management Interrupt (DMI) Control Register
MSR Address
Type
00001302h
R/W
Reset Value
00000000_00000000h
DMI Control Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
DMI Control Register Bit Descriptions
Bit
Name
Description
63:10
9
RSVD
Reserved. Write as read.
DMI Trap Flag.
DMI_TF
0: Disable DMI single stepping.
1: If DMI_STALL (bit 8) is 0, DMI occurs after the successful execution of each instruc-
tion. If DMI_STALL is 1, debug stall occurs after the successful execution of each
instruction.
8
7
6
5
DMI_STALL
DMM_SUSP
DMI_TSS
DMI Stall.
0: If not in DMM, DMI conditions cause DMIs.
1: DMI conditions cause a debug stall.
Enable SUSP# during DMM. Enable SUSP# during DMM mode.
0: Disable.
1: Enable.
Task Switch Debug Fault Control.
0: Task switch debug faults cause debug exceptions.
1: Task switch debug exceptions cause DMIs when not in DMM.
DMM_CACHE
Cache Control during DMM.
0: Do not change CR0 CD and NW bits when entering DMM.
1: Set CR0, CD and NW bits when entering DMM.
4
3
2
DMI_ICEBP
DMI_DBG
DMI_EXT
Enable DMIs on ICEBP (F1) Instructions.
0: Disable.
1: Enable.
Enable Replacing Debug Exceptions as DMIs.
0: Disable.
1: Enable.
Enable External TDBGI Pin. Enable DMIs caused by the TDBGI pin (ball AB2) when not
in DMM.
0: Disable.
1: Enable.
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CPU Core Register Descriptions
DMI Control Register Bit Descriptions (Continued)
Description
Bit
Name
1
DMI_GPF
DMI General Protection Faults. When enabled and not in DMM mode, allow general
protection faults to generate DMIs.
0: Disable.
1: Enable.
0
DMI_INST
DMI Instructions. Enable DMI instructions DMINT and RDM. If not enabled, executing a
DMI instruction generates an invalid operation fault.
0: Disable.
1: Enable.
5.5.2.22 Temporary MSRs
Temporary 0 MSR (TEMP0_MSR)
Temporary 2 MSR (TEMP2_MSR)
MSR Address
Type
00001310h
R/W
MSR Address
Type
00001312h
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
Reset Value
xxxxxxxx_xxxxxxxxh
Temporary 1 MSR (TEMP1_MSR)
Temporary 3 MSR (TEMP3_MSR)
MSR Address
Type
00001311h
R/W
MSR Address
Type
00001313h
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
Reset Value
xxxxxxxx_xxxxxxxxh
TEMPx_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TEMPx
TEMPx_MSR Bit Descriptions
Bit
Name
Description
63:32
31:0
RSVD
Reserved. Write as read.
TEMPx
Temporary x. Used by microcode, usually for holding operands for address calculations.
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5.5.2.23 Segment Selector/Flags MSRs
The Segment Selector/Flags MSRs provide access to the segment selector and segment flags parts of a segment register.
The contents of segment registers should be accessed using MOV or SVDC/RSDC.
ES Segment Selector/Flags Register (ES_SEL_MSR)
LDT Segment Selector/Flags Register (LDT_SEL_MSR)
MSR Address
Type
00001320h
R/W
MSR Address
Type
00001326h
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
Reset Value
xxxxxxxx_xxxxxxxxh
CS Segment Selector/Flags Register (CS_SEL_MSR)
Temp Segment Selector/Flags Register (TM_SEL_MSR)
MSR Address
Type
00001321h
R/W
MSR Address
Type
00001327h
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
Reset Value
xxxxxxxx_xxxxxxxxh
SS Segment Selector/Flags Register (SS_SEL_MSR)
TSS Segment Selector/Flags Register (TSS_SEL_MSR)
MSR Address
Type
00001322h
R/W
MSR Address
Type
00001328h
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
Reset Value
xxxxxxxx_xxxxxxxxh
DS Segment Selector/Flags Register (DS_SEL_MSR)
IDT Segment Selector/Flags Register (IDT_SEL_MSR)
MSR Address
Type
00001323h
R/W
MSR Address
Type
00001329h
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
Reset Value
xxxxxxxx_xxxxxxxxh
FS Segment Selector/Flags Register (FS_SEL_MSR)
GDT Segment Selector/Flags Register (GDT_SEL_MSR)
MSR Address
Type
00001324h
R/W
MSR Address
Type
0000132Ah
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
Reset Value
xxxxxxxx_xxxxxxxxh
GS Segment Selector/Flags Register (GS_SEL_MSR)
MSR Address
Type
00001325h
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
Segment Selector/Flags MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
G
RSVD DPL SELECTOR
P
S
X
A
TI RPL
Segment Selector/Flags MSR Bit Descriptions
Bit
Name
Description
63:32
31
RSVD
G
Reserved.
Limit Granularity Bit.
Stack Address Size / Code Default Size.
Reserved.
30
B/D
RSVD
AVL
RSVD
P
29
28
Available. Bit available for operating system use.
Reserved.
27:24
23
Present.
22:21
20
DPL
S
Descriptor Privilege Level.
Non-System Descriptor.
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CPU Core Register Descriptions
Segment Selector/Flags MSR Bit Descriptions (Continued)
Bit
Name
Description
19
18
X
Executable Non-System Segment.
Expand Down Data Segment / Conforming Code Segment.
Writable Data Segment / Readable Code Segment.
Accessed Segment.
E/C
17
W/R
16
A
15:3
2
SELECTOR
Segment Selector.
TI
Descriptor Table Indicator (LDT/GDT).
Requestor Privilege Level.
1:0
RPL
5.5.2.24 SMM Header MSR (SMM_HDR_MSR)
MSR Address
Type
0000132Bh
R/W
Reset Value
00000000_00000000h
The SMM_HDR_MSR provides access to the address register that controls where SMI data is written.
SMM_HDR_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SMM_HDR
SMM_HDR_MSR Bit Descriptions
Bit
Name
Description
63:32
31:0
RSVD
Reserved. Write as read.
SMM_HDR
SMM Header. Address that indicates where SMI data is written. SMI data is written at
lower addresses than SMM_HDR (negative offsets).
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5.5.2.25 DMM Header MSR (DMM_HDR_MSR)
MSR Address
Type
0000132Ch
R/W
Reset Value
00000000_00000000h
DMM_HDR_MSR provides access to the address register that controls where DMI data is written.
DMM_HDR_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DMM_HDR
DMM_HDR_MSR Bit Descriptions
Bit
Name
Description
63:32
31:0
RSVD
Reserved. Write as read.
DMM_HDR
DMM Header. Address that indicates where DMI data is written. DMI data is written at
lower addresses than DMM_HDR (negative offsets).
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CPU Core Register Descriptions
5.5.2.26 Segment Base/Limit MSRs
The segment base/limit MSRs provide access to the segment limit and segment base parts of a segment register. The limit
value is the true limit; it does not need to be altered based on the limit granularity bit. The contents of segment registers
should be accessed using MOV or SVDC/RSDC.
ES Segment Base/Limit MSR (ES_BASE_MSR)
Temp Segment Base/Limit MSR (TEMP_BASE_MSR)
MSR Address
Type
00001330h
R/W
MSR Address
Type
00001337h
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
Reset Value
xxxxxxxx_xxxxxxxxh
CS Segment Base/Limit MSR (CS_BASE_MSR)
TSS Segment Base/Limit MSR (TSS_BASE_MSR)
MSR Address
Type
00001331h
R/W
MSR Address
Type
00001338h
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
Reset Value
xxxxxxxx_xxxxxxxxh
SS Segment Base/Limit MSR (SS_BASE_MSR)
IDT Segment Base/Limit MSR (IDT_BASE_MSR)
MSR Address
Type
00001332h
R/W
MSR Address
Type
00001339h
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
Reset Value
xxxxxxxx_xxxxxxxxh
DS Segment Base/Limit MSR (DS_BASE_MSR)
GDT Segment Base/Limit MSR (GDT_BASE_MSR)
MSR Address
Type
00001333h
R/W
MSR Address
Type
0000133Ah
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
Reset Value
xxxxxxxx_xxxxxxxxh
FS Segment Base/Limit MSR (FS_BASE_MSR)
SMM Segment Base/Limit MSR (SMM_BASE_MSR
MSR Address
Type
00001334h
R/W
MSR Address
Type
0000133Bh
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
Reset Value
xxxxxxxx_xxxxxxxxh
GS Segment Base/Limit MSR (GS_BASE_MSR)
DMM Segment Base/ Limit MSR (DMM_BASE_MSR)
MSR Address
Type
00001335h
R/W
MSR Address
Type
0000133Ch
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
Reset Value
xxxxxxxx_xxxxxxxxh
LDT Segment Base/Limit MSR (LDT_BASE_MSR)
MSR Address
Type
00001336h
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
Segment Base/Limit MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
LIMIT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BASE
Segment Base/Limit MSR Bit Descriptions
Description
Bit
Name
63:32
31:0
LIMIT
BASE
Segment Limit.
Segment Base.
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5.5.2.27 Debug Registers 1 and 0 MSR (DR1_DR0_MSR)
MSR Address
Type
00001340h
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
DR1_DR0_MSR provides access to Debug Register 1 (DR1) and Debug Register 0 (DR0). DR0 and DR1 each contain
either an I/O port number or a linear address for use as a breakpoint. The contents of debug registers are more easily
accessed using the MOV instruction.
DR1_DR0_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
DR1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DR0
DR1_DR0_MSR Bit Descriptions
Bit
Name
Description
63:32
31:0
DR1
DR0
Breakpoint 1 I/O Port Number/Linear Address.
Breakpoint 0 I/O Port Number/Linear Address.
5.5.2.28 Debug Registers 3 and 2 MSR (DR3_DR2_MSR)
MSR Address
Type
00001341h
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
DR3/DR2_MSR provides access to Debug Register 3 (DR3) and Debug Register 2 (DR2). DR2 and DR3 each contain
either an I/O port number or a linear address for use as a breakpoint. The contents of debug registers are more easily
accessed using the MOV instruction.
DR3_DR2_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
DR3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DR2
DR2_DR3_MSR Bit Descriptions
Bit
Name
Description
63:32
31:0
DR3
DR2
Breakpoint 3 I/O Port Number/Linear Address.
Breakpoint 2 I/O Port Number/Linear Address.
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CPU Core Register Descriptions
5.5.2.29 Debug Registers 7 and 6 MSR (DR6_DR7_MSR)
MSR Address
Type
00001343h
R/W
Reset Value
00000000_FFFF0000h
DR7_DR6_MSR provides access to Debug Register 7 (DR7) and Debug Register 6 (DR6). DR6 contains status information
about debug conditions that have occurred. DR7 contains debug condition enables, types, and lengths. The contents of
debug registers are more easily accessed using the MOV instruction.
DR7_DR6_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
LEN3 TYPE3 LEN2 TYPE2 LEN1 TYPE1 LEN0 TYPE0 RSVD GD
RSVD
G3 L3 G2 L2 G1 L1 G0 L0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD (FFFFh)
BT BS BD
RSVD (FFh)
B3 B2 B1 B0
DR7_DR6_MSR Bit Descriptions
Bit
Name
Description
63:62
61:60
59:58
57:56
55:54
53:52
51:50
49:48
47:46
45
LEN3
TYPE3
LEN2
TYPE2
LEN1
TYPE1
LEN0
TYPE0
RSVD
GD
Breakpoint 3 Length.
Breakpoint 3 Type.
Breakpoint 2 Length.
Breakpoint 2 Type.
Breakpoint 1 Length.
Breakpoint 1 Type.
Breakpoint 0 Length.
Breakpoint 0 Type.
Reserved.
Enable Global Detect Faults.
Reserved.
44:40
39, 38
37, 36
35, 34
33, 32
31:16
15
RSVD
G3, L3
G2, L2
G1, L1
G0, L0
RSVD
BT
Breakpoint 3 Enables.
Breakpoint 2 Enables.
Breakpoint 1 Enables.
Breakpoint 0 Enables.
Reserved.
TSS T-Bit Trap Occured.
Single-Step Trap Occured.
Global Detect Fault Occured.
Reserved.
14
BS
13
BD
12:4
3
RSVD
B3
Breakpoint 3 Matched.
Breakpoint 2 Matched.
Breakpoint 1 Matched.
Breakpoint 0 Matched.
2
B2
1
B1
0
B0
136
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33234H
5.5.2.30 Extended Debug Registers 1 and 0 MSR (XDR1_XDR0_MSR)
MSR Address
Type
00001350h
R/W
Reset Value
00000000_00000000h
XDR1/XDR0_MSR provides access to Extended Debug Register 1 (XDR1) and Extended Debug Register 0 (XDR0). XDR0
and XDR1 each contain either an I/O port number or a linear address for use as an extended breakpoint.
XDR1_XDR0_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
XDR1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
XDR0
XDR1_XDR0_MSR Bit Descriptions
Bit
Name
Description
63:32
31:0
XDR1
XDR0
Extended Breakpoint 1 I/O Port Number/Linear Address.
Extended Breakpoint 0 I/O Port Number/Linear Address.
5.5.2.31 Extended Debug Registers 3 and 2 MSR (XDR3_XDR2_MSR)
MSR Address
Type
00001351h
R/W
Reset Value
00000000_00000000h
XDR3/XDR2_MSR provides access to Extended Debug Register 3 (XDR3) and Extended Debug Register 2 (XDR2). XDR2
and XDR3 each contain either an I/O port number or a linear address for use as an extended breakpoint.
XDR3_XDR2_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
XDR3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
XDR2
XDR3_XDR2_MSR Bit Descriptions
Bit
Name
Description
63:32
31:0
XDR3
XDR2
Extended Breakpoint 3 I/O Port Number/Linear Address.
Extended Breakpoint 2 I/O Port Number/Linear Address.
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CPU Core Register Descriptions
5.5.2.32 Extended Debug Registers 5 and 4 MSR (XDR5_XDR4_MSR)
MSR Address
Type
00001352h
R/W
Reset Value
FFFFFFFF_00000000h
XDR5/XDR4_MSR provides access to Extended Debug Register 5 (XDR5) and Extended Debug Register 4 (XDR4). XDR4
contains an opcode match value. XDR5 contains an opcode match mask.
XDR5_XDR4_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
PREFIX_MASK4
OPCODE_MASK4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PREFIX_VALUE4
OPCODE_VALUE4
PN PR PL PC PS PO PA PF
XDR5_XDR4_MSR Bit Descriptions
Bit
Name
Description
63:56
55:32
31
PREFIX_MASK4
Prefix Mask Value for Extended Breakpoint 4.
OPCODE_MASK4
Opcode Mask Value for Extended Breakpoint 4.
PN
REPNE/REPNZ Prefix Value for Extended Breakpoint 4.
REP/REPE/REPZ Prefix Value for Extended Breakpoint 4.
LOCK Prefix Value for Extended Breakpoint 4.
30
PR
29
PL
28
PC
CS Segment Override Prefix Value for Extended Breakpoint 4.
27
PS
SS/DS/ES/FS/GS Segment Override Prefix Value for Extended Breakpoint 4.
Operand Size Prefix Value for Extended Breakpoint 4.
Address Size Prefix Value for Extended Breakpoint 4.
0F or 0F 0F Prefix Value for Extended Breakpoint 4.
Opcode Match Value for Extended Breakpoint 4.
26
PO
25
PA
24
PF
23:0
OPCODE_VALUE4
5.5.2.33 Extended Debug Registers 7 and 6 MSR (XDR7_XDR6_MSR)
MSR Address
Type
00001353h
R/W
Reset Value
xxxxxxxx_xxxxxxxxh
XDR7_XDR6_MSR provides access to the extended breakpoint enables, types, lengths, and status.
XDR7_XDR6_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
LEN3 TYPE3 LEN2 TYPE2 LEN1 TYPE1 LEN0 TYPE0 RSVD E6 E5 E4 E3 E2 E1 E0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RSVD (1FFFFh) BS BI RSVD (1Fh)
9
8
7
6
5
4
3
2
1
0
B6 B5 B5 B3 B2 B1 B0
138
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XDR7_XDR6_MSR Bit Descriptions
Description
Bit
Name
63:62
61:60
59:58
57:56
55:54
53:52
51:50
49:48
47:39
38
LEN3
TYPE3
LEN2
TYPE2
LEN1
TYPE1
LEN0
TYPE0
RSVD
E6
Extended Breakpoint 3 Length.
Extended Breakpoint 3 Type.
Extended Breakpoint 2 Length.
Extended Breakpoint 2 Type.
Extended Breakpoint 1 Length.
Extended Breakpoint 1 Type.
Breakpoint 0 Length.
Breakpoint 0 Type.
Reserved.
Extended Breakpoint 6 Enable.
Extended Breakpoint 5 Enable.
Extended Breakpoint 4 Enable.
Extended Breakpoint 3 Enable.
Extended Breakpoint 2 Enable.
Extended Breakpoint 1 Enable.
Extended Breakpoint 0 Enable.
Reserved. Default = 1FFFFh.
Extended Single-Step Trap Status.
Reserved. Default = 1.
37
E5
36
E4
35
E3
34
E2
33
E1
32
E0
31:15
14
RSVD
BS
13
RSVD
BI
12
ICEBP or INT_1 Status.
11:7
6
RSVD
B6
Reserved. Default = 1Fh.
Extended Breakpoint 6 Status.
Extended Breakpoint 5 Status.
Extended Breakpoint 4 Status.
Extended Breakpoint 3 Status.
Extended Breakpoint 2 Status.
Extended Breakpoint 1 Status.
Extended Breakpoint 0 Status.
5
B5
4
B4
3
B3
2
B2
1
B1
0
B0
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CPU Core Register Descriptions
5.5.2.34 Extended Debug Registers 9 and 8 MSR (XDR9_XDR8_MSR)
MSR Address
Type
00001354h
R/W
Reset Value
FFFFFFFF_00000000h
XDR9_XDR8_MSR provides access to Extended Debug Register 9 (XDR9) and Extended Debug Register 8 (XDR8).
XDR8 contains an opcode match value. XDR9 contains an opcode match mask.
XDR9_XDR8_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
PREFIX_MASK5
OPCODE_MASK5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PREFIX_VALUE5
OPCODE_VALUE5
PN PR PL PC PS PO PA PF
XDR9_XDR8_MSR Bit Descriptions
Bit
Name
Description
63:56
55:32
31
PREFIX_MASK5
Prefix Mask Value for Extended Breakpoint 5.
OPCODE_MASK5
Opcode Mask Value for Extended Breakpoint 5.
PN
REPNE/REPNZ Prefix Value for Extended Breakpoint 5.
REP/REPE/REPZ Prefix Value for Extended Breakpoint 5.
LOCK Prefix Value for Extended Breakpoint 5.
30
PR
29
PL
28
PC
CS Segment Override Prefix Value for Extended Breakpoint 5.
27
PS
SS/DS/ES/FS/GS Segment Override Prefix Value for Extended Breakpoint 5.
Operand Size Prefix Value for Extended Breakpoint 5.
Address Size Prefix Value for Extended Breakpoint 5.
0F or 0F 0F Prefix Value for Extended Breakpoint 5.
Opcode Match Value for Extended Breakpoint 5.
26
PO
25
PA
24
PF
23:0
OPCODE_VALUE5
140
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33234H
5.5.2.35 Extended Debug Registers 11 and 10 MSR (XDR11_XDR10_MSR)
MSR Address
Type
00001355h
R/W
Reset Value
xxxxxxxx_xxxx0000h
XDR11_XDR10_MSR provides access to the extended I/O breakpoint.
XDR11_XDR10_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
IO_PORT
XDR11_XDR10_MSR Bit Descriptions
Bit
Name
Description
63:16
15:0
RSVD
Reserved. These bits are not writable.
IO_PORT
I/O Port for Extended I/O Breakpoint 6.
5.5.2.36 EX Stage Instruction Pointer MSR (EX_IP_MSR)
MSR Address
Type
00001360h
R/W
Reset Value
00000000_00000000h
EX_IP_MSR provides access to the EX stage instruction pointer (effective address).
EX_IP_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
EX_IP
EX_IP_MSR Bit Descriptions
Bit
Name
Description
63:32
31:0
RSVD
EX_IP
Reserved.
EX Stage Effective Instruction Pointer.
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CPU Core Register Descriptions
5.5.2.37 WB Stage Instruction Pointer MSR (WB_IP_MSR)
MSR Address
Type
00001361h
R/W
Reset Value
00000000_00000000h
WB_IP_MSR provides access to the WB stage instruction pointer (effective address).
WB_IP_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
WB_IP
WB_IP_MSR Bit Descriptions
Bit
Name
Description
63:32
31:0
RSVD
Reserved.
WB_IP
WB Stage Effective Instruction Pointer.
5.5.2.38 EX Stage Linear Instruction Pointer MSR (EX_LIP_MSR)
MSR Address
Type
00001364h
RO
Reset Value
00000000_00000000h
EX_LIP_MSR provides access to the EX stage linear instruction pointer.
EX_LIP_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
EX_LIP
EX_LIP_MSR Bit Descriptions
Bit
Name
Description
63:32
31:0
RSVD
Reserved.
EX_LIP
EX Stage Linear Instruction Pointer.
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5.5.2.39 WB Stage Linear Instruction Pointer MSR (WB_LIP_MSR)
MSR Address
Type
00001365h
RO
Reset Value
00000000_00000000h
WB_LIP_MSR provides access to the WB stage linear instruction pointer.
WB_LIP_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
WB_LIP
WB_LIP_MSR Bit Descriptions
Bit
Name
Description
63:32
31:0
RSVD
Reserved.
WB_LIP
WB Stage Linear Instruction Pointer.
5.5.2.40 C1/C0 Linear Instruction Pointer MSR (C1_C0_LIP_MSR)
MSR Address
Type
00001366h
RO
Reset Value
00000000_00000000h
C1_C0_LIP_MSR provides access to linear instruction pointers when the code segment was loaded.
C1_C0_LIP_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
C1_LIP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
C0_LIP
C1_C0_LIP_MSR Bit Descriptions
Bit
Name
Description
63:32
C1_LIP
CS 1 Linear Instruction Pointer. Second most recent linear instruction point when code
segment was loaded.
31:0
C0_LIP
CS 0 Linear Instruction Pointer. Most recent linear instruction point when code seg-
ment was loaded.
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CPU Core Register Descriptions
5.5.2.41 C3/C2 Linear Instruction Pointer MSR (C3_C2_LIP_MSR)
MSR Address
Type
00001367h
RO
Reset Value
00000000_00000000h
C3_C2_LIP_MSR provides access to linear instruction pointers when the code segment was loaded.
C3_C2_LIP_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
C3_LIP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
C2_LIP
C3_C2_LIP_MSR Bit Descriptions
Bit
Name
Description
63:32
C3_LIP
CS 3 Linear Instruction Pointer. Fourth most recent linear instruction point when code
segment was loaded.
31:0
C2_LIP
CS 2 Linear Instruction Pointer. Third most recent linear instruction point when code
segment was loaded.
5.5.2.42 Floating Point Environment Code Segment (FPENV_CS_MSR)
MSR Address
Type
00001370h
R/W
Reset Value
00000000_00000000h
FPENV_CS_MSR provides access to the floating point (FP) environment code segment. Software better accesses the
floating point environment data using the FLDENV/FSTENV and FSAVE/FRSTOR instructions.
FPENV_CS_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
CS
FPENV_CS_MSR Bit Descriptions
Bit
Name
Description
Reserved.
63:16
15:0
RSVD
CS
Code Segment. Selector of code segment of last FP instruction that may have caused
an FP error.
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5.5.2.43 Floating Point Environment Instruction Pointer (FPENV_IP_MSR)
MSR Address
Type
00001371h
R/W
Reset Value
00000000_00000000h
FPENV_IP_MSR provides access to the floating point (FP) environment instruction pointer. Software better accesses the
floating point environment data using the FLDENV/FSTENV and FSAVE/FRSTOR instructions.
FPENV_IP_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
IP
FPENV_IP_MSR Bit Descriptions
Bit
Name
Description
Reserved.
63:32
31:0
RSVD
IP
Instruction Pointer. Effective address of last FP instruction that may have caused an FP
error.
5.5.2.44 Floating Point Environment Data Segment (FPENV_DS_MSR)
MSR Address
Type
00001372h
R/W
Reset Value
00000000_00000000h
FPENV_DS_MSR provides access to the floating point (FP) environment data segment. Software better accesses the float-
ing point environment data using the FLDENV/FSTENV and FSAVE/FRSTOR instructions.
FPENV_DS_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
DS
FPENV_DS_MSR Bit Descriptions
Bit
Name
Description
Reserved.
63:16
15:0
RSVD
DS
Data Segment. Selector of data segment of memory operand of last FP instruction that
may have caused an FP error.
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CPU Core Register Descriptions
5.5.2.45 Floating Point Environment Data Pointer (FPENV_DP_MSR)
MSR Address
Type
00001373h
R/W
Reset Value
00000000_00000000h
FPENV_DP_MSR provides access to the floating point (FP) environment data pointer. Software better accesses the float-
ing point environment data using the FLDENV/FSTENV and FSAVE/FRSTOR instructions.
FPENV_DP_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DP
FPENV_DP_MSR Bit Descriptions
Bit
Name
Description
Reserved.
63:32
31:0
RSVD
DP
Data Pointer. Effective address of memory operand of last FP instruction that may have
caused an FP error.
5.5.2.46 Floating Point Environment Opcode Pointer (FPENV_OP_MSR)
MSR Address
Type
00001374h
R/W
Reset Value
00000000_00000000h
FPENV_OP_MSR provides access to the floating point (FP) environment opcode. Software better accesses the floating
point environment opcode using the FLDENV/FSTENV and FRSTOR/FSAVE instructions.
FPENV_OP_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
OP
FPENV_OP_MSR Bit Descriptions
Bit
Name
Description
Reserved.
63:11
10:0
RSVD
OP
Opcode Pointer. Opcode of last FP instruction executed that may have caused an FP
error.
146
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33234H
5.5.2.47 Address Calculation Unit Configuration MSR (AC_CONFIG_MSR)
MSR Address
Type
00001380h
RO
Reset Value
00000000_00000000h
AC_CONFIG_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RSVD
AC_CONFIG_MSR Bit Descriptions
Bit
Name
Description
Reserved.
63:1
0
RSVD
LOCK_EN
Lock Enable. Allow Address Calculation Unit (AC) to issue locked requests to Data
Memory Subsystem (DM).
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