INTEGRATED CIRCUITS
DATA SHEET
UDA1325
Universal Serial Bus (USB) CODEC
1999 May 10
Preliminary specification
File under Integrated Circuits, IC01
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
All I2S inputs and I2S outputs support standard I2S-bus
format and the LSB justified serial data format with word
lengths of 16, 18 and 20 bits.
APPLICATIONS
• USB monitors
• USB speakers
Via the digital I/O module with its I2S input and output, an
external DSP can be used for adding extra sound
processing features for the audio playback channel.
• USB microphones
• USB headsets
• USB telephone/answering machines
• USB links in consumer audio devices.
The microcontroller is responsible for handling the
high-level USB protocols, translating the incoming control
requests and managing the user interface via general
purpose pins and an I2C-bus.
GENERAL DESCRIPTION
The ADAC enables the wide and continuous range of
playback sampling frequencies. By means of a Sample
Frequency Generator (SFG), the ADAC is able to
reconstruct the average sample frequency from the
incoming audio samples. The ADAC also performs the
playback sound processing. The ADAC consists of a
FIFO, an unique audio feature processing DSP, the SFG,
digital filters, a variable hold register, a Noise Shaper (NS)
and a Filter Stream DAC (FSDAC) with line output drivers.
The audio information is applied to the ADAC via the USB
processor or via the digital I2S input of the digital I/O
module.
The UDA1325 is a single chip stereo USB codec
incorporating bitstream converters designed for
implementation in USB-compliant audio peripherals and
multimedia audio applications. It contains a USB interface,
an embedded microcontroller, an Analog-to-Digital
Interface (ADIF) and an Asynchronous Digital-to-Analog
Converter (ADAC).
The USB interface consists of an analog front-end and a
USB processor. The analog front-end transforms the
differential USB data into a digital data stream. The USB
processor buffers the incoming and outgoing data from the
analog front-end and handles all low-level USB protocols.
The USB processor selects the relevant data from the
universal serial bus, performs an extensive error detection
and separates control information and audio information.
The control information is made accessible to the
microcontroller. At playback, the audio information
becomes available at the digital I2S output of the digital I/O
module or is fed directly to the ADAC. At recording, the
audio information is delivered by the ADIF or by the digital
I2S input of the I2S-bus interface.
The ADIF consists of an Programmable Gain Amplifier
(PGA), an Analog-to-Digital Converter (ADC) and a
Decimator Filter (DF). An Analog Phase Lock Loop (APLL)
or oscillator is used for creating the clock signal of the
ADIF. The clock frequency for the ADIF can be controlled
via the microcontroller. Several clock frequencies are
possible for sampling the analog input signal at different
sampling rates.
The wide dynamic range of the bitstream conversion
technique used in the UDA1325 for both the playback and
recording channel guarantees a high audio sound quality.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
UDA1325PS
UDA1325H
SDIP42
QFP64
plastic shrink dual in-line package; 42 leads (600 mil)
SOT270-1
SOT319-2
plastic quad flat package; 64 leads (lead length 1.95 mm);
body 14 × 20 × 2.8 mm
1999 May 10
3
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
QUICK REFERENCE DATA
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDE
supply voltage periphery
supply voltage core
total supply current
4.75
5.0
5.25
3.6
tbf
V
VDDI
3.0
−
−
3.3
60
V
IDD(tot)
IDD(tot)(ps)
mA
µA
total supply current in power-saving note 1
mode
360
−
Dynamic performance DAC
(THD + N)/S total harmonic distortion plus
noise-to-signal ratio
fs = 44.1 kHz; RL = 5 kΩ
fi = 1 kHz (0 dB)
−
−
−
−
−90
0.0032 0.01
−80
dB
%
fi = 1 kHz (−60 dB)
−30
3.2
95
−20
10
−
dB
%
S/N
signal-to-noise ratio at bipolar zero A-weighted at code 0000H 90
dBA
V
Vo(FS)(rms)
full-scale output voltage
(RMS value)
VDD = 3.3 V
−
0.66
−
Dynamic performance PGA and ADC
(THD + N)/S total harmonic distortion plus
noise-to-signal ratio
fs = 44.1 kHz;
PGA gain = 0 dB
fi = 1 kHz; (0 dB);
Vi = 1.0 V (RMS)
−
−
−85
0.0056 0.01
−80
dB
%
fi = 1 kHz (−60 dB)
−
−
−30
3.2
95
−20
10.0
−
dB
%
S/N
signal-to-noise ratio
Vi = 0.0 V
90
dBA
General characteristics
fi(s)
audio input sample frequency
operating ambient temperature
5
0
−
25
55
70
kHz
Tamb
°C
Note
1. Exclusive the IDDE current which depends on the components connected to the I/O pins.
1999 May 10
4
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
BLOCK DIAGRAM
P0.7 to P0.0
P2.0 to P2.7
CLK
27
D+
D−
8 (9)
6 (8)
7, 5, 3, 64,
62, 60, 58, 56
14, 16, 18, 20,
22, 23, 29, 30
V
V
V
V
V
V
V
V
V
V
(10) 9
(11) 10
(12) 11
(13) 12
(23) 32
(24) 33
(29) 38
(30) 39
(33) 42
(35) 44
DDI
SSI
V
24 (19)
SSX
SSE
XTAL1b 25 (20)
XTAL2b 26 (21)
ANALOG FRONT-END
USB-PROCESSOR
OSC
48 MHz
DDE
DDO
SSO
DDA1
SSA1
DDA2
SSA2
TIMING
V
28 (22)
52 (39)
53 (40)
DDX
V
DDA3
XTAL2a
OSC
ADC
ANALOG
PLL
XTAL1a 54 (41)
V
55 (42)
SSA3
GP2/DO 63 (4)
GP3/WSO 1 (5)
GP4/BCKO 2 (6)
GP1/DI 13 (14)
DIGITAL I/O
(17) 19 SCL
(18) 21 SDA
GP0/BCKI 17 (16)
GP5/WSI 15 (15)
MICRO-
CONTROLLER
PSEN 31
MUX
FIFO
DA 57 (1)
WS 59 (2)
BCK 61 (3)
SAMPLE
FREQUENCY
GENERATOR
AUDIO FEATURE
PROCESSING DSP
2
I S-BUS
INTERFACE
DECIMATOR
FILTER
(7) 4 SHTCB
(26) 35 TC
UPSAMPLE FILTERS
VARIABLE HOLD REGISTER
3rd-ORDER NOISE SHAPER
TEST
CONTROL
BLOCK
EA 48
ALE 50
(27) 36 RTCB
VINL 43 (34)
VINR 47 (36)
LEFT
Σ∆ ADC
PGA
PGA
UDA1325
LEFT
DAC
−
+
(25) 34 VOUTL
(28) 37 VOUTR
RIGHT
Σ∆ ADC
+
−
RIGHT
DAC
REFERENCE VOLTAGE
VRN 49 (37)
VRP 51 (38)
45, 46
n.c.
41 (32)
40 (31)
V
V
MGM108
ref(AD)
ref(DA)
The pin numbers given in parenthesis refer to the SDIP42 version.
Fig.1 Block diagram (QFP64 package).
5
1999 May 10
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
PINNING
PIN
PIN
SYMBOL
I/O
DESCRIPTION
QFP64 SDIP42
GP3/WSO
GP4/BCKO
P0.5
1
2
3
4
5
6
5
6
−
7
−
8
I/O
I/O
I/O
I
general purpose pin 3 or word select output
general purpose pin 4 or bit clock output
Port 0.5 of the microcontroller
SHTCB
P0.6
shift clock of the test control block (active HIGH)
Port 0.6 of the microcontroller
I/O
I/O
D−
negative data line of the differential data bus, conforms to the USB
standard
P0.7
D+
7
8
−
9
I/O
I/O
Port 0.7 of the microcontroller
positive data line of the differential data bus, conforms to the USB
standard
VDDI
9
10
11
12
13
14
−
15
−
16
−
−
−
−
digital supply voltage for core
digital ground for core
VSSI
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
VSSE
digital ground for I/O pads
VDDE
−
digital supply voltage for I/O pads
general purpose pin 1 or data input
Port 2.0 of the microcontroller
general purpose pin 5 or word select input
Port 2.1 of the microcontroller
general purpose pin 0 or bit clock input
Port 2.2 of the microcontroller
serial clock line I2C-bus
GP1/DI
P2.0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
−
GP5/WSI
P2.1
GP0/BCKI
P2.2
SCL
17
−
18
−
P2.3
Port 2.3 of the microcontroller
serial data line I2C-bus
SDA
P2.4
Port 2.4 of the microcontroller
Port 2.5 of the microcontroller
crystal oscillator ground (48 MHz)
crystal input (analog; 48 MHz)
crystal output (analog; 48 MHz)
48 MHz clock output signal
P2.5
−
VSSX
19
20
21
−
22
−
XTAL1b
XTAL2b
CLK
I
O
O
VDDX
−
supply crystal oscillator (48 MHz)
Port 2.6 of the microcontroller
Port 2.7 of the microcontroller
program store enable (active LOW)
supply voltage for operational amplifier
operational amplifier ground
P2.6
I/O
I/O
I/O
−
−
O
P2.7
−
−
PSEN
VDDO
VSSO
23
24
25
26
27
28
VOUTL
TC
voltage output left channel
I
test control input (active HIGH)
asynchronous reset input of the test control block (active HIGH)
voltage output right channel
RTCB
VOUTR
I
O
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
PIN
PIN
SYMBOL
VDDA1
I/O
DESCRIPTION
QFP64 SDIP42
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
29
30
31
32
33
34
35
−
−
36
−
37
−
38
39
40
41
42
−
−
−
O
O
−
I
analog supply voltage 1
analog ground 1
VSSA1
Vref(DA)
Vref(AD)
VDDA2
VINL
VSSA2
n.c.
reference voltage output DAC
reference voltage output ADC
analog supply voltage 2
input signal left channel PGA
analog ground 2
−
−
−
I
not connected
n.c.
not connected
VINR
EA
input signal right channel PGA
external access (active LOW)
negative reference input voltage ADC
address latch enable (active HIGH)
positive reference input voltage ADC
−
I
VRN
ALE
−
I
VRP
VDDA3
XTAL2a
XTAL1a
VSSA3
P0.0
−
O
I
supply voltage for crystal oscillator and analog PLL
crystal output (analog; ADC)
crystal input (analog; ADC)
−
I/O
I
crystal oscillator and analog PLL ground
Port 0.0 of the microcontroller
data Input (digital)
DA
1
P0.1
−
2
I/O
I
Port 0.1 of the microcontroller
word select Input (digital)
WS
P0.2
−
3
I/O
I
Port 0.2 of the microcontroller
bit clock Input (digital)
BCK
P0.3
−
4
I/O
I/O
I/O
Port 0.3 of the microcontroller
general purpose pin 2 or data output
Port 0.4 of the microcontroller
GP2/DO
P0.4
−
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
GP3/WSO
GP4/BCKO
P0.5
1
2
51 VRP
50 ALE
49 VRN
48 EA
3
SHTCB
P0.6
4
5
47 VINR
46 n.c.
45 n.c.
44 V
D−
6
P0.7
7
D+
8
SSA2
V
9
43 VINL
42 V
DDI
V
10
11
12
UDA1325H
SSI
DDA2
V
41 V
40 V
39 V
38 V
SSE
ref(AD)
V
DDE
ref(DA)
SSA1
GP1/DI 13
P2.0 14
DDA1
GP5/WSI 15
P2.1 16
37 VOUTR
36 RTCB
35 TC
GP0/BCKI 17
P2.2 18
34 VOUTL
SCL 19
33 V
SSO
MGL349
Fig.2 Pin configuration (QFP64 package).
8
1999 May 10
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
FUNCTIONAL DESCRIPTION
The Universal Serial Bus (USB)
Data and power is transferred via the USB over a 4-wire
cable. The signalling occurs over two wires and
point-to-point segments. The signals on each segment are
differentially driven into a cable of 90 Ω intrinsic
impedance. The differential receiver features input
sensitivity of at least 200 mV and sufficient common mode
rejection.
handbook, halfpage
V
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
DA
WS
SSA3
The analog front-end
XTAL1a
XTAL2a
The analog front-end is an on-chip generic USB
3
BCK
transceiver. It is designed to allow voltage levels up to VDD
from standard or programmable logic to interface with the
physical layer of the USB. It is capable of receiving and
transmitting serial data at full speed (12 Mbits/s).
V
4
GP2/DO
GP3/WSO
GP4/BCKO
SHTCB
D−
DDA3
5
VRP
VRN
VINR
6
7
The USB processor
V
8
SSA2
The USB processor forms the interface between the
analog front-end, the ADIF, the ADAC and the
microcontroller. The USB processor consists of:
9
D+
VINL
V
V
10
11
12
13
14
15
16
17
18
19
20
21
DDI
DDA2
• A bit clock recovery circuit
V
V
UDA1325
SSI
ref(AD)
• The Philips Serial Interface Engine (PSIE)
• The Memory Management Unit (MMU)
• The Audio Sample Redistribution (ASR) module.
V
V
SSE
ref(DA)
V
V
DDE
SSA1
V
GP1/DI
GP5/WSI
GP0/BCKI
SCL
DDA1
Bit clock recovery
VOUTR
RTCB
TC
The bit clock recovery circuit recovers the clock from the
incoming USB data stream using four times over-sampling
principle. It is able to track jitter and frequency drift
specified by the USB specification.
SDA
VOUTL
V
V
SSX
SSO
Philips Serial Interface Engine (PSIE)
V
XTAL1b
XTAL2b
DDO
The Philips SIE implements the full USB protocol layer.
It translates the electrical USB signals into data bytes and
control signals. Depending upon the USB device address
and the USB endpoint address, the USB data is directed
to the correct endpoint buffer. The data transfer could be
of bulk, isochronous, control or interrupt type.
V
DDX
MGM106
The functions of the PSIE include: synchronization pattern
recognition, parallel/serial conversion, bit
stuffing/de-stuffing, CRC checking/generation, PID
verification/generation, address recognition and
handshake evaluation/generation.
The amount of bytes/packet on all endpoints is limited by
the PSIE hardware to 8 bytes/packet, except for both
isochronous endpoints (336 bytes/packet).
Fig.3 Pin configuration (SDIP42 package).
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Memory Management Unit (MMU) and integrated RAM The Analog-to-Digital Interface (ADIF)
The MMU and integrated RAM handle the temporary data
storage of all USB packets that are received or sent over
the bus.
The ADIF is used for sampling an analog input signal from
a microphone or line input and sending the audio samples
to the USB interface. The ADIF consists of a stereo
Programmable Gain Amplifier (PGA), a stereo
Analog-to-Digital Converter (ADC) and Decimation Filters
(DFs). The sample frequency of the ADC is determined by
the ADC clock (see Section “The clock source of the
analog-to-digital interface”). The user can also select a
digital serial input instead of an analog input. In this event
the sample frequency is determined by the continuous WS
The MMU and integrated RAM handle the differences
between data rate of the USB and the application allowing
the microcontroller to read and write USB packets at its
own speed.
The audio data is transferred via an isochronous data sink
endpoint or source endpoint and is stored directly into the
RAM. Consequently, no handshaking mechanism is used. clock with a range between 5 to 55 kHz. Digital serial input
is possible with four formats (I2S-bus, 16, 18 or 20 bits
LSB-justified).
Audio Sample Redistribution (ASR)
The ASR reads the audio samples from the MMU and
integrated RAM and distributes these samples equidistant
over a 1 ms frame period. The distributed audio samples
are translated by the digital I/O module to standard I2S-bus
format or 16, 18 or 20 bits LSB-justified I2S-bus format.
The ASR generates the bit clock output (BCKO) and the
Word Select Output signal (WSO) of the I2S output.
Programmable Gain Amplifier circuit (PGA)
This circuit can be used for a microphone or line input.
The input audio signals can be amplified by seven different
gains (−3 dB, 0 dB, 3 dB, 9 dB, 15 dB, 21 dB and 27 dB).
The gain settings are given in Table 17.
The Analog-to-Digital Converter (ADC)
The 80C51 microcontroller
The stereo ADC of the UDA1325 consists of two 3rd-order
Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The oversampling ratio is 128.
Both ADCs can be switched off in power saving mode (left
and right separate). The ADC clock is generated by the
analog PLL or the ADC oscillator.
The microcontroller receives the control information
selected from the USB by the USB processor. It can be
used for handling the high-level USB protocols and the
user interfaces. The microcontroller does not handle the
audio stream.
The major task of the software process that is mapped
upon the microcontroller, is to control the different modules
of the UDA1325 in such a way that it behaves as a USB
device.
The Decimation Filter (DF)
The decimator filter converts the audio data from 128fs
down to 1fs with a word width of 8, 16 or 24 bits. This data
can be transmitted over the USB as mono or stereo in
1, 2 or 3 bytes/sample. The decimator filters are clocked
by the ADC clock.
The embedded 80C51 microcontroller is compatible with
the 80C51 family of microcontrollers described in the
80C51 family single-chip 8-bit microcontrollers of “Data
Handbook IC20”, which should be read in conjunction with
this data sheet.
The internal ROM size is 12 kbyte. The internal RAM size
is 256 byte. A Watchdog Timer is not integrated.
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
The clock source of the analog-to-digital interface
The clock source of the ADIF is the analog PLL or the ADC oscillator. The preferred clock source can be selected.
The ADC clock used for the ADC and decimation filters is obtained by dividing the clock signal coming from the analog
PLL or from the ADC oscillator by a factor Q.
Using the analog PLL the user can select 3 basic APLL clock frequencies (see Table 1).
By connecting the appropriate crystal the user can choose any clock signal between 8.192 and 14.08 MHz via the ADC
oscillator.
Table 1 The analog PLL clock output frequencies
APLL CLOCK
FCODE (1 AND 0)
FREQUENCY (MHz)
00
01
10
11
11.2896
8.1920
12.2880
11.2896
The dividing factor Q can be selected via the microcontroller. With this dividing factor Q the user can select a range of
ADC clock signals allowing several different sample frequencies (see Table 2).
Table 2 ADC clock frequencies and sample frequencies based upon using the APLL as a clock source
APLL CLOCK
DIVIDE FACTOR Q ADC CLOCK FREQUENCY (MHz) SAMPLE FREQUENCY (kHz)
FREQUENCY (MHz)
8.1920
11.2896
12.2880
1
2
4
8
1
2
4
8
1
2
4
8
4.096
2.048
32
16
1.024
8
0.512 (not supported)
5.6448
4 (not supported)
44.1
22.05
11.025
5.5125
48
2.8224
1.4112
0.7056
6.144
3.072
24
1.536
12
0.768
6
Table 3 ADC clock frequencies and sample frequencies based upon using the OSCAD as a clock source
OSCAD CLOCK
DIVIDE FACTOR Q ADC CLOCK FREQUENCY (MHz) SAMPLE FREQUENCY (kHz)
FREQUENCY (MHz)
(1)
fosc
Q(2)
fosc/(2Q)
fosc/(256Q)(3)
Notes
1. The oscillator frequency (and therefore the crystal) of OSCAD must be between 8.192 and 14.08 MHz.
2. The Q factor can be 1, 2, 4 or 8.
3. Sample frequencies below 5 kHz and above 55 kHz are not supported.
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
The Asynchronous Digital-to-Analog Converter
(ADAC)
Table 4 Frequency domains for audio processing by the
DSP
The ADAC receives audio data from the USB processor or
from the digital I/O-bus. The ADAC is able to reconstruct
the sample clock from the rate at which the audio samples
arrive and handles the audio sound processing. After the
processing, the audio signal is upsampled, noise-shaped
and converted to analog output voltages capable of driving
a line output.
DOMAIN
SAMPLE FREQUENCY (kHz)
1
2
3
4
5 to 12
12 to 25
25 to 40
40 to 55
The upsampling filters and variable hold function
The ADAC consists of:
• A Sample Frequency Generator (SFG)
• FIFO registers
After the audio feature processing DSP two upsampling
filters and a variable hold function increase the
oversampling rate to 128fs.
• An audio feature processing DSP
• Two digital upsampling filters and a variable hold
register
The noise shaper
A 3rd-order noise shaper converts the oversampled data
to a noise-shaped bitstream for the FSDAC. The in-band
quantization noise is shifted to frequencies well above the
audio band.
• A digital Noise Shaper (NS)
• A Filter Stream DAC (FSDAC) with integrated filter and
line output drivers.
The Sample Frequency Generator (SFG)
The Filter Stream DAC (FSDAC)
The SFG controls the timing signals for the asynchronous
digital-to-analog conversion. By means of a digital PLL,
the SFG automatically recovers the applied sampling
frequency and generates the accurate timing signals for
the audio feature processing DSP and the upsampling
filters.
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post filter is not needed
because of the inherent filter function of the DAC.
On-board amplifiers convert the FSDAC output current to
an output voltage signal capable of driving a line output.
The lock time of the digital PLL can be chosen (see
Table 8). While the digital PLL is not in lock, the ADAC is
muted. As soon as the digital PLL is in lock, the mute is
released as described in Section “Soft mute control”.
First-In First-Out (FIFO) registers
The FIFO registers are used to store the audio samples
temporarily coming from the USB processor or from the
digital I/O input. The use of a FIFO (in conjunction with the
SFG) is necessary to remove all jitter present on the
incoming audio signal.
The sound processing DSP
A DSP processes the sound features. The control and
mapping of the sound features is explained in Section
“Controlling the playback features of the ADAC”.
Depending on the sampling rate (fs) the DSP knows four
frequency domains in which the treble and bass are
regulated. The domain is chosen automatically.
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
USB ENDPOINT DESCRIPTION
The UDA1325 has following six endpoints:
• USB control endpoint 0
• USB control endpoint 1
• USB status interrupt endpoint 1
• USB status interrupt endpoint 2
• Isochronous data sink endpoint
• Isochronous data source endpoint.
Table 5 Endpoint description
ENDPOINT
NUMBER
ENDPOINT
INDEX
MAX. PACKET
SIZE (BYTES)
ENDPOINT TYPE
control (default)
DIRECTION
0
1
0
1
2
3
4
5
6
7
out
in
8
8
8
8
8
8
control
out
in
2
3
4
5
interrupt
in
interrupt
in
isochronous out
isochronous in
out
in
336
336
CONTROLLING THE PLAYBACK FEATURES
Controlling the playback features of the ADAC
The exchange of control information between the microcontroller and the ADAC is accomplished through a serial
hardware interface comprising the following pins:
L3_DATA: microcontroller interface data line
L3_MODE: microcontroller interface mode line
L3_CLK: microcontroller interface clock line.
See also the description of Port 3 of the 80C51 microcontroller.
Information transfer through the microcontroller bus is organized in accordance with the so-called ‘L3’ format, in which
two different modes of operation can be distinguished; address mode and data transfer mode.
The address mode is required to select a device communicating via the L3-bus and to define the destination registers
for the data transfer mode. Data transfer for the UDA1325 can only be in one direction, from microcontroller to ADAC to
program its sound processing features and other functional features.
ADDRESS MODE
The address mode is used to select a device (in this case the ADAC) for subsequent data transfer and to define the
destination registers. The address mode is characterized by L3_MODE being LOW and a burst of 8 pulses on L3_CLK,
accompanied by 8 data bits on L3_DATA. Data bits 0 and 1 indicate the type of the subsequent data transfer as shown
in Table 6.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Table 6 Selection of data transfer type
BIT1
BIT0
DATA TRANSFER TYPE
0
0
1
1
0
1
0
1
audio feature registers (volume left, volume right, bass and treble)
not used
control registers
not used
Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the ADAC
is 000101 (bits 7 to 2). In the event that the ADAC receives a different address, it will deselect its microcontroller interface
logic.
DATA TRANSFER MODE
The selection preformed in the address mode remains active during subsequent data transfers, until the ADAC receives
a new address command. The data transfer mode is characterized by L3_MODE being HIGH and a burst of 8 pulses on
L3_CLK, accompanied by 8 data bits. All transfers are bitwise, i.e. they are based on groups of 8 bits. Data will be stored
in the ADAC after the eight bit of a byte has been received. The principle of a multibyte transfer is illustrated in the figure
below.
t
halt
n
L3MODE
L3CLOCK
L3DATA
MGD018
address
data byte #1
data byte #2
address
PROGRAMMING THE SOUND PROCESSING AND OTHER FEATURES
The sound processing and other feature values are stored in independent registers. The first selection of the registers is
achieved by the choice of data transfer type. This is performed in the address mode, bits 1 and 0 (see Table 6).
The second selection is performed by bit 7 and/or bit 6 of the data byte depending of the selected data transfer type.
Data transfer type ‘audio feature registers’
When the data transfer type ‘audio feature registers’ is selected 4 audio feature registers can be selected depending on
bits 7 and 6 of the data byte (see Table 7).
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Table 7 ADAC audio feature registers
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
REGISTER
0
0
1
1
0
1
0
1
VR5
VL5
X
VR4
VL4
BB4
TR4
VR3
VL3
BB3
TR3
VR2
VL2
BB2
TR2
VR1
VL1
BB1
TR1
VR0
VL0
BB0
TR0
volume right
volume left
bass
X
treble
The sequence for controlling the ADAC audio feature registers via the L3-bus is given in the figure below.
DATA_TRANSFER_TYPE
DEVICE ADDRESS = $5
d
(L3_MODE = LOW)
L3_DATA
0
0
1
0
1
0
0
0
bit 0
bit 7
LEFT VOLUME; TREBLE
RIGHT VOLUME; BASS
REGISTER
ADDRESS
(L3_MODE = HIGH)
L3_DATA
X
X
X
X
X
X
X
X
bit 0
bit 7
L3_CLK
MGS270
Data transfer type ‘control registers’
When the data transfer type ‘control registers’ is selected 2 general control registers can be selected depending on bit 7
of the data byte (see Table 7).
The sequence for controlling the ADAC control registers via the L3-bus is given in the figure below.
DATA_TRANSFER_TYPE
DEVICE ADDRESS = $5
d
(L3_MODE = LOW)
L3_DATA
0
1
1
0
1
0
0
0
bit 0
bit 7
REGISTER
ADDRESS
DATA OF THE CONTROL REGISTER
(L3_MODE = HIGH)
L3_DATA
X
X
X
X
X
X
X
X
bit 0
bit 7
L3_CLK
MGS269
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Table 8 ADAC general control registers
REGISTER
BIT
DESCRIPTION
reset ADAC
VALUE
COMMENT
Control register 0
0
0 = not reset
1 = reset
1
2
3
4
soft mute control
0 = not muted
1 = mutes
synchronous/asynchronous
channel manipulation
de-emphasis
0 = asynchronous
1 = synchronous
select 0
0 = L -> L, R -> R
1 = L -> R, R -> L
0 = de-emphasis off
1 = de-emphasis on
6 and 5 audio mode
00 = flat mode
01 = min. mode
10 = min. mode
11 = max. mode
7
selecting bit
0
Control register 1
1 and 0 serial I2S-bus input format
00 = I2S-bus
01 = 16-bit LSB justified
10 = 18-bit LSB justified
11 = 20-bit LSB justified
3 and 2 digital PLL mode
00 = adaptive
01 = fix state 1
10 = fix state 2
11 = fix state 3
select 00
4
digital PLL lock mode
0 = adaptive
1 = fixed
select 1
6 and 5 digital PLL lock speed
00 = lock after 512 samples
select 00
01 = lock after 2048 samples
10 = lock after 4096 samples
11 = lock after 16348 samples
7
selecting bit
1
Soft mute control
When the mute (bit 1 of control register 0) is active for the playback channel, the value of the sample is decreased
smoothly to zero following a raised cosine curve. There are 32 coefficients used to step down the value of the data, each
one being used 32 times before stepping to the next. This amounts to a mute transition of 23 ms at fs = 44.1 kHz. When
the mute is released, the samples are returned to the full level again following a raised cosine curve with the same
coefficients being used in reversed order.
The mute, on the master channel is synchronized to the sample clock, so that operation always takes place on complete
samples.
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Volume control
The volume of the UDA1325 can be controlled from 0 dB down to −60 dB (in steps of 1 dB). Below −60 dB the audio
signal is muted (−∞ dB). The setting of 0 dB is always referenced to the maximum available volume setting. Independant
volume control of the left and right channel is possible (balance control).
Table 9 Volume settings right playback channel
VR5
VR4
VR3
VR2
VR1
VR0
VOLUME (dB)
0
0
0
0
0
...
1
1
1
1
0
0
0
0
0
...
1
1
1
1
0
0
0
0
0
...
1
1
1
1
0
0
0
0
1
...
1
1
1
1
0
0
1
1
0
...
0
0
1
1
0
1
0
1
0
...
0
1
0
1
0
0
−1
−2
−3
...
−59
−60
−∞
−∞
Table 10 Volume settings left playback channel
VL5
VL4
VL3
VL2
VL1
VL0
VOLUME (dB)
0
0
0
0
0
...
1
1
1
1
0
0
0
0
0
...
1
1
1
1
0
0
0
0
0
...
1
1
1
1
0
0
0
0
1
...
1
1
1
1
0
0
1
1
0
...
0
0
1
1
0
1
0
1
0
...
0
1
0
1
0
0
−1
−2
−3
...
−59
−60
−∞
−∞
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Treble control
For the playback channel, treble can be regulated in three audio modes: minimum, flat and maximum mode. In flat mode
the audio is not influenced. In minimum and maximum mode, the treble range is from 0 to 6 dB in steps of 2 dB.
The programmable treble filter is implemented digitally and has a fixed corner frequency of 3000 Hz for the minimum
mode and 1500 Hz for the maximum mode. Because of the exceptional amount of programmable gain, treble should be
used with adequate prior attenuation, using volume control.
Table 11 Treble settings
TREBLE (dB)
TR4
TR3
TR2
TR1
TR0
FLAT SET
MIN. SET
MAX. SET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
...
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
...
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
...
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
...
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
...
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
2
2
4
4
4
4
6
6
6
6
6
6
0
0
0
0
2
2
2
2
4
4
4
4
6
6
6
6
6
6
Bass control
For the playback channel, bass can be regulated in three audio modes: minimum, flat and maximum mode. In flat mode
the audio is not influenced. In minimum mode the bass range is from 0 to approximately 14 dB in steps of 1.5 dB.
In maximum mode, the bass range is from 0 to approximately 24 dB in steps of 2 dB. The programmable bass filters are
implemented digitally and have a fixed corner frequency of 100 Hz for the minimum mode and 75 Hz for the maximum
mode. Because of the exceptional amount of programmable gain, bass should be used with adequate prior attenuation,
using volume control.
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Table 12 Bass boost settings
BASS (dB)
BB4
BB3
BB2
BB1
BB0
FLAT SET
MIN. SET
MAX. SET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
...
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
...
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
...
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
...
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
...
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1.1
1.7
1.1
1.7
2.4
3.6
2.4
3.6
3.7
5.4
3.7
5.4
5.2
7.4
5.2
7.4
6.8
9.4
6.8
9.4
8.4
11.3
11.3
13.3
13.3
15.2
15.2
17.3
17.3
19.2
19.2
21.2
21.2
23.2
23.2
23.2
23.2
8.4
10.2
10.2
11.9
11.9
13.7
13.7
13.7
13.7
13.7
13.7
13.7
13.7
13.7
13.7
De-emphasis
De-emphasis is controlled by bit 4 of control register 0. The de-emphasis filter can be switched on or off. The digital
de-emphasis filter is dimensioned to produce the de-emphasis frequency characteristics for the sample rate 44.1 kHz.
De-emphasis is synchronized to the sample clock, so that operation always takes place on complete samples.
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Filter characteristics playback channel
The overall filter characteristic of the UDA1325 in flat mode is given in Fig.4 (de-emphasis off). The overall filter
characteristic of the UDA1325 includes the filter characteristics of the DSP in flat mode plus the filter characteristic of the
FSDAC (fs = 44.1 kHz)
MGM110
−0
−20
volume
(dB)
−40
−60
−80
−100
−120
−140
−160
0
10
20
30
40
50
60
70
80
90
100
f (kHz)
Fig.4 Overall filter characteristics of the UDA1325.
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
DSP extension port for enhanced playback audio processing
An external DSP can be used for adding extra sound processing features via the I2S inputs and outputs of the digital I/O
module. The UDA1325 supports the standard I2S-bus data protocol and the LSB-justified serial data input format with
word lengths of 16, 18 and 20 bits. Using the 4-pin digital I/O option the UDA1325 device acts as a master, controlling
the BCKO and WSO signals. Using the 6-pin digital I/O option GP2, GP3 and GP4 are output pins (master) and GP0,
GP1 and GP5 are input pins (slave).
The period of the WSO signal is determined by the number of samples in the 1 ms frame of the USB. This implies that
the WSO signal does not have a constant time period, but is jittery.
The characteristic timing of the I2S-bus signals is illustrated in Figs 5 and 6.
LEFT
WS
RIGHT
t
t
s;WS
t
h;WS
t
BCK(H)
BCK(L)
t
t
r
f
BCK
T
t
cy
s;DAT
t
h;DAT
DATA
LSB
MSB
MGK003
Fig.5 Timing of digital I/O input signals.
1999 May 10
21
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h
WS
BCK
LEFT
3
RIGHT
3
1
2
>=8
1
2
>=8
DATA
MSB B2
LSB MSB B2
LSB MSB
2
INPUT FORMAT I S-BUS
WS
RIGHT
LEFT
16
15
2
1
16
15
2
1
BCK
DATA
MSB B2
B15 LSB
LSB-JUSTIFIED FORMAT 16 BITS
MSB B2
B15 LSB
WS
RIGHT
17
LEFT
18
17
16
15
2
1
18
16
15
2
1
BCK
DATA
LSB
LSB
MSB B2
B3
B4
B17
MSB B2
B3
B4
B17
LSB-JUSTIFIED FORMAT 18 BITS
WS
LEFT
18
RIGHT
17 16
20
19
17
16
15
2
1
20
19
18
15
2
1
BCK
LSB
LSB
DATA
MSB B2
B3
B4
B5
B6
B19
MSB B2
B3
B4
B5
B6
B19
MGK002
LSB-JUSTIFIED FORMAT 20 BITS
Fig.6 Input formats.
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
PORT DEFINITION 80C51
Port 1
Table 13 Port 1 of the 80C51 microcontroller
8 BIT PORT 1
LOW
no error
BIT
FUNCTION
ADAC_error
HIGH
COMMENT
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
error
GP1
GP2
GP3
GP4
GP5
SCL
SDA
general purpose pins
I2C-bus
Port 3
Table 14 Port 3 of the 80C51 microcontroller
8 BIT PORT 3
BIT
3.0
3.1
FUNCTION
ASR_error
LOW
HIGH
COMMENT
no error
error
suspend
PSIE_MMU_SUSPEND
no suspend
suspend input from USB interface
during normal operation or input from
restart circuit
3.2
3.3
GP0 (INT0_N)
general purpose pin
PSIE_MMU_INT (INT1_N)
interrupt input from USB interface
during normal operation or input from
restart circuit
3.4
3.5
3.6
3.7
PSIE_MMU_READY
L3_MODE
L3_CLK
L3_DATA
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
MEMORY AND REGISTER SPACE 80C51
Overview registers
RESET
VALUE
ADDRESS
REGISTER
Port registers
Table 15 Register location and recommended values
after Power-on reset
80h
90h
A0h
B0h
P0
FFh
FFh
FFh
FFh
P1
P2
P3
RESET
VALUE
ADDRESS
REGISTER
0800h
0801h
1000h
1001h
1002h
1003h
2000h
4000h
4001h
PGA gain
09
5C
00
00
01
00
8B
ADIF control
I2C registers (SIO1 registers)
clock shop settings
reset control and APLL settings
IO selection register
power control
D8h
D9h
DAh
DBh
S1CON
S1STA
S1DAT
S1ADR
00h
ASR settings
Interrupts
data register PSIE
command register PSIE
The UDA1325 supports up to five (of maximal 7) interrupt
sources. Each interrupt source corresponds to an interrupt
vector in the CPU program memory address space:
Table 16 Special function register location
Source 0: vector 0003h external interrupt 0 (INT0_N)
Source 1: vector 000Bh Timer 0 interrupt
RESET
VALUE
ADDRESS
REGISTER
Source 2: vector 0013h external interrupt 1 (INT1_N)
Source 3: vector 001Bh Timer 1 interrupt
CPU registers
81h
82h
83h
D0h
E0h
F0h
SP
Source 4: vector 0023h UART interrupt (not present)
Source 5: vector 002Bh Timer 2 interrupt (not present)
Source 6: vector 0033h I2C interrupt.
DPL
DPH
PSW
ACC
B
INTERRUPT ENABLE REGISTER (IE)
Each interrupt source can be individually enabled or
disabled by setting or clearing a bit in IE. This register also
contains a global interrupt enable bit (EA) which can be
cleared to disable all interrupts at once.
Interrupt registers
A8h
B8h
IE
IP
00h
00h
Timer 0 and Timer 1 registers
7
6
5
4
3
2
1
0
Power On Value
88h
89h
8Ah
8Bh
8Ch
8Dh
T01CON
T01MOD
T0L
00h
00h
00h
00h
00h
00h
0
0
0
0
0
0
0
0
EX0 (vector 0003h))
ET0 (vector 000Bh))
EX1 (vector 0013h)
ET1 (vector 001Bh)
ES0 (n.a.)
ET2 (n.a.)
ES1 (vector 0033h)
EA
T1L
T0h
T1h
PCON registers
87h
PCON
00h
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Internal registers
Table 17 PGA gain registers
ADDRESS
REGISTER
COMMENTS
BIT
VALUE
0800h
PGA gain register
reserved
7
6
X
PGA input selection
0 (do not change it)
PGA gain right channel
5, 4 and 3 000 = −3 dB
001 = 0 dB
010 = 3 dB
011 = 9 dB
100 = 15 dB
101 = 21 dB
110 = 27 dB
111 = 27 dB
PGA gain left channel
2, 1 and 0 000 = −3 dB
001 = 0 dB
010 = 3 dB
011 = 9 dB
100 = 15 dB
101 = 21 dB
110 = 27 dB
111 = 27 dB
Table 18 ADIF control registers
ADDRESS
REGISTER
COMMENTS
BIT
VALUE
0801h
ADIF control register
reserved
7
X
number of bits per audio sample
to be transmitted to the host
6 and 5 00 = reserved
01 = 8 bits audio samples
10 = 16 bits audio samples
11 = 24 bits audio samples
0 = mono
mono/stereo selection
4
3
2
1 = stereo
selection audio input recording
channel
0 = digital serial audio input
1 = analog input
selection high-pass filter of
ADIF (DC-filter)
0 = high-pass filter off
1 = high-pass filter on
I2S-bus input serial input format
recording channel
1 and 0 00 = I2S-bus
01 = 16-bit LSB justified
10 = 18-bit LSB justified
11 = 20-bit LSB justified
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Table 19 Clock shop register
ADDRESS
REGISTER
COMMENTS
BIT
VALUE
1000h
clock shop settings
selection ADC clock source
7
0 = ADC clock from APLL
1 = ADC clock from OSCAD
divide factor Q
6 and 5 00 = ADC clock divided-by-1
01 = ADC clock divided-by-2
10 = ADC clock divided-by-4
11 = ADC clock divided-by-8
clock ADAC
4
3
2
1
0
0 = enable
1 = disable
clock 48 MHz internal
clock recovered by PSIE
ADC clock
0 = enable
1 = disable
0 = enable
1 = disable
0 = enable
1 = disable
OSCAD oscillator
0 = power on
1 = power off
Table 20 Reset control and APLL register
ADDRESS
REGISTER
reset control and APLL fcode (1 and 0)
settings clock frequency selection APLL
COMMENTS
BIT
VALUE
1001h
7 and 6 00 = 256 × 44.1 kHz
01 = 256 × 32 kHz
10 = 256 × 48 kHz
11 = 256 × 44.1 kHz
reserved
5
4
X
reset ADAC
0 = reset off
1 = reset on
reset MMU
3
2
1
0
0 = reset off
1 = reset on
reset digital I/O-interface
reset ADIF
0 = reset off
1 = reset on
0 = reset off
1 = reset on
reserved
X
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Table 21 I/O selection register
ADDRESS
REGISTER
COMMENTS
BIT
VALUE
1002h
I/O selection register
microcontroller control on
48 MHz oscillator
7
0 = UPC control disabled
(48 MHz oscillator is enabled)
1 = UPC control enabled
audio format
6 and 5 00 = 4-pins I2S
01 = 6-pins I2S
10 = 3-pins I2S (only input)
11 = 3-pins I2S (only input)
GP4 I/O if BIT0 = 1
GP3 I/O if BIT0 = 1
GP2 I/O if BIT0 = 1
GP1 I/O if BIT0 = 1
GP4 to GP1 function
4
3
2
1
0
0 = output
1 = input
0 = output
1 = input
0 = output
1 = input
0 = output
1 = input
0 = I2S usage
1 = general purpose usage
Table 22 Power control register
ADDRESS
REGISTER
COMMENTS
BIT
VALUE
1003h
power control register
analog modules
suspend input selection for P3.1
of the microcontroller
7
0 = suspend from USB interface
connected to P3.1 during
normal operation
1 = suspend from restart circuit
connected to P3.1 (e.g. after
power-down)
interrupt input selection for
P3.3 (INT1_N) of the
microcontroller
6
0 = interrupt from USB
interface connected to P3.3
during normal operation
1 = interrupt from restart circuit
connected to P3.3 (e.g. after
power-down)
power APLL
5
4
3
2
1
0
0 = power on
1 = power off
power FSDAC
power ADC left
power ADC right
power PGA left
power PGA right
0 = power on
1 = power off
0 = power on
1 = power off
0 = power on
1 = power off
0 = power on
1 = power off
0 = power on
1 = power off
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Table 23 ASR control register
ADDRESS
REGISTER
COMMENTS
robust word clock
BIT
VALUE
2000h
ASR control register
7
0 = off (not recommended)
1 = on (recommended)
6 and 5 00 = I2S-bus
01 = 16-bit LSB justified
serial I2S-bus output format
digital I/O interface
10 = 18-bit LSB justified
11 = 20-bit LSB justified
0 = mono phase inversal off
1 = mono phase inversal on
phase inversion (on right mono
output)
4
bits per sample modi
3 and 2 00 = reserved
01 = 8-bit audio
10 = 16-bit audio
11 = 24-bit audio
mono or stereo operation
ASR register start-up mode
1
0
0 = mono
1 = stereo
0 = stop (e.g. at alternate
setting with bandwidth equal to
zero)
1 = go
START-UP BEHAVIOUR AND POWER MANAGEMENT
Start-up of the UDA1325
After power-on (of VDDA1), an internal Power-on reset signal becomes HIGH after a certain RC time. This RC time is
created by using the internal resistor (2 × 50 kΩ) divider for creating the reference voltage for the FSDAC in combination
with the capacitor connected externally to the VREFDA pin. The FSDAC and the internal resistor divider are supplied by
VDDA1 and VSSA1. The RC time can be calculated using R = 25000 Ω and C = Cref.
During 20 ms after Power-on reset becomes HIGH the UDA1325 has to initiate the internal registers. During this
initialisation, the user should prevent indicating the ‘connected’ status to the USB-host. This can be done by forcing the
DP-line LOW (i.e. via one of the GP pins).
Power Management
The total current drawn from the USB supply (for i.e. bus-powered operation of the UDA1325 application) must be less
than 500 µA in suspend mode. In order to reach that low current target, the total power dissipation of the UDA1325 can
be reduced by disabling all internal clocks and switching off all internal analog modules.
Important note: In order to make use of power reduction (Power-down mode) and be able to restart after power-down, a
number of precautions must be taken!
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
AT INITIALISATION TIME
• Bit 7of the power control register (mux_ctrl_suspend) must be set to ‘1’, in order to connect the CLK_ON of the USB
processor with P3.1 of the microcontroller
• Bit 6 of the power control register (mux_ctrl_int1) must be set to ‘0’, in order to connect the PSIE_MMU_INT output pin
of the USB processor with P3.3 (INT1_N) of the microcontroller
• Bit 7of the I/O selection register must be set to ‘1’, in order to enable the power-on control of the 48 MHz crystal
oscillator automatically by the microcontroller.
IN NORMAL OPERATION MODE
In normal operation working mode, a suspend can be initiated by the falling edge of the CLK_ON output signal of the
USB processor. This falling edge comes about 2 ms after the rising edge of the PSIE_MMU_SUSPEND output signal of
the USB processor. At this moment, several actions should be taken by the microcontroller:
• All analog modules of the UDA1325 must be switched off; this can be done by setting bits 5 to 0 of the power control
register to ‘1’ and bit 0 of the clock shop register to ‘1’
• Bit 6 of the power control register (mux_ctrl_int1) must be set to ‘1’, in order to awake from power-down by the
CLK_ON signal of the USB processor
• Put all GP pins in the high or low state (depending of how they are used in the UDA1325 application)
• Put the microcontroller in Power-down mode. This can be done via the PCON register of the microcontroller. This
results in an automatically switching off the 48 MHz crystal oscillator and with that all internal clocks (if they are
enabled).
On the rising edge of the CLK_ON output signal, the 48 MHz crystal oscillator will be switched on automatically and with
that all internal clocks (if they are enabled). At the same time, a counter starts counting for 2048 clock cycles (170 µs).
This time is necessary for stabilising the 48 MHz clock of the 48 MHz crystal oscillator.
When the counter reaches its end value (after 2048 cycles), a rising edge will be detected on the P3.3 (INT1_N) of the
microcontroller. At this moment, following actions should be taken by the microcontroller:
• The Power-down mode of the microcontroller must be switched off
• Re-initialise all GP pins
• All analog modules of the UDA1325 must be switched on; this can be done by setting bits 5 to 0 of the power control
register to ‘0’ and bit 0 of the clock shop register to ‘0’
• Bit 6 of the power control register (mux_ctrl_int1) must be set to ‘0’, in order to connect the PSIE_MMU_INT output pin
of the USB processor again with P3.3 (INT1_N) of the microcontroller.
The UDA1325 is now back in its normal operation mode and can be put back in power reduction mode by the falling edge
of the CLK_ON signal of the USB processor.
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
COMMAND SUMMARY
COMMAND NAME
RECIPIENT
CODING
DATA PHASE
Initialization commands
Set address/enable
Read address/enable
Set endpoint enable
Read endpoint enable
Set mode
device
device
device
device
device
D0h
D0h
D8h
D8h
F3h
write 1 byte
read 1 byte
write 1 byte
read 1 byte
write 1 byte
Data flow commands
Read interrupt register
Select endpoint
device
F4h
00h
01h
read 1 byte
read 1 byte (optional)
read 1 byte (optional)
read 1 byte (optional)
read 1 byte
read 1 byte
read 1 byte
write 1 byte
write 1 byte
write 1 byte
read n bytes
write n bytes
none
control OUT
control IN
other endpoints
control OUT
00h + endpoint index
Get endpoint status
Set endpoint status
40h
control IN
41h
other endpoints
control OUT
40h + endpoint index
40h
control IN
41h
other endpoints
selected endpoint
selected endpoint
selected endpoint
selected endpoint
selected endpoint
40h + endpoint index
Read buffer
F0h
F0h
F1h
F2h
FAh
Write buffer
Acknowledge setup
Clear buffer
none
Validate buffer
none
General commands
Read current frame number
F5h
read 1 or 2 bytes
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
COMMAND DESCRIPTIONS
Command procedure
Table 24
BIT
DESCRIPTION
Address
Enable
the value written becomes
the device address
This chapter describes the commands that can be used by
the microcontroller to control the USB processor. There
are three basic types of commands:
a ‘1’ enables this function
• Initialization commands
• Data flow commands
• General commands.
READ ADDRESS/ENABLE
Command: D0h.
Data: read 1 byte.
A command is represented by an 8 bit code. It can be
followed by one or more data write cycles or one or more
read cycles or a combination. The PSIE_MMU_READY
output connected to Port 3.4 of the microcontroller
indicates that the previous action (command write, data
read or data write) has completed. A new action can only
be initiated if PSIE_MMU_READY is TRUE. The data is
valid from the moment PSIE_MMU_READY becomes
TRUE.
The read address/enable command is used to read the
USB assigned address and the enable bit of the device.
The format of the data phase is the same as for the set
address/enable command.
SET ENDPOINT ENABLE
Command: D8h.
Data: write 1 byte.
The PSIE contains a number of interrupt registers, one for
each endpoint. Every time a transition occurs, the interrupt
flag for the involved endpoint is set. The PSIE_MMU_INT
connected to Port 3.3 is an OR function of all interrupt
registers.
The set endpoint enable command is used to set the
enable bits for the non default endpoints.
7
6
5
4
3
2
1
0
Power On Value
X
X
X
X
X
X
X
0
Initialization commands
Enable
Initialization commands are used during the enumeration
process of the USB network. They are used to set the USB
assigned address, enable endpoints and select the
configuration of the device.
Reserved
If the enable bit is ‘1’, the non default endpoints are
enabled, if ‘0’, the non default endpoints are disabled.
The function then only responds to the default control
endpoint.
SET ADDRESS/ENABLE
Command: D0h.
After bus reset, the enable bit is set to ‘0’.
Data: write 1 byte.
READ ENDPOINT ENABLE
Command: D8h.
The set address/enable command is used to set the USB
assigned address and enable the function. The device
always powers up disabled and should be enabled after a
bus reset.
Data: read 1 byte.
The read endpoint enable command is used to read the
enable bit for the non default endpoints of the function.
The format of the data phase is the same as for the set
endpoint enable command.
7
6
5
4
3
2
1
0
Power On Value
0
0
0
0
0
0
0
0
Address
Enable
SET MODE
Command: F3h.
Data: write 1 byte.
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
An interrupt is also generated after a bus reset. When the
interrupt register consists of all zeros, and an interrupt was
generated, there was a bus reset. The interrupt is cleared
when the interrupt register is read.
7
6
5
4
3
2
1
0
Reset value
Bus Reset
0
0
1
1
1
1
1
1
T
T
F
F
T
T
T
T
IsoOut
7
6
5
4
3
2
1
0
IsoIn
IntIsoOut
IntIsoIn
Power On Value
0
0
0
0
0
0
0
0
ErrorDebugMode
AlwaysPLLClock
Reserved
Reserved
Control OUT
Control IN
Endpoint 1 OUT
Endpoint 1 IN
Endpoint 2 IN
Endpoint 3 IN
Endpoint 4 OUT
Endpoint 5 IN
Reset value: gives the value of the bits after Power-on
reset. Bus reset: a ‘F’ indicates that the value of the bit is
not changed during a bus reset. a ‘T’ indicates that during
a bus reset, the bit is reset to its reset value.
SELECT ENDPOINT
Table 25
Command: 00h + endpoint index.
Data: optional read 1 byte.
BIT
DESCRIPTION
IsoOut
IsoIn
ISO out endpoint can be
used
The select endpoint command initializes an internal
pointer to the start of the selected buffer. Optionally, this
command can be followed by a data read. Bit 0 is low if the
buffer is empty and high if the buffer is full. There is one
command for every endpoint.
ISO in endpoint can be
used
IntIsoOut
IntIsoIn
allow interrupt from ISO
out endpoint
7
6
5
4
3
2
1
0
allow interrupt from ISO in
endpoint
Power On Value
X
X
X
X
X
X
X
0
ErrorDebugMode
AlwaysPLLClock
Setting chip in debug
mode
Full/Empty
Reserved
the PLL clock must keep
on running
GET ENDPOINT STATUS
Data flow commands
Command: 40h + endpoint index.
Data: read 1 byte.
Data flow commands are used to manage the data
transmission between the USB endpoints and the host.
Much of the data flow is initiated via the interrupt to the
microcontroller. The microcontroller uses these
commands to access the endpoint buffers and determine
whether the endpoint buffers have valid data.
The get endpoint status command is followed by one data
read that returns the status of the last transaction of the
selected endpoint. This command also resets the
corresponding interrupt flag in the interrupt register, and
clears the status, indicating that it was read. There is one
command for every endpoint.
READ INTERRUPT REGISTER
Command: F4h.
7
6
5
4
3
2
1
0
Data: read 1 byte.
Power On Value
0
0
0
0
0
0
0
0
The read interrupt register command returns the value of
the interrupt register. Every time a packet is received or
transmitted, an interrupt will be generated and a flag
specific to the physical endpoint will be set in the interrupt
register. Reading the status of the endpoint will clear the
flag.
Data Receive/Transmit
Error Code
Setup Packet
Data 0/1 Packet
Previous Status not Read
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Table 26 Error codes
SET ENDPOINT STATUS
Command: 40h + endpoint index.
Data: write 1 byte.
ERROR
RESULT
CODE
0000
0001
no error
This command is used to stall or unstall an endpoint. Only
the least significant bit has a meaning. When the stalled bit
is equal to 1, the endpoint is stalled, when equal to 0, the
endpoint is unstalled. There is one command for every
endpoint.
PID encoding error; bits 7 to 4 in the PID
token are not the inversion of bits 3 to 0
0010
0011
PID unknown; PID encoding is valid, but PID
does not exist
unexpected packet; packet is not of the type
expected (token, data or acknowledge), or
SETUP token received on non-control
endpoint
A stalled control endpoint is automatically unstalled when
it receives a SETUP token, regardless of the contents of
the packet. If the endpoint should stay in stalled state, the
microcontroller should restall it.
0100
0101
0110
0111
1000
1001
1010
token CRC error
data CRC error
When a stalled endpoint is unstalled, it is also re-initialized.
This means that its buffer is flushed and the next DATA
PID that will be sent or expected (depending on the
direction of the endpoint) is DATA0.
time out error
babble error
unexpected end-of-packet
sent or received NAK
7
6
5
4
3
2
1
0
sent stall, a token was received, but the
endpoint was stalled
Power On Value
X
X
X
X
X
X
X
0
Stalled
Reserved
1011
overflow error, the received data packet was
larger then the buffer size of the selected
endpoint
1100
1101
1110
1111
sent empty packet (ISO only)
bitstuff error
READ BUFFER
Command: F0h.
Data: read n bytes (max. 10).
error in sync
wrong data PID
The read buffer command is followed by a number of data
reads, which returns the contents of the selected endpoint
data buffer. After each read, the internal buffer pointer is
incremented by 1.
Table 27
BIT
DESCRIPTION
Data receive/transmit
a ‘1’ indicates data has
been received or
transmitted successfully
The buffer pointer is not reset to the buffer start by the read
buffer command. This means that reading a buffer can be
interrupted by any other command (except for select
endpoint).
Error code
see Table 26
Setup packet
a ‘1’ indicates the last
received packet had a
SETUP token (this will
always read ‘0’ for IN
buffers)
Data 0/1 packet
a ‘1’ indicates the last
received packet had a
DATA 1 PID
Previous status not read
a ‘1’ indicates a second
event occurred before the
previous status was read
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
The data in the buffer are organized as follows:
Byte 0: transfer successful, number of data bytes (MSB)
Byte 1: number of data bytes (LSB)
Byte 2: data byte 0
acknowledged explicitly that it has seen the SETUP
packet.
If the microcontroller is reading the data from a SETUP
packet, and a new SETUP packet arrives, the device must
accept this new SETUP packet. So the data, currently
being read by the microcontroller, is overwritten with the
new packet. On the arrival of the new packet, the
commands validate buffer and clear buffer are disabled.
If the microcontroller has finished reading the data from
the buffer, it will try to clear the buffer. The device will
ignore this command, so the new SETUP packet in the
buffer is not cleared. The microcontroller will now detect
the interrupt of the new SETUP packet and will start
reading the new data in the buffer.
Byte 3: data byte 1
Byte 4: data byte 2
Byte 5: data byte 3
Byte 6: data byte 4
Byte 7: data byte 5
Byte 8: data byte 6
Byte 9: data byte 7.
Bytes 0 and 1 indicate the number of bytes in the buffer.
Byte 0 is the Most Significant Byte (MSB). Byte 1 is the
Least Significant Byte (LSB). Only bits 1 and 0 of byte 0
are used in the number of bytes indication.
A SETUP token can be followed by an IN token. After the
SETUP token, the microcontroller will start filling the IN
buffer. A SETUP token will clear the IN buffer. This avoids
the following problem: after a SETUP token, the
microcontroller fills the IN buffer. If the SETUP token is
followed by a SETUP token and shortly followed by an IN
token, the device will send the contents of the IN buffer to
the host. The IN buffer was filled after the first SETUP
token. That is why after a SETUP token the IN buffer is
cleared.
Bit 7 of byte 0 indicates if the transaction was successful
(bit 7 is ‘1’ if the transaction was successful). Bits 6 to 2 of
byte 0 are reserved.
WRITE BUFFER
Command: F0h.
If the microcontroller is still filling the buffer when the
second SETUP token arrives, the SETUP token will clear
the IN buffer. If the microcontroller has filled the IN buffer,
it will validate the buffer. So clearing the IN buffer on
receiving a SETUP token is not enough.
Data: write n bytes (max. 10).
The write buffer command is followed by a number of data
writes, which load the endpoint buffer. After each write, the
internal buffer pointer is incremented by 1.
If a SETUP token is received, the device will also disable
the validate buffer command for the IN buffer. If the
microcontroller needs to fill the buffer after a SETUP token,
the command acknowledge setup command must be sent
to enable the validate buffer command.
The buffer pointer is not reset to the buffer start by the write
buffer command. This means that writing a buffer can be
interrupted by any other command (except for select
endpoint).
The data must be organized in the same way as described
in the read buffer command. Bits 7 to 2 of byte 0 are
reserved and must be filled with zeros.
CLEAR BUFFER
Command: F2h.
Data: none.
ACKNOWLEDGE SETUP
Command: F1h.
Data: none.
When a packet is received completely, an internal
endpoint buffer full flag is set. All subsequent packets will
be refused by returning a NACK to the host. When the
microcontroller has read the data, it should free the buffer
by the clear buffer command. When the buffer is cleared,
new packets will be accepted.
The arrival of a SETUP packet flushes the IN buffer and
disables the validate buffer and clear buffer commands for
both IN and OUT endpoints.
The microcontroller needs to re-enable these commands
by the acknowledge setup command. This ensures that
the last SETUP packet stays in the buffer and no packet
can be sent back to the host until the microcontroller has
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
VALIDATE BUFFER
Command: FAh.
Data: none.
S1CON register
The CPU can read from and write to this 8-bit SFR.
Two bits are effected by the SIO1 hardware: the SI bit is
set when a serial interrupt is requested, and the STO bit is
cleared when a STOP condition is present on the I2C-bus.
The STO bit is also cleared when ENS1 = ‘0’. Reset
initializes S1CON to 00h.
When the microcontroller has written data into an IN buffer,
it should set the buffer full flag by the validate buffer
command. This indicates that the data in the buffer are
valid and can be sent to the host when the next IN token is
received.
7
6
5
4
3
2
1
0
Power On Value
0
0
0
0
0
0
0
0
General commands
READ CURRENT FRAME NUMBER
Command: F5h.
CR0
CR1
AA
SI
STO
STA
ENS1
CR2
Data: read 1 or 2 bytes.
This command is followed by one or two data reads and
returns the frame number of the last successfully received
SOF. The frame number is eleven bits wide. The frame
number is returned least significant byte first. In case the
user is only interested in the lower 8 bits of the frame
number only the first byte needs to be read.
CR2, 1 AND 0 - THE CLOCK RATE BITS
These three bits determine the serial clock frequency
when SIO1 is in a master mode.
The various serial rates are shown in Table 28.
I2C MASTER/SLAVE INTERFACE
Table 28 Serial clock rates (SCL line)
The I2C module implements a master/slave I2C-bus
interface with integrated shift register, shift timing
generation and slave address recognition. It is compliant
to the I2C-bus specification IC20/Jan92. I2C standard
mode (100 kHz SCL) and fast mode (400 kHz) are
supported. Low speed mode and extended 10 bit
addressing are unsupported.
I2C BIT FREQUENCY
CR2
CR1
CR0
(kHz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1200
600
400
300
150
Characteristics of the I2C-bus
100
The I2C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to VDDE via a pull-up resistor.
75
3.9 ... 501
The timing definition of the I2C-bus is given in Fig.7.
When the CR bits are ‘111’, the maximum bit rate for the
data transfer will be derived from the Timer 1 overflow rate
divided by 2 (i.e. every time the Timer 1 overflows, the
SCL signal will toggle).
Programmer’s view
For a detailed description of the I2C-bus protocol refer to
Philips Integrated Circuits Data Handbook IC20, 8XC552.
The programmer’s view of the I2C library function is -with
one exception- identical to that of the 8XC552
microcontroller. Only the bit rate frequency selection in
S1CON and the handling of the Timer 1 overflow
information deviates to accommodate 400 kHz operation.
1999 May 10
35
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SDA
t
t
t
t
t
t
r
BUF
LOW
HD;STA
SP
f
SCL
t
t
SU;STO
HD;STA
t
t
t
t
SU;STA
HD;DAT
HIGH
SU;DAT
P
S
P
Sr
MBC611
Fig.7 Definition of timing of the I2C-bus.
hadnbo,kfullpagewidt
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
All digital I/Os
VI/O
IO
DC input/output voltage range
output current
−0.5
−
−
−
VDDE
V
VDDE = 5.0 V
4
mA
Temperature values
Tj
junction temperature
0
−
−
125
+150
70
°C
°C
°C
Tstg
Tamb
storage temperature
−55
0
operating ambient temperature
25
Electrostatic handling
Ves
electrostatic handling
note 1
note 2
−3000
−300
−
−
+3000
+300
V
V
Notes
1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
2. Equivalent to discharging a 200 pF capacitor through a 2.5 µH series conductor.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient
UDA1325PS
UDA1325H
in free air
in free air
48
48
K/W
K/W
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VDDE
VDD
PARAMETER
supply voltage periphery (I/O)
MIN.
TYP.
MAX.
UNIT
4.75
3.0
5.0
3.3
5.25
3.6
V
V
supply voltage (core)
DC input voltage range
for D+ and D−
for VINL and VINR
for digital I/Os
VI
0.0
−
−
VDD
−
V
V
V
0.5VDD
0.0
−
VDDE
1999 May 10
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Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
DC CHARACTERISTICS
VDDE = 5.0 V; VDD = 3.3 V; Tamb = 25 °C; fosc = 48 MHz; fs = 44.1 kHz; unless otherwise specified.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDE
VDDI
VDDA1
VDDA2
VDDA3
VDDO
VDDX
IDDE
digital supply voltage periphery
digital supply voltage core
analog supply voltage 1
4.75
5.0
5.25
V
V
V
V
V
V
V
3.0
3.0
3.0
3.0
3.0
3.0
−
−
−
−
−
3.3
3.3
3.3
3.3
3.3
3.3
3.7
39.0
3.6
8.0
0.9
3.0
1.2
200
1.2
3.6
3.6
3.6
3.6
3.6
3.6
−
−
−
−
9.0(2)
analog supply voltage 2
analog supply voltage 3
operational amplifier supply voltage
crystal oscillator supply voltage
digital supply current periphery
digital supply current core
analog supply current 1
note 1
mA
mA
mA
mA
mA
mA
mA
mW
mW
IDDI
IDDA1
IDDA2
IDDA3
IDDO
IDDX
analog supply current 2
analog supply current 3
operational amplifier supply current
crystal oscillator supply current
total power dissipation
−
−
−
−
−
13.0(3)
−
Ptot
Pps
total power dissipation in power
saving mode
note 4
−
Inputs/outputs D+ and D−
VI
static DC input voltage
−0.5
2.8
−
−
VDDI
3.6
V
V
VO(H)
static DC output voltage HIGH
RL = 15 kΩ
connected to GND
VO(L)
ILO
static DC output voltage LOW
RL = 1.5 kΩ
connected to VDD
−
−
−
−
0.3
10
V
high impedance data line output
leakage current
µA
VI(diff)
differential input sensitivity
0.2
0.8
0.8
−
−
−
−
2.5
2.0
V
V
V
VCM(diff)
VSE(R)(th)
differential common mode range
single-ended receiver threshold
voltage
CIN
transceiver input capacitance
pin to GND
−
−
20
pF
Digital input pins
VIL
VIH
ILI
LOW-level input voltage
−
−
−
−
−
0.3VDDE
V
HIGH-level input voltage
input leakage current
input capacitance
0.7VDDE
VDDE
V
−
−
1
5
µA
pF
CI
1999 May 10
38
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
PGA and ADC
Vref(AD)
reference voltage PGA and ADC
−
−
0.5VDDA2
VDDA2
−
−
V
V
Vref(ADC)(pos) positive reference voltage of the
ADC
Vref(ADC)(neg) negative reference voltage of the
ADC
−
−
−
0.0
−
−
−
V
V
VI(PGA)
DC input voltage VINL and VINR of
the PGA
0.5VDDA2
12.5
RI(PGA)
DC input resistance at VINL and
VINR of the PGA
kΩ
Filter stream DAC
Vref(DA) reference voltage DAC
VO(CM)
−
−
−
0.5VDDA1
0.5VDDA1
11
−
−
−
V
V
Ω
common mode output voltage
RO(VOUT)
output resistance at VOUTL and
VOUTR
RO(L)
CO(L)
output load resistance
output load capacitance
2.0
−
−
−
50
kΩ
pF
−
Notes
1. This value depends strongly on the application. The specified value is the typical value obtained using the application
diagram as illustrated in Fig.8.
2. At start-up of the OSCAD oscillator.
3. At start-up of the OSC48 oscillator.
4. Exclusive the IDDE current which depends on the components connected to the I/O pins.
1999 May 10
39
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
AC CHARACTERISTICS
VDDE = 5.0 V; VDDI = 3.3 V; Tamb = 25 °C; fosc = 48 MHz; fs = 44.1 kHz; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Driver characteristics D+ and D− (full-speed mode)
fo(s)
tr
audio sample output frequency
rise time
5
−
−
−
−
−
−
55
kHz
CL = 50 pF
CL = 50 pF
4
20
ns
ns
%
V
tf
fall time
4
20
trf(m)
Vcr
rise/fall time matching (tr/tf)
output signal crossover voltage
driver output resistance
90
110
2.0
43
1.3
Ro(drive)
steady-state drive 28
5
Ω
Data source timings D+ and D− (full-speed mode)
fi(s)
audio sample input frequency
full speed data rate
frame interval
−
55
kHz
Mbits/s
ms
ffs(D)
tfr(D)
tJ1(diff)
11.97
12.00
1.0000
0.0
12.03
1.0005
+3.5
0.9995
source differential jitter to next
transition
−3.5
ns
tJ2(diff)
source differential jitter for paired
transitions
−4.0
0.0
+4.0
ns
tW(EOP)
tEOP(diff)
source end of packet width
160
−
−
175
ns
ns
differential to end of packet
transition skew
−2.0
+5.0
tJR1
receiver data jitter tolerance to next
transition
−18.5
−9.0
40
0.0
0.0
−
+18.5
+9.0
−
ns
ns
ns
ns
tJR2
receiver data jitter tolerance for
paired transitions
tEOPR1
tEOPR2
end of packet width at receiver
must reject as end of packet
end of packet width at receiver
must accept as end of packet
82
−
−
Serial input/output data timing
fs
system clock frequency
−
5
12
−
−
−
−
−
−
−
−
−
−
MHz
kHz
ns
fi(WS)
tr
word selection input frequency
rise time
55
20
20
−
−
−
−
−
−
−
−
tf
fall time
ns
tBCK(H)
tBCK(L)
ts;DAT
th;DAT
ts;WS
th;WS
bit clock HIGH time
bit clock LOW time
data set-up time
55
55
10
20
20
10
ns
ns
ns
data hold time
ns
word selection set-up time
word selection hold time
ns
ns
1999 May 10
40
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SDA and SCL lines for 100 kHz I2C devices
fSCL
tBUF
SCL clock frequency
0
−
−
100
kHz
bus free time between a STOP and
START condition
4.7
−
µs
tHD;STA
hold time (repeated) START
condition
4.0
−
−
µs
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
4.7
4.0
4.7
−
−
−
−
−
−
µs
µs
µs
tHIGH
tSU;STA
set-up time for a repeated START
condition
tSU;STO
tHD;DAT
tSU;DAT
tr
set-up time for STOP condition
data hold time
4.0
5.0
250
−
−
−
−
−
−
−
−
1000
µs
µs
ns
ns
data set-up time
rise time of both SDA and SCL
signals
tf
fall time of both SDA and SCL
signals
−
−
−
−
300
400
ns
CL(bus)
capacitive load for each bus line
pF
Oscillator 1 (system clock)
fosc
oscillator frequency
−
−
48
50
−
−
MHz
%
δ
duty factor
gm
transconductance
12.8
0.6
4.5
4.1
3.7
22.1
1.1
4.8
4.6
7.6
30.2
2.3
5.2
5.0
13.0
mS
kΩ
pF
Ro
output resistance
Ci(XTAL1a)
Ci(XTAL2a)
Istart
parasitic input capacitance XTAL1a
parasitic input capacitance XTAL2a
start-up current
pF
mA
Oscillator 2 (for ADC clock)
fosc
oscillator frequency
8.192
−
−
50
14.08
−
MHz
%
δ
duty cycle
gm
transconductance
8.1
1.3
5.0
4.1
2.4
13.6
2.0
5.4
4.6
5.0
18.1
4.0
5.7
5.0
8.4
mA/V
kΩ
Ro
output resistance
Ci(XTAL1b)
Ci(XTAL2b)
Istart
parasitic input capacitance XTAL1b
parasitic input capacitance XTAL2b
start-up current
pF
pF
mA
1999 May 10
41
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
SYMBOL
Analog PLL (for ADC clock)
fclk(PLL) PLL clock frequency
δ
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
8.1920
11.2896
12.2880 MHz
duty factor
−
−
50
−
%
tstrt(PO)
start-up time after power-on
−
10
ms
Power-on reset
(2)
tsu(PO)
power-on set-up-time
note 1
25Cref
−
−
ms
PGA and ADC
Vi(FS)(rms)
full-scale input voltage (RMS value) PGA gain = −3 dB
PGA gain = 0 dB
−
−
−
−
−
−
−
−
1414(3)
1000
708
355
178
89
−
−
−
−
−
−
−
20
mV
mV
mV
mV
mV
mV
mV
pF
PGA gain = 3 dB
PGA gain = 9 dB
PGA gain = 15 dB
PGA gain = 21 dB
PGA gain = 27 dB
44
Ci(PGA)
input capacitance of the PGA
−
(THD + N)/S total harmonic distortion plus
noise-to-signal ratio
fs = 44.1 kHz at
input signal of
1 kHz; PGA
gain = 0 dB;
note 4
Vi (0 dB)
1.0 V (RMS)
−
−
−
−
90
−
0.640
−
−85
0.0056
−30
3.2
−80
0.01
−20
10.0
−
−
7.04
−
dB
%
Vi (−60 dB)
dB
%
S/N
αct
fs
signal to noise ratio
Vi = 0.0 V
95
dBA
dB
crosstalk between channels
sample frequency (128fs)
digital output level
PGA gain = 0 dB
100
−
−2.0
MHz
dBFS
OL
PGA gain = 0 dB,
Vi = 1 V (RMS)
1999 May 10
42
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Filter stream DAC
RES
resolution
16
−
0.66
−
−
bits
Vo(FS)(rms)
full-scale output voltage
(RMS value)
VDD = 3.3 V
−
V
SVRR
supply voltage ripple rejection at
fripple = 1 kHz
Vripple(p-p) = 0.1 V
−
60
−
dB
V
DDA and VDDO
∆Vo
αct
channel unbalance
maximum volume
−
−
0.03
95
−
−
dB
dB
crosstalk between channels
RL = 5 kΩ
(THD + N)/S total harmonic distortion plus
noise-to-signal ratio
fs = 44.1 kHz;
RL = 5 kΩ; note 5
at input signal of
1 kHz (0 dB)
−
−
−
−
−90
0.0032
−30
3.2
−80
0.01
−20
10
dB
%
at input signal of
1 kHz (−60 dB)
dB
%
S/N
signal-to-noise ratio at bipolar zero A-weighting at
code 0000H
90
95
−
dB
Notes
1. Strongly depends on the external decoupling capacitor connected to Vref(DA)
.
2. Cref in µF.
3. Although a level of 1.414 V (RMS) would be required to optimal drive the ADC in this gain setting, this level can not
be used. Due to the 3.3 V supply voltage input, signals of 1.17 V (RMS) and higher will result in clipping.
4. Measured with the APLL as ADC clock source.
5. Measured with I2S-bus input as digital source.
1999 May 10
43
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
APPLICATION INFORMATION
+V
+V
A
A
R35
R27
1 Ω
1 Ω
C34
C32
47 µF
47 µF
(16 V)
(16 V)
C38
C21
100 nF
(63 V)
100 nF
(63 V)
V
V
V
V
DDA2
SSA1
DDA1
44
SSA2
39
38
42
GP0/BCKI
GP5/WSI
GP1/DI
BCKI
17
15
13
digital
input
WSI
playback
DI
BCK
WS
DA
BCK
61
59
57
digital
input
recording
WS
DA
+V
C
R48
1.5 kΩ
V
L1
X4
USB
1
2
3
4
8
1
2
3
4
R7
D−
7
6
5
6
8
22 Ω
R16
D+
UDA1325H
22 Ω
C16
10 nF
(50 V)
C18
22 pF
(63 V)
C17
22 pF
(63 V)
C15
10 nF
(50 V)
C8
VINR
VINL
47
43
analog
input
recording
47 µF (16 V)
C22
47 µF (16 V)
L5
C44
1
XTAL2b
26
1.5 µH
10 nF (63 V)
C38
12 pF (63 V)
X1
48 MHz
XTAL1b
C37
25
12 pF (63 V)
XTAL2a
XTAL1a
53
54
ADC XTAL
C5
C6
18 pF
(50 V)
18 pF
(50 V)
L8
10
9
11
12
V
V
+V
A(ext)
A
C
D
BLM32A07
L7
V
V
V
SSE
SSI
C25
DDI
DDE
C26
+V
BLM32A07
L6
100 nF
(63 V)
100 nF
(63 V)
L2
L3
V
+V
D(ext)
BLM32A07
BLM32A07
BLM32A07
C24
C27
C47
C46
C45
100 µF
(16 V)
100 µF
(16 V)
100 µF
(16 V)
100 nF
(63 V)
100 nF
(63 V)
R17
1 Ω
R25
1 Ω
GND
MGM760
+V
+V
C
D
Fig.8 Application diagram UDA1325H (continued in Fig.9).
44
1999 May 10
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
+V
+V
A
A
R10
R8
1 Ω
1 Ω
C7
C11
47 µF
100 nF
(63 V)
(16 V)
C19
100 nF
(63 V)
V
V
VRN
VRP
SSA3
DDA3
55
52
49
51
D
D
D
Q
Q
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
A0
A1
A2
A3
A4
A5
O0
11
7
6
5
7
6
56
18
17
14
13
8
19
16
15
12
9
10
9
O1
58
60
62
64
3
12
O2
13
Q
Q
Q
Q
Q
Q
V
5
4
3
2
1
0
8
D
D
D
O3
4
3
2
7
15
O4
16
6
D1
O5
17
5
7
74HCT373D
6
D
O6
18
A6
A7
A8
1
0
5
4
5
4
D
O7
19
7
3
2
3
CC
D2
+V
25
24
21
LE
OE
20
10
ALE
D
50
11
1
A9
A10
A11
A12
A13
EEPM27128
100 nF
(50 V)
C24
GND
23
2
V
CC
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
PSEN
+V
28
14
D
14
16
18
20
22
23
31
100 nF
(50 V)
26
C25
GND
OE
CE
22
20
27
1
PGM
V
PP
R28
+V
EA
D
48
4.7 kΩ
R20
+V
+V
D
D
3
(internal ROM)
(external ROM)
1 Ω
V
A0
A1
A2
SS
DD
PTC
SCL
SDA
C36
100 nF
(63 V)
1
8
7
6
5
+V
2
1
D
2
3
4
D4
J3
1
UDA1325H
PCF85116-3
R38
10 kΩ
R39
10 kΩ
V
SDA
SCL
V
21
19
(I2C-bus)
2
ref(DA)
ref(AD)
40
41
V
C29
100 nF
(63 V)
C41
47 µF
(16 V)
C28
100 nF
(63 V)
C31
47 µF
(16 V)
C35
VOUTR
VOUTL
37
34
47 µF (16 V)
analog
output
playback
C48
47 µF (16 V)
GP4/BCKO
GP3/WSO
GP2/DO
2
1
BCKO
WSO
digital
output
playback
63
DO
RTCB
TC
36
35
4
SHTCB
33
32
24
28
V
V
V
V
DDX
SSO
C33
DDO
SSX
C28
100 nF
(63 V)
100 nF
(63 V)
L13
BLM32A07
C39
C18
47 µF
100 nF
(63 V)
R43
1 Ω
R26
1 Ω
(16 V)
MGM761
+V
+V
C
A
Fig.9 Application diagram UDA1325H (continued from Fig.8).
45
1999 May 10
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h
+V
+V
A
+V
+V
A
A
A
R35
1 Ω
R27
1 Ω
R10
1 Ω
R8
1 Ω
C34
C32
C7
C11
+V
47 µF
47 µF
47 µF
100 nF
(63 V)
D
(16 V)
(16 V)
(16 V)
C38
C21
C19
R20 1 Ω
100 nF
(63 V)
100 nF
(63 V)
100 nF
(63 V)
V
V
V
V
DDA2
V
V
VRN
VRP
SSA1
DDA1
35
SSA2
SSA3
DDA3
V
DD
A0
A1
A2
SS
30
29
33
42
39
37
38
C36
100 nF
(63 V)
1
2
3
4
8
7
6
5
+V
D
PTC
SCL
SDA
GP0/BCKI
GP5/WSI
GP1/DI
D4
BCKI
WSI
DI
16
15
14
digital
input
playback
PCF85116-3
V
R38
10 kΩ
R39
10 kΩ
SDA
SCL
V
1
2
18
17
BCK
WS
DA
(I2C-bus)
BCK
WS
DA
3
2
1
digital
input
recording
ref(DA)
31
32
V
ref(AD)
C29
100 nF
(63 V)
C41
47 µF
(16 V)
C28
100 nF
(63 V)
C31
47 µF
(16 V)
+V
C
V
USB
L1
X4
R48
1.5 kΩ
1
2
3
4
8
1
2
3
4
R7
D−
7
6
5
8
9
C35
22 Ω
R16
VOUTR
VOUTL
28
25
D+
47 µF (16 V)
analog
output
playback
22 Ω
C16
10 nF
(50 V)
C18
22 pF
(63 V)
C17
22 pF
(63 V)
C15
C48
10 nF
(50 V)
UDA1325PS
47 µF (16 V)
C8
VINR
VINL
36
34
analog
input
recording
47 µF (16 V)
C22
GP4/BCKO
GP3/WSO
GP2/DO
6
5
4
BCKO
WSO
47 µF (16 V)
digital
output
playback
L5
1.5 µH
C44
DO
1
XTAL2b
21
10 nF (63 V)
C38
12 pF (63 V)
C37
X1
48 MHz
XTAL1b
RTCB
TC
27
26
7
20
12 pF (63 V)
SHTCB
XTAL2a
XTAL1a
40
41
ADC XTAL
C5
18 pF
(50 V)
C6
18 pF
(50 V)
11
10
V
12
13
24
23
19
22
L8
V
V
V
V
V
V
V
DDX
V
V
SSI
C25
DDI
SSE
C26
DDE
SSO
C33
DDO
SSX
C28
+V
+V
+V
A(ext)
A
C
D
BLM32A07
L7
100 nF
(63 V)
100 nF
(63 V)
100 nF
(63 V)
100 nF
(63 V)
BLM32A07
L6
L13
BLM32A07
L2
L3
BLM32A07
BLM32A07
C39
C18
C24
C27
D(ext)
BLM32A07
C47
100 µF
(16 V)
C46
100 µF
(16 V)
C45
47 µF
100 nF
(63 V)
100 nF
(63 V)
100 nF
(63 V)
R43
1 Ω
R26
1 Ω
R17
1 Ω
R25
1 Ω
100 µF
(16 V)
(16 V)
GND
MGS271
+V
+V
C
+V
+V
A
C
D
Fig.10 Application diagram UDA1325PS.
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
PACKAGE OUTLINES
SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)
SOT270-1
D
M
E
A
2
A
L
A
1
c
e
(e )
w M
Z
1
b
1
M
H
b
42
22
pin 1 index
E
1
21
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
max.
A
A
(1)
(1)
Z
1
2
w
UNIT
b
b
c
D
E
e
e
L
M
M
H
1
1
E
min.
max.
max.
1.3
0.8
0.53
0.40
0.32
0.23
38.9
38.4
14.0
13.7
3.2
2.9
15.80
15.24
17.15
15.90
mm
5.08
0.51
4.0
1.778
15.24
0.18
1.73
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
90-02-13
95-02-04
SOT270-1
1999 May 10
47
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT319-2
y
X
A
51
33
52
32
Z
E
e
A
2
H
A
E
(A )
3
E
A
1
θ
w M
p
pin 1 index
L
p
b
L
20
64
detail X
1
19
w M
Z
v
M
D
A
b
p
e
D
B
H
v
M
B
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
7o
0o
0.25 2.90
0.05 2.65
0.50 0.25 20.1 14.1
0.35 0.14 19.9 13.9
24.2 18.2
23.6 17.6
1.0
0.6
1.2
0.8
1.2
0.8
mm
3.20
0.25
1
1.95
0.2
0.2
0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-08-01
SOT319-2
1999 May 10
48
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
SOLDERING
Introduction
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
WAVE SOLDERING
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mount components are mixed on
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
Through-hole mount packages
SOLDERING BY DIPPING OR BY SOLDER WAVE
• For packages with leads on two sides and a pitch (e):
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
MANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
300 and 400 °C, contact may be up to 5 seconds.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Surface mount packages
REFLOW SOLDERING
MANUAL SOLDERING
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 May 10
49
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Suitability of IC packages for wave, reflow and dipping soldering methods
SOLDERING METHOD
WAVE
REFLOW(1) DIPPING
suitable(2)
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(3)
MOUNTING
PACKAGE
Through-hole mount DBS, DIP, HDIP, SDIP, SIL
−
suitable
Surface mount
BGA, SQFP
suitable
suitable
suitable
suitable
suitable
−
−
−
−
−
PLCC(4), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(4)(5)
not recommended(6)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 May 10
50
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 May 10
51
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For all other countries apply to: Philips Semiconductors,
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5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1999
SCA64
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545002/750/01/pp52
Date of release: 1999 May 10
Document order number: 9397 750 02805
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