Fujitsu MPE3XXXAE User Manual
MPE3xxxAE  
DISK DRIVES  
PRODUCT MANUAL  
C141-E093-02EN  
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PREFACE  
This manual describes the MPE3xxxAE series, a 3.5-inch hard disk drive with a BUILT-IN controller  
that is compatible with the ATA interface.  
This manual explains, in detail, how to incorporate the hard disk drives into user systems.  
This manual assumes that users have a basic knowledge of hard disk drives and their application in  
computer systems.  
This manual consists of the following six chapters:  
Chapter 1  
Chapter 2  
Chapter 3  
Chapter 4  
Chapter 5  
Chapter 6  
DEVICE OVERVIEW  
DEVICE CONFIGURATION  
INSTALLATION CONDITIONS  
THEORY OF DEVICE OPERATION  
INTERFACE  
OPERATIONS  
In this manual, disk drives may be referred to as drives or devices.  
C141-E093-01EN  
iii  
Conventions for Alert Messages  
This manual uses the following conventions to show the alert messages. An alert message consists of  
an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or  
just a signal word.  
The following are the alert signals and their meanings:  
This indicates a hazarous situation likely to result in serious personal  
injury if the user does not perform the procedure correctly.  
This indicates a hazarous situation could result in personal injury if the  
user does not perform the porocedure correctly.  
This indicates a hazarous situation could result in minor or moderate  
personal injury if the user does not perform the procedure correctly.  
This alert signal also indicates that damages to the product or other  
property, may occur if the user does not perform the procedure  
correctly.  
This indicates information that could help the user use the product more  
efficiently.  
In the text, the alert signal is centered, followed below by the indented message. A wider line space  
precedes and follows the alert message to show where the alert message begins and ends. The  
following is an example:  
(Example)  
IMPORTANT  
HA (host adapter) consists of address decoder, driver, and receiver.  
ATA is an abbreviation of "AT attachment". The disk drive is  
conformed to the ATA-4 interface  
The main alert messages in the text are also listed in the “Important Alert Items.”  
iv  
C141-E093-01EN  
LIABILITY EXCEPTION  
"Disk drive defects" refers to defects that involve adjustment, repair, or replacement.  
Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or  
mishandling, inappropriate operating environments, defects in the power supply or cable, problems of  
the host system, or other causes outside the disk drive.  
C141-E093-01EN  
v
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CONTENTS  
page  
CHAPTER 1 DEVICE OVERVIEW ................................................................................... 1 - 1  
1.1 Features .......................................................................................................................... 1 - 1  
1.1.1 Functions and performance ............................................................................................ 1 - 1  
1.1.2 Adaptability.................................................................................................................... 1 - 2  
1.1.3 Interface.......................................................................................................................... 1 - 2  
1.2  
Device Specifications ..................................................................................................... 1 - 4  
1.2.1 Specifications summary.................................................................................................. 1 - 4  
1.2.2 Model and product number ............................................................................................ 1 - 5  
1.3  
1.4  
1.5  
1.6  
1.7  
1.8  
1.9  
Power Requirements....................................................................................................... 1 - 5  
Environmental Specifications......................................................................................... 1 - 8  
Acoustic Noise ............................................................................................................... 1 - 8  
Shock and Vibration....................................................................................................... 1 - 9  
Reliability....................................................................................................................... 1 - 9  
Error Rate ....................................................................................................................... 1 - 10  
Media Defects................................................................................................................. 1 - 10  
CHAPTER 2 DEVICE CONFIGURATION ....................................................................... 2 - 1  
2.1  
2.2  
Device Configuration ..................................................................................................... 2 - 1  
System Configuration..................................................................................................... 2 - 3  
2.2.1 ATA interface................................................................................................................. 2 - 3  
2.2.2 1 drive connection .......................................................................................................... 2 - 3  
2.2.3 2 drives connection......................................................................................................... 2 - 3  
CHAPTER 3 INSTALLATION CONDITIONS ................................................................. 3 - 1  
3.1  
3.2  
3.3  
Dimensions..................................................................................................................... 3 - 1  
Mounting........................................................................................................................ 3 - 3  
Cable Connections.......................................................................................................... 3 - 7  
3.3.1 Device connector............................................................................................................ 3 - 7  
3.3.2 Cable connector specifications ....................................................................................... 3 - 8  
3.3.3 Device connection .......................................................................................................... 3 - 8  
3.3.4 Power supply connector (CN1) ...................................................................................... 3 - 9  
3.3.5 System configuration for Ultra DMA............................................................................. 3 - 9  
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vii  
3.4  
Jumper Settings .............................................................................................................. 3 - 12  
3.4.1 Location of setting jumpers ............................................................................................ 3 - 12  
3.4.2 Factory default setting .................................................................................................... 3 - 13  
3.4.3 Jumper configuration...................................................................................................... 3 - 13  
CHAPTER 4 THEORY OF DEVICE OPERATION ......................................................... 4 - 1  
4.1  
4.2  
Outline............................................................................................................................ 4 - 1  
Subassemblies ................................................................................................................ 4 - 1  
4.2.1 Disk ................................................................................................................................ 4 - 1  
4.2.2 Head ............................................................................................................................... 4 - 2  
4.2.3 Spindle............................................................................................................................ 4 - 2  
4.2.4 Actuator.......................................................................................................................... 4 - 2  
4.2.5 Air filter.......................................................................................................................... 4 - 3  
4.3  
4.4  
4.5  
Circuit Configuration...................................................................................................... 4 - 4  
Power-on Sequence ........................................................................................................ 4 - 6  
Self-calibration ............................................................................................................... 4 - 8  
4.5.1 Self-calibration contents ................................................................................................. 4 - 8  
4.5.2 Execution timing of self-calibration ............................................................................... 4 - 9  
4.5.3 Command processing during self-calibration ................................................................. 4 - 9  
4.6  
Read/write Circuit........................................................................................................... 4 - 10  
4.6.1 Read/write preamplifier (PreAMP)................................................................................. 4 - 10  
4.6.2 Write circuit.................................................................................................................... 4 - 10  
4.6.3 Read circuit..................................................................................................................... 4 - 11  
4.6.4 Synthesizer circuit .......................................................................................................... 4 - 12  
4.7  
Servo Control ................................................................................................................. 4 - 12  
4.7.1 Servo control circuit ....................................................................................................... 4 - 13  
4.7.2 Data-surface servo format............................................................................................... 4 - 16  
4.7.3 Servo frame format......................................................................................................... 4 - 16  
4.7.4 Actuator motor control ................................................................................................... 4 - 18  
4.7.5 Spindle motor control..................................................................................................... 4 - 19  
CHAPTER 5 INTERFACE................................................................................................... 5 - 1  
5.1  
Physical Interface ........................................................................................................... 5 - 2  
5.1.1 Interface signals.............................................................................................................. 5 - 2  
5.1.2 Signal assignment on the connector ............................................................................... 5 - 3  
5.2  
Logical Interface............................................................................................................. 5 - 6  
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C141-E093-01EN  
5.2.1 I/O registers .................................................................................................................... 5 - 6  
5.2.2 Command block registers............................................................................................... 5 - 8  
5.2.3 Control block registers ................................................................................................... 5 - 13  
5.3  
Host Commands ............................................................................................................. 5 - 13  
5.3.1 Command code and parameters...................................................................................... 5 - 14  
5.3.2 Command descriptions................................................................................................... 5 - 16  
5.3.3 Error posting................................................................................................................... 5 - 61  
5.4  
Command Protocol......................................................................................................... 5 - 62  
5.4.1 Data transferring commands from device to host ........................................................... 5 - 62  
5.4.2 Data transferring commands from host to device ........................................................... 5 - 64  
5.4.3 Commands without data transfer.................................................................................... 5 - 66  
5.4.4 Other commands............................................................................................................. 5 - 67  
5.4.5 DMA data transfer commands........................................................................................ 5 - 67  
5.5  
Ultra DMA feature set .................................................................................................... 5 - 69  
5.5.1 Overview ........................................................................................................................ 5 - 69  
5.5.2 Phases of operation......................................................................................................... 5 - 70  
5.5.3 Ultra DMA data in commands........................................................................................ 5 - 70  
5.5.3.1 Initiating an Ultra DMA data in burst............................................................................. 5 - 70  
5.5.3.2 The data in transfer......................................................................................................... 5 - 71  
5.5.3.3 Pausing an Ultra DMA data in burst............................................................................... 5 - 71  
5.5.3.4 Terminating an Ultra DMA data in burst........................................................................ 5 - 72  
5.5.4 Ultra DMA data out commands...................................................................................... 5 - 74  
5.5.4.1 Initiating an Ultra DMA data out burst........................................................................... 5 - 74  
5.5.4.2 The data out transfer....................................................................................................... 5 - 75  
5.5.4.3 Pausing an Ultra DMA data out burst............................................................................. 5 - 75  
5.5.4.4 Terminating an Ultra DMA data out burst...................................................................... 5 - 76  
5.5.5 Ultra DMA CRC rules.................................................................................................... 5 - 78  
5.5.6 Series termination required for Ultra DMA .................................................................... 5 - 79  
5.6  
Timing............................................................................................................................ 5 - 80  
5.6.1 PIO data transfer............................................................................................................. 5 - 80  
5.6.2 Multiword data transfer .................................................................................................. 5 - 81  
5.6.3 Ultra DMA data transfer................................................................................................. 5 - 82  
5.6.3.1 Initiating an Ultra DMA data in burst............................................................................. 5 - 82  
5.6.3.2 Ultra DMA data burst timing requirements .................................................................... 5 - 83  
5.6.3.3 Sustained Ultra DMA data in burst................................................................................. 5 - 85  
5.6.3.4 Host pausing an Ultra DMA data in burst ...................................................................... 5 - 86  
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ix  
5.6.3.5 Device terminating an Ultra DMA data in burst............................................................. 5 - 87  
5.6.3.6 Host terminating an Ultra DMA data in burst................................................................. 5 - 88  
5.6.3.7 Initiating an Ultra DMA data out burst........................................................................... 5 - 89  
5.6.3.8 Sustained Ultra DMA data out burst............................................................................... 5 - 90  
5.6.3.9 Device pausing an Ultra DMA data out burst................................................................. 5 - 91  
5.6.3.10 Host terminating an Ultra DMA data out burst............................................................... 5 - 92  
5.6.3.11 Device terminating an Ultra DMA data in burst............................................................. 5 - 93  
5.6.4 Power-on and reset ......................................................................................................... 5 - 94  
CHAPTER 6 OPERATIONS ................................................................................................ 6 - 1  
6.1  
Device Response to the Reset......................................................................................... 6 - 1  
6.1.1 Response to power-on .................................................................................................... 6 - 2  
6.1.2 Response to hardware reset ............................................................................................ 6 - 3  
6.1.3 Response to software reset.............................................................................................. 6 - 4  
6.1.4 Response to diagnostic command .................................................................................. 6 - 5  
6.2  
Address Translation........................................................................................................ 6 - 6  
6.2.1 Default parameters.......................................................................................................... 6 - 6  
6.2.2 Logical address............................................................................................................... 6 - 7  
6.3  
Power Save..................................................................................................................... 6 - 8  
6.3.1 Power save mode............................................................................................................ 6 - 8  
6.3.2 Power commands ........................................................................................................... 6 - 10  
6.4  
Defect Management........................................................................................................ 6 - 10  
6.4.1 Spare area ....................................................................................................................... 6 - 11  
6.4.2 Alternating defective sectors .......................................................................................... 6 - 11  
6.5  
Read-Ahead Cache ......................................................................................................... 6 - 13  
6.5.1 Data buffer configuration ............................................................................................... 6 - 13  
6.5.2 Caching operation........................................................................................................... 6 - 14  
6.5.3 Usage of read segment.................................................................................................... 6 - 15  
6.6  
Write Cache.................................................................................................................... 6 - 20  
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C141-E093-01EN  
FIGURES  
page  
1.1  
2.1  
2.2  
2.3  
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
3.7  
3.8  
3.9  
3.10  
3.11  
Current fluctuation (Typ.) when power is turned on....................................................... 1 - 7  
Disk drive outerview ...................................................................................................... 2 - 1  
1 drive system configuration .......................................................................................... 2 - 3  
2 drives configuration..................................................................................................... 2 - 3  
Dimensions..................................................................................................................... 3 - 2  
Orientation...................................................................................................................... 3 - 3  
Limitation of side-mounting........................................................................................... 3 - 4  
Mounting frame structure ............................................................................................... 3 - 4  
Surface temperature measurement points ....................................................................... 3 - 5  
Service area .................................................................................................................... 3 - 6  
Connector locations........................................................................................................ 3 - 7  
Cable connections........................................................................................................... 3 - 8  
Power supply connector pins (CN1)............................................................................... 3 - 9  
Cable configuration ........................................................................................................ 3 - 10  
Cable type detection using CBLID- signal  
(Host sensing the condition of the CBLID- signal) ........................................................ 3 - 11  
3.12  
Cable type detection using IDENTIFY DEVICE data  
(Device sensing the condition of the CBLID- signal)..................................................... 3 - 11  
3.13  
3.14  
3.15  
3.16  
3.17  
3.18  
4.1  
Jumper location .............................................................................................................. 3 - 12  
Factory default setting .................................................................................................... 3 - 13  
Jumper setting of master or slave device ........................................................................ 3 - 13  
Jumper setting of Cable Select ....................................................................................... 3 - 14  
Example (1) of Cable Select ........................................................................................... 3 - 14  
Example (2) of Cable Select ........................................................................................... 3 - 14  
Head structure................................................................................................................. 4 - 2  
MPE3xxxAE Block diagram.......................................................................................... 4 - 5  
Power-on operation sequence......................................................................................... 4 - 7  
Block diagram of servo control circuit ........................................................................... 4 - 13  
Physical sector servo configuration on disk surface ....................................................... 4 - 14  
96 servo frames in each track ......................................................................................... 4 - 17  
Execution example of READ MULTIPLE command .................................................... 5 - 19  
Read Sector(s) command protocol.................................................................................. 5 - 63  
Protocol for command abort........................................................................................... 5 - 64  
4.2  
4.3  
4.4  
4.5  
4.6  
5.1  
5.2  
5.3  
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xi  
5.4  
WRITE SECTOR(S) command protocol........................................................................ 5 - 65  
Protocol for the command execution without data transfer ............................................ 5 - 66  
Normal DMA data transfer............................................................................................. 5 - 68  
Ultra DMA termination with pull-up or pull-down ........................................................ 5 - 79  
PIO data transfer timing.................................................................................................. 5 - 80  
Multiword DMA data transfer timing (mode 2) ............................................................. 5 - 81  
Initiating an Ultra DMA data in burst............................................................................. 5 - 82  
Sustained Ultra DMA data in burst................................................................................. 5 - 85  
Host pausing an Ultra DMA data in burst ...................................................................... 5 - 86  
Device terminating an Ultra DMA data in burst............................................................. 5 - 87  
Host terminating an Ultra DMA data in burst................................................................. 5 - 88  
Initiating an Ultra DMA data out burst........................................................................... 5 - 89  
Sustained Ultra DMA data out burst............................................................................... 5 - 90  
Device pausing an Ultra DMA data out burst................................................................. 5 - 91  
Host terminating an Ultra DMA data out burst............................................................... 5 - 92  
Device terminating an Ultra DMA data out burst........................................................... 5 - 93  
Power-on Reset Timing.................................................................................................. 5 - 94  
Response to power-on .................................................................................................... 6 - 2  
Response to hardware reset ............................................................................................ 6 - 3  
Response to software reset.............................................................................................. 6 - 4  
Response to diagnostic command .................................................................................. 6 - 5  
Address translation (example in CHS mode).................................................................. 6 - 7  
Address translation (example in LBA mode) ................................................................. 6 - 8  
Sector slip processing..................................................................................................... 6 - 11  
Alternate cylinder assignment ........................................................................................ 6 - 12  
Data buffer configuration ............................................................................................... 6 - 13  
5.5  
5.6  
5.7  
5.8  
5.9  
5.10  
5.11  
5.12  
5.13  
5.14  
5.15  
5.16  
5.17  
5.18  
5.19  
5.20  
6.1  
6.2  
6.3  
6.4  
6.5  
6.6  
6.7  
6.8  
6.9  
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C141-E093-01EN  
TABLES  
page  
1.1  
1.2  
1.3  
1.4  
1.5  
1.6  
3.1  
3.2  
4.1  
4.2  
5.1  
5.2  
5.3  
5.4  
5.5  
5.6  
5.7  
5.8  
5.9  
5.10  
5.11  
5.12  
5.13  
5.14  
5.15  
6.1  
Specifications ................................................................................................................. 1 - 4  
Model names and product numbers................................................................................ 1 - 5  
Current and power dissipation........................................................................................ 1 - 6  
Environmental specifications.......................................................................................... 1 - 8  
Acoustic noise specification ........................................................................................... 1 - 8  
Shock and vibration specification................................................................................... 1 - 9  
Surface temperature measurement points and standard values ....................................... 3 - 5  
Cable connector specifications ....................................................................................... 3 - 8  
Self-calibration execution timechart ............................................................................... 4 - 9  
Write clock frequency and transfer rate of each zone ..................................................... 4 - 12  
Interface signals.............................................................................................................. 5 - 2  
Signal assignment on the interface connector................................................................. 5 - 3  
I/O registers .................................................................................................................... 5 - 7  
Command code and parameters...................................................................................... 5 - 14  
Information to be read by IDENTIFY DEVICE command ............................................ 5 - 30  
Features register values and settable modes ................................................................... 5 - 35  
Diagnostic code .............................................................................................................. 5 - 39  
Features Register values (subcommands) and functions ................................................ 5 - 49  
Format of device attribute value data.............................................................................. 5 - 52  
Format of insurance failure threshold value data............................................................ 5 - 53  
SMART error log data format ........................................................................................ 5 - 56  
SMART self test log data format.................................................................................... 5 - 58  
Command code and parameters...................................................................................... 5 - 61  
Recommended series termination for Ultra DMA .......................................................... 5 - 79  
Ultra DMA data burst timing requirements .................................................................... 5 - 83  
Default parameters.......................................................................................................... 6 - 6  
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CHAPTER 1  
DEVICE OVERVIEW  
1.1  
1.2  
1.3  
1.4  
1.5  
1.6  
1.7  
1.8  
1.9  
Features  
Device Specifications  
Power Requirements  
Environmental Specifications  
Acoustic Noise  
Shock and Vibration  
Reliability  
Error Rate  
Media Defects  
Overview and features are described in this chapter, and specifications and power requirement are  
described.  
The MPE3xxxAE series are a 3.5-inch hard disk drive with a built-in ATA controller. The disk drive is  
compact and reliable.  
1.1  
Features  
1.1.1  
(1)  
Functions and performance  
Compact  
The disk has 1 or 2 disks of 95 mm (3.5 inches) diameter, and its height is 26.1 mm (1 inch).  
(2)  
(3)  
Large capacity  
The disk drive can record up to 8.46 GB (formatted) on one disk using the 48/51 EPR4ML  
recording method and 15 recording zone technology. The MPE3xxxAE series have a  
formatted capacity of 4.33 GB to 17.34 GB respectively.  
High-speed Transfer rate  
The disk drive has an internal data rate up to 40.7 MB/s. The disk drive supports an external  
data rate up to 16.7 MB/s or 66.6 MB/s (ultra DMA mode 4).  
C141-E093-01EN  
1 - 1  
(4)  
Average positioning time  
Use of a rotary voice coil motor in the head positioning mechanism greatly increases the  
positioning speed. The average positioning time is 9.5 ms (at read).  
1.1.2  
Adaptability  
(1)  
Power save mode  
The power save mode feature for idle operation, stand by and sleep modes makes the disk  
drive ideal for applications where power consumption is a factor.  
(2)  
(3)  
Wide temperature range  
The disk drive can be used over a wide temperature range (5°C to 55°C).  
Low noise and vibration  
In Ready status, the noise of the disk drive is only about 3.5 bels (MPE3173AE, Typical  
Sound Power per ISO7779 and ISO9296).  
1.1.3  
Interface  
(1)  
Connection to interface  
With the built-in ATA interface controller, the disk drive can be connected to an ATA  
interface of a personal computer.  
(2)  
(3)  
512KB data buffer  
The disk drive uses a 512KB data buffer to transfer data between the host and the disk media.  
In combination with the read-ahead cache system described in item (3) and the write cache  
described in item (6), the buffer contributes to efficient I/O processing.  
Read-ahead cache system  
After the execution of a disk read command, the disk drive automatically reads the subsequent  
data block and writes it to the data buffer (read ahead operation). This cache system enables  
fast data access. The next disk read command would normally cause another disk access.  
But, if the read ahead data corresponds to the data requested by the next read command, the  
data in the buffer can be transferred instead.  
(4)  
Master/slave  
The disk drive can be connected to ATA interface as daisy chain configuration. Drive 0 is a  
master device, drive 1 is a slave device.  
1 - 2  
C141-E093-01EN  
(5)  
(6)  
Error correction and retry by ECC  
If a recoverable error occurs, the disk drive itself attempts error recovery. The 40 bytes ECC  
has improved buffer error correction for correctable data errors.  
Write cache  
When the disk drive receives a write command, the disk drive posts the command completion  
at completion of transferring data to the data buffer completion of writing to the disk media.  
This feature reduces the access time at writing.  
C141-E093-01EN  
1 - 3  
1.2  
Device Specifications  
1.2.1  
Specifications summary  
Table 1.1 shows the specifications of the disk drive.  
Table 1.1 Specifications  
MPE3043AE  
MPE3084AE  
MPE3173AE  
Formatted Capacity (*1)  
4.33 GB  
8.45 GB  
17.34 GB  
Number of Disks  
Number of Heads  
1
1
1
2
4
2
Number of Cylinders  
17,301 + 140  
(User + Alternate & SA)  
Bytes per Sector  
Recording Method  
Track Density  
512  
48/51 EPR4ML  
18,250 TPI  
352,728 BPI  
5,400 rpm  
Bit Density  
Rotational Speed  
Average Latency  
Positioning time  
5.56 ms  
•
•
•
Minimum  
Average  
Maximum  
1.5 ms typical  
(Read) 9.5 ms typical, (Write) 10.5 ms typical  
(Read) 18 ms typical, (Write) 19 ms typical  
Start/Stop time  
• Start (0 rpm to Drive Read)  
Typical: 8 sec., Maximum: 16 sec.  
Typical: 20 sec., Maximum: 30 sec.  
•
Stop (at Power Down)  
Interface  
ATA–4  
(Maximum Cable length: 0.46 m)  
Data Transfer Rate  
•
•
To/From Media  
To/From Host  
20.3 to 34.4 MB/s  
16.7 MB/s Max. (burst PIO mode 4, burst DMA mode 2), 66.6 MB/s Max.  
(burst ultra DMA mode 4)  
Data buffer  
512 KB  
Physical Dimensions  
(Height ´ Width ´ Depth)  
26.1 mm max. × 101.6 mm × 146.0 mm  
(1.03” max. × 4.0” × 5.75”)  
Weight  
620 g  
*1: Capacity under the LBA mode.  
Under the CHS mode (normal BIOS specification), formatted capacity, number of cylinders, number of heads, and number of  
sectors are as follows.  
Model  
Formatted Capacity  
4,334.70 MB  
No. of Cylinder  
8,959  
No. of Heads No. of Sectors  
MPE3043AE  
MPE3084AE  
MPE3173AE  
15  
16  
16  
63  
63  
63  
8,455.20 MB  
16,383  
8,455.20 MB  
16,383  
1 - 4  
C141-E093-02EN  
1.2.2  
Model and product number  
Table 1.2 lists the model names and product numbers.  
Table 1.2 Model names and product numbers  
Capacity  
Mounting  
Screw  
Model Name  
Order No.  
Remarks  
(user area)  
4.33 GB  
8.45 GB  
MPE3043AE  
MPE3084AE  
MPE3173AE  
No. 6-32UNC CA05743-B311  
No. 6-32UNC CA05743-B321  
—
—
—
17.34 GB No. 6-32UNC CA05743-B341  
1.3  
Power Requirements  
Input Voltage  
(1)  
(2)  
·
·
+ 5 V ±5 %  
+ 12 V ±8 %  
Ripple  
+12 V  
200 mV (peak to peak) 100 mV (peak to peak)  
DC to 1 MHz DC to 1 MHz  
+5 V  
Maximum  
Frequency  
C141-E093-01EN  
1 - 5  
(3)  
Current Requirements and Power Dissipation  
Table 1.3 lists the current and power dissipation.  
Table 1.3 Current and power dissipation  
Typical RMS current (*1) [mA]  
+12 V  
Mode of Operation  
Typical Power (*2) [watts]  
+5 V  
Model  
MPE3043AE MPE3084AE MPE3173AE All Models MPE3043AE MPE3084AE MPE3173AE  
Spin up  
1800 peak  
1800 peak  
1800 peak  
540  
21.9  
21.9  
21.9  
640 peak  
Idle (Ready) (*3)  
R/W (On Track) (*4)  
Seek (Random) (*5)  
Standby  
140  
180  
270  
7.0  
140  
180  
270  
7.0  
170  
210  
300  
7.0  
420  
450  
450  
185  
185  
3.8  
4.4  
5.5  
1.0  
1.0  
3.8  
4.4  
5.5  
1.0  
1.0  
4.1  
4.8  
5.9  
1.0  
1.0  
Sleep  
7.0  
7.0  
7.0  
*1 Current is typical rms except for spin up.  
*2 Power requirements reflect nominal values for +12V and +5V power.  
*3 Idle mode is in effect when the drive is not reading, writing, seeking, or executing any commands. A portion of the R/W circuitry is powered  
down, the spindle motor is up to speed and the Drive ready condition exists.  
*4 R/W mode is defined as 50% read operations and 50% write operations on a single physical track.  
*5 Seek mode is defined as continuous random seek operations with minimum controller delay.  
1 - 6  
C141-E093-01EN  
(4)  
Current fluctuation (Typ.) when power is turned on  
[A]  
0.5  
+5VDC  
(0.5A/div)  
0.0  
[A]  
1.5  
1.0  
0.5  
+12VDC  
(0.5A/div)  
0.0  
0
1
2
3
4
5
6
7
8
[seconds]  
Figure 1.1 Current fluctuation (Typ.) when power is turned on  
(5)  
Power on/off sequence  
The voltage detector circuit monitors +5 V and +12 V. The circuit does not allow a write  
signal if either voltage is abnormal. This prevents data from being destroyed and eliminates  
the need to be concerned with the power on/off sequence.  
C141-E093-01EN  
1 - 7  
1.4  
Environmental Specifications  
Table 1.4 lists the environmental specifications.  
Table 1.4 Environmental specifications  
Temperature  
• Operating  
5°C to 55°C (ambient)  
5°C to 60°C (disk enclosure surface)  
• Non-operating  
–40°C to 60°C  
• Thermal Gradient  
20°C/hour or less  
Humidity  
• Operating  
• Non-operating  
• Maximum Wet Bulb  
8% to 80%RH (Non-condensing)  
5% to 85%RH (Non-condensing)  
29°C  
Altitude (relative to sea level)  
• Operating  
–60 to 3,000 m (–200 to 10,000 ft)  
–60 to 12,000 m (–200 to 40,000 ft)  
• Non-operating  
1.5  
Acoustic Noise  
Table 1.5 lists the acoustic noise specification.  
Table 1.5 Acoustic noise specification  
MPE3043AE  
MPE3084AE  
Sound Power  
per ISO 7779 and  
ISO9296  
Model  
MPE3173AE  
3.5 bels  
Idle mode (DRIVE  
READY)  
3.4 bels  
(Typical at 1m)  
Seek mode (Random)  
4.0 bels  
29 dBA  
4.1 bels  
30 dBA  
Idle mode (DRIVE  
READY)  
Sound Pressure  
(Typical at 1m)  
Seek mode (Random)  
35 dBA  
36 dBA  
1 - 8  
C141-E093-01EN  
1.6  
Shock and Vibration  
Table 1.6 lists the shock and vibration specification.  
Table 1.6 Shock and vibration specification  
Vibration (swept sine, one octave per minute)  
• Operating  
5 to 300 Hz, 0.5G-0-peak  
(without non-recovered errors)  
5 to 400 Hz, 4G-0-peak (no damage)  
• Non-operating  
Shock (half-sine pulse, operating)  
• 2 ms duration  
30G (without non-recovered error)  
10G (without non-recovered error)  
• 11 ms duration  
Shock (half-sine pulse, non-operating)  
• 2 ms duration  
250G (typical, no damage)  
75G (no damage)  
• 11 ms duration  
1.7  
Reliability  
(1)  
Mean time between failures (MTBF)  
The mean time between failures (MTBF) is 500,000 POH (power on hours) or more  
(operation: 24 hours/day, 7 days/week).  
This does not include failures occurring during the first three months after installation.  
MTBF is defined as follows:  
Total operation time in all fields  
MTBF=  
(H)  
number of device failure in all fields  
"Disk drive defects" refers to defects that involve repair, readjustment, or replacement. Disk  
drive defects do not include failures caused by external factors, such as damage caused by  
handling, inappropriate operating environments, defects in the power supply host system, or  
interface cable.  
(2)  
(3)  
Mean time to repair (MTTR)  
The mean time to repair (MTTR) is 30 minutes or less, if repaired by a specialist maintenance  
staff member.  
CSS cycle  
The number of CSS must be less than 40,000.  
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1 - 9  
(4)  
Service life  
In situations where management and handling are correct, the disk drive requires no overhaul  
for five years when the DE surface temperature is less than 48°C. When the DE surface  
temperature exceeds 48°C, the disk drives requires no overhaul for five years or 20,000 hours  
of operation, whichever occurs first. Refer to item (3) in Subsection 3.2 for the measurement  
point of the DE surface temperature.  
(5)  
1.8  
(1)  
Data assurance in the event of power failure  
Except for the data block being written to, the data on the disk media is assured in the event of  
any power supply abnormalities. This does not include power supply abnormalities during  
disk media initialization (formatting) or processing of defects (alternative block assignment).  
Error Rate  
Known defects, for which alternative blocks can be assigned, are not included in the error rate  
count below. It is assumed that the data blocks to be accessed are evenly distributed on the  
disk media.  
Unrecoverable read error  
Read errors that cannot be recovered by read retries without user's retry and ECC corrections  
shall occur no more than 10 times when reading data of 1015 bits. Read retries are executed  
according to the disk drive's error recovery procedure, and include read retries accompanying  
head offset operations.  
(2)  
Positioning error  
Positioning (seek) errors that can be recovered by one retry shall occur no more than 10 times  
in 107 seek operations.  
1.9  
Media Defects  
Defective sectors are replaced with alternates when the disk is formatted prior to shipment  
from the factory (low level format). Thus, the host sees a defect-free device.  
Alternate sectors are automatically accessed by the disk drive. The user need not be concerned  
with access to alternate sectors.  
Chapter 6 describes the low level format at shipping.  
1 - 10  
C141-E093-01EN  
CHAPTER 2  
DEVICE CONFIGURATION  
2.1  
2.2  
Device Configuration  
System Configuration  
2.1  
Device Configuration  
Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write  
preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle  
motors actuators, and a circulating air filter.  
Figure 2.1 Disk drive outerview  
C141-E093-01EN  
2 - 1  
(1)  
Disk  
The outer diameter of the disk is 95 mm. The inner diameter is 25 mm. The number of disks  
used varies with the model, as described below. The disks are rated at over 40,000 start/stop  
operations.  
MPE3043AE: 1 disk  
MPE3084AE: 1 disk  
MPE3173AE: 2 disks  
(2)  
Head  
The heads are of the contact start/stop (CSS) type. The head touches the disk surface while the  
disk is not rotating and automatically lifts when the disk starts.  
(3)  
(4)  
Spindle motor  
The disks are rotated by a direct drive Hall-less DC motor.  
Actuator  
The actuator uses a revolving voice coil motor (VCM) structure which consumes low power  
and generates very little heat. The head assembly at the tip of the actuator arm is controlled  
and positioned by feedback of the servo information read by the read/write head. If the power  
is not on or if the spindle motor is stopped, the head assembly stays in the specific CSS zone  
on the disk and is fixed by a mechanical lock.  
(5)  
Air circulation system  
The disk enclosure (DE) is sealed to prevent dust and dirt from entering. The disk enclosure  
features a closed loop air circulation system that relies on the blower effect of the rotating  
disk. This system continuously circulates the air through the recirculation filter to maintain  
the cleanliness of the air in the disk enclosure.  
(6)  
(7)  
Read/write circuit  
The read/write circuit uses a LSI chip for the read/write preamplifier. It improves data  
reliability by preventing errors caused by external noise.  
Controller circuit  
The controller circuit consists of an LSI chip to improve reliability. The high-speed  
microprocessor unit (MPU) achieves a high-performance AT controller.  
2 - 2  
C141-E093-01EN  
2.2  
System Configuration  
ATA interface  
2.2.1  
Figures 2.2 and 2.3 show the ATA interface system configuration. The drive has a 40-pin PC  
AT interface connector and supports the PIO transfer till 16.7 MB/s (PIO mode 4), the DMA  
transfer till 16.7 MB/s (Multiword DMA mode 2), and the ultra DMA transfer till 66.6 MB/s  
(Ultra DMA mode 4).  
2.2.2  
1 drive connection  
HA  
Host  
Disk drive  
(Host adaptor)  
ATA interface  
AT bus  
(Host interface)  
Figure 2.2 1 drive system configuration  
2.2.3  
2 drives connection  
HA  
Host  
Disk drive #0  
(Host adaptor)  
AT bus  
(Host interface)  
Disk drive #1  
ATA interface  
Note:  
When the drive that is not conformed to ATA is connected to the disk drive is above  
configuration, the operation is not guaranteed.  
Figure 2.3 2 drives configuration  
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2 - 3  
IMPORTANT  
HA (host adapter) consists of address decoder, driver, and receiver.  
ATA is an abbreviation of "AT attachment". The disk drive is  
conformed to the ATA-4 interface.  
At high speed data transfer (PIO mode 3, mode 4, DMA mode 2 or  
ultra DMA mode 4), occurrence of ringing or crosstalk of the signal  
lines (AT bus) between the HA and the disk drive may be a great  
cause of the obstruction of system reliability. Thus, it is necessary  
that the capacitance of the signal lines including the HA and cable  
does not exceed the ATA-3 and ATA-4 standard, and the cable  
length between the HA and the disk drive should be as short as  
possible.  
2 - 4  
C141-E093-01EN  
CHAPTER 3  
INSTALLATION CONDITIONS  
3.1  
3.2  
3.3  
3.4  
Dimensions  
Mounting  
Cable Connections  
Jumper Settings  
3.1  
Dimensions  
Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw  
holes. All dimensions are in mm.  
C141-E093-01EN  
3 - 1  
Figure 3.1 Dimensions  
3 - 2  
C141-E093-02EN  
3.2  
Mounting  
(1)  
Orientation  
Figure 3.2 illustrates normal orientation for the disk drive. The disk drives can be mounted in  
any orientation.  
Horizontal mounting with the PCB facing down  
Figure 3.2 Orientation  
(2)  
Frame  
The disk enclosure (DE) body is connected to signal ground (SG) and the mounting frame is  
also connected to signal ground. These are electrically shorted.  
Note:  
Use No.6-32UNC screw for the mounting screw and the screw length should satisfy the  
specification in Figure 3.4.  
(3)  
Limitation of side-mounting  
When the disk drive is mounted using the screw holes on both side of the disk drive, use two  
screw holes shown in Figure 3.3.  
Do not use the center hole. For screw length, see Figure 3.4.  
C141-E093-01EN  
3 - 3  
Use these screw  
holes  
Do not use this screw holes  
Figure 3.3 Limitation of side-mounting  
Side surface  
mounting  
2.5  
2.5  
2.5  
Bottom surface mounting  
DE  
DE  
2
PCA  
B
A
Frame of system  
cabinet  
Frame of system  
cabinet  
4.5 or  
less  
Screw  
Screw  
5.0 or less  
Details of A  
Details of B  
Figure 3.4 Mounting frame structure  
3 - 4  
C141-E093-01EN  
(4)  
Ambient temperature  
The temperature conditions for a disk drive mounted in a cabinet refer to the ambient  
temperature at a point 3 cm from the disk drive. Pay attention to the air flow to prevent the  
DE surface temperature from exceeding 60°C.  
Provide air circulation in the cabinet such that the PCA side, in particular, receives sufficient  
cooling. To check the cooling efficiency, measure the surface temperatures of the DE.  
Regardless of the ambient temperature, this surface temperature must meet the standards listed  
in Table 3.1. Figure 3.5 shows the temperature measurement point.  
1
Figure 3.5 Surface temperature measurement points  
Table 3.1 Surface temperature measurement points and standard values  
No.  
1
Measurement point  
Temperature  
60°C max  
DE cover  
C141-E093-01EN  
3 - 5  
(5)  
Service area  
Figure 3.6 shows how the drive must be accessed (service areas) during and after installation.  
- Mounting screw hole  
[Q side]  
- Mounting screw hole  
[P side]  
- Cable connection  
- Mode setting switches  
[R side]  
- Mounting screw hole  
Figure 3.6 Service area  
(6)  
External magnetic fields  
Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure  
that the disk drive is not affected by external magnetic fields.  
3 - 6  
C141-E093-01EN  
3.3  
Cable Connections  
Device connector  
3.3.1  
The disk drive has the connectors and terminals listed below for connecting external devices.  
Figure 3.7 shows the locations of these connectors and terminals.  
·
·
Power supply connector (CN1)  
ATA interface connector (CN1)  
Power supply  
connector (CN1)  
Mode  
Setting  
Pins  
ATA  
interface  
connector  
Figure 3.7 Connector locations  
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3 - 7  
3.3.2  
Cable connector specifications  
Table 3.2 lists the recommended specifications for the cable connectors for Host system that  
do not support Ultra DMA modes greater than mode 2.  
For Host system that support Ultra DMA modes greater than mode 2, it is recommended to  
use the 80-conductor cable assembly. The 80-conductor cable assembly is manufactured by  
AMP or 3M.  
Table 3.2 Cable connector specifications  
Name  
Cable socket  
Model  
Manufacturer  
Fujitsu  
FCN-707B040-AU/B  
(closed-end type)  
ATA interface cable  
(40-pin, CN1)  
Cable socket  
FCN-707B040-AU/O  
Fujitsu  
(through-end type)  
Cable socket housing  
Contact  
1-480424-0  
60617-4  
AMP  
AMP  
Power supply cable  
(CN1)  
Note :  
The cable of twisted pairs and neighboring line separated individually is not allowed to use  
for the host interface cable. It is because that the location of signal lines in these cables is  
not fixed, and so the problem on the crosstalk among signal lines may occur.  
It is recommended to use the ribbon cable for ATA interface that cable length is less than  
18 inch (46 cm) and cable capacitance is less than 35 pico farad. Also it is recommended  
to use AWG18 power supply cable.  
3.3.3  
Device connection  
Figure 3.8 shows how to connect the devices.  
ATA interface cable  
Power supply cable  
Disk Drive #0  
DC  
power supply  
Host system  
Disk Drive #1  
Figure 3.8 Cable connections  
3 - 8  
C141-E093-01EN  
3.3.4  
Power supply connector (CN1)  
Figure 3.9 shows the pin assignment of the power supply connector (CN1).  
1
2
3
4
+12VDC  
+12V RETURN  
1
2
3
4
+5V RETURN  
+5VDC  
(Viewed from cable side)  
Figure 3.9 Power supply connector pins (CN1)  
3.3.5  
System configuration for Ultra DMA  
Host system that support Ultra DMA transfer modes greater than mode 2 shall not share I/O  
ports. They shall provide separate drivers and separate receivers for each cable.  
a) The 80-conductor cable assemblies shall be used for systems operating at Ultra DMA  
modes greater than 2. The 80-coductor cable assemblies may be used in place of 40-  
conductor cable assemblies to improve signal quality for data transfer modes that do not  
require an 80-conductor cable assembly. And the 80-conductor cable assembly shall meet  
the following specifications.  
1) The assembly utilizes a fine pitch cable to double the number of conductors available  
to the 40-pin connector. The grounds assigned by the interface are commoned with  
the additional 40 conductors to provide a ground between each signal line and  
provide the effect of a common ground plane.  
2) The cable assembly may contain up to 3 connectors which shall be uniquely colored  
as follows. All connectors shall have position 20 blocked.  
·
The System Board Connector shall have a Blue base and Black retainer. Pin 34  
(PDIAG-: CBLID-) shall be connected to ground and shall not be wired to the  
cable assembly.  
·
·
Connector Device “0” shall have a Black base and Black retainer.  
Connector Device “1” shall have a Gray base and Black retainer. Pin 28 (CSEL)  
shall not be connected to the cable (contact 28 may be removed to meet this  
requirement).  
·
The cable assembly may be printed with connector identifiers.  
3) Typical cable characteristics are shown as follows.  
·
·
·
Cable: AWG 30 (pitch: 0.635 mm)  
Single Ended impedance: typical 80 W.  
Cable capacitance: typical 57 pF/m  
4) The dimensions are shown in Figure 3.10.  
C141-E093-01EN  
3 - 9  
254.0 to 457.2 mm  
(10 to 18 inch)  
127.0 to 304.8 mm  
(5 to 12 inch)  
101.6 to 152.4 mm  
(4 to 6 inch)  
Pin 40 (Ground)  
Pin 34  
open  
Pin 34 contact  
(PDIAG-:CBLID- signal)  
Pin 30 (Ground)  
Symbolizes Pin 34  
Conductor being cut  
Pin 26 (Ground)  
Pin 24 (Ground)  
Pin 22 (Ground)  
Pin 19 (Ground)  
Position 1  
Pin 2 (Ground)  
System Board  
Connector  
Connector 1  
Connector 2  
Figure 3.10 Cable configuration  
b) Host system that do not support Ultra DMA modes greater than mode 2 shall not connect  
to the PDIAG-:CBLID- signal.  
c) Host system that do support Ultra DMA modes greater than mode 2 shall either connect  
directly to the device without using a cable assembly, or determine the cable assembly  
type. Determining the cable assembly type may be done either by the host sensing the  
condition of the PDIAG-:CBLID- signal (see Figure 3.11), or by relying on information  
from the device (see Figure 3.12). Hosts that rely on information from the device shall  
have a 0.047 mF capacitor connected from the PDIAG-:CBLID- signal to ground. The  
tolerance on this capacitor shall be 20% or less.  
3 - 10  
C141-E093-01EN  
Host detected CBLID- above VIH  
PDIAG-: CBLID- conductor  
Host detected CBLID- below VIL  
open  
PDIAG-: CBLID- conductor  
Host  
Device 1  
Device 0  
Host  
Device 1  
with 80-conductor cable  
Device 0  
with 40-conductor cable  
Figure 3.11 Cable type detection using CBLID- signal  
(Host sensing the condition of the CBLID- signal)  
IDENTIFY DEVICE information  
word 93 bit13:0  
IDENTIFY DEVICE information  
word 93 bit13:1  
Device detected CBLID- below VIL  
Device detected CBLID- above VIH  
open  
PDIAG-:CBLID- conductor  
PDIAG-:CBLID- conductor  
0.047 mF  
±10% or  
±20%  
0.047 mF  
±10% or  
±20%  
Host  
Device 1  
Device 0  
Host  
Device 1  
Device 0  
with 40-conductor cable  
with 80-conductor cable  
Figure 3.12 Cable type detection using IDENTIFY DEVICE data  
(Device sensing the condition of the CBLID- signal)  
C141-E093-01EN  
3 - 11  
3.4  
Jumper Settings  
3.4.1  
Location of setting jumpers  
Figure 3.13 shows the location of the jumpers to select drive configuration and functions.  
DC Power Connector  
Interface Connector  
40  
2
1
1
Figure 3.13 Jumper location  
3 - 12  
C141-E093-01EN  
3.4.2  
Factory default setting  
Figure 3.14 shows the default setting position at the factory. (Master device setting)  
DC Power Connector  
Interface Connector  
Figure 3.14 Factory default setting  
3.4.3  
Jumper configuration  
Device type  
Master device (device #0) or slave device (device #1) is selected.  
(1)  
2
4
6 8  
2
4
6 8  
= shorted  
1
3
5 7  
9
1
3
5 7  
9
(a) Master device  
(b) Slave device  
Figure 3.15 Jumper setting of master or slave device  
Note:  
When the device type is set by the jumper on the device, the device should not be  
configured for cable selection.  
(2)  
Cable Select (CSEL)  
In Cable Select mode, the device can be configured either master device or slave device. For  
use of Cable Select function, Unique interface cable is needed.  
C141-E093-01EN  
3 - 13  
2
1
4
3
6 8  
5 7  
9
CSEL connected to the interface cable selection  
can be done by the special interface cable.  
Figure 3.16 Jumper setting of Cable Select  
Figures 3.17 and 3.18 show examples of cable selection using unique interface cables.  
By connecting the CSEL of the master device to the CSEL Line (conductor) of the cable and  
connecting it to ground further, the CSEL is set to low level. The device is identified as a  
master device. At this time, the CSEL of the slave device does not have a conductor. Thus,  
since the slave device is not connected to the CSEL conductor, the CSEL is set to high level.  
The device is identified as a slave device.  
CSEL conductor  
Open  
GND  
Host system  
Master device  
Slave device  
Figure 3.17 Example (1) of Cable Select  
CSEL conductor  
Open  
GND  
Host system  
Slave device  
Master device  
Figure 3.18 Example (2) of Cable Select  
3 - 14  
C141-E093-01EN  
(3)  
Special jumper settings  
(a) 2.1 GB clip (Limit capacity to 2.1 GB)  
If the drive cannot be recognized by system with legacy BIOS’s which do not allow single  
volume sizes greater than approximately 2.1 GB, the following jumper settings should be  
applied.  
2
4
6 8  
2
4
6 8  
2
4
6 8  
1
3
5 7  
9
1
3
5 7  
9
1
3
5 7  
9
Master Device  
Slave Device  
Cable Select  
Model  
No. of cylinders  
4,092  
No. of heads  
No. of sectors  
MPE3043AE  
16  
16  
16  
63  
63  
63  
MPE3084AE  
MPE3173AE  
4,092  
4,092  
(b) Slave present  
If the slave device does not use the Device Active/Slave Present (DASP–) signal to  
indicate its presence, the device is configured as a Master with slave present when the  
following jumper settings is applied.  
2
4
6 8  
1
3
5 7  
9
Slave present  
C141-E093-01EN  
3 - 15  
This page is intentionally left blank.  
CHAPTER 4  
THEORY OF DEVICE OPERATION  
4.1  
4.2  
4.3  
4.4  
4.5  
4.6  
4.7  
Outline  
Subassemblies  
Circuit Configuration  
Power-on sequence  
Self-calibration  
Read/write Circuit  
Servo Control  
This chapter explains basic design concepts of the disk drive. Also, this chapter explains  
subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks.  
4.1  
Outline  
This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of  
the disk drive. Second part (Sections 4.3 through 4.7) explains a servo information recorded  
in the disk drive and drive control method.  
4.2  
Subassemblies  
The disk drive consists of a disk enclosure (DE) and printed circuit assembly (PCA).  
The DE contains all movable parts in the disk drive, including the disk, spindle, actuator,  
read/write head, and air filter. For details, see Subsections 4.2.1 to 4.2.5.  
The PCA contains the control circuits for the disk drive. The disk drive has one PCA. For  
details, see Sections 4.3.  
4.2.1  
Disk  
The DE contains the disks with an outer diameter of 95 mm. The MPE3043AE and  
MPE3084AE have 1 disk. The MPE3173AE has 2 disks.  
The head contacts the disk each time the disk rotation stops; the life of the disk is 40,000  
contacts or more.  
Servo data is recorded on each cylinder (total 96). Servo data written at factory is read out by  
the read/write head. For servo data, see Section 4.7.  
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4 - 1  
4.2.2  
Head  
Figure 4.1 shows the read/write head structures. The Numerals 0 to 7 indicate read/write  
heads. These heads are raised from the disk surface as the spindle motor approaches the rated  
rotation speed.  
MPE3043AE  
MPE3084AE  
Spindle  
Actuator  
Spindle  
Actuator  
1
0
0
MPE3173AE  
Spindle  
Actuator  
3
2
1
0
Figure 4.1 Head structure  
4.2.3  
Spindle  
The spindle consists of a disk stack assembly and spindle motor. The disk stack assembly is  
activated by the direct drive sensor-less DC spindle motor, which has a speed of 5,400 rpm.  
The spindle is controlled with detecting a PHASE signal generated by counter electromotive  
voltage of the spindle motor at starting. After that, the rotational speed is kept with detecting a  
servo information.  
4.2.4  
Actuator  
The actuator consists of a voice coil motor (VCM) and a head carriage. The VCM moves the  
head carriage along the inner or outer edge of the disk. The head carriage position is  
controlled by feeding back the difference of the target position that is detected and reproduced  
from the servo information read by the read/write head.  
4 - 2  
C141-E093-01EN  
4.2.5  
Air filter  
There are two types of air filters: a breather filter and a circulation filter.  
The breather filter makes an air in and out of the DE to prevent unnecessary pressure around  
the spindle when the disk starts or stops rotating. When disk drives are transported under  
conditions where the air pressure changes a lot, filtered air is circulated in the DE.  
The circulation filter cleans out dust and dirt from inside the DE. The disk drive cycles air  
continuously through the circulation filter through an enclosed loop air cycle system operated  
by a blower on the rotating disk.  
C141-E093-01EN  
4 - 3  
4.3  
Circuit Configuration  
Figure 4.2 shows the disk drive circuit configuration.  
(1)  
Read/write circuit  
The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read  
channel (RDC).  
The PreAMP consists of the write current switch circuit, that flows the write current to the  
head coil, and the voltage amplifier circuit, that amplitudes the read output from the head.  
The RDC is the read demodulation circuit using the Extended Partial Response Class 4  
(EPR4), and contains the Viterbi detector, programmable low pass filter, 10-tap adaptive  
digital FIR filter, synthesizer, and data separator circuits. The RDC also contains the 48/51  
group coded recording (GCR) encoder and decoder and servo demodulation circuit.  
(2)  
Servo circuit  
The position and speed of the voice coil motor are controlled by 2 closed-loop servo using the  
servo information recorded on the data surface. The servo information is an analog signal  
converted to digital for processing by a MPU and then reconverted to an analog signal for  
control of the voice coil motor.  
(3)  
(4)  
Spindle motor driver circuit  
The circuit measures the interval of a PHASE signal generated by counter-electromotive  
voltage of a motor, or servo mark at the MPU and controls the motor speed comparing target  
speed.  
Controller circuit  
Major functions are listed below.  
·
·
·
·
·
·
Data buffer management  
ATA interface control and data transfer control  
Sector format control  
Defect management  
ECC control  
Error recovery and self-diagnosis  
4 - 4  
C141-E093-01EN  
Figure 4.2 MPE3xxxAE Block diagram  
C141-E093-01EN  
4 - 5  
4.4  
Power-on Sequence  
Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is  
described below.  
a) After the power is turned on, the disk drive executes the MPU bus test, internal register  
read/write test, and work RAM read/write test. When the self-diagnosis terminates  
successfully, the disk drive starts the spindle motor.  
b) The disk drive executes self-diagnosis (data buffer read/write test) after enabling response  
to the ATA bus.  
c) After confirming that the spindle motor has reached rated speed, the disk drive releases the  
heads from the actuator magnet lock mechanism by applying current to the VCM. This  
unlocks the heads which are parked at the inner circumference of the disks.  
d) The disk drive positions the heads onto the SA area and reads out the system information.  
e) The disk drive executes self-seek-calibration. This collects data for VCM torque and  
mechanical external forces applied to the actuator, and updates the calibrating value.  
f) The drive becomes ready. The host can issue commands.  
4 - 6  
C141-E093-01EN  
Power on  
Start  
Self-diagnosis 1  
• MPU bus test  
• Inner register  
write/read test  
• Work RAM write/read  
test  
a)  
The spindle motor starts.  
Self-diagnosis 2  
• Data buffer write/read  
test  
b)  
c)  
Confirming spindle motor  
speed  
Release heads from  
actuator lock  
d)  
Initial on-track and read  
out of system information  
e)  
f)  
Execute self-calibration  
Drive ready state  
(command waiting state)  
End  
Figure 4.3 Power-on operation sequence  
C141-E093-01EN  
4 - 7  
4.5  
Self-calibration  
The disk drive occasionally performs self-calibration in order to sense and calibrate  
mechanical external forces on the actuator, and VCM torque. This enables precise seek and  
read/write operations.  
4.5.1  
Self-calibration contents  
(1)  
Sensing and compensating for external forces  
The actuator suffers from torque due to the FPC forces and winds accompanying disk  
revolution. The torque vary with the disk drive and the cylinder where the head is positioned.  
To execute stable fast seek operations, external forces are occasionally sensed.  
The firmware of the drive measures and stores the force (value of the actuator motor drive  
current) that balances the torque for stopping head stably. This includes the current offset in  
the power amplifier circuit and DAC system.  
The forces are compensated by adding the measured value to the specified current value to the  
power amplifier. This makes the stable servo control.  
To compensate torque varying by the cylinder, the disk is divided into 14 areas from the  
innermost to the outermost circumference and the compensating value is measured at the  
measuring cylinder on each area at factory calibration. The measured values are stored in the  
SA cylinder. In the self-calibration, the compensating value is updated using the value in the  
SA cylinder.  
(2)  
Compensating open loop gain  
Torque constant value of the VCM has a dispersion for each drive, and varies depending on  
the cylinder that the head is positioned. To realize the high speed seek operation, the value  
that compensates torque constant value change and loop gain change of the whole servo  
system due to temperature change is measured and stored.  
For sensing, the firmware mixes the disturbance signal to the position signal at the state that  
the head is positioned to any cylinder. The firmware calculates the loop gain from the position  
signal and stores the compensation value against to the target gain as ratio.  
For compensating, the direction current value to the power amplifier is multiplied by the  
compensation value. By this compensation, loop gain becomes constant value and the stable  
servo control is realized.  
To compensate torque constant value change depending on cylinder, whole cylinders from  
most inner to most outer cylinder are divided into 14 partitions at calibration in the factory,  
and the compensation data is measured for representative cylinder of each partition. This  
measured value is stored in the SA area. The compensation value at self-calibration is  
calculated using the value in the SA area.  
4 - 8  
C141-E093-01EN  
4.5.2  
Execution timing of self-calibration  
Self-calibration is executed when:  
·
·
The power is turned on.  
The self-calibration execution timechart of the disk drive specifies self-calibration.  
The disk drive performs self-calibration according to the timechart based on the time elapsed  
from power-on. The timechart is shown in Table 4.1. After power-on, self-calibration is  
performed about every 30 minutes.  
Table 4.1 Self-calibration execution timechart  
Time elapsed  
At power-on  
Time elapsed (accumulated)  
Initial calibration  
1
2
3
4
5
6
About 30 minutes  
About 30 minutes  
About 30 minutes  
About 30 minutes  
About 30 minutes  
About 30 minutes  
About 60 minutes  
About 90 minutes  
About 120 minutes  
About 150 minutes  
7
.
.
Every about 30 minutes  
.
9
4.5.3  
Command processing during self-calibration  
If the disk drive receives a command execution request from the host while executing self-  
calibration according to the timechart, the disk drive terminates self-calibration and starts  
executing the command precedingly. In other words, if a disk read or write service is  
necessary, the disk drive positions the head to the track requested by the host, reads or writes  
data, and restarts calibration.  
This enables the host to execute the command without waiting for a long time, even when the  
disk drive is performing self-calibration. The command execution wait time is about  
maximum 100 ms.  
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4 - 9  
4.6  
Read/write Circuit  
The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the  
read circuit, and the synthesizer in the read channel (RDC).  
4.6.1  
Read/write preamplifier (PreAMP)  
One PreAMP is mounted on the FPC. The PreAMP consists of an 4 or 8-channel read  
preamplifier and a write current switch and senses a write error. Each channel is connected to  
each data head. The head IC switches the heads by the serial port (SDEN, SCLK, SDATA).  
The IC generates a write error sense signal (WUS) when a write error occurs due to head short-  
circuit or head disconnection.  
4.6.2  
Write circuit  
The write data is output from the hard disk controller (HDC) with the NRZ data format, and  
sent to the encoder circuit in the RDC with synchronizing with the write clock. The NRZ  
write data is converted from 48-bits data to 51-bits data by the encoder circuit then sent to the  
PreAMP, and the data is written onto the media.  
(1)  
(2)  
48/51 GCR  
The disk drive converts data using the 48/51 group coded recording (GCR) algorithm.  
Write precompensation  
Write precompensation compensates, during a write process, for write non-linearity generated  
at reading.  
4 - 10  
C141-E093-01EN  
4.6.3  
Read circuit  
The head read signal from the PreAMP is regulated by the variable gain amplifier (VGA)  
circuit. Then the output is converted into the sampled read data pulse by the programmable  
filter circuit and the adaptive equalizer circuit. This clock signal is converted into the NRZ  
data by the 48/51 GCR decoder circuit based on the read data maximum-likelihood-detected  
by the Viterbi detection circuit, then is sent to the HDC.  
(1)  
(2)  
VGA circuit  
The VGA circuit automatically regulates the output amplitude to a constant value even when  
the input amplitude level fluctuates. The VGA output is maintained at a constant level even  
when the head output fluctuates due to the head characteristics or outer/inner head positions.  
Programmable filter  
The programmable filter circuit has a low-pass filter function that eliminates unnecessary high  
frequency noise component and a high frequency boost-up function that equalizes the  
waveform of the read signal.  
Cut-off frequency of the low-pass filter and boost-up gain are controlled from each DAC  
circuit in read channel by an instruction of the parallel data signal from MPU (M1). The MPU  
optimizes the cut-off frequency and boost-up gain according to the transfer frequency of each  
zone.  
(3)  
(4)  
Adaptive equalizer circuit  
This circuit is 10-tap adaptive digital FIR filter circuit that cosine-equalizes the head read  
signal to the Extended Partial Response Class 4 (EPR4) waveform.  
Viterbi detection circuit  
The digital data output from the adaptive equalizer circuit is sent to the Viterbi detection  
circuit. The Viterbi detection circuit demodulates data according to the survivor path  
sequence.  
(5)  
(6)  
Data separator circuit  
The data separator circuit generates clocks in synchronization with the output of the adaptive  
equalizer circuit. To write data, the VFO circuit generates clocks in synchronization with the  
clock signals from a synthesizer.  
48/51 GCR decoder  
This circuit converts the 48-bits read data into the 51-bits NRZ data.  
C141-E093-01EN  
4 - 11  
4.6.4  
Synthesizer circuit  
The drive uses constant density recording to increase total capacity. This is different from the  
conventional method of recording data with a fixed data transfer rate at all data area. In the  
constant density recording method, data area is divided into zones by radius and the data  
transfer rate is set so that the recording density of the inner cylinder of each zone is nearly  
constant. The drive divides data area into 15 zones to set the data transfer rate. Table 4.2  
describes the data transfer rate and recording density (BPI) of each zone.  
Table 4.2 Write clock frequency and transfer rate of each zone  
Zone  
0
1
2
3
4
5
6
7
Cylinder  
0
to  
965  
to  
2151  
to  
3581  
to  
4791  
to  
6121  
to  
8031  
to  
9441  
to  
964  
2150  
3580  
4790  
6120  
8030  
9440  
11210  
Transfer rate  
[MB/s]  
34.44  
34.44  
34.44  
34.44  
33.41  
31.83  
30.59  
28.71  
Zone  
8
9
10  
11  
12  
13  
14  
Cylinder  
11211 12171 12591 13431 14431 15861 16661  
to to to to to to to  
12170 12590 13430 14430 15860 16660 17300  
Transfer rate  
[MB/s]  
27.68  
27.14  
26.10  
24.80  
22.96  
21.93  
20.36  
The MPU transfers the data transfer rate setup data to the RDC that includes synthesizer circuit  
to change the data transfer rate.  
4.7  
Servo Control  
The actuator motor and the spindle motor are submitted to servo control. The actuator motor  
is controlled for moving and positioning the head to the track containing the desired data. To  
turn the disk at a constant velocity, the actuator motor is controlled according to the servo data  
that is written on the data side beforehand.  
4 - 12  
C141-E093-01EN  
4.7.1  
Servo control circuit  
Figure 4.4 is the block diagram of the servo control circuit. The following describes the  
functions of the blocks:  
(1)  
MPU  
SVC  
(5)  
(2)  
(3)  
(4)  
DAC  
VCM current  
Servo  
DSP  
unit  
P.  
Amp.  
ADC  
burst  
Head  
capture  
CSR  
Position Sense  
VCM  
(6)  
(7)  
Driver  
Spindle  
motor  
control  
Spindle  
motor  
CSR: Current Sense Resistor  
VCM: Voice Coil Motor  
Figure 4.4 Block diagram of servo control circuit  
(1)  
Microprocessor unit (MPU)  
The MPU includes DSP unit, etc., and the MPU starts the spindle motor, moves the heads to  
the reference cylinders, seeks the specified cylinder, and executes calibration according to the  
internal operations of the MPU.  
The major internal operations are listed below.  
a. Spindle motor start  
Starts the spindle motor and accelerates it to normal speed when power is applied.  
b. Move head to reference cylinder  
Drives the VCM to position the head at the any cylinder in the data area. The logical  
initial cylinder is at the outermost circumference (cylinder 0).  
C141-E093-01EN  
4 - 13  
c. Seek to specified cylinder  
Drives the VCM to position the head to the specified cylinder.  
d. Calibration  
Senses and stores the thermal offset between heads and the mechanical forces on the  
actuator, and stores the calibration value.  
Servo frame  
(96 servo frames per revolution)  
Figure 4.5 Physical sector servo configuration on disk surface  
4 - 14  
C141-E093-01EN  
(2)  
(3)  
(4)  
(5)  
(6)  
Servo burst capture circuit  
The four servo signals can be synchronously detected by the STROB signal, full-wave  
rectified integrated.  
A/D converter (ADC)  
The A/D converter (ADC) receives the servo signals are integrated, converts them to digital,  
and transfers the digital signal to the DSP unit.  
D/A converter (DAC)  
The D/A converter (DAC) converts the VCM drive current value (digital value) calculated by  
the DSP unit into analog values and transfers them to the power amplifier.  
Power amplifier  
The power amplifier feeds currents, corresponding to the DAC output signal voltage to the  
VCM.  
Spindle motor control circuit  
The spindle motor control circuit controls the sensor-less spindle motor. This circuit detects  
number of revolution of the motor by the interrupt generated periodically, compares with the  
target revolution speed, then flows the current into the motor coil according to the  
differentiation (aberration).  
(7)  
(8)  
Driver circuit  
The driver circuit is a power amplitude circuit that receives signals from the spindle motor  
control circuit and feeds currents to the spindle motor.  
VCM current sense resistor (CSR)  
This resistor controls current at the power amplifier by converting the VCM current into  
voltage and feeding back.  
C141-E093-01EN  
4 - 15  
4.7.2  
Data-surface servo format  
Figure 4.5 describes the physical layout of the servo frame. The three areas indicated by (1) to  
(3) in Figure 4.6 are described below.  
(1)  
Inner guard band  
The head is in contact with the disk in this space when the spindle starts turning or stops, and  
the rotational speed of the spindle can be controlled on this cylinder area for head moving.  
(2)  
(3)  
Data area  
This area is used as the user data area and SA area.  
Outer guard band  
This area is located at outer position of the user data area, and the rotational speed of the  
spindle can be controlled on this cylinder area for head moving.  
4.7.3  
Servo frame format  
As the servo information, the drive uses the two-phase servo generated from the gray code and  
Pos A to D. This servo information is used for positioning operation of radius direction and  
position detection of circumstance direction.  
The servo frame consists of 5 blocks; write/read recovery, servo mark, gray code, Pos A to D  
and PAD. Figure 4.6 shows the servo frame format.  
4 - 16  
C141-E093-01EN  
0.18 ms  
0.84 ms  
0.24 ms  
0.48 ms  
0.92 ms 0.84 ms 0.84 ms  
1.64 ms  
1.16 ms  
0.84 ms  
POS  
A
POS  
B
POS  
D
POS  
C
PAD  
SCD  
PA  
ASM  
SSM  
W/R Recovery Field  
7.98 ms  
Servo  
Frame  
Servo  
Frame  
DATA  
DATA  
115.7 ms  
Figure 4.6 96 servo frames in each track  
(1)  
(2)  
Write/read recovery  
This area is used to absorb the write/read transient and to stabilize the AGC.  
Servo mark (SMK1, SMK2)  
This area generates a timing for demodulating the gray code and position-demodulating Pos A  
to D by detecting the servo mark.  
C141-E093-01EN  
4 - 17  
(3)  
(4)  
(5)  
Preamble  
This area is used to synchronize with the PLL, which is used to search the SSM by detecting  
the ASM.  
Gray code (including index bit)  
This area is used as cylinder address. The data in this area is converted into the binary data by  
the gray code demodulation circuit.  
Pos A, Pos B, Pos C, Pos D  
This area is used as position signals between tracks, and the device control at on-track so that  
Pos A level equals to Pos B level.  
(6)  
PAD  
This area is used as a gap between servo and data.  
4.7.4  
Actuator motor control  
The voice coil motor (VCM) is controlled by feeding back the servo data recorded on the data  
surface. The MPU fetches the position sense data on the servo frame at a constant interval of  
sampling time, executes calculation, and updates the VCM drive current.  
The servo control of the actuator includes the operation to move the head to the reference  
cylinder, the seek operation to move the head to the target cylinder to read or write data, and  
the track-following operation to position the head onto the target track.  
(1)  
Operation to move the head to the reference cylinder  
The MPU moves the head to the reference cylinder when the power is turned. The reference  
cylinder is in the data area.  
When power is applied the heads are moved from the inner circumference shunt zone to the  
normal servo data zone in the following sequence:  
a) Micro current is fed to the VCM to press the head against the inner circumference.  
b) A current is fed to the VCM to move the head toward the outer circumference.  
c) When the servo mark is detected the head is moved slowly toward the outer circumference  
at a constant speed.  
d) If the head is stopped at the reference cylinder from there. Track following control starts.  
4 - 18  
C141-E093-01EN  
(2)  
Seek operation  
Upon a data read/write request from the host, the MPU confirms the necessity of access to the  
disk. If a read or instruction is issued, the MPU seeks the desired track.  
The MPU feeds the VCM current via the D/A converter and power amplifier to move the  
head. The MPU calculates the difference (speed error) between the specified target position  
and the current position for each sampling timing during head moving. The MPU then feeds  
the VCM drive current by setting the calculated result into the D/A converter. The calculation  
is digitally executed by the firmware. When the head arrives at the target cylinder, the track is  
followed.  
(3)  
Track following operation  
Except during head movement to the reference cylinder and seek operation under the spindle  
rotates in steady speed, the MPU does track following control. To position the head at the  
center of a track, the DSP drives the VCM by feeding micro current. For each sampling time,  
the VCM drive current is determined by filtering the position difference between the target  
position and the position clarified by the detected position sense data. The filtering includes  
servo compensation. These are digitally controlled by the firmware.  
4.7.5  
Spindle motor control  
Hall-less three-phase eight-pole motor is used for the spindle motor, and the 3-phase full/half-  
wave analog current control circuit is used as the spindle motor driver (called SVC hereafter).  
The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled  
by sending several signals from the MPU to the SVC. There are three modes for the spindle  
control; start mode, acceleration mode, and stable rotation mode.  
(1)  
Start mode  
When power is supplied, the spindle motor is started in the following sequence:  
a) After the power is turned on, the MPU sends a signal to the SVC to charge the change  
pump capacitor of the SVC. The charged amount defines the current that flows in the  
spindle motor.  
b) When the charge pump capacitor is charged enough, the MPU sets the SVC to the motor  
start mode. Then, a current (approx. 2.1 A) flows into the spindle motor.  
c) The SVC generates a phase switching signal by itself, and changes the phase of the current  
flowed in the motor in the order of (V-phase to U-phase), (W-phase to U-phase), (W-phase  
to V-phase), (U-phase to V-phase), (U-phase to W-phase), and (V-phase to W-phase) (after  
that, repeating this order).  
d) During phase switching, the spindle motor starts rotating in low speed, and generates a  
counter electromotive force. The SVC detects this counter electromotive force and reports  
to the MPU using a PHASE signal for speed detection.  
C141-E093-01EN  
4 - 19  
e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a specific  
period, the MPU resets the SVC and starts from the beginning. When a PHASE signal is  
sent, the SVC enters the acceleration mode.  
(2)  
Acceleration mode  
In this mode, the MPU stops to send the phase switching signal to the SVC. The SVC starts a  
phase switching by itself based on the counter electromotive force. Then, rotation of the  
spindle motor accelerates. The MPU calculates a rotational speed of the spindle motor based  
on the PHASE signal from the SVC, and accelerates till the rotational speed reaches 5,400  
rpm. When the rotational speed reaches 5,400 rpm, the SVC enters the stable rotation mode.  
(3)  
Stable rotation mode  
The MPU calculates a time for one revolution of the spindle motor based on the PHASE signal  
from the SVC. The MPU takes a difference between the current time and a time for one  
revolution at 5,400 rpm that the MPU already recognized. Then, the MPU keeps the rotational  
speed to 5,400 rpm by charging or discharging the charge pump for the different time. For  
example, when the actual rotational speed is 5,600 rpm, the time for one revolution is 10.714  
ms. And, the time for one revolution at 5,400 rpm is 11.111 ms. Therefore, the MPU  
discharges the charge pump for 0.397 ms ´ k (k: constant value). This makes the flowed  
current into the motor lower and the rotational speed down. When the actual rotational speed  
is later than 5,400 rpm, the MPU charges the pump the other way. This control  
(charging/discharging) is performed every 1/6 revolution.  
4 - 20  
C141-E093-01EN  
CHAPTER 5  
INTERFACE  
5.1  
5.2  
5.3  
5.4  
5.5  
5.6  
Physical Interface  
Logical Interface  
Host Commands  
Command Protocol  
Ultra DMA feature set  
Timing  
C141-E093-01EN  
5 - 1  
5.1  
Physical Interface  
5.1.1  
Interface signals  
Table 5.1 shows the interface signals.  
Table 5.1 Interface signals  
Description  
Host  
Dir  
Dev  
Acrorym  
CSEL  
Cable select  
see note  
Chip select 0  
Chip select 1  
Data bus bit 0  
Data bus bit 1  
Data bus bit 2  
Data bus bit 3  
Data bus bit 4  
Data bus bit 5  
Data bus bit 6  
Data bus bit 7  
Data bus bit 8  
Data bus bit 9  
Data bus bit 10  
Data bus bit 11  
Data bus bit 12  
Data bus bit 13  
Data bus bit 14  
Data bus bit 15  
CS0–  
®
CS1–  
®
DD0  
«
DD1  
«
DD2  
«
DD3  
«
DD4  
«
DD5  
«
DD6  
«
DD7  
«
DD8  
«
DD9  
«
DD10  
«
DD11  
«
DD12  
«
DD13  
«
DD14  
«
DD15  
«
Device active or slave present  
Device address bit 0  
see note  
DASP–  
DA0  
®
®
®
®
Device address bit 1  
DA1  
Device address bit 2  
DA2  
DMA acknowledge  
DMACK–  
DMARQ  
INTRQ  
DIOR–  
HDMARDY–  
HSTROBE  
IORDY  
DDMARDY–  
DSTROBE  
DIOW–  
STOP  
DMA request  
¬
Interrupt request  
¬
I/O read  
®
®
®
DMA ready during Ultra DMA data in bursts  
Data strobe during Ultra DMA data out bursts  
I/O ready  
¬
¬
¬
DMA ready during Ultra DMA data out bursts  
Data strobe during Ultra DMA data in bursts  
I/O write  
®
®
Stop during Ultra DMA data bursts  
Passed diagnostics  
Cable type detection  
see note  
PDIAG–  
CBLID–  
Reset  
RESET–  
®
Note See signal descriptions  
5 - 2  
C141-E093-01EN  
5.1.2  
Signal assignment on the connector  
Table 5.2 shows the signal assignment on the interface connector.  
Table 5.2 Signal assignment on the interface connector  
Pin No.  
Signal  
Pin No.  
Signal  
1
3
5
7
RESET–  
DATA7  
DATA6  
DATA5  
DATA4  
DATA3  
DATA2  
DATA1  
DATA0  
GND  
2
4
6
8
GND  
DATA8  
DATA9  
DATA10  
DATA11  
DATA12  
DATA13  
DATA14  
DATA15  
(KEY)  
GND  
GND  
GND  
CSEL  
GND  
reserved  
PDIAG–, CBLID–  
DA2  
CS1–  
GND  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
DMARQ  
DIOW–, STOP  
DIOR–, HDMARDY–, HSTROBE  
IORDY, DDMARDY–,  
DSTROBE  
DMACK–  
INTRQ  
DA1  
DA0  
CS0–  
DASP–  
[signal]  
[I/O]  
[Description]  
RESET–  
I
Reset signal from the host. This signal is low active and is  
asserted for a minimum of 25 ms during power on. The device has  
a 10 kW pull-up resistor on this signal.  
DATA 0-15  
I/O  
I
Sixteen-bit bi-directional data bus between the host and the  
device. These signals are used for data transfer  
DIOW–, STOP  
DIOW– is the strobe signal asserted by the host to write device  
registers or the data port.  
DIOW– shall be negated by the host prior to initiation of an Ultra  
DMA burst. STOP shall be negated by the host before data is  
transferred in an Ultra DMA burst. Assertion of STOP by the host  
during an Ultra DMA burst signals the termination of the Ultra  
DMA burst.  
C141-E093-01EN  
5 - 3  
[signal]  
DIOR–  
[I/O]  
I
[Description]  
DIOR– is the strobe signal asserted by the host to read device  
registers or the data port.  
HDMARDY–  
HSTROBE  
INTRQ  
I
HDMARDY– is a flow control signal for Ultra DMA data in  
bursts. This signal is asserted by the host to indicate to the device  
that the host is ready to receive Ultra DMA data in bursts.  
The host may negate HDMARDY- to pause an Ultra DMA data in  
burst.  
I
HSTROBE is the data out strobe signal from the host for an Ultra  
DMA data out burst. Both the rising and falling edge of  
HSTROBE latch the data from DATA 0-15 into the device. The  
host may stop generating HSTROBE edges to pause an Ultra  
DMA data out burst.  
O
Interrupt signal to the host.  
This signal is negated in the following cases:  
– assertion of RESET– signal  
– Reset by SRST of the Device Control register  
– Write to the command register by the host  
– Read of the status register by the host  
– Completion of sector data transfer  
(without reading the Status register)  
When the device is not selected or interrupt is disabled, the  
INTRQ  
Signal shall be in a high impedance state.  
CS0–  
I
I
I
Chip select signal decoded from the host address bus. This signal  
is used by the host to select the command block registers.  
CS1–  
Chip select signal decoded from the host address bus. This signal  
is used by the host to select the control block registers.  
DA 0-2  
Binary decoded address signals asserted by the host to access task  
file registers.  
KEY  
–
Key pin for prevention of erroneous connector insertion  
PIDAG–  
I/O  
This signal is an input mode for the master device and an output  
mode for the slave device in a daisy chain configuration. This  
signal indicates that the slave device has been completed self  
diagnostics.  
This signal is pulled up to +5 V through 10 kW resistor at each device.  
CBLID–  
DASP–  
I/O  
I/O  
This signal is used to detect the cable type (80 or 40-conductor  
cable) installed in the system. This signal is pulled up to +5 V  
through 10 kW resistor at each device.  
This is a time-multiplexed signal that indicates that the device is  
active and a slave device is present.  
This signal is pulled up to +5 V through 10 kW resistor at each device.  
5 - 4  
C141-E093-01EN  
[signal]  
IORDY  
[I/O]  
O
[Description]  
This signal is negated to extend the host transfer cycle of any host  
register access (Read or Write) when the device is not ready to  
respond to a data transfer request.  
DDMARDY–  
DSTROBE  
O
O
DDMARDY– is a flow control signal for Ultra DMA data out bursts.  
This signal is asserted by the device to indicate to the host that the  
device is ready to receive Ultra DMA data out bursts. The device may  
negate DDMARDY– to pause an Ultra DMA data out burst.  
DSTROBE is the data in strobe signal from the device for an Ultra  
DMA data in burst. Both the rising and falling edge of  
DSTROBE latch the data from DATA 0-15 into the host. The  
device may stop generating DSTROBE edges to pause an Ultra  
DMA data in burst.  
CSEL  
I
This signal to configure the device as a master or a slave device.  
When CSEL signal is grounded, the IDD is a master device.  
When CSEL signal is open, the IDD is a slave device.  
This signal is pulled up with 10 kW resistor.  
DMACK–  
DMARQ  
I
The host system asserts this signal as a response that the host  
system receive data or to indicate that data is valid.  
O
This signal is used for DMA transfer between the host system and  
the device. The device asserts this signal when the device  
completes the preparation of DMA data transfer to the host system  
(at reading) or from the host system (at writing).  
The direction of data transfer is controlled by the IOR- and IOW-  
signals. In other word, the device negates the DMARQ signal  
after the host system asserts the DMACK– signal. When there is  
another data to be transferred, the device asserts the DMARQ  
signal again.  
When the DMA data transfer is performed, IOCW16–, CS0– and  
CS1- signals are not asserted. The DMA data transfer is a 16-bit  
data transfer. The device has a 10 kW pull-down resistor on this  
signal.  
GND  
–
Grounded  
Note:  
"I" indicates input signal from the host to the device.  
"O" indicates output signal from the device to the host.  
"I/O" indicates common output or bi-directional signal between the host and the device.  
C141-E093-01EN  
5 - 5  
5.2  
Logical Interface  
The device can operate for command execution in either address-specified mode; cylinder-  
head-sector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE  
information indicates whether the device supports the LBA mode. When the host system  
specifies the LBA mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of  
the Device/Head register indicates the head No. under the LBA mode, and all bits of the  
Cylinder High, Cylinder Low, and Sector Number registers are LBA bits.  
The sector No. under the LBA mode proceeds in the ascending order with the start point of  
LBA0 (defined as follows).  
LBA0 = [Cylinder 0, Head 0, Sector 1]  
Even if the host system changes the assignment of the CHS mode by the INITIALIZE  
DEVICE PARAMETER command, the sector LBA address is not changed.  
LBA = [((Cylinder No.) ´ (Number of head) + (Head No.)) ´ (Number of sector/track)]  
+ (Sector No.) – 1  
5.2.1  
I/O registers  
Communication between the host system and the device is done through input-output (I/O)  
registers of the device.  
These I/O registers can be selected by the coded signals, CS0–, CS1–, and DA0 to DA2 from  
the host system. Table 5.3 shows the coding address and the function of I/O registers.  
5 - 6  
C141-E093-01EN  
Table 5.3 I/O registers  
I/O registers  
Host I/O  
address  
CS0–  
CS1–  
DA2  
DA1  
DA0  
Read operation  
Write operation  
Command block registers  
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Data  
Data  
X'1F0'  
X'1F1'  
X'1F2'  
X'1F3'  
X'1F4'  
X'1F5'  
X'1F6'  
X'1F7'  
—
Error Register  
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Device/Head  
Status  
Features  
Sector Count  
Sector Number  
Cylinder Low  
Cylinder High  
Device/Head  
Command  
(Invalid)  
X
X
(Invalid)  
Control block registers  
0
0
1
1
1
1
1
1
0
1
Alternate Status  
—
Device Control  
—
X'3F6'  
X'3F7'  
Notes:  
1. The Data register for read or write operation can be accessed by 16 bit data bus  
(DATA0 to DATA15).  
2. The registers for read or write operation other than the Data registers can be accessed  
by 8 bit data bus (DATA0 to DATA7).  
3. When reading the Drive Address register, bit 7 is high-impedance state.  
4. The LBA mode is specified, the Device/Head, Cylinder High, Cylinder Low, and  
Sector Number registers indicate LBA bits 27 to 24, 23 to 16, 15 to 8, and 7 to 0.  
C141-E093-01EN  
5 - 7  
5.2.2  
Command block registers  
(1)  
Data register (X'1F0')  
The Data register is a 16-bit register for data block transfer between the device and the host  
system. Data transfer mode is PIO or LBA mode.  
(2)  
Error register (X'1F1')  
The Error register indicates the status of the command executed by the device. The contents  
of this register are valid when the ERR bit of the Status register is 1.  
This register contains a diagnostic code after power is turned on, a reset , or the EXECUTIVE  
DEVICE DIAGNOSTIC command is executed.  
[Status at the completion of command execution other than diagnostic command]  
Bit 7  
Bit 6  
UNC  
Bit 5  
X
Bit 4  
Bit 3  
X
Bit 2  
Bit 1  
Bit 0  
ICRC  
IDNF  
ABRT TK0NF AMNF  
X: Unused  
- Bit 7:  
Interface CRC error (ICRC). This bit indicates that an interface CRC error has  
occurred during an Ultra DMA data transfer. The content of this bit is not  
applicable for Multiword DMA transfers.  
- Bit 6:  
Uncorrectable Data Error (UNC). This bit indicates that an uncorrectable data  
error has been encountered.  
- Bit 5:  
- Bit 4:  
Unused  
ID Not Found (IDNF). This bit indicates an error except for, uncorrectable error  
and SB not found, and Aborted Command.  
- Bit 3:  
- Bit 2:  
Unused  
Aborted Command (ABRT). This bit indicates that the requested command was  
aborted due to a device status error (e.g. Not Ready, Write Fault) or the command  
code was invalid.  
- Bit 1:  
- Bit 0:  
Track 0 Not Found (TK0NF). This bit indicates that track 0 was not found  
during RECALIBRATE command execution.  
Address Mark Not Found. This bit indicates that an SB not found error has been  
encountered.  
5 - 8  
C141-E093-01EN  
[Diagnostic code]  
X'01': No Error Detected.  
X'02': HDC Register Compare Error  
X'03': Data Buffer Compare Error.  
X'05': ROM Sum Check Error.  
X'80': Device 1 (slave device) Failed.  
Error register of the master device is valid under two devices (master and slave)  
configuration. If the slave device fails, the master device posts X’80’ OR (the  
diagnostic code) with its own status (X'01' to X'05').  
However, when the host system selects the slave device, the diagnostic code of the  
slave device is posted.  
(3)  
(4)  
Features register (X'1F1')  
The Features register provides specific feature to a command. For instance, it is used with SET  
FEATURES command to enable or disable caching.  
Sector Count register (X'1F2')  
The Sector Count register indicates the number of sectors of data to be transferred in a read or  
write operation between the host system and the device. When the value in this register is  
X'00', the sector count is 256.  
When this register indicates X'00' at the completion of the command execution, this indicates  
that the command is completed successfully. If the command is not completed successfully,  
this register indicates the number of sectors to be transferred to complete the request from the  
host system. That is, this register indicates the number of remaining sectors that the data has  
not been transferred due to the error.  
The contents of this register has other definition for the following commands; INITIALIZE  
DEVICE PARAMETERS, FORMAT TRACK, SET FEATURES, IDLE, STANDBY and SET  
MULTIPLE MODE.  
(5)  
Sector Number register (X'1F3')  
The contents of this register indicates the starting sector number for the subsequent command.  
The sector number should be between X'01' and [the number of sectors per track defined by  
INITIALIZE DEVICE PARAMETERS command.  
Under the LBA mode, this register indicates LBA bits 7 to 0.  
C141-E093-01EN  
5 - 9  
(6)  
(7)  
(8)  
Cylinder Low register (X'1F4')  
The contents of this register indicates low-order 8 bits of the starting cylinder address for any  
disk-access.  
At the end of a command, the contents of this register are updated to the current cylinder  
number.  
Under the LBA mode, this register indicates LBA bits 15 to 8.  
Cylinder High register (X'1F5')  
The contents of this register indicates high-order 8 bits of the disk-access start cylinder  
address.  
At the end of a command, the contents of this register are updated to the current cylinder  
number. The high-order 8 bits of the cylinder address are set to the Cylinder High register.  
Under the LBA mode, this register indicates LBA bits 23 to 16.  
Device/Head register (X'1F6')  
The contents of this register indicate the device and the head number.  
When executing INITIALIZE DEVICE PARAMETERS command, the contents of this  
register defines "the number of heads minus 1".  
Bit 7  
X
Bit 6  
L
Bit 5  
X
Bit 4  
DEV  
Bit 3  
HS3  
Bit 2  
HS2  
Bit 1  
HS1  
Bit 0  
HS0  
- Bit 7:  
- Bit 6:  
- Bit 5:  
- Bit 4:  
- Bit 3:  
- Bit 2:  
- Bit 1:  
- Bit 0:  
Unused  
L. 0 for CHS mode and 1 for LBA mode.  
Unused  
DEV bit. 0 for the master device and 1 for the slave device.  
HS3 CHS mode head address 3 (23). LBA bit 27.  
HS2 CHS mode head address 3 (22). LBA bit 26.  
HS1 CHS mode head address 3 (21). LBA bit 25.  
HS0 CHS mode head address 3 (20). LBA bit 24.  
5 - 10  
C141-E093-01EN  
(9)  
Status register (X'1F7')  
The contents of this register indicate the status of the device. The contents of this register are  
updated at the completion of each command. When the BSY bit is cleared, other bits in this  
register should be validated within 400 ns. When the BSY bit is 1, other bits of this register  
are invalid. When the host system reads this register while an interrupt is pending, it is  
considered to be the Interrupt Acknowledge (the host system acknowledges the interrupt). Any  
pending interrupt is cleared (negating INTRQ signal) whenever this register is read.  
Bit 7  
BSY  
Bit 6  
Bit 5  
DF  
Bit 4  
DSC  
Bit 3  
DRQ  
Bit 2  
0
Bit 1  
0
Bit 0  
ERR  
DRDY  
- Bit 7:  
Busy (BSY) bit. This bit is set whenever the Command register is accessed.  
Then this bit is cleared when the command is completed. However, even if a  
command is being executed, this bit is 0 while data transfer is being requested  
(DRQ bit = 1).When BSY bit is 1, the host system should not write the command  
block registers. If the host system reads any command block register when BSY  
bit is 1, the contents of the Status register are posted. This bit is set by the device  
under following conditions:  
(a) Within 400 ns after RESET- is negated or SRST is set in the Device Control  
register, the BSY bit is set. the BSY bit is cleared, when the reset process is  
completed.  
The BSY bit is set for no longer than 15 seconds after the IDD accepts reset.  
(b) Within 400 ns from the host system starts writing to the Command register.  
(c) Within 5 ms following transfer of 512 bytes data during execution of the  
READ SECTOR(S), WRITE SECTOR(S), FORMAT TRACK, or WRITE  
BUFFER command.  
Within 5 ms following transfer of 512 bytes of data and the appropriate  
number of ECC bytes during execution of READ LONG or WRITE LONG  
command.  
- Bit 6:  
Device Ready (DRDY) bit. This bit indicates that the device is capable to  
respond to a command.  
The IDD checks its status when it receives a command. If an error is detected  
(not ready state), the IDD clears this bit to 0. This is cleared to 0 at power-on and  
it is cleared until the rotational speed of the spindle motor reaches the steady  
speed.  
- Bit 5:  
- Bit 4:  
The Device Write Fault (DF) bit. This bit indicates that a device fault (write  
fault) condition has been detected.  
If a write fault is detected during command execution, this bit is latched and  
retained until the device accepts the next command or reset.  
Device Seek Complete (DSC) bit. This bit indicates that the device heads are  
positioned over a track.  
In the IDD, this bit is always set to 1 after the spin-up control is completed.  
C141-E093-01EN  
5 - 11  
- Bit 3:  
Data Request (DRQ) bit. This bit indicates that the device is ready to transfer  
data of word unit or byte unit between the host system and the device.  
- Bit 2:  
- Bit 1:  
- Bit 0:  
Always 0.  
Always 0.  
Error (ERR) bit. This bit indicates that an error was detected while the previous  
command was being executed. The Error register indicates the additional  
information of the cause for the error.  
(10)  
Command register (X'1F7')  
The Command register contains a command code being sent to the device. After this register  
is written, the command execution starts immediately.  
Table 5.3 lists the executable commands and their command codes. This table also lists the  
necessary parameters for each command which are written to certain registers before the  
Command register is written.  
5 - 12  
C141-E093-01EN  
5.2.3  
Control block registers  
(1)  
Alternate Status register (X'3F6')  
The Alternate Status register contains the same information as the Status register of the  
command block register.  
The only difference from the Status register is that a read of this register does not imply  
Interrupt Acknowledge and INTRQ signal is not reset.  
Bit 7  
BSY  
Bit 6  
Bit 5  
DF  
Bit 4  
DSC  
Bit 3  
DRQ  
Bit 2  
0
Bit 1  
0
Bit 0  
ERR  
DRDY  
(2)  
Device Control register (X'3F6')  
The Device Control register contains device interrupt and software reset.  
Bit 7  
X
Bit 6  
X
Bit 5  
X
Bit 4  
X
Bit 3  
X
Bit 2  
Bit 1  
nIEN  
Bit 0  
0
SRST  
- Bit 2:  
SRST is the host software reset bit. When this bit is set, the device is held reset  
state. When two device are daisy chained on the interface, setting this bit resets  
both device simultaneously.  
The slave device is not required to execute the DASP- handshake.  
- Bit 1:  
nIEN bit enables an interrupt (INTRQ signal) from the device to the host. When  
this bit is 0 and the device is selected, an interruption (INTRQ signal) can be  
enabled through a tri-state buffer. When this bit is 1 or the device is not selected,  
the INTRQ signal is in the high-impedance state.  
5.3  
Host Commands  
The host system issues a command to the device by writing necessary parameters in related  
registers in the command block and writing a command code in the Command register.  
The device can accept the command when the BSY bit is 0 (the device is not in the busy  
status).  
The host system can halt the uncompleted command execution only at execution of hardware  
or software reset.  
When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data transfer) and the  
host system writes to the command register, the correct device operation is not guaranteed.  
C141-E093-01EN  
5 - 13  
5.3.1  
Command code and parameters  
Table 5.4 lists the supported commands, command code and the registers that needed  
parameters are written.  
Table 5.4 Command code and parameters (1 of 2)  
Command code (Bit)  
Parameters used  
Command name  
7
0
1
1
0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
6
0
1
1
1
1
1
0
0
0
1
0
1
1
1
1
0
1
0
0
1
1
5
1
0
0
0
0
0
1
1
0
1
0
1
1
1
0
0
0
1
1
1
1
4
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
0
1
0
0
3
0
0
1
0
0
1
1
0
X
X
0
1
1
1
0
0
0
0
0
0
1
2
0
1
0
0
1
0
1
0
X
X
0
1
1
1
1
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
X
X
0
0
1
1
1
0
0
1
1
0
0
0
R
0
FR SC SN CY DH  
READ SECTOR(S)  
READ MULTIPLE  
READ DMA  
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
N
N
Y
N
N
N*  
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
N
N
N
N
N
N
Y*  
Y
Y
N
N
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
N
N
N
N
N
N
Y
Y
Y
N
N
Y
Y
Y
Y
Y
Y
Y
Y
D
Y
Y
D
D
D
D
D*  
Y
Y
Y
D
D
R
R
1
READ VERIFY SECTOR(S)  
WRITE MULTIPLE  
WRITE DMA  
R
0
WRITE VERIFY  
WRITE SECTOR(S)  
RECALIBRATE  
R
X
X
1
SEEK  
INITIALIZE DEVICE DIAGNOSTIC  
IDENTIFY DEVICE  
IDENTIFY DEVICE DMA  
SET FEATURES  
0
0
1
SET MULTIPLE MODE  
EXECUTE DEVICE DIAGNOSTIC  
FORMAT TRACK  
READ LONG  
0
0
0
R
R
0
WRITE LONG  
READ BUFFER  
WRITE BUFFER  
0
IDLE  
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
1
N
N
N
Y
N
Y
N
N
N
N
N
N
D
D
D
IDLE IMMEDIATE  
STANDBY  
1
1
0
1
0
1
1
0
0
0
1
0
0
0
1
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
5 - 14  
C141-E093-01EN  
Table 5.4 Command code and parameters (2 of 2)  
Command code (Bit)  
Parameters used  
Command name  
7
6
5
4
3
2
1
0
FR SC SN CY DH  
STANDBY IMMEDIATE  
1
1
0
1
0
1
1
0
0
0
1
0
0
0
0
0
N
N
N
N
N
N
N
N
N
N
N
N
D
D
D
SLEEP  
1
1
0
1
0
1
1
0
1
0
0
1
0
1
1
0
CHECK POWER MODE  
1
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
SMART  
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
1
0
Y
N
N
N
Y
N
Y
N
Y
N
Y
N
Y
N
Y
N
D
D
Y
D
FLUSH CACHE  
SET MAX ADDRESS  
READ NATIVE MAX ADDRESS  
Notes:  
FR : Features Register  
SC : Sector Count Register  
SN : Sector Number Register  
CY: Cylinder Registers  
DH : Drive/Head Register  
R: R = 0 or 1  
Y: Necessary to set parameters  
Y*: Necessary to set parameters under the LBA mode.  
N: Necessary to set parameters (The parameter is ignored if it is set.)  
N*: May set parameters  
D: The device parameter is valid, and the head parameter is ignored.  
D*: The command is addressed to the master device, but both the master device and the  
slave device execute it.  
X: Do not care  
C141-E093-02EN  
5 - 15  
5.3.2  
Command descriptions  
The contents of the I/O registers to be necessary for issuing a command and the example  
indication of the I/O registers at command completion are shown as following in this  
subsection.  
Example: READ SECTOR(S)  
At command issuance (I/O registers setting contents)  
Bit  
7
0
´
6
0
5
1
´
4
0
3
0
2
0
1
0
0
0
1F7H(CM)  
1F6H(DH)  
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
L
DV  
Head No. / LBA [MSB]  
Start cylinder address [MSB]  
/ LBA  
Start cylinder address [LSB] / LBA  
Start sector No.  
Transfer sector count  
xx  
/ LBA [LSB]  
At command completion (I/O registers contents to be read)  
Bit  
7
6
5
4
3
2
1
0
1F7H(ST)  
1F6H(DH)  
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
Error information  
DV End Head No. / LBA [MSB]  
L
´
´
End cylinder address [MSB] / LBA  
End cylinder address [LSB] / LBA  
End sector No.  
/ LBA [LSB]  
X‘00’  
Error information  
CM: Command register  
DH: Device/Head register  
CH: Cylinder High register  
CL: Cylinder Low register  
SN: Sector Number register  
SC: Sector Count register  
FR: Features register  
ST: Status register  
ER: Error register  
L: LBA (logical block address) setting bit  
DV: Device address. bit  
x, xx: Do not care (no necessary to set)  
5 - 16  
C141-E093-01EN  
Note:  
1. When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the  
CH, CL and SN registers indicate the LBA bits (bits of the DH register are the MSB  
(most significant bit) and bits of the SN register are the LSB (least significant bit).  
2. At error occurrence, the SC register indicates the remaining sector count of data transfer.  
3. In the table indicating I/O registers contents in this subsection, bit indication is omitted.  
(1)  
READ SECTOR(S) (X'20' or X'21')  
This command reads data of sectors specified in the Sector Count register from the address specified  
in the Device/Head, Cylinder High, Cylinder Low and Sector Number registers. Number of sectors  
can be specified to 256 sectors in maximum. To specify 256 sectors reading, '00' is specified. For  
the DRQ, INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.1.  
If the head is not on the track specified by the host, the device performs a implied seek. After  
the head reaches to the specified track, the device reads the target sector.  
The DRQ bit of the Status register is always set prior to the data transfer regardless of an error  
condition.  
Upon the completion of the command execution, command block registers contain the  
cylinder, head, and sector addresses (in the CHS mode) or logical block address (in the LBA  
mode) of the last sector read.  
If an error occurs in a sector, the read operation is terminated at the sector where the error occurred.  
Command block registers contain the cylinder, the head, and the sector addresses of the sector  
(in the CHS mode) or the logical block address (in the LBA mode) where the error occurred,  
and remaining number of sectors of which data was not transferred.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
0
0
1
0
0
0
0
R
L
DV Start head No. /LBA [MSB]  
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
Start cylinder No. [MSB]/ LBA  
Start cylinder No. [LSB] / LBA  
Start sector No.  
/ LBA [LSB]  
Transfer sector count  
xx  
R = 0 or 1  
C141-E093-01EN  
5 - 17  
At command completion (I/O registers contents to be read)  
1F7H(ST) Status information  
DV End head No. /LBA [MSB]  
1F6H(DH)  
L
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
End cylinder No. [MSB] / LBA  
End cylinder No. [LSB] / LBA  
End sector No.  
/ LBA [LSB]  
00 (*1)  
Error information  
*1 If the command is terminated due to an error, the remaining number of  
sectors of which data was not transferred is set in this register.  
(2)  
READ MULTIPLE (X'C4')  
This command operates similarly to the READ SECTOR(S) command. The device does not  
generate an interrupt (assertion of the INTRQ signal) on each every sector. An interrupt is  
generated after the transfer of a block of sectors for which the number is specified by the SET  
MULTIPLE MODE command.  
The implementation of the READ MULTIPLE command is identical to that of the READ  
SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE  
MODE command are transferred without intervening interrupts. In the READ MULTIPLE  
command operation, the DRQ bit of the Status register is set only at the start of the data block,  
and is not set on each sector.  
The number of sectors (block count) to be transferred without interruption is specified by the  
SET MULTIPLE MODE command. The SET MULTIPLE MODE command should be  
executed prior to the READ MULTIPLE command.  
When the READ MULTIPLE command is issued, the Sector Count register contains the number of  
sectors requested (not a number of the block count or a number of sectors in a block).  
Upon receipt of this command, the device executes this command even if the value of the Sector  
Count register is less than the defined block count (the value of the Sector Count should not be 0).  
If the number of requested sectors is not divided evenly (having the same number of sectors  
[block count]), as many full blocks as possible are transferred, then a final partial block is  
transferred. The number of sectors in the partial block to be transferred is n where n =  
remainder of ("number of sectors"/"block count").  
If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is  
executed or when the READ MULTIPLE command is disabled, the device rejects the READ  
MULTIPLE command with an ABORTED COMMAND error.  
If an error occurs, reading sector is stopped at the sector where the error occurred. Command  
block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the  
logical block address (in the LBA mode) of the sector where the error occurred, and remaining  
number of sectors that had not transferred after the sector where the error occurred.  
An interrupt is generated when the DRQ bit is set at the beginning of each block or a partial block.  
5 - 18  
C141-E093-01EN  
Figure 5.1 shows an example of the execution of the READ MULTIPLE command.  
·
·
Block count specified by SET MULTIPLE MODE command = 4 (number of sectors in a  
block)  
READ MULTIPLE command specifies;  
Number of requested sectors = 9 (Sector Count register = 9)  
¯
Number of sectors in incomplete block = remainder of 9/4 =1  
Command Issue  
Parameter  
Write  
Status read  
Status read  
Status read  
~
BSY  
DRDY  
INTRQ  
DRQ  
5
6
7
8
9
1
2
3
4
Sector  
transferred  
Partial  
block  
Block  
Block  
Figure 5.1 Execution example of READ MULTIPLE command  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1
1
0
0
0
1
0
0
1F6H(DH)  
L
DV Start head No. /LBA [MSB]  
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
Start cylinder No. [MSB]/ LBA  
Start cylinder No. [LSB] / LBA  
Start sector No.  
Transfer sector count  
xx  
/ LBA [LSB]  
At command completion (I/O registers contents to be read)  
1F7H(ST) Status information  
DV End head No. /LBA [MSB]  
1F6H(DH)  
L
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
End cylinder No. [MSB] / LBA  
End cylinder No. [LSB] / LBA  
End sector No.  
/ LBA [LSB]  
00H (*1)  
Error information  
*1 If the command is terminated due to an error, the remaining number of sectors for which  
data was not transferred is set in this register.  
C141-E093-01EN  
5 - 19  
(3)  
READ DMA (X'C8' or X'C9')  
This command operates similarly to the READ SECTOR(S) command except for following  
events.  
·
·
·
The data transfer starts at the timing of DMARQ signal assertion.  
The device controls the assertion or negation timing of the DMARQ signal.  
The device posts a status as the result of command execution only once at completion of  
the data transfer.  
When an error, such as an unrecoverable medium error, that the command execution cannot be  
continued is detected, the data transfer is stopped without transferring data of sectors after the erred  
sector. The device generates an interrupt using the INTRQ signal and posts a status to the host  
system. The format of the error information is the same as the READ SECTOR(S) command.  
In LBA mode  
The logical block address is specified using the start head No., start cylinder No., and first  
sector No. fields. At command completion, the logical block address of the last sector and  
remaining number of sectors of which data was not transferred, like in the CHS mode, are set.  
The host system can select the DMA transfer mode by using the SET FEATURES command.  
1) Multiword DMA transfer mode 2:  
Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command  
2) Ultra DMA transfer mode 2:  
Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES command  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
1
1
0
0
1
0
0
R
L
DV Start head No. /LBA [MSB]  
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
Start cylinder No. [MSB]/ LBA  
Start cylinder No. [LSB] / LBA  
Start sector No.  
/ LBA [LSB]  
Transfer sector count  
xx  
R = 0 or 1  
5 - 20  
C141-E093-01EN  
At command completion (I/O registers contents to be read)  
1F7H(ST) Status information  
DV End head No. /LBA [MSB]  
1F6H(DH)  
L
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
End cylinder No. [MSB] / LBA  
End cylinder No. [LSB] / LBA  
End sector No.  
/ LBA [LSB]  
00 (*1)  
Error information  
*1 If the command is terminated due to an error, the remaining number of  
sectors of which data was not transferred is set in this register.  
(4)  
READ VERIFY SECTOR(S) (X'40' or X'41')  
This command operates similarly to the READ SECTOR(S) command except that the data is  
not transferred to the host system.  
After all requested sectors are verified, the device clears the BSY bit of the Status register and  
generates an interrupt. Upon the completion of the command execution, the command block  
registers contain the cylinder, head, and sector number of the last sector verified.  
If an error occurs, the verify operation is terminated at the sector where the error occurred. The  
command block registers contain the cylinder, the head, and the sector addresses (in the CHS  
mode) or the logical block address (in the LBA mode) of the sector where the error occurred.  
The Sector Count register indicates the number of sectors that have not been verified.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
0
1
0
0
0
0
0
R
L
DV Start head No. /LBA [MSB]  
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
Start cylinder No. [MSB]/ LBA  
Start cylinder No. [LSB] / LBA  
Start sector No.  
/ LBA [LSB]  
Transfer sector count  
xx  
R = 0 or 1  
C141-E093-01EN  
5 - 21  
At command completion (I/O registers contents to be read)  
1F7H(ST) Status information  
DV End head No. /LBA [MSB]  
1F6H(DH)  
L
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
End cylinder No. [MSB] / LBA  
End cylinder No. [LSB] / LBA  
End sector No.  
/ LBA [LSB]  
00 (*1)  
Error information  
*1 If the command is terminated due to an error, the remaining number of  
sectors of which data was not transferred is set in this register.  
(5)  
WRITE SECTOR(S) (X'30' or X'31')  
This command writes data of sectors from the address specified in the Device/Head, Cylinder  
High, Cylinder Low, and Sector Number registers to the address specified in the Sector Count  
register. Number of sectors can be specified to 256 sectors in maximum. Data transfer begins  
at the sector specified in the Sector Number register. For the DRQ, INTRQ, and BSY  
protocols related to data transfer, see Subsection 5.4.2.  
If the head is not on the track specified by the host, the device performs a implied seek. After  
the head reaches to the specified track, the device writes the target sector.  
The data stored in the buffer, and CRC code and ECC bytes are written to the data field of the  
corresponding sector(s). Upon the completion of the command execution, the command block  
registers contain the cylinder, head, and sector addresses of the last sector written.  
If an error occurs during multiple sector write operation, the write operation is terminated at  
the sector where the error occurred. Command block registers contain the cylinder, the head,  
the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the  
sector where the error occurred. Then the host can read the command block registers to  
determine what error has occurred and on which sector the error has occurred.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
0
0
1
1
0
0
0
R
L
DV Start head No. /LBA [MSB]  
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
Start cylinder No. [MSB]/ LBA  
Start cylinder No. [LSB] / LBA  
Start sector No.  
/ LBA [LSB]  
Transfer sector count  
xx  
R = 0 or 1  
5 - 22  
C141-E093-01EN  
At command completion (I/O registers contents to be read)  
1F7H(ST) Status information  
DV End head No. /LBA [MSB]  
1F6H(DH)  
L
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
End cylinder No. [MSB] / LBA  
End cylinder No. [LSB] / LBA  
End sector No.  
/ LBA [LSB]  
00 (*1)  
Error information  
*1 If the command is terminated due to an error, the remaining number of  
sectors of which data was not transferred is set in this register.  
(6)  
WRITE MULTIPLE (X'C5')  
This command is similar to the WRITE SECTOR(S) command. The device does not generate  
interrupts (assertion of the INTRQ signal) on each sector but on the transfer of a block which  
contains the number of sectors for which the number is defined by the SET MULTIPLE  
MODE command.  
The implementation of the WRITE MULTIPLE command is identical to that of the WRITE  
SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE  
MODE command are transferred without intervening interrupts. In the WRITE MULTIPLE  
command operation, the DRQ bit of the Status register is required to set only at the start of the  
data block, not on each sector.  
The number of sectors (block count) to be transferred without interruption is specified by the  
SET MULTIPLE MODE command. The SET MULTIPLE MODE command should be  
executed prior to the WRITE MULTIPLE command.  
When the WRITE MULTIPLE command is issued, the Sector Count register contains the number  
of sectors requested (not a number of the block count or a number of sectors in a block).  
Upon receipt of this command, the device executes this command even if the value of the Sector  
Count register is less than the defined block count the value of the Sector Count should not be 0).  
If the number of requested sectors is not divided evenly (having the same number of sectors  
[block count]), as many full blocks as possible are transferred, then a final partial block is  
transferred. The number of sectors in the partial block to be transferred is n where n =  
remainder of ("number of sectors"/"block count").  
If the WRITE MULTIPLE command is issued before the SET MULTIPLE MODE command  
is executed or when WRITE MULTIPLE command is disabled, the device rejects the WRITE  
MULTIPLE command with an ABORTED COMMAND error.  
Disk errors encountered during execution of the WRITE MULTIPLE command are posted after  
attempting to write the block or the partial block that was transferred. Write operation ends at the  
sector where the error was encountered even if the sector is in the middle of a block. If an error  
occurs, the subsequent block shall not be transferred. Interrupts are generated when the DRQ bit of  
the Status register is set at the beginning of each block or partial block.  
C141-E093-01EN  
5 - 23  
The contents of the command block registers related to addresses after the transfer of a data  
block containing an erred sector are undefined. To obtain a valid error information, the host  
should retry data transfer as an individual requests.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
1
1
0
0
0
1
0
1
L
DV Start head No. /LBA [MSB]  
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
Start cylinder No. [MSB]/ LBA  
Start cylinder No. [LSB] / LBA  
Start sector No.  
Transfer sector count  
xx  
/ LBA [LSB]  
At command completion (I/O registers contents to be read)  
1F7H(ST) Status information  
DV End head No. /LBA [MSB]  
1F6H(DH)  
L
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
End cylinder No. [MSB] / LBA  
End cylinder No. [LSB] / LBA  
End sector No.  
/ LBA [LSB]  
00H  
Error information  
Note:  
When the command terminates due to error, only the DV bit and the error information  
field are valid.  
(7)  
WRITE DMA (X'CA' or X'CB')  
This command operates similarly to the WRITE SECTOR(S) command except for following  
events.  
·
·
·
The data transfer starts at the timing of DMARQ signal assertion.  
The device controls the assertion or negation timing of the DMARQ signal.  
The device posts a status as the result of command execution only once at completion of  
the data transfer.  
When an error, such as an unrecoverable medium error, that the command execution cannot be  
continued is detected, the data transfer is stopped without transferring data of sectors after the  
erred sector. The device generates an interrupt using the INTRQ signal and posts a status to  
the host system. The format of the error information is the same as the WRITE SECTOR(S)  
command.  
A host system can be select the following transfer mode using the SET FEATURES  
command.  
5 - 24  
C141-E093-01EN  
1) Multiword DMA transfer mode 2:  
Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command  
2) Ultra DMA transfer mode 2:  
Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES command  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
1
1
0
0
1
0
1
R
L
DV Start head No. /LBA [MSB]  
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
Start cylinder No. [MSB]/ LBA  
Start cylinder No. [LSB] / LBA  
Start sector No.  
Transfer sector count  
xx  
/ LBA [LSB]  
R = 0 or 1  
At command completion (I/O registers contents to be read)  
1F7H(ST) Status information  
DV End head No. /LBA [MSB]  
1F6H(DH)  
L
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
End cylinder No. [MSB] / LBA  
End cylinder No. [LSB] / LBA  
End sector No.  
/ LBA [LSB]  
00 (*1)  
Error information  
*1 If the command is terminated due to an error, the remaining number of  
sectors of which data was not transferred is set in this register.  
(8)  
WRITE VERIFY (X'3C')  
This command operates similarly to the WRITE SECTOR(S) command except that the device  
verifies each sector immediately after being written. The verify operation is a read and check for  
data errors without data transfer. Any error that is detected during the verify operation is posted.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
0
0
1
1
1
1
0
0
L
DV Start head No. /LBA [MSB]  
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
Start cylinder No. [MSB]/ LBA  
Start cylinder No. [LSB] / LBA  
Start sector No.  
/ LBA [LSB]  
Transfer sector count  
xx  
C141-E093-01EN  
5 - 25  
At command completion (I/O registers contents to be read)  
1F7H(ST) Status information  
DV End head No. /LBA [MSB]  
1F6H(DH)  
L
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
End cylinder No. [MSB] / LBA  
End cylinder No. [LSB] / LBA  
End sector No.  
/ LBA [LSB]  
00 (*1)  
Error information  
*1 If the command is terminated due to an error, the remaining number of  
sectors of which data was not transferred is set in this register.  
(9)  
RECALIBRATE (X'1x', x: X'0' to X'F')  
This command performs the calibration. Upon receipt of this command, the device sets BSY  
bit of the Status register and performs a calibration. When the device completes the  
calibration, the device updates the Status register, clears the BSY bit, and generates an  
interrupt.  
This command can be issued in the LBA mode.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
0
0
0
1
x
x
x
x
DV  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
xx  
xx  
xx  
xx  
xx  
At command completion (I/O registers contents to be read)  
1F7H(ST)  
Status information  
DV  
1F6H(DH)  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
xx  
xx  
xx  
xx  
Error information  
5 - 26  
C141-E093-01EN  
(10)  
SEEK (X'7x', x : X'0' to X'F')  
This command performs a seek operation to the track and selects the head specified in the  
command block registers. After completing the seek operation, the device clears the BSY bit  
in the Status register and generates an interrupt.  
The IDD always sets the DSC bit (Drive Seek Complete status) of the Status register to 1.  
In the LBA mode, this command performs the seek operation to the cylinder and head position  
in which the sector is specified with the logical block address.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
0
1
1
1
x
x
x
x
L
DV  
Head No. /LBA [MSB]  
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
Cylinder No. [MSB]  
Cylinder No. [LSB] / LBA  
Sector No. / LBA [LSB]  
/ LBA  
xx  
xx  
At command completion (I/O registers contents to be read)  
1F7H(ST) Status information  
DV Head No. /LBA [MSB]  
Cylinder No. [MSB] / LBA  
1F6H(DH)  
L
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
Cylinder No. [LSB] / LBA  
Sector No. / LBA [LSB]  
xx  
Error information  
C141-E093-01EN  
5 - 27  
(11)  
INITIALIZE DEVICE PARAMETERS (X'91')  
The host system can set the number of sectors per track and the maximum head number  
(maximum head number is "number of heads minus 1") per cylinder with this command.  
Upon receipt of this command, the device sets the BSY bit of Status register and saves the  
parameters. Then the device clears the BSY bit and generates an interrupt.  
When the SC register is specified to X'00', an ABORTED COMMAND error is posted. Other  
than X'00' is specified, this command terminates normally.  
The parameters set by this command are retained even after reset or power save operation  
regardless of the setting of disabling the reverting to default setting.  
In LBA mode  
The device ignores the L bit specification and operates with the CHS mode specification. An  
accessible area of this command within head moving in the LBA mode is always within a default  
area. It is recommended that the host system refers the addressable user sectors (total number of  
sectors) in word 60 to 61 of the parameter information by the IDENTIFY DEVICE command.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
1
0
0
1
0
0
0
1
DV  
Max. head No.  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
xx  
xx  
xx  
Number of sectors/track  
xx  
At command completion (I/O registers contents to be read)  
1F7H(ST) Status information  
DV Max. head No.  
1F6H(DH)  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
xx  
xx  
xx  
xx  
Error Information  
(12)  
IDENTIFY DEVICE (X'EC')  
The host system issues the IDENTIFY DEVICE command to read parameter information (512  
bytes) from the device. Upon receipt of this command, the drive sets the BSY bit of Status  
register and sets required parameter information in the sector buffer. The device then sets the  
DRQ bit of the Status register, and generates an interrupt. After that, the host system reads the  
information out of the sector buffer. Table 5.5 shows the arrangements and values of the  
parameter words and the meaning in the buffer.  
5 - 28  
C141-E093-01EN  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
1
1
1
0
1
1
0
0
DV  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
xx  
xx  
xx  
xx  
xx  
At command completion (I/O registers contents to be read)  
1F7H(ST)  
Status information  
DV  
1F6H(DH)  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
xx  
xx  
xx  
xx  
Error information  
C141-E093-01EN  
5 - 29  
Table 5.5 Information to be read by IDENTIFY DEVICE command (1 of 4)  
Word  
0
Value  
X‘045A’  
*2  
Description  
General Configuration *1  
Number of cylinders  
Reserved  
1
2
X‘0000’  
*3  
3
Number of Heads  
Retired  
4
X‘0000’  
X‘0000’  
X‘003F’  
5
Retired  
6
Number of sectors per track  
7-9  
10-19  
20  
X‘000000000000’ Retired  
–
Serial number (ASCII code) *4  
X‘0000’  
X‘0400’  
X‘0004’  
–
Retired  
21  
Buffer size in 512 byte increments  
22  
Number of ECC bytes transferred at READ LONG or WRITE LONG command  
Firmware revision (ASCII code) *5  
Model number (ASCII code) *6  
23-26  
27-46  
47  
–
X‘8010’  
X‘0000’  
X‘0B00’  
X‘0000’  
X‘0200’  
X‘0000’  
X‘0007’  
(Variable)  
(Variable)  
(Variable)  
(Variable)  
*10  
Maximum number of sectors per interrupt on READ/WRITE MULTIPLE command  
Reserved  
48  
49  
Capabilities *7  
50  
Reserved  
51  
PIO data transfer mode *8  
52  
Retired  
53  
Enable/disable setting of words 54-58, 64-70 and 88 *9  
umber of current Cylinders  
54  
55  
Number of current Head  
56  
Number of current sectors per track  
Total number of current sectors  
57-58  
59  
Transfer sector count currently set by READ/WRITE MULTIPLE command  
Total number of user addressable sectors (LBA mode only)  
Retired  
60-61  
62  
*11  
X‘0000’  
X‘xx07’  
X‘0003’  
X‘0078’  
X‘0078’  
X‘0078’  
X‘0078’  
X‘00’  
63  
Multiword DMA transfer mode *12  
Advance PIO transfer mode support status *13  
Minimum multiword DMA transfer cycle time per word : 120 [ns]  
Manufacturer's recommended DMA transfer cycle time : 120 [ns]  
Minimum PIO transfer cycle time without flow control : 120 [ns]  
Minimum PIO transfer cycle time with IORDY flow control : 120 [ns]  
Reserved  
64  
65  
66  
67  
68  
69-79  
80  
X‘001E’  
X‘0000’  
X‘3469’  
X‘4008’  
X‘4000’  
X‘00xx’  
X‘000x’  
X‘4000’  
X‘xx1F’  
X‘00xx’  
X‘0000’  
X‘00xx’  
X‘0000’  
X‘x000’  
X‘00’  
Major version number *14  
81  
Minor version number (not reported)  
Support of command sets *15  
82  
83  
Support of command sets *16  
84  
Support of command set/feature extension (fixed)  
Enable/disable Command set/feature enabled. *17  
Enable/disable Command set/feature enabled. *18  
Default of command set/feature (fixed)  
Ultra DMA modes *19  
85  
86  
87  
88  
89  
Time required for security erase unit completion *20  
Time required for Enhanced security erase completion  
Current advanced power management value  
Reserved  
90  
91  
92  
93  
CBLID detection results *21  
94-127  
128  
129-255  
Reserved  
X‘xx’  
Security Status  
X‘00’  
Reserved  
5 - 30  
C141-E093-01EN  
Table 5.5 Information to be read by IDENTIFY DEVICE command (2 of 4)  
*1 Word 0: General configuration  
Bit 15: 0 = ATA device  
0
Bit 14-8: Vendor specific  
Bit 7: 1 = Removable media device  
Bit 6: 1 = not removable controller and/or device  
Bit 5-1: Vendor specific  
0
1
Bit 0: Reserved  
0
*2 Number of Cylinders, *3 Number of Heads,  
*11 Total number of user addressable sectors (LBA mode only.)  
MPE3043AE MPE3084AE MPE3173AE  
*2  
*3  
X‘22FF’  
X‘0F’  
X‘3FFF’  
X‘10’  
*11 X‘812F4F’  
X‘FBFC10’ X‘204C5B4’  
*4 Word 10-19: Serial number; ASCII code (20 characters, right-justified)  
*5 Word 23-26: Firmware revision; ASCII code (8 characters, Left-justified)  
*6 Word 27-46: Model number;  
ASCII code (40 characters, Left-justified), remainder filled with blank code (X'20')  
One of the following model numbers;  
MPE3043AE, MPE3084AE, MPE3173AE  
*7 Word 49: Capabilities  
Bit 15-14: Reserved  
Bit 13:  
Bit 12:  
Bit 11:  
Bit 10:  
Bit 9:  
Standby timer value 0 = Standby timer values shall be managed by the device  
Reserved  
IORDY support  
1=Supported  
IORDY inhibition 0=Disable inhibition  
LBA support  
DMA support  
1=Supported  
1=Supported  
Bit 8:  
Bit 7-0: Vendor specific  
*8 Word 51: PIO data transfer mode  
Bit 15-8: PIO data transfer mode  
Bit 7-0: Vendor specific  
X'02'=PIO mode 2  
*9 Word 53: Enable/disable setting of word 54-58 ,64-70 and 88  
Bit 15-3: Reserved  
Bit 2:  
Bit 1:  
Bit 0:  
Enable/disable setting of word 88  
Enable/disable setting of word 64-70 1=Enable  
Enable/disable setting of word 54-58 1=Enable  
1=Enable  
*10 Word 59: Transfer sector count currently set by READ/WRITE MULTIPLE command  
Bit 15-9: Reserved  
Bit 8:  
Multiple sector transfer 1=Enable  
Bit 7-0: Transfer sector count currently set by READ/WRITE MULTIPLE without interrupt  
supports 2, 4, 8 and 16 sectors.  
C141-E093-01EN  
5 - 31  
Table 5.5 Information to be read by IDENTIFY DEVICE command (3 of 4)  
*12 Word 63: Multiword DMA transfer mode  
Bit 15-8: Currently used multiword DMA transfer mode  
Bit 7-0: Supportable multiword DMA transfer mode  
Bit 2=1 Mode 2  
Bit 1=1 Mode 1  
Bit 0=1 Mode 0  
*13 Word 64: Advance PIO transfer mode support status  
Bit 15-8: Reserved  
Bit 7-0: Advance PIO transfer mode  
Bit 1=1 Mode 4  
Bit 0=1 Mode 3  
*14 Word 80: Major version number  
Bit 15-5: Reserved  
Bit 4:  
Bit 3:  
Bit 2:  
Bit 1:  
Bit 0:  
ATA-4 Supported=1  
ATA-3 Supported=1  
ATA-2 Supported=1  
ATA-1 Supported=1  
Undefined  
*15 Word 82: Support of command sets  
Bit 15: Reserved  
Bit 14: NOP command supported = 0  
Bit 13: Read Buffer command supported = 1  
Bit 12: Write Buffer command supported = 1  
Bit 11: Write Verify command supported (Old Spec.) = 0  
Bit 10: Host Protected Area feature command supported = 1  
Bit 9:  
Bit 8:  
Bit 7:  
Bit 6:  
Bit 5:  
Bit 4:  
Bit 3:  
Bit 2:  
Bit 1:  
Bit 0:  
Device Reset command supported = 0  
SERVICE Interrupt supported = 0  
Release Interrupt supported = 0  
Lock Ahead supported = 1  
Write-cache supported = 1  
Packet command feature set supported = 0  
Power Management feature set supported=1  
Removable feature set supported=0  
Security feature set supported=0  
SMART feature set supported=1  
*16 Word 83: Support of command sets  
Bit 15:  
Bit 14:  
0
1
Bit 13-5: Reserved  
Bit 4:  
Bit 3:  
Bit 2:  
Bit 1:  
Bit 0:  
Removable Media Status Notification feature set supported = 0  
Advanced Power Management feature set supported = 1  
CFA feature set supported = 0  
READ/WRITE DMA QUEUED supported = 0  
DOWNLOAD MICROCODE command supported = 0  
5 - 32  
C141-E093-01EN  
Table 5.5 Information to be read by IDENTIFY DEVICE command (4 of 4)  
*17 Word 85: Enable/disable Command set/feature enabled  
Bit 15:  
Bit 14:  
Bit 13:  
Bit 12:  
Bit 11:  
Bit 10:  
Bit 9:  
Bit 8:  
Bit 7:  
Bit 6:  
Bit 5:  
Bit 4:  
Bit 3:  
Bit 2:  
Bit 1:  
Bit 0:  
Reserved  
NOP command supported = 0  
READ BUFFER command supported = 0  
WRITE BUFFER command supported = 0  
Reserved  
Host Protected Area feature set supported = 0  
DEVICE RESET command supported = 0  
SERVICE interrupt enabled = 0  
Release interrupt enabled = 0  
Look-ahead enabled = 1  
Write cache enabled = 1  
PACKET Command feature set supported = 0  
Power Management feature set supported = 0  
Removable Media feature set supported = 0  
Security Mode feature set enabled = 0  
SMART feature set enabled = 1  
*18 Word 86: Enable/disable Command set/feature enabled  
Bit 15-5: Reserved  
Bit 4:  
Bit 3:  
Bit 2:  
Bit 1:  
Bit 0:  
Removable Media Status Notification feature set enabled = 0  
Advanced Power Management feature set enabled = 1  
CFA feature set supported = 0  
READ/WRITE DMA QUEUED command supported = 0  
DOWNLOAD MICROCODE command supported = 0  
*19 Word 88: Ultra DMA modes  
Bit 15-13: Reserved  
Bit 12-8: Currently used Ultra DMA transfer modes  
Bit 7-5: Reserved  
Bit 4-0: Supportable Ultra DMA transfer mode  
Bit 4=1 Mode 4  
Bit 3=1 Mode 3  
Bit 2=1 Mode 2  
Bit 1=1 Mode 1  
Bit 0=1 Mode 0  
*20 Word 89: Time required for SECURITY ERASE UNIT command to complete  
MPE3102AH: X’0009’ (18 minutes)  
MPE3136AH: X’000C’ (24 minutes)  
MPE3204AH: X’0012’ (36 minutes)  
MPE3273AH: X’0018’ (48 minutes)  
*21 Word 93: CBLID– detection results  
Bit 15-14: Reserved  
Bit 13:  
Device detected CBLID– above VIH (80-conductor cable) = 1  
Device detected CBLID– below VIL (40-conductor cable) = 0  
Reserved  
Bit 12-0:  
C141-E093-01EN  
5 - 33  
(13)  
IDENTIFY DEVICE DMA (X'EE')  
When this command is not used to transfer data to the host in DMA mode, this command  
functions in the same way as the Identify Device command.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
1
1
1
0
1
1
1
0
DV  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
xx  
xx  
xx  
xx  
xx  
At command completion (I/O registers contents to be read)  
1F7H(ST)  
Status information  
DV  
1F6H(DH)  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
xx  
xx  
xx  
xx  
Error information  
(14)  
SET FEATURES (X'EF')  
The host system issues the SET FEATURES command to set parameters in the Features  
register for the purpose of changing the device features to be executed. For the transfer mode  
(Feature register = 03), detail setting can be done using the Sector Count register.  
Upon receipt of this command, the device sets the BSY bit of the Status register and saves the  
parameters in the Features register. Then, the device clears the BSY bit, and generates an  
interrupt.  
If the value in the Features register is not supported or it is invalid, the device posts an  
ABORTED COMMAND error.  
Table 5.6 lists the available values and operational modes that may be set in the Features  
register.  
5 - 34  
C141-E093-01EN  
Table 5.6 Features register values and settable modes  
Features Register  
X‘02’  
Drive operation mode  
Enables the write cache function.  
X‘03’  
Specifies the transfer mode. Supports PIO mode 4, single word DMA mode  
2, and multiword DMA mode regardless of Sector Count register contents.  
X‘04’  
X‘05’  
X‘33’  
X‘54’  
X‘55’  
X‘66’  
X‘77’  
X‘81’  
X‘82’  
X‘84’  
X‘85’  
X‘88’  
X‘99’  
X‘AA’  
X‘AB’  
X‘BB’  
No operation.  
Enable the advanced power management function.  
No operation.  
No operation.  
Disables read cache function.  
Disables the reverting to power-on default settings after software reset.  
No operation.  
No operation.  
Disables the write cache function.  
No operation.  
Disable the advanced power management function.  
No operation.  
No operation.  
Enables the read cache function.  
No operation.  
Specifies the transfer of 4-byte ECC for READ LONG and WRITE LONG  
commands.  
X‘CC’  
Enables the reverting to power-on default settings after software reset.  
At power-on or after hardware reset, the default mode is the same as that is set with a value  
greater than X‘AA’ (except for write cache). If X‘66’ is specified, it allows the setting value  
greater than X‘AA’ which may have been modified to a new value since power-on, to remain  
the same even after software reset.  
C141-E093-01EN  
5 - 35  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
1
1
1
0
1
1
1
1
DV  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
xx  
xx  
xx  
xx or transfer mode  
[See Table 5.6]  
At command completion (I/O registers contents to be read)  
1F7H(ST)  
Status information  
DV  
1F6H(DH)  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
xx  
xx  
xx  
xx  
Error information  
The host sets X'03' to the Features register. By issuing this command with setting a value to  
the Sector Count register, the transfer mode can be selected. Upper 5 bits of the Sector Count  
register defines the transfer type and lower 3 bits specifies the binary mode value.  
However, the IDD can operate with the PIO transfer mode 4 and multiword DMA transfer  
mode 2 regardless of reception of the SET FEATURES command for transfer mode setting.  
The IDD supports following values in the Sector Count register value. If other value than  
below is specified, an ABORTED COMMAND error is posted.  
PIO default transfer mode  
00000 000 (X‘00’)  
PIO flow control transfer mode X  
00001 000 (X‘08’: Mode 0)  
00001 001 (X‘09’: Mode 1)  
00001 010 (X‘0A’: Mode 2)  
00001 011 (X‘0B’: Mode 3)  
00001 100 (X‘0C’: Mode 4)  
Multiword DMA transfer mode X  
Ultra DMA transfer mode X  
00100 000 (X‘20’: Mode 0)  
00100 001 (X‘21’: Mode 1)  
00100 010 (X‘22’: Mode 2)  
01000 000 (X‘40’: Mode 0)  
01000 001 (X‘41’: Mode 1)  
01000 010 (X‘42’: Mode 2)  
01000 011 (X‘43’: Mode 3)  
01000 100 (X‘44’: Mode 4)  
5 - 36  
C141-E093-01EN  
(15)  
SET MULTIPLE MODE (X'C6')  
This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE  
commands. The block count (number of sectors in a block) for these commands are also  
specified by the SET MULTIPLE MODE command.  
The number of sectors per block is written into the Sector Count register. The IDD supports 2,  
4, 8 and 16 (sectors) as the block counts.  
Upon receipt of this command, the device sets the BSY bit of the Status register and checks  
the contents of the Sector Count register. If the contents of the Sector Count register is valid  
and is a supported block count, the value is stored for all subsequent READ MULTIPLE and  
WRITE MULTIPLE commands. Execution of these commands is then enabled. If the value  
of the Sector Count register is not a supported block count, an ABORTED COMMAND error  
is posted and the READ MULTIPLE and WRITE MULTIPLE commands are disabled.  
If the contents of the Sector Count register is 0 when the SET MULTIPLE MODE command  
is issued, the READ MULTIPLE and WRITE MULTIPLE commands are disabled.  
When the SET MULTIPLE MODE command operation is completed, the device clears the  
BSY bit and generates an interrupt.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
1
1
0
0
0
1
1
0
DV  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
xx  
xx  
xx  
Sector count/block  
xx  
At command completion (I/O registers contents to be read)  
1F7H(ST)  
Status information  
DV  
1F6H(DH)  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
xx  
xx  
xx  
Sector count/block  
Error information  
After power-on or after hardware reset, the READ MULTIPLE and WRITE MULTIPLE  
command operation are disabled as the default mode.  
C141-E093-01EN  
5 - 37  
Regarding software reset, the mode set prior to software reset is retained after software reset.  
The parameters for the multiple commands which are posted to the host system when the  
IDENTIFY DEVICE command is issued are listed below. See Subsection 5.3.2 for the  
IDENTIFY DEVICE command.  
Word 47 = 8010: Maximum number of sectors that can be transferred per interrupt by the  
READ MULTIPLE and WRITE MULTIPLE commands are 16 (fixed).  
Word 59 = 0000: The READ MULTIPLE and WRITE MULTIPLE commands are  
disabled.  
= 01xx:  
The READ MULTIPLE and WRITE MULTIPLE commands are  
enabled. "xx" indicates the current setting for number of sectors that can  
be transferred per interrupt by the READ MULTIPLE and WRITE  
MULTIPLE commands.  
e.g. 0110 = Block count of 16 has been set by the SET MULTIPLE  
MODE command.  
(16)  
EXECUTE DEVICE DIAGNOSTIC (X'90')  
This command performs an internal diagnostic test (self-diagnosis) of the device. This  
command usually sets the DRV bit of the Drive/Head register is to 0 (however, the DV bit is  
not checked). If two devices are present, both devices execute self-diagnosis.  
If device 1 is present:  
·
·
·
Both devices shall execute self-diagnosis.  
The device 0 waits for up to 5 seconds until device 1 asserts the PDIAG- signal.  
If the device 1 does not assert the PDIAG- signal but indicates an error, the device 0 shall  
append X‘80’ to its own diagnostic status.  
·
·
The device 0 clears the BSY bit of the Status register and generates an interrupt. (The  
device 1 does not generate an interrupt.)  
A diagnostic status of the device 0 is read by the host system. When a diagnostic failure  
of the device 1 is detected, the host system can read a status of the device 1 by setting the  
DV bit (selecting the device 1).  
When device 1 is not present:  
·
·
The device 0 posts only the results of its own self-diagnosis.  
The device 0 clears the BSY bit of the Status register, and generates an interrupt.  
Table 5.7 lists the diagnostic code written in the Error register which is 8-bit code.  
If the device 1 fails the self-diagnosis, the device 0 "ORs" X‘80’ with its own status and sets  
that code to the Error register.  
5 - 38  
C141-E093-01EN  
Table 5.7 Diagnostic code  
Code  
Result of diagnostic  
X‘01’  
X‘03’  
X‘05’  
X‘8x’  
No error detected.  
Data buffer compare error  
ROM sum check error  
Failure of device 1  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
1
0
0
1
0
0
0
0
DV  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
xx  
xx  
xx  
xx  
xx  
At command completion (I/O registers contents to be read)  
1F7H(ST)  
Status information  
00  
1F6H(DH)  
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
00  
00  
01H  
01H  
Diagnostic code  
(17)  
FORMAT TRACK (X'50')  
Upon receipt of this command, the device sets the DRQ bit and waits the completion of 512-  
byte format parameter transfer from the host system. After completion of transfer, the device  
clears the DRQ bits, sets the BSY bit. However the device does not perform format operation,  
but the drive clears the BYS bit and generates an interrupt soon. When the command  
execution completes, the device clears the BSY bit and generates an interrupt.  
The drive supports this command for keep the compatibility with previous drive only.  
READ LONG (X'22' or X'23')  
(18)  
This command operates similarly to the READ SECTOR(S) command except that the device  
transfers the data in the requested sector and the ECC bytes to the host system. The ECC error  
correction is not performed for this command. This command is used for checking ECC  
function by combining with the WRITE LONG command.  
C141-E093-01EN  
5 - 39  
The READ LONG command supports only single sector operation.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
0
0
1
0
0
0
1
R
L
DV  
Head No. /LBA [MSB]  
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
Cylinder No. [MSB]  
Cylinder No. [LSB] / LBA  
/ LBA  
Sector No.  
/ LBA [LSB]  
Number of sectors to be transferred  
xx  
R = 0 or 1  
At command completion (I/O registers contents to be read)  
1F7H(ST) Status information  
DV Head No. /LBA [MSB]  
Cylinder No. [MSB] / LBA  
1F6H(DH)  
L
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
Cylinder No. [LSB] / LBA  
Sector No. / LBA [LSB]  
00 (*1)  
Error information  
*1 If the command is terminated due to an error, this register indicates 01.  
(19)  
WRITE LONG (X'32' or X'33')  
This command operates similarly to the READ SECTOR(S) command except that the device  
writes the data and the ECC bytes transferred from the host system to the disk medium. The  
device does not generate ECC bytes by itself. The WRITE LONG command supports only  
single sector operation.  
This command is operated under the following conditions:  
·
The command is issued in a sequence of the READ LONG or WRITE LONG (to the same  
address) command issuance. (WRITE LONG command can be continuously issued after  
the READ LONG command.)  
If above condition is not satisfied, the command operation is not guaranteed.  
5 - 40  
C141-E093-01EN  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
0
0
1
1
0
0
1
R
L
DV  
Head No. /LBA [MSB]  
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
Cylinder No. [MSB]  
Cylinder No. [LSB] / LBA  
/ LBA  
Sector No.  
/ LBA [LSB]  
Number of sectors to be transferred  
xx  
R = 0 or 1  
At command completion (I/O registers contents to be read)  
1F7H(ST) Status information  
DV Head No. /LBA [MSB]  
Cylinder No. [MSB] / LBA  
1F6H(DH)  
L
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
Cylinder No. [LSB] / LBA  
Sector No. / LBA [LSB]  
00 (*1)  
Error information  
*1 If the command is terminated due to an error, this register indicates 01.  
(20)  
READ BUFFER (X'E4')  
The host system can read the current contents of the sector buffer of the device by issuing this  
command. Upon receipt of this command, the device sets the BSY bit of Status register and  
sets up the sector buffer for a read operation. Then the device sets the DRQ bit of Status  
register, clears the BSY bit, and generates an interrupt. After that, the host system can read up  
to 512 bytes of data from the buffer.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
1
1
1
0
0
1
0
0
DV  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
xx  
xx  
xx  
xx  
xx  
C141-E093-01EN  
5 - 41  
At command completion (I/O registers contents to be read)  
1F7H(ST)  
Status information  
DV  
1F6H(DH)  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
xx  
xx  
xx  
xx  
Error information  
(21)  
WRITE BUFFER (X'E8')  
The host system can overwrite the contents of the sector buffer of the device with a desired  
data pattern by issuing this command. Upon receipt of this command, the device sets the BSY  
bit of the Status register. Then the device sets the DRQ bit of Status register and clears the  
BSY bit when the device is ready to receive the data. After that, 512 bytes of data is  
transferred from the host and the device writes the data to the sector buffer, then generates an  
interrupt.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
1
1
1
0
1
0
0
0
DV  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
xx  
xx  
xx  
xx  
xx  
At command completion (I/O registers contents to be read)  
1F7H(ST)  
Status information  
DV  
1F6H(DH)  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
xx  
xx  
xx  
xx  
Error information  
5 - 42  
C141-E093-01EN  
(22)  
IDLE (X'97' or X'E3')  
Upon receipt of this command, the device sets the BSY bit of the Status register, and enters  
the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device  
generates an interrupt even if the device has not fully entered the idle mode. If the spindle of  
the device is already rotating, the spin-up sequence shall not be implemented.  
If the contents of the Sector Count register is other than 0, the automatic power-down function  
is enabled and the timer starts countdown immediately. When the timer reaches the specified  
time, the device enters the standby mode.  
If the contents of the Sector Count register is 0, the automatic power-down function is  
disabled.  
Enabling the automatic power-down function means that the device automatically enters the  
standby mode after a certain period of time. When the device enters the idle mode, the timer  
starts countdown. If any command is not issued while the timer is counting down, the device  
automatically enters the standby mode. If any command is issued while the timer is counting  
down, the timer is initialized and the command is executed. The timer restarts countdown after  
completion of the command execution.  
The period of timer count is set depending on the value of the Sector Count register as shown  
below.  
Sector Count register value  
[X'00']  
Point of timer  
Disable of timer  
0
1 to 240  
[X'01' to X'F0']  
(Value ´ 5) seconds  
(Value – 240) ´ 30 minutes  
21 minutes  
241 to 251 [X'F1' to X'FB']  
252  
253  
[X'FC']  
[X'FD']  
8 hours  
254 to 255 [X'FE' to X'FF']  
21 minutes 15 seconds  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
X'97' or X'E3'  
DV  
1F6H(DH)  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
xx  
xx  
xx  
Period of timer  
xx  
C141-E093-01EN  
5 - 43  
At command completion (I/O registers contents to be read)  
1F7H(ST)  
Status information  
DV  
1F6H(DH)  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
xx  
xx  
xx  
xx  
Error information  
(23)  
IDLE IMMEDIATE (X'95' or X'E1')  
Upon receipt of this command, the device sets the BSY bit of the Status register, and enters  
the idle mode. Then, the device clears the BSY bit, and generates an interrupt. This command  
does not support the automatic power-down function.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
X'95' or X'E1'  
DV  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
xx  
xx  
xx  
xx  
xx  
At command completion (I/O registers contents to be read)  
1F7H(ST)  
Status information  
DV  
1F6H(DH)  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
xx  
xx  
xx  
xx  
Error information  
5 - 44  
C141-E093-01EN  
(24)  
STANDBY (X'96' or X'E2')  
Upon receipt of this command, the device sets the BSY bit of the Status register and enters the  
standby mode. The device then clears the BSY bit and generates an interrupt. The device  
generates an interrupt even if the device has not fully entered the standby mode. If the device  
has already spun down, the spin-down sequence is not implemented.  
If the contents of the Sector Count register is other than 0, the automatic power-down function  
is enabled and the timer starts countdown when the device returns to idle mode.  
When the timer value reaches 0 (passed a specified time), the device enters the standby mode.  
If the contents of the Sector Count register is 0, the automatic power-down function is  
disabled.  
Under the standby mode, the spindle motor is stopped. Thus, when the command involving a  
seek such as the READ SECTOR(s) command is received, the device processes the command  
after driving the spindle motor.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
X'96' or X'E2'  
DV  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
xx  
xx  
xx  
Period of timer  
xx  
At command completion (I/O registers contents to be read)  
1F7H(ST)  
Status information  
DV  
1F6H(DH)  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
xx  
xx  
xx  
xx  
Error information  
(25)  
STANDBY IMMEDIATE (X'94' or X'E0')  
Upon receipt of this command, the device sets the BSY bit of the Status register and enters the  
standby mode. The device then clears the BSY bit and generates an interrupt. This command  
does not support the automatic power-down sequence.  
C141-E093-01EN  
5 - 45  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
X'94' or X'E0'  
DV  
1F6H(DH)  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
xx  
xx  
xx  
xx  
xx  
At command completion (I/O registers contents to be read)  
1F7H(ST)  
Status information  
DV  
1F6H(DH)  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
xx  
xx  
xx  
xx  
Error information  
(26)  
SLEEP (X'99' or X'E6')  
This command is the only way to make the device enter the sleep mode.  
Upon receipt of this command, the device sets the BSY bit of the Status register and enters the  
sleep mode. The device then clears the BSY bit and generates an interrupt. The device  
generates an interrupt even if the device has not fully entered the sleep mode.  
In the sleep mode, the spindle motor is stopped and the ATA interface section is inactive. All  
I/O register outputs are in high-impedance state.  
The only way to release the device from sleep mode is to execute a software or hardware reset.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
X'99' or X'E6'  
DV  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
xx  
xx  
xx  
xx  
xx  
5 - 46  
C141-E093-01EN  
At command completion (I/O registers contents to be read)  
1F7H(ST)  
Status information  
DV  
1F6H(DH)  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
xx  
xx  
xx  
xx  
Error information  
(27)  
CHECK POWER MODE (X'98' or X'E5')  
The host checks the power mode of the device with this command.  
The host system can confirm the power save mode of the device by analyzing the contents of  
the Sector Count and Sector Number registers.  
The device sets the BSY bit and sets the following register value. After that, the device clears  
the BSY bit and generates an interrupt.  
Power save mode  
Sector Count register Sector Number register  
• During moving to standby mode  
• Standby mode  
X'00'  
N/A  
• During returning from the standby mode  
• Idle mode  
X'FF'  
X'FF'  
X'00'  
X'FF'  
• Active mode  
C141-E093-01EN  
5 - 47  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
X'98' or X'E5'  
DV  
1F6H(DH)  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
xx  
xx  
xx  
xx  
xx  
At command completion (I/O registers contents to be read)  
1F7H(ST)  
Status information  
DV  
1F6H(DH)  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
xx  
xx  
xx  
X'00', X'80' or X'FF'  
Error information  
(28)  
SMART (X'B0)  
This command performs operations for device failure predictions according to a subcommand  
specified in the FR register. If the value specified in the FR register is supported, the Aborted  
Command error is posted.  
It is necessary for the host to set the keys (CL = 4Fh and CH = C2h) in the CL and CH  
registers prior to issuing this command. If the keys are set incorrectly, the Aborted Command  
error is posted.  
In the default setting, the failure prediction feature is enabled.  
The device collects or updates several items to forecast failures. In the following sections, the  
values of items collected or updated by the device to forecast failures are referred to as  
attribute values.  
5 - 48  
C141-E093-01EN  
Table 5.8 Features Register values (subcommands) and functions (1/2)  
Features Resister Function  
X’D0’  
SMART Read Attribute Values:  
A device that received this subcommand asserts the BSY bit and saves all the  
updated attribute values. The device then clears the BSY bit and transfers 512-  
byte attribute value information to the host.  
* For infomation about the format of the attribute value information, see Table  
5.9.  
X’D1’  
X’D2’  
SMART Read Attribute Thresholds:  
This subcommand is used to transfer 512-byte insurance failure threshold value  
data to the host.  
* For information about the format of the insurance failure threshold value data,  
see Table 5.10.  
SMART Enable-Disable Attribute AutoSave:  
This subcommand is used to enable (SC register ¹ 00h) or disable (SC register =  
00h) the setting of the automatic saving feature for the device attribute data. The  
setting is maintained every time the device is turned off and then on. When the  
automatic saving feature is enabled, the attribute values are saved before the  
device enters the power saving mode. However, if the failure prediction feature  
is disabled, the attribute values are not automatically saved.  
When the device receives this subcommand, it asserts the BSY bit, enables or  
disables the automatic saving feature, then clears the BSY bit.  
SMART Save Attribute Values:  
X’D3’  
X’D4’  
When the device receives this subcommand, it asserts the BSY bit, saves device  
attribute value data, then clears the BSY bit.  
SMART Executive Off-line Immediate:  
A device which receives this command asserts the BSY bit, then starts collecting  
the off-line data specified in the SN register, or stops.  
In the off-line mode, after BSY is cleared, off-line data are collected. In the  
captive mode, it collects off-line data with the BSY assertion as is, then clears the  
BSY when collection of data is completed.  
SN  
Off-line data collection mode  
00h: Off-line diagnosis (off-line mode)  
01h: Simple self test (off-line mode)  
02h: Comprehensive self test (off-line mode)  
7Fh: Self test stop  
81h: Simple self test (captive mode)  
82h: Comprehensive self test (captive mode)  
SMART Read Log Sector:  
X’D5’  
A device which receives this sub-command asserts the BSY bit, then reads the  
log sector specified in the SN register. Next, it clears the BSY bit and transmits  
the log sector to the host computer. 01h should be specified in the SC register.  
SN:  
Log sector  
01h:  
06h:  
SMART error log  
SMART self test log  
80h-9Fh: Host vendor log  
*
See Table 5.11 concerning the SMART error log data format.  
See Table 5.12 concerning the SMART self test log data format.  
C141-E093-01EN  
5 - 49  
Table 5.8 Features Register values (subcommands) and functions (2/2)  
Features Resister Function  
X’D6’  
SMART Write Log Sector:  
A device which receives this sub-command asserts the BSY bit and when it has  
prepared to receive data from the host computer, it sets DRQ and clears the BSY  
bit. Next, it receives 512 bytes of data from the host computer and writes the  
specified log sector in the SN register. 01h should be specified in the SC register.  
SN:  
Log sector  
80h-9Fh:  
Host vendor log  
*
The host can write any desired data in the host vendor log.  
X’D8’  
X’D9’  
X’DA’  
SMART Enable Operations:  
This subcommand enables the failure prediction feature. The setting is  
maintained even when the device is turned off and then on.  
When the device receives this subcommand, it asserts the BSY bit, enables the  
failure prediction feature, then clears the BSY bit.  
SMART Disable Operations:  
This subcommand disables the failure prediction feature. The setting is  
maintained even when the device is turned off and then on.  
When the device receives this subcommand, it asserts the BSY bit, disables the  
failure prediction feature, then clears the BSY bit.  
SMART Return Status:  
When the device receives this subcommand, it asserts the BSY bit and saves the  
current device attribute values. Then the device compares the device attribute  
values with insurance failure threshold values. If there is an attribute value  
exceeding the threshold, F4h and 2Ch are loaded into the CL and CH registers. If  
there are no attribute values exceeding the thresholds, 4Fh and C2h are loaded  
into the CL and CH registers. After the settings for the CL and CH registers have  
been determined, the device clears the BSY bit.  
X’DB’  
SMART Enable/Disable Auto Off-line:  
This sets automatic off-line data collection in the enabled (when the SC register  
specification ¹ 00h) or disabled (when the SC register specification = 00) state.  
This setting is preserved whether the drive’s power is switched on or off.  
If four hours have passed since the power was switched on, or since the last time  
that off-line data were collected, off-line data collection is performed without  
relation to any command from the host computer.  
The host must regularly issue the SMART Read Attribute Values subcommand (FR register =  
D0h), SMART Save Attribute Values subcommand (FR register = D3h), or SMART Return  
Status subcommand (FR register = DAh) to save the device attribute value data on a medium.  
Alternative, the device must issue the SMART Enable-Disable Attribute AutoSave  
subcommand (FR register = D2h) to use a feature which regularly save the device attribute  
value data to a medium.  
The host can predict failures in the device by periodically issuing the SMART Return Status  
subcommand (FR register = DAh) to reference the CL and CH registers.  
5 - 50  
C141-E093-01EN  
If an attribute value is below the insurance failure threshold value, the device is about to fail or  
the device is nearing the end of its life . In this case, the host recommends that the user  
quickly backs up the data.  
At command issuance (I-O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
1
0
1
1
0
0
0
0
DV  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
Key (C2h)  
Key (4Fh)  
xx  
xx  
Subcommand  
At command completion (I-O registers setting contents)  
1F7H(ST)  
Status information  
DV  
1F6H(DH)  
xx  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
Key-failure prediction status (C2h-2Ch)  
Key-failure prediction status (4Fh-F4h)  
xx  
xx  
Error information  
The attribute value information is 512-byte data; the format of this data is shown below. The  
host can access this data using the SMART Read Attribute Values subcommand (FR register =  
D0h). The insurance failure threshold value data is 512-byte data; the format of this data is  
shown below. The host can access this data using the SMART Read Attribute Thresholds  
subcommand (FR register = D1h).  
C141-E093-01EN  
5 - 51  
Table 5.9 Format of device attribute value data  
Byte  
00, 01  
02  
Item  
Data format version number  
Attribute 1  
Attribute ID  
03, 04  
05  
Status flag  
Current attribute value  
Attribute value for worst case so far  
Raw attribute value  
Reserved  
06  
07 to 0C  
0D  
0E to 169  
Attribute 2 to  
attribute 30  
(The format of each attribute value is the same as  
that of bytes 02 to 0D.)  
16A  
16B  
Off-line data collection status  
Self test execution status  
16C, 16D  
16E  
Off-line data collection execution time [sec.]  
Reserved  
16F  
Off-line data collection capability  
Trouble prediction capability flag  
Error logging capability  
170, 171  
172  
173  
Vendor unique  
174  
Simple self test execution time [min.]  
Comprehensive self test execution time [min.]  
175  
176 to 181 Reserved  
182 to 1FE Vendor unique  
1FF  
Check sum  
5 - 52  
C141-E093-01EN  
Table 5.10 Format of insurance failure threshold value data  
Byte  
Item  
00, 01  
02  
Data format version number  
Threshold 1  
Attribute ID  
03  
Insurance failure threshold  
Reserved  
04 to 0D  
0E to 169  
Threshold 2 to  
threshold 30  
(The format of each threshold value is the same as  
that of bytes 02 to 0D.)  
16A to 17B Reserved  
17C to 1FE Vendor unique  
1FF  
Check sum  
·
·
Data format version number  
The data format version number indicates the version number of the data format of the  
device attribute values or insurance failure thresholds. The data format version numbers of  
the device attribute values and insurance failure thresholds are the same. When a data  
format is changed, the data format version numbers are updated.  
Attribute ID  
The attribute ID is defined as follows:  
Attribute ID  
Attribute name  
(Indicates unused attribute data.)  
0
1
Read error rate  
2
Throughput performance  
Spin up time  
3
4
Start/stop count  
5
Re-allocated sector count  
Seek error rate  
7
8
9
Seek time performance  
Power-on time  
10  
Number of retries made to activate the spindle motor  
Number of power-on-power-off times  
(Reserved)  
12  
13 to 198  
199  
200  
Ultra ATA CRC error rate  
Write error rate  
201 to 255 (Unique to vendor)  
C141-E093-01EN  
5 - 53  
·
Status flag  
Bit  
0
Meaning  
If this bit 1, it indicates that if the attribute exceeds the threshold, it is  
the attribute covered by the drive warranty.  
1
If this bit is 1 (0), it indicates the attribute only updated by an on-line  
test (off-line test).  
2
3
4
If this bit 1, it indicates the attribute that represents performance.  
If this bit 1, it indicates the attribute that represents an error rate.  
If this bit 1, it indicates the attribute that represents the number of  
occurrences.  
5
If this bit 1, it indicates the attribute that can be collected/saved even if  
the drive fault prediction function is disabled.  
6 to 15  
Reserve bit  
·
·
Current attribute value  
The current attribute value is the normalized raw attribute data. The value varies between  
01h and 64h. The closer the value gets to 01h, the higher the possibility of a failure. The  
device compares the attribute values with thresholds. When the attribute values are larger  
than the thresholds, the device is operating normally.  
Attribute value for the worst case so far  
This is the worst attribute value among the attribute values collected to date. This value  
indicates the state nearest to a failure so far.  
·
·
Raw attribute value  
Raw attributes data is retained.  
Off-line data collection status  
Bits 0 to 6: Indicates the situation of off-line data collection according to the table below.  
Bit 7: If this bit is 1, it indicates that the automatic off-line data collection function is  
enabled.  
Status Byte  
Meaning  
Off-line data collection is not started.  
0
2
3
4
5
6
Off-line data collection has been completed normally.  
Reserved.  
Off-line data collection has been suspended by a command interrupt.  
Off-line data collection has been aborted by a command interrupt.  
Off-line data collection has been aborted by a fatal error.  
5 - 54  
C141-E093-01EN  
·
Self test execution status  
Bits 0 to 3: Indicates the rest of self-test in 0 to 9 (corresponding 0 to 90%).  
Bit 4 to 7: Indicates the self-test execution status at the following table.  
Self-test  
Meaning  
execution status  
0
Self-test has been completed normally or has not been executed.  
Self-test has been stopped by the host computer.  
Self-test has been suspended by hard or soft reset.  
Self-test has been aborted by a fatal error.  
1
2
3
4
Self-test has been completed abnormally by an unknown meaning.  
Self-test has been completed abnormally by write test.  
Self-test has been completed abnormally by serbo test.  
Self-test has been completed abnormally by read test.  
Reserved  
5
6
7
8 to 14  
15  
Self-test is in progress.  
·
Off-line data collection capability  
Indicates the method of off-line data collection carried out by the drive. If the off-line data  
collection capability is 0, it indicates that off-line data collection is not supported.  
Bit  
0
Meaning  
Indicates that Execute Off-Line Immediate is supported.  
Vendor unique  
1
2
Indicates that off-line data collection being executed is aborted when a  
new command is received.  
3
4
Indicates that supports off-line read scan function.  
Indicates that supports self-test function.  
·
Failure prediction capability flag  
Bit 0: The attribute value data is saved to a media before the device enters power saving  
mode.  
Bit 1: The device automatically saves the attribute value data to a media after the  
previously set operation.  
Bits 2 to 15: Reserved bits  
C141-E093-01EN  
5 - 55  
·
Error logging capability  
Bit 0: Indicates that error logging function.  
Bits 1 to 7: Reserved bits  
Check sum  
·
·
Two’s complement of the lower byte, obtained by adding 511-byte data one byte at a time  
from the beginning.  
Insurance failure threshold  
The limit of a varying attribute value. The host compares the attribute values with the  
thresholds to identify a failure.  
If an unrecoverable error is detected during execution of a command received by the device  
from the host computer, the device saves the SMART error log on the disk medium.  
The host computer can issue the SMART Read Log Sector sub-command (FR register = D5h,  
SN register = 01h) and read the SMART error log.  
Table 5.11 SMART error log data format (1/2)  
Byte  
Item  
00  
01  
Error log version number  
The most recent “Error Log” point  
02 to 31  
32  
Error Log Data Reserved  
Structure 1  
Command Data  
Device Control register  
Features register  
Structure  
33  
34  
Sector Count register  
Sector Number register  
Cylinder Low register  
Cylinder High register  
Device/Head register  
Command register  
35  
36  
37  
38  
39  
3A to 3D  
Elapsed time [ms] from the point when the  
power is turned on until command reception  
Error Data  
Structure  
3E  
3F  
40  
41  
42  
43  
44  
Reserved  
Error register  
Sector Count register  
Sector Number register  
Cylinder Low register  
Cylinder High register  
Device/Head register  
5 - 56  
C141-E093-01EN  
Table 5.11 SMART error log data format (2/2)  
Byte  
45  
Item  
Error Log Data  
Structure 1  
Status register  
Vendor Unique  
State  
Error Data  
Structure  
46 to 58  
59  
5A, 5B  
5C to 1C3  
Total power on time [hour]  
Error Log Data This format of each error log data structure is the same as Byte 02  
Structure 2 to  
Error Log Data  
Structure 5  
to 5B.  
1C4, 1C5  
Drive Error Total Number  
1C6 to 1FE Reserved  
1FF  
Checksum  
·
Error log index  
Indicates the latest error log number. If an error has not occurred, 00 is displayed.  
Error log 1 to 5  
·
·
When an error occurs, the error log index value is incremented and information at the time  
the error occurred is recorded in the error log area specified by this value. When the error  
log index exceeds 05, it returns to 01.  
Command data 1 to 5  
Indicates five commands data in order received by the device until the error occurs.  
Commands for which an error occurred are included in Command Data 5.  
·
·
Error data  
Indicates the I/O register values when the error is reported.  
State  
Bits 0 to 3: Indicates the drive status when received error commands according to the  
following table.  
Bits 4 to 7: Vendor unique  
C141-E093-01EN  
5 - 57  
Bit  
Meaning  
0
Unclear status  
Sleep status  
1
2
Standby status  
3
4
Active status or idle status (BSY bit = 0)  
Off-line data collection being executed  
Reserved  
5 to F  
The host computer can issue the SMART Execute Off-line Immediate sub-command (FR  
Register = D4h) and cause the device to execute a self test. When the self test is completed,  
the device saves the SMART self test log to the disk medium.  
The host computer can issue the SMART Read Log Sector sub-command (FR Register = D5h,  
SN Register = 06h) and can read the SMART self test log.  
Table 5.12 SMART self test log data format  
Byte  
00, 01  
02  
Item  
Self test log data format version number  
Self test log 1  
Self test mode (SN Register Value)  
03  
Self test execution status  
04, 05  
Total power on time until the self test is  
completed. [hours]  
06  
Self test error No.  
Error LBA  
07 to 0A  
0B to 19  
1A to 1F9  
Vendor unique  
Self test log 2 to  
21  
(Each log data format is the same as that in  
byte 02 to 19.)  
1FA, 1FB  
1FC  
Vendor unique  
Self test index  
Reserved  
1FD, 1FE  
1FF  
Check sum  
·
Self test log 1 to 21  
When executes self test, the self test index value is incremented and the self test execution  
result is recorded in the self log test area specified by this value. When the self test index  
exceeds 21, it returns to 01.  
5 - 58  
C141-E093-01EN  
·
Self test index  
Indicates the latest self test log number. If the self test has not been executed, 00h is  
displayed.  
(29)  
SET MAX ADDRESS (F9)  
This command allows the maximum address accessible by the user to be set in LBA or CHS mode.  
Upon receipt of the command, the device sets the BSY bit and saves the maximum address  
specified in the DH, CH, CL and SN registers. Then, it clears BSY and generates an interrupt.  
The new address information set by this command is reflected in Words 1, 54, 57, 58, 60 and  
61 of IDENTIFY DEVICE information. If an attempt is made to perform a read or write  
operation for an address beyond the new address space, an ID Not Found error will result.  
When SC register bit 0, VV (Value Volatile), is 1, the value set by this command is held even after  
power on and the occurrence of a hard reset. When the VV bit is 0, the value set by this command  
becomes invalid when the power is turned on or a hard reset occurs, and the maximum address  
returns to the value (default value if not set) most lately set when VV bit = 1.  
After power on and the occurrence of a hard reset, the host can issue this command only once  
when VV bit = 1. If this command with VV bit = 1 is issued twice or more, any command  
following the first time will result in an Aborted Command error.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
1
1
1
1
1
0
0
1
L
DV  
Max head/LBA [MSB]  
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
Max. cylinder [MSB]/Max. LBA  
Max. cylinder [LSB]/Max. LBA  
Max. sector/Max. LBA [LSB]  
1F2H(SC)  
1F1H(FR)  
xx  
xx  
VV  
At command completion (I/O registers contents to be read)  
1F7H(ST) Status information  
DV Max head/LBA [MSB]  
1F6H(DH)  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
Max. cylinder [MSB]/Max. LBA  
Max. cylinder [LSB]/Max. LBA  
Max. sector/Max. LBA [LSB]  
1F2H(SC)  
1F1H(ER)  
xx  
Error information  
C141-E093-01EN  
5 - 59  
(30)  
READ NATIVE MAX ADDRESS (F8)  
This command posts the maximum address intrinsic to the device, which can be set by the  
SET MAX ADDRESS command. Upon receipt of this command, the device sets the BSY bit  
and indicates the maximum address in the DH, CH, CL and SN registers. Then, it clears BSY  
and generates an interrupt.  
At command issuance (I/O registers setting contents)  
1F7H(CM)  
1F6H(DH)  
1
1
1
1
1
0
0
0
L
DV  
xx  
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(FR)  
xx  
xx  
xx  
xx  
xx  
At command completion (I/O registers contents to be read)  
1F7H(ST) Status information  
DV Max head/LBA [MSB]  
1F6H(DH)  
´
´
´
1F5H(CH)  
1F4H(CL)  
1F3H(SN)  
1F2H(SC)  
1F1H(ER)  
Max. cylinder [MSB]/Max. LBA  
Max. cylinder [LSB]/Max. LBA  
Max. sector/Max. LBA [LSB]  
xx  
Error information  
5 - 60  
C141-E093-01EN  
5.3.3  
Error posting  
Table 5.13 lists the defined errors that are valid for each command.  
Table 5.13 Command code and parameters  
Command name  
Error register (X'1F1')  
Status register (X'1F7')  
ICRC UNC  
V
INDF  
V
ABRT  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
*
TR0NF  
DRDY  
V
DWF  
V
ERR  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
READ SECTOR(S)  
WRITE SECTOR(S)  
READ MULTIPLE  
WRITE MULTIPLE  
READ DMA  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
WRITE DMA  
V
V
V
WRITE VERIFY  
V
V
V
V
V
READ VERIFY SECTOR(S)  
RECALIBRATE  
V
V
V
V
V
V
SEEK  
V
V
V
INITIALIZE DEVICE PARAMETERS  
IDENTIFY DEVICE  
IDENTIFY DEVICE DMA  
SET FEATURES  
V
V
V
V
V
V
V
V
SET MULTIPLE MODE  
EXECUTE DEVICE DIAGNOSTIC  
FORMAT TRACK  
READ LONG  
V
V
*
*
*
*
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
WRITE LONG  
READ BUFFER  
WRITE BUFFER  
IDLE  
IDLE IMMEDIATE  
STANDBY  
STANDBY IMMEDIATE  
SLEEP  
CHECK POWER MODE  
SMART  
V
V
V
FLUSH CACHE  
SET MAX ADDRESS  
READ NATIVE MAX ADDRESS  
Invalid command  
V: Valid on this command  
*: See the command descriptions.  
C141-E093-01EN  
5 - 61  
5.4  
Command Protocol  
The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue  
a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is  
cleared to 0.  
Commands can be executed only when the DRDY bit of the Status register is 1. However, the  
following commands can be executed even if DRDY bit is 0.  
·
·
EXECUTE DEVICE DIAGNOSTIC  
INITIALIZE DEVICE PARAMETERS  
5.4.1  
Data transferring commands from device to host  
The execution of the following commands involves data transfer from the device to the host.  
·
·
·
·
·
·
IDENTIFY DEVICE  
IDENTIFY DEVICE DMA  
READ SECTOR(S)  
READ LONG  
READ BUFFER  
SMART: SMART Read Attribute Values, SMART Read Attribute Thresholds  
The execution of these commands includes the transfer one or more sectors of data from the  
device to the host. In the READ LONG command, 516 bytes are transferred. Following  
shows the protocol outline.  
a) The host writes any required parameters to the Features, Sector Count, Sector Number,  
Cylinder, and Device/Head registers.  
b) The host writes a command code to the Command register.  
c) The device sets the BSY bit of the Status register and prepares for data transfer.  
d) When one sector (or block) of data is available for transfer to the host, the device sets  
DRQ bit and clears BSY bit. The drive then asserts INTRQ signal.  
e) After detecting the INTRQ signal assertion, the host reads the Status register. The host  
reads one sector of data via the Data register. In response to the Status register being read,  
the device negates the INTRQ signal.  
f) The drive clears DRQ bit to 0. If transfer of another sector is requested, the device sets the  
BSY bit and steps d) and after are repeated.  
Even if an error is encountered, the device prepares for data transfer by setting the DRQ bit.  
Whether or not to transfer the data is determined for each host. In other words, the host  
should receive the relevant sector of data (512 bytes of uninsured dummy data) or release the  
DRQ status by resetting.  
Figure 5.2 shows an example of READ SECTOR(S) command protocol, and Figure 5.3  
shows an example protocol for command abort.  
5 - 62  
C141-E093-01EN  
Command  
b c  
Parameter write  
Status read  
e
Status read  
~
• • • •  
• • • •  
a
e
BSY  
d
f
d
DRDY  
DRQ  
INTRQ  
Data transfer  
Expanded  
Command  
Min. 30 ms (*1)  
• • •  
DRQ  
INTRQ  
Data Reg.  
Selection  
• • • •  
• • • •  
Data  
IOR-  
• • • •  
Word  
0
1
2
255  
IOCS16-  
*1 When the IDD receives a command that hits the cache data during read-ahead, and  
transfers data from the buffer without reading from the disk medium.  
Figure 5.2 Read Sector(s) command protocol  
Even if the error status exists, the drive makes a preparation (setting the DRQ bit) of data  
transfer. It is up to the host whether data is transferred. In other words, the host should  
receive the data of the sector (512 bytes of uninsured dummy data) or release the DRQ by  
resetting.  
C141-E093-01EN  
5 - 63  
Note:  
For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to  
clear INTRQ (interrupt) signal. The Status register should be read within a period from the  
DRQ setting by the device to 5 ms after the completion of the sector data transfer. Note  
that the host does not need to read the Status register for the reading of a single sector or  
the last sector in multiple-sector reading. If the timing to read the Status register does not  
meet above condition, normal data transfer operation is not guaranteed.  
When the host new command even if the device requests the data transfer (setting in DRQ  
bit), the correct device operation is not guaranteed.  
Command  
Status read  
Parameter write  
~
BSY  
DRDY  
DRQ  
INTRQ  
Data transfer  
* Transfers dummy data  
* The host should receive 512-byte dummy data or release the DRQ set state by resetting.  
Figure 5.3 Protocol for command abort  
5.4.2  
Data transferring commands from host to device  
The execution of the following commands involves Data transfer from the host to the drive.  
·
·
·
·
·
FORMAT TRACK  
WRITE SECTOR(S)  
WRITE LONG  
WRITE BUFFER  
WRITE VERIFY  
The execution of these commands includes the transfer one or more sectors of data from the  
host to the device. In the WRITE LONG command, 516 bytes are transferred. Following  
shows the protocol outline.  
a) The host writes any required parameters to the Features, Sector Count, Sector Number,  
Cylinder, and Device/Head registers.  
b) The host writes a command code in the Command register. The drive sets the BSY bit of  
the Status register.  
5 - 64  
C141-E093-01EN  
c) When the device is ready to receive the data of the first sector, the device sets DRQ bit and  
clears BSY bit.  
d) The host writes one sector of data through the Data register.  
e) The device clears the DRQ bit and sets the BSY bit.  
f) When the drive completes transferring the data of the sector, the device clears BSY bit and  
asserts INTRQ signal. If transfer of another sector is requested, the drive sets the DRQ bit.  
g) After detecting the INTRQ signal assertion, the host reads the Status register.  
h) The device resets INTRQ (the interrupt signal).  
I) If transfer of another sector is requested, steps d) and after are repeated.  
Figure 5.4 shows an example of WRITE SECTOR(S) command protocol, and Figure 5.3  
shows an example protocol for command abort.  
Command  
Parameter write  
Status read  
g
Status read  
g
~
b
• • • •  
• • • •  
a
f
BSY  
DRDY  
DRQ  
c
e
h
INTRQ  
Data transfer  
d
d
Expanded  
Command  
DRQ  
Max. 1 ms  
• • •  
Data Reg. Selection  
Data  
• • • •  
• • • •  
IOR-  
• • • •  
Word  
0
1
2
255  
IOCS16  
Figure 5.4 WRITE SECTOR(S) command protocol  
C141-E093-01EN  
5 - 65  
Note:  
For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to  
clear INTRQ (interrupt) signal. The Status register should be read within a period from the  
DRQ setting by the device to 5 ms after the completion of the sector data transfer. Note  
that the host does not need to read the Status register for the first and the last sector to be  
transferred. If the timing to read the Status register does not meet above condition, normal  
data transfer operation is not assured guaranteed.  
When the host issues the command even if the drive requests the data transfer (DRQ bit is  
set), or when the host executes resetting, the device correct operation is not guaranteed.  
5.4.3  
Commands without data transfer  
Execution of the following commands does not involve data transfer between the host and the  
device.  
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
RECALIBRATE  
SEEK  
READY VERIFY SECTOR(S)  
EXECUTE DEVICE DIAGNOSTIC  
INITIALIZE DEVICE PARAMETERS  
SET FEATURES  
SET MULTIPLE MODE  
IDLE  
IDLE IMMEDIATE  
STANDBY  
STANDBY IMMEDIATE  
CHECK POWER MODE  
FLUSH CACHE  
SECURITY ERASE PREPARE  
SECURITY FREEZE LOCK  
SMART: except for SMART Read Attribute values and SMART Read Attribute  
Thresholds  
·
·
SET MAX ADDRESS  
READ NATIVE MAX ADDRESS  
Figure 5.5 shows the protocol for the command execution without data transfer.  
Command  
Parameter write  
Status read  
~
BSY  
DRDY  
INTRQ  
Figure 5.5 Protocol for the command execution without data transfer  
5 - 66  
C141-E093-01EN  
5.4.4  
Other commands  
·
·
·
READ MULTIPLE  
SLEEP  
WRITE MULTIPLE  
See the description of each command.  
5.4.5  
DMA data transfer commands  
·
·
READ DMA  
WRITE DMA  
Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE  
SECTOR(S) command except the point that the host initializes the DMA channel preceding  
the command issuance.  
The interrupt processing for the DMA transfer differs the following point.  
·
The interrupt processing for the DMA transfer differs the following point.  
a) The host writes any parameters to the Features, Sector Count, Sector Number,  
Cylinder, and Device/Head register.  
b) The host initializes the DMA channel  
c) The host writes a command code in the Command register.  
d) The device sets the BSY bit of the Status register.  
e) The device asserts the DMARQ signal after completing the preparation of data  
transfer. The device asserts either the BSY bit during DMA data transfer.  
f) When the command execution is completed, the device clears both BSY and DRQ  
bits and asserts the INTRQ signal.  
g) The host reads the Status register.  
h) The host resets the DMA channel.  
C141-E093-01EN  
5 - 67  
Command  
c, d  
Status read  
Parameter write  
~
a
BSY  
• •  
DRDY  
INTRQ  
f
g
e
• •  
DRQ  
• •  
Data transfer  
Expanded  
[Multiword DMA transfer]  
DRQ  
• • • •  
• • • •  
DMARQ  
DMACK-  
• • • •  
• • • •  
IOR- or  
IOW-  
Word  
0
1
n-1  
n
Figure 5.6 Normal DMA data transfer  
5 - 68  
C141-E093-01EN  
5.5  
Ultra DMA feature set  
Overview  
5.5.1  
Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA  
commands. When this protocol is enabled it shall be used instead of the Multiword DMA  
protocol when these commands are issued by the host. This protocol applies to the Ultra  
DMA data burst only. When this protocol is used there are no changes to other elements of  
the ATA protocol (e.g.: Command Block Register access).  
Several signal lines are redefined to provide new functions during an Ultra DMA burst. These  
lines assume these definitions when 1) an Ultra DMA Mode is selected, and 2) a host issues a  
READ DMA or a WRITE DMA, command requiring data transfer, and 3) the host asserts  
DMACK-. These signal lines revert back to the definitions used for non-Ultra DMA transfers  
upon the negation of DMACK- by the host at the termination of an Ultra DMA burst. All of  
the control signals are unidirectional. DMARQ and DMACK- retain their standard  
definitions.  
With the Ultra DMA protocol, the control signal (STROBE) that latches data from DD (15:0)  
is generated by the same agent (either host or device) that drives the data onto the bus.  
Ownership of DD (15:0) and this data strobe signal are given either to the device during an  
Ultra DMA data in burst or to the host for an Ultra DMA data out burst.  
During an Ultra DMA burst a sender shall always drive data onto the bus, and after a sufficient  
time to allow for propagation delay, cable settling, and setup time, the sender shall generate a  
STROBE edge to latch the data. Both edges of STROBE are used for data transfers so that the  
frequency of STROBE is limited to the same frequency as the data. The highest fundamental  
frequency on the cable shall be 16.67 million transitions per second or 8.33 MHz (the same as  
the maximum frequency for PIO Mode 4 and DMA Mode 2).  
Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the  
Ultra DMA Modes the device is capable of supporting. The Set transfer mode subcommand  
in the SET FEATURES command shall be used by a host to select the Ultra DMA Mode at  
which the system operates. The Ultra DMA Mode selected by a host shall be less than or  
equal to the fastest mode of which the device is capable. Only the Ultra DMA Mode shall be  
selected at any given time. All timing requirements for a selected Ultra DMA Mode shall be  
satisfied. Devices supporting Ultra DMA Mode 2 shall also support Ultra DMA Modes 0 and  
1. Devices supporting Ultra DMA Mode 1 shall also support Ultra DMA Mode 0.  
An Ultra DMA capable device shall retain its previously selected Ultra DMA Mode after  
executing a Software reset sequence. An Ultra DMA capable device shall clear any previously  
selected Ultra DMA Mode and revert to its default non-Ultra DMA Modes after executing a  
Power on or hardware reset.  
Both the host and device perform a CRC function during an Ultra DMA burst. At the end of  
an Ultra DMA burst the host sends the its CRC data to the device. The device compares its  
CRC data to the data sent from the host. If the two values do not match the device reports an  
error in the error register at the end of the command. If an error occurs during one or more  
Ultra DMA bursts for any one command, at the end of the command, the device shall report  
the first error that occurred.  
C141-E093-01EN  
5 - 69  
5.5.2  
Phases of operation  
An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out  
bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase,  
the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra  
DMA burst may be paused during the data transfer phase (see 5.5.3 and 5.5.4 for the detailed  
protocol descriptions for each of these phases, 5.6 defines the specific timing requirements).  
In the following rules DMARDY- is used in cases that could apply to either DDMARDY- or  
HDMARDY-, and STROBE is used in cases that could apply to either DSTROBE or  
HSTROBE. The following are general Ultra DMA rules.  
a) An Ultra DMA burst is defined as the period from an assertion of DMACK- by the host to  
the subsequent negation of DMACK-.  
b) A recipient shall be prepared to receive at least two data words whenever it enters or  
resumes an Ultra DMA burst.  
5.5.3  
Ultra DMA data in commands  
5.5.3.1 Initiating an Ultra DMA data in burst  
The following steps shall occur in the order they are listed unless otherwise specifically  
allowed (see 5.6.3.1 and 5.6.3.2 for specific timing requirements):  
1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.  
2) The device shall assert DMARQ to initiate an Ultra DMA burst. After assertion of  
DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE.  
3) Steps (3), (4) and (5) may occur in any order or at the same time. The host shall assert  
STOP.  
4) The host shall negate HDMARDY-.  
5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-,  
DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst.  
6) Steps (3), (4) and (5) shall have occurred at least tACK before the host asserts DMACK-.  
The host shall keep DMACK- asserted until the end of an Ultra DMA burst.  
7) The host shall release DD (15:0) within tAZ after asserting DMACK-.  
8) The device may assert DSTROBE tZIORDY after the host has asserted DMACK-. Once the  
device has driven DSTROBE the device shall not release DSTROBE until after the host  
has negated DMACK- at the end of an Ultra DMA burst.  
9) The host shall negate STOP and assert HDMARDY- within tENV after asserting DMACK-.  
After negating STOP and asserting HDMARDY-, the host shall not change the state of  
either signal until after receiving the first transition of DSTROBE from the device (i.e.,  
after the first data word has been received).  
10) The device shall drive DD (15:0) no sooner than tZAD after the host has asserted DMACK-,  
negated STOP, and asserted HDMARDY-.  
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C141-E093-01EN  
11) The device shall drive the first word of the data transfer onto DD (15:0). This step may  
occur when the device first drives DD (15:0) in step (10).  
12) To transfer the first word of data the device shall negate DSTROBE within tFS after the  
host has negated STOP and asserted HDMARDY-. The device shall negate DSTROBE no  
sooner than tDVS after driving the first word of data onto DD (15:0).  
5.5.3.2 The data in transfer  
The following steps shall occur in the order they are listed unless otherwise specifically  
allowed (see 5.6.3.3 and 5.6.3.2 for specific timing requirements):  
1) The device shall drive a data word onto DD (15:0).  
2) The device shall generate a DSTROBE edge to latch the new word no sooner than tDVS  
after changing the state of DD (15:0). The device shall generate a DSTROBE edge no  
more frequently than tCYC for the selected Ultra DMA Mode. The device shall not  
generate two rising or two falling DSTROBE edges more frequently than 2tCYC for the  
selected Ultra DMA mode.  
3) The device shall not change the state of DD (15:0) until at least tDVH after generating a  
DSTROBE edge to latch the data.  
4) The device shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra  
DMA burst is paused, whichever occurs first.  
5.5.3.3 Pausing an Ultra DMA data in burst  
The following steps shall occur in the order they are listed unless otherwise specifically  
allowed (see 5.6.3.4 and 5.6.3.2 for specific timing requirements).  
a) Device pausing an Ultra DMA data in burst  
1) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra  
DMA burst has been transferred.  
2) The device shall pause an Ultra DMA burst by not generating DSTROBE edges.  
NOTE - The host shall not immediately assert STOP to initiate Ultra DMA burst  
termination when the device stops generating STROBE edges. If the device does not  
negate DMARQ, in order to initiate ULTRA DMA burst termination, the host shall  
negate HDMARDY- and wait tRP before asserting STOP.  
3) The device shall resume an Ultra DMA burst by generating a DSTROBE edge.  
b) Host pausing an Ultra DMA data in burst  
1) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra  
DMA burst has been transferred.  
2) The host shall pause an Ultra DMA burst by negating HDMARDY-.  
C141-E093-01EN  
5 - 71  
3) The device shall stop generating DSTROBE edges within tRFS of the host negating  
HDMARDY-.  
4) If the host negates HDMARDY- within tSR after the device has generated a  
DSTROBE edge, then the host shall be prepared to receive zero or one additional data  
words. If the host negates HDMARDY- greater than tSR after the device has  
generated a DSTROBE edge, then the host shall be prepared to receive zero, one or  
two additional data words. The additional data words are a result of cable round trip  
delay and tRFS timing for the device.  
5) The host shall resume an Ultra DMA burst by asserting HDMARDY-.  
5.5.3.4 Terminating an Ultra DMA data in burst  
a) Device terminating an Ultra DMA data in burst  
The following steps shall occur in the order they are listed unless otherwise specifically  
allowed (see 5.6.3.5 and 5.6.3.2 for specific timing requirements):  
1) The device shall initiate termination of an Ultra DMA burst by not generating  
DSTROBE edges.  
2) The device shall negate DMARQ no sooner than tSS after generating the last  
DSTROBE edge. The device shall not assert DMARQ again until after the Ultra  
DMA burst is terminated.  
3) The device shall release DD (15:0) no later than tAZ after negating DMARQ.  
4) The host shall assert STOP within tLI after the device has negated DMARQ. The host  
shall not negate STOP again until after the Ultra DMA burst is terminated.  
5) The host shall negate HDMARDY- within tLI after the device has negated DMARQ.  
The host shall continue to negate HDMARDY- until the Ultra DMA burst is  
terminated. Steps (4) and (5) may occur at the same time.  
6) The host shall drive DD (15:0) no sooner than tZAH after the device has negated  
DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC  
calculation (see 5.5.5):  
7) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host  
has asserted STOP. No data shall be transferred during this assertion. The host shall  
ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra  
DMA burst is terminated.  
8) If the host has not placed the result of its CRC calculation on DD (15:0) since first  
driving DD (15:0) during (6), the host shall place the result of its CRC calculation on  
DD (15:0) (see 5.5.5).  
9) The host shall negate DMACK- no sooner than tMLI after the device has asserted  
DSTROBE and negated DMARQ and the host has asserted STOP and negated  
HDMARDY-, and no sooner than tDVS after the host places the result of its CRC  
calculation on DD (15:0).  
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C141-E093-01EN  
10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of  
DMACK-.  
11) The device shall compare the CRC data received from the host with the results of its  
own CRC calculation. If a miscompare error occurs during one or more Ultra DMA  
bursts for any one command, at the end of the command the device shall report the  
first error that occurred (see 5.5.5).  
12) The device shall release DSTROBE within tIORDYZ after the host negates DMACK-.  
13) The host shall not negate STOP no assert HDMARDY- until at least tACK after  
negating DMACK-.  
14) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK  
after negating DMACK.  
b) Host terminating an Ultra DMA data in burst  
The following steps shall occur in the order they are listed unless otherwise specifically  
allowed (see 5.6.3.6 and 5.6.3.2 for specific timing requirements):  
1) The host shall not initiate Ultra DMA burst termination until at least one data word of  
an Ultra DMA burst has been transferred.  
2) The host shall initiate Ultra DMA burst termination by negating HDMARDY-. The  
host shall continue to negate HDMARDY- until the Ultra DMA burst is terminated.  
3) The device shall stop generating DSTROBE edges within tRFS of the host negating  
HDMARDY-.  
4) If the host negates HDMARDY- within tSR after the device has generated a  
DSTROBE edge, then the host shall be prepared to receive zero or one additional data  
words. If the host negates HDMARDY- greater than tSR after the device has  
generated a DSTROBE edge, then the host shall be prepared to receive zero, one or  
two additional data words. The additional data words are a result of cable round trip  
delay and tRFS timing for the device.  
5) The host shall assert STOP no sooner than tRP after negating HDMARDY-. The host  
shall not negate STOP again until after the Ultra DMA burst is terminated.  
6) The device shall negate DMARQ within tLI after the host has asserted STOP. The  
device shall not assert DMARQ again until after the Ultra DMA burst is terminated.  
7) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host  
has asserted STOP. No data shall be transferred during this assertion. The host shall  
ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra  
DMA burst is terminated.  
8) The device shall release DD (15:0) no later than tAZ after negating DMARQ.  
9) The host shall drive DD (15:0) no sooner than tZAH after the device has negated  
DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC  
calculation (see 5.5.5).  
C141-E093-01EN  
5 - 73  
10) If the host has not placed the result of its CRC calculation on DD (15:0) since first  
driving DD (15:0) during (9), the host shall place the result of its CRC calculation on  
DD (15:0) (see 5.5.5).  
11) The host shall negate DMACK- no sooner than tMLI after the device has asserted  
DSTROBE and negated DMARQ and the host has asserted STOP and negated  
HDMARDY-, and no sooner than tDVS after the host places the result of its CRC  
calculation on DD (15:0).  
12) The device shall latch the host's CRC data from DD (15:0) on the negating edge of  
DMACK-.  
13) The device shall compare the CRC data received from the host with the results of its  
own CRC calculation. If a miscompare error occurs during one or more Ultra DMA  
burst for any one command, at the end of the command, the device shall report the  
first error that occurred (see 5.5.5).  
14) The device shall release DSTROBE within tIORDYZ after the host negates DMACK-.  
15) The host shall neither negate STOP nor assert HDMARDY- until at least tACK after the  
host has negated DMACK-.  
16) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK  
after negating DMACK.  
5.5.4  
Ultra DMA data out commands  
5.5.4.1 Initiating an Ultra DMA data out burst  
The following steps shall occur in the order they are listed unless otherwise specifically  
allowed (see 5.6.3.7 and 5.6.3.2 for specific timing requirements):  
1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.  
2) The device shall assert DMARQ to initiate an Ultra DMA burst.  
3) Steps (3), (4), and (5) may occur in any order or at the same time. The host shall assert  
STOP.  
4) The host shall assert HSTROBE.  
5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep CS0-, CS1-,  
DA2, DA1, and DA0 negated until after negating DMACK- at the end of the burst.  
6) Steps (3), (4), and (5) shall have occurred at least tACK before the host asserts DMACK-.  
The host shall keep DMACK- asserted until the end of an Ultra DMA burst.  
7) The device may negate DDMARDY- tZIORDY after the host has asserted DMACK-. Once  
the device has negated DDMARDY-, the device shall not release DDMARDY- until after  
the host has negated DMACK- at the end of an Ultra DMA burst.  
8) The host shall negate STOP within tENV after asserting DMACK-. The host shall not assert  
STOP until after the first negation of HSTROBE.  
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C141-E093-01EN  
9) The device shall assert DDMARDY- within tLI after the host has negated STOP. After  
asserting DMARQ and DDMARDY- the device shall not negate either signal until after  
the first negation of HSTROBE by the host.  
10) The host shall drive the first word of the data transfer onto DD (15:0). This step may  
occur any time during Ultra DMA burst initiation.  
11) To transfer the first word of data: the host shall negate HSTROBE no sooner than tLI after  
the device has asserted DDMARDY-. The host shall negate HSTROBE no sooner than  
tDVS after the driving the first word of data onto DD (15:0).  
5.5.4.2 The data out transfer  
The following steps shall occur in the order they are listed unless otherwise specifically  
allowed (see 5.6.3.8 and 5.6.3.2 for specific timing requirements):  
1) The host shall drive a data word onto DD (15:0).  
2) The host shall generate an HSTROBE edge to latch the new word no sooner than tDVS after  
changing the state of DD (15:0). The host shall generate an HSTROBE edge no more  
frequently than tCYC for the selected Ultra DMA Mode. The host shall not generate two  
rising or falling HSTROBE edges more frequently than 2 tCYC for the selected Ultra DMA  
mode.  
3) The host shall not change the state of DD (15:0) until at least tDVH after generating an  
HSTROBE edge to latch the data.  
4) The host shall repeat steps (1), (2) and (3) until the data transfer is complete or an Ultra  
DMA burst is paused, whichever occurs first.  
5.5.4.3 Pausing an Ultra DMA data out burst  
The following steps shall occur in the order they are listed unless otherwise specifically  
allowed (see 5.6.3.9 and 5.6.3.2 for specific timing requirements).  
a) Host pausing an Ultra DMA data out burst  
1) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra  
DMA burst has been transferred.  
2) The host shall pause an Ultra DMA burst by not generating an HSTROBE edge.  
Note: The device shall not immediately negate DMARQ to initiate Ultra DMA burst  
termination when the host stops generating HSTROBE edges. If the host does not  
assert STOP, in order to initiate Ultra DMA burst termination, the device shall negate  
DDMARDY- and wait tRP before negating DMARQ.  
3) The host shall resume an Ultra DMA burst by generating an HSTROBE edge.  
C141-E093-01EN  
5 - 75  
b) Device pausing an Ultra DMA data out burst  
1) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra  
DMA burst has been transferred.  
2) The device shall pause an Ultra DMA burst by negating DDMARDY-.  
3) The host shall stop generating HSTROBE edges within tRFS of the device negating  
DDMARDY-.  
4) If the device negates DDMARDY- within tSR after the host has generated an  
HSTROBE edge, then the device shall be prepared to receive zero or one additional  
data words. If the device negates DDMARDY- greater than tSR after the host has  
generated an HSTROBE edge, then the device shall be prepared to receive zero, one  
or two additional data words. The additional data words are a result of cable round  
trip delay and tRFS timing for the host.  
5) The device shall resume an Ultra DMA burst by asserting DDMARDY-.  
5.5.4.4 Terminating an Ultra DMA data out burst  
a) Host terminating an Ultra DMA data out burst  
The following stops shall occur in the order they are listed unless otherwise specifically  
allowed (see 5.6.3.10 and 5.6.3.2 for specific timing requirements):  
1) The host shall initiate termination of an Ultra DMA burst by not generating  
HSTROBE edges.  
2) The host shall assert STOP no sooner than tSS after it last generated an HSTROBE  
edge. The host shall not negate STOP again until after the Ultra DMA burst is  
terminated.  
3) The device shall negate DMARQ within tLI after the host asserts STOP. The device  
shall not assert DMARQ again until after the Ultra DMA burst is terminated.  
4) The device shall negate DDMARDY- with tLI after the host has negated STOP. The  
device shall not assert DDMARDY- again until after the Ultra DMA burst termination  
is complete.  
5) If HSTROBE is negated, the host shall assert HSTROBE with tLI after the device has  
negated DMARQ. No data shall be transferred during this assertion. The device shall  
ignore this transition on HSTROBE. HSTROBE shall remain asserted until the Ultra  
DMA burst is terminated.  
6) The host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5)  
7) The host shall negate DMACK- no sooner than tMLI after the host has asserted  
HSTROBE and STOP and the device has negated DMARQ and DDMARDY-, and no  
sooner than tDVS after placing the result of its CRC calculation on DD (15:0).  
8) The device shall latch the host's CRC data from DD (15:0) on the negating edge of  
DMACK-.  
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C141-E093-01EN  
9) The device shall compare the CRC data received from the host with the results of its  
own CRC calculation. If a miscompare error occurs during one or more Ultra DMA  
bursts for any one command, at the end of the command, the device shall report the  
first error that occurred (see 5.5.5).  
10) The device shall release DDMARDY- within tIORDYZ after the host has negated  
DMACK-.  
11) The host shall neither negate STOP nor negate HSTROBE until at least tACK after  
negating DMACK-.  
12) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK  
after negating DMACK.  
b) Device terminating an Ultra DMA data out burst  
The following steps shall occur in the order they are listed unless otherwise specifically  
allowed (see 5.6.3.11 and 5.6.3.2 for specific timing requirements):  
1) The device shall not initiate Ultra DMA burst termination until at least one data word  
of an Ultra DMA burst has been transferred.  
2) The device shall initiate Ultra DMA burst termination by negating DDMARDY-.  
3) The host shall stop generating an HSTROBE edges within tRFS of the device negating  
DDMARDY-.  
4) If the device negates DDMARDY- within tSR after the host has generated an  
HSTROBE edge, then the device shall be prepared to receive zero or one additional  
data words. If the device negates DDMARDY- greater than tSR after the host has  
generated an HSTROBE edge, then the device shall be prepared to receive zero, one  
or two additional data words. The additional data words are a result of cable round  
trip delay and tRFS timing for the host.  
5) The device shall negate DMARQ no sooner than tRP after negating DDMARDY-.  
The device shall not assert DMARQ again until after the Ultra DMA burst is  
terminated.  
6) The host shall assert STOP with tLI after the device has negated DMARQ. The host  
shall not negate STOP again until after the Ultra DMA burst is terminated.  
7) If HSTROBE is negated, the host shall assert HSTROBE with tLI after the device has  
negated DMARQ. No data shall be transferred during this assertion. The device shall  
ignore this transition of HSTROBE. HSTROBE shall remain asserted until the Ultra  
DMA burst is terminated.  
8) The host shall place the result of its CRC calculation on DD (15:0) (see 5.5.5).  
9) The host shall negate DMACK- no sooner than tMLI after the host has asserted  
HSTROBE and STOP and the device has negated DMARQ and DDMARDY-, and no  
sooner than tDVS after placing the result of its CRC calculation on DD (15:0).  
10) The device shall latch the host's CRC data from DD (15:0) on the negating edge of  
DMACK-.  
C141-E093-01EN  
5 - 77  
11) The device shall compare the CRC data received from the host with the results of its  
own CRC calculation. If a miscompare error occurs during one or more Ultra DMA  
bursts for any one command, at the end of the command, the device shall report the  
first error that occurred (see 5.5.5).  
12) The device shall release DDMARDY- within tIORDYZ after the host has negated DMACK-.  
13) The host shall neither negate STOP nor HSTROBE until at least tACK after negating  
DMACK-.  
14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least tACK  
after negating DMACK.  
5.5.5  
Ultra DMA CRC rules  
The following is a list of rules for calculating CRC, determining if a CRC error has occurred  
during an Ultra DMA burst, and reporting any error that occurs at the end of a command.  
a) Both the host and the device shall have a 16-bit CRC calculation function.  
b) Both the host and the device shall calculate a CRC value for each Ultra DMA burst.  
c) The CRC function in the host and the device shall be initialized with a seed of 4ABAh at  
the beginning of an Ultra DMA burst before any data is transferred.  
d) For each STROBE transition used for data transfer, both the host and the device shall  
calculate a new CRC value by applying the CRC polynomial to the current value of their  
individual CRC functions and the word being transferred. CRC is not calculated for the  
return of STROBE to the asserted state after the Ultra DMA burst termination request has  
been acknowledged.  
e) At the end of any Ultra DMA burst the host shall send the results of its CRC calculation  
function to the device on DD (15:0) with the negation of DMACK-.  
f) The device shall then compare the CRC data from the host with the calculated value in its  
own CRC calculation function. If the two values do not match, the device shall save the  
error and report it at the end of the command. A subsequent Ultra DMA burst for the same  
command that does not have a CRC error shall not clear an error saved from a previous  
Ultra DMa burst in the same command. If a miscompare error occurs during one or more  
Ultra DMA bursts for any one command, at the end of the command, the device shall  
report the first error that occurred.  
g) For READ DMA or WRITE DMA commands: When a CRC error is detected, it shall be  
reported by setting both ICRC and ABRT (bit 7 and bit 2 in the Error register) to one.  
ICRC is defined as the "Interface CRC Error" bit. The host shall respond to this error by  
re-issuing the command.  
h) A host may send extra data words on the last Ultra DMA burst of a data out command. If  
a device determines that all data has been transferred for a command, the device shall  
terminate the burst. A device may have already received more data words than were  
required for the command. These extra words are used by both the host and the device to  
calculate the CRC, but, on an Ultra DMA data out burst, the extra words shall be discarded  
by the device.  
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C141-E093-01EN  
I) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1.  
Note: Since no bit clock is available, the recommended approach for calculating CRC is  
to use a word clock derived from the bus strobe. The combinational logic shall then be  
equivalent to shifting sixteen bits serially through the generator polynominal where DD0 is  
shifted in first and DD15 is shifted in last.  
5.5.6  
Series termination required for Ultra DMA  
Series termination resistors are required at both the host and the device for operation in any of  
the Ultra DMA Modes. The following table describes recommended values for series  
termination at the host and the device.  
Table 5.14 Recommended series termination for Ultra DMA  
Signal  
DIOR-:HDMARDY-:HSTROBE  
DIOW-:STOP  
Host Termination  
33 ohm  
Device Termination  
120 ohm A.I.*1  
82 ohm  
33 ohm  
CS0-, CS1-  
33 ohm  
82 ohm  
DA0, DA1, DA2  
DMACK-  
33 ohm  
82 ohm  
33 ohm  
82 ohm  
DD15 through DD0  
DMARQ  
33 ohm  
240 ohm A.I.*1  
22 ohm  
82 ohm  
INTRQ  
82 ohm  
22 ohm  
IORDY:DDMARDY-:DSTROBE  
82 ohm  
22 ohm  
Note: Only those signals requiring termination are listed in this table. If a  
signal is not listed, series termination is not required for operation in an Ultra  
DMA Mode. For signals also requiring a pull-up or pull-down resistor at the  
host see Figure 5.7.  
Note (*1): “A.I.” means an Active Inductance.  
Figure 5.7 Ultra DMA termination with pull-up or pull-down  
C141-E093-01EN  
5 - 79  
5.6  
Timing  
5.6.1  
PIO data transfer  
Figure 5.8 shows of the data transfer timing between the device and the host system.  
t0  
Addresses  
t1  
t9  
t2  
DIOR-/DIOW-  
t2i  
Write data  
DD0-DD15  
t3  
t4  
Read data  
DD0-DD15  
t5  
t6  
t10  
t11  
IORDY  
Symbol  
t12  
Timing parameter  
Min.  
120  
25  
70  
25  
20  
10  
—
5
Max.  
—
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t0  
t1  
Cycle time  
Data register selection setup time for DIOR-/DIOW-  
Pulse width of DIOR-/DIOW-  
—
t2  
—
t2i  
t3  
Recovery time of DIOR-/DIOW-  
—
Data setup time for DIOW-  
—
t4  
Data hold time for DIOW-  
—
t5  
Time from DIOR- assertion to read data available  
Data hold time for DIOR-  
50  
t6  
—
t9  
Data register selection hold time for DIOR-/DIOW-  
10  
—
0
—
t10  
t11  
t12  
Time from DIOR-/DIOW- assertion to IORDY "low" level  
Time from validity of read data to IORDY "high" level  
Pulse width of IORDY  
35  
—
—
1,250  
Figure 5.8 PIO data transfer timing  
5 - 80  
C141-E093-01EN  
5.6.2  
Multiword data transfer  
Figure 5.9 shows the multiword DMA data transfer timing between the device and the host  
system.  
t0  
DMARQ  
DMACK-  
tJ  
tC  
tI  
tK  
tD  
DIOR-/DIOW-  
Write data  
DD0-DD15  
tG  
tH  
Read data  
DD0-DD15  
tE  
tF  
Symbol  
Timing parameter  
Min.  
120  
—
70  
—
5
Max.  
—
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t0  
tC  
tD  
tE  
tF  
tG  
tH  
tI  
Cycle time  
Delay time from DMACK assertion to DMARQ negation  
Pulse width of DIOR-/DIOW-  
35  
—
Data setup time for DIOR-  
30  
—
Data hold time for DIOR-  
Data setup time for DIOW-  
20  
10  
0
—
Data hold time for DIOW-  
—
DMACK setup time for DIOR-/DIOW-  
DMACK hold time for DIOR-/DIOW-  
Continuous time of high level for DIOR-/DIOW-  
—
tJ  
5
—
tK  
25  
—
Figure 5.9 Multiword DMA data transfer timing (mode 2)  
C141-E093-01EN  
5 - 81  
5.6.3  
Ultra DMA data transfer  
Figures 5.10 through 5.19 define the timings associated with all phases of Ultra DMA bursts.  
Table 5.15 contains the values for the timings for each of the Ultra DMA Modes.  
5.6.3.1 Initiating an Ultra DMA data in burst  
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.  
Note:  
The definitions for the STOP, HDMARDY-and DSTROBE signal lines are not in effect  
until DMARQ and DMACK are asserted.  
Figure 5.10 Initiating an Ultra DMA data in burst  
5 - 82  
C141-E093-01EN  
5.6.3.2 Ultra DMA data burst timing requirements  
Table 5.15 Ultra DMA data burst timing requirements (1 of 2)  
NAME  
MODE 0  
(in ns)  
MODE 1  
(in ns)  
MODE 2  
(in ns)  
MODE 3  
(in ns)  
MODE 4  
(in ns)  
COMMENT  
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX (see Notes 1 and 2)  
t2CYCTYP  
tCYC  
240  
160  
120  
90  
60  
Typical sustained average two cycle  
time  
112  
73  
54  
39  
25  
Cycle time allowing for asymmetry  
and clock variations (from STROBE  
edge to STROBE edge)  
t2CYC  
230  
154  
115  
86  
57  
Two cycle time allowing for clock  
variations (from rising edge to next  
rising edge or from falling edge to  
next falling edge of STROBE)  
tDS  
15  
5
10  
5
7
5
7
5
5
5
6
Data setup time (at recipient)  
(see Note 4)  
tDH  
tDVS  
Data hold time (at recipient)  
(see Note 4)  
70  
48  
30  
20  
Data valid setup time at sender (from  
data valid until STROBE edge)  
(see Note 5)  
tDVH  
6
0
6
0
6
0
6
0
6
0
Data valid hold time at sender (from  
STROBE edge until data may  
become invalid) (see Note 5)  
tFS  
230  
150  
200  
150  
170  
150  
130  
100  
120 First STROBE time (for device to  
first negate DSTROBE from STOP  
during a data in burst)  
tLI  
0
0
0
0
0
100 Limited interlock time (see Note 3)  
tMLI  
20  
20  
20  
20  
20  
Interlock time with minimum  
(see Note 3)  
tUI  
0
0
0
0
0
Unlimited interlock time (see Note 3)  
tAZ  
10  
10  
10  
10  
10  
Maximum time allowed for output  
drivers to release (from asserted or  
negated)  
tZAH  
tZAD  
tENV  
20  
0
20  
0
20  
0
20  
0
20  
0
Minimum delay time required for  
output  
Drivers to assert or negate (from  
released)  
20  
70  
50  
75  
20  
70  
30  
70  
20  
70  
20  
60  
20  
55  
NA  
60  
20  
55  
Envelope time (from DMACK- to  
STOP and HDMARDY- during data  
in burst initiation and from DMACK  
to STOP during data out burst  
initiation)  
tSR  
NA STROBE-to-DMARDY-time (if  
DMARDY- is negated before this long  
after STROBE edge, the recipient shall  
receive no more than one additional  
data word)  
tRFS  
60  
Ready-to-final-STROBE time (no  
STROBE edges shall be sent this  
long after negation of DMARDY-)  
tRP  
160  
125  
100  
100  
100  
Ready-to-pause time (that recipient  
shall wait to pause after negating  
DMARDY-)  
tIORDYZ  
20  
20  
20  
20  
20  
Maximum time before releasing  
IORDY  
C141-E093-01EN  
5 - 83  
Table 5.15 Ultra DMA data burst timing requirements (2 of 2)  
NAME  
MODE 0  
(in ns)  
MODE 1  
(in ns)  
MODE 2  
(in ns)  
MODE 3  
(in ns)  
MODE 4  
(in ns)  
COMMENT  
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX (see Notes 1 and 2)  
tZIORDY  
tACK  
tSS  
0
0
0
0
0
Minimum time before driving  
IORDY  
20  
50  
20  
50  
20  
50  
20  
50  
20  
50  
Setup and hold times for DMACK-  
(before assertion or negation)  
Time from STROBE edge to  
negation of DMARQ or assertion of  
STOP (when sender terminates a  
burst)  
Notes:  
1) Unless otherwise specified, timing parameters shall be measured at the connector of the sender or receiver to which the parameter  
applies (see Note 5 for exceptions). For example, the sender shall stop generating STROBE edges t after the negation of  
RFS  
DMARDY-. Both STROBE and DMARDY- timing measurements are taken at the connector of the sender.  
2) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.  
3) tUI, tMLI and tLI indicate sender-to-recipient or recipient-to-sender interlocks, i.e., one agent (either sender or recipient) is waiting for  
the other agent to respond with a signal before proceeding. t is an unlimited interlock that has no maximum time value. MtLI is a  
UI  
limited time-out that has a defined minimum. t is a limited time-out that has a defined maximum.  
LI  
4) Special cabling shall be required in order to meet data setup (t ) and data hold (tDH) times in modes 3 and 4.  
DS  
5) Timing for tDVS and tDVH shall be met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value.  
5 - 84  
C141-E093-01EN  
5.6.3.3 Sustained Ultra DMA data in burst  
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.  
Note:  
DD (15:0) and DSTROBE are shown at both the host and the device to emphasize that  
cable setting time as well as cable propagation delay shall not allow the data signals to be  
considered stable at the host until some time after they are driven by the device.  
Figure 5.11 Sustained Ultra DMA data in burst  
C141-E093-01EN  
5 - 85  
5.6.3.4 Host pausing an Ultra DMA data in burst  
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.  
Notes:  
1) The host may assert STOP to request termination of the Ultra DMA burst no sooner  
than tRP after HDMARDY- is negated.  
2) If the tSR timing is not satisfied, the host may receive zero, one or two more data  
words from the device.  
Figure 5.12 Host pausing an Ultra DMA data in burst  
5 - 86  
C141-E093-01EN  
5.6.3.5 Device terminating an Ultra DMA data in burst  
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.  
Note:  
The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in  
effect after DMARQ and DMACK are negated.  
Figure 5.13 Device terminating an Ultra DMA data in burst  
C141-E093-01EN  
5 - 87  
5.6.3.6 Host terminating an Ultra DMA data in burst  
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.  
Note:  
The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in  
effect after DMARQ and DMACK are negated.  
Figure 5.14 Host terminating an Ultra DMA data in burst  
5 - 88  
C141-E093-01EN  
5.6.3.7 Initiating an Ultra DMA data out burst  
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.  
Note:  
The definitions for the STOP, DDMARDY- and HSTROBE signal lines are not in effect  
until DMARQ and DMACK are asserted.  
Figure 5.15 Initiating an Ultra DMA data out burst  
C141-E093-01EN  
5 - 89  
5.6.3.8 Sustained Ultra DMA data out burst  
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.  
Note:  
DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize  
that cable setting time as well as cable propagation delay shall not allow the data signals to  
be considered stable at the device until some time after they are driven by the host.  
Figure 5.16 Sustained Ultra DMA data out burst  
5 - 90  
C141-E093-01EN  
5.6.3.9 Device pausing an Ultra DMA data out burst  
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.  
Notes:  
1) The device may negate DMARQ to request termination of the Ultra DMA burst no  
sooner than tRP after DDMARDY- is negated.  
2) If the tSR timing is not satisfied, the device may receive zero, one or two more data  
words from the host.  
Figure 5.17 Device pausing an Ultra DMA data out burst  
C141-E093-01EN  
5 - 91  
5.6.3.10 Host terminating an Ultra DMA data out burst  
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.  
Note:  
The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in  
effect after DMARQ and DMACK are negated.  
Figure 5.18 Host terminating an Ultra DMA data out burst  
5 - 92  
C141-E093-01EN  
5.6.3.11 Device terminating an Ultra DMA data in burst  
5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.  
Note:  
The definitions for the STOP, DDMARDY- and HSTROBE signal lines are no longer in  
effect after DMARQ and DMACK are negated.  
Figure 5.19 Device terminating an Ultra DMA data out burst  
C141-E093-01EN  
5 - 93  
5.6.4  
Power-on and reset  
Figure 5.20 shows power-on and reset (hardware and software reset) timing.  
(1)  
Only master device is present  
Clear Reset *1  
Power-on  
tM  
RESET-  
Software reset  
tN  
BSY  
DASP-  
tP  
*1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset.  
Master and slave devices are present (2-drives configuration)  
Clear Reset  
(2)  
[Master device]  
tN  
BSY  
DASP-  
[Slave device]  
BSY  
tQ  
tP  
PDIAG-  
DASP-  
tS  
tR  
Timing parameter  
Symbol  
tM  
tN  
Min.  
25  
Max.  
—
Unit  
ms  
ns  
ms  
s
Pulse width of RESET-  
Time from RESET- negation to BSY set  
—
400  
1
tP  
Time from RESET- negation to DASP- or DIAG- negation  
Self-diagnostics execution time  
—
tQ  
—
30  
tR  
Time from RESET- negation to DASP- assertion (slave device)  
Duration of DASP- assertion  
—
400  
31  
ms  
s
tS  
—
Figure 5.20 Power-on Reset Timing  
5 - 94  
C141-E093-01EN  
CHAPTER 6  
OPERATIONS  
6.1  
6.2  
6.3  
6.4  
6.5  
6.6  
Device Response to the Reset  
Address Translation  
Power Save  
Defect Management  
Read-Ahead Cache  
Write Cache  
6.1  
Device Response to the Reset  
This section describes how the PDIAG- and DASP- signals responds when the power of the  
IDD is turned on or the IDD receives a reset or diagnostic command.  
C141-E093-01EN  
6 - 1  
6.1.1  
Response to power-on  
After the master device (device 0) releases its own power-on reset state, the master device  
shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1).  
The master device recognizes presence of the slave device when it confirms assertion of the  
DASP- signal. Then, the master device checks a PDIAG- signal to see if the slave device has  
successfully completed the power-on diagnostics.  
If the master device cannot confirm assertion of the DASP- signal within 450 ms, the master  
device recognizes that no slave device is connected.  
After the slave device (device 1) releases its own power-on reset state, the slave device shall  
report its presence and the result of power-on diagnostics to the master device as described  
below:  
DASP- signal: Asserted within 400 ms, and negated after the first command is received from  
the host or within 31 seconds or after executing software reset, which ever  
comes first.  
PDIAG- signal: Negated within 1 ms and asserted within 30 seconds, then negated within 31  
seconds.  
Power on  
Master device  
Power On Reset-  
Status Reg.  
BSY bit  
Max. 31 sec.  
Checks DASP- for up to  
450 ms.  
If presence of a slave device is  
confirmed, PDIAG- is checked for  
up to 31 seconds.  
Slave device  
Power On Reset-  
BSY bit  
Max. 1 ms.  
PDIAG-  
DASP-  
Max. 30 sec.  
Max. 400 ms.  
Max. 31 sec.  
Figure 6.1 Response to power-on  
6 - 2  
C141-E093-01EN  
6.1.2  
Response to hardware reset  
Response to RESET- (hardware reset through the interface) is similar to the power-on reset.  
Upon receipt of hardware reset, the master device checks a DASP- signal for up to 450 ms to  
confirm presence of a slave device. The master device recognizes the presence of the slave  
device when it confirms assertion of the DASP- signal. Then the master device checks a  
PDIAG- signal to see if the slave device has successfully completed the self-diagnostics.  
If the master device cannot confirm assertion of the DASP- signal within 450 ms, the master  
device recognizes that no slave device is connected.  
After the slave device receives the hardware reset, the slave device shall report its presence  
and the result of the self-diagnostics to the master device as described below:  
DASP- signal: Asserted within 400 ms, and negated after the first command is received from  
the host or within 31 seconds or after executing software reset, which ever  
comes first.  
PDIAG- signal: Negated within 1 ms and asserted within 30 seconds, then negated within 31  
seconds  
Reset-  
Master device  
Status Reg.  
BSY bit  
Max. 31 sec.  
If presence of a slave device is  
Checks DASP- for up to  
450 ms.  
confirmed, PDIAG- is checked for  
up to 31 seconds.  
Slave device  
BSY bit  
Max. 1 ms.  
PDIAG-  
DASP-  
Max. 30 sec.  
Max. 400 ms.  
Max. 31 sec.  
.
Figure 6.2 Response to hardware reset  
C141-E093-01EN  
6 - 3  
6.1.3  
Response to software reset  
The master device does not check the DASP- signal for a software reset. If a slave device is  
present, the master device checks the PDIAG- signal for up to 31 seconds to see if the slave  
device has completed the self-diagnosis successfully.  
After the slave device receives the software reset, the slave device shall report its presence and  
the result of the self-diagnostics to the master device as described below:  
PDIAG- signal: negated within 1 ms and asserted within 30 seconds then negated within 31  
seconds.  
When the IDD is set to a slave device, the IDD asserts the DASP- signal when negating the  
PDIAG- signal, and negates the DASP- signal when asserting the PDIAG- signal.  
X'3F6' Reg.  
Master device  
X"0C"  
or X"04"  
X"00"  
Status Reg.  
BSY bit  
Max. 31 sec.  
If the slave device is preset, DASP- is checked for up to  
31 seconds.  
Slave device  
BSY bit  
Max. 1 ms.  
PDIAG-  
DASP-  
Max. 30 sec.  
Figure 6.3 Response to software reset  
6 - 4  
C141-E093-01EN  
6.1.4  
Response to diagnostic command  
When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the  
slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see  
if the slave device has completed the self-diagnosis successfully.  
The master device does not check the DASP- signal.  
After the slave device receives the EXECUTE DEVICE DIAGNOSTIC command, it shall  
report the result of the self-diagnostics to the master device as described below:  
PDIAG- signal: negated within 1 ms and asserted within 5 seconds then negated within 6  
seconds.  
When the IDD is set to a slave device, the IDD asserts the DASP- signal when negating the  
PDIAG- signal, and negates the DASP- signal when asserting the PDIAG- signal.  
X'1F7' Reg.  
Write  
Master device  
Status Reg.  
BSY bit  
Max. 6 sec.  
If the slave device is preset, DASP- signal is checked for up to  
6 seconds.  
Slave device  
BSY bit  
Max. 1 ms.  
PDIAG-  
DASP-  
Max. 5 sec.  
Figure 6.4 Response to diagnostic command  
C141-E093-01EN  
6 - 5  
6.2  
Address Translation  
When the IDD receives any command which involves access to the disk medium, the IDD  
always implements the address translation from the logical address (a host-specified address)  
to the physical address (logical to physical address translation).  
Following subsections explains the CHS translation mode.  
6.2.1  
Default parameters  
In the logical to physical address translation, the logical cylinder, head, and sector addresses  
are translated to the physical cylinder, head, and sector addresses based on the number of  
heads and the number of sectors per track which are specified with an INITIALIZE DEVICE  
PARAMETERS command. This is called as the current translation mode.  
If the number of heads and the number of sectors are not specified with an INITIALIZE  
DEVICE PARAMETERS command, the default values listed in Table 6.1 are used. This is  
called as the default translation mode. The parameters in Table 6.1 are called BIOS  
specification.  
Table 6.1 Default parameters  
MPE3043AE  
8,959  
MPE3084AE  
16,383  
16  
MPE3173AE  
Number of cylinders  
Number of head  
Parameters  
(logical)  
15  
Number of sectors/track  
63  
Formatted capacity (GB)  
4.33  
8.45  
17.34  
As long as the formatted capacity of the IDD does not exceed the value shown on Table 6.1,  
the host can freely specify the number of cylinders, heads, and sectors per track.  
Generally, the device recognizes the number of heads and sectors per track with the  
INITIALIZE DEVICE PARAMETER command. However, it cannot recognizes the number  
of cylinders. In other words, there is no way for the device to recognize a host access area on  
logical cylinders. Thus the host should manage cylinder access to the device.  
The host can specify a logical address freely within an area where an address can be specified  
(within the specified number of cylinders, heads, and sectors per track) in the current  
translation mode.  
The host can read an addressable parameter information from the device by the IDENTIFY  
DEVICE command (Words 54 to 56).  
6 - 6  
C141-E093-01EN  
6.2.2  
Logical address  
(1)  
CHS mode  
Logical address assignment starts from physical cylinder (PC) 0, physical head (PH) 0, and  
physical sector (PS) 1 and is assigned by calculating the number of sectors per track which is  
specified by the INITIALIZE DEVICE PARAMETERS command. The head address is  
advanced at the subsequent sector from the last sector of the current physical head address.  
The first physical sector of the subsequent physical sector is the consecutive logical sector  
from the last sector of the current physical sector.  
Figure 6.5 shows an example (assuming there is no track skew).  
Physical sector  
1
2
3
62 63 64  
LS LS  
..  
..  
.. 126 127 .. 189 190.. 574 575 576  
Physical cylinder 0  
LS LS  
1
LS LS  
63  
LS LS  
63  
LS SP SP  
7
2
63  
1
1
1
Physical head 0  
..  
..  
..  
LH0  
LH1  
LH2  
Physical sector  
1
LS  
8
56 57  
LS LS  
63  
183  
575 576  
SP SP  
..  
..119  
120 ..182  
..............  
Physical cylinder 0  
Physical head 1  
LS LS  
63  
LS LS  
63  
1
1
1
..  
..  
..  
..............  
....  
LH10  
LH11  
LH12  
LH13  
ex: Zone 0  
Physical parameter  
- Physical sector: 1 to 574 (For the rest, 2 spare sectors)  
Specification of INITIALIZE DEVICE PARAMETERS command  
- Logical head: LH=0 to 14  
- Logical sector: LS=1 to 63  
Figure 6.5 Address translation (example in CHS mode)  
C141-E093-01EN  
6 - 7  
(2)  
LBA mode  
Logical address assignment in the LBA mode starts from physical cylinder 0, physical head 0,  
and physical sector 1. The logical address is advanced at the subsequent sector from the last  
sector of the current track. The first physical sector of the subsequent physical track is the  
consecutive logical sector from the last sector of the current physical track.  
Figure 6.6 shows an example of (assuming there is no track skew).  
Physical sector  
1
2
3
573 574 575 576  
......................  
......................  
Physical cylinder 0  
Physical head 0  
LBA LBA LBA  
LBA LBA SP  
572 573  
SP  
0
1
2
573 574 575 576  
1
2
3
......................  
......................  
Physical cylinder 0  
Physical head 1  
LBA LBA LBA  
574 575 576  
LBA LBA SP  
1146 1147  
SP  
ex: Zone 0  
Physical parameter  
- Physical sector: 1 to 574 (For the rest, 2 spare sectors)  
Figure 6.6 Address translation (example in LBA mode)  
6.3  
Power Save  
The host can change the power consumption state of the device by issuing a power command  
to the device.  
6.3.1  
Power save mode  
There are four types of power consumption state of the device including active mode where all  
circuits are active.  
In the power save mode, power supplying to the part of the circuit is turned off. There are  
three types of power save modes:  
·
·
·
Idle mode  
Standby mode  
Sleep mode  
6 - 8  
C141-E093-02EN  
(1)  
Active mode  
In this mode, all the electric circuit in the device are active or the device is under seek, read or  
write operation.  
A device enters the active mode under the following conditions:  
·
A command with Seek or Write or Read is issued.  
(2)  
Idle mode  
In this mode, circuits on the device is set to power save mode.  
The device enters the Idle mode under the following conditions:  
·
·
A IDLE or IDLE IMMEDIATE command is issued in the active or standby mode.  
When one of following command is issued, the command is executed narmally and the  
device is still in the idle mode.  
- Reset (hardware or software)  
- IDLE command  
- IDLE IMMEDIATE command  
- A command with out Seek or Write or Read is issued.  
(3)  
Standby mode  
In this mode, the VCM circuit is turned off and the spindle motor is stopped.  
The device can receive commands through the interface. However if a command with disk  
access is issued, response time to the command under the standby mode takes longer than the  
active or Idle mode because the access to the disk medium cannot be made immediately.  
The drive enters the standby mode under the following conditions:  
·
·
·
A STANDBY or STANDBY IMMEDIATE command is issued in the active or idle mode.  
When automatic power down sequence is enabled, the timer has elapsed.  
A reset is issued in the sleep mode.  
When one of following commands is issued, the command is executed normally and the  
device is still stayed in the standby mode.  
·
·
·
·
Reset (hardware or software)  
STANDBY command  
STANDBY IMMEDIATE command  
INITIALIZE DEVICE PARAMETERS command  
C141-E093-02EN  
6 - 9  
·
·
INITIALIZE DEVICE PARAMETERS command  
CHECK POWER MODE command  
(4)  
Sleep mode  
The power consumption of the drive is minimal in this mode. The drive enters only the  
standby mode from the sleep mode. The only method to return from the standby mode is to  
execute a software or hardware reset.  
The drive enters the sleep mode under the following condition:  
·
A SLEEP command is issued.  
Issued commands are invalid (ignored) in this mode.  
6.3.2  
Power commands  
The following commands are available as power commands.  
·
·
·
·
·
·
IDLE  
IDLE IMMEDIATE  
STANDBY  
STANDBY IMMEDIATE  
SLEEP  
CHECK POWER MODE  
6.4  
Defect Management  
Defective sectors of which the medium defect location is registered in the system space are  
replaced with spare sectors in the formatting at the factory shipment.  
All the user space area are formatted at shipment from the factory based on the default  
parameters listed in Table 6.1.  
6 - 10  
C141-E093-01EN  
6.4.1  
Spare area  
Following two types of spare area are provided in the user space.  
1) Spare sector for sector slip:  
used for alternating defective sectors at formatting in shipment in case that a physical track  
contains one or two defective sectors (2 sectors/track)  
2) Spare cylinder for alternative assignment:  
used for alternative assignment for the third and subsequent defective sectors in case that a  
physical track contains three or more defective sectors, and also used by automatic  
alternative assignment. (1 cylinder/drive)  
6.4.2  
Alternating defective sectors  
The two alternating methods described below are available:  
(1)  
Sector slip processing  
A defective sector is not used and is skipped and a logical sector address is assigned to the  
subsequent normal sector (physically adjacent sector to the defective sector).  
When defective sector is present, the sector slip processing is performed in the formatting.  
Figure 6.7 shows an example where (physical) sector 5 is defective on head 0 in cylinder 0.  
Index  
Sector (physical)  
574 575  
576  
1
1
2
2
3
4
5
6
5
7
8
7
Cylinder 0  
Head 0  
Defective  
sector  
SP  
3
4
6
573 574
unused  
If an access request to sector 5 is specified, the device accesses physical sector 6 instead of sector 5.  
Figure 6.7 Sector slip processing  
C141-E093-01EN  
6 - 11  
(2)  
Alternate cylinder assignment  
A defective sector is assigned to the spare sector in the alternate cylinder.  
This processing is performed when a physical track contains three or more defective sectors,  
and when the automatic alternate processing is performed.  
Figure 6.8 shows an example where (physical) sector 5 is detective on head 0 in cylinder 0.  
Index  
Sector (physical)  
576  
575  
1
2
3
4
4
5
6
6
7
7
Cylinder 0  
Defective  
sector  
Head 0  
575  
576  
3
1
2
3
(unused)  
Alternate  
cylinder  
Already  
assigned  
Head 0  
Defective sector is assigned to unassigned sector.  
1 alternate cylinder is provided in outer side.  
When an access request to sector 5 is specified, the device accesses the alternated sector in the  
alternate cylinder instead of sector 5. When an access request to sectors next to sector 5 is  
specified, the device seeks to cylinder 0, head 0, and continues the processing.  
Figure 6.8 Alternate cylinder assignment  
(3)  
Automatic alternate assignment  
The device performs the automatic assignment at following case.  
1) Automatic alternate assignment is done when a read error is recovered by retry beyond the  
regulation number of times during read error retry.  
Before automatic alternate assignment, the device performs rewriting the corrected data to  
the erred sector and rereading. If no error occurs at rereading, the automatic alternate  
assignment is not performed.  
And, this automatic alternate assignment is done only once toward the read command  
receipt from the host.  
2) When a write error occurs and the error does not recovered.  
6 - 12  
C141-E093-01EN  
6.5  
Read-Ahead Cache  
After a read command which reads the data from the disk medium is completed, the read-  
ahead cache function reads the subsequent data blocks automatically and stores the data in the  
data buffer.  
When the next command requests to read the read-ahead data, the data can be transferred from  
the data buffer without accessing the disk medium. The host can access the data at higher  
speed.  
6.5.1  
Data buffer configuration  
The device has a 512-KB data buffer. The buffer is used by divided into two and other  
commands parts; for MPU work, for read cache of read commands and other commands (see  
Figure 6.9).  
512 KB (524,288 bytes)  
for MPU work  
for READ command  
for WRITE command  
63 KB  
305 KB  
132 KB  
(64,512 bytes)  
(312,832 bytes)  
(135,168 bytes)  
Figure 6.9 Data buffer configuration  
The read-ahead operation is performed at execution of the READ SECTOR(S), READ  
MULTIPLE, or READ DMA command, and read-ahead data are stored in the buffer for read  
cache.  
C141-E093-01EN  
6 - 13  
6.5.2  
Caching operation  
The caching operation is performed only at receipt of the following commands. The device  
transfers data from the data buffer to the host system if the following data exist in the data buffer.  
·
·
All sector data to be processed by the command  
A part of data including the starting sector to be processed by the command  
When a part of data to be processed exist in the data buffer, the remaining data are read from  
the disk medium and are transferred to the host system.  
(1)  
Commands that are object of caching operation  
The following commands are object of caching operation.  
·
·
·
·
READ SECTOR (S)  
READ MULTIPLE  
READ DMA  
READ VERIFY  
When the caching operation is disabled by the SET FEATURES command, no caching  
operation is performed.  
(2)  
Data that are object of caching operation  
The following data are object of caching operation.  
1) Read-ahead data read from the disk medium in the data buffer after completion of the  
command that are object of caching operation.  
2) Data transferred to the host system once by requesting with the command that are object of  
caching operation. When the sector data requested by the host does not finish storing in  
the buffer for read cache, it is not object of caching operation. And also, when the  
sequential hit occurs continuously, the caching data required by the host becomes invalid.  
(3)  
Invalidating caching data  
Caching data in the data buffer is invalidated in the following case.  
1) Commands other than the following commands are issued (all caching data are invalidated)  
·
·
·
·
READ SECTOR(S)  
READ DMA  
READ MULTIPLE  
READ VERIFY  
2) Caching operation is disabled by the SET FEATURES command.  
3) Command issued by the host is terminated with an error.  
4) Soft reset or hard reset is executed, or power is turned off.  
6 - 14  
C141-E093-01EN  
6.5.3  
Usage of read segment  
This subsection explains the usage of the read segment buffer at following cases.  
(1)  
Miss-hit (no hit)  
A lead block of the read-requested data is not stored in the data buffer. The requested data is  
read from the disk media.  
1) Sets the host address pointer (HAP) and the disk address pointer (DAP) to the sequential  
address to the last read segment.  
HAP  
Segment only for read  
DAP  
2) Transfers the requested data that already read to the host system with reading the requested  
data from the disk media.  
Stores the read-requested  
data upto this point  
HAP  
Empty area  
Read-requested data  
DAP  
3) After reading the requested data and transferring the requested data to the host system had  
been completed, the disk drive continues to read till a certain amount of data is stored.  
HAP  
(stopped)  
Read Ahead Data  
Read-requested data  
(stopped)  
DAP  
4) Following shows the cache enabled data for next read command.  
Cache enabled data  
Start LBA  
Last LBA  
6 - 15  
C141-E093-01EN  
(3)  
Sequential read  
When the disk drive receives the read command that targets the sequential address to the  
previous read command, the disk drive tries to fill the buffer space with the read ahead data.  
a. Sequential command just after non-sequential command  
1) At receiving the sequential read command, the disk drive sets the DAP and HAP to  
the sequential address of the last read command and reads the requested data.  
HAP  
Mis-hit data  
Empty data  
DAP  
2) The disk drive transfers the requested data that is already read to the host system with  
reading the requested data.  
HAP  
Mis-hit data  
Requested data  
Empty data  
DAP  
3) After completion of the reading and transferring the requested data to the host system,  
the disk drive performs the read-ahead operation continuously till a certain amount of  
data is stored.  
HAP  
Read-  
ahead  
data  
Empty  
data  
Mis-hit data  
Requested data  
DAP  
6 - 16  
C141-E093-01EN  
b. Sequential hit  
When the last sector address of the previous read command is sequential to the lead sector  
address of the received read command, the disk drive transfers the hit data in the buffer to  
the host system.  
The disk drive performs the read-ahead operation of the new continuous data to the empty  
area that becomes vacant by data transfer at the same time as the disk drive starts  
transferring data to the host system.  
1) In the case that the contents of buffer is as follows at receiving a read command;  
HAP (Completion of transferring requested data)  
Read-ahead data  
Hit data  
DAP  
Last LBA Start LBA  
2) The disk drive starts the read-ahead operation to the empty area that becomes vacant  
by data transfer at the same time as the disk drive starts transferring hit data.  
HAP  
Read-ahead data  
New read-ahead data  
Hit data  
DAP  
3) After completion of data transfer of hit data, the disk drive performs the read-ahead  
operation for the data area of which the disk drive transferred hit data.  
HAP  
Read-ahead data  
DAP  
C141-E093-01EN  
6 - 17  
(3)  
Full hit (hit all)  
All requested data are stored in the data buffer. The disk drive starts transferring the requested  
data from the address of which the requested data is stored. After completion of command, a  
previously existed cache data before the full hit reading are still kept in the buffer, and the disk  
drive does not perform the read-ahead operation. If the disk drive receives a full hit command  
while performing the read-ahead operation, the disk drive starts transfering the requested data  
without stopping the read-ahead operation.  
1) In the case that the contents of the data buffer is as follows for example and the previous  
command is a sequential read command, the disk drive sets the HAP to the address of  
which the hit data is stored.  
Last position at previous read command  
HAP  
HAP (set to hit position for data transfer)  
Cache data  
Full hit data  
Cache data  
DAP  
Last position at previous read command  
2) The disk drive transfers the requested data but does not perform the read-ahead operation.  
HAP  
(stopped)  
Cache data  
Full hit data  
Cache data  
(4)  
Partially hit  
A part of requested data including a lead sector are stored in the data buffer. The disk drive  
starts the data transfer from the address of the hit data corresponding to the lead sector of the  
requested data, and reads remaining requested data from the disk media directly.  
Following is an example of partially hit to the cache data.  
Cache data  
Last LBA  
Start LBA  
6 - 18  
C141-E093-01EN  
1) The disk drive sets the HAP to the address where the partially hit data is stored, and sets  
the DAP to the address just after the partially hit data.  
HAP  
Partially hit data  
Lack data  
DAP  
2) The disk drive starts transferring partially hit data and reads lack data from the disk media  
at the same time.  
HAP  
(stopped)  
Requested data to be transferred  
Partially hit data  
Lack data  
DAP  
C141-E093-01EN  
6 - 19  
6.6  
Write Cache  
The write cache function of the drive makes a high speed processing in the case that data to be  
written by a write command is logically sequent the data of previous command and random  
write operation is performed.  
When the drive receives a write command, the drive starts transferring data of sectors  
requested by the host system and writing on the disk medium. After transferring data of  
sectors requested by the host system, the drive generates the interrupt of command complete.  
Also, the drive sets the normal end status in the Status register. The drive continues writing  
data on the disk medium. When all data requested by the host are written on the disk medium,  
actual write operation is completed.  
The drive receives the next command continuously. If the received command is a "sequential  
write" (data to be written by a command is logically sequent to data of previous command),  
the drive starts data transfer and receives data of sectors requested by the host system. At this  
time, if the write operation of the previous command is still been executed, the drive  
continuously executes the write operation of the next command from the sector next to the last  
sector of the previous write operation. Thus, the latency time for detecting a target sector of  
the next command is eliminated. This shortens the access time. The drive generates an  
interrupt of command complete after completion of data transfer requested by the host system  
as same as at previous command. When the write operation of the previous command had  
been completed, the latency time occurs to search the target sector.  
If the received command is not a "sequential write", the drive receives data of sectors  
requested by the host system as same as "sequential write". The drive generates the interrupt  
of command complete after completion of data transfer requested by the host system.  
Received data is processed after completion of the write operation to the disk medium of the  
previous command.  
Even if a hard reset or soft reset is received or the write cache function is disabled by the SET  
FEATURES command during unwritten data is kept, the instruction is not executed until  
remaining unwritten data is written onto the disk medium.  
The drive uses a write data as a read cache data. When a read command is issued to the same  
address after the write command, the read operation to the disk medium is not performed.  
When an error occurs during the write operation, the drive makes retry as much as possible. If  
the error cannot be recovered by retry, the drive stops the write operation to the erred sector,  
and continues the write operation from the next sector if the write data is remained. (If the  
drive stacks a write command, for that the drive posts the command completion, next to the  
command that write operation is stopped by error occurrence.) After an error occurs at above  
write operation, the drive posts the error status to the host system at next command. (The  
drive does not execute this command, sets the error status that occurred at the write operation,  
and generates the interrupt for abnormal end. However, when the drive receives a write  
command after the completion of error processing, the drive posts the error after writing the  
write data of the write command.)  
6 - 20  
C141-E093-01EN  
At the time that the drive has stopped the command execution after the error recovery has  
failed, the write cache function is disabled automatically. The releasing the disable state can  
be done by the SET FEATURES command. When the power of the drive is turned on after  
the power is turned off once, the status of the write cache function returns to the default state.  
The default state is “write cache enable”, and can be disable by the SET FEATURES  
command.  
The write cache function is operated with the following command.  
·
·
·
WRITE SECTOR(S)  
WRITE MULTIPLE  
WRITE DMA  
IMPORTANT  
When the write cache function is enabled, the transferred data from  
the host by the WRITE SECTOR(S) is not completely written on the  
disk medium at the time that the interrupt of command complete is  
generated. When the unrecoverable error occurs during the write  
operation, the command execution is stopped. Then, when the drive  
receives the next command, it generates an interrupt of abnormal  
end. However an interrupt of abnormal end is not generated when  
a write automatic assignment succeeds. However, since the host  
may issue several write commands before the drive generates an  
interrupt of abnormal end, the host cannot recognize that the  
occurred error is for which command generally. Therefore, it is  
very hard to retry the unrecoverable write error for the host in the  
write cache operation generally. So, take care to use the write  
cache function.  
C141-E093-01EN  
6 - 21  
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