AMD SB600
Register Reference Manual
(Public Version)
Technical Reference Manual
Rev. 3.03
P/N: 46155_sb600_rrg_pub_3.03
©2008 Advanced Micro Devices, Inc.
Table of Contents
1 Introduction .............................................................................................................7
2 Register Descriptions: PCI Devices.....................................................................13
BAR0/BAR2/BAR1/BAR3 Registers (SATA I/O Register for IDE mode)..............................................24
BAR4 Registers (SATA I/O Register for IDE mode).............................................................................24
Host Controller Operational Registers (EOR_Reg).............................................................................................. 82
USB2.0 Debug Port Registers.............................................................................................................................. 92
SMBus Module and ACPI Block (Device 20, Function 0)............................................................ 96
Legacy ISA and ACPI Controller........................................................................................................126
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
Table of Contents
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Proprietary
Audio Registers (Device 20, Function 5)............................................................................................198
Modem Registers (Device 20, Function 6).........................................................................................213
HD Audio Controller PCI Configuration Space Registers (Device 20 Function 2)..............................227
3 Register Descriptions: PCI Bridges...................................................................249
4 Register Descriptions: General Purpose Functions/Interrupt Controllers/Support
Function Pins.............................................................................................................277
GPIO..................................................................................................................................................277
General Purpose Event (GPE)...........................................................................................................283
ExtEvent to Generate SMI#................................................................................................................................ 287
THRMTRIP/TALERT.................................................................................................................. 288
Real Time Clock (RTC).............................................................................................................. 289
Direct Access Registers.....................................................................................................................296
Appendix A: AC97 Audio FAQs ...............................................................................299
Appendix B: Revision History..................................................................................300
©2008 Advanced Micro Devices, Inc.
List of Figures
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AMD SB600 Register Reference Manual
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List of Figures
Figure 4 SMBus/ACPI PCI Configuration Space Function Block Association..............................................................96
©2008 Advanced Micro Devices, Inc.
List of Figures
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AMD SB600 Register Reference Manual
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List of Tables
Table 1-1: Register Description Table Notation—Example............................................................................................7
Table 2-6 HceStatus Register......................................................................................................................................69
Table 2-8 IDE Device Registers Mapping..................................................................................................................196
Table 4-1: GPIO Pins.................................................................................................................................................277
Table 4-6: THRMTRIP Pin.........................................................................................................................................288
©2008 Advanced Micro Devices, Inc.
List of Tables
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AMD SB600 Register Reference Manual
Proprietary
1 Introduction
1.1
About this Manual
This manual is a register reference guide for the AMD SB600 Southbridge. It integrates the key I/O,
communications, and audio features required in a state-of-the-art PC into a single device. It is specifically
designed to operate with AMD’s RADEON IGP Xpress family of integrated graphics processor products in
both desktop and mobile PCs.
1.2 Nomenclature and Conventions
1.2.1
Recent Updates
Updates recent to each revision are highlighted in red.
1.2.2
Numeric Representations
•
•
Hexadecimal numbers are prefixed with “0x” or suffixed with “h,” whenever there is a possibility
of confusion. Other numbers are decimal.
Registers (or fields) of an identical function are sometimes indicated by a single expression in
which the part of the signal name that changes is enclosed in square brackets. For example,
registers HOST_DATA0 through to HOST_DATA7 is represented by the single expression
HOST_DATA[7:0].
1.2.3
Register Description
All registers in this document are described with the format of the sample table below. All offsets are
in hexadecimal notation, while programmed bits are in either binomial or hexadecimal notation.
Table 1-1: Register Description Table Notation—Example
Latency Timer – RW – 8 bits – [Offset: 0Dh]
Field Name
Bits
Default
Description
Latency Timer (R/W)
7:0
00h
This bit field is used to specify the time in number of PCI
clocks, the SATA controller as a master is still allowed to
control the PCI bus after its GRANT_L is deasserted. The
lower three bits [0A:08] are hardwired to 0 h , resulting in a
time granularity of 8 clocks.
Latency Timer. Reset Value: 00h
©2008 Advanced Micro Devices, Inc.
About this Manual
AMD SB600 Register Reference Manual
Proprietary
Page 7
Register Information
Value/Content in the Example
Register name
Latency Timer
Read / Write capability
R = Readable
W = Writable
RW
RW = Readable and Writable
Register size
8 bits
Register address(es)*
Field name
Offset: 0Dh
Latency Timer (R/W)
Field position/size
Field default value
Field description
7:0
00h
“This bit … 8 clocks.”
Field mirror information
Brief register description
Latency Timer. Reset Value: 00h
* Note: There maybe more than one address; the convention used is as follows:
[aperName:offset] - single mapping, to one aperture/decode and one offset
[aperName1, aperName2, …, aperNameN:offset] - multiple mappings to different apertures/decodes but same
offset
[aperName:startOffset-endOffset] - mapped to an offset range in the same aperture/decode
Warning: Do not attempt to modify values of registers or bit fields marked "Reserved." Doing so may cause
the system to behave in unexpected manners.
©2008 Advanced Micro Devices, Inc.
Nomenclature and Conventions
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AMD SB600 Register Reference Manual
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1.3 Features of the SB600
CPU Interface
ƒ
Supports serial interrupt on quiet and
continuous modes
ƒ
Supports both Single and Dual core AMD
CPUs
DMA Controller
ƒ Desktop: Athlon 64, Athlon 64 FX, Athlon
64 X2, Sempron, Opteron, dual-core
Opteron
ƒ
ƒ
ƒ
ƒ
Two cascaded 8237 DMA controllers
Supports PC/PCI DMA
ƒ Mobile: Athlon XP-M, Mobile Athlon 64,
Supports LPC DMA
Turion 64, Mobile Sempron
Supports type F DMA
PCI Host Bus Controller
LPC host bus controller
ƒ
ƒ
ƒ
ƒ
ƒ
Supports PCI Rev. 2.3 specification
Supports PCI bus at 33MHz
ƒ
Supports LPC based super I/O and flash
devices
Supports up to 6 bus master devices
Supports 40-bit addressing
ƒ
ƒ
Supports two master/DMA devices
Supports TPM version 1.1/1.2 devices for
enhanced security
Supports interrupt steering for plug-n-play
devices
ƒ
Supports SPI devices
ƒ
ƒ
Supports concurrent PCI operations
Supports hiding of PCI devices by
BIOS/hardware
SATA II AHCI Controller
ƒ
ƒ
ƒ
ƒ
Supports four SATA ports, complying with the
SATA 2.0 specification
ƒ
Supports spread spectrum on PCI clocks
Supports SATA II 3.0GHz PHY, with
backward compatibility with 1.5GHz
USB controllers
ƒ
5 OHCI and 1 EHCI Host controllers to
support 10 USB ports
Supports RAID striping (RAID 0) across all 4
ports
ƒ
All 10 ports are USB 1.1 (“Low Speed”, “Full
Speed”) and 2.0 (“High Speed”) compatible
Supports RAID mirroring (RAID 1) across all 4
ports
ƒ
ƒ
ƒ
ƒ
Supports ACPI S1~S5
ƒ
ƒ
ƒ
Supports RAID 10 (4 ports needed)
Supports legacy keyboard/mouse
Supports USB debug port
Supports both AHCI mode and IDE mode
Supports advanced power management with
ACHI mode
Supports port disable with individual control
SMBus Controller
IDE Controller
ƒ
ƒ
SMBus Rev. 2.0 compliant
ƒ
ƒ
Single PATA channel support
Support SMBALERT # signal / GPIO
Supports PIO, Multi-word DMA, and Ultra
DMA 33/66/100/133 modes
Interrupt Controller
ƒ
32x32byte buffers on each channel for
buffering
ƒ
Supports IOAPIC/X-IO APIC mode for 24
channels of interrupts
ƒ
ƒ
ƒ
Swap bay support by tri-state IDE signals
Supports Message Signaled Interrupt (MSI)
Integrated IDE series resistors
ƒ
ƒ
Supports 8259 legacy mode for 15 interrupts
Supports programmable level/edge triggering
on each channels
©2008 Advanced Micro Devices, Inc.
Features of the SB600
AMD SB600 Register Reference Manual
Proprietary
Page 9
AC Link interface
ƒ
ƒ
ƒ
ƒ
Supports for both audio and modem codecs
Compliant with AC-97 codec Rev. 2.3
6/8 channel support on audio codec
RTC (Real Time Clock)
ƒ
ƒ
ƒ
256-byte battery-backed CMOS RAM
Hardware supported century rollover
RTC battery monitoring feature
Multiple functions for audio and modem
Codec operations
Power Management
ƒ
ƒ
ƒ
ƒ
Bus master logic
ƒ
ACPI specification 2.0 compliant power
management schemes
Supports up to 3 codecs simultaneously
Supports SPDIF output
ƒ
ƒ
ƒ
Supports C2, C3, C4, ACPI states
Supports C1e and C3 pop-up
Separate bus from the HD audio
Supports S0, S1, S2, S3, S4, and S5
HD Audio
ƒ
Wakeup events for S1, S2, S3, S4/S5
generated by:
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
4 Independent output streams (DMA)
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
Any GEVENT pin
Any GPM pin
USB
4 Independent input streams (DMA)
Up to 16 channels of audio output per stream
Supports up to 4 codecs
Power button
Internal RTC wakeup
SMI# event
Up to 192kHz sample rate
Up to 32-bit per sample
Message Signaled Interrupt (MSI) capability
64-bit addressing capability for MSI
ƒ
ƒ
Full support for On-Now™
Supports CPU SMM, generating SMI# signal
upon power management events
64-bit addressing capability for DMA bus
master
ƒ
ƒ
GPIO supports on external wake up events
ƒ
ƒ
Unified Audio Architecture (UAA) compatible
Supports CLKRUN# on PCI power
management
HD Audio registers can be located anywhere
in the 64-bit address space
ƒ
ƒ
Provides clock generator and CPU STPCLK#
control
Timers
Support for ASF
ƒ
ƒ
ƒ
8254-compatible timer
Microsoft High Precision Event Timer (HPET)
ACPI power management timer
©2008 Advanced Micro Devices, Inc.
Features of the SB600
AMD SB600 Register Reference Manual
Proprietary
Page 10
1.4
Block Diagrams
This section contains two block diagrams for the SB600. Figure 1 shows the SB600 internal PCI devices with
their assigned bus, device, and function numbers. Figure 2 shows the SB600 internal PCI devices and the
major function blocks.
ALINK-EXPRESS II
AC97 Audio
AB
Bus 0 DEV 20
Function 5
Device ID 4382h
AC97
B-LINK
A-LINK
PORT 1
PORT 0
4 PORTS
SATA Controller 1
AC97 Modem
Bus 0 DEV 18 Function 0
Device ID 4380h
Bus 0 DEV 20
Function 6
Device ID 438Eh
USB:OHCI x5
Bus 0 DEV 19 Function 0:4
Device ID 4387h : 4388h :
B-LINK
HD Audio
10 PORTS
Bus 0 DEV 20
Function 2
4389h : 438Ah : 438Bh
USB:EHCI
Device ID 4383h
Bus 0 DEV 19 Function 5
Device ID 4386h
Debug port
ALINK
IDE
1 CHANNEL
PCI Bridge
Bus 0 DEV 20
Function 1
Device ID 438Ch
Bus 0 DEV 20
Function 4
6 PCI SLOTS
Device ID 4384h
LPC
LPC bus
SPI bus
Bus 0 DEV 20
Function 3
Device ID 438Dh
SMBUS /ACPI
Bus 0 DEV 20 Function 0
Device ID 4385h
Figure 1 SB600 PCI Internal Devices
©2008 Advanced Micro Devices, Inc.
Block Diagrams
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AMD SB600 Register Reference Manual
Proprietary
ALINK-EXPRESS II
AB
B-LINK
A-LINK
PORT 1
PORT 0
AC97 Audio
4 PORTS
SATA
Controller
AC97
AC97 Modem
B-LINK
HD Audio
USB:OHCI
10 PORTS
USB:EHCI
Debug port
ALINK
1
CHANNEL
IDE
LPC bus
SPI bus
SMBUS /ACPI
BUS Controler
LPC
ROM
GPIO
PCI Bridge
6 PCI SLOTS
RTC
X1/X2
SIRQ
SERIRQ#
PICD[0]
RTC_IRQ#,
PIDE_INTRQ,
SIDE_INTRQ,
USB_IRQ#,
AC97INTAB,
AC97INTBB
APIC
PIC
BM
SPEAKER
8250 TIMER
INTERRUPT
controller
ACPI / HW
Monitor
SMI
SMBUS
PM
INTR
PWRGOOD
CPURST,
IGNNE#,
FERRB#,
INT# F:A
GEVENT[7:0],SLPBUTTON
TEMPDEAD, TEMPCAUT,
SHUTDOWN,DC_STOP#
SCIOUT, SLP#,
INIT#,
RESET#
CPUSTP#, PCISTP#,
STPCLK#, SOFF#, SMI#,
SMIACT#
Figure 2 SB600 PCI Internal Devices and Major Function Blocks
©2008 Advanced Micro Devices, Inc.
Block Diagrams
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AMD SB600 Register Reference Manual
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2 Register Descriptions: PCI Devices
2.1 SATA Registers (Device 18, Function 0)
Note: Some SATA functions are controlled by, and associated with, certain PCI configuration registers in the
SMBus/ACPI device. For more information refer to section 2.3: SMBus Module and ACPI Block (Device 20,
Function 0). The diagram below lists these SATA functions and the associated registers.
SATA
SATA Enables
SATA power saving
SATA Interrupt Map register
SATA Smart Power Control
PCI_Reg:
AC/AFh
5Ch
98h
2.1.1
PCI Configuration Space
The PCI Configuration Space registers define the operation of the SB600’s SATA controller on the PCI bus.
These registers are accessible only when the SATA controller detects a Configuration Read or Write
operation, with its IDSEL asserted, on the 32-bit PCI bus.
Register Name
Vendor ID
Offset Address
00h
Device ID
02h
Command
04h
Status
06h
Revision ID/Class Code
Cache Link Size
Master Latency Timer
Header Type
08h
0Ch
0Dh
0Eh
0Fh
10h
BIST Mode Type
Base Address 0
Base Address 1
14h
Base Address 2
18h
Base Address 3
1Ch
20h
24h
2Ch
34h
3Ch
3Dh
3Eh
3Fh
40h
Bus Master Interface Base Address
AHCI Base Address
Subsystem ID and Subsystem Vendor ID
Capabilities Pointer
Interrupt Line
Interrupt Pin
Min_gnt
Max_latency
Misc control
Watch Dog Control And Status
Watch Dog Counter
MSI Control
44h
46h
50h
MSI Address
54h
MSI Upper Address
MSI Data
Power Management Capability ID
Power Management Capability
Power Management Control And Status
58h
5Ch
60h
62h
64h
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
Proprietary
Page 13
Register Name
Serial ATA Capability Register 0
Serial ATA Capability Register 1
IDP Index
Offset Address
70h
74h
78h
7Ch
88h
8Ch
90h
94h
C0h
C4h
IDP Data
PHY Port0 Control
PHY Port1 Control
PHY Port2 Control
PHY Port3 Control
BIST pattern Count
PCI Target Control TimeOut Counter
Vendor ID - R - 16 bits - [PCI_Reg:00h]
Field Name
Vendor ID
Bits
15:0
Default
Description
1002h
This register holds a unique 16-bit value assigned to a vendor.
Combined with the device ID, it identifies any PCI device.
Device ID - R - 16 bits - [PCI_Reg:02h]
Field Name
Device ID
Bits
15:0
Default
Description
4380h
This register holds a unique 16-bit value assigned to a device.
Combined with the vendor ID, it identifies any PCI device.
4380h for the non-Raid5 controller
4381h for the Raid5 controller.
Bonding option default to the non-Raid 5 controller.
Command - RW - 16 bits - [PCI_Reg:04h]
Field Name
Bits
Default
Description
I/O Access Enable
0
1
2
0b
This bit controls access to the I/O space registers. When this
bit is 1, it enables the SATA controller to respond to PCI IO
space access.
This bit controls access to the memory space registers. When
this bit is 1, it enables the SATA controller to respond to PCI
memory space access
Memory Access Enable
Bus Master Enable
0b
0b
Bus master function enable.
1 = Enable
0 = Disable.
Special Cycle
3
4
5
6
0b
0b
0b
0b
Read Only. Hardwired to ‘0’
Recognition Enable
Memory Write and
Invalidate Enable
VGA Palette Snoop
Enable
Read Only. Hardwired to ‘0’
Read Only. Hard-wired to ‘0’ indicating that the SATA host
controller does not need to snoop VGA palette cycles.
If set to 1, the IDE host controller asserts PERR- when it is the
agent receiving data AND it detects a parity error. PERR- is
not asserted if this bit is 0.
PERR- Detection Enable
Wait Cycle Enable
SERR- Enable
7
0b
0b
Read Only.
Hard-wired to ‘0’ to indicate that the SATA controller does not
need to insert a wait state between the address and data on
the AD lines.
If set to 1, and bit 6 is set, then the SATA controller asserts
SERR- when it detects an address parity error. SERR- is not
asserted if this bit is 0.
Read Only. Hard-wired to ‘0’ to indicate that fast back to back
is only allowed to the same agent.
Complies with the PCI 2.3 specification.
Reserved.
8
9
Fast Back-to-Back
Enable
Interrupt Disable
Reserved
0b
0b
10
15:11
©2008 Advanced Micro Devices, Inc.
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SATA Registers (Device 18, Function 0)
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Status - RW - 16 bits - [PCI_Reg:06h]
Field Name
Reserved
Interrupt Status
Capabilities List
Bits
2:0
3
Default
Description
Reserved.
0b
1b
Interrupt status bit. Complies with the PCI 2.3 specification.
Read Only. Hardwired to 1 to indicate that the Capabilities
Pointer is located at 34h.
4
66MHz Support
5
1b
66MHz capable. This feature is supported in the SATA
controller.
Reserved
Fast Back-to-Back
Capable
6
7
Reserved.
0b
0b
Read Only. Hard-wired to ‘0’ to indicate that it is fast back to
back incapable.
Data Parity reported. Set to 1 if the SATA controller detects
PERR- asserted while acting as the PCI master (whether
PERR- was driven by the SATA controller or not.). Write ‘1’ to
clear this bit.
Data Parity Error
8
DEVSEL- Timing
10:9
01b
Read only.
These bits indicate DEVSEL- timing when performing a
positive decode. Since DEVSEL- is asserted to meet the
medium timing, these bits are encoded as 01b.
Signaled Target Abort. This bit is set to 1, when the SATA
controller signals Target Abort. Write ‘1’ to clear this bit.
Received Target Abort. This bit is set to 1 when the SATA
controller that generated the PCI cycle (SATA controller is the
PCI master) is aborted by a PCI target. Write ‘1’ to clear this
bit.
Signaled Target Abort
Received Target Abort
11
12
0b
0b
Received Master Abort
Status
13
0b
Received Master Abort Status. Set to 1 when the SATA
controller, acting as a PCI master, aborts a PCI bus memory
cycle. Write ‘1’ to clear this bit..
SERR- Status
14
15
0b
0b
SERR- status. This bit is set to 1 when the SATA controller
detects a PCI address parity error. Write ‘1’to clear this bit.
Detected Parity Error. This bit is set to 1 when the SATA
controller detects a parity error. Write ‘1’ to clear this bit.
Detected Parity Error
Revision ID/Class Code- R - 32 bits - [PCI_Reg:08h]
Field Name
Revision ID
Bits
Default
Description
These bits are hardwired to 00h to indicate the revision level of
the chip design.
7:0
00h
Operating Mode
Selection
15:8
8Fh
RW
Programmable I/F.
Bit [15] = Master IDE Device. Always 1.
Bits [14:12] = Reserved. Always read as 0’s.
Bit [11] = Programmable indicator for Secondary. Always 1 to
indicate that both modes are supported.
Bit [10] = Operating Mode for Secondary.
1 = Native PCI-mode.
0 = Compatibility Mode
Bit [9] = Programmable indicator for Primary. Always 1 to
indicate that both modes are supported.
Bit [8] = Operating Mode for Primary.
1 = Native PCI-mode.
0 = Compatibility
Sub-Class Code
Class Code
23:16
31:24
01h
01h
Sub-Class Code. 01h to indicate an IDE Controller. See Note.
Class Code. These 8 bits are read only and wired to 01h to
indicate a Mass-Storage Controller.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
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Page 15
Revision ID/Class Code- R - 32 bits - [PCI_Reg:08h]
Field Name
Bits
Default
Description
Note: This field is only writeable when PCI_Reg:40h[0] is set.
Sub-Class Code Program Interface Controller Type
01
06
04
8F
01
00
IDE
AHCI
RAID
Cache Line Size - RW - 8 bits - [PCI_Reg:0Ch]
Field Name
Reserved
Cache Line Size Register
Bits
Default
Description
3:0
7:4
Reserved.
If the value is 1, then the cache line size is 16 DW (64 byte).
0h
Master Latency Timer - RW - 8 bits - [PCI_Reg:0Dh]
Field Name
Reserved
Bits
Default
Description
2:0
Reserved.
Master Latency Timer
7:3
00h
Master Latency Timer. This number, in units of clocks,
represents the guaranteed time slice allowed to the IDE host
controller for burst transactions.
Header Type - R - 8 bits - [PCI_Reg:0Eh]
Field Name
Bits
Default
Description
Header Type
7:0
00h
Header Type. Since the IDE host controller is a single-function
device, this register contains a value of 00h.
BIST Mode Type - RW - 8 bits - [PCI_Reg:0Fh]
Field Name
Bits
Default
Description
Completion Code
3:0
0h
Read Only.
Indicates the completion code status of BIST. A non-zero
value indicates a failure.
Reserved
Start BIST
BIST Capable
5:4
6
7
Reserved.
0b
0b
Since bit [7] is 0, program this bit take no effect.
Read Only. Hard-wired to ‘0’ indicating that there is no HBA
related BIST function.
Base Address 0 - RW - 32 bits - [PCI_Reg:10h]
Field Name
Resource Type Indicator
Bits
Default
Description
RTE (Resource Type Indicator). This bit is wired to 1 to
indicate that the base address field in this register maps to I/O
space.
0
1b
Reserved
2:1
Reserved.
Primary IDE CS0 Base
Address
31:3
0000_
0000h
Base Address for Primary IDE Bus CS0. This register is used
for native mode only. Base Address 0 is not used in
compatibility mode.
Base Address 1 - RW - 32 bits - [PCI_Reg:14h]
Field Name
Resource Type Indicator
Bits
Default
Description
RTE (Resource Type Indicator). This bit is wired to 1 to
indicate that the base address field in this register maps to I/O
space.
0
1b
Reserved
1
Reserved.
Primary IDE CS1 Base
Address
31:2
0000_
0000h
Base Address for Primary IDE Bus CS1. This register is used
for native mode only. Base Address 1 is not used in
compatibility mode.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
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Page 16
Base Address 2 - RW - 32 bits - [PCI_Reg:18h]
Field Name
Resource Type Indicator
Bits
Default
Description
This bit is wired to 1 to indicate that the base address field in
this register maps to I/O space.
0
1b
Reserved
2:1
Reserved.
Secondary IDE CS0
Base Address
31:3
0000_
0000h
Base Address for Secondary IDE Bus CS0. This register is
used for native mode only. Base Address 2 is not used in
compatibility mode.
Base Address 3 - RW - 32 bits - [PCI_Reg:1Ch]
Field Name
Resource Type Indicator
Bits
Default
Description
This bit is wired to 1 to indicate that the base address field in
this register maps to I/O space.
0
1b
Reserved
1
Reserved.
Secondary IDE CS1
Base Address
31:2
0000_
0000h
Base Address for Secondary IDE Bus CS1. This register is
used for native mode only. Base Address 3 is not used in
compatibility mode.
Bus Master Interface Base Address - RW - 32 bits - [PCI_Reg:20h]
Field Name
Bits
0
Default
Description
This bit is wired to 1 to indicate that the base address field in
this register maps to I/O space.
Resource Type Indicator
1b
Reserved
3:1
Reserved.
Bus Master Interface
Register Base Address
31:4
0000_
000h
Base Address for the Bus Master interface registers, and
corresponds to AD[15:4].
AHCI Base Address - RW - 32 bits - [PCI_Reg:24h]
Field Name
Bits
Default
Description
Resource Type Indicator
0
0b
This bit is wired to 0 to indicate a request for register memory
space.
Reserved
9:1
Reserved.
AHCI Base Address
31:10
000000h Base address of register memory space. This represents a
memory space for support of 4 ports.
Subsystem ID and Subsystem Vendor ID - RW - 32 bits - [PCI_Reg:2Ch]
Field Name
Bits
Default
Description
Subsystem Vendor ID
15:0
0000h
Subsystem Vendor ID. This can only be written once by the
software.
Subsystem ID
31:16
0000h
Subsystem ID. This can only be written once by the software.
Capabilities Pointer - R - 8 bits - [PCI_Reg:34h]
Field Name
Bits
Default
Description
Capabilities Pointer
7:0
60h
The first pointer of the Capability block
Interrupt Line - RW - 8 bits - [PCI_Reg:3Ch]
Field Name
Bits
Default
Description
Interrupt Line
7:0
00h
Identifies which input on the interrupt controller the function’s
PCI interrupt request pin (as specified in its Interrupt Pin
register) is routed to.
Interrupt Pin - R - 8 bits - [PCI_Reg:3Dh]
Field Name
Bits
Default
Description
Interrupt Pin
7:0
01h
Hard-wired to 01h.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
Proprietary Page 17
Min_gnt - R - 8 bits - [PCI_Reg:3Eh]
Field Name
Minimum Grant
Bits
7:0
Default
Description
00h
This register specifies the desired settings for how long of a
burst the SATA controller needs. The value specifies a period
of time in units of ¼ microseconds.
Hard-wired to 0’s and always read as 0’s.
Max_latency - R - 8 bits - [PCI_Reg:3Fh]
Field Name
Bits
Default
Description
Maximum Latency
7:0
00h
This register specifies the Maximum Latency time required
before the SATA controller as a bus-master can start an
accesses
Hard-wired to 0’s and always read as 0’s.
Misc Control - RW - 32 bits - [PCI_Reg:40h]
Field Name
Subclass code write
Enable
Bits
Default
Description
0
1
2
0b
Once set, Program Interface register (PCI_Reg:09h), subclass
code register (PCI_Reg:0Ah) and Multiple Message Capable
bits (PCI_Reg50h[19:17]) can be programmable.
When clear, dynamic power saving function for SATA internal
memory macros will be performed to reduce power
consumption.
When set, dynamic power saving function for SATA core clock
will be performed during partial/slumber mode to reduce power
consumption.
Disable Dynamic Sata
Memory Power Saving
0b
0b
Enable dynamic Sata
Core Power Saving
Reserved
Disable Speed up XP
Boot
3
4
Reserved.
0b
When clear, it fastens XP boot up in IDE mode. However, this
bit needs to be set, when enable SATA partial/slumber power
function is in IDE mode.
When set, the SATA partial/slumber power function can be
enabled in IDE mode, but the BIOS IO trap is needed to speed
up XP boot-up in IDE mode.
Please refer to BAR5 + offset 12C/1Ac/22C/2AC[11:8] for the
SATA partial/slumber modes that are allowed.
Reserved
Reserved
Reserved
5
15:6
16
17
18
0b
Reserved.
Disable port0
Disable port1
Disable port2
Disable port3
Reserved
0b
0b
0b
0b
When set, port0 is disabled and port0 clock is shut down.
When set, port1 is disabled and port1 clock is shut down.
When set, port2 is disabled and port2 clock is shut down.
When set, port3 is disabled and port3 clock is shut down.
Reserved.
19
31:20
Watch Dog Control And Status - RW - 16 bits - [PCI_Reg:44h]
Field Name
Watchdog Enable
Bits
Default
Description
Set this bit to enable the watchdog counter for all the PCI
down stream transaction.
0
0b
Watchdog Timeout
Status
1
0b
Watchdog Counter Timeout Status bit. This bit indicates that
the watchdog counter has expired for PCI down stream
transaction and the transaction got aborted due to counter has
expired.
Software writes 1 to clear the status.
Reserved
15:2
Reserved.
Watch Dog Counter - RW - 16 bits - [PCI_Reg:46h]
Field Name
Watchdog Counter
Reserved
Bits
Default
Description
Specifies the timeout retry count for PCI down stream retries.
Reserved.
7:0
80h
15:8
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
Proprietary
Page 18
MSI Control - RW- 32 bits - [PCI_Reg:50h]
Field Name
Capability ID
Bits
Default
Description
7:0
05h
Read-Only.
Capability ID. It indicates that this is and MSI capability ID.
Capability Next Pointer
15:8
70h
Read-Only.
Next Pointer (hard wired to 70h, points to Index Data pair
capability
Message Signaled
Interrupt Enable
Multiple Message
Capable
16
0b
MSI Enable.
19:17
010b
Multiple Message Capable.
Multiple Message Enable
MSI 64-bit Address
22:20
23
000b
1b
Multiple Message Enable.
Read-Only
Support 64-bit address.
Reserved
31:24
Reserved.
MSI Address - RW- 32 bits - [PCI_Reg:54h]
Field Name
Reserved
Bits
Default
Description
1:0
Reserved.
MSI Address
31:2
0000_0000h Lower 32 bits of the system specified message address
always DW aligned.
MSI Upper Address - RW- 32 bits - [PCI_Reg:58h]
Field Name
Bits
Default
Description
MSI Upper Address
31:0
0000_0000h Upper 32 bits of the system specified message address.
This register is optional and only implemented if
MC.C64=1.
MSI Data - RW- 16 bits - [PCI_Reg:5Ch]
Field Name
Bits
Default
Description
MSI Data
15:0
0000h
MSI Data
Power Management Capability ID - R- 16 bits - [PCI_Reg:60h]
Field Name
Capability ID
Bits
Default
Description
7:0
01h
Capability ID. Indicates this is power management capability
ID.
Capability Next Pointer
15:8
50h
Next Pointer.
Power Management Capability - R- 16 bits - [PCI_Reg:62h]
Field Name
Bits
Default
Description
Version
2:0
010b
Indicates support for Revision 1.1 of the PCI Power
Management Specification.
PME Clock
Reserved
Device Specific
Initialization
Aux_Current
3
4
5
0b
1b
Indicates that PCI clock is not required to generate PME#.
Reserved
Indicates whether device-specific initialization is required.
8:6
000b
Reports the maximum Suspend well current required when
in the D3COLD state. Hard wired to 000b.
The D1 state is not supported.
The D2 state is not supported.
Read-Only.
D1_Support
D2_Support
PME_Support
9
10
15:11
0b
0b
00h
©2008 Advanced Micro Devices, Inc.
SATA Registers (Device 18, Function 0)
AMD SB600 Register Reference Manual
Proprietary
Page 19
PCI Power Management Control And Status - RW- 16 bits - [PCI_Reg:64h]
Field Name
Bits
Default
Description
Power State
1:0
00b
This field is used both to determine the current power state
of the HBA and to set a new power state. The values are:
00 – D0 state
11 – D3HOT state
The D1 and D2 states are not supported. When in the
D3HOT state, the configuration space is available, but the
register memory spaces are not. Additionally, interrupts
are blocked.
Reserved
PME Enable
Reserved
7:2
8
14:9
15
Reserved
0b
0b
Read-only. Hard-wired to ‘0’ indicates PME disable
Reserved.
Read-only. Hard-wired to ‘0’ as PME disable
PME Status
Serial ATA Capability Register 0 - R- 32 bits - [PCI_Reg:70h]
Field Name
Capability ID
Bits
7:0
15:8
19:16
Default
12h
00h
0h
Description
Capability ID. Indicates this is a Serial ATA Capability ID.
Next Pointer, end of the list.
Minor revision number of the SATA Capability Pointer
implemented.
Capability Next Pointer
Minor Revision
Major Revision
Reserved
23:20
31:24
1h
Major revision number of the SATA Capability Pointer
implemented.
Reserved
Serial ATA Capability Register 1 - R- 32 bits - [PCI_Reg:74h]
Field Name
Bits
Default
Description
BAR Location
3:0
1111b
Value 1111b indicates that the Index-Data Pair is implemented
in Dwords directly following SATACR1 in the PCI configuration
space.
BAR Offset
Reserved
23:4
00000h
Indicates the offset into the BAR where the Index-Data Pair
are located in Dword granularity. Since the BAR location is
setting at 1111b, this field is not used anymore.
Reserved
31:24
IDP Index Register - RW- 32 bits - [PCI_Reg:78h]
Field Name
Reserved
Bits
Default
Description
1:0
Reserved
IDP Index
9:2
00h
This register selects the Dword offset of the memory mapped
AHCI register to be accessed. The IDP Index should be sized
such that it can access the entire ABAR register space for the
particular implementation. See Note.
Reserved
31:10
Reserved
Note: ABAR is AHCI memory map registers located at AHCI base address (BAR5) space.
IDP Data Register - RW- 32 bits - [PCI_Reg:7Ch]
Field Name
IDP Data
Bits
Default
Description
31:0
This register is a “window” through which data is read or
written to the memory mapped register pointed to by the IDP
Index register. Note that a physical register is not actually
implemented as the data is actually stored in the memory
mapped registers.
Since this is not a physical register, the “default” value is the
same as the default value of the register pointed to by IDP
Index.
All register accesses to IDP Data are Dword granularity
©2008 Advanced Micro Devices, Inc.
SATA Registers (Device 18, Function 0)
Proprietary Page 20
AMD SB600 Register Reference Manual
PHY Port0 Control - RW- 32 bits - [PCI_Reg:88h]
Field Name
Port0 PHY
TX main driver swing
Bits
23:0
4:0
Default
B40014h PHY port0 fine-tune register.
10100b Port0 Tx driving swing[4:0] is valid for SATA 1.5G. It sets the
Description
TX main driver swing. The user can program the optimum
value for each SATA port.
Bit 4
1
Bit 3
0
Bit 2
0
Bit 1
0
Bit0 Nominal Output
0
0
0
0
0
0
0
0
400mv
450mv
500mv
550mv
600mv
650mv
700mv
750mv
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Note: This applies to all the ASIC Revisions A11 and above.
Port0 Tx driving swing[7:5] is valid for both SATA 3G and
1.5G. It sets the TX pre-emphasis driver strength. The user
can program the optimum pre-emphasis value for each SATA
port if TX pre-emphasis enable bit is turned on.
TX pre-emphasis driver
swing
7:5
000b
Bit 7
0
Bit 6
0
Bit 5 pre-emphasis amount
0
1
0
1
0
1
0
1
0mv
0
0
25mv
50mv
75mv
100mv
125mv
150mv
175mv
0
1
0
1
1
0
1
0
1
1
1
1
Note: This applies to all the ASIC Revisions A11 and above.
TX pre-emphasis enable
Reserved
13
0b
Turns on TX pre-emphasis output
1: Enable pre-emphasis
0: Disable pre-emphasis
Reserved.
31:24
PHY Port1 Control - RW- 32 bits - [PCI_Reg:8Ch]
Field Name
Port1 PHY
TX main swing
Bits
23:0
4:0
Default
B40014h PHY port1 fine-tune register.
10100b Port1 Tx driving swing[4:0] is valid at SATA 1.5G. It sets the
Description
TX main driver swing. The user can program the optimum
value for each SATA port.
Bit 4
1
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0 Nominal Output
0
0
0
0
0
0
0
0
400mv
450mv
500mv
550mv
600mv
650mv
700mv
750mv
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Note: This applies to all the ASIC Revisions A11 and above.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
Proprietary
Page 21
PHY Port1 Control - RW- 32 bits - [PCI_Reg:8Ch]
Field Name
TX pre-emphasis driver
swing
Bits
Default
Description
7:5
000b
Port1 Tx driving swing[7:5] is valid for both SATA 3G and
1.5G. It sets the TX pre-emphasis driver strength. The user
can program the optimum pre-emphasis value for each SATA
port if TX pre-emphasis enable bit turned on.
Bit 7
0
Bit 6
0
Bit 5 pre-emphasis amount
0
1
0
1
0
1
0
1
0mv
0
0
25mv
50mv
75mv
100mv
125mv
150mv
175mv
0
1
0
1
1
0
1
0
1
1
1
1
Note: This applies to all the ASIC Revisions A11 and above.
Turns on port1 TX pre-emphasis output.
1: Enable pre-emphasis
TX pre-emphasis enable
13
0b
0: Disable pre-emphasis
PHY Port2 Control - RW- 32 bits - [PCI_Reg:90h]
Field Name
Port2 PHY
TX main swing
Bits
23:0
4:0
Default
B40014h PHY port2 fine-tune register.
10100b Port2 Tx driving swing[4:0] is valid at SATA 1.5G.
Description
Bit 4
1
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0 Nominal Output
0
0
0
0
0
0
0
0
400mv
450mv
500mv
550mv
600mv
650mv
700mv
750mv
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Note: This applies to all the ASIC Revisions A11 and above.
Port2 Tx driving swing[7:5] is valid for both SATA 3G and
1.5G. It sets the TX pre-emphasis driver strength. The user
can program the optimum pre-emphasis value for each SATA
port if TX pre-emphasis enable bit turned on.
TX pre-emphasis driver
swing
7:5
000b
Bit 7
0
Bit 6
0
Bit 5 pre-emphasis amount
0
1
0
1
0
1
0
1
0mv
0
0
25mv
50mv
75mv
100mv
125mv
150mv
175mv
0
1
0
1
1
0
1
0
1
1
1
1
Note: This applies to all the ASIC Revisions A11 and above.
Turns on port2 TX pre-emphasis output
1: Enable pre-emphasis
TX pre-emphasis enable
13
0b
0: Disable pre-emphasis
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
Proprietary
Page 22
PHY Port3 Control - RW- 32 bits - [PCI_Reg:94h]
Field Name
Port3 PHY
TX main swing
Bits
23:0
4:0
Default
B40014h PHY port3 fine-tune register.
10100b Port3 Tx driving swing[4:0] is valid at SATA 1.5G.
Description
Bit 4
1
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0 Nominal Output
0
0
0
0
0
0
0
0
400mv
450mv
500mv
550mv
600mv
650mv
700mv
750mv
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Note: This applies to all the ASIC Revisions A11 and above.
Port3 Tx driving swing[7:5] is valid for both SATA 3G and
1.5G. It sets the TX pre-emphasis driver strength. The user
can program the optimum pre-emphasis value for each SATA
port if TX pre-emphasis enable bit turned on.
TX pre-emphasis driver
swing
7:5
000b
Bit 7
0
Bit 6
0
Bit 5 pre-emphasis amount
0
1
0
1
0
1
0
1
0mv
0
0
25mv
50mv
75mv
100mv
125mv
150mv
175mv
0
1
0
1
1
0
1
0
1
1
1
1
Note: This applies to all the ASIC Revisions A11 and above.
Turns on port3 TX pre-emphasis output
1: Enable pre-emphasis
TX pre-emphasis enable
13
0b
0: Disable pre-emphasis
BIST Pattern Count - RW - 32 bits - [PCI_Reg:C0h]
Field Name
Bits
Default
Description
BIST Pattern Count
31:0
0000_20 This count specifies how many Octal WORD pattern need to
00h
be checked before BIST Done bit be set. This count value is
used fro all the 4 ports. 400h default value would be used for
tester, which means 32K DWORD pattern would be compared
for BIST test. Value of “0000_0000”h means the maximum
patterns (16,000, 000, 000) checked.
PCI Target Control TimeOut Counter - RW – 8 bits - [PCI_Reg:C4h]
Field Name
PCI Target Control
TimeOut Count
Bits
7:0
Default
80h
Description
This register is used for programming the PCI Target Control
TimeOut Count used to clear any stale target commands to
the hosts controller. Granularity is 15.5us (Count * 15.5 us)
The counter will be disabled if the count is programmed to 0x0.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
Proprietary
Page 23
2.1.2
BAR0/BAR2/BAR1/BAR3 Registers (SATA I/O Register for IDE mode)
BAR0/BAR2 uses 8 bytes of I/O space. BAR0 is used for Primary channel and BAR2 is used for Secondary
channel during IDE native mode. BAR1/BAR3 uses 2 bytes of I/O space. BAR1 is used for Primary channel
and BAR3 is used for Secondary channel during IDE native mode.
Address (hex)
Compatibility Mode
Name and Function
Read Function
Native Mode (Offset)
Write Function
IDE Command Block Registers
Primary
Secondary
BAR0/BAR2
1F0
170
(Primary or Secondary)
Base Address 0 + 0
(Primary or Secondary)
Base Address 0 + 1
(Primary or Secondary)
Base Address 0 + 2
(Primary or Secondary)
Base Address + 3
(Primary or Secondary)
Base Address + 4
(Primary or Secondary)
Base Address + 5
Data (16 bit)
Error register
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
Status
Data (16 bit)
Features register
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
1F1
1F2
1F3
1F4
1F5
1F6
1F7
171
172
173
174
175
176
177
(Primary or Secondary)
Base Address + 6
(Primary or Secondary)
Base Address + 7
Command
IDE Control Block Registers
Primary
Secondary
BAR1/BAR3
3F6
376
(Primary or Secondary)
Base Address + 2
Alternate Status
Device Control
2.1.3
BAR4 Registers (SATA I/O Register for IDE mode)
BAR4 uses 16 bytes of I/O space. The Bus-master interface base address register (BAR4) defines the base
address of the IO spare.
Register Name
Offset Address
[Primary/Secondary]
00h/08h
Bus-master IDE Command
Bus-master IDE Status
Descriptor Table Pointer
02h/0Ah
04h/0Ch
Bus-master IDE Command - RW- 8 bits - [IO_Reg: BAR4 + 00/08h]
Field Name
Bus Master IDE
Start/Stop
Bits
Default
Description
0
0b
Bus Master IDE Start (1)/Stop (0).
This bit will not be reset by interrupt from IDE device. This must
be reset by soft ware (device driver).
Reserved.
Bus Master IDE r/w (direction) control
0 = Memory -> IDE
Reserved
2:1
3
Bus Master Read/Write
0b
1 = IDE -> Memory
This bit should not change during Bus Master transfer cycle, even
if terminated by Bus Master IDE stop.
Reserved.
Reserved
7:4
©2008 Advanced Micro Devices, Inc.
SATA Registers (Device 18, Function 0)
AMD SB600 Register Reference Manual
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Page 24
Bus-master IDE Status - RW- 8 bits - [IO_Reg: BAR4 + 02/0Ah]
Field Name
Bits
Default
Description
Bus Master Active
0
0b
Bus Master IDE active. This bit is set to 1 when bit 0 in the Bus
Master IDE command address register is set to 1. The IDE host
controller sets this bit to 0 when the last transfer for a region is
performed. This bit is also set to 0 when bit 0 of the Bus Master
IDE command register is set to 0.
Bus Master DMA Error
IDE Interrupt
1
2
0b
0b
IDE DMA error. This bit is set when the IDE host controller
encounters a target abort, master abort, or Parity error while
transferring data on the PCI bus. Write ‘1’ clears this bit
IDE Interrupt. Indicates when an IDE device has asserted its
interrupt line. IRQ14 is used for the Primary channel and IRQ15 is
used for the secondary channel. If the interrupt status bit is set to
0, by writing a 1 to this bit while the interrupt line is still at the
active level, this bit remains 0 until another assertion edge is
detected on the interrupt line.
Reserved
Master Device DMA
Capable
Slave Device DMA
Capable
Simplex Only
4:3
5
Reserved.
Device 0 (Master) DMA capable.
0b
0b
0b
6
7
Device 1 (Slave) DMA capable.
Read Only
Simplex only. This bit is hard-wired as 0.
Descriptor Table Pointer - RW- 32 bits - [IO_Reg: BAR4 + 04/0Ch]
Field Name
Reserved
Bits
Default
Description
1:0
0h
Reserved. Always read as 0’s.
Descriptor Table Base
Address
31:2
0000_0000h Base Address of Descriptor Table. These bits correspond to
Address [31-02].
2.1.4
BAR5 Registers
These are the AHCI memory map registers. The base address is defined through the ABAR (BAR5) register.
Register Name
Generic Host Control
Offset Address
00h-23h
Reserved
24h-9Fh
Vendor Specific registers
Port 0 port control registers
Port 1 port control registers
Port 2 port control registers
Port 3 port control registers
A0h-FFh
100h-17Fh
180h-1FFh
200h-27Fh
280h-2FFh
2.1.4.1 Generic Host Control
The following registers apply to the entire HBA.
Register Name
Host Capabilities(CAP)
Global Host Control(GHC)
Interrupt Status(IS)
Ports Implemented(PI)
Offset Address
00h-03h
04h-07h
08h-0Bh
0Ch-0Fh
10h-13h
14h-17h
18h-1Bh
1Ch-1Fh
20h-23h
Version(VS)
Command Completion Coalescing Control(CCC_CTL)
Command Completion Coalescing Ports(CCC_PORTS)
Enclosure Management Location(EM_LOC)
Enclosure Management Control(EM_CTL)
©2008 Advanced Micro Devices, Inc.
SATA Registers (Device 18, Function 0)
Proprietary Page 25
AMD SB600 Register Reference Manual
HBA Capabilities – R - 32bits [Mem_reg: ABAR + 00h]
Field Name
Bits
Default
Description
Number of Ports(NP)
4:0
00011b
0’s based value indicating the maximum number of ports
supported by the HBA silicon. A maximum of 32 ports can be
supported. A value of ‘0h’, indicating one port, is the
minimum requirement. Note that the number of ports
indicated in this field may be more than the number of ports
indicated in the GHC.PI register.
Supports External SATA
(SXS)
5
0b
When set to ‘1’, indicates that the HBA has one or more
Serial ATA ports that has a signal only connector that is
externally accessible. If this bit is set to ‘1’, software may
refer to the PxCMD.ESP bit to determine whether a specific
port has its signal connector externally accessible as a signal
only connector (i.e. power is not part of that connector).
When the bit is cleared to ‘0’, indicates that the HBA has no
Serial ATA ports that have a signal only connector externally
accessible.
Enclosure Management
Supported (EMS)
6
7
0b
1b
When set to ‘1’, indicates that the HBA supports enclosure
management. When enclosure management is supported,
the HBA has implemented the EM_LOC and EM_CTL global
HBA registers. When cleared to ‘0’, indicates that the HBA
does not support enclosure management and the EM_LOC
and EM_CTL global HBA registers are not implemented.
When set to ‘1’, indicates that the HBA supports command
completion coalescing. When command completion
coalescing is supported, the HBA has implemented the
CCC_CTL and the CCC_PORTS global HBA registers.
When cleared to ‘0’, indicates that the HBA does not support
command completion coalescing and the CCC_CTL and
CCC_PORTS global HBA registers are not implemented.
0’s based value indicating the number of command slots per
port supported by this HBA. A minimum of 1 and maximum
of 32 slots per port can be supported. The same number of
command slots is available on each implemented port.
Indicates whether the HBA can support transitions to the
Partial state. When cleared to ‘0’, software must not allow
the HBA to initiate transitions to the Partial state via
aggressive link power management nor the PxCMD.ICC field
in each port, and the PxSCTL.IPM field in each port must be
programmed to disallow device initiated Partial requests.
When set to ‘1’, HBA and device initiated Partial requests can
be supported.
Command Completion
Coalescing Supported
(CCCS)
Number of Command
Slots (NCS)
12:8
11111b
1b
Partial State Capable
(PSC)
13
Slumber State Capable
(SSC)
14
1b
Indicates whether the HBA can support transitions to the
Slumber state. When cleared to ‘0’, software must not allow
the HBA to initiate transitions to the Slumber state via
aggressive link power management nor the PxCMD.ICC field
in each port, and the PxSCTL.IPM field in each port must be
programmed to disallow device initiated Slumber requests.
When set to ‘1’, HBA and device initiated Slumber requests
can be supported.
PIO Multiple DRQ Block
(PMD)
15
16
1b
0b
If set to ‘1’, the HBA supports multiple DRQ block data
transfers for the PIO command protocol. If cleared to ‘0’ the
HBA only supports single DRQ block data transfers for the
PIO command protocol.
When set to ‘1’, indicates that the HBA supports Port
Multiplier FIS-based switching. When cleared to ‘0’, indicates
that the HBA does not support FIS-based switching. AHCI
1.0 and 1.1 HBAs shall have this bit cleared to ‘0’.
FIS-based Switching
Supported (FBSS)
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
Proprietary
Page 26
HBA Capabilities – R - 32bits [Mem_reg: ABAR + 00h]
Field Name
Supports Port Multiplier
(SPM)
Bits
Default
Description
17
1b
Indicates whether the HBA can support a Port Multiplier.
When set, a Port Multiplier using command-based switching
is supported. When cleared to ‘0’, a Port Multiplier is not
supported, and a Port Multiplier may not be attached to this
HBA.
Supports AHCI mode
only (SAM)
18
0b
The SATA controller may optionally support AHCI access
mechanisms only. A value of '0' indicates that in addition to
the native AHCI mechanism (via ABAR), the SATA controller
implements a legacy, task-file based register interface such
as SFF-8038i. A value of '1' indicates that the SATA
controller does not implement a legacy, task-file based
register interface.
Supports Non-Zero DMA
Offsets (SNZO)
19
0b
2h
When set to ‘1’, indicates that the HBA can support non-zero
DMA offsets for DMA Setup FISes. This bit is reserved for
future AHCI enhancements. AHCI 1.0 and 1.1 HBAs shall
have this bit cleared to ‘0’.
Interface Speed Support
(ISS)
23:20
Indicates the maximum speed the HBA can support on its
ports. These encodings match the system software
programmable PxSCTL.DET.SPD field. Values are:
Bits
0000
0001
Definition
Reserved
Gen 1 (1.5 Gbps)
Gen 1 (1.5 Gbps) and Gen 2 (3
Gbps)
0010
0011 - 1111
Reserved
Supports Command List
Override (SCLO)
24
1b
When set to ‘1’, the HBA supports the PxCMD.CLO bit and its
associated function. When cleared to ‘0’, the HBA is not
capable of clearing the BSY and DRQ bits in the Status
register in order to issue a software reset if these bits are still
set from a previous operation.
Supports Activity LED
(SAL)
25
26
1b
1b
When set to ‘1’, the HBA supports a single activity indication
output pin. This pin can be connected to an LED on the
platform to indicate device activity on any drive. When
cleared to ‘0’, this function is not supported.
When set to ‘1’, the HBA can support auto-generating link
requests to the Partial or Slumber states when there are no
commands to process. When cleared to ‘0’, this function is
not supported and software shall treat the PxCMD.ALPE and
PxCMD.ASP bits as reserved.
Supports Aggressive
Link Power Management
(SALP)
Supports Staggered
Spin-up (SSS)
27
28
29
0b
1b
1b
When set to ‘1’, the HBA supports staggered spin-up on its
ports, for use in balancing power spikes. When cleared to ‘0’,
this function is not supported. This value is loaded by the
BIOS prior to OS initialization.
When set to ‘1’, the HBA supports mechanical presence
switches on its ports for use in hot plug operations. When
cleared to ‘0’, this function is not supported. This value is
loaded by the BIOS prior to OS initialization.
When set to ‘1’, the HBA supports the PxSNTF
(SNotification) register and its associated functionality.
When cleared to ‘0’, the HBA does not support the
PxSNTF (SNotification) register and its associated
functionality.
Supports Mechanical
Presence Switch (SMPS)
Supports SNotification
Register (SSNTF)
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
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Page 27
HBA Capabilities – R - 32bits [Mem_reg: ABAR + 00h]
Field Name
Supports Native
Command Queuing
(SNCQ)
Bits
Default
Description
30
1b
Indicates whether the HBA supports Serial ATA native
command queuing. If set to ‘1’, an HBA shall handle DMA
Setup FISes natively, and shall handle the auto-activate
optimization through that FIS. If cleared to ‘0’, native
command queuing is not supported and software should not
issue any native command queuing commands.
Indicates whether the HBA can access 64-bit data structures.
When set to ‘1’, the HBA shall make the 32-bit upper bits of
the port DMA Descriptor, the PRD Base, and each PRD entry
read/write. When cleared to ‘0’, these are read-only and
treated as ‘0’ by the HBA.
Supports 64-bit
Addressing (S64A)
31
1b
Global HBA Control – RW - 32bits [Mem_reg: ABAR + 04h]
Field Name
Bits
Default
Description
HBA Reset (HR)
0
0b
When set by SW, this bit causes an internal reset of the HBA.
All state machines that relate to data transfers and queuing
shall return to an idle condition, and all ports shall be re-
initialized via COMRESET (if staggered spin-up is not
supported). If staggered spin-up is supported, then it is the
responsibility of software to spin-up each port after the reset
has completed.
When the HBA has performed the reset action, it shall reset
this bit to ‘0’. A software write of ‘0’ shall have no effect. For
a description on which bits are reset when this bit is set.
This global bit enables interrupts from the HBA. When
cleared (reset default), all interrupt sources from all ports are
disabled. When set, interrupts are enabled.
Interrupt Enable (IE)
1
2
0b
0b
MSI Revert to Single
Message (MRSM)
Read Only
When set to ‘1’ by hardware, indicates that the HBA
requested more than one MSI vector but has reverted to
using the first vector only. When this bit is cleared to ‘0’, the
HBA has not reverted to single MSI mode (i.e. hardware is
already in single MSI mode, software has allocated the
number of messages requested, or hardware is sharing
interrupt vectors if MC.MME < MC.MMC).
The HBA may revert to single MSI mode when the number of
vectors allocated by the host is less than the number
requested. This bit shall only be set to ‘1’ when the following
conditions hold:
•
•
•
•
MC.MSIE = ‘1’ (MSI is enabled)
MC.MMC > 0 (multiple messages requested)
MC.MME > 0 (more than one message allocated)
MC.MME != MC.MMC (messages allocated not
equal to number requested)
When this bit is set to ‘1’, single MSI mode operation is in use
and software is responsible for clearing bits in the IS register
to clear interrupts.
This bit shall be cleared to ‘0’ by hardware when any of the
four conditions stated is false. This bit is also cleared to ‘0’
when MC.MSIE = ‘1’ and MC.MME = 0h. In this case, the
hardware has been programmed to use single MSI mode,
and is not “reverting” to that mode.
Reserved
30:3
Reserved.
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AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
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Page 28
Global HBA Control – RW - 32bits [Mem_reg: ABAR + 04h]
Field Name
Bits
Default
Description
AHCI Enable (AE)
31
0b
When set, indicates that communication to the HBA shall be
via AHCI mechanisms. This can be used by an HBA that
supports both legacy mechanisms (such as SFF-8038i) and
AHCI to know when the HBA is running under an AHCI
driver.
When set, software shall only communicate with the HBA
using AHCI. When cleared, software shall only communicate
with the HBA using legacy mechanisms. When cleared
FISes are not posted to memory and no commands are sent
via AHCI mechanisms.
Software shall set this bit to ‘1’ before accessing other AHCI
registers.
Interrupt Status - RW -32 bits [Mem_reg: ABAR + 08h]
Field Name
Interrupt Pending Status
(IPS)
Bits
Default
0000_
0000h
Description
31:0
If set, indicates that the corresponding port has an interrupt
pending. Software can use this information to determine
which ports require service after an interrupt.
The IPS[x] bit is only defined for ports that are implemented
or for the command completion coalescing interrupt defined
by CCC_CTL.INT. All other bits are reserved.
Write 1 to clear these status bits.
Ports Implemented Register - R -32 bits [Mem_reg: ABAR + 0Ch]
Field Name
Bits
Default
Description
Port Implemented (PI)
31:0
0000000Fh
This register is bit significant. If a bit is set to ‘1’, the
corresponding port is available for software to use. If a bit is
cleared to ‘0’, the port is not available for software to use.
The maximum number of bits set to ‘1’ shall not exceed
CAP.NP + 1, although the number of bits set in this register
may be fewer than CAP.NP + 1. At least one bit shall be set
to ‘1’.
AHCI Version- R – 32 bits [Mem_reg: ABAR + 10h]
Field Name
Minor Version Number
(MNR)
Bits
Default
Description
15:0
0100h
Indicates the minor version is “10”.
Major Version Number
(MJR)
31:16
0001h
Indicates the major version is “1”
Version: V1.10
Command Completion Coalescing Control(CCC_CTL) - RW – 32 bits [Mem_reg: ABAR + 14h]
Field Name
Bits
Default
Description
CCC_CTL Enable
0
0b
When cleared to ‘0’, the command completion coalescing
feature is disabled and no CCC interrupts are generated.
When set to ‘1’, the command completion coalescing feature
is enabled and CCC interrupts may be generated based on
timeout or command completion conditions. Software shall
only change the contents of the TV and CC fields when EN is
cleared to ‘0’. On transition of this bit from ‘0’ to ‘1’, any
updated values for the TV and CC fields shall take effect.
Reserved
Reserved
2:1
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SATA Registers (Device 18, Function 0)
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Page 29
Command Completion Coalescing Control(CCC_CTL) - RW – 32 bits [Mem_reg: ABAR + 14h]
Field Name
Bits
Default
Description
CCC Interrupt (INT)
7:3
1Fh
Read Only
Specifies the interrupt used by the CCC feature. This
interrupt must be marked as unused in the Ports
Implemented (PI) register by the corresponding bit being set
to ‘0’. Thus, the CCC interrupt corresponds to the interrupt
for an unimplemented port on the controller. When a CCC
interrupt occurs, the IS.IPS[INT] bit shall be asserted to ‘1’.
This field also specifies the interrupt vector used for MSI.
Specifies the number of command completions that are
necessary to cause a CCC interrupt. The HBA has an
internal command completion counter, hCccComplete.
hCccComplete is incremented by one each time a selected
port has a command completion. When hCccComplete is
equal to the command completions value, a CCC interrupt is
signaled. The internal command completion counter is reset
to ‘0’ on the assertion of each CCC interrupt. A value of ‘0’
for this field shall disable CCC interrupts being generated
based on the number of commands completed, i.e. CCC
interrupts are only generated based on the timer in this case.
The timeout value is specified in 1 millisecond intervals. The
timer accuracy shall be within 5%. hCccTimer is loaded with
this timeout value. The hCccTimer is only decremented when
commands are outstanding on selected ports. The HBA will
signal a CCC interrupt when hCccTimer has decremented to
‘0’. The hCccTimer is reset to the timeout value on the
assertion of each CCC interrupt. A timeout value of ‘0’ is
reserved.
Command Completions
(CC)
15:8
01h
Timeout Value (TV)
31:16
0001h
Command Completion Coalescing Ports - RW – 32 bits [Mem_reg: ABAR + 18h]
Field Name
Bits
Default
Description
Ports (PRT)
31:0
00000000h
This register is bit significant. Each bit corresponds to a
particular port, where bit 0 corresponds to port 0. If a bit is
set to ‘1’, the corresponding port is part of the command
completion coalescing feature. If a bit is cleared to ‘0’, the
port is not part of the command completion coalescing
feature. Bits set to ‘1’ in this register must also have the
corresponding bit set to ‘1’ in the Ports Implemented register.
An updated value for this field shall take effect within one
timer increment (1 millisecond).
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
Proprietary
Page 30
2.1.4.2 Port Registers (One Set Per Port)
The algorithm for the software to determine the offset is as follows:
•
Port offset = 100h + (PI Asserted Bit Position * 80h)
Register Name
Port-N Command List Base Address(PNCLB)
Port-N Command List Base Address Upper 32-
Bits(PNCLBU)
Offset Address
00h-03h + Port offset
04h-07h + Port offset
Port-N FIS Base Address(PNFB)
08h-0Bh + Port offset
0Ch-0Fh + Port offset
10h-13h + Port offset
14h-17h + Port offset
18h-1Bh + Port offset
1Ch-1Fh + Port offset
20h-23h + Port offset
24h-27h + Port offset
28h-2Bh + Port offset
2Ch-2Fh + Port offset
30h-33h + Port offset
34h-37h + Port offset
38h-3Bh + Port offset
3Ch-3Fh + Port offset
40h-43h + Port offset
44h-6Fh + Port offset
70h-7Fh + Port offset
Port-N FIS Base Address Upper 32-Bits(PNFBU)
Port-N Interrupt Status(PNIS)
Port-N Interrupt Enable(PNIE)
Port-N Command and Status(PNCMD)
Reserved
Port-N Task File Data(PNTFD)
Port-N Signature(PNSIG)
Port-N Serial ATA Status (PNSSTS)
Port-N Serial ATA Control (PNSCTL)
Port-N Serial ATA Error (PNSERR)
Port-N Serial ATA Active (PNSACT)
Port-N Command Issue(PNCI)
Port-N SNotification (PNSNTF)
Reserved for FIS-based Switching Definition
Reserved
Port-N Vendor Specific(PNVS)
*N is the port number, 0 ~ 3
Port-N Command List Base Address -RW -32 bits [Mem_reg: ABAR + port offset + 00h]
Field Name
Bits
Default
Description
Reserved
9:0
Reserved.
Command List Base
Address (CLB)
31:10
000000h
Indicates the 32-bit base physical address for the command
list for this port. This base is used when fetching commands
to execute. The structure pointed to by this address range is
1K-bytes in length. This address must be 1K-byte aligned as
indicated by bits 09:00 being read only.
Port-N Command List Base Upper Address -RW - 32 bits [Mem_reg: ABAR + port offset + 04h]
Field Name
Bits
Default
Description
Command List Base
Address Upper (CLBU)
31:0
00000000h
Indicates the upper 32-bits for the command list base
physical address for this port. This base is used when
fetching commands to execute.
This register shall be read only ‘0’ for HBAs that do not
support 64-bit addressing.
Port–N FIS Base Address -RW -32 bits [Mem_reg: ABAR + port offset + 08h]
Field Name
Reserved
FIS Base Address (FB)
Bits
7:0
31:8
Default
Description
Reserved.
000000h
Indicates the 32-bit base physical address for received FISes.
The structure pointed to by this address range is 256 bytes in
length. This address must be 256-byte aligned as indicated
by bits 07:00 being read only.
©2008 Advanced Micro Devices, Inc.
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SATA Registers (Device 18, Function 0)
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Page 31
Port-N FIS Base Address Upper –RW – 32 bits [Mem_reg: ABAR + port offset + 0Ch]
Field Name
FIS Base Address Upper
(FBU)
Bits
31:0
Default
0000_
0000h
Description
Indicates the upper 32-bits for the received FIS base physical
address for this port.
This register shall be read only ‘0’ for HBAs that do not
support 64-bit addressing.
Port–N Interrupt Status - RW - 32 bits [Mem_reg: ABAR + port offset + 10h]
Field Name
Device to Host Register
FIS Interrupt (DHRS)
PIO Setup FIS Interrupt
(PSS)
Bits
0
Default
Description
0b
A D2H Register FIS has been received with the ‘I’ bit set, and
has been copied into system memory.
A PIO Setup FIS has been received with the ‘I’ bit set, it has
been copied into system memory, and the data related to that
FIS has been transferred. This bit shall be set even if the
data transfer resulted in an error.
1
0b
DMA Setup FIS Interrupt
(DSS)
Set Device Bits Interrupt
(SDBS)
Unknown FIS Interrupt
(UFS)
2
3
4
0b
0b
0b
A DMA Setup FIS has been received with the ‘I’ bit set and
has been copied into system memory.
A Set Device Bits FIS has been received with the ‘I’ bit set
and has been copied into system memory.
Read Only
When set to ‘1’, indicates that an unknown FIS was received
and has been copied into system memory. This bit is cleared
to ‘0’ by software clearing the PxSERR.DIAG.F bit to ‘0’.
Note that this bit does not directly reflect the PxSERR.DIAG.F
bit. PxSERR.DIAG.F is set immediately when an unknown
FIS is detected, whereas this bit is set when that FIS is
posted to memory. Software should wait to act on an
unknown FIS until this bit is set to ‘1’ or the two bits may
become out of sync.
Descriptor Processed
(DPS)
Port Connect Change
Status (PCS)
5
6
0b
0b
A PRD with the ‘I’ bit set has transferred all of its data.
Read Only
1=Change in Current Connect Status. 0=No change in
Current Connect Status. This bit reflects the state of
PxSERR.DIAG.X. This bit is only cleared when
PxSERR.DIAG.X is cleared.
Device Mechanical
Presence Status (DMPS)
7
0b
When set, indicates that a mechanical presence switch
attached to this port has been opened or closed, which may
lead to a change in the connection state of the device. This
bit is only valid if both CAP.SMPS and P0CMD.MPSP are set
to ‘1’.
Reserved
PhyRdy Change Status
(PRCS)
21:8
22
Reserved
Read Only
0b
0b
When set to ‘1’ indicates the internal PhyRdy signal changed
state. This bit reflects the state of P0SERR.DIAG.N. To
clear this bit, software must clear P0SERR.DIAG.N to ‘0’.
Indicates that the HBA received a FIS from a device whose
Port Multiplier field did not match what was expected. The
IPMS bit may be set during enumeration of devices on a Port
Multiplier due to the normal Port Multiplier enumeration
process. It is recommended that IPMS only be used after
enumeration is complete on the Port Multiplier.
Indicates that the HBA received more bytes from a device
than was specified in the PRD table for the command.
Reserved
Incorrect Port Multiplier
Status (IPMS)
23
24
Overflow Status (OFS)
0b
Reserved
Interface Non-fatal Error
Status (INFS)
Interface Fatal Error
Status (IFS)
25
26
0b
0b
Indicates that the HBA encountered an error on the Serial
ATA interface but was able to continue operation.
Indicates that the HBA encountered an error on the Serial
ATA interface which caused the transfer to stop.
27
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
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Page 32
Port–N Interrupt Status - RW - 32 bits [Mem_reg: ABAR + port offset + 10h]
Field Name
Host Bus Data Error
Status (HBDS)
Bits
28
Default
Description
0b
Indicates that the HBA encountered a data error
(uncorrectable ECC / parity) when reading from or writing to
system memory.
Host Bus Fatal Error
Status (HBFS)
29
0b
Indicates that the HBA encountered a host bus error that it
cannot recover from, such as a bad software pointer. In PCI,
such an indication would be a target or master abort.
This bit is set whenever the status register is updated by the
device and the error bit (bit 0) is set.
When set, a device status has changed as detected by the
cold presence detect logic. This bit can either be set due to a
non-connected port receiving a device, or a connected port
having its device removed. This bit is only valid if the port
supports cold presence detect as indicated by PxCMD.CPD
set to ‘1’.
Task File Error Status
(TFES)
Cold Port Detect Status
(CPDS)
30
31
0b
0b
Write 1 to clear these status bits.
Port-N Interrupt Enable - RW -32 bits [Mem_reg: ABAR + port offset + 14h]
Field Name
Device to Host Register
FIS Interrupt Enable
(DHRE)
Bits
0
Default
Description
When set, GHC.IE is set, and P0IS.DHRS is set, the HBA
shall generate an interrupt.
0b
PIO Setup FIS Interrupt
Enable (PSE)
DMA Setup FIS Interrupt
Enable (DSE)
Set Device Bits FIS
Interrupt Enable (SDBE)
Unknown FIS Interrupt
Enable (UFE)
Descriptor Processed
Interrupt Enable (DPE)
Port Change Interrupt
Enable (PCE)
1
2
3
4
5
6
7
0b
0b
0b
0b
0b
0b
0b
When set, GHC.IE is set, and P0IS.PSS is set, the HBA shall
generate an interrupt.
When set, GHC.IE is set, and P0IS.DSS is set, the HBA shall
generate an interrupt.
When set, GHC.IE is set, and P0IS.SDBS is set, the HBA
shall generate an interrupt.
When set, GHC.IE is set, and P0IS.UFS is set to ‘1’, the HBA
shall generate an interrupt.
When set, GHC.IE is set, and P0IS.DPS is set, the HBA shall
generate an interrupt.
When set, GHC.IE is set, and P0IS.PCS is set, the HBA shall
generate an interrupt.
Device Mechanical
Presence Enable
(DMPE)
When set, and GHC.IE is set to ‘1’, and P0IS.DMPS is set,
the HBA shall generate an interrupt.
For systems that do not support a mechanical presence
switch, this bit shall be a read-only ‘0’.
Reserved
When set to ‘1’, and GHC.IE is set to ‘1’, and P0IS.PRCS is
set to ‘1’, the HBA shall generate an interrupt.
When set, and GHC.IE and P0IS.IPMS are set, the HBA shall
generate an interrupt.
Reserved
PhyRdy Change Interrupt
Enable (PRCE)
Incorrect Port Multiplier
Enable (IPME)
Overflow Enable (OFE)
21:8
22
0b
0b
0b
23
24
When set, and GHC.IE and P0IS.OFS are set, the HBA shall
generate an interrupt.
Reserved
Interface Non-fatal Error
Enable (INFE)
Interface Fatal Error
Enable (IFE)
Host Bus Data Error
Enable (HBDE)
Host Bus Fatal Error
Enable (HBFE)
Task File Error Enable
(TFEE)
25
26
Reserved
0b
0b
0b
0b
0b
When set, GHC.IE is set, and P0IS.INFS is set, the HBA shall
generate an interrupt.
When set, GHC.IE is set, and P0IS.IFS is set, the HBA shall
generate an interrupt.
When set, GHC.IE is set, and P0IS.HBDS is set, the HBA
shall generate an interrupt.
When set, GHC.IE is set, and P0IS.HBFS is set, the HBA
shall generate an interrupt.
27
28
29
30
When set, GHC.IE is set, and P0S.TFES is set, the HBA shall
generate an interrupt.
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AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
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Page 33
Port-N Interrupt Enable - RW -32 bits [Mem_reg: ABAR + port offset + 14h]
Field Name
Cold Presence Detect
Enable (CPDE)
Bits
31
Default
Description
0b
When set, GHC.IE is set, and P0S.CPDS is set, the HBA
shall generate an interrupt.
For systems that do not support cold presence detect, this bit
shall be a read-only ‘0’.
Port-N Command and Status - R - 32 bits [Mem_reg: ABAR + port offset + 18h]
Field Name
Bits
Default
Description
Start (ST)
0
0b
RW
When set, the HBA may process the command list. When
cleared, the HBA may not process the command list.
Whenever this bit is changed from a ‘0’ to a ‘1’, the HBA
starts processing the command list at entry ‘0’. Whenever
this bit is changed from a ‘1’ to a ‘0’, the PxCI register is
cleared by the HBA upon the HBA putting the controller into
an idle state. This bit shall only be set to ‘1’ by software after
PxCMD.FRE has been set to ‘1’.
Spin-Up Device (SUD)
Power On Device (POD)
1
1b
This bit is read/write for HBAs that support staggered spin-up
via CAP.SSS. This bit is read only ‘1’ for HBAs that do not
support staggered spin-up. On an edge detect from ‘0’ to ‘1’,
the HBA shall start a COMRESET initialization sequence to
the device. Clearing this bit to ‘0’ does not cause any OOB
signal to be sent on the interface. When this bit is cleared to
‘0’ and PxSCTL.DET=0h, the HBA will enter listen mode.
This bit is read/write for HBAs that support cold presence
detection on this port as indicated by PxCMD.CPD set to ‘1’.
This bit is read only ‘1’ for HBAs that do not support cold
presence detect. When set, the HBA sets the state of a pin
on the HBA to ‘1’ so that it may be used to provide power to a
cold-presence detectable port.
2
3
1b
0b
Command List Override
(CLO)
RW
Setting this bit to ‘1’ causes PxTFD.STS.BSY and
PxTFD.STS.DRQ to be cleared to ‘0’. This allows a software
reset to be transmitted to the device regardless of whether
the BSY and DRQ bits are still set in the PxTFD.STS register.
The HBA sets this bit to ‘0’ when PxTFD.STS.BSY and
PxTFD.STS.DRQ have been cleared to ‘0’. A write to this
register with a value of ‘0’ shall have no effect.
This bit shall only be set to ‘1’ immediately prior to setting the
PxCMD.ST bit to ‘1’ from a previous value of ‘0’. Setting this
bit to ‘1’ at any other time is not supported and will result in
indeterminate behavior. Software must wait for CLO to be
cleared to ‘0’ before setting PxCMD.ST to ‘1’.
FIS Receive Enable
(FRE)
4
0b
RW
When set, the HBA may post received FISes into the FIS
receive area pointed to by PxFB (and for 64-bit HBAs,
PxFBU). When cleared, received FISes are not accepted by
the HBA, except for the first D2H register FIS after the
initialization sequence, and no FISes are posted to the FIS
receive area.
System software must not set this bit until PxFB (PxFBU)
have been programmed with a valid pointer to the FIS receive
area, and if software wishes to move the base, this bit must
first be cleared, and software must wait for the FR bit in this
register to be cleared
Reserved
7:5
Reserved
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AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
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Page 34
Port-N Command and Status - R - 32 bits [Mem_reg: ABAR + port offset + 18h]
Field Name
Current Command Slot
(CCS)
Bits
12:8
Default
00h
Description
This field is valid when P0CMD.ST is set to ‘1’ and shall be
set to the command slot value of the command that is
currently being issued by the HBA. When P0CMD.ST
transitions from ‘1’ to ‘0’, this field shall be reset to ‘0’. After
P0CMD.ST transitions from ‘0’ to ‘1’, the highest priority slot
to issue from next is command slot 0. After the first
command has been issued, the highest priority slot to issue
from next is P0CMD.CCS + 1. For example, after the HBA
has issued its first command, if CCS = 0h and P0CI is set to
3h, the next command that will be issued is from command
slot 1.
Mechanical Presence
Switch State (MPSS)
13
1b
The MPSS bit reports the state of a mechanical presence
switch attached to this port. If CAP.SMPS is set to ‘1’ and the
mechanical presence switch is closed then this bit is cleared
to ‘0’. If CAP.SMPS is set to ‘1’ and the mechanical presence
switch is open then this bit is set to ‘1’. If CAP.SMPS is set to
‘0’ then this bit is cleared to ‘0’. Software should only use this
bit if both CAP.SMPS and P0CMD.MPSP are set to ‘1’.
When set, the FIS Receive DMA engine for the port is
running.
When this bit is set, the command list DMA engine for the
port is running. See the AHCI state machine in section.
The CPS bit reports whether a device is currently detected on
this port via cold presence detection. If CPS is set to ‘1’, then
the HBA detects via cold presence that a device is attached
to this port. If CPS is cleared to ‘0’ , then the HBA detects via
cold presence that there is no device attached to this port.
RW
This bit is read/write for HBAs that support a Port Multiplier
(CAP.SPM = ‘1’). This bit is read-only for HBAs that do not
support a port Multiplier (CAP.SPM = ‘0’). When set to ‘1’ by
software, a Port Multiplier is attached to the HBA for this port.
When cleared to ‘0’ by software, a Port Multiplier is not
attached to the HBA for this port. Software is responsible for
detecting whether a Port Multiplier is present; hardware does
not auto-detect the presence of a Port Multiplier.
When set to ‘1’, indicates that this port’s signal and power
connectors are externally accessible via a joint signal and
power connector for blindmate device hot plug. When
cleared to ‘0’, indicates that this port’s signal and power
connectors are not externally accessible via a joint signal and
power connector.
FIS Receive Running
(FR)
Command List Running
(CR)
Cold Presence State
(CPS)
14
15
16
0b
0b
0b
Port Multiplier Attached
(PMA)
17
0b
Hot Plug Capable Port
(HPCP)
18
19
1b
0b
Mechanical Presence
Switch Attached to Port
(MPSP)
If set to ‘1’, the platform supports an mechanical presence
switch attached to this port. If cleared to ‘0’, the platform
does not support a mechanical presence switch attached to
this port. When this bit is set to ‘1’, P0CMD.HPCP should
also be set to ‘1’.
Cold Presence Detection
(CPD)
20
21
0b
0b
If set to ‘1’, the platform supports cold presence detection on
this port. If cleared to ‘0’, the platform does not support cold
presence detection on this port. When this bit is set to ‘1’,
P0CMD.HPCP should also be set to ‘1’.
When set to '1', indicates that this port’s signal connector is
externally accessible on a signal only connector. When set to
'1', CAP.SXS shall be set to '1'. When cleared to ‘0’, indicates
that this port’s signal connector is not externally accessible
on a signal only connector. ESP is mutually exclusive with
the HPCP bit in this register.
External SATA Port
(ESP)
Reserved
23:22
Reserved
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
Proprietary
Page 35
Port-N Command and Status - R - 32 bits [Mem_reg: ABAR + port offset + 18h]
Field Name
Bits
Default
Description
Device is ATAPI (ATAPI)
24
0b
RW
When set to ‘1’, the connected device is an ATAPI device.
This bit is used by the HBA to control whether or not to
generate the desktop LED when commands are active.
RW
When set to ‘1’, the HBA shall drive the LED pin active for
commands regardless of the state of P0CMD.ATAPI. When
cleared, the HBA shall only drive the LED pin active for
commands if P0CMD.ATAPI set to ‘0’.
Drive LED on ATAPI
Enable (DLAE)
25
26
0b
0b
Aggressive Link Power
Management Enable
(ALPE)
RW
When set to ‘1’, the HBA shall aggressively enter a lower link
power state (Partial or Slumber) based upon the setting of the
ASP bit. Software shall only set this bit to ‘1’ if CAP.SALP is
set to ‘1’; if CAP.SALP is cleared to ‘0’ software shall treat
this bit as reserved.
Aggressive Slumber /
Partial (ASP)
27
0b
RW
When set to ‘1’, and ALPE is set, the HBA shall aggressively
enter the Slumber state when it clears the PxCI register and
the PxSACT register is cleared or when it clears the PxSACT
register and PxCI is cleared. When cleared, and ALPE is set,
the HBA shall aggressively enter the Partial state when it
clears the PxCI register and the PxSACT register is cleared
or when it clears the PxSACT register and PxCI is cleared. If
CAP.SALP is cleared to ‘0’ software shall treat this bit as
reserved.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
Proprietary
Page 36
Port-N Command and Status - R - 32 bits [Mem_reg: ABAR + port offset + 18h]
Field Name
Interface Communication
Control (ICC)
Bits
31:28
Default
Description
0h
RW
This field is used to control power management states of the
interface. If the Link layer is currently in the L_IDLE state,
writes to this field shall cause the HBA to initiate a transition
to the interface power management state requested. If the
Link layer is not currently in the L_IDLE state, writes to this
field shall have no effect.
Value
Fh - 7h Reserved
6h
Slumber: This shall cause the HBA to
Definition
request a transition of the interface to the
Slumber state. The SATA device may
reject the request and the interface shall
remain in its current state.
5h - 3h Reserved
2h
Partial: This shall cause the HBA to
request a transition of the interface to the
Partial state. The SATA device may reject
the request and the interface shall remain
in its current state.
1h
0h
Active: This shall cause the HBA to
request a transition of the interface into the
active state.
No-Op / Idle: When software reads this
value, it indicates the HBA is ready to
accept a new interface control command,
although the transition to the previously
selected state may not yet have occurred.
When the system software writes a non-reserved value other
than No-Op (0h), the HBA shall perform the action and
update this field back to Idle (0h).
If software writes to this field to change the state to a state
the link is already in (i.e. interface is in the active state and a
request is made to go to the active state), the HBA shall take
no action and return this field to Idle. If the interface is in a
low power state and software wants to transition to a different
low power state, software must first bring the link to active
and then initiate the transition to the desired low power state.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
Proprietary
Page 37
Port-N Task Fike Data – R – 32 bits [Mem_reg: ABAR + port offset + 20h]
Field Name
Bits
Default
Description
Status (STS)
7:0
7Fh
Contains the latest copy of the task file status register. Fields
of note in this register that affect AHCI hardware operation
are:
Bit
7
Field Definition
BSY
cs
Indicates the interface is busy
Command specific
6:4
3
DRQ Indicates a data transfer is requested
cs Command specific
ERR Indicates an error during the transfer.
2:1
0
ERROR
Reserved
15:8
31:16
00h
Contains the latest copy of the task file error register.
Reserved
Port-N Signature – R – 32 bits [Mem_reg: ABAR + port offset + 24h]
Field Name
Bits
Default
Description
Signature (SIG)
31:0
FFFFFFFFh
Contains the signature received from a device on the first
D2H Register FIS. The bit order is as follows:
Bit
Field
31:24 LBA High Register
23:16 LBA Mid Register
15:08 LBA Low Register
07:00 Sector Count Register
It is updated once after a reset sequence.
Port-N Serial ATA Status – R – 32 bits [Mem_reg: ABAR + port offset + 28h]
Field Name
Bits
Default
Description
Device Detection (DET)
3:0
0h
Indicates the interface device detection and Phy state.
0h
No device detected and Phy communication not
established
1h
Device presence detected but Phy communication
not established
3h
Device presence detected and Phy communication
established
4h
Phy in offline mode as a result of the interface
being disabled or running in a BIST loopback mode
All other values reserved. Read Only
Current Interface Speed
(SPD)
7:4
0h
Indicates the negotiated interface communication speed.
0h
Device not present or communication not
established
1h
2h
Generation 1 communication rate negotiated
Generation 2 communication rate negotiated
All other values reserved. Read Only
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
Proprietary Page 38
Port-N Serial ATA Status – R – 32 bits [Mem_reg: ABAR + port offset + 28h]
Field Name
Bits
Default
Description
Interface Power
Management (IPM)
11:8
0h
Indicates the current interface state:
0h
Device not present or communication not
established
1h
2h
6h
Interface in active state
Interface in Partial power management state
Interface in Slumber power management state
All other values reserved. Read Only
Reserved
Reserved
31:12
Port-N Serial ATA Control – RW – 32 bits [Mem_reg: ABAR + port offset + 2Ch]
Field Name
Device Detection
Initialization (DET)
Bits
3:0
Default
Description
0h
Controls the HBA’s device detection and interface
initialization.
0h
No device detection or initialization action
requested
1h
Perform interface communication initialization
sequence to establish communication. This is
functionally equivalent to a hard reset and results
in the interface being reset and communications
reinitialized. While this field is 1h, COMRESET is
transmitted on the interface. Software should
leave the DET field set to 1h for a minimum of 1
millisecond to ensure that a COMRESET is sent
on the interface.
4h
Disable the Serial ATA interface and put Phy in
offline mode.
All other values reserved
This field may only be modified when P0CMD.ST is ‘0’.
Changing this field while the P0CMD.ST bit is set to ‘1’
results in undefined behavior. When P0CMD.ST is set to ‘1’,
this field should have a value of 0h.
Note: It is permissible to implement any of the Serial ATA
defined behaviors for transmission of COMRESET when
DET=1h.
Speed Allowed (SPD)
7:4
0h
Indicates the highest allowable speed of the interface.
0h
1h
No speed negotiation restrictions
Limit speed negotiation to Generation 1
communication rate
2h Limit speed negotiation to a rate not greater than
Generation 2 communication rate
All other values reserved
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
Proprietary Page 39
Port-N Serial ATA Control – RW – 32 bits [Mem_reg: ABAR + port offset + 2Ch]
Field Name
Bits
Default
Description
Interface Power
Management Transitions
Allowed (IPM)
11:8
0h
Indicates which power states the HBA is allowed to transition
to. If an interface power management state is disabled, the
HBA is not allowed to initiate that state and the HBA must
PMNAKP any request from the device to enter that state.
0h
1h
2h
No interface restrictions
Transitions to the Partial state disabled
Transitions to the Slumber state disabled
Transitions to both Partial and Slumber states
3h
disabled
All other values reserved
Read Only
Select Power
Management (SPM)
Port Multiplier Port
(PMP)
15:12
19:16
31:20
0h
0h
Read Only
Reserved
Reserved
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
Proprietary Page 40
Port-N Serial ATA Error – RW – 32 bits [Mem_reg: ABAR + port offset + 30h]
Field Name
Bits
Default
Description
ERROR
15:0
0000h
The ERR field contains error information for use by host
software in determining the appropriate response to the error
condition.
15:12 Reserved
Internal Error (E): The host bus adapter
experienced an internal error that caused the
operation to fail and may have put the host bus
adapter into an error state. The internal error
may include a master or target abort when
attempting to access system memory, an
11
elasticity buffer overflow, a primitive mis-
alignment, a synchronization FIFO overflow, and
other internal error conditions. Typically when an
internal error occurs, a non-fatal or fatal status bit
in the PxIS register will also be set to give
software guidance on the recovery mechanism
required.
Protocol Error (P): A violation of the Serial ATA
protocol was detected.
10
9
Persistent Communication or Data Integrity
Error (C): A communication error that was not
recovered occurred that is expected to be
persistent. Persistent communications errors
may arise from faulty interconnect with the
device, from a device that has been removed or
has failed, or a number of other causes.
Transient Data Integrity Error (T): A data
integrity error occurred that was not recovered by
the interface. This bit is set upon any error when
a Data FIS is received, including reception FIFO
overflow, CRC error or 10b8b decoding error.
8
7:2
Reserved
Recovered Communications Error (M):
Communications between the device and host
was temporarily lost but was re-established. This
can arise from a device temporarily being
removed, from a temporary loss of Phy
synchronization, or from other causes and may
be derived from the PhyNRdy signal between the
Phy and Link layers.
1
0
Recovered Data Integrity Error (I): A data
integrity error occurred that was recovered by the
interface through a retry operation or other
recovery action. This bit is set upon any error
when a Data FIS is received, including reception
FIFO overflow, CRC error or 10b8b decoding
error.
Write 1 to clear these bits.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
Proprietary Page 41
Port-N Serial ATA Error – RW – 32 bits [Mem_reg: ABAR + port offset + 30h]
Field Name
Bits
Default
Description
Diagnostics (DIAG)
31:16
0000h
Contains diagnostic error information for use by diagnostic
software in validating correct operation or isolating failure
modes:
Write ‘1’ clears these bits
31:27 Reserved
Exchanged (X): When set to one this bit
26
25
indicates a COMINIT signal was received. This
bit is reflected in the P0IS.PCS bit.
Unknown FIS Type (F): Indicates that one or
more FISs were received by the Transport layer
with good CRC, but had a type field that was not
recognized/known.
Transport state transition error (T): Indicates
that an error has occurred in the transition from
one state to another within the Transport layer
since the last time this bit was cleared. This bit is
always 0 in current implementation.
24
23
Link Sequence Error (S): Indicates that one or
more Link state machine error conditions was
encountered. The Link Layer state machine
defines the conditions under which the link layer
detects an erroneous transition. This bit is always
0 in current implementation.
Handshake Error (H): Indicates that one or more
R_ERR handshake response was received in
response to frame transmission. Such errors may
be the result of a CRC error detected by the
recipient, a disparity or 8b/10b decoding error, or
other error condition leading to a negative
handshake on a transmitted frame.
22
CRC Error (C): Indicates that one or more CRC
errors occurred with the Link Layer.
21
20
Disparity Error (D): This field is not used by
AHCI. This bit is always 0 in current
implementation.
10B to 8B Decode Error (B): Indicates that one
or more 10B to 8B decoding errors occurred.
19
18
Comm Wake (W): Indicates that a Comm Wake
signal was detected by the Phy.
Phy Internal Error (I): Indicates that the Phy
detected some internal error. This bit is always 0
in current implementation.
17
16
PhyRdy Change (N): Indicates that the PhyRdy
signal changed state. This bit is reflected in the
P0IS.PRCS bit.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
Proprietary
Page 42
Port-N Serial ATA Active – RW – 32 bits [Mem_reg: ABAR + port offset + 34h]
Field Name
Bits
Default
Description
Device Status (DS)
31:0
00000000h
This field is bit significant. Each bit corresponds to the TAG
and command slot of a native queued command, where bit 0
corresponds to TAG 0 and command slot 0. This field is set
by software prior to issuing a native queued command for a
particular command slot. Prior to writing PxCI[TAG] to ‘1’,
software will set DS[TAG] to ‘1’ to indicate that a command
with that TAG is outstanding. The device clears bits in this
field by sending a Set Device Bits FIS to the host. The HBA
clears bits in this field that are set to ‘1’ in the SActive field of
the Set Device Bits FIS. The HBA only clears bits that
correspond to native queued commands that have completed
successfully.
Software should only write this field when PxCMD.ST is set to
‘1’. This field is cleared when PxCMD.ST is written from a ‘1’
to a ‘0’ by software. This field is not cleared by a
COMRESET or a software reset.
Port-N Command Issue – RW – 32 bits [Mem_reg: ABAR + port offset + 38h]
Field Name
Bits
Default
Description
Commands Issued (CI)
31:0
00000000h
This field is bit significant. Each bit corresponds to a
command slot, where bit 0 corresponds to command slot 0.
This field is set by software to indicate to the HBA that a
command has been built in system memory for a command
slot and may be sent to the device. When the HBA receives
a FIS which clears the BSY, DRQ, and ERR bits for the
command, it clears the corresponding bit in this register for
that command slot. Bits in this field shall only be set to ‘1’ by
software when PxCMD.ST is set to ‘1’.
This field is also cleared when PxCMD.ST is written from a ‘1’
to a ‘0’ by software.
Port- N SNotification – RWC – 32 bits [Mem_reg: ABAR + port offset + 3Ch]
Field Name
Bits
Default
Description
PM Notify (PMN)
15:0
0000h
This field indicates whether a particular device with the
corresponding PM Port number issued a Set Device Bits FIS
to the host with the Notification bit set.
PM Port 0h sets bit 0
…
PM Port Fh sets bit 15
Individual bits are cleared by software writing 1’s to the
corresponding bit positions.
This field is reset to default on a HBA Reset, but it is not reset
by COMRESET or software reset.
Reserved
31:16
Reserved
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SATA Registers (Device 18, Function 0)
Proprietary
Page 43
2.2
OCHI USB 1.1 and EHCI USB 2.0 Controllers
Note: Some USB functions are controlled by, and associated with, certain PCI configuration registers in the
SMBus/ACPI device. For more information refer to section 2.3: SMBus Module and ACPI Block (Device 20,
Function 0). The diagram below lists these USB functions and the associated registers.
USB
OHCI / EHCI Controller Enables
USB Reset / PowerDown
USB Legacy control
USB Smart Power Control
USB PM & SMI Control
PCI_Reg:
61/64/65/68/6Bh
ACh
0Fh 78h
3Ch
BEh
5B/5Ch
2.2.1
OHCI Registers (Device 19, Function 0, 1, 2, 3, 4)
2.2.1.1 PCI Configuration Registers (PCI_Reg)
There are 5 Open-HCI compatible USB host controllers present (functions 0, 1, 2, 3, and 4), and each has
their own set of registers. This section describes the configuration registers necessary for the OpenHCI-
compliant USB Host Controllers to interface with other system components in a PCI-based PC host. These
registers are accessed for set-up during PCI initialization or through special cycles during normal system
runtime. Below is summary of the registers that are necessary for the OpenHCI-compliant USB Host
Controller to be successfully configured in a PCI-based PC host.
OHCI0 – PCI config
Register Name
Device / Vendor ID
Command
Offset Address
00h
04h
Status
06h
Revision ID / Class Code
Miscellaneous
08h
0Ch
BAR_OHCI
10h
Subsystem Vendor ID / Subsystem ID
Capability Pointer
Interrupt Line
2Ch
34h
3Ch
Config Timers / MSI Disable
Port Disable Control
OHCI Misc Control
Over Current Control 1
Over Current Control 2
OHCI OverCurrent Enable
Target Timeout Control
MSI Control
40h – 41h
42h – 43h
50h
58h
5Ch
68h – 69h
74h
D0h
MSI Address
D4h
MSI Data
D8h
HT MSI Support
E4h
OHCI1/2/3/4 – PCI config
©2008 Advanced Micro Devices, Inc.
OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
Proprietary
Page 44
Register Name
Device / Vendor ID
Command
Offset Address
00h
04h
06h
08h
0Ch
10h
2Ch
34h
3Ch
D0h
D4h
D8h
Status
Revision ID / Class Code
Miscellaneous
BAR_OHCI
Subsystem Vendor ID / Subsystem ID
Capability Pointer
Interrupt Line
MSI Control
MSI Address
MSI Data
Figure 3 PCI Configuration Spaces for OHCI
There are 5 OHCI compatible USB host controllers present (functions 0, 1, 2, 3 and 4), and each has their
own set of registers.
Device / Vendor ID – R - 32 bits - [PCI_Reg : 00h]
Field Name
VEND_ID
Bits
15:0
Default
Description
1002h
Vendor ID
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
OCHI USB 1.1 and EHCI USB 2.0 Controllers
Proprietary Page 45
Device / Vendor ID – R - 32 bits - [PCI_Reg : 00h]
Field Name
DEV_ID
Bits
31:16
Default
Description
Function 0: 4387h
Function 1: 4388h
Function 2: 4389h
Function 3: 438Ah
Function 4: 438Bh
Device ID
Command – RW - 16 bits - [PCI_Reg : 04h]
Field Name
IO Space
Bits
0
Default
Description
0b
A value of 0 disables the device response.
Accesses
A value of 1 allows the device to respond to I/O Space accesses.
Memory Space
Accesses
Bus Master
1
2
0b
0b
A value of 0 disables the device response.
A value of 1 allows the device to respond to Memory Space accesses.
A value of 0 disables the device from generating PCI accesses.
A value of 1 allows the device to behave as a bus master.
Hard-wired to 0, indicating no Special Cycle support.
When it is 0, Memory Write must be used.
Special Cycle
Memory Write
and Invalidate
Command
3
4
0b
0b
When it is 1, masters may generate the command.
VGA Palette
Register
Accesses
5
6
0b
0b
Hard-wired to 0, indicating the device should treat palette write accesses
like all other accesses.
Parity Enable
When it is 1, the device must take its normal action when a parity error is
detected.
When it is 0, the device sets its Detected Parity Error status bit (bit 15 in
the Status register) when an error is detected, but continues normal
operations without asserting PERR#.
Reserved
SERR# Enable
7
8
0b
0b
Hard-wired to 0 per PCI2.3 spec.
A value of 0 disables the SERR# driver.
A value of 1 enables the SERR# driver.
Address parity errors are reported only if this bit and bit [6] are 1.
A value of 0 means that only fast back-to-back transactions to the same
agent are allowed.
A value of 1 means the master is allowed to generate fast back-to-back
transactions to different agents.
A value of 0 enables the assertion of the device/function’s INTx# signal.
A value of 1 disables the assertion of the device/function’s INTx# signal.
Reserved
Fast Back-to-
Back Enable
9
0b
0b
Interrupt Disable
Reserved
10
15:11
Status – R - 16 bits - [PCI_Reg : 06h]
Field Name
Reserved
Interrupt Status
Bits
2:0
3
Default
Description
Reserved
0b
This bit reflects the state of the interrupt in the device/function. Only
when the Interrupt Disable bit in the command register is a 0 and this
Interrupt Status bit is a 1 will the device’s/function’s INTx# signal be
asserted. Setting the Interrupt Disable bit to a 1 has no effect on the
state of this bit.
Capabilities List
4
1b
A value of 0 indicates that no New Capabilities linked list is available.
A value of 1 indicates that the value read at offset 34h is a pointer in
Configuration Space to a linked list of new capabilities.
Hard-wired to 1, indicating 66MHz capable.
66 MHz Capable
Reserved
Fast Back-to-
Back Capable
5
6
7
1b
1b
Reserved
Hard-wired to 1, indicating Fast Back-to-Back capable.
©2008 Advanced Micro Devices, Inc.
OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
Proprietary
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Status – R - 16 bits - [PCI_Reg : 06h]
Field Name
Master Data
Parity Error
Bits
8
Default
Description
0b
This bit is set only when three conditions are met: 1) the bus agent
asserted PERR# itself (on a read) or observed PERR# asserted (on a
write); 2) the agent setting the bit acted as the bus master for the
operation in which the error occurred; and 3) the Parity Error Response
bit (Command register) is set.
DEVSEL timing
Signaled Target
Abort
10:9
11
01b
0b
Hard-wired to 01b – medium timing
This bit is set by a target device whenever it terminates a transaction
with Target-Abort.
Received Target
Abort
Received Master
Abort
Signaled System
Error
Detected Parity
Error
12
13
14
15
0b
0b
0b
0b
This bit is set by a master device whenever its transaction is terminated
with Target-Abort.
This bit is set by a master device whenever its transaction (except for
Special Cycle) is terminated with Master-Abort.
This bit is set whenever the device asserts SERR#.
This bit is set by the device whenever it detects a parity error, even if
parity error handling is disabled (as controlled by bit 6 in the Command
register).
Revision ID / Class Code – R - 32 bits - [PCI_Reg : 08h]
Field Name
Revision ID
PI
Bits
Default
Description
7:0
00h
Revision ID.
15:8
10h
Programming Interface. A constant value of ‘10h’ indentifies the device
being an OpenHCI Host Controller.
SC
BC
23:16
31:24
03h
0Ch
Sub Class. A constant value of ‘03h’ indentifies the device being of
Universal Serial Bus.
Base Class. A constant value of ‘0Ch’ identifies the device being a Serial
Bus Controller.
Miscellaneous – RW/R - 32 bits - [PCI_Reg : 0Ch]
Field Name
Bits
Default
Description
Cache Line Size
7:0
00h
This read/write field specifies the system cacheline size in units of
DWORDs and must be initialized to 00h.
Latency Timer
Header Type
15:8
00h
[9:8] hard-wired to 00b, resulting in a timer granularity of at least four
clocks. This field specifies, in units of PCI bus clocks, the value of the
Latency Timer for this PCI bus master.
This field identifies the layout of the second part of the predefined header
(beginning at byte 10h in Configuration Space) and also whether or not
the device contains multiple functions.
23:16
80h/00h
Function 0: Bit[23] hard-wired to 1 Æ the device has multiple functions.
Function 1: Bit[23] hard-wired to 0 Æ the device is single function.
Function 2: Bit[23] hard-wired to 0 Æ the device is single function.
Function 3: Bit[23] hard-wired to 0 Æ the device is single function.
Function 4: Bit[23] hard-wired to 0 Æ the device is single function.
Bits [22:16] are hard-wired to 00h.
BIST
31:24
00h
Hard-wired to 00h, indicating no build-in BIST support.
Bar_OHCI – RW - 32 bits - [PCI_Reg : 10h]
Field Name
Bits
Default
Description
IND
0
0b
Indicator. A constant value of ‘0’ indicates that the operational registers
of the device are mapped into memory space of the main memory of the
PC host system. Read Only.
TP
2:1
0h
Type. A constant value of ‘00b’ indicates that the base register is 32-bit
wide and can be placed anywhere in the 32-bit memory space; i.e., lower
4 GB of the main memory of the PC host. Read Only.
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OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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Bar_OHCI – RW - 32 bits - [PCI_Reg : 10h]
Field Name
PM
Bits
3
Default
Description
0b
Prefetch memory. A constant value of ‘0’ indicates that there is no
support for “prefetchable memory”. Read Only.
11:4
00h
Represents a maximum of 4-KB addressing space for the OpenHCi’s
operational registers. Read Only.
BAR
31:12
000h
Base Address. Specifies the upper 20 bits of the 32-bit starting base
address. This represent a maximum of 4-KB addressing space for the
OpenHCI’s operational registers.
Subsystem Vendor ID / Subsystem ID – RW - 32 bits - [PCI_Reg : 2Ch]
Field Name
Subsystem Vendor ID
Subsystem ID
Bits
15:0
31:16
Default
0000h
0000h
Description
Can only be written once by software.
Can only be written once by software.
Capability Pointer – R - 8 bits - [PCI_Reg : 34h]
Field Name
Capability Pointer
Bits
Default
Description
7:0
D0h
Address of the 1st element of capability link.
Interrupt Line – RW – 32 bits - [PCI_Reg : 3Ch]
Field Name
Bits
Default
Description
Interrupt Line
7:0
00h
The Interrupt Line register is an eight-bit register used to
communicate interrupt line routing information. The register
is read/write and must be implemented by any device (or
device function) that uses an interrupt pin. POST software
will write the routing information into this register as it
initializes and configures the system.
The value in this register tells which input of the system
interrupt controller(s) the device's interrupt pin is connected
to. The device itself does not use this value; rather it is used
by device drivers and operating systems. Device drivers
and operating systems can use this information to determine
priority and vector information. Values in this register are
system architecture specific.
Interrupt Pin
15:8
Read Only by default.
01h
02h
03h
02h
03h
OHCI0: Hard-wired to 01h, corresponding to using INTA#.
OHCI1: Hard-wired to 02h, corresponding to using INTB#.
OHCI2: Hard-wired to 03h, corresponding to using INTC#.
OHCI3: Hard-wired to 02h, corresponding to using INTB#.
OHCI4: Hard-wired to 03h, corresponding to using INTC#.
MIN_GNT
MAX_LAT
23:16
31:24
00h
00h
Read Only. Hardwired to 00h to indicate no major
requirements for the settings of Latency Timers.
Read Only. Hardwired to 00h to indicate no major
requirements for the settings of the Latency Timers.
Config Timers / MSI Disable (OHCI0 only) – RW - 16 bits - [PCI_Reg : 40h]
Field Name
Bits
Default
Description
TRDY Timer
7:0
80h
Target Ready timer to timeout non-responding target.
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OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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Page 48
Config Timers / MSI Disable (OHCI0 only) – RW - 16 bits - [PCI_Reg : 40h]
Field Name
MSI Disable
Bits
12:8
Default
00h
Description
When these bits are set MSI capability will be disabled for
the corresponding Host Controller.
Bit 8 – OHCI0
Bit 9 – OHCI1
Bit 10 – OHCI2
Bit 11 – OHCI3
Bit 12 – OHCI4
Reserved
15:13
0h
Reserved
Port Disable (OHCI0 only) – RW - 16 bits - [PCI_Reg : 42h]
Field Name
Bits
Default
Description
Port_disable
9:0
00h
When these bits are set the corresponding ports are
disabled. For example, if bit-0 is set, then port-0 (its
corresponding port) is disabled; if bit-1 is set, then its
corresponding port (port-1) is disabled (and so on).
Reserved
Reserved
15:10
00h
OHCI Misc Control (OHCI0 only) – RW - 16 bits - [PCI_Reg: 50h]
Field Name
Reserved
DisUsbS3OvrCur
Bits
7:0
8
Default
00h
Description
Reserved.
0b
Set to 1 to disable over-current detection for both EHCII and
OHCI.
Reserved
9
0b
1b
1b
0b
Reserved.
OHCI Cache Enable
OHCI Prefetch Enable
SMI Handshake Disable
10
11
12
Enable bit for 64 byte OHCI DMA cache.
Enable bit to prefetch next cache line for OHCI DMA reads.
If this bit is set the Handshake between USB and ACPI is
disabled when SMI is requested by USB
Reserved.
Reserved
15: 13
0h
Over Current Control 1 (OHCI0 only) – R - 32 bits - [PCI_Reg : 58h]
Field Name
Bits
Default
Description
Port0 OverCurrent Control
3:0
Fh
The register is to control the OverCurrent pin mapping for
Port-0. There are 10 OverCurrent pins (USB_OC0 ~
USB_OC9), any value greater than 0x9h will disable the
OverCurrent function for port-0.
Port1 OverCurrent Control
Port2 OverCurrent Control
Port3 OverCurrent Control
Port4 OverCurrent Control
7:4
Fh
Fh
Fh
Fh
The register is to control the OverCurrent pin mapping for
Port-1. There are 10 OverCurrent pins (USB_OC0 ~
USB_OC9), any value greater than 0x9h will disable the
OverCurrent function for port-1.
The register is to control the OverCurrent pin mapping for
Port-2. There are 10 OverCurrent pins (USB_OC0 ~
USB_OC9), any value greater than 0x9h will disable the
OverCurrent function for port-2.
The register is to control the OverCurrent pin mapping for
Port-3. There are 10 OverCurrent pins (USB_OC0 ~
USB_OC9), any value greater than 0x9h will disable the
OverCurrent function for port-3.
The register is to control the OverCurrent pin mapping for
Port-4. There are 10 OverCurrent pins (USB_OC0 ~
USB_OC9), any value greater than 0x9h will disable the
OverCurrent function for port-4.
11:8
15:12
19:16
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OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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Page 49
Over Current Control 1 (OHCI0 only) – R - 32 bits - [PCI_Reg : 58h]
Field Name
Bits
Default
Description
Port5 OverCurrent Control
23:20
Fh
The register is to control the OverCurrent pin mapping for
Port-5. There are 10 OverCurrent pins (USB_OC0 ~
USB_OC9), any value greater than 0x9h will disable the
OverCurrent function for port-5.
Port6 OverCurrent Control
Port7 OverCurrent Control
27:24
31:28
Fh
Fh
The register is to control the OverCurrent pin mapping for
Port-6. There are 10 OverCurrent pins (USB_OC0 ~
USB_OC9), any value greater than 0x9h will disable the
OverCurrent function for port-6.
The register is to control the OverCurrent pin mapping for
Port-7. There are 10 OverCurrent pins (USB_OC0 ~
USB_OC9), any value greater than 0x9h will disable the
OverCurrent function for port-7.
There are 10 pins can be used as USB OverCurrent function –
USB_OC0#/GPM0# USB_OC1#/GPM1# USB_OC2#/GPM2# USB_OC3#/GPM3#
USB_OC4#/GPM4# USB_OC5#/GPM5# USB_OC6#/GEVENT6# USB_OC7#/GEVENT7#
USB_OC8#/GPM8# USB_OC9#/SLP_S2/GPM9#
Register value-to-OverCurrent Pin mapping:
USB_OC0# = 0000, USB_OC1# = 0001, USB_OC2# = 0010, USB_OC3# = 0011,
USB_OC4# = 0100, USB_OC5# = 0101, USB_OC6# = 0110, USB_OC7# = 0111,
USB_OC8# = 1000, USB_OC9# = 1001
* Note: Since OverCurrent pins can be used as GPM# as well, the corresponding register bits to set the pin as
OverCurrent have to be set in Smbus Controller.
Over Current Control 2 (OHCI0 only) – R - 32 bits - [PCI_Reg : 5Ch]
Field Name
Bits
Default
Description
Port8 OverCurrent Control
3:0
Fh
The register is to control the OverCurrent pin mapping for
Port-8. There are 10 OverCurrent pins (USB_OC0 ~
USB_OC9), any value greater than 0x9h will disable the
OverCurrent function for port-8.
Port9 OverCurrent Control
7:4
Fh
The register is to control the OverCurrent pin mapping for
Port-9. There are 10 OverCurrent pins (USB_OC0 ~
USB_OC9), any value greater than 0x9h will disable the
OverCurrent function for port-9.
Reserved
31:8
Reserved
There are 10 pins can be used as USB OverCurrent function –
USB_OC0#/GPM0# USB_OC1#/GPM1# USB_OC2#/GPM2# USB_OC3#/GPM3#
USB_OC4#/GPM4# USB_OC5#/GPM5# USB_OC6#/GEVENT6# USB_OC7#/GEVENT7#
USB_OC8#/GPM8# USB_OC9#/SLP_S2/GPM9#
Register value-to-OverCurrent Pin mapping:
USB_OC0# = 0000, USB_OC1# = 0001, USB_OC2# = 0010, USB_OC3# = 0011,
USB_OC4# = 0100, USB_OC5# = 0101, USB_OC6# = 0110, USB_OC7# = 0111,
USB_OC8# = 1000, USB_OC9# = 1001
*Note: Since OverCurrent pins can be used as GPM# as well, the corresponding register bits to set the pin as
OverCurrent have to be set in Smbus Controller.
OHCI OverCurrent Enable (OHCI0 only) – RW - 16 bits - [PCI_Reg : 68h]
Field Name
OHCI OverCurrent Enable
Bits
9:0
Default
00h
Description
Writing this bit to a one enables the respective port to be
sensitive to over-current conditions as wake-up events when
it is owned by OHCI.
Reserved
15:10
00h
Reserved
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OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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Target Timeout Control (OHCI0 only) – RW - 32 bits - [PCI_Reg : 74h]
Field Name
Bits
Default
Description
Retry counter
7:0
FFh
Counter to control the purge of the delay queue when the
host controller does not return the ack. After the counter
expires the transaction is target aborted.
The retry counter can be disabled by writing 00h in this
Register.
Reserved
Timeout Timer
23:8
31:24
0000h
80h
Reserved
Timer to control the purge of the delay queue when the
master that has initiated the access does not return to
complete the transaction. After the timer expires the queue
is invalidated and the next transaction is serviced.
MSI Control – RW - 32 bits - [PCI_Reg : D0h]
Field Name
MSI USB
Bits
7:0
Default
05h
00h
0b
Description
MSI USB ID. Read only.
Pointer to next capability structure
Set to 1 to disable IRQ. Use MSI instead.
Reserved
Next Item Pointer
MSI Control Out
Reserved
MSI Control
Reserved
15:8
16
19:17
22:20
31:23
0h
0h
MSI control field
00h
Reserved
MSI Address – RW - 32 bits - [PCI_Reg : D4h]
Field Name
Bits
Default
Description
MSI Address
31:0
0h
System-specified message address.
MSI Data – RW - 16 bits - [PCI_Reg : D8h]
Field Name
Bits
Default
Description
MSI Data
15:0
0h
System-specified message.
2.2.1.2 OHCI Operational Registers (MEM_Reg)
The Host Controller (HC) contains a set of on-chip operational registers, which are mapped into a non-
cacheable portion of the system addressable space. These registers are used by the Host Controller Driver
(HCD) and should be read and written as Dwords.
Reserved bits may be allocated in future releases and should not be assumed to contain 0. The Host
Controller Driver should always preserve the value(s) of the reserved field. When a write to set/clear register
is written, bits written to reserved fields should be 0.
Register Name
HcRevision
Offset Address
0h
4h
HcControl
HcCommandStatus
HcInterruptStatus
HcInterruptEnable
HcInterruptDisable
HcHCCA
HcPeriodCurrentED
HcControlHeadED
HcControlCurrentED
HcBulkHeadED
8h
Ch
10h
14h
18h
1Ch
20h
24h
28h
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Register Name
HcBulkCurrentED
HcDoneHead
Offset Address
2Ch
30h
HcFmInterval
34h
HcFmRemaining
HcFmNumber
38h
3Ch
40h
44h
48h
HcPeriodicStart
HcLSThreshold
HcRhDescriptorA
HcRhDescriptorB
HCRhStatus
4Ch
50h
HcRhPortStatus[1]
…
54h
…
HcRhPortStatus[NDP]
54+4*NDP
HcRevision – R - 32 bits - [MEM_Reg : 00h]
Field Name
REV
Bits
7:0
Default
Description
10h
Revision.
This read-only field contains the version of HCI specification.
L
8
1b
Legacy
This read-only field is 1, indicating that the legacy support registers are
present in this HC.
Reserved
31:9
Reserved
HcControl - 32 bits - [MEM_Reg : 04h]
Field Name
CBSR
Bits
1:0
Default
HCD
HC
Description
00b
RW
R
ControlBulkServiceRatio
This specifies the service ratio between Control and
Bulk Eds. Before processing any of the non-periodic
lists, HC must compare the ratio specified with its
internal count on how many nonempty Control Eds
have been processed, in determining whether to
continue serving another Control ED or switching to
Bulk Eds.
CBSR
No. of Control Eds Over Bulk Eds Served
0
1:1
1
2:1
2
3:1
3
4:1
PLE
2
0b
RW
R
PeriodicListEnable
This bit is set to enable the processing of the periodic
list in the next Frame. If cleared by HCD, processing
of the periodic list does not occur after the next SOF.
HC must check this bit before it starts processing the
list.
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OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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HcControl - 32 bits - [MEM_Reg : 04h]
Field Name
Bits
Default
HCD
HC
Description
IE
3
0b
RW
R
IsochronousEnable
This bit is used by HCD to enable/disable processing
of isochronous Eds. While processing the periodic list
in a Frame, HC checks he status of this bit when it
finds an Isochronous ED (F=1). If set (enabled), HC
continues processing the Eds. If cleared (disabled),
HC halts processing of the periodic list (which now
contains only isochronous Eds) and begins
processing the Bulk/Control lists. Setting this bit is
guaranteed to take effect in the next Frame (not the
current Frame).
CLE
4
0b
RW
R
ControlListEnable
This bit is set to enable the processing of the Control
list in the next Frame. If cleared by HCD, processing
of the Control list does not occur after the next SOF.
HC must check this bit whenever it determines to
process the list. When disabled, HCD may modify the
list. If HcControlCurrentED is pointing to an ED to be
removed, HCD must advance the pointer by updating
HcControlCurrentED before re-enabling processing of
the list.
BLE
5
0b
RW
R
BulkListEnable
This bit is set to enable the processing of the Bulk list
in the next Frame. If cleared by HCD, processing of
the Bulk list does not occur after the next SOF. HC
checks this bit whenever it determines to process the
list. When disabled, HCD may modify the list. If
HcBulkCurrentED is pointing to an ED to be removed,
HCD must advance the pointer by updating
HcBulkCurrentED before re-enabling processing of
the list.
HCFS
7:6
00b
RW
RW
HostControllerFunctionalState for USB
00b: USBRESET
01b: USBRESUME
10b: USBOPERATIONAL
11b: USBSUSPEND
A transition to USBOPERATIONAL from another
state causes SOF generation to begin 1 ms
later. HCD may determine whether HC has
begun sending SOFs by reading the
StartofFrame field of HcInterruptStatus.
This field may be changed by HC only when in
the USBSUSPEND state. HC may move from the
USBSUSPEND state to the USBRESUME state after
detecting the resume signaling from a
downstream port.
HC enters USBSUSPEND after a software reset,
whereas it enters USBRESET after a hardware
reset. The latter also resets the Root Hub and
asserts subsequent reset signaling to
downstream ports.
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AMD SB600 Register Reference Manual
OCHI USB 1.1 and EHCI USB 2.0 Controllers
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HcControl - 32 bits - [MEM_Reg : 04h]
Field Name
Bits
Default
HCD
HC
Description
IR
8
0b
RW
R
InterruptRouting
This bit determines the routing of interrupts generated
by events registered in HcInterruptStatus. If clear, all
interrupts are routed to the normal host bus interrupt
mechanism. If set, interrupts are routed to the System
Management Interrupt. HCD clears this bit upon a
hardware reset, but it does not alter this bit upon a
software reset. HCD uses this bit as a tag to indicate
the ownership of HC.
RWC
9
0b
RW
RW
RemoteWakeupConnected
This bit indicates whether HC supports remote
wakeup signaling. If remote wakeup is supported and
used by the system it is the responsibility of system
firmware to set this bit during POST. HC clears the bit
upon a hardware reset but does not alter it upon a
software reset. Remote wakeup signaling of the host
system is host-bus-specific and is not described in
this specification.
RWE
10
0b
RW
R
RemoteWakeupEnable
This bit is used by HCD to enable or disable the
remote wakeup feature upon the detection of
upstream resume signaling. When this bit is set and
the ResumeDetected bit in HcInterruptStatus is set, a
remote wakeup is signaled to the host system.
Setting this bit has no impact on the generation of
hardware interrupt.
Reserved
31:11
Reserved
HcCommandStatus - 32 bits - [MEM_Reg : 08h]
Field Name
HCR
Bits
0
Default
HCD
HC
Description
0b
RW
RW
HostControllerReset
This bit is set by HCD to initiate a software reset of
HC.Regardless of the functional state of HC, it moves
to the USBSUSPEND state in which most of the
operational registers are reset except those stated
otherwise; e.g., the InterruptRouting field of
HcControl, and no Host bus accesses are allowed.
This bit is cleared by HC upon the completion of the
reset operation. The reset operation must be
completed within 10 ms. This bit, when set, should
not cause a reset to the Root Hub and no subsequent
reset signaling should be asserted to its downstream
ports.
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AMD SB600 Register Reference Manual
OCHI USB 1.1 and EHCI USB 2.0 Controllers
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HcCommandStatus - 32 bits - [MEM_Reg : 08h]
Field Name
CLF
Bits
1
Default
HCD
HC
Description
0b
RW
RW
ControlListFilled
This bit is used to indicate whether there are any TDs
on the Control list. It is set by HCD whenever it adds
a TD to an ED in the Control list. When HC begins to
process the head of the Control list, it checks CLF. As
long as ControlListFilled is 0, HC will not start
processing the Control list. If CF is 1, HC will start
processing the Control list and will set
ControlListFilled to 0. If HC finds a TD on the list,
then HC will set ControlListFilled to 1 causing
the Control list processing to continue. If no TD is
found on the Control list, and if the HCD does not set
ControlListFilled, then ControlListFilled will still be 0
when HC completes processing the Control list and
Control list processing will stop.
BLF
2
0b
RW
RW
BulkListFilled
This bit is used to indicate whether there are any TDs
on the Bulk list. It is set by HCD whenever it adds a
TD to an ED in the Bulk list. When HC begins to
process the head of the Bulk list, it checks BF. As
long as BulkListFilled is 0, HC will not start
processing the Bulk list. If BulkListFilled is 1, HC will
start processing the Bulk list and will set BF to 0. If
HC finds a TD on the list, then HC will set
BulkListFilled to 1 causing the Bulk list processing to
continue. If no TD is found on the Bulk list, and if
HCD does not set BulkListFilled, then BulkListFilled
will still be 0 when HC completes processing the Bulk
list and Bulk list processing will stop. BulkListFilled
This bit is used to indicate whether there are any TDs
on the Bulk list. It is set by HCD whenever it adds a
TD to an ED in the Bulk list. When HC begins to
process the head of the Bulk list, it checks BF. As
long as BulkListFilled is 0, HC will not start
processing the Bulk list. If BulkListFilled is 1, HC will
start processing the
Bulk list and will set BF to 0. If HC finds a TD on the
list, then HC will set BulkListFilled to 1 causing the
Bulk list processing to continue. If no TD is found on
the Bulk list, and if HCD does not set BulkListFilled,
then BulkListFilled will still be 0 when HC completes
processing the Bulk list and Bulk list processing will
stop.
OCR
3
0b
RW
RW
OwnershipChangeRequest
This bit is set by an OS HCD to request a change of
control of the HC. When set HC will set the
OwnershipChange field in HcInterruptStatus. After
the changeover, this bit is cleared and remains so
until the next request from OS HCD.
Reserved
SOC
15:4
17:16
00b
R
RW
SchedulingOverrunCount
These bits are incremented on each scheduling
overrun error. It is initialized to 00b and wraps around
at 11b. This will be incremented when a scheduling
overrun is detected even if SchedulingOverrun in
HcInterruptStatus has already been set. This is used
by HCD to monitor any persistent scheduling
problems.
Reserved
31:18
Reserved
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OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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HcInterruptStatus – RW - 32 bits - [MEM_Reg : 0Ch]
Field Name
SO
Bits
0
Default
HCD
HC
Description
0b
RW
RW
SchedulingOverrun
This bit is set when the USB schedule for the current
Frame overruns and after the update of
HccaFrameNumber. A scheduling overrun will also
cause the SchedulingOverrunCount of
HcCommandStatus to be incremented.
WritebackDoneHead
WDH
1
0b
RW
RW
This bit is set immediately after HC has written
HcDoneHead to HccaDoneHead. Further updates of
the HccaDoneHead will not occur until this bit has
been cleared. HCD should only clear this bit after it
has saved the content of HccaDoneHead.
StartofFrame
This bit is set by HC at each start of a frame and after
the update of HccaFrameNumber. HC also generates
a SOF token at the same time.
SF
2
3
0b
0b
RW
RW
RW
RW
RD
ResumeDetected
This bit is set when HC detects that a device on the
USB is asserting resume signaling. It is the transition
from no resume signaling to resume signaling
causing this bit to be set. This bit is not set when
HCD sets the USBRESUME state.
UE
4
0b
RW
RW
UnrecoverableError
This bit is set when HC detects a system error not
related to USB. HC should not proceed with any
processing nor signaling before the system error has
been corrected. HCD clears this bit after HC has
been reset.
FNO
5
6
0b
0b
RW
RW
RW
RW
FrameNumberOverflow
This bit is set when the MSb of HcFmNumber (bit 15)
changes value, from 0 to 1 or from 1 to 0, and after
HccaFrameNumber has been updated.
RootHubStatusChange
RHSC
This bit is set when the content of HcRhStatus or the
content of any of HcRhPortStatus
[NumberofDownstreamPort] has changed.
Reserved
OC
29:7
30
Reserved
OwnershipChange
0b
RW
RW
This bit is set by HC when HCD sets the
OwnershipChangeRequest field in
HcCommandStatus. This event, when unmasked, will
always generate an System Management Interrupt
(SMI) immediately.
This bit is tied to 0b when the SMI pin is not
implemented.
Reserved
31
Reserved
HcInterruptEnable - 32 bits - [MEM_Reg : 10h]
Field Name
Bits
Default
HCD
HC
Description
SO
0
0b
RW
RW
0 - Ignore
1 - Enable interrupt generation due to Scheduling
Overrun.
WDH
SF
1
2
0b
0b
RW
RW
RW
RW
0 - Ignore
1 - Enable interrupt generation due to HcDoneHead
Writeback.
0 - Ignore
1 - Enable interrupt generation due to Start of Frame.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
OCHI USB 1.1 and EHCI USB 2.0 Controllers
Proprietary
Page 56
HcInterruptEnable - 32 bits - [MEM_Reg : 10h]
Field Name
RD
Bits
3
Default
HCD
HC
Description
0b
RW
W
0 - Ignore
1 - Enable interrupt generation due to Resume
Detect.
UE
4
5
6
0b
0b
0b
RW
RW
RW
RW
RW
RW
0 - Ignore
1 - Enable interrupt generation due to Unrecoverable
Error.
0 - Ignore
1 - Enable interrupt generation due to Frame Number
Overflow.
0 - Ignore
FNO
RHSC
1 - Enable interrupt generation due to Root Hub
Status Change.
Reserved
OC
29:7
30
Reserved
0 - Ignore
0b
0b
RW
RW
RW
R
1 - Enable interrupt generation due to Ownership
Change.
A ‘0’ written to this field is ignored by HC. A '1' written
to this field enables interrupt generation due to events
specified in the other bits of this register. This is used
by HCD as a Master Interrupt Enable.
MIE
31
HcInterruptDisable - 32 bits - [MEM_Reg : 14h]
Field Name
Bits
Default
HCD
HC
Description
SO
0
0b
RW
R
0 - Ignore
1 - Disable interrupt generation due to Scheduling
Overrun.
WDH
1
0b
RW
R
0 - Ignore
1 - Disable interrupt generation due to HcDoneHead
Writeback.
SF
2
3
0b
0b
RW
RW
R
R
0 - Ignore
1 - Disable interrupt generation due to Start of Frame.
0 - Ignore
RD
1 - Disable interrupt generation due to Resume
Detect.
UE
4
5
6
0b
0b
0b
RW
RW
RW
R
R
R
0 - Ignore
1 - Disable interrupt generation due to Unrecoverable
Error.
0 - Ignore
1 - Disable interrupt generation due to Frame Number
Overflow.
0 - Ignore
FNO
RHSC
1 - Disable interrupt generation due to Root Hub
Status Change.
Reserved
OC
29:7
30
Reserved
0 - Ignore
0b
0b
RW
RW
R
R
1 - Disable interrupt generation due to Ownership
Change.
A '0' written to this field is ignored by HC. A '1' written
to this field disables interrupt generation due to
events specified in the other bits of this register. This
field is set after a hardware or software reset.
MIE
31
HcHCCA - 32 bits - [MEM_Reg : 18h]
Field Name
Reserved
HCCA
Bits
7:0
31:8
Default
HCD
HC
Description
Reserved
000000h
RW
R
This is the base address of the Host Controller
Communication Area
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HcPeriodCurrentED - 32 bits - [MEM_Reg : 1Ch]
Field Name
Reserved
PCED
Bits
3:0
31:4
Default
HCD
HC
Description
Reserved
0000000
h
R
RW
PeriodCurrentED
This is used by HC to point to the head of one of the
Periodic lists which will be processed in the current
Frame. The content of this register is updated by HC
after a periodic ED has been processed. HCD may
read the content in determining which ED is currently
being processed at the time of reading.
HcControlHeadED- 32 bits - [MEM_Reg : 20h]
Field Name
Reserved
CHED
Bits
3:0
31:4
Default
HCD
HC
Description
Reserved
0000000
h
RW
R
ControlHeadED
HC traverses the Control list starting with the
HcControlHeadED pointer. The content is loaded
from HCCA during the initialization of HC.
HcControlCurrentED - 32 bits - [MEM_Reg : 24h]
Field Name
Reserved
CCED
Bits
3:0
31:4
Default
HCD
HC
Description
Reserved
0000000 RW
h
RW
ControlCurrentED
This pointer is advanced to the next ED after serving
the present one. HC will continue processing the list
from where it left off in the last Frame. When it
reaches the end of the Control list, HC checks the
ControlListFilled of in HcCommandStatus. If set, it
copies the content of HcControlHeadED to
HcControlCurrentED and clears the bit. If not set, it
does nothing. HCD is allowed to modify this register
only when the ControlListEnable of HcControl is
cleared. When set, HCD only reads the
instantaneous value of this register. Initially, this is set
to zero to indicate the end of the Control list.
HcBulkHeadED - 32 bits - [MEM_Reg : 28h]
Field Name
Reserved
BHED
Bits
3:0
31:4
Default
HCD
HC
Description
Reserved
0b
RW
R
BulkHeadED
HC traverses the Bulk list starting with the
HcBulkHeadED pointer. The content is loaded from
HCCA during the initialization of HC.
HcBulkCurrentED - 32 bits - [MEM_Reg : 2Ch]
Field Name
Reserved
Bits
3:0
Default
HCD
HC
Description
Reserved
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HcBulkCurrentED - 32 bits - [MEM_Reg : 2Ch]
Field Name
BCED
Bits
31:4
Default
0000000
h
HCD
RW
HC
RW
Description
BulkCurrentED
This is advanced to the next ED after the HC has
served the present one. HC continues processing the
list from where it left off in the last Frame. When it
reaches the end of the Bulk list, HC checks the
ControlListFilled of HcControl. If set, it copies the
content of HcBulkHeadED to HcBulkCurrentED and
clears the bit. If it is not set, it does nothing. HCD is
only allowed to modify this register when the
BulkListEnable of HcControl is cleared. When set,
the HCD only reads the instantaneous value of this
register. This is initially set to zero to indicate the end
of the Bulk list.
HcDoneHead - 32 bits - [MEM_Reg : 30h]
Field Name
Reserved
DH
Bits
3:0
31:4
Default
HCD
HC
Description
Reserved
0b
R
RW
DoneHead
When a TD is completed, HC writes the content of
HcDoneHead to the NextTD field of the TD. HC then
overwrites the content of HcDoneHead with the
address of this TD. This is set to zero whenever HC
writes the content of this register to HCCA. It also
sets the WritebackDoneHead of HcInterruptStatus.
HcFmInterval - 32 bits - [MEM_Reg : 34h]
Field Name
Bits
Default
HCD
HC
Description
FI
13:0
2EDFh
RW
R
FrameInterval
This specifies the interval between two consecutive
SOFs in bit times. The nominal value is set to be
11,999.
HCD should store the current value of this field before
resetting HC. By setting the HostControllerReset
field of HcCommandStatus as this will cause the HC
to reset this field to its nominal value. HCD may
choose to restore the stored value upon the
completion of the Reset sequence.
Reserved
FSMPS
15:14
30:16
Reserved
FSLargestDataPacket
0000h
RW
RW
R
R
This field specifies a value which is loaded into the
Largest Data Packet Counter at the beginning of
each frame. The counter value represents the largest
amount of data in bits which can be sent or received
by the HC in a single transaction at any given time
without causing scheduling overrun. The field value is
calculated by the HCD.
FIT
31
0b
FrameIntervalToggle
HCD toggles this bit whenever it loads a new value to
FrameInterval
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OCHI USB 1.1 and EHCI USB 2.0 Controllers
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HcFmRemaining - 32 bits - [MEM_Reg : 38h]
Field Name
FR
Bits
13:0
Default
HCD
HC
Description
0000h
R
RW
FrameRemaining
This counter is decremented at each bit time. When it
reaches zero, it is reset by loading the FrameInterval
value specified in HcFmInterval at the next bit time
boundary. When entering the USBOPERATIONAL
state, HC re-loads the content with the
FrameInterval of HcFmInterval and uses the updated
value from the next SOF.
Reserved
FRT
30:14
31
Reserved
FrameRemainingToggle
0b
R
RW
This bit is loaded from the FrameIntervalToggle field
of HcFmInterval whenever FrameRemaining
reaches 0. This bit is used by HCD for the
synchronization between FrameInterval and
FrameRemaining.
HcFmNumber - 32 bits - [MEM_Reg : 3Ch]
Field Name
Bits
Default
HCD
HC
Description
FN
15:0
0000h
R
RW
This is incremented when HcFmRemaining is re-
loaded. It will be rolled over to 0h after ffffh. When
entering the USBOPERATIONAL state, this will be
incremented automatically. The content will be written
to HCCA after HC has incremented the
FrameNumber at each frame boundary and sent a
SOF but before HC reads the first ED in that Frame.
After writing to HCCA, HC will set the
StartofFrame in HcInterruptStatus.
Reserved
31:16
Reserved
HcPeriodicStart - 32 bits - [MEM_Reg : 40h]
Field Name
Bits
Default
HCD
HC
Description
PS
13:0
0000h
RW
R
PeriodicStart
After a hardware reset, this field is cleared. This is
then set by HCD during the HC initialization. The
value is calculated roughly as 10% off from
HcFmInterval. A typical value will be 3E67h. When
HcFmRemaining reaches the value specified,
processing of the periodic lists will have priority over
Control/Bulk processing. HC will therefore start
processing the Interrupt list after completing the
current Control or Bulk transaction that is in progress.
Reserved
31:14
Reserved
HcLSThreshold - 32 bits - [MEM_Reg : 44h]
Field Name
Bits
Default
HCD
HC
Description
LST
11:0
0628h
RW
R
LSThreshold
This field contains a value which is compared to the
FrameRemaining field prior to initiating a Low Speed
transaction. The transaction is started only if
FrameRemaining this field. The value is calculated
by HCD with the consideration of transmission and
setup overhead.
Reserved
31:12
Reserved
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HcRhDescriptorA - 32 bits - [MEM_Reg : 48h]
Field Name
NDP
Bits
7:0
Default
HCD
HC
Description
02h
R
R
NumberDownstreamPorts
These bits specify the number of downstream ports
supported by the Root Hub.
PSM
8
0b
RW
R
PowerSwitchingMode
This bit is used to specify how the power switching of
the Root Hub ports is controlled. It is implementation-
specific. This field is only valid if the
NoPowerSwitching field is cleared.
0: all ports are powered at the same time.
1: each port is powered individually. This mode
allows port power to be controlled by either the global
switch or per-port switching. If the
PortPowerControlMask bit is set, the port responds
only to port power commands
(Set/ClearPortPower). If the port mask is cleared,
then the port is controlled only by the global power
switch (Set/ClearGlobalPower).
NPS
9
1b
RW
R
NoPowerSwitching
These bits are used to specify whether power
switching is supported or port are always powered. It
is implementation- specific. When this bit is cleared,
the PowerSwitchingMode specifies global or per-
port switching.
0: Ports are power switched
1: Ports are always powered on when the HC is
powered on
DT
10
11
0b
1b
R
R
R
DeviceType
This bit specifies that the Root Hub is not a
compound device. The Root Hub is not permitted to
be a compound device. This field should always
read/write 0.
OCPM
RW
OverCurrentProtectionMode
This bit describes how the overcurrent status for the
Root Hub ports are reported. At reset, this field
should reflect the same mode as
PowerSwitchingMode. This field is valid only if the
NoOverCurrentProtection field is cleared.
0: over-current status is reported collectively for all
downstream ports
1: over-current status is reported on a per-port basis
NOCP
12
0b
RW
R
NoOverCurrentProtection
This bit describes how the overcurrent status for the
Root Hub ports are reported. When this bit is cleared,
the OverCurrentProtectionMode field specifies
global or per-port reporting.
0: Over-current status is reported collectively for all
downstream ports
1: No overcurrent protection supported
Reserved
POTPGT
23:13
31:24
Reserved
PowerOnToPowerGoodTime
02h
RW
R
This byte specifies the duration HCD has to wait
before accessing a powered-on port of the Root Hub.
It is implementation-specific. The unit of time is 2 ms.
The duration is calculated as POTPGT * 2 ms.
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HcRhDescriptorB - 32 bits - [MEM_Reg : 4Ch]
Field Name
Bits
Default
HCD
HC
Description
DR
15:0
0000h
RW
R
DeviceRemovable
Each bit is dedicated to a port of the Root Hub. When
cleared, the attached device is removable. When set,
the attached device is not removable.
bit 0: Reserved
bit 1: Device attached to Port #1
bit 2: Device attached to Port #2
...
bit15: Device attached to Port #15
PPCM
31:16
0000h
RW
R
PortPowerControlMask
Each bit indicates if a port is affected by a global
power control command when
PowerSwitchingMode is set. When set, the port's
power state is only affected by per-port power control
(Set/ClearPortPower). When cleared, the port is
controlled by the global power switch
(Set/ClearGlobalPower). If the device is configured
to global switching mode
(PowerSwitchingMode=0), this field is not valid.
bit 0: Reserved
bit 1: Ganged-power mask on Port #1
bit 2: Ganged-power mask on Port #2
...
bit15: Ganged-power mask on Port #15
HcRhStatus - 32 bits - [MEM_Reg : 50h]
Field Name
LPS
Bits
0
Default
HCD
HC
Description
0b
RW
R
(Read) LocalPowerStatus
The Root Hub does not support the local power
status feature; thus, this bit is always read as ‘0’.
(Write) ClearGlobalPower
In global power mode (PowerSwitchingMode=0),
This bit is written to ‘1’ to turn off power to all ports
(Clear)
PortPowerStatus). In per-port power mode, it clears
PortPowerStatus only on ports whose
PortPowerControlMask bit is not set. Writing a ‘0’
has no effect.
OCI
1
0b
0b
R
RW
OverCurrentIndicator
This bit reports overcurrent conditions when the
global reporting is implemented. When set, an
overcurrent condition exists. When cleared, all power
operations are normal. If per-port overcurrent
protection is implemented this bit is always ‘0’
Reserved
(Read) DeviceRemoteWakeupEnable
This bit enables a ConnectStatusChange bit as a
resume event, causing a USBSUSPEND to
USBRESUME state transition and setting the
ResumeDetected interrupt.
Reserved
DRWE
14:2
15
RW
R
0 = ConnectStatusChange is not a remote wakeup
event.
1 = ConnectStatusChange is a remote wakeup
event.
(Write) SetRemoteWakeupEnable
Writing a '1' sets DeviceRemoveWakeupEnable.
Writing a '0' has no effect.
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OCHI USB 1.1 and EHCI USB 2.0 Controllers
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HcRhStatus - 32 bits - [MEM_Reg : 50h]
Field Name
LPSC
Bits
16
Default
HCD
HC
Description
0b
RW
R
(Read) LocalPowerStatusChange
The Root Hub does not support the local power
status feature; thus, this bit is always read as ‘0’.
(Write) SetGlobalPower
In global power mode (PowerSwitchingMode=0),
This bit is written to ‘1’ to turn on power to all ports
(Clear)
PortPowerStatus). In per-port power mode, it sets
PortPowerStatus only on ports whose
PortPowerControlMask bit is not set. Writing a ‘0’
has no effect.
OCIC
17
0b
RW
W
RW
OverCurrentIndicatorChange
This bit is set by hardware when a change has
occurred to the OCI field of this register. The HCD
clears this bit by writing a ‘1’. Writing a ‘0’ has no
effect.
Reserved
CRWE
30:18
31
Reserved
-
R
(Write) ClearRemoteWakeupEnable
Writing a '1' clears DeviceRemoveWakeupEnable.
Writing a '0' has no effect.
HcRhPortStatus - 32 bits - [MEM_Reg : 50h+4*(1:NDP)]
Field Name
CCS
Bits
Default
HCD
HC
Description
(Read) CurrentConnectStatus
This bit reflects the current state of the downstream
port.
0
0b
RW
RW
0 = No device connected
1 = Device connected
(Write) ClearPortEnable
The HCD writes a ‘1’ to this bit to clear the
PortEnableStatus bit.
Writing a ‘0’ has no effect. The
CurrentConnectStatus is not affected by any write.
Note: This bit is always read ‘1b’ when the attached
device is non-removable
(DeviceRemoveable[NDP]).
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HcRhPortStatus - 32 bits - [MEM_Reg : 50h+4*(1:NDP)]
Field Name
PES
Bits
Default
HCD
HC
Description
1
0b
RW
RW
(Read) PortEnableStatus
This bit indicates whether the port is enabled or
disabled. The Root Hub may clear this bit when an
overcurrent condition, disconnect event, switched-off
power, or operational bus error such as babble is
detected. This change also causes
PortEnabledStatusChange to be set. HCD sets this
bit by writing SetPortEnable and clears it by writing
ClearPortEnable. This bit cannot be set when
CurrentConnectStatus is cleared. This bit is also
set, if not already, at the completion of a port reset
when ResetStatusChange is set or port suspend
when SuspendStatusChange is set.
0 = Port is disabled
1 = Port is enabled
(Write) SetPortEnable
The HCD sets PortEnableStatus by writing a ‘1’.
Writing a ‘0’ has no effect. If CurrentConnectStatus
is cleared, this write does not set PortEnableStatus,
but instead sets ConnectStatusChange. This
informs the driver that it attempted to enable a
disconnected port.
PSS
2
0b
RW
RW
(Read) PortSuspendStatus
This bit indicates the port is suspended or in the
resume sequence. It is set by a SetSuspendState
write and cleared when PortSuspendStatusChange
is set at the end of the resume interval. This bit
cannot be set if CurrentConnectStatus is cleared.
This bit is also cleared when
PortResetStatusChange is set at the end of the port
reset or when the HC is placed in the USBRESUME
state. If an upstream resume is in progress, it should
propagate to the HC.
0 = Port is not suspended
1 = Port is suspended
(Write) SetPortSuspend
The HCD sets the PortSuspendStatus bit by writing
a ‘1’ to this bit. Writing a ‘0’ has no effect. If
CurrentConnectStatus is cleared, this write does
not set PortSuspendStatus; instead it sets
ConnectStatusChange. This informs the driver that
it attempted to suspend a disconnected port.
(Read) PortOverCurrentIndicator
POCI
3
0b
RW
RW
This bit is only valid when the Root Hub is configured
in such a way that overcurrent conditions are
reported on a per-port basis. If per-port overcurrent
reporting is not supported, this bit is set to 0. If
cleared, all power operations are normal for this port.
If set, an overcurrent condition exists on this port.
This bit always reflects the overcurrent input signal
0 = No overcurrent condition.
1 = Overcurrent condition detected.
(Write) ClearSuspendStatus
The HCD writes a ‘1’ to initiate a resume. Writing a ‘0’
has no effect. A resume is initiated only if
PortSuspendStatus is set.
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HcRhPortStatus - 32 bits - [MEM_Reg : 50h+4*(1:NDP)]
Field Name
PRS
Bits
Default
HCD
HC
Description
4
0b
RW
RW
(Read) PortResetStatus
When this bit is set by a write to SetPortReset, port
reset signaling is asserted. When reset is completed,
this bit is cleared when PortResetStatusChange is
set. This bit cannot be set if CurrentConnectStatus
is cleared.
0 = Port reset signal is not active
1 = Port reset signal is active
(Write) SetPortReset
The HCD sets the port reset signaling by writing a ‘1’
to this bit. Writing a ‘0’ has no effect. If
CurrentConnectStatus is cleared, this write does
not set PortResetStatus, but instead sets
ConnectStatusChange. This informs the driver that
it attempted to reset a disconnected port.
Reserved
Reserved
PPS
7:5
8
0b
RW
RW
(Read) PortPowerStatus
This bit reflects the port’s power status, regardless of
the type of power switching implemented. This bit is
cleared if an overcurrent condition is detected. HCD
sets this bit by writing SetPortPower or
SetGlobalPower. HCD clears this bit by writing
ClearPortPower or ClearGlobalPower. Which
power control switches are enabled is determined by
PowerSwitchingMode and
PortPortControlMask[NDP]. In global switching
mode, (PowerSwitchingMode=0), only
Set/ClearGlobalPower controls this bit. In per-port
power switching (PowerSwitchingMode=1), if the
PortPowerControlMask[NDP] bit for the port is set,
only Set/ClearPortPower commands are enabled. If
the mask is not set, only Set/ClearGlobalPower
commands are enabled. When port power is
disabled, CurrentConnectStatus,
PortEnableStatus, PortSuspendStatus, and
PortResetStatus should be reset.
0 = Port power is off
1 = Port power is on
(Write) SetPortPower
The HCD writes a ‘1’ to set the PortPowerStatus bit.
Writing a ‘0’ has no effect.
Note: This bit is always reads ‘1b’ if power switching
is not supported.
LSDA
9
X
RW
RW
(Read) LowSpeedDeviceAttached
This bit indicates the speed of the device attached to
this port. When set, a Low Speed device is attached
to this port. When clear, a Full Speed device is
attached to this port. This field is valid only when the
CurrentConnectStatus is set.
0 = Full speed device attached
1 = Low speed device attached
(Write) ClearPortPower
The HCD clears the PortPowerStatus bit by writing a
‘1’ to this bit. Writing a ‘0’ has no effect.
Reserved
Reserved
15:10
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HcRhPortStatus - 32 bits - [MEM_Reg : 50h+4*(1:NDP)]
Field Name
CSC
Bits
Default
HCD
HC
Description
16
0b
RW
RW
ConnectStatusChange
This bit is set whenever a connect or disconnect
event occurs. The HCD writes a ‘1’ to clear this bit.
Writing a ‘0’ has no effect. If CurrentConnectStatus
is cleared when a SetPortReset, SetPortEnable, or
SetPortSuspend write occurs, this bit is set to force
the driver to re-evaluate the connection status since
these writes should not occur if the port is
disconnected.
0 = No change in CurrentConnectStatus
1 = Change in CurrentConnectStatus
Note: If the DeviceRemovable[NDP] bit is set, this
bit is set only after a Root Hub reset to inform the
system that the device is attached.
PESC
PSSC
17
18
0b
0b
RW
RW
RW
RW
PortEnableStatusChange
This bit is set when hardware events cause the
PortEnableStatus bit to be cleared. Changes from
HCD writes do not set this bit. The HCD writes a ‘1’ to
clear this bit. Writing a ‘0’ has no effect.
0 = No change in PortEnableStatus
1 = Change in PortEnableStatus
PortSuspendStatusChange
This bit is set when the full resume sequence has
been completed. This sequence includes the 20-s
resume pulse, LS EOP, and 3-ms resychronization
delay. The HCD writes a ‘1’ to clear this bit. Writing a
‘0’ has no effect. This bit is also cleared when
ResetStatusChange is set.
0 = Resume is not completed
1 = Resume completed
OCIC
19
0b
0b
RW
RW
RW
RW
PortOverCurrentIndicatorChange
This bit is valid only if overcurrent conditions are
reported on a per-port basis. This bit is set when Root
Hub changes the PortOverCurrentIndicator bit. The
HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has no
effect.
0 = No change in PortOverCurrentIndicator
1 = PortOverCurrentIndicator has changed
PortResetStatusChange
PRSC
20
This bit is set at the end of the 10-ms port reset
signal.
The HCD writes a ‘1’ to clear this bit. Writing a ‘0’ has
no effect.
0 = Port reset is not complete
1 = Port reset is complete
Reserved
31:21
Reserved
2.2.2
USB Legacy Keyboard Operation
2.2.2.1 Overview
To support applications and drivers in non-USB-aware environments (e.g., DOS), the Host Controller needs
to provide some amount of hardware support for the emulation of a PS/2 keyboard and/or mouse by their
USB equivalents. For Open HCI, this emulation support is provided by a set of registers that are controlled
by code running in SMM. Working in conjunction, this hardware and software produces approximately the
same behavior-to-application code as would be produced by a PS/2-compatible keyboard and/or mouse
interface.
To minimize hardware impact, the Host Controller accesses a USB keyboard and/or mouse using the
©2008 Advanced Micro Devices, Inc.
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standard OpenHCI descriptor-based accesses. The emulation code sets up the appropriate Endpoint
Descriptors and Transfer Descriptors that cause data to be sent to or received from a USB keyboard/mouse
using the normal USB protocols. When data is received from the keyboard/mouse, the emulation code is
notified and becomes responsible for translating the USB keyboard/mouse data into a data sequence that is
equivalent to what would be produced by a PS/2-compatible keyboard/mouse interface. The translated data
is made available to the system through the legacy keyboard interface I/O addresses at 60h and 64h.
Likewise, when data/control is to be sent to the keyboard (as indicated by the system writing to the legacy
keyboard interface), the emulation code is notified and becomes responsible for translating the information
into appropriate data to be sent to the USB keyboard/mouse through the transfer descriptor mechanism.
On the PS/2 keyboard/mouse interface, a read of I/O port 60h returns the current contents of the keyboard
output buffer; a read of I’O port 64h returns the contents of the keyboard status register. An I/O write to port
60h or 64h puts data into the keyboard input buffer (data is being input into the keyboard subsystem). When
emulation is enabled, reads and writes of registers 60h and 64h are captured in HceOutput, HceStatus,
and/or HceInput operational registers.
The emulation hardware described in this document supports a mixed environment in which either the
keyboard or mouse is located on USB, and the other device is attached to a standard PS/2 interface.
2.2.2.2 System Requirements
The sections below define the system requirements that must be met in order for the OpenHCI legacy
support to function properly.
Host Controller Mapping
The Host Controller uses memory addresses to enable system software to access its operational registers.
In a PCI implementation, the address of the Host Controller operations registers is set in BAR_OHCI. The
address range specified in BAR_OHCI must be accessible to SMM code. The address in BAR_OHCI should
not be modified by any software while the emulation software has control of the Host Controller. The only
exception to this is when the OS is booting and is trying to interrogate the PCI bus. It is common for an OS,
as it is loaded, to enumerate and ‘size’ the various buses on the machine. For a PCI system, the OS typically
writes a value to each card’s BAR to determine the memory space occupied by that card. If emulation is
running during enumeration, the Host Controller may generate an SMI as the OS is changing the BAR from
the value that the emulation code is using.
Intercept Port 60h and 64h Accesses
When emulation is enabled, I/O accesses of I/O ports 60h and 64h must be handled by the Host Controller.
The Host Controller must be positioned in the system so that it can do a positive decode of accesses to I/O
addresses 60h and 64h on the PCI bus. If a keyboard controller is present in the system, it must either use
subtractive decode or have provisions to disable its decode of ports 60h and 64h. If the legacy keyboard
controller uses positive decode and is turned off during emulation, it must be possible for the emulation code
to quickly re-enable and disable the legacy keyboard controller’s 60h and 64h decode. This is necessary to
support a mixed operating environment.
Interrupts
The Host Controller must connect to IRQ1 and IRQ12 on the system board and be wired OR with other non-
legacy IRQ1 and IRQ12 sources. IRQ1 and IRQ12 from the legacy keyboard controller (if present) must be
routed through the Host Controller.
Run-time Memory
Legacy emulation requires that the Host Controller have read/write access to a portion of system memory
that is not used by a system OS for any purpose. In addition, this memory must be accessible by the host
CPU while the host CPU is in SMM.
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2.2.2.3 Programming Interface
The following modification is needed for the HcRevision register:
Table 2-1 HcRevision Register
HcRevision - 32 bits
Field Name
Revision
Bits
7:0
Reset
10h
HCD
HC
Description
R
R
This read-only field contains the BCD representation
of the version of the HCI specification that is
implemented by this HC. For example, a value of 11h
corresponds to version 1.1. All of the HC
implementations that are compliant with this
specification will have a value of 10h.
This read-only field is 1 to indicate that the legacy
support registers are present in this HC.
Reserved
Legacy
8
1b
R
R
Reserved
31:9
Legacy Support Registers
Four operational registers are used to provide the legacy support. Each of these registers is located on a 32-
bit boundary. The offset of these registers is relative to the base address of the Host Controller operational
registers with HceControl located at offset 100h.
Table 2-2 Legacy Support Registers
Offset
Register
Description
100h
HceControl
Used to enable and control the emulation hardware and report various status
information.
104h
108h
10Ch
HceInput
The emulation side of the legacy Input Buffer register.
HceOutput
HceStatus
The emulation side of the legacy Output Buffer register where the keyboard and
mouse data is to be written by software.
The emulation side of the legacy Status register.
Three of the operational registers (HceStatus, HceInput, HceOutput) are accessible at I/O address 60h and
64h when emulation is enabled. Reads and writes to the registers using I/O addresses have side effects as
Table 2-3 Emulated Registers
I/O
Address
Cycle Type Register Contents
Accessed/Modified
Side Effects
60h
60h
64h
64h
IN
HceOutput
HceInput
HceStatus
HceInput
IN from port 60h will set OutputFull in
HceStatus to 0
OUT
IN
OUT to port 60h will set InputFull to 1 and
CmdData to 0 in HceStatus.
IN from port 64h returns current value of
HceStatus with no other side effect.
OUT
OUT to port 64h will set InputFull to 0 and
CmdData in HceStatus to 1.
HceInput Register
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Table 2-4 HceInput Registers
HceInput – RW - 32 bits
Field Name
InputData
Reserved
Bits
7:0
31:8
Default
00h
Description
This register holds data that is written to I/O ports 60h and 64h.
Reserved
I/O data that is written to ports 60h and 64h is captured in this register when emulation is enabled. This
register may be read or written directly by accessing it with its memory address in the Host Controller’s
operational register space. When accessed directly with a memory cycle, reads and writes of this register
have no side effects.
HceOutput Register
Table 2-5 HceOutput Register
HceOutput – RW - 32 bits
Description
This register hosts data that is returned when an I/O read of port 60h
is performed by application software.
Reserved
Field Name
OutputData
Bits
7:0
Default
00h
Reserved
31:8
The data placed in this register by the emulation software is returned when I/O port 60h is read and
emulation is enabled. On a read of this location, the OutputFull bit in HceStatus is set to 0.
HceStatus Register
Table 2-6 HceStatus Register
HceStatus – RW - 32 bits
Field Name
Bits
Default
Description
OutputFull
0
0b
The HC sets this bit to 0 on a read of I/O port 60h. If IRQEn is set and
AuxOutputFull is set to 0, then an IRQ1 is generated as long as this bit
is set to 1. If IRQEn is set and AuxOutputFull is set to 1, then an IRQ12
is generated as long as this bit is set to 1. While this bit is 0 and
CharacterPending in HceControl is set to 1, an emulation interrupt
condition exists.
InputFull
1
0b
Except for the case of a Gate A20 sequence, this bit is set to 1 on an
I/O write to address 60h or 64h. While this bit is set to 1 and emulation
is enabled, an emulation interrupt condition exists.
Nominally used as a system flag by software to indicate a warm or cold
boot.
The HC sets this bit to 0 on an I/O write to port 60h and to 1 on an I/O
write to port 64h.
This bit reflects the state of the keyboard inhibit switch and is set if the
keyboard is NOT inhibited.
Flag
2
3
4
5
0b
0b
0b
0b
CmdData
Inhibit Switch
AuxOutputFull
IRQ12 is asserted whenever this bit is set to 1 and OutputFull is set to 1
and the IRQEn bit is set.
Time-out
Parity
Reserved
6
7
31:8
0b
0b
Used to indicate a time-out
Indicates parity error on keyboard/mouse data.
Reserved
The contents of the HceStatus Register are returned on an I/O Read of port 64h when emulation is enabled.
Reads and writes of port 60h and writes to port 64h can cause changes in this register. Emulation software
can directly access this register through its memory address in the Host Controller’s operational register
space. Accessing this register through its memory address produces no side effects.
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HceControl Register
Table 2-7 HceControl Register
HceControl - 32 bits
Field Name
Bits
Reset
Description
EmulationEnable
0
0b
When set to 1, the HC is enabled for legacy emulation.
The HC decodes accesses to I/O registers 60h and 64h and
generates IRQ1 and/or IRQ12 when appropriate.
Additionally, the HC generate s an emulation interrupt at
appropriate times to invoke the emulation software.
This bit is a static decode of the emulation interrupt
condition. [Read-only]
When set, an emulation interrupt is generated when the
OutputFull bit of the HceStatus register is set to 0.
When set, the HC generates IRQ1 or IRQ12 as long as the
OutputFull bit in HceStatus is set to 1. If the
EmulationInterrupt
CharacterPending
IRQEn
1
2
3
-
0b
0b
AuxOutputFull bit of HceStatus is 0, then IRQ1 is
generated; if it is 1, then an IRQ12 is generated.
When set to 1, IRQ1 and IRQ12 from the keyboard
controller causes an emulation interrupt. The function
controlled by this bit is independent of the setting of the
EmulationEnable bit in this register.
ExternalIRQEn
4
0b
GateA20Sequence
IRQ1Active
IRQ12Active
A20State
5
6
0b
0b
0b
0b
-
Set by HC when a data value of D1h is written to I/O port
64h. Cleared by HC on write to I/O port 64h of any value
other than D1h.
Indicates that a positive transition on IRQ1 from keyboard
controller has occurred. SW may write a 1 to this bit to
clear it (set it to 0). SW write of a 0 to this bit has no effect.
Indicates that a positive transition on IRQ12 from keyboard
controller has occurred. SW may write a 1 to this bit to
clear it (set it to 0). SW write of a 0 to this bit has no effect.
Indicates current state of Gate A20 on keyboard controller.
Used to compare against value written to 60h when
GateA20Sequence is active.
7
8
Reserved
31:9
Must read as 0s.
2.2.3
EHCI Registers (Device 19, Function 5)
The Enhanced USB Host Controller contains two sets of software accessible hardware registers—Memory-
mapped Host Controller Registers and optional PCI configuration registers (PCI_Reg).
Mapping into non-cacheable memory, Memory-mapped USB Host Controller Registers consists of a set of
read-only Capability registers (MEM_Reg) , a set of read/write operational registers(EOR_Reg) and a set of
read/write Debug Port registers (DBUG_Reg). Implemented as memory-mapped I/O space, the operational
registers are 32 bits in length and should be read and written as Dwords.
2.2.3.1 PCI Configuration Registers
Registers Name
Device / Vendor ID
Command
Offset Address
00h
04h
06h
08h
0Ch
Status
Revision ID / Class Code
Miscellaneous
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Base Address – BAR_EHCI
Subsystem ID / Subsystem Vendor ID
Capability Pointer
Interrupt Line
EHCI Misc Control
Serial Bus Release Number – SBRN
Frame Length Adjustment – FLADJ
PME Control
10h
2Ch
34h
3Ch
50h
60h
61h
C0h
C4h
PME Data / Status
MSI Control
MSI Address
D0h
D4h
MSI Data
D8h
EHCI Debug Port Support
E4h
USB Legacy Support Extended Capability – USBLEGSUP
USB Legacy Support Control/Status - USBLEGCTLSTS
1The EECP field is in the read-only HCCPARAMS register [MEM_Reg: 08h] with the value of A0h.
EECP+0h1
EECP+4h1
DEVICE / VENDOR ID – R - 32 bits - [PCI_Reg : 00h]
Field Name
VEND_ID
DEV_ID
Bits
15:0
31:16
Default
Description
1002h
Function 5: 4386h
Vendor ID
Device ID
Command – RW - 16 bits - [PCI_Reg : 04h]
Field Name
IO Space Accesses
Bits
Default
Description
0
0b
A value of 0 disables the device response.
A value of 1 allows the device to respond to I/O Space
accesses.
Memory Space Accesses
Bus Master
1
2
0b
0b
A value of 0 disables the device response.
A value of 1 allows the device to respond to Memory Space
accesses.
A value of 0 disables the device from generating PCI
accesses.
A value of 1 allows the device to behave as a bus master.
Hard-wired to 0, indicating no Special Cycle support.
When it is 0, Memory Write must be used.
When it is 1, masters may generate the command.
Hard-wired to 0, indicating the device should treat palette
write accesses like all other accesses.
When it is 1, the device must take its normal action when a
parity error is detected.
Special Cycle
3
4
0b
0b
Memory Write and
Invalidate Command
VGA Palette Register
Accesses
5
6
0b
0b
Parity Enable
When it is 0, the device sets its Detected Parity Error status
bit (bit 15 in the Status register) when an error is detected,
but does not assert PERR# and continues normal operation.
Hard-wired to 0 per PCI2.3 spec.
A value of 0 disables the SERR# driver.
A value of 1 enables the SERR# driver.
Address parity errors are reported only if this bit and bit [6]
are 1.
Reserved
SERR# Enable
7
8
0b
0b
Fast Back-to-Back Enable
Interrupt Disable
Reserved
9
0b
0b
A value of 0 means fast back-to-back transactions to the
same agent only are allowed.
A value of 1 means the master is allowed to generate fast
back-to-back transactions to different agents.
A value of 0 enables the assertion of the device/function’s
INTx# signal.
A value of 1 disables the assertion of the device/function’s
INTx# signal.
Reserved
10
15:11
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Status – R - 16 bits - [PCI_Reg : 06h]
Field Name
Reserved
Interrupt Status
Bits
Default
Description
2:0
3
Reserved
0b
This bit reflects the state of the interrupt in the
device/function. Only when the Interrupt Disable bit in the
command register is a 0 and this Interrupt Status bit is a 1,
will the device’s/function’s INTx# signal be asserted. Setting
the Interrupt Disable bit to a 1 has no effect on the state of
this bit.
Capabilities List
4
1b
A value of 0 indicates that no New Capabilities linked list is
available.
A value of 1 indicates that the value read at offset 34h is a
pointer in Configuration Space to a linked list of new
capabilities.
66 MHz Capable
Reserved
Fast Back-to-Back
Capable
5
6
7
1b
1b
0b
Hard-wired to 1, indicating 66MHz capable.
Reserved
Hard-wired to 1, indicating Fast Back-to-Back capable.
Master Data Parity Error
8
This bit is set only when three conditions are met: 1) the bus
agent asserted PERR# itself (on a read) or observed PERR#
asserted (on a write); 2) the agent setting the bit acted as the
bus master for the operation in which the error occurred; and
3) the Parity Error Response bit (Command register) is set.
Hard-wired to 01b – medium timing
DEVSEL timing
Signaled Target Abort
10:9
11
01b
0b
This bit is set by a target device whenever it terminates a
transaction with Target-Abort.
Received Target Abort
Received Master Abort
12
13
0b
0b
This bit is set by a master device whenever its transaction is
terminated with Target-Abort.
This bit is set by a master device whenever its transaction
(except for Special Cycle) is terminated with Master-Abort.
This bit is set whenever the device asserts SERR#.
This bit is set by the device whenever it detects a parity error,
even if parity error handling is disabled (as controlled by bit 6
in the Command register).
Signaled System Error
Detected Parity Error
14
15
0b
0b
Revision ID / Class Code – R - 32 bits - [PCI_Reg : 08h]
Field Name
Revision ID
PI
Bits
Default
Description
7:0
00h
Revision ID.
15:8
20h
Programming Interface. A constant value of ‘20h’ indentifies
the device being an EHCI Host Controller.
SC
BC
23:16
31:24
03h
0Ch
Sub Class. A constant value of ‘03h’ indentifies the device
being of Universal Serial Bus.
Base Class. A constant value of ‘0Ch’ identifies the device
being a Serial Bus Controller.
Miscellaneous – RW - 32 bits - [PCI_Reg : 0Ch]
Field Name
Bits
Default
Description
Cache Line Size
7:0
00h
This read/write field specifies the system cacheline size in
units of DWORDs and must be initialized to 00h.
[9:8] hard-wired to 00b, resulting in a timer granularity of at
least four clocks. This field specifies, in units of PCI bus
clocks, the value of the Latency Timer for this PCI bus
master.
Latency Timer
15:8
00h
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Miscellaneous – RW - 32 bits - [PCI_Reg : 0Ch]
Field Name
Header Type
Bits
Default
Description
23:16
00h
This field identifies the layout of the second part of the
predefined header (beginning at byte 10h in Configuration
Space) and also whether or not the device contains multiple
functions.
EHCI has single function and bit[23:16] hard-wired to 00h.
Read Only.
BIST
31:24
00h
Hard-wired to 00h, indicating no build-in BIST support.
BAR_EHCI – RW - 32 bits - [PCI_Reg : 10h]
Field Name
Bits
Default
Description
Indicator. A constant value of ‘0’ indicates that the
operational registers of the device are mapped into memory
space of the main memory of the PC host system.
Read Only.
IND
TP
0
0b
2:1
3
0h
0b
Type. A constant value of ‘00b’ indicates that the base
register is 32-bit wide and can be placed anywhere in the
32-bit memory space; i.e., lower 4 GB of the main memory
of the PC host.
Read Only.
PM
Prefetch Memory. A constant value of ‘0’ indicates that
there is no support for “prefetchable memory”.
Read Only.
Reserved
BA
7:4
31:8
0h
0h
Read Only.
Base Address. Corresponds to memory address signals
[31:8].
BAR register. Base address used for the memory mapped capability and operational registers.
Subsystem ID / Subsystem Vendor ID – RW - 32 bits - [PCI_Reg : 2Ch]
Field Name
Subsystem Vendor ID
Subsystem ID
Bits
15:0
31:16
Default
0000h
0h
Description
Can only be written once by software.
Can only be written once by software.
Capability Pointer – R - 8 bits - [PCI_Reg : 34h]
Field Name
Capability Pointer
Bits
Default
Description
7:0
C0h
Address of the 1st element of capability link.
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Interrupt Line - RW - 32 bits - [PCI_Reg : 3Ch]
Field Name
Interrupt Line
Bits
Default
Description
7:0
00h
The Interrupt Line is a field used to communicate interrupt
line routing information. The register is read/write and must
be implemented by any device (or device function) that uses
an interrupt pin. POST software will write the routing
information into this register as it initializes and configures
the system.
The value in this field tells which input of the system
interrupt controller(s) the device's interrupt pin is connected
to. The device itself does not use this value; rather it is used
by device drivers and operating systems. Device drivers
and operating systems can use this information to determine
priority and vector information. Values in this register are
system architecture specific.
Interrupt Pin
MIN_GNT
MAX_LAT
15:8
23:16
31:24
04h
00h
00h
Read Only by default.
Hard-wired to 04h, which corresponds to using INTD#.
Read Only. Hard-wired to 00h to indicate no major
requirements for the settings of Latency Timers.
Read Only. Hard-wired to 00h to indicate no major
requirements for the settings of Latency Timers.
EHCI Misc Control – RW - 32 bits - [PCI_Reg : 50h]
Field Name
Reserved
PME Disable
MSI Disable
Reserved
Bits
4:0
5
Default
00h
0b
0b
000h
Eh
Description
Reserved
Set to 1 to disable EHCI PME support
Set to 1 to disable EHCI MSI support
Reserved
6
15:7
19:16
Cache Timer Control
Control the purge timeout timer if HC doesn't come back to
request the data.
Counter
Max Time (ns)
45
Min Time (ns)
0
1
2
3
4
5
6
7
8
9
30
60
90
180
120
360
240
720
480
1440
960
2880
1920
3840
7680
5760
11520
23040
46080
92160
184320
368640
737280
No limit
15360
30720
A
B
C
D
E
F
61440
122880
245760
491520
Cache Prefetch Disable
20
0b
0b
0: Enable EHCI cache prefetch.
1: Disable EHCI cache prefetch.
Reserved
Disable Async QH Cache
on IN xfer
23:21
24
Set to 1 to disable async QH/QTD cache during IN xfer.
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EHCI Misc Control – RW - 32 bits - [PCI_Reg : 50h]
Field Name
Disable Async QH Cache
on OUT xfer
Bits
Default
Description
25
0b
Set to 1 to disable async QH/QTD cache during OUT xfer.
Disable Async Data
Cache
Disable Periodic List
Cache
26
27
0b
0b
0h
Set to 1 to disable async data cache request.
Set to 1 to disable periodic list cache.
Reserved
Reserved
31:28
SBRN – R - 8 bits - [PCI_Reg : 60h]
Default Description
Field Name
Bits
SBRN
7:0
20h
Hard-wired to 20h.
FLADJ – RW - 8 bits - [PCI_Reg : 61h]
Field Name
Bits
Default
Description
FLADJ
5:0
20h
Frame Length Timing Value. Each decimal value change to
this register corresponds to 16 high-speed
bit times. The SOF cycle time (number of SOF counter clock
periods to generate a SOF micro-frame length) is equal to
59488 + value in this field. The default value is decimal 32
(20h), which gives a SOF cycle time of 60000.
FLADJ Value in decimals
[hexadecimal value]
Frame Length
(# High Speed bit
times in decimals)
59488
0 [00h]
1 [01h]
59504
2 [02h]
59520
…
…
31 [1Fh]
32 [20h]
…
59984
60000
…
62 [3Eh]
63 [3Fh]
Reserved.
60480
60496
Reserved
7:6
PME Control – RW - 32 bits - [PCI_Reg : C0h]
Field Name
Bits
Default
Description
Cap_ID
7:0
01h
Read only.
A value of “01h” identifies the linked list item as being the
PCI Power Management registers.
Next ItemPointer
Version
15:8
D0h
Read only.
This field provides an offset into the function’s PCI
Configuration Space pointing to the location of next item in
the function’s capability list. If there are no additional items
in the Capabilities List, this register is set to 00h.
Read only.
A value of “010b” indicates that this function complies with
Revision 1.1 of the PCI Power Management Interface
Specification.
18:16
010b
0b
PME clock
Reserved
19
20
Read only.
When this bit is a “0”, it indicates that no PCI clock is
required for the function to generate PME#.
Reserved
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PME Control – RW - 32 bits - [PCI_Reg : C0h]
Field Name
Bits
Default
Description
DSI
21
0b
Read only.
The Device Specific Initialization bit indicates whether
special initialization of this function is required (beyond the
standard PCI configuration header) before the generic class
device driver is able to use it.
Aux_Current
24:22
000b
Read only.
This 3 bit field reports the 3.3Vaux auxiliary current
requirements for the PCI function.
If the Data Register has been implemented by this function:
• Reads of this field must return a value of “000b”.
• The Data Register takes precedence over this field for
3.3Vaux current requirement reporting.
D1_Support
D2_Support
PME_Support
25
26
1b
1b
If this bit is a “1”, this function supports the D1
Power Management State.
If this bit is a “1”, this function supports the D2
Power Management State.
31:27
0Fh
Read only.
This 5-bit field indicates the power states in which the
function may assert PME#. A value of 0b for any bit
indicates that the function is not capable of asserting the
PME# signal while in that power state.
bit(31) 1XXXXb - PME# can be asserted from D3cold bit(30)
X1XXXb - PME# can be asserted from D3hot
bit(29) XX1XXb - PME# can be asserted from D2
bit(28) XXX1Xb - PME# can be asserted from D1
bit(27) XXXX1b - PME# can be asserted from D0
PME Data / Status – RW - 32 bits - [PCI_Reg : C4h]
Field Name
Bits
Default
Description
PowerState
1:0
00b
This 2-bit field is used both to determine the current power
state of a function and to set the function into a new power
state. The definition of the field values is given below.
00b - D0
01b - D1
10b - D2
11b - D3hot
If software attempts to write an unsupported, optional state to
this field, the write operation must be completed normally on
the bus; however, the data is discarded and no state change
occurs.
Reserved
PME_En
7:2
8
Reserved
0b
A “1” enables the function to assert PME#. When “0”, PME#
assertion is disabled. This bit defaults to “0” if the function
does not support PME# generation from D3cold.
This 4-bit field is used to select which data is to be reported
through the Data register and Data_Scale field.
This 2-bit read-only field indicates the scaling factor to be
used when interpreting the value of the Data register. The
value and meaning of this field will vary depending on which
data value has been selected by the Data_Select field.
This bit is set when the function would normally assert the
PME# signal independent of the state of the PME_En bit.
Reserved
Data_Select
Data_Scale
12:9
0000b
00b
14:13
PME_Status
Reserved
15
0b
21:16
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PME Data / Status – RW - 32 bits - [PCI_Reg : C4h]
Field Name
B2_B3#
Bits
Default
Description
22
1b
Read only.
The state of this bit determines the action that is to occur as a
direct result of programming the function to D3hot.. A “1”
indicates that when the bridge function is programmed to
D3hot, its secondary bus’s PCI clock will be stopped (B2).
Read only.
A “0” indicates that the bus power/clock control policies are
disabled. When the Bus Power/Clock Control mechanism is
disabled, the bridge’s PMCSR PowerState field cannot be
used by the system software to control the power or clock of
the bridge’s secondary bus.
BPCC_En
Data
23
0b
31:24
00h
Read only.
This register is used to report the state dependent data
requested by the Data_Select field. The value of this register
is scaled by the value reported by the Data_Scale field.
MSI Control – RW - 32 bits - [PCI_Reg : D0h]
Field Name
MSI USB
Next Item Pointer
MSI Control Out
Reserved
Bits
7:0
Default
05h
E4h
0b
Description
MSI USB ID. Read only.
Pointer to next capability structure
Set to 1 to disable IRQ. Use MSI instead.
Reserved
15:8
16
19:17
22:20
23
0h
MSI Control
64-bit Address Capable
0h
MSI control field
0b
If EHCI is in 64 bit address mode as specified by 64-bit
Addressing Capability bit in HCCPARAMS register [MEM
Reg: 08h] , this bit is set to 1 indicating that EHCI is capable
of generating a 64-bit message address. Otherwise it is set
to 0 indicating the EHCI is not capable of generating a 64-bit
address.
Read only
Reserved
31:24
00h
Reserved
MSI Address – RW - 32 bits - [PCI_Reg : D4h]
Field Name
Bits
Default
Description
MSI Address
31:0
0h
System-specified message address.
MSI Data – RW - 16 bits - [PCI_Reg : D8h]
Field Name
Bits
Default
Description
MSI Data
15:0
0h
System-specified message
DBUG_PRT Control – R - 32 bits - [PCI_Reg : E4h]
Field Name
Bits
Default
Description
CAP_ID
7:0
0Ah
The value of 0Ah in this field identifies that the function
supports a Debug Port.
Next Item Pointer
Offset
15:8
28:16
00h
0E0h
Pointer to next capability structure
This 12 bit field indicates the byte offset (up to 4K) within the
BAR indicated by BAR#. This offset is required to be
DWORD aligned and therefore bits 16 and 17 are always
zero.
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OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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Page 77
DBUG_PRT Control – R - 32 bits - [PCI_Reg : E4h]
Field Name
Bits
Default
Description
Bar #
31:29
1h
A 3-bit field, which indicates which one of the possible 6
Base Address Register offsets, contains the Debug Port
registers. For example, a value of 1h indicates the first BAR
(offset 10h) while a value of 5 indicates that the BAR at 20h.
This offset is independent as to whether the BAR is 32 or 64
bit. For example, if the offset were 3 indicating that the BAR
at offset 18h contains the Debug Port. BARs at offset 10 and
14h may or may not be implemented. This field is read only
and only values 1-6h are valid. (A 64-bit BAR is allowed.)
Only a memory BAR is allowed.
USBLEGSUP – RW - 32 bits - [PCI_Reg : EECP + 00h]
Field Name
Bits
Default
Description
Capability ID
7:0
01h
This field identifies the extended capability. A value of 01h
identifies the capability as Legacy Support. This extended
capability requires one additional 32-bit register for
control/status information, and this register is located at
offset EECP+04h.
Read Only.
Next EHCI Extended
Capability Pointer
15:8
16
00h
0b
This field points to the PCI configuration space offset of the
next extended capability pointer. A value of 00h indicates
the end of the extended capability list.
Read Only.
HC BIOS Owned
Semaphore
The BIOS sets this bit to establish ownership of the EHCI
controller. System BIOS will set this bit to a zero in
response to a request for ownership of the EHCI controller
by system software.
Reserved
HC OS Owned Semaphore
23:17
24
These bits are reserved and must be set to zero.
System software sets this bit to request ownership of the
EHCI controller. Ownership is obtained when this bit reads
as one and the HC BIOS Owned Semaphore bit reads as 0.
These bits are reserved and must be set to zero.
0b
Reserved
31:25
USBLEGCTLSTS – RW - 32 bits - [PCI_Reg : EECP + 04h]
Field Name
Bits
Default
Description
USB SMI Enable
0
0b
When this bit is a one, and the SMI on USB Complete bit
(above) in this register is a one, the host controller will issue
an SMI immediately.
SMI on USB Error Enable
1
2
0b
0b
0b
0b
0b
When this bit is a one, and the SMI on USB Error bit (above)
in this register is a one, the host controller will issue an SMI
immediately.
When this bit is a one, and the SMI on Port Change Detect
bit (above) in this register is a one, the host controller will
issue an SMI immediately.
When this bit is a one, and the SMI on Frame List Rollover
bit (above) in this register is a one, the host controller will
issue an SMI immediately.
When this bit is a one, and the SMI on Host System Error bit
(above) in this register is a one, the host controller will issue
an SMI immediately.
SMI on Port Change
Enable
SMI on Frame List Rollover
Enable R/W
3
SMI on Host System Error
Enable
4
SMI on Async Advance
Enable
5
When this bit is a one, and the SMI on Async Advance bit
(above) in this register is a one, the host controller will issue
an SMI immediately.
Reserved.
12:6
These bits are reserved and must be set to zero.
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OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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USBLEGCTLSTS – RW - 32 bits - [PCI_Reg : EECP + 04h]
Field Name
SMI on OS Ownership
Enable
SMI on PCI Command
Enable
Bits
Default
Description
13
0b
When this bit is a one AND the OS Ownership Change bit is
one, the host controller will issue an SMI.
When this bit is one and SMI on PCI Command is one, then
the host controller will issue an SMI.
When this bit is one and SMI on BAR is one, then the host
controller will issue an SMI.
Shadow bit of USB Interrupt (USBINT) bit in the USBSTS
register. To set this bit to a zero, system software must
write a one to the USB Interrupt bit in the USBSTS register.
Read Only.
14
15
16
0b
0b
0b
SMI on BAR Enable
SMI on USB Complete
SMI on USB Error
17
0b
Shadow bit of USB Error Interrupt (USBERRINT) bit in the
USBSTS register. To set this bit to a zero, system software
must write a one to the USB Error Interrupt bit in the
USBSTS register.
Read Only.
SMI on Port Change
Detect.
18
19
20
21
0b
0b
0b
0b
Shadow bit of Port Change Detect bit in the USBSTS
register. To set this bit to a zero, system software must write
a one to the Port Change Detect bit in the USBSTS register.
Read Only.
Shadow bit of Frame List Rollover bit in the USBSTS
register. To set this bit to a zero, system software must write
a one to the Frame List Rollover bit in the USBSTS register.
Read Only.
Shadow bit of Host System Error bit in the USBSTS register.
To set this bit to a zero, system software must write a one to
the Host System Error bit in the USBSTS register.
Read Only.
Shadow bit of the Interrupt on Async Advance bit in the
USBSTS register. To set this bit to a zero, system software
must write a one to the Interrupt on Async
Advance bit in the USBSTS register.
SMI on Frame List Rollover
SMI on Host System Error
SMI on Async Advance
Read Only.
Reserved.
SMI on OS Ownership
Change
28:22
29
These bits are reserved and must be set to zero.
This bit is set to one whenever the HC OS Owned
Semaphore bit in the USBLEGSUP register transitions from
1 to 0 or 0 to 1.
0b
SMI on PCI Command
30
31
0b
0b
This bit is set to one whenever the PCI Command Register
is written.
This bit is set to one whenever the Base Address Register
(BAR) is written.
SMI on BAR R/WC
2.2.3.2 Host Controller Capability Registers (MEM_Reg)
This block of registers is memory-mapped. Access address is equal to offset address plus base address defined in
BAR[PCI_Reg : 10h].
Registers Name
Capability Register Length - CAPLENGTH
Reserved
Offset Address
00h
01h
02h
04h
08h
0Ch
Host Controller Interface Version – HCIVERSION
Structural Parameters – HCSPARAMS
Capability Parameters - HCCPARMAS
Companion Port Route Description – HCSP-PORTROUTE
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CAPLENGTH – R - 8 bits - [MEM_Reg : 00h]
Description
This register is used as an offset to add to register base to find the beginning of the Operational Register Space.
Default value = 20h.
HCIVERSION – R - 16 bits - [MEM_Reg : 02h]
Field Name
HCIVERSION
Bits
Default
Description
15:0
0100h
This is a two-byte register containing a BCD encoding of the
version number of interface to which this host controller
interface conforms.
HCSPARAMS – R - 32 bits - [MEM_Reg : 04h]
Field Name
N_PORTS
Bits
Default
Description
3:0
Ah
This field specifies the number of physical downstream ports
implemented on this host controller. The value of this field
determines how many port registers are addressable in the
Operational Register Space. Valid values are in the range
of 1H to FH. A zero in this field is undefined.
Port Power Control (PPC)
4
0b
0b
This field indicates whether the host controller
implementation includes port power control. A one in this bit
indicates the ports have port power switches. A zero in this
bit indicates the port does not have port power switches.
The value of this field affects the functionality of the Port
Power field in each port status and control register.
These bits are reserved and should be set to zero.
This field indicates the method used by this implementation
for how all ports are mapped to companion controllers. The
value of this field has the following interpretation:
0 = The first N_PCC ports are routed to the lowest
numbered function companion host controller, the next
N_PCC port are routed to the next lowest function
companion controller, and so on.
Reserved
Port Routing Rules
6:5
7
1 = The port routing is explicitly enumerated by the first
N_PORTS elements of the HCSP-PORTROUTE array.
This field indicates the number of ports supported per
companion host controller. It is used to indicate the port
routing configuration to system software. For example, if
N_PORTS has a value of 6 and N_CC has a value of 2 then
N_PCC could have a value of 3. The convention is that the
first N_PCC ports are assumed to be routed to companion
controller 1, the next N_PCC ports to companion controller
2, etc. In the previous example, the N_PCC could have
been 4, where the first 4 are routed to companion controller
1 and the last two are routed to companion controller 2. The
number in this field must be consistent with N_PORTS and
N_CC.
Number of Ports per
Companion Controller
(N_PCC)
11:8
2h
Number of Companion
Controller (N_CC)
15:12
5h
This field indicates the number of companion controllers
associated with this USB 2.0 host controller. A zero in this
field indicates there are no companion host controllers.
Port-ownership hand-off is not supported. Only high-speed
devices are supported on the host controller root ports. A
value larger than zero in this field indicates there are
companion USB 1.1 host controller(s). Port-ownership
hand-offs are supported. High, Full- and Low-speed devices
are supported on the host controller root ports.
Port Indicators
(P_INDICATOR)
16
0b
This bit indicates whether the ports support port indicator
control. When this bit is a one, the port status and control
registers include a read/writeable field for controlling the
state of the port indicator.
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OCHI USB 1.1 and EHCI USB 2.0 Controllers
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HCSPARAMS – R - 32 bits - [MEM_Reg : 04h]
Field Name
Reserved
Debug Port Number
Bits
19:17
23:20
Default
Description
These bits are reserved and should be set to zero.
Optional. This register identifies which of the host controller
ports is the debug port. The value is the port number (one-
based) of the debug port. A non-zero value in this field
indicates the presence of a debug port. The value in this
register must not be greater than N_PORTS.
1h
Reserved
31:24
These bits are reserved and should be set to zero.
HCCPARAMS – R - 32 bits - [MEM_Reg : 08h]
Field Name
64-bit Addressing
Capability
Bits
Default
Description
0
0b
This field documents the addressing range capability of this
implementation.
0 = Data structures using 32-bit address memory pointers
1 = Data structures using 64-bit address memory pointers
If this bit is set to a zero, then system software must use a
frame list length of 1024 elements with this host controller.
The USBCMD register Frame List Size field is a read-only
register and should be set to zero. If set to a one, then
system software can specify and use a smaller frame list
and configure the host controller via the USBCMD register
Frame List Size field. The frame list must always be aligned
on a 4K page boundary. This requirement ensures that the
frame list is always physically contiguous.
Programmable Frame List
Flag
1
1b
Asynchronous Schedule
Park Capability
2
0b
1h
If this bit is set to a one, then the host controller supports the
park feature for high-speed queue heads in the
Asynchronous Schedule. The feature can be disabled or
enabled and set to a specific level by using the
Asynchronous Schedule Park Mode Enable and
Asynchronous Schedule Park Mode Count fields in the
USBCMD register.
These bits are reserved and should be set to zero.
This field indicates, relative to the current position of the
executing host controller, where software can reliably
update the isochronous schedule. When bit [7] is zero, the
value of the least significant 3 bits indicates the number of
micro-frames a host controller can hold a set of isochronous
data structures (one or more) before flushing the state.
When bit [7] is a one, then host software assumes the host
controller may cache an isochronous data structure for an
entire frame.
Reserved
Isochronous Scheduling
Threshold
3
7:4
EHCI Extended
Capabilities Pointer (EECP)
15:8
A0h
This optional field indicates the existence of a capabilities
list. A value of 00h indicates no extended capabilities are
implemented. A non-zero value in this register indicates the
offset in PCI configuration space of the first EHCI extended
capability. The pointer value must be 40h or greater if
implemented to maintain the consistency of the PCI header
defined for this class of device.
Reserved
31:16
These bits are reserved and should be set to zero.
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OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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HCSP-PORTROUTE – R - 60 bits - [MEM_Reg : 0Ch]
Description
This optional field is valid only if Port Routing Rules field in the HCSPARAMS register is set to a one. This field is a
15-element nibble array (each 4 bits is one array element). Each array location corresponds one-to-one with a
physical port provided by the host controller.
2.2.3.3 Host Controller Operational Registers (EOR_Reg)
This block of registers is memory-mapped. The base offset, EHCI_EOR, is defined in CAPLENGTH register
(MEM_Reg: 00h, default value = 20h).
Registers Name
USB Command – USBCMD
USB Satus – USBSTS
Offset Address
EHCI_EOR + 00h
EHCI_EOR + 04h
EHCI_EOR + 08h
EHCI_EOR + 0Ch
EHCI_EOR + 10h
EHCI_EOR + 14h
EHCI_EOR + 18h
EHCI_EOR + (1Ch~3Fh)
EHCI_EOR + 40h
EHCI_EOR + (44h~68h)
EHCI_EOR + 84h
EHCI_EOR + 88h
EHCI_EOR + 8Ch
EHCI_EOR + 90h
EHCI_EOR + 94h
EHCI_EOR + 98h
EHCI_EOR + 9Ch
EHCI_EOR + A0h
EHCI_EOR + A8h
0E0h~0F0h (* Note)
USB Interrupt Enable – USBINTR
USB Frame Index – FRINDEX
4G Segment Selector – CTRLDSSEGMENT
Frame List Base Address – PERIODICLISTBASE
Next Asynchronous List Address – ASYNCLISTADDR
Reserved
Configured Flag – CONFIGFLAG
Port Status/Control – PORTSC (1-N_PORTS)
Packet Buffer Threshold Values
USB PHY Status 0
USB PHY Status 1
USB PHY Status 2
UTMI Control
Bist Control / Loopback Test
EOR MISC Control
USB Phy Calibration
EOR Debug Purpose
USB Debug Port
The base offset of Debug Port registers is defined directly in DBUG_PRT Control register (EHCI_PCI_CFG xE4[28:16]),
regardless of the value in CAPLENGTH register (MEM_Reg: 00h) so range is equivalent to EHCI_EOR + (C0h~D0h).
USBCMD – RW - 32 bits - [EOR_Reg : EHCI_EOR + 00h]
Field Name
Bits
Default
Description
Run/Stop (RS)
0
0b
1=Run, 0=Stop.
When set to a 1, the Host Controller proceeds with execution of the
schedule. The Host Controller continues execution as long as this bit is
set to a 1. When this bit is set to 0, the Host Controller completes the
current and any actively pipelined transactions on the USB and then
halts. The Host Controller must halt within 16 micro-frames after
software clears the Run bit. The HC Halted bit in the status register
indicates when the Host Controller has finished its pending pipelined
transactions and has entered the stopped state. Software must not write
a one to this field unless the host controller is in the Halted state (i.e.
HCHalted in the USBSTS register is a one). Doing so will yield
undefined results.
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OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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USBCMD – RW - 32 bits - [EOR_Reg : EHCI_EOR + 00h]
Field Name
Host Controller
Reset
Bits
Default
Description
1
0b
This control bit is used by software to reset the host controller. The
effects of this on Root Hub registers are similar to a Chip Hardware
Reset. When software writes a one to this bit, the Host Controller resets
its internal pipelines, timers, counters, state machines, etc. to their initial
value. Any transaction currently in progress on USB is immediately
terminated. A USB reset is not driven on downstream ports. PCI
Configuration registers are not affected by this reset. All operational
registers, including port registers and port state machines are set to their
initial values. Port ownership reverts to the companion host controller(s).
Software must reinitialize the host controller in order to return the host
controller to an operational state. This bit is set to zero by the Host
Controller when the reset process is complete. Software cannot
terminate the reset process early by writing a zero to this register.
Software should not set this bit to a one when the HCHalted bit in the
USBSTS register is a zero. Attempting to reset an actively running host
controller will result in undefined behavior.
(HCRESET)
Frame List Size
3:2
00b
This field is R/W only if Programmable Frame List Flag in the
HCCPARAMS registers is set to a one. This field specifies the size of
the frame list. The size the frame list controls which bits in the Frame
Index Register should be used for the Frame List Current index. Values
mean:
00b = 1024 elements (4096 bytes) Default value
01b = 512 elements (2048 bytes)
10b = 256 elements (1024 bytes) – for resource-constrained
environments
11b = Reserved
[Read/Write or Read-only]
Periodic
Schedule
Enable
4
5
6
0b
0b
0b
This bit controls whether the host controller skips processing the Periodic
Schedule.
0 = Do not process the Periodic Schedule
1 = Use the PERIODICLISTBASE register to access the Periodic
Schedule.
This bit controls whether the host controller skips processing the
Asynchronous Schedule.
0b = Do not process the Asynchronous Schedule
1b = Use the ASYNCLISTADDR register to access the Asynchronous
Schedule.
This bit is used as a doorbell by software to tell the host controller to
issue an interrupt the next time it advances asynchronous schedule.
Software must write a 1 to this bit to ring the doorbell. When the host
controller has evicted all appropriate cached schedule state, it sets the
Interrupt on Async Advance status bit in the USBSTS register. If the
Interrupt on Async Advance Enable bit in the USBINTR register is a one
then the host controller will assert an interrupt at the next interrupt
threshold. The host controller sets this bit to a zero after it has set the
Interrupt on Async Advance status bit in the USBSTS register to a one.
Software should not write a one to this bit when the asynchronous
schedule is disabled. Doing so will yield undefined results.
This control bit is not required. If implemented, it allows the driver to
reset the EHCI controller without affecting the state of the ports or the
relationship to the companion host controllers. For example, the
PORSTC registers should not be reset to their default values and the CF
bit setting should not go to zero (retaining port ownership relationships).
A host software read of this bit as zero indicates the Light Host Controller
Reset has completed and it is safe for host software to re-initialize the
host controller. A host software read of this bit as a one indicates the
Light Host Controller Reset has not yet completed.
Asynchronous
Schedule
Enable
Interrupt on
Async Advance
Doorbell
Light Host
Controller Reset
(Optional)
7
0b
If not implemented a read of this field will always return a zero.
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OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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USBCMD – RW - 32 bits - [EOR_Reg : EHCI_EOR + 00h]
Field Name
Asynchronous
Schedule Park
Mode Count
(Optional)
Bits
Default
Description
9:8
00b
If the Asynchronous Park Capability bit in the HCCPARAMS register is a
one, then this field defaults to 3h and is R/W. Otherwise it defaults to
zero and is RO. It contains a count of the number of successive
transactions the host controller is allowed to execute from a high-speed
queue head on the Asynchronous schedule before continuing traversal
of the Asynchronous schedule. Valid values are 1h to 3h. Software
must not write a zero to this bit when Park Mode Enable is a one as this
will result in undefined behavior.
[Read/Write or Read-only]
Reserved
10
11
This bit is reserved and should be set to Zero.
[Read-only]
If the Asynchronous Park Capability bit in the HCCPARAMS register is a
one, then this bit defaults to a 1h and is R/W. Otherwise the bit must be
a zero and is RO. Software uses this bit to enable or disable Park mode.
When this bit is one, Park mode is enabled. When this bit is a zero, Park
mode is disabled.
Asynchronous
Schedule Park
Mode Enable
(Optional)
0b
Reserved
Interrupt
Threshold
Control
15:12
23:16
This bit is reserved and should be set to Zero.
08h
This field is used by system software to select the maximum rate at
which the host controller will issue interrupts. The only valid values are
defined below. If software writes an invalid value to this register, the
results are undefined.
00h = Reserved
01h = 1 micro-frame
02h = 2 micro-frames
04h = 4 micro-frames
08h = 8 micro-frames (default, equates to 1 ms)
10h = 16 micro-frames (2 ms)
20h = 32 micro-frames (4 ms)
40h = 64 micro-frames (8 ms)
Any other value in this register yields undefined results. Software
modifications to this bit while HCHalted bit is equal to zero results in
undefined behavior.
Reserved
31:24
These bits are reserved and should be set to Zeros.
USBSTS - RW - 32 bits - [EOR_Reg : EHCI_EOR + 04h]
Field Name
Bits
Default
Description
USBINT
0
0b
USB Interrupt. The Host Controller sets this bit to 1 on the completion of
a USB transaction, which results in the retirement of a Transfer Descriptor
that had its IOC bit set. The Host Controller also sets this bit to 1 when a
short packet is detected (actual number of bytes received was less than
the expected number of bytes).
USBERRINT
1
0b
USB Error Interrupt . The Host Controller sets this bit to 1 when
completion of a USB transaction results in an error condition (e.g., error
counter underflow). If the TD on which the error interrupt occurred also
had its IOC bit set, both this bit and USBINT bit are set.
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OCHI USB 1.1 and EHCI USB 2.0 Controllers
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USBSTS - RW - 32 bits - [EOR_Reg : EHCI_EOR + 04h]
Field Name
Port Change
Detect
Bits
Default
Description
2
0b
Port Change Detect. The Host Controller sets this bit to a one when any
port for which the Port Owner bit is set to zero (see Section 2.3.9) has a
change bit transition from a zero to a one or a Force Port Resume bit
transition from a zero to a one as a result of a J-K transition detected on a
suspended port. This bit will also be set as a result of the Connect Status
Change being set to a one after system software has relinquished
ownership of a connected port by writing a zero to a port's Port Owner bit.
This bit is allowed to be maintained in the Auxiliary power well.
Alternatively, it is also acceptable that on a D3 to D0 transition of the
EHCI HC device, this bit is loaded with the OR of all of the PORTSC
change bits (including: Force port resume, over-current change,
enable/disable change and connect status change).
Frame List
Rollover
3
0b
Frame List Rollover. The Host Controller sets this bit to a one when the
Frame List Index rolls over from its maximum value to zero. The exact
value at which the rollover occurs depends on the frame list size. For
example, if the frame list size (as programmed in the Frame List Size field
of the USBCMD register) is 1024, the Frame Index Register rolls over
every time FRINDEX[13] toggles. Similarly, if the size is 512, the Host
Controller sets this bit to a one every time FRINDEX[12] toggles.
Host System Error. The Host Controller sets this bit to 1 when a serious
error occurs during a host system access involving the Host Controller
module. In a PCI system, conditions that set this bit to 1 include PCI
Parity error, PCI Master Abort, and PCI Target Abort. When this error
occurs, the Host Controller clears the Run/Stop bit in the Command
register to prevent further execution of the scheduled TDs.
Host System Error
4
5
0b
0b
1b
Interrupt on Async
Advance
Interrupt on Async Advance. System software can force the host
controller to issue an interrupt the next time the host controller advances
the asynchronous schedule by writing a one to the Interrupt on Async
Advance Doorbell bit in the USBCMD register. This status bit indicates the
assertion of that interrupt source.
Reserved
HCHalted
11:6
12
These bits are reserved and should be set to zero.
HCHalted. This bit is a zero whenever the Run/Stop bit is a one. The Host
Controller sets this bit to one after it has stopped executing as a result of
the Run/Stop bit being set to 0, either by software or by the Host
Controller hardware (e.g. internal error). [Read-only]
Reclamation
13
14
0b
0b
Reclamation. This is a read-only status bit, which is used to detect an
empty asynchronous schedule. [Read-only]
Periodic Schedule
Status
Periodic Schedule Status. The bit reports the current real status of the
Periodic Schedule. If this bit is a zero then the status of the Periodic
Schedule is disabled. If this bit is a one then the status of the Periodic
Schedule is enabled. The Host Controller is not required to immediately
disable or enable the Periodic Schedule when software transitions the
Periodic Schedule Enable bit in the USBCMD register. When this bit and
the Periodic Schedule Enable bit are the same value, the Periodic
Schedule is either enabled (1) or disabled (0). [Read-only]
Asynchronous
Schedule Status
15
0b
Asynchronous Schedule Status. The bit reports the current real status of
the Asynchronous Schedule. If this bit is a zero then the status of the
Asynchronous Schedule is disabled. If this bit is a one then the status of
the Asynchronous Schedule is enabled. The Host Controller is not
required to immediately disable or enable the Asynchronous Schedule
when software transitions the Asynchronous Schedule Enable bit in the
USBCMD register. When this bit and the Asynchronous Schedule Enable
bit are the same value, the Asynchronous Schedule is either enabled (1)
or disabled (0). [Read-only]
Reserved
31:16
These bits are reserved and should be set to zero.
©2008 Advanced Micro Devices, Inc.
OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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USBINTR –RW - 32 bits - [EOR_Reg : EHCI_EOR + 08h]
Field Name
USB Interrupt
Enable
Bits
Default
Description
0
0b
When this bit is a one, and the USBINT bit in the USBSTS register is a
one, the host controller will issue an interrupt at the next interrupt
threshold. The interrupt is acknowledged by software clearing the
USBINT bit.
USB Error
Interrupt Enable
1
0b
When this bit is a one, and the USBERRINT bit in the USBSTS register is
a one, the host controller will issue an interrupt at the next interrupt
threshold. The interrupt is acknowledged by software clearing the
USBERRINT bit.
Port Change
Interrupt Enable
2
3
4
5
0b
0b
0b
0b
When this bit is a one, and the Port Change Detect bit in the USBSTS
register is a one, the host controller will issue an interrupt. The interrupt is
acknowledged by software clearing the Port Change Detect bit.
When this bit is a one, and the Frame List Rollover bit in the USBSTS
register is a one, the host controller will issue an interrupt. The interrupt is
acknowledged by software clearing the Frame List Rollover bit.
When this bit is a one, and the Host System Error Status bit in the
USBSTS register is a one, the host controller will issue an interrupt. The
interrupt is acknowledged by software clearing the Host System Error bit.
When this bit is a one, and the Interrupt on Async Advance bit in the
USBSTS register is a one, the host controller will issue an interrupt at the
next interrupt threshold. The interrupt is acknowledged by software
clearing the Interrupt on Async Advance bit.
Frame List
Rollover Enable
Host System Error
Enable
Interrupt on Async
Advance Enable
Reserved
31:6
These bits are reserved and should be zero
FRINDEX –RW - 32 bits - [EOR_Reg : EHCI_EOR + 0Ch]
Field Name
Bits
Default
Description
Frame Index
13:0
0h
When this bit is a one, and the Interrupt on Async Advance bit in the
USBSTS register is a one, the host controller will issue an interrupt at the
next interrupt threshold. The interrupt is acknowledged by software
clearing the Interrupt on Async Advance bit.
Reserved
31:14
These bits are reserved and should be zero
CTRLDSSEGMENT –RW - 32 bits - [EOR_Reg : EHCI_EOR + 10h]
Field Name
CTRLDSSEGME
NT
Bits
Default
Description
31:0
0h
This 32-bit register corresponds to the most significant address bits
[63:32] for all EHCI data structures. If the 64-bit Addressing Capability
field in HCCPARAMS is a zero, then this register is not used. Software
cannot write to it and a read from this register will return zeros.
If the 64-bit Addressing Capability field in HCCPARAMS is a one, then
this register is used with the link pointers to construct 64-bit addresses to
EHCI control data structures. This register is concatenated with the
link pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or
any control data structure link field to construct a 64-bit address.
This register allows the host software to locate all control data structures
within the same 4 Gigabyte memory segment.
PERIODICLISTBASE –RW - 32 bits - [EOR_Reg : EHCI_EOR + 14h]
Field Name
Bits
Default
Description
Reserved
11:0
These bits are reserved. Must be written as 0s. During runtime, the
values of these bits are undefined.
Base Address
31:12
000h
These bits correspond to memory address signals [31:12], respectively.
©2008 Advanced Micro Devices, Inc.
OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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Page 86
ASYNCLISTADDR –RW - 32 bits - [EOR_Reg : EHCI_EOR + 18h]
Field Name
Reserved
Link Pointer Low
(LPL)
Bits
Default
Description
4:0
31:5
These bits are reserved and their value has no effect on operation.
These bits correspond to memory address signals [31:5], respectively.
This field may only reference a Queue Head (QH).
00h
CONFIGFLAG –RW - 32 bits - [EOR_Reg : EHCI_EOR + 40h]
Field Name
Configure Flag
(CF)
Bits
Default
Description
0
0b
Host software sets this bit as the last action in its process of configuring
the Host Controller. This bit controls the default port-routing control
logic. Bit values and side-effects are listed below:
0b = Port routing control logic default-routes each port to an
implementation dependent classic host controller.
1b = Port routing control logic default-routes all ports to this host
controller.
Reserved
31:1
These bits are reserved and should be set to zero.
PORTSC (1-N_PORTS) –RW - 32 bits - [EOR_Reg : EHCI_EOR + (44h~68h)]
Field Name
Current Connect
Status
Bits
0
Default
Description
0b
1 = Device is present on port.
0 = No device is present.
This value reflects the current state of the port, and may not correspond
directly to the event that caused the Connect Status Change bit (Bit 1) to
be set. This field is zero if Port Power is zero. [Read-only]
1 = Change in Current Connect Status.
Connect Status
Change
1
0b
0 = No change.
Indicates a change has occurred in the port’s Current Connect Status.
The host controller sets this bit for all changes to the port device connect
status, even if system software has not cleared an existing connect status
change. For example, the insertion status changes twice before system
software has cleared the changed condition, hub hardware will be
“setting” an already-set bit (i.e., the bit will remain set). Software sets this
bit to 0 by writing a 1 to it. This field is zero if Port Power is zero.
1 = Enable.
Port
2
0b
Enabled/Disabled
0 = Disable
Ports can only be enabled by the host controller as a part of the reset and
enable. Software cannot enable a port by writing a one to this field. The
host controller will only set this bit to a one when the reset sequence
determines that the attached device is a high-speed device. Ports can be
disabled by either a fault condition (disconnect event or other fault
condition) or by host software. Note that the bit status does not change
until the port state actually changes. There may be a delay in disabling or
enabling a port due to other host controller and bus events. When the port
is disabled (0b) downstream propagation of data is blocked on this port,
except for reset. This field is zero if Port Power is zero.
1 = Port enabled/disabled status has changed.
Port
Enable/Disable
Change
3
4
0b
0b
0 = No change.
For the root hub, this bit gets set to a one only when a port is disabled due
to the appropriate conditions existing at the EOF2. Software clears this bit
by writing a 1 to it. This field is zero if Port Power is zero.
1 = This port currently has an over-current condition.
0 = This port does not have an over-current condition.
This bit will automatically transition from a one to a zero when the over
current condition is removed.
Over-current
Active
©2008 Advanced Micro Devices, Inc.
OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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Page 87
PORTSC (1-N_PORTS) –RW - 32 bits - [EOR_Reg : EHCI_EOR + (44h~68h)]
Field Name
Force Port
Resume
Bits
6
Default
Description
1 = Resume detected/driven on port.
0 = No resume (K-state) detected/driven on port.
0b
This functionality defined for manipulating this bit depends on the value of
the Suspend bit. For example, if the port is not suspended (Suspend and
Enabled bits are a one) and software transitions this bit to a one, then the
effects on the bus are undefined. Software sets this bit to a 1 to drive
resume signaling. The Host Controller sets this bit to a 1 if a J-to-K
transition is detected while the port is in the Suspend state. When this bit
transitions to a one because a J-to-K transition is detected, the Port
Change Detect bit in the USBSTS register is also set to a one. If software
sets this bit to a one, the host controller must not set the Port Change
Detect bit. Note that when the EHCI controller owns the port, the resume
sequence follows the defined sequence documented in the USB
Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven
on the port as long as this bit remains a one. Software must appropriately
time the Resume and set this bit to a zero when the appropriate amount
of time has elapsed. Writing a zero (from one) causes the port to return to
high-speed mode (forcing the bus below the port into a high-speed idle).
This bit will remain a one until the port has switched to the high-speed
idle. The host controller must complete this transition within 2 milliseconds
of software setting this bit to a zero. This field is zero if Port Power is zero.
1 = Port in suspend state.
Suspend
7
0b
0 = Port not in suspend state.
Port Enabled Bit and Suspend bit of this register define the port states as
follows:
Bits [Port Enabled, Suspend]
Port State
Disable
Enable
Suspend
0X
10
11
When in suspend state, downstream propagation of data is blocked on
this port, except for port reset. The blocking occurs at the end of the
current transaction, if a transaction was in progress when this bit was
written to 1. In the suspend state, the port is sensitive to resume
detection. Note that the bit status does not change until the port is
suspended and that there may be a delay in suspending a port if there is
a transaction currently in progress on the USB. A write of zero to this bit is
ignored by the host controller. The host controller will unconditionally set
this bit to a zero when:
- Software sets the Force Port Resume bit to a zero (from a one).
- Software sets the Port Reset bit to a one (from a zero).
If host software sets this bit to a one when the port is not enabled (i.e.
Port enabled bit is a zero) the results are undefined. This field is zero if
Port Power is zero.
©2008 Advanced Micro Devices, Inc.
OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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Page 88
PORTSC (1-N_PORTS) –RW - 32 bits - [EOR_Reg : EHCI_EOR + (44h~68h)]
Field Name
Bits
Default
Description
Port Reset
8
0b
1 = Port is in Reset.
0 = Port is not in Reset.
When software writes a one to this bit (from a zero), the bus reset
sequence as defined in the USB Specification Revision 2.0 is started.
Software writes a zero to this bit to terminate the bus reset sequence.
Software must keep this bit at a one long enough to ensure the reset
sequence, as specified in the USB Specification Revision 2.0, completes.
Note: when software writes this bit to a one, it must also write a zero to
the Port Enable bit.
Note that when software writes a zero to this bit there may be a delay
before the bit status changes to a zero. The bit status will not read as a
zero until after the reset has completed. If the port is in high-speed mode
after reset is complete, the host controller will automatically enable this
port (e.g. set the Port Enable bit to a one). A host controller must
terminate the reset and stabilize the state of the port within 2 milliseconds
of software transitioning this bit from a one to a zero. For example: if the
port detects that the attached device is high-speed during reset, then the
host controller must have the port in the enabled state within 2ms of
software writing this bit to a zero.
The HCHalted bit in the USBSTS register should be a zero before
software attempts to use this bit. The host controller may hold Port Reset
asserted to a one when the
HCHalted bit is a one. This field is zero if Port Power is zero.
This bit is reserved for future use, and should return a value of zero when
read.
Reserved
9
Line Status
11:10
These bits reflect the current logical levels of the D+ (bit 11) and D-
(bit 10) signal lines. These bits are used for detection of low-speed USB
devices prior to the port reset and enable sequence. This field is valid
only when the port enable bit is zero and the current connect status bit is
set to a one.
The encoding of the bits are:
Bits[11:10] USB State Interpretation
00b
10b
01b
11b
SE0
J-state
K-state
Not Low-speed device, perform EHCI reset
Not Low-speed device, perform EHCI reset
Low-speed device, release ownership of port
Undefined Not Low-speed device, perform EHCI reset.
This value of this field is undefined if Port Power is zero.
[Read-only]
Port Power
12
The function of this bit depends on the value of the Port Power Control
(PPC) field in the HCSPARAMS register. The behavior is as follows:
PPC PP Operation
0b
switches. Each port is hard-wired to power.
1b 1b/0b RW - Host controller has port power control switches.
1b
RO - Host controller does not have port power control
This bit represents the current setting of the switch (0 = off, 1 = on). When
power is not available on a port (i.e.
PP equals a 0), the port is non-functional and will not report attaches,
detaches, etc.
When an over-current condition is detected on a powered port and PPC is
a one, the PP bit in each affected port may be transitioned by the host
controller from a 1 to 0 (removing power from the port).
[Read-write or Read-only]
©2008 Advanced Micro Devices, Inc.
OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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Page 89
PORTSC (1-N_PORTS) –RW - 32 bits - [EOR_Reg : EHCI_EOR + (44h~68h)]
Field Name
Bits
Default
Description
Port Owner
13
1b
This bit unconditionally goes to a 0b when the Configured bit in the
CONFIGFLAG register makes a 0b to 1b transition. This bit
unconditionally goes to 1b whenever the Configured bit is zero.
System software uses this field to release ownership of the port to a
selected host controller (in the event that the attached device is not a
high-speed device). Software writes a one to this bit when the attached
device is not a high-speed device. A one in this bit means that a
companion host controller owns and controls the port.
Writing to this bit has no effect if the P_INDICATOR bit in the
HCSPARAMS register is a zero. If P_INDICATOR bit is a one, then the bit
encodings are:
Port Indicator
Control
15:14
00b
Bit Value Meaning
00b
01b
10b
11b
Port indicators are off
Amber
Green
Undefined
Refer to the USB Specification Revision 2.0 for a description on how
these bits are to be used. This field is zero if Port Power is zero.
When this field is zero, the port is NOT operating in a test mode. A non-
zero value indicates that it is operating in test mode and the specific test
mode is indicated by the specific value. The encoding of the test mode
bits are (0110b - 1111b are reserved):
Port Test Control
19:16
0000b
Bits
Test Mode
0000b Test mode not enabled
0001b Test J_STATE
0010b Test K_STATE
0011b Test SE0_NAK
0100b Test Packet
0101b Test FORCE_ENABLE
Wake on Connect
Enable
Wake on
Disconnect
Enable
20
21
0b
0b
Writing this bit to a one enables the port to be sensitive to device
connects as wake-up events. This field is zero if Port Power is zero.
Writing this bit to a one enables the port to be sensitive to device
disconnects as wake-up events. This field is zero if Port Power is zero.
Wake on Over-
current Enable
Reserved
22
0b
Writing this bit to a one enables the port to be sensitive to over-current
conditions as wake-up events. This field is zero if Port Power is zero.
Reserved
31:23
Packet Buffer Threshold Values – RW - 32 bits - [EOR_Reg : EHCI_EOR + 84h]
Field Name
IN Threshold
Bits
7:0
Default
10h
Description
The PCI transaction starts when threshold of internal FIFO for receive
packet is reached.
The value represents multiple of 8 bytes – 10h means 128 bytes. The
smallest acceptable value is 08h (64 bytes).
Reserved
Reserved
15:8
OUT Threshold
23:16
60h
The transmit packet starts at UTMI interface when threshold of internal
FIFO for transmit packet is reached.
The value represents multiple of 8 bytes – 10h means 128 bytes. The
smallest acceptable value is 08h (64 bytes).
Reserved
Reserved
31:24
©2008 Advanced Micro Devices, Inc.
OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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Page 90
USB PHY Status 0 – RW - 32 bits - [EOR_Reg: EHCI_EOR + 88h]
Field Name
Bits
Default
Description
PORT0_PHYStatus
PORT1_PHYStatus
PORT2_PHYStatus 23:16
PORT3_PHYStatus 31:24
7:0
15:8
00h
00h
00h
00h
Read only. PHY Status of Port0
Read only. PHY Status of Port1
Read only. PHY Status of Port2
Read only. PHY Status of Port3
Note: PORTx_PHYStatus[7:0] = { 0, RCKSEL, DUTYADJ[2:0], HSADJ[2:0] } where x=0 ~ 3
USB PHY Status 1 – RW - 32 bits - [EOR_Reg: EHCI_EOR + 8Ch]
Field Name
Bits
Default
Description
PORT4_PHYStatus
PORT5_PHYStatus
PORT6_PHYStatus 23:16
PORT7_PHYStatus 31:24
7:0
15:8
00h
00h
00h
00h
Read only. PHY Status of Port4
Read only. PHY Status of Port5
Read only. PHY Status of Port6
Read only. PHY Status of Port7
USB PHY Status 2 – RW - 32 bits - [EOR_Reg: EHCI_EOR + 90h]
Field Name
Reserved
Bits
Default
Description
15:0
Reserved
PORT8_PHYStatus 23:16
PORT9_PHYStatus 31:24
00h
00h
Read only. PHY Status of Port8
Read only. PHY Status of Port9
UTMI Control – RW - 32 bits - [EOR_Reg: EHCI_EOR + 94h]
Field Name
VControl
Bits
Default
Description
6:0
0h
Control PHY setting
Group-0 (VControlModeSel=0)
VControl[6:0] = {RCKSEL, DUTYADJ[2:0], HSADJ[2:0]}
- HSADJ : HS TX current adjustment
000 : -10%
001 : -5%
100 : 0%
101 : +5%
110 : +10%
- DUTYADJ: adjust clk480 (in analog PHY) duty cycle from range 40-
60% to 60-40%.
- RCKSEL : to select the RCK fall into 50% or 57% of the eye
0 – 50% (center) of the eye
1 – 64% of the eye to increase setup time
Group-1 (VControlModeSel =1)
VControl[6:0] = {Reserved, TESTMODE[3:0] }
VControlModeSel
Reserved
VLoadB
7
11:8
12
0b
1b
To select PHY Vcontrol group0/1.
Reserved
Update PHY control mode (active load)
0: Load the new VControl value to PHY/common block
1: Only VControlModeSel value to PHY will be updated for selecting
different PHY status group (see PHY status registers, EOR_Reg x88 ~
x90). But VControl[6:0] value inside PHY won’t get affected.
Port Number
16:13
0h
Select the corresponding port PHY or common block to load the
VControl bits.
0000 – Port0
0001 – Port1
0010 – Port2
……
1001 – Port9
1010 ~ 1110 : Reserved , no effect
1111 – Common block
©2008 Advanced Micro Devices, Inc.
OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
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Page 91
UTMI Control – RW - 32 bits - [EOR_Reg: EHCI_EOR + 94h]
Field Name
VBusy
Bits
Default
Description
17
0b
RO – To block software write to [16:8] when port router is updating the
field.
Reserved
31:18
Reserved
BIST Control / Loopback Test – RW - 32 bits - [EOR_Reg : EHCI_EOR + 98h]
Field Name
Bits
7:0
8
Default
00h
Description
Reserved
Enable Loop Back
test
Reserved
0b
Enable external USB Port Loop back test.
The Loop Back test is to set one port to TX mode (Test Packet mode)
and one port in RX mode (Test SE0_NAK). Please reference to
PORTSCx[19:16] control the port into TX or RX mode.
Read Only.
Loopback Test
Status
9
0b
Loop back status.
0: CRC Error on Loop Back Receiving Data
1: Good CRC on Loop Back Receiving data
Read Only.
Loopback Test
Done
10
0b
Indicate Loop back test done.
Reserved
31:11
00000h
EOR MISC Control – RW - 32 bits - [EOR_Reg : EHCI_EOR + 9Ch]
Field Name
Reserved
EHCI Power
Saving Enable
Bits
11:0
12
Default
000h
0b
Description
Reserved
Enable power saving clock gating. When enabled, dynamic clock gating
is enabled when EHCI is not at operational mode. The clock goes to all
memory module will be gated off, and the internal bus clock also gets
gated off unless the connection interrupt is detected.
Reserved
Reserved
31:13
00000h
USB Common PHY Calibration – RW - 32 bits - [EOR_Reg: EHCI_EOR + A0h]
Field Name
Bits
Default
Description
ComCalBus
6:0
xx
Enables power saving clock gating (this was original at bit-31). When
enabled, dynamic clock gating is enabled when EHCI is not at
operational mode. The clock goes to all memory module will be gated
off, The blink clock also is gated off unless the connection interrupt is
detected.
Reserved
7
15:8
16
0b
00h
0b
Reserved
NewCalBus
UsbCommonCalib
ration
AddToCommonCa
libration
New calibration bus signed value. Bit-15 is the signed bit.
If set, the PHY’s calibration value in bit[6:0] is returned to the PHY ports.
If clear, the value after adjustment is returned to the PHY ports.
If set, the signed NewCalBus is added to the ComCalBus and returned
to the PHY ports. Any overflow is clamped to all ones. Any underflow is
clamped to all zeros.
17
0b
If clear, the NewCalBus (bit-14:8) replaces the ComCalBus and returns
to the PHY ports.
Reserved
Note:
31:18
0000h
Reserved
1. The equation for calibration resistor is as follows: Rcal = 1/ [1/59.4 + CalValue/(1.05*3.8k ohm)], where the
CalValue is the final 7 bits of calibration setting send to PHY.
2. The total termination resistance value for HS USB D+/D- should include another 5 ohm resistance from FS
driver.
2.2.3.4 USB2.0 Debug Port Registers
This block of registers is memory-mapped. The base offset, Dbase, is directly defined in DBUG_PRT
©2008 Advanced Micro Devices, Inc.
OCHI USB 1.1 and EHCI USB 2.0 Controllers
Proprietary Page 92
AMD SB600 Register Reference Manual
Control register (EHCI_PCI_CFG xE4[28:16], default = 0E0h), regardless of the value in register (MEM_Reg:
00h).
Registers Name
Control / Status
USB PIDs
Offset Address
DBase + 00h
DBase + 04h
Data Buffer
Device Address
DBase + (08h~0Ch)
DBase + 10h
Control / Status – RW - 32 bits - [DBUG_Reg : DBase + 00h]
Field Name
Bits
Default
Description
Data Length
3:0
0h
For write operations, this field is set by software to indicate to the
hardware how many bytes of data in Data Buffer are to be transferred
to the console when Write/Read# is set when software sets Go. A
value of 0h indicates that a zero-length packet should be sent. A value
of 1-8 indicates 1-8 bytes are to be transferred. Values 9-Fh are illegal
and how hardware behaves if used is undefined.
For read operations, this field is set by hardware to indicate to software
how many bytes in Data Buffer are valid in response to software setting
Go when Write/Read# is cleared. A value of 0h indicates that a zero
length packet was returned. (The state of Data Buffer is not defined.)
A value of 1-8 indicates 1-8 bytes were received. Hardware is not
allowed to return values 9-Fh. The transferring of data always starts
with byte 0 in the data area and moves toward byte 7 until the transfer
size is reached.
Write/Read#
Go
4
5
0b
0b
Software sets this bit to indicate that the current request is a write and
clears it to indicate a read.
Software sets this bit to cause the hardware to perform a request.
Writing this bit to a 1 when the bit is already set may result in undefined
behavior. Writing a 0 to this bit has no effect. When set, the hardware
clears this bit when the hardware sets the Done bit. (Completion of a
request is indicated by the Done bit.)
Error/Good#
Exception
6
0b
Read Only
Updated by hardware at the same time it sets the Done bit. When set it
indicates that an error occurred. Details of the error are provided in the
Exception field. When cleared, it indicates that the request terminated
successfully.
9:7
000b
Read Only
This field indicates the exception when Error/Good# is set. This field
cannot be cleared by software. Reset default = 000b.
Value
000b
001b
Meaning
None
Transaction error: indicates the USB2 transaction
had an error (CRC, bad PID, timeout, etc.)
HW error. Request was attempted (or in progress)
when the port was suspended or reset.
Reserved
010b
011b-111b
In Use
10
0b
0b
Set by software to indicate that the port is in use. Cleared by software
to indicate that the port is free and may be used by other software.
(This bit has no affect on hardware.)
Reserved
Reserved
Done
15:11
16
RWC
This bit is set by HW to indicate that the request is complete. Writing a
1 to this bit will clear it. Writing a 0 to this bit has no effect.
Reserved
Reserved
27:17
©2008 Advanced Micro Devices, Inc.
OCHI USB 1.1 and EHCI USB 2.0 Controllers
AMD SB600 Register Reference Manual
Proprietary
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Control / Status – RW - 32 bits - [DBUG_Reg : DBase + 00h]
Field Name
Bits
Default
Description
Enabled
28
0b
This bit is a one if the debug port is enabled for operation.
Software can clear this by writing a zero to it. The controller clears the
bit for the same conditions where hardware clears the Port
Enable/Disable Change bit (in the PORTSC register). (Note: this bit is
not cleared when System Software clears the Port Enabled/Disabled bit
(in the PORTSC register). Software can directly set this bit, if the port is
already enabled in the associated Port Status and Control register (this
is HW enforced).
Reserved
Owner
29
30
Reserved
0b
When debug software writes a one to this bit, the ownership of the
debug port is forced to the EHCI controller (i.e. Immediately taken away
from the companion controller). If the port was already owned by the
EHCI controller, then setting this bit is has no effect. This bit overrides
all of the ownership related bits in the standard EHCI registers. Reset
default = 0. Note that the value in this bit may not affect the value
reported in the Port Owner bit in the associated PORTSC register.
Reserved
Reserved
31
USB PIDs – RW - 32 bits - [DBUG_Reg : DBase + 04h]
Field Name
Bits
Default
Description
Token PID
7:0
00h
The debug port controller sends this PID as the Token PID for each
USB transaction. Software will typically set this field to either IN, OUT
or SETUP PID values. Reset default = undefined.
The debug port controller sends this PID to begin the data packet when
sending data to USB (i.e. Write/Read# is asserted). Software will
typically set this field to either DATA0 or DATA1 PID values. Reset
default = undefined.
Send PID
15:8
00h
00h
Received PID
23:16
Read Only
The debug port controller updates this field with the received PID for
transactions in either direction. When the controller is sending data
(Write/Read# is asserted), this field is updated with the handshake PID
that is received from the device. When the host controller is receiving
data (Write/Read# is not asserted), this field is updated with the data
packet PID (if the device sent data), or the handshake PID (if the device
NAKs the request). This field is valid when the controller sets the Done
bit. Reset default = undefined.
Reserved
31:24
Reserved
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Data Buffer – RW - 64 bits - [DBug_Reg : DBase + 08h/0Ch]
Field Name
Data Buffer
Bits
Default
00000000 The least significant byte is accessed at offset 08h and the most
significant byte is accessed at offset 0Fh. Each byte in Data Buffer can
00000000 be individually accessed. Data Buffer must be written with data before
Description
63:0
_
h
software initiates a write request. For a read request, Data Buffer
contains valid data when Done is set, Error/Good# is cleared, and Data
Length specifies the number of bytes that are valid. Reset default =
undefined.
Device Address – RW - 32 bits - [DBUG_Reg : DBase + 10h]
Field Name
Bits
Default
Description
USB Endpoint
3:0
1h
4-bit field that identifies the endpoint used by the controller for all Token
PID generation.
Reserved
7:4
Reserved
USB Address
14:8
7Fh
7-bit field that identifies the USB device address used by the controller
for all Token PID generation.
Reserved
31:15
Reserved
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2.3
SMBus Module and ACPI Block (Device 20, Function 0)
Some registers in the SMBus/ACPI PCI configuration space (PCI_reg, see section 2.3.1) contain controls
and settings for a number of blocks within the SB600. Figure 4 below shows these blocks, with their affected
functions and the associated PCI_reg registers.
Bus 0 Dev 20 Function 0
SATA
USB
PCI
RTC
SATA Enables
SATA power saving
SATA Interrupt Map register
SATA Smart Power Control
OHCI / EHCI Controller Enables
USB Reset / PowerDown
USB Legacy control
USB Smart Power Control
USB PM & SMI Control
PCI Stop Clock enable
PCI Bridge Soft Reset Enable
PCI Bus drive strength registers
RTC Ram Protection
External RTC Enable
RTC I/O Addr Enable
PCI_Reg:
C0h
PCI_Reg:
PCI_Reg:
PCI_Reg:
AC/AFh
5Ch
64h
6Ah
6Ch
64h
98h
78h
64/68/6Bh
5Ch
98h
Keyboard Control
PIC / IOAPIC
GPIO
SMBus / I2C
Keyboard Reset
PIC /IOAPIC Enable
IOAPIC Base Address
IOAPIC clock control
GPIO Enables
GPIO Status
Gpio input / output registers
I2C port enables
Keyboard Interrupt IRQ 12 filter
External keyboard reset enable
Mouse control
I2C port Address register
I2C port R/W shadow port
I2C bus revision ID
Smbus base Address
SATA SMBus control
PCI_Reg:
PCI_Reg:
Serirq controller registers
74h
64h
81:80 h
58:50 h
BC h
A0:AC h
--
PCI_Reg:
--
PCI_Reg:
64h
62h
69h
AD:ACh
10h
D5:D2 h
08h
90 h
--
I/O PORTS
Memory Window
LPC
Misc
I/O Port Address enables
I/O C50 -C52 Enable
PM I/O register CD6 / CD7 Enable
Base Addr I/O or Mem map control
K8 I/O Wake Address
ISA Address Decode registers
ROM Address enables
LPC Controller Enable
LPC Drive strength control
K8 Intr Enable
MSI Mapping register
Ext Gate A20
AB register base address
Multimedia timer enable
8250 Timer Eenable
PCI-SPCI clock ratio
PCI_Reg:
PCI_Reg:
41h
49:48 h
--
C0h
64h
--
PCI_Reg:
--
78h
F4h
PCI_Reg:
B0/E0h
74h
62h
F0h
64h
--
Figure 4 SMBus/ACPI PCI Configuration Space Function Block Association
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2.3.1
PCI Configuration Registers and Extended Registers
2.3.1.1 PCIE Configuration Registers
Register Name
Configuration Offset
00h
VendorID
DeviceID
02h
Command
04h
STATUS
06h
Revision ID/Class Code
Cache Line Size
Latency Timer
08h
0Ch
0Dh
0Eh
0Fh
10h
14h
18h
1Ch
20h
24h
Header Type
BIST
Base Address 0
Base Address 1
Base Address 2
Base Address 3
Base Address 4
Base Address 5
Cardbus CIS Pointer
Subsystem Vendor
Subsystem ID
28h
2Ch
2Eh
30h
Expansion ROM Base Address
Capability Pointer
Interrupt Line
34h
3Ch
3Dh
3Eh
3Fh
40h
Interrupt Pin
Min_Gnt
Max_Lat
PCI Control
MiscFunction
41h
DmaLimit
42h
DmaEnhanceEnable
ISA Address Decode Control Register #1
ISA Address Decode Control Register #2
GPIO_52_to_49_Cntrl
GPIO_56_to_53_Cntrl
GPIO_60_to_57_Cntrl
GPIO_64_to_61_Cntrl
GPIO_73_to_70_Cntrl
SmartPowerControl1
SmartPowerControl2
MiscEnable
43h
48h
49h
50h
52h
54h
56h
5Ah
5Ch
5Dh
62h
AzIntMap
63h
Features Enable
SeriallrqControl
64h
69h
RTCProtect
USB Reset
TestMode
IoApic_Conf
6Ah
6Bh
6Ch
74h
IoAddrEnable
78h
GPIO_69_68_66_65_Cntrl
GPIO_3_to_0_Cntrl
GPIO_32_31_14_13_Cntrl
Smbus Base Address
IDE_GPIO_Cntrl
7Eh
80h
82h
90h
A0h
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Register Name
IDE_GPIO_In
GPIO_48_47_46_37_Cntrl
GPIO_12_to_4_Cntrl
SATA_Cntrl
SataIntMap
MSI_Mapping_Capability
PcilntGpio
Configuration Offset
A4h
A6h
A8h
ACh
AFh
B0h
BCh
BEh
C0h
D2h
D3h
D4h
D5h
D6h
E0h
F0h
F4h
F6h
F7h
F8h
FCh
UsbIntMap
IoDrvSth
I2CbusConfig
I2CCommand
I2CShadow1
I2Cshadow2
I2CBusRevision
MSI_Weight
AB_REG_BAR
WakeIoAddr
MwaitID
MwaitSts
ExtendedAddrPort
ExtendedDataPort
VendorID - R - 16 bits - [PCI_Reg: 00h]
Field Name
VendorID
Bits
15:0
Default
Description
1002h
Vendor ID
Vendor ID register: Vendor Identification
DeviceID - R - 16 bits - [PCI_Reg: 02h]
Field Name
DeviceID
Bits
31:16
Default
Description
4385h
Device ID
Device ID register: Device Identification Number
Command- RW - 16 bits - [PCI_Reg: 04h]
Field Name
I/O Space
Bits
Default
Description
0
1
2
3
1b
This bit controls a device’s response to IO space accesses. A
value of 1 enables it and a value of 0 disables it. Since this
module does claim certain legacy IO cycles, this bit is default
to 1.
Memory Space
Bus Master
1b
0b
0b
This bit controls a device’s response to memory space
accesses. A value of 1 enables it and a value of 0 disables it.
Since this module does claim certain memory cycles if BIOS is
strapped to the PCI bus, this bit is default to 1.
A value of 0 disables the device from generating PCI
accesses. A value of 1 allows it to behave as a bus master.
ACPI/SMBus does not have PCI master and so it is always 0.
[Read-only]
A value of 0 causes the devices to ignore all special cycle
operations. A value of 1 allows the device to monitor Special
Cycle operations. This module does not respond to special
cycle and so this is hardcoded to 0
Special Cycle
Memory Write &
Invalidate Enable
4
5
0b
0b
This bit is an enable bit for using the Memory Write and
Invalidate command. This module will not generate this
command and so it is always 0. [Read-only]
This bit controls how VGA compatible and graphics devices
handle accesses to VGA pallette registers. This does not
apply to this module and so it is always 0. [Read-only]
VGA Palette Snoop
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Command- RW - 16 bits - [PCI_Reg: 04h]
Field Name
Bits
Default
Description
Parity Error Response
6
0b
This bit controls the device’s response to parity errors. When
the bit is set, the device must take its normal action when a
parity error is detected. When the bit is 0, the device must
ignore any parity errors that it detects and continue normal
operation.
Wait Cycle Control
SERR# Enable
7
0b
This bit is used to control whether or not a device does
address/data stepping. This module does not use address
stepping. [Read-only]
This bit is an enable bit for SERR# driver. A value of 0
disables the SERR# and a value of 1 enables it.
This bit indicates whether device is fast back-to-back capable.
ACPI/SMbus does not support this function and so this bit is
always 0. [Read-only]
8
9
0b
0b
Fast Back-to-Back
Enable
Reserved
15:10
00h
PCI Command register
STATUS- RW - 16 bits - [PCI_Reg: 06h]
Field Name
Reserved
MSI Mapping Capability
Bits
3:0
4
Default
Description
1/0b
[Read-only] This bit indicates whether the device can support
MSI mapping. For K8 system this device is MSI mapping
capable so default value is 1; for P4 system this device does
not support MSI mapping so default value is 0.
This bit indicates whether the device can support 66 MHz.
This device is 66 MHz capable. [Read-only]
This bit indicates whether the device supports user definable
feature. This module does not support this feature and so it is
always 0. [Read-only]
66 MHz Capable
UDF Supported
5
6
1b
0b
Fast Back-to-Back
Capable
7
8
0b
0b
This bit indicates whether the device is capable of fast back-to-
back cycles. This module does not support this feature and so
it is always 0. [Read-only]
Set to 1 if the Parity Error Response bit is set, and the module
has detected PERR# asserted while acting as a PCI master
(regardless PERR# was driven by this module).
These bits encode the timing of DEVSEL#. This module will
always respond in medium timing and so these bits are always
11.
Data Parity Error
Detected
DEVSEL Timing
10:9
01b
Signaled Target Abort
Received Target Abort
Received Master Abort
11
12
13
0b
0b
0b
This bit is set by a slave device whenever it terminates a cycle
with a Target-Abort.
This bit is set by a master device whenever its transaction is
terminated with a Target-Abort.
This bit is set by a slave device whenever it terminates its
transaction with Master-Abort.
Signaled System Error
Detected Parity Error
14
15
0b
0b
This bit is set by device whenever the device asserts SERR#.
This bit is set by device whenever it detects a parity error,
even if parity error handling is disabled.
PCI device status register
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Revision ID/Class Code- R - 32 bits - [PCI_Reg: 08h]
Field Name
RevisionID
Bits
Default
Description
7:0
11h /
This field reflects the ASIC revision.
12h /
13h
11h : For ASIC revision A11
12h : For ASIC revision A12
13h : For ASIC revision A13
For ASIC revisions after A13, by default this field will read 13h
still. However, if SMBUS PCI config 70h bit 8 is set to 1, a
hidden revision ID can be read from this field.
0C0500h denotes a SMBUS controller.
Class Code
31:8
0C0500h
Revision ID/Class Code register
Cache Line Size- R - 8 bits - [PCI_Reg: 0Ch]
Field Name
Bits
Default
Description
Cache Line Size
7:0
00h
This register specifies the system cacheline size. This module
does not use Memory Write and Invalidate command and so
this register is not applicable. It is hardcoded to 0.
Cache line size register
Latency Timer- R - 8 bits - [PCI_Reg: 0Dh]
Field Name
Bits
Default
Description
Latency Timer
7:0
00h
This register specifies the value of the Latency Timer. This is
not used in this module and so it is always 0.
Latency timer register
Header Type- R - 8 bits - [PCI_Reg: 0Eh]
Field Name
Header Type
Bits
Default
Description
7:0
80h
This device is a multifunction device.
Header type register
BIST- R - 8 bits - [PCI_Reg: 0Fh]
Default Description
Field Name
BIST
Bits
7:0
00h
The module has no built-in self-test and so this is always 0.
BIST register
Base Address 0- R - 32 bits - [PCI_Reg: 10h]
Field Name
Bits
Default
Description
IO/Memory
0
1b
1 = IO
0 = Memory
Reserved
3:1
000b
SmBusBaseAd
Base Address 0 register
31:4
0000000h SMBus Base Address
Base Address 1- R - 32 bits - [PCI_Reg: 14h]
Field Name
Reserved
MultiMediaTimerBaseAd
dr
Bits
Default
Description
9:0
31:10
000h
000000h
Hardwired to 0; memory map only
High Precision Event Timer (also called Multi-media Timer)
base address.
Base Address 1 register
Base Address 2- R - 32 bits - [PCI_Reg: 18h]
Field Name
Bits
Default
Description
Base Address 2
31:0
0000_000 Not used and is hardcoded to 0.
0h
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Base Address 2- R - 32 bits - [PCI_Reg: 18h]
Field Name
Bits
Default
Description
Base Address 2 register
Base Address 3- R - 32 bits - [PCI_Reg: 1Ch]
Field Name
Bits
Default
Description
Base Address 3
31:0
0000_000 Not used and is hardcoded to 0.
0h
Base Address 3 register
Base Address 4- R - 32 bits - [PCI_Reg: 20h]
Field Name
Bits
Default
Description
Base Address 4
31:0
0000_000 Not used and is hardcoded to 0.
0h
Base Address 4 register
Base Address 5- R - 32 bits - [PCI_Reg: 24h]
Field Name
Bits
Default
Description
Base Address 5
31:0
0000_000 Not used and is hardcoded to 0.
0h
Base Address 5 register
Cardbus CIS Pointer- R - 32 bits - [PCI_Reg: 28h]
Field Name
Bits
Default
Description
Cardbus CIS Pointer
31:0
0000_000 Not used and is hardcoded to 0.
0h
Cardbus CIS Pointer register
Subsystem Vendor ID- W - 16 bits - [PCI_Reg: 2Ch]
Field Name
Bits
Default
Description
Subsystem Vendor ID
Subsystem Vendor ID register
15:0
0000h
Write once.
Subsystem ID- W - 16 bits - [PCI_Reg: 2Eh]
Field Name
Subsystem ID
Bits
Default
Description
15:0
0000h
Write once.
Subsystem ID register
Expansion ROM Base Address - R - 8 bits - [PCI_Reg: 30h]
Field Name
Expansion ROM Base
Address
Bits
Default
Description
7:0
00h
Not used and is hardcoded to 0.
Expansion ROM Base Address register
Capability Pointer - R - 8 bits - [PCI_Reg: 34h]
Field Name
Capability Pointer
Bits
Default
Description
For K8 system default value is B0h; for P4 system default
value is 00h.
7:0
B0/00h
Capability Pointer register
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Interrupt Line - R - 8 bits - [PCI_Reg: 3Ch]
Field Name
Interrupt Line
Bits
Default
Description
7:0
00h
This module does not generate interrupt. This register is
hardcoded to 0.
Interrupt Line register
Interrupt Pin – R - 8 bits - [PCI_Reg: 3Dh]
Field Name
Bits
Default
Description
Interrupt Pin
7:0
00h
This register specifies which interrupt pin the device issues.
This module does not generate interrupt but contains the
actual interrupt controller. This register is hardcoded to 0.
Interrupt Pin register
Min_Gnt - R - 8 bits - [PCI_Reg: 3Eh]
Field Name
Bits
Default
Description
Min_Gnt
7:0
00h
This register specifies the desired settings for Latency Timer
values. Value of 0 indicates that the device has no major
requirements for the setting. This value is hardcoded to 0.
Min_Gnt register
Max_Lat - R - 8 bits - [PCI_Reg: 3Fh]
Field Name
Bits
Default
Description
Max_Lat
7:0
00h
This register specifies the desired settings for Latency Timer
values. Value of 0 indicates that the device has no major
requirements for the setting. This value is hardcoded to 0.
Max_Lat register
PCI Control- RW - 8 bits - [PCI_Reg: 40h]
Field Name
Reserved
KB2RstEnable
Bits
Default
Description
1:0
2
00b
0b
When set, KeyBoard reset (KBRST#) pin will generate a
system wide reset (ARST#) for P4 system; for K8 system,
additional control by PMIO 66h Bit 5 determines whether INIT#
or ARST# is generated
Reserved
7:3
0h
PCI Control register
MiscFunction- RW - 8 bits - [PCI_Reg: 41h]
Field Name
Reserved
ExtraROM AddrEnable2
Bits
Default
Description
0
1
0b
0b
This bit only has meaning if xbus ROM is used. If this bit is
set, addresses between FFF80000h to FFFDFFFFh will be
directed to the ROM interface
Reserved
WatchDogDecodeEn
ExtraROM AddrEnable1
2
3
4
0b
0b
0b
Enables watchdog decode
This bit is meaningful if ROM interface is strapped to the xbus
ROM (sits on PCI bus). If this bit is set, addresses between
0E0000h to 0EFFFFh will be directed to the ROM interface.
When set, this module will decode cycles to IO C50, C51, C52:
GPM controls.
MiscfuncEnable
5
0b
Reserved
7:6
00b
MiscFunction register
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DmaLimit- RW - 8 bits - [PCI_Reg: 42h]
Field Name
DmaBurstLimit
Bits
6:0
Default
Description
00h
Enables the amount of burst data the legacy DMA engine can
sustain before it should give up the internal bus.
DmaLimitEnable
7
0h
This is another enhancement to the legacy DMA engine. In
the original design, certain DMA request (such as Infrared) will
cause the legacy DMA engine to dominate the internal bus for
a very long time (up to 512 bytes) and thereby causing long
latency for other devices. Setting this bit will cause the legacy
DMA engine to limit its transfer per burst based on bits [6:0]
DmaLimit register
DmaPrefetchEnable RW - 8 bits - [PCI_Reg: 43h]
Field Name
Bits
Default
Description
DmaPrefetchEnable
0
1b
Legacy read DMA prefetch function enable.
1 – Enable
0 – Disable
When set, the DMA engine will keep the data inside the FIFO,
even though the requesting device has deasserted the DMA
request. When the device requests data again, the DMA
engine will have data available instead of having to fetch data
from the memory again. Note this enhancement only applies to
channel 0, 1, 2, and 3. It has no effect on channel 5, 6, or 7
Reserved
7:1
00h
DmaPrefetchEnable register
ISA Address Decode Control Register #1- RW - 8 bits - [PCI_Reg: 48h]
Field Name
Bits
Default
Description
Window 0
0
1
2
3
1b
1b
1b
1b
896K to 960K PCI enable
640K to 768K PCI enable
512K to 640K PCI enable
0K to 512K PCI enable
Window 1
Window 2
Window 3
Reserved
7:4
0h
ISA Address Decode Control Register #1: This register defines the enable bits for four memory segments. If the
enable bit is set to 1, an ISA master or DMA access to the memory segment associated with that bit is forwarded to
the internal bus. The SB600 does not have any ISA master, because the bus is internal; however, it may affect
DMA transfers with the LPC module. Software should set all these bits to 1's.
ISA Address Decode Control Register #2- RW - 8 bits - [PCI_Reg: 49h]
Field Name
Bits
Default
Description
Window 0
0
1
2
3
4
5
6
7
1b
1b
1b
1b
1b
1b
1b
1b
C0000h to C3FFFh
C4000h to C7FFFh
C8000h to CBFFFh
CC000h to CFFFFh
D0000h to D3FFFh
D4000h to D7FFFh
D8000h to DBFFFh
DC000h to DFFFFh
Window 1
Window 2
Window 3
Window 4
Window 5
Window 6
Window 7
ISA Address Decode Control Register #1: This register defines the PCI enable bits for four memory segments. If
the enable bit is set to 1, an ISA master or DMA access to the memory segment associated with that bit is forward
to the internal bus. The SB600 does not have any ISA master, because the bus is internal; however, it may affect
the DMA transfers with the LPC module. Software should set all these bits to 1's.
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GPIO_52_to_49_Cntrl - RW – 16 bits - [PCI_Reg: 50h]
Field Name
GPIO_Out
Bits
Default
Description
Write 1 to set and 0 to clear each of the GPIO port; providing
the corresponding enable bits (7:4) are set to 0
Bit[0] for GPIO49/FANOUT2
3:0
0h
Bit[1] for GPIO50/FANIN0
Bit[2] for GPIO51/FANIN1
Bit[3] for GPIO52/FANIN2
GPIO_Out_En#
7:4
Fh
GPIO output port enable for each of the GPIO port
0: Output = GPIO_Out
1: Output = tristate
GPIO_Status
Reserved
11:8
15:12
-
0h
GPIO input status for each of the GPIO port
GPIO_52_to_49_Cntrl register
GPIO_56_to_53_Cntrl - RW – 16 bits - [PCI_Reg: 52h]
Field Name
GPIO_Out
Bits
Default
Description
Write 1 to set and 0 to clear each of the GPIO port; providing
the corresponding enable bits (7:4) are set to 0
Bit[0] for GPIO53/VIN0
3:0
0h
Bit[1] for GPIO54/VIN1
Bit[2] for GPIO55/VIN2
Bit[3] for GPIO56/VIN3
GPIO_Out_En#
7:4
Fh
GPIO output port enable for each of the GPIO port
0: Output = GPIO_Out
1: Output = tristate
GPIO_Status
Reserved
11:8
15:12
-
0h
GPIO input status for each of the GPIO port
GPIO_56_to_53_Cntrl register
GPIO_60_to_57_Cntrl - RW – 16 bits - [PCI_Reg: 54h]
Field Name
GPIO_Out
Bits
Default
Description
Write 1 to set and 0 to clear each of the GPIO port providing
the corresponding enable bits (7:4) are set to 0
Bit[0] for GPIO57/VIN4
3:0
0h
Bit[1] for GPIO58/VIN5
Bit[2] for GPIO59/VIN6
Bit[3] for GPIO60/VIN7
GPIO_Out_En#
7:4
Fh
GPIO output port enable for each of the GPIO port
0: Output = GPIO_Out
1: Output = tristate
GPIO_Status
Reserved
11:8
15:12
-
0h
GPIO input status for each of the GPIO port
GPIO_60_to_57_Cntrl register
GPIO_64_to_61_Cntrl - RW – 16 bits - [PCI_Reg: 56h]
Field Name
GPIO_Out
Bits
Default
Description
Write 1 to set and 0 to clear each of the GPIO port providing
the corresponding enable bits (7:4) are set to 0
Bit[0] for GPIO61/TEMPIN0
3:0
0h
Bit[1] for GPIO62/TEMPIN1
Bit[2] for GPIO63/TEMPIN2
Bit[3] for GPIO64/TEMPIN3
GPIO_Out_En#
7:4
Fh
GPIO output port enable for each of the GPIO port
0: Output = GPIO_Out
1: Output = tristate
GPIO_Status
Reserved
11:8
15:12
-
0h
GPIO input status for each of the GPIO port
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GPIO_64_to_61_Cntrl - RW – 16 bits - [PCI_Reg: 56h]
Field Name
Bits
Default
Description
GPIO_64_to_61_Cntrl register
ASFSMbusIoBase- RW - 16 bits - [PCI_Reg: 58h]
Field Name
Bits
Default
Description
ASFSMBusEnable
0
0h
0 – Disable ASF controller
1 – Enable ASF controller
Reserved
ASFSMBase
3:1
15:4
000b
FFFh
ASF SM bus controller Io base address
GPIO_73_to_70_Cntrl - RW – 16 bits - [PCI_Reg: 5Ah]
Field Name
GPIO_Out
Bits
Default
Description
Write 1 to set and 0 to clear each of the GPIO port ; providing
the corresponding GPIO_OUT_En# and GPIO_Enable are set
appropriately
3:0
0h
Bit[0] for GPIO70/REQ3#
Bit[1] for GPIO71/REQ4#
Bit[2] for GPIO72/GNT3#
Bit[3] for GPIO73/GNT4#
GPIO_Out_En#
7:4
Fh
GPIO output port enable for each of the GPIO port
0: Output = GPIO_Out
1: Output = tristate
GPIO_Status
GPIO_Enable
11:8
15:12
-
0h
GPIO input status for each of the GPIO port
GPIO function enable for each of the GPIO port
When set, the pin becomes GPIO
0: GPIO disabled
1: GPIO enabled
GPIO_73_to_70_Cntrl register
SmartPowerControl1A - RW – 8 bits - [PCI_Reg: 5Ch]
Field Name
CheckLpc
Bits
Default
Description
0
0b
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt if LPC is idle
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt if HD audio is
idle
CheckAz
1
0b
CheckAc97
2
3
0b
0b
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt if AC97 is idle
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt if HD Audio
PCIBridge is idle
CheckPciBridge
CheckUsb
CheckSata
CheckIde
CheckC3
4
5
6
7
0b
0b
0b
0b
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt if USBis idle
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt if SATA is idle
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt if IDE is idle
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt if CPU is in C3
state
SmartPowerControl1A register
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SMBus Module and ACPI Block (Device 20, Function 0)
AMD SB600 Register Reference Manual
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SmartPowerControl1B - RW – 8 bits - [PCI_Reg: 5Dh]
Field Name
CheckVIN0
Bits
Default
Description
0
0b
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt if VIN0 has
reached or passed the threshold
CheckVIN1
CheckVIN2
CheckVIN3
CheckVIN4
CheckVIN5
CheckVIN6
CheckVIN7
1
2
3
4
5
6
7
0b
0b
0b
0b
0b
0b
0b
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt if VIN1 has
reached or passed the threshold
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt if VIN2 has
reached or passed the threshold
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt if VIN3 has
reached or passed the threshold
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt if VIN4 has
reached or passed the threshold
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt if VIN5 has
reached or passed the threshold
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt if VIN6 has
reached or passed the threshold
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt if VIN7 has
reached or passed the threshold
SmartPowerControl1B register
MiscEnable- RW - 8 bits - [PCI_Reg: 62h]
Field Name
IRQ1_Filter
Bits
Default
Description
0
0b
Keyboard interrupt filter enable (IRQ1)
Filtering is done so that the first rising edge of IRQ1 would
cause the IRQ1 going to the PIC (8259 programmable
interrupt controller) to go asserted, but subsequent changes to
IRQ1 would not have any effect on the IRQ1 going to the PIC
until a access to the keyboard was done (I/O read
of port 60.
The Main effect is that software could mask IRQ1, do several
accesses / commands to the keyboard controller that
subsequently cause numerous IRQ1’s, do one final I/O read
access of port 60 and know that when IRQ1 was unmasked
that no pending keyboard interrupt would be generated.
Mouse Interrupt Filter Enable (IRQ12)
0 – Disable IRQ12 filtering
1 – Enable IRQ12 filtering
K8 INTR Enable (BIOS should set this bit after PIC
initialization)
IRQ12_Filter
K8_INTR
1
2
0b
0b
0 – Disable K8 INTR message
1 – Enable K8 INTR message
MT3_Set
3
4
0b
0b
If this bit is set, K8 INTR NMI Message Type field (Bit3) is
forced to be 1; otherwise K8 INTR NMI Message Type is
controlled by MT3_Auto. Recommended method is to use
MT3_Auto bit.. In AMD K8 system, all interrupts are sent to
CPU via messages. In MP base (such as Linux), the message
may need to be in certain format.
If this bit is set, K8 INTR NMI Message Type field (Bit3) is 1 if
APIC is also active; otherwise K8 INTR NMI Message Type is
0
MT3_Auto
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AMD SB600 Register Reference Manual
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MiscEnable- RW - 8 bits - [PCI_Reg: 62h]
Field Name
Bits
Default
Description
USB_Fast_SMI_Disable
5
0b
For K8 system, legacy USB can request SMI# to be sent out
early before IO completion. Some applications may have
problem with this feature. BIOS should set this bit to 1 to
disable the feature.
Reserved
IDE_GPIO_Enable
MiscEnable register
6
7
0b
0b
If this bit is set to 1, the IDE bus is configured as GPIO
AzIntMap- RW - 8 bits - [PCI_Reg: 63h]
Field Name
Bits
Default
Description
AzIntMap
2:0
110b
Interrupt routing table for HD Audio. Setting this register
routes the HD audio’s interrupt to the specific PCI interrupt
before it is routed to the interrupt controller
000 – INTA#
001 – INTB#
010 – INTC#
011 – INTD#
100 – INTE#
101 – INTF#
110 – INTG#
111 – INTH#
Reserved
7:3
00000b
Features Enable- RW - 32 bits - [PCI_Reg: 64h]
Field Name
Bits
Default
Description
PIC_Enable
0
1b
PIC (8259) Programmable Interrupt Controller enable
0 - I/O cycles to master PIC:20,21, slave PIC:a0, a1, ELCR
registers 4D0, 4D1h, and the PCI interrupt Mapping Registers
(C00, C01), and Numberic Coprocessor Error Register
(IRQ13) (0F0h) are not accepted.
1 - (default) I/O cycles to APIC are not decoded but I/O cycles
to these above addresses will be positive decoded on PCI and
run to the internal 8259 PIC
Timer_Enable
1
2
1b
1b
0 – I/O cycles to timers/counter (040-043h) will not be claimed
on ISA
1 – I/O cycles to timers/counter will be claimed on ISA and run
to the internal 8254 Timer/Counter
PMIO_Register Enable
Power management enable register
0 – I/O cycles to Power management registers (CD6 and
CD7h) will not be claimed
1 – I/O cycles to Power management registers will be claimed
and run to the internal Power Management logic (BIOS should
always set it to 1)
Ioapic_enable
CheckOwnReq
3
4
0b
0b
When set, this block will decode ioapic address
If set, the SB600 will check its own REQ# as the PCI_ACTIVE
signal in addition to BMREQ#
BmReqEn
Reserved
XIOAPIC_ENA
GEVENT5_ENA
Ext_KBRST_EnB
5
6
7
8
9
0b
0b
1b
0b
0b
BMREQ# enable
XIOAPIC enable; this bit is only valid if bit 3 is set.
BIOS should always set this bit to 1 to enable GEVENT5.
Enable external KB_RST# input. When set to 0, GEVENT[1]
is used as KBRST# input
MultiMediaTimerIrqEn
Ext_A20En
10
11
0b
0b
High Precision Event Timer (also called Multimedia Timer)
interrupt enable
Enable external Ga20In input. When set to 1, GEVENT[0] is
used as Ga20In input
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AMD SB600 Register Reference Manual
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Page 107
Features Enable- RW - 32 bits - [PCI_Reg: 64h]
Field Name
Smi_Gevent_En
Bits
Default
Description
Enable all the events with the capability of doing both SMI#
and SCI to SMI# assertion. If enabled, an assertion at any of
the event inputs will cause SMI# to be asserted if SCI EN is
not set.
12
0b
0 – Disable
1 – Enable
Intr_block_En
13
14
0b
0b
Applicable in the PIC system. When enabled, it will block any
pending interrupt for approximately 500ns after IntrAck cycle
from the host.
0 – Disable
1 – Enable
When set, port 0 of APIC is connected to output of the PIC and
port 2 is connected to IRQ0 (timer0)
When clear, port 0 of APIC is connected to IRQ0 (timer0) and
port 2 is connected to the output of the PIC. Software should
set this bit to conform with MP spec.
USB SMI# enable:
ApicPort02Swap
UsbSmiEn
15
16
0b
0b
1 = Enable
0 = Disable
Enable SERR# to SMI# assertion
0 – Disable
Serr2Smi_En
1 – Enable
Gevent1_en0
Gevent1_en1
Gevent1_en2
LpcEnable
17
18
19
20
21
0b
0b
0b
0b
0b
GEVENT group 0 enable (GPM[7] to SMI#/SCI enable) to
ACPI function
GEVENT group 1 enable (GPM[6] to SMI#/SCI enable) to
ACPI function
GEVENT group 2 enable (GPM[5:4] to SMI#/SCI enable) to
ACPI function
1 – Enable lpc controller
0 – Disable lpc controller
RtcSelect
Writing this bit with 1 will toggle the selection between Internal
RTC and External RTC which is set via strap bit.
Reading this bit returns the internal/external mode:
1 = External RTC
0 = Internal RTC
Gevent1_en3
22
0b
0b
0b
0b
GEVENT group 3 enable (ExtEvent[1:0], PCIePme) to ACPI
function
GEVENT group 4 enable (GPM[3:0]) to ACPI function
Gevent1_en4
Reserved
DmaVerifyEn
23
24
25
With LPC is replacing the ISA bus, software needs to set this
bit in order to for DMA verify to work properly
This is the old method to merge the normal IRQ1 with the USB
legacy IRQ1 function. Since this is no longer needed, software
should always leave this bit with 0.
This is the old method to merge the normal IRQ12 with the
USB legacy IRQ12 function. Since this is no longer needed,
software should always leave this bit with 0.
SB_ClkStpEn[0] enables PciStpB to stop primary PCI clock.
SB_ClkStpEn[1] enables PciStpB to stop secondary PCI clock
USB A20 enable
IRQ1MergeEn
IRQ12MergeEn
SB_ClkStpEn
26
27
0b
29:28
00b
UsbA20En
UsbLegacyIrqEn
Features Enable register
30
31
0b
0b
Enable for IRQ1/12 from USB (BIOS should always set it to 1)
UsbEnable - RW - 8 bits - [PCI_Reg: 68h]
Field Name
EHCI_enable
OHCI_0_enable
OHCI_1_enable
Bits
Default
Description
0
1
2
1b
1b
1b
Set to 1 to enable EHCI
Set to 1 to enable OHCI_0
Set to 1 to enable OHCI_1
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AMD SB600 Register Reference Manual
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Page 108
UsbEnable - RW - 8 bits - [PCI_Reg: 68h]
Field Name
OHCI_2_enable
OHCI_3_enable
OHCI_4_enable
Reserved
Bits
Default
Description
3
4
5
1b
1b
1b
Set to 1 to enable OHCI_2
Set to 1 to enable OHCI_3
Set to 1 to enable OHCI_4
7:6
00b
UsbEnable register
SeriallrqControl- RW - 8 bits - [PCI_Reg: 69h]
Field Name
NumStartBits
Bits
Default
Description
This field defines the number of clocks in the start frame.
Start Frame Width = 4 + 2 * NumStartBits
Total number of serial IRQ's = 17 + NumSerIrqbits
0 - 17 serial IRQ's (15 IRQ, SMI#, + IOCHK#)
1 - 18 serial IRQ's (15 IRQ, SMI#, IOCHK#, INTA#)
...
1:0
00b
NumSerIrqBits
5:2
0h
15 - 32 serial IRQ's
The SB600 serial IRQ can support 15 IRQ#, SMI#, IOCHK#,
INTA#, INTB#, INTC#, and INTD#.
When serial SMI# is used, BIOS will need to check SIO (or
device that generates serial SMI#) for status.
0 - Continuous mode
1 - Active (quiet) mode
Setting this bit to 1 enable the serial IRQ function
SerIrqMode
6
7
0b
0b
SerialIrqEnable
SeriallrqControl register
RTCProtect- RW - 8 bits - [PCI_Reg: 6Ah]
Field Name
Bits
Default
Description
RTCProtect38_3F
0
0b
When set, RTC RAM index 38:3Fh will be locked from
read/write. This bit can only be written once.
RTCProtectF0_FF
RTCProtectE0_EF
RTCProtectD0_DF
RTCProtectC0_CF
1
0b
0b
When set, RTC RAM index F0:FFh will be locked from
read/write. This bit can only be written once.
When set, RTC RAM index E0:EFh will be locked from
read/write. This bit can only be written once.
When set, RTC RAM index D0:DFh will be locked from
read/write. This bit can only be written once.
When set, RTC RAM index C0:CFh will be locked from
read/write. This bit can only be written once.
2
3
0b
4
0b
Reserved
7:5
000b
RTCProtect register
USB Reset- RW - 8 bits - [PCI_Reg: 6Bh]
Field Name
Force Reset to USB Host
Controllers
Bits
Default
Description
These are software control bits that force the reset of the USB
host controllers.
4:0
00h
Force USB Port PHY
Power Down
Force PHY PLL Power
Down
Force USB Port PHY
Reset
5
6
7
0b
0b
0b
Forces USB PHY into power down mode.
Forces USB PHY PLL into power down mode.
Forces USB PHY reset.
USB Reset register
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SMBus Module and ACPI Block (Device 20, Function 0)
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Page 109
TestMode- RW - 16 bits - [PCI_Reg: 6C]
Field Name
DMA_Timing
Bits
Default
Description
0
0b
To be used by BIOS only; when set, legacy DMA will insert 1
extra idle clock in between requests. Software should always
set this bit.
TestMode
4:1
5
0h
0b
These bits are for testing only. Software should not write to
these bits.
When set, PCIB_SReset_En (x3e bit 22 of PCI Bridge) will be
writable.
These bits are for testing only. Software should not write to
these bits.
PCIB_SReset_En Mask
TestMode
15:6
000h
TestMode register
IoApic_Conf- RW - 32 bits - [PCI_Reg: 74h]
Field Name
Reserved
Mem_IO_Map
Bits
Default
000b
1b
Description
2:0
3
Base address mapping
1 = memory map
0 = IO map
Reserved
4
0b
IoApic_Addr
31:5
1111_
1110_
1100_
0000_
0000_
0000_
000b
Base address for IOAPIC
IoApic_Conf register.
IoAddrEnable - RW - 32 bits - [PCI_Reg: 78h]
Field Name
Bits
Default
Description
DmaAddr_En
0
1b
0x000:0x01F, 0x080:0x08F, 0x0C0:0xCF, 0x0D0:0x0DF,
0x40B, 0x4D6,
0x40,0x41, 0x42, 0x43
0x70
0x71
0xC14
0xC49, 0xC4A
0xC52
0xC6C
0xC6F
0xCD6,0 xCD7
PitAddr_En
1
2
3
4
5
6
7
8
9
1b
1b
1b
1b
1b
1b
1b
1b
1b
NmiAddr_En
RtcAddr_En
Misc_Enable1
Misc_Enable2
Misc_Enable3
Misc_Enable4
Misc_Enable5
PM_Addr_Enable
Reserved
Cms_Enable
Reserved
Port92Enable
Reserved
10
11
13:12
14
31:15
0b
1b
Address 0xC50, 0xC51
Port 92 enable
00b
1b
00000h
IoAddrEnable Register: When a bit is set, this block will decode the corresponding address. If the bit is cleared, this
block will not claim the corresponding address. This is to allow the legacy port to be behind the PCI bridge.
GPIO_69_68_66_65_Cntrl - RW – 16 bits - [PCI_Reg: 7Eh]
Field Name
GPIO_Out
Bits
Default
Description
Write 1 to set and 0 to clear each of the GPIO port providing
the corresponding bits [7:4] are enabled
Bit[0] for GPIO65/BMREQ#
3:0
0h
Bit[1] for GPIO66/LLB#
Bit[2] for GPIO68/LDRQ1#
Bit[3] for GPIO69/RTC_IRQ#
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AMD SB600 Register Reference Manual
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Page 110
GPIO_69_68_66_65_Cntrl - RW – 16 bits - [PCI_Reg: 7Eh]
Field Name
GPIO_Out_En#
Bits
Default
Description
GPIO output port enable for each of the GPIO port
0: Output = GPIO_Out
7:4
Fh
1: Output = tristate
GPIO_Status
Reserved
11:8
15:12
-
0h
GPIO input status for each of the GPIO port
GPIO_69_68_66_65_Cntrl register
GPIO_3_to_0_Cntrl - RW – 16 bits - [PCI_Reg: 80h]
Field Name
GPIO_Out
Bits
Default
Description
Write 1 to set and 0 to clear each of the GPIO port providing
the corresponding bits [7:4] are enabled
Bit[0] for GPIO0/ SSMUXSEL
3:0
0h
Bit[1] for GPIO1/ROM_CS#
Bit[2] for GPIO2/SPKR
Bit[3] for GPIO3/FANOUT0
GPIO_Out_En#
7:4
Fh
GPIO output port enable for each of the GPIO port
0: Output = GPIO_Out
1: Output = tristate
For GPIO1, this is applicable only if we are not using the
external PCI bus as the ROM interface.
GPIO input status for each of the GPIO port
GPIO_Status
11:8
-
Reserved
15:12
0h
GPIO_3_to_0_Cntrl register
GPIO_32_31_14_13_Cntrl - RW – 16 bits - [PCI_Reg: 82h]
Field Name
GPIO_Out
Bits
Default
Description
Write 1 to set and 0 to clear each of the GPIO port providing
the corresponding bits [7:4] and [15:12] are enabled
Bit[0] for GPIO13/LAN_RST#
3:0
0h
Bit[1] for GPIO14/ROM_RST#
Bit[2] for GPIO31/SPI_HOLD#
Bit[3] for GPIO32/SPI_CS#
GPIO_Out_En#
7:4
Fh
GPIO output port enable for each of the GPIO port
0: Output = GPIO_Out
1: Output = tristate
GPIO_Status
GPIO_Enable
11:8
15:12
-
0h
GPIO input status for each of the GPIO port
GPIO function enable for each of the GPIO port
0: GPIO disabled
1: GPIO enabled
GPIO_32_31_14_13_Cntrl register
Smbus Base Address - R – 32 bits - [PCI_Reg: 90h]
Field Name
IO/Memory
Bits
Default
Description
0
1b
1 = IO
0 = Memory
Reserved
3:1
000b
SmBusBaseAd
31:4
0000000h SMBus Base Address
Smbus Base Address register (also accessible through 10h)
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SMBus Module and ACPI Block (Device 20, Function 0)
AMD SB600 Register Reference Manual
Proprietary
Page 111
SmartPowerControl2A - RW – 8 bits - [PCI_Reg: 98h]
Field Name
CheckLpc
Bits
Default
Description
0
0b
If SmartVoltEnable2 is set and this bit is also set, the
SmartPower2 function will only assert SmartVolt2 if LPC is idle
If SmartVoltEnable2 is set and this bit is also set, the
SmartPower2 function will only assert SmartVolt2 if azalia (HD
audio) is idle
If SmartVoltEnable2 is set and this bit is also set, the
SmartPower2 function will only assert SmartVolt2 if AC97 is
idle
CheckAz
1
2
3
0b
0b
0b
CheckAc97
CheckPciBridge
If SmartVoltEnable2 is set and this bit is also set, the
SmartPower2 function will only assert SmartVolt2 if azalia
PCIBridge is idle
CheckUsb
CheckSata
4
5
0b
0b
If SmartVoltEnable2 is set and this bit is also set, the
SmartPower2 function will only assert SmartVolt2 if USBis idle
If SmartVoltEnable2 is set and this bit is also set, the
SmartPower2 function will only assert SmartVolt2 if SATA is
idle
CheckIde
CheckC3
6
7
0b
0b
If SmartVoltEnable2 is set and this bit is also set, the
SmartPower2 function will only assert SmartVolt2 if IDE is idle
If SmartVoltEnable2 is set and this bit is also set, the
SmartPower2 function will only assert SmartVolt2 if CPU is in
C3 state
SmartPowerControl2A register
SmartPowerControl2B - RW – 8 bits - [PCI_Reg: 99h]
Field Name
CheckVIN0
Bits
Default
Description
0
0b
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt2 if VIN0 has
reached or passed the threshold
CheckVIN1
CheckVIN2
CheckVIN3
CheckVIN4
CheckVIN5
CheckVIN6
CheckVIN7
1
2
3
4
5
6
7
0b
0b
0b
0b
0b
0b
0b
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt2 if VIN1 has
reached or passed the threshold
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt2 if VIN2 has
reached or passed the threshold
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt2 if VIN3 has
reached or passed the threshold
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt2 if VIN4 has
reached or passed the threshold
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt2 if VIN5 has
reached or passed the threshold
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt2 if VIN6 has
reached or passed the threshold
If SmartVoltEnable is set and this bit is also set, the
SmartPower function will only assert SmartVolt2 if VIN7 has
reached or passed the threshold
SmartPowerControl2B register
SmartPowerControl2C - RW – 8 bits - [PCI_Reg: 9Ah]
Field Name
Bits
Default
Description
SmartVoltIdleTime2
6:0
0h
Amount of “idle” time (in 2us increment) the SmartPower2
function should wait before it should assert SmartVolt 2
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AMD SB600 Register Reference Manual
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Proprietary
Page 112
SmartPowerControl2C - RW – 8 bits - [PCI_Reg: 9Ah]
Field Name
Bits
Default
Description
SmartVoltEnable2
7
0b
Enable bit for the SmartPower2 function. When set, the logic
will monitor the logic (defined by 98h). If all of the
corresponding modules are idle,
SmartPowerControl2C register
SmartVolt function is meant to provide a mechanism to control the external power supply in order to reduce
additional system power consumption. For example, software can set SmartPowerControl2A[6] and
SmartPowerControl2A[7]. Whenever CPU enters C3 state and IDE (PATA) controller is not active, this function will
assert GPIO5. System design can use this signal to control the power supply to reduce the ATA power by 5~10%.
Another example is to connect an ambient light sensor to one of the VIN inputs. When the circuit has detected the
ambient light is below certain threshold, this function can automatically dim the LCD back light.
IDE_GPIO_Cntrl – RW - 32 bits - [PCI_Reg:A0]
Field Name
GPIO_Out
Bits
Default
Description
When the IDE bus is used as GPIO, these bits control the
output of each IDE data bit; providing the corresponding bits
[31:16] are enabled
15:0
0000h
GPIO_Out_En#
31:16
FFFFh
When the IDE bus is used as GPIO, these bits control the
output enable of each IDE data bit.
0 = Enable
1 = Tristate
IDE_GPIO_Cntrl register
IDE_GPIO_In – R - 16 bits - [PCI_Reg: A4h]
Field Name
Bits
Default
Description
GPIO_Status
15:0
----
When the IDE bus is used as GPIIO, these are the read ports
for each IDE data bit.
IDE_GPIO_In register
GPIO_48_47_46_37_Cntrl - RW – 16 bits - [PCI_Reg: A6h]
Field Name
GPIO_Out
Bits
Default
Description
Write 1 to set and 0 to clear each of the GPIO port providing
the corresponding bits [7:4] and [15:12] are enabled
Bit[0] for GPIO37/DPSLP_OD#
3:0
0h
Bit[1] for GPIO46/AZ_SDIN3
Bit[2] for GPIO47/SPI_CLK
Bit[3] for GPIO48/FANOUT1
GPIO_Out_En#
7:4
Fh
GPIO output port enable for each of the GPIO port
0: Output = GPIO_Out
1: Output = tristate
GPIO_Status
GPIO_Enable
11:8
15:12
-
0h
GPIO input status for each of the GPIO port
GPIO function enable for each of the GPIO port
0: GPIO disabled
1: GPIO enabled
Bit[13] [15] no effect
Use PM_Reg: 60h bit [2] to configure GPIO48/FANOUT1.
GPIO_48_47_46_37_Cntrl register
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AMD SB600 Register Reference Manual
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GPIO_12_to_4_Cntrl – RW – 32 bits - [PCI_Reg: A8h]
Field Name
GPIO_Out
Bits
Default
Description
Write 1 to set and 0 to clear each of the GPIO port providing
the corresponding bits [15:8], [25], [31:30] are enabled
Output for GPIO[12:11][9:4]
7:0
00h
Bit[0] for GPIO4/SMARTVOLT
Bit[1] for GPIO5/SHUTDOWN/SMARTVOLT2
Bit[2] for GPIO6/GNI#
Bit[3] for GPIO7/VGATE
Bit[4] for GPIO8/DDC1_SDA
Bit[5] for GPIO9/DDC1_SCL
Bit[6] for GPIO11/SPI_DO
Bit[7] for GPIO12/SPI_DI
GPIO_Out_En#
15:8
FFh
GPIO output port enable for each of the GPIO port
0: Output = GPIO_Out
1: Output = tristate
GpioIn
GPIO10_Out
GPIO10_Out_En#
23:16
24
25
-
0b
1b
GPIO input status for each of the GPIO port
Write 1 to set and 0 to clear GPIO10/SATA_IS0#
GPIO output port enable for GPIO10/SATA_IS0#
0: Output = GPIO10_Out
1: Output = tristate
GPIO10_Status
Reserved
GPIO_Enable
26
29:27
31:30
-
GPIO input status for GPIO10/SATA_IS0#
000b
0h
GPIO function enable for GPIO[12:11]
0: GPIO disabled
1: GPIO enabled
GPIO_12_to_4_Cntrl register
SATA_Cntrl - RW – 16 bits - [PCI_Reg: ACh]
Field Name
GPIO67_Out
GPIO67_Out_En#
Bits
Default
Description
0
1
0b
1b
Write 1 to set and 0 to clear GPIO67/SATA_ACT#
GPIO output port enable for GPIO67/SATA_ACT#
0: Output = GPIO67_Out
1: Output = tristate
GPIO67_Status
GPIO67_Enable
2
3
-
0b
GPIO input status for GPIO67/SATA_ACT#
GPIO function enable for GPIO67/SATA_ACT#
0: GPIO disabled
1: GPIO enabled
SMI_CMD_action
4
1b
If this bit is enabled, SMI_CMD or SLP_trap will cause SMI
being sent to host regardless of EOS status. Otherwise, SMI is
sent only when EOS=1.
Reserved
SataEnable
SataSmbusCfg
7:5
8
10:9
0h
1b
00b
SATA enable
SATA SMBus configuration.
00: Reserved
01: Disable SATA SMBus
10: Reserved
11: Enable SATA SMBu
There is only one SATA SMBus (I2C) interface for the two
SATA controllers. The SATA I2C interface is only used for
characterization purposes. Use either an external I2C master
or the on-chip SMBus as I2C master to talk to the SATA I2C
target.
Reserved
SataPsvEn
Reserved
12:11
13
14
00b
1b
0b
SATA power saving enable
HiddenMsiEnable
15
0b
Setting this bit will make PCI_Reg:B0h, bit 16 to show up as 1.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
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Page 114
SATA_Cntrl - RW – 16 bits - [PCI_Reg: ACh]
Field Name
Bits
Default
Description
ExtendIntrToWakeTime
18:16
000b
This is used in K8 system to extend the interrupt break event
status. Whenever there is an apic interrupt, this logic will
extend the break event status by the amount of time defined
by this register. This is to avoid potential race condition
between CPU issuing the C1e command and the SB seeing
an interrupt. If CPU tries to enter C state before the extension
time expires, SB will break out from the C state. Each count
represents 2 microsecond increment and it has an uncertainty
of 2 microseconds.
DrqMaskEn
19
20
0b
0b
Setting this bit to 1 will cause the legacy DMA request to be
blocked if the DMA channel has not been initialized properly.
This bit is applicable to ASIC revision A21 and above.
Setting this bit to 1 will cause narrow pulses (less than several
A-link clocks wide) on the IDE IRQ line to be filtered out. This
means that no interrupt will be generated. This bit is applicable
to ASIC revision A21 and above.
IdeIrqFilterEn
TmrIrqEnhanceDisable
PIC_APIC_coexist
21
22
0b
0b
This bit should be set to 1 for the normal operation of the 8254
timer. This setting is required by ASIC revisions A11, A12, and
A13.
This bit should be set to 1 if PIC and APIC are to be enabled
at the same time in K8 system. There is no harm done even if
they don’t coexist at the same time.
Reserved
SataIntMap
25:23
28:26
000b
000b
SATA interrupt mapping to PCI interrupt
000 - INTA#, 001 - INTB#, 010 - INTC#, 011 - INTD#, 100 -
INTE#, 101 - INTF#, 110 - INTG#, 111 - INTH#
Reserved
31:29
000b
SATA_Cntrl register
MSI Mapping Capability - R - 32 bits - [PCI_Reg: B0h]
Field Name
Capability ID
Capability Pointer
MsiEnable
Bits
7:0
15:8
16
Default
08h
00h
0b
Description
This is a HyperTransport capability list item.
This is the end of capability list.
MSI enable programmable through PCI_Reg: ADh bit 7
The address for mapping MSIs is fixed at
0000_0000_FEEx_xxxxh.
Fixed
17
1b
Reserved
Capability Type
26:18
31:27
000h
10101b
This is an MSI Mapping Capability block.
MSI Mapping Capability register
PciIntGpio - RW - 16 bits - [PCI_Reg: BCh]
Field Name
PciIntGpioOut
Bits
Default
Description
3:0
0h
Output data for each PCI INT# GPIO providing bits [7:4] and
[15:12] are enabled
PciIntGpioEnB
PciIntGpioStatus
PciIntIsGpio
7:4
11:8
15:12
Fh
-
0h
Output enable for each PCI INT# GPIO (active low)
Input status for each PCI INT# GPIO [Read Only]
Set to 1 to use PCI interrupt INTH/G/F/E# as GPIO
PciIntGpio register
UsbIntMap - RW - 16 bits - [PCI_Reg: BEh]
Field Name
UsbInt1Map
UsbInt2Map
Reserved
Bits
Default
000b
001b
00b
Description
2:0
5:3
(OHCI0) UsbInt1 interrupt mapping to PCI interrupt
(OHCI1 & OHCI3) UsbInt2 interrupt mapping to PCI interrupt
7:6
UsbInt3Map
UsbInt4Map
10:8
13:11
010b
011b
(OHCI2 & OHCI4) UsbInt3 interrupt mapping to PCI interrupt
(EHCI) UsbInt4 interrupt mapping to PCI interrupt
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AMD SB600 Register Reference Manual
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Page 115
UsbIntMap - RW - 16 bits - [PCI_Reg: BEh]
Field Name
Reserved
Bits
Default
Description
15:14
00b
UsbIntMap register
Encoding:
000 - INTA#, 001 - INTB#, 010 - INTC#, 011 - INTD#, 100 - INTE#, 101 - INTF#, 110 - INTG#, 111 - INTH#
IoDrvSth - RW - 32 bits - [PCI_Reg: C0h]
Field Name
IoDrvSth_AD
Bits
Default
Description
1:0
11b
IO drive strength (bits [2:1]); together with bit 26 make up the
drive strength control for AD[31:0], CBE0#, CBE1#, CBE2#,
CBE3# and PAR pads.
IoDrvSth_Cntrl
IoDrvSth_GNT
3:2
5:4
11b
11b
IO drive strength (bits [2:1]); together with bit 26 make up the
drive strength control for A_RST#, FRAME#, IRDY#,
DEVSEL#, TRDY#, LOCK#, STOP#, PERR#, SERR#,
CLKRUN# and PCIRST# pads
IO drive strength (bits [2:1];; together with bit 27 make up the
drive strength control for GNT#[2:0], GNT3#, GNT4#, GNT5#,
and GNT6# pads
IoDrvSth_ClkGrpA
IoDrvSth_ClkGrpB
IoDrvSth_Lpc
7:6
9:8
11b
11b
11b
IO drive strength (bits [2:1];; together with bit 27 make up the
drive strength control for PCICLK[6:5] pads
IO drive strength (bits [2:1];; together with bit 27 make up the
drive strength control for PCICLK[4:1] pads
IO drive strength (bits [2:1];; together with bit 28 make up the
drive strength control for LAD[3:0], LFRAME#, and
LDRQ#[1:0] pads
12:11
IoDrvSth_Ac97
IoDrvSth_Int
13:12
15:14
17:16
19:18
11b
11b
11b
11b
IO drive strength for AC_SYNC, AC_SDOUT and SPDIF_OUT
pads
IO drive strength for INTA#, INTB#, INTC#, INTD#, INTE#,
INTF#, INTG# and INTH# pads
IO drive strength for REQ#[1:0], REQ3#, REQ4#, REQ5# and
REQ6# pads when these pads are configured as GPIO
IO drive strength for BMREQ#, EXTEVENT1#, GPIO[0, 1, 2, 4,
5, 6, 7, 8, 9, 10, 13, 37], GPOC[0:1], DPRSLPVR,
IO drive strength for GPIO[3, 48:52],
IO drive strength (bits [2:1];; together with bit 29 make up the
drive strength control for CPU_STP#/DPSLP_3V#, GA20IN,
KBRST#, SERIRQ and SATA_ACT# pads
IO drive strength for IDE pads
IoDrvSth_Req
IoDrvSth_GpioA
IoDrvSth_GpioB
IoDrvSth_Misc
21:20
23:22
11b
IoDrvSth_Ide
25:24
26
27
28
29
11b
1b
1b
1b
1b
IoDrvSth_AD_0
IoDrvSth_GNT_0
IoDrvSth_Lpc_0
IoDrvSth_Misc_0
Reserved
Bit 0 of IoDrvSth_AD
Bit 0 of IoDrvSth_GNT
Bit 0 of IoDrvSth_Lpc
Bit 0 of IoDrvSth_Misc
31:30
11b
IoDrvSth: Each three bit field controls the number of P and N transistors enabled in the final stage of the output
driver for the designated pads. By controlling the number of transistors enabled, the designer can optimize the drive
characteristics of signals based on the topology of their specific design. For drive strength with 3 bit control, the
drive strength table is shown below. The values are non-linear and values for each bit field of this register are as
follows:
Value
111b
110b
101b
100b
011b
010b
001b
000b
Relative Strength
Description
100%
88%
77%
66%
66%
55%
44%
33%
All P and N transistors are enabled when the pad drives
Approximately 88% of the P and N transistors are enabled
Approximately 77% of the P and N transistors are enabled
Approximately 66% of the P and N transistors are enabled
Approximately 66% of the P and N transistors are enabled
Approximately 55% of the P and N transistors are enabled
Approximately 44% of the P and N transistors are enabled
Approximately 33% of the P and N transistors are enabled
©2008 Advanced Micro Devices, Inc.
SMBus Module and ACPI Block (Device 20, Function 0)
AMD SB600 Register Reference Manual
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Page 116
IoDrvSth - RW - 32 bits - [PCI_Reg: C0h]
Field Name
Bits
Default
Description
For control with only two bits, one can assume the four drive strength settings (corresponding to 25, 50, 75, and
100% respectively).
For the PCI interface, bits [3:0] and 26 control the AD and PCI control signals, The table below contains
recommendations based on empirical data collected from a live system:
S2
S1
S0
Percent Drive Strength
Loads
SMBUS PCI Register, Index C0h
Bits[1:0] = 01; Bits[3:2] = 00, bit 26
= 0
0
0
0
33%
For 0-1 loads
Bits[1:0] = 10; Bits[3:2] = 00, bit 26
= 1
0
0
0
0
1
1
1
0
1
44%
55%
66%
For 2 loads
For 3-4 loads
For 4-5 loads
Bits[1:0] = 01; Bits[3:2] = 01, bit 26
= 0
Bits[1:0] = 01; Bits[3:2] = 01, bit 26
= 1
For LPC bus, the drive strength is determined by SMBUS PCI C0h, bits [11:10] and [28]
S2
0
S1
0
S0
0
Percent Drive Strength
Loads
SMBUS PCI Register, Index C0h
Bits[11:10] = 00, bit 28 = 0
Bits[11:10] = 00, bit 28 = 1
Bits[11:10] = 01, bit 28 = 0
Bits[11:10] = 01, bit 28 = 1
33%
44%
55%
66%
For 0-1 loads
For 2 loads
For 3-4 loads
For 4-5 loads
0
0
1
0
1
0
0
1
1
I2CbusConfig - RW - 8 bits - [PCI_Reg: D2h]
Field Name
Bits
Default
Description
I2CController Enable
I2CbusInterrupt
0
1
0b
0b
I2C controller host interface enable
0 : SMI#
1 : IRQ
Reserved
7:2
00h
I2CbusConfig register: Registers D2-D5 control the interface when this chip is the I2C slave.
I2CCommand - RW - 8 bits - [PCI_Reg: D3h]
Field Name
I2Ccommand
Bits
Default
Description
7:0
00h
I2C Host Slave Command; this value specifies the command
value to be matched for I2C master accesses to the
I2Ccontroller host slave interface.
I2CCommand register
I2CShadow1- RW - 8 bits - [PCI_Reg: D4h]
Field Name
Bits
Default
Description
Read/Write ShadowPort1
0
0b
Read/Write for Shadow Port 1
This bit must be programmed to 0 because I2C slave
controller only responds to Word Write Transaction.
SMBus Slave Address for shadow port 1
I2CslaveAddr1
7:1
00h
This value specifies the address used to match against
incoming I2C addresses for Shadow port 1.
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AMD SB600 Register Reference Manual
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary
Page 117
I2CShadow1- RW - 8 bits - [PCI_Reg: D4h]
Field Name
Bits
Default
Description
I2CShadow1 register
I2Cshadow2- RW - 8 bits - [PCI_Reg: D5h]
Field Name
Bits
Default
Description
Read/Write ShadowPort2
0
0b
Read/Write for Shadow Port 2
This bit must be programmed to 0 because I2C slave
controller only responds to Word Write Transaction.
SMBus Slave Address for shadow port 2
I2CslaveAddr2
7:1
00h
This value specifies the address used to match against
incoming I2C addresses for Shadow port 2.
I2Cshadow2 register
I2CBusRevision - RW - 8 bits - [PCI_Reg: D6h]
Field Name
I2CbusRevision
Bits
Default
Description
7:0
00h
Revision ID
I2CBusRevision register
MSI_Weight - RW – 8 bits - [PCI_Reg: E0h]
Bits
5:0
7:6
Default
100000b
00b
Description
Used by bios to tune MSI messaging priority
MSI_weight
Reserved
MSI_Weight register
AB_REG_BAR - RW - 32 bits - [PCI_Reg: F0h]
Field Name
Bits
Default
Description
AB_REG_BAR
31:0
0000_000 Base Address for A-link Bridge Register
0h
AB_REG_BAR register
WakeIoAddr- RW - 16 bits - [PCI_Reg: F4h]
Field Name
Bits
Default
Description
WakeIoAddr
15:0
0000h
IO Address for C-State Wake-up by CPU (K8 only). The BIOS
can program an address inside K8 and this location. The K8
can then use it to generate an IO write to tell SB to wake from
C state (location inside K8 is TBD).
WakeIoAddr register
MwaitID- RW - 8 bits - [PCI_Reg: F6h]
Field Name
Bits
Default
Description
Mwait_physical_ID
3:0
0100b
This is used for P4 dual core system. Two physical CPU IDs
with default values 00 and 01 to match with addr[19:18] of
MWAIT and ADS_after_MWAIT. Usage TBD
Mwait_logical_ID
MwaitID register
7:4
0100b
This is used for P4 dual core system. Two logical CPU IDs
with default values 00 and 01 to match with addr[17:16] of
MWAIT and ADS_after_MWAIT. Usage TBD
MwaitSts- R - 8 bits - [PCI_Reg: F7h]
Field Name
Bits
Default
Description
Mwait_cpu0_sts
0
0b
Set to 1 by MWAIT with addr[19:18] = Mwait_physical_ID[1:0]
and addr[17:16] = Mwait_logical_ID[1:0]. Cleared by
ADS_after_MWAIT with the same addr[19:16].
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AMD SB600 Register Reference Manual
SMBus Module and ACPI Block (Device 20, Function 0)
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Page 118
MwaitSts- R - 8 bits - [PCI_Reg: F7h]
Field Name
Bits
Default
Description
Mwait_cpu1_sts
1
0b
Set to 1 by MWAIT with addr[19:18] = Mwait_physical_ID[3:2]
and addr[17:16] = Mwait_logical_ID[1:0]. Cleared by
ADS_after_MWAIT with the same addr[19:16].
Mwait_cpu2_sts
Mwait_cpu3_sts
Reserved
2
3
0b
0b
0h
Set to 1 by MWAIT with addr[19:18] = Mwait_physical_ID[1:0]
and addr[17:16] = Mwait_logical_ID[3:2]. Cleared by
ADS_after_MWAIT with the same addr[19:16].
Set to 1 by MWAIT with addr[19:18] = Mwait_physical_ID[3:2]
and addr[17:16] = Mwait_logical_ID[3:2]. Cleared by
ADS_after_MWAIT with the same addr[19:16].
7:4
MwaitSts register. This register is to be used for P4 dual core system. Usage TBD.
ExtendedAddrPort- RW - 32 bits - [PCI_Reg: F8h]
Field Name
Bits
Default
Description
ExtendedAddrPort
31:0
00h
Address port for the extended register block
ExtendedAddrPort register..
ExtendedDataPort- RW - 32 bits - [PCI_Reg: FCh]
Field Name
Bits
Default
Description
ExtendedDataPort
31:0
00h
Data port for the extended register block
ExtendedDataPort register.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
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2.3.1.2 Extended Registers
Register Name
AudioPortConfig
AudioGpioControl
Configuration Offset
00h
04h
AudioPortConfig- RW - 32 bits - [Extend_Reg: 00h]
Field Name
AzPort0Config
Bits
Default
Description
1:0
01b
Port configuration for HD Audio and AC97 input port:
00 or 11 = GPIO port
01 = Set as ac97 port
10 = Set as HD Audio port
AzPort1Config
AzPort2Config
AzPort3Config
3:2
5:4
7:6
01b
10b
10b
Port configuration for HD Audio and AC97 input port:
00 or 11 = GPIO port
01 = Set as ac97 port
10 = Set as HD Audio port
Port configuration for HD Audio and AC97input port:
00 or 11 = GPIO port
01 = Set as ac97 port
10 = Set as HD Audio port
Port configuration for HD Audio and AC97input port:
00 or 11 = GPIO port
01 = Set as ac97 port
10 = Set as HD Audio port
Reserved
AudioGpioIn0Status
15:8
16
-
-
-
-
-
When ACZ_SDIN0 is configured as GPIO, this bit returns the
GPIO input status.
When ACZ_SDIN 1 is configured as GPIO, this bit returns the
GPIO input status.
When ACZ_SDIN 2 is configured as GPIO, this bit returns the
GPIO input status.
When ACZ_SDIN 3 is configured as GPIO, this bit returns the
GPIO input status.
AudioGpioIn1Status
AudioGpioIn2Status
AudioGpioIn3Status
AzRstGpioIN
17
18
19
20
When AZ_RST# is configured as GPIO, this bit returns the
GPIO input status.
Reserved
Ac97RstGpioIn
23:21
24
-
-
-
-
-
When AC_RST# is configured as GPIO, this bit returns the
GPIO input status.
When AC_BitClk is configured as GPIO, this bit returns the
GPIO input status.
When AC_Sync is configured as GPIO, this bit returns the
GPIO input status.
When AC_DataOut is configured as GPIO, this bit returns the
GPIO input status.
Ac97BclkGpioIn
Ac97SyncGpioIn
Ac97DOutGpioIn
SpdifGpioIn
25
26
27
28
When AC_SPDIF is configured as GPIO, this bit returns the
GPIO input status.
Reserved
31:29
AudioPortConfig register.
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AMD SB600 Register Reference Manual
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Proprietary
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AudioGpioControl – RW - 32 bits - [Extend_Reg: 04h]
Field Name
Bits
Default
Description
AudioGpioOut0OeB
0
1b
When ACZ_SDIN0 is configured as GPIO, this bit represents
the output enable.
1 – Tristate
0 – Enable
AudioGpioOut1OeB
AudioGpioOut2OeB
AudioGpioOut3OeB
AzRstGpioOutOeB
1
2
3
4
1b
1b
1b
1b
When ACZ_SDIN1 is configured as GPIO, this bit represents
the output enable.
1 – Tristate
0 – Enable
When ACZ_SDIN2 is configured as GPIO, this bit represents
the output enable.
1 – Tristate
0 – Enable
When ACZ_SDIN3 is configured as GPIO, this bit represents
the output enable.
1 – Tristate
0 – Enable
When AZ_RST# is configured as GPIO, this bit represents the
output enable.
1 – Tristate
0 – Enable
Reserved
Ac97RstGpioOutOeB
7:5
8
1b
1b
1b
1b
1b
When AC_RST# is configured as GPIO, this bit represents the
output enable.
1 – Tristate
0 – Enable
When AC_BitClk is configured as GPIO, this bit represents the
output enable.
1 – Tristate
0 – Enable
When AC_Sync is configured as GPIO, this bit represents the
output enable.
1 – Tristate
0 – Enable
When AC_ SDOut is configured as GPIO, this bit represents
the output enable.
1 – Tristate
0 – Enable
Ac97BclkGpioOeB
Ac97SyncGpioOeB
Ac97DOutGpioOeB
SpdifGpioOeB
9
10
11
12
When AC_SPDIF is configured as GPIO, this bit represents
the output enable.
1 – Tristate
0 – Enable
Reserved
AudioGpioOut0
15:13
16
0b
0b
0b
0b
When ACZ_SDIN 0 is configured as GPIO, this bit represents
the output value if the output is enabled.
1 – High
0 – Low
When ACZ_SDIN 1 is configured as GPIO, this bit represents
the output value if the output is enabled.
1 – High
0 – Low
When ACZ_SDIN 2 is configured as GPIO, this bit represents
the output value if the output is enabled.
1 – High
0 – Low
AudioGpioOut1
AudioGpioOut2
AudioGpioOut3
17
18
19
When ACZ_SDIN 3 is configured as GPIO, this bit represents
the output value if the output is enabled.
1 – High
0 – Low
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AMD SB600 Register Reference Manual
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary
Page 121
AudioGpioControl – RW - 32 bits - [Extend_Reg: 04h]
Field Name
AzRstGpioOut
Bits
Default
Description
20
0b
When AZ_RST# is configured as GPIO, this bit represents the
output value if the output is enabled.
1 – High
0 – Low
Reserved
Ac97RstGpioOut
23:21
24
0b
0b
0b
0b
0b
When AC_RST# is configured as GPIO, this bit represents the
output value if the output is enabled.
1 – High
0 – Low
When AC_BITCLK is configured as GPIO, this bit represents
the output value if the output is enabled.
1 – High
0 – Low
When AC_SYNC is configured as GPIO, this bit represents the
output value if the output is enabled.
1 – High
0 – Low
When AC_SDOUT is configured as GPIO, this bit represents
the output value if the output is enabled.
1 – High
0 – Low
Ac97BclkGpioOut
Ac97SyncGpioOut
Ac97DOutGpioOut
SpdifGpioOut
25
26
27
28
When SPDIF_OUT is configured as GPIO, this bit represents
the output value if the output is enabled.
1 – High
0 – Low
Reserved
31:29
AudioGpioControl register.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
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Proprietary
Page 122
2.3.2
SMBus Registers
Register Name
Offset Address
SMBusStatus
SMBusSlaveStatus
SMBusControl
00h
01h
02h
SMBusHostCmd
SMBusAddress
SMBusData0
03h
04h
05h
SMBusData1
06h
SMBusBlockData
SMBusSlaveControl
SMBusShadowCmd
SMBusSlaveEvent
SlaveData
07h
08h
09h
0A-0Bh
0C-0Dh
0Eh
SMBusTiming
Note: The SMBus registers are located at the IO memory space base address defined by PCI configuration
register 90-93h
SMBusStatus - RW - 8 bits - [SMBUS:00h]
Field Name
HostBusy
Bits
Default
Description
0
0b
This bit indicates the SMBus controller is in the process of
completing a command. When this bit is set, software should
not access any other SMBus registers [Read-only]
This bit is set by hardware to indicate the completion of the last
host command. This bit can be cleared by writing an 1 to it.
This bit is set by hardware to indicate an error of one of the
following: 1) illegal command field, 2) unclaimed cycle, 3) host
device time-out. This bit can be cleared by writing an 1 to it.
This bit is set by hardware to indicate SMBus transaction
collision; this bit can be cleared by writing an 1 to it.
This bit is set by hardware to indicate a failed bus transaction,
set when SMBusControl.Kill bit is set. This bit is cleared by
writing an 1 to it
SMBusInterrupt
DeviceErr
1
2
0b
0b
BusCollision
Failed
3
4
0b
0b
Reserved
7:5
000b
SMBusSlaveStatus - RW - 8 bits - [SMBUS:01h]
Field Name
Bits
Default
Description
SlaveBusy
0
0b
This bit indicates the SMBus controller slave interface is in the
process of receiving data. Software should not try to access
any other SMBus register when this bit is set. [Read-only]
Writing a 1 to this bit will initialize the slave. It is unnecessary to
write it back to 0. A read from it will always return a 0.
This bit is set by hardware to indicate a slave cycle event match
of the SMBus slave command and SMBus Slave Event match.
This bit can be cleared by writing an 1 to it.
SlaveInit
1
2
0b
0b
SlaveStatus
Shadow1Status
Shadow2Status
AlertStatus
3
4
5
0b
0b
0b
This bit is set by hardware to indicate a slave cycle address
match of the SMB_Shadow1 port. This bit can be cleared by
writing a 1 to it.
This bit is set by hardware to indicate a slave cycle address
match of the SMB_Shadow2 port. This bit can be cleared by
writing a 1 to it.
This bit is set by hardware to indicate SMBALERT_ signal. This
function is not supported. [Read-only]
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SMBusSlaveStatus - RW - 8 bits - [SMBUS:01h]
Field Name
Reserved
Bits
Default
Description
7:6
00b
SMBusControl - RW - 8 bits - [SMBUS:02h]
Field Name
InterruptEnable
Bits
Default
Description
0
0b
Enable the generation of interrupts on the completion of current
host transaction.
Kill
1
4:2
0b
000b
Stop the current host transaction in process
000 – Quick Read or Write
001 – Byte Read or Write
SMBusProtocol
010 – Byte Data Read or Write
011 – Word Data Read or Write
100 – Reserved
101 – Block Read or Write
110 – Reserved
111 – Reserved
Reserved
Start
5
6
0b
0b
Writing an 1 in this field initiates SMBus controller host interface
to execute the command programmed in the SMBusProtocol
field
Reserved
7
0b
SMBusHostCmd - RW – 8 bits - [SMBUS:03h]
Field Name
SMBusHostCmd
Bits
Default
Description
This field contains the data transmitted in the command field of
SMBus host transaction
7:0
00h
SMBusAddress - RW - 8 bits - [SMBUS:04h]
Field Name
Bits
Default
Description
SMBusRdWr
0
0b
1 – Execute a Read command
0 – Execute a Write command
SMBusAddr
7:1
00h
This field contains the 7-bit address of the target slave device.
SMBusData0 - RW - 8 bits - [SMBUS:05h]
Field Name
Bits
Default
Description
SMBusData0
7:0
00h
This register should be programmed with a value to be
transmitted in the data 0 field of an SMBus host interface
transaction. For Block Write commands, the count of the
memory should be stored in this field. The value of this
register is loaded into the block transfer count field. This valid
value for block command count is between 1 and 32. For
block reads, count received from SMBus device is stored here.
SMBusData1 - RW - 8 bits - [SMBUS:06h]
Field Name
Bits
Default
Description
SMBusData1
7:0
00h
This register should be programmed with a value to be
transmitted in the data 1 field of an SMBus host interface
transaction.
SMBusBlockData - RW - 8 bits - [SMBUS:07h]
Field Name
SMBusBlockData
Bits
Default
Description
This register is used to transfer data into or out of the block
data storage array.
7:0
00h
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SMBusSlaveControl - RW - 8 bits - [SMBUS:08h]
Field Name
SlaveEnable
Bits
Default
Description
0
0b
Enable the generation of an interrupt or resume event upon an
external SMBus master generating a transaction with an
address that matches the host controller slave port of 10h and
a command field which matches the SMBus slave control
register and a match of corresponding enabled events.
Enable the generation of an interrupt or resume event upon an
external SMBus master generating a transaction with an
address that matches the SMBus Shadow 1 register.
Enable the generation of an interrupt or resume event upon an
external SMBus master generating a transaction with an
address that matches the SMBus Shadow 2 register.
Enable the generation of an interrupt or resume event on the
assertion of AMBALERT_ signal. (This function is not
supported). [Read-only]
SMBusShadow1En
SMBusShadow2En
SMBusAlertEnable
Reserved
1
2
0b
0b
0b
0h
3
7:4
SMBusShadowCmd - RW - 8 bits - [SMBUS:09h]
Field Name
Bits
Default
Description
SMBusShadowCmd
7:0
00h
This field contains the command value which was received
during an external SMBus master access whose address field
matched the host slave address (10h) or one of the slave
shadow ports.
SMBusSlaveEvent - RW - 16 bits - [SMBUS:0A-0Bh]
Field Name
Bits
Default
Description
SMBusSlaveEvent
15:0
0000h
This field contains data bits used to compare against incoming
data to the SMBus Slave Data register. When a bit in this
register is 1 and a corresponding bit in SMBus Slave register
is set, then an interrupt or resume event is generated if the
command value matches the value in the SMBus slave control
register and the access was to SMBus host address 10h.
SlaveData - RW - 16 bits - [SMBUS:0C-0Dh]
Field Name
Bits
Default
Description
SlaveData
15:0
0000h
This field contains the data value which was transmitted during
an external SMBus master access whose address field
matched one of the slave shadow port addresses or the
SMBus host controller slave port address of 10h.
SMBusTiming - RW - 8 bits - [SMBUS:0Eh]
Field Name
Bits
Default
Description
SMBusTiming
7:0
A0h
This register controls the frequency on the SMBUS. The
formula to calculate the frequency is:
Frequency = 66Mhz/(SmBusTiming * 4)
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2.3.3
Legacy ISA and ACPI Controller
2.3.3.1 Legacy Block Registers
There are two sets of registers in the ACPI/SMBus module. The first set is in the PCI configuration space
and the registers control the behavior of the PCI interface. The second set is in the Memory/IO mapped
address space. These registers control the functions of the module.
2.3.3.1.1 IO-Mapped Control Registers
Register Name
Dma_Ch 0
Offset Address
00h
Dma_Ch 1
02h
Dma_Ch 2
04h
Dma_Ch 3
06h
Dma_Status
08h
Dma_WriteRequest
Dma_WriteMask
Dma_WriteMode
Dma_Clear
Dma_MasterClr
Dma_ClrMask
Dma_AllMask
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
20h
IntrCntrlReg1
IntrCntrlReg2
21h
TimerCh0
40h
TimerCh1
41h
TimerCh2
42h
Tmr1CntrlWord
Nmi_Status
43h
61h
RtcAddrPort
70h
RtcDataPort
71h
AlternatRtcAddrPort
AlternatRtcDataPort
Dma_PageCh2
Dma_PageCh3
Dma_PageCh1
Dma_Page_Reserved1
Dma_Page_Reserved2
Dma_Page_Reserved3
Dma_PageCh0
Dma_Page_Reserved4
Dma_PageCh6
Dma_PageCh7
Dma_PageCh5
Dma_Page_Reserved5
Dma_Page_Reserved6
Dma_Page_Reserved7
Dma_Refresh
72h
73h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
92h
FastInit
IntrCntrl2Reg1
IntrCntrl2Reg2
Dma2_Ch4Addr
Dma2_Ch4Cnt
Dma2_Ch5Addr
Dma2_Ch5Cnt
Dma2_Ch6Addr
A0h
A1h
C0h
C2h
C4h
C6h
C8h
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Register Name
Dma2_Ch6Cnt
Dma2_Ch7Addr
Dma2_Ch7Cnt
Dma_Status
Dma_WriteRequest
Dma_WriteMask
Dma_WriteMode
Dma_Clear
Offset Address
CAh
CCh
CEh
D0h
D2h
D4h
D6h
D8h
Dma_Clear
DAh
Dma_ClrMask
Dma_ClrMask
NCP_Error
DCh
DEh
F0h
DMA1_Extend
IntrEdgeControl
DMA2_Extend
Pci_Intr_Index
Pci_Intr_Data
Pci_Error
40Bh
4D0h
4D6h
C00h
C01h
C14h
C50h
C51h
C52h
C6Fh
CD0h
CD1h
CD4h
CD5h
CD6h
CD7h
CMIndex
CMData
GpmPort
Isa_Misc
PM2_Index
PM2_Data
BIOSRAM_Index
BIOSRAM_Data
PM_Index
PM_Data
.
The PCI I/O registers are 32-bit registers decoded from the full 32-bit PCI address and C/BE[3:0]#.
Therefore, the bytes within a 32-bit address are selected with the valid byte enables. Registers and bits
within a register marked as reserved are not implemented. Writes have no effect on reserved registers. All
PCI I/O registers can be accessed via 8, 16, or 32-bit cycles (i.e., each byte is individually selected by the
byte enables).
Dma_Ch 0- RW – 16 bits - [IO_Reg: 00h]
Field Name
Dma_Ch 0
Bits
Default
Description
15:0
0000h
DMA1 Ch0 Base and Current Address
Dma_Ch 0 register
Dma_Ch 1- RW – 16 bits - [IO_Reg: 02h]
Field Name
Dma_Ch 1
Bits
Default
Description
15:0
0000h
DMA1 Ch1 Base and Current Address
Dma_Ch 1 register
Dma_Ch 2- RW – 16 bits - [IO_Reg: 04h]
Field Name
Dma_Ch 2
Bits
Default
Description
15:0
0000h
DMA2 Ch2 Base and Current Address
Dma_Ch 2 register
Dma_Ch 3- RW – 16 bits - [IO_Reg: 06h]
Field Name
Dma_Ch 3
Bits
Default
Description
15:0
0000h
DMA1 Ch3 Base and Current Address
Dma_Ch 3 register
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Dma_Status- RW – 8 bits - [IO_Reg: 08h]
Field Name
Dma_Status
Bits
Default
Description
7:0
00h
Returns status when read; command for write
Dma_Status register
Dma_WriteRequest- RW – 8 bits - [IO_Reg: 09h]
Field Name
Bits
Default
Description
Dma_WriteRequest
7:0
00h
Request register.
Dma_WriteRequest register
Dma_WriteMask- RW – 8 bits - [IO_Reg: 0Ah]
Field Name
Dma_WriteMask
Bits
Default
Description
7:0
00h
Channel mask register.
Dma_WriteMask register
Dma_WriteMode- RW – 8 bits - [IO_Reg: 0Bh]
Field Name
Dma_WriteMode
Bits
Default
Description
7:0
00h
Mode register.
Dma_WriteMode register
Dma_Clear- RW – 8 bits - [IO_Reg: 0Ch]
Field Name
Dma_Clear
Bits
Default
Description
7:0
00h
Channel 0-3 DMA clear byte pointer
Dma_Clear register
Dma_MasterClr- RW – 8 bits - [IO_Reg: 0Dh]
Field Name
Dma_MasterClr
Bits
Default
Description
7:0
00h
Intermediate register.
Dma_MasterClr register
Dma_ClrMask- RW – 8 bits - [IO_Reg: 0Eh]
Field Name
Dma_ClrMask
Bits
Default
Description
7:0
00h
Channel 0-3 DMA Clear Mask
Dma_ClrMask register
Dma_AllMask- RW – 8 bits - [IO_Reg: 0Fh]
Field Name
Dma_AllMask
Bits
Default
Description
7:0
00h
Mask register.
Dma_AllMask register
IntrCntrl1Reg1- RW – 8 bits - [IO_Reg: 20h]
Field Name
Bits
Default
Description
IntrCntrl1Reg1
7:0
00h
IRQ0 – IRQ7:
Read IRR, ISR
Write ICW1, OCW2, OCW3
IntrCntrl1Reg1register
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IntrCntrl1Reg2- RW – 8 bits - [IO_Reg: 21h]
Field Name
IntrCntrl1Reg2
Bits
Default
Description
7:0
00h
IRQ0 – IRQ7:
Read IMR
Write ICW2, ICW3, ICW4, OCW1
IntrCntrl1Reg2 register
IMCR_Index- RW – 8 bits - [IO_Reg: 22h]
Field Name
Bits
Default
Description
IMCR_Index
7:0
00h
The IMCR is supported by two read/writeable IO ports 22/23h;
which are used as index and data port respectively. The
actual IMCR register is located at index 70h.
IMCR_Index register
IMCR_Data- RW – 8 bits - [IO_Reg: 23h]
Field Name
Bits
Default
Description
IMCR_Data
7:0
00h
The IMCR is supported by two read/writeable IO ports 22/23h;
which are used as index and data port respectively. The
actual IMCR register is located at index 70h and it is at bit 0.
The actual IMCR bit can only be accessed when bit port 22 is
set to 70h. Default value of IMCR is 0.
IMCR_Data register
TimerCh0- RW – 8 bits - [IO_Reg: 40h]
Field Name
Bits
Default
Description
TimerCh0
7:0
00h
8254 Timer 1 – Counter 0 Data Port
This timer is known as the System Clock timer and it is always
on. It is clocked internally by OSC/12 (1.19318MHz), and
asserts IRQ0 every time the timer rolls over. This timer is
used for time-of-day, diskette time-out, and other system
timing functions.
TimerCh0 register
TimerCh1- RW – 8 bits - [IO_Reg: 41h]
Field Name
Bits
Default
Description
TimerCh1
7:0
00h
8254 Timer 1 – Counter 1 Data Port
This timer is normally used for ISA refresh cycles and is also
clocked by OSC/12 (1.19818MHz). Since this refresh function
is no longer needed (we don't have an external ISA bus), it
can be used as a general purpose timing function.
TimerCh1 register
TimerCh2- RW – 8 bits - [IO_Reg: 42h]
Field Name
Bits
Default
Description
TimerCh2
7:0
00h
8254 Timer 1 - Counter 2 Data Port
This is the speaker tone generator and is enabled by IO port
61H. It is clocked by OSC/12 (1.19318MHz) and directly
drives the output SPKR that goes to a speaker.
TimerCh2 register
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Tmr1CntrlWord - RW – 8 bits - [IO_Reg: 43h]
Field Name
CntDownSelect
Bits
Default
Description
0
0b
0 – Binary countdown
1 – BCD countdown
ModeSelect
3:1
000b
000 – Asserts OUT signal at end of count
001 – Hardware re-triggerable one-shot
010 – Rate generator
011 – Square wave output
100 – Software triggered strobe
101 – Hardware triggered strobe
110 – 111 – not used
CmmandSelect
CounterSelect
5:4
7:6
00b
00b
00 – Counter latch command
01 – Read/write least significant byte
10 – Read/write most significant byte
11 – Read/write least, and then most significant byte
00 - Select counter 0
01 - Select counter 1
10 - Select counter 2
11 – Read back command
Tmr1CntrlWord register: This is the control word to access the 8254 timer 1. It is used to select which counter will
be accessed and how it will be accessed. This register specifies the counter, the operating mode, the order and
size of the count value, and whether it counts down in a 16 bit or BCD format.
If a counter is programmed to read or write two-byte counts, the following precaution applies: A program must not
transfer control between writing the first and second byte to another routine which also writes into that same
counter; otherwise, the counter will be loaded with an incorrect value. The count must always be completely loaded
with both bytes.
Nmi_Status - RW – 8 bits - [IO_Reg: 61h]
Field Name
SpkrEnable
Bits
Default
Description
0
0b
0 - Disable counter 2
1 - Enable counter 2
0 - Speaker timer off
1 - Speaker timer on
0 - Enable Parity Error to NMI generation (from SERR# or
PERR#)
SpkrTmrEnable
Parity_Nmi_En
1
2
0b
1b
1 - Disable Parity Error to NMI generation and clear bit 7
Iochk_Nmi_En
3
1b
0 - Enable IoChk to NMI generation
1 - Disable IoChk to NMI generation
The output of the counter 1 (8254). (Read-only)
The output of the counter 2. [Read-only]
NMI is triggered by serial IOCHK. [Read-only]
NMI is caused by parity error (either PERR# or SERR#).
[Read-only]
RefClk
SpkrClk
IoChk_Nmi
ParErr_Nmi
4
5
6
7
-
-
-
-
Nmi_Status register: Independent read and write registers will be accessed at this port. When writing to port 61H,
bits[3:0] allow software to enable/disable parity error NMI's and control the speaker timer. When reading port 61H,
status on parity errors, speaker count, speaker control and refresh cycles is returned.
Nmi_Enable - RW – 8 bits - [IO_Reg: 70h]
Field Name
RTC Address Port
NmiEnable
Bits
6:0
7
Default
00h
Description
This is used with either internal RTC or external RTC
0 - NMI enable
0b
1 - NMI disable [Write-only]
Nmi_Enable register
RtcDataPort - RW – 8 bits - [IO_Reg: 71h]
Field Name
Bits
Default
Description
RTC Data Port
7:0
00h
This is used with either internal RTC or external RTC
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RtcDataPort - RW – 8 bits - [IO_Reg: 71h]
Bits Default Description
Field Name
RtcDataPort
AlternatRtcAddrPort - RW – 8 bits - [IO_Reg: 72h]
Field Name
AlternatRTCAddrPort
Bits
7:0
Default
00h
Description
This is used with internal RTC. This port allows user to specify
the full 8 bit address (instead of bank0/bank1 indexing) to
access the 256 byte RTC RAM
AlternatRtcAddrPort
AlternatRtcDataPort - RW – 8 bits - [IO_Reg: 73h]
Field Name
AlternatRTC Data Port
AlternatRtcDataPort
Bits
7:0
Default
00h
Description
This is used with internal RTC in conjunction with port h72
Dma_PageCh2 - RW – 8 bits - [IO_Reg: 81h]
Field Name
Dma_PageCh2
Bits
Default
Description
7:0
00h
DMA2 ch 2 page register
Dma_PageCh2 register
Dma_PageCh3 - RW – 8 bits - [IO_Reg: 82h]
Field Name
Dma_PageCh3
Bits
Default
Description
7:0
00h
DMA2 ch 3 page register
Dma_PageCh3 register
Dma_PageCh1 - RW – 8 bits - [IO_Reg: 83h]
Field Name
Dma_PageCh1
Bits
Default
Description
7:0
00h
DMA2 ch 1 page register
Dma_PageCh1 register
Dma_Page_Reserved1- RW – 8 bits - [IO_Reg: 84h]
Field Name
Bits
Default
Description
Dma_Page_Reserved1
7:0
00h
Dma Page Reserved1 register
Dma_Page_Reserved1 register
Dma_Page_Reserved2- RW – 8 bits - [IO_Reg: 85h]
Field Name
Bits
Default
Description
Dma_Page_Reserved2
7:0
00h
Dma Page Reserved2 register
Dma_Page_Reserved2 register
Dma_Page_Reserved3- RW – 8 bits - [IO_Reg: 86h]
Field Name
Bits
Default
Description
Dma_Page_Reserved3
7:0
00h
Dma Page Reserved3 register
Dma_Page_Reserved3 register
Dma_PageCh0 - RW – 8 bits - [IO_Reg: 87h]
Field Name
Dma_PageCh0
Dma_PageCh0 register
Bits
Default
Description
7:0
00h
DMA2 ch 0 page register
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Dma_Page_Reserved4- RW – 8 bits - [IO_Reg: 88h]
Field Name
Bits
Default
Description
Dma_Page_Reserved4
7:0
00h
Dma Page Reserved4 register
Dma_Page_Reserved4 register
Dma_PageCh6 - RW – 8 bits - [IO_Reg: 89h]
Field Name
Dma_PageCh6
Bits
Default
Description
7:0
00h
DMA2 ch 6 page register
Dma_PageCh6 register
Dma_PageCh7 - RW – 8 bits - [IO_Reg: 8Ah]
Field Name
Dma_PageCh7
Bits
Default
Description
7:0
00h
DMA2 ch 7 page register
Dma_PageCh7 register
Dma_PageCh5 - RW – 8 bits - [IO_Reg: 8Bh]
Field Name
Dma_PageCh5
Bits
Default
Description
7:0
00h
DMA2 ch 5 page register
Dma_PageCh5 register
Dma_Page_Reserved5- RW – 8 bits - [IO_Reg: 8Ch]
Field Name
Bits
Default
Description
Dma_Page_Reserved5
7:0
00h
Dma Page Reserved5 register
Dma_Page_Reserved5 register
Dma_Page_Reserved6- RW – 8 bits - [IO_Reg: 8Dh]
Field Name
Bits
Default
Description
Dma_Page_Reserved6
7:0
00h
Dma Page Reserved6 register
Dma_Page_Reserved6 register
Dma_Page_Reserved7- RW – 8 bits - [IO_Reg: 8Eh]
Field Name
Bits
Default
Description
Dma_Page_Reserved7
7:0
00h
Dma Page Reserved7 register
Dma_Page_Reserved7 register
Dma_Refresh- RW – 8 bits - [IO_Reg: 8Fh]
Field Name
Dma_Refresh
Bits
Default
Description
7:0
00h
DMA2 ch4 page register.
Dma_Refresh register
FastInit- RW – 8 bits - [IO_Reg: 92h]
Field Name
Bits
Default
Description
FastInit
0
0b
FAST_INIT. This read/write bit provides a fast software
executed processor reset function. Writing
a 1 to this bit will cause the INIT assertion for approximately
4ms.
Before another INIT pulse can be generated via this register,
this bit must be written back to a 0.
A20EnB
1
0b
A20Enable Bar bit; if set to 1, A20M is disabled.
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IntrCntrl2Reg1- RW – 8 bits - [IO_Reg: A0h]
Field Name
IntrCntrl2Reg1
Bits
Default
Description
7:0
00h
IRQ8 – IRQ15:
Read IRR, ISR
Write ICW1, OCW2, OCW3
IntrCntrl2Reg1 register
IntrCntrl2Reg2- RW – 8 bits - [IO_Reg: A1h]
Field Name
Bits
Default
Description
IntrCntrl2Reg2
7:0
00h
IRQ8 – IRQ15:
Read IMR
Write ICW2, ICW3, ICW4, OCW1
IntrCntrl2Reg2 register
Dma2_Ch4Addr - RW – 8 bits - [IO_Reg: C0h]
Field Name
Dma2_Ch4Addr
Bits
Default
Description
7:0
00h
DMA2 Ch4 Base and Current Address
Dma2_Ch4Addr register
Dma2_Ch4Cnt – RW – 8 bits - [IO_Reg: C2h]
Field Name
Dma2_Ch4Cnt
Bits
Default
Description
7:0
00h
DMA2 Ch4 Base and Current Count
Dma2_Ch4Cnt register
Dma2_Ch5Addr - RW – 8 bits - [IO_Reg: C4h]
Field Name
Dma2_Ch5Addr
Bits
Default
Description
7:0
00h
DMA2 Ch5 Base and Current Address
Dma2_Ch5Addr register
Dma2_Ch5Cnt - RW – 8 bits - [IO_Reg: C6h]
Field Name
Dma2_Ch5Cnt
Bits
Default
Description
7:0
00h
DMA2 Ch4 Base and Current Count
Dma2_Ch5Cnt register
Dma2_Ch6Addr - RW – 8 bits - [IO_Reg: C8h]
Field Name
Dma2_Ch6Addr
Bits
Default
Description
7:0
00h
DMA2 Ch6 Base and Current Address
Dma2_Ch6Addr register
Dma2_Ch6Cnt - RW – 8 bits - [IO_Reg: CAh]
Field Name
Dma2_Ch6Cnt
Bits
Default
Description
7:0
00h
DMA2 Ch6 Base and Current Count
Dma2_Ch6Cnt register
Dma2_Ch7Addr - RW – 8 bits - [IO_Reg: CCh]
Field Name
Dma2_Ch7Addr
Bits
Default
Description
7:0
00h
DMA2 Ch5 Base and Current Address
Dma2_Ch7Addr register
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Dma_Ch7Cnt - RW – 8 bits - [IO_Reg: CEh]
Field Name
Dma2_Ch7Cnt
Bits
Default
Description
7:0
00h
Channel 7 DMA base and current count
Dma2_Ch7Cnt register
Dma_Status - RW – 8 bits - [IO_Reg: D0h]
Field Name
Dma_Status
Bits
Default
Description
7:0
00h
DMA2 status register
Dma_Status register
Dma_WriteRequest - RW – 8 bits - [IO_Reg: D2h]
Field Name
Bits
Default
Description
Dma_WriteRequest
7:0
00h
DMA2 request register
Dma_WriteRequest register
Dma_WriteMask - RW – 8 bits - [IO_Reg: D4h]
Field Name
Dma_WriteMask
Bits
Default
Description
7:0
00h
DMA2 channel mask register
Dma_WriteMask register
Dma_WriteMode - RW – 8 bits - [IO_Reg: D6h]
Field Name
Dma_WriteMode
Bits
Default
Description
7:0
00h
DMA2 mode register
Dma_WriteMode register
Dma_Clear - RW – 8 bits - [IO_Reg: D8h]
Field Name
Dma_Clear
Bits
Default
Description
7:0
00h
Channel 4-7 clear byte pointer
Dma_Clear register
Dma_Clear - RW – 8 bits - [IO_Reg: DAh]
Field Name
Dma_Clear
Bits
Default
Description
7:0
00h
Channel 4-7 DMA master clear
Dma_Clear register
Dma_ClrMask - RW – 8 bits - [IO_Reg: DCh]
Field Name
Dma_ClrMask
Bits
Default
Description
7:0
00h
Channel 4-7 DMA Clear Mask
Dma_ClrMask register
Dma_ClrMask - RW – 8 bits - [IO_Reg: DEh]
Field Name
Dma_AllMask
Bits
Default
Description
7:0
00h
DMA2 mask register
Dma_AllMask register
NCP_Error - RW – 8 bits - [IO_Reg: F0h]
Field Name
Reserved
WarmBoot
Bits
6:0
7
Default
00h
Description
0b
Warm or cold boot indicator
0 – Cold
1 – Warm, this bit is set when any value is written to this
register;
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NCP_Error - RW – 8 bits - [IO_Reg: F0h]
Field Name
Bits
Default
Description
NCP_Error register: In addition to the WarmBoot function, writing to this port will assert IGNNE# if FERR# is true. If
FERR# is false, then write to this port will not assert IGNNE#.
DMA1_Extend - RW – 8 bits - [IO_Reg: 40Bh]
Field Name
DMA1_Extend
Bits
Default
Description
7:0
00h
DMA1 extended write mode register
DMA1_Extend register
IntrEdgeControl- RW – 16 bits - [IO_Reg: 4D0h]
Field Name
IRQ0Control
IRQ1Control
Reserved
Bits
Default
Description
0
1
0b
0b
1 = Level, 0 = Edge
1 = Level, 0 = Edge
2
0b
IRQ3Control
IRQ4Control
IRQ5Control
IRQ6Control
IRQ7Control
IRQ8Control
IRQ9Control
IRQ10Control
IRQ11Control
IRQ12Control
Reserved
3
4
5
6
7
8
9
10
11
12
13
14
15
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
1 = Level, 0 = Edge
1 = Level, 0 = Edge
1 = Level, 0 = Edge
1 = Level, 0 = Edge
1 = Level, 0 = Edge
(Read Only) Always edge
1 = Level, 0 = Edge
1 = Level, 0 = Edge
1 = Level, 0 = Edge
1 = Level, 0 = Edge
IRQ14Control
IRQ15Control
1 = Level, 0 = Edge
1 = Level, 0 = Edge
0b
IntrEdgeControl register: This register programs each interrupt to be either edge or level sensitive.
DMA2_Extend - RW – 8 bits - [IO_Reg: 4D6h]
Field Name
DMA2_Extend
Bits
Default
Description
7:0
00h
DMA2 extended write mode register
DMA2_Extend register
Pci_Intr_Index - RW – 8 bits - [IO_Reg: C00h]
Field Name
Pci_Intr_Index
Bits
Default
Description
PCI interrupt index – selects which PCI interrupt to map
0h – INTA#
7:0
00h
1h – INTB#
2h – INTC#
3h – INTD#
4h – Interrupt generated by ACPI
5h – Interrupt generated by Sm Bus
6h – Reserved
7h – Ac97 audio
8h – Ac97 modem
9h – INTE#
Ah – INTF#
Bh – INTG#
Ch – INTH#
Pci_Intr_Index register
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Pci_Intr_Data - RW – 8 bits - [IO_Reg: C01h]
Field Name
Pci_Intr_Data
Bits
Default
Description
7:0
00h
PCI redirection register; map PCI interrupt addressed by
Pci_Intr_Index to a PIC IRQ
[7:4] – Not used
Straight encoding of [3:0] to : IRQ0 thru IRQ15
Note: Do not map to IRQ 0, 2, 8, 13 – they are reserved
Pci_Intr_Data register
Note: If IOXAPIC is enabled, software must make sure interrupts are not re-routed; i.e., they should all be set to 0.
When IOXAPIC is enabled, IRQ[15:0] are routed directly to INT[15:0]. INTH#, INTG#, INTF#, INTE#, INTD#, INTC#,
INTB#, and INTA# are routed to INTIN[23:16], SMBus interrupt is routed to INTIN[20], SCI# is routed to INTIN[9],
and the High Precision Event Timer (also called the Multimedia Timer) can be routed to either INTIN[22] or
INTIN[23].
Pci_Error - RW – 8 bits - [IO_Reg: C14h]
Field Name
Serr_Nmi_Status
Bits
Default
Description
Set to 1 when NMI generation is enabled and SERR# has
been asserted due to a PCI error. Cleared by writing a one to
port 61h, bit 2. [Read-only]
0
-
Perr_Nmi_Status
Serr_Nmi
1
2
-
Set to 1 when NMI generation is enabled and PERR# has
been asserted due to a PCI data parity error. Cleared by
writing a one to port 61h, bit 2. [Read-only]
Enable NMI generation from SERR#
0 – Enable
1 – Disable
Enable NMI generation from PERR#
0 – Enable
1b
1b
0h
Perr_Nmi
3
1 – Disable
Reserved
7:4
Pci_Error register
CMIndex - RW – 8 bits - [IO_Reg: C50h]
Field Name
Bits
Default
Description
CMIndex
7:0
00h
Index register to client management register block
00h – IdRegister
02h – TempStatus
03h – TempInterrupt
12h – SmBus control (control to Gpoc[3:0] pins
thru Bit Bang)
13h - Misccontrol
others – super IO – not used
CMIndex register
CMData - RW – 8 bits - [IO_Reg: C51h]
Field Name
CMData
Bits
7:0
Default
Description
00h
Data register to client management register block
CMData register
GpmPort - RW – 8 bits - [IO_Reg: C52h]
Field Name
Bits
Default
Description
If CMIndex.13h[7:6] == 00, then this is the read port for
GPM[7:0].
Gpm
7:0
--
If CMIndex.13h[7:6]= 01, then this is the output enable for
GPM[7:0], 0=enable, 1=tristate
If CMIndex.13h[7:6]=10, then this is the output state control
(providing enable is turned on)
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GpmPort - RW – 8 bits - [IO_Reg: C52h]
Field Name
Bits
Default
Description
GpmPort register
Isa_Misc - RW – 8 bits - [IO_Reg: C6Fh]
Field Name
Reserved
FlashRomEn
Bits
Default
Description
5:0
6
00h
0b
Flash program enable. This only applies if the chip is
strapped to have the ROM on the PCI bus . Set to 1 to enable
programming of the Flash ROM. During write cycles to the
system ROM space, ROMCS# is only asserted if this bit is
set 1.
Reserved
7
0b
Isa_Misc register: FlashRom Enable. This only applies if the chip is strapped to have the ROM on the secondary
PCI bus.
BIOSRAM_Index - RW – 8 bits - [IO_Reg: CD4h]
Field Name
BiosRamIndex
Bits
Default
Description
7:0
00h
BIOS RAM index register. This register selects one of the
256 bytes of BIOS RAM. Data in this RAM is preserved until
RSMRST# is asserted, or S5 power is lost.)
BiosRamIndex register
BIOSRAM_Data - RW – 8 bits - [IO_Reg: CD5h]
Field Name
Bits
Default
Description
BiosRamData
7:0
00h
Power management data register. This register provides the
read/write access to the indexed register.
BiosRamData register
PM_Index - RW – 8 bits - [IO_Reg: CD6h]
Field Name
Bits
Default
Description
PM_Index
7:0
00h
Power management index register. This register selects one
more information.)
PM_Index register
PM_Data - RW – 8 bits - [IO_Reg: CD7h]
Field Name
Bits
Default
Description
PM_Data
7:0
00h
Power management data register. This register provides the
read/write access to the indexed register. (See section
PM_Data register
2.3.3.1.2 Client Management Registers (Accessed through C50h and C51h)
Register Name
IdRegister
TempStatus
TempInterrupt
I2Ccontrol
Offset Address
00h
02h
03h
12h
13h
Index13
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IdRegister - R – 8 bits - [IO_Reg: 00h]
Field Name
IdRegister
Bits
7:0
Default
Description
00h
IdRegister register
TempStatus - R – 8 bits - [IO_Reg: 02h]
Field Name
Bits
Default
Description
TALERT
0
-
Logical status of TALERT/GPIO64 input.
Read will clear this bit.
Reserved
7:1
00h
TempStatus register
TempInterrupt - RW – 8 bits - [IO_Reg: 03h]
Field Name
Reserved
Bits
Default
Description
0
0b
TempSmiEnable
1
0b
1 - Generate SMI# upon TALERT
0 - Do not generate SMI# upon TALERT
Reserved
ScratchBit
2
3
0b
0b
This placebo bit has no function, but it may be used for
software status
Reserved
7:4
0h
TempInterrupt register
I2CControl - RW – 8 bits - [IO_Reg: 12h]
Field Name
Gpoc0Status
Gpoc1Status
Bits
Default
Description
0
1
2
-
-
1b
Gpoc0 status. [Read-only]
Gpoc1 status. [Read-only]
1 - Gpoc0 is tristate
Gpoc0_OE_
0 - Gpoc0 is asserted low
Gpoc1_OE_
Gpoc2Status
3
4
1b
-
1 - Gpoc1 is tristate
0 - Gpoc1 is asserted low
Gpoc2 status. [Read-only]
Gpoc3Status
Gpoc2_OE_
5
6
-
1b
Gpoc3 status. [Read-only]
1 - Gpoc2 is tristate
0 - Gpoc2 is output enabled
Gpoc3_OE_
7
1b
1 – Gpoc3 is tristate
0 – Gpoc3 is output enabled
I2CControl register: Writing to this register controls the output of the four Gpoc outputs (GPOC[3:0]_OE) and
reading returns the status of these pins.
Index13– 8 bits - [IO_Reg: 13h]
Default
Field Name
GPIO64En
Bits
0
Description
0b
GPIO64 output enable
1 = Enable
0 = Tristate
GPIO64OUT
Gpoc[3:2]OUT
ScratchBit
1
3:2
5:4
0b
00b
00b
GPIO64 output data
Gpoc[3:2] output data
Placebo bit, has no function but may be used for software
status
GpmPortSel
7:6
00b
00-Read port
01-Output enable
10-Output port
Index13 misc control register
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2.3.3.1.3 System Reset Register (IO CF9)
Note: Refer to PM IO reg x85 for a detailed description. This register has been designed to be dual-port
accessible.
2.3.3.2 Power Management (PM) Registers
The power management (PM) block is resident in the PCI/LPC/ISA bridge. The PM registers are accessed
via IO mapped registers xCD6h and xCD7h. The index address is first programmed into IO register xCD6h.
Read or write values are accessed through IO register xCD7h.
Register Name
MiscControl
Offset Address
00h
MiscStatus
01h
SmiWakeUpEventEnable1
SmiWakeUpEventEnable2
SmiWakeUpEventEnable3
SmiWakeUpEventStatus1
SmiWakeUpEventStatus2
SmiWakeUpEventStatus3
InactiveTmrEventEnable1
InactiveTmrEventEnable2
InactiveTmrEventEnable3
PmTmr1InitValue
PmTmr1CurValue
PwrLedExtEvent
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
PwrLedExtEvent
AcpiStatus
AcpiEn
S1AgpStpEn
11h
PmTmr2InitValue
PmTmr2CurValue
Programlo0RangeLo
Programlo0RangeHi
ProgramIo1RangeLo
ProgramIo1RangeHi
ProgramIo2RangeLo
ProgramIo2RangeHi
ProgramIo3RangeLo
ProgramIo3RangeHi
ProgramIoEnable
IOMonitorStatus
InactiveTmrEventEnable4
AcpiPm1EvtBlkLo
AcpiPm1EvtBlkHi
AcpiPm1CntBlkLo
AcpiPm1CntBlkHi
AcpiPmTmrBlkLo
AcpiPmTmrBlkHi
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
20h
21h
22h
23h
24h
25h
CpuControlLo
26h
CpuControlHi
27h
AcpiGpe0BlkLo
28h
AcpiGpe0BlkHi
29h
AcpiSmiCmdLo
AcpiSmiCmdHi
2Ah
2Bh
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Register Name
AcpiPmaCntBlkLo
AcpiPmaCntBlkHi
AcpiSsCntBlkLo
AcpiSsCntBlkHi
GEvtConfig0
Offset Address
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Eh
3Fh
40h
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
76h
77h
GEvtConfig1
GPMConfig0
GPMConfig1
GPMConfig2
GPMConfig3
GEvtLevelConfig
GPMLevelConfig0
GPMLevelConfig1
GEvtStatus
PMEStatus0
PMEStatus1
OthersConfig
VRT_T1
VRT_T2
AD_Pull_UpB
PM_Enable
TPRESET1
TPRESET2
TESTENABLE
PWRBTTN_CLR
SoftPciRst
Reserved
Reserved
Reserved
MiscOption
SmiSciSts0
SmiSciSts1
SmiSciSts2
SmiSciSts3
MwaitEnable
MwaitSmiSts
Options_0
Options_1
Shadow_SCI
SwitchVoltageTime
SwitchGHI_Time
UsbPMControl
MiscEnable66
MiscEnable67
MiscEnable68
WatchDogTimerControl
WatchDogTimerBase0
WatchDogTimerBase1
WatchDogTimerBase2
WatchDogTimerBase3
S_LdtStartTime
EnhanceOption
C4Control
PopUpEndTime
PwrFailShadow
Tpreset1b
SOS3ToS5Enable0
SOS3ToS5Enable1
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Register Name
SOS3ToS5Enable2
SOS3ToS5Enable3
NoStatusControl0
NoStatusControl1
MiscEnable7C
DprSlpVrMinTime
SMAF0
Offset Address
78h
79h
7Ah
7Bh
7Ch
7Dh
80h
SMAF1
81h
SMAF2
82h
SMAF3
83h
WakePinCntl
84h
CF9Rst
85h
ThermThrotCntl
LdtStpCmd
86h
87h
LdtStartTime
88h
AgpStartTime
LdtAgpTimeCntl
StutterTime
89h
8Ah
8Bh
StpClkDlyTime
AbPmeCntl
8Ch
8Dh
8Eh
FakeAsr
FakeAsrEn
8Fh
GEVENTOUT
GEVENTEN
90h
91h
GEVENTIN
92h
GPM98OUT
94h
GPM98EN
95h
GPM98IN
96h
K8C1ePort
99:98h
9Ah
9Bh
9E:9Ch
9Fh
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
B1:B0h
B2h
EnhanceControl
K8C1eReadPort
MsiSignature
AutoArbDisWaitTime
Programlo4RangeLo
Programlo4RangeHi
Programlo5RangeLo
Programlo5RangeHi
Programlo6RangeLo
Programlo6RangeHi
Programlo7RangeLo
Programlo7RangeHi
PIO7654Enable
PIO7654Status
PllDebug
AltDebugBusCntrl
C2Count
B3h
C3Count
B4h
MiscControl - RW – 8 bits - [PM_Reg: 00h]
Field Name
Reserved
Bits
Default
Description
0
0b
Timer1ExpEn
1
0b
Set to 1 to enable SMI# when PM_TIMER1 expires. When
PM_TIMER1 (inactivity) expires, the SB will update bit 1 of
MiscStatus and issue SMI#. This bit allows the software to
disable/enable all inactivity timer reload enables at indexes
08,09, and 0A.
Timer2ExpEn
2
0b
Set to 1 to enable SMI# when PM_TIMER2 expires.
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MiscControl - RW – 8 bits - [PM_Reg: 00h]
Field Name
Reserved
SmiReq
Bits
Default
Description
3
4
0b
0b
Software initiated SMI#. When set, SB will update bit [4] of
the MiscStatus and issue SMI#.
Reserved
7:5
000b
MiscControl register
MiscStatus - RW – 8 bits - [PM_Reg: 01h]
Field Name
Bits
Default
Description
SmiEvent
0
0b
SB sets this bit to indicate an SMI# was issued due to events
specified by index 02, 03, 04, 1C, or A8h
Timer1Exp
Timer2Exp
Reserved
SmiReq
1
2
3
4
0b
0b
0b
0b
SB sets this bit to indicate that PM_TIMER1 has expired.
SB sets this bit to indicate that PM_TIMER2 has expired.
SB sets this bit to indicate the software initiated SMI# was
issued.
Reserved
StatusRst
6:5
7
00b
0b
Writing a 1 to this location will reset PM status registers 05h,
06h, and 07h, 1Dh, and A9h. This mechanism provides a
quick way to reset all status.
MiscStatus register
SmiWakeUpEventEnable1 - RW – 8 bits - [PM_Reg: 02h]
Field Name
Bits
Default
Description
SmiWakeUpEventEnable1
7:0
00h
Enable SMI# on IRQ[15:8] activity.
SmiWakeUpEventEnable1 register.
SmiWakeUpEventEnable2 - RW – 8 bits - [PM_Reg: 03h]
Field Name
Bits
Default
Description
SmiWakeUpEventEnable2
7:0
00h
Enables SMI# on {IRQ[7:3], NMI, IRQ[1:0]} activity.
SmiWakeUpEventEnable2 register.
SmiWakeUpEventEnable3 - RW – 8 bits - [PM_Reg: 04h]
Field Name
ExtEvent0
ExtEvent1
GAME_SMI_EN
FDD_SMI_EN
HDD_SMI_EN
COM_SMI_EN
LPT_SMI_EN
SLP_SMI_EN
Bits
Default
Description
Enables SMI# on external event input 0
Enables SMI# on external event input 1
Enables SMI# on game port activity (201h)
Enables SMI# on floppy drive activity
Enables SMI# on IDE device activity (201h)
Enables SMI# on serial ports activity (201h)
Enables SMI# on parallel port activity (201h)
Enables SMI# on sleep command
0
0b
1
0b
2
0b
3
0b
4
0b
5
0b
6
0b
7
0b
SmiWakeUpEventEnable3 register.
SmiWakeUpEventStatus1 - RW – 8 bits - [PM_Reg: 05h]
Field Name
Bits
Default
Description
SmiWakeUpEventStatus1
7:0
00h
Set to 1 to identify IRQ[15:8] activity as source of SMI#.
SmiWakeUpEventStatus1 register.
SmiWakeUpEventStatus2 - RW – 8 bits - [PM_Reg: 06h]
Field Name
Bits
Default
Description
SmiWakeUpEventStatus2
7:0
00h
Set to 1 to identify IRQ[7:0] activity as source of SMI#.
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SmiWakeUpEventStatus2 - RW – 8 bits - [PM_Reg: 06h]
Field Name
Bits
Default
Description
SmiWakeUpEventStatus2 register.
SmiWakeUpEventStatus3 - RW – 8 bits - [PM_Reg: 07h]
Field Name
ExtEvt0_SMI_Status
Bits
Default
Description
Set to 1 to indicate ExtEvent0 as the source of SMI#. Write 1
to clear this bit.
0
0b
ExtEvt1_SMI_Status
GAME_SMI_Status
FDD_SMI_Status
HDD_SMI_Status
COM_SMI_Status
LPT_SMI_Status
SLP_SMI_Status
1
2
3
4
5
6
7
0b
0b
0b
0b
0b
0b
0b
Set to 1 to indicate ExtEvent1 as the source of SMI#. Write 1
to clear this bit.
Set to 1 to indicate game port activity as the source of SMI#.
Write 1 to clear this bit.
Set to 1 to indicate floppy activity as the source of SMI#.
Write 1 to clear this bit.
Set to 1 to indicate IDE activity as the source of SMI#. Write
1 to clear this bit.
Set to 1 to indicate serial port activity as the source of SMI#.
Write 1 to clear this bit.
Set to 1 to indicate parallel port activity as the source of
SMI#. Write 1 to clear this bit.
Set to 1 to indicate sleep command as the source of SMI#.
Write 1 to clear this bit.
SmiWakeUpEventStatus3 register: Set to one to identify PioRng.
InactiveTmrEventEnable1 - RW – 8 bits - PM_Reg: 08h]
Field Name
Bits
Default
Description
InactiveTmrEventEnable1
7:0
00h
Enables Timer 1 reload on IRQ[15:8] activity.
InactiveTmrEventEnable1 register.
InactiveTmrEventEnable2 - RW – 8 bits - [PM_Reg: 09h]
Field Name
Bits
Default
Description
InactiveTmrEventEnable2
7:0
00h
Enables Timer 1 reload on {IRQ[7:3], NMI, IRQ[1:0]} activity.
InactiveTmrEventEnable2 register.
InactiveTmrEventEnable3 - RW – 8 bits - [PM_Reg: 0Ah]
Field Name
ExtEvt0_Timer1Enable
ExtEvt1_Timer1Enable
GamePort_Timer1Enable
Floppy_Timer1Enable
IDE_Timer1Enable
COM_Timer1Enable
Parallel_Timer1Enable
Reserved
Bits
0
1
2
3
4
5
6
Default
Description
0b
0b
0b
0b
0b
0b
0b
0b
Enables Timer1 reload on ExtEvent0 inactivity
Enables Timer1 reload on ExtEvent1 inactivity
Enables Timer1 reload on Gameport inactivity
Enables Timer1 reload on Floppy port inactivity
Enables Timer1 reload on IDE port inactivity
Enables Timer1 reload on COM port inactivity
Enables Timer1 reload on Parallel port inactivity
7
InactiveTmrEventEnable3 register.
PmTmr1InitValue - RW – 8 bits - [PM_Reg: 0Bh]
Field Name
PmTmr1InitValue
Bits
Default
Description
6 bit-timer; Initial/reload value for 6 bit decrementing counter.
Count range from 1 minute to 64 minutes with 4 second
accuracy.
5:0
000000b
Reserved
7:6
00b
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PmTmr1CurValue - R – 8 bits - [PM_Reg: 0Ch]
Field Name
PmTmr1CurValue
Reserved
Bits
Default
Description
5:0
-
Current value of decrementing counter
7:6
00b
PwrLedExtEvent - RW – 8 bits - [PM_Reg: 0Dh]
Field Name
ExtEvent0State
ExtEvent1State
ExtEvent0RF
Bits
Default
Description
0
1
2
-
-
0b
Logical value of EXTEVENT0. [Read-only]
Logical value of EXTEVENT1. [Read-only]
Set to one to configure EXTEVENT0 as rising edge sensitive.
0 as falling edge sensitive
ExtEvent1RF
3
0b
Set to one to configure EXTEVENT1 as rising edge sensitive.
0 as falling edge sensitive
Reserved
7:4
0100b
PwrLedExtEvent register.
AcpiControl - RW – 8 bits - [PM_Reg: 0Eh]
Field Name
Bits
Default
Description
AcpiSmiEn
0
0b
Set to 1 to enable SMI# generation when ACPI driver writes
one to GBL_RLS (bit [2] of AcpiPm1CntBlk:00h). When an
SMI# is issued, the SB updates bit [0] of the AcpiStatus
register.
BIOS_RLS
SmiCmdEn
1
2
0b
0b
Writing 1 to this bit will cause GblStatus to be set. This bit is
always read back as 0.
Set to 1 to enable SMI# generation when ACPI driver writes
to the SmiCmd port. When set to 1, SB will update bit 2 of
MiscStatus and issue an SMI# on write to SmiCmd port.
Set to 1 to enable SB to decode the ACPI I/O address space.
When set, SB uses the contents of the PM registers at index
20-2B to decode ACPI I/O address.
AcpiDecodeEnable
3
0b
VRT_SMI_En
Reserved
RtcClkPUB
4
5
6
0b
0b
0b
Set to 1 to enable SB to generate SMI# upon (RTC) VRT low.
This bit controls the integrated pull-up for RTCCLK
0: Enable
1: Disable
7
0b
This bit controls the CPU receiver Vref
0: Vref = Vcpu / 2 (recommended setting for P4 CPU)
1: Vref = Vbandgap / 2 = 0.6v (recommended setting for K8
CPU)
BG1RESDIV0_SEL
AcpiControl register.
AcpiStatus- R – 8 bits - PM_Reg: 0Fh]
Field Name
Bits
Default
Description
AcpiSmiStatus
0
-
Set to 1 by SB to indicate SMI# was due to write to Acpi
power management register.
SMI# due to SERR#
Set to one by SB to indicate SMI# was due to write to
AcpiSmiCmd port.
SerrSmiStatus
SmiCmdStatus
1
2
-
-
SmSmiStatus
UsbSmiStatus
SerSmiStatus
RtcAvailable
3
4
5
6
-
-
-
-
SmBus SMI# status
USB SMI# status
Serial SMI# status
1: Rtc clock running
0: Bad Rtc clock. RTC battery may not be present
NbThermStatus
7
-
NB thermal event status
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AcpiEn - RW – 8 bits - [PM_Reg: 10h]
Field Name
EOSEnale
Bits
0
Default
Description
0b
Set 1 by software and clear by hardware. This bit needs to
be set in order to generate SMI#/SCI
RTC_En_En
1
0b
RTC_EN enable bit. When this bit is set, RTC_EN
(AcpiPmEvtBlk, index x02, bit 10) is visible; otherwise, it is
always 0
Reserved
TMR_En_En
2
3
0b
0b
TMR_EN enable bit. When this bit is set, TM_EN
(AcpiPmEvtBlk, index x02, bit 0) is visible; otherwise, it is
always 0
LEVENT_EN_EN
GBL_EN_EN
4
5
6
7
0b
0b
0b
0b
LEVENT_EN enable bit. When this bit is set, LEVENT_EN
(AcpiGpe0Blk, index x04, bit 8) is visible; otherwise, it is
always 0
GBL_EN enable bit. When this bit set, GBL_EN
(AcpiPmEvtBlk, index x02, bit 5) is visible; otherwise, it is
always 0
PciExpWakeDis enable bit. When this bit is set,
PciExpWakeDis (AcpiPmEvtBlk, index x02, bit 14) is visible;
otherwise, it is always 1
This bit is applicable to ASIC Revision A12 and above.
0: ACPI_EVENT[30] register is routed to use GPIO2 as input
1: ACPI_EVENT[30] register is routed to use GPIO66 as
input
PciExpWakeDisEn
GpioToGEventSel
S1AgpStpEn - RW – 8 bits - [PM_Reg: 11h]
Field Name
Bits
Default
Description
S1AgpStpEn
0
0b
AgpStp enable in S1 state
1: Enable
0: Disable
Reserved
7:1
00h
S1AgpStpEn register.
PmTmr2InitValue - RW – 8 bits - [PM_Reg: 12h]
Field Name
PmTmr2InitValue
Bits
Default
Description
7:0
00h
PmTmr2 load value
PmTmr2InitValue register.
PmTmr2CurValue - R – 8 bits - [PM_Reg: 13h]
Field Name
Bits
Default
Description
PmTmr2CurValue
7:0
--
PmTmr2 current value
PmTmr2CurValue register.
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AMD SB600 Register Reference Manual
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Programlo0RangeLo - RW – 8 bits - [PM_Reg: 14h]
Field Name
Bits
Default
Description
ProgramIo0Mask
3:0
0h
These four bits are used to mask the least 4 bits of the 16 bit
I/O. If bit [3] is set, then bit [3] of the I/O address is not
compared. If it is not set, then bit [3] of the monitored
address is 0. The same applies for the other three bits [2:0].
For example, if x15=80h, x14[7:4]=Ah, and x14[3:0]=3h, then
the monitored range is 80A4h : 80A0h (bit 0 and 1 are
masked)
ProgramIo0RangeLo
7:4
0h
I/O range base address; these bits define the least significant
byte of the 16 bit I/O range base address that is programmed
to trigger SMI# when the address is accessed. Bit 7
corresponds to Addr[7] and bit 4 to Addr[4].
ProgramIo0RangeLo register.
ProgramIo0RangeHi - RW – 8 bits - [PM_Reg: 15h]
Field Name
Bits
Default
Description
ProgramIo0RangeHi
7:0
00h
I/O range base address; these bits define the most significant
byte of the 16 bit I/O range base address. Bit 7 corresponds
to Addr[15] and bit 0 to Addr[8].
ProgramIo0RangeHi register.
ProgramIo1RangeLo - RW – 8 bits - [PM_Reg: 16h]
Field Name
Bits
Default
Description
ProgramIo1Mask
3:0
0h
These four bits are used to mask the least 4 bits of the 16 bit
I/O. If bit [3] is set, then bit [3] of the I/O address is not
compared. If it is not set, then bit [3] of the monitored
address is 0. The same applies to the other three bits [2:0].
For example, if x15=80h, x14[7:4]=Ah, and x14[3:0]=3h, then
the monitored range is 80A4h : 80A0h (bit 0 and 1 are
masked)
ProgramI01RangeLo
7:4
0h
I/O range base address; these bits define the least significant
byte of the 16 bit I/O range base address that is programmed
to trigger SMI# when the address is accessed. Bit 7
corresponds to Addr[7] and bit 4 to Addr[4].
ProgramIo1RangeLo register.
ProgramIo1RangeHi - RW – 8 bits - [PM_Reg: 17h]
Field Name
Bits
Default
Description
ProgramIo1RangeHi
7:0
00h
I/O range base address; these bits define the most significant
byte of the 16 bit I/O range base address. Bit 7 corresponds
to Addr[15] and bit 0 to Addr[8].
ProgramIO1RangeHi register.
ProgramIo2RangeLo - RW – 8 bits - [PM_Reg: 18h]
Field Name
Bits
Default
Description
ProgramIo2Mask
3:0
0h
These four bits are used to mask the least 4 bits of the 16 bit
I/O. If bit [3] is set, then bit [3] of the I/O address is not
compared. If it is not set, then bit [3] of the monitored
address is 0. The same applies for the other three bits.
For example, if x15=80h, x14[7:4]=Ah, and x14[3:0]=3h, then
the monitored range is 80A4h : 80A0h (bit 0 and 1 are
masked)
ProgramIo2RangeLo
7:4
0h
I/O range base address; these bits define the least significant
byte of the 16 bit I/O range base address that is programmed
to trigger SMI# when the address is accessed. Bit 7
corresponds to Addr[7] and bit 4 to Addr[4].
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ProgramIo2RangeLo - RW – 8 bits - [PM_Reg: 18h]
Bits Default Description
Field Name
ProgramIo2RangeLo register.
ProgramIo2RangeHi - RW – 8 bits - [PM_Reg: 19h]
Field Name
Bits
Default
Description
ProgramIo2RangeHi
7:0
00h
I/O range base address; these bits define the most significant
byte of the 16 bit I/O range base address. Bit 7 corresponds
to Addr[15] and bit 0 to Addr[8].
ProgramIo2RangeHi register.
ProgramIo3RangeLo - RW – 8 bits - [PM_Reg: 1Ah]
Field Name
Bits
Default
Description
ProgramIo3Mask
3:0
0h
These four bits are used to mask the least 4 bits of the 16 bit
I/O. If bit [3] is set, then bit [3] of the I/O address is not
compared. If it is not set, then bit [3] of the monitored
address is 0. The same applies to the other three bits [2:0].
For example, if x15=80h, x14[7:4]=Ah, and x14[3:0]=3h, then
the monitored range is 80A4h : 80A0h (bit 0 and 1 are
masked)
ProgramIo3RangeLo
7:4
0h
I/O range base address; these bits define the least significant
byte of the 16 bit I/O range base address that is programmed
to trigger SMI# when the address is accessed. Bit 7
corresponds to Addr[7] and bit 4 to Addr[4].
ProgramIo3RangeLo register.
ProgramIo3RangeHi - RW – 8 bits - [PM_Reg: 1Bh]
Field Name
Bits
Default
Description
ProgramIo3RangeHi
7:0
00h
I/O range base address; these bits define the most significant
byte of the 16 bit I/O range base address. Bit 7 corresponds
to Addr[15] and bit 0 to Addr[8].
ProgramIo3RangeHi register.
ProgramIoEnable - RW – 8 bits - [PM_Reg: 1Ch]
Field Name
AD_LIB_MonitorEn
MIDI_MonitorEn
Bits
Default
0b
Description
0
1
2
Enables AD_LIB monitoring to trigger SMI#, 1=On, 0=Off
Enables MIDI monitoring to trigger SMI#; 1= On, 0= Off
Enables Audio/MSS monitoring to trigger SMI#; 1= On, 0 =
Off
0b
0b
AudioMSSMonitorEn
MouseKbMonitorEn
ProgramIo3Enable
ProgramIo2Enable
ProgramIo1Enable
ProgramIo0Enable
IOMonitorEn register
3
4
5
6
7
0b
0b
0b
0b
0b
Enables Mouse/Keyboard monitoring to trigger SMI#; 1= On,
0 = Off
Enables IO monitoring for ProgramIO3 (defined by index 1A,
1B); 1= On, 0 = Off
Enables IO monitoring for ProgramIO2 (defined by index 18,
19); 1= On, 0 = Off
Enables IO monitoring for ProgramIO1 (defined by index 16,
17); 1= On, 0 = Off
Enables IO monitoring for ProgramIo0 (defined by index 14,
15); 1= On, 0 = Off
IOMonitorStatus - RW – 8 bits - [PM_Reg: 1Dh]
Field Name
Bits
Default
Description
AD_LIB_MonitorStatus
MIDI_MonitorStatus
AudioMSSMonitorStatus
0
1
2
-
-
-
AD_LIB status bit; write 1’b1 to clear the status
MIDI status bit; write 1’b1 to clear the status bit
Audio/MSS status bit; write 1’b1 to clear the status bit
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IOMonitorStatus - RW – 8 bits - [PM_Reg: 1Dh]
Field Name
MouseKbMonitorStatus
ProgramIo3Status
Bits
3
4
Default
Description
-
-
Mouse/keyboard status bit; write 1’b1 to clear the status bit
Programmable IO 3 status bit; write 1’b1 to clear the status
bit
ProgramIo2Status
ProgramIo1Status
ProgramIo0Status
IOMonitorStatus register
5
6
7
-
-
-
Programmable IO 2 status bit; write 1’b1 to clear the status
bit
Programmable IO 1 status bit; write 1’b1 to clear the status
bit
Programmable IO 0 status bit; write 1’b1 to clear the status
bit
InactiveTmrEventEnable4 - RW – 8 bits - [PM_Reg: 1Eh]
Field Name
AD_LIB_Timer1Enable
MIDI_Timer1Enable
Audio_Timer1Enable
Keyboard_Time1Enable
PIO3_Timer1Enable
PIO2_Timer1Enable
PIO1_Timer1Enable
PIO0_Timer1Enable
Bits
Default
Description
0
1
0b
0b
Enables Timer1 reload on AD_LIB inactivity
Enables Timer1 reload on MIDI inactivity
2
3
4
5
6
7
0b
0b
0b
0b
0b
0b
Enables Timer1 reload on Audio inactivity
Enables Timer1 reload on Keyboard/Mouse port inactivity
Enables Timer1 reload on PIO3 port inactivity
Enables Timer1 reload on PIO2 port inactivity
Enables Timer1 reload on PIO1 port inactivity
Enables Timer1 reload on PIO0 port inactivity
InactiveTmrEventEnable4 register.
AcpiPm1EvtBlkLo - RW – 8 bits - [PM_Reg: 20h]
Field Name
Reserved
Bits
Default
Description
1:0
00b
AcpiPm1EvtBlkLo
7:2
00h
These bits define the least significant byte of the 16 bit I/O
range base address of the ACPI power management Event
Block. Bit 2 corresponds to Addr[2] and bit 7 corresponds to
Addr[7].
AcpiPm1EvtBlkLo register.
AcpiPm1EvtBlkHi - RW – 8 bits - [PM_Reg: 21h]
Field Name
Bits
Default
Description
AcpiPm1EvtBlkHi
7:0
00h
These bits define the most significant byte of the 16 bit I/O
range base address. Bit 0 corresponds to Addr[8] and bit 7
corresponds to Addr[15].
AcpiPm1EvtBlkHi register.
AcpiPm1CntBlkLo - RW – 8 bits - [PM_Reg: 22h]
Field Name
Reserved
Bits
Default
Description
0
0b
AcpiPm1CntBlkLo
7:1
00h
These bits define the least significant byte of the 16 bit I/O
base address of the ACPI power management Control block.
Bit 1 corresponds to Addr[1] and bit 7 corresponds to Addr[7].
AcpiPm1CntBlkLo register.
AcpiPm1CntBlkHi - RW – 8 bits - [PM_Reg: 23h]
Field Name
Bits
Default
Description
AcpiPm1CntBlkHi
7:0
00h
These bits define the most significant byte of the 16 bit I/O
base address. Bit 0 corresponds to Addr[8] and bit 7
corresponds to Addr[15].
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AcpiPm1CntBlkHi - RW – 8 bits - [PM_Reg: 23h]
Field Name
Bits
Default
Description
AcpiPm1CntBlkHi register.
AcpiPmTmrBlkLo - RW – 8 bits - [PM_Reg: 24h]
Field Name
Reserved
Bits
Default
Description
0
0b
AcpiPmTmrBlkLo
7:1
00h
These bits define the least significant byte of the 16 bit I/O
base address of the ACPI power management Timer block.
Bit 1 corresponds to Addr[1] and bit 7 corresponds to Addr[7].
AcpiPmTmrBlkLo register.
AcpiPmTmrBlkHi - RW – 8 bits - [PM_Reg: 25h]
Field Name
Bits
Default
Description
AcpiPmTmrBlkHi
7:0
00h
These bits define the most significant byte of the 16 bit I/O
base address. Bit 0 corresponds to Addr[8] and bit 7
corresponds to Addr[15].
AcpiPmTmrBlkHi register.
CpuControlLo - RW – 8 bits - [PM_Reg: 26h]
Field Name
Reserved
CpuControlLo
Bits
Default
000b
00h
Description
2:0
7:3
These bits define the least significant byte of the 16 bit I/O
base address of the ACPI power management CPU Control
block. Bit 3 corresponds to Addr[3] and bit 7 corresponds to
Addr[7]. Addr[2:0] are ignored because this register block is 6
byte long.
CpuControlLo register.
CpuControlHi - RW – 8 bits - [PM_Reg: 27h]
Field Name
Bits
Default
Description
CpuControlHi
7:0
00h
These bits define the most significant byte of the 16 bit I/O
base address. Bit 0 corresponds to Addr[8] and bit 7
corresponds to Addr[15].
CpuControlHi register.
AcpiGpe0BlkLo - RW – 8 bits - [PM_Reg: 28h]
Field Name
Reserved
Bits
Default
Description
1:0
00b
AcpiGpe0BlkLo
7:2
00h
These bits define the least significant byte of the 16 bit I/O
base address of the ACPI power management General
Purpose Event block. Bit 2 corresponds to Addr[2] and bit 7
corresponds to Addr[7]. Addr[1:0] are ignored because this
register block is 4 byte long.
AcpiGpe0BlkLo register.
AcpiGpe0BlkHi - RW – 8 bits - [PM_Reg: 29h]
Field Name
Bits
Default
Description
AcpiGpe0BlkHi
7:0
00h
These bits define the most significant byte of the 16 bit I/O
base address. Bit 0 corresponds to Addr[8] and bit 7
corresponds to Addr[15].
AcpiGpe0BlkHi register.
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AcpiSmiCmdLo - RW – 8 bits - [PM_Reg: 2Ah]
Field Name
AcpiSmiCmdLo
Bits
Default
Description
7:0
00h
These bits define the least significant byte of the 16 bit I/O
base address of the ACPI SMI Command block. Bit 0
corresponds to Addr[0] and bit 7 corresponds to Addr[7]. The
address is required to be DWORD-aligned (Bit[1:0]=00b)
AcpiSmiCmdLo register.
AcpiSmiCmdHi - RW – 8 bits - [PM_Reg: 2Bh]
Field Name
Bits
Default
Description
AcpiSmiCmdHi
7:0
00h
These bits define the most significant byte of the 16 bit I/O
base address. Bit 0 corresponds to Addr[8] and bit 7
corresponds to Addr[15].
AcpiSmiCmdHi register.
AcpiPmaCntBlkLo - RW – 8 bits - [PM_Reg: 2Ch]
Field Name
Bits
Default
Description
AcpiPmaCntBlkLo
7:0
00h
These bits define the least significant byte of the 16 bit I/O
base address of the ACPI power management additional
control block. Bit 0 corresponds to Addr[0] and bit 7
corresponds to Addr[7].
AcpiPmaCntBlkLo register.
AcpiPmaCntBlkHi - RW – 8 bits - [PM_Reg: 2Dh]
Field Name
Bits
Default
Description
AcpiPmaCntBlkHi
7:0
00h
These bits define the most significant byte of the 16 bit I/O
base address. Bit 0 corresponds to Addr[8] and bit 7
corresponds to Addr[15].
AcpiPmaCntBlkHi register.
GEvtConfig0 – RW – 8 bits - [PM_Reg: 30h]
Field Name
Bits
Default
Description
GEvtConfig0
7:0
00h
GEVENT Configuration. These 8 bits are used for
configuring general purpose events 0-3. Two bits for each
event pin. Bit[1:0] for GEVENT[0], bit[3:2] for GEVENT[1]
and so on
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 GEVENT to generate SMI#
10 GEVENT to generate SMI# followed by SCI
11 GEVENT to generate IRQ13
GEvtConfig0 register.
GEvtConfig1 – RW – 8 bits - [PM_Reg: 31h]
Field Name
Bits
Default
Description
GEvtConfig1
7:0
00h
GEVENT Configuration. These 8 bits are used for
configuring General Purpose Events 4-7. Two bits for each
event pin. Bit[1:0] for GEVENT[4], bit[3:2] for GEVENT[5]
and so on
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 GEVENT to generate SMI#
10 GEVENT to generate SMI# followed by SCI
11 GEVENT to generate IRQ13
GEvtConfig1 register.
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AMD SB600 Register Reference Manual
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GPMConfig0 – RW – 8 bits - [PM_Reg: 32h]
Field Name
Bits
Default
Description
ExtEvent0Config
1:0
3:2
5:4
7:6
00b
These two bits configure ExtEvent0
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 ExtEvent0 to generate SMI#
10 ExtEvent0 to generate SMI# followed by SCI
11 ExtEvent0 to generate IRQ13
These two bits configure ExtEvent1
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
ExtEvent1Config
PCIePmeConfig
Gpm0Config
00b
00b
00b
01 ExtEvent1 to generate SMI#
10 ExtEvent1 to generate SMI# followed by SCI
11 ExtEvent1 to generate IRQ13
These two bits configure PCIePme
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 PCIePme to generate SMI#
10 PCIePme to generate SMI# followed by SCI
11 PCIePme to generate IRQ13
These two bits configure GPM0
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 GPM0 to generate SMI#
10 GPM0 to generate SMI# followed by SCI
11 GPM0 to generate IRQ13
GPMConfig1- RW – 8 bits - [PM_Reg: 33h]
Field Name
Bits
Default
Description
Gpm1Config
1:0
3:2
5:4
7:6
00b
These two bits configure GPM1
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 GPm1 to generate SMI#
10 Gpm1 to generate SMI# followed by SCI
11 GPm1 to generate IRQ13
These two bits configure GPM2
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 Gpm2 to generate SMI#
10 Gpm2 to generate SMI# followed by SCI
11 GPm2 to generate IRQ13
These two bits configure GPM3
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 GPM3 to generate SMI#
10 GPM3 to generate SMI# followed by SCI
11 GPM3 to generate IRQ13
These two bits configure GPM8
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
Gpm2Config
Gpm3Config
Gpm8Config
00b
00b
00b
01 GPM8 to generate SMI#
10 GPM8 to generate SMI# followed by SCI
11 GPM8 to generate IRQ13
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GPMConfig2- RW – 8 bits - [PM_Reg: 34h]
Field Name
Gpio0Config
Bits
Default
Description
1:0
3:2
5:4
7:6
00b
These two bits configure Gpio0 or WAKE#
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 Gpio0 to generate SMI#
10 Gpio0 to generate SMI# followed by SCI
11 Gpio0 to generate IRQ13
These two bits configure GPM4
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 Gpm4 to generate SMI#
10 Gpm4 to generate SMI# followed by SCI
11 Gpm4 to generate IRQ13
These two bits configure GPM5
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 Gpm5 to generate SMI#
10 Gpm5 to generate SMI# followed by SCI
11 Gpm5 to generate IRQ13
These two bits configure AzPme
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
Gpm4Config
Gpm5Config
AzPmeConfig
00b
00b
00b
01 AzPme to generate SMI#
10 AzPme to generate SMI# followed by SCI
11 AzPme to generate IRQ13
GPMConfig3 – RW – 8 bits - [PM_Reg: 35h]
Field Name
Bits
Default
Description
Gpm6Config
Gpm7Config
Gpio2Config
SataSciConfig
1:0
3:2
5:4
7:6
00b
These two bits configure GPM6
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 Gpm6 to generate SMI#
10 Gpm6 to generate SMI# followed by SCI
11 Gpm6 to generate IRQ13
These two bits configure GPM7
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 Gpm7 to generate SMI#
10 Gpm7 to generate SMI# followed by SCI
11 Gpm7 to generate IRQ13
These two bits configure Gpio2
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 Gpio2 to generate SMI#
10 Gpio2 to generate SMI# followed by SCI
11 Gpio2 to generate IRQ13
These two bits configure SataSci
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
00b
00b
00b
01 SataSci to generate SMI#
10 SataSci to generate SMI# followed by SCI
11 SataSci to generate IRQ13
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SMBus Module and ACPI Block (Device 20, Function 0)
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Page 152
GEvtLevelConfig - RW – 8 bits - [PM_Reg: 36h]
Field Name
Bits
Default
Description
GEvtLevelConfig
7:0
00h
GEVENT input level configuration
1 - Rising edge trigger
0 - Falling edge trigger
GEvtLevelConfig register.
GPMLevelConfig0 - RW – 8 bits - [PM_Reg: 37h]
Field Name
ExtEvent0LevelConfig
Bits
Default
Description
ExtEvent0 input level configuration
1 – Rising edge trigger
0
0b
0 – Falling edge trigger
ExtEvent1LevelConfig
PCIePmeLevelConfig
Gpm0LevelConfig
Gpm1LevelConfig
Gpm2LevelConfig
Gpm3LevelConfig
Gpm8LevelConfig
1
2
3
4
5
6
7
0b
0b
0b
0b
0b
0b
0b
ExtEvent1 input level configuration
1 – Rising edge trigger
0 – Falling edge trigger
PCIePme input level configuration
1 – Rising edge trigger
0 – Falling edge trigger
GPM0 input level configuration
1 – Rising edge trigger
0 – Falling edge trigger
GPM1 input level configuration
1 – Rising edge trigger
0 – Falling edge trigger
GPM2 input level configuration
1 – Rising edge trigger
0 – Falling edge trigger
GPM3 input level configuration
1 – Rising edge trigger
0 – Falling edge trigger
GPM8 input level configuration
1 – Rising edge trigger
0 – Falling edge trigger
GPMLevelConfig1 - RW – 8 bits - [PM_Reg: 38h]
Field Name
Gpio0LevelConfig
Bits
Default
Description
Gpio[0] or WAKE# input level configuration
1 – Rising edge trigger
0
0b
0 – Falling edge trigger
Gpm4LevelConfig
Gpm5LevelConfig
AzPmeLevelConfig
Gpm6LevelConfig
Gpm7LevelConfig
Gpio2LevelConfig
1
2
3
4
5
6
0b
0b
0b
0b
0b
0b
GPM4 input level configuration
1 – Rising edge trigger
0 – Falling edge trigger
GPM5 input level configuration
1 – Rising edge trigger
0 – Falling edge trigger
AzPme input level configuration
1 – Rising edge trigger
0 – Falling edge trigger
GPM6 input level configuration
1 – Rising edge trigger
0 – Falling edge trigger
GPM7 input level configuration
1 – Rising edge trigger
0 – Falling edge trigger
Gpio[2] input level configuration
1 – Rising edge trigger
0 – Falling edge trigger
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary
Page 153
GPMLevelConfig1 - RW – 8 bits - [PM_Reg: 38h]
Field Name
Bits
Default
Description
SataSciLevelConfig
7
0b
SataSci input level configuration
1 – Rising edge trigger
0 – Falling edge trigger
GEvtStatus - RW – 8 bits - [PM_Reg: 39h]
Field Name
GEvtStatus
Bits
Default
Description
7:0
--
GEVENT status. Write 1 to clear each bit
GEvtStatus register.
PMEStatus0 - RW – 8 bits - [PM_Reg: 3Ah]
Field Name
ExtEvent0Status
ExtEvent1Status
PCIePmeStatus
Gpm0Status
Gpm1Status
Gpm2Status
Gpm3Status
Gpm8Status
Bits
Default
Description
0
1
2
3
4
5
6
7
0b
0b
0b
0b
0b
0b
0b
0b
EXTEVENT0 -> SMI# status; write 1 to clear
EXTEVENT1 -> SMI# status; write 1 to clear
PCIePme -> SMI# status; write 1 to clear
GPM0 -> SMI# status; write 1 to clear
GPM1 -> SMI# status; write 1 to clear
GPM2 -> SMI# status; write 1 to clear
GPM3 -> SMI# status; write 1 to clear
GPM8 -> SMI# status; write 1 to clear
PMEStatus1- RW – 8 bits - [PM_Reg: 3Bh]
Field Name
Gpio0Status
Gpm4Status
Gpm5Status
AzPmeStatus
Gpm6Status
Gpm7Status
Gpio2Status
SataSciStatus
Bits
Default
Description
0
1
2
3
4
5
6
7
0b
0b
0b
0b
0b
0b
0b
0b
Gpio0 or WAKE# -> SMI# status; write 1 to clear
GPM4 -> SMI# status; write 1 to clear
GPM5 -> SMI# status; write 1 to clear
AzPme -> SMI# status; write 1 to clear
GPM6 -> SMI# status; write 1 to clear
GPM7 -> SMI# status; write 1 to clear
Gpio2 -> SMI# status; write 1 to clear
SataSci -> SMI# status; write 1 to clear
OthersConfig- RW – 8 bits - [PM_Reg: 3Ch]
Field Name
Bits
Default
Description
LegacySMIConfig
1:0
3:2
5:4
00b
These two bits configure legacy SMI# events
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 Legacy SMI EVENT to generate SMI#
10 Legacy SMI EVENT to generate SMI# followed by SCI
11 Legacy SMI EVENT to generate IRQ13
These two bits configure TALERT pin
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 TALERT to generate SMI#
10 TALERT to generate SMI# followed by SCI
11 TALERT to generate IRQ13
These two bits configure internal USB PME
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
TALERTConfig
USBConfig
00b
00b
01 UsbPme to generate SMI#
10 UsbPme to generate SMI# followed by SCI
11 UsbPme to generate IRQ13
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary
Page 154
OthersConfig- RW – 8 bits - [PM_Reg: 3Ch]
Field Name
Ac97Config
Bits
Default
Description
7:6
00b
These two bits configure AC97 PME
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 Ac97 PME to generate SMI#
10 Ac97 PME to generate SMI# followed by SCI
11 Ac97 PME to generate IRQ13
MorePmeConfig – RW – 8 bits - [PM_Reg: 3Dh]
Fi/eld Name
OtherThermConfig
Bits
Default
Description
These two bits configure OtherTherm
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
1:0
00b
01 OtherTherm to generate SMI#
10 OtherTherm to generate SMI# followed by SCI
11 OtherTherm to generate IRQ13
These two bits configure GPM[9]
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 GPM[9] to generate SMI#
10 GPM[9] to generate SMI# followed by SCI
11 GPM[9] to generate IRQ13
These two bits configure PCIeHotPlug
00 ACPI Event (trigger SCIOUT or SMI#
depending on SCI_EN bit)
01 PCIeHotPlug to generate SMI#
10 PCIeHotPlug to generate SMI# followed by SCI
11 PCIeHotPlug to generate IRQ13
Gpm9Config
3:2
5:4
7:6
00b
00b
00b
PCIeHotPlugConfig
Reserved
VRT_T1 - RW – 8 bits - [PM_Reg: 3Eh]
Field Name
Bits
Default
Description
VRT_T1
7:0
01h
The RTC battery is sampled (to conserve power) periodically
to checks its state of health. VRT_T1 and VRT_T2 make up
the interval of the checking. When VRT_Enable is high, the
battery is being sampled. When VRT_enable is low, the
battery is not being sampled. This register defines the time
of VRT enable being high for RTC battery monitor circuit, in
miliseconds.
VRT_T1 register.
VRT_T2 - RW – 8 bits - [PM_Reg: 3Fh]
Field Name
Bits
Default
Description
VRT_T2
7:0
FFh
This register defines the time of VRT enable being low for the
RTC battery monitor circuit, in 4 ms increment.
VRT_T2 register.
AD_Pull_UpB - RW – 8 bits - [PM_Reg: 40h]
Field Name
Bits
Default
Description
AD_Pull_UpB
7:0
00h
This register controls integrated pull-up for AD[31:24]
respectively.
0: Enable
1: Disable
AD_Pull_UpB register.
©2008 Advanced Micro Devices, Inc.
AMD SB600 Register Reference Manual
SMBus Module and ACPI Block (Device 20, Function 0)
Proprietary
Page 155
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