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CPX8000 Series CPX8216/CPX8216T
CompactPCI® System
Reference Manual
CPX8216A/RM4
August 2002 Edition
Safety Summary
The following general safety precautions must be observed during all phases of operation, service, and repair of
this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual
could result in personal injury or damage to the equipment.
The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as
the user of the product, should follow these warnings and all other safety precautions necessary for the safe
operation of the equipment in your operating environment.
Ground the Instrument.
To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If the
equipment is supplied with a three-conductor AC power cable, the power cable must be plugged into an approved
three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground
(safety ground) at the power outlet. The power jack and mating plug of the power cable meet International
Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes.
Do Not Operate in an Explosive Atmosphere.
Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes.
Operation of any electrical equipment in such an environment could result in an explosion and cause injury or
damage.
Keep Away From Live Circuits Inside the Equipment.
Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other
qualified service personnel may remove equipment covers for internal subassembly or component replacement
or any internal adjustment. Service personnel should not replace components with power cable connected. Under
certain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, such
personnel should always disconnect power and discharge circuits before touching components.
Use Caution When Exposing or Handling a CRT.
Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To
prevent CRT implosion, do not handle the CRT and avoid rough handling or jarring of the equipment. Handling
of a CRT should be done only by qualified service personnel using approved safety mask and gloves.
Do Not Substitute Parts or Modify Equipment.
Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local
Motorola representative for service and repair to ensure that all safety features are maintained.
Observe Warnings in Manual.
Warnings, such as the example below, precede potentially dangerous procedures throughout this manual.
Instructions contained in the warnings must be followed. You should also employ all other safety precautions
which you deem necessary for the operation of the equipment in your operating environment.
Warn ing
To prevent serious injury or death from dangerous voltages, use extreme
caution when handling, testing, and adjusting this equipment and its
components.
Warning
Flammability
All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating
of 94V-0 by UL-recognized manufacturers.
CE Notice (European Community)
Warnin g
This is a Class A product. In a domestic environment, this product may
cause radio interference, in which case the user may be required to take
adequate measures.
!
Warning
Motorola Computer Group products with the CE marking comply with the EMC Directive
(89/336/EEC). Compliance with this directive implies conformity to the following
European Norms:
EN55022 “Limits and Methods of Measurement of Radio Interference Characteristics
of Information Technology Equipment”; this product tested to Equipment Class A
EN55024 “Information technology equipment—Immunity characteristics—Limits and
methods of measurement”
This product also fulfills EN60950 (product safety) which is essentially the requirement for
the Low Voltage Directive (73/23/EEC).
AC configurations of this system also meet the requirements of the following European
standards:
EN61000-3-2 “Limits of Harmonic Current Emissions (equipment input current ≤ 16
A per phase)”
EN61000-3-3 “Limits of Voltage Fluctuations and Flicker in Low-Voltage Supply
Systems for Equipment with Rated Current ≤ 16 A”
In accordance with European Community directives, a “Declaration of Conformity” has
been made and is available on request. Please contact your sales representative.
This product is not a workstation per the European Ergonomic Standard.
Kein Bildschirmarbeitsplatz nach dem Europäischen Ergonomie Standard.
FCC Class A
This equipment has been tested and found to comply with the limits for a Class A digital
device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide
reasonable protection against harmful interference when the equipment is operated in a
commercial environment. This equipment generates, uses, and can radiate radio frequency
energy and, if not installed and used in accordance with the instruction manual, may cause
harmful interference to radio communications. Operation of this equipment in a residential
area is likely to cause harmful interference in which case the user will be required to correct
the interference at his own expense.
Changes or modifications not expressly approved by Motorola Computer Group could void
the user’s authority to operate the equipment.
Use only shielded cables when connecting peripherals to assure that appropriate radio
frequency emissions compliance is maintained.
EMI Caution
Caution
This equipment generates, uses and can radiate electromagnetic energy. It
may cause or be susceptible to electromagnetic interference (EMI) if not
installed and used with adequate EMI protection.
!
Caution
Notice
While reasonable efforts have been made to assure the accuracy of this document,
Motorola, Inc. assumes no liability resulting from any omissions in this document, or from
the use of the information obtained therein. Motorola reserves the right to revise this
document and to make changes from time to time in the content hereof without obligation
of Motorola to notify any person of such revision or changes.
Electronic versions of this material may be read online, downloaded for personal use, or
referenced in another document as a URL to the Motorola Computer Group Web site. The
text itself may not be published commercially in print or electronic form, edited, translated,
or otherwise altered without the permission of Motorola, Inc.
It is possible that this publication may contain reference to or information about Motorola
products (machines and programs), programming, or services that are not available in your
country. Such references or information must not be construed to mean that Motorola
intends to announce such Motorola products, programming, or services in your country.
Limited and Restricted Rights Legend
If the documentation contained herein is supplied, directly or indirectly, to the U.S.
Government, the following notice shall apply unless otherwise agreed to in writing by
Motorola, Inc.
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in
subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov.
1995) and of the Rights in Noncommercial Computer Software and Documentation clause
at DFARS 252.227-7014 (Jun. 1995).
Motorola, Inc.
Computer Group
2900 South Diablo Way
Tempe, Arizona 85282
About this Manual
Summary of Changes ................................................................................................xix
Systems Supported ....................................................................................................xxi
Comments and Suggestions .....................................................................................xxii
PICMG Compliance ................................................................................................. 1-1
Bus Access and Control ........................................................................................... 1-4
The Hot Swap Controller/Bridge (HSC) Module .................................................... 1-5
Hot Swap Controller ................................................................................................ 1-6
System Processor Configurations ............................................................................ 1-7
The Active/Passive Configuration .................................................................... 1-8
I/O Configurations ................................................................................................. 1-10
Power/Fan Modules ........................................................................................ 1-10
Drive Modules .................................................................................................1-11
CPU Complex Architecture ................................................................................... 1-12
The CPU Module ............................................................................................ 1-12
Chassis ID for CPX8216T ..................................................................................... 1-13
Alarms and LEDs ................................................................................................... 1-13
H.110 Telephony Bus ............................................................................................. 1-14
Board Insertion and Extraction Features ................................................................ 1-14
Staged Pins ...................................................................................................... 1-15
BD_SEL# ........................................................................................................ 1-15
ENUM# ........................................................................................................... 1-15
vii
Hot Swap Control Status Register (CSR) ........................................................ 1-16
Physical Connection Process ........................................................................... 1-17
Hardware Connection Process ......................................................................... 1-17
Software Connection Process .......................................................................... 1-18
Software Disconnection Process ..................................................................... 1-18
Typical Insertion and Extraction Processes ..................................................... 1-19
Device Drivers ........................................................................................................ 1-19
Overview .................................................................................................................. 2-1
Connectors and Jumper Settings ....................................................................... 2-4
COM1 Connector (J15) .............................................................................. 2-5
Debug Connector (J19) .............................................................................. 2-6
CPV5350 ................................................................................................................ 2-16
Connectors ....................................................................................................... 2-18
Transition Module ........................................................................................... 2-19
DRAM Memory Configuration ....................................................................... 2-20
Keyboard/Mouse PS2 Connector .................................................................... 2-20
Ethernet Connectors ........................................................................................ 2-21
CHAPTER 3 CPX8540 Carrier Card
Overview .................................................................................................................. 3-1
CPX8540 Carrier Card ............................................................................................. 3-1
Connector Pinouts ..................................................................................................... 3-4
viii
CHAPTER 4 PMC Modules
Overview .................................................................................................................. 4-1
SCSI-2 Controller PMC ........................................................................................... 4-1
Overview .................................................................................................................. 5-1
CPX750HATM Transition Module .......................................................................... 5-1
Serial Port Interface Jumper (J8 and J9) ........................................................... 5-4
Connectors ........................................................................................................ 5-4
Parallel I/O Port Connector (J7) ................................................................ 5-9
EIDE Connector (J15) ............................................................................. 5-11
PMC I/O Connectors ............................................................................... 5-14
CPV5350TM80 Transition Module ....................................................................... 5-29
Connectors ...................................................................................................... 5-31
Serial Port Connectors ............................................................................. 5-33
EIDE Headers (J5) ................................................................................... 5-36
Floppy Header (J9) .................................................................................. 5-38
Keyboard/Mouse/Power LED Header (J6) .............................................. 5-40
USB Headers (J12 and J19) ..................................................................... 5-41
SM Bus and LM78 Header (J1) ............................................................... 5-42
Fan Tachometer Headers (J3 and J4) ....................................................... 5-43
ix
Chapter Overview ..................................................................................................... 6-1
Parts of the System ................................................................................................... 6-2
CompactPCI Card Cage Reference .......................................................................... 6-4
Backplane Reference ................................................................................................ 6-5
Power Supply Connectors (PS1, PS2, PS3) ............................................................. 6-6
H.110 Power Connector (CPX8216T Only) ............................................................. 6-7
Alarm Interface Connector (ALARM) ..................................................................... 6-8
Floppy Drive Connectors (FDA, FDB) .................................................................... 6-8
IDE Drive Connectors (IDEA and IDEB) ................................................................ 6-9
Peripheral Power Connectors (PWR1, PWR2, PWR3, PWR4) ............................. 6-10
Secondary (Rear) Side I/O Connectors ........................................................... 6-26
(Transition Slots 7 and 9) ....................................................................................... 6-27
Primary (Front) Side I/O Connectors .................................................................... 6-38
Primary (Front) Side (Slots 1-6 and 11-16) .................................................... 6-38
Primary (Front) Side CPU Connectors ............................................................ 6-40
Primary (Front) Side HSC Connectors ............................................................ 6-40
Secondary (Rear) Side I/O Connectors .................................................................. 6-50
Secondary (Rear) Side CPU Transition Module Connectors ................................. 6-50
Power Distribution Panel ........................................................................................ 6-54
Dual Input DC Power Distribution Panel (CPX8216) .................................... 6-55
Dual Breaker DC Power Distribution Panel (CPX8216) ................................ 6-55
H.110 DC Power Distribution Panel (CPX8216T) ......................................... 6-56
Power Supplies ....................................................................................................... 6-58
x
APPENDIX A Specifications
Environmental Characteristics .................................................................................A-1
Power Supply Electrical Specifications ...................................................................A-2
APPENDIX B Related Documentation
Motorola Computer Group Documents ...................................................................B-1
Related Specifications ..............................................................................................B-2
URLs ........................................................................................................................B-4
xi
Figure 1-1. CPX8216 Domains ............................................................................... 1-2
Figure 1-2. CPX8216 Standard System Layout ...................................................... 1-3
Figure 1-3. CPX8216T H.110 System Layout ........................................................ 1-4
Figure 1-4. CPX8216 I/O Bus Connectivity ........................................................... 1-5
Figure 1-5. The CPX8216T H.110 Bus ................................................................. 1-14
Figure 2-1. CPV5350 Component Side View ....................................................... 2-19
Figure 2-2. Keyboard/Mouse Connector Diagram ................................................ 2-20
Figure 3-1. PMC Modules to CPX8540 Carrier Card ............................................ 3-2
Figure 3-2. Installing a PMC Module ..................................................................... 3-3
Figure 5-1. CPX750HATM Transition Module ...................................................... 5-3
Figure 5-2. Serial Port Interface Jumper (J9) Settings ............................................ 5-4
Figure 5-3. DTE Port Configuration (COM1 and COM2) ................................... 5-19
Figure 5-4. EIA-232-D DCE Port Configuration (Ports 3 and 4) ......................... 5-21
Figure 5-5. EIA-232-D DTE Port Configuration (Ports 3 and 4) ......................... 5-22
Figure 5-6. EIA-530 DCE Port Configuration (Ports 3 and 4) ............................. 5-23
Figure 5-7. EIA-530 DTE Port Configuration (Ports 3 and 4) ............................. 5-24
Figure 5-8. V.35-DCE Port Configuration (Ports 3 and 4) .................................... 5-25
Figure 5-9. V.35-DTE Port Configuration (Ports 3 and 4) .................................... 5-26
Figure 5-10. X.21-DCE Port Configuration (Ports 3 and 4) ................................. 5-27
Figure 5-11. X.21-DTE Port Configuration (Ports 3 and 4) ................................. 5-28
Figure 5-12. Keyboard/Mouse Connector Diagram .............................................. 5-32
Figure 6-1. CPX8216 Front View ........................................................................... 6-2
Figure 6-2. CPX8216 Rear View ............................................................................ 6-3
Figure 6-3. Card Cage Rail Color Scheme—CPX8216 Standard System .............. 6-4
Figure 6-4. Card Cage Rail Color Scheme—CPX8216T H.110 System ................ 6-4
Figure 6-5. CPX8216 and CPX8216T Backplane—Primary Side ......................... 6-5
Figure 6-6. The CPX8216T H.110 Bus ................................................................. 6-37
Figure 6-7. Alarm Display Panel Block Diagram ................................................. 6-51
Figure 6-8. Alarm Display Panel—Front View .................................................... 6-52
Figure 6-9. AC Power Distribution Panel—Front View ....................................... 6-54
Figure 6-10. Dual Input DC Power Distribution Panel—Front View ................... 6-55
Figure 6-11. Dual Breaker DC Power Distribution Panel—Front View ............... 6-56
Figure 6-12. H.110 DC Power Distribution Panel ................................................ 6-57
xiii
Table 2-1. CompactPCI Boards ............................................................................... 2-1
Table 2-2. USB 0 Connector J18 ............................................................................. 2-4
Table 2-3. USB 1 Connector J17 ............................................................................. 2-4
Table 2-4. 10BaseT/100BaseTx Connector J8 ........................................................ 2-5
Table 2-5. COM1 Connector J15 ............................................................................ 2-5
Table 2-6. Debug Connector (J19) .......................................................................... 2-6
Table 2-7. DRAM Mezzanine Connector (J10) .................................................... 2-10
Table 2-8. EIDE Compact FLASH Connector J9 ................................................. 2-14
Table 2-9. CPV5350 Front Panel Connectors, Board Headers and Components . 2-18
Table 2-10. Keyboard/Mouse P/S2 Connector Pin Assignments (J50) ................ 2-20
Table 2-11. Ethernet Connector Pin Assignments (J13 and J6) ............................ 2-21
Table 2-12. USB Connector Pin Assignments (J14) ............................................. 2-21
Table 2-13. Serial Port Connector Pin Assignments (J24 and J25) ...................... 2-22
Table 2-14. Video Connector Pin Assignments (J23) ........................................... 2-22
Table 3-1. CPCI J3 I/O Connector Pinout ............................................................... 3-4
Table 3-2. CPCI J5 I/O Connector Pinout ............................................................... 3-4
Table 3-3. PCI 32-bit Interface Connector P11/J11, P21/J21 ................................. 3-5
Table 3-4. PCI 32-bit Interface Connector P12/J12, P22/J22 ................................. 3-7
Table 3-5. PCI 64 bit PCI extension on PMC Connector J13, J23 ......................... 3-8
Table 3-6. User-Defined I/O PCI Interface Connector P14/J14, P24/J24 ............... 3-9
Table 4-1. PMC Switch Settings ............................................................................. 4-3
Table 4-2. PMC Pin Assignments ........................................................................... 4-4
Table 5-1. System Components ............................................................................... 5-1
Table 5-2. J3 User I/O Connector ............................................................................ 5-5
Table 5-3. J5 User I/O Connector ............................................................................ 5-6
Table 5-4. COM1 (J11) and COM2 (J10) ............................................................... 5-7
Table 5-5. Serial Port 3 (J6) .................................................................................... 5-7
Table 5-6. Serial Port 4 (J24) .................................................................................. 5-8
Table 5-7. Parallel I/O Connector (J7) .................................................................... 5-9
Table 5-8. Keyboard/Mouse Connector (J16) ....................................................... 5-10
Table 5-9. EIDE Connector (J15) ...........................................................................5-11
Table 5-10. Floppy Connector (J17) ..................................................................... 5-12
Table 5-11. +5Vdc Power Connector (J14) ........................................................... 5-13
Table 5-12. Speaker Output Connector (J13) ........................................................ 5-13
xv
Table 5-13. PMC I/O Connector (J2) .................................................................... 5-14
Table 5-14. PMC I/O Connector (J21) .................................................................. 5-15
Table 5-15. Keyboard/Mouse P/S2 Connector Pin Assignments (J14) ................. 5-32
Table 5-16. Ethernet Connector Pin Assignments (J13 and J18) .......................... 5-33
Table 5-17. Serial Port Connector Pin Assignments
(J21 and J10) ........................................................................................................... 5-33
Table 5-18. Video Connector Pin Assignments (J16) ............................................ 5-34
Table 5-19. Parallel Connector Pin Assignments (J20) ......................................... 5-35
Table 5-20. EIDE Header (J5) Pin Assignments ................................................... 5-36
Table 5-21. Floppy Header (J9) Pin Assignments ................................................. 5-38
Table 5-22. Keyboard/Mouse/Power LED Header (J6) Pin Assignments ............ 5-40
Table 5-23. USB Headers (J12 and J19) Pin Assignments .................................... 5-41
Table 5-24. SM Bus and LM78 Header (J1)Pin Assignments .............................. 5-42
Table 5-25. Fan Tachometer Header (J3 and J4) Pin Assignments ....................... 5-43
Table 5-26. Indicator LED/Miscellaneous Header (J2) Pin Assignments ............. 5-43
Table 6-1. System Components ............................................................................... 6-1
Table 6-2. PS1, PS2, and PS3 Pin Assignments ...................................................... 6-6
Table 6-3. Fan Module Pin Assignments ................................................................ 6-7
Table 6-4. H.110 Power Connector ......................................................................... 6-7
Table 6-6. FDA and FDB Pin Assignments ............................................................ 6-8
Table 6-7. IDEA and IDEB Pin Assignments ......................................................... 6-9
Table 6-8. PWR1, PWR2, PWR3, PWR4 Pin Assignments ................................. 6-10
Table 6-9. SIG1, SIG2, SIG3, SIG4 Pin Assignments .......................................... 6-11
Table 6-10. P5 Connector, I/O Slots 1-6 and 11-16
(User I/O) ................................................................................................................ 6-12
Table 6-11. P4 Connector, I/O Slots 1-6 and 11-16 (User I/O) ............................. 6-12
Table 6-12. P3 Connector, I/O Slots 1-6 and 11-16 (User I/O) ............................. 6-12
Table 6-13. P2 Connector, I/O Slots 1-6 and 11-16 (CPCI Bus) ........................... 6-13
Table 6-14. P1 Connector, I/O Slots 1-6 and 11-16 (CPCI Bus) ........................... 6-14
Table 6-15. P5 Connector, CPU Slots 7 and 9 ....................................................... 6-17
Table 6-16. P4 Connector, CPU Slots 7 and 9 ....................................................... 6-18
Table 6-17. P3 Connector, CPU Slots 7 and 9 ....................................................... 6-20
Table 6-18. P2 Connector, CPU Slot 7 (Domain A) .............................................. 6-20
Table 6-19. P2 Connector, CPU Slot 9 (Domain B) .............................................. 6-22
Table 6-20. P1 Connector, CPU Slots 7 and 9 ....................................................... 6-23
Table 6-21. P5 Connector, I/O Slots 1-6 and 11-16 (User I/O) ............................. 6-26
Table 6-22. P4 Connector, I/O Slots 1-6 and 11-16 (User I/O) ............................. 6-26
Table 6-23. P3 Connector, I/O Slots 1-6 and 11-16 (User I/O) ............................. 6-26
xvi
Table 6-24. P5 Connector, CPU Transition Module Slots .................................... 6-27
Table 6-25. P3 Connector, CPU Transition Slots 7 and 9 ..................................... 6-28
Table 6-26. P5 Connector, HSC/Bridge (Slots 8 and 10) ...................................... 6-29
Table 6-27. P4 Connector, HSC/Bridge (Slots 8 and 10) ...................................... 6-29
Table 6-28. P3 Connector, HSC Slots 8 and 10 .................................................... 6-31
Table 6-29. P2 Connector, HSC Slot 10 ................................................................ 6-32
Table 6-30. P2 Connector, HSC Slot 8 .................................................................. 6-34
Table 6-31. P1 Connector, HSC Slots 8 and 10 .................................................... 6-35
Table 6-32. P4 Connector, I/O Slots 1-6, 11-16 .................................................... 6-38
Table 6-33. P5 Connector, HSC/Bridge (Slots 8 and 10) ...................................... 6-40
Table 6-34. P4 Connector, HSC Slots 8 and 10 .................................................... 6-42
Table 6-35. P3 Connector, HSC Slots 8 and 10 .................................................... 6-44
Table 6-36. P2 Connector, HSC Slot 10 ................................................................ 6-45
Table 6-37. P2 Connector, HSC Slot 8 .................................................................. 6-47
Table 6-38. P1 Connector, HSC Slots 8 and 10 .................................................... 6-48
Table 6-39. P5 Connector, I/O Slots 1-6 and 11-16 (User I/O) ............................. 6-50
Table 6-40. P3 Connector, I/O Slots 1-6 and 11-16 (User I/O) ............................. 6-50
Table 6-41. Alarm LED Color and Description .................................................... 6-52
Table 6-42. Alarm Display Panel Interface Connector (J4) .................................. 6-53
Table 6-43. Remote Alarm Connector (J1) ........................................................... 6-53
Table 6-44. DC Analog Voltages for H.110 Bus ................................................... 6-57
Table A-1. Total Regulation (per Output) ...............................................................A-3
Table B-1. Related Specifications ...........................................................................B-2
xvii
About this Manual
This manual is directed at the person who needs detailed configuration and
specification information for CompactPCI modules and system
subassemblies of the CPX8000 series computer system. Included is an
overview of the system architecture for the CPX8216 and CPX81216T
the modules and subassemblies covered.
This manual does not provide installation, removal, or use procedures.
People requiring this type of information should refer to the CompactPCI
CPX8216 and CPX8216T System Installation and Use manual as listed in
Appendix B, Related Documentation.
Summary of Changes
is a history of the changes affecting this manual.
Date
Change
July 2002
Modules.
Domain ownership further defined, see Chapter 1, System
Architecture
added (with Smart cable), see Dual Breaker DC Power
April 2002
Section describing system domains and domain
ownership information added, see System Domains on
page 1-1.
Section describing hot swap controllers added, see Hot
Swap Controller on page 1-6.
xix
Date
Change
Power distribution information added, see Power
Distribution Panel on page 6-54.
August 2001
Details about assigning chassis IDs on the CPX8216T
system added. See Chassis ID for CPX8216T on page
1-13.
Updated model numbers, see Systems Supported in this
section.
April 2001
Added cautions regarding hot swap software and hot
swappable drives.
July 2000
Updated pin assignment tables for connector P2
(HSC and CPU slots.)
March 2000
November 1999
DC Input voltage changed to -36Vdc to -72Vdc. Changed
URLs to reflect new Web sites.
Added System Architecture chapter.
Added TNV branch circuit safety standards information.
Added the Index.
August 1999
Added information for the CPV5350 Intel CPU
Added information for the H.110 Backplane and Power
Distribution Panel for the CPX8216T system
May 1999
Replaced Figure 2-1 with corrected board illustration
Original Document
January 1999
xx
Systems Supported
This information in this manual applies to the modules and subassemblies
supported by the following systems:
Model Number
Description
CPX8216SK24
CPX8216 Dual SCSI 466 MHz PowerPC Starter Kit,
256MB
CPX8216TSK24
CPX8216SK25
CPX8216TSK25
CPX8216T Dual EIDE 700 MHz Pentium Starter Kit,
512MB
CPX8216 Dual EIDE 700 MHz Pentium Starter Kit,
512MB
CPX8216T Dual EIDE 466 MHz PowerPC Starter
Kit, 256MB
xxi
Overview
❏ Chapter 5, Transition/Bridge Modules
❏ Chapter 6, Subassembly Reference
❏ Appendix A, Specifications
❏ Appendix B, Related Documentation
Comments and Suggestions
Motorola welcomes and appreciates your comments on its documentation.
We want to know what you think about our manuals and how we can make
them better. Mail comments to:
Motorola Computer Group
Reader Comments DW164
2900 S. Diablo Way
Tempe, Arizona 85282
You can also submit comments to the following e-mail address:
In all your correspondence, please list your name, position, and company.
Be sure to include the title and part number of the manual and tell how you
used it. Then tell us your feelings about its strengths and weaknesses and
any recommendations for improvements.
xxii
Conventions Used in This Manual
The following typographical conventions are used in this document:
bold
is used for user input that you type just as it appears; it is also used for
commands, options and arguments to commands, and names of
programs, directories and files.
italic
is used for names of variables to which you assign values. Italic is also
used for comments in screen displays and examples, and to introduce
new terms.
courier
is used for system output (for example, screen displays, reports),
examples, and system prompts.
<Enter>, <Return> or <CR>
represents the carriage return or Enter key.
Ctrl
represents the Control key. Execute control characters by pressing the
Ctrl key and the letter simultaneously, for example, Ctrl-d.
xxiii
1System Architecture
1
PICMG Compliance
The CPX8216 system is designed to be fully compliant with the
CompactPCI Hot Swap Specification developed by the PCI Industrial
Computers Manufacturing Group (PICMG). With the proper software
support and testing, it should be possible to integrate all proprietary and
third-party I/O modules which are compatible with this specification.
Further, the system allows the use of I/O modules which are not hot
swappable, but the system must be powered off when such modules are
inserted and extracted.
The CPX8216 also features the ability to hot swap system and nonsystem
processor boards, a feature which is beyond the scope of the PICMG
specification. As part of its commitment to open standards, Motorola will
propose that the processor hot swap capabilities of the CPX8216 be added
to the Hot Swap Specification. At this point, however, there are no third-
party CPU modules which are compatible with the CPX8216 system.
System Domains
The high availability and high slot count of the CPX8216 systems is made
possible by implementing two host CPU slots and multiple CompactPCI
bus segments in a single chassis. These bus segments, along with other
system resources are grouped into two logical domains, A and B, which
host sits on. Domain A includes CompactPCI bus segment A (slots 1 to 8),
the power supply/fan tray modules and alarm controls. In the CPX8216,
domain B consists of the CompactPCI bus segment B (slots 9 to 16). For
further information on domain control or ownership, see the section, Hot
Swap Controller on page 1-6.
1-1
System Architecture
1
Alarm Controls
Bus B
Drive
Bays
Bus A
Power Supply/FanTrays
Domain A
Domain B
Domain A/B
Figure 1-1. CPX8216 Domains
System Layout
The CPX8216 is a 16-slot, high-availability CompactPCI system with two
separate 6-slot CompactPCI I/O domains and the capability to contain
modules. It is also possible to configure the system as a simplex, high I/O
system containing a single CPU-HSC pair. Even as a simplex system, the
CPX8216 still provides improved availability through redundant power
supplies and the control/monitoring capabilities of the HSC, as described
in The Hot Swap Controller/Bridge (HSC) Module on page 1-5.
CPX8216
The CPX8216 standard system consists of two 8-slot subsystems, or
domains, each with two slots for the host processor and six slots for
nonhost CompactPCI boards. The HSC board mounts in the rear of the
chassis, behind the secondary CPU slot. Figure 1-2 on page 1-3 provides a
diagram of this configuration.
1-2
Computer Group Literature Center Web Site
CPX8216
1
Rear Card Locations
Segment A
Segment B
CPU Transition Module
CPU Transition Module
Segment B Segment A
Segment B
Transition Slots
Segment B
Transition Slots
HSC
HSC
1
2
3
4
5
6
7
9
11 12 13 14 15 16
Segment A
I/O Slots
Segment B
I/O Slots
Compact PCI
Segment A
Compact PCI Bus
Segment B
Front Card Locations
2450 9812
Figure 1-2. CPX8216 Standard System Layout
Each of the two independent I/O domains has its own system processor
slot. Each system processor has direct access to its local bus through an
onboard PCI-to-PCI (P2P) bridge. Each domain is also capable of
supporting a Hot Swap Controller (HSC) module that contains its own P2P
bridge. Thus, in a fully redundant configuration, there are two bridges that
have access to each of the I/O buses—one associated with the CPU and one
with the HSC. Only one of the bridges may be active at a time, however.
1-3
System Architecture
1
CPX8216T (H.110)
The CPX8216T H.110 system consists of two 8-slot subsystems, or
domains, each with one slot for the host processor, one slot for the front-
loaded HSC, and six slots for nonhost CompactPCI boards. Figure 1-3 on
page 1-4 provides a diagram of this configuration.
Rear Card Locations
Segment A
Segment B
CPU Transition Module
CPU Transition Module
Segment B
Segment B
Transition Slots
Transition Slots
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CPU
A
CPU
B
Segment A
I/O Slots
Segment B
I/O Slots
Segment A
HSC
Segment B
HSC
Compact PCI
Segment A
Compact PCI Bus
Segment B
Front Card Locations
Figure 1-3. CPX8216T H.110 System Layout
Bus Access and Control
In the fully redundant configuration, the CPU in the left system slot, CPU
A, is associated with the HSC in the right HSC slot, HSC A (note that HSC
A actually sits on the Domain B bus). There is a local connection between
each CPU-HSC pair that allows the CPU in one domain to control the other
domain through its HSC. This architecture is illustrated in the following
figure.
1-4
Computer Group Literature Center Web Site
The Hot Swap Controller/Bridge (HSC) Module
1
Special Backplane
PCI Interconnects
C
P
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I/ODomainA
I/ODomain B
I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O
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Primary CompactPCI
Buses
Figure 1-4. CPX8216 I/O Bus Connectivity
In addition to providing bridges to the remote I/O buses, the HSC provides
the services necessary to hot swap CPU boards and nonhost processor
boards and also controls the system alarm panel, fans, and power supplies.
The Hot Swap Controller/Bridge (HSC) Module
The HSC module connects to the CPU module through a local PCI bus, as
illustrated in Figure 1-2 and Figure 1-3. The HSC module contains a PCI-
to-PCI bridge and also contains a Hot Swap Controller.
The functionality provided by the HSC is at the heart of the High
Availability CPX8216 System. Its primary functions include:
❏ Providing a bridge between the two eight-slot CompactPCI buses
so that they can be managed by a single CPU module
❏ Maintaining a Control Status Register which contains information
on the status of each system module
1-5
System Architecture
1
❏ Controlling power and resets to each system module through
radial connections
❏ Monitoring and controlling CPU boards, nonhost boards, and
peripherals, including power and fan sleds, board and system
LEDs, and alarms
Hot Swap Controller
Each of the nonhost slots in the system can be controlled from either HSC.
When an HSC has control over a domain it has control over the nonhost
boards in that domain. Each host processor/bridge pair is controlled as a
single item by the other processor/bridge pair. The bridge and the host
processor are linked together so that both must be present for power to be
applied. A host processor cannot be operated without its HSC.
With the CPX8216 architecture it is important that the system initializes to
a state that allows the host processors and HSCs to be in control of the
system. The default conditions are:
❏ System processors and bridges are powered up (if present)
❏ System processors and bridges are disconnected from their busses
❏ HSCs are not in control of either domain
❏ Nonhost boards are powered off
❏ Peripheral bays are powered up (if present)
❏ Fans and power supplies are powered on
Note
System components such as fans and power supplies may be
controlled by either HSC but not both. Default control belongs to
Domain A and whichever HSC has control of Domain A has
control of the system functions.
If Domain A is not controlled, nonhost boards are powered-off
and all LED updates to the display panel and power supplies are
suspended. Also, monitoring of alarm inputs from the display
panel and power supplies are inhibited.
1-6
Computer Group Literature Center Web Site
System Processor Configurations
1
Subsequent to the default, the system software must determine the
configuration of the system and then proceed to change it.
System Processor Configurations
The CPX8216 is a flexible system that allows for multiple configurations
of processor control, I/O redundancy, and peripheral configurations. The
following sections briefly touch on possible configurations.
As noted above, there are three possible processor/control configurations:
❏ A simplex system containing a single CPU-HSC pair controlling
both I/O domains
❏ An active/passive configuration similar to the simplex
configuration, but providing a warm backup for both the CPU and
the HSC
❏ An active/active or load-sharing configuration in which each CPU
runs a single domain while also serving as a backup to the other
CPU.
Note
H.110 traffic and HA Linux do not support a load-
sharing configuration.
The following sections give a general description of these configurations.
The Simplex Configuration
Because of the flexible nature of the CPX8216, it is possible to configure
it with different levels of redundancy and availability. For applications
which do not require the benefits of full high availability, it is possible to
configure the CPX8216 as a simplex, 16-slot system. This configuration
provides the benefits of redundant power supplies and the system
monitoring capabilities of the fully redundant configuration.
1-7
System Architecture
1
The simplex configuration is illustrated in the following figure.
H
S
C
C
P
U
A
A
I/ODomainA
I/ODomainB
I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O
S
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The Active/Passive Configuration
In the active/passive configuration, one CPU manages all twelve I/O slots,
much like in the simplex configuration. In addition, the second CPU serves
as a warm standby, ready to run the system in the event of a failure on the
active system.
The active/passive configuration is illustrated in the following figure.
Active CPU
Active HSC
C
P
U
H
S
C
H
S
C
C
P
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A
B
B
A
I/O Domain A
I/O Domain B
Passive
CPU/HSC
I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O
S
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1-8
Computer Group Literature Center Web Site
The Active/Active or Load-Sharing Configuration
1
The Active/Active or Load-Sharing Configuration
In the load sharing configuration, each CPU manages six of the twelve I/O
slots, much like a dual 8-slot system with the added benefit of one CPU
being able to control all twelve I/O slots if the other CPU fails. It is
important in a load-sharing configuration to note that the total critical
activity does not exceed the capabilities of a single CPU, because either
one of the CPUs must be ready to take over the load carried by the other.
The active/active configuration is illustrated in the following figure.
H
S
C
C
P
U
H
S
C
C
P
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B
A
B
A
I/ODomainA
I/ODomain B
I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O
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Note
H.110 traffic and HA Linux do not support a load-sharing
configuration.
1-9
System Architecture
1
I/O Configurations
The CPX8216 contains two independent 8-slot CompactPCI buses. One
slot in each bus is dedicated to a system processor, and another is needed
for the HSC. This leaves six slots on each bus to support I/O devices or
nonsystem processors.
One possible configuration is to use the CPX8216 as a high I/O
CompactPCI system with redundant CPUs. With this configuration, it is
possible to run twelve independent I/O modules within a CPX8216
system. Applications requiring dense processing power could use all
twelve I/O slots to support nonsystem processors.
Such a system would be protected against a CPU or HSC fault, but it would
be vulnerable to data losses if any of the I/O modules or nonsystem
processor modules were to fail. In systems handling critical data, it is
possible to implement a 2N or an N+1 I/O redundancy strategy that allows
the level of service to be continued in the event that a module fails.
In the case of a 2N-redundant system, each I/O module or nonsystem
processor module is matched with an identical module on the other bus.
The paired modules can be configured in an active/passive arrangement or
a load-sharing arrangement in which each carries half of the load of a
single module. In an N+1 arrangement, multiple modules are backed up by
a single spare. For example, a single passive nonsystem processor module
can be used to back up five others.
Peripherals
Power/Fan Modules
The CPX8216 system requires a minimum of two power/fan sled modules
and a fan-only sled module to provide adequate power and cooling for a
fully loaded, nonredundant system. The system can contain a third power
supply/fan sled as part of an N+1 strategy, meaning that the system can
continue providing service if one of the modules fails. These modules are
hot swappable and available for DC and AC environments.
1-10
Computer Group Literature Center Web Site
Drive Modules
1
The fans run at either high speed (default) or temperature controlled, which
can be changed using the operating system software via the API.
Drive Modules
The CPX8216 contains four hot-swappable peripheral bays, all of which
support both SCSI and EIDE protocols.
Caution
The hot swapping of hard drives is supported when your system is
configured with the appropriate software support for hot swap and when
the drives are in a hot-swap drive carrier.
!
Caution
SCSI devices can be configured to be fully hot-swappable, and data can be
hot switched between two independent SCSI controllers. EIDE devices are
assigned to a single EIDE controller. They can be warm swapped, meaning
that a failed device can be replaced once the controller has been powered
off.
The rear of the CPX8216 chassis may be configured with either single or
double, fixed, floppy drives. Floppy drives are not hot-swappable.
For more information on installing both hot-swappable and non-hot-
swappable drives, refer to the Drive Removal and Installation chapter of
the CPX8216 and CPX8216T CompactPCI System Installation and Use
manual.
1-11
System Architecture
1
CPU Complex Architecture
The CPU complex in the CPX8216 contains two CPU modules and their
corresponding Hot Swap Controller (HSC) modules. The figure below
illustrates the architecture, including elements on the boards as well as
local connections between the CPU modules and the PCI-to-PCI (P2P)
connections to the local CompactPCI buses.
Local Connections between CPU Modules
Proc
RAM
RAM
Proc
HSC
P2P
HSC
P2P
Enet
Enet
ISA P2P
IDE
P2P ISA
IDE
Serial
Link
Serial
Link
CompactPCI Bus
CompactPCI Bus
The CPU Module
In addition to the processor, RAM, etc., each CPU module contains one:
❏ Up to two Ethernet controllers
❏ Up to two serial communications links
❏ P2P bridge to the local CompactPCI bus
❏ Local PCI Bus connection to the HSC
1-12
Computer Group Literature Center Web Site
Switching Service to the Passive CPU
1
Switching Service to the Passive CPU
The switchover from one CPU to another is initiated by the passive CPU
when there is an indication that there is something wrong with the active
CPU--such as a failed heartbeat protocol. The passive side notifies the
active side that it is about to begin a switchover process. If the active side
agrees to the switchover, then the two sides coordinate the hand-off and no
bus signals, clocks, or devices should be corrupted. If the active system
fails to cooperate with the takeover attempt, then we must assume that bus
signals, clocks, and devices attached to the bus may be corrupted.
In a more extreme takeover, it is possible for the passive CPU to power-on
reset the active CPU and to take control that way.
Chassis ID for CPX8216T
A unique 5-bit chassis ID can be assigned for each CPX8216T system.
Hex values are on the rotary switches located on the HSC boards. A jumper
can be added to J14 to double the number of unique identifiers. This
feature should be used if more than 15 chassis are deployed in one location.
The HSC boards are shipped with no jumper as the default. For guidelines
on setting the chassis ID on your CPX8216T system, refer to the CPX8000
Series CPX8216 and CPX8216T CompactPCI System Installation and Use
manual.
Alarms and LEDs
In order to provide a uniform appearance, without depending on individual
board manufacturers, the CPX8216 contains a separate alarm display
panel, which runs across the top of the chassis. In addition to In
Service/Out of Service LED indicators for all sixteen slots, the alarm
display panel contains LEDs for system status (System in
Service/Component out of Service/System out of Service) and for the three
standard Telco levels (Critical/Major/Minor). The three Telco alarms are
also signalled through a dry contact relay.
1-13
System Architecture
1
H.110 Telephony Bus
The CPX8216T supports an H.110 Computer Telephony Bus. The H.110
bus uses P4/J4 as defined in the PICMG specification for CompactPCI.
P5
P4
H. 110 Bus
P3
P2
CompactPCI Bus
System Slot
P1
HSC Slot
2557 9906
Figure 1-5. The CPX8216T H.110 Bus
Board Insertion and Extraction Features
The PICMG specification details software and hardware features, in order
to support hot swapping of I/O boards. Hardware features include:
❏ Staged pins that control voltages when inserting or extracting
boards
❏ BD_SEL#, HEALTHY#, and ENUM# signals
❏ Hot swap control status register
1-14
Computer Group Literature Center Web Site
Staged Pins
1
Staged Pins
The PICMG CompactPCI hot swap specification provides for three
separate pin lengths in order to control the insertion and extraction
voltages and to notify the system when boards are inserted or extracted.
The longest pins, which include VCC pins and GND pins, are the first to
mate during the insertion process and the last to break contact during
extraction. These pins are used to supply power to pre-charge the PCI
interface signals to a neutral state before they contact the bus. This pre-
charging serves to minimize the capacitive effects of the board as it makes
or breaks contact with the bus.
The medium-length pins carry PCI and other signal traffic.
The shortest pins are used to assert signals, including BD_SEL#. During
insertion, the BD_SEL# signal enables the board to attach to the local PCI
bus. On extraction, it causes the board to logically and electrically
disconnect from the PCI bus before the bus pins physically break contact
with the bus.
BD_SEL#
ENUM#
BD_SEL# is asserted by one of the pins that mate last on insertion and
break first on extraction. On insertion, the signal tells the board to connect
to the PCI bus. On extraction this pin breaks first, causing the board to
logically and electrically disconnect from the PCI bus before the PCI bus
pins physically break contact with the bus.
An ENUM interrupt is generated when a board is hot inserted into the
CPX8216 chassis, or when an operator trips the board microswitch by
raising its ejector handles. The signal informs the active CPU that the
status of a board has changed. The CPU then identifies the board by polling
the INSert and EXTract bits in all of the boards’ Control Status Registers.
1-15
System Architecture
1
Hot Swap Control Status Register (CSR)
The CPX8216 supports hot swap CompactPCI cards with the standard
control status register defined by the PICMG Hot Swap Specification. The
register is visible in PCI configuration space and provides hot swap control
and status bits: INS and EXT. The INS signal is set when ENUM# is
asserted by a board being inserted into the system. The EXT signal is
asserted when ENUM# is asserted by an operator triggering the
microswitch in the board handles. The host also uses these bits to
acknowledge and de-assert ENUM#.
The Hot Swap Process
PICMG divided the complete hot swap process into physical, hardware
and software connection processes. These processes are formally broken
down further into a group of transitional states, which are illustrated in the
following figure.
PHYSICAL
CONNECTION CONNECTION STATES
STATES
HARDW ARE
SOFTW ARE
CONNECTION
STATES
P0
P1
H0
H1
H2
S0
H1F
S1
S2
S3
S2Q
S3Q
When inserting a board, it goes through all states from P0 to S3.
Conversely, a board transitions from S3 to P0 before being extracted.
During normal operation, no states are skipped. Extracting a board in a
software connection state other than S0 is likely to disrupt software enough
to crash the system, but the CompactPCI bus, from a purely electrical point
of view, will not be disrupted enough to cause logic levels to be violated.
Certain states are overlapping. For example, when the board is fully seated
(completed P1), but has not yet started the hardware connection process
1-16
Computer Group Literature Center Web Site
Physical Connection Process
1
(H0), it said to be in the P1/H0 state. Similarly, one can speak of a board
being in the H2/S0 state.
Physical Connection Process
The physical connection process is the basic process of putting a board into
a live system, or physically removing the board. The process includes two
states:
❏ P0 - The board is physically separate from the system
❏ P1 - The board is fully seated, but not powered, and not active on
the PCI bus. All pins are connected.
Hardware Connection Process
The hardware connection process involves the electrical connection or
disconnection of the board. This process includes three states:
❏ H0 - The board is not active on the PCI bus. This state is equivalent
to P1 above.
❏ H1 - The board has powered up and is sufficiently initialized to
connect to the PCI bus.
❏ H2 - The board is powered, and enabled for access by a PCI bus
transaction (normally by the host) in PCI configuration space only.
The board configuration space is not yet initialized.
When a newly inserted board has completed H2, the board is operable
from a hardware perspective. It has run its power up diagnostics, initialized
itself, loaded EEPROM data, etc. The blue LED is off in the H2 state,
indicating that the board should not be pulled out.
1-17
System Architecture
1
Software Connection Process
The software connection process includes the tasks needed to configure
and load software. This process contains four states:
❏ S0 - The Software Connection Process has not been initiated. The
board’s configuration space registers are accessible but not yet
initialized.
❏ S1 - The board is configured by the system. The system has
initialized the board’s PCI configuration space registers with I/O
space, memory space, interrupts and PCI bus numbers. The board
is ready to be accessed by a device driver, but no drivers are loaded
at this time.
❏ S2 - The necessary supporting software (drivers, etc.) have been
loaded. The board is ready for use by the OS and/or the
application, but no operations involving the board are active or
pending.
❏ S3 - The board is active. Software operations are either active or
pending.
Software Disconnection Process
The software disconnection process defines two additional states which
are used when quiescing activity on a board in preparation for extraction:
❏ S3Q - The software is completing current operations, but is not
allowed to start new ones. When current operations are completed,
the board transitions to S2.
❏ S2Q - The board is quiesced. This is the same state as S2, except
that no new operations are allowed to be initiated.
The Software Disconnection Process proceeds as S3, S3Q, S2Q, S1, and
finally S0.
1-18
Computer Group Literature Center Web Site
Typical Insertion and Extraction Processes
1
Typical Insertion and Extraction Processes
Many of the steps in the insertion and extraction processes are automated
by software. After the operator installs a board, it automatically advances
to P1. The hardware connection process proceeds automatically and
asserts the ENUM# signal to initiate the software connection process. The
host responds to the bussed ENUM# signal by reading the Hot Swap
Control Status Register of each board to find out which one is signaling an
insertion or extraction (INS or EXT bit asserted). Upon detecting an
insertion, the Host responds by adding software drivers to support the
newly inserted board.
Extraction is initiated when the operator opens the board ejector handle,
which activates a mechanical switch to assert ENUM#. The hot plug
system driver senses ENUM# and notifies software that board activity
must be quiesced and that software device drivers should be unloaded. The
application that is using the board is informed that the resource is no longer
available. When the board is ready for extraction, software informs the
operator by illuminating the blue LED. After extraction, all system
resources previously assigned to that board are made available for other
uses.
Device Drivers
In order to take full advantage of the high availability functions of the
CPX8216, and to support hot swap, board device drivers need to be
enhanced. Drivers need to cease all activity when the device is about to be
hot swapped, and they need to support initialization of the device without
support from the device firmware or BIOS.
Further, high availability device drivers need to be able to enter a standby
mode while bus control is being passed from one CPU to another. They
also provide diagnostic interfaces for run time fault detection and for pre-
initialization testing of newly inserted boards.
1-19
2CPU Modules
2
Overview
This chapter provides reference information for the CompactPCI system
controller/host CPU modules supported in the CPX8216 system.
The correct jumper setting and pin-out information is provided for each
module.
Note
The CPX750HA is sometimes identified as an MCP750HA in
some chassis and firmware documentation, for packaging and
ordering purposes, but both numbers apply to the same board.
Your system may not contain all boards listed in this chapter, or
it may contain third-party boards that are not listed in this
chapter. For information about third-party boards, refer to the
board manufacturer’s documentation.
This chapter contains information for the following CompactPCI boards:
Slots
Part No.
Description
Occupied Page
CPX750HA
CPV5350
PowerPC Hot Swappable CPU
Intel Hot Swappable CPU
1
1
2-1
2-16
CPX750HA
The CPX750HA is a single-slot, single-board computer equipped with a
PowerPC™ 750 Series microprocessor. The processor implements a
backside cache controller and the board comes with 1MB of cache
memory.
2-1
CPU Modules
The CPX750HA offers many standard features desirable in a CompactPCI
computer system, such as:
2
❏ PCI Bridge and Interrupt Controller
❏ ECC Memory Controller chipset
❏ 5MB to 9MB of linear FLASH memory
❏ IDE CompactFlash memory
❏ 16MB to 256MB of ECC-protected DRAM
❏ Interface to a CompactPCI bus
❏ Several I/O peripherals
The I/O peripheral interfaces present on the onboard PCI bus include:
❏ One 10/100-BASE-T Ethernet interface
❏ One USB host controller
❏ One SA master/slave interface
❏ One Fast EIDE interface
❏ One PMC Slot
Functions provided from the ISA bus are two asynchronous and two
synchronous/asynchronous serial ports, keyboard, mouse, a floppy disk
controller, printer port, a real time clock, and NVRAM.
The CPX750HA interfaces to a CompactPCI bus using a DEC 21154 PCI-
to-PCI bridge device. This device provides a 64-bit primary and a 64-bit
secondary interface allowing full 64-bit data access between CompactPCI
bus devices and the host/PCI bridge. This bus is capable of driving seven
CompactPCI slots.
Another key feature of the CPX750HA is the PCI (Peripheral Component
Interconnect) bus. In addition to the onboard local bus peripherals, the PCI
bus supports an industry-standard mezzanine interface, IEEE P1386.1
PMC (PCI Mezzanine Card). PMC modules offer a variety of possibilities
for I/O expansion.
2-2
Computer Group Literature Center Web Site
CPX750HA
The base board supports PMC I/O for the front panel or through backplane
connector J3 to a CPX750HATM transition module.
2
RST
ABT
BFL CPU
CPI
CPCI
2
1
190
189
J19
2-3
CPU Modules
Connectors and Jumper Settings
2
The next sections provide pinout information and jumper settings for the
CPX750HA board. Additional pinout assignments can be found in
Chapters 3 through 6.
Backplane Connectors (P5, P4, P3, P2, P1)
Refer to the backplane reference section for the backplane connector pin
assignments.
Front USB Connectors (J17 and J18)
Two USB Series A receptacles are located at the front panel of the
CPX750HA board. The pin assignments for these connectors are as
follows:
Table 2-2. USB 0 Connector J18
1
2
3
4
UVCC0
UDATA0N
UDATA0P
GND
Table 2-3. USB 1 Connector J17
1
2
3
4
UVCC1
UDATA1N
UDATA1P
GND
10BaseT/100BaseTx Connector (J8)
The 10BaseT/100BaseTx Connector is an RJ45 connector located on the
front panel of the CPX750HA board. The pin assignments for this
connector are as follows:
2-4
Computer Group Literature Center Web Site
Connectors and Jumper Settings
2
Table 2-4. 10BaseT/100BaseTx Connector J8
1
2
3
4
5
6
7
8
TD+
TD-
RD+
AC Terminated
AC Terminated
RD-
AC Terminated
AC Terminated
COM1 Connector (J15)
A standard DB9 receptacle is located on the front panel of the CPX750HA
to provide the interface to the COM1 serial port. These COM1 signals are
also routed to J11 on the transition module. A terminal may be connected
to J15 or J11 on the transition module but not both at the same time. The
pin assignments for this connector is as follows:
Table 2-5. COM1 Connector J15
1
2
3
4
5
6
7
8
9
DCD
RXD
TXD
DTR
GND
DSR
RTS
CTS
RI
2-5
CPU Modules
Debug Connector (J19)
2
A 190-pin connector (J19 on the CPX750HA base board) provides access
to the processor bus (MPU bus) and some bridge/memory controller
signals. It can be used for debugging purposes. The pin assignments are
listed in the following table.
Table 2-6. Debug Connector (J19)
1
PA0
PA1
2
3
PA2
PA3
4
5
PA4
PA5
6
7
PA6
PA7
8
9
PA8
PA9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
PA10
PA12
PA14
PA16
PA18
PA20
PA22
PA24
PA26
PA28
PA30
PA_PAR0
PA_PAR2
APE*
PD0
PA11
PA13
PA15
PA17
PA19
PA21
PA23
PA25
PA27
PA29
PA31
PA_PAR1
PA_PAR3
RSRV*
PD1
GND
PD2
PD3
2-6
Computer Group Literature Center Web Site
Connectors and Jumper Settings
Table 2-6. Debug Connector (J19) (continued)
2
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
PD4
PD5
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
PD6
PD7
PD8
PD9
PD10
PD12
PD14
PD16
PD18
PA20
PD22
PD24
PD26
PD28
PD30
PD32
PD34
PD36
PD38
PD40
PD42
PD44
PD46
PD48
PA50
PD52
PD54
PD11
PD13
PD15
PD17
PD19
PD21
PD23
PD25
PD27
PD29
PD31
PD33
PD35
PD37
PD39
PD41
PD43
PD45
PD47
PD49
PD51
PD53
PD55
+5V
2-7
CPU Modules
Table 2-6. Debug Connector (J19) (continued)
2
95
PD56
GND
PD57
96
97
PD58
PD59
98
99
PD60
PD61
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
PD62
PD63
PDPAR0
PDPAR2
PDPAR4
PDPAR6
No Connection
DPE*
PDPAR1
PDPAR3
PDPAR5
PDPAR7
No Connection
DBDIS*
TSIZ0
TT0
TT1
TSIZ1
TT2
TSIZ2
TT3
No Connection
No Connection
No Connection
No Connection
No Connection
DBWO*
TS*
TT4
CI*
WT*
GLOBAL*
SHARED*
AACK*
ARTY*
DRTY*
TA*
+3.3V
XATS*
TBST*
No Connection
No Connection
DBG*
TEA*
No Connection
No Connection
DBB*
2-8
Computer Group Literature Center Web Site
Connectors and Jumper Settings
Table 2-6. Debug Connector (J19) (continued)
2
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
No Connection
TCLK_OUT
No Connection
MPUBR1*
MPUBG1*
WDT1TO*
WDT2TO*
L2BR*
ABB*
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
MPUBG-0*
MPUBR0*
IRQ0*
MCHK*
SMI*
CKSTPI*
CKSTPO*
HALTED (N/C)
TLBISYNC*
TBEN
L2BG*
CLAIM*
No Connection
No Connection*
No Connection*
No Connection*
No Connection
SRST1*
No Connection
No Connection
No Connection
NAPRUN
QREQ*
GND
SRESET*
QACK*
HRESET*
CPUTDO
CPUTDI
GND
CPUCLK1
CPUTCK
CPUTMS
CPUTRST*
No Connection
No Connection
2-9
CPU Modules
DRAM Mezzanine Connector (J10)
2
A 190-pin connector (J10 on the CPX750HA base board) supplies the
interface between the memory bus and the RAM300 DRAM mezzanine.
The pin assignments are listed in the following table.
Table 2-7. DRAM Mezzanine Connector (J10)
1
A_RAS∗
B_RAS∗
C_RAS∗
D_RAS∗
OEL∗
A_CAS∗
B_CAS∗
C_CAS∗
D_CAS∗
OEU∗
2
3
4
5
6
7
8
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
WEL∗
WEU∗
ROMBCS∗
RAMBEN
EN5VPWR
RAL1
ROMACS∗
RAMAEN
RAMCEN
RAL0
GND
RAL2
RAL3
RAL4
RAL5
RAL6
RAL7
RAL8
RAL9
RAL10
RAL12
RAU1
RAL11
RAU0
RAU2
RAU3
RAU4
RAU5
RAU6
RAU7
RAU8
RAU9
RAU10
RAU12
RAU11
2-10
Computer Group Literature Center Web Site
Connectors and Jumper Settings
Table 2-7. DRAM Mezzanine Connector (J10) (continued)
2
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
RDL0
RDL1
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
RDL2
RDL3
RDL4
RDL5
RDL6
RDL7
RDL8
RDL9
RDL10
RDL12
RDL14
RDL16
RDL18
RDL20
RDL22
RDL24
RDL26
RDL28
RDL30
RDL32
RDL34
RDL36
RDL38
RDL40
RDL42
RDL44
RDL46
RDL48
RDL50
RDL11
RDL13
RDL15
RDL17
RDL19
RDL21
RDL23
RDL25
RDL27
RDL29
RDL31
RDL33
RDL35
RDL37
RDL39
RDL41
RDL43
RDL45
RDL47
RDL49
RDL51
+5V
GND
2-11
CPU Modules
Table 2-7. DRAM Mezzanine Connector (J10) (continued)
2
97
RDL52
RDL54
RDL56
RDL58
RDL60
RDL62
CDL0
RDL53
RDL55
RDL57
RDL59
RDL61
RDL63
CDL1
98
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
CDL2
CDL3
CDL4
CDL5
CDL6
CDL7
No Connection
RDU0
No Connection
RDU1
RDU2
RDU3
RDU4
RDU5
RDU6
RDU7
RDU8
RDU9
RDU10
RDU12
RDU14
RDU16
RDU18
RDU20
RDU22
RDU24
RDU26
RDU28
RDU11
RDU13
RDU15
RDU17
RDU19
RDU21
RDU23
RDU25
RDU27
RDU29
+3.3V
2-12
Computer Group Literature Center Web Site
Connectors and Jumper Settings
Table 2-7. DRAM Mezzanine Connector (J10) (continued)
2
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
RDU30
RDU32
RDU34
RDU36
RDU38
RDU40
RDU42
RDU44
RDU46
RDU48
RDU50
RDU52
RDU54
RDU56
RDU58
RDU60
RDU62
CDU0
RDU31
RDU33
RDU35
RDU37
RDU39
RDU41
RDU43
RDU45
RDU47
RDU49
RDU51
RDU53
RDU55
RDU57
RDU59
RDU61
RDU63
CDU1
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
GND
CDU2
CDU3
CDU4
CDU5
CDU6
CDU7
2-13
CPU Modules
EIDE Compact FLASH Connector (J9)
2
A 50-pin Compact FLASH card header connector provides the EIDE
interface to the Compact FLASH Memory Card. The pin assignments for
this connector are as follows:
Table 2-8. EIDE Compact FLASH Connector J9
1
GND
DATA3
2
3
DATA4
DATA5
4
5
DATA6
DATA7
6
7
DCS1A_L
GND
GND
8
9
GND
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
GND
GND
+5V
GND
GND
GND
GND
DA2
DA1
DA0
DATA0
DATA1
DATA2
NO CONNECT
CD1_L
CD2_L
DATA11
DATA13
DATA15
NO CONNECT
DIOWA_L
INTRQA
MASTER/SLAVE
RST_L
DATA12
DATA14
DCS3A_L
DIORA_L
NO CONNECT
+5V
NO CONNECT
DIORDYA
NO CONNECT
NO CONNECT
2-14
Computer Group Literature Center Web Site
Connectors and Jumper Settings
Table 2-8. EIDE Compact FLASH Connector J9
2
45
47
49
NO CONNECT
DATA8
NO CONNECT
DATA9
46
48
50
DATA10
GND
Flash Bank Selection (J6)
The CPX750HA base board has provision for 1MB of 16-bit flash
memory. The RAM300 memory mezzanine accommodates 4MB or 8MB
of additional 64-bit flash memory.
The flash memory is organized in either one or two banks, each bank either
16- or 64-bits wide. Bank B contains the onboard debugger, PPCBug.
To enable flash bank A (4MB or 8MB of firmware resident on soldered-in
devices on the RAM300 mezzanine), place a jumper across header J6 pins
1 and 2. To enable flash bank B (1MB of firmware located in sockets on
the base board), place a jumper across header J6 pins 2 and 3.
J6
J6
3
2
1
3
2
1
Flash Bank A Enabled (4MB/8MB, Soldered)
Flash Bank B Enabled (1MB, Sockets)
(Factory Configuration)
2-15
CPU Modules
CPV5350
2
The CPV5350 Single Board Computer (SBC) is a hot swap, CompactPCI
(Compact Peripheral Communication Interface) compliant computer with
high availability platform support. It is powered by a PICMG (PCI
Industrial Computer Manufacturers Group) compatible Pentium® II
Deschutes Mobile Module. The CPV5350’s 6U CompactPCI standard
form factor (160mm x 233mm x 61mm), 4HP (.8 inch) is designed for
installation into PICMG CompactPCI-compliant backplanes.
The CPV5350 provides:
❏ Standard PC I/O
❏ USB
❏ PCI EIDE
❏ 3D AGP graphics
❏ Dual fast Ethernet controllers
❏ Optional onboard CompactFlash™ connector
The CPV5350’s front panel has connectors for:
❏ Keyboard/mouse
❏ Video
❏ Two serial ports (COM1 and COM2)
❏ Two Ethernet ports
❏ Two USB ports
❏ LED Indicator lights for watchdog alarm, speaker status, hard disk
drive activity, and power.
Refer to the following illustration for front panel connectors and LEDs on
the CPV5350.
2-16
Computer Group Literature Center Web Site
CPV5350
2
Video
V
I
D
E
O
COM 1
1
COM 2
2
Ethernet 1
1
E
T
H
E
R
N
E
Ethernet 2
USB
T
2
Keyboard/Mouse
RESET
Indicator
Lights
RESET
ALRM SPKR
PWR
HDD
CPV5350
2-17
CPU Modules
Connectors
2
The next table lists the connectors available to support devices on the
CPV5350. Figure 2-1 on page 2-19 shows the location of the connectors
described in the table.
Table 2-9. CPV5350 Front Panel Connectors, Board
Headers and Components
Connector
J1
Description
Backplane connector
Backplane connector
Backplane connector
Backplane connector
Backplane connector
Ethernet 2
J2
J3
J4
J5
J6
J9
EIDE
J10
J12
J13
J14
J16
J21
J23
J24
J25
J50
Reserved (in-circuit programming)
Reserved (in-circuit emulator)
Ethernet 1
USB port 1
Reset (connected to push-button on the front panel)
Flash ROM
Video connector
COM1 (Serial Port 1)
COM2 (Serial Port 2)
Keyboard/Mouse
2-18
Computer Group Literature Center Web Site
Transition Module
2
J5
J3
J1
J4
J2
U50
U34
U30
U35
U31
U38
8
1
J17
J20
2
1
U25
U26
1
2
BT1
U55
U62
J12
J21
U11
T1
T2
J51
CR2 CR4
1
2
J23
J24
J25
J13
J6
J14
J50
CR3
CRI
Figure 2-1. CPV5350 Component Side View
Transition Module
The CPV5350TM80 transition module provides backplane I/O through the
J3 and J5 connectors on the CPV5350 controller module.
When the identical function is available through the CPV5350’s front
panel and the rear transition module, you can use either the front or the
rear, not both.
2-19
CPU Modules
DRAM Memory Configuration
2
The CPV5350 has one 168-pin DIMM site for memory expansion. The
DIMM sites accept industry standard PC100-compliant DIMM modules
(8, 16, 32, 64, 128, or 256MB) with or without ECC. You can use either
registered or unbuffered memory modules.
Keyboard/Mouse PS2 Connector
The keyboard/mouse connector (J50) uses a 6-pin, female PS/2 connector.
Table 2-10. Keyboard/Mouse P/S2 Connector Pin
Assignments (J50)
Pin
Signal
Number Mnemonic
Signal Description
Keyboard Data
1
2
3
4
5
6
7
KBDDAT
AUXDAT
GND
Auxiliary Data
Ground
KBDVCC
KBDCLK
AUXCLK
CGND
Keyboard Power (current limited to .75 Amp)
Keyboard Clock
Auxiliary Clock
Common Ground
6
5
3
4
2
1
7
2489 9902
Figure 2-2. Keyboard/Mouse Connector Diagram
2-20
Computer Group Literature Center Web Site
Ethernet Connectors
Ethernet Connectors
2
Ethernet 1 (J13) and Ethernet 2 (J6) use standard RJ-45 connectors.
Table 2-11. Ethernet Connector Pin Assignments (J13 and
J6)
Pin
Number
Signal Mnemonic Signal Description
1
2
3
4
5
6
7
8
TX+
TX-
RX+
--
Differential transmit lines
Differential transmit lines
Differential receive lines
--
--
--
RX-
--
Differential receive lines
--
--
--
Universal Serial Bus (USB) Connector
USB Port 1 and Port 2 (J14) use a 2 x 4 pin USB connector.
Table 2-12. USB Connector Pin Assignments (J14)
Pin
Number
Signal Mnemonic Signal Description
1
2
3
4
+5V
Current limited USB power
DATA+
DATA-
GND
USB serial communication differential
USB serial communication differential
USB port common
2-21
CPU Modules
Serial Port Connectors
2
COM 1 (Serial Port 1) (J24) and COM 2 (Serial Port 2) (J25) use 2 x 9-pin
D-sub connectors.
Table 2-13. Serial Port Connector Pin Assignments (J24
and J25)
Pin
Signal
Number Mnemonic
Signal Description
1
2
DCD-
RX
data set has detected the data carrier
Receives serial data input from communication
link
3
4
5
6
7
TX
Sends serial output to communication link
data set is ready to establish a communication link
Ground
DTR-
GND
DSR-
RTS-
data set is ready to establish a communication link
indicates to data set that UART is ready to
exchange data
8
9
CTS-
RI-
data set is ready to exchange data
modem has received a telephone ringing signal
Video Connector
The video connector (J23) uses a 15-pin high density D-sub connector.
Table 2-14. Video Connector Pin Assignments (J23)
Pin
Number
Signal Mnemonic Signal Description
1
2
3
RED
Red signal
Green signal
Blue signal
GREEN
BLUE
2-22
Computer Group Literature Center Web Site
Video Connector
Table 2-14. Video Connector Pin Assignments (J23)
2
Pin
Number
Signal Mnemonic Signal Description
4
NC
Not connected
Video return
Video return
Video return
Video return
Not connected
Video return
Not connected
5
DACVSS
DACVSS
DACVSS
DACVSS
NC
6
7
8
9
10
11
12
DACVSS
NC
DDCDAT
Display data channel data signal for
DDC2 support
13
14
15
HSYNC
VSYNC
DDCCLK
Horizontal synchronization
Vertical synchronization
Display data channel clock signal for
DDC2 support
2-23
3CPX8540 Carrier Card
3
Overview
This chapter provides reference information for the CPX8540 carrier card.
The CPV8540 is a 64-bit, 6U, single-width (4HP) CompactPCI® card that
provides front access to PMC modules with both front and rear I/O
connectivity. Rear I/O connections via J3 and J5 allow its use in both
H.110 CT bus. The correct jumper settings and pin-out information is
provided for each connector on the carrier card.
This chapter does not include the system controller/host modules. For
information about the system controller/host, refer to Chapter 2, CPU
Modules.
CPX8540 Carrier Card
The CPX8540 carrier card provides connectivity to a wide variety of
video, ATM, analog, serial, and many other functions. The board supports
one double-width or two single-width PMC mezzanine modules.
Once connected, the PMC modules are accessed via front panel
connections of the carrier card. In addition, I/O lines are brought out to the
carrier card’s rear 2mm pin and socket connectors, allowing rear panel
connections in systems such as the CPX8216T chassis.
Key features of the CPX8540 are:
❏ Supports standard (IEEEP1386.1) PMC mezzanine modules
❏ Holds one double-width or two single-width modules
❏ All PMC I/O brought out to the front panel and to rear connectors
❏ Single CompactPCI load via DEC 21154 bridge
❏ Supports 5.0 or 3.3 Volt PMC modules
❏ Supports Plug and Play
3-1
CPX8540 Carrier Card
Connector Pinouts
The tables in this section provide the connector pinout information for the
rear connectors on the carrier card.
3
Table 3-1. CPCI J3 I/O Connector Pinout
ROW A
ROW B
ROW C
ROW D
ROW E
14
13
12
11
10
9
+3.3V
+3.3V
+3.3V
+5V
+5V
14
13
12
11
10
9
PMC1IO5
PMC1IO10
PMC1IO15
PMC1IO20
PMC1IO25
PMC1IO30
PMC1IO35
PMC1IO40
PMC1IO45
PMC1IO50
PMC1IO55
PMC1IO60
V(I/O)
PMC1IO4
PMC1IO9
PMC1IO14
PMC1IO19
PMC1IO24
PMC1IO29
PMC1IO34
PMC1IO39
PMC1IO44
PMC1IO49
PMC1IO54
PMC1IO59
PMC1IO64
PMC1IO3
PMC1IO8
PMC1IO13
PMC1IO18
PMC1IO23
PMC1IO28
PMC1IO33
PMC1IO38
PMC1IO43
PMC1IO48
PMC1IO53
PMC1IO58
PMC1IO63
PMC1IO2
PMC1IO7
PMC1IO12
PMC1IO17
PMC1IO22
PMC1IO27
PMC1IO32
PMC1IO37
PMC1IO42
PMC1IO47
PMC1IO52
PMC1IO57
PMC1IO62
PMC1IO1
PMC1IO6
PMC1IO11
PMC1IO16
PMC1IO21
PMC1IO26
PMC1IO31
PMC1IO36
PMC1IO41
PMC1IO46
PMC1IO51
PMC1IO56
PMC1IO61
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
NOTE: PMC1IO* signals are those connected to the lower PMC slot, or slot 1.
Table 3-2. CPCI J5 I/O Connector Pinout
ROW A
ROW B
ROW C
ROW D
ROW E
13
12
11
PMC2IO5
PMC2IO10
PMC2IO15
PMC2IO4
PMC2IO9
PMC2IO14
PMC2IO3
PMC2IO8
PMC2IO13
PMC2IO2
PMC2IO7
PMC2IO12
PMC2IO1
PMC2IO6
PMC2IO11
13
12
11
3-4
Computer Group Literature Center Web Site
Connector Pinouts
Table 3-2. CPCI J5 I/O Connector Pinout (continued)
10
9
8
7
6
5
4
3
2
1
PMC2IO20
PMC2IO25
PMC2IO30
PMC2IO35
PMC2IO40
PMC2IO45
PMC2IO50
PMC2IO55
PMC2IO60
V(I/O)
PMC2IO19
PMC2IO24
PMC2IO29
PMC2IO34
PMC2IO39
PMC2IO44
PMC2IO49
PMC2IO54
PMC2IO59
PMC2IO64
PMC2IO18
PMC2IO23
PMC2IO28
PMC2IO33
PMC2IO38
PMC2IO43
PMC2IO48
PMC2IO53
PMC2IO58
PMC2IO63
PMC2IO17
PMC2IO22
PMC2IO27
PMC2IO32
PMC2IO37
PMC2IO42
PMC2IO47
PMC2IO52
PMC2IO57
PMC2IO62
PMC2IO16
PMC2IO21
PMC2IO26
PMC2IO31
PMC2IO36
PMC2IO41
PMC2IO46
PMC2IO51
PMC2IO56
PMC2IO61
10
9
8
7
6
5
4
3
2
1
3
NOTE: PMC2IO* signals are those connected to the upper PMC slot, or slot 2.
Table 3-3. PCI 32-bit Interface Connector P11/J11, P21/J21
Pin#
1
Signal Name
TCK
Signal Name
-12V
Pin #
2
3
GND
INTA#
INTC#
+5V
4
5
INTB#
BUSMODE1#
INTD#
GND
6
7
8
9
PCI-RSVD*
PCI-RSVD*
GND
10
12
14
16
18
20
22
24
11
13
15
17
19
21
23
CLK
GND
GNT#
REQ#
+5V
V (I/O)
AD[28]
AD[25]
AD[31]
AD[27]
GND
3-5
CPX8540 Carrier Card
Table 3-3. PCI 32-bit Interface Connector P11/J11, P21/J21 (continued)
Pin#
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
Signal Name
GND
Signal Name
C/BE[3]#
AD[21]
+5V
Pin #
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
3
AD[22]
AD[19]
V (I/O)
FRAME#
GND
AD[17]
GND
IRDY#
+5V
DEVSEL#
GND
LOCK#
SBO#
SDONE#
PAR
GND
V (I/O)
AD[12]
AD[09]
GND
AD[15]
AD[11]
+5V
C/BE[0]#
AD[05]
GND
AD[06]
AD[04]
V (I/O)
AD[02]
AD[00]
GND
AD[03]
AD[01]
+5V
REQ64#
3-6
Computer Group Literature Center Web Site
Connector Pinouts
Table 3-4. PCI 32-bit Interface Connector P12/J12, P22/J22
Pin#
1
Signal Name
+12V
Signal Name
TRST#
Pin #
2
3
3
TMS
TDO
4
5
TDI
GND
6
7
GND
PCI-RSVD*
PCI-RSVD*
+3.3V
8
9
PCI-RSVD*
BUSMODE2#
RST#
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
BUSMODE3#
BUSMODE4#
GND
+3.3V
PCI-RSVD*
AD[30]
GND
AD[29]
AD[26]
+3.3V
AD[24]
IDSEL
+3.3V
AD[23]
AD[20]
GND
AD[18]
AD[16]
GND
C/BE[2]#
PMC-RSVD
+3.3V
TRDY#
GND
STOP#
PERR#
+3.3V
GND
SERR#
C/BE[1]#
AD[14]
GND
GND
AD[13]
AD[10]
+3.3V
AD[08]
3-7
CPX8540 Carrier Card
Table 3-4. PCI 32-bit Interface Connector P12/J12, P22/J22 (continued)
Pin#
51
Signal Name
AD[07]
Signal Name
PMC-RSVD
PMC-RSVD
GND
Pin #
52
3
53
+3.3V
54
55
PMC-RSVD
PMC-RSVD
GND
56
57
PMC-RSVD
PMC-RSVD
+3.3V
58
59
60
61
ACK64#
GND
62
63
PMC-RSVD
64
Table 3-5. PCI 64 bit PCI extension on PMC Connector J13, J23
Pin#
1
Signal Name
-
Signal Name
GND
Pin #
2
3
GND
C/BE7#
C/BE5#
GND
4
5
C/BE6#
C/BE4#
V(I/O)
AD63
AD61
GND
6
7
8
9
PAR64
AD62
GND
10
12
14
16
18
20
22
24
26
28
30
11
13
15
17
19
21
23
25
27
29
AD60
AD58
GND
AD59
AD57
V(I/O)
AD55
AD53
GND
AD56
AD54
GND
AD52
AD50
AD51
3-8
Computer Group Literature Center Web Site
Connector Pinouts
Table 3-5. PCI 64 bit PCI extension on PMC Connector J13, J23
Pin#
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
Signal Name
AD49
GND
AD47
AD45
V(I/O)
AD43
AD41
GND
AD39
AD37
GND
AD35
AD33
V(I/O)
-
Signal Name
GND
AD48
AD46
GND
AD44
AD42
GND
AD40
AD38
GND
AD36
AD34
GND
AD32
-
Pin #
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
3
-
GND
-
GND
Table 3-6. User-Defined I/O PCI Interface Connector P14/J14, P24/J24
Pin#
Signal Name
1-64
I/O
3-9
4PMC Modules
4
Overview
This chapter provides reference information for the PMC module
supported in the CPX8216 system.
SCSI-2 Controller PMC
The SCSI-2 controller provides fast and wide, single-ended, SCSI-2
(Small Computer System Interface-2) high throughput connectivity for
host carrier boards equipped with PMC (PCI Mezzanine Card)
connections.
The PMC adapter is a plug-and-play device with systems that are
compliant with the PCI Local Bus Specification (revision 2.0).
This controller has the following capabilities:
❏ Single-wide PMC module
❏ 32-bit wide PCI bus support
❏ 128Kb onboard flash memory
❏ 20 Mbps Fast and Wide SCSI-2
❏ Single-ended SCSI-2 interfaces
❏ Front and rear User I/O
❏ 68-pin front panel connector
❏ 64-pin JN4/PN4 rear connector
❏ +3.3V and +5V signaling
❏ Compliance to PCI local bus specification (Revision 2.0)
4-1
PMC Modules
The following figure shows the PMC150 component layout and front
panel.
PN4
PN2
PN1
4
U5
U31
U1
JP40
U15
U14
U13
S1
4118 0702
4-2
Computer Group Literature Center Web Site
Switch Settings
Switch Settings
Use this table as a guideline for configuring the 6-position dip switch on
your PMC.
Table 4-1. PMC Switch Settings
4
Switch
On Function
Use INTA
Off Function
No Use INTA
No Use INTB
No Use INTC
No Use INTD
TERM Disable
Big Endian
Default
On
1
2
3
4
5
6
Use INTB
Off
Use INTC
Off
Use INTD
Off
TERM Enable
Little Endian
On
On
Configure the Big/Little endian mode to your appropriate application for proper
software operation.
Make sure only one INTx line switch is in the ON position.
Enable TERM ENAB is On only if this SCSI controller is physically at the end
of the SCSI bus. If the SCSI controller is in any other position on the bus, TERM
ENAB must be in the OFF mode.
Terminators - The SCSI bus (cable) must be properly terminated at each
end of the bus. The first and last device on the bus should be the only
devices that are set to terminate the bus.
Terminator Power - The SCSI terminators require adequate voltage to
properly terminate the SCSI bus. All SCSI host adapters on the bus should
be set to supply terminator power; and where possible, be located at the
end of the bus and serve as bus terminators.The terminator resistors must
be present on the first and last device on the bus only.
4-3
PMC Modules
Connector Pin Assignments
The table below provides the connector pin assignments for the SCSI
connector on the PMC adapter. The connector uses a 68-pin Euro-style
SCSI cable, either shielded for external or internal cabinet applications or
non-shielded for internal cabinet applications only. For rear I/O, a 64-pin
conductor cable is used. The pin assignments are also provided in the
following table.
4
Table 4-2. PMC Pin Assignments
64-Pin
68-Pin
Connector
Number
Conductor
Cable
Number
68-Pin
Connector
Number
Signal
name
Signal
name
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
1
2
3
4
5
6
7
8
1
3
5
7
2
4
6
8
10
12
14
16
18
20
22
35
36
37
38
39
40
41
42
43
44
45
-DB(12)
-DB(13)
-DB(14)
-DB(15)
-DB(P1)
-DB(0)
-DB(1)
-DB(2)
-DB(3)
-DB(4)
-DB(5)
9
11
13
15
17
19
21
9
10
11
Ground
Ground
Ground
Ground
12
13
14
15
16
17
18
19
20
21
22
23
23
25
27
29
31
33
N/C
N/C
35
24
26
28
30
32
34
N/C
N/C
36
46
47
48
49
50
51
52
53
54
55
56
57
-DB(6)
-DB(7)
-DB(P)
Ground
Ground
TERMPWR
TERMPWR
Reserved
Ground
-ATN
Ground
TERMPWR
TERMPWR
Reserved
Ground
Ground
Ground
37
39
41
38
40
42
Ground
-BSY
Ground
4-4
Computer Group Literature Center Web Site
Connector Pin Assignments
Table 4-2. PMC Pin Assignments (continued)
64-Pin
68-Pin
Connector
Number
Conductor
Cable
Number
68-Pin
Connector
Number
Signal
name
Signal
name
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
24
25
26
27
28
29
30
31
32
33
34
43
45
47
49
51
53
55
57
59
61
63
44
46
48
50
52
54
56
58
60
62
64
58
59
60
61
62
63
64
65
66
67
68
-ACK
-RST
-MSG
-SEL
-C/D
-REQ
-I/O
-DB(8)
-DB(9)
-DB(10)
-DB(11)
4
4-5
5Transition/Bridge Modules
5
Overview
This chapter provides reference information for the various transition and
bridge modules supported in the CPX8216 system.
The correct jumper setting and pin-out information is provided for each
module.
Note
The CPX750HATM is also used with the MCP750HA in some
chassis configurations.
Your system may not contain all boards listed in this chapter, or
it may contain third-party boards that are not listed in this
chapter. For information about third-party boards, refer to the
board manufacturer’s documentation.
Table 5-1. System Components
Topic:
Page:
5-1
CPX750HATM Transition Module
CPV5350TM80 Transition Module
5-29
CPX750HATM Transition Module
The CPX750HATM transition module provides the interface between the
standard Parallel Port, EIDE port, floppy port, keyboard/mouse port, Serial
Port connectors, and the CPX750HA CompactPCI Single Board Computer
module.
5-1
Transition/Bridge Modules
The CPX750HATM transition module includes:
❏ Industry-standard connectors for these interfaces:
–
–
Two asynchronous RJ-45 serial ports (DTE)
Two asynchronous/synchronous HD-26 serial ports, labeled
Serial 3 and Serial 4 on the face plate, which can be configured
for EIA-232-D, EIA-530, V.35, or X.21 interfaces (DCE or
DTE) through the installation of Motorola’s Serial Interface
Modules (SIMs)
5
–
–
One parallel port (IEEE Standard 1284-I compliant)
One combination keyboard/mouse port
❏ Two 60-pin Serial Interface Module (SIM) connectors for
configuring the asynchronous/synchronous serial ports
❏ One 34-pin header for floppy port
❏ Two 64-pin headers for PMCIO (1 ground pin provided with each
PMCIO signal)
Figure 5-1 on page 5-3 shows the CPX750HATM transition module
component layout and the front panel. See Connectors on page 5-4 for a
list of the front panel port connectors.
Serial Ports 3 and 4 Default Configuration
The CPX750HATM serial ports 3 and 4 are factory configured as follows:
❏ Serial Port 3: DTE (with SIMM 01-W3877B01A installed)
❏ Serial Port 4: DCE (with SIMM 01-W3876B01A installed)
5-2
Computer Group Literature Center Web Site
Transition/Bridge Modules
Serial Port Interface Jumper (J8 and J9)
J8 (for serial port 3) and J9 (for serial port 4) set the serial ports to either
DTE or DCE communication. For more information about configuring the
serial port, see Installing the Serial Interface Modules on page 5-16.
1
2
3
1
2
3
5
DCE
DTE
11650 9610
Figure 5-2. Serial Port Interface Jumper (J9) Settings
Connectors
Refer to Figure 5-1 on page 5-3 for the location of the following connectors
Backplane Connectors (J3/J4/J5)
I/O signals and power are provided to the CPX750HATM from the
CPX750 through CompactPCI connectors J3 and J5. The J4 connector is
for physical alignment purposes only and has no functional pin
connections or assignments.
Connector J3 is a 95-pin AMP Z-pack 2mm hard metric type B connector.
This connector routes the I/O signals for the PMC I/O and serial channels.
The pin assignments for J3 are as follows (outer row F is assigned and used
as ground pins but is not shown in the table):
Connector J4 is a 110-pin 2mm hard metric type A connector. This
connector is placed on the board for alignment purposes only. The keying
tabs on the type A connector assist with alignment of pins in the backplane
connector during insertion of the boards. No signals are connected to J4
except the row F ground pins.
Connector J5 is a 110-pin AMP Z-pack 2mm hard metric type B connector.
This connector routes the I/O signals for the IDE (secondary port), the
keyboard, the mouse, the two USB ports, and the printer ports. The pin
5-4
Computer Group Literature Center Web Site
Connectors
assignments for J5 are as follows (the outer row F is assigned and used as
ground pins but is not shown in the table):
Table 5-2 and Table 5-3 provide the pin assignments and signal mnemonics
for connectors J3 and J5 (J4 is not shown)
Table 5-2. J3 User I/O Connector
ROW A
19 Reserved
18 Reserved
17 Reserved
16 Reserved
15 Reserved
14 +3.3V
ROW B
+12V
ROW C
-12V
ROW D
RXD3
GND
ROW E
RXD4
RXC4
5
19
18
17
16
15
14
13
12
GND
RXC3
MXCLK
GND
MXDI
MXSYNC_L MXDO
TXC3
GND
TXC4
Reserved
+3.3V
Reserved
+3.3V
TXD3
+5V
TXD4
+5V
13 PMCIO5
PMCIO4
PMCIO3
PMCIO8
PMCIO2
PMCIO7
PMCIO1
PMCIO6
12 PMCIO10 PMCIO9
11 PMCIO15 PMCIO14 PMCIO13 PMCIO12
PMCIO11 11
10 PMCIO20 PMCIO19 PMCIO18 PMCIO17
PMCIO16 10
9
8
7
6
5
4
3
2
1
PMCIO25 PMCIO24 PMCIO23 PMCIO22
PMCIO30 PMCIO29 PMCIO28 PMCIO27
PMCIO35 PMCIO34 PMCIO33 PMCIO32
PMCIO40 PMCIO39 PMCIO38 PMCIO37
PMCIO45 PMCIO44 PMCIO43 PMCIO42
PMCIO50 PMCIO49 PMCIO48 PMCIO47
PMCIO55 PMCIO54 PMCIO53 PMCIO52
PMCIO60 PMCIO59 PMCIO58 PMCIO57
PMCIO21
PMCIO26
PMCIO31
PMCIO36
PMCIO41
PMCIO46
PMCIO51
PMCIO56
PMCIO61
9
8
7
6
5
4
3
2
1
VIO
PMCIO64 PMCIO63 PMCIO62
Row F is assigned and used as ground pins but is not shown in the table
5-5
Transition/Bridge Modules
Table 5-3. J5 User I/O Connector
ROW A
Reserved
KBDDAT
Reserved
STB_L
AFD_L
PD2
ROW B
ROW C
Reserved
KBAUXVCC
Reserved
UVCC0
Reserved
PD1
ROW D
+5V
ROW E
SPKROC_L
AUXCLK
Reserved
Reserved
UVCC1
PD0
22
21
20
19
18
17
16
15
14
13
12
11
10
9
GND
22
21
20
19
18
17
16
15
14
13
12
11
10
9
KBDCLK
Reserved
GND
AUXDAT
GND
Reserved
GND
Reserved
INIT_L
PD5
5
ERR_L
PD3
PD6
PD4
SLIN_L
PD7
SLCT
PE
BUSY
RIa
ACK_L
GND
RTSa
CTSa
DTRa
DCDa
+5V
RXDa
DSRa
TXDa
RTSb
CTSb
RIb
+5V
DTRb
DCDb
GND
RXDb
DSRb
TXDb
TR0_L
MTR1_L
Reserved
CS1FX_L
Reserved
DMARQ
DD14
WPROT_L
DIR_L
INDEX_L
CS3FX_L
GND
RDATA_L
STEP_L
MTR0_L
DA1
HDSEL_L
WDATA_L
DS1_L
Reserved
DA0
DSKCHG_L
WGATE_L
DS0_L
Reserved
DA2
8
8
7
7
6
Reserved
DIOW_L
GND
6
5
IORDY
DD0
DMACK_L
DD15
DIOR_L
INTRQ
DD1
5
4
4
3
DD3
DD12
DD2
DD13
3
2
DD9
DD5
DD10
DD4
DD11
2
1
RESET_L
DRESET_L
DD7
DD8
DD6
1
Row F is assigned and used as ground pins but is not shown in the table
Asynchronous Serial Port Connectors (J10 and J11)
The interface for the asynchronous serial ports, COM1 and COM2, is
provided with two RJ-45 connectors, J11 and J10. The connector shields
5-6
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Connectors
for these ports are tied to chassis ground. The pin assignments and signal
mnemonics for these connectors are listed in the next table.
Table 5-4. COM1 (J11) and COM2 (J10)
Pin
1
Signal
DCD
RTS
2
5
3
GND
TXD
RXD
GND
CTS
4
5
6
7
8
DTR
Asynchronous/Synchronous Serial Port Connectors (J6 and J24)
provided by two HD-26 connectors, J6 and J24. The connector shields for
these ports are tied to chassis ground.
The pin assignments and signal mnemonics for Serial Port 3 are listed in
Table 5-5, and the pin assignments and signal mnemonics for Serial Port 4
are listed in Table 5-6.
Table 5-5. Serial Port 3 (J6)
Pin
1
Signal
No Connect
TXD3
Signal
Pin
14
15
16
17
18
SP3_P14
TXCI3
SP3_P16
RXCI3
LLB3
2
3
RXD3
RTS3
4
5
CTS3
5-7
Transition/Bridge Modules
Table 5-5. Serial Port 3 (J6) (continued)
Pin
6
Signal
Signal
SP3_P19
DTR3
Pin
19
20
21
22
23
24
25
26
DSR3
7
GND
8
DCD3
RLB3
9
SP3_P9
SP3_P10
SP3_P11
SP3_P12
SP3_P13
RI3
10
11
12
13
SP3_P23
TXCO3
TM3
5
SP3_P26
Table 5-6. Serial Port 4 (J24)
Pin
1
Signal
Signal
SP4_P14
TXCI4
SP4_P16
RXCI4
LLB4
Pin
14
15
16
17
18
19
20
21
22
23
24
25
26
No Connect
TXD4
2
3
RXD4
4
RTS4
5
CTS4
6
DSR4
SP4_P19
DTR4
7
GND
8
DCD4
RLB4
9
SP4_P9
SP4_P10
SP4_P11
SP4_P12
SP4_P13
RI4
10
11
12
13
SP4_P23
TXCO4
TM4
SP4_P26
5-8
Computer Group Literature Center Web Site
Connectors
Parallel I/O Port Connector (J7)
The interface for the parallel port is a standard IEEE P1284-C, 36-pin
connector, J7. The functionality of each signal depends on the mode of
operation of this bidirectional Parallel Peripheral Interface. Refer to the
IEEE P1284 D2.00 Standard for a complete description of each signal
function. The connector shield is tied to chassis ground.
The pin assignments and signal mnemonics for this connector are listed in
the next table.
5
Table 5-7. Parallel I/O Connector (J7)
Pin
1
Signal
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
No Connect
Pin
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PRBSY
PRSEL
PRACK_
PRFAULT_
PRPE
2
3
4
5
6
PRD0
7
PRD1
8
PRD2
9
PRD3
10
11
12
13
14
15
16
17
18
PRD4
PRD5
PRD6
PRD7
PRINIT_
PRSTB_
SELIN_
AUTOFD_
Pull-up
5-9
Transition/Bridge Modules
Keyboard/Mouse Connector (J16)
The Keyboard/Mouse interface is provided by a 6-pin circular DIN
connector. To use the keyboard function only, a keyboard may be
connected directly to this connector. To use both the keyboard and the
mouse functions, use the Y-adapter cable provided with the
CPX750HATM. Refer to the following table for pin assignments.
Table 5-8. Keyboard/Mouse Connector (J16)
5
Pin
1
Signal
KBD DAT
MSDAT
GND
2
3
4
+5Vdc Fused
KBDCLK
MSCLK
5
6
USB Connectors (J19 and J18)
The standard version of the CPX750 routes the USB port signals only to
the CPX750 front panel USB connectors J18 and J17. Therefore the USB
port connectors (J19 and J18) on the CPX750HATM are not active. The
USB ports can be routed to the CPX750HATM using an alternate build
option of the CPX750. Contact your local Motorola Sales office for details.
5-10
Computer Group Literature Center Web Site
Connectors
EIDE Connector (J15)
The CPX750HATM provides a 40-pin header (J15) to interface to the
CPX750 secondary EIDE port. The pin assignments and signal mnemonics
for this connector are listed in the next table.
Table 5-9. EIDE Connector (J15)
Pin
1
Signal
DRESET_L
DD7
Signal
GND
Pin
2
5
3
DD8
4
5
DD6
DD9
6
7
DD5
DD10
8
9
DD4
DD11
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
DD3
DD12
DD2
DD13
DD1
DD14
DD0
DD15
GND
No Connect
GND
DMARQ
DIOW_L
DIOR_L
IORDY
DMACK_L
INTRQ
DA1
GND
GND
No Connect
GND
No Connect
No Connect
DA2
DA0
CS1FX_L
No Connect
CS3FX_L
GND
5-11
Transition/Bridge Modules
Floppy Port Connector (J17)
The CPX750HATM provides a 34-pin header (J17) to interface to a floppy
disk drive. The pin assignments and signal mnemonics for this connector
are listed in the next table.
Table 5-10. Floppy Connector (J17)
Pin
1
Signal
GND
Signal
Pin
2
5
No Connect
No Connect
No Connect
INDEX_L
MTR0_L
DS1_L
3
GND
4
5
GND
6
7
No Connect
GND
8
9
10
12
14
16
18
20
22
24
26
28
30
32
34
11
13
15
17
19
21
23
25
27
29
31
33
GND
No Connect
GND
DS0_L
MTR1_L
DIR_L
No Connect
GND
STEP_L
GND
WDATA_L
WGATE_L
TR0_L
GND
GND
GND
WPROT_L
RDATA_L
HDSEL_L
DSKCHG_L
GND
GND
GND
+5Vdc Power Connector (J14)
The CPX750HATM has a 4-pin header that can be used to provide +5Vdc
power to offboard devices. This power is derived from the fused +5Vdc
power on the CPX750. Any external device powered from this connector
5-12
Computer Group Literature Center Web Site
Connectors
must not draw more than 200mA. The pin assignments are listed in the
following table.
Table 5-11. +5Vdc Power Connector (J14)
Pin
1
Signal
+5Vdc
GND
2
5
3
GND
4
No Connect
Speaker Output Connector (J13)
The 2-pin header (J13) provides connection to an external speaker from the
CPX750 PCB Counter 2 output. The speaker driver, located on the
CPX750 PCB, consists of a 500 mA (max) current sink transistor in series
with a 33 ohm resistor. The pin assignments are listed in the following
table.
Table 5-12. Speaker Output Connector (J13)
Pin
1
Signal
GND
2
SPKROC_L
5-13
Transition/Bridge Modules
PMC I/O Connectors
The PMC I/O connectors consist of two 64-pin header connectors J2 and
J21. The pin assignments and signal mnemonics for these connectors are
listed below.
Table 5-13. PMC I/O Connector (J2)
Pin
1
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Signal
Pin
2
5
PMCIO1
PMCIO2
PMCIO3
PMCIO4
PMCIO5
PMCIO6
PMCIO7
PMCIO8
PMCIO9
PMCIO10
PMCIO11
PMCIO12
PMCIO13
PMCIO14
PMCIO15
PMCIO16
PMCIO17
PMCIO18
PMCIO19
PMCIO20
PMCIO21
3
4
5
6
7
8
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
5-14
Computer Group Literature Center Web Site
Connectors
Table 5-13. PMC I/O Connector (J2) (continued)
Pin
43
45
47
49
51
53
55
57
59
61
63
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Signal
Pin
44
46
48
50
52
54
56
58
60
62
64
PMCIO22
PMCIO23
PMCIO24
PMCIO25
PMCIO26
PMCIO27
PMCIO28
PMCIO29
PMCIO30
PMCIO31
PMCIO32
5
Table 5-14. PMC I/O Connector (J21)
Pin
1
Signal
Signal
Pin
2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PMCIO33
PMCIO34
PMCIO35
PMCIO36
PMCIO37
PMCIO38
PMCIO39
PMCIO40
PMCIO41
PMCIO42
PMCIO43
3
4
5
6
7
8
9
10
12
14
16
18
20
22
11
13
15
17
19
21
5-15
Transition/Bridge Modules
Table 5-14. PMC I/O Connector (J21) (continued)
Pin
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Signal
Pin
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
PMCIO44
PMCIO45
PMCIO46
PMCIO47
PMCIO48
PMCIO49
PMCIO50
PMCIO51
PMCIO52
PMCIO53
PMCIO54
PMCIO55
PMCIO56
PMCIO57
PMCIO58
PMCIO59
PMCIO60
PMCIO61
PMCIO62
PMCIO63
PMCIO64
5
Installing the Serial Interface Modules
Configure the serial ports 3 and 4 for the required interface by installing
the appropriate SIM.
5-16
Computer Group Literature Center Web Site
Installing the Serial Interface Modules
Prior to installing the SIMs, set the jumpers on header J8 (for Serial Port
3) and header J9 (for Serial Port 4) for either DCE or DTE. Set the jumper
to position 1-2 if the SIM is for a DTE interface. Set the jumper to position
2-3 if the SIM is for a DCE interface.
1
2
3
1
2
3
DCE
DTE
5
You must set the jumpers and install the SIMs prior to installing the
CPX750HATM transition module in the system chassis.
The SIMs plug into connector J23 (for Serial Port 3) or J1 (for Serial Port
4) on the CPX750HATM transition module.
Install the SIMs on the CPX750HATM transition module per the following
procedure:
1. Align the SIM so that P1 on the SIM lines up with the appropriate SIM
connector (J23 for Serial Port 3 or J1 for Serial Port 4) on the transition
module. Note the position of the alignment key on P1. See the next
figure.
2. Place the SIM onto the transition module SIM connector, making sure
that the mounting holes also line up with the standoffs on the transition
module.
Mounting Hole
P1
Alignment
Key
11637 9610
Mounting Hole
5-17
Transition/Bridge Modules
3. Gently press the top of the SIM to seat it on the transition module SIM
connector. If the SIM does not seat with gentle pressure, re-check the
alignment of the connectors.
Note
Do not force the SIM onto the transition module.
4. Secure the SIM to the transition module standoffs with the two
Phillips-head screws provided. Do not over tighten the screws.
5
Port Configuration Diagrams
asynchronous serial ports.
COM1 and COM2 Asynchronous Serial Ports
The asynchronous serial port (COM1 and COM2) configuration is shown
in Figure 5-3 on page 5-19.
5-18
Computer Group Literature Center Web Site
Port Configuration Diagrams
9
1
6
8
2
COM1
J15
(Front
Panel)
4
7
3
5
5
TXD
4
2
SOUT1
RTS1#
DTR1#
RTS
DTR
8
5
7
RXD
CTS
SIN1
CTS1#
COM1
(J11)
DSR1#
DCD
GND
1
DCD1#
RI1#
3
6
PC87307
J5
TXD
RTS
4
2
SOUT2
RTS2#
DTR2#
DTR
8
5
7
RXD
CTS
SIN2
CTS2#
COM2
(J10)
DSR2#
DCD
GND
1
DCD2
RI2#
3
6
CPX750HATM
Transition Module
CPX750
2105 9710
Figure 5-3. DTE Port Configuration (COM1 and COM2)
5-19
Port Configuration Diagrams
Z85230 SCC
TXD
DB25
RXD
3
CTS#
5
RTS#
TXD
2
RXD
CTS#
DCD#
RTS#
4
5
DTR#
20
TXC
15
3
2
1
TRXC
RTXC
RXC#
17
J8, J9
ETXC
24
J3/MX
Z8536 CIO
DTR#
DCD#
8
TM#
25
LLB#
RLB#
RI#
22
DSR#
6
DSR#
RI#
RL
21
LL
18
TM#
GND
7
CPX750HATM
Transition Module
CPX750
EIA-232-D DCE SIM
2106 971
Figure 5-4. EIA-232-D DCE Port Configuration (Ports 3 and 4)
5-21
Transition/Bridge Modules
Z85230 SCC
TXD
DB25
2
TXD
RTS#
RXD
RTS#
4
3
RXD
CTS#
DCD#
CTS#
DCD#
5
5
8
ETXC
TXC#
3
24
15
17
2
1
TRXC
RTXC
J8, J9
RXC
J3/MX
Z8536 CIO
DTR#
DTR
LL
20
18
21
6
LLB#
RLB#
RL
DSR#
RI#
DSR#
RI#
22
25
7
TM#
GND#
TM#
CPX750HATM
Transition Module
CPX750
EIA-232-D DTE SIM
2107 971
Figure 5-5. EIA-232-D DTE Port Configuration (Ports 3 and 4)
5-22
Computer Group Literature Center Web Site
Port Configuration Diagrams
Z85230 SCC
DB25
RXDB
16
RXDA
3
TXD
CTSB
13
5
RTS_
CTSA
TXDB
14
+
-
RXD
CTS_
DCD_
TXDA
2
RTSB
19
+
-
RTSA
4
5
DTRB
23
+
-
DTRA
20
TXCB
12
3
TXCA
15
2
1
TRXC
RTXC
RXCB
9
RXCA
17
J8, J9
ETXCB
11
+
-
ETXCA
24
J3/MX
DCDB
10
Z8536 CIO
DTR_
DCDA
8
TM
25
LL_
RI
RL_
26
DSRB
22
DSRA
6
DSR_
RI_
-V
-V
+
-
RL
21
+
-
LL
18
TM_
GND
7
CPX750HATM
Transition Module
CPX750
EIA-530-D DCE SIM
2108 9710
Figure 5-6. EIA-530 DCE Port Configuration (Ports 3 and 4)
5-23
Transition/Bridge Modules
Z85230 SCC
DB25
TXDB
TXDA
14
2
TXD
RTSB
RTSA
19
4
RTS_
RXDB
RXDA
16
3
+
-
RXD
CTS_
DCD_
CTSB
CTSA
13
5
+
-
5
DTRB
DTRA
10
8
+
-
ETXCB
ETXCA
3
11
24
2
1
TRXC
RTXC
TXCB
TXCA
12
15
+
-
J8, J9
RXCB
9
17
+
-
RTXCA
J3/MX
DTRB
DTRA
Z8536 CIO
DTR_
23
20
LL
LL_
18
21
RL
RL_
DSRB
DSRA
22
6
DSR_
RI_
-V
+
-
(R)
26
-V
+
-
TM
TM_
25
7
GND
CPX750HATM
Transition Module
CPX750
EIA-530-D DTE SIM
2109 9710
Figure 5-7. EIA-530 DTE Port Configuration (Ports 3 and 4)
5-24
Computer Group Literature Center Web Site
Port Configuration Diagrams
Z85230 SCC
DB25
Term
Term
RXDB
16
RXDA
3
TXD
CTS
5
RTS_
TXDB
14
2
+
-
RXD
DCD_
CTS_
TXDA
RTS
4
5
DTR
20
Term
Term
Term
TXCB
12
3
TXCA
15
TRXC
RTXC
2
1
RXCB
RXCA
9
17
J3/MX
J8, J9
ETXCB
ETXCA
11
24
+
-
Z8536 CIO
DCD
TM
8
25
22
DTR_
LL_
RI
RL_
DSR
6
21
18
7
DSR_
RI_
RL
LL
TM_
GND
V.35-DCE SIM
CPX750HATM
Transition Module
CPX750
Term = V.35 Termination Network
2110 971
Figure 5-8. V.35-DCE Port Configuration (Ports 3 and 4)
5-25
Transition/Bridge Modules
Z85230 SCC
DB25
Term
Term
TXDB
TXDA
14
2
TXD
RTS
RTS_
4
RXDB
RXDA
16
3
+
-
RXD
CTS_
DCD_
CTS
DCD
5
5
8
Term
ETXCB
ETXCA
3
11
24
TRXC
RTXC
2
1
Term
Term
TXCB
TXCA
12
15
+
-
J8, J9
RXCB
RXCA
9
17
+
-
Z8536 CIO
J3/MX
DTR
LL
20
18
21
6
DTR_
LL_
RL_
RL
DSR
RI
DSR_
RI_
22
TM
25
7
TM_
GND
V.35-DCE SIM
CPX750HATM
Transition Module
CPX750
Term = V.35 Termination Network
2111 971
Figure 5-9. V.35-DTE Port Configuration (Ports 3 and 4)
5-26
Computer Group Literature Center Web Site
Port Configuration Diagrams
Z85230 SCC
DB25
RXDB
16
RXDA
TXD
3
RTS_
TXDB
+
-
14
2
RXD
CTS_
DCD_
TXDA
CTRLB
CTRLA
+
-
11
24
5
3
SETB
12
15
2
1
TRXC
RTXC
SETA
+V
J3/MX
J8, J9
Z8536 CIO
INDB
INDA
9
17
DTR_
NC
NC
LL_
RL_
DSR_
RI_
+V
+V
TM_
GND
7
X.21 DCE SIM
CPX750HATM
Transition Module
CPX750
2112 971
Figure 5-10. X.21-DCE Port Configuration (Ports 3 and 4)
5-27
Transition/Bridge Modules
Z85230 SCC
DB25
TXDB
TXDA
14
2
TXD
CTRLB
CTRLA
11
24
RTS_
RXDB
RXDA
16
3
+
-
RXD
CTS_
DCD_
5
INDB
9
17
+
-
INDLA
3
2
1
TRXC
NC
SETB
SETA
12
15
+
-
J3/MX
J8, J9
RTXC
Z8536 CIO
DTR_
NC
NC
LL_
RL_
DSR_
RI_
+V
+V
TM_
GND
7
X.21 DTE SIM
CPX750HATM
Transition Module
CPX750
Figure 5-11. X.21-DTE Port Configuration (Ports 3 and 4)
5-28
Computer Group Literature Center Web Site
CPV5350TM80 Transition Module
CPV5350TM80 Transition Module
The CPV5350TM80 transition module provides rear I/O connectivity for
the CPV5350 CPU controller module.
The CPV5350TM80 provides rear panel connections for:
❏ Two Ethernet ports
❏ Two serial ports
5
❏ Two Universal Serial Bus ports
❏ One parallel port
❏ One video port
❏ One keyboard/mouse port
❏ On-board headers for keyboard/mouse/power LED
❏ On-board headers for a speaker and reset
❏ On-board EIDE header (supports up to four devices), floppy
drives,
When the identical function is available through the CPV5350 controller’s
front panel and the CPV5350TM80 transition module’s panel, you can use
either the front or the rear connector, but not both.
5-29
Transition/Bridge Modules
The next figure shows the CPV5350TM80 front panel and on-board
connectors and jumpers.
J14
J13
J6
1
J19
J12
E
T
H
E
5
R
N
J18
E
T
2
T2
1
J21
J9
T1
J5
2
J10
V
I
D
E
O
J16
J1
GND
VCC
SMCLK
SMDATA
SMALT
GND
BTI
BYPASS
VCC
GND
GND
INTRUDER
PBRRESET
SCSI
GND
VCC
VCC
VCC
VCC
VCC
P
A
R
A
PIDE
SIDE
ALARM
SPKR
J20
J2
L
L
E
L
J3
J4
J7
CPV5350TM
2493 9902
5-30
Computer Group Literature Center Web Site
Connectors
Connectors
The following table lists the connectors available to support devices on the
CPV5350. The figure on the preceding page shows the location of the
connectors described in the table.
Connector
Description
J1
J2
SM Bus and LM78 connector
EIDE indicator lights, push-button reset, alarm indicator,
and speaker connector
5
J3
Fan tachometer connector
Fan tachometer connector
EIDE connector
Keyboard/Mouse, power LED connector
Miscellaneous Power
Floppy Connector
COM 2
J4
J5
J6
J7
J9
J10
J12
J13
J14
J16
J18
J19
J20
J21
USB port
Ethernet 1
Keyboard/Mouse
Video Connector
Ethernet 2
USB Port
Parallel port connector
COM1
5-31
Transition/Bridge Modules
Keyboard/Mouse PS2 Connector
The keyboard/mouse connector (J14) uses a 6-pin, female PS/2 connector.
Table 5-15. Keyboard/Mouse P/S2 Connector Pin
Assignments (J14)
Pin
1
Signal Mnemonic Signal Description
KBDDAT
AUXDAT
GND
Keyboard Data
5
2
Auxiliary Data
3
Ground
4
KBDVCC
KBDCLK
AUXCLK
CGND
Keyboard Power (current limited to .75 Amp)
Keyboard Clock
5
6
Auxiliary Clock
7
Common Ground
6
4
5
3
2
1
7
2489 9902
Figure 5-12. Keyboard/Mouse Connector Diagram
5-32
Computer Group Literature Center Web Site
Connectors
Ethernet Connectors
Ethernet 1 (J13) and Ethernet 2 (J18) use standard RJ-45 connectors.
Table 5-16. Ethernet Connector Pin Assignments (J13 and
J18)
Pin
1
Signal Mnemonic Signal Description
TX+
TX-
RX+
--
Differential transmit lines
5
2
Differential transmit lines
3
Differential receive lines
4
--
5
--
--
6
RX-
--
Differential receive lines
7
--
--
8
--
Serial Port Connectors
COM 1 (Serial Port 1, J21) and COM 2 (Serial Port 2, J10) use 2 x 9-pin
D-sub connectors.
Table 5-17. Serial Port Connector Pin Assignments
(J21 and J10)
Signal
Pin Mnemonic
Signal Description
1
2
3
4
5
DCD-
RX
Data set has detected the data carrier
Receives serial data input from communication link
Sends serial output to communication link
Data set is ready to establish a communication link
Ground
TX
DTR-
GND
5-33
Transition/Bridge Modules
Table 5-17. Serial Port Connector Pin Assignments
(J21 and J10) (continued)
Signal
Pin Mnemonic
Signal Description
6
7
8
9
DSR-
RTS-
CTS-
RI-
Data set is ready to establish a communication link
Indicates to data set that UART is ready to exchange data
Data set is ready to exchange data
5
Modem has received a telephone ringing signal
Video Connector
The video connector (J16) uses a 15-pin high density D-sub connector.
Table 5-18. Video Connector Pin Assignments (J16)
Signal
Pin
1
Mnemonic
Signal Description
Red signal
RED
2
GREEN
BLUE
Green signal
Blue signal
3
4
NC
Not connected
Video return
Video return
Video return
Video return
Not connected
Video return
Not connected
5
DACVSS
DACVSS
DACVSS
DACVSS
NC
6
7
8
9
10
11
DACVSS
NC
5-34
Computer Group Literature Center Web Site
Connectors
Table 5-18. Video Connector Pin Assignments (J16)
Signal
Pin
12
13
14
15
Mnemonic
Signal Description
DDCDAT
HSYNC
Display data channel data signal for DDC2 support
Horizontal synchronization
VSYNC
Vertical synchronization
DDCCLK
Display data channel clock signal for DDC2 support
5
Parallel Port Connector (J20)
The parallel port (J20) uses a 25-pin, D-sub connector.
Table 5-19. Parallel Connector Pin Assignments (J20)
Pin
Signal Mnemonic Signal Description
1
STROBE-
D0
Data at parallel port is valid
2
Parallel data lines
3
D1
Parallel data line
4
D2
Parallel data line
5
D3
Parallel data line
6
D4
Parallel data line
7
D5
Parallel data line
8
D6
Parallel data line
9
D7
Parallel data line
10
11
12
13
14
ACK-
BUSY
PE
Acknowledge data retrieval
Printer cannot accept more data
Printer out of paper
Set high when selected
Causes printer to add a line feed
SELECT
AFD-
5-35
Transition/Bridge Modules
Table 5-19. Parallel Connector Pin Assignments (J20)
Pin
15
16
17
18
19
20
21
22
23
24
25
Signal Mnemonic Signal Description
ERR-
INIT-
SLIN-
GND
GND
GND
GND
GND
GND
GND
GND
Set low when an error is detected
Initializes the printer
Selects the printer
Ground
5
Ground
Ground
Ground
Ground
Ground
Ground
Ground
EIDE Headers (J5)
Table 5-20. EIDE Header (J5) Pin Assignments
Signal
Pin Mnemonic
Signal
Description
Signal
Mnemonic
Signal
Description
Pin
1
3
5
7
Reset
DD7
DD6
DD5
Reset signal
to drive
2
GND
DD8
DD9
DD10
Ground
Drive data
line
4
6
8
Drive data
line
Drive data
line
Drive data
line
Drive data
line
Drive data
line
5-36
Computer Group Literature Center Web Site
Connectors
Table 5-20. EIDE Header (J5) Pin Assignments
Signal
Signal
Signal
Signal
Pin Mnemonic
Description
Pin
Mnemonic
Description
9
DD4
DD3
DD2
DD1
DD0
Drive data
line
10
DD11
DD12
DD13
DD14
DD15
Drive data
line
11
13
15
17
Drive data
line
12
14
16
18
Drive data
line
Drive data
line
Drive data
line
5
Drive data
line
Drive data
line
Drive data
line
Drive data
line
19
21
GND
Ground
20
22
-
-
DMARQ
Drive DMA
request
GND
Ground
23
25
27
29
31
IOW
Drive I/O
write
24
26
GND
Ground
IOR
Drive I/O
read
GND
Ground
IORDY
DMACK
INTRQ
Drive is ready 28
for I/O cycles
CSEL
GND
Cable select
Ground
Drive DMA
acknowledge
30
Drive
32
IOCS16
16 bit
interrupt
request
register is
decoded
5-37
Transition/Bridge Modules
Table 5-20. EIDE Header (J5) Pin Assignments
Signal
Pin Mnemonic
Signal
Description
Signal
Mnemonic
Signal
Description
Pin
33
35
37
DA1
DA0
CS1
Drive register 34
and data port
address lines
PDIAG
Output from
drive 1 and
monitored
by drive 0
Drive register 36
and data port
address lines
DA2
Drive
register and
data port
5
address lines
Chip select
drive 0, also
command
register block
select
38
40
CS3
Chip select
drive 1, also
command
register
block select
39
DASP
Drive active
slave present
GND
Ground
Floppy Header (J9)
Table 5-21. Floppy Header (J9) Pin Assignments
Signal
Signal
Signal
Signal
Pin
Mnemonic Description Pin
Mnemonic
Description
1
GND
Drive
common
2
DRVDENS0 Disk density
select
communication
3
5
-
-
4
6
-
-
GND
Drive
common
DRVDENS1 Disk density
select
communication
7
GND
Drive
common
8
INDEX
Beginning of a
track
5-38
Computer Group Literature Center Web Site
Connectors
Table 5-21. Floppy Header (J9) Pin Assignments
Signal
Signal
Signal
Signal
Pin
Mnemonic Description Pin
Mnemonic
Description
9
GND
GND
GND
GND
GND
Drive
common
10
12
14
16
18
MTR0
DS1
Motor enable
output
11
13
15
17
Drive
common
Drive select 1
Drive
common
DS0
Drive select 0
5
Drive
common
MTR1
DIR
Motor enable
output
Drive
Controls
common
direction of the
floppy disk drive
head during seek
operation
19
GND
Drive
common
20
STEP
Supplies step
pulses to move
head during seek
operations
21
23
GND
GND
Drive
common
22
24
WDATA
WGATE
Writes serial data
to disk drive
Drive
common
Enables head of
disk drive to
write to disk
25
GND
Drive
common
26
TR0
Head of floppy
disk drive is at
track 0
5-39
Transition/Bridge Modules
Table 5-21. Floppy Header (J9) Pin Assignments
Signal
Signal
Signal
Signal
Pin
Mnemonic Description Pin
Mnemonic
Description
27
GND
GND
GND
Drive
common
28
30
32
WPROT
RDATA
HDSEL
Disk is write
protected
29
31
Drive
common
Raw read data
from disk drive
Drive
common
Determines the
side of the floppy
disk being
5
accessed
33
GND
Drive
common
34
DSKCHG
Notifies disk
drive controller
that the drive
door is open
Keyboard/Mouse/Power LED Header (J6)
The table below shows the pin assignments for the keyboard, mouse, and
power LED header.
Table 5-22. Keyboard/Mouse/Power LED Header (J6) Pin
Assignments
Signal
Signal
Signal
Signal
Pin
Mnemonic Description
Pin
Mnemonic
Description
1
PWRLED
GND
Power LED
Indicator
2
KBDCLK
Clock for
keyboard
3
Ground
4
KBDDAT
Data line for
keyboard
5-40
Computer Group Literature Center Web Site
Connectors
Table 5-22. Keyboard/Mouse/Power LED Header (J6) Pin
Assignments (continued)
Signal
Signal
Signal
Signal
Pin
Mnemonic Description
Pin
Mnemonic
Description
5
GND
Ground
6
AUXDAT
Data line for
mouse
7
9
-
-
8
GND
Ground
GND
Ground
10
KBDVCC
Keyboard
power (.75A)
5
11
-
-
12
AUXCLK
Clock for
mouse
USB Headers (J12 and J19)
Table 5-23. USB Headers (J12 and J19) Pin Assignments
Pin
1
Signal Mnemonic Signal Description
+5V
Current limited USB power
2
DATA-
DATA+
GND
USB serial communications differential pair
USB serial communications differential pair
USB Port common
3
4
5-41
Transition/Bridge Modules
SM Bus and LM78 Header (J1)
Table 5-24. SM Bus and LM78 Header (J1)Pin
Assignments
Signal
Mnemonic
Signal
Description Pin
Signal
Mnemonic
Signal
Description
Pin
5
1
OPEN-
Chassis
intrusion
signal
2
GND
Ground
3
GND
Ground
4
SMBALERT-
SM bus
interrupt
signal
5
7
9
GND
Ground
6
SMBDATA
SMBCLK
VCC
SM bus data
strobe signal
VCC
SM bus
power
8
SM bus
clock signal
BYPASS
Power
switch
10
SM bus
power
bypass signal
11
BT1-
Board
12
GND
Ground
temperature
interrupt
signal
5-42
Computer Group Literature Center Web Site
Connectors
Fan Tachometer Headers (J3 and J4)
Refer to the next table for pin assignments and signal descriptions for the
Fan Tachometer headers (J3 and J4) on the CPV5350 Transition Module.
Table 5-25. Fan Tachometer Header (J3 and J4) Pin
Assignments
Pin
1
Signal Mnemonic
VCC
Signal Description
SM bus power
5
2
TACH
Tachometer input for fan
Ground
3
GND
4
+12V
12 volt power
Indicator LED/Miscellaneous Header (J2)
Table 5-26. Indicator LED/Miscellaneous Header (J2) Pin
Assignments
Signal
Signal
Signal
Pin Mnemonic Signal Description Pin Mnemonic Description
1
3
VCC
VCC
+5V power(limited
to .75A total)
2
4
SPEAKER Speaker
output
+5V power(limited
to .75A total)
ALARM
Alarm
indicator
LED
5-43
Transition/Bridge Modules
Table 5-26. Indicator LED/Miscellaneous Header (J2) Pin
Assignments (continued)
Signal
Signal
Signal
Pin Mnemonic Signal Description Pin Mnemonic Description
5
VCC
+5V power (limited
to .75A total)
6
EIDE_LED Secondary
channel
EIDE
activity LED
5
7
VCC
VCC
GND
+5V power (limited
to .75A total)
8
-
-
-
9
+5V power (limited 10
to .75A total)
-
11
Ground
12
PBRESET- Push button
reset
5-44
Computer Group Literature Center Web Site
6Subassembly Reference
6
Chapter Overview
This chapter provides reference information for the various subassemblies
of the CPX8216 and CPX8216T system. It covers only those items
associated with the system enclosure. For information about CompactPCI
board components, refer to the appropriate chapter in this manual.
Table 6-1. System Components
Topic:
Page:
6-2
Parts of the System
Backplane Reference
Alarm Display Panel
Power Distribution Panel
Power Supplies
6-4
6-5
6-51
6-54
6-58
6-1
Subassembly Reference
Parts of the System
Front Peripheral Bay
Alarm Board
SYSTEM
STATUS
TELCO
STATUS
SYSTEM
IN SERVICE
COMPONENT
OUT OF SERVICE
ALARM
CONNECTION
TBD
MAJOR CRITICAL
MI NOR
1
2
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
CompactPCI
Cardcage
6
3
4
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
ESD BONDING
POINT
Cable
Pass-Thru
OUT OF
SERVICE
OUT OF
SERVICE
IN
SERVICE
IN
SERVICE
OUT OF
SERVICE
IN
SERVICE
2
3
1
Power Supplies
Figure 6-1. CPX8216 Front View
6-2
Computer Group Literature Center Web Site
Subassembly Reference
Industry standard CompactPCI cardguides are used for the front controller
boards and rear transition boards. The CPU slot is identified with red guide
rails, the I/O slots with black rails, and the Hot Swap Controller/Bridge
slots with tan rails (see Figure 6-3 and Figure 6-4 on page 6-4).
Rear Slots
Backplane
6
6
8
15
16
9
1
2
3
5
7
13 14
10 11 12
4
Front Slots
Figure 6-3. Card Cage Rail Color Scheme—CPX8216 Standard System
Rear Slots
Backplane
6
8
15
16
1
2
3
5
7
9
13 14
10
11 12
4
Front Slots
Figure 6-4. Card Cage Rail Color Scheme—CPX8216T H.110 System
Each slot, both controller and transition, has one ESD cardguide clip and
one ESD alignment pin clip. All clips are located on the bottom cardguide
only.
6-4
Computer Group Literature Center Web Site
Backplane Reference
Backplane Reference
The backplane provides the interconnect for all 16-slot, 6U CompactPCI
bus, N+1 power distribution, alarm signal distribution, and IDE device
signal/status distribution.
All sixteen CompactPCI slots accept any standard 6U CompactPCI board
or transition module which meet IEEE 1101.1, IEEE 1101.10, and
IEEE1101.11 specifications. The slots are 64-bit, 33 MHz PCI compliant.
Secondary Side
Alarm, Floppy, IDE
PWR, and SIG Connectors
6
FDB
FDA
P5
P4
P3
IDEA IDEB
PWR2
P2
P1
SIG2
PWR4
H.110 BAT
and Ring
Voltages on
Secondary
Side
SIG4
PRIMARY SIDE
PS1
PS2
PS3
(CPX8216T
Only)
Figure 6-5. CPX8216 and CPX8216T Backplane—Primary Side
6-5
Subassembly Reference
Power Supply Connectors (PS1, PS2, PS3)
The three power supply connectors, PS1, PS2, and PS3, are located on the
primary side of the backplane.
Note
The shaded pins are high current pins. Present[n]# is grounded
on the backplane.
Table 6-2. PS1, PS2, and PS3 Pin Assignments
Pin
1
Signal
Signal
Present[n]#
-12Vdc
A_DOUT#
PS[n]_DIN#
-12Vdc
N/C
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
GND
6
2
GND
3
+3.3Vdc
+3.3Vdc
+S5Vdc
-S5Vdc
4
5
6
7
+5_Share
+S3.3Vdc
-S3.3Vdc
+3.3_Share
+12Vdc
+12Vdc
+12Vdc
A_CLK
PS[n]_FRAME#
N/C
8
N/C
9
N/C
10
11
12
13
14
15
N/C
+5Vdc
+5Vdc
GND
GND
6-6
Computer Group Literature Center Web Site
H.110 Power Connector (CPX8216T Only)
Table 6-3. Fan Module Pin Assignments
Pin
1
Signal
Color
Pin Signal
Color
N/C
6
N/C
2
+12V_System In
+12V_Fan
Tach
Grey
Red
7
+12V_System Out
+12V_Fan_Rtn
Speed Ctl
N/C
Brown
Black
3
8
4
Blue
9
Yellow
5
N/C
10
6
H.110 Power Connector (CPX8216T Only)
H.110 BAT and Ring voltages are supplied to the backplane directly from
the Power Distribution Panel. This section applies to CPX8216T systems
only.
Table 6-4. H.110 Power Connector
Pin
1
Signal
-Vbat
2
Vbat RTN
-SELVbat
SELVbat RTN
VRG
3
4
5
6
VRG RTN
6-7
Subassembly Reference
Alarm Interface Connector (ALARM)
The alarm interface connector is located on the secondary side of the
backplane. Alarm signals are routed through the backplane to the ALARM
connector. The alarm board attaches to this connector by ribbon cable.
Table 6-5. ALARM Connector Pin Assignments
Pin
1
Signal
Pin
2
Signal
ALM_A_CLK
ALM_B_CLK
ALM_A_DOUT#
ALM_B_DOUT#
ALM_A_FRAME#
ALM_A_DIN#
GND
3
4
GND
6
5
6
ALM_A_5V
ALM_B_5V
ALM_B_FRAME#
7
8
9
10
12
11
Floppy Drive Connectors (FDA, FDB)
The backplane supports two standard IDE floppy drives. The floppy drive
connectors, FDA and FDB, are located on the secondary side of the
backplane. FDA is controlled by domain A, and FDB is controlled by
domain B.
Table 6-6. FDA and FDB Pin Assignments
Pin
1
Signal
Signal
Pin
2
GND
Not Connected
Not Connected
Not Connected
F_[n]_INDEX#
F_[n]_MTRO#
F_[n]_DS1#
3
GND
4
5
Key (pin missing)
GND
6
7
8
9
GND
10
12
11
GND
6-8
Computer Group Literature Center Web Site
IDE Drive Connectors (IDEA and IDEB)
Table 6-6. FDA and FDB Pin Assignments (continued)
Pin
13
15
17
19
21
23
25
27
29
31
33
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Signal
Pin
14
16
18
20
22
24
26
28
30
32
34
F_[n]_DS0#
F_[n]_MTR1#
F_[n]_DIR#
F_[n]_STEP#
F_[n]_WDATA#
F_[n]_WGATE#
F_[n]_TR0#
6
F_[n]_WPROT#
F_[n]_RDATA#
F_[n]_HDSEL#
F_[n]_DSKCHG#
IDE Drive Connectors (IDEA and IDEB)
The two IDE drive connectors are located on the secondary side of the
backplane. IDEA is controlled by Domain A; IDEB by Domain B.
Table 6-7. IDEA and IDEB Pin Assignments
Pin
1
Signal
Signal
Pin
2
IDE_[n]_RST#
IDE_[n]_D7
IDE_[n]_D6
IDE_[n]_D5
IDE_[n]_D4
IDE_[n]_D3
IDE_[n]_D2
GND
3
IDE_[n]_D8
IDE_[n]_D9
IDE_[n]_D10
IDE_[n]_D11
IDE_[n]_D12
IDE_[n]_D13
4
5
6
7
8
9
10
12
14
11
13
6-9
Subassembly Reference
Table 6-7. IDEA and IDEB Pin Assignments (continued)
Pin
15
17
19
21
23
25
27
29
31
33
35
37
39
Signal
Signal
Pin
16
18
20
22
24
26
28
30
32
34
36
38
40
IDE_[n]_D1
IDE_[n]_D13
IDE_[n]_D15
Key (pin missing)
GND
IDE_[n]_D0
GND
IDE_[n]_DMARQ
IDE_[n]_DIOW#
IDE_[n]_DIOR#
IDE_[n]_IORDY
IDE_[n]_DMACK#
IDE_[n]_INTRQ
IDE_[n]_DA1
IDE_[n]_DA0
IDE_[n]_CS1FX#
IDE_[n]_DASP
GND
GND
No Connect
GND
6
IDE_[n]_IOCS16#
IDE_[n]_PDIAG#
IDE_[n]_DA2
IDE_[n]_CS3FX#
GND
Peripheral Power Connectors (PWR1, PWR2,
PWR3, PWR4)
The four peripheral power connectors are located on the secondary side of
the CPX8216 backplane. All four connectors have the same pin-out and
can be used interchangeably.
Table 6-8. PWR1, PWR2, PWR3, PWR4 Pin Assignments
Pin
1
Signal
+5 Volts
Ground
2
6-10
Computer Group Literature Center Web Site
Peripheral Signal Connectors (SIG1, SIG2, SIG3, SIG4)
Table 6-8. PWR1, PWR2, PWR3, PWR4 Pin Assignments
Pin
3
Signal
Ground
+12 Volts
4
Peripheral Signal Connectors (SIG1, SIG2,
SIG3, SIG4)
The four peripheral signal connectors are located on the secondary side of
the CPX8216 backplane. All four connectors have the same pin-out. The
connectors map to different locations in the Hot Swap Controller
peripheral registers, and cannot be used interchangeably.
6
Table 6-9. SIG1, SIG2, SIG3, SIG4 Pin Assignments
Pin
1
Signal
Per[n]_Pwr_ON#
Per[n]_LED1#
Per[n]_LED2#
Per[n]_PSNT_A#
Per[n]_PSNT_B#
2
3
4
5
CompactPCI Connectors (P1, P2, P3, P4, P5)—
CPX8216 Standard Backplane
Primary (Front) Side I/O Connectors (Slots 1-6 and 11-16)
In the front I/O slots (system slots 1-6 and 11-16), connectors P3, P4, and
P5 are reserved for user I/O.
6-11
Subassembly Reference
Connectors P1 and P2 carry the CompactPCI bus (bus A for slots 1-6, bus
B for slots 11-16).
Table 6-10. P5 Connector, I/O Slots 1-6 and 11-16
(User I/O)
POS
Row Z
Row A
Row B
Row C
Row D
Row E
Row F
22-1
GND
I/O
I/O
I/O
I/O
I/O
GND
All I/O pins pass through the backplane to the transition module, they do not make any connection
to the backplane.
6
Table 6-11. P4 Connector, I/O Slots 1-6 and 11-16 (User I/O)
POS
25-15
14
Row Z
Row A
Row B
Row C
Row D
Row E
Row F
GND
I/O
I/O
I/O
I/O
I/O
GND
KEY AREA
13
12
11-1
GND
I/O
I/O
I/O
I/O
I/O
GND
All I/O pins pass through the backplane to the transition module, they do not make any connection
to the backplane.
Table 6-12. P3 Connector, I/O Slots 1-6 and 11-16 (User I/O)
POS
Row Z
Row A
Row B
Row C
Row D
Row E
Row F
19-1
GND
I/O
I/O
I/O
I/O
I/O
GND
All I/O pins pass through the backplane to the transition module, they do not make any connection
to the backplane.
6-12
Computer Group Literature Center Web Site
Primary (Front) Side I/O Connectors (Slots 1-6 and 11-16)
Table 6-13. P2 Connector, I/O Slots 1-6 and 11-16 (CPCI Bus)
Row
Z
Row
F
POS
22
Row A
Row B
GA3
Row C
GA2
Row D
GA1
Row E
GA0
RSV
RSV
RSV
GND GA4
GND
GND
GND
GND
GND
21
GND
GND
GND
RSV
RSV
RSV
RSV
20
GND
GND
RSV
19
GND GND
18
GND _BRSVP2
A18
_BRSVP2B _BRSVP2
GND
_BRSVP2E18 GND
18
C18
6
17
16
15
GND _BRSVP2
A17
GND
GND
GND _BRSVP2
A16
_BRSVP2B
16
_BRSVP2E16 GND
GND
GND _BRSVP2
A15
GND
14
13
12
11
10
9
GND _AD[35]
GND _AD[38]
GND _AD[42]
GND _AD[45]
GND _AD[49]
GND _AD[52]
GND _AD[56]
GND _AD[59]
_AD[34]
GND
_AD[33]
VIO
GND
_AD[32]
_AD[36]
_AD[39]
_AD[43]
_AD[46]
_AD[50]
_AD[53]
_AD[57]
GND
GND
GND
GND
GND
GND
GND
GND
_AD[37]
GND
_AD[41]
GND
_AD[40]
VIO
_AD[44]
GND
_AD[48]
GND
_AD[47]
VIO
_AD[51]
GND
8
_AD[55]
GND
_AD[54]
VIO
7
_AD[58]
Signals beginning with an underscore (_) are prefixed with the bus name:
*For boards located in slots 1-6 (Domain A), the signal name is prefixed with PCI_A (for
example, PCI_A_AD[49]).
*For boards located in slots 11-16 (Domain B), the signal name is prefixed with PCI_B (for
example, PCI_B_AD[49]).
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.
6-13
Subassembly Reference
Table 6-13. P2 Connector, I/O Slots 1-6 and 11-16 (CPCI Bus)
Row
Z
Row
F
POS
Row A
Row B
Row C
_AD[61]
VIO
Row D
Row E
6
5
4
GND _AD[63]
_AD[62]
GND
_AD[60]
GND
GND
GND
GND _C/BE[5]# GND
C/BE[4]# _PAR64
GND VIO
_BRSVP2B _C/BE[7]# GND
4
_C/BE[6]
3
2
1
GND
GND
GND
GND
GND
GND
GND
6
GND
Signals beginning with an underscore (_) are prefixed with the bus name:
*For boards located in slots 1-6 (Domain A), the signal name is prefixed with PCI_A (for
example, PCI_A_AD[49]).
*For boards located in slots 11-16 (Domain B), the signal name is prefixed with PCI_B (for
example, PCI_B_AD[49]).
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.
Table 6-14. P1 Connector, I/O Slots 1-6 and 11-16 (CPCI Bus)
Row
Z
Row
F
POS
25
Row A
Row B
_REQ64#
5V
Row C
A_ENUM# 3.3V
VIO _AD[0]
Row D
Row E
GND 5V
5V
GND
24
GND _AD[1]
_ACK64# GND
Signals beginning with an underscore (_) are prefixed with the bus name:
*For boards located in slots 1-6 (Domain A), the signal name is prefixed with PCI_A (for
example, PCI_A_AD[49]).
*For boards located in slots 11-16 (Domain B), the signal name is prefixed with PCI_B (for
example, PCI_B_AD[49]).
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.
Signal A_ENUM# in Domain A (slots 1-6), B_ENUM# in Domain B (Slots 11-16).
6-14
Computer Group Literature Center Web Site
Primary (Front) Side I/O Connectors (Slots 1-6 and 11-16)
Table 6-14. P1 Connector, I/O Slots 1-6 and 11-16 (CPCI Bus)
Row
Z
Row
F
POS
23
22
21
20
19
18
17
16
15
Row A
Row B
_AD[4]
GND
Row C
_AD[3]
3.3V
Row D
5V
Row E
_AD[2]
_AD[5]
GND 3.3V
GND
GND
GND _AD[7]
GND 3.3V
_AD[6]
_M66EN
_AD[11]
GND
_AD[9]
GND
_AD[8]
VIO
_C/BE[0]# GND
GND _AD[12]
GND 3.3V
_AD[10]
_AD[13]
_C/BE[1]
_PERR#
_LOCK#
GND
GND
GND
GND
GND
GND
_AD[15]
GND
_AD[14]
3.3V
GND _SERR#
GND 3.3V
_PAR
6
_SDONE
_SBO#
VIO
GND
GND _DEVSEL# GND
_STOP#
GND 3.3V
_FRAME#
_IRDY#
BD_SEL[n]# _TRDY#
14-
12
KEY AREA
11
10
9
GND _AD[18}
GND _AD[21]
GND _C/BE[3]
GND _AD[26]
GND _AD[30]
GND REQ[N]#
_AD[17]
GND
_AD[16]
3.3V
GND
_C/BE[2]# GND
_AD[20]
GND
_AD[19]
_AD[22]
_AD[24]
_AD[27]
_AD[31]
GNT[N]#
GND
GND
GND
GND
GND
GND
_IDSEL
GND
_AD[23]
VIO
8
_AD[25]
GND
7
_AD[29]
GND
_AD[28]
3.3V
6
CLK[N]
GND
5
GND _BRSVP1A _BRSVP1B RST[N]#
5
5
Signals beginning with an underscore (_) are prefixed with the bus name:
*For boards located in slots 1-6 (Domain A), the signal name is prefixed with PCI_A (for
example, PCI_A_AD[49]).
*For boards located in slots 11-16 (Domain B), the signal name is prefixed with PCI_B (for
example, PCI_B_AD[49]).
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.
Signal A_ENUM# in Domain A (slots 1-6), B_ENUM# in Domain B (Slots 11-16).
6-15
Subassembly Reference
Table 6-14. P1 Connector, I/O Slots 1-6 and 11-16 (CPCI Bus)
Row
Z
Row
F
POS
Row A
Row B
Row C
Row D
Row E
4
GND _BRSVP1A HLTY[N]#
4
VIO
_INTP
_INTS
GND
3
2
1
GND _INTA#
GND TCK
GND 5V
_INTB#
5V
_INTC#
TMS
5V
_INTD#
TDI
GND
GND
GND
TDO
+12V
-12V
TRST#
5V
Signals beginning with an underscore (_) are prefixed with the bus name:
6
*For boards located in slots 1-6 (Domain A), the signal name is prefixed with PCI_A (for
example, PCI_A_AD[49]).
*For boards located in slots 11-16 (Domain B), the signal name is prefixed with PCI_B (for
example, PCI_B_AD[49]).
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.
Signal A_ENUM# in Domain A (slots 1-6), B_ENUM# in Domain B (Slots 11-16).
6-16
Computer Group Literature Center Web Site
Primary (Front) Side CPU Slot Connectors (7 and 9)
Primary (Front) Side CPU Slot Connectors (7 and 9)
Table 6-15. P5 Connector, CPU Slots 7 and 9
Row
Z
Row
F
POS
22
21
20
19
18
17
16
15
14
13
12
11
10
Row A
Row B
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Row C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Row D
I/O
Row E
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND I/O
GND I/O
GND I/O
GND I/O
GND I/O
GND I/O
GND I/O
GND I/O
GND I/O
GND I/O
GND I/O
GND I/O
GND _TR0#
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
I/O
I/O
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
_WPROT# _RDATA#
_HDSEL#
_DSKCHG GND
#
9
8
7
GND _MTR1#
GND _RSV1#
GND _CS1FX#
_DIR#
_STEP#
_MTR0#
_DA1
_WDATA# _WGATE# GND
_INDEX#
_CS3FX#
_DS1#
A_DS0#
_RSV0#
GND
GND
_DASP#
Signals in bold text are prefixed with IDE_A if the board resides in slot 7 or IDE_B if the board
resides in slot 9.
Signals in shaded cells are prefixed with F_A if the board resides in slot 7 or F_B if the board
resides in slot 9.
All I/O pins pass through the backplane to the transition module; they do not make any connection
to the backplane.
6-17
Subassembly Reference
Table 6-15. P5 Connector, CPU Slots 7 and 9 (continued)
Row
Z
Row
F
POS
Row A
Row B
I/O
Row C
_PDIAG#
_DIOW#
I/O
Row D
Row E
6
5
4
3
2
1
GND _IOCS16#
GND _DMARQ
GND _D14
GND _D3
_DA0
_DA2
GND
GND
GND
GND
GND
GND
_IORDY
_D0
_DMACK# _DIOR#
_D15
_D13
_D4
_INTRQ
_D1
_D12
_D5
_D2
GND _D9
_D10
_D11
_D6
GND I/O
_RST#
_D7
_D8
6
Signals in bold text are prefixed with IDE_A if the board resides in slot 7 or IDE_B if the board
resides in slot 9.
Signals in shaded cells are prefixed with F_A if the board resides in slot 7 or F_B if the board
resides in slot 9.
All I/O pins pass through the backplane to the transition module; they do not make any connection
to the backplane.
Table 6-16. P4 Connector, CPU Slots 7 and 9
POS Row Z Row A
Row B
_AD35
_AD39
_AD44
_+3.3
Row C
_AD34
_AD38
_AD43
_AD48
_AD51
Row D
_AD33
GND
Row E
_AD32
_AD37
_AD41
_AD46
_AD50
Row F
GND
GND
GND
GND
GND
25
24
23
22
21
GND
GND
GND
GND
GND
_AD36
_AD40
_AD45
_AD49
_AD53
_AD42
_AD47
GND
_AD52
The _+5 and _+3 in the shaded cells are provided by the CPU board; they are not connected to the
system power plane. These signals are prefixed with CPUA if the board resides in slot 7 or CPU
B if the board resides in slot 8 (for example, CPUA_+5).
Signals beginning with an underscore (_) are prefixed with the local PCI bus name:
*For boards located in slot 7 (Domain A), the signal name is prefixed with L_PCI_A (for example,
L_PCI_A_AD17).
*For boards located in slot 9 (Domain B), the signal name is prefixed with L_PCI_B (for example,
L_PCI_B_AD17).
6-18
Computer Group Literature Center Web Site
Primary (Front) Side CPU Slot Connectors (7 and 9)
Table 6-16. P4 Connector, CPU Slots 7 and 9 (continued)
POS Row Z Row A
Row B
_+3.3
Row C
_AD56
_AD59
_PAR64
_CBE6#
_AD1
Row D
_AD55
GND
Row E
_AD54
_AD58
_AD62
_CBE5#
_ACK64#
_AD3
Row F
GND
GND
GND
GND
GND
GND
20
19
18
17
16
15
GND
GND
GND
GND
GND
GND
_AD57
_AD61
_CBE4#
_REQ64#
_AD2
_AD60
_+3.3
_AD63
GND
_CBE7#
_+3.3
_AD0
GND
_AD6
_AD5
_AD4
14-
12
KEY AREA
6
11
10
9
GND
GND
GND
GND
GND
_AD9
_AD8
_+5
_CBE0#
_AD12
GND
_AD7
GND
GND
GND
GND
_AD13
_PAR
_AD11
GND
_AD10
_AD14
_SERR#
_CBE1#
_+5
_AD15
8
_STOP#
_LOCK#
_TRDY#
_PERR#
GND
7
_FRAME# _IRDY#
_DEVSEL GND
#
6
5
4
3
2
1
GND
GND
GND
GND
GND
GND
_AD18
_AD21
_CBE3#
_AD28
_GNT#
_INTA#
_+5
_AD17
_AD20
_IDSEL
_AD26
_AD31
_INTC#
_AD16
GND
CBE2#
_AD19
_AD22
_AD24
_AD29
_RST#
GND
GND
GND
GND
GND
GND
_CLK
_+5
_AD23
_AD25
_AD30
_INTD#
_AD27
_REQ#
_INTB#
The _+5 and _+3 in the shaded cells are provided by the CPU board; they are not connected to the
system power plane. These signals are prefixed with CPUA if the board resides in slot 7 or CPU
B if the board resides in slot 8 (for example, CPUA_+5).
Signals beginning with an underscore (_) are prefixed with the local PCI bus name:
*For boards located in slot 7 (Domain A), the signal name is prefixed with L_PCI_A (for example,
L_PCI_A_AD17).
*For boards located in slot 9 (Domain B), the signal name is prefixed with L_PCI_B (for example,
L_PCI_B_AD17).
6-19
Subassembly Reference
Table 6-17. P3 Connector, CPU Slots 7 and 9
POS Row Z Row A
Row B
I/O
Row C
I/O
Row D
I/O
Row E
I/O
Row F
GND
GND
GND
GND
GND
GND
19
18
17
16
15
GND
GND
GND
GND
GND
I/O
HS_REQ_
I/O
I/O
I/O
I/O
HS_GNT_ I/O
I/O
I/O
I/O
HS_FLT_
HS_EJ_
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
14-1 GND
I/O
I/O
I/O
All I/O pins pass through the backplane to the transition module; they do not make any
connection to the backplane.
6
If the CPU is mounted in slot 7, the HS signals will end with A (for example, HS_REQ_A).
If the CPU is mounted in slot 9, the HS signals will end with B (for example, HS_REQ_B).
Table 6-18. P2 Connector, CPU Slot 7 (Domain A)
POS Row Z Row A
Row B
GA3
Row C
GA2
Row D
GA1
Row E
GA0
RSV
RSV
RSV
Row F
GND
GND
GND
GND
GND
22
21
20
19
18
GND
GND
GND
GND
GND
GA4
CLK6
CLK5
GND
GND
GND
GND
RSV
RSV
RSV
RSV
GND
RSV
_BRSVP2
A18
_BRSVP2
B18
_BRSVP2
C18
GND
_BRSVP2
E18
17
16
GND
GND
_BRSVP2
A17
GND
_PRST#
_REQ6#
GND
GNT6#
GND
GND
_BRSVP2
A16
_BRSVP2
B16
_DEG#
_BRSVP2
E16
Signals beginning with an underscore (_) are prefixed with the bus name PCI_A (for example,
PCI_A_AD[49]).
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.
6-20
Computer Group Literature Center Web Site
Primary (Front) Side CPU Slot Connectors (7 and 9)
Table 6-18. P2 Connector, CPU Slot 7 (Domain A) (continued)
POS Row Z Row A
Row B
Row C
Row D
Row E
Row F
15
GND
_BRSVP2
A15
GND
_FAL#
REQ5#
GNT5#
GND
14
13
12
11
10
9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
_AD[35]
_AD[38]
_AD[42]
_AD[45]
_AD[49]
_AD[52]
_AD[56]
_AD[59]
_AD[63]
_AD[34]
GND
_AD[33]
VIO
GND
_AD[32]
_AD[36]
_AD[39]
_AD[43]
_AD[46]
_AD[50]
_AD[53]
_AD[57]
_AD[60]
_PAR64
_C/BE[6]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
_AD[37]
GND
_AD[41]
GND
_AD[40]
VIO
_AD[44]
GND
_AD[48]
GND
_AD[47]
VIO
6
_AD[51]
GND
8
_AD[55]
GND
_AD[54]
VIO
7
_AD[58]
GND
6
_AD[62]
_AD[61]
VIO
5
_C/BE[5]# GND
C/BE[4]#
4
VIO
_BRSVP2
_C/BE[7]# GND
B4
3
2
1
GND
GND
GND
CLK4
CLK2
CLK1
GND
CLK3
GND
GNT3#
REQ4#
GNT4#
REQ3#
REQ2#
GND
GND
GND
_SYSEN#
REQ1#
GNT2#
GNT1#
Signals beginning with an underscore (_) are prefixed with the bus name PCI_A (for example,
PCI_A_AD[49]).
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.
6-21
Subassembly Reference
Table 6-19. P2 Connector, CPU Slot 9 (Domain B)
POS Row Z Row A
Row B
GA3
Row C
GA2
Row D
GA1
Row E
GA0
RSV
RSV
RSV
Row F
GND
GND
GND
GND
GND
22
21
20
19
18
GND
GND
GND
GND
GND
GA4
CLK16
CLK15
GND
GND
GND
GND
RSV
RSV
RSV
RSV
GND
RSV
_BRSVP2
A18
_BRSVP2
B18
_BRSVP2
C18
GND
_BRSVP2
E18
17
16
15
GND
GND
GND
_BRSVP2
A17
GND
_PRST#
_DEG#
_FAL#
_REQ16#
GND
GNT16#
GND
GND
GND
6
_BRSVP2
A16
_BRSVP2
B16
_BRSVP2
E16
_BRSVP2
A15
GND
REQ15#
GNT15#
14
13
12
11
10
9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
_AD[35]
_AD[38]
_AD[42]
_AD[45]
_AD[49]
_AD[52]
_AD[56]
_AD[59]
_AD[63]
_AD[34]
GND
_AD[33]
VIO
GND
_AD[32]
_AD[36]
_AD[39]
_AD[43]
_AD[46]
_AD[50]
_AD[53]
_AD[57]
_AD[60]
_PAR64
_C/BE[6]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
_AD[37]
GND
_AD[41]
GND
_AD[40]
VIO
_AD[44]
GND
_AD[48]
GND
_AD[47]
VIO
_AD[51]
GND
8
_AD[55]
GND
_AD[54]
VIO
7
_AD[58]
GND
6
_AD[62]
_AD[61]
VIO
5
_C/BE[5]# GND
VIO _BRSVP2
B4
C/BE[4]#
4
_C/BE[7]# GND
Signals beginning with an underscore (_) are prefixed with the bus name PCI_B (for example,
PCI_B_AD[49]).
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.
6-22
Computer Group Literature Center Web Site
Primary (Front) Side CPU Slot Connectors (7 and 9)
Table 6-19. P2 Connector, CPU Slot 9 (Domain B) (continued)
POS Row Z Row A
Row B
GND
Row C
Row D
Row E
Row F
GND
GND
GND
3
2
1
GND
GND
GND
CLK14
CLK12
CLK11
GNT13#
_SYSEN#
REQ11#
REQ14#
GNT12#
GNT11#
GNT14#
REQ13#
REQ12#
CLK13
GND
Signals beginning with an underscore (_) are prefixed with the bus name PCI_B (for example,
PCI_B_AD[49]).
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.
6
Table 6-20. P1 Connector, CPU Slots 7 and 9
POS
Row Z
Row A
Row B
Row C
Row D
Row E
Row F
25
GND
5V
_REQ64 A_ENU
3.3V
5V
GND
#
M#
24
GND
_AD[1]
5V
VIO
_AD[0]
_ACK64 GND
#
23
22
21
GND
GND
GND
3.3V
_AD[4]
GND
_AD[3]
3.3V
5V
_AD[2]
_AD[5]
GND
GND
_AD[7]
3.3V
_AD[6]
_AD[9]
_AD[8]
_M66EN _C/BE[0] GND
#
20
19
GND
GND
_AD[12] GND
3.3V
VIO
_AD[11] _AD[10] GND
_AD[15] _AD[14] GND
_AD[13] GND
Signals beginning with an underscore (_) are prefixed with the bus name:
*For boards located in slot 7 (Domain A), the signal name is prefixed with PCI_A (for example,
PCI_A_AD[49]).
*For boards located in slot 9 (Domain B), the signal name is prefixed with PCI_B (for example,
PCI_B_AD[49]).
Shaded cell A_ENUM# applies to Domain A; Domain B signal B_ENUM#.
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.
Signals enclosed in parentheses () are not used
6-23
Subassembly Reference
Table 6-20. P1 Connector, CPU Slots 7 and 9 (continued)
POS
18
Row Z
GND
GND
GND
Row A
_SERR# GND
3.3V
Row B
Row C
Row D
_PAR
Row E
Row F
3.3V
_C/BE[1] GND
_PERR# GND
_LOCK# GND
17
_SDONE _SBO#
GND
16
_DEVSE GND
L#
VIO
_STOP#
15
GND
3.3V
_FRAME _IRDY#
#
BD_SEL _TRDY# GND
[n]#
14-12
11
KEY AREA
6
GND
_AD[18} _AD[17] _AD[16] GND
_C/BE[2] GND
#
10
9
GND
GND
GND
GND
GND
GND
_AD[21] GND
_C/BE[3] _IDSEL
_AD[26] GND
3.3V
_AD[23] GND
VIO _AD[25] _AD[24] GND
_AD[20] _AD[19] GND
_AD[22] GND
8
7
_AD[30] _AD[29] _AD[28] GND
(REQ#) GND 3.3V (CLK)
_BRSVP _BRSVP RST[N]# GND
1A5 1B5
_BRSVP HLTY[N] VIO
_AD[27] GND
_AD[31] GND
6
5
(GNT#)
GND
GND
GND
4
3
GND
GND
_INTP
_INTS
1A4
#
_INTA#
_INTB#
_INTC#
5V
_INTD#
Signals beginning with an underscore (_) are prefixed with the bus name:
*For boards located in slot 7 (Domain A), the signal name is prefixed with PCI_A (for example,
PCI_A_AD[49]).
*For boards located in slot 9 (Domain B), the signal name is prefixed with PCI_B (for example,
PCI_B_AD[49]).
Shaded cell A_ENUM# applies to Domain A; Domain B signal B_ENUM#.
Signals RSV are not connected.
Signals beginning with _BRSV are bussed, but not used.
Signals enclosed in parentheses () are not used
6-24
Computer Group Literature Center Web Site
Primary (Front) Side CPU Slot Connectors (7 and 9)
Table 6-20. P1 Connector, CPU Slots 7 and 9 (continued)
POS
Row Z
GND
Row A
TCK
5V
Row B
5V
Row C
TMS
Row D
TDO
Row E
TDI
Row F
GND
GND
2
1
GND
-12V
TRST#
+12V
5V
Signals beginning with an underscore (_) are prefixed with the bus name:
*For boards located in slot 7 (Domain A), the signal name is prefixed with PCI_A (for example,
PCI_A_AD[49]).
*For boards located in slot 9 (Domain B), the signal name is prefixed with PCI_B (for example,
PCI_B_AD[49]).
Shaded cell A_ENUM# applies to Domain A; Domain B signal B_ENUM#.
Signals RSV are not connected.
6
Signals beginning with _BRSV are bussed, but not used.
Signals enclosed in parentheses () are not used
6-25
Subassembly Reference
Secondary (Rear) Side I/O Connectors
Note
I/O slot connectors P2 and P1 do not connect through to the
transition module.
Table 6-21. P5 Connector, I/O Slots 1-6 and 11-16 (User
I/O)
POS
Row Z Row A Row B Row C Row D Row E Row F
GND I/O I/O I/O I/O I/O GND
22-1
All I/O pins pass through the backplane to the transition module, they do not
make any connection to the backplane.
6
Table 6-22. P4 Connector, I/O Slots 1-6 and 11-16 (User
I/O)
POS
25-15
14
Row Z Row A Row B Row C Row D Row E Row F
GND
I/O
I/O
I/O
I/O
I/O
GND
KEY AREA
13
12
11-1
GND
I/O
I/O
I/O
I/O
I/O
GND
All I/O pins pass through the backplane to the transition module, they do not
make any connection to the backplane.
Table 6-23. P3 Connector, I/O Slots 1-6 and 11-16 (User
I/O)
POS
Row Z Row A Row B Row C Row D Row E Row F
GND I/O I/O I/O I/O I/O GND
19-1
All I/O pins pass through the backplane to the transition module, they do not
make any connection to the backplane.
6-26
Computer Group Literature Center Web Site
CPU Transition Module Connectors (Transition Slots 7 and 9)
CPU Transition Module Connectors
(Transition Slots 7 and 9)
Note
CPU transition module connectors P4, P2, and P1 are not
connected.
Table 6-24. P5 Connector, CPU Transition Module Slots
Row
Z
Row
F
POS
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Row A
Row B
I/O
Row C
I/O
Row D Row E
GND I/O
GND I/O
GND I/O
GND I/O
GND I/O
GND I/O
GND I/O
GND I/O
GND I/O
GND I/O
GND I/O
GND I/O
GND RSVD
GND RSVD
GND RSVD
GND RSVD
I/O
I/O
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
8
7
All I/O pins pass through the backplane; they do not make any connection to the
backplane.
All RSVD pins are internally connected and pass through. They are reserved for
the IDE and Floppy drive signals; the transition module should avoid
connections to these pins.
6-27
Subassembly Reference
Table 6-24. P5 Connector, CPU Transition Module Slots
Row
Z
Row
F
POS
Row A Row B
Row C Row D Row E
6
5
4
3
2
1
GND RSVD
GND RSVD
GND RSVD
GND RSVD
GND RSVD
GND I/O
I/O
RSVD
RSVD
I/O
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
GND
GND
GND
GND
GND
GND
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
6
All I/O pins pass through the backplane; they do not make any connection to the
backplane.
All RSVD pins are internally connected and pass through. They are reserved for
the IDE and Floppy drive signals; the transition module should avoid
connections to these pins.
Table 6-25. P3 Connector, CPU Transition Slots 7 and 9
Row
Z
Row
B
Row
C
Row
D
Row
E
Row
F
POS
19
Row A
GND I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
GND
GND
GND
GND
18
GND RSVD
GND RSVD
GND RSVD
GND RSVD
GND I/O
17
16
15
14-1
All I/O pins pass through the backplane, they do not make any connection to the
backplane.
All RSVD pins are internally connected and pass through. They are reserved for
the IDE and Floppy drive signals; the transition module should avoid
connections to these pins.
6-28
Computer Group Literature Center Web Site
Hot Swap Controller/Bridge Connectors (Transition Slots 8 and 10)
Hot Swap Controller/Bridge Connectors
(Transition Slots 8 and 10)
The Hot Swap Controller/Bridge for Domain A resides in transition
module slot 10. The Hot Swap Controller/Bridge for Domain B resides in
transition module slot 8.
Table 6-26. P5 Connector, HSC/Bridge (Slots 8 and 10)
POS
Row Z
Row A
Row B
Row C
Row D
Row E
Row F
22-1
GND
RSVD
RSVD
RSVD
RSVD
RSVD
GND
6
Connector P5 is reserved for future use.
Table 6-27. P4 Connector, HSC/Bridge (Slots 8 and 10)
Row
Z
Row
F
POS
25
Row A
_AD36
_AD40
_AD45
_AD49
_AD53
_AD57
_AD61
_CBE4#
Row B
_AD35
_AD39
_AD44
_+3.3
Row C
_AD34
_AD38
_AD43
_AD48
_AD51
_AD56
_AD59
_PAR64
Row D
_AD33
_GND
_AD42
_AD47
_GND
_AD55
_GND
_AD63
Row E
_AD32
_AD37
_AD41
_AD46
_AD50
_AD54
_AD58
_AD62
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
24
23
22
21
_AD52
_+3.3
20
19
_AD60
_+3.3
18
The _GND, _+5 and _+3 in the shaded cells are provided by the CPU board; they are not
connected to the system power plane. These signals are prefixed with CPUA if the board resides
in slot 10 or CPUB if the board resides in slot 8 (for example, CPUA_+5).
Unshaded signals beginning with an underscore (_) are prefixed with the local PCI bus name:
*For boards located in slot 10 (Domain A), the signal name is prefixed with L_PCI_A (for
example, L_PCI_A_AD17).
*For boards located in slot 8 (Domain B), the signal name is prefixed with L_PCI_B (for
example, L_PCI_B_AD17).
6-29
Subassembly Reference
Table 6-27. P4 Connector, HSC/Bridge (Slots 8 and 10) (continued)
Row
Z
Row
F
POS
17
Row A
_REQ64#
_AD2
Row B
_CBE7#
_+3.3
Row C
_CBE6#
_AD1
Row D
_GND
_AD0
_GND
Row E
GND
GND
GND
_CBE5#
GND
16
_ACK64# GND
15
_AD6
_AD5
_AD4
_AD3
GND
14-12 KEY AREA
11
10
9
GND
GND
GND
GND
GND
_AD9
_AD8
_+5
_CBE0#
_AD12
_GND
_AD11
_GND
_PERR#
_GND
_AD7
GND
GND
GND
GND
_AD13
_PAR
_AD10
_AD14
_SERR#
6
_CBE1#
_+5
_AD15
8
_STOP#
_LOCK#
_TRDY#
7
_FRAME# _IRDY#
_DEVSEL GND
#
6
5
4
3
2
1
GND
GND
GND
GND
GND
GND
_AD18
_AD21
_CBE3#
_AD28
_GNT#
_INTA#
_+5
_AD17
_AD20
_IDSEL
_AD26
_AD31
_INTC#
_AD16
_GND
CBE2#
_AD19
_AD22
_AD24
_AD29
_RST#
GND
GND
GND
GND
GND
GND
_CLK
_+5
_AD23
_AD25
_AD30
_INTD#
_AD27
_REQ#
_INTB#
The _GND, _+5 and _+3 in the shaded cells are provided by the CPU board; they are not
connected to the system power plane. These signals are prefixed with CPUA if the board resides
in slot 10 or CPUB if the board resides in slot 8 (for example, CPUA_+5).
Unshaded signals beginning with an underscore (_) are prefixed with the local PCI bus name:
*For boards located in slot 10 (Domain A), the signal name is prefixed with L_PCI_A (for
example, L_PCI_A_AD17).
*For boards located in slot 8 (Domain B), the signal name is prefixed with L_PCI_B (for
example, L_PCI_B_AD17).
6-30
Computer Group Literature Center Web Site
Hot Swap Controller/Bridge Connectors (Transition Slots 8 and 10)
Table 6-28. P3 Connector, HSC Slots 8 and 10
POS Row Z Row A
Row B
Row C
Row D
Row E
Row F
19
18
17
16
15
14
13
12
11
10
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A/B#
ALM_B_5 INT_HSC_ Per3_Pwr_ Per1_Pwr_ GND
V
2
ON#
ON#
HS_REQ_
B
HS_REQ_
A
INT_HSC_ Per3_LED1 Per1_LED1 GND
1
#
#
HS_GNT_ HS_GNT_ INT_HSC_ Per3_LED2 Per1_LED2 GND
B
A
4
#
#
HS_FLT_B HS_FLT_A INT_HSC_ Per3_PSN
T_B#
Per1_PSN
T_B#
GND
3
6
HS_EJ_B
HS_EJ_A
INT_HSC_ Per4_Pwr_ Per2_Pwr_ GND
ON# ON#
6
INT_HSC_ INT_HSC_ INT_HSC_ Per4_LED1 Per2_LED1 GND
8
7
5
#
#
A_CLK
A_DOUT# PS_1_DIN Per4_LED2 Per2_LED2 GND
#
#
#
B_CLK
B_DOUT# PS_2_DIN Per4_PSN
T_B#
Per2_PSN
T_B#
GND
GND
#
ALM_A_F PS_1_FRA PS_3_DIN ALM_A_D
RAME#
ME#
#
IN#
ALM_B_F PS_2_FRA PS_3_FRA
B_ENUM# GND
RAME#
RST3#
RST2#
RST1#
ME#
ME#
9
8
7
6
GND
GND
GND
GND
RST6#
RST5#
RST4#
HLTY10#
HLTY9#
HLTY8#
HLTY7#
RST16#
RST15#
RST14#
HLTY16#
RST13#
RST12#
RST11#
GND
GND
GND
BD_SEL6# HLTY6#
BD_SEL16 GND
#
A/B# GND Domain B (slot 8).
ALM_B_5V in Domain B (slot 8); ALM_A_5V in Domain A (slot 10).
B_ENUM# in Domain B (slot 8); A_ENUM in Domain A (slot 10).
BD_SEL7# in Domain B, BD_SEL9# in Domain A.
6-31
Subassembly Reference
Table 6-28. P3 Connector, HSC Slots 8 and 10 (continued)
POS Row Z Row A
Row B
Row C
Row D
Row E
Row F
5
4
3
2
1
GND
GND
GND
GND
GND
BD_SEL5# HLTY5#
BD_SEL4# HLTY4#
BD_SEL3# HLTY3#
BD_SEL2# HLTY2#
BD_SEL1# HLTY1#
BD_SEL7# HLTY15#
BD_SEL15 GND
#
RST10#
RST9#
RST8#
RST7#
HLTY14#
HLTY13#
HLTY12#
HLTY11#
BD_SEL14 GND
#
BD_SEL13 GND
#
BD_SEL12 GND
#
6
BD_SEL11 GND
#
A/B# GND Domain B (slot 8).
ALM_B_5V in Domain B (slot 8); ALM_A_5V in Domain A (slot 10).
B_ENUM# in Domain B (slot 8); A_ENUM in Domain A (slot 10).
BD_SEL7# in Domain B, BD_SEL9# in Domain A.
Table 6-29. P2 Connector, HSC Slot 10
POS Row Z Row A
Row B
GA3
Row C
GA2
Row D
GA1
Row E
GA0
RSV
RSV
RSV
Row F
GND
GND
GND
GND
GND
22
21
20
19
18
GND
GND
GND
GND
GND
GA4
CLK6
CLK5
GND
GND
GND
GND
RSV
RSV
RSV
RSV
GND
RSV
_BRSVP2
A18
_BRSVP2
B18
_BRSVP2
C18
GND
_BRSVP2
E18
17
GND
_BRSVP2
A17
GND
(_PRST#)
_REQ6#
GNT6#
GND
Signals beginning with an underscore (_) are prefixed with the bus name PCI_B (for example,
PCI_B_AD[49]).
Signals in parentheses are not used.
6-32
Computer Group Literature Center Web Site
Hot Swap Controller/Bridge Connectors (Transition Slots 8 and 10)
Table 6-29. P2 Connector, HSC Slot 10 (continued)
POS Row Z Row A
Row B
Row C
Row D
Row E
Row F
16
GND
_BRSVP2
A16
_BRSVP2
B16
(_DEG#)
GND
_BRSVP2
E16
GND
15
GND
_BRSVP2
A15
GND
(_FAL#)
REQ5#
GNT5#
GND
14
13
12
11
10
9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
_AD[35]
_AD[38]
_AD[42]
_AD[45]
_AD[49]
_AD[52]
_AD[56]
_AD[59]
_AD[63]
_AD[34]
GND
_AD[33]
VIO
GND
_AD[32]
_AD[36]
_AD[39]
_AD[43]
_AD[46]
_AD[50]
_AD[53]
_AD[57]
_AD[60]
_PAR64
_C/BE[6]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
_AD[37]
GND
_AD[41]
GND
_AD[40]
VIO
6
_AD[44]
GND
_AD[48]
GND
_AD[47]
VIO
_AD[51]
GND
8
_AD[55]
GND
_AD[54]
VIO
7
_AD[58]
GND
6
_AD[62]
_AD[61]
VIO
5
_C/BE[5]# GND
C/BE[4]#
4
VIO
_BRSVP2
_C/BE[7]# GND
B4
3
2
1
GND
GND
GND
CLK4
CLK2
CLK1
GND
CLK3
GND
GNT3#
REQ4#
GNT4#
REQ3#
REQ2#
GND
GND
GND
_SYSEN#
REQ1#
GNT2#
GNT1#
Signals beginning with an underscore (_) are prefixed with the bus name PCI_B (for example,
PCI_B_AD[49]).
Signals in parentheses are not used.
6-33
Subassembly Reference
Table 6-30. P2 Connector, HSC Slot 8
POS Row Z Row A
Row B
GA3
Row C
GA2
Row D
GA1
Row E
GA0
RSV
RSV
RSV
Row F
GND
GND
GND
GND
GND
22
21
20
19
18
GND
GND
GND
GND
GND
GA4
CLK16
CLK15
GND
GND
GND
GND
RSV
RSV
RSV
RSV
GND
RSV
_BRSVP2
A18
_BRSVP2
B18
_BRSVP2
C18
GND
_BRSVP2
E18
17
16
15
GND
GND
GND
_BRSVP2
A17
GND
(_PRST#)
(_DEG#)
(_FAL#)
_REQ16#
GND
GNT16#
GND
GND
GND
6
_BRSVP2
A16
_BRSVP2
B16
_BRSVP2
E16
_BRSVP2
A15
GND
REQ15#
GNT15#
14
13
12
11
10
9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
_AD[35]
_AD[38]
_AD[42]
_AD[45]
_AD[49]
_AD[52]
_AD[56]
_AD[59]
_AD[63]
_AD[34]
GND
_AD[33]
VIO
GND
_AD[32]
_AD[36]
_AD[39]
_AD[43]
_AD[46]
_AD[50]
_AD[53]
_AD[57]
_AD[60]
_PAR64
_C/BE[6]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
_AD[37]
GND
_AD[41]
GND
_AD[40]
VIO
_AD[44]
GND
_AD[48]
GND
_AD[47]
VIO
_AD[51]
GND
8
_AD[55]
GND
_AD[54]
VIO
7
_AD[58]
GND
6
_AD[62]
_AD[61]
VIO
5
_C/BE[5]# GND
C/BE[4]#
4
VIO
_BRSVP2
_C/BE[7]# GND
B4
3
GND
CLK14
GND
GNT13# REQ14#
GNT14#
GND
Signals beginning with an underscore (_) are prefixed with the bus name PCI_A (for example,
PCI_A_AD[49]).
Signals in parentheses are not used.
6-34
Computer Group Literature Center Web Site
Hot Swap Controller/Bridge Connectors (Transition Slots 8 and 10)
Table 6-30. P2 Connector, HSC Slot 8 (continued)
POS Row Z Row A
Row B
CLK13
GND
Row C
Row D
Row E
Row F
GND
2
1
GND
GND
CLK12
CLK11
_SYSEN#
REQ11#
GNT12#
GNT11#
REQ13#
REQ12#
GND
Signals beginning with an underscore (_) are prefixed with the bus name PCI_A (for example,
PCI_A_AD[49]).
Signals in parentheses are not used.
Table 6-31. P1 Connector, HSC Slots 8 and 10
6
POS Row Z Row A
Row B
_REQ64#
5V
Row C
Row D
Row E
5V
Row F
GND
GND
GND
GND
25
24
23
22
21
20
19
18
17
16
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
5V
A_ENUM# 3.3V
_AD[1]
3.3V
VIO
_AD[0]
_ACK64#
_AD[2]
_AD[5]
_AD[4]
GND
_AD[3]
3.3V
5V
_AD[7]
3.3V
_AD[6]
_M66EN
_AD[11]
GND
_AD[9]
GND
_AD[8]
VIO
_C/BE[0]# GND
_AD[12]
3.3V
_AD[10]
_AD[13]
_C/BE[1]
_PERR#
_LOCK#
GND
GND
GND
GND
GND
_AD[15]
GND
_AD[14]
3.3V
_SERR#
3.3V
_PAR
_SDONE
_SBO#
VIO
GND
_DEVSEL GND
#
_STOP#
15
GND
3.3V
_FRAME# _IRDY#
BD_SEL[n _TRDY#
]#
GND
14-
12
KEY AREA
11
10
9
GND
GND
GND
_AD[18}
_AD[17]
GND
_AD[16]
3.3V
GND
_C/BE[2]# GND
_AD[21]
_C/BE[3]
_AD[20]
GND
_AD[19]
_AD[22]
GND
GND
_IDSEL
_AD[23]
A_ENUM# in Domain A (slot 10); B_ENUM# in Domain B (slot 8).
6-35
Subassembly Reference
Table 6-31. P1 Connector, HSC Slots 8 and 10 (continued)
POS Row Z Row A
Row B
GND
Row C
VIO
Row D
_AD[25]
GND
Row E
Row F
GND
GND
GND
GND
8
7
6
5
GND
GND
GND
GND
_AD[26]
_AD[30]
REQ[N]#
_AD[24]
_AD[27]
_AD[31]
GNT[N]#
_AD[29]
GND
_AD[28]
3.3V
CLK[N]
GND
_BRSVP1
A5
_BRSVP1
B5
RST[N]#
4
GND
_BRSVP1
A4
HLTY[N]# VIO
_INTP
_INTS
GND
6
3
2
1
GND
GND
GND
_INTA#
TCK
5V
_INTB#
5V
_INTC#
5V
_INTD#
TDI
GND
GND
GND
TMS
TDO
+12V
-12V
TRST#
5V
A_ENUM# in Domain A (slot 10); B_ENUM# in Domain B (slot 8).
6-36
Computer Group Literature Center Web Site
H.110 Bus Connectors—CPX8216T System Only
H.110 Bus Connectors—CPX8216T System
Only
On each domain, the H.110 bus passes through connector P4 across the I/O
and HSC slots. It does not connect to the CPU slot (see Figure 6-6).
P5
P4
H. 110 Bus
6
P3
P2
CompactPCI Bus
System Slot
P1
HSC Slot
2557 9906
Figure 6-6. The CPX8216T H.110 Bus
6-37
Subassembly Reference
Primary (Front) Side I/O Connectors
Pinout Information for See:
Connector:
P5
P4
P3
P2
P1
Table 6-10 on page 6-12
Table 6-32 on page 6-38
Table 6-12 on page 6-12
Table 6-13 on page 6-13
Table 6-14 on page 6-14
6
Primary (Front) Side (Slots 1-6 and 11-16)
The I/O connectors for slots 1-6 and 11-16, except for the P4 connector,
which carries the H.110 bus, use the same pinouts as the standard
CPX8216 backplane.
Table 6-32. P4 Connector, I/O Slots 1-6, 11-16
Row
Z
Row
F
POS
25
Row A
SGA4
GA4
Row B
SGA3
GA3
Row C
SGA2
GA2
Row D Row E
NP
NP
NP
NP
SGA1
GA1
SGA0
GA0
FG
FG
FG
FG
24
23
+12V
PSF0#
CT_RST[n]# CT_EN[n]# -12V
RSVD RSVD
CT_MC
22
RSVD RSVD
NP=Not Populated. P4 implements the full H.110 Bus connections, which requires P4 to use
depopulated connectors.
CT_RST1# through CT_RST6# are routed radially to the bridge slots.
CT_EN1# is connected to BD_SEL1# on the backplane, and so forth.
[n]=n is the slot number.
Refer to the H.110 specifications for line terminations.
6-38
Computer Group Literature Center Web Site
Primary (Front) Side (Slots 1-6 and 11-16)
Table 6-32. P4 Connector, I/O Slots 1-6, 11-16 (continued)
Row
Z
Row
F
POS
21
Row A
Row B
Row C
RSVD
NP
Row D Row E
NP
NP
NP
NP
NP
NP
NP
-SELVbat PSF1#
RSVD SELVbat RTN
FG
NP
NP
NP
NP
NP
NP
20
NP
NP
NP
NP
NP
NP
NP
NP
NP
NP
NP
NP
NP
NP
19
NP
NP
NP
18
VRG
NP
NP
VRG RTN
NP
17
NP
16
NP
NP
NP
6
15
-Vbat
NP
Vbat RTN
14-12 KEY AREA
11
10
9
NP
NP
NP
NP
NP
NP
NP
NP
NP
NP
NP
CT_D29
CT_D27
CT_D24
CT_D21
CT_D19
CT_D16
CT_D13
CT_D11
CT_D8
CT_D30
+3.3V
CT_D31
CT_D28
CT_D26
CT_D23
CT_D23
CT_D18
CT_D15
CT_D12
CT_D10
CT_D6
V(I/O) CT_FRAME_A# GND
+5V
CT_FRAME_B# GND
CT_D25
CT_D22
+5V
GND
+5V
FR_COMP#
CT_C8_A
CT_C8_A
GND
GND
GND
8
7
GND
GND
+3.3V
+3.3V
GND
6
CT_D17
CT_D14
+5V
CT_NETREF_1 GND
CT_NETREF_2 GND
5
4
SCLK
GND
GND
GND
GND
3
CT_D9
CT_D5
+3.3V
SCLK-D
2
CT_D4
CT_D7 GND
1
CT_D0
CT_D1
CT_D2 CT_D3
NP=Not Populated. P4 implements the full H.110 Bus connections, which requires P4 to use
depopulated connectors.
CT_RST1# through CT_RST6# are routed radially to the bridge slots.
CT_EN1# is connected to BD_SEL1# on the backplane, and so forth.
[n]=n is the slot number.
Refer to the H.110 specifications for line terminations.
6-39
Subassembly Reference
Primary (Front) Side CPU Connectors
pinouts as the CPX8216 standard backplane.
For Pinout Information See:
for Connector:
P5
Table 6-17 on page 6-20
Table 6-18 on page 6-20
Table 6-19 on page 6-22
Table 6-20 on page 6-23
P4
P3
P2-Domain A
P2-Domain B
P1
6
Primary (Front) Side HSC Connectors
The HSC/Bridge slot is unique. All five connectors (P5 through P1) use
standard tails, and none of the connectors pass through to the rear.
Table 6-33. P5 Connector, HSC/Bridge (Slots 8 and 10)
POS Row Z Row A
Row B
_AD35
_AD39
_AD44
_+3.3
Row C
_AD34
_AD38
_AD43
_AD48
Row D
_AD33
_GND
_AD42
_AD47
Row E
_AD32
_AD37
_AD41
_AD46
Row F
GND
GND
GND
GND
25
24
23
22
GND
GND
GND
GND
_AD36
_AD40
_AD45
_AD49
The _GND, _+5 and _+3 in the shaded cells are provided by the CPU board; they are not
connected to the system power plane. These signals are prefixed with CPUA if the board resides
in slot 10 or CPUB if the board resides in slot 8 (for example, CPUA_+5).
Unshaded signals beginning with an underscore (_) are prefixed with the local PCI bus name:
*For boards located in slot 10 (Domain A), the signal name is prefixed with L_PCI_A (for
example, L_PCI_A_AD17).
*For boards located in slot 8 (Domain B), the signal name is prefixed with L_PCI_B (for example,
L_PCI_B_AD17).
6-40
Computer Group Literature Center Web Site
Primary (Front) Side HSC Connectors
Table 6-33. P5 Connector, HSC/Bridge (Slots 8 and 10) (continued)
POS Row Z Row A
Row B
_AD52
_+3.3
Row C
_AD51
_AD56
_AD59
_PAR64
_CBE6#
_AD1
Row D
_GND
_AD55
_GND
_AD63
_GND
_AD0
Row E
_AD50
_AD54
_AD58
_AD62
_CBE5#
_ACK64#
_AD3
Row F
GND
GND
GND
GND
GND
GND
GND
21
20
19
18
17
16
15
GND
GND
GND
GND
GND
GND
GND
_AD53
_AD57
_AD61
_CBE4#
_REQ64#
_AD2
_AD60
_+3.3
_CBE7#
_+3.3
_AD6
_AD5
_AD4
_GND
6
14-
12
KEY AREA
11
10
9
GND
GND
GND
GND
GND
_AD9
_AD8
_+5
_CBE0#
_AD12
_GND
_AD11
_GND
_PERR#
_GND
_AD7
GND
GND
GND
GND
_AD13
_PAR
_AD10
_AD14
_SERR#
_CBE1#
_+5
_AD15
8
_STOP#
_LOCK#
_TRDY#
7
_FRAME# _IRDY#
_DEVSEL GND
#
6
5
4
3
GND
GND
GND
GND
_AD18
_AD21
_CBE3#
_AD28
_+5
_AD17
_AD20
_IDSEL
_AD26
_AD16
_GND
_AD23
_AD25
CBE2#
_AD19
_AD22
_AD24
GND
GND
GND
GND
_CLK
_+5
_AD27
The _GND, _+5 and _+3 in the shaded cells are provided by the CPU board; they are not
connected to the system power plane. These signals are prefixed with CPUA if the board resides
in slot 10 or CPUB if the board resides in slot 8 (for example, CPUA_+5).
Unshaded signals beginning with an underscore (_) are prefixed with the local PCI bus name:
*For boards located in slot 10 (Domain A), the signal name is prefixed with L_PCI_A (for
example, L_PCI_A_AD17).
*For boards located in slot 8 (Domain B), the signal name is prefixed with L_PCI_B (for example,
L_PCI_B_AD17).
6-41
Subassembly Reference
Table 6-33. P5 Connector, HSC/Bridge (Slots 8 and 10) (continued)
POS Row Z Row A
Row B
_REQ#
_INTB#
Row C
_AD31
_INTC#
Row D
_AD30
_INTD#
Row E
_AD29
_RST#
Row F
GND
GND
2
1
GND
GND
_GNT#
_INTA#
The _GND, _+5 and _+3 in the shaded cells are provided by the CPU board; they are not
connected to the system power plane. These signals are prefixed with CPUA if the board resides
in slot 10 or CPUB if the board resides in slot 8 (for example, CPUA_+5).
Unshaded signals beginning with an underscore (_) are prefixed with the local PCI bus name:
*For boards located in slot 10 (Domain A), the signal name is prefixed with L_PCI_A (for
example, L_PCI_A_AD17).
6
*For boards located in slot 8 (Domain B), the signal name is prefixed with L_PCI_B (for example,
L_PCI_B_AD17).
Table 6-34. P4 Connector, HSC Slots 8 and 10
Row
Z
Row
F
POS
25
Row A
SGA4
GA4
Row B
SGA3
GA3
Row C
SGA2
GA2
Row D Row E
NP
NP
NP
NP
NP
NP
NP
NP
SGA1
GA1
SGA0
GA0
FG
FG
FG
FG
FG
NP
NP
NP
24
23
+12V
PSF0#
CT_RST[n]# CT_EN[n]# -12V
CT_MC
22
RSVD
RSVD
RSVD
NP
RSVD RSVD
21
-SELVbat PSF1#
RSVD SELVbat RTN
20
NP
NP
NP
NP
NP
NP
NP
NP
19
NP
NP
NP
18
VRG
NP
VRG RTN
NP=Not Populated. P4 implements the full H.110 Bus connections, which requires P4 to use
depopulated connectors.
CT_RST1# through CT_RST6# are routed radially to the bridge slots.
CT_EN1# is connected to BD_SEL1# on the backplane, and so forth.
[n]=n is the slot number.
Refer to the H.110 specifications for line terminations.
6-42
Computer Group Literature Center Web Site
Primary (Front) Side HSC Connectors
Table 6-34. P4 Connector, HSC Slots 8 and 10 (continued)
Row
Z
Row
F
POS
17
Row A
NP
Row B
NP
Row C
NP
Row D Row E
NP
NP
NP
NP
NP
NP
NP
NP
NP
NP
16
NP
NP
NP
NP
15
-Vbat
NP
NP
Vbat RTN
14-
12
KEY AREA
11
10
9
NP
NP
NP
NP
NP
NP
NP
NP
NP
NP
NP
CT_D29
CT_D30
+3.3V
CT_D31
CT_D28
CT_D26
CT_D23
CT_D23
CT_D18
CT_D15
CT_D12
CT_D10
CT_D6
V(I/O) CT_FRAME_A# GND
6
CT_D27
CT_D24
CT_D21
CT_D19
CT_D16
CT_D13
CT_D11
CT_D8
+5V
CT_FRAME_B# GND
CT_D25
CT_D22
+5V
GND
+5V
FR_COMP#
CT_C8_A
GND
GND
GND
GND
8
7
GND
GND
+3.3V
+3.3V
GND
CT_C8_A
6
CT_D17
CT_D14
+5V
CT_NETREF_1
5
CT_NETREF_2 GND
4
SCLK
GND
GND
GND
GND
3
CT_D9
CT_D5
+3.3V
SCLK-D
2
CT_D4
CT_D7 GND
1
CT_D0
CT_D1
CT_D2 CT_D3
NP=Not Populated. P4 implements the full H.110 Bus connections, which requires P4 to use
depopulated connectors.
CT_RST1# through CT_RST6# are routed radially to the bridge slots.
CT_EN1# is connected to BD_SEL1# on the backplane, and so forth.
[n]=n is the slot number.
Refer to the H.110 specifications for line terminations.
6-43
Subassembly Reference
Table 6-35. P3 Connector, HSC Slots 8 and 10
Row
Z
Row
F
POS
Row A
Row B
Row C
INT_HSC_ Per3_Pwr_
ON#
Row D
Row E
19
GND A/B#
ALM_B_5
V
Per1_Pwr_
ON#
GND
2
18
17
16
15
14
13
12
11
10
GND HS_REQ_B HS_REQ_A INT_HSC_ Per3_LED1 Per1_LED1 GND
1
#
#
GND HS_GNT_B HS_GNT_
A
INT_HSC_ Per3_LED2 Per1_LED2 GND
4
#
#
GND HS_FLT_B HS_FLT_A INT_HSC_ Per3_PSNT Per1_PSNT GND
6
3
_B#
INT_HSC_ Per4_Pwr_
ON#
_B#
GND HS_EJ_B
HS_EJ_A
Per2_Pwr_
ON#
GND
6
GND INT_HSC_ INT_HSC_ INT_HSC_ Per4_LED1 Per2_LED1 GND
8
7
5
#
#
GND A_CLK
A_DOUT#
PS_1_DIN# Per4_LED2 Per2_LED2 GND
#
#
GND B_CLK
B_DOUT#
PS_2_DIN# Per4_PSNT Per2_PSNT GND
_B# _B#
GND ALM_A_F
RAME#
PS_1_FRA PS_3_DIN# ALM_A_DI
GND
ME#
N#
GND ALM_B_F
RAME#
PS_2_FRA PS_3_FRA
B_ENUM# GND
ME#
ME#
9
8
7
6
GND RST3#
GND RST2#
GND RST1#
RST6#
RST5#
RST4#
HLTY10#
HLTY9#
HLTY8#
HLTY7#
RST16#
RST15#
RST14#
HLTY16#
RST13#
RST12#
RST11#
GND
GND
GND
GND BD_SEL6# HLTY6#
BD_SEL16 GND
#
A/B# GND Domain B (slot 8).
ALM_B_5V in Domain B (slot 8); ALM_A_5V in Domain A (slot 10).
B_ENUM# in Domain B (slot 8); A_ENUM in Domain A (slot 10).
BD_SEL7# in Domain B, BD_SEL9# in Domain A.
6-44
Computer Group Literature Center Web Site
Primary (Front) Side HSC Connectors
Table 6-35. P3 Connector, HSC Slots 8 and 10 (continued)
Row
Z
Row
F
POS
Row A
Row B
Row C
Row D
Row E
5
GND BD_SEL5# HLTY5#
GND BD_SEL4# HLTY4#
GND BD_SEL3# HLTY3#
GND BD_SEL2# HLTY2#
GND BD_SEL1# HLTY1#
BD_SEL7# HLTY15#
BD_SEL15 GND
#
4
3
2
1
RST10#
RST9#
RST8#
RST7#
HLTY14#
HLTY13#
HLTY12#
HLTY11#
BD_SEL14 GND
#
BD_SEL13 GND
#
BD_SEL12 GND
#
6
BD_SEL11 GND
#
A/B# GND Domain B (slot 8).
ALM_B_5V in Domain B (slot 8); ALM_A_5V in Domain A (slot 10).
B_ENUM# in Domain B (slot 8); A_ENUM in Domain A (slot 10).
BD_SEL7# in Domain B, BD_SEL9# in Domain A.
Table 6-36. P2 Connector, HSC Slot 10
POS Row Z Row A
Row B
GA3
Row C
GA2
Row D
GA1
Row E
GA0
RSV
RSV
RSV
Row F
GND
GND
GND
GND
GND
22
21
20
19
18
GND
GND
GND
GND
GND
GA4
CLK6
CLK5
GND
GND
GND
GND
RSV
RSV
RSV
RSV
GND
RSV
_BRSVP2
A18
_BRSVP2
B18
_BRSVP2
C18
GND
_BRSVP2
E18
17
GND
_BRSVP2
A17
GND
(_PRST#)
_REQ6#
GNT6#
GND
Signals beginning with an underscore (_) are prefixed with the bus name PCI_B (for example,
PCI_B_AD[49]).
Signals in parentheses are not used.
6-45
Subassembly Reference
Table 6-36. P2 Connector, HSC Slot 10 (continued)
POS Row Z Row A
Row B
Row C
Row D
Row E
Row F
16
GND
_BRSVP2
A16
_BRSVP2
B16
(_DEG#)
GND
_BRSVP2
E16
GND
15
GND
_BRSVP2
A15
GND
(_FAL#)
REQ5#
GNT5#
GND
14
13
12
11
10
9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
_AD[35]
_AD[38]
_AD[42]
_AD[45]
_AD[49]
_AD[52]
_AD[56]
_AD[59]
_AD[63]
_AD[34]
GND
_AD[33]
VIO
GND
_AD[32]
_AD[36]
_AD[39]
_AD[43]
_AD[46]
_AD[50]
_AD[53]
_AD[57]
_AD[60]
_PAR64
_C/BE[6]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
_AD[37]
GND
_AD[41]
GND
_AD[40]
VIO
6
_AD[44]
GND
_AD[48]
GND
_AD[47]
VIO
_AD[51]
GND
8
_AD[55]
GND
_AD[54]
VIO
7
_AD[58]
GND
6
_AD[62]
_AD[61]
VIO
5
_C/BE[5]# GND
C/BE[4]#
4
VIO
_BRSVP2
_C/BE[7]# GND
B4
3
2
1
GND
GND
GND
CLK4
CLK2
CLK1
GND
CLK3
GND
GNT3#
REQ4#
GNT4#
REQ3#
REQ2#
GND
GND
GND
_SYSEN#
REQ1#
GNT2#
GNT1#
Signals beginning with an underscore (_) are prefixed with the bus name PCI_B (for example,
PCI_B_AD[49]).
Signals in parentheses are not used.
6-46
Computer Group Literature Center Web Site
Primary (Front) Side HSC Connectors
Table 6-37. P2 Connector, HSC Slot 8
POS Row Z Row A
Row B
GA3
Row C
GA2
Row D
GA1
Row E
GA0
RSV
RSV
RSV
Row F
GND
GND
GND
GND
GND
22
21
20
19
18
GND
GND
GND
GND
GND
GA4
CLK16
CLK15
GND
GND
GND
GND
RSV
RSV
RSV
RSV
GND
RSV
_BRSVP2
A18
_BRSVP2
B18
_BRSVP2
C18
GND
_BRSVP2
E18
17
16
15
GND
GND
GND
_BRSVP2
A17
GND
(_PRST#)
(_DEG#)
(_FAL#)
_REQ16#
GND
GNT16#
GND
GND
GND
6
_BRSVP2
A16
_BRSVP2
B16
_BRSVP2
E16
_BRSVP2
A15
GND
REQ15#
GNT15#
14
13
12
11
10
9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
_AD[35]
_AD[38]
_AD[42]
_AD[45]
_AD[49]
_AD[52]
_AD[56]
_AD[59]
_AD[63]
_AD[34]
GND
_AD[33]
VIO
GND
_AD[32]
_AD[36]
_AD[39]
_AD[43]
_AD[46]
_AD[50]
_AD[53]
_AD[57]
_AD[60]
_PAR64
_C/BE[6]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
_AD[37]
GND
_AD[41]
GND
_AD[40]
VIO
_AD[44]
GND
_AD[48]
GND
_AD[47]
VIO
_AD[51]
GND
8
_AD[55]
GND
_AD[54]
VIO
7
_AD[58]
GND
6
_AD[62]
_AD[61]
VIO
5
_C/BE[5]# GND
C/BE[4]#
4
VIO
_BRSVP2
_C/BE[7]# GND
B4
3
GND
CLK14
GND
GNT13# REQ14#
GNT14#
GND
Signals beginning with an underscore (_) are prefixed with the bus name PCI_A (for example,
PCI_A_AD[49]).
Signals in parentheses are not used.
6-47
Subassembly Reference
Table 6-37. P2 Connector, HSC Slot 8 (continued)
POS Row Z Row A
Row B
CLK13
GND
Row C
Row D
Row E
Row F
GND
GND
2
1
GND
GND
CLK12
CLK11
_SYSEN#
REQ11#
GNT12#
GNT11#
REQ13#
REQ12#
Signals beginning with an underscore (_) are prefixed with the bus name PCI_A (for example,
PCI_A_AD[49]).
Signals in parentheses are not used.
Table 6-38. P1 Connector, HSC Slots 8 and 10
6
Row
Z
Row
F
POS
Row A
Row B
Row C
Row D
Row E
25
GND 5V
_REQ64#
A_ENUM 3.3V
#
5V
GND
24
23
22
21
GND _AD[1]
GND 3.3V
5V
VIO
_AD[0]
_ACK64# GND
_AD[4]
GND
_AD[3]
3.3V
5V
_AD[2]
_AD[5]
GND
GND
GND _AD[7]
GND 3.3V
_AD[6]
_M66EN
_AD[9]
_AD[8]
_C/BE[0] GND
#
20
19
18
17
16
15
GND _AD[12]
GND 3.3V
GND
VIO
_AD[11]
GND
_AD[10]
_AD[13]
GND
GND
_AD[15]
GND
_AD[14]
3.3V
GND _SERR#
GND 3.3V
_PAR
_C/BE[1] GND
_SDONE
GND
_SBO#
VIO
GND
_PERR#
_LOCK#
_TRDY#
GND
GND
GND
GND _DEVSEL#
GND 3.3V
_STOP#
BD_SEL[n]#
_FRAME#
_IRDY#
14-
12
KEY AREA
11
GND _AD[18}
_AD[17]
_AD[16]
GND
_C/BE[2] GND
#
A_ENUM# in Domain A (slot 10); B_ENUM# in Domain B (slot 8).
6-48
Computer Group Literature Center Web Site
Primary (Front) Side HSC Connectors
Table 6-38. P1 Connector, HSC Slots 8 and 10 (continued)
Row
Z
Row
F
POS
10
9
Row A
Row B
GND
Row C
3.3V
Row D
_AD[20]
GND
Row E
GND _AD[21]
GND _C/BE[3]
GND _AD[26]
GND _AD[30]
GND REQ[N]#
_AD[19]
_AD[22]
_AD[24]
_AD[27]
_AD[31]
GND
GND
GND
GND
GND
_IDSEL
GND
_AD[23]
VIO
8
_AD[25]
GND
7
_AD[29]
GND
_AD[28]
3.3V
6
CLK[N]
GND
5
GND _BRSVP1A5 _BRSVP1B5 RST[N]#
GNT[N]# GND
6
4
GND _BRSVP1A4 HLTY[N]#
VIO
_INTP
5V
_INTS
_INTD#
TDI
GND
GND
GND
GND
3
GND _INTA#
GND TCK
GND 5V
_INTB#
5V
_INTC#
TMS
2
TDO
1
-12V
TRST#
+12V
5V
A_ENUM# in Domain A (slot 10); B_ENUM# in Domain B (slot 8).
6-49
Subassembly Reference
Secondary (Rear) Side I/O Connectors
Note
I/O slot connectors P4, P2, and P1 do not connect through to the
transition module.
Table 6-39. P5 Connector, I/O Slots 1-6 and 11-16 (User
I/O)
POS
Row Z Row A Row B Row C Row D Row E Row F
GND I/O I/O I/O I/O I/O GND
22-1
All I/O pins pass through the backplane to the transition module, they do not
make any connection to the backplane.
6
Table 6-40. P3 Connector, I/O Slots 1-6 and 11-16 (User
I/O)
POS
Row Z Row A Row B Row C Row D Row E Row F
GND I/O I/O I/O I/O I/O GND
19-1
All I/O pins pass through the backplane to the transition module, they do not
make any connection to the backplane.
Secondary (Rear) Side CPU Transition Module
Connectors
The CPU transition module connectors use the same pinouts as the
connectors in the CPX8216 standard backplane.
Note
backplane.
For Pinout Information
for Connector:
See:
P5
P3
Table 6-24 on page 6-27
Table 6-25 on page 6-28
6-50
Computer Group Literature Center Web Site
Alarm Display Panel
Alarm Display Panel
The alarm display panel provides the system LEDs and remote alarm
functions for the CPX8216 and the CPX8216T. It is powered and
controlled from each of the two Hot Swap Controllers within the system
(see Figure 6-7).
Telco
Relay
LEDs
o
o
o
o
o
o
o
o
Uncommitted
Digital Inputs
Alarm PLD
6
POR
System LEDs
Slot 1 LEDs
PWR A
PWR B
REG
Domain A
Logic
GND
Slot 2 LEDs
Clock A
o
o
o
Frame A
DOUT A
DIN A
Slot 6 LEDs
Slot 11 LEDs
Clock B
Frame B
Data B
o
Domain B
Logic
o
o
Slot 15 LEDs
Figure 6-7. Alarm Display Panel Block Diagram
The alarm display panel features three system status LEDs, three Telco
alarm status LEDs, three slot status LEDs for each slot, and an RJ-45
connector for Telco alarm status output to an external interface (see Figure
6-8). Normally, only two of the three slot status LEDs are visible—the
third is covered by the panel’s overlay.
6-51
Subassembly Reference
SYSTEM
STATUS
TELCO
SYSTEM
IN SERVICE
COMPONENT
OUT OFSERVICE
ALARM
COMPONENT
MAJOR
CRITICAL
MINOR
STATUS
CONNECTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Figure 6-8. Alarm Display Panel—Front View
The alarm display panel LEDs are controlled by bits in the Hot Swap
Controller’s register, which are set by the system software. This allows full
user customization of alarm event reporting. The next table provides the
color and standard nomenclature for the LEDs on the alarm panel.
6
Table 6-41. Alarm LED Color and Description
Alarm
LED Color
Green
Yellow
Red
Description
In Service
Controller Board Slot
Status
N/A (or Out of Service)
Out of Service
System In Service
Component Out of Service
System Out of Service
Minor
Green
Yellow
Red
System Status
Telco Status
Yellow
Red
Major
Red
Critical
6-52
Computer Group Literature Center Web Site
Alarm Display Panel Interface Connector (J4)
Alarm Display Panel Interface Connector (J4)
Connector J4 receives system alarm signals from the backplane connector
ALARM.
Table 6-42. Alarm Display Panel Interface Connector (J4)
Pin
1
Signal
Pin
2
Signal
ALM_A_CLK
ALM_B_CLK
ALM_A_DOUT#
ALM_B_DOUT#
ALM_A_FRAME#
ALM_A_DIN#
GND
3
4
GND
5
6
ALM_A_5V
ALM_B_5V
ALM_B_FRAME#
6
7
8
9
10
12
14
11
13
Remote Alarm Connector (J1)
The RJ-45 remote alarm connector (J1) provides standard telco alarm
signals to remote alarm equipment. The connector also has a jacket shield
to protective earth ground through two separate pins (E1 and E2).
Table 6-43. Remote Alarm Connector (J1)
Pin
1
Signal
Signal
Pin
5
Critical Alarm
Critical Alarm Return
Major Alarm
Minor Alarm
Minor Alarm Return
Rack Alarm
2
6
3
7
4
Major Alarm Return
Rack Alarm Return
8
6-53
Subassembly Reference
Power Distribution Panel
The power distribution panel, located in the rear of the chassis below the
transition module cardcage, distributes the AC or DC input power to the
system’s power supplies.
There are three versions of the power distribution panel:
❏ AC (CPX8216)
❏ Dual Input DC (CPX8216)
❏ Dual Breaker DC (CPX8216)
❏ H.110 DC (CPX8216T)
6
The CPX8216T can be configured with AC or DC power, however only
the DC version has the dual input option and the H.110 bus analog voltage
inputs.The H.110 bus on P4/J4 operates without the analog voltages
present, but if analog cards are being used (for example, line or trunk
cards) the analog voltages are required.
If the system requires the analog H.110 bus, voltages need to use the dual
DC power distribution panel. If the system requires an AC configuration,
a special AC power distribution panel must be used. Contact your
Motorola sales representative for information.
AC Power Distribution Panel (CPX8216)
The AC version of the panel is shown in the figure below.
90-260 VAC
l
0
Figure 6-9. AC Power Distribution Panel—Front View
6-54
Computer Group Literature Center Web Site
Dual Input DC Power Distribution Panel (CPX8216)
Dual Input DC Power Distribution Panel (CPX8216)
The dual input DC version allows redundant input power supplies for full
high-availability applications. It is recommended that each input source be
independent of the other.
-48 VDC
-48 VDC
ON
ON
-48 VDC RTN
-48 VDC RTN
2572 9907
6
Figure 6-10. Dual Input DC Power Distribution Panel—Front View
Use 12 AWG or larger wire with a #10 ring terminal to connect the DC
power source to the system.
Ring Terminal
WIDTH
STUD SIZE: #10
WIDTH: .490 inch (12.446 mm) or smaller
WIRE GAGE: 12AWG or bigger
Dual Breaker DC Power Distribution Panel (CPX8216)
The dual breaker 48VDC version also allows redundant input power
supplies for full high-availability applications. It is recommended that each
input source be independent of the other. This power distribution panel has
two 30A push/pull circuit breakers and is designed for use with a Smart
cable that includes breakers and additional circuitry that detect the failure
of a single input DC power supply.
6-55
Subassembly Reference
Figure 6-11. Dual Breaker DC Power Distribution Panel—Front View
The dual breaker DC power distribution panel is available without the two
30A circuit breakers, provided that circuit breaker protection is provided
elsewhere and there is allowance for a rating of 30A for each feed.
6
Use either a standard Smart cable or the optional right-angle Smart cable
(for limited space requirements) to connect the DC power source to the
system. Cable length is 10 feet.
Part Number
Cable Description
30-W2750E01A
30-W2750E03A
Standard Smart cable
Right-angle Smart cable
H.110 DC Power Distribution Panel (CPX8216T)
The H.110 DC power distribution panel provides dual DC input for system
power as well six additional power input connectors for the H.110 BAT
and Ring Voltages. The H.110 DC power distribution panel is only
compatible with the CPX8216T system.
Caution
The six H.110 power inputs must only be attached to approved Telephone
Network Voltage (TNV) branch circuits. TNV branch circuits must
comply with all requirements called for in these safety standards: IEC
950/EN60 950, UL #1950, and CSA #950. Attaching those inputs to non-
TNV-approved power sources will cause the system to fail compliance
with safety regulations and may cause damage to the system backplane and
system components.
!
Caution
6-56
Computer Group Literature Center Web Site
H.110 DC Power Distribution Panel (CPX8216T)
H.110 BAT and
Ring Voltage
Terminal Block
System Power
Terminal Blocks
-48 VDC
-48 VDC
ON
ON
-48 VDC
RTN
-48 VDC
RTN
2573 9907
Figure 6-12. H.110 DC Power Distribution Panel
The analog voltages on the H.110 bus are:
6
Table 6-44. DC Analog Voltages for H.110 Bus
Description
Voltage Inputs
Battery
Return
Ringing
SELV
-48V DC
Nominal 48V, range of 40V to 72V
90 VAC nominal
24V DC nominal, range of <60V
Use 12 AWG or larger wire with a #10 ring terminal to connect the DC
system power source to the system. Use 12 AWG or larger wire with a #6
ring terminal to connect the DC TNV voltages to the H.110 power
connectors.
Ring Terminal - System Power
Ring Terminal - H.110 Power
WIDTH
STUD SIZE: #10
STUD SIZE: #6
WIDTH: .490 inch (12.446 mm) or smaller
WIRE GAGE: 12AWG or bigger
WIRE GAGE: 12AWG or bigger
6-57
Power Supplies
Power Supplies
The AC and DC power supplies are mounted on a sled along with the
CPX8216 and CPX8216T System Installation and Use manual.
For the power coupling to the backplane, refer to the information in Power
Supply Connectors (PS1, PS2, PS3) on page 6-6. For the electrical
specification for the power supply, refer to Power Supply Electrical
Specifications on page A-2.
6
6-58
ASpecifications
A
Environmental Characteristics
ENVIRONMENTAL CHARACTERISTICS
Temperature
Operating:
0º to 50º C (32º to 122º F) continuous duty with linear current derating
between +50º C to +60º C (122º to 140º F) to 50% maximum rated power
Storage and Transit:
-25º TO +85º C (-13º to 185º F)
Maximum Altitude
Operating:
Linear current derating to 85% between 8,000 feet and 12,000 feet
30,000 feet
Storage and Transit:
Shock
No degradation at 25g shock of 11ms duration at 1/2 sine wave in three
planes.
Vibration
No degradation at sine 10 to 100 to 10Hz to 2g 10min/decade three planes.
Meets NEBS Bellcore TR-NWT-000063, Zone 4 Earthquake Vibration
Acoustic Noise
Maximum sound level 70dbA (measured at 1 meter from the power supply
at all points around it using a sound-level meter meeting ANSI Standard
S1.4-1983, General Purpose Sound-Level Meter)
Cooling
The power supply meets all specifications when cooled by the fan in its
subenclosure within the restriction of the system enclosure.
A-1
Specifications
A
Power Supply Electrical Specifications
AC Input
AC Voltage: 90 Vac to 132 Vac or 190 Vac to 260 Vac (autoranging)
AC Frequency: 47 Hz to 63 Hz
Power Factor: Minimum 0.98 at full load and nominal line
Turn-on Surge Current: 20 Amps at +/- 2A for one line cycle
Efficiency: -72% typical at full load and nominal line, including output Oring diodes
Input Current: Measured 6.0A maximum at 115 Vac, 3A maximum at 230 Vac at
475 watts
DC Input
DC Voltage: -36 Vdc to -72 Vdc (autoranging)
Turn-on Threshold: -38.5 Vdc to -41Vdc
Turn-on Surge Current: 20 Amps at -36 Vdc maximum in less than 4 msec.
Efficiency: 70% minimum at full load and nominal line, including output Oring
diodes
Input Current: Measured 13A @ -48 Vdc at 475W
Output
All measurements are made at the output connector of the power supply. The power
Minimum Load Operation: None
Total Regulation: Total regulation is any combination of line, load and cross
regulation, actual set point (as a deviation from the nominal set point), warm up, and
temperature that results in an output voltage that deviates from the nominal set point.
Table A-1 provides the total regulation for each output:
A-2
Computer Group Literature Center Web Site
Power Supply Electrical Specifications
A
Table A-1. Total Regulation (per Output)
Output
Maximum
Total
Number
Voltage
Set Point at Load Current
Loads
Regulation
V1
V2
V3
+5.0V
+5.06Vdc@20A
+/- 5 mV
40A
0 to 40A
±3%
±3%
±5%
+3.3V
+3.36Vdc@20A
+/- 5 mV
40A
0 to 40A
+12.0V
+12.1Vdc@4A
+/- 24 mV
10.4A cont.
(11.5A peak
for max. 5
sec.)
0 to 10.4A
V4
-12.0V
-12.1Vdc@2A
+/- 12 mV
4A
0 to 4A
±5%
Output Power
400 Watts total continuous maximum from all outputs. Any mix of
outputs totaling 400W is acceptable.
DC Output Voltage
Adjustment
No output adjustments.
Output Noise
Total periodic and random deviation (PARD) noise found on outputs of
the power module shall be, as measured at the backplane:
-From 0 to 30 MHz bandwidth for ripple <50 mV
-From 0 to 100 MHz bandwidth for spikes <75 mV
Overload Protection
All DC outputs have a method to protect the power supply from overloads
and shorts. When one output is overloaded, then all outputs are turned off.
Cycling the AC or DC input off then on will cause the power supply to
attempt recovery.
Output to Output Short The power supply provides protection when any output is shorted to any
Protection
other output. A short is considered to be any interconnection that results
in any output deviating from its regulation range by more than 0.7 Volts.
Cycling the AC or DC input off then on will cause the power supply to
attempt recovery.
A-3
Specifications
A
Overshoot
Overshoot does not exceed 2.0% of any output voltage under the
following conditions: power failure, enabled, disabled, and AC input
cycled on/off. Overshoot is the phenomena where the magnitude of
voltage of an output temporarily exceeds its final or stabilized value.
Load Change Transient Any DC voltage returns to 1% within 2mS in response to a 25% change
Response
in the load. The +5V output does not vary more than 3% in response to a
25% change in load. The 12V output does not go out of regulation during
a 0.5A change in the +12V load.
Proper Operation
The power supply operates properly when subjected to a 10% delta
During Dynamic Loads dynamic load with a 50% duty cycle at all frequencies from zero to 2
MHz, or 2 times the switching frequency of the power supply, whichever
is greater.
Undershoot and Reverse With respect to its normal zero reference voltage, no output voltage,
Voltage
under any normal condition, become of a polarity opposite to its normal
operation polarity (excluding applying an external reverse voltage).
Output Risetime
The +5V output will have a monotonic rise from 2V to 4.75V. The +5V
output will transition from +2V to +4.75V in less than 50mS when loaded
to 37.5A or less.
The +5V output will always be above +3.3V output.
The +3.3V output will transition from +2V to 13.3V in less than 50mS.
The skew in risetime between +5V and +3.3V outputs will be less than 50
mS.
The +12V output will transition from +2V to +10.8V in less than 50 mS.
The above conditions will be over the complete input range and load
range, from minimum to maximum load with a capacitive load.
Holdover Storage
Output voltage stays within regulation limits for at least 20 msec. from
the last peak of the line voltage cycle after input power is removed. The
power supply does not latch off during an AC line loss condition that is
less than the hold up time.
A-4
Computer Group Literature Center Web Site
Power Supply Electrical Specifications
A
Over Voltage Protection A Single Fault condition is the failure of any one device within the power
supply. The condition includes both the shorting of any output and the
failure of any one device within the power supply.
Under any single fault condition:
The +5V outputs limit voltage at 6.4Vdc maximum.
The +3.3V output limits voltage at 4.2Vdc maximum
The ±12V outputs do not exceed ±15.0Vdc, respectively.
Control Signals
ENABLE POWER# (Input to Power Supply):
Turns on and off the power supply outputs. When the Enable Power#
signal is low, the power supply will be ON. When the Enable Power#
signal is high or open, the power supply will be OFF.
POWER GOOD# (Output from Power Supply):
This signal is low when the power supply output voltages are good. The
signal is high when the power supply voltages are bad. The voltage is
good when it is within ±5% of the set voltage.
A-5
BRelated Documentation
B
Motorola Computer Group Documents
The Motorola publications listed below are referenced in this manual. You
can obtain paper or electronic copies of Motorola Computer Group
publications by:
❏ Contacting your local Motorola sales office
❏ Visiting MCG’s World Wide Web literature site,
❏ To locate and view the most up-to-date product information in
PDF or HTML format, visit
Motorola
Document Title
Publication Number
Compact PCI CPX8216 and CPX8216T System Installation and
Use
CPX8216A/IH
MCP750HA/IH
MCP750A/IH
MCP750HA Hot Swap CompactPCI Single Board Computer
Installation and Use
MCP750 CompactPCI Single Board Computer Installation and
Use
MCP750 Single Board Computer Programmer’s Reference Guide MCP750A/PG
PPCBug Firmware Package User’s Guide PPCBUGA1/UM, and
PPCBUGA2/UM
B-1
Related Documentation
Motorola
Publication Number
B
Document Title
TMCP700 Transition Module Installation and Use
TMCP700A/IH
CPV5350A/IH
CPV5350 CompactPCI Single Board Computer and Transition
Module installation and Reference
CPV8540 CompactPCI Hot Swap Carrier Card User Manual
(Single PMC)
CPV8540A/UM
CPV8540 CompactPCI Hot Swap Carrier Card User Manual (Dual CPV8540B/UM
PMC)
Related Specifications
For additional information, refer to the following table for related
specifications. For your convenience, a source for the listed document is
also provided. It is important to note that in many cases, the information is
preliminary and the revision levels of the documents are subject to change
without notice.
Table B-1. Related Specifications
Publication
Document Title and Source
Number
Electronic Industries Alliance http://www.eia.org/
Interface Between Data Terminal Equipment and Data Circuit-
Terminating Equipment Employing Serial Binary Data Interchange;
TIA/EIA-232
Standard
Electronic Industries Alliance;
http://global.ihs.com/index.cfm (for publications)
B-2
Computer Group Literature Center Web Site
Related Specifications
Table B-1. Related Specifications (continued)
B
Publication
Number
Document Title and Source
Versatile Backplane Bus: VMEbus
ANSI/IEEE
Standard 1014-1987
Institute of Electrical and Electronics Engineers, Inc.
OR
Microprocessor system bus for 1 to 4 byte data
Bureau Central de la Commission Electrotechnique Internationale
3, rue de Varembé
Geneva, Switzerland
IEEE Standard for Compact Embedded PC Modules
IEEE P996.1
IEEE - Common Mezzanine Card Specification (CMC)
Institute of Electrical and Electronics Engineers, Inc.
P1386 Draft 2.0
IEEE - PCI Mezzanine Card Specification (PMC)
Institute of Electrical and Electronics Engineers, Inc.
P1386.1 Draft 2.0
Bidirectional Parallel Port Interface Specification
Institute of Electrical and Electronics Engineers, Inc.
IEEE Standard 1284
PCI Industrial Manufacturers Group (PICMG) http://www.picmg.com/
Compact PCI Specification
CPCI Rev. 2.1
Dated 9/2/97
PCI-to-PCI Bridge Specification
PCI-ISA Specification
Rev. 1.02
Rev. 2.0
CompactPCI Hot Swap Specification
PIMCG 2.1 R1.0
PCI Industrial Computers Manufacturers Group (PICMG)
Peripheral Component Interconnect (PCI) Local Bus Specification,
Revision 2.0, 2.1, 2.2
PCI Local Bus
Specification
PCI Special Interest Group;
B-3
Related Documentation
URLs
B
The following URLs (uniform resource locators) may provide helpful
sources of additional information about this product, related services, and
development tools. Please note that, while these URLs have been verified,
they are subject to change without notice.
❏ Motorola Computer Group OEM Services,
❏ Technobox Inc.,
B-4
Computer Group Literature Center Web Site
Index
configurations
A
AC power input A-2
acoustic noise A-1
active/active 1-9
I/O 1-10
adapters, PMC 4-1
alarm board. See alarm display panel
altitude, operating A-1
connectors (CPV5350)
B
backplane
USB 2-21
connectors 6-6
reference 6-5
branch circuits, TNV 6-56
bridge connector slots 6-29
bus access in CPX8216T 1-4
bus connectors, H.110 6-37
bus segments 1-1
bus, PCI 2-2
connectors (CPV5350TM80)
Ethernet 5-33
parallel port 5-35
serial port 5-33
video 5-34
connectors (CPX750HA)
C
cables
debug 2-6
DC power cable 6-55
card cage reference 6-4
carrier card
diagram 3-2
features 3-1
USB 2-4
connectors (CPX750HATM)
chassis ID 1-13
circuit breakers 6-56
floppy port 5-12
I/O 5-5, 5-6
keyboard/mouse 5-10
parallel port 5-9
serial port 5-6, 5-7
transition module 5-4
COM connectors (CPV5350) 2-22
COM connectors (CPV5350TM80) 5-33
COM connectors (CPX750A) 2-5
COM connectors (CPX750HATM) 5-6
Compact Flash connector 2-14
CompactPCI board standards 6-5
CompactPCI connectors 6-11 to 6-35
IN-1
USB 5-10
connectors (CPX8216)
alarm 6-8
CPV5350TM80
CPU slot 6-17
fan module 6-7
floppy drive 6-8
HSC/bridge 6-29
I/O 6-11
I/O slot 6-26
IDE drive 6-9
power 6-10
keyboard/mouse/power LED
header 5-40
power supply 6-6
signal 6-11
connectors (CPX8216T)
bus, H.110 6-37
CPU 6-40
CPX750HA
fan module 6-7
HSC 6-40, 6-48
I/O 6-38, 6-50
power 6-7
transition module 6-50
connectors (CPX8540)
32-bit PCI 3-5, 3-7
64-bit (PMC) 3-8
I/O 3-4
controller, SCSI-2 4-1
conventions used in the manual xxiii
cooling A-1
CPU connectors, H.110 6-40
CPU module, features 1-12
CPU slot connectors 6-17
CPV5350
CPX750HATM
I
board connectors 2-18
component layout 2-19
Ethernet connector 2-21
features 2-16
indicator lights 2-16
keyboard/mouse connector 2-20
memory DIMM 2-20
N
D
E
X
keyboard/mouse connector 5-10
parallel port connector 5-9
PMC I/O connector 5-14
power connector 5-12
serial port configuration 5-2
serial port connectors 5-7
IN-2
Computer Group Literature Center Web Site
SIMs 5-16
speaker connector 5-13
USB connectors 5-10
CPX8216
fan module 6-7
flash memory 2-15
floppy port connector 5-12
front panel, CPV5350 2-16
front panel, CPX750HATM 5-6
bus access 1-4
CPU modules 1-12
standard system 1-2
subsystems 1-2
system description 1-1
CPX8216T
chassis ID 1-13
H.110 system 1-2
power connector
ring voltage 6-7
power connector 6-7
power distribution panel, DC 6-56
telephony bus 1-14
CPX8540
carrier card 3-1
features 3-1
floppy 5-38
D
DC power input A-2
debugging 2-6
USB 5-41
default conditions 1-6
device drivers 1-19
domains, HSC 6-29
domains, IDE drive 6-9
DRAM memory 2-20
DRAM mezzanine connector 2-10
dual HSC 1-6
hot swap controller 1-6
hot swap features
dual system 1-9
D
E
X
E
control status register 1-14
signals 1-14
staged pins 1-14
EIDE connector 5-11
electrical specifications, power supply A-2
environmental specifications A-1
ESD clips 6-4
hot swap process 1-16 to 1-19
HSC. See hot swap controller
http://www.motorola.com/computer/literature
IN-3
I
I/O connectors, H.110 6-38
I/O connectors, primary 6-11
I/O connectors, secondary 6-26
I/O devices 1-10
features 4-1
I/O interfaces, PCI bus 2-2
I/O slots 6-4
IDE drive connectors 6-9
initialization state 1-6
installing
output power A-3
fan module 6-7
PMC modules 3-2
SIMs 5-16
parallel port signals 5-9
PCI bus 2-2
ISA bus functions 2-2
I/O interfaces 2-2
peripherals, using in system 1-11
pin assignments
J
J10 connector 2-10
J11 connector 2-5
J15 connector 2-5
J17 connector 2-4
J18 connector 2-4
J19 connector 2-6
J8 connector 2-4
J9 connector 2-14
jumper settings
Flash selection 2-15
SCSI-2 4-3
alarm connector 6-8
CPX750HA
pin assignments (CPV5350)
Ethernet 2-21
keyboard/mouse 2-20
serial port 2-22
pin assignments (CPV5350TM80)
serial port 5-4
SIMs 5-16
fan tach 5-43
L
SM BUS/LM78 5-42
USB 5-41
video 5-34
LED indicator lights 2-16
LEDs, description 6-52
load-sharing configuration 1-9
logical system domains 1-1
I
N
D
E
X
M
manual conventions xxiii
memory banks 2-15
memory expansion 2-20
modules
pin assignments (CPX750HA)
COM1 2-5
debug 2-6
IN-4
Computer Group Literature Center Web Site
DRAM mezzanine 2-10
Ethernet 2-5
USB 2-4
pin assignments (CPX750HATM)
COM1/COM2 5-6
EIDE connector 5-11
floppy port 5-12
I/O connector 5-5, 5-6
keyboard/mouse 5-10
parallel port 5-9
dual input distribution panel 6-55
output A-3
power connector 5-12
serial port 5-7
speaker connector 5-13
pin assignments (CPX8216)
CPU slots 6-17
fan module 6-7
floppy connector 6-8
HSC/bridge 6-29
I/O 6-11
I/O slots 6-26
IDE drive 6-9
signal connectors 6-11
transition module slots 6-27
pin assignments (CPX8216T)
fan module 6-7
HSC 6-40 to 6-48
I/O connectors 6-50
pin assignments (CPX8540) 3-4 to 3-9
I/O 3-4
serial port
signals 5-7
PCI 32-bit 3-5, 3-7
PCI 64-bit 3-8
pin assignments (MPMC150) 4-4
PMC adapter pin assignments 4-4
PMC carrier card
expansion 2-2
features 3-1
I/O connector 5-14
PMC module
D
E
X
service switchover 1-13
setting the chassis ID 1-13
shock A-1
signal connectors 6-11
simplex configuration, power supplies 1-7
smart cable 6-55, 6-56
http://www.motorola.com/computer/literature
IN-5
speaker connector 5-13
specifications
Telephone Network Voltage (TNV) 6-56
termination, SCSI bus 4-3
transition module connectors,
(CPX8216T) 6-50
electrical A-2
environmental A-1
status indicators 2-16
status LEDs 1-13, 6-51
switch settings
MPMC150 4-3
PMC Adapter 4-3
system
architecture 1-4
device drivers 1-19
EIDE devices 1-11
peripherals 1-10
SCSI devices 1-11
simplex configuration 1-7
slots 6-4
USB connectors (CPX750HA) 2-4
USB connectors (CPX750HATM) 5-10
V
status LEDs 1-13, 6-51
system domains, description 1-1
vibration A-1
video connector 2-22
I
N
D
E
X
IN-6
Computer Group Literature Center Web Site
|
