Virtex-4 LX/SX
Prototype Platform
User Guide
UG078 (v1.2) May 24, 2006
R
P/N 0402226-06
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Table of Contents
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CD-ROM Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1. Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2. Power Supply Jacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3. Configuration Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. JTAG Termination Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6a. Upstream System ACE Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6b. Downstream System ACE Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6c. Upstream Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6d. Downstream Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. Prototyping Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8. VCCO-Enable Supply Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9. VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10. Oscillator Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
11. Differential Clock Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
12. DUT Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
13. Pin Breakout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
14. User LEDs (Active-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
15. PROGRAM Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
16. RESET Switch (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
17. DONE LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
18. INIT LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
19. Platform Flash ISPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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Preface
About This Guide
This user guide describes the features and operation of the Virtex™-4 prototype platform
and describes how to configure chains of FPGAs and serial PROMs.
Guide Contents
This manual contains one chapter:
•
Additional Resources
To find additional documentation, see the Xilinx website at:
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document:
Convention
Meaning or Use
Example
Messages, prompts, and
program files that the system
displays
Courier font
speed grade: - 100
Literal commands that you enter
in a syntactical statement
Courier bold
ngdbuild design_name
Commands that you select from
a menu
File → Open
Helvetica bold
Keyboard shortcuts
Ctrl+C
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Preface: About This Guide
Convention
Meaning or Use
Example
Variables in a syntax statement
for which you must supply
values
ngdbuild design_name
See the Development System
Reference Guide for more
information.
Italic font
References to other manuals
If a wire is drawn so that it
overlaps the pin of a symbol, the
two nets are not connected.
Emphasis in text
An optional entry or parameter.
However, in bus specifications, ngdbuild [option_name]
Square brackets [ ]
Braces { }
such as bus[7:0], they are
design_name
required.
A list of items from which you
must choose one or more
lowpwr ={on|off}
lowpwr ={on|off}
Separates items in a list of
choices
Vertical bar
|
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
Vertical ellipsis
.
.
.
Repetitive material that has
been omitted
Repetitive material that has
been omitted
allow block block_name
loc1 loc2 ... locn;
Horizontal ellipsis . . .
Online Document
The following conventions are used in this document:
Convention
Meaning or Use
Example
See the section “Additional
Resources” for details.
Cross-reference link to a location
in the current document
Blue text
Refer to “Title Formats” in
Chapter 1 for details.
Cross-reference link to a location See Figure 2-5 in the Virtex-II
Red text
in another document
Handbook.
Go to http://www.xilinx.com
for the latest speed files.
Blue, underlined text
Hyperlink to a website (URL)
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Virtex-4 LX/SX Prototype Platform
Package Contents
•
•
•
•
•
•
Xilinx Virtex™-4 prototype platform board
User guide
Device vacuum tool
Headers for test points
CD-ROM
One low-voltage, 14-pin, dual-inline package (DIP) crystal oscillator
CD-ROM Contents
•
User guide in PDF format
•
Example designs
♦
These designs include the Verilog source code, user constraints files (*.ucf),
documentation in PDF, and a readme.txt file
•
Bitstream files (*.bit) for each part type supported by the board (Bitstream synthesized
using Xilinx tools)
•
•
•
Full schematics of the board in both PDF format and ViewDraw schematic format
PC board layout in Pads PCB format
Gerber files in *.pho and *.pdf for the PC board (There are many free or shareware
Gerber file viewers available on the Web for viewing and printing these files)
Introduction
The Virtex-4 prototype platform and demonstration boards allow designers to investigate
and experiment with the features of Virtex-4 series FPGAs. This user guide describes the
features and operation of the Virtex-4 prototype platform, including how to configure
chains of FPGAs and serial PROMs.
Note: Prototype platforms are intended strictly for evaluating the functionality of Virtex-4 features
and are not intended for A/C characterization or high-speed I/O evaluation.
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Introduction
Features
•
•
•
•
Independent power supply jacks for VCCINT, VCCO, and VCCAUX
Selectable VCCO-enable pins for each SelectIO™ bank
Configuration port for use with Parallel Cable III and Parallel Cable IV cables
32 clock inputs
♦
♦
♦
4 differential clock pairs
4 LVTTL-type oscillator sockets
20 breakout clock pins
•
•
•
•
Power indicator LEDs
Onboard Platform Flash ISPROM (32 Mb) for configuration
Onboard power supplies for the Platform Flash ISPROM
JTAG port for reprogramming the XCF32P series reconfigurable ISPROM and the user
FPGA, also known as the device under test (DUT)
•
Upstream and downstream System ACE™ connectors and configuration interface
connectors
•
•
Onboard battery holder
One low-voltage, 14-pin, DIP crystal oscillators
The kit contains headers that can be soldered to the breakout area, if desired. These headers
are useful with certain types of oscilloscope probes for either connecting function
generators or wiring pins to the prototype area.
The Virtex-4 prototype platform (the board) contains a DUT FPGA and one In-System
Programmable Configuration PROM (ISPROM). The ISPROM can hold up to 33,554,432
bits. The DUT can be configured either from the ISPROM or from the configuration ports
(Parallel Cable III/IV cable).
In addition to the ISPROM and the configuration ports, there are upstream connectors and
downstream connectors. The upstream connectors can be connected to configure the DUT
by using the System ACE configuration solution or by chaining another board. The
downstream connectors can be used to connect to another board in a chain for serial
configuration. A maximum of two boards can be chained together.
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Introduction
Figure 1 shows a block diagram of the board.
2x Diff Pair
Clocks
Upstream
Interface
Connector
Upstream
System ACE
Interface
2x
SMA
SMA
LVTTL
Connector
Configuration
Port
To Test Points
on All Pins
Virtex-4 DUT
LEDs
PROGRAM
User RESET
VBATT
DONE
LED
INIT
LED
Downstream
System ACE
Interface
LVTTL
2x
SMA
SMA
Downstream
Interface
Connector
Connector
2x Diff Pair
Clocks
Power Bus and Switches
5V Jack -or- 5V Brick
VCCINT
VCCO
VCC Jack
VCCO Jack
VCCAUX Jack
VCCAUX
VCC3
VCC1V8
AVCC
UG078_01_101204
Figure 1: Virtex-4 LX/SX Prototype Platform Block Diagram
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Detailed Description
Detailed Description
numbered sections that follow.
6a
6c
4
11
10
9
1
13
3
2
19
13
13
12
13
8
7
14
17
16
5
18
15
6b
6d
UG078_02_101904
Figure 2: Detailed Description of Virtex-4 LX/SX Prototype Platform Components
1. Power Switch
The board has an onboard power supply and an ON|OFF power switch. When lit, a green
LED indicates power from the power brick connector or the 5V jack.
On Position
In the ON position, the power switch enables delivery of all power to the board by way of
voltage regulators situated on the backside of the board. These regulators feed off a 5V
external power brick or the 5V power supply jack.
The voltage regulators deliver fixed voltages. Maximum current range for each supply will
power supply. If the current exceeds maximum ratings, use the power jacks to supply
power to the DUT.
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Detailed Description
Table 1: Voltage Ranges
Label Maximum Voltage
VCCINT
Maximum Current
1.2V
3.3V
2.5V
3.3V
1.8V
2.5V
1A
2A
VCCO
VCCAUX
VCC
1.5A
2A
VCC1V8
AVCC
1A
25 mA
Off Position
In the OFF position, the power switch disables all modes of powering the DUT.
Power Enable Jumpers
For each power supply there are headers marked SUPPLY on one side and JACK on the
other side. Appropriate placements of jumpers on these headers enables delivery of all
power from either the onboard regulators or the three power supply jacks marked
VCCINT, VCCO, and VCCAUX.
2. Power Supply Jacks
One method of delivering power to the DUT is by way of the power supply jacks. (Consult
voltage rating for each device you are using.) The power supply jacks are:
•
VCCINT
♦
Supplies voltage to the VCCINT of the DUT
•
VCCO
♦
♦
Supplies I/O voltages to the DUT
Each bank can be powered from one of two sources (VCCO, VCCINT) by
appropriate placement of jumpers on the header
•
VCCAUX
Supplies voltage to the VCCAUX DUT pins
♦
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Detailed Description
3. Configuration Ports
These headers can be used to connect a Parallel Cable III or Parallel Cable IV cable to the
on the board.
Table 2: Serial Mode
Configuration Port Header
Parallel Cable III/IV Pins
VCC3
GND
CCLK
DONE
DIN
VCC
GND
CCLK
D/P
DIN
PROG
INIT
PROG
Table 3: JTAG Mode
Configuration Port Header
Parallel Cable IV Connector
Parallel Cable III Pins
Parallel Cable IV Pins
VCC3V3
GND
TMS
VCC
GND
TMS
TDI
VCC
GND
TMS
TDI
TDI
TDO
TCK
TDO
TCK
TDO
TCK
INIT
INIT
UP
DN
TDI
PROM
TDO
TMS
TCK
TDO
TDI
DUT
TDO
UG078_03_082404
Figure 3: JTAG Chain Termination
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Detailed Description
4. JTAG Chain
Jumper J17 provides the ability to have the Virtex-4 in the JTAG chain or remove it from the
JTAG chain.
Note: The Virtex-4 device must not be in the socket when detecting the ISPROM in the chain.
5. JTAG Termination Jumper
The DUT TDO pin can be jumpered to the TDO TERM pin or the downstream TDO pin.
When another board is connected to the downstream System ACE connector or
downstream interface connector, jumper the DUT TDO pin to the downstream TDO pin
for serial chaining. The connection allows the DUT TDO pin to be connected to the next
device in the chain.
The TCK and TMS pins are parallel feedthrough connections from the upstream
System ACE interface connector to the downstream System ACE interface connector and
drive the TCK and TMS pins of the onboard PROM and the DUT.
Note: The termination jumper must be in place on the last board in the chain to connect the TDO pin
of the final device to the TDO feedback chain.
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Detailed Description
6a. Upstream System ACE Interface Connector
configure the DUT. Any JTAG configuration stream can source this connector. For
example, a System ACE controller with a CompactFlash card can be used to generate very
large JTAG streams for configuring multiple Virtex-4 prototype platforms using the
downstream System ACE interface connector.
GND
UPSTREAM_TDO
UPSTREAM_TDI
GND
GND
UPSTREAM_TMS
NC
UPSTREAM_TCK
GND
VCC_TMP
19 17 15 13 11 9
7
5
6
3
4
1
2
20 18 16 14 12 10 8
VCC_TMP
VCC_TMP
VCC_TMP
VCC_TMP
GND
VCC3_EN
VCC3_EN
VCC3_EN
VCC3_EN
GND
UG078_04_051004
Figure 4: Upstream System ACE Interface Connector (20-Pin Female)
6b. Downstream System ACE Interface Connector
configuration information to a DUT in a downstream prototype platform board from
sources such as a Parallel Cable III cable or an upstream System ACE interface connector.
GND
VCC_TMP
VCC_TMP
VCC_TMP
VCC_TMP
GND
VCC3_EN
VCC3_EN
VCC3_EN
VCC3_EN
20 18 16 14 12 10 8
6
5
4
3
2
1
19 17 15 13 11 9
7
VCC_TMP
GND
DOWNSTREAM_TCK
GND
NC
DOWNSTREAM_TMS
GND
DOWNSTREAM_TDI
GND
DOWNSTREAM_TDO
UG078_05_051004
Figure 5: Downstream System ACE Interface Connector (20-Pin Male)
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Detailed Description
6c. Upstream Interface Connector
select map or slave-serial mode. This connector can be sourced by a downstream interface
connector of another prototype platform board.
GND
GND
GND
NC
AFX_M2
AFX_M1
AFX_M0
NC
GND
GND
GND
GND
NC
NC
NC
GND
NC
NC
NC
NC
CS_B
NC
TMS
TDI
DIN
D1
TDO
D2
TCK
D3
NC
D4
NC
D5
NC
D6
DOUT_BUSY
INIT
D7
DONE
CCLK
NC
PROG
RW_B
UG027_06_051004
Figure 6: Upstream Interface Connector (44-Pin Female)
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Detailed Description
6d. Downstream Interface Connector
information to the DUT in the downstream prototype platform board.
NC
NC
CLK
PROG
DONE
INIT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TCK
TDO
NC
DOWNSTREAM_TDI
TMS
DOUT_BUSY
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
GND
GND
GND
GND
GND
GND
NC
UG027_07_051004
Figure 7: Downstream Interface Connector (44-Pin Male)
7. Prototyping Area
The prototyping area accommodates 0.10-inch spaced ICs. The kit contains headers that
can be soldered to the breakout area, if desired. Power and ground buses are located at the
top and bottom edges, respectively, of the prototyping area.
8. VCCO-Enable Supply Jumpers
Virtex-4 series devices have 9 to 17 SelectIO banks, labeled 0 through 16, each with a
VCCO-enable supply jumper. The VCCO-enable supply jumpers can connect each bank to
one of the two onboard supplies, VCCINT or the VCCO supply. These jumpers must be
installed for the Virtex-4 device to function normally.
9. VBATT
An onboard battery holder is connected to the VBATT pin of the DUT. If an external power
supply is used, the associated jumper must be removed and instead use a 12 mm lithium
coin battery (3V).
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Detailed Description
10. Oscillator Sockets
The board has four crystal oscillator sockets, all wired for standard LVTTL-type oscillators.
termination resistors can be changed by the user. The oscillator sockets accept both half-
and full-sized oscillators and are powered by the DUT VCCO power supply.
Table 4: Oscillator Socket Clock Pin Connections for SF363 and FF668
SF363
FF668
Pin
Number
Pin
Number
Label
OSC
Clock Name
Clock Name
Socket
Top 1
IO_L1N_GCLK_CC_LC_3
IO_L1P_GCLK_CC_LC_3
IO_L1P_GCLK_CC_LC_4
IO_L1N_GCLK_CC_LC_4
A11
B12
IO_L1N_GCLK_CC_LC_3
IO_L1P_GCLK_CC_LC_3
IO_L1P_GCLK_CC_LC_4
IO_L1N_GCLK_CC_LC_4
B14
B15
OSC
Socket
Top 2
OSC
Socket
Bottom 1
W13
W12
AF12
AE12
OSC
Socket
Bottom 2
Table 5: Oscillator Socket Clock Pin Connections for FF1148 and FF1513
FF1148 FF1513
Pin
Number
Pin
Number
Label
Clock Name
Clock Name
OSC
Socket
Top 1
IO_L1N_GCLK_CC_LC_3
IO_L1P_GCLK_CC_LC_3
IO_L1P_GCLK_CC_LC_4
IO_L1N_GCLK_CC_LC_4
G18
F18
IO_L1N_GCLK_CC_LC_3
IO_L1P_GCLK_CC_LC_3
IO_L1P_GCLK_CC_LC_4
IO_L1N_GCLK_CC_LC_4
N20
P20
OSC
Socket
Top 2
OSC
Socket
Bottom 1
AF18
AE18
AH20
AH19
OSC
Socket
Bottom 2
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Detailed Description
11. Differential Clock Inputs
In addition to the oscillator sockets, there are eight 50Ω SMA connectors that allow
connection to an external function generator. These connect to the DUT clock pads as
differential clock pairings (DIFFERENTIAL PAIRS) are as shown in the tables.
Table 6: SMA Clock Pin Connections for SF363 and FF668
SF363
FF668
Pin
Number
Pin
Number
Label
Clock Name
Clock Name
N
P
IO_L8N_GC_LC_3
B7
A7
IO_L8N_GC_LC_3
C12
C13
IO_L8P_GC_LC_3
IO_L8P_GC_LC_3
N
P
IO_L2N_GC_VRP_LC_3
IO_L2P_GC_VRN_LC_3
IO_L2N_GC_LC_4
B9
IO_L2N_GC_VRP_LC_3
IO_L2P_GC_VRN_LC_3
IO_L2N_GC_LC_4
A11
A10
W5
Y5
A12
N
P
AB10
AC10
AD11
AD12
IO_L2P_GC_LC_4
IO_L2P_GC_LC_4
N
P
IO_L8N_GC_CC_LC_4
IO_L8P_GC_CC_LC_4
W8
W9
IO_L8N_GC_CC_LC_4
IO_L8P_GC_CC_LC_4
Table 7: SMA Clock Pin Connections for FF1148 and FF1513
FF1148
FF1513
Pin
Pin
Number
Label
Clock Name
Clock Name
Number
G16
N
P
IO_L8N_GC_CC_LC_3
IO_L8P_GC_CC_LC_3
IO_L2N_GC_VRP_LC_3
IO_L2P_GC_VRP_LC_3
IO_L2N_GC_LC_4
IO_L8N_GC_CC_LC_3
IO_L8P_GC_CC_LC_3
IO_L2N_GC_VRP_LC_3
IO_L2P_GC_VRP_LC_3
IO_L2N_GC_LC_4
K21
L21
G17
N
P
J17
K19
H17
J19
N
P
AF16
AG16
AH17
AJ17
AF18
AF19
AJ19
AK19
IO_L2P_GC_LC_4
IO_L2P_GC_LC_4
N
P
IO_L8N_GC_CC_LC_4
IO_L8P_GC_CC_LC_4
IO_L8N_GC_CC_LC_4
IO_L8P_GC_CC_LC_4
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Detailed Description
12. DUT Socket
The DUT socket contains the user FPGA, referred to as the device under test (DUT). The
DUT must be oriented using the P1 indicator on the board.
Caution! Failure to insert the device to the proper orientation can damage the device. To avoid
pin damage, always use the vacuum tool provided when inserting or removing the Virtex-4
device. When using BGA packages, do not apply pressure to the device while activating the
socket. Doing so can damage the socket and/or the device.
13. Pin Breakout
The pin breakout area is used to monitor or apply signals to each of the DUT pins. Headers
can be soldered to the breakout area to use with certain types of oscilloscope probes, for
either connecting function generators or wiring pins to the pin breakout area. Clocks in the
Table 8: Breakout Clock Pin Connections for SF363 and FF668
SF363
FF668
Pin
Number
Pin
Number
Label
Clock Name
Clock Name
IO_L4P_GC_LC_3
B10
C10
B13
A13
A8
IO_L4P_GC_LC_3
B13
B12
IO_L4N_GC_VREF_LC_3
IO_L5P_GC_LC_3
IO_L4N_GC_VREF_LC_3
IO_L5P_GC_LC_3
A16
IO_L5N_GC_LC_3
IO_L6P_GC_LC_3
IO_L5N_GC_LC_3
IO_L6P_GC_LC_3
A15
A10
IO_L6N_GC_LC_3
IO_L7P_GC_LC_3
B8
IO_L6N_GC_LC_3
IO_L7P_GC_LC_3
B10
B14
A14
C11
B11
Y6
B17
IO_L7N_GC_LC_3
IO_L3P_GC_LC_3
IO_L7N_GC_LC_3
IO_L3P_GC_LC_3
A17
C14
IO_L3N_GC_LC_3
IO_L4P_GC_LC_4
IO_L3N_GC_LC_3
IO_L4P_GC_LC_4
C15
AF11
AF10
AE14
AE13
AE10
AD10
AD17
AD16
AB17
AC17
IO_L4N_GC_VREF_LC_4
IO_L5P_GC_LC_4
W6
W11
W10
Y7
IO_L4N_GC_VREF_LC_4
IO_L5P_GC_LC_4
IO_L5N_GC_LC_4
IO_L6P_GC_LC_4
IO_L5N_GC_LC_4
IO_L6P_GC_LC_4
IO_L6N_GC_LC_4
IO_L7P_GC_VRN_LC_4
IO_L7N_GC_VRP_LC_4
IO_L3P_GC_CC_LC_4
IO_L3N_GC_CC_LC_4
W7
Y10
Y9
IO_L6N_GC_LC_4
IO_L7P_GC_VRN_LC_4
IO_L7N_GC_VRP_LC_4
IO_L3P_GC_CC_LC_4
IO_L3N_GC_CC_LC_4
Y12
Y11
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Detailed Description
Table 9: Breakout Clock Pin Connections for FF1148 and FF1513
FF1148 FF1513
Pin
Number
Pin
Number
Label
Clock Name
Clock Name
IO_L4P_GC_LC_3
E13
E17
IO_L4P_GC_LC_3
J21
J20
IO_L4N_GC_VREF_LC_3
IO_L5P_GC_LC_3
IO_L4N_GC_VREF_LC_3
IO_L5P_GC_LC_3
K18
M21
M20
L20
IO_L5N_GC_LC_3
IO_L6P_GC_LC_3
K17
IO_L5N_GC_LC_3
IO_L6P_GC_LC_3
E16
IO_L6N_GC_LC_3
IO_L7P_GC_LC_3
F16
IO_L6N_GC_LC_3
IO_L7P_GC_LC_3
L19
K19
P22
IO_L7N_GC_LC_3
IO_L3P_GC_LC_3
J19
IO_L7N_GC_LC_3
IO_L3P_GC_LC_3
P21
H19
N22
IO_L3N_GC_LC_3
IO_L4P_GC_LC_4
H18
IO_L3N_GC_LC_3
IO_L4P_GC_LC_4
M22
AG20
AF20
AL20
AL19
AH18
AG18
AL21
AK21
AJ21
AJ20
AK18
AK17
AG18
AG17
AE17
AE16
AJ19
AK19
AH19
AH18
IO_L4N_GC_VREF_LC_4
IO_L5P_GC_LC_4
IO_L4N_GC_VREF_LC_4
IO_L5P_GC_LC_4
IO_L5N_GC_LC_4
IO_L6P_GC_LC_4
IO_L5N_GC_LC_4
IO_L6P_GC_LC_4
IO_L6N_GC_LC_4
IO_L7P_GC_VRN_LC_4
IO_L7N_GC_VRP_LC_4
IO_L3P_GC_CC_LC_4
IO_L3N_GC_CC_LC_4
IO_L6N_GC_LC_4
IO_L7P_GC_VRN_LC_4
IO_L7N_GC_VRP_LC_4
IO_L3P_GC_CC_LC_4
IO_L3N_GC_CC_LC_4
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Detailed Description
14. User LEDs (Active-High)
There are 16 active-high user LEDs on the board. Before configuration, the LEDs reflect the
status of the configuration mode pins. During configuration, the LEDs are in a high-
impedance condition. After configuration, the LEDs are available to the user and reflect the
status of pins D0-D7 and D24-D31 (corresponding to LED 0- LED 15). The LED
Table 10: LED Assignments and Corresponding I/O
Pin Number For Package Type
LED
0
After Configuration
SF363
U9
FF668
AD13
AC13
AC15
AC16
AA11
AA12
AD14
AC14
D13
FF1148
G13
F13
FF1513
B16
1
V10
V11
U12
V8
A16
R22
T23
2
J21
3
H22
H13
H14
M20
N20
K14
J14
4
G15
G16
N24
M25
H15
J16
5
V9
6
V12
V13
D6
7
Available as user LEDs
8
9
E7
D14
10
11
12
13
14
15
E14
D15
F6
F15
D21
E21
D26
E26
F16
F11
L14
L16
E6
F12
L15
K16
F25
E15
F15
F13
N18
N19
F14
F26
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Detailed Description
15. PROGRAM Switch
The active-low PROGRAM switch, when pressed, grounds the program pin on the DUT.
16. RESET Switch (Active-Low)
The RESET switch connects to a standard I/O pin on the DUT, allowing the user, after
configuration, to reset the logic within the DUT. When pressed, this switch grounds the
pin.
Table 11 shows the INIT pin locations for the available DUT package types.
Table 11: User Hardware and Corresponding I/O Pins
Pin Number For Package Type
Label
SF363
FF668
FF1148
FF1513
RESET
R16
W24
AP21
AH23
Note: Refer to the readme.txt file for implementation of this user pin.
17. DONE LED
The DONE LED indicates the status of the DONE pin on the DUT. This LED lights when
DONE is high or if power is applied to the board without a part in the socket.
18. INIT LED
The INIT LED lights during initialization.
19. Platform Flash ISPROM
A 32-Mb Platform Flash In-System Programmable Configuration PROM (ISPROM) is
description.
Table 12: Platform Flash ISPROM Configuration
Label
Description
J46
Provides power to the ISPROM. These jumpers must be installed for proper
operation of the ISPROM.
J45
J43
Sets the design revision control for the ISPROM.
Enables or disables the ISPROM by placing the address counter in reset and
DATA output lines in high-impedance state.
J42
J8
Sets the ISPROM for serial or select map configuration.
Selects one of two modes of CCLK operation:
• ISPROM provides CCLK (PROM CLKOUT)
• FPGA provides CCLK (FPGA CCLK)
22
Virtex-4 LX/SX Prototype Platform
UG078 (v1.2) May 24, 2006
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