Data Book
32bit Micro controller
TLCS-900/H1 series
TMP92CZ26AXBG
TENTATIVE
It’s first version technical data sheet.
Since this revision 0.2 is still under working, there may
be some mistakes in it.
When you will start to design, please order the latest
one.
Rev0.2
09/Dec./2005
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3.12 8 bit timers (TMRA) ･･････････････････････････････････ 92CZ26A-266
3.13 16 bit timer (TMRB) ･･････････････････････････････････ 92CZ26A-294
3.14 Serial channel (SIO) ･･････････････････････････････････ 92CZ26A-315
3.15 Serial Bus Interface (SBI) ･････････････････････････････ 92CZ26A-344
3.16 USB controller ･･････････････････････････････････････
92CZ26A-366
3.17 SPIC (SPI controller) ･････････････････････････････････ 92CZ26A-477
3.18 I2S ･････････････････････････････････････････････････ 92CZ26A-496
3.19 LCD controller (LCDC) ･･･････････････････････････････ 92CZ26A-508
3.20 Touch screen interface (TSI) ･･････････････････････････ 92CZ26A-564
3.21 Real time clock (RTC) ････････････････････････････････ 92CZ26A-574
3.22 Melody/Alarm generator ･･･････････････････････････････ 92CZ26A-589
3.23 Analog/Digital Converter ･････････････････････････････ 92CZ26A-595
3.24 Watch dog timer ････････････････････････････････････
92CZ26A-615
3.25 Power Management Circuit (PMC) ････････････････････ 92CZ26A-619
3.26 Multiply and Accumulate Calculation unit (MAC) ･･･････ 92CZ26A-628
3.27 Debug mode ･････････････････････････････････････････ 92CZ26A-633
4. Electrical Characteristics ･･･････････････････････････････････ 92CZ26A-640
5. Table of Special function registers (SFRs) ･････････････････････ 92CZ26A-665
6. Package ････････････････････････････････････････････････････ 92CZ26A-748
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TMP92CZ26A
CMOS 32-Bit Micro controllers
TMP92CZ26AXBG
1. Outline and Features
TMP92CZ26A is high-speed advanced 32-bit micro-controller developed for controlling equipment which
processes mass data.
TMP92CZ26AXBG is housed in a 228-pin BGA package.
(1) CPU : 32-bit CPU(High-speed 900/H1 CPU)
•
•
•
•
Compatible with TLCS-900/L1 instruction code
16Mbytes of linear address space
General-purpose register and register banks
Micro DMA : 8channels (62.5ns/4 bytes at fSYS = 80MHz, best case)
(2) Minimum instruction execution time : 12.5ns ( at fSYS = 80MHz)
(3) Internal RAM: 288K-byte (can be used for program, data and display memory)
Internal ROM: 8 K-byte(memory for Boot only)
It enables that load user program from USB, UART to Internal RAM.
92CZ26A-1
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TMP92CZ26A
(4) External memory expansion
•
•
Expandable up to 3.1G bytes (shared program/data area)
Can simultaneously support 8/16-bit width external data bus
…… Dynamic data bus sizing
•
Separate bus system
(5) Memory controller
•
•
Chip select output
: 4 channel
One channel in 4 channels is enabled detailed AC enable setting
(6) 8-bit timers
: 8 channels
: 2 channel
(7) 16-bit timer/event counter
(8) General-purpose serial interface : 1 channels
•
•
UART/synchronous mode
IrDA ver1.0 (115.2 kbps) selectable :
(There is the restriction in the setting baud rate when use this function together other functions)
(9) Serial bus interface: 1 channel
I2C bus mode only
•
(10) USB (universal serial bus) controller: 1 channel
•
•
•
Support to USB (REV1.1)
Full-speed (12 Mbps) (Low-speed is not supported.)
Endpoint 0: Control 64 bytes × 1-FIFO
Endpoint 1: BULK (output) 64 bytes × 2-FIFO
Endpoint 2: BULK (input) 64 bytes × 2-FIFO
Endpoint 3: Interrupt (input) 8 bytes × 1-FIFO
Descriptor RAM: 384 bytes
•
(11) I2S (Inter-IC Sound)interface: 2 channel
•
•
•
I2S bus mode selectable (Master, transmission only)
Data Format is supported Left/Right Justify
Built in FIFO buffer of 128 bytes (64 bytes × 2) every each channels.
(12) LCD controller
•
•
•
•
Supported up to monochrome, 4, 16 and 64 gray levels and 256/4096 color for STN
Supported up to 4096/65536/262144/16777216 color for TFT
Supported up to PIP (Picture In Picture Display)
Supported up to H/W Rotation function for support to various LCDM
(13) SDRAM controller :1 channel
•
•
Supported 16M, 64M, 128M, 256M and 512Mbit SDR (Single-data-rate) SDRAM
Can use not only as Data RAM for LCD display but also operate program direct from SDRAM
(14) Timer for real-time clock (RTC)
Based on TC8521A
•
(15) Key-on wakeup (Interrupt key input)
(16) 10-bit A/D converter (Built in Sample Hold circuit)
: 6 channels
92CZ26A-2
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TMP92CZ26A
(17) Touch screen interface
•
Built-in Switch of Low-resistor, and available to delete external components for shift change
row/column
(18) Watch dog timer
(19) Melody/alarm generator
•
•
•
Melody: Output of clock 4 to 5461Hz
Alarm: Output of the 8 kinds of alarm pattern
5 kinds of interval interrupt
(20) MMU
•
•
Expandable up to 3.1G bytes (3 local area/8 bank method)
Independent bank for each Program, Read-data, Write-data, Source and Destination of DMAC (Odd
channel/Even channel) and LCD-display-data
(21) Interrupts: 56 interrupts
•
•
•
9 CPU interrupts
……
……
……
Software interrupt instruction and illegal instruction
Seven selectable priority levels
38 internal interrupts
9 external interrupts
Seven selectable priority levels
(8 interrupt selectable negative/positive of edge)
(22) DMAC function: 6 channels
High-speed data transfer enable by controlling which convert micro DMA function and this function
•
(23) Input/Output ports : 136 pins (Except Data bus (16bit), Address bus (24bit) and RD pin)
(24) Nand_Flash interface: 2 channel
•
•
•
•
Available to connect directly with NAND flash
Supported up to SLC type and MLC type
Data Bus 8/16 Bit, Page Size 512/2048 Bytes
Built-in Rees Solomon calculation circuits which enabled correct 4-address, and detect error more
than 5-address
(25) SPI controller : 1 channel
•
•
Supported up to SPI mode of SD card and MMC card
Built-in FIFO buffer of 32 bytes to each Input/Output
(26) Product/Sum calculation: 1 channel
•
•
calculation 32×32+64 =64Bit , 64-32×32 = 64Bit , 32×32-64 =64Bit
I/O method
(27) Signed calculation is supported.
92CZ26A-3
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TMP92CZ26A
(28) Stand-by function
•
•
•
Three Halt modes
: IDLE2 (programmable), IDLE1, STOP
Each pin status programmable for stand-by mode
Built-in power supply management circuits (PMC) for leak current provision
(29) Clock controller
•
Built-in two blocks of clock doubler (PLL). PLL supplies 48 MHz for USB and 80 MHz for CPU from
10MHz
•
•
Clock gear function: Selectable high-frequency clock fc to fc/16
Clock for Timer (fs = 32.768 kHz)
(30) Operating voltage:
•
•
Internal V = 1.5V, External I/O Vcc = 3.0 to 3.6 V
CC
2 power supplies (Internal power supply (1.4 to 1.6), External power supply (3.0 to 3.6)
(31) Package
228 pin FBGA :P-FBGA228-1515-0.80A5
•
92CZ26A-4
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TMP92CZ26A
DVCC3A [12]
DVCC3B [1]
DVCC1A [5]
DVCC1B [1]
DVSSCOM
(AN0 to AN1)PG0 to PG1
(AN2, MX)PG2
(AN3, MY, ADTRG )PG3
(AN4 to AN5)PG4 to PG5
10-bit 6ch
AD
Converter
900/H1 CPU
AVCC, AVSS
VREFH, VREFL
DVCC1C [1]
DVSS1C [1]
X1
PLL
XWA
XBC
XDE
XHL
XIX
W
A
C
E
L
H-OSC
Touch Screen
X2
(PX, INT4)P96
(PY)P97
B
I/F
(TSI)
Clock gear
D
XT1
XT2
RESET
DBGE
AM [1:0]
L-OSC
(TXD0)P90
H
IX
SERIAL I/O
SIO0
(RXD0)P91
(CTS0, SCLK0)P92
(I2S0CKO)PF0
(I2S0DO)PF1
(I2S0WS)PF2
(I2S1CKO)PF3
(I2S1DO)PF4
(I2S1WS)PF5
I2S
XIY
IY
(I2S0)
PZ0 (EI_PODDATA)
PZ1 (EI_SYNCLK)
PZ2 (EI_PODREQ)
PZ3(EI_REFCLK)
PZ4(EI_TRGIN)
PZ5(EI_COMRESET)
PZ6(EO_MCUDATA)
PZ7(EO_MCUREQ)
XIZ
IZ
I2S
XSP
SP
(I2S1)
32bit
SR
DSU
PMC
SBI (I2Cbus)
(SDA)PV6
(SCL)PV7
F
D+
D -
P C
USB
PM7 (PWE)
Controller
(X1USB) PX5
PC0 (INT0)
PC2 (INT2)
8BIT TIMER
(TMRA0)
Interrupt
Controller
WATCH-DOG TIMER
MMU
(TA0IN, INT1)PC1
(TA1OUT, MLDALM)PM1
(TA2IN, INT3)PC3
(TA3OUT)PP1
8BIT TIMER
(TMRA1)
D0 to D7
P10 to P17 (D8 to D15)
PORT1
8BIT TIMER
(TMRA2)
P40 to P47 (A0 to A7)
P50 to P57 (A8 to A15)
P60 to P67 (A16 to A23)
PORT4
PORT5
PORT6
8BIT TIMER
(TMRA3)
MAC
8BIT TIMER
(TMRA4)
DMAC
8BIT TIMER
(TMRA5)
P70 (RD )
P73 (EA24)
(TA5OUT)PP2
PORT7
PORT8
8BIT TIMER
(TMRA6)
P74 (EA25)
P75(R/ W , NDR/B )
P76 ( WAIT )
P80 ( CS0 )
P81 ( CS1 , SDCS )
P82 ( CS2 , CSZA , SDCS )
P83 ( CS3 , CSXA )
P84 ( CSZB )
8BIT TIMER
(TMRA7)
(TA7OUT, INT5)PP3
16BIT TIMER
(TMRB0)
(TB0IN0, INT6)PP4
(TB0OUT0)PP6
(TB1IN0, INT7)PP5
(TB1OUT0)PP7
16BIT TIMER
(TMRB1)
P85 ( CSZC )
(SPDI)PR0
(SPDO)PR1
( SPCS ) PR2
(SPCLK)PR3
SPI
Controller
P71 ( WRLL , NDRE )
P72 ( WRLU , NDWE )
P86 ( CSZD , ND0CE )
NAND-FLASH
I/F (2ch)
288KB RAM
P87 (
CSXB ND1CE
,
)
(LCP0)PK0
(LLOAD)PK1
PJ5 (NDALE)
PJ6 (NDCLE)
(LFR)PK2
PA0 to PA7 (KI0 to KI7)
PN0 to PN7 (KO0 to KO7)
PC7 (KO8)
(LVSYNC)PK3
(LHSYNC)PK4
(LGOE2 to 0)PK7 to 5
(LD7 to 0)PL7 to 0
(LD15 to 8)PT7 to 0
(LD22 to 16)PU6 to 0
(LD23, EO_TRGOUT)PU7
(CLKOUT, LDIV)PX4
PX7
( SDRAS , SRLLB )PJ0
( SDCAS , SRLUB )PJ1
( SDWE , SRWR )PJ2
KEY-BOARD
I/F
LCD
Controller
BOOT ROM 8KB
PM2 ( ALARM , MLDALM )
RTC
MELODY/
ALARM-OUT
PV3
PV4
PORTV
PV0 (SCLK0)
PV1
PV2
SDRAM
Controller
(SDLLDQM)PJ3
(SDLUDQM)PJ4
(SDCKE)PJ7
PW7 to 0
PC4 (EA26)
PC5 (EA27)
PC6 (EA28)
(SDCLK)PF7
Figure 1.1 Block Diagram of TMP92CZ26A
92CZ26A-5
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TMP92CZ26A
2. Pin Assignment and Pin Functions
The assignment of input/output pins for TMP92CZ26A, their names and functions are as follows;
2.1 Pin Assignment Diagram (Top View)
Figure 2.1.1 shows the pin assignment of the TMP92CZ26A.
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17
D1 D2 D3
D5 D6 D7 D8 D9 D10 D11 D12 D13
D15 D16 D17
E14 E15 E16 E17
F14 F15 F16 F17
G14 G15 G16 G17
H14 H15 H16 H17
J14 J15 J16 J17
K14 K15 K16 K17
L14 L15 L16 L17
M14 M15 M16 M17
N14 N15 N16 N17
P15 P16 P17
E1 E2 E3 E4
F1 F2 F3 F4
G1 G2 G3 G4
H1 H2 H3 H4
J1 J2 J3 J4
K1 K2 K3 K4
L1 L2 L3 L4
M1 M2 M3 M4
N1 N2 N3 N4
P1 P2 P3
F6 F7 F8 F9 F10 F11
G6 G7
H6
G12
H12
J12
K12
L12
J6
TMP92CZ26A
P-FBGA228
K6
L6
TOP VIEW
M6 M7 M8 M9 M10 M11 M12
P5 P6 P7 P8 P9 P10 P11 P12 P13
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17
U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17
Figure 2.1.1 Pin assignment diagram (P-FBGA228)
4 balls of A1, A17, U1 and U17 (most outside 4 corner of BGA package) are Dummy Balls.
These balls are not connected with internal LSI chip, electrical characteristics.
A1 and U1, A17 and U17 are shorted in internal package. It is recommended that using to
OPEN check of mounting if mounting this LSI to Target board.
Example: If checking signal (or voltage) via A1-U1-U17-A17, short U17 and U1 on Target board
beforehand, and input signal (or voltage) from A1, and check voltage of A17.
92CZ26A-6
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TMP92CZ26A
Table 2.1.1 Pin number and the name
Ball
No.
Ball
No.
Ball
Ball
No.
Pin name
Dummy1
Pin name
Pin name
PT5,LD13
Pin name
No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
D9
P73,EA24
J15
J16
J17
K1
P15
P16
P17
R1
R2
R3
PK4,LHSYNC
PG2,AN2, MX
PA6,KI6
D10 PF4,I2S1DO
D11 PF7,SDCLK
D12 PJ4,SDLUDQM
P47,A7
P13,D11
P46,A6
P14,D12
PA5,KI5
PN3,KO3
PN4,KO4
PN5,KO5
PN6,KO6
DVCC3A2
DVCC3A7
PT4,LD12
PT3,LD11
P45,A5
X2
PA3,KI3
D13 P85,
K2
PC7,KO8
CSZC
PA1,KI1
D15 PU6,LD22
D16 P61,A17
D17 P60,A16
K3
PC3,INT3,TA2IN
PX5,X1USB
PP7,TB1OUT0
PP1,TA3OUT
PP3,INT5,TA7OUT
PP5,INT7,TB1IN0
DVCC1A5
PF1,I2S0DO
PJ6,NDCLE
K4
R4
R5
R6
R7
R8
R9
K6
E1
E2
E3
E4
P96,PX,INT4
PW1
K12
K14
K15
K16
K17
L1
A10 PJ1,
A11 P87,
A12 P83,
A13 P81,
A14 P72,
A15 P70,
,
SDCAS SRLUB
,
PW2
CSXB ND1CE
,
PW3
PR2,
SPCS
CS3 CSXA
,
E14 PU7,LD23,EO_TRGOUT
E15 PU4,LD20
P44,A4
R10 PX7
CS1 SDCS
,
PK2,LFR
PN7,KO7
PM1,MLDALM,TA1OUT
PM7,PWE
DVSS3
R11 PZ0,EI_PODDATA
R12 PZ2,EI_PODREQ
R13 PZ4,EI_TRGIN
R14 PZ6,EO_MCUDATA
R15 PZ7,EO_MCUREQ
R16 P15,D13
NDWE
WRLU
RD
E16 P57,A15
L2
A16 P65,A21
A17 Dummy3
E17 P56,A14
L3
F1
F2
F3
F4
F6
F7
F8
F9
DVCC1B1
PW6
L4
B1
B2
B3
B4
B5
B6
B7
B8
B9
VREFH
L6
PG5,AN5
PW5
L12
L14
L15
L16
L17
M1
M2
M3
M4
M6
M7
M8
M9
M10
M11
M12
M14
M15
M16
M17
N1
DVSS7
PG3,AN3,MY,
PA7,KI7
PW4
PT2,LD10
PT1,LD9
P43,A3
R17 DVCC1A3
ADTRG
DVCC3A12
DVCC3A11
DVSS11
DVCC3A10
T1
T2
X1
PA2,KI2
AM0
PA0,KI0
P42,A2
T3
AM1
PF2,I2S0WS
PF0,I2S0CKO
PJ5,NDALE
PK3,LVSYNC
PC0,INT0
T4
PP6,TB0OUT0
PL0,LD0
PL2,LD2
PL4,LD4
PL5,LD5
PR1,SPDO
PL6,LD6
PK1,LLOAD
P00,D0
F10 DVSS10
F11 DVCC3A9
F14 PU5,LD21
F15 PU2,LD18
F16 P55,A13
F17 P54,A12
T5
PM2,
,
T6
ALARM MLDALM
B10 PJ2,
B11 PJ0,
B12 P86.
B13 P82,
,
P90,TXD0
DVCC3A3
DVSS4
T7
SDWE SRWR
,
T8
SDRAS SRLLB
,
T9
CSZD ND0CE
,
,
DVCC3A4
DVSS5
T10
T11
T12
T13
T14
T15
T16
T17
U1
U2
U3
U4
U5
U6
U7
U8
U9
CS2 CSZA SDCS
B14 P75,R/ W ,NDR/
G1
G2
G3
G4
G6
G7
DVCC3B1
PW7
B
B15 P71,
,
DVCC3A5
DVSS6
WRLL NDRE
B16 P64,A20
PV0,SCLK0
PV1
P02,D2
B17 DVCC1A4
DVCC3A6
PK7,LGOE2
PT0,LD8
P04,D4
C1
C2
C3
C4
C5
C6
C7
C8
C9
AVCC
DVSS1
DVSS12
P06,D6
VREFL
P11,D9
PG4,AN4
PG1,AN1
PA4,KI4
PC5,EA27
G12 DVSS9
P41,A1
P12,D10
Dummy2
G14 PU3,LD19
G15 PU0,LD16
G16 P53,A11
G17 P52,A10
P40,A0
DVCC1A1
PC1,INT1,TA0IN
P91,RXD0
DVSS1C
RESET
D+
N2
P76,
N3
D-
WAIT
PF5,I2S1WS
PF3,I2S1CKO
H1
H2
H3
H4
H6
PV7,SCL
PV6,SDA
PV3
N4
DVCC1A2
PL1,LD1
PL3,LD3
XT1
N14
N15
N16
N17
P1
PK6,LGOE1
PK5,LGOE0
P17,D15
C10 PJ7,SDCKE
C11 PJ3,SDLLDQM
PV2
C12 P84,
C13 P80,
DVCC3A1
P16,D14
XT2
CSZB
CS0
H12 DVCC3A8
H14 PU1,LD17
H15 PT7,LD15
H16 P51,A9
DVCC1C
PC2,INT2
U10 PL7.LD7
U11 PK0,LCP0
U12 P01,D1
U13 P03,D3
U14 P05,D5
U15 P07,D7
U16 P10,D8
U17 Dummy4
C14 P67,A23
C15 P66,A22
C16 P63,A19
C17 P62,A18
P2
P3
P92,SCLK0,
CTS0
P5
PX4,CLKOUT, LDIV
PP2,TA5OUT
PP4,INT6,TB0IN0
PR0,SPDI
H17 P50,A8
P6
D1
D2
D3
D5
D6
D7
D8
P97,PY
J1
J2
PN2,KO2
PN1,KO1
PN0,KO0
PV4
P7
AVSS
P8
PW0
J3
P9
PR3,SPCLK
PG0,AN0
PC6,EA28
PC4,EA26
P74,EA25
J4
P10
P11
P12
P13
DBGE
PZ1,EI_SYNCLK
J6
DVSS2
J12
J14
DVSS8
PZ3,EI_REFCLK
PT6,LD14
PZ5,EI_COMRESET
Note1: The P96, P97 and PG0~PG5 operate with the AVCC power supply.
Note2: The PW0~PW7 and PV0~PV7 operate with the DVCC3B power supply.
Note3: The X1 and X2 operate with the DVCC1C power supply.
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TMP92CZ26A
2.2 Pin names and Functions
The names of the input/output pins and their functions are described below.
Table 2.2.1 Pin names and functions (1/6)
Number of
Pin name
D0 to D7
I/O
Functions
Pins
8
I/O
I/O
Data: Data bus D0 to D7.
P10 to P17
D8 to D15
P40 to P47
A0 to A7
P50 to P57
A8 to A15
P60 to P67
A16 to A23
P70
Port 1: I/O port. Input or output is specifiable in units of bit.
Data : Data bus D8 to D15.
8
8
8
I/O
Output
Output
Output
Output
I/O
Port 4: Output port.
Address : Address bus A0 to A7.
Port 5: Output port.
Address : Address bus A8 to A15.
Port 6 : I/O port. Input or output is specifiable in units of bit.
Address : Address bus A16 to A23.
Port 70 : Output port.
8
1
Output
Output
Output
I/O
Read : Outputs strobe signal to read external memory.
Port 71 : Output port.
RD
P71
1
1
Output
Output
I/O
Write : Outputs strobe signal to write data on pins D0 to D7.
NAND Flash read : Outputs strobe signal to read external NAND-Flash.
Port 72 : I/O port.
WRLL
NDRE
P72
WRLU
NDWE
P73
Output
Output
I/O
Write : Outputs strobe signal to write data on pins D8 to D15.
NAND Flash write : Write enable for NAND Flash.
Port 73 : I/O port.
1
1
1
EA24
P74
Output
I/O
Expanded address 24.
Port 74 : I/O port.
EA25
P75
Output
I/O
Expanded address 25.
Port 75 : I/O port.
R/ W
Output
Input
Read/Write : “High” represents read or dummy cycle and “Low” write cycle.
NAND Flash Ready(1) / Busy(0) input.
NDR/ B
P76
I/O
Port 76: I/O port.
1
Input
Wait: Signal used to request CPU bus wait.
WAIT
P80
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Port 80: Output port.
1
1
CS0
Chip select 0: Outputs “Low” when address is within specified address area.
Port 81 : Output port
P81
CS1
Chip select 1: Outputs “Low” when address is within specified address area.
Chip select for SDRAM : Outputs “Low” when the address is within SDRAM address area.
Port 82 : Output port.
SDCS
P82
1
1
CS2
Chip select 2: Outputs “Low” when address is within specified address area.
Expanded address ZA : Outputs “Low” when address is within specified address area.
Chip select for SDRAM : Outputs “0” when the address is within SDRAM address area.
Port 83 : Output port.
CSZA
SDCS
P83
CS3
Chip select 3: Outputs “Low” when address is within specified address area.
Expanded address XA : Outputs “Low” when address is within specified address area.
Port 84 : Output port.
CSXA
P84
1
1
CSZB
P85
Expanded address ZB : Outputs “Low” when address is within specified address area.
Port 85 : Output port.
CSZC
Expanded address ZC : Outputs “Low” when address is within specified address area.
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TMP92CZ26A
Table 2.2.1 Pin names and functions (2/6)
Number
of Pins
Pin name
I/O
Functions
P86
Output
Output
Output
Output
Output
Output
I/O
Port 86 : Output port.
CSZD
ND0CE
P87
1
1
Expanded address ZD : Outputs “Low” when address is within specified address area.
Chip select of NAND Flash 0: Outputs “Low” when NAND Flash 0 is enable.
Port 87 : Output port.
CSXB
ND1CE
P90
Expanded address XB : Outputs “Low” when address is within specified address area.
Chip select of NAND Flash 1: Outputs “Low” when NAND Flash 1 is enable.
Port 90: I/O port.
1
1
TXD0
P91
Output
I/O
Transmit data of serial 0: programmable open drain output.
Port 91: I/O port. (Schmitt input)
RXD0
P92
Input
I/O
Receive data of serial 0.
Port 92: I/O port. (Schmitt input)
SCLK0
CTS0
P96
1
1
I/O
Clock I/O of serial 0
Input
Input
Input
Output
Input
Output
Input
Input
I/O
Enable to send data of serial 0 (Clear to send).
Port 96: Input port. (schmitt input, with pull-up resistor)
Interrupt request pin 4 : Interrupt request pin with programmable rising/falling edge.
X-Plus : Pin connected to X+ pin for Touch Screen I/F.
Port 97: Input port. (schmitt input)
INT4
PX
P97
1
PY
Y-Plus : Pin connected to Y+ pin for Touch Screen I/F.
Port A0 to A7: Input port.
PA0 to PA7
KI0 to KI7
PC0
8
1
Key input 0 to 7: For key on wake-up 0 to 7. (Schmitt input, with pull-up resistor)
Port C0: I/O port. (Schmitt input)
INT0
PC1
Input
I/O
Interrupt request pin 0 : Interrupt request pin with programmable rising/falling edge.
Port C1: I/O port. (Schmitt input)
INT1
TA0IN
PC2
1
1
1
Input
Input
I/O
Interrupt request pin 1 : Interrupt request pin with programmable rising/falling edge.
Timer A0 input: Input pin of 8 bit timer 0.
Port C2: I/O port. (Schmitt input)
INT2
PC3
Input
I/O
Interrupt request pin 2 : Interrupt request pin with programmable rising/falling edge.
Port C3: I/O port. (Schmitt input)
INT3
TA2IN
PC4
Input
Input
I/O
Interrupt request pin 3 : Interrupt request pin with programmable rising/falling edge.
Timer A2 input: Input pin of 8 bit timer 2.
Port C4: I/O port.
1
1
1
1
EA26
PC5
Output
I/O
Expanded address 26.
Port C5: I/O port.
EA27
PC6
Output
I/O
Expanded address 27.
Port C6: I/O port.
EA28
PC7
Output
I/O
Expanded address 28.
Port C7: I/O port.
KO8
Output
Key output 8: Key scan strobe pin (programmable open drain output).
92CZ26A-9
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TMP92CZ26A
Table 2.2.1 Pin names and functions (3/6)
Number of
Pins
Pin name
PF0
I/O
Functions
I/O
Output
I/O
Port F0: I/O port.
1
1
1
1
1
1
1
2
I2S0CKO
PF1
Outputs clock of I2S0.
Port F1: I/O port.
I2S0DO
PF2
Output
I/O
Outputs data of I2S0.
Port F2: I/O port.
I2S0WS
PF3
Output
I/O
Outputs word select signal of I2S0.
Port F3: I/O port.
I2S0WS
PF4
Output
I/O
Outputs clock of I2S1.
Port F4: I/O port.
I2S1CKO
PF5
Output
I/O
Outputs data of I2S1.
Port F5: I/O port.
I2S1WS
PF7
Output
Output
Output
Input
Outputs word select signal of I2S1.
Port F7: Output port.
SDCLK
PG0 to PG1
AN0 to AN1
PG2
Clock for SDRAM.
Port G0 to G1: Input port.
Input
Analog input pin 0 to 1 : Input pin of A/D converter.
Port G2: Input port.
Input
AN2
1
1
Input
Analog input pin 2 : Input pin of A/D converter.
X-Minus : Pin connected to X- pin for Touch Screen I/F.
Port G3: Input port.
MX
Output
Input
PG3
AN3
Input
Analog input pin 3 : Input pin of A/D converter.
Y-Minus : Pin connected to Y- pin for Touch Screen I/F.
A/D Trigger : Request signal of A/D start.
Port G4 to G5: Input port.
MY
Output
Input
ADTRG
PG4 to PG5
AN4 to AN5
PJ0
Input
2
1
Input
Analog input pin 4 to 5 : Input pin of A/D converter.
Port J0: Output port.
Output
Output
Output
Output
Output
Output
SDRAS
SRLLB
PJ1
Outputs strobe signal of SDRAM row address.
Data enable signal for D0 to D7 of SRAM.
Port J1: Output port.
SDCAS
SRLUB
PJ2
Outputs strobe signal of SDRAM column address.
Data enable signal for D8 to D15 of SRAM.
1
1
Output
Output
Output
Output
Output
Output
Output
I/O
Port J2: Output port.
SDWE
SRWR
PJ3
Outputs write enable signal of SDRAM.
Write enable of SRAM: Outputs strobe signal to write data.
Port J3: Output port.
1
1
1
1
1
SDLLDQM
PJ4
Data enable signal for D0 to D7 of SDRAM.
Port J4: Output port.
SDLUDQM
PJ5
Data enable signal for D8 to D15 of SDRAM.
Port J5: I/O port.
NDALE
PJ6
Output
I/O
Address latch enable signal of NAND Flash.
Port J6: I/O port.
NDCLE
PJ7
Output
Output
Output
Command latch enable signal of NAND Flash.
Port J7: Output port.
SDCKE
Clock enable signal of SDRAM.
92CZ26A-10
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TMP92CZ26A
Table 2.2.1 Pin names and functions (4/6)
Number of
Pins
Pin name
PK0
I/O
Functions
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Port K0: Output port.
1
1
1
1
1
1
1
1
8
LCP0
Signal for LCD driver.
PK1
Port K1: Output port.
LLOAD
PK2
Signal for LCD driver.: Data load signal
Port K2: Output port.
LFR
Signal for LCD driver.
PK3
Port K3: Output port.
LVSYNC
PK4
Signal for LCD driver. : Vertical sync signal
Port K4: Output port.
LHSYNC
PK5
Signal for LCD driver. : Horizontal sync signal.
Port K5: Output port.
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
LGOE0
PK6
Signal for LCD driver.
Port K6: Output port.
LGOE1
PK7
Signal for LCD driver.
Port K7: Output port.
LGOE2
PL0 to PL7
LD0 to LD7
PM1
Signal for LCD driver.
Port L0 to L7: Output port.
Data bus for LCD driver: LD0 to LD7.
Port M1: Output port.
TA1OUT
MLDALM
PM2
1
1
Timer A1 output: Output pin of 8 bit timer 1.
Melody / Alarm output pin.
Port M2: Output port.
Alarm output from RTC.
ALARM
MLDALM
PM7
Melody / Alarm output pin (inverted).
Port M7 : Output port
PWE
External power supply control output: Pin to control ON/OFF of external power
supply. In stand-by mode, outputs “L” level. In other than stand-by mode, outputs
“H” level.
1
PN0 to PN7
KO0 to KO7
PP1
I/O
Output
I/O
Port N: I/O port.
8
1
1
Key output 0 to 7 : Key scan strobe pin (programmable open drain output).
Port P1: I/O port.
TA3OUT
PP2
Output
I/O
Timer A3 output: Output pin of 8 bit timer 3.
Port P2: I/O port.
TA5OUT
PP3
Output
I/O
Timer A5 output: Output pin of 8 bit timer 5.
Port P3: I/O port. (Schmitt input)
INT5
1
1
1
Input
Output
I/O
Interrupt request pin 5 : Interrupt request pin with programmable rising/falling edge.
Timer A7 output: Output pin of 8 bit timer 7.
Port P4: I/O port. (Schmitt input)
TA7OUT
PP4
INT6
Input
Input
I/O
Interrupt request pin 6 : Interrupt request pin with programmable rising/falling edge.
Timer B0 input: Input pin of 16 bit timer 0.
Port P5: I/O port. (Schmitt input)
TB0IN0
PP5
INT7
Input
Input
Output
Output
Output
Output
I/O
Interrupt request pin 7 : Interrupt request pin with programmable rising/falling edge.
Timer B1 input: Input pin of 16 bit timer 1.
Port P6: I/O port.
TB1IN0
PP6
1
1
1
1
1
TB0OUT0
PP7
Timer B0 output: Output pin of 16 bit timer 0.
Port P7: I/O port.
TB1OUT0
PR0
Timer B1 output: Output pin of 16 bit timer 1.
Port R0: I/O port.
SPDI
Input
I/O
Data input pin of SD card.
PR1
Port R1: I/O port.
SPDO
PR2
Output
I/O
Data output pin of SD card.
Port R2: I/O port.
SPCS
Output
Chip select signal of SD card.
92CZ26A-11
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TMP92CZ26A
Table 2.2.1 Pin names and functions (5/6)
Number of
Pins
Pin name
I/O
Functions
PR3
I/O
Output
I/O
Port R3: I/O port.
1
8
6
1
SPCLK
PT0 to PT7
LD8 to LD15
PU0 to PU4,PU6
LD16 to LD20,LD22
PU5
Clock output pin of SD card.
Port T0 to T7: I/O port.
Output
I/O
Data bus for LCD driver: LD8 to LD15.
Port U0 to U4 , U6: I/O port
Data bus for LCD driver: LD16 to LD20, LD22.
Port U5: I/O port
Output
I/O
LD21
Output
I/O
Data bus for LCD driver: LD21
Port U7: I/O port
PU7
LD23
1
1
Output
Output
I/O
Data bus for LCD driver: LD23
Debug mode output pin
Port V0 : I/O port
EO_TRGOUT
PV0
SCLK0
Output
I/O
Clock I/O of serial 0.
PV1
1
1
2
Port V1: I/O port.
PV2
I/O
Port V2: I/O port.
PV3 to PV4
PV6
Output
I/O
Port V3 to V4: Output port.
Port V6: I/O port
Send/receive data in I2C mode.
1
SDA
I/O
PV7
I/O
Port V7: I/O port
1
8
SCL
I/O
Input/output clock in I2C mode.
Port W0 to W7: I/O port.
Port X4 : Output port
PW0 to PW7
PX4
I/O
Output
Output
Output
I/O
CLKOUT
LDIV
1
Internal clock output pin
Output pin for LCD driver
Port X5: I/O port.
PX5
1
1
1
X1USB
PX7
Input
I/O
Clock input pin of USB.
Port X7: I/O port.
PZ0
I/O
Port Z0: I/O port. (Schmitt input)
Debug mode input pin
EI_PODDATA
PZ1
Input
I/O
Port Z1: I/O port. (Schmitt input)
Debug mode input pin
1
1
1
1
1
1
1
EI_SYNCLK
PZ2
Input
I/O
Port Z2: I/O port. (Schmitt input)
Debug mode input pin
EI_PODREQ
PZ3
Input
I/O
Port Z3: I/O port. (Schmitt input)
Debug mode input pin
EI_REFCLK
PZ4
Input
I/O
Port Z4: I/O port. (Schmitt input)
Debug mode input pin
EI_TRGIN
PZ5
Input
I/O
Port Z5: I/O port. (Schmitt input)
Debug mode input pin
EI_COMRESET
PZ6
Input
I/O
Port Z6: I/O port. (Schmitt input)
Debug mode output pin
Port Z7: I/O port. (Schmitt input)
Debug mode output pin
EO_MCUDATA
PZ7
Output
I/O
EO_MCUREQ
Output
92CZ26A-12
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TMP92CZ26A
Table 2.2.1 Pin names and functions (6/6)
Number of
Pins
Pin name
I/O
Functions
Data pin connected to USB.
D+, D-
2
1
I/O
In case USB is not used, connect both pins to pull-up(DVCC3A) or pull-down resistor for protect
current flows it.
CLKOUT
AM1,AM0
DBGE
Output
Internal clock output pin.
Operation mode;
Fix to AM1=”0”,AM0=”1” for 16 bit external bus starting.
Fix to AM1=”1”,AM0=”0” is prohibit to set.
Fix to AM1=”1”,AM0=”1” for BOOT (32 bit internal Mask ROM) starting.
Fix to AM1=”0”,AM0=”0” is prohibited to set.
2
Input
1
2
Input
Input pin in debug mode. (This pin is set to “Debug mode” by input “0”.)
High-frequency oscillator circuit connection pin.
X1/X2
I/O
XT1/XT2
RESET
2
I/O
Low-frequency oscillator circuit connection pin.
1
Input
Reset : Initialize TMP92CZ26A (schmitt input , with pull-up resistor)
VREFH
1
Input
Pin for reference voltage input to A/D converter(H).
VREFL
1
Input
Pin for reference voltage input to A/D converter(L).
AVCC
1
−
−
−
−
−
−
−
−
−
Power supply pin for A/D converter.
AVSS
1
GND pin for AD converter (0V).
DVCC3A
DVCC3B
DVCC1A
DVCC1B
DVSSCOM
DVCC1C
DVSS1C
12
1
Power supply pin for peripheral I/O-A (Connect all DVCC3A pins to power supply pin.)
Power supply pin for peripheral I/O-B (Connect all DVCC3B pins to power supply pin.)
Power supply pin for internal logic-A. (Connect all DVCC1A pins to power supply pin.)
Power supply pin for internal logic-B. (Keep the voltage DVCC1A level.)
GND pin (0V). (Connect all DVSS pins to GND(0V).)
5
1
12
1
Power supply pin for High speed oscillator. (Keep the voltage DVCC1A level.)
GND pin (0V). (Connect to GND(0V).)
1
Dummy1 and Dummy2, Dummy3 and Dummy4 are shorted in package. (These pins are not
connected with internal LSI chip.)
Dummy4-1
4
−
Table 2.2.2 shows the range of operational voltage for power supply pins.
Table 2.2.2 the range of operational voltage for power supply pins
Range of
Power supply pin
operational
voltage
DVCC1A
DVCC1B
1.4V~1.6V
3.0V~3.6V
DVCC1C
DVCC3A
DVCC3B
AVCC
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TMP92CZ26A
3. Operation
This section describes the basic components, functions and operation of the TMP92CZ26A.
3.1 CPU
The TMP92CZ26A contains an advanced high-speed 32-bit CPU (900/H1 CPU)
3.1.1 CPU Outline
900/H1 CPU is high-speed and high-performance CPU based on 900/L1 CPU. 900/H1
CPU has expanded 32-bit internal data bus to process Instructions more quickly.
Outline is as follows:
Table 3.1.1Outline of TMP92CZ26A
Parameter
TMP92CZ26A
Width of CPU Address Bus
Width of CPU Data Bus
Internal Operating Frequency
Minimum Bus Cycle
24-bit
32-bit
Max 80MHz
1-clock access
(12.5ns at 80MHz)
32-bit 2-1-1-1 clock access
32 bit 2-clock access
Internal RAM
Internal Boot ROM
Internal I/O
8-bit,
INTC,SDRAMC,
MEMC,LCDC,
TSI,PORT,
PMC
2-clock access
16-bit,
MMU,USB,
NDFC,SPIC,DMAC
I2S
2-clock access
32-bit,
2-clock access
MAC
32-bit,
MAC
1-clock access
8-bit,
TMRA,TMRB,
SIO,RTC,
5 to 6-clock access
MLD/ALM, SBI
CGEAR,ADC,WDT
External memory
(SRAM, MASKROM etc.)
External memory
(SDRAM)
8/16-bit 2-clock access
(can insert some waits)
16-bit 1-clock access
External memory
(NAND FLASH)
8/16-bit 2-clock access
(can inset some waits)
Minimum Instruction
Execution Cycle
1-clock(12.5ns at 80MHz)
Conditional Jump
Instruction Queue Buffer
Instruction Set
2-clock(25.0ns at 80MHz)
12-byte
Compatible with TLCS-900/L1
(LDX instruction is deleted)
Only maximum mode
8-channel
CPU mode
Micro DMA
Hardware DMA
6-channel
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3.1.2 Reset Operation
When resetting the TMP92CZ26A microcontroller, ensure that the power supply voltage
is within the operating voltage range, and that the internal high-frequency oscillator has
stabilized. Then hold the RESET input Low for at least 20 system clocks (32µs at
X1=10MHz).
At reset, since the clock doublers (PLL0) is bypassed and clock-gear is set to 1/16, system
clock operates at 625 kHz(X1=10MHz).
When the Reset has been accepted, the CPU performs the following. CPU internal
registers do not change when the Reset is released.
•
•
Sets the Stack Pointer (XSP) to 00000000H.
Sets bits <IFF2:0> of the Status Register (SR) to “111” (thereby setting the Interrupt
Level Mask Register to level 7).
•
Clears bits <RFP1:0> of the Status Register to 00 (thereby selecting Register Bank 0).
When the Reset is released, the CPU starts executing instructions according to the
Program Counter settings.
•
Sets the Program Counter (PC) as follows in accordance with the Reset Vector stored
at address FFFF00H~FFFF02H:
PC<7:0>
←
←
←
data in location FFFF00H
data in location FFFF01H
data in location FFFF02H
PC<15:8>
PC<23:16>
When the Reset is accepted, the CPU sets internal I/O, ports and other pins as follows.
•
Initializes the internal I/O registers as table of “Special Function Register” in Section
5.
Note1: This LSI builds in RAM internally. However, the data in internal RAM may not be held by Reset
operation. After reset, initialize the data in internal RAM.
Note2: This LSI builds in PMC function (for reducing stand-by current by blocking the power supply of
DVCC1A and DVCC1C). However, if executing reset operation without supplying DVCC1A and
DVCC1C, the current may flow to internal. When reset this LSI, supply the power of DVCC1A and
DVCC1C first and wait until the power supply stabilizes.
power and the timing of releasing reset.
92CZ26A-15
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Write
Read
Figure 3.1.1 TMP92CZ26A Reset timing chart
92CZ26A-16
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TMP92CZ26A
This LSI has the restriction for the order of supplying power. Be sure to supply external
3.3V power with 1.5V power is supplied.
Power Off
Power On
Stand-by Mode (PMC)
DVCC1A
1.5V
Power
DVCC1B
DVCC1C
Power supply is falling with
in 100mS, and stabilizes.
Power supply is rising with
in 100mS, and stabilizes.
After 1.5V power
supply is rising,
set 3.3V to ON.
After 1.5V power
supply is falling, set
3.3V to OFF.
3.3V
Power
DVCC3A
DVCC3B
High-frequency oscillation
AVCC
stabilization time
＋20 system clock
RESET
PWE terminal
Note1: Inernal 1.5 V and External 3.3V power supply can be set to ON/OFF at the same time. However, external pin
may become unstable condition momentary. Therefore, set external power supply to ON/OFF during internal
power supply is stabile like above figure if there is possibility to affect machinery connected with micro controller.
Note2: When setting to ON, don’t set 3.3V power supply earlier than 1.5V power supply. When setting to OFF, don’t
set to 3.3V power supply later than 1.5 V power supply.
Figure 3.1.2 Power on Reset Timing Example
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3.1.3 Setting of AM0 and AM1
Table 3.1.2 Operation Mode Setup Table
Mode Setup input pin
Operation Mode
RESET
DBGE
AM1
AM0
0
1
0
1
0
Debug mode
0
1
16-bit external bus starting
Test mode (Prohibit to set)
1
1
0
0
1
0
Test mode (Prohibit to set)
BOOT(32-bit internal-MROM )
starting
1
(BOOT mode)
0
Test mode (Prohibit to set)
1
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3.2 Memory Map
Figure 3.2.1 is a memory map of the TMP92CZ26A.
000000H
Internal I/O
(8 Kbyte)
Direct area(n)
000100H
64Kbyte area
(nn)
001FF0H
002000H
010000H
Internal RAM
(288 Kbyte)
046000H
04A000H
(Internal Back Up RAM 16kbyte)
External memory
16Mbyte area
(R)
(−R)
(R+)
F00000H
F10000H
Provisional Emulator Control Area
(64kbyte)
(Note1)
(R + R8/16)
(R + d8/16)
(nnn)
External memory
FFFF00H
FFFFFFH
Vector table (256 Byte)
(
Internal area)
Figure 3.2.1 Memory Map
Note1: Don’t use specified 64kbyte area of above 16M byte when using debug mode. This is because the area is reserved
for control in the debug mode.
Note2: Don’t use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved as internal area.
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3.3 Clock Function and Standby Function
TMP92CZ26A contains (1) clock gear, (2) clock doubler (PLL), (3) standby controller and (4)
noise-reducing circuit. They are used for low-power, low-noise systems.
This chapter is organized as follows:
3.3.1 Block diagram of system clock
3.3.2 SFRs
3.3.3 System clock controller
3.3.4 Prescaler clock controller
3.3.5 Noise-reducing circuit
3.3.7 Standby controller
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The clock operating modes are as follows: (a) PLL-OFF Mode (X1, X2 pins only),
(b) PLL-ON Mode (X1, X2, and PLL).
The clock frequency input from the X1 and X2 pins is called fOSCH and the clock
frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by
SYSCR1<GEAR2:0> is called the system clock fSYS. And one cycle of fSYS is defined to
as one state.
instruction
interrupt
instruction
interrupt
Reset
(f
/16)
OSCH
instruction
interrupt
release Reset
IDLE2 mode
(I/O operate)
instruction
interrupt
PLL-OFF mode
/gear value)
STOP mode
(Stops all circuits)
instruction
interrupt
(f
OSCH
IDLE1 mode
(Operate only oscillator)
Instruction (Note)
instruction
IDLE2 mode
(I/O operate)
interrupt
PLL-ON mode
((12 or 16)×f /gear value)
instruction
interrupt
OSCH
IDLE1 mode
(Operate only oscillator)
Note 1: If you shift from PLL-ON mode to PLL-OFF mode, execute following setting in the same order.
(1) Change CPU clock (Set “0” to PLLCR0<FCSEL>)
(2) Stop PLL circuit (Set “0” to PLLCR1<PLLON>)
Note 2: It’s prohibited to shift from PLL-ON mode to STOP mode directly.
You should set PLL-OFF mode once, and then shift to STOP mode.
Figure 3.3.1 System clock block diagram
The clock frequency input from the X1 and X2 pins is called fOSCH and the clock frequency input from the XT1 and XT2 pins is
called fs. The clock frequency selected by SYSCR1<GEAR2:0> is called the system clock f
. And one cycle of f
is defined
SYS
SYS
to as one state.
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3.3.1 Block diagram of system clock
SYSCR0<WUEF>
SYSCR2<WUPTM1:0>
φT0
÷4
Warming up timer
(High/Low frequency oscillator circuit)
φT0TMR
÷2
Lock up timer
÷2
÷8
(PLL)
SYSCR0<XTEN >
SYSCR0<PRCK>
PLLCR1<PLLON>,
PLLCR0<LUPFG>
XT1
XT2
Low frequency
Oscillator circuit
fs
fs
fc
fc/2
fc/4
f
SYS
fc/8
fPLL
Clock Doubler0
(PLL0)
fc/16
÷2
f
IO
÷2
× (12 or16)
÷2 ÷4 ÷8 ÷16
X1
X2
High frequency
Oscillator circuit
SYSCR1<GEAR2:0>
Clock gear
f
OSCH
PLLCR0<FCSEL>
SYSCR0<USBCLK1:0>
Clock Doubler1
fPLLUSB
(PLL1)× 24
÷5
f
X1USB
USB
f
SYS
CPU
RAM
LCDC
TMRA0:7,TMRB0:1
Prescaler
f
io
Memory
Controller
NAND-Flash
Controller
φT0TMR
Interrupt
Controller
SIO0
fOSCH4
I2S
I/O ports
φT0
Prescaler
TSI
SDRAMC
DMAC
MAC
SBI
SPIC
Prescaler
RTC
fs
MLD/ALM
ADC
USB
f
USB
Figure 3.3.2 Block Diagram of System clock
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TMP92CZ26A has two PLL circuits: one is for CPU (PLL0) and the other for USB (PLL1).
Each PLL can be controlled independently. Frequency of external oscillator is 6 to 10MHz.
Don’t connect oscillator more than10MHz. When clock is input by using external oscillator,
range of input frequency is 6 to10MHz. Don’t input the clock over 10MHz.
Table 3.3.1 Setting example for f
OSCH
System
clock:
System
clock:
USB
clock:
High frequency:
f
OSCH
f
f
f
USB
SYS
SYS
(a) PLL, USB (PLL0 ON/PLL1ON)
10.0 MHz
Max 80 MHz
Max 80 MHz
Max 10 MHz
Max 60 MHz
Max 60 MHz
Max 10 MHz
48 MHz
(b) PLL, No USB (PLL0 ON/PLL1OFF)
(c) No PLL, No USB (PLL0 OFF/PLL1OFF)
Max 10.0 MHz
Max 10.0 MHz
−
−
Note: When using USB, set high-frequency oscillator to 10.0 MHz.
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3.3.2 SFR
7
6
5
4
3
2
1
0
bit Symbol
XTEN
R/W
1
WUEF
R/W
PRCK
R/W
USBCLK1
USBCLK0
SYSCR0
(10E0H)
Read/write
After Reset
R/W
0
R/W
0
0
0
Low
Select the clock of
USB(fUSB
Warm-up
Timer
Select
Prescaler
clock
-frequency
oscillator
circuit (fs)
0: Stop
)
00:Disable
01: Reserved
10:X1USB
0: Write
Don’t care
Note3
0: fSYS/2
1: fSYS/8
1: Oscillation 11:fPLLUSB
1: Write
start timer
0: Read
end
Function
warm-up
1: Read
do not end
warm-up
2
7
6
5
4
3
1
0
SYSCR1
(10E1H)
bit Symbol
Read/write
After Reset
GEAR2
GEAR1
R/W
0
GEAR0
1
0
Select gear value of high frequency (fc)
000: fc
001: fc/2
010: fc/4
Function
011: fc/8
100: fc/16
101: Reserved
110: Reserved
111: Reserved
7
6
5
4
3
2
1
0
bit Symbol
Read/write
After Reset
–
R/W
CKOSEL WUPTM1 WUPTM0 HALTM1
HALTM0
R/W
SYSCR2
(10E2H)
R/W
0
R/W
R/W
0
R/W
1
0
1
1
Always
write “0”
Select
Warm-Up Timer
HALT mode
00: Reserved
CLKOUT
0: fSYS
1: fS
00: reserved
01: 28/inputted frequency
10:214/inputted frequency
11:216/inputted frequency
01: STOP mode
10: IDLE1 mode
11: IDLE2 mode
Function
Note1: SYSCR0<bit7><bit3><bit1>,SYSCR1<bit7:3> and SYSCR2<bit1:0> are read as undefined value.
Note2: By reset, low frequency oscillator circuit is enabled.
Note3: Don’t write SYSCR0 resiter during warming up. Because the warm-up end flag doesn’t become enable if
write ”0” to SYSCR0<WUEF> bit during warming up.
( Read-modify-write is prohibited for SYSCR0 register during warming up.)
Figure 3.3.3 SFR for system clock
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0
7
6
5
4
3
2
1
PROTECT
Bit symbol
Read/Write
After reset
−
R/W
EXTIN
R/W
0
DRVOSCH
DRVOSCL
R/W
EMCCR0
(10E3H)
R
0
R/W
1
0
1
Always
write “0”.
Protect flag
0: OFF
1: ON
1: External fc oscillator
clock drive ability
fs oscillator
drive ability
Function
1: NORMAL 1: NORMAL
0: WEAK 0: WEAK
Bit symbol
Read/Write
After reset
Function
EMCCR1
(10E4H)
Switching the protect ON/OFF by write to following 1st-KEY,2nd-KEY
1st-KEY: EMCCR1=5AH,EMCCR2=A5H in succession write
2nd-KEY: EMCCR1=A5H,EMCCR2=5AH in succession write
Bit symbol
Read/Write
After reset
Function
EMCCR2
(10E5H)
Note: In case restarting the oscillator in the stop oscillation state (e.g. Restart the oscillator in STOP mode), set
EMCCR0<DRVOSCH>, <DRVOSCL>=”1”.
Figure 3.3.4 SFR for system clock
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0
7
6
5
4
3
2
1
PLLCR0
(10E8H)
bit symbol
Read/Write
After reset
FCSEL
R/W
0
LUPFG
R
0
Select
Lock-up
timer
fc-clock
0 : f
Function
Status flag
0 : not end
1 : end
OSCH
1 : f
PLL
Note: Be carefull that logic of PLLCR0<LUPFG> is different from 900/L1’s DFM.
7
6
5
4
3
2
1
0
PLLCR1
(10E9H)
bit symbol
Read/Write
After reset
PLL0
R/W
PLL1
R/W
LUPSEL
R/W
PLLTIMES
R/W
0
0
0
0
PLL0 for
CPU
PLL1 for
USB
Select
Select the
number of
PLL
stage of
Lock up
counter
0: 12 stage
(for PLL0)
1:13 stage
(for PLL1)
0: Off
1: On
0: Off
1: On
0: ×12
1: ×16
Function
Figure 3.3.5 SFR for PLL
7
6
5
4
3
2
1
0
bit symbol
Read/Write
After reset
Function
Px7D
Px6D
Px5D
Px4D
Px3D
Px2D
Px1D
Px0D
PxDR
(xxxxH)
R/W
1
1
1
1
1
1
1
1
Output/Input buffer drive-register for standby-mode
(Purpose and method of using)
• This register is used to set each pin-status at stand-by mode.
• All ports have this format’s register. (“x” means port-name.)
• For each register, refer to 3.5 Function of Ports.
• Before “HALT” instruction is executed, set each register pin-status. They will be
effective after CPU executes “HALT” instruction.
• This register is effective in all stand-by modes (IDLE2, IDLE1 or STOP).
• This register is effective when using PMC function. For details, refer to PMC
section.
The truth table to control Output/Input-buffer is below.
OE
0
PxnD Output buffer
Input buffer
OFF
0
1
0
1
OFF
OFF
OFF
ON
0
ON
1
OFF
1
OFF
Note1: OE means an output enable signal before stand-by mode. Basically, PxCR is used as OE.
Note2: “n” in PxnD means bit-number of PORTx.
Figure 3.3.6 SFR for drive register
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3.3.3 System clock controller
The system clock controller generates the system clock signal (fSYS) for the CPU core and
internal I/O.
SYSCR0<XEN> and SYSCR0<XTEN> control enabling and disabling of each oscillator.
SYSCR1<GEAR2:0> sets the high frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4,
fc/8, fc/16). These functions can reduce the power consumption of the equipment in which
the device is installed.
The combination of settings <XEN> = “1”, <SYSCK> = “0” and <GEAR2 to 0> = “100” will
be PLL-OFF mode and cause the system clock (fSYS) to be set to fc/16 after reset.
For example, fSYS is set to 625 kHz when the 10MHz oscillator is connected to the X1 and
X2 pins.
(1) Clock gear controller
f
is set according to the contents of the Clock Gear Select Register SYSCR1<GEAR2:
SYS
0> to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of f
reduces power consumption.
SYS
(Example)
Changing clock gear
SYSCR1
EQU
10E1H
LD
LD
(SYSCR1),XXXXX001B
(DUMMY),00H
;
Changes system clock f
Dummy instruction
fc/2
SYS to
X: don't care
(High-speed clock gear changing)
To change the clock gear, write the register value to the SYSCR1<GEAR2 to 0> register.
It is necessary the warming up time until changing after writing the register value.
There is the possibility that the instruction next to the clock gear changing instruction is
executed by the clock gear before changing. To execute the instruction next to the clock gear
switching instruction by the clock gear after changing, input the dummy instruction as
follows (instruction to execute the write cycle).
(Example)
SYSCR1
EQU
LD
10E1H
(SYSCR1),XXXXX010B
(DUMMY),00H
;
;
Changes f
to fc/4
SYS
LD
Dummy instruction
Instruction to be executed after clock gear changed
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3.3.4 Clock doubler (PLL)
PLL0 outputs the fPLL clock signal, which is 12 or 16 times as fast as fOSCH. That is, the
low-speed frequency oscillator can be used as external oscillator, even though the internal
clock is high-frequency.
Since Reset initializes PLL0 to stop status, setting to PLLCR0 and PLLCR1-register is
needed before use.
Like an oscillator, this circuit requires time to stabilize. This is called the lock-up time
and it is measured by 12-stage binary counter. Lock-up time is about 0.41ms at fOSCH
10MHz.
=
=
PLL (PLL1) which is special for USB is build in. Lock-up time is about 0.82ms at fOSCH
10MHz measured by 13-stage binary counter.
Note1: Input frequency limitation for PLL
The limitation of input frequency (High frequency oscillation) for PLL is following.
fOSCH = X to X MHz (Vcc = 1.4 to 1.6V)
Note2: PLLCR0<LUPFG>
The logic of PLLCR0<LUPFG> is different from 900/L1’s DFM.
Be careful to judge an end of lock-up time.
Note3: PLLCR1<PLL0>, PLLCR1<PLL1>
It’s prohibited to turn ON both PLL0 and PLL1 simultaneously.
If turning ON simultaneously, one PLL should be turn ON after finishing the lock up of the other PLL.
=10MHz.
Frequency of fSYS
fOSH
fPLL
fc
fc/2
fc/4
fc/8
fc/16
10MHz
fOSH 10MHz
×12 120MHz
×16 160MHz
10MHz
60MHz
80MHz
5MHz
30MHz
40MHz
2.5MHz
15MHz
20MHz
1.25MHz
7.5MHz
10MHz
625KHz
3.75MHz
5MHz
Figure 3.3.7 The frequency of fSYS at fOSH =10MHz
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The following is a setting example for PLL0-starting and PLL0-stopping.
(Example-1) PLL0-starting
PLLCR0
PLLCR1
EQU
EQU
LD
10E8H
10E9H
(PLLCR1),1XXXXXXXXB
;
Enables PLL0 operation and starts lock-up.
LUP:
BIT
JR
5,(PLLCR0)
;
;
;
Detects end of lock-up
Z,LUP
LD
(PLLCR0), X1XXXXXXB
Changes fc from 10 MHz to 60 MHz.
X: Don't care
<PLL0>
<FCSEL>
PLL output: f
PLL
Lockup timer
<LUPFG>
Counts up by f
OSCH
During lock-up
After lock-up
System clock f
SYS
Starts PLL0 operation and
Starts lock-up.
Changes from 10MHz to 60MHz.
Ends of lock-up
(Example-2) PLL0-stopping
PLLCR0
PLLCR1
EQU
EQU
LD
10E8H
10E9H
(PLLCR0),X0XXXXXXB
(PLLCR1),0XXXXXXXB
;
;
Changes fc from 60 MHz to10 MHz.
Stop PLL
LD
X: Don't care
<FCSEL>
<PLL0>
PLL0 output: f
PLL
System clock f
SYS
Changes from 60MHz to 10 MHz.
Stops PLL0 operation .
Note) PLL1 operates as well.
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Limitation point on the use of PLL0
1. If you stop PLL operation during using PLL0, you should execute following setting in
the same order.
Change the clock f
Stop PLL0
to f
OSCH
LD
LD
(PLLCR0),X0XXXXXXB
(PLLCR1),0XXXXXXXB
;
;
PLL
X: Don't care
2. If you shift to STOP mode during using PLL, you should execute following setting in the
same order.
LD
(SYSCR2),XXXX01XXB
(PLLCR0), X0XXXXXXB
(PLLCR1), 0XXXXXXXB
;
;
;
;
Set the STOP mode
Change the system clock fPLL to fOSCH
Stop PLL0
LD
LD
HALT
Shift to STOP mode
X: Don't care
Examples of settings are below;
(1) Start Up / Change Control
(OK) High frequency oscillator operation mode(fOSCH )→PLL0 start up
→ PLL0 use mode (fPLL
)
LD
BIT
JR
LD
(PLLCR1), 1XXXXXXXB
5,(PLLCR0)
;
;
;
;
PLL0 start up / lock up start
LUP:
Z,LUP
Check for the flag of lock up end
(PLLCR0), X1XXXXXXB
Change the system clock fOSCH to fPLL
X: Don't care
(2) Change / Stop Control
(OK) PLL0 use mode (fPLL )→ High frequency oscillator operation mode(fOSCH
)
→ PLL0 Stop
LD
LD
(PLLCR0),X0XXXXXXB
(PLLCR1),0XXXXXXXB
;
;
Change the system clock fPLL to fOSCH
Stop PLL0
X: Don't care
(OK) PLL0 use mode (fPLL ) → Set the STOP mode
→High frequency oscillator operation mode (fOSCH) → PLL stop
→ HALT(High frequency oscillator stop)
LD
(SYSCR2),XXXX01XXB
;
Set the STOP mode
(This command can be executed before use of PLL0)
Change the system clock f
Stop PLL0
to f
OSCH
LD
(PLLCR0),X0XXXXXXB
(PLLCR1),0XXXXXXXB
;
;
;
PLL
LD
HALT
Shift to STOP mode
X: Don't care
(NG) PLL0 use mode (fPLL) → Set the STOP mode
→ HALT(High frequency oscillator stop)
LD
(SYSCR2),XXXX01XXB
;
Set the STOP mode
(This command can be executed before use of PLL0)
Shift to STOP mode
HALT
;
X: Don't care
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3.3.5 Noise reduction circuits
Noise reduction circuits are built in, allowing implementation of the following features.
(1) Reduced drivability for high-frequency oscillator circuit
(2) Reduced drivability for low-frequency oscillator circuit
(3) Single drive for high-frequency oscillator circuit
(4) SFR protection of register contents
These are set in EMCCR0 to EMCCR2 registers.
(1) Reduced drivability for high-frequency oscillator circuit
(Purpose)
Reduces noise and power for oscillator when a resonator is used.
(Clock diagram)
f
OSCH
X1 pin
C1
Enable oscillation
resonator
C2
EMCCR0<DRVOSCH>
X2 pin
(Setting method)
The drivability of the oscillator is reduced by writing”0” to EMCCR0<DRVOSCH>
register. By reset, <DRVOSCH> is initialized to “1” and the oscillator starts oscillation
by normal-drivability when the power-supply is on.
Note: This function (EMCCR0<DRVODCH>= “0”) is available to use in case fOSCH = 6 to 10MHz condition.
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(2) Reduced drivability for low-frequency oscillator circuit
(Purpose)
Reduces noise and power for oscillator when a resonator is used.
(Block diagram)
XT1 pin
C1
Enable oscillation
Resonator
EMCCR0<DRVOSCL>
C2
f
S
XT2 pin
(Setting method)
The drivability of the oscillator is reduced by writing 0 to the EMCCR0<DRVOSCL>
register. By Reset, <DRVOSCL> is initialized to “1”.
(3) Single drive for high-frequency oscillator circuit
(Purpose)
Not need twin-drive and protect mistake-operation by inputted noise to X2 pin when
the external-oscillator is used.
(Block diagram)
f
OSCH
X1 pin
Enable oscillation
EMCCR0<DRVOSCH>
X2 pin
(Setting method)
The oscillator is disabled and starts operation as buffer by writing “1” to
EMCCR0<EXTIN> register. X2-pin is always outputted”1”.
By reset,<EXTIN> is initialized to “0”.
Note: Do not write EMCCR0<EXTIN> = “1” when using external resonator.
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(4) Runaway provision with SFR protection register
(Purpose)
Provision in runaway of program by noise mixing.
Write operation to specified SFR is prohibited so that provision program in runaway
prevents that it is in the state which is fetch impossibility by stopping of clock,
memory control register (Memory controller, MMU) is changed.
And error handling in runaway becomes easy by INTP0 interruption.
Specified SFR list
1. Memory controller
B0CSL/H, B1CSL/H, B2CSL/H, B3CSL/H, BECSL/H
MSAR0, MSAR1, MSAR2, MSAR3,
MAMR0, MAMR1, MAMR2, MAMR3, PMEMCR,
MEMCR0, CSTMGCR, WRTMGCR, RDTMGCR0
RDTMGCR1, BROMCR
2. MMU
LOCALPX/PY/PZ, LOCALLX/LY/LZ,
LOCALRX/RY/RZ, LOCALWX/WY/WZ,
LOCALESX/ESY/ESZ, LOCALEDX/EDY/EDZ,
LOCALOSX/OSY/OSZ, LOCALODX/ODY/ODZ
3. Clock gear
SYSCR0, SYSCR1, SYSCR2, EMCCR0
4. PLL
PLLCR0,PLLCR1
5. PMC
PMCCTL
(Operation explanation)
Execute and release of protection (write operation to specified SFR) becomes
possible by setting up a double key to EMCCR1 and EMCCR2 register.
(Double key)
1st-KEY: Succession writes in 5AH at EMCCR1 and A5H at EMCCR2
2nd-KEY: Succession writes in A5H at EMCCR1 and 5AH at EMCCR2
A state of protection can be confirmed by reading EMCCR0<PROTECT>.
By reset, protection becomes OFF.
And INTP0 interruption occurs when write operation to specified SFR was executed
with protection on state.
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3.3.6 Standby controller
(1) Halt Modes and Port Drive-register
When the HALT instruction is executed, the operating mode switches to IDLE2,
IDLE1 or STOP Mode, depending on the contents of the SYSCR2<HALTM1 to 0>
register and each pin-status is set according to PxDR-register.
7
6
5
4
3
2
1
0
bit symbol
Read/Write
After reset
Function
Px7D
Px6D
Px5D
Px4D
Px3D
Px2D
Px1D
Px0D
PxDR
(xxxxH)
R/W
1
1
1
1
1
1
1
1
Output/Input buffer drive-register for standby-mode
(Purpose and method of using)
• This register is used to set each pin-status at stand-by mode.
• All ports have this format’s register. (“x” means port-name.)
• For each register, refer to 3.5 Function of Ports.
• Before “HALT” instruction is executed, set each register pin-status. They will be
effective after CPU executes “HALT” instruction.
• This register is effective in all stand-by modes (IDLE2, IDLE1 or STOP).
• This register is effective when using PMC function. For details, refer to PMC
section.
The truth table to control Output/Input-buffer is below.
OE
0
PxnD Output buffer
Input buffer
OFF
0
1
0
1
OFF
OFF
OFF
ON
0
ON
1
OFF
1
OFF
Note1: OE means an output enable signal before stand-by mode.Basically, PxCR is used as OE.
Note2: “n” in PxnD means bit-number of PORTx.
The subsequent actions performed in each mode are as follows:
a.IDLE2: Only the CPU halts.
The internal I/O is available to select operation during IDLE2 mode by
setting the following register.
Table 3.3.2 shows the registers of setting operation during IDLE2 mode.
Table 3.3.2 SFR setting operation during IDLE2 mode
Internal I/O
SFR
TMRA01
TMRA23
TMRA45
TMRA67
TMRB0
TMRB1
SIO0
TA01RUN<I2TA01>
TA23RUN<I2TA23>
TA45RUN<I2TA45>
TA67RUN<I2TA67>
TB0RUN<I2TB0>
TB1RUN<I2TB1>
SC0MOD1<I2S0>
SBIBR0<I2SBI>
SBI
A/D converter
WDT
ADMOD1<I2AD>
WDMOD<I2WDT>
b.IDLE1: Only the oscillator, RTC (real-time clock), and MLD continue to
operate.
c. STOP: All internal circuits stop operating.
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Table 3.3.3 I/O operation during Halt Modes
Halt Mode
SYSCR2 <HALTM1:0>
IDLE2
11
IDLE1
10
STOP
01
CPU, MAC
I/O ports
Stop
Depends on PxDR register setting
TMRA, TMRB
SIO,SBI
Available to select
Operation block
A/D converter
Block
WDT
Stop
I2S, LCDC, SDRAMC,
Interrupt controller,
SPIC, DMAC, NDFC,
USB
Operate
RTC, MLD
Operate
(2) How to release the Halt mode
These HALT states can be released by resetting or requesting an interrupt. The halt
release sources are determined by the combination between the states of interrupt
mask register <IFF2:0> and the halt modes. The details for releasing the HALT status
are shown in Table 3.3.4.
• Released by requesting an interrupt
The operating released from the halt mode depends on the interrupt enabled status.
When the interrupt request level set before executing the HALT instruction exceeds
the value of interrupt mask register, the interrupt due to the source is processed after
releasing the halt mode, and CPU status executing an instruction that follows the
HALT instruction. When the interrupt request level set before executing the HALT
instruction is less than the value of the interrupt mask register, releasing the halt
mode is not executed.(in non-maskable interrupts, interrupt processing is processed
after releasing the halt mode regardless of the value of the mask register.) However
only for INT0 to INT5, INT6, INT7(unsynchronous interrupt), INTKEY,INTRTC,
INTALM interrupts, even if the interrupt request level set before executing the HALT
instruction is less than the value of the interrupt mask register, releasing the halt
mode is executed. In this case, interrupt processing, and CPU starts executing the
instruction next to the HALT instruction, but the interrupt request flag is held at “1”.
• Releasing by resetting
Releasing all halt status is executed by resetting.
When the STOP mode is released by RESET, it is necessary enough resetting time to
set the operation of the oscillator to be stable.
When releasing the halt mode by resetting, the internal RAM data keeps the state
before the “HALT” instruction is executed. However the other settings contents are
initialized. (Releasing due to interrupts keeps the state before the “HALT” instruction
is executed.)
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Table 3.3.4 Source of Halt state clearance and Halt clearance operation
Interrupt Enabled
(interrupt level) ≥ (interrupt mask) (interrupt level) < (interrupt mask)
Interrupt Disabled
Status of Received Interrupt
Halt mode
IDLE2
IDLE1
STOP
IDLE2
IDLE1
STOP
×
×
−
−
−
INTWDT
INT0 to 5 (Note1)
INTKEY
*1
*1
{
{
{
*2
*2
INTUSB
×
*1
{
{
×
{
×
*1
INT6 to 7(PORT) (Note1)
INT6 to 7(TMRB)
×
{
×
{
×
×
×
×
{
{
INTALM, INTRTC
INTTA0 to 7, INTTP0
INTTB00 to 01, INTTB10 to 11
INTRX,INTTX, INTSBI
INTI2S0 to 1, INTLCD,
INTAD, INTADHP
INTSPIRX,INTSPITX
INTRSC, INTRDY
INTDMA0 to 5
×
×
×
×
×
RESET
Reset initializes the LSI
: After clearing the Halt mode, CPU starts interrupt processing.
{: After clearing the Halt mode, CPU resumes executing starting from instruction following the HALT instruction.
×: It can not be used to release the halt mode.
−: The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is
not this combination type.
*1: Releasing the halt mode is executed after passing the warmming-up time.
*2: 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode. Therefore, the system of low
power dissipation can be built. However, the way of use is limited as below.
• Shift to IDLE1 mode :
Execute Halt instruction when the flag of INT_SUS or INT_CLKSTOP is “1” ( SUSPEND state )
• Release from IDLE1 mode :
Release Halt state by the request of INT_RESUME or INT_CLKON ( request of release SUSPEND )
Release Halt state by the request of INT_URST_STR or INT_URST_END ( request of RESET )
Note1: When the Halt mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold level
H until starting interrupt processing. If level L is set before holding level L, interrupt processing is correctly
started.
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(Example - releasing IDLE1 Mode)
An INT0 interrupt clears the Halt state when the device is in IDLE1 Mode.
Address
8200H
8203H
8206H
8209H
820BH
820EH
LD
(PCFC), 02H
(IIMC0), 00H
(INTE0), 06H
5
; Sets PC1 to INT0 interrupt.
; Select INT0 interrupt rising edge.
; Sets INT0 interrupt level to 6.
; Sets CPU interrupt level to 5.
; Sets Halt mode to IDLE1 mode.
; Halts CPU.
LD
LD
EI
LD
(SYSCR2), 28H
HALT
INT0
INT0 interrupt routine.
RETI
820FH
LD
XX, XX
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(3) Operation
a. IDLE2 Mode
In IDLE2 Mode, only specific internal I/O operations, as designated by the
IDLE2 Setting Register, can take place. Instruction execution by the CPU stops.
Figure 3.3.8 illustrates an example of the timing for clearance of the IDLE2
Mode Halt state by an interrupt.
X1
A0~A23
Data
D0~D31
RD
Data
WR
Interrupt for
releasing Halt
IDLE2
mode
Figure 3.3.8 Timing chart for IDLE2 Mode Halt state cleared by interrupt
b. IDLE1 Mode
In IDLE1 Mode, only the internal oscillator and the RTC and MLD continue to
operate. The system clock stops.
In the Halt state, the interrupt request is sampled asynchronously with the
system clock; however, clearance of the Halt state (i.e. restart of operation) is
synchronous with it.
Figure 3.3.9 illustrates the timing for clearance of the IDLE1 Mode Halt state by
an interrupt.
X1
A0~A23
D0~D31
RD
Data
Data
WR
Interrupt for
releasing Halt
IDLE1
mode
Figure 3.3.9 Timing chart for IDLE1 Mode Halt state cleared by interrupt
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c. STOP Mode
When STOP Mode is selected, all internal circuits stop, including the internal
oscillator.
After STOP Mode has been cleared system clock output starts when the warm-up
time has elapsed, in order to allow oscillation to stabilize.
Figure 3.3.10 illustrates the timing for clearance of the STOP Mode Halt state by an
interrupt.
Warm-up
time
X1
A0~A23
D0~D31
RD
Data
Data
Interrupt for
releasing Halt
STOP
mode
Figure 3.3.10 Timing chart for STOP Mode Halt state cleared by interrupt
Table 3.3.5 Example of warming-up time after releasing STOP-mode
@f
OSCH
=10 MHz
SYSCR2<WUPTM1:0>
10 (214)
01 (28)
11 (216)
25.6 us
1.6384 ms
6.5536 ms
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Table 3.3.6 Input Buffer State Table
Input Buffer State
In HALT mode (IDLE2/1/STOP)
<PxDR>=1 <PxDR>=0
When the CPU is operating
Input Function
Name
Port Name
During Reset
OFF
16bit Start OFF
Boot Start ON
16bit Start OFF
Boot Start ON
When Used
as function
Pin
When Used
as function
Pin
When Used as When Used
function Pin as Input port
When Used
as Input port
When Used
as Input port
D0-D7
D0-D7
−
−
−
ON upon
OFF
OFF
external read
P10-P17
D8-D15
P60-P67
−
−
−
−
−
−
−
−
P71-P74
P75
NDR/
W
ON
ON
OFF
P76
WAIT
P90
−
−
−
−
P91
RXD0
ON
ON
OFF
P92
CTS0 ,SCLK0
ON
P96 *1
P97
INT4
ON
ON
−
KI0-7
−
−
−
PA0-PA7 *1
PC0
INT0
ON
ON
OFF
PC1
INT1,TA0IN
INT2
PC2
PC3
INT3,TA2IN
−
PC4-PC7
PF0-PF5
PG0-PG2
PG4,PG5 *2
PG3 *2
PJ5-PJ6
PN0-PN7
PP1-PP2
PP3
−
−
−
−
−
−
ON upon port
read
−
−
OFF
OFF
ADTRG
ON
ON
ON
−
OFF
−
−
−
−
−
INT5
PP4
INT6,TB0IN0
ON
ON
OFF
PP5
INT7,TB1IN0
PR0
SPDI
PR1-PR3
PT0-PT7
PU0-PU4,
PU6,PU7
PU5
−
−
−
−
−
−
ON
ON
ON
−
PV0-PV2
PV6-PV7
PW0-PW7
PX5
−
SDA, SCL
OFF
−
X1USB
−
ON
ON
PX7
EI_PODDATA,
EI_SYNCLK,
EI_PODREQ,
EI_REFCLK,
EI_TRGIN,
PZ0-PZ5
ON
EI_COMRESET
PZ6-PZ7
DBGE
−
−
−
−
−
−
D+, D-
Always ON
RESET
AM0,AM1
X1,XT1
−
−
−
IDLE2/DLE1: ON
ON: The buffer is always turned on. A current flows the input buffer if the input *1: Port having a pull-up/pull-down resistor.
pin is not driven.
*2: AIN input does not cause a current to flow through the buffer.
OFF: The buffer is always turned off.
-
: No applicable
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Table 3.3.7 Output buffer State Table (1/2)
Output Buffer State
In HALT mode (IDLE2/1/STOP)
<PxDR>=1 <PxDR>=0
When Used When Used When Used
When the CPU is operating
Output Function
Name
Port Name
During Reset
When Used
as function
Pin
When Used
as Output
port
When Used
as function
Pin
as Output
port
as function as Output
Pin
port
D0-7
D0-7
OFF
−
−
−
ON upon
OFF
16bit Start ON
Boot Start OFF
external write
P10-17
D8-15
ON
ON
P40-P47
P50-P57
A0-A7
ON
A8-A15
16bit Start ON
Boot Start OFF
P60-67
A16-A23
OFF
P70
P71
P72
P73
P74
P75
P76
P80
P81
RD
WRLL , NDRE
WRLU , NDWE
EA24
ON
ON
ON
OFF
EA25
R/ W
−
−
−
−
OFF
CS0
ON
ON
CS1 , SDCS
CS2 , CSZA ,
SDCS
P82
P83
P84
CS3 , CSXA
CSZB
ON
ON
ON
OFF
P85
CSZC
P86
CSZD , ND0CE
CSXB , ND1CE
TXD0
P87
P90
OFF
P91
−
−
ON
−
−
ON
−
−
OFF
−
P92
SCLK0
P96
PX
−
ON
−
−
ON
−
−
OFF
−
P97
PY
PC0-PC3
PC4
PC5
PC6
PC7
PF0
PF1
PF2
PF3
PF4
PF5
PF7
PG2
PG3
PJ0
−
EA26
EA27
EA28
OFF
KO8
I2S0CKO
I2S0DO
I2S0WS
I2S1CKO
I2S1DO
I2S1WS
SDCLK
MX
ON
OFF
MY
SDRAS , SRLLB
SDCAS , SRLUB
SDWE , SRWR
SDLLDQM
SDLUDQM
NDALE
NDCLE
SDCKE
LCP0
PJ1
ON
ON
OFF
ON
PJ2
PJ3
PJ4
PJ5
OFF
PJ6
PJ7
ON
ON
OFF
PK0
PK1
PK2
PK3
PK4
PK5
PK6
PK7
PL0-PL7
LLOAD
LFR
LVSYNC
LHSYNC
LGOE0
LGOE1
LGOE2
LD0-LD7
ON
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Table 3.3.8 Output buffer state table (2/2)
Output Buffer State
In HALT mode (IDLE2/1/STOP)
<PxDR>=1 <PxDR>=0
When Used When Used When Used
When the CPU is operating
Output Function
Name
Port Name
During Reset
When Used
as function
Pin
When Used
as Output
port
When Used
as function
Pin
as Output
port
as function
Pin
as Output
port
PM1
PM2
PM7
MLDALM,TA1OUT
MLDALM , ALARM
PWE
ON
PN0-PN7
PP1
KO0-KO7
TA3OUT
TA5OUT
TA7OUT
−
ON
ON
OFF
OFF
ON
PP2
PP3
PP4-PP5
PP6
−
ON
−
−
ON
−
−
OFF
−
TB0OUT0
TB1OUT0
−
PP7
PR0
PR1
SPDO
SPCS
PR2
PR3
SPCLK
OFF
PT0-PT7
PU0-PU6
LD8-LD15
ON
ON
ON
ON
OFF
OFF
LD16-LD22
LD23
PU7
EO_TRGOUT
ON
PV0
PV1
SCLK0
OFF
−
−
−
−
PV2
−
PV3-PV4
PV6
−
ON
OFF
ON
SDA
ON
ON
OFF
PV7
SCL
PW0-PW7
PX4
−
−
−
−
CLKOUT, LDIV
ON
ON
OFF
PX5
−
−
−
−
−
PX7
OFF
OFF
PZ0-PZ5
−
EO_MCUDATA,
EO_MCUREQ
PZ6-PZ7
D+, D-
ON
ON
ON
−
ON/OF depend on USBC operation
IDLE2/1:ON,
X2
−
STOP: output ”H”
IDLE2/1:ON,
Always ON
XT2
−
STOP: output ”HZ”
ON: The buffer is always turned on. When the bus is released, *1: Port having a pull-up/pull-down resistor.
however, output buffers for some pins are turned off.
OFF: The buffer is always turned off.
-
: No applicable
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3.4 Boot ROM
The TMP92CZ26A contains boot ROM for downloading a user program, and supports two
kinds of downloading methods.
3.4.1
Operation Modes
The TMP92CZ26A has two operation modes: MULTI mode and BOOT mode. The
operation mode is selected according to the AM1 and AM0 pin levels when RESET is
asserted.
(1) MULTI mode:
(2) BOOT mode:
After reset, the CPU fetches instructions from external memory and
executes them.
After reset, the CPU fetches instructions from internal boot ROM
and executes them. The boot ROM loads a user program into internal
RAM from USB, or via UART, and then branches to the internal
RAM. In this way the user program starts boot operation. Table 3.4.2
shows an outline of boot operation.
Table 3.4.1 Operation Modes
Mode Setting Pins
Operation Mode
RESET
AM1
AM0
0
1
1
0
1
0
1
0
MULTI
Start from external 16-bit bus memory
TEST (Setting prohibited)
BOOT (Start from internal boot ROM)
TEST (Setting prohibited)
Table 3.4.2 Outline of Boot Operation
Loading
Operation after
Loading
Name
Priority
Source
I/F
Destination
(a)
(b)
1
2
PC (UART)
UART
USB
Branch to internal
RAM
Internal RAM
PC (USB_HOST)
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3.4.2
Hardware Specifications of Internal Boot ROM
(1) Memory map
Figure 3.4.1 shows a memory map of BOOT mode.
The boot ROM incorporated in the TMP92CZ26A is an 8-Kbyte ROM area mapped to
addresses 3FE000H to 3FFFFFH.
In MULTI mode, the boot ROM is not mapped and the above area is mapped as an
external area.
000000H
Internal I/O
001FF0H
002000H
010000H
Internal RAM
(288 Kbytes)
046000H
(Internal Backup RAM 16 Kbytes)
04A000H
3FE000H
Internal Boot ROM
(8 Kbytes)
3FFF00H
(B) Reset/Interrupt (Note)
Vector Area (256 bytes)
400000H
FFFF00H
(A) Reset/Interrupt (Note)
Vector Area (256 bytes)
FFFFFFH
Note: BROMCR<VACE> = “1” : (B) when booting
BROMCR<VACE> = “0” : (A) when multi mode
Figure 3.4.1 Memory Map of BOOT Mode
(2) Switching the boot ROM area to an external area
After the boot sequence is executed in BOOT mode, an application system program
may start running without a reset being asserted. In this case, it is possible to switch
the boot ROM area to an external area.
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3.4.3
Outline of Boot Operation
The method for downloading a user program can be selected from two types: from UART,
or via USB.
After reset, the boot program on the internal boot ROM executes as shown in Figure 3.4.2.
Regardless of the downloading method used, the boot program downloads a user program
boot program uses the internal RAM (common to all the downloading methods).
Start
Yes
RESUME check
PMCCTL<PCM_ON>=1
No
Clock setting
• fSYS = fOSCH
• fUSB = fOSCH × 24/5
(a)
(b)
Yes
UART
check
No
Download via UART
No
USB
check
Yes
Download via
USB
Branch to internal RAM
46000h
Branch to internal RAM
3000h
Note 1:To download a user program via USB, a USB device driver and special application software are needed on
the PC.
Note 2: To download a user program via UART, special application software is needed on the PC.
Note 3: The (a), (b) in the above flowchart indicate points where the settings of external port pins are changed. For
details, see Table 3.4.3.
Figure 3.4.2 Flowchart for Internal Boot ROM Operation
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(1) Port settings
Table 3.4.3 shows the port settings by the boot program. When designing your
for using the boot program.
The boot program only sets the ports shown in the table below; other ports are left as
they are after reset or at startup of the boot program.
Table 3.4.3 Port Settings by the Boot Program
Description
(b)
Function
Name
Port Name
I/O
(a)
(c)
UART
No change from after reset
state (input port)
P90
TXD0
Output
Set as TXD0 output pin
No change from (b)
No change from (a)
P91
−−−
−−−
RXD0
D+
Input
I/O
Set as RXD0 input pin
USB
No change
D−
I/O
No change from after reset
state (input port)
PU6
PUCTL
Output
Set as output port
No change from (b)
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Table 3.4.4 Recommended Pin Connections
Recommended Pin Connections for Each Download Method
Function
Name
Port Name
I/O
UART
USB
UART P90
P91
TXD0
Output
Input
Connect to the level shifter.
No special setting is needed
for booting via USB.
RXD0
Add a pull-up resistor (100
kΩ recommended) to prevent
transition to UART processing.
USB
−−−
D+
I/O
No special setting is needed
for booting via UART.
Connect to the USB connector
by adding a dumping resistor
(27Ω recommended) and a
programmable pull-up resistor
(1.5 kΩ recommended). When
USB is not accessed, the pin
level should be fixed with a
resistor to prevent flow-through
current.
−−−
D−
I/O
Connect to the USB connector
by adding a dumping resistor
(27Ω recommended). When
USB is not accessed, the pin
level should be fixed with a
resistor to prevent flow-through
current.
If USB is not used, add a
pull-up or pull-down resistor to
prevent flow-through current
on the D+/D- pins.
PU6
PUCTL
Output
This pin is used to control
ON/OFF of the D+ pin’s
pull-up resistor. Add a switch
externally so that the pull-up is
turned on when “1”. Reset sets
this pin as an input port, so
add a pull-down resistor (100
kΩ recommended).
−
Note 1: When a user program is downloaded from UART and USB is used in the system, the pull-up resistor for USB’s D+ pin
should not be turned on in BOOT mode.
Note 2: When a user program is downloaded via USB, do not start the UART application software on the PC.
Note 3: When a user program is downloaded via UART, do not connect a USB connector.
Note 4: When USB is not used, the D+ and D- pins must be pulled up or down to prevent flow-through current.
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(2) I/O register settings
Table 3.4.5 shows the I/O registers that are set by the boot program.
After the boot sequence, if execution moves to an application system program
without a reset being asserted, the settings of these I/O registers must be taken into
account. Also note that the registers in the CPU and the internal RAM remain in the
state after execution of the boot program.
Table 3.4.5 I/O Register Settings by Boot Program
Register Name Set Value
Description
Watchdog timer not active
WDMOD
WDCR
00H
B1H
70H
00H
2CH
00H
Watchdog timer disabled
High-frequency and low-frequency oscillators operating
Clock gear = 1/1
SYSCR0
SYSCR1
SYSCR2
PLLCR0
Initial value
PLL clock not used
PLLCR1
00H
or
Normally PLL is disabled.
However, only in the case of booting via USB, PLL is
activated for USB.
60H
04H
44H
INTEUSB
INTETC01
USB interrupt level setting
INTTC interrupt level setting
Note: The values to be set in the I/O registers for UART and USB are not described here. If these functions are
needed in a user program, set each I/O register as necessary.
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3.4.4
Downloading a User Program via UART
(1) Connection example
Figure 3.4.4 shows an example of connections for downloading a user program via
UART (using a 16-bit NOR Flash memory device as program memory).
UART 3 pins
TXD
TXD0 P90 (OUT)
RXD0, P91 (IN)
D+ D-
P82, CS2
Level
Shifter
RXD
PC
CE
OE
WE
RTS
P70, RD
PJ2, SRWR
TMP92CZ26A
NOR
AM0
AM1
Flash Memory
D0 toD15
D0 to D15
A1 to 20
A0 toA19
Note: When USB is not used, add a pull-up or pull-down resistor to the D+ and D- pins to prevent flow-through
current.
Figure 3.4.4 UART Connection Example
(2) UART interface specifications
SIO channel 0 is used for downloading a user program.
The UART communication format in BOOT mode is shown below. Before booting, the
PC must also be set up with the same conditions.
Although the default baud rate is 9600 bps, this can be changed as shown in Table
Serial transfer mode:
Data length
:
:
:
:
:
:
UART (asynchronous) mode, full-duplex
8 bits
Parity bit
None
STOP bit
1 bit
Handshake
None
Baud rate (default)
9600 bps
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(3) UART data transfer format
rate modification command, operation command, and version management
information, respectively.
Please also refer to the description of boot program operation later in this section.
Table 3.4.6 Supported Frequencies (X1)
6.00 MHz
8.00 MHz
9.00 MHz
10.00 MHz
Note: The built-in PLL (clock multiplier) is not used regardless of the oscillation frequency.
Table 3.4.7 Transfer Format
Byte Number to
Transfer
Transfer data from PC to TMP92CZ26A
Baud Rate
Transfer data from TMP92CZ26A to PC
Boot
1st byte
Matching data (5AH)
9600 bps
− (Frequency measurement and baud
rate auto setting)
ROM
OK: Echo back data (5AH)
Error: No transfer
2nd byte
−
−
3rd byte
to
Version management information
6th byte
7th byte
8th byte
9th byte
−
Frequency information
−
Baud rate modification command
OK: Echo back data
Error: Error code x 3
−
10th byte
to
User program
New baud rate NG: Operation stop by checksum error
Intel Hex format (binary)
(n − 4)th byte
(n − 3)th byte
−
−
OK: SUM (High)
(See (4)-c).)
(n − 2)th byte
OK: SUM (Low)
−
(n − 1)th byte
User program start command (C0H)
OK: Echo back data (C0H)
Error: Error code x 3
n’th byte
−
RAM
−
Branch to user program start address
“Error code x 3” means that the error code is transmitted three times. For example, if the error code is 62H, the
TMP92CZ26A transmits 62H three times. For error codes, see (4)-b).
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Table 3.4.8 Baud Rate Modification Command
Baud Rate (bps)
9600
28H
19200
18H
38400
07H
57600
06H
115200
03H
Modification Command
Note 1: If f
OSCH
(oscillation frequency) is 10.0 MHz, 57600 and 115200 bps are not supported.
Note 2: If f
OSCH
(oscillation frequency) is 6.00, 8.00, or 9.00 MHz, 38400, 57600, and 115200 bps are not
supported.
Table 3.4.9 Operation Command
Operation Command
C0H
Operation
User program start
Table 3.4.10 Version Management Information
Version Information
FRM1
ASCII Code
46H, 52H, 4DH, 31H
Table 3.4.11 data of measuring frequency
X1-X2 oscillator frequency
(MHz)
6.000
09H
8.000
0AH
9.000
08H
10.000
0BH
(4) Description of the UART boot program operation
The boot program receives a user program sent from the PC via UART and transfers
it to the internal RAM. If the transfer ends normally, the boot program calculates
SUM and sends the result to the PC before executing the user program. The execution
start address is the first address received. The boot program enables users to perform
customized on-board programming.
When UART is used to download a user program, the maximum allowed program
size is 282 Kbytes (3000H – 49800H). (The extended Intel Hex format is supported.)
a) Operation procedure
1. Connect the serial cable. This must be done before the microcontroller is reset.
2. Set the AM1 and AM0 pins to “1” and reset the microcontroller.
3. The receive data in the 1st byte is matching data (5AH). Upon starting in
BOOT mode, the boot program goes to a state in which it waits for matching
data. When matching data is received, the initial baud rate of the serial
channel is automatically set to 9600 bps.
4. The 2nd byte is used to echo back 5AH to the PC upon completion of the
automatic baud rate setting in the 1st byte. If automatic baud rate setting fails,
the boot program stops operation.
5. The 3rd through 6th bytes are used to send the version management
information of the boot program in ASCII code. The PC should check that the
correct version of the boot program is used.
6. The 7th byte is used to send information on the measured frequency. The PC
should check that the frequency of the resonator is measured correctly.
7. The receive data in the 8th byte is baud rate modification data. The five kinds
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the baud rate is not changed, the initial baud rate data (28H: 9600 bps) must
be sent. Baud rate modification becomes effective after the echo back
transmission is completed.
8. The 9th byte is used to echo back the received data to the PC when the data
received in the 8th byte is one of the baud rate modification data
corresponding to the operating frequency of the microcontroller. Then, the
baud rate is changed. If the received baud rate data does not correspond to the
operating frequency, the boot program stops operation after sending the baud
rate modification error code (62H).
9. The receive data in the 10th to (n-4)th bytes is received as binary data in Intel
Hex format. No echo back data is returned to the PC.
The boot program ignores received data and does not send error code to the PC
until it receives the start mark (3AH for “:”) of Intel Hex format. After
receiving the start mark, the boot program receives a range of data from
record length to checksum and writes the received data to the specified RAM
addresses successively.
If a receive error or checksum error occurs, the boot program stops operation
without sending error code to the PC.
The boot program executes the SUM calculation routine upon detecting the
end record. Thus, after sending the end record, the PC should be placed in a
state in which it waits for SUM data.
10. The (n-3)th and (n-2)th bytes are used to send the SUM value to the PC in the
order of upper byte and lower byte. For details on how to calculate SUM, see
“SUM calculation” to be described later. SUM calculation is performed after
detecting the end record only when no receives error or checksum error has
occurred. Immediately after SUM calculation is completed, the boot program
sends the SUM value to the PC. After sending the end record, the PC should
determine whether or not writing to RAM has completed successfully based
on whether or not the SUM value is received from the boot program.
11. After sending the SUM value, the boot program waits for the user program
start command (C0H). If the SUM value is correct, the PC should send the
user program start command in the (n-1)th byte.
12. The n’th byte is used to echo back the user program start command to the PC.
After sending the echo back data, the boot program sets the stack pointer to
4A000H and jumps to the address that is received first as Intel Hex format
data.
13. If the user program start command is not correct or a receive error has
occurred, the boot program stops operation after sending the error code to the
PC three times.
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b) Error codes
PC of its processing status.
Table 3.4.12 Error Codes
Error Code
62H
Meaning
Unsupported baud rate
64H
A1H
A3H
Invalid operation command
Framing error in received data
Overrun error in received data
Note 1: If a receive error occurs while a user program is being received, no error code will be sent to the PC.
Note 2: After sending an error code, the boot program stops operation.
c) SUM calculation
1. Calculation method
SUM is calculated by adding data in bytes and is returned in words, as
explained below.
Example:
If the data to be calculated consists of the 4 bytes
A1H
B2H
C3H
D4H
shown to the left, SUM is calculated as follows:
A1H + B2H + C3H + D4H = 02EAH
SUM (HIGH) = 02H
SUM (LOW) = EAH
2. Data to be calculated
SUM is calculated from the data at the first received address through the last
received address.
Even if received addresses are not continuous, unwritten addresses are also
included in SUM calculation. The user program should not contain unwritten
gaps.
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d) Notes on Intel Hex format (binary)
1. After receiving the checksum of a record, the boot program waits for the start
mark (3AH for “:”) of the next record. If data other than 3AH is received
between records, it is ignored.
2. Once the PC program has finished sending the checksum of an end record, it
must wait for 2 bytes of data (upper and lower bytes of SUM) before sending
any other data. This is because after receiving the checksum of an end record,
the boot program calculates SUM and returns the result to the PC in 2 bytes.
3. Writing to areas other than internal RAM may cause incorrect operation. To
transfer a record, set the paragraph address to 0000H.
4. Since the address pointer is initially set to 00H, the record type to be
transferred first does not have to be an address record.
5. Addresses 3000H to 49800H are allocated as the user program download
area.
6. A user program in Intel Hex format (ASCII codes) must be converted into
binary data in advance, as explained in the example below.
Example: How to convert an Intel Hex file into binary format
The following shows how an Intel Hex format file is displayed on a text editor.
: 103000000607F100030000F201030000B1F16010B7
: 00000001FF
However, the actual data consists of ASCII codes, as shown below.
3A3130333030303030303630374631303030333030303046323031303330303030
423146313630313042370D0A3A303030303030303146460D0A
Thus, the ASCII codes must be converted into binary data based on the conversion rules
shown in the table below.
ASCII Code
Binary Data
3A
3A (Only 3A remains the same.)
30 to 39
41 or 61
42 or 62
43 or 63
44 or 64
45 or 65
46 or 66
0D0A
0 to 9
A
B
C
D
E
F
Delete
Intel Hex format
Data record
3A 10 3000 00 0607F100030000F201030000B1F16010 B7
Data
Checksum
Record type
Address
Record length
: (Start mark)
3A 00 0000 01 FF
Data
Record type
Address
Record length
: (Start mark)
End record
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e) User program receive error
If either of the following error conditions occurs while a user program is being
received, the boot program stops operation.
If the record type is other than 00H, 01H, or 02H
If a checksum error occurs
f) Measured frequency/baud rate error
When the boot program receives matching data, it measures the oscillation
frequency. If an error is within plus or minus 3%, the boot program decides on that
frequency.
in the case of 10.00 MHz /9600 bps, the baud rate is actually set at 9615.38 bps. To
establish communication, the sum of the baud rate setting error and the measured
frequency error must be within plus or minus 3 %.
Table 3.4.13 Baud Rate Setting Errors (%)
9600 bps
19200 bps
38400 bps
57600 bps
115200 bps
6.000 MHz
8.000 MHz
9.000 MHz
10.000 MHz
0.2
0.2
0.2
0.2
0.2
0.2
−
−
−
−
−
−
−
−
−
−
−0.7
0.2
−
−1.4
−: Not supported
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(5) Others
a) Handshake function
Although the CTS pin is available in the TMP92CZ26A, the boot program does
not use it for transfer control.
b) RS-232C connector
The RS-232C connector must not be connected or disconnected while the boot
program is running.
c) Software on the PC
When downloading a user program via UART, special application software is
needed on the PC.
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3.4.5
Downloading a User Program via USB
(1) Connection example
Figure 3.4.5 shows an example of connections for downloading a user program via
USB (using a 16-bit NOR Flash memory device as program memory).
PUCTL
PU6, LD22
RXD,P91
P82, CS2
R4 =
100 kΩ
R2 = 27 Ω
CE
OE
WE
P70, RD
PJ2, SRWR
R1 = 1.5 kΩ
D+
PC
D−
TMP92CZ26A
R3 = 27 Ω
NOR Flash
D0 to D15
AM0
AM1
D0 to D15
A0 to A19
A1 to A20
Note 1: The value of pull-up and pull-down resistors are recommended values.
Note 2: The PU6 and LD22 pins are assigned as PUCTL (pull-up control) output for USB. Be careful about this if the
system uses the 24-bit TFT display function.
Note 3: Since the input gates of the D+ and D- pins are always open even at unused (unaccessed) times, these pins
must be set to a fixed level to prevent flow-through current. Although the level setting is not specified in the
above diagram, be sure to fix the level of the D+ and D- pins by referring to the chapter on USB.
Figure 3.4.5 USB Connection Example
(2) USB interface specifications
When a user program is downloaded via USB, the oscillation frequency should be set
to 10.00 MHz. The transfer speed should be fixed to full speed (12 Mbps).
The boot program uses the following two transfer types.
Table 3.4.14 Transfer Types Used by the Boot Program
Transfer Type
Description
Control Transfer
Bulk Transfer
Used for transmitting standard requests and vendor requests.
Used for responding to vendor requests and transmitting a user program.
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The following shows an overview of the USB communication flow.
(Legends)
Control Transfer
Bulk Transfer
Host (PC)
TMP92CZ26A
Send GET_DISCRIPTOR
Connection
Recognition
Send DESCRIPTOR information
Send the microcontroller information command
Send microcontroller information data
Prepare microcontroller
information data
Check data
Data Transfer
Send the microcontroller information command
Send microcontroller information data
Convert Intel Hex
format data into binary
data
Prepare microcontroller
information data
Check data
Send data
Send the user program transfer start command
Send a user program
Load the received data into the
specified RAM address area
& prepare microcontroller
information data
(If the received data cannot be loaded
into RAM for some reason, it is
discarded.)
Transfer End
Processing
Transmit the transfer result
command 2 seconds after
completion of user
Send the transfer result command
Send transfer result data
program transfer
Prepare transfer result data
Check data
Branch to
internal RAM
Figure 3.4.6 Overall Flowchart
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Table 3.4.15 Vendor Request Commands
Command Name
Value of
Operation
Notes
bRequest
Microcontroller information
command
00H
02H
Send microcontroller Microcontroller information data is
information
sent by bulk IN transfer after the
setup stage is completed.
User program transfer start
command
Receive a user
program
Set the size of a user program in
wIndex.
The user program is received by bulk
OUT transfer after the setup stage is
completed.
User program transfer result
command
04H
Send the transfer
result
Transfer result data is sent by bulk IN
transfer after the setup stage is
completed.
Table 3.4.16 Setup Command Data Structure
Field Name
Value
Meaning
bmRequestType
40H
D7
0: Host to Device
D6-D5 2: Vendor
D4-D0 0: Device
bRequest
00H, 02H, 04H
00H~FFFFH
00H: Microcontroller information
02H: User program transfer start
04H: User program transfer result
wValue
Own data number
(Not used by boot program)
User program size
wIndex
00H~FFFFH
0000H
(Used when starting a user program transfer)
Fixed
wLength
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Table 3.4.17 Standard Request Commands
Standard Request
Response Method
GET_STATUS
CLEAR_FEATURE
SET_FEATURE
Automatic response by hardware
Automatic response by hardware
Automatic response by hardware
Automatic response by hardware
Automatic response by hardware
Not supported
SET_ADDRESS
GET_DISCRIPTOR
SET_DISCRIPTOR
GET_CONFIGRATION
SET_CONFIGRATION
GET_INTERFACE
SET_INTERFACE
SYNCH_FRAME
Automatic response by hardware
Automatic response by hardware
Automatic response by hardware
Automatic response by hardware
Ignored
Table 3.4.18 Information Returned by GET_DISCRIPTOR
DeviceDescriptor
Field Name
Value
Meaning
Blength
12H
18 bytes
BdescriptorType
BcdUSB
01H
Device descriptor
USB Version 1.1
0110H
00H
BdeviceClass
BdeviceSubClass
BdeviceProtocol
BmaxPacketSize0
IdVendor
Device class (Not in use)
Sub command (Not in use)
Protocol (Not in use)
EP0 maximum packet size (64 bytes)
Vendor ID
00H
00H
40H
0930H
6504H
0001H
00H
IdProduct
Product ID (0)
BcdDevice
Device version (v0.1)
Imanufacturer
Index value of string descriptor indicating manufacturer
name
Iproduct
00H
00H
Index value of string descriptor indicating product name
IserialNumber
Index value of string descriptor indicating product serial
number
BnumConfigurations
01H
There is one configuration.
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ConfigrationDescriptor
Field Name
Value
Meaning
bLength
09H
9 bytes
Configuration descriptor
bDescriptorType
wTotalLength
02H
Total length (32 bytes) which each descriptor of both
configuration descriptor, interface
0020H
and endpoint is added.
bNumInterfaces
bConfigurationValue
iConfiguration
01H
01H
00H
There is one interface.
Configuration number 1
Index value of string descriptor indicating
configuration name (Not in use)
bmAttributes
MaxPower
80H
31H
Bus power
Maximum power consumption (49 mA)
InterfaceDescriptor
Field Name
Value
Meaning
bLength
09H
04H
00H
00H
02H
FFH
00H
50H
00H
9 bytes
bDescriptorType
bInterfaceNumber
bAlternateSetting
bNumEndpoints
bInterfaceClass
bInterfaceSubClass
bInterfaceProtocol
iIinterface
Interface descriptor
Interface number 0
Alternate setting number 0
There are two endpoints.
Specified device
Bulk only protocol
Index value of string descriptor indicating interface
name (Not in use)
EndpointDescriptor
Field Name
Value
Meaning
<Endpoint1>
blength
07H
05H
7 bytes
bDescriptorType
bEndpointAddress
bmAttributes
wMaxPacketSize
bInterval
Endpoint descriptor
EP1= OUT
01H
02H
Bulk transfer
0040H
00H
Payload 64 bytes
(Ignored for bulk transfer)
<Endpoint2>
bLength
07H
05H
7 bytes
bDescriptor
Endpoint descriptor
EP2 = IN
bEndpointAddress
bmAttributes
wMaxPacketSize
bInterval
82H
02H
Bulk transfer
0040H
00H
Payload 64 bytes
(Ignored for bulk transfer)
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Table 3.4.19 Information Returned for the Microcontroller Information Command
Microcontroller Information
TMP92CZ26A
ASCII Code
54H, 4DH, 50H, 39H, 32H, 43H, 5AH, 32H, 36H,20H, 20H, 20H, 20H, 20H, 20H
Table 3.4.20 Information Returned for the User Program Transfer Result Command
Transfer Result
Value
Error Conditions
No error
00H
02H
User program not received
The user program transfer result is received without the user program
transfer start command being received first.
Received file not in Intel Hex format
User program size error
04H
06H
The first data of a user program is not “:” (3AH).
The size of a received user program is larger than the value set in
wIndex of the user program transfer start command.
Download address error
08H
0AH
The specified user program download address is not in the designated
area.
The user program size is over 10 Kbytes.
Protocol error or other error
The user program transfer start or user program transfer result
command is received first.
A checksum error is detected in the Intel Hex file.
A record type error is detected in the Intel Hex file.
The length of an address record in the Intel Hex file is 3 or longer.
The length of an end record in the Intel Hex file is other than 0.
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(3) Description of the USB boot program operation
The boot program loads a user program in Intel Hex format sent from the PC into the
internal RAM. When the user program has been loaded successfully, the user program
starts executing from the first address received.
The boot program thus enables users to perform customized on-board programming.
a. Operation procedure
1. Connect the USB cable.
2. Set the AM0 and AM1 pins to “1” and reset the microcontroller.
3. After recognizing USB connection, the PC checks the information on the
connected device using the GET_DISCRIPTOR command.
4. The PC sends the microcontroller information command by control transfer
(vendor request). After the setup stage is completed, the PC checks
microcontroller information data by bulk IN transfer.
5. Upon receiving the microcontroller information command, the boot program
prepares microcontroller information in ASCII code.
6. The PC prepares the user program to be loaded by converting an Intel Hex file
into binary format.
7. The PC sends the user program transfer start command by control transfer
(vendor request). After the setup stage is completed, the PC transfers the user
program by bulk OUT transfer.
8. After the user program has been transferred, the PC waits for about two
seconds and then sends the user program transfer result command by control
transfer (vendor request). After the setup stage is completed, the PC checks
the transfer result by bulk IN transfer.
9. Upon receiving the user program transfer result command, the boot program
prepares the transfer result value to be returned.
10. If the transfer result is other than OK, the boot program enters the error
processing routine and will not automatically recover from it. In this case,
terminate the device driver on the PC and retry from step 2.
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b. Notes on the user program format (binary)
1. After receiving the checksum of a record, the boot program waits for the start
mark (3AH for “:”) of the next record. If data other than 3AH is received
between records, it is ignored.
2. Since the address pointer is initially set to 00H, the record type to be
transferred first does not have to be an address record.
3. Addresses 3000H to 497FFH (282 Kbytes) are allocated as the user program
download area. The user program should be contained within this area.
4. A user program in Intel Hex format (normally written in ASCII code) must be
converted into binary data before it can be transferred. See the example
below for how to convert an Intel Hex file into binary format.
When a user program is downloaded via USB, the maximum allowed record
length is 250 bytes.
Example: Transfer data when writing 16-byte data in Intel Hex format from address 3000H
The following shows how an Intel Hex format file is displayed on a text editor.
: 103000000607F100030000F201030000B1F16010B7
: 00000001FF
However, the actual data consists of ASCII codes, as shown below.
3A3130333030303030303630374631303030333030303046323031303330303030
423146313630313042370D0A3A303030303030303146460D0A
Thus, the ASCII codes must be converted into binary data based on the conversion rules shown
in the table below.
ASCII Code
Binary Data
3A
3A (Only 3A remains the same.)
30~39
0~9
41 or 61
42 or 62
43 or 63
44 or 64
45 or 65
46 or 66
0D0A
A
B
C
D
E
F
Delete
The above Intel Hex file is converted into binary data as follows:
Data record
3A 10 3000 00 0607F100030000F201030000B1F16010 B7
Data
Checksum
Record type
Address
Record length
: (Start mark\)
3A 00 0000 01 FF
Checksum
Record type
Address
Record length
: (Start mark)
End record
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(4) Others
a) USB connector
The USB connector must not be connected or disconnected while the boot
program is running.
b) Software on the PC
To download a user program via USB, a USB device driver and special
application software are needed on the PC.
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3.5 Interrupts
Interrupts are controlled by the CPU Interrupt Mask Register <IFF2 to 0> (bits 12 to 14
of the Status Register) and by the built-in interrupt controller.
TMP92CZ26A has a total of 56 interrupts divided into the following five types:
Interrupts generated by CPU: 9 sources
• Software interrupts: 8 sources
• Illegal Instruction interrupt: 1 source
Internal interrupts: 38 sources
• Internal I/O interrupts: 30 sources
• Micro DMA Transfer End interrupts /HDMA Transfer End interrupts: 6 sources
• Micro DMA Transfer End interrupts: 2 source
External interrupts: 9 sources
• Interrupts on external pins (INT0 to INT7, INTKEY)
A fixed individual interrupt vector number is assigned to each interrupt source. Any one of
seven levels of priority can also be assigned to each maskable interrupt. Non-maskable
interrupts have a fixed priority level of 7, the highest level.
When an interrupt is generated, the interrupt controller sends the priority of that interrupt
to the CPU. When more than one interrupt are generated simultaneously, the interrupt
controller sends the priority value of the interrupt with the highest priority to the CPU. (The
highest priority level is 7, the level used for non-maskable interrupts.)
The CPU compares the interrupt priority level which it receives with the value held in the
CPU interrupt mask register <IFF2:0>. If the priority level of the interrupt is greater than or
equal to the value in the interrupt mask register, the CPU accepts the interrupt.
However, software interrupts and illegal instruction interrupts generated by the CPU, and
are processed irrespective of the value in <IFF2:0>.
The value in the interrupt mask register <IFF2:0> can be changed using the EI instruction
(EI num sets <IFF2:0> to num). For example, the command EI3 enables the acceptance of all
non-maskable interrupts and of maskable interrupts whose priority level, as set in the
interrupt controller, is 3 or higher. The commands EI and EI0 enable the acceptance of all
non-maskable interrupts and of maskable interrupts with a priority level of 1 or above (hence
both are equivalent to the command EI1).
The DI instruction (Sets <IFF2:0> to 7) is exactly equivalent to the EI7 instruction. The DI
instruction is used to disable all maskable interrupts (since the priority level for maskable
interrupts ranges from 0 to 6). The EI instruction takes effect as soon as it is executed.
In addition to the general-purpose interrupt processing mode described above, there is also a
micro DMA processing mode that can transfer data to internal/external memory and built-in
I/O, and HDMA processing mode. In micro DMA mode the CPU, and in HDMA mode the DMA
controller automatically transfers data in 1byte, 2byte or 4byte blocks. HDMA mode allows
transfer faster than Micro DMA mode.
In addition, the TMP92CZ26A also has a software start function in which micro DMA and
HDMA processing is requested in software rather than by an interrupt. Figure 3.5.1 is a
flowchart showing overall interrupts processing.
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DMA soft start
Interrupt processing
request
Interrupt specified
by DMA
YES
start vector ?
Clear interrupt request flag
NO
Interrupt vector calue “V”
read interrupt request F/F clear
to HDMA processing flow
YES
Start specified
by HDMA
General-purpose
interrupt
NO
PUSH
PUSH
SR<IFF2:0> ← Level of
PC
SR
Data transfer by micro
DMA
processing
accepted
interrupt + 1
Micro DMA
processing
INTNEST ← INTNEST + 1
COUNT ← COUNT − 1
PC ← (FFFF00H + V)
YES
Clear vector register
generating micro DMA
transfer end interrupt
(INTTC0)
COUNT = 0
NO
Interrupt processing
program
RETI instruction
POP SR
POP PC
INTNEST ← INTNEST − 1
End
Figure 3.5.1 Interrupt processing Sequence
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3.5.1 General-purpose Interrupt Processing
When the CPU accepts an interrupt, it usually performs the following sequence of
operations. However, in the case of software interrupts and illegal instruction interrupts
generated by the CPU, the CPU skips steps (1) and (3), and executes only steps (2), (4), and
(5).
(1) The CPU reads the interrupt vector from the interrupt controller. When more than one
interrupt with the same priority level have been generated simultaneously, the
interrupt controller generates an interrupt vector in accordance with the default
priority and clears the interrupt requests. (The default priority is determined as
follows: The smaller the vector value, the higher the priority.)
(2) The CPU pushes the program counter (PC) and status register (SR) onto the top of the
stack (Pointed to by XSP).
(3) The CPU sets the value of the CPU’s interrupt mask register <IFF2:0> to the priority
level for the accepted interrupt plus 1. However, if the priority level for the accepted
interrupt is 7, the register’s value is set to 7.
(4) The CPU increments the interrupt nesting counter INTNEST by 1.
(5) The CPU jumps to the address given by adding the contents of address FFFF00H + the
interrupt vector, then starts the interrupt processing routine.
On completion of interrupt processing, the RETI instruction is used to return control
to the main routine. RETI restores the contents of the program counter and the status
register from the stack and decrements the interrupt nesting counter INTNEST by 1.
Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts,
however, can be enabled or disabled by a user program. A program can set the priority
level for each interrupt source. (A priority level setting of 0 or 7 will disable an interrupt
request.) If an interrupt request is received for an interrupt with a priority level equal to
or greater than the value set in the CPU interrupt mask register <IFF2:0>, the CPU will
accept the interrupt. The CPU interrupt mask register <IFF2:0> is then set to the value
of the priority level for the accepted interrupt plus 1.
If during interrupt processing, an interrupt is generated with a higher priority than the
interrupt currently being processed, or if, during the processing of a non-maskable
interrupt processing, a non-maskable interrupt request is generated from another source,
the CPU will suspend the routine which it is currently executing and accept the new
interrupt. When processing of the new interrupt has been completed, the CPU will resume
processing of the suspended interrupt.
If the CPU receives another interrupt request while performing processing steps (1) to
(5), the new interrupt will be sampled immediately after execution of the first instruction
of its interrupt processing routine. Specifying DI as the start instruction disables nesting
of maskable interrupts.
After a reset, initializes the interrupt mask register <IFF2:0> to 111, disabling all
maskable interrupts.
Table 3.5.1 shows the TMP92CZ26A interrupt vectors and micro DMA start vectors.
FFFF00H to FFFFFFH (256 bytes) is designated as the interrupt vector area.
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Table 3.5.1 TMP92CZ26A Interrupt Vectors and Micro DMA/HDMA Start Vectors
Micro DMA
/HDMA Start
Vector
Default
Priority
Interrupt Source and Source of
Micro DMA Request
Vector Address Refer
Value to Vector
Type
1
Reset or [SWI0] instruction
0000H
FFFF00H
2
[SWI1] instruction
0004H
0008H
000CH
0010H
0014H
0018H
001CH
0020H
0024H
−
FFFF04H
FFFF08H
FFFF0CH
FFFF10H
FFFF14H
FFFF18H
FFFF1CH
FFFF20H
FFFF24H
−
3
Illegal instruction or [SWI2] instruction
[SWI3] instruction
4
Non
maskable
5
[SWI4] instruction
6
[SWI5] instruction
7
[SWI6] instruction
8
[SWI7] instruction
9
(Reserved)
10
−
INTWD: Watchdog timer
Micro DMA (Note 2)
INT0: INT0 pin input
INT1: INT1 pin input
INT2: INT2 pin input
INT3: INT3 pin input
INT4: INT4 pin input (TSI)
INTALM: ALM(8KHz, 512Hz, 64Hz, 2Hz, 1Hz)
INTTA4: 8-bit timer 4
INTTA5: 8-bit timer 5
INTTA6: 8-bit timer 6
INTTA7: 8-bit timer 7
INTP0: Protect 0 (Write to SFR)
(Reserved)
−
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
0028H
002CH
0030H
0034H
0038H
003CH
0040H
0044H
0048H
004CH
0050H
0054H
0058H
005CH
0060H
0064H
0068H
006CH
0070H
0074H
0078H
007CH
0080H
0084H
0088H
008CH
0090H
0094H
0098H
009CH
00A0H
00A4H
00A8H
00ACH
00B0H
FFFF28H
FFFF2CH
FFFF30H
FFFF34H
FFFF38H
FFFF3CH
FFFF40H
FFFF44H
FFFF48H
FFFF4CH
FFFF50H
FFFF54H
FFFF58H
FFFF5CH
FFFF60H
FFFF64H
FFFF68H
FFFF6CH
FFFF70H
FFFF74H
FFFF78H
FFFF7CH
FFFF80H
FFFF84H
FFFF88H
FFFF8CH
FFFF90H
FFFF94H
FFFF98H
FFFF9CH
FFFFA0H
FFFFA4H
FFFFA8H
FFFFACH
FFFFB0H
0AH(Note 1)
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
INTTA0: 0
16H
INTTA1: 8-bit timer 1
INTTA2: 8-bit timer 2
INTTA3: 8-bit timer 3
INTTB0: 16-bit timer 0
INTTB1: 16-bit timer 0
INTKEY: Key wakeup
INTRTC: RTC (Alarm interrupt)
(Reserved)
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H (Note 1)
21H
Maskable
INTLCD: LCDC
INTRX: Serial receive end
INTTX: Serial transmission end
INTTB10: 16-bit timer 1
INTTB11: 16-bit timer 1
INT5: INT5 pin input
INT6: INT6 pin input
INT7: INT7 pin input
INTI2S0: I2S (Channel 0)
INTI2S1: I2S (Channel 1)
INTADM: AD Monitor function
INTSBI: SBI
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
INTSPIRX: SPIC receive
INTSPITX: SPIC transmission
INTRSC: NAND Flash controller
INTRDY: NAND Flash controller
INTUSB: USB
00B4H
00B8H
00BCH
00C0H
00C4H
FFFFB4H
FFFFB8H
FFFFBCH
FFFFC0H
FFFFC4H
2DH
2EH
2FH
30H
31H
(Reserved)
(Reserved)
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Micro DMA
Default
Priority
Interrupt Source and Source of
Micro DMA Request
Vector Address Refer
Type
/HDMA Start
Vector
Value
to Vector
51
52
53
54
55
56
57
58
59
60
−
INTADHP: AD most priority conversion end
INTAD: AD conversion end
00C8H
00CCH
00D0H
00D4H
00D8H
00DCH
00E0H
00E4H
00E8H
00ECH
00F0H
:
FFFFC8H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
−
FFFFCCH
FFFFD0H
FFFFD4H
FFFFD8H
FFFFDCH
FFFFE0H
FFFFE4H
FFFFE8H
FFFFECH
FFFFF0H
:
INTTC0/INTDMA0: Micro DMA0 /HDMA0 end
INTTC1/INTDMA1: Micro DMA1 /HDMA1 end
INTTC2/INTDMA2: Micro DMA2 /HDMA2 end
INTTC3/INTDMA3: Micro DMA3 /HDMA3 end
INTTC4/INTDMA4: Micro DMA4 /HDMA4 end
INTTC5/INTDMA5: Micro DMA5 /HDMA5 end
Maskable
INTTC6
INTTC7
: Micro DMA6 end
: Micro DMA7 end
to
(Reserved)
to
−
00FCH
FFFFFCH
−
Note 1: When standing-up micro DMA/HDMA , set at edge detect mode.
Note 2 : Micro DMA default priority.
Micro DMA stands up prior to other maskable interrupt.
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3.5.2 Micro DMA processing
In addition to general-purpose interrupt processing, the TMP92CZ26A also includes a
micro DMA function and HDMA function. This section explains about Micro DMA function.
For the HDMA function, please refer 3.23 DMA controller.
Micro DMA processing for interrupt requests set by micro DMA is performed at the
highest priority level for maskable interrupts (Level 6), regardless of the priority level of
the interrupt source.
Because the micro DMA function has been implemented with the cooperative operation
of CPU, when CPU is a state of standby (IDLE2,IDLE1,STOP) by HALT instruction, the
requirement of micro DMA will be ignored (Pending).
Micro DMA is supported 8 channels and can be transferred continuously by specifying
the micro DMA burst function in the following.
Note: When using the micro DMA transfer end interrupt, always write “1” to bit 7 of SIMC register.
(1) Micro DMA operation
When an interrupt request is generated by an interrupt source that specified by the
micro DMA /HDMA start vector register, and Micro DMA start is specified by DMA
selection register, the micro DMA triggers a micro DMA request to the CPU at
interrupt priority level 6 and starts processing the request. When IFF = 7, Micro DMA
request cannot be accepted.
The 8 micro DMA channels allow micro DMA processing to be set for up to 8 types of
interrupt at once.
When micro DMA is accepted, the interrupt request flip-flop assigned to that
channel is cleared. Data in 1byte or 2byte or4byte blocks is automatically transferred
at once from the transfer source address to the transfer destination address set in the
control register, and the transfer counter is decremented by “1”. If the value of the
counter after it has been decremented is not “0”, DMA processing ends with no change
in the value of the micro DMA start vector register. If the value of the decremented
counter is “0”, a micro DMA transfer end interrupt (INTTC0 to INTTC7) is sent from
the CPU to the interrupt controller.
In addition, the micro DMA /HDMA start vector register is cleared to “0”, the next
micro DMA operation is disabled and micro DMA processing terminates.
If an interrupt request is triggered for the interrupt source in use during the
interval between the time at which the micro DMA /HDMA start vector is cleared and
the next setting, general-purpose interrupt processing is performed at the interrupt
level set. Therefore, if the interrupt is only being used to initiate micro DMA /HDMA
(and not as a general-purpose interrupt), the interrupt level should first be set to 0
(e.g., interrupt requests should be disabled).
If micro DMA and general-purpose interrupts are being used together as described
above, the level of the interrupt which is being used to initiate micro DMA processing
should first be set to a lower value than all the other interrupt levels. In this case,
edge-triggered interrupts are the only kinds of general interrupts which can be
accepted.
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If micro DMA requests are set simultaneously for more than one channel, priority is
not based on the interrupt priority level but on the channel number: The lower the
channel number, the higher the priority (Channel 0 thus has the highest priority and
channel 7 the lowest).
Note: Don’t start any micro DMAs by one interrupt. If any micro DMA are set by it, micro DMA that
channel number is biggest (priority is lowest) is not started.(Because interrupt flag is
cleared by micro DMA that priority is highest)
Although the control registers used for setting the transfer source and transfer
destination addresses are 32 bits wide, this type of register can only output 24-bit
addresses. Accordingly, micro DMA can only access 16 Mbytes (The upper 8 bits of a
32-bit address are not valid).
Three micro DMA transfer modes are supported: 1byte transfer, 2byte (One word)
transfers and 4byte transfers. After a transfer in any mode, the transfer source and
transfer destination addresses will either be incremented or decremented, or will
remain unchanged. This simplifies the transfer of data from memory to memory, from
I/O to memory, from memory to I/O, and from I/O to I/O. For details of the various
transfer modes, see section 3.5.2 (4) “Detailed description of the transfer mode
register”.
Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing
operations can be performed per interrupt source (Provided that the transfer counter
for the source is initially set to 0000H).
Micro DMA processing can be initiated by any one of 48 different interrupts – the 47
start.
Figure 3.5.2 shows a 2-byte transfer carried out using a micro DMA cycle in
Transfer Destination Address INC Mode (micro DMA transfers are the same in every
mode except Counter Mode). (The conditions for this cycle are as follows: both source
and destination memory are internal-RAM and multipled by 4 numbered source and
destination addresses).
1 state
(1)
(2)
(3)
(4)
(5)
fSYS
A23 to 0
src
dst
(Note) Actually, src and dst address are not outputted to A23-0 pins
because they are address of internal-RAM.
Figure 3.5.2 Timing for micro DMA cycle
States (1) and (2): Instruction fetch cycle (Prefetches the next instruction code)
State (3): Micro DMA read cycle.
State (4): Micro DMA write cycle.
State (5): (The same as in state (1), (2).)
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(2) Soft start function
The TMP92CZ26A can initiate micro DMA/HDMA either with an interrupt or by
using the micro DMA /HDMA soft start function, in which micro DMA or HDMA is
initiated by a Write cycle which writes to the register DMAR.
Writing “1” to each bit of DMAR register causes micro DMA or HDMA to be
performed once. On completion of the transfer, the bits of DMAR for the completed
channel are automatically cleared to “0”.
When writing again “1” to it, soft start can execute continuously until the DMA
transfer counter (DMACn) or HDMA transfer counter B (HDMACBn) become “0”.
When a burst is specified by the register DMAB, data is transferred continuously
from the initiation of micro DMA until the value in the micro DMA transfer counter is
“0”.
Note1: If it is started by software, don’t set any channels to start in same time.
Note2: If be started sequentially, restart it after confirming micro DMA of all channels is completed
(all micro DMA are set to “0”).
Symbol NAME
Address
7
6
5
4
3
2
1
0
DREQ7 DREQ6 DREQ5
DREQ4
DREQ3
DREQ2
DREQ1
DREQ0
109H
(Prohibit
RMW)
R/W
DMA
DMAR
Request
0
0
0
0
0
0
0
0
1: Start DMA
(3) Transfer control registers
The transfer source address and the transfer destination address are set in the following
registers. An instruction of the form LDC cr,r can be used to set these registers.
Channel 0
DMAS0
DMAD0
Micro DMA source address register 0
Micro DMA destination address register 0
Micro DMA counter register 0
DMAC0
DMAM0
Micro DMA mode register 0
Channel 7
DMAS7
Micro DMA source address register 7
Micro DMA destination address register 7
Micro DMA counter register 7
DMAD7
DMAC7
DMAM7
Micro DMA mode register 7
8 bits
16 bits
32 bits
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(4) Detailed description of the transfer mode register
Mode
0
0
0
DMAM0 to 7
DMAMn[4:0]
0 0 0 z z
Mode Description
Execution Time
Destination INC mode
(DMADn +) ← (DMASn)
DMACn ← DMACn - 1
5 states
if DMACn = 0 then INTTCn
0 0 1 z z
0 1 0 z z
0 1 1 z z
1 0 0 z z
Destination DEC mode
(DMADn -) ← (DMASn)
5 states
5 states
5 states
DMACn
← DMACn - 1
if DMACn = 0 then INTTCn
Source INC mode
(DMADn) ← (DMASn +)
DMACn
← DMACn - 1
if DMACn = 0 then INTTCn
Source DEC mode
(DMADn) ← (DMASn -)
DMACn
← DMACn – 1
if DMACn = 0 then INTTCn
Source and destination INC mode
(DMADn +) ← (DMASn +)
6 states
DMACn
← DMACn – 1
If DMACn = 0 then INTTCn
1 0 1 z z
1 1 0 z z
1 1 1 00
Source and destination DEC mode
(DMADn -) ← (DMASn -)
DMACn ← DMACn – 1
If DMACn = 0 then INTTCn
Destination and fixed mode
(DMADn) ← (DMASn)
DMACn ← DMACn – 1
If DMACn = 0 then INTTCn
Counter mode
6 states
5 states
5 states
DMASn ← DMASn + 1
DMACn ← DMACn – 1
If DMACn = 0 then INTTCn
ZZ:
00 = 1-byte transfer
01 = 2-byte transfer
10 = 4-byte transfer
11 = Reserved
Note 1:n stands for the micro DMA channel number (0 to 7).
DMADn+/DMASn+: Post increment (Register value is incremented after transfer).
DMADn−/DMASn−: Post decrement (Register value is decremented after transfer).
“I/O” signifies fixed memory addresses; “memory” signifies incremented or decremented memory addresses.
Note 2: The transfer mode register should not be set to any value other than those listed above.
Note 3: The execution state number shows number of best case (1-state memory access).
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3.5.3 Interrupt Controller Operation
diagram shows the interrupt controller circuit. The right-hand side shows the CPU
interrupt request signal circuit and the halt release circuit.
For each of the 59 interrupts channels there is an interrupt request flag (consisting of a
flip-flop), an interrupt priority setting register and a micro DMA /HDMA start vector
register. The interrupt request flag latches interrupt requests from the peripherals.
The flag is cleared to “0” in the following cases: when a reset occurs, when the CPU reads
the channel vector of an interrupt it has received, when the CPU receives a micro DMA
request (when micro DMA is set), when the CPU receives a HDMA request (when HDMA is
set), when a micro DMA burst transfer is terminated, and when an instruction that clears
the interrupt for that channel is executed (by writing a micro DMA start vector to the
INTCLR register).
An interrupt priority can be set independently for each interrupt source by writing the
priority to the interrupt priority setting register (e.g., INTE0 or INTE12). Six interrupt
priorities levels (1 to 6) are provided. Setting an interrupt source’s priority level to 0 (or 7)
disables interrupt requests from that source.
If more than one interrupt request with a given priority level are generated
simultaneously, the default priority (The interrupt with the lowest priority or, in other
words, the interrupt with the lowest vector value) is used to determine which interrupt
request is accepted first. The 3rd and 7th bits of the interrupt priority setting register
indicate the state of the interrupt request flag and thus whether an interrupt request for a
given channel has occurred.
If several interrupts are generated simultaneously, the interrupt controller sends the
interrupt request for the interrupt with the highest priority and the interrupt’s vector
address to the CPU. The CPU compares the mask value set in <IFF2:0> of the status
register (SR) with the priority level of the requested interrupt; if the latter is higher, the
interrupt is accepted. Then the CPU sets SR<IFF2:0> to the priority level of the accepted
interrupt + 1. Hence, during processing of the accepted interrupt, new interrupt requests
with a priority value equal to or higher than the value set in SR<IFF2:0> (e.g., interrupts
with a priority higher than the interrupt being processed) will be accepted.
When interrupt processing has been completed (e.g., after execution of a RETI instruction),
the CPU restores to SR<IFF2:0> the priority value which was saved on the stack before the
interrupt was generated.
The interrupt controller also includes eight registers which are used to store the micro
DMA /HDMA start vector. Writing the start vector of the interrupt source for the micro
DMA or /HDMA processing (See Table), enables the corresponding interrupt to be processed
by micro DMA or HDMA processing. The values must be set in the micro DMA parameter
registers (e.g., DMAS and DMAD) or HDMA parameter registers (e.g., HDMAS, and
HDMAD) prior to micro DMA or HDMA processing.
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(1) Interrupt priority setting registers
Symbol
Name
Address
7
6
5
4
3
2
1
0
−
INT0
INT1
INT3
INT5
INT7
INT0
enable
−
R
−
−
R/W
−
I0C
R
I0M2
0
I0M1
R/W
0
I0M0
0
INTE0
F0H
Always write “0”.
INT2
0
INT1 & INT2
enable
I2C
R
I2M2
I2M1
R/W
0
I2M0
I1C
R
I1M2
0
I1M1
R/W
0
I1M0
0
INTE12
INTE34
INTE56
INTE7
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
0
0
I4M2
0
0
I4M0
0
0
INT4
INT3 & INT4
enable
I4C
R
I4M1
R/W
0
I3C
R
I3M2
0
I3M1
R/W
0
I3M0
0
0
0
INT6
INT5 & INT6
enable
I6C
R
I6M2
0
I6M1
R/W
0
I6M0
0
I5C
R
I5M2
0
I5M1
R/W
0
I5M0
0
0
0
−
INT7
enable
−
R
−
−
R/W
−
I7C
R
I7M2
0
I7M1
R/W
0
I7M0
0
Always write “0”.
INTTA1 (TMRA1)
0
INTTA0 (TMRA0)
INTTA0 &
INTETA01 INTTA1
enable
ITA1C ITA1M2 ITA1M1 ITA1M0 ITA0C ITA0M2 ITA0M1 ITA0M0
R
0
R/W
0
R
0
R/W
0
0
0
0
0
INTTA3 (TMRA3)
INTTA2 (TMRA2)
INTTA2 &
INTETA23 INTTA3
enable
ITA3C ITA3M2 ITA3M1 ITA3M0 ITA2C ITA2M2 ITA2M1 ITA2M0
R
0
R/W
0
R
0
R/W
0
0
0
0
0
INTTA5 (TMRA5)
INTTA4 (TMRA4)
INTTA4 &
INTETA45 INTTA5
enable
ITA5C ITA5M2 ITA5M1 ITA5M0 ITA4C ITA4M2 ITA4M1 ITA4M0
R
0
R/W
0
R
0
R/W
0
0
0
0
0
INTTA7 (TMRA7)
INTTA6 (TMRA6)
INTTA6 &
INTETA67 INTTA7
enable
ITA7C ITA7M2 ITA7M1 ITA7M0 ITA6C ITA6M2 ITA6M1 ITA6M0
R
0
R/W
0
R
0
R/W
0
0
0
0
0
lxxM2
lxxM1
lxxM0
Function (Write)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Disables interrupt requests
Sets interrupt priority level to 1
Sets interrupt priority level to 2
Sets interrupt priority level to 3
Sets interrupt priority level to 4
Sets interrupt priority level to 5
Sets interrupt priority level to 6
Disables interrupt requests
Interrupt request flag
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TMP92CZ26A
Symbol
Name
Address
D8H
7
6
5
4
3
2
1
0
INTTB01 (TMRB0)
INTTB00 (TMRB0)
INTTB00 &
INTTB01
enable
ITB01C ITB01M2 ITB01M1 ITB01M0 ITB00C ITB00M2 ITB00M1 ITB00M0
INTETB0
R
0
R/W
0
R
0
R/W
0
0
0
0
0
INTTB11 (TMRB1)
INTTB10 (TMRB1)
INTTB10 &
INTTB11
enable
ITB11C ITB11M2 ITB11M1 ITB11M0 ITB10C ITB10M2 ITB10M1 ITB10M0
INTETB1
INTES0
D9H
DBH
E0H
E1H
E3H
E5H
E8H
E9H
R
0
R/W
0
R
0
R/W
0
0
0
0
0
INTTX0
INTRX0
INTRX0 &
INTTX0
enable
ITX0C ITX0M2 ITX0M1 ITX0M0 IRX0C IRX0M2 IRX0M1 IRX0M0
R
0
R/W
0
R
0
R/W
0
0
0
0
0
INTADM
INTSBI
INTSBI &
INTADM
enable
IADM0C IADMM2 IADMM1 IADMM0 ISBI0C ISBIM2 ISBIM1 ISBIM0
INTESBIADM
INTESPI
R
0
R/W
0
R
0
R/W
0
0
0
0
0
INTSPITX
INTSPIRX
INTSPI
enable
ISPITC ISPITM2 ISPITM1 ISPITM0 ISPIRC ISPIRM2 ISPIRM1 ISPIRM0
R
0
R/W
0
R
0
R/W
0
0
0
0
0
−
INTUSB
IUSBC IUSBM2 IUSBM1 IUSBM0
INTUSB
enable
−
−
−
−
−
−
−
INTEUSB
INTEALM
INTERTC
INTEKEY
R
0
R/W
0
Always write “0”.
0
0
−
INTALM
IALMC IALMM2 IALMM1 IALMM0
INTALM
enable
−
−
−
−
−
R
0
R/W
0
Always write “0”.
0
IRM2
0
0
IRM0
0
−
INTRTC
INTRTC
enable
−
−
IRC
R
IRM1
R/W
0
Always write “0”.
0
−
INTKEY
INTKEY
enable
−
−
IKC
R
IKM2
IKM1
R/W
0
IKM0
0
Always write “0”.
0
0
lxxM2
lxxM1
lxxM0
Function (Write)
Disables interrupt requests
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Sets interrupt priority level to 1
Sets interrupt priority level to 2
Sets interrupt priority level to 3
Sets interrupt priority level to 4
Sets interrupt priority level to 5
Sets interrupt priority level to 6
Disables interrupt requests
Interrupt request flag
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TMP92CZ26A
Symbol
Name
Address
EAH
7
6
5
4
3
2
1
0
−
INTLCD
ILCD1C ILCDM2 ILCDM1 ILCDM0
INTLCD
enable
−
−
−
−
INTELCD
R
0
R/W
0
Always write “0”.
INTI2S1
0
0
INTI2S0
INTI2S0 &
II2S1C II2S1M2 II2S1M1 II2S1M0 I I2S0C II2S0M2 II2S0M1 II2S0M0
INTEI2S01 INTI2S1
enable
EBH
ECH
EEH
EFH
R
0
R/W
0
R/W
0
R/W
0
0
0
0
0
INTRSC
INTRDY
INTRSC &
INTENDFC INTRDY
enable
IRSCC IRSCM2 IRSCM1 IRSCM0 IRDYC IRDYM2 IRDYM1 IRDYM0
R
0
R/W
0
R
0
R/W
0
0
0
0
IP0M2
0
0
−
INTP0
INTP0
INTEP0
−
R
−
−
R/W
−
IP0C
R
IP0M1
R/W
0
IP0M0
enable
Always write “0”.
INTADHP
0
INTAD
INTAD &
0INTEAD INTADHP
enable
IADHPC
IADC
R/W
0
IADM2 IADM1
R/W
IADM0
0
IADHPM2 IADHPM1 IADHPM0
R
0
R/W
0
0
0
0
0
lxxM2
lxxM1
lxxM0
Function (Write)
Disables interrupt requests
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Sets interrupt priority level to 1
Sets interrupt priority level to 2
Sets interrupt priority level to 3
Sets interrupt priority level to 4
Sets interrupt priority level to 5
Sets interrupt priority level to 6
Disables interrupt requests
Interrupt request flag
92CZ26A-80
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TMP92CZ26A
Symbol
Name
Address
F1H
7
6
5
4
3
2
1
0
INTTC1/INTDMA1
INTTC0/INTDMA0
INTTC0/INTDMA0 &
INTTC1/INTDMA1
enable
ITC1C
ITC1M2
ITC1M1
ITC1M0
ITC0C
ITC0M2
ITC0M1
ITC0M0
INTETC01
/IDMA1C /IDMA1M2 /IDMA1M1 /IDMA1M0 /IDMA0C /IDMA0M2 /IDMA0M1 /IDMA0M0
/INTEDMA01
R
0
R/W
0
R
0
R/W
0
0
0
0
0
INTTC3/INTDMA3
INTTC2/INTDMA2
INTTC2/INTDMA2 &
INTTC3/INTDMA3
enable
ITC3C
ITC3M2
ITC3M1
ITC3M0
ITC2C
ITC2M2
ITC2M1
ITC2M0
INTETC23
F2H
F3H
/IDMA3C /IDMA3M2 /IDMA3M1 /IDMA3M0 /IDMA2C /IDMA2M2 /IDMA2M1 /IDMA2M0
/INTEDMA23
R
0
R/W
0
R
0
R/W
0
0
0
0
0
INTTC5/INTDMA5
INTTC4/INTDMA4
INTTC4/INTDMA4 &
INTTC5/INTDMA5
enable
ITC5C
ITC5M2
ITC5M1
ITC5M0
ITC4C
ITC4M2
ITC4M1
ITC4M0
INTETC45
/IDMA5C /IDMA5M2 /IDMA5M1 /IDMA5M0 /IDMA4C /IDMA4M2 /IDMA4M1 /IDMA4M0
/INTEDMA45
R
0
R/W
0
R
0
R/W
0
0
0
0
0
INTTC7 (DMA7)
INTTC6 (DMA6)
INTTC6 & INTTC7
enable
ITC7C
ITC7M2
ITC7M1
R/W
0
ITC7M0
ITC6C
ITC6M2
ITC6M1
R/W
0
ITC6M0
F4H
F7H
INTETC67
INTWDT
R
0
R
0
0
0
0
0
−
−
−
INTWD
INTWD
enable
−
R
−
−
R/W
−
ITCWD
−
−
−
−
R
0
Always write “0”.
lxxM2
lxxM1
lxxM0
Function (Write)
Disables interrupt requests
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Sets interrupt priority level to 1
Sets interrupt priority level to 2
Sets interrupt priority level to 3
Sets interrupt priority level to 4
Sets interrupt priority level to 5
Sets interrupt priority level to 6
Disables interrupt requests
Interrupt request flag
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TMP92CZ26A
(2) External interrupt control
Symbol
Name
Address
7
6
5
4
3
2
1
0
−
I5EDGE
I4EDGE
I3EDGE
I2EDGE
I1EDGE
I0EDGE
I0LE
W
0
W
0
W
0
W
0
W
0
W
0
R/W
0
R/W
0
Interrupt
F6H
INT5EDGE INT4EDGE INT3EDGE INT2EDGE INT1EDGE INT0EDGE INT0
Always
write “0”.
IIMC0
input mode
control 0
(Prohibit
RMW)
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
1: Falling
0: Edge
mode
1: Level
mode
I7EDGE
I6EDGE
W
0
W
0
Interrupt
FAH
(Prohibit
RMW)
IIMC1
input mode
control 0
INT7EDGE INT6EDGE
0: Rising
1: Falling
0: Rising
1: Falling
Note 1:Disable INT0 request before changing INT0 pin mode from level sense to edge sense.
(change <I0LE>from “1” to “0”)
DI
LD
LD
(IIMC0), XXXXXX0-B
(INTCLR), 0AH
; Switches from level to edge.
; Clears interrupt request flag.
NOP
NOP
NOP
EI
; Wait EI execution
Note 2:X: Don’t care, –: No change
Note 3:See electrical characteristics in section 4 for external interrupt input pulse width.
Note 4: In port setting, if 16 bit timer input is selected and capture control is executed, INT6 and
INT7 don’t depend on IIMC1 register setting. INT6 and INT7 operate by setting
TBnMOD<TBnCPM1:0>.
Settings of External Interrupt Pin Function
Interrupt
Pin Name
Mode
Setting Method
Rising edge
Falling edge
High level
<I0LE> = 0,<I0EDGE> = 0
<I0LE> = 0, <I0EDGE> = 1
<I0LE> = 1
INT0
PC0
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Falling edge
<I1EDGE> = 0
<I1EDGE> = 0
<I2EDGE> = 0
<I2EDGE> = 1
<I3EDGE> = 0
<I3EDGE> = 1
<I4EDGE> = 0
<I4EDGE> = 1
<I5EDGE> = 0
<I5EDGE> = 1
<I6EDGE> = 0
<I6EDGE> = 1
<I7EDGE> = 0
<I7EDGE> = 1
INT1
INT2
INT3
INT4
INT5
INT6
INT7
PC1
PC2
PC3
P96
PP3
PP4
PP5
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TMP92CZ26A
(3) SIO receive interrupt control
Symbol
Name
Address
7
6
5
4
3
2
1
0
−
−
IR0LE
W
0
W
0
W
1
SIO
F5H
Always
write “0”
(Note)
Always
write “0”
0:INTRX0
edge
interrupt
mode
control
SIMC
(Prohibit
RMW)
mode
1:INTRX0
level
mode
Note: When using the micro DMA transfer end interrupt, always write “1”.
INTRX0 edge enable
0
Edge detect INTRX0
1
“H” level INTRX0
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TMP92CZ26A
(4) Interrupt request flag clear register
The interrupt request flag is cleared by writing the appropriate micro DMA /HDMA start
For example, to clear the interrupt flag INT0, perform the following register operation after
execution of the DI instruction.
INTCLR
0AH
; Clears interrupt request
flag INT0.
←
Symbol
INTCLR
Name
Address
7
6
5
4
3
2
1
0
CLRV7
CLRV6
CLRV5
CLRV4
CLRV3
CLRV2
CLRV1
CLRV0
Interrupt
clear
F8H
W
(Prohibit
RMW)
0
0
0
0
0
0
0
0
control
Interrupt vector
(5) Micro DMA start vector registers
These registers assign micro DMA /HDMA processing to sets which source corresponds to
DMA. The interrupt source whose micro DMA /HDMA start vector value matches the vector set
in one of these registers is designated as the micro DMA /HDMA start source.
When the micro DMA transfer counter (DMACn) or HDMA transfer counter B (HDMACBn)
value reaches “0”, the micro DMA /HDMA transfer end interrupt corresponding to the channel
is sent to the interrupt controller, the micro DMA /HDMA start vector register is cleared, and
the micro DMA /HDMA start source for the channel is cleared. Therefore, in order for micro
DMA /HDMA processing to continue, the micro DMA /HDMA start vector register must be set
again during processing of the micro DMA /HDMA transfer end interrupt.
If the same vector is set in the micro DMA /HDMA start vector registers of more than one
channel, the lowest numbered channel takes priority.
Accordingly, if the same vector is set in the micro DMA /HDMA start vector registers for two
different channels, the interrupt generated on the lower-numbered channel is executed until
micro DMA /HDMA transfer is complete. If the micro DMA /HDMA start vector for this channel
has not been set in the channel’s micro DMA /HDMA start vector register again, micro DMA
/HDMA transfer for the higher-numbered channel will be commenced. (This process is known
as micro DMA /HDMA chaining.)
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TMP92CZ26A
Symbol
DMA0V
Name
Address
100H
7
6
5
4
3
2
1
0
DMA0V5 DMA0V4
DMA0V3
DMA0V2 DMA0V1 DMA0V0
DMA0
start
R/W
0
0
0
0
0
0
vector
DMA0 start vector
DMA1V3 DMA1V2 DMA1V1 DMA1V0
R/W
DMA1V5 DMA1V4
DMA1
start
DMA1V
DMA2V
DMA3V
101H
102H
103H
0
0
0
0
0
0
vector
DMA1 start vector
DMA2V3 DMA2V2 DMA2V1 DMA2V0
R/W
DMA2V5 DMA2V4
DMA2
start
0
0
0
0
0
0
vector
DMA2 start vector
DMA3V3 DMA3V2 DMA3V1 DMA3V0
R/W
DMA3V5 DMA3V4
DMA3
start
0
0
0
0
0
0
vector
DMA3 start vector
DMA4V3 DMA4V2
R/W
DMA4V5 DMA4V4
DMA4V1 DMA4V0
DMA4
start
DMA4V
DMA5V
DMA6V
DMA7V
104H
105H
106H
107H
0
0
0
0
0
0
vector
DMA4 start vector
DMA5V3 DMA5V2
R/W
DMA5V5 DMA5V4
DMA5V1 DMA5V0
DMA5
start
0
0
0
0
0
0
vector
DMA5 start vector
DMA6V3 DMA6V2
R/W
DMA6V5 DMA6V4
DMA6V1 DMA6V0
DMA6
start
0
0
0
0
0
0
vector
DMA6 start vector
DMA7V3 DMA7V2
R/W
DMA7V5 DMA7V4
DMA7V1 DMA7V0
DMA7
start
0
0
0
0
0
0
vector
DMA7 start vector
(6) Micro DMA/HDMA select register
This register selectable that is started either Micro DMA or HDMA processing.
Micro DMA /HDMA start vector register (DMAnV) shared with both functions. When
interrupt which match with vector value that is set to DMA/HDMA start vector register
generated, use this register.
Symbol
NAME
Address
7
6
5
4
3
2
1
0
DMASEL5 DMASEL4 DMASEL3 DMASEL2 DMASEL1 DMASEL0
R/W
Micro
0
0:Micro
DMA5
0
0:Micro
DMA4
0
0:Micro
DMA3
0
0:Micro
DMA2
0
0:Micro
DMA1
0
0:Micro
DMA0
DMASEL DMA/HDMA 10AH
select
1:HDMA5 1:HDMA4 1:HDMA3 1:HDMA2 1:HDMA1 1:HDMA0
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TMP92CZ26A
(7) Specification of a micro DMA burst
Specifying the micro DMA burst function causes micro DMA transfer, once started, to
continue until the value in the transfer counter register reaches “0”. Setting any of the bits in
the register DMAB which correspond to a micro DMA channel (as shown below) to “1” specifies
that any micro DMA transfer on that channel will be a burst transfer.
Symbol
DMAB
Name
Address
108H
7
6
5
4
3
2
1
0
DBST7
DBST6
DBST5
DBST4
DBST3
DBST2
DBST1
DBST0
R/W
DMA
burst
0
0
0
0
0
0
0
0
1: DMA request on Burst mode
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TMP92CZ26A
(8) Notes
The instruction execution unit and the bus interface unit in this CPU operate
independently. Therefore, if immediately before an interrupt is generated, the CPU fetches
an instruction which clears the corresponding interrupt request flag, the CPU may execute
this instruction in between accepting the interrupt and reading the interrupt vector. In this
case, the CPU will read the default vector 0004H and jump to interrupt vector address
FFFF04H.
To avoid this, an instruction which clears an interrupt request flag should always be
preceded by a DI instruction. And in the case of setting an interrupt enable again by EI
instruction after the execution of clearing instruction, execute EI instruction after clearing
and more than 3-instructions (e.g., “NOP” × 3 times). If placed EI instruction without
waiting NOP instruction after execution of clearing instruction, interrupt will be enable
before request flag is cleared.
In the case of changing the value of the interrupt mask register <IFF2:0> by execution of
POP SR instruction, disable an interrupt by DI instruction before execution of POP SR
instruction.
In addition, please note that the following two circuits are exceptional and demand
special attention.
In level mode INT0 is not an edge-triggered interrupt. Hence, in level mode the
interrupt request flip-flop for INT0 does not function. The peripheral interrupt
request passes through the S input of the flip-flop and becomes the Q output. If the
interrupt input mode is changed from edge mode to level mode, the interrupt
request flag is cleared automatically.
If the CPU enters the interrupt response sequence as a result of INT0 going from 0
to 1, INT0 must then be held at 1 until the interrupt response sequence has been
completed. If INT0 is set to level mode so as to release a halt state, INT0 must be
held at 1 from the time INT0 changes from 0 to 1 until the halt state is released.
(Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing
INT0 to revert to 0 before the halt state has been released.)
When the mode changes from level mode to edge mode, interrupt request flags
which were set in level mode will not be cleared. Interrupt request flags must be
cleared using the following sequence.
INT0 level mode
DI
LD (IIMC0), 00H
; Switches from level to edge.
LD (INTCLR), 0AH ; Clears interrupt request flag.
NOP
NOP
NOP
EI
; Wait EI execution
In level mode (The register SIMC<IRxLE> set to “1”), the interrupt request flip-flop
can only be cleared by a reset or by reading the serial channel receive buffer. It
cannot be cleared by an instruction.
INTRX
Note: The following instructions or pin input state changes are equivalent to instructions which
clear the interrupt request flag.
INT0: Instructions which switch to level mode after an interrupt request has been
generated in edge mode.
The pin input changes from high to low after an interrupt request has been
generated in level mode. (“H” → “L”)
INTRX:Instructions which read the receive buffer.
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TMP92CZ26A
3.6
DMAC (DMA Controller)
The TMP92CZ26A incorporates a DMA controller (DMAC) having six channels. This DMAC can
realize data transfer faster than the micro DMA function by the 900/H1 CPU.
The DMAC has the following features:
1) Six independent channels of DMA
2) Two types of transfer start requests
Hardware request (using an interrupt source connected with the INTC) or software
request can be selected for each channel.
3) Various source/destination combinations
The combination of transfer source and destination can be selected for each channel
from the following four types: memory to memory, memory to I/O, I/O to memory, I/O
to I/O.
4) Transfer address mode
Only the dual address mode is supported.
5) Dual-count mechanism and DMA end interrupt
Two count registers are provided to execute multiple DMA transfers by one DMA
request and to generate multiple DMA requests at a time. The DMA end interrupt
(INTDMA0 to INTDMA5) is also provided so that a general-purpose interrupt routine
can be used to prepare for the next processing.
6) Priorities among DMA channels (the same as the micro DMA acceptance specifications
of the INTC)
DMA requests are basically accepted in the order in which they are asserted. If more
than one request is asserted simultaneously or it looks as if two requests were
asserted simultaneously because one of the requests has been put on hold while other
processing was being performed, the smaller-numbered channel is given a higher
priority.
7) DMAC bus occupancy limiting function
The DMAC incorporates a special timer for limiting its bus occupancy time to avoid
excessive interference with the CPU or LCDC operation.
8) The DMAC can be used in HALT (IDLE2) mode.
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TMP92CZ26A
3.6.1 Block Diagram
Figure 3.6.1 shows an overall block diagram for the DMAC.
Bus
Multiplexer
Address Bus
State
SDRAM Controller
LCD Controller
Address Bus
Data Bus
State
Source Memory, I/O
Address Bus
Bus ACK
Bus REQ
INTC (Interrupt Controller)
Data Bus
State
CPU
Interrupt REQ
31
0
7
0
DMAnV
DMASn
Destination Memory, I/O
→DMAC or micro DMA request
source setting
→Micro DMA source address setting
Address Bus
Address Bus
DMADn
→Micro DMA destination address setting
15
Data Bus
State
DMAR
Data Bus
State
→DMAC or micro DMA soft start
setting
0
Micro DMA REQ,
DMACn
Micro DMA Channel
DMAB
→Micro DMA transfer count setting
7
0
→Micro DMA burst setting
DMAMn
Micro DMA ACK,
INTTCn
DMASEL
→Micro DMA mode setting
→DMAC or micro DMA select
setting
DMAC
DMA REQ,
DMA Channel
31
0
Address Bus
State
HDMASn
→DMA source address setting
HDMADn
DMA ACK,
INTDMAn
Data Bus
→DMA destination address setting
15
0
HDMACAn
→DMA transfer count A setting
HDMACBn
→DMA transfer count B setting
7
0
HDMAMn
→DMA mode setting
HDMAE
→DMA operation enable/disable
HDMATR
→DMA maximum bus occupancy
time setting, mode setting
Note: “n” denotes a channel number. Micro DMA has eight channels (0 to 7) and DMA has six channels (0 to 5).
Figure 3.6.1 Overall Block Diagram
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TMP92CZ26A
3.6.2 SFRs
The DMAC has the following SFRs. These registers are connected to the CPU via a 16-bit
data bus.
(1) HDMASn (DMA Transfer Source Address Setting Register)
The HDMASn register is used to set the DMA transfer source address. When the source
address is updated by DMA execution, HDMASn is also updated.
HDMAS0 to HDMAS5 have the same configuration.
Although the bus sizing function is supported, the address alignment function is not
supported. Therefore, specify an even-numbered address for transferring 2 bytes and an
address that is an integral multiple of 4 for transferring 4 bytes.
HDMASn Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
DnSA7
DnSA6
DnSA5
DnSA4
DnSA3
DnSA2
DnSA1
DnSA0
HDMASn
R/W
0
0
0
0
0
0
0
0
Source address [7:0] for DMAn
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
Function
DnSA15
DnSA14
DnSA13
DnSA12
DnSA11
DnSA10
DnSA9
DnSA8
R/W
0
0
0
0
0
0
0
0
Source address [15:8] for DMAn
23
22
21
20
19
18
17
16
bit Symbol
Read/Write
After reset
Function
DnSA23
DnSA22
DnSA21
DnSA20
DnSA19
DnSA18
DnSA17
DnSA16
R/W
0
0
0
0
0
0
0
0
Source address [23:16] for DMAn
Source address
Source address
Source address
[7:0]
[23:16]
(0902H)
(0912H)
(0922H)
(0932H)
(0942H)
(0952H)
[15:8]
HDMAS0
(0900H)
HDMAS1
(0910H)
HDMAS2
(0920H)
HDMAS3
(0930H)
HDMAS4
(0940H)
HDMAS5
(0950H)
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
(0901H)
(0911H)
(0921H)
(0931H)
(0941H)
(0951H)
Note: Read-modify-write instructions can be used on all these registers.
Figure 3.6.2 HDMASn Register
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(2) HDMADn (DMA Transfer Destination Address Setting Register)
The HDMADn register is used to set the DMA transfer destination address. When the
destination address is updated by DMA execution, HDMADn is also updated.
HDMAD0 to HDMAD5 have the same configuration.
Although the bus sizing function is supported, the address alignment function is not
supported. Therefore, specify an even-numbered address for transferring 2 bytes and an
address that is an integral multiple of 4 for transferring 4 bytes.
HDMADn Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
DnDA7
DnDA6
DnDA5
DnDA4
DnDA3
DnDA2
DnDA1
DnDA0
HDMADn
R/W
0
0
0
0
0
0
0
0
Destination address [7:0] for DMAn
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
Function
DnDA15
DnDA14
DnDA13
DnDA12
DnDA11
DnDA10
DnDA9
DnDA8
R/W
0
0
0
0
0
0
0
0
Destination address [15:8] for DMAn
23
22
21
20
19
18
17
16
bit Symbol
Read/Write
After reset
Function
DnDA23
DnDA22
DnDA21
DnDA20
DnDA19
DnDA18
DnDA17
DnDA16
R/W
0
0
0
0
0
0
0
0
Destination address [23:16] for DMAn
Destination
Destination
Destination
address
[7: 0]
address
[23: 16]
address
[15: 8]
HDMAD0
(0904H)
HDMAD1
(0914H)
HDMAD2
(0924H)
HDMAD3
(0934H)
HDMAD4
(0944H)
HDMAD5
(0954H)
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
(0906H)
(0916H)
(0926H)
(0936H)
(0946H)
(0956H)
(0905H)
(0915H)
(0925H)
(0935H)
(0945H)
(0955H)
Note: Read-modify-write instructions can be used on all these registers.
Figure 3.6.3 HDMADn Register
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(3) HDMACAn (DMA Transfer Count A Setting Register)
The HDMACAn register is used to set the number of times a DMA transfer is to be
performed by one DMA request. HDMACAn contains 16 bits and can specify up to 65536
transfers (0001H = one transfer, FFFFH = 65535 transfers, 0000H = 65536 transfers). Even
when the transfer count A is updated by DMA execution, HDMACAn is not updated.
HDMACA0 to HDMACA5 have the same configuration.
HDMACAn Register
7
6
5
4
3
2
1
0
HDMACAn
bit Symbol
Read/Write
After reset
Function
DnCA7
DnCA6
DnCA5
DnCA4
DnCA3
DnCA2
DnCA1
DnCA0
R/W
0
0
0
0
0
0
0
0
Transfer count A [7:0] for DMAn
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
Function
DnCA15
DnCA14
DnCA13
DnCA12
DnCA11
DnCA10
DnCA9
DnCA8
R/W
0
0
0
0
0
0
0
0
Transfer count A [15:8] for DMAn
Transfer count A
[15: 8]
Transfer count A
[7: 0]
HDMACA0
(0908H)
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
(0909H)
(0919H)
(0929H)
(0939H)
(0949H)
(0959H)
HDMACA1
(0918H)
HDMACA2
(0928H)
HDMACA3
(0938H)
HDMACA4
(0948H)
HDMACA5
(0958H)
Note: Read-modify-write instructions can be used on all these registers.
Figure 3.6.4 HDMACAn Register
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(4) HDMACBn (DMA Transfer Count B Setting Register)
The HDMACBn register is used to set the number of times a DMA request is to be made.
HDMACBn contains 16 bits and can specify up to 65536 requests (0001H = one request,
FFFFH = 65535 requests, 0000H = 65536 requests). When the transfer count B is updated
by DMA execution, HDMACBn is also updated.
HDMACB0 to HDMACB5 have the same configuration.
HDMACBn Register
7
6
5
4
3
2
1
0
HDMACBn
bit Symbol
Read/Write
After reset
Function
DnCB7
DnCB6
DnCB5
DnCB4
DnCB3
DnCB2
DnCB1
DnCB0
R/W
0
0
0
0
0
0
0
0
Transfer count B [7:0] for DMAn
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
Function
DnCB15
DnCB14
DnCB13
DnCB12
DnCB11
DnCB10
DnCB9
DnCB8
R/W
0
0
0
0
0
0
0
0
Transfer count B [15:8] for DMAn
Transfer count B
[15: 8]
Transfer count B
[7: 0]
HDMACB0
(090AH)
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
(090BH)
(091BH)
(092BH)
(093BH)
(094BH)
(095BH)
HDMACB1
(091AH)
HDMACB2
(092AH)
HDMACB3
(093AH)
HDMACB4
(094AH)
HDMACB5
(095AH)
Note: Read-modify-write instructions can be used on all these registers.
Figure 3.6.5 HDMACBn Register
92CZ26A-93
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(5) HDMAMn (DMA Transfer Mode Setting Register)
The HDMAMn register is used to set the DMA transfer mode.
HDMAM0 to HDMAM5 have the same configuration.
HDMAMn Register
7
6
5
4
3
2
DnM2
R/W
0
1
0
HDMAMn
bit Symbol
Read/Write
After reset
DnM4
DnM3
DnM1
DnM0
0
0
0
0
DMA transfer mode
Transfer data size
000: Destination INC (I/O → MEM) 00: 1 byte
001: Destination DEC (I/O → MEM) 01: 2 bytes
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
100: Source/destination INC
(MEM → MEM)
10: 4 bytes
11: Reserved
Function
101: Source/destination DEC
(MEM → MEM)
110: Source/destination fixed
(I/O→ I/O)
111: Reserved
(Note 2)
Transfer mode
[7: 0]
HDMAM0
(090CH)
HDMAM1
(091CH)
HDMAM2
(092CH)
HDMAM3
(093CH)
HDMAM4
(094CH)
HDMAM5
(095CH)
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Note 1: Read-modify-write instructions can be used on all these registers.
Note 2: INC: Post-increment
Dec: Post-decrement
I/O: Fixed memory address
MEM: Memory address to be incremented or decremented
Figure 3.6.6 HDMAMn Register
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(6) HDMAE (DMA Operation Enable Register)
The HDMAE register is used to enable or disable the DMAC operation.
Bits 0 to 5 correspond to channels 0 to 5. Unused channels should be set to “0”.
HDMAE Register
7
6
5
4
3
2
1
0
HDMAE
(097EH)
bit Symbol
Read/Write
After reset
DMAE5
DMAE4
DMAE3
DMAE2
DMAE1
DMAE0
R/W
0
0
0
0
0
0
DMA channel operation
0: Disable
Function
1: Enable
Note: Read-modify-write instructions can be used on this register.
Figure 3.6.7 HDMAE Register
(7) HDMATR (DMA Maximum Bus Occupancy Time Setting Register)
The HDMATR register is used to set the maximum duration of time the DMAC can
occupy the bus. The TMP92CZ26A does not have priority levels for bus arbitration.
Therefore, once the DMAC owns the bus, other masters (such as the LCDC) must wait until
the DMAC completes its transfer operation and releases the bus. This could lead to
problems in the system. For example, if the LCDC cannot own the bus as required, the LCD
display function may not work properly. To avoid such a situation, the DMAC limits the
duration of its bus occupancy by using this timer register. When the DMAC occupies the
bus for the duration of time set in this register, it releases the bus even if the specified DMA
operation has not been completed yet. After waiting for 16 states, the DMAC asserts a bus
request again to execute the rest of the DMA operation.
The DMAC counts the bus occupancy time regardless of which channel is occupying the
bus. To set the maximum bus occupancy time, ensure that the HDMAE register is set to
“00H” and set HDMATR<DMATE> to “1” and <DMATR6:0> to the desired value.
Note: In case of using S/W start with HDMA, transmission start is to set to "1" DMAR
register. However DMAR register can't be used to confirm flag of transmission end. DMAR
register reset to "0" when HDMA release bus occupation once with HDMATR function.
HDMATR Register
HDMATR
(097FH)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
DMATE
DMATR6 DMATR5 DMATR4 DMATR3
R/W
DMATR2
DMATR1
DMATR0
0
0
0
0
0
0
0
0
Timer
Maximum bus occupancy time setting
The value to be set in <DMATR6:0> should be obtained by
operation
0: Disable
1: Enable
Function
“maximum bus occupancy time / (256/f
“00H” cannot be set.
)”.
SYS
Note: Read-modify-write instructions can be used on this register.
Figure 3.6.8 HDMATR Register
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3.6.3 DMAC Operation Description
(1) Overall flowchart
Figure 3.6.9 shows a flowchart for DMAC operation when an interrupt (DMA) is
requested.
Interrupt (DMA) request
To general-purpose interrupt or
micro DMA processing flow
Interrupt specified by
DMA start vector?
No
Yes
Interrupt request F/F clear
& bus REQ assert
No
Bus ACK?
Yes
Internal timer start
HDMASn read
HDMADn write
Yes
Yes
Timer match?
No
HDMACAn -1=0?
Yes
No
Bus REQ deassert
HDMACBn -1=0?
No
INTDMAn assert
END
Figure 3.6.9 Overall Flowchart
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(2) Bus arbitration
The TMP92CZ26A includes three controllers (DMA controller, LCD controller, SDRAM
controller) that function as bus masters apart from the CPU. These controllers operate
independently and assert a bus request as required. The controller that receives a bus
acknowledgement acts as the bus master. No priorities are assigned to these three
controllers, and bus requests are processed in the order in which they are asserted. Once
one of the controllers owns the bus, bus requests from other controllers are put on hold until
the bus is released again. While one of the controllers is occupying the bus, CPU processing
including non-maskable interrupt requests is also put on hold.
(3) Transfer source and destination memory setting
Either internal or external memory can be set as the source and destination memory or
I/O to be accessed by the DMAC. Even when the MMU is used in external memory, the
addresses to be accessed by the DMAC should be specified using logical addresses. The
DMAC accesses the specified source and destination addresses according to the bus width
and number of waits set in the memory controller and the bank settings made in the MMU.
Although the bus sizing function is supported, the address alignment function is not
supported. Therefore, specify an even-numbered address for transferring 2 bytes and an
address that is an integral multiple of 4 for transferring 4 bytes.
Table 3.6.1 Difference point of address setting between HDMA and micro DMA
Data Length
HDMA
Micro DMA
1byte
2byte
4byte
1byte
2byte
4byte
No restriction
Even address
Source address
Address in multiples of 4
No restriction
No restriction
Destination address
Even address
Address in multiples of 4
(4) Operation timing
The following diagram shows an example of operation timing for transferring 2 bytes
from 16-bit memory connected with the CS2 area to 8-bit memory connected with the CS1
area.
CPU execution
DMAC/read
CPU execution cycle
DMAC/write
cycle
SDCLK
int_xx
busrq
busak
CS2
Undefined after interrupt
request is asserted until
DMAC read cycle is
started
CS1
800000H
400000H
400001H
A23 ∼ A0
RD
SRWR
SRLUB
SRLLB
ZZ34H
ZZ12H
1234H
D15 ∼ D0
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3.6.4 Setting Example
This section explains how to set the DMAC using an example.
(1) Transferring music data from internal RAM to I2S by DMA transfer
The 32 Kbytes of data stored in the internal RAM at addresses 2000H to 9FFFH shall be
transferred to FIFO-RAM via I2S. Each time an INTI2S request is asserted, 64 bytes (4
bytes x 16 times) shall be transferred to FIFO-RAM using DMAC channel 0. Since INTI2S
is an FIFO empty interrupt, the first data must be set in advance. Therefore, only the first
64 bytes shall be transferred by DMA soft start. After 32 Kbytes have been transferred, the
INTDMA0 interrupt routine shall be activated to prepare for the next processing.
(a) Main routine
No
Instruction
Comments
1
2
3
4
5
6
7
8
9
ldl
ldl
(hdmas0),2000H
(hdmad0),i2sbuf
; Source address = 2000H
; Destination address = i2sbuf
; Counter A = 16
ldw (hdmaca0),16
ldw (hdmacb0),512
; Counter B = 512 (32768/64)
; Transfer mode = source INC, 4 bytes
; Enable DMA channel 0.
; Transfer the first 64 bytes by DMA soft start.
;
ldb
set
ld
(hdmam0),0AH
0,(hdmae)
(dmar),01H
nop
ld
(dma0v),i2s_vector
(intedma01),xxH
; INTI2S = DMA0
10
11
12
13
ld
; INTDMA level = x
ldw (i2sctl0),xxxxH
ldw (i2sctl1),xxxxH
; Set operation mode for I2S.
; Start I2S transmission.
; Enable CPU interrupts.
ei
xx
(b) INTDMA0 interrupt routine
No Instruction
Comments
1
2
3
4
5
6
7
8
9
res
0,(hdmae)
; Disable DMA channel 0.
:
:
:
:
10
11
reti
;
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3.6.5 Note
1. In case of using S/W start with HDMA, transmission start is to set to "1" DMAR
register. However DMAR register can't be used to confirm flag of transmission end.
DMAR register reset to "0" when HDMA release bus occupation once with HDMATR
function. We recommend to use HDMACBn register (counter value) to confirm flag of
transmission end.
92CZ26A-99
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3.6.6 Considerations for Using More Than One Bus Master
In the TMP92CZ26A, the LCD controller, SDRAM controller, and DMA controller may act as
the bus master apart from the CPU. Therefore, care must be exercised to enable each of these
functions to operate smoothly.
To facilitate explanation of DMA operation performed by each bus master, the DMA transfer
operation performed by the DMA controller is defined as “HDMA”, the display RAM read
operation performed by the LCD controller as “LDMA”, and the SDRAM auto refresh operation
performed by the SDRAM controller as “ARDMA”.
The following explains various cases where two or more bus masters may operate at the
same time.
(1) CPU + HDMA
The DMA controller performs DMA transfer (HDMA) after issuing a bus request to the
CPU and getting a bus acknowledgement. The DMA controller may be active while the CPU
is in HALT mode (IDLE2 mode only), in which case HDMA does not interfere with the CPU
operation. However, if HDMA is started while the CPU is active, the CPU cannot execute
instructions while HDMA is being performed.
Before activating the DMA controller, therefore, it is necessary to estimate the CPU stop
time (defined as “tSTOP (HDMA)”) based on the transfer time, transfer start interval, and
number of channels to be used.
CPU bus stop rate = tSTOP (HDMA)[s] / HDMA start interval [s]
HDMA start interval [s] = HDMA start interrupt period [s]
Note: The HDMA start interval depends on the period of the HDMA start interrupt source. However, it is also
possible to start HDMA by software.
tSTOP (HDMA) [s] = (Source read time + Destination write time) × Transfer count + α
state/byte
Memory Type
Read / Write
External SDRAM
16-bit bus
External SRAM
16-bit bus
External SRAM
8-bit bus
Internal RAM
(Note 2)
Burst 1 / 2
(Note 1)
(Note 3)
(Note 3)
1 / 4
2 / 2
2 / 1
Read
Write
(Note 2)
1 word 6 / 2
(Note 2)
Burst 1 / 2
(Note 3)
(Note 3)
2 / 2
2 / 1
1 / 4
(Note 2)
1 word 3 / 2
Note 1: 2-1-1-1 access. Each consecutive address can be accessed in 1 state.
Note 2: The transfer speed varies depending on the combination of source and destination.
a) When the source or destination is internal RAM or internal I/O (SFR), burst access (6-1-1-1 access)
is possible. Only consecutive addresses on the same page can be accessed in 1 state. Additional 4
states are needed at the end of each burst access.
b) When the source or destination is other than internal RAM or internal I/O, 1-word access is used.
Note 3: In the case of 0 waits
state/byte
SPI
I/O Type
Read / Write
I2S
NANDF
USB
Read
Write
−
2 / 2
2 / 2
2 / 2
2 / 2
2 / 4
2 / 4
2 / 4
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Sample 1) Calculation example for CPU + HDMA
Conditions:
CPU operation speed (fSYS
)
: 60 MHz
I2S sampling frequency
: 48 KHz (60 MHz/25/50 = 48 KHz)
: 16 bits
I2S data transfer bit length
DMAC channel 0 used to transfer 5 Kbytes from internal RAM to I2S
Calculation example:
DMAC source data read time:
Internal RAM data read time = 1 state/4 bytes (However, the first 1 byte requires 2 states.)
DMAC destination write time:
I2S register write time = 2 states/4 bytes
Transfer count
To transfer 5 Kbytes of data in 4-byte units, the transfer count is calculated as follows:
5 Kbytes/4 bytes = 1280 [times]
Since I2S generates an interrupt for every 64 bytes, the DMAC’s counter A is set to 16 (64 bytes/4 bytes = 16
times) and counter B is set to 80.
* Since an interrupt is generated 80 times, the first read to internal RAM (which requires 1 additional state)
occurs 80 times, requiring additional 80 states in total. In addition, from bus REQ to bus ACK, an overhead
time of 2 states is also needed for each interrupt request, requiring additional 160 states in total.
tSTOP (HDMA) = (((1 + 2) × 16) × 80) + 80 + 160) / fSYS [S] = 68 [μS]
HDMA start interval [s] = 1 / I2S sampling frequency [Hz] × (64 / 16 )
= 83.33 [mS]
CPU bus stop rate = tSTOP (HDMA) [s] / HDMA start interval [s]
= 68 [μS] / 83.33 [mS] = 0.08 [%]
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(2) CPU + LDMA
The LCD controller performs DMA transfer (LDMA) after issuing a bus request to the
CPU and getting a bus acknowledgement.
If LDMA is not performed properly, the LCD display function cannot work properly.
Therefore, LDMA must have higher priority than the CPU. While LDMA is being
performed, the CPU cannot execute instructions.
To display data on the LCD using the LCD controller, it is necessary to estimate to what
degree LDMA would interfere with the CPU operation based on the display RAM type,
display RAM bus width, LCDD type, display pixel count, and display quality.
The time the CPU stops operation while the LCD controller transfers data for one line is
defined as “tSTOP (LDMA)”, which is calculated as shown below for each display mode.
tSTOP (LDMA) = (SegNum × K / 8) × tLRD
16-bit external SRAM
Internal RAM
: tLRD = (2 + wait count) / fSYS [Hz] / 2
: tLRD = 1 / fSYS [Hz] / 4
16-bit external SDRAM :tLRD= 1 / fSYS [Hz] / 2
SegNum
K
: Number of segments to be displayed
: Number of bits needed for displaying 1 pixel
Monochrome
4 gray scales
16 gray scales
256 colors
K = 1
K = 2
K = 4
K = 8
K = 12
K = 16
K = 24
4096 colors
65536 colors
262144/16777216 colors
Note 1: When SDRAM is used, the overhead time is added as shown below.
STOP [s] = (SegNum × K/8) × tLRD + ((1/fSYS) × 8)
t
Note 2: When internal RAM is used, the overhead time is added as shown below.
STOP [s] = ( SegNum × K/8 )×tLRD + (1/fSYS
t
)
The CPU bus stop rate indicates what proportion of the 1-line data update time
tLP is taken up by tSTOP(LDMA) and is calculated as follows:
CPU bus stop rate = tSTOP (LDMA) [s] / LHSYNC [period: s]
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Sample2) Calculation examples for CPU + LDMA
Conditions 1:
CPU operation speed (fSYS
)
: 60 MHz
Display RAM
: Internal RAM
Display size
: QVGA (320seg × 240com)
: 65536 colors (TFT)
Display quality
Refresh rate
: 70 Hz (including 20 clocks of dummy cycles)
Calculation example 1:
tSTOP (LDMA)
= ((SegNum × K / 8) × tLRD) + (1 / fSYS [Hz])
= ((320 × 16 / 8) × 1 / fSYS [Hz] / 4) + (1 / fSYS [Hz])
= ((640) × 16.67 [ns] / 4) + 16.67 [ns]
= 2.68 [μs]
LHSYNC [period: s] = 1/70 [Hz] /(COM+20=260) = 54.95 [μs]
CPU bus stop rate
= tSTOP (LCD)[s] / LHSYNC [period: s]
= 2.68 [μs] / 54.95 [μs] = 4.88 [%]
Conditions 2:
CPU operation speed (fSYS
)
: 10 MHz
Display RAM
: 16-bit external SRAM (0 waits)
: QVGA (240seg × 320com)
: 4096 colors (STN)
Display size
Display quality
Refresh rate
: 100 Hz (0 dummy cycles)
Calculation example 2:
tSTOP (LDMA)
= (SegNum × K / 8) × tLRD
= (240 × 12 / 8) × ( 2 + wait count) / fSYS [Hz] / 2
= (360) × 200 [ns] / 2
= 36 [μs]
LHSYNC [period: s]
CPU bus stop rate
= 1/100 [Hz] / (COM = 240) = 41.67 [μs]
= tSTOP (LCD)[s] / LHSYNC [period: s]
= 36 [μs] / 41.67 [μs] = 86.40 [%]
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TMP92CZ26A
(3) CPU + LDMA + ARDMA
The SDRAM controller owns the bus not only when SDRAM is used as the LCD display
RAM but also when SDRAM is used as work, data, or stack area. The SDRAM controller
occupies the bus (ARDMA) while it refreshes SDRAM data by the auto refresh function.
No special consideration is needed for the ARDMA time normally as it ends within
several clocks per specified number of states. However, if the LCD controller occupies the
bus continuously, ARDMA cannot be executed at normal intervals and refresh data is
stored in a counter specifically provided in the SDRAM controller. In this case, ARDMA is
executed successively after the LCD controller releases the bus.
The priorities among the three bus masters should be set in the order of LCDC >
SDRAMC > CPU. The time the CPU stops operation while the LCD controller and SDRAM
controller are transferring data for one line is defined as “tSTOP (LDMA･ARDMA)”, which is
calculated as follows:
tSTOP (LDMA･ARDMA) = tSTOP (LDMA)[s] − (tSTOP (LDMA)[s] / AR interval [s] × 2 / fSYS [Hz])
CPU bus stop rate = tSTOP (LDMA･ARDMA)[s] / LHSYNC [period: s]
Auto Refresh Intervals
SDRCR<SRS2: 0>
Auto Refresh
Interval
Frequency (System Clock)
SRS2
SRS1
SRS0
6 MHz
10MHz
20MHz
40MHz
60MHz
80MHz
(states)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
47
78
7.8
4.7
7.8
2.4
3.9
1.18
1.95
0.78
1.30
0.59
0.98
1.95
3.90
5.85
7.80
11.70
15.60
13.0
156
312
468
624
936
1248
26.0
15.6
31.2
46.8
62.4
93.6
124.8
7.8
3.90
2.60
52.0
15.6
23.4
31.2
46.8
62.4
7.80
5.20
78.0
11.70
15.60
23.40
31.20
7.80
104.0
156.0
208.0
10.40
15.60
20.80
Unit: [μs]
92CZ26A-104
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TMP92CZ26A
Sample3) Calculation example for CPU + LDMA + ARDMA
Conditions:
CPU operating speed(fSYS
)
: 60 MHz
Display RAM
: 16-bit external SDRAM
: QVGA (320seg × 240com)
: 65536 colors (TFT)
Display size
Display quality
Refresh rate
: 70 Hz (including 20 clocks of dummy cycles)
: Every 936 states (15.6 μs)
SDRAM auto refresh
Calculation example:
tSTOP (LDMA)
=((SegNum × K / 8) × tLRD) + (8 / fSYS [Hz])
= ((320 ×16 / 8) × 1 / fSYS [Hz] / 2) + (8 / fSYS [Hz])
= ((640) × 16.67 [ns] / 2) + 133.33 [ns]
= 5.47 [μs]
LHSYNC [period:s]
= 1/70 [Hz] / (COM + 20 = 260) = 54.95 [μs]
Since SDRAM is auto-refreshed once or less in 5.47 [μs]:
tSTOP (ARDMA)
= 2 / fSYS [Hz] = 33.33 [ns]
CPU bus stop rate
= tSTOP(LDMA･ARDMA) [s] / LHSYNC [period:s]
= (5.47 [μs] + 33.33 [ns]) / 54.95 [μs] = 10.01 [%]
92CZ26A-105
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TMP92CZ26A
(4) CPU + LDMA+ ARDMA + HDMA
This is a case in which all the bus masters are active at the same time.
Since the LCD display function cannot work properly if the LCD controller cannot
perform LDMA properly, the priorities among the four bus masters should be set in the
order of LDMA > ARDMA > HDMA > CPU.
Before calculating the CPU bus stop rate, the conditions for proper LCD display shall be
considered first.
Setup time 1
LHSYNC
LCP0
LD-bus
LDMA1
Setup time 2
HDMA
(Worst case)
LDMA2
The above diagram shows the LHSYNC signal, LCP0 signal, and LD-bus signal for
transferring data from the LCD controller to the LCD driver, and the transfer operation
(LDMA1) for reading data from the display RAM into the FIFO buffer in the LCD
controller.
LDMA is started immediately after data has been transferred to the LCD driver. If
HDMA is started immediately before LDMA1 is started, LDMA must wait until HDMA
has finished before it can be started (LDMA2). LDMA2 must finish operation before the
LCD driver output for the next stage is started.
LHSYNC [period: s] − LCD driver data transfer time [s] − tSTOP(LCD) [s]
= HDMA continuous time [s] + CPU operation time [s]
In the case of STN display
LCD driver data transfer time [s] = SegNum/8×(1/fSYS) × (LD bus transfer speed)
In the case of TFT display
LCD driver data transfer time [s] = SegNum×(1/ fSYS) × (LD bus transfer speed)
92CZ26A-106
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TMP92CZ26A
Sample 4) Calculation example for CPU + LDMA+ ARDMA + HDMA
Conditions:
CPU operation speed (fSYS
)
: 60 MHz
Display RAM
: QVGA (320seg × 240com)
: 65536 colors (TFT)
Display quality
Refresh rate
: 70 Hz (including 20 clocks of dummy cycles)
: Every 936 states (15.6 μs)
: 16-bit width
SDRAM Auto Refresh
SDRAM
HDMA
: Transfers 5 Kbytes from internal RAM to I2S
Calculation example:
tSTOP (LDMA)
=((SegNum × K / 8) × tLRD) + (1 / fSYS [Hz])
= ((320 ×16 / 8) × 1 / fSYS [Hz] / 4) + (1 / fSYS [Hz])
= ((640) ×16.67 [ns] / 4) + 16.67 [ns]
= 2.68 [μs]
LHSYNC [period: s]
tSTOP (HDMA)
= 1/70 [Hz] /(COM+20 = 260) = 54.95 [μs]
= (((1 + 2) × 16) × 80) + 80 + 160) / fSYS [s] = 68 [μs]
LCD driver data transfer time [s]
= SegNum × (1/fSYS) × (LD bus transfer speed)
= 320 × (1/60 MHz) × 16 = 85 [μs]
Since LHSYNC [period: s] < LCD driver data transfer time [s], this setting is not possible.
When the transfer speed is changed to x4, the LCD driver data transfer time is calculated as follows:
(The transfer speed should be adjusted according to the required specifications.)
LCD driver data transfer time [s]
= SegNum × (1/fSYS) × (LD bus transfer speed)
= 320 × (1 / 60MHz) × 4 = 21.3 [μs]
LHSYNC [period: s] − LCD driver data transfer time [s] − tSTOP(LDMA)
= 54.95 [μs] − 21.3 [μs] − 2.68 [μs] = 30.94 [μs]
To realize proper LCD display, the maximum time HDMA can occupy the bus at a time (maximum HDMA time) must
be set to 30.92 [μS] or less. Although transferring all 5 Kbytes from the internal RAM to I2S requires tSTOP (HDMA) = 68
[μs], the maximum HDMA time should be limited by using the HDMATR register.
92CZ26A-107
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TMP92CZ26A
HDMATR Register
7
6
5
4
3
2
1
0
HDMATR
(097FH)
bit Symbol
Read/Write
After reset
DMATE
DMATR6 DMATR5 DMATR4 DMATR3
R/W
DMATR2
DMATR1
DMATR0
0
0
0
0
0
0
0
0
Timer
Maximum bus occupancy time setting
operation
0: Disable
1: Enable
The value to be set in <DMATR6:0> should be obtained by
“maximum bus occupancy time / (256/fSYS)”.
“00H” cannot be set.
Function
Note: Read-modify-write instructions can be used on this register.
By writing “87H” to the HDMATR register, the maximum HDMA time is set to 29.9 [μs]
(256 × 7 × (1 / fSYS)). Since HDMA start interval [period:s] = 83.33 [ms] is longer than
LHSYNC [period:s] = 54.95 [μs], it is assumed that HDMA transfer occurs once during
LHSYNC [period:s].
Since SDRAM is auto-refreshed once or less in 5.47 [μs]:
tSTOP (ARDMA) = 2 / fSYS [Hz] = 33.33 [ns]
The time LDMA, ARDMA, and HDMA all occupy the bus is defined as:
tSTOP(LDMA･ARDMA･HDMA)
Based on the above, the CPU bus stop rate is calculated as follows:
CPU bus stop rate = tSTOP(LDMA･ARDMA･HDMA) [s] / LHSYNC [period:s]
= (5.47 [μs] + 33.33 [ns]+29.9 [μs]) / 54.95 [μs] = 64.42 [%]
Note: To be precise, the bus assert time and RAM access time are added each time the HDMA transfer time is
forcefully terminated at 29.9 [μs].
92CZ26A-108
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TMP92CZ26A
Sample 5) Calculation example when using CPU + LCDC + SDRAMC + HDMA
at same time (Worst case)
Conditions:
CPU operation speed (fSYS
)
: 80MHz
Display RAM
: Internal RAM
Display size
: QVGA (320seg × 240com)
: 16777216 color (TFT)
: 70Hz
Display quality
Refresh rate
HDMA
: Transfers 225 Kbytes from internal RAM to SDRAM
Calculation example:
tSTOP (LCD)
= ((SegNum × K/8) × tLRD) + (1/fSYS [Hz])
= ((320 × 24/8) × 1/fSYS [Hz]/4) + (1/fSYS [Hz])
= ((960) × 12.5 [nS]/4) + 12.5 [nS]
= 3.0125 [μS]
LHSYNC [period: S]
= 1/70 [Hz]/ (COM+20) = 54.9 [μS]
t
STOP (HDMA)
= (((2 + 1) × 4) × 57600) + 28800 + 14400)/fSYS [S] = 9180 [μS]
LCD driver data transfer time [S]
= SegNum × (1/fsys) × (LD bus transfer speed)
= 320 × (1/80MHz) × 8 = 32 [μS]
LHSYNC [cycle S] - LCD driver data transfer time [S] − tSTOP (LCD)
= 54.9 [μS] − 32 [μS] − 3.0125 [μS] = 19.8875 [μS]
To realize proper LCD display, the maximum time HDMA can occupy the bus at a time (maximum HDMA time)
must be set to 19.8875 [μS] or less. Although transferring all 225 Kbytes from the internal RAM to SDRAM requires tSTOP
(HDMA) = 9180 [μs], the maximum HDMA time should be limited by using the HDMATR register.
HDMATR register
7
DMATE
6
5
4
3
2
1
0
Bit Symbol
Read/Write
After reset
DMATR6
DMATR5
DMATR4
DMATR3
DMATR2
DMATR1
DMATR0
HDMATR
(097FH)
R/W
0
0
0
0
0
0
0
0
Timer
Maximum bus occupancy time setting
The value to be set in <DMATR6:0> should be obtained by
operation
0: Disable
1:Enable
Function
“Maximum bus occupancy time / (256/f
“00H” cannot be set.
)”.
SYS
Note: Read-modify-write instructions can be used on this register.
By writing “86H” to the HDMATR register, the maximum HDMA time is set to 19.2[μs]
(256 × 6 × (1 / fSYS)).
Note: To be precise, the bus assert time and RAM access time are added each time the HDMA transfer time is
forcefully terminated at 19.2 [μs].
92CZ26A-109
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TMP92CZ26A
3.7 Function of ports
general-purpose I/O ports, these pins are also used by internal CPU and I/O functions. Table
3.7.2 lists I/O registers and their specifications.
Table 3.7.1 Port Functions (1/3) (R: PD= with programmable pull-down resistor, U= with pull-up resistor)
Number of
Pins
Pin Name for built-in
function
Port Name
Pin Name
I/O
R
I/O Setting
Port 1
P10 to P17
P40 to P47
P50 to P57
P60 to P67
P70
8
8
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I/O
Output
Output
I/O
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
bit
bit
D8 to D15
A0 to A7
A8 to A15
A16 to A23
RD
Port 4
Port 5
Port 6
Port 7
bit
bit
Output
I/O
(Fixed)
bit
,
P71
WRLL NDRE
,
NDWE
P72
I/O
bit
WRLU
EA24
EA25
P73
I/O
bit
P74
I/O
bit
P75
I/O
bit
R/ W , NDR/ B
P76
I/O
bit
WAIT
CS0
Port 8
P80
Output
Output
Output
Output
Output
Output
Output
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
,
P81
CS1 SDCS
,
P82
CS2 CSZA
,
P83
CS3 CSXA
P84
CSZB
P85
CSZC
CSZD , ND0CE
P86
CSXB , ND1CE
TXD0
P87
1
1
1
1
1
1
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
2
Output
I/O
−
−
(Fixed)
bit
Port 9
P90
P91
I/O
−
bit
RXD0
SCLK0,
CTS0
P92
I/O
−
bit
P96
Input
Input
Input
I/O
PD
−
(Fixed)
(Fixed)
(Fixed)
bit
INT4, PX
PY
P97
Port A
Port C
PA0 to PA7
PC0
U
−
KI0 to KI7
INT0
PC1
I/O
−
bit
INT1, TA0IN
INT2
PC2
I/O
−
bit
PC3
I/O
−
bit
INT3, TA2IN
EA26
PC4
I/O
−
bit
PC5
I/O
−
bit
EA27
PC6
I/O
−
bit
EA28
PC7
I/O
−
bit
KO8
Port F
PF0
I/O
−
bit
I2S0CKO
I2S0DO
I2S0WS
I2S1CKO
I2S1DO
I2S1WS
SDCLK
AN0 to AN1
AN2, MX
PF1
I/O
−
bit
PF2
I/O
−
bit
PF3
I/O
−
bit
PF4
I/O
−
bit
PF5
I/O
−
bit
PF7
Output
Input
Input
Input
Input
−
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
Port G
PG0 to PG1
PG2
−
−
AN3,
, MY
ADTRG
AN4 to AN5
PG3
−
PG4 to PG5
−
92CZ26A-110
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TMP92CZ26A
Table 3.7.1 Port Functions (2/3)
Number of
Pin Name for built-in
function
Port Name
Port J
Pin Name
PJ0
I/O
R
I/O Setting
Pins
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
1
1
1
8
1
1
1
1
1
1
1
1
1
1
1
8
,
SDRAS SRLLB
Output
Output
Output
Output
Output
I/O
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
bit
,
SDCAS SRLUB
PJ1
,
SDWE SRWR
PJ2
PJ3
SDLLDQM
SDLUDQM
NDALE
PJ4
PJ5
PJ6
I/O
bit
NDCLE
PJ7
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
I/O
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
(Fixed)
bit
SDCKE
Port K
PK0
LCP0
PK1
LLOAD
PK2
LFR
PK3
LVSYNC
LHSYNC
LGOE0
PK4
PK5
PK6
LGOE1
PK7
LGOE2
Port L
PL0 to PL7
PM1
PM2
PM7
PN0 to PN7
PP1
LD0 to LD7
MLDALM, TA1OUT
Port M
,
ALARM MLDALM
PWE
Port N
Port P
KO0 to KO7
TA3OUT
TA5OUT
INT5, TA7OUT
INT6, TB0IN0
INT7, TB1IN0
TB0OUT0
TB1OUT0
SPDI
I/O
bit
PP2
I/O
bit
PP3
I/O
bit
PP4
I/O
bit
PP5
I/O
bit
PP6
Output
Output
I/O
(Fixed)
(Fixed)
bit
PP7
Port R
PR0
PR1
I/O
bit
SPDO
SPCS
PR2
I/O
bit
PR3
I/O
bit
SPCLK
Port T
Port U
PT0 to PT7
PU0 to PU4
,PU6
PU5
I/O
bit
LD8 to LD15
6
I/O
−
bit
LD16 to LD20 , LD22
1
1
1
1
1
1
1
1
1
8
1
1
1
I/O
I/O
−
−
−
−
−
−
−
−
−
−
−
−
−
bit
bit
LD21
PU7
LD23, EO_TRGOUT
Port V
PV0
I/O
bit
SCLK0
PV1
I/O
bit
−
PV2
I/O
bit
−
PV3
Output
Output
I/O
(Fixed)
(Fixed)
bit
−
PV4
−
PV6
SDA
PV7
I/O
bit
SCL
Port W
Port X
PW0 to PW7
PX4
I/O
bit
−
Output
I/O
bit
CLKOUT, LDIV
PX5
bit
X1USB
PX7
I/O
bit
−
92CZ26A-111
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TMP92CZ26A
Table 3.7.1 Port Functions (3/3)
Number of
Pin Name for built-in
Port Name
Port Z
Pin Name
PZ0
I/O
R
I/O Setting
Pins
1
function
EI_PODDATA
EI_SYNCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
−
−
−
−
−
−
−
−
bit
bit
bit
bit
bit
bit
bit
bit
PZ1
PZ2
PZ3
PZ4
PZ5
PZ6
PZ7
1
1
EI_PODREQ
EI_REFCLK
1
1
EI_TRGIN
1
EI_COMRESET
EO_MCUDATA
EO_MCUREQ
1
1
92CZ26A-112
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TMP92CZ26A
Table 3.7.2 I/O Port and Specifications (1/4)
X: Don’t care
I/O register
Port
Port 1
Pin name
Specification
Pn
X
X
X
X
X
X
X
X
X
X
X
X
X
1
PnCR
PnFC
PnFC2
None
P10 toP17
Input port
0
1
0
Output port
D8 to D15 bus
Output port
X
1
0
1
0
1
Port 4
Port 5
Port 6
P40 to P47
P50 to P57
P60 to P67
None
None
None
None
0
None
None
A0 to A7 Output
Output port
A8 to A15 Output
Input port
0
None
Output port
1
A16 to A23 Output
Output port
X
1
0
0
1
Port 7
P70 to P76
P71 to P76
P70
1
Input port
0
Output
RD
None
Output
WRLL
P71
1
1
1
1
Output
NDRE
0
Output
P72
WRLU
1
None
Output
0
NDWE
P73
P74
P75
EA24 Output
EA25 Output
X
X
X
X
X
X
1
1
1
0
0
1
1
1
1
1
0
R/
Output
W
NDR/B Input
Input
WAIT
P76
Port 8
P80 to P87
P80
Output port
0
Output
CS0
CS1
X
1
None
Output
P81
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
1
0
1
1
X
1
1
1
1
1
1
0
1
0
1
1
0
1
Output
SDCS
Output
P82
CS2
Output
Output
CSZA
SDCS
Output
None
P83
CS3
Output
Output
Output
Output
CSXA
CSZB
CSZC
CSZD
ND0CE
P84
P85
P86
None
0
1
0
1
Output
P87
CSXB Output
Output
ND1CE
92CZ26A-113
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TMP92CZ26A
Table3.7.2 I I/O Port and Specifications (2/4)
X: Don’t care
I/O register
PnCR PnFC
Port
Port 9
Pin name
Specification
Pn
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
PnFC2
None
None
None
None
0
P90, P92
P91
Input port
0
0
Input port, RXD0 Input
Input port
0
None
P96
None
0
None
0
P97
Input port
None
P90 to P92
P90
Output port
1
TXD0 Output
1
1
0
TXD0 Output (Open-drain)
SCLK0 Output
1
1
1
1
P92
1
0
SCLK0,
Input
CTS0
0
0
0
P96
INT4 Input
Input port
None
1
None
Port A
Port C
PA0 to PA7
0
None
None
KI0 to KI7 Input
Input port
1
PC0 to PC7
0
0
Output port
1
0
PC0
PC1
INT0 Input
0
1
INT1 Input
0
1
TA0IN Input
1
1
PC2
PC3
INT2 Input
0
1
None
INT3 Input
0
1
TA2IN Input
1
1
PC4
EA26 Output
EA27 Output
EA28 Output
KO8 Output (Open-drain)
Input port
0
1
PC5
0
1
PC6
0
1
PC7
1
1
Port F
PF0 to PF5
PF0 to PF5
PF7
0
1
0
Output port
0
Output port
None
X
0
PF0
I2S0CKO Output
I2S0DO Output
I2S0WS Output
I2S1CKO Output
I2S1DO Output
I2S1WS Output
SDCLK Output
1
PF1
X
1
None
PF2
X
1
PF3
X
1
PF4
X
X
X
X
1
PF5
X
1
PF7
None
1
92CZ26A-114
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TMP92CZ26A
Table3.7.2 I/O Port and Specifications (3/4)
X: Don’t care
I/O register
PnCR PnFC
Port
Port G
Pin name
Specification
Pn
X
PnFC2
None
PG0 to PG5
Input port
0
1
0
AN0 to AN5 Input
Input
None
ADTRG
PG3
PG2
MX Output Note:
MY Output Note:
Input port
PG3
Port J
PJ5 to PJ6
PJ5 to PJ6
PJ0 to PJ4,
PJ7
X
X
0
1
0
0
Output port
Output port
X
None
0
,
Output
Output
Output
SDRAS SRLLB
PJ0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
1
1
,
SDCAS SRLUB
PJ1
None
,
None
SDWE SRWR
PJ2
PJ3
SDLLDQM Output
SDLUDQM Output
NDALE Output
NDCLE Output
SDCKE Output
Output port
PJ4
PJ5
1
1
PJ6
PJ7
None
1
0
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
0
0
1
0
0
0
1
1
Port K
PK0 to PK7
PK0
LCP0 output
PK1
LLOAD output
LFR output
PK2
None
None
PK3
LVSYNC output
LHSYNC output
LGOE0 output
LGOE1 output
LGOE2 output
Output port
PK4
PK5
PK6
PK7
Port L
PL0 to PL7
PL0 to PL7
PM1 to PM2
PM1
None
None
None
None
LD0 to LD7 Output
Output port
Port M
TA1OUTOutput
MLDALM Output
1
Output
PM2
0
MLDALM
Output
1
ALARM
PM7
PWE Output
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Port N
Port P
PN0 to PN7
Input port
0
1
None
Output port (CMOS Output)
KO Output (Open-drain Output)
Input port
PP1 to PP5
PP1 to PP5
PP6 to PP7
PP1
0
Output port
1
Output port
None
TA3OUT output
TA5OUT output
INT5 input
1
1
0
1
0
1
0
1
PP2
PP3
1
1
1
None
TA7OUT output
INT6 input
PP4
PP5
TB0IN0 input
INT7 input
TB1IN0 input
PP6
PP7
TB0OUT0 output
TB1OUT1 output
1
1
None
Note: Case of using touch screen
92CZ26A-115
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TMP92CZ26A
Table 3.7.2 I/O Port and Specifications (4/4)
X: Don’t care
I/O register
PnCR PnFC
Port
Port R
Pin name
Specification
Pn
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
PnFC2
PR0 to PR3
PR0 to PR3
PR0
Input port
0
0
Output port
SPDI Input
SPDO Output
SPCS Output
SPCLK Output
Input port
1
0
1
1
1
0
1
1
0
1
1
X
0
1
0
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
0
0
1
X
0
0
0
0
0
1
1
1
1
1
None
PR1
PR2
PR3
Port T
Port U
PT0 to PT7
PT0 toPT7
PT0 to PT7
PU0 to PU7
PU0 to PU7
PU0 to PU7
PU7
None
None
Output port
LD8 to LD15 Output
Input port
Output port
LD16 to LD23 Output
EO_TRGOUT (
= “0”) Note:
DBGE
Port V
PV0 to PV2
PV0 to PV4
PV6 to PV7
PV6 to PV7
PV6 to PV7
PV0
Input port
Output port
Input port
Output port
None
0
Output port (Open-drain)
SCLK0 Output
SDA I/O
1
None
PV6
0
1
0
1
SDA I/O (Open-drain)
SCL I/O
PV7
SCL I/O (Open-drain)
Input port
Port W
Port X
PW0 to PW7
X
0
0
None
PW0 to PW7
PX5, PX7
PX4
Output port
Input port
X
X
X
X
0
1
0
0
0
0
0
1
1
1
0
0
X
X
X
X
X
X
X
X
Output port
Output port
CLKOUT Output
LDIV Output
X1USB Input
Input port
None
1
PX5, PX7
PX4
None
None
None
1
PX5
X
X
X
X
X
X
X
X
X
X
X
0
0
Port Z
PZ0 to PZ7
Output port
1
EI_PODDATA (
= “0”) Note:
DBGE
PZ0
PZ1
PZ2
PZ3
PZ4
PZ5
PZ6
PZ7
X
X
X
X
X
X
X
X
EI_SYNCLK (
= “0”) Note:
= “0”) Note:
= “0”) Note:
DBGE
EI_PODREQ (
DBGE
DBGE
EI_REFCLK (
EI_TRGIN (
None
= “0”) Note:
DBGE
EI_COMRESET (
= “0”) Note:
DBGE
DBGE
EO_MCUDATA (
= “0”) Note:
= “0”) Note:
EO_MCUREQ (
DBGE
Note: When Debug mode, it is set to the Debug pin regardless of port setting.
92CZ26A-116
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TMP92CZ26A
3.7.1 Port 1 (P10 to P17)
Port1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or
outputs by control register P1CR and function register P1FC.
In addition to functioning as a general-purpose I/O port, port1 can also function as a data
bus (D8 to D15).
Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 1
to the following function pins:
AM1
AM0
Function Setting after reset is released
0
0
1
1
0
1
0
1
Don’t use this setting
Data bus (D8 to D15)
Don’t use this setting
Input port (P10 to P17)
P1CR Register
P1FC Register
External write enable
P1 Register
S
0
1
P10 to P17
(D8 to D15)
D8 to D15
Selector
S
1
0
Port read data
D8 to D15
Selector
External read enable
Figure 3.7.1 Port1
92CZ26A-117
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Port 1 register
7
P17
6
P16
5
P15
4
P14
3
P13
2
P12
1
P11
0
P10
P1
(0004H)
bit Symbol
Read/Write
After reset
R/W
Data from external port (Output latch register is cleared to “0”)
Port 1 Control register
7
6
5
4
3
2
1
0
P1CR
(0006H)
bit Symbol
Read/Write
After reset
Function
P17C
P16C
P15C
P14C
P13C
P12C
P11C
P10C
W
0
0
0
0
0
0
0
0
0: Input 1: Output
Port 1 Function register
7
6
5
4
3
2
1
0
P1FC
(0007H)
bit Symbol
Read/Write
After reset
Note2:
P1F
W
0/1
0: Port
1:Data bus
(D8 to D15)
Function
Port 1 Drive register
7
P17D
6
P16D
5
P15D
4
P14D
3
P13D
2
P12D
1
P11D
0
P10D
P1DR
(0081H)
bit Symbol
Read/Write
After reset
Function
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
Note1: Read-modify-write is prohibited for P1CR, P1FC.
Note2: It is set to “Port” or “Data bus” by AM pins state.
Figure 3.7.2 Register for Port1
92CZ26A-118
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3.7.2 Port 4 (P40 to P47)
Port4 is an 8-bit general-purpose Output ports. In addition to functioning as a
general-purpose Output port, port4 can also function as an address bus (A0 to A7). Each bit
can be set individually for function. Setting the AM1 and AM0 pins as shown below and
resetting the device initialize port 4 to the following function pins:
AM1
AM0
Function Setting after reset is released
0
0
1
1
0
1
0
1
Don’t use this setting
Address bus (A0 to A7)
Don’t use this setting
Output port (P40 to 47)
P4FC Register
P4 Register
S
0
P40 to P47
(A0 to A7)
1
A0 to A7
Selector
Read data
Figure 3.7.3 Port4
92CZ26A-119
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TMP92CZ26A
Port 4 register
7
P47
6
P46
5
P45
4
P44
3
P43
2
P42
1
P41
0
P40
P4
(0010H)
bit Symbol
Read/Write
After reset
R/W
0
0
0
0
0
0
0
0
Port 4 Function register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Note2:
P47F
P46F
P45F
P44F
P43F
P42F
P41F
P40F
P4FC
(0013H)
W
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0:Port 1:Address bus (A0 to A7)
Port 4 Drive register
Function
7
P47D
6
P46D
5
P45D
4
P44D
3
P43D
2
P42D
1
P41D
0
P40D
P4DR
(0084H)
bit Symbol
Read/Write
After reset
Function
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
Note1: Read-modify-write is prohibited for P4FC.
Note2: It is set to “Port” or “Data bus” by AM pins state.
Figure 3.7.4 Register for Port1r
92CZ26A-120
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TMP92CZ26A
3.7.3 Port 5 (P50 to P57)
Port5 is an 8-bit general-purpose Output ports. In addition to functioning as a
general-purpose I/O port, port5 can also function as an address bus (A8 to A15). Each bit
can be set individually for function. Setting the AM1 and AM0 pins as shown below and
resetting the device initialize port 5 to the following function pins:
AM1
AM0
Function Setting after reset is released
0
0
1
1
0
1
0
1
Don’t use this setting
Address bus (A8 ~ A15)
Don’t use this setting
Output port (P50 ~ P57)
P5FC Register
P5 Register
S
P50 to P57
(A8 to A15)
0
1
A8 to A15
Read data
Selector
Figure 3.7.5 Port5
92CZ26A-121
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Port 5 register
7
P57
6
P56
5
P55
4
P54
3
P53
2
P52
1
P51
0
P50
P5
(0014H)
bit Symbol
Read/Write
After reset
R/W
0
0
0
0
0
0
0
0
Port 5 Function register
7
6
5
4
3
2
1
0
P5FC
(0017H)
bit Symbol
Read/Write
After reset
Note2:
P57F
P56F
P55F
P54F
P53F
P52F
P51F
P50F
W
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0:Port 1:Address bus (A8 to A15)
Port 5 Drive register
Function
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
P57D
P56D
P55D
P54D
P53D
P52D
P51D
P50D
P5DR
(0085H)
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
Note1: Read-modify-write is prohibited for P5FC.
Note2: It is set to “Port” or “Data bus” by AM pins state.
Figure 3.7.6 Register for Port5
92CZ26A-122
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3.7.4 Port 6 (P60 to P67)
Port6 is an 8-bit general-purpose I/O ports. Bits can be individually set as either inputs
or outputs and function by control register P6CR and function register P6FC.
In addition to functioning as a general-purpose I/O port, port6 can also function as an
address bus (A16 to A23). Setting the AM1 and AM0 pins as shown below and resetting the
device initialize port 6 to the following function pins:
AM1
AM0
Function Setting after reset is released
0
0
1
1
0
1
0
1
Don’t use this setting
Address bus(A16 ~ A23)
Don’t use this setting
Input port(P60 ~ P67)
P6CR Register
P6FC Register
P6 Register
S
P60 to P67
(A16 to A23)
0
1
A16 to A23
Read data
Selector
S
1
0
Selector
Figure 3.7.7 Port6
92CZ26A-123
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Port 6 register
7
6
5
4
3
2
1
0
P6
(0018H)
bit Symbol
Read/Write
After reset
P67
P66
P65
P64
P63
P62
P61
P60
R/W
Data from external port (Output latch register is cleared to “0”)
Port 6 Control register
7
P67C
6
P66C
5
P65C
4
P64C
3
P63C
2
P62C
1
P61C
0
P60C
P6CR
(001AH)
bit Symbol
Read/Write
After reset
Function
W
0
0
0
0
0
0
0
0
0:Input 1:Output
Port 6 Function register
7
6
5
4
3
2
1
0
P6FC
(001BH)
bit Symbol
Read/Write
After reset
Note2:
P67F
P66F
P65F
P64F
P63F
P62F
P61F
P60F
W
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0: Port 1:Address bus (A16 to A23)
Port 6 Drive buffer register
Function
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
P67D
P66D
P65D
P64D
P63D
P62D
P61D
P60D
P6DR
(0086H)
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
Note: Read-modify-write is prohibited for P6CR, P6FC.
Note2: It is set to “Port” or “Data bus” by AM pins state.
Figure 3.7.8 Register for Port6
92CZ26A-124
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3.7.5 Port 7 (P70 to P76)
Port7 is a 7-bit general-purpose I/O port (P70 is used for output only). Bits can be
individually set as either inputs or outputs by control register P7CR and function register
P7FC. In addition to functioning as a general-purpose I/O port, P70 to P76 pins can also
function interface-pin for external memory.
A reset initializes P70 pin to output port mode, and P71 to P76 pins to input port mode.
Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 7
to the following function pins:
Initial setting of P70 pin
AM1
AM0
Function Setting after reset is released
Don’t use this setting
0
0
1
1
0
1
0
1
pin
RD
Don’t use this setting
Output port (P70)
P7FC register
P7 register
S
0
P70 (
)
RD
1
RD
Selector
Port read data
P7CR register
P7FC register
P7 register
S
0
1
P71 (
P72 (
,
,
)
)
WRLL NDRE
NDWE
WRLU
S
0
1
Selector
NDRE ,NDWE
WRLL , WRLU
Selector
S
1
0
Port read data
Selector
Figure 3.7.9 Port7
92CZ26A-125
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P7CR register
P7FC register
S
P73 (EA24)
P74 (EA25)
P7 register
0
1
EA24, EA25
Read data
Selector
S
1
0
Selector
P7CR register
P7FC register
P7 register
S
0
1
P75(R/W,
)
NDR /B
R/W
Selector
S
1
0
Port read data
Selector
NDR/B
P7CR register
P7FC register
P76 (
)
WAIT
P7 register
Port read data
WAIT
Figure 3.7.10 Port7
92CZ26A-126
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Port 7 register
7
6
P76
5
P75
4
P74
3
P73
2
P72
1
P71
0
P70
P7
(001CH)
bit Symbol
Read/Write
R/W
Data from external port Data from external port Data from external port
(Output latch register is (Output latch register is (Output latch register is
After reset
1
set to “1”)
cleared to “0”)
set to “1”)
Port 7 Control register
7
7
6
P76C
5
P75C
4
P74C
3
P73C
2
P72C
1
P71C
0
P7CR
(001EH)
bit Symbol
Read/Write
After reset
Function
W
0
0
0
0
0
0
0: Input 1: Output
Port 7 Function register
6
P76F
5
P75F
4
P74F
3
P73F
W
2
P72F
1
P71F
0
P70F
bit Symbol
Read/Write
After reset
Function
P7FC
(001FH)
0
0
0
0
0
0
0/1 Note3:
0:Port
1:
RD
0:Port
0:Port
0:Port
Refer to following table
1:
1:
at
NDWE
<P72>=0
at
1:
WAIT
at
NDRE
<P71>=0
WRLU
at
WRLL
<P72>=1
<P71>=1
Port 7 Drive register
7
6
5
4
3
2
1
0
P76D
P75D
P74D
P73D
R/W
1
P72D
P71D
P70D
bit Symbol
Read/Write
After reset
Function
P7DR
(0087H)
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
P71 setting
P72 setting
<
P73 setting
<P73C>
<
<P72C>
<P71C>
>
0
1
0
1
0
1
<P72F>
0
<P71F>
0
<P73F>
0
Input Port
Reserved
Output Port
Output
Input Port
Reserved
Output Port
EA24Output
Input Port
Reserved
Output Port
Output
(at <P71>=0)
Output
WRLL
(at <P71>=1)
NDWE
NDRE
(at <P72>=0)
1
1
1
Output
WRLU
(at <P72>=1)
P76 setting
P75 setting
<P75C>
P74 setting
<P76C>
<P74C>
0
1
0
1
0
1
<P76F>
0
<P75F>
0
<P74F>
0
Input Port
Output Port
Reserved
Input Port
Output Port
R/W Output
Input Port
Reserved
Output Port
EA25Output
Input
WAIT
NDR/ Input
B
1
1
1
Note1: Read-modify-write is prohibited for P7CR, P7FC.
Note2: When
and
are used, set registers by following order to avoid outputting negative glitch.
bit1
NDRE
NDWE
Order
Registser bit2
------------------------------------------------------
(1)
(2)
(3)
P7
0
1
1
0
1
1
P7FC
P7CR
Note3: Note2: It is set to “Port” or “Data bus” by AM pins state.
Figure 3.7.11 Register for Port7
92CZ26A-127
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3.7.6 Port 8 (P80 to P87)
Port 80 to 87 are 8-bit output ports. Resetting sets output latch of P82 to “0” and output
latches of P80 to P81, P83 to P87 to “1”. But if it is started at boot mode (AM [1:0]= “11”),
output latch of P82 is set to “1”.
Port 8 also function as interface-pin for external memory.
Writing “1” in the corresponding bit of P8FC, P8FC2 enables the respective functions.
Resetting resets P8FC to “0” and P8FC2 to “0”, sets all bits to output ports.
Reset
Function
control2
P8FC2 write
Function
control
P80 (
P81 (
P82 (
P83 (
P84 (
P85 (
P86 (
)
CS0
P8FC write
Output latch
P8 write
,
)
,
)
CS1 SDCS
S
,
)
CS2 CSZA SDCS
,
CS3 CSXA
)
)
,
CSZB
CSZC
CSZD ND0CE
Selector
)
)
P87 ( CSXB ,
ND1CE
,
,
,
,
,
,
,
CS0 SDCS SDCS CSXA CSZB CSZC ND0CE ND1CE
P8 read
“1”,
,
,
,“1”, “1”, “1”, “1”
SDCS CSZA CSXA
,
,
,
,
,
,
, CSXB
CS0 CS1 CS2 CS3 CSZB CSZC CSZD
Figure 3.7.12 Port 8
92CZ26A-128
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Port 8 register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
P87
P86
P85
P84
P83
P82
P81
P80
P8
(0020H)
R/W
1
1
1
1
1
0 (Note3)
1
1
Port 8 Function register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
P87F
P86F
P85F
P84F
P83F
P82F
P81F
P80F
P8FC
(0023H)
W
0
0
0
0
0
0
0
0
0: Port
0: Port
0: Port
0: Port
1:
Refer to following table
0: Port
0: Port
Function
1: <P87F2> 1: <P86F2> 1:
1:
1:
CS0
CSZC
CSZB
CS1
Port 8 Function registers 2
7
6
5
4
3
2
P82F2
W
1
0
bit Symbol
Read/Write
After reset
P87F2
P86F2
P83F2
P81F2
P8FC2
(0021H)
W
0
0
0
0
0
Refer to following table
0:
CSZD
0: <P81F>
0: CSXB
1:
1:
SDCS
ND0CE
Function
1:
ND1CE
Port 8 Drive register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
P87D
P86D
P85D
P84D
P83D
P82D
P81D
P80D
P8DR
(0088H)
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
P83 setting
P86 setting
P82 setting
<P82F>
<P83F>
<P83F2>
<P86F>
0
1
0
1
0
1
<P86F2>
0
<P82F2>
0
0
1
Output
port
CS3
Output
Output
Output port
Output
CSZD
Output port
Output
CS2
SDCS
Output
Don’t setting
ND0CE
Output
CSZA
Output
1
CSXA
1
P87 setting
<P87F>
0
1
<P87F2>
0
1
Output port
Output
Output
CSXB
Don’t setting
ND1CE
Note1: Read-modify-write is prohibited for P8FC and P8FC2.
Note2: Don’t write “1” to P8<P82>- register before setting P82-pin to /CS2 or /CSZA because of P82-pin output “0” as /CE for
program memory by reset.
Note3: If it is started at boot mode (AM [1:0]= “11”), output latch of P82 is set to “1”.
Note4: When
and
are used, set registers by following order.
ND0CE
ND1CE
bit1
Order
Registser bit2
------------------------------------------------------
(1)
(2)
(3)
P8
1
1
1
1
1
1
P8FC2
P8FC
Figure 3.7.13 Register for Port 8
92CZ26A-129
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TMP92CZ26A
3.7.7 Port 9 (P90 to P92, P96, P97)
P90 to P92 are 3-bit general-purpose I/O port. I/O can be set on bit basis using the
control register. Resetting sets P90 to P92 to input port and all bits of output latch to”1”.
P96 to P97 are 2-bit general-purpose input port.
Writing “1” in the corresponding bit of P9FC enables the respective functions.
Resetting resets the P9FC to “0”, and sets all bits to input ports.
(1) Port 90 (TXD0), Port 91 (RXD0), Port 92 (SCLK0,
)
CTS0
Port 90 to 92 are general-purpose I/O port. They are also used either SIO0. Each pin
is below.
SIO mode
(SIO0 module)
TXD0
UART, IrDA mode
(SIO0 module)
TXD0
P90
P91
P92
(Data output)
RXD0
(Data output)
RXD0
(Data input)
SCLK0
(Data input)
CTS0
(Clock input or
output)
(Clear to send)
Reset
Direction
control
(on bit basis)
P9CR write
Function
control
(on bit basis)
P9FC write
S
S
A
Output latch
P90 (TXD0)
Selector
B
P9 write
Open-drain enable
P9FC2<P90F2>
TXD0 output
S
B
Selector
A
P9 read
Figure 3.7.14 P90
92CZ26A-130
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TMP92CZ26A
Reset
Direction
control
(on bit basis)
P9CRwrite
Function
control
(on bit basis)
P9FCwrite
S
S
A
Output latch
Selector
B
P91(RXD0)
P92(SCLK0,
P9 write
)
CTS0
SCLK0 output
S
B
Selector
A
P9 read
RXD0 input
SCLK0 input
input
CTS0
Figure 3.7.15 P91, 92
Reset
Function
control
AVCC
TSICR0<PXEN>
Switch for TSI
typ.10Ω
<PYEN>
P9FC write
TSICR0<TSI7>
P96 (INT4,PX)
P97 (PY)
P9 read
TSICR1<DBC7>
Only for P96
S
A
Rising/Falling
De-bounce
Circuit
INT4
Selector
edge-ditection
B
TSICR0<TWIEN , TSI7>
IIMC<I4EDGE>
TSICR0<PXEN>
TSICR0<TSI7>
Pull-down resistor
typ.50KΩ
Figure 3.7.16 Port 96,97
92CZ26A-131
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TMP92CZ26A
Port 9 register
7
P97
6
P96
5
4
3
3
3
2
P92
1
P91
R/W
0
P90
bit Symbol
Read/Write
P9
(0024H)
R
Data from external
port
Data from external port (Output
latch register is set to “1”)
After reset
Port 9 control register
7
7
6
5
4
2
P92C
1
P91C
W
0
P90C
bit Symbol
Read/Write
After reset
Function
P9CR
(0026H)
0
0
0
Refer to following table
Port 9 function register
6
P96F
W
5
4
2
P92F
W
1
0
P90F
W
bit Symbol
Read/Write
After reset
P9FC
(0027H)
0
0
0
0: Input
port
1: INT4
Refer to
following
table
Refer to
following
table
Function
Port 9 Function registers 2
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
−
W
0
−
W
0
P90F2
W
0
P9FC2
(0025H)
Always
write “0”
Always
write “0”
0:CMOS
1:
Function
open-drain
Port 9 drive register
7
P97D
6
P96D
5
4
3
2
P92D
1
P91D
R/W
1
0
P90D
bit Symbol
Read/Write
After reset
Function
P9DR
(0089H)
R/W
1
1
1
1
Input/Output buffer drive register for standby mode
P91 setting
<P91C>
P90 setting
<P90C>
P92 setting
<P92C>
0
1
0
1
0
1
<P92F>
<P90F>
0
Input port,
Input
Input port,
Input port Output port
Don’t
setting
Input port
RXD0 Input
Output port
0
1
Input
TXD0
Output
CTS0
Don’t setting
CTS0
1
Don’t setting
Note 1: Read-modify-write is prohibited for P9CR, P9FC and P9FC2.
Note 2: When setting P96 pin to INT4 input, set P9DR<P96D> to “0” (prohibit input), and when driving P96 pin to “0”, execute
HALT instruction. This setting generates INT4 inside. If don’t using external interrupt in HALT condition, set like an
interrupt don’t generated. (e.g. change port setting)
Figure 3.7.17 Register for Port 9
92CZ26A-132
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TMP92CZ26A
3.7.8 Port A (PA0 to PA7)
Port A0 to A7 are 8-bit general-purpose input ports with pull-up resistor. In addition to
functioning as general-purpose I/O ports, port A0 to A7 can also Key-on wake-up function
as Keyboard interface. The various functions can each be enabled by writing a “1” to the
corresponding bit of the Port A Function Register (PAFC).
Resetting resets all bits of the register PAFC to “0” and sets all pins to be input port.
INTKEY
Rising edge
-ditection
PA0~PA7
8 input OR
Reset
KEY-ON
ENABLE
(on bit basis)
Pull-up resistor
PAFC write
PA0 to PA7
(KI0 to KI7)
PA read
Figure 3.7.18 Port A
When PAFC = “1”, if either of input of KI0-KI7 pins falls down, INTKEY interrupt is
generated. INTKEY interrupt can release all HALT mode.
92CZ26A-133
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TMP92CZ26A
Port A register
7
PA7
6
PA6
5
PA5
4
PA4
3
PA3
2
PA2
1
PA1
0
PA0
PA
(0028H)
bit Symbol
Read/Write
After reset
R
Data from external port
Port A Function register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PA7F
PA6F
PA5F
PA4F
PA3F
PA2F
PA1F
PA0F
PAFC
(002BH)
W
0
0
0
0
0
0
0
0
0: KEY IN disable
1: KEY IN enable
Port A Drive register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PA7D
PA6D
PA5D
PA4D
PA3D
PA2D
PA1D
PA0D
PADR
(008AH)
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
Note 1: Read-modify-write is prohibited for PAFC.
Figure 3.7.19 Register for Port A
92CZ26A-134
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TMP92CZ26A
3.7.9 Port C (PC0 to PC7)
PC0 to PC7 are 8-bit general-purpose I/O port. Each bit can be set individually for input
or output. Resetting sets Port C to an input port. It also sets all bits of the output latch
register to “1”.
In addition to functioning as a general-purpose I/O port, Port C can also function as
input pin for timers (TA0IN, TA2IN), input pin for external interruption (INT0 to INT3),
Extension address function (EA26, EA27, EA28) and output pin for Key (KO8). Above
setting is used the function register PCFC. Edge select of external interruption establishes
it with IIMC register, which there is in interruption controller.
(1) PC0 (INT0), PC2 (INT2)
Reset
Direction control
PCCR write
Function control
PCFC write
S
PC0 (INT0)
PC2(INT2)
Output latch
PCwrite
S
B
Selector
A
PC read
Level/edge selection
INT0
INT2
and
Rising/Falling selection
IIMC<I0LE, I0EDGE>
<I2LE, I2EDGE>
Figure 3.7.20 Port C0, C2
92CZ26A-135
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TMP92CZ26A
(2) PC1 (INT1, TA0IN), PC3 (INT3, TA2IN)
Reset
Direction control
PCCR write
Function control
PCFCwrite
S
PC1 (INT1,TA0IN)
PC3 (INT3, TA2IN)
Output latch
PCwrite
S
B
Selector
A
PC read
Level/edge selection
INT1
INT3
and
Rising/Falling selection
IIMC<I1LE, I1EDGE>
<I3LE, I3EDGE>
TA0IN
TA2IN
Figure 3.7.21 Port C1,C3
92CZ26A-136
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TMP92CZ26A
(3) PC4 (EA26), PC5 (EA27), PC6 (EA28)
Reset
Direction
control
(on bit basis)
PCCRwrite
Function
control
(on bit basis)
PCFC write
S
PC4(EA26)
S
A
B
PC5(EA27)
PC6(EA28)
Output latch
Selector
PC write
C
EA26
EA27
EA28
S
B
Selector
A
PC read
Figure 3.7.22 Port C4, C5, C6
(4) PC7 (KO8)
Reset
Direction
control
PCCR write
Function
control
PCFC write
PC7(KO8)
S
Output latch
Open-drain enable
PC write
S
B
Selector
A
PC read
Figure 3.7.23 Port C7
92CZ26A-137
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TMP92CZ26A
Port C register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PC
(0030H)
R/W
Data from external port (Output latch register is set to “1”)
Port C control register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PC7C
PC6C
PC5C
PC4C
PC3C
PC2C
PC1C
PC0C
PCCR
(0032H)
W
0
0
0
0
0
0
0
0
0: Input 1: Output
Port C function register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PC7F
PC6F
PC5F
PC4F
PC3F
PC2F
PC1F
PC0F
PCFC
(0033H)
W
0
0
0
0
0
0
0
0
Refer to following table
Port C drive register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PC7D
PC6D
PC5D
PC4D
PC3D
PC2D
PC1D
PC0D
PCDR
(008CH)
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
PC1 setting
0
PC0 setting
<PC0C>
PC2 setting
<PC2C>
<PC1C>
0
1
1
0
1
<PC2F>
<PC1F>
<PC0F>
0
1
Input port
INT2
Output port
Don’t setting
0
1
Input port
INT1
Output port
TA0IN input
0
1
Input port
INT0
Output port
Don’t setting
PC5 setting
PC4 setting
<PC4C>
PC3 setting
0
<PC5C>
<PC3C>
0
1
0
1
1
<PC5F>
<PC4F>
<PC3F>
0
1
Input port
EA27output
Output port
Reserved
0
1
Input port
EA26 output
Output port
Reserved
0
1
Input port
INT3
Output port
TA2IN input
PC7 setting
0
PC6 setting
<PC6C>
<PC7C>
1
0
1
<PC7F>
0
<PC6F>
0
Input port
Don’t
setting
Output port
KO8output
(Open-drain)
Input port
EA28output
Output port
Reserved
1
1
Note 1: Read-Modify-Write is prohibited for the registers PCCR, PCFC.
Note 2: When setting PC3-PC0 pins to INT3-INT0 input, set PCDR<PC3D: PC0D> to “0000”(prohibit input), and when driving
PC3-PC0 pins to “0”, execute HALT instruction. This setting generates INT3-INT0 inside. If don’t use external interrupt
in HALT condition, set like an interrupt don’t generated. (e.g. change port setting)
Figure 3.7.24 Register for Port C
92CZ26A-138
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TMP92CZ26A
3.7.10 Port F (PF0 to PF5, PF7)
Port F0 to F5 are 6-bit general-purpose I/O ports. Resetting sets PF0 to PF5 to be input
ports. It also sets all bits of the output latch register to “1”. In addition to functioning as
general-purpose I/O port pins, PF0 to PF5 can also function as the output for I2S0, I2S1. A
pin can be enabled for I/O by writing a “1” to the corresponding bit of the Port F Function
Register (PFFC).
Port F7 is 1-bit general-purpose output port. In addition to functioning as
general-purpose output port, PF7 can also function as the SDCLK output. Resetting sets
PF7 to be a SDCLK output port.
(1) Port F0 (I2S0CKO), Port F1 (I2S0DO), Port F2 (I2S0WS), Port F3 (I2S1CKO), Port F4
(I2S1DO), Port F5 (I2S1WS), Port F0 to F5 are general-purpose I/O port. They are also
used either I2S. Each pin is below.
I2Smode
I2Smode
(I2S0Module)
(I2S1Module)
I2S0CKO
I2S1CKO
PF0
PF1
PF2
PF4
PF5
PF6
(Clock output)
(Clock output)
I2S0DO
I2S1DO
(Data output)
(Data output)
I2S0WS
I2S1WS
(Word-select
output)
(Word-select
output)
92CZ26A-139
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Reset
Direction
control
(on bit basis)
PFCR write
Function
control
(on bit basis)
PFFC write
S
S
A
Output latch
Selector
B
PF0 (I2S0CKO)
PF3 (I2S1CKO)
PF write
I2S0CKO output
S
B
I2S1CKO/X1D4output
Selector
A
PF read
Figure 3.7.25 Port F0, F3
Reset
Direction
control
(on bit basis)
PFCRwrite
Function
control
(on bit basis)
PFFC write
S
S
A
Output latch
PF1(I2S0DO)
PF2(I2S0WS)
PF4(I2S1DO)
PF5(I2S1WS)
Selector
B
PF write
I2S0DO,I2S1DO output
I2S0WS,I2S1WS output
S
B
Selector
A
PF read
Figure 3.7.26 Port F1, F2, F4, F5
92CZ26A-140
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TMP92CZ26A
(2) Port F7 (SDCLK),
Port F7 is general-purpose output port. In addition to functioning as general-purpose
output port, PF7 can also function as the SDCLK output.
Reset
Function
control
(on bit basis)
PFFC write
S
A
S
PF7(SDCLK)
Output latch
Selector
B
SDCLK
PF write
PF read
Figure 3.7.27 Port F7
92CZ26A-141
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TMP92CZ26A
Port F register
7
PF7
R/W
1
6
5
PF5
4
PF4
3
PF3
2
PF2
1
PF1
0
PF0
bit Symbol
Read/Write
After reset
PF
(003CH)
R/W
Data from external port (Output latch register is set to “1”)
Port F control register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PF5C
PF4C
PF3C
PF2C
PF1C
PF0C
PFCR
(003EH)
W
0
0
0
0
0
0
Refer to following table
Port F function register
7
PF7F
W
6
5
PF5F
4
PF4F
3
PF3F
2
PF2F
1
PF1F
0
PF0F
bit Symbol
Read/Write
After reset
PFFC
(003FH)
W
1
0
0
0
0
0
0
0: Port
Refer to following table
Function
1: SDCLK
Port F drive register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PF7D
PF6D
PF5D
PF4D
PF3D
PF2D
PF1D
PF0D
PFDR
(008FH)
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
PF0 setting
<PF0C>
PF1 setting
PF2 setting
<PF2C>
<PF1C>
0
1
0
1
0
1
<PF2F>
<PF1F>
<PF0F>
0
1
Input port
Output port
0
1
Input port
Output port
0
1
Input port
Output port
I2S0WS output
I2S0DO output
I2S0CKOoutput
PF4 setting
<PF4C>
PF5 setting
PF3 setting
<PF3C>
<PF5C>
0
1
0
1
0
1
<PF5F>
<PF4F>
<PF3F>
0
1
Input port
Output port
0
1
Input port
Output port
0
1
Input port
Output port
I2S1WS output
I2S1DO output
I2S1CKOoutput
Note 1: Read-Modify-Write is prohibited for the registers PFCR, PFFC and PFFC2.
Figure 3.7.28 Register for Port F
92CZ26A-142
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3.7.11 Port G (PG0 to PG5)
PG0 to PG5 are 6-bit input port and can also be used as the analog input pins for the
internal AD converter. PG3 can also be used as ADTRG pin for the AD converter.
PG2, PG3 can also be used as MX, MY pin for Touch screen interface.
(PG) register is prohibited to access by byte. All the instruction (Arithmetic/Logical/
Bit operation and rotate/shift instruction) access by byte are prohibited. Word access is
always needed.
Port G read
PG0(AN0),
PG1(AN1),
PG2(AN2,MX),
PG3(AN3,MY,
PG4(AN4)
)
ADTRG
PG5(AN5)
Conversion
AD
Channel
Selector
Result
Converter
Register
AD read
ADTRG
(for PG3 only)
(PG2,PG3 only)
TSICR0<MXEN,
MYEN >
Switch for TSI
Typ.10Ω
TSICR0<TSI7 >
Figure 3.7.29 Port G
92CZ26A-143
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Port G register
7
6
5
4
3
2
1
0
PG
(0040H)
Bit Symbol
Read/Write
After reset
PG5
PG4
PG3
PG2
PG1
PG0
R
Data from external port
Note: Selection of the input channel of AD converter and ADTRG input mode register is enabled by setting AD converter.
Port G Function register
7
6
5
4
3
2
1
0
Bit Symbol
Read/Write
After reset
Function
PG3F
W
0
PGFC
(0043H)
0: Input port
or AN3
1:
ADTRG
Port G driver register
7
6
5
4
3
2
1
0
Bit Symbol
Read/Write
After reset
Function
PG3D
PG2D
PGDR
(0090H)
R/W
1
1
Input/Output buffer
drive register for
standby mode
Figure 3.7.30 Register for Port G
Note 1: Read-Modify-Write is prohibited for the registers PGFC.
Note 2: (PG) register is prohibited to access by byte. All the instruction (Arithmetic/ Logical/ Bit operation and rotate/ shift
instruction) access by byte are prohibited. Word access is always needed.
Example:
LD
wa, (PG) : Using only “a” register data, and cancel “w” register data.
Note 3: Don’t use PG register at the state that mingles Analog input and Digital input.
92CZ26A-144
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3.7.12 Port J (PJ0 to PJ7)
PJ0 to PJ4 and PJ7 are 6-bit output port. Resetting sets the output latch PJ to “1”, and
they output “1”. PJ5 to PJ6 are 2-bit input/output port. In addition to functioning as port,
Port J also functions as output pins for SDRAM (
,
,
, SDLLDQM,
SDCAS SDWE
SDRAS
SDLUDQM, and SDCKE), SRAM (
,
and
) and NAND-Flash(NDALE
SRLUB
SRWR SRLLB
and NDCLE). Above setting is used the function register PJFC.
But Output signal either SDRAM or SRAM for PJ0 to PJ2 are selected automatically
according to the setting of memory controller.
Reset
Function
control2
(on bit basis)
PJFC2 write
Function
control
(on bit basis)
PJ0(
PJ1 (
,
)
SDRAS SRLLB
S
,
)
SDCAS SRLUB
PJ2(
,
)
SDWE SRWR
PJFC write
PJ3(SDLLDQM)
PJ4(SDLUDQM)
PJ7(SDCKE)
Selector
Selector
PJ write
,
,
SRLLB SRLUB SRWR
PJ read
,
,
, SDLLDQM, SDLUDQM, SDCKE
SDRAS SDCAS SDWE
Figure 3.7.31 Port J0 to J4 and J7
92CZ26A-145
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TMP92CZ26A
Reset
Direction
control
PJCR write
Function
control
PJFC write
S
S
A
Output latch
PJ5 (NDALE),
PJ6 (NDCLE)
Selector
B
PJ write
NDALE, NDCLE
output
S
B
Selector
A
PJ read
Figure 3.7.32 Port J5,J6
92CZ26A-146
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TMP92CZ26A
Port J register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
PJ
(004CH)
R/W
1
Data from external port
(Output latch register is
set to “1”)
1
1
1
1
1
After reset
Port J control register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PJ6C
PJ5C
PJCR
(004EH)
W
0
0
0: Input, 1: Output
Port J function register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PJ7F
PJ6F
PJ5F
PJ4F
PJ3F
PJ2F
PJ1F
PJ0F
PJFC
(004FH)
W
0
0
0
0
0
0
0
0
0: Port
1: SDCKE 1: NDCLE 1: NDALE 1:
SDLUDQM SDLLDQM
0: Port
0: Port
0: Port
0: Port
0: Port
1:
0: Port
0: Port
Function
1:
,
1:
,
1:
,
SDWE
SRWR
SDCAS
SRLUB
SDRAS
SRLLB
Port J drive register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PJ7D
PJ6D
PJ5D
PJ4D
PJ3D
PJ2D
PJ1D
PJ0D
PJDR
(0093H)
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
Note 1: Read-Modify-Write is prohibited for the registers PJCR and PJFC.
Figure 3.7.33 Register for Port J
92CZ26A-147
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TMP92CZ26A
3.7.13 Port K (PK0 to PK7)
PK0 to PK7 are 8-bit output ports. Resetting sets the output latch PK to “0”, and PK0 to
PK7 pins output “0”. In addition to functioning as output port function, Port K also
function as output pins for LCD controller (LCP0, LHSYNC, LLOAD, LFR, LVSYNC, and
LGOE0 to LGOE2).
Above setting is used the function register PKFC.
Reset
Function control
PK0 (LCP0)
(on bit basis)
PK1 (LLOAD)
PK2 (LFR)
PKFC write
PK3 (LVSYNC)
PK4 (LHSYNC)
PK5 (LGOE0)
PK6 (LGOE1)
PK7 (LGOE2)
S
A
B
Output latch
PK write
Output buffer
LCP0, LLOAD, LFR, LVSYNC,LHSYNC,LGOE0 to LGOE2
PK read
Figure 3.7.34 Port K0 to K7
92CZ26A-148
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TMP92CZ26A
Port K register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PK7
PK6
PK5
PK4
PK3
PK2
PK1
PK0
PK
(0050H)
R/W
0
0
0
0
0
0
0
0
Port K function register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PK7F
PK6F
PK5F
PK4F
PK3F
PK2F
PK1F
PK0F
PKFC
(0053H)
W
0
0
0
0
0
0
0
0
0:Port
0:Port
0:Port
1:LGOE0
0:Port
0: Port
0: Port
0: Port
0: Port
Function
1:LGOE2
1:LGOE1
1: LHSYNC 1: LVSYNC 1: LFR
1: LLOAD
1: LCP0
Port K drive register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PK7D
PK6D
PK5D
PK4D
PK3D
PK2D
PK1D
PK0D
PKDR
(0094H)
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
Note 1: Read-Modify-Write is prohibited for the registers PKFC.
Figure 3.7.35 Register for Port K
92CZ26A-149
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TMP92CZ26A
3.7.14 Port L (PL0 to PL7)
PL0 to PL7 are 8-bit output ports. Resetting sets the output latch PL to “0”, and PL0 to
PL7 pins output “0”. In addition to functioning as a general-purpose output port, Port L
can also function as a data bus for LCD controller (LD0 to LD7). Above setting is used the
function register PLFC.
Reset
Function
control
PLFC write
R
Output latch
S
A
Selector
B
PL0 to PL7
(LD0 to LD7)
PL write
LD0 to LD7
PL read
Figure 3.7.36 Port L0 to L7
92CZ26A-150
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TMP92CZ26A
Port L register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
PL
(0054H)
R/W
0
0
0
0
0
0
0
0
Port L function register
7
PL7F
6
PL6F
5
PL5F
4
PL4F
3
PL3F
2
PL2F
1
PL1F
0
PL0F
PLFC
(0057H)
bit Symbol
Read/Write
After reset
Function
W
0
0
0
0
0
0
0
0
0: Port 1: Data bus for LCDC (LD7 toLD0)
Port L drive register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PL7D
PL6D
PL5D
PL4D
PL3D
PL2D
PL1D
PL0D
PLDR
(0095H)
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
Note 1: Read-Modify-Write is prohibited for the registers PLFC.
Figure 3.7.37 Register for Port L
92CZ26A-151
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TMP92CZ26A
3.7.15 Port M (PM1, PM2, PM7)
PM1, PM2 and PM7 are 3-bit output ports. Resetting sets the output latch PM to “1”, and
PM1, PM2 and PM7 pins output “1”. In addition to functioning as output ports, Port M also
function as output pin for timers (TA1OUT), output pins for RTC alarm (
), output
ALARM
pin for melody/alarm generator (MLDALM,
) and Power control pin (PWE).
MLDALM
Above setting is used the function register PMFC.
PM1 has two output function which MLDALM and TA1OUT, and PM2 has two output
function which
and
. This selection is used PM<PM1>, PM<PM2>.
MLDALM
ALARM
Reset
Function control
PMFC write
S
S
Output latch
A
PM1
(MLDALM,
TA1OUT)
Y
Selector
B
PM write
PM Reset
A
S
TA1OUT
MLDALM
Y
Selector
B
Figure 3.7.38 Port M1
92CZ26A-152
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TMP92CZ26A
Reset
Function control
(on bit basis)
PMFC write
S
S
Output latch
A
PM2
( ALARM ,
MLDALM )
Y
Selector
B
PM write
PM read
A
S
MLDALM
ALARM
Y
Selector
B
Figure 3.7.39 Port M2
Reset
Function
control
(on bit basis)
PMFC write
S
S
Output latch
A
PM7 (PWE)
Y
Selector
B
PM write
PM read
PWE
Figure 3.7.40 Port M7
92CZ26A-153
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TMP92CZ26A
Port M register
7
PM7
R/W
1
6
6
5
4
3
3
2
PM2
1
PM1
0
0
bit Symbol
Read/Write
After reset
PM
(0058H)
R/W
1
1
Port M function register
7
PM7F
W
5
4
2
PM2F
1
PM1F
bit Symbol
Read/Write
After reset
PMFC
(005BH)
W
0
0
0
0: Port
0: Port
0: Port
1: PWE
1: ALARM 1: MLDALM
at <PM2>=1, at <PM1>=1,
Function
MLDALM
TA1OUT
at <PM2>=0 at <PM1>=0
Port M drive register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PM7D
R/W
1
PM2D
PM1D
PMDR
(0096H)
R/W
1
1
Input/Outp
ut buffer
drive
register for
standby
mode
Input/Output buffer
drive register for
standby mode
Function
Note 1: Read-Modify-Write is prohibited for the registers PMFC.
Figure 3.7.41 Register for Port M
92CZ26A-154
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TMP92CZ26A
3.7.16 Port N (PN0 to PN7)
PN0 to PN7 are 8-bit general-purpose I/O port. Each bit can be set individually for input
or output. Resetting sets Port N to an input port. In addition to functioning as a
general-purpose I/O port, Port N can also function as interface pin for key-board (KO0 to
KO7). This function can set to open-drain type output buffer.
Reset
Direction
control
(on bit basis)
PNCR write
Function
control
(on bit basis)
PNFC write
S
PN0(KO0) to PN7(KO7)
Output latch
Open-drain
enable
PN write
S
B
Selector
A
PC read
Figure 3.7.42 Port N
92CZ26A-155
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TMP92CZ26A
Port N register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PN7
PN6
PN5
PN4
PN3
PN2
PN1
PN0
PN
(005CH)
R/W
Data from external port (Output latch register is set to “1”)
Port N control register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PN7C
PN6C
PN5C
PN4C
PN3C
PN2C
PN1C
PN0C
PNCR
(005EH)
W
0
0
0
0
0
0
0
0
0: Input
1: Output
Port N function register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PN7F
PN6F
PN5F
PN4F
PN3F
PN2F
PN1F
PN0F
PNFC
(005FH)
W
0
0
0
0
0
0
0
0
0: CMOS output 1: Open-drain output
Port N drive register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PN7D
PN6D
PN5D
PN4D
PN3D
PN2D
PN1D
PN0D
PNDR
(0097H)
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
Note 1: Read-Modify-Write is prohibited for the registers PNCR and PNFC.
Figure 3.7.43 Register for Port N
92CZ26A-156
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TMP92CZ26A
3.7.17 Port P (PP1 to PP7)
Port P1 to P5 are 6-bit general-purpose I/O ports. Each bit can be set individually for
input or output. Resetting sets port P1 to P5 to input port and output latch to “0”. In
addition to functioning as general-purpose I/O port pins, P0 to P5 can also function as
output pin for timers (TA3OUT, TA5OUT, TA7OUT), input pin for timers (TB0IN0,
TB1IN0), input pin for external interruption (INT5 to INT7).
Port P6 and P7 are 2-bit output port. Resetting sets output latch to “0”.In addition to
functioning as output port, PP6 and PP7 can also function as output pin for timers
(TB0OUT0, TB1OUT1).
Above setting is used the control register PPCR and function register PPFC.
Edge select of external interruption establishes it with IIMC register, which there is in
interruption controller.
In port setting, if 16 bit timer input is selected and capture control is executed, INT6 and
INT7 don’t depend on IIMC1 register setting. INT6 and INT7 operate by setting
TBnMOD<TBnCPM1:0>.
Reset
Direction
control
(on bit basis)
PPCR write
Function
control
(on bit basis)
PPFC write
R
A
S
Output latch
PP write
Selector
B
PP1 (TA3OUT)
PP2 (TA5OUT)
TA3OUT output
TA5OUT output
S
B
Selector
A
PP read
Figure 3.7.44 Port P1, P2
92CZ26A-157
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TMP92CZ26A
Reset
Direction control
(on bit basis)
PPCR write
Function
control
(on bit basis)
PPFC write
R
S
A
Output latch
Selector
PP3 (INT5, TA7OUT)
B
PP write
TA7OUT
S
B
Selector
A
PP read
Level/edge selection
and
INT5
Rising/Falling selection
IIMC<I5LE, I5EDGE>
Figure 3.7.45 Port P3
Reset
Direction control
(on bit basis)
PPCR write
Function control
(on bit basis)
PPFC write
R
PP4 (INT6,TB0IN0)
PP5 (INT7, TB1IN0)
Output latch
PP write
PP read
S
B
Selector
A
Level/edge selection
INT6
INT7
and
Rising/Falling selection
(from TMRB0) INT6
(from TMRB1) INT7
IIMC<I1LE, I1EDGE>
<I3LE, I3EDGE>
TB0IN0
TB1IN0
Figure 3.7.46 Port P4,P5
92CZ26A-158
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TMP92CZ26A
Reset
Function
control
(on bit basis)
PPFC write
R
A
S
Output latch
Selector
B
PP6 (TB0OUT0)
PP7 (TB1OUT0)
PP write
TB0OUT0 output
TB1OUT0 output
Figure 3.7.47 Port P6, P7
92CZ26A-159
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TMP92CZ26A
Port P register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
PP7
PP6
PP5
PP4
R/W
PP3
PP2
PP1
PP
(0060H)
0
0
Data from external port
(Output latch register is cleared to “0”)
After reset
Port P control register
7
6
5
PP5C
4
PP4C
3
PP3C
W
0
2
PP2C
1
PP1C
0
0
PPCR
(0062H)
bit Symbol
Read/Write
After reset
Function
0
0
0
0
0: Input 1: Output
Port P function register
7
PP7F
6
PP6F
5
PP5F
4
PP4F
W
3
PP3F
2
PP2F
1
PP1F
bit Symbol
Read/Write
After reset
Function
PPFC
(0063H)
0
0
0
0
0
0
0
0:Port
0:Port
Refer to following table
1:TB1OUT0 1:TB0OUT0
Port P drive register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PP7D
PP6D
PP5D
PP4D
R/W
1
PP3D
PP2D
PP1D
PPDR
(0098H)
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
PP2 setting
PP1 setting
<PP1C>
>
PP3 setting
<PP3C>
<
<PP2C>
>
0
1
0
1
0
1
<PP1F>
<PP3F>
<PP2F>
0
1
Input port
INT5 input
Output port
TA7OUT output
0
1
Input port
Don’t setting TA3OUT output
Output port
0
1
Input port
Don’t setting TA5OUT output
Output port
PP5 setting
PP4 setting
<PP5C>
<PP4C>
0
1
0
1
<PP5F>
<PP4F>
0
1
Input port
INT7 input
Output port
TB1IN0 input
0
1
Input port
INT6 input
Output port
TB0IN0 input
Note1: Read-Modify-Write is prohibited for the registers PPCR, PPFC.
Note2: When setting PP5, PP4, PP3 pins to INT7,INT6,INT5 input, set PPDR<PP5D:3D> to “0000” (prohibit input), and when
driving PP5,PP4,PP3 pins to “0”, execute HALT instruction. This setting generates INT7, INT6, and INT5 inside. If don’t using
external interrupt in HALT condition, set like an interrupt don’t generated.
Figure 3.7.48 Register for Port P
92CZ26A-160
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TMP92CZ26A
3.7.18 Port R (R0 to R3)
Port R0 to R3 are 4-bit general-purpose I/O ports. Each bit can be set individually for
input or output. Resetting sets port R0 to R3 to input port and output latch to “0”. In
addition to functioning as general-purpose I/O port pins, PR0 to PR3 can also function as
SPI controller pin (SPCLK, SPCS , SPDO and SPDI).
Above setting is used the control register PRCR and function register PRFC.
Reset
Direction
control
(on bit basis)
PRCR write
Function
control
(on bit basis)
PRFC write
PR0(SPDI)
R
Output latch
PR write
S
B
Selector
A
PR read
SPDI input
Figure 3.7.49 Port R0
92CZ26A-161
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TMP92CZ26A
Reset
Direction
control
(on bit basis)
PRCR write
Function
control
(on bit basis)
PRFC write
S
R
PR1(SPDO),
A
Output latch
Selector
PR2( SPCS ),
PR3(SPCLK)
B
PR write
SPDO,
SPCS ,
SPCLK
S
B
Selector
A
PR read
Figure 3.7.50 Port R1 to R3
92CZ26A-162
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TMP92CZ26A
Port R register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
PR3
PR2
PR1
PR0
PR
(0064H)
R/W
Data from external port
(Output latch register is cleared to “0”)
After reset
Port R control register
7
7
6
6
5
4
3
PR3C
2
PR2C
1
PR1C
0
PR0C
bit Symbol
Read/Write
After reset
Function
PRCR
(0066H)
W
0
0
0
0
0: Input, 1: Output
Port R function register
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PR3F
PR2F
PR1F
PR0F
PRFC
(0067H)
W
0
0
0
0
0: Port
1: SPCLK
0: Port
1:
0: Port
1: SPDO
0: Port
1: SPDI
Function
SPCS
PR1 setting
PR0 setting
<PR0C>
<PR1C>
0
1
0
1
<PR1F>
<PR0F>
0
1
Input port
Output port
0
1
Input port
SPDI input
Output port
(Reserved)
(Reserved) SPDO output
PR3setting
<PR3C>
PR2 setting
<PR2C>
0
1
0
1
<PR3F>
<PR2F>
0
1
Input port
(Reserved)
Output port
SPCLK
output
0
1
Input port
(Reserved) SPCS Output
Output port
Port R drive register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PR3D
PR2D
PR1D
PR0D
PRDR
(0099H)
R/W
1
1
1
1
Input/Output buffer drive register
for standby mode
Function
Note: Read-Modify-Write is prohibited for the registers PRCR, PRFC.
Figure 3.7.51 Register for Port R
92CZ26A-163
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TMP92CZ26A
3.7.19 Port T (PT0 to PT7)
Port T0 to T7 are 8-bit general-purpose I/O ports. Each bit can be set individually for
input or output. Resetting sets port T0 to T7 to input port and output latch to “0”. In
addition to functioning as general-purpose I/O port pins, PT0 to PT7 can also function as
data bus pin for LCD controller (LD8 to LD15).
Above setting is used the control register PTCR and function register PTFC.
Reset
Direction
control
(on bit basis)
PTCR write
Function
control
(on bit basis)
PTFC write
S
Output latch
S
A
PT0 to PT7
(LD8 to LD15)
Selector
B
PT write
LD8 to LD15
S
B
Selector
A
PT read
Figure 3.7.52 Port T0 to T7
92CZ26A-164
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TMP92CZ26A
Port T register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
PT7
PT6
PT5
PT4
PT3
PT2
PT1
PT0
PT
(00A0H)
R/W
Data from external port (Output latch register is cleared to “0”)
Port T control register
After reset
7
6
5
4
3
2
1
0
PTCR
(00A2H)
bit Symbol
Read/Write
After reset
Function
PT7C
PT6C
PT5C
PT4C
PT3C
PT2C
PT1C
PT0C
W
0
0
0
0
0
0
0
0
0: Input 1: Output
Port T function register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PT7F
PT6F
PT5F
PT4F
PT3F
PT2F
PT1F
PT0F
PTFC
(00A3H)
W
0
0
0
0
0
0
0
0
0: Port 1: Data bus for LCDC (LD15 to LD8)
Port T drive register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PT7D
PT6D
PT5D
PT4D
PT3D
PT2D
PT1D
PT0D
PTDR
(009BH)
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
Note1: Read-Modify-Write is prohibited for the registers PTCR, PTFC.
Note2: When PT is used as LD15 to LD8, set applicable PTnC to”1”.
Figure 3.7.53 Register for Port T
92CZ26A-165
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TMP92CZ26A
3.7.20 Port U (PU0 to PU7)
Port U0 to U7 are 8-bit general-purpose I/O ports. Each bit can be set individually for
input or output. Resetting sets port U0 to U7 to input port and output latch to “0”. In
addition to functioning as general-purpose I/O port pins, PU0 to PU7 can also function as
data bus pin for LCD controller (LD16 to LD23) and SDCLK input function.
Above setting is used the control register PUCR and function register PUFC.
In addition to functioning as above function, PU7 can also function as communication for
debug mode (EO_TRGOUT). These functions are operated when it is started in debug
mode. In this case, PU7 can not be used as LD23 function.
Reset
Debug mode
Direction
control
(on bit basis)
PUCR write
Function
control
(on bit basis)
PUFC write
R
Output latch
S
A
PU0~PU4,PU6
(LD16 to LD20,LD22)
PU7
Selector
PU write
LD16 to LD20, LD22,LD23
EO_TRGOUT
B
(LD23,EO_TRGOUT)
C
S
B
Selector
A
PU read
Figure 3.7.54 Port U0 to U4 , U6 , U7
92CZ26A-166
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TMP92CZ26A
Reset
Direction
control
(on bit basis)
PUCR wirte
Function
control
(on bit basis)
PUFC write
R
S
A
Output latch
PU5 (LD21)
Selector
B
PU write
LD21
S
B
Selector
A
PU read
Figure 3.7.55 Port U5
92CZ26A-167
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TMP92CZ26A
Port U register
7
PU7
6
PU6
5
PU5
4
PU4
3
PU3
2
PU2
1
PU1
0
PU0
PU
(00A4H)
Bit Symbol
Read/Write
After reset
R/W
Data from external port (Output latch register is cleared to “0”)
Port U control register
7
6
5
4
3
2
1
0
Bit Symbol
Read/Write
After reset
Function
PU7C
PU6C
PU5C
PU4C
PU3C
PU2C
PU1C
PU0C
PUCR
(00A6H)
W
0
0
0
0
0
0
0
0
0: Input 1: Output
Port U function register
7
6
5
4
3
2
1
0
Bit Symbol
Read/Write
After reset
Function
PU7F
PU6F
PU5F
PU4F
PU3F
PU2F
PU1F
PU0F
PUFC
(00A7H)
W
0
0
0
0
0
0
0
0
0: Port
1: LD23
0: Port
1: LD22
0: Port
0: Port
1: LD20
0: Port
1: LD19
0: Port
1: LD18
0: Port
1: LD17
0: Port
1:
1: LD16
LD21@
<PU5C>=1
Note: When PU is used as LD23 to LD16, set applicable PUnC to “1”.
Port U drive register
7
6
5
4
3
2
1
0
Bit Symbol
Read/Write
After reset
Function
PU7D
PU6D
PU5D
PU4D
PU3D
PU2D
PU1D
PU0D
PUDR
(009CH)
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
Note1: Read-Modify-Write is prohibited for the registers PUCR, PUFC.
Note2: When use PU as LD23 to LD16, set PUnC to “1”. When use PU5 as LD21, set PU5C to “1”.
Figure 3.7.56 Register for Port U
92CZ26A-168
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TMP92CZ26A
3.7.21 Port V (PV0 to PV4, PV6, PV7)
Port V0 to V2, V6 and V7 are 5-bit general-purpose I/O ports. Each bit can be set
individually for input or output. Resetting sets port V0 to V2, V6 and V7 to input port and
output latch to “0”. In addition to functioning as general-purpose I/O port pins, PV can also
function as input or output pin for SBI (SDA, SCL) and output for SIO(SCLK0) (Note).
Above setting is used the control register PVCR and function register PVFC.
Port V3 and V4 are 2-bit general-purpose output ports. Resetting clear port V3 and V4 to
output latch to “0”.
Reset
Direction control
(on bit basis)
PVCR write
Function control
(on bit basis)
PVFC write
R
PV0 (SCLK0)
S
A
Output latch
PV1
PV2
Selector
B
PV write
SCLK0 出力
B
Selector
A
PV read
Note: SIO function support function that input clock from SCLK0, basically. However, if setting to PV0 pin, this function supports only
the output function.
Figure 3.7.57 Port V0 to V2
92CZ26A-169
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TMP92CZ26A
Reset
R
Output latch
PV3
PV4
PV write
PV read
Figure 3.7.58 Port V3, V4
Reset
Direction
control
(on bit basis)
PVCR write
Function
control
(on bit basis)
PVFC write
S
A
R
PV6(SDA)
PV7(SCL)
Output latch
Selector
B
Open-drain enable
PV write
PVFC2<PV6F2,PV7F2>
SDA,SCL output
S
B
Selector
A
PV read
SDA,SCL input
Figure 3.7.59 Port V6, V7
92CZ26A-170
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TMP92CZ26A
Port V register
7
PV7
6
PV6
5
4
PV4
3
PV3
2
PV2
R/W
1
PV1
0
PV0
PV
(00A8H)
bit Symbol
Read/Write
R/W
Data from external port
Data from external port
After reset
(Output latch register is
cleared to “0”)
(Output latch register is cleared to “0”)
Port V control register
7
PV7C
6
PV6C
5
4
3
3
2
PV2C
1
PV1C
W
0
0
PV0C
PVCR
(00AAH)
bit Symbol
Read/Write
After reset
Function
0
0
0
0
0: Input 1: Output
0: Input 1: Output
Port V function register
7
PV7F
6
PV6F
5
4
2
PV2F
1
PV1F
W
0
PV0F
bit Symbol
PVFC
(00ABH) Read/Write
After reset
W
0
0
0
0
0
Function
Refer to following table
Refer to following table
PV1 setting
0
PV0 setting
PV2 setting
<PV2C>
<PV1C>
<PV0C>
0
1
1
0
1
<PV2F>
<PV1F>
<PV0F>
0
1
Input port
Reserved
Output port
Reserved
0
1
Input port
Reserved
Output port
Reserved
0
1
Input port
Reserved
Output port
SCLK0 output
Note: SCLK0 is only output.
PV7 setting
0
PV6 setting
<PV6C>
<PV7C>
<PV7F>
1
0
1
<PV6F>
0
1
Input port
Reserved
Output port
SCL I/O
0
1
Input port
Reserved
Output port
SDA I/O
Port V function register 2
7
PV7F2
W
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PV6F2
W
0
PVFC2
(00A9H)
0
0:CMOS
1:Open
0:CMOS
1:Open
Function
-drain
-drain
Port V drive register
7
6
5
4
3
2
1
0
PVDR
(009DH)
bit Symbol
Read/Write
After reset
Function
PV7D
PV6D
PV4D
PV3D
PV2D
R/W
1
PV1D
PV0D
R/W
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
Note: Read-Modify-Write is prohibited for the registers PVCR, PVFC and PVFC2.
Figure 3.7.60 Register for Port V
92CZ26A-171
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TMP92CZ26A
3.7.22 Port W (PW0 to PW7)
Port W0 to W7 are 8-bit general-purpose I/O ports. Each bit can be set individually for
input or output. Resetting sets port W0 to W7 to input port and output latch to “0”.
Above setting is used the control register PWCR and function register PWFC.
Reset
Direction
control
(on bit basis)
PWCR write
Function
control
(on bit basis)
PWFC write
PW0 to PW7
R
Output latch
PW write
S
B
Selector
A
PW read
Figure 3.7.61 Port W0 to W7
92CZ26A-172
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TMP92CZ26A
Port W register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
PW7
PW6
PW5
PW4
PW3
PW2
PW1
PW0
PW
(00ACH)
R/W
Data from external port (Output latch register is cleared to “0”)
Port W control register
After reset
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PW7C
PW6C
PW5C
PW4C
PW3C
PW2C
PW1C
PW0C
PWCR
(00AEH)
W
0
0
0
0
0
0
0
0
0: Input 1: Output
Port W function register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PW7F
PW6F
PW5F
PW4F
PW3F
PW2F
PW1F
PW0F
PWFC
(00AFH)
W
0
0
0
0
0
0
0
0
0: Port 1: Reserved
Port W drive register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PW7D
PW6D
PW5D
PW4D
PW3D
PW2D
PW1D
PW0D
PWDR
(009EH)
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
Note1: Read-Modify-Write is prohibited for the registers PWCR, PWFC.
Figure 3.7.62 Register for Port W
92CZ26A-173
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TMP92CZ26A
3.7.23 Port X (PX4, PX5 and PX7)
Port X5 and X7 are 2-bit general-purpose I/O ports. Each bit can be set individually for
input or output. Resetting sets port X5 and X7 to input port and output latch to “0”. In
addition to functioning as general-purpose I/O port pins, PX5 and PX7 can also function as
USB clock input pin (X1USB).
Above setting is used the control register PXCR and function register PXFC.
Port X4 is 1-bit general-purpose output port. Resetting sets output latch to “0”. In
addition to functioning as general-purpose output port, PX4 can also function as system
clock output pin (CLKOUT) and output pin (LDIV). This setting is used the PX register
and function register PXFC.
Reset
Function
control
(on bit basis)
PXFC write
R
Output latch
S
A
PX4 (CLKOUT)
(LDIV)
PX write
Selector
B
PX read
S
A
CLKOUT output
LDIV output
Selector
B
Figure 3.7.63 Port X4
92CZ26A-174
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TMP92CZ26A
Reset
Direction
control
(on bit basis)
PXCR write
Function
control
(on bit basis)
PXFC write
PX5 (X1USB)
PX7
R
Output latch
PX write
S
B
Selector
A
PX read
X1USB input
Figure 3.7.64 Port X5, X7
92CZ26A-175
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TMP92CZ26A
Port X register
7
PX7
R/W
6
5
PX5
4
PX4
3
3
2
2
1
1
0
bit Symbol
Read/Write
PX
(00B0H)
R/W
Data from external port
(Output latch register is cleared to “0”)
Port W control register
After reset
7
PX7C
W
0
0: Input
1: Output
6
6
5
PX5C
W
0
0: Input
1: Output
4
0
0
bit Symbol
Read/Write
After reset
PXCR
(00B2H)
Function
Port W function register
7
5
4
3
2
1
bit Symbol
Read/Write
After reset
PX7F
W
0
PX5F
PX4F
PXFC
(00B3H)
W
0
0
0:Port
1: Reserved
0:Port
0:Port
1:X1USB
input
1:CLKOUT
at <PX4> = 0
LDIV
Function
at <PX4> = 1
Port W drive register
7
PXD7
R/W
1
6
5
PXD5
4
PXD4
3
2
1
0
bit Symbol
Read/Write
After reset
PXDR
(009FH)
R/W
1
1
Input/Output buffer drive register
for standby mode
Function
Note: Read-Modify-Write is prohibited for the registers PWCR, PWFC.
Figure 3.7.65 Register for Port X
92CZ26A-176
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TMP92CZ26A
3.7.24 Port Z (PZ0 to PZ7)
Port Z0 to Z7 are 8-bit general-purpose I/O ports. Each bit can be set individually for
input or output. Resetting sets port Z0 to Z7 to input port and output latch to “0”.
In addition to functioning as general-purpose I/O port function, Port Z can also function
as communication for debug mode (EI_PODDATA, EI_SYNCLK, EI_PODREQ,
EI_REFCLK, EI_TRGIN, EI_COMRESET, EO_MCUDATA and EO_MCUREQ). These
functions are operated when it is started in debug mode. (There is not Function register in
this port. When DBGE is set to “0”, this port set to debug communication function.)
Reset
Debug mode
Direction
control
(on bit basis)
PZCR write
R
PZ0 (EI_PODDATA)
PZ1 (EI_SYNCLK)
PZ2 (EI_PODREQ)
PZ3 (EI_REFCLK)
PZ4 (EI_TRGIN)
Output latch
PZ write
PZ5 (EI_COMRESET)
S
B
Selector
A
PZ read
EI_PODDATA
EI_SYNCLK
EI_PODREQ
EI_REFCLK
EI_TRGIN
EI_COMRESET
Figure 3.7.66 Port Z0 to Z5
92CZ26A-177
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TMP92CZ26A
Reset
Debug mode
Direction
control
(on bit basis)
PZCR write
R
A
S
Output latch
PZ6(EO_MCUDATA)
PZ7(EO_MCUREQ)
Selector
B
PZ write
EO_MCUDATA
EO_MCUREQ
B
S
Selector
PZ read
A
Figure 3.7.67 Port Z6 to Z7
92CZ26A-178
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TMP92CZ26A
Port Z register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PZ7
PZ6
PZ5
PZ4
PZ3
PZ2
PZ1
PZ0
PZ
(0068H)
R/W
Data from external port (Output latch register is cleared to “0”)
Port Z control register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PZ7C
PZ6C
PZ5C
PZ4C
PZ3C
PZ2C
PZ1C
PZ0C
PZCR
(006AH)
W
0
0
0
0
0
0
0
0
0: Input 1: Output
Port Z drive register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PZ7D
PZ6D
PZ5D
PZ4D
PZ3D
PZ2D
PZ1D
PZ0D
PZDR
(009AH)
R/W
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
Note: Read-Modify-Write is prohibited for the registers PZCR.
Figure 3.7.68 Register for Port Z
92CZ26A-179
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TMP92CZ26A
3.8
Memory Controller (MEMC)
3.8.1 Functions
TMP92CZ26A has a memory controller with a variable 4-block address area that controls as
follows.
(1) 4-block address area support
Specifies a start address and a block size for 4-block address area (block0 to 3).
* SRAM or ROM
* SDRAM
: All CS-blocks (CS0 to CS3) are supported.
: Either CS1 or CS2-blocks is supported.
: Only CS2-blocks is supported.
* Page-ROM
* NAND-Flash
: CS setting is not needed. If using NAND-Flash, set
BROMCR<CSDIS> to “1” as external area for avoiding
conflicting with other CS memory.
(2) Connecting memory specifications
Specifies SRAM, ROM, SDRAM as memories to connect with the selected address areas.
(3) Data bus width selection
Whether 8-bit or 16bit is selected as the data bus width of the respective block address areas.
(4) Wait control
Wait specification bit in the control register and WAIT input pin control the number of waits
in the external bus cycle. The number of waits of read cycle and write cycle can be specified
individually. The number of waits is controlled in 15 mode mentioned below.
0 to 10 wait, 12wait,
16 wait, 20 wait
4+N wait (controls with WAIT pin)
92CZ26A-180
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TMP92CZ26A
3.8.2 Control register and Operation after reset release
This section describes the registers to control the memory controller, the state after reset
release and necessary settings.
(1) Control Register
･ Control register: BnCSH/BnCSL(n=0 to 3, EX)
Sets the basic functions of the memory controller that is the connecting memory
type, the number of waits to be read and written.
･ Memory start address register: MSARn(n=0 to 3)
Sets a start address in the selected address areas.
･ Memory address mask register: MAMR (n=0 to 3)
Sets a block size in the selected address areas.
･ Page ROM control register: PMEMCR
Sets to control Page-ROM.
･ Adjust the timing of control signal register: CSTMGCR, WRTMGCR, RDTMGCRn
Adjust the timing of rising/falling edge of control signals.
･ Internal-Boot ROM control register: BROMCR
Sets to access Boot-ROM.
92CZ26A-181
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TMP92CZ26A
Table 3.8.1 Control register
7
6
5
4
3
2
1
0
B0CSL
(0140H)
Bit symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
B0WW3
B0WW2
B0WW1
B0WW0
B0WR3
B0WR2
B0WR1
B0WR0
R/W
0
B0E
R/W
0
0
1
0
0
0
1
0
B0CSH
(0141H)
B0REC
B0OM1
B0OM0
R/W
B0BUS1
B0BUS0
0
0
0
0
0
MAMR0
(0142H)
M0V20
M0V19
M0V18
M0V17
M0V16
M0V15
M0V14-V9
M0V8
R/W
R/W
R/W
1
1
1
1
1
1
1
1
MSAR0
(0143H)
M0S23
M0S22
M0S21
M0S20
M0S19
M0S18
M0S17
M0S16
1
1
1
1
1
1
1
1
B1CSL
(0144H)
B1WW3
B1WW2
B1WW1
B1WW0
B1WR3
B1WR2
B1WR1
B1WR0
0
B1E
R/W
0
0
1
0
0
0
1
0
B1CSH
(0145H)
B1REC
B1OM1
B1OM0
R/W
B1BUS1
B1BUS0
0
0
0
0
0
MAMR1
(0146H)
M1V21
M1V20
M1V19
M1V18
M1V17
M1V16
M1V15-V9
M1V8
R/W
R/W
R/W
1
1
1
1
1
1
1
1
MSAR1
(0147H)
M1S23
M1S22
M1S21
M1S20
M1S19
M1S18
M1S17
M1S16
1
1
1
1
1
1
1
1
B2CSL
(0148H)
B2WW3
B2WW2
B2WW1
B2WW0
B2WR3
B2WR2
B2WR1
B2WR0
0
0
1
0
0
0
1
0
B2CSH
(0149H)
B2E
B2M
B2REC
B2OM1
B2OM0
R/W
B2BUS1
B2BUS0
R/W
1
0
0
0
0
0
0
MAMR2
(014AH)
M2V22
M2V21
M2V20
M2V19
M2V18
M2V17
M2V16
M2V15
R/W
R/W
R/W
1
1
1
1
1
1
1
1
MSAR2
(014BH)
M2S23
M2S22
M2S21
M2S20
M2S19
M2S18
M2S17
M2S16
1
1
1
1
1
1
1
1
B3CSL
(014CH)
B3WW3
B3WW2
B3WW1
B3WW0
B3WR3
B3WR2
B3WR1
B3WR0
0
B3E
R/W
0
0
1
0
0
0
1
0
B3CSH
(014DH)
B3REC
B3OM1
B3OM0
R/W
B3BUS1
B3BUS0
0
0
0
0
0
M3V22
M3V21
M3V20
M3V19
M3V18
M3V17
M3V16
M3V15
MAMR3
(014EH)
R/W
R/W
1
1
1
1
1
1
1
1
M3S23
M3S22
M3S21
M3S20
M3S19
M3S18
M3S17
M3S16
MSAR3
(014FH)
1
1
1
1
1
1
1
1
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TMP92CZ26A
Table 3.8.2 Control register
7
6
5
4
3
2
1
0
BEXCSL
(0159H)
Bit Symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
Bit Symbol
Read/Write
After Reset
BEXWW3
BEXWW2
BEXWW1
BEXWW0
BEXWR3
BEXWR2
BEXWR1
BEXWR0
R/W
0
0
1
0
0
0
BEXOM0
R/W
1
0
BEXCSH
(0158H)
BEXREC
BEXOM1
BEXBUS1 BEXBUS0
0
OPGE
R/W
0
0
0
0
PMEMCR
(0166H)
OPWR1
OPWR0
PR1
PR0
R/W
R/W
R/W
0
0
0
1
0
CSTMGCR
(0168H)
TACSEL1
TACSEL0
TAC1
TAC0
R/W
0
0
0
0
WRTMGCR
(0169H)
TCWSEL1 TCWSEL0 TCWS1
R/W
TCWS0
R/W
TCWH1
TCWH0
R/W
0
0
0
0
0
0
RDTMGCR0
(016AH)
B1TCRS1
B1TCRS0
B1TCRH1 B1TCRH0 B0TCRS1
R/W
B0TCRS0
B0TCRH1 B0TCRH0
R/W
R/W
R/W
0
0
0
0
0
0
0
0
RDTMGCR1
(016BH)
B3TCRS1
B3TCRS0
B3TCRH1 B3TCRH0 B2TCRS1
R/W
B2TCRS0
B2TCRH1 B2TCRH0
R/W
R/W
R/W
0
0
0
0
0
0
0
ROMLESS
R/W
0
BROMCR
(016CH)
CSDIS
VACE
1
0/1
1/0
-
RAMCR
(016DH)
R/W
Always
write “1”
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(2) Operation after releasing reset
The data bus width at starting is determined depending on state of AM1/AM0 pins after
releasing reset. Then, the external memory access as follows;
AM1
AM0
Start Mode
0
0
1
1
0
1
0
1
Don’t use this setting
Start with 16-bit data bus (note)
Don’t use this setting
Start with BOOT(32-bit internal-MROM )
Note: A memory to be used to start after releasing reset is either NOR-Flash or Masked-ROM.NAND-Flash,
SDRAM can’t be used.
AM1/AM0 pins are valid only just after releasing reset. In other cases, the data bus width
is the value set in the control register <BnBUS 1:0>.
After reset, only control register (B2CSH/B2CSL) of the block address area 2 is effective
automatically. (B2CSH<B2E> is set to “1” by reset).
The data bus width which is specified by AM1/AM0 pin is loaded to the bit to specify the
bus width of the control register in the block address area 2.
The block address area 2 is set to address 000000H to FFFFFFH by reset
(B2CSH<B2M> is reset to “0”) .
After releasing reset, the block address areas are specified by MSARn and MAMRn.
Then, set BnCS.
Set BnCSH<BnE> to “1” in order to enable the setting.
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3.8.3 Basic functions and register setting
In this section, setting of the block address area, the connecting memory and the number
of waits out of the memory controller’s functions are described.
(1) Block address area specification
The block address areas of CS0 to CS3 are specified by MSAR0 to MSAR3 and MAMR0 to
MAMR3.
(a) Memory start address register
Figure 3.8.1 shows the memory start address registers. MSAR0 to MSAR3 set the start
addresses for the CS0 to CS3 areas. Set the upper eight bits (A23 to A16) of the start
address in <S23:16>. The lower 16 bits of the start address (A15 to A0) are permanently set
to 0. Accordingly, the start address can only be set in 64-Kbyte increments, starting from
address register value.
Memory Start Address Registers (for areas CS0 to CS3)
7
6
5
4
3
2
1
0
MSAR0
(0143H) (0147H)
MSAR1
Bit symbol
Read/Write
After reset
Function
S23
S22
S21
S20
S19
S18
S17
S16
R/W
MSAR2 MSAR3
(014BH) (014FH)
1
1
1
1
1
1
1
1
Determines A23 to A16 of start address
Sets start addresses for areas CS0 to CS3
Figure 3.8.1 Memory Start Address Register
Start Address
Value in start address register (MSAR0 to MSAR3)
Address
000000H
000000H .................... 00H
64KByte
010000H .................... 01H
020000H .................... 02H
030000H .................... 03H
040000H .................... 04H
050000H .................... 05H
060000H .................... 06H
to
to
FF0000H ................... FFH
FFFFFFH
Figure 3.8.2 Relationship between Start Address and Start Address Register Value
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(b) Memory address mask registers
Figure 3.8.3 shows the memory address mask registers. MAMR0 to MAMR3 are used to
set the size of the CS0 to CS3 areas by specifying a mask for each bit of the start address set
in MAMR0 to MAMR3. The compare operation used to determine if an address is in the
CS0 to CS3 areas is only performed for bus address bits corresponding to bits set to 0 in
these registers.
Also, the address bits that can be masked by MAMR0 to MAMR3 differ between CS0 to
CS3 areas.
Block address area CS0 : A20 to A8
Block address area CS1 : A21 to A8
Block address area CS2 to CS3 : A22 to A15
Accordingly, the size that can be each area is different.
Note: After releasing reset, only the control register of the block address area 2 is valid. The control register of
the block address area 2 has <B2M> bit. Setting <B2M> bit to “0” sets the block address area 2 to
addresses 000000H to FFFFFFH. Setting <B2M> bit to “1” specifies the start address and the address
area size as it is in the other block address area.
Memory Address Mask Register ( for CS0 area)
7
6
5
4
3
2
1
0
MAMR0
(0142H)
Bit symbol
Read/Write
After reset
Function
V20
V19
V18
V17
V16
V15
V14∼9
V8
R/W
1
1
1
1
1
1
1
1
Sets size of CS0 area 0: Used for address compare
Range of possible settings for CS0 area size: 256Bytes to 2MBytes
Memory Address Mask Register ( for CS1 area)
7
6
5
4
3
2
1
0
MAMR1
(0146H)
Bit symbol
Read/Write
After reset
Function
V21
V20
V19
V18
V17
V16
V15∼9
V8
R/W
1
1
1
1
1
1
1
1
Sets size of CS1 area 0: Used for address compare
Range of possible settings for CS1 area size: 256Bytes to 4MBytes
Memory Address Mask Register ( for CS2,CS3 area)
7
6
5
4
3
2
1
0
MAMR2 MSAR3
(014AH) (014FH)
Bit symbol
Read/Write
After reset
Function
V22
V21
V20
V19
V18
V17
V16
V15
R/W
1
1
1
1
1
1
1
1
Sets size of CS2 or CS3 area 0: Used for address compare
Range of possible settings for CS2 or CS3 area size: 32KBytes to 8MBytes
Figure 3.8.3 Memory Address Mask Registers
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(c) Setting memory start addresses and address areas
An example of specifying a 64-Kbyte address area starting from 010000H using the CS0
areas i describes.
Set 01H in MSAR0<S23:16> (Corresponding to the upper 8 bits of the start address).
Next, calculate the difference between the start address and the anticipated end address
(01FFFFH) based on the size of the CS0 area. Bits 20 to 8 of the result correspond to the
mask value to be set for the CS0 area. Setting this value in MAMR0<V20:8> sets the area
size. This example sets 07H in MAMR0 to specify a 64K-byte area.
Memory
end
address
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
F
F
F
F
H
CS0 area
size
(64 Kbytes)
S23 S22 S21 S20 S19 S18 S17 S16
Memory
start
address
MSAR0
MSMR0
0
0
0
0
0
0
0
1
0
1
H
V20 V19 V18 V17 V16 V15
V14 to V9
V8
Memory address
mask register
setting
7
0
H
Setting of 07H specifies a 64-Kbyte area.
(d) Address area size specification
that cannot be set by memory start address register and address mask register
combinations. When setting an area size using a combination indicated by “Δ”, set the start
address mask register in the desired steps starting from 000000H.
If the CS2 area is set to 16 Mbytes or if two or more areas overlap, the smaller CS area
number has the higher priority.
Example: To set the area size for CS0 to 128 Kbytes:
a. Valid start addresses
000000H
128 Kbytes
020000H
128 Kbytes
128 Kbytes
Any of these addresses may be set as the start address.
040000H
060000H
:
b. Invalid start addresses
000000H
64 Kbytes
010000H
This is not an integer multiple of the desired area size setting.
Hence, none of these addresses can be set as the start address.
128 Kbytes
030000H
128 Kbytes
050000H
:
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Table 3.8.3 Valid Area Sizes for Each CS Area
Size
(Byte)
256
512
32 K
64 K
128 K
256 K
512 K
1 M
2 M
4 M
8 M
CS area
CS0
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
○
○
○
○
○
○
○
○
○
CS1
CS2
CS3
Δ
Δ
Δ
Δ
Δ
○
○
Note:“Δ” indicates areas that cannot be set by memory start address register and address mask
register combinations.
(e) Block address area Priority
When the set block address area overlaps with the built-in memory area, or both two
address areas overlap, the block address area is processed according to priority as follows.
Built-in I/O > Built-in memory > Block address area 0 > 1 > 2 > 3
(f) Wait control for outside the block address area of CS0 to CS3
Also, that any accessed areas outside the address spaces set by CS0 to CS3 are processed
as the CSEX space. Therefore, settings of CSEX (BEXCSH, L-register) apply for the control
of wait cycles, data bus width, etc,.
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(2) Connection Memory Specification
Setting BnCSH<BnOM1:0> specifies the memory type to be connected with the block
address areas. The interface signal is output according to the set memory as follows;
BnCSH<BnOM1:0>
BnOM1
BnOM0
Function
0
0
1
1
0
1
0
1
SRAM/ROM (Default)
(Reserved)
(Reserved)
SDRAM
Note1: SDRAM should be set only with CS1 or CS2 .
(3) Data Bus Width Specification
The data bus width is set for every block address area. The bus size is set by
BnCSH<BnBUS1:0> as follows;
BnCSH<BnBUS1:0>
<BnBUS1> <BnBUS0>
Function
0
0
1
1
0
1
0
1
8-bit bus mode (Default)
16-bit bus mode
Reserved
Don’t use this setting
Note1: SDRAM should be set to “01”(16-bit bus).
This way of changing the data bus width depending on the address being accessed is
called “dynamic bus sizing”. The part where the data is output to is depended on the data
width, the bus width and the start address.
The number of external data bus pin in TMP92CZ26A are 16 pin. Therefore, please
ignore the bus width of memory = 32 bit in the table.
Note: Since there is a possibility of abnormal writing/reading of the data if two memories with different bus
width are put in consecutive address, do not execute a access to both memories with one command.
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Operand Start
Bus width of Memory
(bit)
CPU Data
D31 to D24 D23 to D16 D15 to D8
Operand Data
Size (bit)
CPU Address
Address
D7 to D0
4n + 0
8/16/32
8
4n + 0
4n + 1
4n + 1
4n + 2
4n + 2
4n + 3
4n + 3
4n + 3
(1) 4n + 0
(2) 4n + 1
4n + 0
(1) 4n + 1
(2) 4n + 2
(1) 4n + 1
(2) 4n + 2
4n + 1
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b15 to b8
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b15 to b8
xxxxx
xxxxx
xxxxx
b7 to b0
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
b7 to b0
xxxxx
4n + 1
16/32
8/16
32
b7 to b0
xxxxx
b7 to b0
xxxxx
4n + 2
8
xxxxx
8
xxxxx
b7 to b0
xxxxx
4n + 3
16
b7 to b0
xxxxx
32
xxxxx
xxxxx
b7 to b0
b15 to b8
b7 to b0
b7 to b0
b15 to b8
xxxxx
8
16/32
8
4n + 0
xxxxx
b15 to b8
xxxxx
xxxxx
4n + 1
b7 to b0
xxxxx
16
32
8
b15 to b8
xxxxx
b7 to b0
xxxxx
(1) 4n + 2
(2) 4n + 1
4n + 2
b7 to b0
b15 to b8
b7 to b0
xxxxx
16
xxxxx
4n + 2
16
32
b15 to b8
xxxxx
4n + 2
(1) 4n + 3
(2) 4n + 4
(1) 4n + 3
(2) 4n + 4
(1) 4n + 3
(2) 4n + 4
(1) 4n + 0
(2) 4n + 1
(3) 4n + 2
(4) 4n + 3
(1) 4n + 0
(2) 4n + 2
4n + 0
(1) 4n + 0
(2) 4n + 1
(3) 4n + 2
(4) 4n + 3
(1) 4n + 1
(2) 4n + 2
(3) 4n + 4
(1) 4n + 1
(2) 4n + 4
(1) 4n + 2
(2) 4n + 3
(3) 4n + 4
(4) 4n + 5
(1) 4n + 2
(2) 4n + 4
(1) 4n + 2
(2) 4n + 4
(1) 4n + 3
(2) 4n + 4
(3) 4n + 5
(4) 4n + 6
(1) 4n + 3
(2) 4n + 4
(3) 4n + 6
(1) 4n + 3
(2) 4n + 4
xxxxx
b7 to b0
b15 to b8
xxxxx
8
xxxxx
b7 to b0
xxxxx
4n + 3
16
32
b15 to b8
xxxxx
xxxxx
xxxxx
b15 to b8
b7 to b0
b15 to b8
b23 to b16
b31 to b24
b7 to b0
xxxxx
xxxxx
8
xxxxx
4n + 0
xxxxx
b15 to b8
16
32
b31 to b24 b23 to b16
b31 to b24 b23 to b16 b15 to b8
b7 to b0
b7 to b0
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b15 to b8
b23 to b16
b31 to b24
xxxxx
8
xxxxx
xxxxx
4n + 1
4n + 2
4n + 3
b7 to b0
16
32
b23 to b16 b15 to b8
xxxxx
b7 to b0
xxxxx
b31 to b24
xxxxx
b23 to b16 b15 to b8
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b15 to b8
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b7 to b0
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
xxxxx
b31 to b24
b7 to b0
xxxxx
32
xxxxx
b15 to b8
b23 to b16
b31 to b24
b7 to b0
8
xxxxx
xxxxx
b15 to b8
16
32
b31 to b24 b23 to b16
xxxxx xxxxx
b31 to b24 b23 to b16
xxxxx
xxxxx
b7 to b0
b15 to b8
b23 to b16
b31 to b24
xxxxx
8
xxxxx
xxxxx
b7 to b0
16
32
b23 to b16 b15 to b8
xxxxx
xxxxx
b31 to b24
xxxxx
b31 to b24 b23 to b16 b15 to b8
xxxxx: During read, input data to the bus is ignored. At write, the bus is high impedance and the write
strobe signal remains no-active.
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(4) Wait control
The external bus cycle completes for two states minimum(25 ns at fSYS = 80 MHz).
Setting the BnCSL<BnWW3:0> specifies the number of waits in the write cycle, and
BnCSL<BnWR3:0> specifies the number of waits in the read cycle. <BnWW3:0> is set with
the same method as <BnWR3:0> as follows;
BnCSL<BnWW>/<BnWR>
<BnWW3>
<BnWR3>
<BnWW2>
<BnWR2>
<BnWW1>
<BnWR1>
<BnWW0>
<BnWR0>
Function
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2 states (0 waits) access fixed mode
3 states (1 wait) access fixed mode (Default)
4 states (2 waits) access fixed mode
5 states (3 waits) access fixed mode
6 states (4 waits) access fixed mode
7 states (5 waits) access fixed mode
8 states (6 waits) access fixed mode
9 states (7 waits) access fixed mode
10 states (8 waits) access fixed mode
11 states (9 waits) access fixed mode
12 states (10 waits) access fixed mode
14 states (12 waits) access fixed mode
18 states (16 waits) access fixed mode
22 states (20 waits) access fixed mode
6 states + WAIT pin input mode
others
(Reserved)
Note 1:For SDRAM, above setting is ineffective. Refer to the section 3.18 SDRAM controller.
Note 2:For NAND flash, this setting is ineffective.
(i) Waits number fixed mode
The bus cycle is completed with the set states. The number of states is selected from 2
states (0 waits) to 12 states (10 waits), 14 states(12 waits), 18 states(16 waits) and 22
states(20 waits).
WAIT
(ii)
pin input mode
WAIT
WAIT
pin state
This mode samples the
input pins. It continuously samples the
and inserts a wait if the pin is active. The bus cycle is minimum 6 states. The bus cycle is
completed when the wait signal is non active (“High” level) at 6 states. The bus cycle is
extended as long as the wait signal is active in case more than 6 states.
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(5) Recovery (Data hold) cycle control
CE
OE
for read
Some memory have an AC specification about data hold time from
or
cycle and a data confliction problem may occur. To avoid this problem, 1-dummy cycle can
be inserted after CSm-block access cycle by setting “1” to BmCSH<BmREC> register.
This 1-dummy cycle is inserted when the next cycle is for another CS-block.
BnCSH<BnREC>
0
1
No dummy cycle is inserted (Default).
Dummy cycle is inserted.
When not inserting a dummy cycle (0 waits)
SDCLK
A23 to A0
CSm
CSn
RD
When inserting a dummy cycle (0 waits)
Dummy
SDCLK
A23 to A0
CSm
CSn
RD
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(6) Adjust Function for the timing of control signal
This function can change the timing of CSn ,CSZx , CSXx ,R/ W , RD , WRxx , SRWR andSRxxB
signals and adjust the timing according to the set-up/hold time of the memories.
As for the CSn ,CSZx , CSXx ,R/ W and WRxx , SRWR , SRxxB (at write cycle), it can be changed
for only 1 CS area. While for RD and SRxxB (at read cycle), it can be changed for all CS
areas. As for CS area and EX area which is not set this function, it operates with base bus
timing (Refer to (7)).
This can not be used together with BnCSH<BnREC> function.
For control signal of SDRAM, it can be adjusted in SDRAM controller.
CSTMGCR<TxxSEL1:0>, WRTMGCR<TxxSEL1:0>
00
01
10
11
Change the timing of CS0 area
Change the timing of CS1 area
Change the timing of CS2 area
Change the timing of CS3 area
CSTMGCR<TAC1:0>
00
01
10
11
TAC = 0 × fSYS (Default)
TAC = 1 × fSYS
TAC = 2 × fSYS
(Reserved)
TAC:The delay from (A23-0) to (CSn, CSZx, CSXx, R/W).
WRTMGCR<TCWS/H1:0>
00
01
10
11
TCWS/H = 0.5 × fSYS (Default)
TCWS/H = 1.5 × fSYS
TCWS/H = 2.5 × fSYS
TCWS/H = 3.5 × fSYS
TCWS:The delay from (CSn) to (WRxx,SRWR,SRxxB).
TCWH:The delay from (WRxx,SRWR,SRxxB) to (CSn).
RDTMGCR0/1<BnTCRH1:0>
00
01
10
11
TCRH = 0 × fSYS (Default)
TCRH = 1 × fSYS
TCRH = 2 × fSYS
TCRH = 3 × fSYS
TCRH:The delay from (RD,SRxxB) to (CSn).
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RDTMGCR0/1<BnTCRS1:0>
00
01
10
11
TCRS = 0.5 × fSYS (Default)
TCRS = 1.5 × fSYS
TCRS = 2.5 × fSYS
TCRS = 3.5 × fSYS
TCRS:The delay from (CSn) to (RD,SRxxB).
TW
T2
T3
Tn-2
Tn-1
Tn
T1
SDCLK
(80MHz)
A23 to 0
CSn
R/ W
TAC
TAC
RD
TCRS
Read
cycle
SRxxB
TCRH
D15 to 0
Input
WRxx
SRWR
SRxxB
D15 to 0
Write
cycle
TCWH
Output
TCWS
TCWS
Output
Note: TW cycle is inserted by setting BnCSL register. If it is set to 0-Wait, TW cycle is not inserted.
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(7) Basic bus timing
(a) External read/write cycle (0 waits)
T1
T2
SDCLK
(60 MHz)
CSn
A23 to A0
RD , SRxxB
D15 to D0
Read
Write
Input
SRWR , SRxxB
WRxx
D15 to D0
Output
(b) External read/write cycle (1 wait)
T1
TW
T2
SDCLK
(60 MHz)
CSn
A23 to A0
RD , SRxxB
D15 to D0
Read
Write
Input
SRWR , SRxxB
WRxx
D15 to D0
Output
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(c) External read bus cycle (1 wait + TAC: 1fSYS + TCRS: 1.5fSYS + TCRH: 1fSYS
External write bus cycle (1 wait + TAC: 1fSYS + TCWS/H: 1.5fSYS
)
)
T6
T1
T2
T3
T4
T5
SDCLK
(80 MHz)
CSn
TAC
TAC
A23 to 0
RD SRxxB
D15 to 0
TCRS
TCRH
Read
Write
Input
SRWR , SRxxB
WRxx
TCWS
TCWS
TCWH
TCWH
D15 to 0
WAIT
Output
WAIT
(d) External read/write cycle (4 waits +
pin input mode)
T6
T1
T2
T3
T4
T5
SDCLK
(80 MHz)
CSn
A23 to 0
RD SRxxB
D15 to 0
Read
Write
Input
SRWR , SRxxB
WRxx
D15 to 0
WAIT
Output
Sampling
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WAIT
(e) External read/write cycle (4 waits +
pin input mode)
T6
T1
T2
T3
T4
T5
TW
SDCLK
(80 MHz)
CSn
A23 to 0
RD SRxxB
D15 to 0
Read
Input
SRWR , SRxxB
WRxx
Write
D15 to 0
WAIT
Output
Sampling
Sampling
WAIT
WAIT
(f) External read bus cycle (4 waits +
pin input mode +TAC: 1fSYS + TCRS: 1.5fSYS
+ TCRH: 1fSYS
)
External write bus cycle (4 waits +
pin input mode + TAC: 1fSYS
+ TCWS/H: 1.5fSYS
)
T10
T8
T9
T1
T2
T3
TW
T4∼T7
SDCLK
(80 MHz)
CSn
A23 to 0
RD SRxxB
D15 to 0
Read
Input
SRWR , SRxxB
WRxx
Write
TCWS
TCWS
D15 to 0
WAIT
Output
Sampling
Sampling
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(8) Connecting to external memory
Figure 3.8.4 shows an example of how to connect external 16-bit SRAM and 16-bit NOR
flash to the TMP92CZ26A.
TMP92CZ26A
RD
16-bit SRAM
OE
SRLLB
SRLUB
LDS
UDS
SRWR
CS0
R/W
CE
D [15:0]
A0
I/O [16:1]
Not connect
A1
A0
A1
A2
A2
A3
16-bit NOR flash
OE
WE
CE
CS2
DQ [15:0]
A0
A1
A2
Figure 3.8.4 Example of External 16-Bit SRAM and NOR Flash Connection
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3.8.4 ROM Page mode Access Control
This section describes ROM page mode accessing and how to set registers. ROM page mode
is set by PMEMCR.
(1)
Operation and how to set the registers
TMP92CZ26A supports ROM access with the page mode. The ROM access with the page
mode is specified only in CS2.
Setting PMEMCR<OPGE> to “1” sets the memory access of CS2 to ROM page mode access.
The number of read cycles is set by the PMEMCR<OPWR1:0>.
PMEMCR<OPWR1:0>
<OPWR1> <OPWR0>
Number of Cycle in a Page
1 state (n-1-1-1 mode) (n ≥ 2)
2 state (n-2-2-2 mode) (n ≥ 3)
3 state (n-3-3-3 mode) (n ≥ 4)
4 state (n-4-4-4 mode) (n ≥ 5)
0
0
1
1
0
1
0
1
Note: Set the number of waits “n” to the control register (BnCSL) in each block address area.
The page size (the number of bytes) of ROM in the CPU size is set to PMEMCR<PR1:0>.
When data is read out until a border of the set page, the controller completes the page reading
operation. The start data of the next page is read in the normal cycle. The following data is set
to page read again.
PMEMCR<PR1:0>
<PR1>
<PR0>
ROM Page Size
0
0
1
1
0
1
0
1
64 bytes
32 bytes
16 bytes (Default)
8 bytes
SDCLK
t
CYC
A2~A23
A0~A1
+0
+1
+2
+3
CS2
RD
t
t
HA
HR
t
t
t
t
AD2
AD3
AD2
AD2
t
t
t
t
HA
RD3
HA
HA
Input
Data
Input
Data
Input
Data
Input
Data
D0~D15
Figure 3.8.5 Page mode access Timing
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3.8.5 Internal Boot ROM Control
This section describes about built-in boot ROM.
For the specification of S/W in boot ROM, refer to the section 3.4 boot ROM.
(1) BOOT mode
BOOT mode is started by following AM1 and AM0 pins condition with reset.
AM1
AM0
Start mode
0
0
1
1
0
1
0
1
Don’t use this setting
Start with 16-bit data bus
Don’t use this setting
Start with boot (32-bit internal MROM)
(2) Boot ROM memory map
Boot ROM is consist of 8-Kbyte masked ROM and assigned 3FE000H to 3FFFFFH
address.
000000H
04A000H
Internal I/O , RAM
3FE000H
Internal boot ROM
(8 Kbytes)
3FFF00H
400000H
(B) Reset/Interrupt
Vector area
(256 bytes)
FFFF00H
(A) Reset/Interrupt
Vector area
(256 bytes)
(3) Reset/interrupt address conversion circuit
Originally, reset/interrupt vector area is assigned FFFF00H to FFFFEFH ((A) area) in
TLCS-900/H1.
But because boot ROM is assigned to another area, reset/interrupt vector address
conversion circuit is prepared.
In BOOT mode, reset/interrupt vector area is assigned 3FFF00H to 3FFFEFH ((B) area)
area by it. And after boot sequence, its area can be changed to (A) area by setting
BROMCR<VACE> to “0”. So, (A) area can be used only for application system program.
This BROMCR<VACE> is initialized to “1” in BOOT mode. At another starting mode,
this register has no meaning.
Note: The last 16-byte area (FFFFF0H to FFFFFFH) is reserved for an emulator. So, this area is not changed
by <VACE> register.
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(4) Disappearing boot ROM
After boot sequence in BOOT mode, an application system program may continue to run
without reset asserting. In this case, an external memory which is mapped 3FE000H to
3FFFFFH address can not be accessed because of boot ROM is assigned.
To solve it, internal boot ROM can be disappered by setting BROMCR<ROMLESS> to
“1”.
This <ROMLESS> is initialized to “0” in BOOT mode. At another starting mode, this bit
is initialized to “1”.
If this bit has been set to “1”, writing “0” is disabled.
7
6
5
4
3
2
1
0
BROMCR Bit symbol
CSDIS
ROMLESS
R/W
VACE
(016CH)
Read/Write
After Reset
Function
1
0/1 (note)
1/0 (note)
Vector
Nand_Flash Boot ROM
area
0: use
address
CS output
0: Enable
1: Disable
1: not use
conversion
0: Disable
1: Enable
Note: The value after reset release is depending on start mode.
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3.8.6 Cautions
CS
RD
and
(1) Note the timing between
CS
(Chip
RD
If the load capacitance of the
(Read signal) is greater than that of the
select signal), it is possible that an unintended read cycle occurs due to a delay in the read
signal. Such an unintended read cycle may cause a trouble as in the case of (a) in Figure
SDCLK
(60 MHz)
A23 to A0
CSm
CSn
RD
(a)
Figure 3.8.6 Read Signal Delay Read Cycle
Example: When using an externally connected NOR flash which users JEDEC standard
commands, note that the toggle bit may not be read out correctly. If the read signal in the
cycle immediately preceding the access to the NOR flash does not go high in time, as
Toggle bit RD cycle
Memory access
SDCLK
(60 MHz)
A23 to A0
NOR flash
chip select
RD
Toggle bit
(b)
Figure 3.8.7 NOR Flash Toggle Bit Read Cycle
When the toggle bit reverse with this unexpected read cycle, CPU always reads same
value of the toggle bit, and cannot read the toggle bit correctly.
To avoid this phenomenon, the data polling function control is recommended. Or use the
RD
adjust timing function for rising edge of
generating this phenomenon.
(RDTMGCRn<BnTCRH1:0>) in order to avoid
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(2) Note the NAND flash area setting
And since CS3 area is recommended to assign address from 000000H to 3FFFFFH, this
case is explained.
CS3
In this case, “NAND flash” and CS3 area are overlapped. But
pin don’t become
CS0
CS3 SDCS CSXA
CSXB
to
active by setting BROMCR<CSDIS> to “1”. And also
to
,
,
,
CSZA
CSZD
pins don’t become to active.
to
Note1: In this case, the address from 000000H to 049FFFH of 296 Kbytes in CS3’s memory can’t be used.
Note2: 16 byte area (001FF0H to 001FFFH) for NAND Flash are fixed like a following without relationship to
setting CS bock. Therefore, NAND flash area don’t according to CS3 area setting.
(NAND-Flash area specification)
1. bus width
: Depend on NDFMCR1<BUSW> in NAND Flash controller.
: Depend on NDFMCR<SPLW1:0>,<SPHW1:0> in NAND Flash controller
2.WAIT control
000000H
001FF0H
Internal I/O
NAND flash
(16 bytes)
All CS pins become to unactibe
by BROMCR<CSDIS> =”1”
002000H
Internal RAM
(288 Kbytes)
04A000H
COMMON X
(2 Mbytes)
CS3 area setting
000000H to 3FFFFFH (4 Mbytes)
200000H
400000H
LOCAL X
(2 Mbytes)
Figure 3.8.8 Recommended CS3 setting
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3.9 External Memory Extension Function (MMU)
This is MMU function which can expand program/data area to 3.1G bytes by having 4-type
local area.
The recommendation address memory map is shown in Figure 3.9.1.
However, when total capacity of used memory is less than 16M bytes, please refer to section of
Memory controller. Setting of register in MMU is not necessary.
An area which can be set as BANK is called LOCAL-area. Since the address for LOCAL area
is fixed, it cannot be changed.
And, area that cannot be set as BANK is called COMMON-area.
Basically one series of program should be closed within one bank. Please don’t jump to the
same LOCAL-area in the different bank directly by JP instruction and so on. Refer to the
examples as follows.
TMP92CZ26A has following external pins to connect external memory-LSI.
Address bus
Chip Select
: EA28, EA27, EA26, EA25, EA24 and A23 to A0
: CS0 toCS3 , CSXA toCSXB , CSZA toCSXD, SDCS ,
ND0CE and ND1CE
Data bus
: D15 to D0
3.9.1 Recommended memory map
Figure 3.9.1 shows one of recommendation address memory map. It can be expanded to
maximum memory size.
Figure 3.9.3 also shows one of recommendation address memory map. It’s for a simple
memory system like internal Boot-ROM with NAND-Flash and SDRAM.
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Memory controller
setting
pin (512MB)
ND0CE
Address memory map
000000H
ND1CE pin (512MB)
Internal I/O, RAM
CSXA
CSXB
COMMON-X
(2MB)
512MB(2MB×256)
512MB(2MB×256)
CS3-area
4MB
200000H
LOCAL-X
(2MB)
・・・
255 256 ・・
511
Bank 0
Bank 0
1
1
2
2
3
3
・・・ 15
400000H
600000H
LOCAL-Y
(2MB)
・・・
63
・・・ 15
CS1-area
4MB
SDCS : 64MB*(SDRAM case 2MB×32) or CS1 pin: 128MB (2MB×64)
COMMON-Y
(2MB)
800000H
LOCAL-Z
(4MB)
3
Bank 0
1
2
・・・ 127 128 ・・・ 255 ・・・ 384 ・・・ 511
CS2-area
8MB
C00000H
COMMON-Z
(4MB)
CSZA pin (Note)
・・・
CSZB pin
pin
CSZD
512MB(4MB×128)
: Internal area
FFFF00H
FFFFFFH
Vector area
: Overlapped with COMMON-Area and disabled setting as LOCAL-area.
Note1: CSZA is a chip-select for not only bank0 to 127 of LOCAL-Z but also COMMON-Z.
Note2:In case of connect SDRAM to Y-area, 64MB(2MB×32) is maximum
Figure 3.9.1Recommendation memory map for maximum specification (Logical address)
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LOCAL-X
LOCAL-Y
LOCAL-Z
92CZ26A
SDCS or CS1
128MB or
*64MB
CSXA to CSXB ,
EA24 to 28
CSZA to CSZD ,
EA24 to 28
512MB×2=1024MB
512MB×4=2048MB
CSXA
CSZA
CSZD
000000H
Bank0
Bank0
Bank384
Bank0
Internal-I/O and
Internal RAM
63
511
127
255
CSXB
CSZB
Bank256
Bank128
255
511
CSZC
Bank256
383
Note: In case of connect SDRAM to Y-area, 64MB(2MB×32) is maximum
Figure 3.9.2 Recommendation memory map for maximum specification (Physical address)
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Memory controller
setting
pin (512MB)
pin (512MB)
ND0CE
ND1CE
Address memory map
000000H
Internal-I/O, RAM
COMMON-X
(2MB)
200000H
LOCAL-X
(2MB)
Internal Boot-ROM (8KB)
3FE000H
400000H
LOCAL-Y
(2MB)
600000H
800000H
COMMON-Y
(2MB)
LOCAL-Z
(4MB)
Bank 0
1
2
3
・・・ 15
CS2-area
8MB
C00000H
COMMON-Z
(4MB)
SDCS pin
64MB(4MB×16)
FFFF00H
FFFFFFH
Vector area
:Internal area
: Overlapped with COMMON-Area and disabled setting as LOCAL-area.
Note: In case of connect SDRAM to Z-area, 64MB (4MB×16) is maximum
Figure 3.9.3Recommendation memory map for simple system (Logical address)
LOCAL-Z
92CZ26A
SDCS
4MB×16=64MB
SDCS
000000H
Bank 0
Internal-I/O
and RAM
3FE000H
Internal Boot-ROM
15
Note: In case of connect SDRAM to Z-area, 64MB(4MB×16) is maximum
Figure 3.9.4 Recommendation memory map for simple system (Physical address)
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3.9.2 Control register
There are 24-registers for MMU. They are prepared for 8-purpose using (as Program,
read-data, write-data and LCDC-display-data, source-data for odd/even number channel DMA,
destination-data for odd/even number channel DMA), and 3-local area (LOCAL-X, Y and Z).
These 8-purpose registers can access a data accessed easily.
(How to use)
At first, set enable register and using bank-number of each LOCAL register. In that case,
set a combination pin and memory setting to the Ports and Memory controller. After that, if
CPU or LCDC access to logical address of the local area, MMU converts logical address to
physical address according to the bank number, and output it. The physical address is
output to the external address bus pin. By this operation, accessing to external memory
becomes possible. And, if accessed same logical address, physical address is changed by
bank that be set to register in program, and enable accessing that memory of other bank.
Note:
1) When set the bank page, it inhibit to set overlapped area with common area ( because Local area
and common area shows same physical address)
2) In the LOCAL-area, changing Program bank number (LOCALPX, Y or Z) is disabled. Program bank
setting of each local area must change in common area. (But bank setting of data-Read, data-Write
and LCDC-display data can change also in local area.)
3) After data bank number (LOCALRn, LOCALWn or LOCALLn, LOCALEDn, LOCALSn, LOCALODn;
“n” means X, Y or Z) register is set by an instruction, don’t access its memory by next instruction
because of some clocks are needed to be effective MMU setting. In this case, insert dummy
instruction which accesses SFR or another memory between them like following example.
(Example)
ld
xix, 200000h
;
ldw
(localrx), 8001h
; read-data bank number is set
ldw
ldw
wa, (localrx)
wa, (xix)
; <---- Inserted Dummy instruction which accesses SFR
; instruction which reads bank1 of local-X area.
4) When LOCAL-Z area is used, Chip select signal CSZA should be assigned to P82-pin.
In this case, CSZA works as chip select signal for not only bank0 to 15 but also COMMON-Z.
But for it, following setting after reset is needed before P82 setting.
ldw
ldw
ldw
ldw
(localpz), 8000h ; LOCAL-Z Bank enable for program
(localrz), 8000h ; LOCAL-Z Bank enable for data read
(localwz), 8000h ; LOCAL-Z Bank enable for data write
(locallz), 8000h ; LOCAL-Z Bank enable for LCD display memory (*2)
(p8fc), -----0--B ; Assign P82 to CSZA
(p8fc2), -----1--B
(*1)
ld
ld
;
(*1) If COMMON-Z area is not used as data write memory, this setting is not needed.
(*2) If COMMON-Z area is not used as LCD display memory, this setting is not needed.
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3.9.2.1
Program bank register
The bank number used as program memory is set to these registers. In certain bank, cannot
diverge directly to different bank of same local area. To change program bank number in the
same local area is disable.
LOCAL-X register for Program
7
6
5
4
3
2
1
0
LOCALPX
(880H)
bit Symbol
Read/Write
After reset
X7
X6
X5
X4
X3
X2
X1
X0
R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X
(“0” is disabled because of overlapped with Common-area.)
Function
15
14
13
12
11
10
9
8
X8
R/W
0
(881H)
bit Symbol
Read/Write
After reset
LXE
R/W
0
BANK for
LOCALX
0: Disable
1: Enable
Set BANK number for LOCAL-X
X8-X0 setting and CS
Function
000000000 to 011111111 CSXA
100000000 to 111111111 CSXB
LOCAL-Y register for Program
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Y5
Y4
Y3
Y2
Y1
Y0
LOCALPY
(882H)
R/W
0
0
0
0
0
0
Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
Function
15
14
13
12
11
10
9
8
(883H)
bit Symbol
Read/Write
After reset
LYE
R/W
0
BANK for
LOCALY
0: Disable
1: Enable
Function
LOCAL-Z register for Program
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
LOCALPZ
(884H)
R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-Z
(“3” is disabled because of overlapped with Common-area.)
Function
15
LZE
R/W
14
13
12
11
10
9
8
Z8
(885H)
bit Symbol
Read/Write
R/W
After reset
0
0
BANK for
LOCALZ
0: Disable
1: Enable
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
Function
000000000 to 001111111 CSZA
010000000 to 011111111 CSZB
100000000 to 101111111 CSZC
110000000 to 111111111 CSZD
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3.9.2.2
LCD display bank register
The bank page used as LCD display memory is set to these registers. Since the bank register
for CPU and LCDC are prepared independently, the bank page for CPU (Program, Read-data,
write-data) can change during LCD display on.
LOCAL-X register for LCD
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
X7
X6
X5
X4
X3
X2
X1
X0
LOCALLX
(888H)
R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
15
14
13
12
11
10
9
8
X8
R/W
0
(889H)
bit Symbol
Read/Write
After reset
LXE
R/W
0
BANK for
LOCALX
0: Disable
1: Enable
Set BANK number for LOCAL-X
X8-X0 setting and CS
Function
000000000～011111111 CSXA
100000000～111111111 CSXB
LOCAL-Y register for LCD
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Y5
Y4
Y3
Y2
Y1
Y0
LOCALLY
(88AH)
R/W
0
0
0
0
0
0
Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
Function
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
LYE
R/W
(88BH)
0
BANK for
LOCALY
0: Disable
1: Enable
Function
LOCAL-Z register for LCD
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
LOCALLZ
(88CH)
R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)
15
14
13
12
11
10
9
8
Z8
bit Symbol
Read/Write
After reset
LZE
R/W
(88DH)
R/W
0
0
BANK for
LOCALZ
0: Disable
1: Enable
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
Function
000000000 to 001111111 CSZA
010000000 to 011111111 CSZB
100000000 to 101111111 CSZC
110000000 to 111111111 CSZD
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3.9.2.3
Read-data bank register
The bank number used as read-data memory is set to these registers. The following is an
example which read data bank register of LOCAL-X is set to “1”. When “ldw wa, (xix)”
instruction is executed, the bank becomes effective at only read data (operand) for xix address.
(Example)
ld
ld
ldw
ldw
xix, 200000h
(localrx), 8001h
wa,(localrx)
wa, (xix)
;
; Set Read data bank.
; <----Insert dummy instruction that access to SFR
; Read bank1 of LOCAL-X area
LOCAL-X register for read
7
6
5
4
3
2
1
0
bit Symbol
X7
X6
X5
X4
X3
X2
X1
X0
LOCALRX
(890H)
Read/Write
After reset
Function
R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
15
LXE
R/W
14
13
12
11
10
9
8
X8
R/W
0
bit Symbol
Read/Write
After reset
(891H)
0
BANK for
LOCALX
0: Disable
1: Enable
Set BANK number for LOCAL-X
X8-X0 setting and CS
Function
000000000 to 011111111 CSXA
100000000 to 111111111 CSXB
LOCAL-Y register for read
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Y5
Y4
Y3
Y2
Y1
Y0
LOCALRY
(892H)
R/W
0
0
0
0
0
0
Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
Function
15
LYE
R/W
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
(893H)
0
BANK for
LOCALY
0: Disable
1: Enable
Function
LOCAL-Z register for read
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
LOCALRZ
(894H)
R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)
15
LZE
R/W
14
13
12
11
10
9
8
Z8
bit Symbol
Read/Write
After reset
R/W
0
(895H)
0
BANK for
LOCALZ
0: Disable
1: Enable
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
Function
000000000 to 001111111 CSZA
010000000 to 011111111 CSZB
100000000 to 101111111 CSZC
110000000 to 111111111 CSZD
92CZ26A-211
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TMP92CZ26A
3.9.2.4
Write-data bank register
The bank number used as write data memory is set to these registers. The following is an
example which data bank register of LOCAL-X is set to “1”. When “ldw (xix), wa” instruction is
extended, the bank becomes effective at only cycle for xix address.
(Example)
ld
xix, 200000h
;
ld
(localwx), 8001h ; Set Write data bank.
ldw
ldw
wa, (localwx)
(xix), wa
; <----Insert dummy instruction that access to SFR
; Write to bank1 of LOCAL-X area
LOCAL-X register for write
7
6
5
4
3
2
1
0
bit Symbol
X7
X6
X5
X4
X3
X2
X1
X0
LOCALWX
(898H)
Read/Write
After reset
Function
R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
15
14
13
12
11
10
9
8
X8
R/W
0
bit Symbol
Read/Write
After reset
LXE
R/W
0
(899H)
BANK for
LOCALX
0: Disable
1: Enable
Set BANK number for LOCAL-X
X8-X0 setting and CS
Function
000000000 to 011111111 CSXA
100000000 to 111111111 CSXB
LOCAL-Y register for write
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Y5
Y4
Y3
Y2
Y1
Y0
LOCALWY
(89AH)
R/W
0
0
0
0
0
0
Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
Function
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
LYE
R/W
(89BH)
0
BANK for
LOCALY
0: Disable
1: Enable
Function
LOCAL-Z register for write
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
LOCALWZ
(89CH)
R/W
0
0
0
0
0
0
0
0
Function
Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
LZE
R/W
Z8
R/W
0
0
(89DH)
BANK for
LOCALZ
0: Disable
1: Enable
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
Function
000000000 to 001111111 CSZA
010000000 to 011111111 CSZB
100000000 to 101111111 CSZC
110000000 to 111111111 CSZD
92CZ26A-212
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TMP92CZ26A
3.9.2.5
DMA-function bank register
In addition to functioning as read/write function of CPU, this LSI can also function which
transfer data at high-speed by internal DMAC becoming bus master. (Please refer to DMAC
section)
In Bank for only DMA that different from Bank for CPU or LCDC display data, although
condition of program bank, read-bank and write-bank for CPU, bank of Source address and
Destination address are enable during operate DMA.
DMAC which assignment is possible in this LSI is 5-channel. But bank controller is 2-type.
Even-channel of DMA-channel 0, 2 and 4 become E-group (ES and ED group), odd-channel of
DMA-channel 1and 3 become O-group (OS and OD group). Assignment every channel is disable
in same group.
Following shows examples of setting bank for DMA_Source address to 1 in LOCALX area and
setting bank for DMA_Destination address to 2 in LOCALY area. If Source address which set to
XXX by using DMA function was set to LOCALX-area and Destination address was set to
LOCALY-area, when DMA of channel 0 is start, LOCALX bank1 is set to source and LOCALY
bank2 is set to destination.
(Example)
ldw
ldw
(localesx), 8001h ; Set DMA source bank for channel 0
(localedy), 8002h ; Set DMA destination bank for channel 0
DMA channel 0 start
92CZ26A-213
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TMP92CZ26A
LOCAL-X register for even-group DMA source
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
X7
X6
X5
X4
X3
X2
X1
X0
LOCALESX
(8A0H)
R/W
After reset
Function
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
15
LXE
R/W
14
13
12
11
10
9
8
X8
bit Symbol
Read/Write
R/W
(8A1H)
After reset
0
0
BANK for
LOCALX
Set BANK number for LOCAL-X
X8-X0 setting and CS
Function
0: Disable
1: Enable
000000000 to 011111111 CSXA
100000000 to 111111111 CSXB
LOCAL-Y register for even-group DMA source
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
Y5
Y4
Y3
Y2
Y1
Y0
LOCALESY
(8A2H)
R/W
After reset
Function
0
0
0
0
0
0
Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
15
LYE
R/W
14
13
12
11
10
9
8
bit Symbol
Read/Write
(8A3H)
After reset
0
BANK for
LOCALY
Function
0: Disable
1: Enable
LOCAL-Z register for even-group DMA source
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
LOCALESZ
(8A4H)
R/W
After reset
Function
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)
15
LZE
R/W
14
13
12
11
10
9
8
Z8
bit Symbol
Read/Write
R/W
(8A5H)
After reset
0
0
BANK for
LOCALZ
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
Function
0: Disable
1: Enable
000000000 to 001111111 CSZA
010000000 to 011111111 CSZB
100000000 to 101111111 CSZC
110000000 to 111111111 CSZD
92CZ26A-214
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TMP92CZ26A
LOCAL-X register for even-group DMA destination
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
X7
X6
X5
X4
X3
X2
X1
X0
LOCALEDX
(8A8H)
R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
LXE
R/W
X8
R/W
0
(8A9H)
0
BANK for
LOCALX
0: Disable
1: Enable
Set BANK number for LOCAL-X
X8-X0 setting and CS
Function
000000000 to 011111111 CSXA
100000000 to 111111111 CSXB
LOCAL-Y register for even-group DMA destination
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Y5
Y4
Y3
Y2
Y1
Y0
LOCALEDY
(8AAH)
R/W
0
0
0
0
0
0
Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
Function
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
LYE
R/W
(8ABH)
0
BANK for
LOCALY
0: Disable
1: Enable
Function
LOCAL-Z register for even-group DMA destination
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
LOCALEDZ
(8ACH)
R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)
15
14
13
12
11
10
9
8
Z8
bit Symbol
Read/Write
After reset
LZE
R/W
R/W
0
(8ADH)
0
BANK for
LOCALZ
0: Disable
1: Enable
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
Function
000000000 to 001111111 CSZA
010000000 to 011111111 CSZB
100000000 to 101111111 CSZC
110000000 to 111111111 CSZD
92CZ26A-215
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TMP92CZ26A
LOCAL-X register for odd-group DMA source
7
6
5
4
3
2
1
0
bit Symbol
X7
X6
X5
X4
X3
X2
X1
X0
LOCALOSX
(8B0H)
Read/Write
After reset
Function
R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
LXE
R/W
X8
R/W
0
(8B1H)
0
BANK for
LOCALX
0: Disable
1: Enable
Set BANK number for LOCAL-X
X8-X0 setting and CS
Function
000000000 to 011111111 CSXA
100000000 to 111111111 CSXB
LOCAL-Y register for odd-group DMA source
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Y5
Y4
Y3
Y2
Y1
Y0
LOCALOSY
(8B2H)
R/W
0
0
0
0
0
0
Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
Function
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
LYE
R/W
(8B3H)
0
BANK for
LOCALY
0: Disable
1: Enable
Function
LOCAL-Z register for odd-group DMA source
7
6
5
4
3
2
1
0
LOCALOSZ
(8B4H)
bit Symbol
Read/Write
After reset
Function
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
LZE
R/W
Z8
R/W
0
(8B5H)
0
BANK for
LOCALZ
0: Disable
1: Enable
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
Function
000000000 to 001111111 CSZA
010000000 to 011111111 CSZB
100000000 to 101111111 CSZC
110000000 to 111111111 CSZD
92CZ26A-216
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TMP92CZ26A
LOCAL-X register for odd-group DMA destination
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
X7
X6
X5
X4
X3
X2
X1
X0
LOCALODX
(8B8H)
R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
LXE
R/W
X8
R/W
0
(8B9H)
0
BANK for
LOCALX
0: Disable
1: Enable
Set BANK number for LOCAL-X
X8-X0 setting and CS
Function
000000000 to 011111111 CSXA
100000000 to 111111111 CSXB
LOCAL-Y register for odd-group DMA destination
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Y5
Y4
Y3
Y2
Y1
Y0
LOCALODY
(8BAH)
R/W
0
0
0
0
0
0
Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
Function
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
LYE
R/W
(8BBH)
0
BANK for
LOCALY
0: Disable
1: Enable
Function
LOCAL-Z register for odd-group DMA destination
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
LOCALODZ
(8BCH)
R/W
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)
15
14
13
12
11
10
9
8
Z8
bit Symbol
Read/Write
After reset
LZE
R/W
R/W
0
(8BDH)
0
BANK for
LOCALZ
0: Disable
1: Enable
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
Function
000000000 to 001111111 CSZA
010000000 to 011111111 CSZB
100000000 to 101111111 CSZC
110000000 to 111111111 CSZD
92CZ26A-217
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TMP92CZ26A
3.9.3 Setting example
This is in case of using like following condition.
No.
(a)
(b)
(c)
(d)
(e)
Used as
Memory
Setting
MMU-area
Logical
address
C00000H to
FFFFFFH
800000H to 000000H to
BFFFFFH
Physical
address
Main
Routine
Character-
ROM
Sub
Routine
LCD
NOR-Flash
(16MB, 1pcs)
COMMON-Z
CSZA ,
32bit,
1wait
Bank0 in
LOCAL-Z
Bank0 in
LOCAL-Y
Bank1 in
LOCAL-Y
Bank2 in
LOCAL-Y
3FFFFFH
SRAM
(16MB, 1pcs)
400000H to 000000H to
5FFFFFH
CS1 ,
16bit,
0wait
1FFFFFH
200000H to
3FFFFFH
Display-RAM
Stack-
Internal-RAM
(288KB)
----
(32bit,
002000H to
049FFFH
RAM
2-1-1-1clk)
(a) Main routine (COMMON-Z)
Logical
Physical
Address
No
Instruction
Comment
Address
1
2
org C00000H
;
C00000H
C000xxH
<-(Same)
<-
ldw (mamr2),80FFH
ldw (b2csl), C222H
ldw (mamr1),40FFH
ldw (b1csl), 8111H
ldw (localpz),8000H
ldw (localrz),8000H
; CS2 800000-ffffff/8MB
3
; CS2 32bit ROM, 1wait
; CS1 400000-7fffff/4MB
; CS1 16bit RAM, 0wait
4
5
5.1
5.2
6
; Enable LOCAL-Z Bank for program
; Enable LOCAL-Z Bank for read-data
ld
(p8fc), 02H
(p8fc2), 04H
xsp,48000H
(localpy),8000H
;
7
ld
;
9
ld
; Stack Pointer = 48000H
10
ldw
; Bank0 in LOCAL-Y is set as Program bank
for sub routine
11
12
13
14
15
:
;
C000yyH
<-
call 400000H
; Call Sub routine
:
:
:
;
;
;
・
・
・
・
From No.2 to No.8 instructions are setting of Ports and Memory controller.
No.9 is a setting for stack pointer. It is assigned to internal-RAM.
No.10 is a setting to execute for No.12’s instruction.
No.12 is an instruction to call sub routine. When CPU outputs 400000H address, MMU will convert and output 000000H
physical address to external address bus: A23 to A0. And
for SRAM will be asserted because of logical address is
CS1
in an area for CS1 at the same time. By these instructions, CPU cans brunch to sub-routine.
(Note: This example is based on sub routine program is already written on SRAM.)
92CZ26A-218
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TMP92CZ26A
(b) Sub routine (Bank-0 in LOCAL-Y)
Logical
Physical
address
No
Instruction
Comment
address
16
17
org 400000H
;
400000H
4000xxH
000000H
0000xxH
ldw
(localwy),8001H
; Bank1 in LOCAL-Y is set to write-data for LCD
Display RAM
; Bank1 in LOCAL-Y is set as LCD display RAM
18
19
ldw
ldw
(locally), 8001H
(localrz), 8001H
; Bank0 in LOCAL-Z is set as read-data
for Character-RAM
20
ld
xiy,800000H
wa,(xiy)
; Index address register for read
Character-ROM
; Read Character-ROM
21
22
ld
:
; Convert it to display-data
;
23
24
ld
ld
(localpy), 82H
xix, 400000H
; Index address register for write LCD
Display data
25
26
27
28
29
30
31
32
ld
:
:
ld
ld
ld
:
(xix), bc
; Write LCD Display data
; Set LCD Controller
;
; Set LCD Start address to LCDC
;
; Start LCD Display operation
;
;
xiz, 400000H
(lsarcl), xiz
(lcdctl0),01H
5000yyH
1000yyH
ret
・No.17 and No.18 are setting for Bank-1 of LOCAL-Y. In this case, LCD Display data is written to SRAM by CPU.
So, (LOCALWY) and (LOCALLY) should be set to same bank-1.
・No.19 is a setting for Bank-0 of LOCAL-Z to read data from character-ROM.
・No.20 and No.21 are instructions to read data from character-ROM. When CPU outputs 800000H address, this MMU will
convert and output 000000H address to external address bus: A23 to A0. And /CSZA for NOR-Flash will be asserted
because of logical address is in an area for CS2 at the same time.
By these instructions, CPU can read data from character ROM.
・No.23 is an instruction which changes Program bank number in the LOCAL-area. This setting is disabled.
・No.24 and No.25 are instructions to write data to SRAM. When CPU outputs 400000H address, this MMU will convert and
output 200000H address to external address bus: A23 to A0. And /CS1 for SRAM will be asserted because of logical
address is in an area for CS1 at the same time.
By these instructions, CPU can write data to SRAM.
・No.28 and No.29 are setting to set LCD starting address to LCD Controller. When LCDC outputs 400000H address in
DMA-cycle, this MMU will convert and output 200000H address to external address bus: A23 to A0. And /CS1 for SRAM
will be asserted because of logical address is in an area for CS1 at the same time.
By these instructions, LCDC can read data from SRAM.
・No.30 is an instruction to start LCD display operation.
92CZ26A-219
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TMP92CZ26A
3.10 SDRAM Controller (SDRAMC)
The TMP92CZ26A incorporates an SDRAM controller (SDRAMC) for accessing SDRAM that can
be used as data memory, program memory, or display memory.
The SDRAMC has the following features:
(1) Supported SDRAM
Data rate type
Memory capacity
Number of banks
Data bus width
Read burst length
Write mode
: SDR (single data rate) type only
: 16 / 64 / 128 / 256 / 512 Mbits
: 2 banks / 4 banks
: 16 bits
: 1 word / full page
: Single mode / Burst mode
(2) Supported initialization sequence commands
Precharge All command
Eight Auto Refresh commands
Mode Register Set command
(3) Access mode
CPU Cycle
HDMA Cycle
LCDC Cycle
Burst length
1 word
Sequential
2
1 word or full page selectable
Full page
Sequential
2
Addressing mode
CAS latency (clock)
Write mode
Sequential
2
Single
Single or burst selectable
(4) Access cycles
CPU access cycles
Read cycle
Write cycle
Data size
: 1 word, 4-3-3-3 states (minimum)
: Single, 3-2-2-2 states (minimum)
: 1 byte / 1 word / 1 long-word
HDMA access cycles
Read cycle
: 1 word, 4-3-3-3 states / full page, 4-1-1-1 states (minimum)
Write cycle
Data size
: Single, 3-2-2-2 states (minimum) / burst, 2-1-1-1 states (minimum)
: 1 byte / 1 word / 1 long-word
LCDC access cycles
Read cycle
: Full page, 4-1-1-1 states (minimum)
: 1 word
Data size
(5) Auto generation of refresh cycles
• Auto Refresh is performed while the SDRAM is not being accessed.
• The Auto Refresh interval is programmable.
• The Self Refresh function is also supported.
Note: The SDRAM address area is determined by the CS1 or CS2 setting of the memory controller. However, the number of
bus cycle states is controlled by the SDRAMC.
92CZ26A-220
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TMP92CZ26A
3.10.1 Control Registers
The SDRAMC has the following control registers.
SDRAM Access Control Register
7
6
5
4
3
2
1
0
SMAC
R/W
0
Bit symbol
Read/Write
After reset
SRDS
–
SMUXW1 SMUXW0
R/W
SPRE
SDACR
(0250H)
1
0
0
0
0
Always
Read data
shift
Address multiplex type
Read/Write
commands
SDRAM
write “0”
controller
function
0: Disable
1: Enable
00: Type A (A9- )
01: Type B (A10- )
10: Type C (A11- )
11: Reserved
0: Without
auto pre-
charge
0: Disable
1: Enable
Function
1: With auto
precharge
SDRAM Command Interval Setting Register
7
6
5
4
3
STRCD
R/W
2
1
0
Bit symbol
Read/Write
After reset
STMRD
STWR
STRP
STRC2
STRC1
STRC0
SDCISR
(0251H)
1
1
1
1
1
0
0
TMRD
TWR
TRP
TRCD
TRC
000: 1 CLK 100: 5 CLK
001: 2 CLK 101: 6 CLK
010: 3 CLK 110: 7 CLK
011: 4 CLK 111: 8 CLK
Function
0: 1 CLK
1: 2 CLK
0: 1 CLK
1: 2 CLK
0: 1 CLK
1: 2 CLK
0: 1 CLK
1: 2 CLK
SDRAM Refresh Control Register
7
6
5
4
3
2
1
0
Bit symbol
Read/Write
After reset
−
R/W
0
SSAE
SRS2
SRS1
R/W
0
SRS0
SRC
SDRCR
(0252H)
1
0
0
0
Always
write “0”
Self
Refresh interval
000: 47 states 100: 468 states Refresh
001: 78 states 101: 624 states
010: 156 states 110: 936 states 0:Disable
011: 312 states 111: 1248 states 1:Enable
Auto
Refresh
auto exit
function
0:Disable
1:Enable
Function
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TMP92CZ26A
SDRAM Command Register
7
6
5
4
3
2
1
SCMM1
R/W
0
0
Bit symbol
Read/Write
After reset
SCMM2
SCMM0
SDCMM
(0253H)
0
0
Command issue (Note 1) (Note 2)
000: Don’t care
001: Initialization sequence
a. Precharge All command
b. Eight Auto Refresh commands
c. Mode Register Set command
010: Precharge All command
100: Reserved
Function
101: Self Refresh Entry command
110: Self Refresh Exit command
Others: Reserved
Note 1: <SCMM2:0> is automatically cleared to “000” after the specified command is issued. Before writing the next
command, make sure that <SCMM2:0> is “000”. In the case of the Self Refresh Entry command, however,
<SCMM2:0> is not cleared to “000” by execution of this command. Thus, this register can be used as a flag for
checking whether or not Self Refresh is being performed.
Note 2: The Self Refresh Exit command can only be specified while Self Refresh is being performed.
SDRAM HDMA Burst Length Select Register
7
6
5
4
3
2
1
0
Bit symbol
Read/Write
After reset
SDBL5
SDBL4
SDBLS
SDBL2
SDBL1
SDBL0
SDBLS
(0254H)
R/W
0
0
0
0
0
0
For HDMA5 For HDMA4 For HDMA3 For HDMA2 For HDMA1 For HDMA0
HDMA burst length
Function
0: 1 Word read / Single write
1: Full page read / Burst write
Figure 3.10.1 Control Registers
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3.10.2 Operation Description
(1) Memory access control
The SDRAMC is enabled by setting SDACR<SMAC> to “1”.
When one of the bus masters (CPU, LCDC, DMAC) generates a cycle to access the SDRAM
address area, the SDRAMC outputs SDRAM control signals.
SDRAM access cycles is controlled by the SDRAMC and does not depend on the number of
waits controlled by the memory controller.
(a) Command issue function
The SDRAMC issues commands as specified by the SDCMM register. The SDRAMC also
issues commands automatically for each SDRAM access cycle generated by each bus
master.
Table 3.10.1 shows the commands that are issued by the SDRAMC.
Table 3.10.1 Commands Issued by the SDRAMC
A15-11
Command
Bank Activate
CKE
CKE
SDxxDQM
A10
SDCS SDRAS SDCAS SDWE
n-1
n
A9-0
RA
X
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
L
RA
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
H
L
H
L
Precharge All
Read
CA
CA
CA
CA
M
H
H
H
H
L
H
H
L
Read with Auto Precharge
Write
L
H
L
L
L
L
Write with Auto Precharge
Mode Register Set
Burst Stop
L
H
L
L
L
H
H
H
H
H
L
L
X
X
X
X
X
H
L
H
L
L
Auto Refresh
X
H
H
H
Self Refresh Entry
Self Refresh Exit
X
L
L
H
X
H
H
Note 1: H = High level, L = Low level, RA = Row address, CA = Column address, M = Mode data, X = Don’t care
Note 2: CKEn = CKE level in the command input cycle
CKEn-1 = CKE level in a cycle immediately before the command input cycle
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(b) Address multiplex function
In access cycles, the A0 to A15 pins output low/column multiplexed addresses. The
between the multiplex width and low/column addresses.
Table3.10.2 Address Multiplex
SDRAM Access Cycle Address
92CZ26A Pin
Name
Row Address
Type B
Column Address
Type A
Type C
<SMUXW> = 00 <SMUXW> = 01
<SMUXW> = 10
A0
A1
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
EA24
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
EA24
EA25
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
EA24
EA25
EA26
A1
A2
A2
A3
A3
A4
A4
A5
A5
A6
A6
A7
A7
A8
A8
A9
A9
A10
AP *
A10
A11
A12
A13
A14
A15
Row Address
*AP: Auto Precharge
(c) Burst length
When the CPU accesses the SDRAM, the burst length is fixed to 1-word read/single write.
When the LCDC accesses the SDRAM, the burst length is fixed to full page.
The burst length can be selected for SDRAM read and write accesses by HDMA if the
following conditions are satisfied:
• The HDMA transfer mode is an increment mode.
• Transfers are made between the SDRAM and internal RAM or internal I/O.
In other cases, HDMA operation can only be performed in 1-word read/single write mode.
Use SDBLS<SDBL5:0> to set the burst length for each HDMA channel.
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TMP92CZ26A
4CLK
3CLK
3CLK
SDCLK
SDCKE
SDLUDQM
SDLLDQM
SDCS
SDRAS
SDCAS
SDWE
A10
RA
RA
CA (n)
CA (n+2)
CA (n+4)
A15-A0
D15-D0
D (n)
D (n+2)
D (n+4)
tRCD=
1CLK
CAS Latency=2CLK
CAS Latency=2CLK
CAS Latency=2CLK
Bank
Read
Read
Read
Active
Figure3.10.2 1-Word Read Cycle Timing
4CLK
1CLK
1CLK
Burst Stop Cycle 2CLK
SDCLK
SDCKE
SDLUDQM
SDLLDQM
SDCS
SDRAS
SDCAS
SDWE
A10
RA
RA
A10
CA (n)
A15-0
A15-A0
D15-D0
D (n)
D (n+2)
D (n+4)
D(dmy)
D (dmy)
tRCD=
1CLK
CAS Latency=2CLK
Burst Stop
Bank
Read
Active
Figure3.10.3 Full-Page Read Cycle Timing
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3CLK
2CLK
2CLK
SDCLK
SDCKE
SDLUDQM
SDLLDQM
SDCS
SDRAS
SDCAS
SDWE
A10
RA
RA
CA (n)
CA (n+2)
CA (n+4)
A15-A0
D15-D0
D (n)
D (n+2)
D (n+4)
tRCD=
1CLK
tWR=
1CLK
tWR=
1CLK
tWR=
1CLK
Bank
Write
Write
Write
Active
Figure3.10.4 Single Write Cycle Timing
2CLK
1CLK
1CLK
Burst Stop Cycle 2CLK
SDCLK
SDCKE
SDLUDQM
SDLLDQM
SDCS
SDRAS
SDCAS
SDWE
A10
RA
RA
A10
CA(n)
CA(n)
D(end)
A15-0
A15-A0
D15-D0
D(n)
D(n+2)
D(n+4)
D(n+6)
tRCD=
1CLK
Burst
Stop
Bank
Active
Write
Figure3.10.5 Burst Write Cycle Timing
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(2) Execution of instructions on SDRAM
The CPU can execute instructions that are stored in the SDRAM. However, the following
operations cannot be performed.
a) Executing the HALT instruction
b) Changing the clock gear setting
c) Changing the settings in the SDACR, SDCMM, and SDCISR registers
These operations, if needed, must be executed by branching to other memory such as
internal RAM.
(3) Command interval adjustment function
Command execution intervals can be adjusted for each command. This function enables the
SDRAM to be accessed at optimum cycles even if the operationg frequency is changed by clock
gear.
Command intervals should be set in the SDCISR register according to the operating
frequency of the TMP92CZ26A and the AC specifications of the SDRAM.
The SDCICR register must not be changed while the SDRAM is being accessed.
The timing waveforms for various cases are shown below.
(a) Mode Register Set command
SDCLK
Next
Command
NOP
MRS
NOP
NOP
COMMAND
TMRD
*TMRD=2CLK (SDCISR<STMRD>=”1”)
(b) Auto Refresh command
SDCLK
COMMAND
AUTO
Next
Command
NOP
NOP
NOP
NOP
NOP
REFRESH
TRC
*TRC=5CLK (SDCISR<STRC2:0>=”100”)
(c) Self Refresh Exit
SDCLK
SDCKE
Next
Command
XXX
NOP
NOP
NOP
NOP
TRC
NOP
COMMAND
*TRC=5CLK (SDCISR<STRC2:0>= “100”)
Exit Self Refresh
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(d) Precharge command
SDCLK
PRECHARGE
Next
Command
NOP
NOP
NOP
COMMAND
TRP
*TRP=2CLK (SDCISR<STRP>= “1”)
(e) Read cycle
SDCLK
NOP
ACTIVE
NOP
READ
NOP
NOP
NOP
ACTIVE
COMMAND
A15-A0
Non MUX-address
Row Address
Column Address
Row Address
DIN
D15-D0
TRCD
TRC
*TRCD=2CLK (SDCISR<STRCD>= “1”)
*TRC=6CLK (SDCISR<STRC2:0>= “101”)
(f) Write cycle
SDCLK
ACTIVE
Row Address
NOP
Column Address
DOUT
NOP
WRITE
NOP
PRECHARG
NOP
ACTIVE
COMMAND
A15-A0
Non MUX-address
Row Address
D15-D0
TRCD
TWR
TRP
TRC
*TRCD=2CLK (SDCISR<STRCD>= “1”)
*TWR=2CLK (SDCISR<STWR>= “1”)
*TRP=2CLK (SDCISR<STRP>= “1”)
*TRC=6CLK (SDCISR<STRC2:0>= “101”)
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(4) Read data shift function
If the AC specifications of the SDRAM cannot be satisfied when data is read from the
SDRAM, the read data can be latched in a port circuit so that the CPU can read the data in
the next state. When this read data shift function is used, the read cycle requires additional
one state. The write cycle is not affected. The timing waveforms for various cases are shown
below.
(a) 1-word read, the read data shift function disabled (SDACR<SRCS> = “0”)
SDCLK
NOP
ACTIVE
READ
NOP
NOP
ACTIVE
READ
COMMAND
A15-A0
D15-D0
Column
Address
Row Address
Row Address
ColumnAddress
DIN1
Internal system
clock
DIN1
Internal dat bus
CPU data read
(b) 1-word read, the read data shift function enabled (SDACR<SRDS> = “1”,
<SRDSCK>=”0”)
SDCLK
COMMAND
A15-A0
NOP
ACTIVE
READ
NOP
NOP
NOP
ACTIVE
ColumnAddress
Row Address
Row Address
DIN1
D15-D0
Internal system
clock
DIN1
CPU data read
Internal data bus
External data latch
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(c) Full-page read, the read data shift function enabled (SDACR<SRDS> = “1”,
<SRDSCK> = “0”)
SDCLK
COMMAND
A15-A0
NOP
ACTIVE
READ
NOP
NOP
ColumnAddress
DIN1
NOP
NOP
Row Address
DIN2
DIN3
D15-D0
Internal system
clock
DIN1
DIN2
DIN3
Internal data bus
External data latch CPU data read
(5) Read/Write commands
The Read/Write commands to be used in 1-word read/single write mode can be specified by
using SDACR<SPRE>.
When SDACR<SPRE> is set to “1”, the Read/Write commands are executed with Auto
Precharge. When Auto Precharge is enabled, the SDRAM is automatically precharged
internally at every access cycle. Thus, the SDRAM is always in a “bank idle” state while it is
not being accessed. This helps reduce the power consumption of the SDRAM but at the cost of
degradation in performance as the Bank Active command is needed at every access cycle.
When SDACR<SPRE> is set to “0”, the Read/Write commands are executed without Auto
Precharge. In this case, the SDRAM is not precharged at every access cycle and is always in a
“bank active” state. This increases the power consumption of the SDRAM, but improves
performance as there is no need to issue the Bank Active command at every access cycle. If an
access is made to outside the SDRAM page boundaries or if the Auto Refresh command is
issued, the SDRAMC automatically issues the Precharge All command.
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(6) Refresh control
The TMP92CZ26A supports two kinds of refresh commands: Auto Refresh and Self Refresh.
(a) Auto Refresh
When SDRCR<SRC> is set to “1”, the Auto Refresh command is automatically issued at
intervals specified by SDRCR<SRS2:0>. The Auto Refresh interval can be specified in a
range of 47 states to 1248 states (0.78 μs to 20.8 μs at f SYS = 60 MHz).
The CPU operation (instruction fetch and execution) is halted while the Auto Refresh
Table3.10.3 shows the Auto Refresh interval settings. The Auto Refresh function cannot be
used in IDLE1 and STOP modes. In these modes, use the Self Refresh function to be
explained next.
Note: A system reset disables the Auto Refresh function.
2 states
SDCLK
SDCKE
SDLUDQM
SDLLDQM
SDCS
SDRAS
SDCAS
SDWE
Auto Refresh
Figure3.10.6 Auto Refresh Cycle Timing
Table3.10.3 Auto Refresh Intervals
Unit [μs]
SDRCR<SRS2:0>
Auto
Frequency (System Clock)
Refresh
Interval
(states)
SRS2
SRS1
SRS0
6 MHz
10 MHz
20 MHz
40 MHz
60 MHz
80 MHz
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
47
78
7.8
13.0
4.7
7.8
2.4
3.9
1.18
1.95
0.78
1.30
0.59
0.98
1.95
3.90
5.85
7.80
11.70
15.60
156
312
468
624
936
1248
26.0
15.6
31.2
46.8
62.4
93.6
124.8
7.8
3.90
2.60
52.0
15.6
23.4
31.2
46.8
62.4
7.80
5.20
78.0
11.70
15.60
23.40
31.20
7.80
104.0
156.0
208.0
10.40
15.60
20.80
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(b) Self Refresh
The Self Refresh Entry command is issued by setting SDCMM<SCMM2:0> to “101”.
Figure3.10.7 shows the Self Refresh cycle timing. Once Self Refresh is started, the SDRAM
is refreshed internally without the need to issue the Auto Refresh command.
Note 1: When standby mode is released by a system reset, the I/O registers are initialized and the Self Refresh state is
exited. Note that the Auto Refresh function is also disabled at this time.
Note 2: The SDRAM cannot be accessed while it is in the Self Refresh state.
Note 3: To execute the HALT instruction after the Self Refresh Entry command, insert at least 10 bytes of NOP or other
instructions between the instruction to set SDCMM<SCMM2:0> to “101” and the HALT instruction.
SDCLK
SDCKE
SDLUDQM
SDLLDQM
SDCS
SDRAS
SDCAS
SDWE
Self Refresh Entry
Self Refresh Exit
Auto Refresh Mode
Set
Figure3.10.7 Self Refresh Cycle Timing
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The Self Refresh state can be exited by the Self Refresh Exit command. The Self Refresh
Exit command is executed when SDCMM<SCMM2:0> is set to “110”. It is also executed
automatically in synchronization with HALT mode release. In either of these two cases,
Auto Refresh is performed immediately after the Self Refresh state is exited. Then, Auto
Refresh is executed at specified intervals. Exiting the Self Refresh state clears
SDCMM<SCMM2:0> to “000”.
Setting SDRCR<SSAE> to “0” disables automatic execution of the Self Refresh Exit
command in synchronization with HALT release. The auto exit function should also be
disabled in cases where the SDRAM operation requirements cannot be met as the operation
clock frequency is reduced by clock gear down, as shown in Figure3.10.8.
Gear down
Gear up
f
SYS
60MHz
｜
｜
625 KHz (10MHz/16)
Interrupt
CPU
CLK
change
CLK
change
SR
EXIT
Auto-EXIT
enable
SR
ENTRY
Auto-EXIT
disable
HALT
HALT mode
SDRAM controller
internal state
Auto Exit
enable
Auto Exit
disable
Auto Exit
enable
SDRAM state
Auto Refresh
Self Refresh
Auto Refresh
Figure3.10.8 Execution Flow for Executing HALT Instruction after Clock Gear Down
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(7) SDRAM initialization sequence
After reset release, the following sequence of commands can be executed to initialize the
SDRAM.
1. Precharge All command
2. Eight Auto Refresh commands
3. Mode Register Set command
The above commands are issued by setting SDCMM<SCMM2:0> to “001”. While these
commands are issued, the CPU operation (instruction fetch, execution) is halted. Before
executing the initialization sequence, appropriate port settings must be made to enable the
SDRAM control signals and address signals (A0 to A15).
After the initialization sequence is completed, SDCMM<SCMM2:0> is automatically
cleared to “000”.
Eight Auto Refresh commands
SDCLK
SDCKE
SDLUDQM
SDLLDQM
SDCS
SDRAS
SDCAS
SDWE
A10
A15-A0
627
227
Precharge All Auto Refresh
Auto Refresh
Auto Refresh
Auto Refresh
Auto Refresh
Mode Register
Set
Figure3.10.9 Initialization Sequence Timing
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(8) Connection example
Figure3.10.10 shows an example of connections between the TMP92CZ26A and SDRAM.
Table3.10.4 Pin Connections
SDRAM Pin Name
92CZ26A
Data Bus Width 16 bits
Pin Name
16M
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
BS
−
64M
A0
128M
A0
256M
A0
512M
A0
A0
A1
A1
A1
A1
A1
A2
A2
A2
A2
A2
A3
A3
A3
A3
A3
A4
A4
A4
A4
A4
A5
A5
A5
A5
A5
A6
A6
A6
A6
A6
A7
A7
A7
A7
A7
A8
A8
A8
A8
A8
A9
A9
A9
A9
A9
A10
A11
A12
A13
A14
A15
SDCS
SDLUDQM
SDLLDQM
SDRAS
A10
A11
BS0
BS1
−
A10
A11
BS0
BS1
−
A10
A11
A12
BS0
BS1
−
A10
A11
A12
BS0
BS1
−
−
−
−
CS
−
−
CS
CS
CS
CS
UDQM
LDQM
RAS
UDQM
LDQM
RAS
UDQM
LDQM
RAS
UDQM
LDQM
RAS
UDQM
LDQM
RAS
SDCAS
CAS
CAS
CAS
CAS
CAS
SDWE
SDCKE
SDCLK
WE
CKE
CLK
WE
CKE
CLK
WE
CKE
CLK
WE
CKE
CLK
WE
CKE
CLK
SDACR
00:
00:
01:
01:
10:
<SMUXW>
TypeA
TypeA
TypeB
TypeB
TypeC
: Command address pin of SDRAM
TMP92CZ26A
SDCLK
SDCKE
CLK
CKE
A13
A12
BS1
BS0
A11-A0
A11-A0
D15-D0
D15-D0
SDRAS
SDCAS
SDWE
SDCS
RAS
CAS
WE
CS
SDLUDQM
SDLLDQM
UDQM
LDQM
1 Mword x 4 banks x 16 bits
Figure3.10.10 An Example of Connections between TMP92CZ26A and SDRAM
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3.10.3 An Example of Calculating HDMA Transfer Time
The following shows an example of calculating the HDMA transfer time when SDRAM is used as
the transfer source.
1) Transfer from SDRAM to internal SRAM
Conditions:
System clock (fSYS
)
: 60 MHz
SDRAM read cycle
: Full page (5-1-1-1), 16-bit data bus
16-bit data bus
SDRAM Auto Refresh interval : 936 states (15.6 μs)
Internal RAM write cycle
Number of bytes to transfer
: 1 state, 32-bit data bus
: 512 bytes
Calculation example:
Transfer time = (SDRAM read time + SRAM write time) × transfer count
+ (SDRAM burst start + stop time)
+ (Precharge time + Auto Refresh time) × Auto Refresh count
(a) Read/write time
(SDRAM read 1 state × 2 + Internal RAM write 1 state) × 512 bytes/4 bytes
= 384 states × 1/60 MHz
= 6.4 μs
(b) Burst start/stop time
Start (TRCD: 2CLK) 5 states + Stop 2 states
= 7states/60 MHz
= 0.117 μs
(c) Auto Refresh time
Based on the above (a), Auto Refresh occurs once or zero times in 384 states. It is
assumed that Auto Refresh occurs once here.
(Precharge (TRP: 2CLK) 2 states + AREF (TRC: 5CLK) 5 states) ×AREF once
= 7 states × 1/60 MHz
= 0.117 μs
Total transfer time = (a) + (b) + (c)
= 6.4 μs + 0.117 μs + 0.117 μs
= 6.634 μs
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3.10.4 Considerations for Using the SDRAMC
This section describes the points that must be taken into account when using the SDRAMC.
Please carefully read the following to ensure proper use of the SDRAMC.
1) WAIT access
When SDRAM is used, the following restriction applies to memory access to other than
the SDRAM.
In the external WAIT pin input setting of the memory controller, the maximum external
WAIT period that can be set is limited to “Auto Refresh interval × 8190”.
2) Execution of the Self Refresh Entry, Initialization Sequence, or Precharge All command
before the HALT instruction
Execution of the commands issued by the SDRAMC (Self Refresh Entry, Initialization
Sequence, Precharge All) requires several states after the SDCMM register is set.
Therefore, to execute the HALT instruction after one of these commands, be sure to insert
at least 10 bytes of NOP or other instructions.
3) Auto Refresh interval setting
When SDRAM is used, the system clock frequency must be set to satisfy the minimum
operation frequency and minimum Auto Refresh interval of the SDRAM to be used.
In a system in which SDRAM is used and the clock is geared up and down, the Auto
Refresh interval must be set carefully.
Before changing the Auto Refresh interval, ensure that SDRCR<SRC> is set to “0” to
disable the Auto Refresh function.
4) Changing SFR settings
Before changing the settings of the SDACR<SPRE> and SDCISR registers, ensure that
the SDRAMC is disabled (SDACR<SMAC> =“0”).
5) Disabling the SDRAMC
Set the following procedure, when disable the SDRAMC.
LD
LD
CP
(SDCMM),0x02
A,(SDCMM)
A,0x00
;
;
;
Issue to All Bank Precharge
LOOP:
Read SDCMM
Palling it until the All Bank Precharge command is
finished
JP
LD
NZ,LOOP
;
;
(SDACR),0x00
Stop the SDRAM controller
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3.11 NAND Flash Controller (NDFC)
3.11.1 Features
The NAND Flash Controller (NDFC) is provided with dedicated pins for connecting with
NAND Flash memory.
The NDFC also has an ECC calculation function for error correction and supports two types
of ECC calculation methods. The ECC calculation method using Hamming codes can be used for
NAND Flash memory of SLC (Single Level Cell) type and is capable of detecting a single-bit
error for every 256 bytes. The ECC calculation method using Reed-Solomon codes can be used
for NAND Flash memory of MLC (Multi Level Cell) type and is capable of detecting four error
addresses for every 518 bytes.
Although the NDFC has two channels (channel 0, channel 1), all pins except for Chip Enable
are shared between the two channels. Only the operation of channel 0 is explained here.
The NDFC has the following features:
1) Controls the NAND Flash memory interface through registers.
2) Supports 8-bit and 16-bit NAND Flash memory devices.
3) Supports page sizes of 512 bytes and 2048 bytes.
4) Supports large-capacity block sizes over 256 Kbytes.
5) Includes an ECC generation circuit using Hamming codes (for SLC type).
6) Includes a 4-address (4-byte) error detection circuit using Reed-Solomon coding/
encoding techniques (for MLC type).
Note 1:The
(Write Protect) pin of NAND Flash is not supported. If this function is needed, prepare it on an
WP
external circuit.
Note 2:The two channels cannot be accessed simultaneously. It is necessary to switch between the two channels.
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3.11.1 Block Diagram
NAND Flash Controller Channel 0 (NDFC0)
ND_CE*
ND0CE
Hamming
ECC
Generator
ND_ALE
ND_CLE
ND_RE*
NDCLE,
NDALE,
NDRE ,
NDWE ,
D15~ D0
ECC
Code
ND WE*
Timing
Generator
ND_RB*
RS ECC Write
Control
Register
Reed-Solomon
ECC
Generator
DATA_OUT[15:0]
DATA_IN[15:0]
D15~D0,
NDR/B
F/F 80-bit
Address
Data
Reed-Solomon
ECC
Calculator
Figure 3.11.1 Block Diagram for NAND Flash Controller
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3.11.2 Operation Description
3.11.2.1 Accessing NAND Flash Memory
The NDFC accesses data on NAND Flash memory indirectly through its internal
registers. This section explains the operations for accessing the NAND Flash.
Since no dedicated sequencer is provided for generating commands to the NAND Flash,
the levels of the NDCLE, NDALE, and NDCE pins must be controlled by software.
NDCLE
NDALE
NDCE
NDRE
NDWE
NDR/B
D15∼D0
NDFMCR0<CLE> = 1
NDFMCR0<CLE> = 0
NDFMCR0<ALE> = 1
ND0FMCR<ALE> = 0
NDFMCR0<CE0> = 1
Figure 3.11.2 Basic Timing for Accessing NAND Flash
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The NDRE and NDWE signals are explained next. Write and read operations to and from
the NAND Flash are performed through the ND0FDTR register. The actual write operation
completes not when the ND0FDTR register is written to but when the data is written to the
external NAND Flash. Likewise, the actual read operation completes not when the
ND0FDTR register is read but when the data is read from the external NAND Flash.
At this time, the Low and High widths of NDRE and NDWE can be adjusted according to
the CPU operating speed (fSYS) and the access time of the NAND Flash. (For details, refer to
the electrical characteristics.)
The following shows an example of accessing the NAND Flash in 6 clocks by setting
NDFMCR0<SPLW1:0>=2 and NDFMCR0<SPHW1:0>=2. (In write cycles, the data drive
time also becomes longer.)
Program Memory Read (1wait)
Program Memory Read (1 wait)
NAND Flash Read
f
SYS
A23∼A0
CS2
FF1234H
001FF0H
FF1238H
RD
SRWR
NDCLE
NDALE
2clk
NDCE
2clk
NDRE
NDWE
NDR/B
D15 ∼ D0
IN (Program)
IN (NAND Flash)
IN (Program)
Program Memory Read (1 wait)
Program Memory Read (1 wait)
NAND Flash Write
f
SYS
FF1234H
A23∼A0
CS2
001FF0H
FF1238H
RD
SRWR
NDCLE
NDALE
NDCE
2clk
NDRE
NDWE
NDR/B
2clk
OUT (NAND Flash)
IN (Program)
IN (Program)
D15 ∼ D0
Figure 3.11.3 Read/Write Access to NAND Flash
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3.11.3 ECC Control
NAND Flash memory devices may inherently include error bits. It is therefore necessary to
implement the error correction processing using ECC (Error Correction Code).
Figure 3.11.4 shows a basic flowchart for ECC control.
Data Write
Data Read
Valid data write to
NAND Flash
Valid data read from
NAND Flash
Valid data write to
ECC generator
Valid data write to
ECC generator
ECC read from
NAND Flash
ECC read
from ECC generator
Write ECC to
NAND Flash
ECC read from
ECC circuit
END
Yes
Is there error?
Error correction
process
No
END
Figure 3.11.4 Basic Flow of ECC Control
Write:
1. When data is written to the actual NAND Flash memory, the ECC generator in
the NDFC simultaneously generates ECC for the written data.
2. The ECC is written to the redundant area in the NAND Flash separately from
the valid data.
Read:
1. When data is read from the actual NAND Flash memory, the ECC generator in
the NDFC simultaneously generates ECC for the read data.
2. The ECC for the written data and the ECC for the read data are compared to
detect and correct error bits.
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3.11.3.1 Differences between Hamming Codes and Reed-Solomon Codes
The NDFC includes an ECC generator supporting NAND Flash memory devices of SLC
(or 2LC: two states) type and MLC (or 4LC: four states) type.
The ECC calculation using Hamming codes (supporting SLC) generates 22 bits of ECC
for every 256 bytes of valid data and is capable of detecting and correcting a single-bit error
for every 256 bytes. Error bit detection calculation and correction must be implemented by
software. When using SmartMedia™, Hamming codes should be used.
The ECC calculation using Reed-Solomon codes (supporting MLC) generates 80 bits of
ECC for every 1 byte to 518 bytes of valid data and is capable of detecting and correcting
error bits at four addresses for every 518 bytes. When using Reed-Solomon codes, error bit
detection calculation is supported by hardware and only error bit correction needs to be
implemented by software.
The differences between Hamming codes and Reed-Solomon codes are summarized in
Table 3.11.1.
Table 3.11.1 Differences between Hamming Codes and Reed-Solomon Codes
Hamming
Reed-Solomon
Maximum number of
correctable errors
Number of ECC bits
Error bit detection
method
1 bit
4 addresses
(All the 8 bits at one address are correctable.)
80 bits/up to 518 bytes
22 bits/256 bytes
Software
Hardware
Error bit correction
method
Software
Software
Error bit detection time
Others
Depends on the software to be used.
Supports SmartMedia™.
See the table below.
-
Number of
Error Bits
Reed-Solomon Error Bit
Notes
Detection Time (Unit: Clocks)
4
3
2
1
0
813 (max)
These values indicate the total number of clocks for
detecting error bit(s) not including the register read/write
time by the CPU.
648 (max)
358 (max)
219 (max)
1
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3.11.3.2 Error Correction Methods
Hamming ECC
•
The ECC generator generates 44 bits of ECC for a page containing 512 bytes of valid data. The error
correction process must be performed in units of 256 bytes (22 bits of ECC). The following explains how
to implement error correction on 256 bytes of valid data using 22 bits of ECC.
•
If the NAND Flash to be used has a large-capacity page size (e.g. 2048 bytes), the error correction
process must be repeated several times to cover the entire page.
1) The calculated ECC and the ECC in the redundant area are rearranged, respectively,
so that the lower 2 bytes represent line parity (LPR15:0) and the upper 1 byte (of which
the upper 6 bits are valid) represents column parity (CPR7:2).
2) The two rearranged ECCs are XORed.
3) If the XOR result is 0 indicating an ECC match, the error correction process ends
normally (no error). If the XOR result is other than 0, it is checked whether or not the
error data can be corrected.
4) If the XOR result contains only one ON bit, it is determined that a single-bit error
exists in the ECC data itself and the error correction process terminates here (error not
correctable).
5) If each pair of bits 0 to 21 of the XOR result is either 01B or 10B, it is determined that
the error data is correctable and error correction is performed accordingly. If the XOR
result contains either 00B or 11B, it is determined that the error data is not correctable
and the error correction process terminates here.
An Example of Correctable
XOR Result
An Example of Uncorrectable
XOR Result
Hexadecimal
Binary
26a65a
2ea65a
10 01 10 00 Column parity
10 10 01 10 Line parity
01 01 10 10
10 11 10 00 Column parity
10 10 01 10
01 01 10 10
Line parity
6) The line and bit positions of the error are detected using the line parity and column
parity of the XOR result, respectively. The error bit thus detected is then inverted. This
completes the error correction process.
Example: When the XOR result is 26a65aH
Convert two bytes of line parity into one byte (10→1, 01→0).
Convert six bits of column parity into three bits (10→1、01→0).
Line parity:
10 10 01 10 01 01 10 10
1 = 212
1
1
0
1
0
0
1
*Error at address 212
Column parity:
10 01 10
1 = 5
1
0
*Error in bit 5
Based on the above, error correction is performed by inverting the data in bit 5 at address 212.
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Reed-Solomon ECC
•
The ECC generator generates 80 bits of ECC for up to 518 bytes of valid data. If the NAND Flash to be
used has a large-capacity page size (e.g. 2048 bytes), the error correction process must be repeated
several times to cover the entire page.
•
Basically no calculation is needed for error correction. If error detection is performed properly, the NDFC
only needs to refer to the error address and error bit. However, it may be necessary to convert the error
address, as explained below.
1) If the error address indicated by the NDRSCAn register is in the range of 000H to
007H, this error exists in the ECC area and no correction is needed in this case.
(It is not able to correct the error in the ECC area. However, if the error exists in the
ECC area, only 4symbol (include the error in the ECC area) can correct the error to this
LSI. Please be careful.)
2) If the error address indicated by the NDRSCAn register is in the range of 008H to
20DH, the actual error address is obtained by subtracting this address from 20 DH.
(If the valid data is processed as 512 byte, the actual error address is obtained by
subtracting this address from 207H when the error address in the range of 008H to
207H.)
Example 1:
NDRSCAn = 005H, NDRSCDn = 04H = 00000100B
As the error address (005H) is in the range of 000H to 007H, no correction is needed.
(Although an error exists in bit 2, no correction is needed.)
Example 2:
NDRSCAn = 083H, NDRSCDn = 81H = 10000001B
The actual error address is obtained by subtracting 083H from 20DH. Thus, the error correction process inverts
the data in bits 7 and 0 at address 18AH.
(If the valid data is 512 byte, the actual error address is obtained by subtracting 083H from 207H. Thus, the error
correction process inverts the data in bits 7 and 0 at address 184H.)
Note:
If the error address (after converted) is in the range of 000H to 007H, it indicates that an error bit exists in
redundant area (ECC). In this case, no error correction is needed. If the number of error bits is not more
than 4 symbols, Reed-Solomon codes calculate each error bit precisely even if it is the redundant area
(ECC).
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3.11.4 Description of Registers
NAND Flash Control 0 Register
7
WE
R/W
0
6
ALE
R/W
0
5
CLE
R/W
0
4
CE0
R/W
0
3
CE1
R/W
0
2
ECCE
R/W
0
1
BUSY
R
0
NDFMCR0
(08C0H)
bit Symbol
Read/Write
After reset
ECCRST
W
0
0
Read-modify-
write
instructions
cannot be
used.
WE
enable
0: Disable 0: “L” out
ALE
control
CLE
control
CE0
control
0: “H” out 0: “H” out
CE1
control
NAND
Flash
state
1: Busy
0: Ready
ECC
ECC circuit
control
reset
control
0: −
1: Reset
*Always
read as
“0”.
0: “L” out
0: Disable
1: Enable
1: Enable 1: “H” out 1: “H” out 1: “L” out
1: “L” out
Function
15
14
13
12
11
10
9
8
(08C1H)
bit Symbol
Read/Write
SPLW1
SPLW0
SPHW1
SPHW0
RSECCL
RSEDN
RSESTA RSECGW
R/W
W
R/W
0
Read-modify-
write
instructions
cannot be
used.
After reset
0
0
0
0
0
Reed-
Solomon
ECC
0
0
Strobe pulse width
(Low width of NDRE , (High width of NDRE ,
NDWE )
Strobe pulse width
Reed-
Reed-
Reed-
Solomon
Solomon
Solomon
ECC
NDWE )
operation error
latch
0: Encode calculation generator
Inserted width
Inserted width
= (f
) × (set value)
= (f
) × (set value)
(Write)
1: Decode
(Read)
start
write
SYS
SYS
Function
0: Disable
1: Enable
0: −
control
1: Start
*Always
read as
“0”.
0: Disable
1: Enable
Figure 3.11.5 NAND Flash Mode Control 0 Register
(a) <ECCRST >
The <ECCRST> bit is used for both Hamming and Reed-Solomon codes.
When NDFMCR1<ECCS>=“0”, setting this bit to “1” clears the Hamming ECC in the
ECC generator. When NDFMCR1<ECCS>=“1”, setting this bit to “1” clears the
Reed-Solomon ECC. Note that this bit is ineffective when NDFMCR0<ECCE>=“0”. Before
writing to this bit, ensure that NDFMCR0<ECCE>=“1”.
(b) <BUSY>
The <BUSY> bit is used for both Hamming and Reed-Solomon codes.
This bit is used to check the state of the NAND Flash memory (NDR/B pin). It is set to “1”
when the NAND Flash is “busy” and to “0” when it is “ready”.
Since the NDFC incorporates a noise filter of several states, a change in the NDR/B pin
state is reflected on the <BUSY> flag after some delay. It is therefore necessary to inert a
delay time by software (e.g. ten NOP instructions) before checking this flag.
Read
command
Delay
time
Sensing <BUSY> flag
Address input
NDWE pin
NDCLE pin
NDALE pin
NDR/B pin
<BUSY> flag
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(c) <ECCE>
The <ECCE> bit is used for both Hamming and Reed-Solomon codes.
This bit is used to enable or disable the ECC generator. To reset the ECC in the ECC
generator (to set <ECCRST> to “1”), the ECC generator must be enabled (<ECCE> = “1”).
(d) <CE1:0>, <CLE>, <ALE>
The <CE1:0>, <CLE>, and <ALE> bits are used for both Hamming and Reed-Solomon
codes to control the pins of the NAND Flash memory.
(e) <WE>
The <WE> bit is used for both Hamming and Reed-Solomon codes to enable or disable
write operations.
(f) <RSECGW>
The <RSECGW> bit is used only for Reed-Solomon codes. When Hamming codes are used,
this bit should be set to “0”.
Since valid data and ECC are processed differently, the NDFC needs to know whether
valid data or ECC is to be read. This control is implemented by software using this bit.
To read valid data from the NAND Flash, set <RSECGW> to “0”. To read ECC written in
the redundant area in the NAND Flash, set <RSECGW> to “1”.
Note 1: Valid data and ECC cannot be read continuously by DMA transfer. After valid data has been read, DMA
transfer should be stopped once to change the <RSECGW> bit from “0” to “1” before ECC can be read.
Note 2: Immediately after ECC is read from the NAND Flash, the NAND Flash access operation or error bit
calculation cannot be performed for a duration of 20 system clocks (fSYS). It is necessary to insert 20 NOP
instructions or the like.
(g) <RSESTA>
The <RSESTA> bit is used only for Reed-Solomon codes.
The error address and error bit position are calculated using an intermediate code
generated from the ECC for written data and the ECC for read data. Setting <RSESTA> to
“1” starts this calculation.
(h) <RSEDN>
The <RSEDN> bit is used only for Reed-Solomon codes. When using Hamming codes, this
bit should be set to “0”.
For a write operation, this bit should be set to “0” (encode) to generate ECC. The ECC
read from the NDECCRDn register is written to the redundant area in the NAND Flash.
For a read operation, this bit should be set to “1” (decode). In this case, valid data is read
from the NAND Flash and the ECC written in the redundant area is also read to generate
an intermediate code for calculating the error address and error bit position.
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(i) <RSECCL>
The <RSECCL> bit is used only for Reed-Solomon codes. When using Hamming codes,
this bit should be set to “0”.
The Reed-Solomon processing unit is comprised of two elements: an ECC generator and
an ECC calculator. The latter is used to calculate the error address and error bit position.
The error address and error bit position are calculated using an intermediate code
generated from the ECC for written data and the ECC for read data. At this time, no special
care is needed if ECC generation and error calculation are performed serially. If these
operations need to be performed parallely, the intermediate code used for error calculation
must be latched while the calculation is being performed. The <RSECCL> bit is provided to
enable this latch operation.
When <RSECCL> is set to “1”, the intermediate code is latched so that the ECC
generator can generate the ECC for another page without problem while the ECC
calculator is calculating the error address and error bit position. At this time, the ECC
generator can perform both encode (write) and decode (read) operations.
When <RSECCL> is set to “0”, the latch is released and the contents of the ECC
calculator are updated as the data in the ECC generator is updated.
Reed-Solomon
ECC
Generator
NDECCRDn
Register
Flow of data
F/F 80bit
<RSECCL>=1 Latch_ON
<RSECCL>=0 Latch_OFF
Reed-Solomon
ECC
Calculator
(j) <SPHW1:0>
The <SPHW1:0> bits are used for both Hamming and Reed-Solomon codes.
These bits are used to specify the High width of the NDRE and NDWE signals. The High
width to be inserted is obtained by multiplying the value set in these bits by f SYS.
(k) <SPLW1:0>
The <SPLW1:0> bits are used for both Hamming and Reed-Solomon codes.
These bits are used to specify the Low width of the NDRE and NDWE signals. The Low
width to be inserted is obtained by multiplying the value set in these bits by fSYS.
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NAND Flash Control 1 Register
7
6
5
4
3
2
1
ECCS
R/W
0
0
NDFMCR1
(08C2H)
bit Symbol
Read/Write
After reset
INTERDY
R/W
INTRSC
R/W
BUSW
R/W
SYSCKE
R/W
0
0
0
0
Clock
control
Ready
interrupt
Reed-
Solomon
calculation
Data bus
width
ECC
calculation
0: Disable end
1: Enable interrupt
0: Disable
0: 8-bit
1: 16-bit
Function
0: Disable
1: Enable
0:Hamming
1: Reed-
1: Enable
Solomon
15
14
13
12
11
10
9
8
(08C3H)
bit Symbol
Read/Write
After reset
Function
STATE3
STATE2
STATE1
STATE0
SEER1
SEER0
R
0
0
0
0
Undefined Undefined
Status read (See the table below.)
Table 3.11.2 Reed-Solomon Calculation Result Status Table
STATE<3:0>
0000
Meaning
Calculation ended 0 (No error)
0001
Calculation ended 1(5 or more symbols in error; not correctable)
0010
Calculation ended 2 (Error found)
0011
0100~1111
Calculation in progress
Note: The <STATE3:0> value becomes effective after the calculation has started.
SEER<1:0>
Meaning
1-address error
2-address error
3-address error
4-address error
00
01
10
11
Note: The <SEER1:0> value becomes effective after the calculation has ended.
(a) <SYSCKE>
The <SYSCKE> bit is used for both Hamming and Reed-Solomon codes.
When using the NDFC, this bit must be set to “1” to enable the system clock. When not
using the NDFC, power consumption can be reduced by setting this bit to “0”.
(b) <ECCS>
The <ECCS> bit is used to select whether to use Hamming codes or Reed-Solomon codes.
This bit is set to “0” for using Hamming codes and to “1” for using Reed-Solomon codes. It
is also necessary to set this bit for clearing ECC.
(c) <BUSW>
The <BUSW> bit is used for both Hamming and Reed-Solomon codes.
This bit specifies the bus width of the NAND Flash to be accessed (“0” = 8 bits, “1” = 16
bits). No other setting is required in the memory controller.
(d) <INTRSC>
The <INTRSC> bit is used only for Reed-Solomon codes. When using Hamming codes,
this bit should be set to “0”.
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This bit is used to enable or disable the interrupt to be generated when the calculation of
error address and error bit position has ended.
The interrupt is enabled when this bit is set to “1” and disabled when “0”.
(e) <INTRDY>
The <INTRDY> bit is used for both Hamming and Reed-Solomon codes.
This bit is used to enable or disable the interrupt to be generated when the status of the
NDR/B pin of the NAND Flash changes from “busy” (0) to “ready” (1). The interrupt is
enabled when this bit is set to “1” and disabled when “0”.
(f) <STATE3:0>、<SEER1:0>
The <STATE3:0> and <SEER1:0> bits are used only for Reed-Solomon codes. When using
Hamming codes, they have no meaning.
These bits are used as flags to indicate the result of error address and error bit
calculation. For details, see Table 3.11.2.
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NAND Flash Data Register 0
7
6
5
4
3
2
1
0
NDFDTR0
(1FF0H)
bit Symbol
Read/Write
After reset
Function
D7
D6
D5
D4
D3
D2
D1
D0
R/W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
NAND Flash Data Register (7-0)
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
Function
D15
D14
D13
D12
D11
D10
D9
D8
(1FF1H)
R/W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
NAND Flash Data Register (15-8)
NAND Flash Data Register 1
7
6
5
4
3
2
1
0
NDFDTR1
(1FF2H)
bit Symbol
Read/Write
After reset
Function
D7
D6
D5
D4
D3
D2
D1
D0
R/W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
NAND Flash Data Register (7-0)
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
Function
D15
D14
D13
D12
D11
D10
D9
D8
(1FF3H)
R/W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
NAND Flash Data Register (15-8)
Note: Although these registers allow both read and write operations, no flip-flop is incorporated. Since write and
read operations are performed in different manners, it is not possible to read out the data that has been just
written.
Figure 3.11.6 NAND Flash Data Registers (NDFDTR0, NDFDTR1)
Write and read operations to and from the NAND Flash memory are performed by
accessing the NDFDTR0 register. When you write to this register, the data is written to the
NAND Flash. When you read from this register, the data is read from the NAND Flash.
The NDFDTR0 register is used for both channel 0 and channel 1.
A total of 4 bytes are provided as data registers to enable 4-byte DMA transfer. For
example, 4 bytes of data can be transferred from 32-bit internal RAM to 8-bit NAND Flash
memory by DMA operation by setting the destination address as NDFDTR0. (NDFDTR1
cannot be set as the destination address.) The actual DMA operation is performed by first
reading 4 bytes from the internal RAM and then writing 1 byte to the NAND Flash four
times from the lowest address.
To access data in the NAND Flash, be sure to access NDFDTR0 (at address 1FF0). For
details, see Table 3.11.3.
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Table 3.11.3 How to Access the NAND Flash Data Register
Write
Access Data Size
Example of instruction
8-bit NAND Flash
16-bit NAND Flash
1-byte access
2-byte access
4-byte access
ld (0x1FF0),a
Supported
Supported
Supported
Not supported
Supported
ld (0x1FF0),wa
ld (0x1FF0),xwa
Supported
Read
Access Data Size
Example of instruction
8-bit NAND Flash
16-bit NAND Flash
1-byte access
2-byte access
4-byte access
ld a,(0x1FF0)
Supported
Supported
Supported
Not supported
Supported
ld wa,(0x1FF0)
ld xwa,(0x1FF0)
Supported
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0
NAND Flash ECC Register 0
7
6
5
4
3
2
1
bit Symbol
Read/Write
After reset
Function
ECCD7
ECCD6
ECCD5
ECCD4
ECCD3
ECCD2
ECCD1
ECCD0
NDECCRD0
(08C4H)
R
0
0
0
0
0
0
0
0
NAND Flash ECC Register (7-0)
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
Function
ECCD15
ECCD14
ECCD13
ECCD12
ECCD11
ECCD10
ECCD9
ECCD8
R
(08C5H)
0
0
0
0
0
0
0
0
NAND Flash ECC Register (15-8)
NAND Flash ECC Register 1
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
ECCD7
ECCD6
ECCD5
ECCD4
ECCD3
ECCD2
ECCD1
ECCD0
NDECCRD1
(08C6H)
R
0
0
0
0
0
0
0
0
NAND Flash ECC Register (7-0)
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
Function
ECCD15
ECCD14
ECCD13
ECCD12
ECCD11
ECCD10
ECCD9
ECCD8
R
(08C7H)
0
0
0
0
0
0
0
0
NAND Flash ECC Register (15-8)
NAND Flash ECC Register 2
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
ECCD7
ECCD6
ECCD5
ECCD4
ECCD3
ECCD2
ECCD1
ECCD0
NDECCRD2
(08C8H)
R
0
0
0
0
0
0
0
0
NAND Flash ECC Register (7-0)
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
Function
ECCD15
ECCD14
ECCD13
ECCD12
ECCD11
ECCD10
ECCD9
ECCD8
(08C9H)
R
0
0
0
0
0
0
0
0
NAND Flash ECC Register (15-8)
NAND Flash ECC Register 3
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
ECCD7
ECCD6
ECCD5
ECCD4
ECCD3
ECCD2
ECCD1
ECCD0
NDECCRD3
(08CAH)
R
0
0
0
0
0
0
0
0
NAND Flash ECC Register (7-0)
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
Function
ECCD15
ECCD14
ECCD13
ECCD12
ECCD11
ECCD10
ECCD9
ECCD8
(08CBH)
R
0
0
0
0
0
0
0
0
NAND Flash ECC Register (15-8)
NAND Flash ECC Register 4
7
6
5
4
3
2
1
0
bit Symbol
ECCD7
ECCD6
ECCD5
ECCD4
ECCD3
ECCD2
ECCD1
ECCD0
NDECCRD4
(08CCH)
Read/Write
After reset
Function
R
0
0
0
0
0
0
0
0
NAND Flash ECC Register (7-0)
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
Function
ECCD15
ECCD14
ECCD13
ECCD12
ECCD11
ECCD10
ECCD9
ECCD8
(08CDH)
R
0
0
0
0
0
0
0
0
NAND Flash ECC Register (15-8)
Figure 3.11.7 NAND Flash ECC Registers
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The NAND Flash ECC register is used to read ECC generated by the ECC generator.
After valid data has been written to or read from the NAND Flash, setting
NDFMCR0<ECCE> to “0” causes the corresponding ECC to be set in this register. (The
ECC in this register is updated when NDFMCR0<ECCE> changes from “1” to “0”.)
When Hamming codes are used, 22 bits of ECC are generated for up to 256 bytes of valid
data. In the case of Reed-Solomon codes, 80 bits of ECC are generated for up to 518 bytes of
valid data. A total of 80 bits of registers are provided, arranged as five 16-bit registers.
These registers must be read in 16-bit units and cannot be accessed in 32-bit units.
After ECC calculation has completed, in the case of Hamming codes, the 16-bit line
parity for the first 256 bytes is stored in the NDECCRD0 register, the 6-bit column parity
for the first 256 bytes in the NDECCRD1 register (<ECCE7:2>), the 16-bit line parity for
the second 256 bytes in the NDECCRD2 register, and the 6-bit column parity for the second
256 bytes in the NDECCRD3 register (<ECCD7:2>). In this case, the NDECCRD4 register
is not used.
In the case of Reed-Solomon codes, 80 bits of ECC are stored in the NDECCRD0,
NDECCRD1, NDECCRD2, NDECCRD3 and NDECCRD4 registers.
Note: Before reading ECC from the NAND Flash ECC register, be sure to set NDFMCR0<ECCE> to “0”.
The ECC in the NAND Flash ECC register is updated when NDFMCR0<ECCE> changes from “1” to
“0”. Also note that when the ECC in the ECC generator is reset by NDFMCR0<ECCRST>, the
contents of this register are not reset.
Register Name
NDECCRD0
Hamming
Reed-Solomon
[15:0] Line parity
(for the first 256 bytes)
[7:2] Column parity
(for the first 256 bytes)
[15:0] Line parity
[15:0]
Reed-Solomon ECC code 79:64
[15:0]
NDECCRD1
NDECCRD2
NDECCRD3
NDECCRD4
Reed-Solomon ECC code 63:48
[15:0]
(for the second 256 bytes)
[7:2] Column parity
(for the second 256 bytes)
Not in use
Reed-Solomon ECC code 47:32
[15:0]
Reed-Solomon ECC code 31:16
[15:0]
Reed-Solomon ECC code 15:0
The table below shows an example of how ECC is written to the redundant area in the
NAND Flash memory when using Reed-Solomon codes.
When using Hamming codes with SmartMedia™, the addresses of the redundant area
are specified by the physical format of SmartMedia™. For details, refer to the
SmartMedia™ Physical Format Specifications.
Register Name
NDECCRD0
Reed-Solomon
NAND Flash Address
[15:0]
Reed-Solomon ECC code 79:64
[15:0]
Upper 8 bits [79:72]→ address 518
Lower 8 bits [71:64] → address 519
Upper 8 bits [63:56] → address 520
Upper 8 bits [55:48] → address 521
Upper 8 bits [47:40] → address 522
Lower 8 bits [39:32] → address 523
Upper 8 bits [31:24] → address 524
Lower 8 bits [23:16] → address 525
Upper 8 bits [15:8] → address 526
Lower 8 bits [7:0] → address 527
NDECCRD1
NDECCRD2
NDECCRD3
NDECCRD4
Reed-Solomon ECC code 63:48
[15:0]
Reed-Solomon ECC code 47:32
[15:0]
Reed-Solomon ECC code 31:16
[15:0]
Reed-Solomon ECC code 15:0
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0
NAND Flash Reed-Solomon Calculation Result Address Register
7
6
5
4
3
2
1
NDRSCA0
(08D0H)
bit Symbol
Read/Write
After reset
Function
RS0A7
RS0A6
RS0A5
RS0A4
RS0A3
RS0A2
RS0A1
RS0A0
R
0
0
0
0
0
0
0
0
NAND Flash Reed-Solomon Calculation Result Address Register (7-0)
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
RS0A9
RS0A8
(08D1H)
R
0
0
NAND Flash
Reed-Solomon
Function
Calculation Result
Address Register (9-8)
7
6
5
4
3
2
1
0
NDRSCA1
(08D4H)
bit Symbol
Read/Write
After reset
Function
RS1A7
RS1A6
RS1A5
RS1A4
RS1A3
RS1A2
RS1A1
RS1A0
R
0
0
0
0
0
0
0
0
NAND Flash Reed-Solomon Calculation Result Address Register (7-0)
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
RS1A9
RS1A8
(08D5H)
R
0
0
NAND Flash Reed-
Solomon Calculation
Result Address
Function
Register (9-8)
7
6
5
4
3
2
1
0
NDRSCA2
(08D8H)
bit Symbol
Read/Write
After reset
Function
RS2A7
RS2A6
RS2A5
RS2A4
RS2A3
RS2A2
RS2A1
RS2A0
R
0
0
0
0
0
0
0
0
NAND Flash Reed-Solomon Calculation Result Address Register (7-0)
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
RS2A9
RS2A8
(08D9H)
R
0
0
NAND Flash Reed-
Solomon Calculation
Result Address
Function
Register (9-8)
7
6
5
4
3
2
1
0
NDRSCA3
(08DCH)
bit Symbol
Read/Write
After reset
Function
RS3A7
RS3A6
RS3A5
RS3A4
RS3A3
RS3A2
RS3A1
RS3A0
R
0
0
0
0
0
0
0
0
NAND Flash Reed-Solomon Calculation Result Address Register (7-0)
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
RS3A9
RS3A8
(08DDH)
R
0
0
NAND Flash Reed-
Solomon Calculation
Result Address
Function
Register (9-8)
Figure 3.11.8 NAND Flash Reed-Solomon Calculation Result Address Register
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If error is found at only one address, the error address is stored in the NDRSCA0 register.
If error is found at two addresses, the NDRSCA0 and NDRSCA1 registers are used to store
the error addresses. In this manner, up to four error addresses can be stored in the
NDRSCA0 to NDRSCA3 registers.
The number of error addresses can be checked by NDFMCR1<SEER1:0>.
NAND Flash Reed-Solomon Calculation Result Data Register
7
6
5
4
3
2
1
0
NDRSCD0
(08D2H)
bit Symbol
Read/Write
After reset
Function
RS0D7
RS0D6
RS0D5
RS0D4
RS0D3
RS0D2
RS0D1
RS0D0
R
0
0
0
0
0
0
0
0
NAND Flash Reed-Solomon Calculation Result Data Register (7-0)
7
6
5
4
3
2
1
0
NDRSCD1
(08D6H)
bit Symbol
Read/Write
After reset
Function
RS1D7
RS1D6
RS1D5
RS1D4
RS1D3
RS1D2
RS1D1
RS1D0
R
0
0
0
0
0
0
0
0
NAND Flash Reed-Solomon Calculation Result Data Register (7-0)
7
6
5
4
3
2
1
0
NDRSCD2
(08DAH)
bit Symbol
Read/Write
After reset
Function
RS2D7
RS2D6
RS2D5
RS2D4
RS2D3
RS2D2
RS2D1
RS2D0
R
0
0
0
0
0
0
0
0
NAND Flash Reed-Solomon Calculation Result Data Register (7-0)
7
6
5
4
3
2
1
0
NDRSCD3
(08DEH)
bit Symbol
Read/Write
After reset
Function
RS3D7
RS3D6
RS3D5
RS3D4
RS3D3
RS3D2
RS3D1
RS3D0
R
0
0
0
0
0
0
0
0
NAND Flash Reed-Solomon Calculation Result Data Register (7-0)
Figure 3.11.9 NAND Flash Reed-Solomon Calculation Result Data Register
If error is found at only one address, the error data is stored in the NDRSCD0 register. If error
is found at two addresses, the NDRSCD0 and NDRSCD1 registers are used to store the error
data. In this manner, the error data at up to four addresses can be stored in the NDRSCD0 to
NDRSCD3 registers.
The number of error addresses can be checked by NDFMCR1<SEER1:0>.
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3.11.5 An Example of Accessing NAND Flash of SLC Type
1. Initialization
;
; ***** Initialize NDFC *****
;
;
Conditions: 8-bit bus, CE0, SLC, 512 (528) bytes/page, Hamming codes
ld
ld
(ndfmcr1),0001h ; 8-bit bus, Hamming ECC, SYSCK-ON
(ndfmcr0),2000h ; SPLW1:0=0, SPHW1:0=2
2. Write
Writing valid data
; ***** Write valid data*****
;
ldw
ldw
ld
(ndfmcr0),2010h ; CE0 enable
(ndfmcr0),20B0h ; WE enable, CLE enable
(ndfdtr0),80h ; Serial input command
(ndfmcr0),20D0h ; ALE enable
ldw
ld
(ndfdtr0),xxh
; Address write (3 or 4 times)
ldw
ld
(ndfmcr0),2095h ; Reset ECC, ECCE enable, CE0 enable
(ndfdtr0),xxh
; Data write (512 times)
Generating ECC →Reading ECC
; ***** Read ECC *****
;
ldw
(ndfmcr0),2010h ; ECC circuit disable
ldw
xxxx,(ndeccrd0) ; Read ECC from internal circuit
;
;
;
;
1’st Read:
D15-0 > LPR15:0
For first 256 bytes
ldw
ldw
ldw
xxxx,(ndeccrd1) ; Read ECC from internal circuit
2’nd Read:
D15-0 > FFh+CPR5:0+11b For first 256 bytes
xxxx,(ndeccrd0) ; Read ECC from internal circuit
3’rd Read:
xxxx,(ndeccrd1) ; Read ECC from internal circuit
4’th Read: D15-0 > FFh+CPR5:0+11b For second 256 bytes
D15-0 > LPR15:0
For second 256 bytes
Writing ECC to NAND Flash
; ***** Write dummy data & ECC*****
;
ldw
ld
(ndfmcr0),2090h ; ECC circuit disable, data write mode
(ndfdtr0),xxh
Write to D520:
Write to D521:
Write to D522:
Write to D525:
Write to D526:
Write to D527:
; Redundancy area data write (16 times)
;
;
;
;
;
;
LPR7:0
> D7-0 For second 256 bytes
LPR15:8
CPR5:0+11b
LPR7:0
> D7-0 For second 256 bytes
> D7-0 For second 256 bytes
> D7-0 For first 256 bytes
> D7-0 For first 256 bytes
> D7-0 For first 256 bytes
LPR15:8
CPR5:0+11b
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Executing page program
; ***** Set auto page program*****
;
ldw
ld
(ndfmcr0),20B0h ; WE enable, CLE enable
(ndfdtr0),10h ; Auto page program command
(ndfmcr0),2010h ; WE disable, CLE disable
ldw
;
;
;
;
;
Wait setup time (from Busy to Ready)
1. Flag polling
2. Interrupt
Reading status
; ***** Read Status*****
;
ldw
ld
(ndfmcr0),20B0h ; WE enable, CLE enable
(ndfdtr0),70h ; Status read command
(ndfmcr0),2010h ; WE disable, CLE disable
xx,(ndfdtr0) ; Status read
ldw
ld
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3. Read
Reading valid data
; ***** Read valid data*****
;
ldw
ldw
ld
(ndfmcr0),2010h ; CE0 enable
(ndfmcr0),20B0h ; WE enable, CLE enable
(ndfdtr0),00h ; Read command
(ndfmcr0),20D0h ; ALE enable
(ndfdtr0),xxh ; Address write (3 or 4 times)
ldw
ld
;
;
;
;
;
Wait setup time (from Busy to Ready)
1. Flag polling
2. Interrupt
ldw
ld
(ndfmcr0),2015h ; Reset ECC, ECCE enable, CE0 enable
xx,(ndfdtr0) ; Data read (512 times)
(ndfmcr0),2010h ; ECC circuit disable
ldw
ld
xx,(ndfdtr0)
xx,(ndfdtr0)
xx,(ndfdtr0)
xx,(ndfdtr0)
; Redundancy data read (8 times)
ld
; ECC data read (3 times)
ld
; Redundancy data read (2 times)
; ECC data read (3 times)
ld
Generating ECC →Reading ECC
; ***** Read ECC *****
;
ldw
ldw
(ndfmcr0),2010h ; ECC circuit disable
xxxx,(ndeccrd0) ; Read ECC from internal circuit
;
;
;
;
1’st Read:
D15-0 > LPR15:0
For first 256 bytes
ldw
ldw
ldw
xxxx,(ndeccrd1) ; Read ECC from internal circuit
2’nd Read:
D15-0 > FFh+CPR5:0+11b For first 256 bytes
xxxx,(ndeccrd0) ; Read ECC from internal circuit
3’rd Read:
xxxx,(ndeccrd1) ; Read ECC from internal circuit
4’th Read: D15-0 > FFh+CPR5:0+11b For second 256 bytes
D15-0 > LPR15:0
For second 256 bytes
Software processing
The ECC data generated for the read operation and the ECC in the
redundant area in the NAND Flash are compared. If any error is found, the
error processing routine is performed to correct the error data. For details,
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4. ID Read
The ID read routine is as follows:
ldw
ld
(ndfmcr0),20B0h ; WE Enable, CLE enable
(ndfdtr0),90h ; Write ID read command
(ndfmcr0),20D0h ; ALE enable, CLE disable
(ndfdtr0),00h ; Write 00
(ndfmcr0),2010h ; WE disable, CLE disable
ldw
ld
ldw
ld
xx,(ndfdtr0)
xx,(ndfdtr0)
; Read 1'st ID maker code
; Read 2'nd ID device code
ld
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3.11.6 An Example of Accessing NAND Flash of MLC Type (When the valid data is processed
as 518byte)
1. Initialization
;
; ***** Initialize NDFC *****
;
;
Conditions: 16-bit bus, CE1, MLC, 2048 (2112) bytes/page, Reed-Solomon codes
ld
ld
(ndfmcr1),0007h ; 16-bit bus, Reed-Solomon ECC, SYSCK-ON
(ndfmcr0),5000h ; SPLW1:0=1, SPHW1:0=1
2. Write
Writing valid data
; ***** Write valid data*****
;
ldw
ldw
ldw
ldw
ldw
ldw
ldw
(ndfmcr0),5008h ; CE1 enable
(ndfmcr0),50A8h ; WE enable, CLE enable
(ndfdtr0),0080h ; serial input command
(ndfmcr0),50C8h ; ALE enable
(ndfdtr0),00xxh ; Address write ( 4 or 5 times)
(ndfmcr0),508Dh ; Reset ECC code, ECCE enable
(ndfdtr0),xxxxh ; Data write (259-times/:518byte)
(256-times/512byte)
Generating ECC →Reading ECC
; ***** Read ECC *****
;
ldw
ldw
ldw
ldw
ldw
(ndfmcr0),5008h ; ECC circuit disable
(ndfmcr0),50A8h ; WE enable, CLE enable
(ndfdtr0),0080h ; serial input command
(ndfmcr0),50C8h ; ALE enable
(ndfdtr0),00xxh ; Address write ( 4 or 5 times)
ldw
ldw
ldw
ldw
ldw
xxxx,(ndeccrd0) ; Read ECC from internal circuit
;
;
;
;
;
Read:
xxxx,(ndeccrd1) ; Read ECC from internal circuit
Read: D63-48
xxxx,(ndeccrd2) ; Read ECC from internal circuit
Read: D47-32
xxxx,(ndeccrd3) ; Read ECC from internal circuit
Read: D31-16
xxxx,(ndeccrd4) ; Read ECC from internal circuit
D79-64
Read:
D15-0
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TMP92CZ26A
Writing ECC to NAND Flash
; ***** Write dummy data & ECC *****
;
ldw
ldw
(ndfmcr0),5088h ; ECC circuit disable, data write mode
(ndfdtr0),xxxxh ; Redundancy area data write
Write to 207-206hex address: > D79-64
(ndfdtr1),xxxxh ; Redundancy area data write
Write to 209-208hex address: > D63-48
(ndfdtr0),xxxxh ; Redundancy area data write
Write to 20B-20Ahex address: > D47-32
(ndfdtr1),xxxxh ; Redundancy area data write
Write to 20D-20Chex address: > D31-16
(ndfdtr0),xxxxh ; Redundancy area data write
Write to 20F-20Ehex address: > D15-0
;
;
;
;
ldw
ldw
ldw
ldw
;
;
;
The write operation is repeated four times to write 2112 bytes.
Executing page program
; ***** Set auto page program*****
;
ldw
ldw
ldw
(ndfmcr0),50A8h ; WE enable, CLE enable
(ndfdtr0),0010h ; Auto page program command
(ndfmcr0),5008h ; WE disable, CLE disable
;
;
;
;
Wait set up time (from Busy to Ready)
1. Flag polling
2. Interrupt
※
In case of LB type NANDF, programming page size is normally each 2112
bytes and ECC calculation is processed each 518 (512) bytes. Please take care
of programming flow. In details, refer the NANDF memory specifications.
Reading status
; ***** Read status*****
;
ldw
ldw
ldw
ldw
(ndfmcr0),50A8h ; WE enable, CLE enable
(ndfdtr0),0070h ; Status read command
(ndfmcr0),5008h ; WE disable, CLE disable
xxxx,(ndfdtr0)
; Status read
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3. Read (including ECC data read)
Reading valid data
; ***** Read valid data*****
;
ldw
ldw
ldw
ldw
ldw
ldw
ldw
(ndfmcr0),5008h ; CE1 enable
(ndfmcr0),50A8h ; WE enable, CLE enable
(ndfdtr0),0000h ; Read command 1
(ndfmcr0),50C8h ; ALE enable
(ndfdtr0),00xxh ; Address write (4 or 5 times)
(ndfmcr0),50A8h ; WE enable, CLE enable
(ndfdtr0),0030h ; Read command 2
;
;
;
;
;
Wait set up time (from Busy to Ready)
1. Flag polling
2. Interrupt
ldw
ldw
(ndfmcr0),540Dh ; ECC reset, ECC circuit enable, decode mode
xxxx,(ndfdtr0)
; Data read (259 times: 518 bytes)
(256-times:512byte)
ldw
ldw
(ndfmcr0),550Ch ; RSECGW enable
xxxx,(ndfdtr0) ; Read ECC (5 times: 80 bits)
;
;
;
Wait set up time (20 system clocks)
(1) Error bit calculation
ldw
ldw
(ndfmcr1),0047h ; Error bit calculation interrupt enable
(ndfmcr0),560Ch ; Error bit calculation circuit start
;
;
Wait set up time
;
Interrupt routine (End of calculation for Reed-Solomon Error bit)
;
INT:
ldw
xxxx,(ndfmcr1)
; Check error status ”STATE3:0, SEER1:0”
;
;
;
;
If error is found, the error processing routine is performed to
Methods”.
;
;
;
The read operation is repeated four times to read 2112 bytes.
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4. ID Read
The ID read routine is as follows:
ldw
ldw
ldw
ldw
ldw
ldw
ldw
(ndfmcr0),50A8h ; WE enable, CLE enable
(ndfdtr0),0090h ; Write ID read command
(ndfmcr0),50C8h ; ALE enable, CLE disable
(ndfdtr0),0000h ; Write 00
(ndfmcr0),5008h ; WE disable, CLE disable
xxxx,(ndfdtr0)
xxxx,(ndfdtr1)
; Read 1'st ID maker code
; Read 2'ndID device code
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3.11.7 An Example of Connections with NAND Flash
TMP92CZ26A
NAND Flash 0
NAND Flash 1
CLE
100KΩ
NDCLE
NDALE
CLE
ALE
ALE
NDRE
NDWE
RE
WE
RE
WE
2KΩ
NDR/B
D[15:0]
R/B (open drain)
I/O[15:0]
R/B (open drain)
I/O[7:0]
CE
WP
CE
WP
ND0CE
ND1CE
External circuits for Write Protect
Note 1: A reset sets the
and
pins as input ports, so pull-up resistors are needed.
NDWE
NDRE
Note 2: The pull-up resistor value for the NDR/B pin must be set appropriately according to the NAND Flash memory to be used and the
capacity of the board (typical: 2 KΩ).
Note 3: The
(Write Protect) pin of NAND Flash is not supported. When this function is needed, prepare it on an external circuit.
WP
Figure 3.11.10 An Example of Connections with NAND Flash
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3.12
8 Bit Timer (TMRA)
The TMP92CZ26A features 8 channel (TMRA0 to TMRA7) built-in 8-bit timers.
These timers are paired into 4 modules: TMRA01, TMRA23, TMRA45 and TMRA67. Each
module consists of 2 channels and can operate in any of the following 4 operating modes.
•
8-bit interval timer mode
16-bit interval timer mode
•
•
8-bit programmable square wave pulse generation output mode (PPG: Variable duty cycle
with variable period)
•
8-bit pulse width modulation output mode (PWM – Variable duty cycle with constant
period)
Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register.
In addition, a timer flip-flop and a prescaler are provided for each pair of channels.
The operation mode and timer flip-flops are controlled by 5bytes registers SFRs
(Special-function registers).
Each of the 4 modules (TMRA01 to TMRA67) can be operated independently. All modules
operate in the same manner; hence only the operation of TMRA01 is explained here.
The contents of this chapter are as follows.
Table 3.12.1 Registers and Pins for Each Module
Module
TMRA01
TMRA23
TMRA45
TMRA67
Specification
Input pin for external
TA0IN
TA2IN
Low-frequency clock
fs
Low-frequency clock
fs
External
pin
clock
(Shared with PC1)
TA1OUT
(Shared with PC3)
TA3OUT
Output pin for timer
flip-flop
TA5OUT
TA7OUT
(Shared with PM1)
TA01RUN (1100H)
TA0REG (1102H)
TA1REG (1103H)
TA01MOD (1104H)
(Shared with PP1)
TA23RUN (1108H)
TA2REG (110AH)
TA3REG (110BH)
TA23MOD (110CH)
(Shared with PP2)
TA45RUN (1110H)
TA4REG (1112H)
TA5REG (1113H)
TA45MOD (1114H)
(Shared with PP3)
TA67RUN (1118H)
TA6REG (111AH)
TA7REG (111BH)
TA67MOD (111CH)
Timer run register
Timer register
SFR
(Address)
Timer mode register
Timer flip-flop
TA1FFCR (1105H)
TA3FFCR (110DH)
TA5FFCR (1115H)
TA7FFCR (111DH)
control register
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Figure 3.12.2 TMRA23 Block Diagram
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Figure 3.12.3 TMRA45 Block Diagram
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3.12.2 Operation of Each Circuit
(1) Prescaler
A 9-bit prescaler generates the input clock to TMRA01.The clock φT0 is selected
using the prescaler clock selection register SYSCR0<PRCK>.
The prescaler operation can be controlled using TA01RUN<TA0PRUN> in the timer
control register. Setting <TA0PRUN> to 1 starts the count; setting <TA0PRUN> to 0
clears the prescaler to 0 and stops operation. Table shows the various prescaler output
clock resolutions.
(Although the prescaler and the timer counter can be started separately, the timer
counter’s operation depends on the prescaler’s input timing.)
Table 3.12.2 Prescaler Output Clock Resolution
Clock gear
selection
Prescaler of
clock gear
SYSCR0
Timer counter input clock
Prescaler of TMRA
−
SYSCR1
TAxxMOD<TAxCLK1:0>
<GEAR2:0>
<PRCK>
φT1(1/2)
fc/8
φT4(1/8)
fc/32
φT16(1/32) φT256(1/512)
000(1/1)
001(1/2)
010(1/4)
011(1/8)
100(1/16)
000(1/1)
001(1/2)
010(1/4)
011(1/8)
100(1/16)
fc/128
fc/256
fc/2048
fc/4096
fc/16
fc/64
0(1/2)
1(1/8)
fc/32
fc/128
fc/256
fc/512
fc/128
fc/256
fc/512
fc/1024
fc/2048
fc/512
fc/8192
fc/64
fc/1024
fc/2048
fc/512
fc/16384
fc/32768
fc/8192
fc/128
fc/32
fc
1/2
fc/64
fc/1024
fc/2048
fc/4096
fc/8192
fc/16384
fc/32768
fc/65536
fc/131072
fc/128
fc/256
fc/512
(2) Up counters (UC0 and UC1)
These are 8-bit binary counters which count up the input clock pulses for the clock
specified by TA01MOD.
The input clock for UC0 is selectable and can be either the external clock input via
the TA0IN pin or one of the three internal clocks φT1, φT4 or φT16. The clock setting is
specified by the value set in TA01MOD<TA01CLK1:0>.
The input clock for UC1 depends on the operation mode. In 16-bit timer mode, the
overflow output from UC0 is used as the input clock. In any mode other than 16-bit
timer mode, the input clock is selectable and can either be one of the internal clocks
φT1, φT16 or φT256, or the comparator output (The match detection signal) from
TMRA0.
For each interval timer the timer operation control register bits TA01RUN
<TA0RUN> and TA01RUN<TA1RUN> can be used to stop and clear the up counters
and to control their count. A reset clears both up counters, stopping the timers.
Note: TMR45 and TMR67 can select low-frequency clock(fs) instead of external clock input.
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(3) Timer registers (TA0REG and TA1REG)
These are 8-bit registers, which can be used to set a time interval. When the value
set in the timer register TA0REG or TA1REG matches the value in the corresponding
up counter, the comparator match detect signal goes active. If the value set in the
timer register is 00H, the signal goes active when the up counter overflows.
The TA0REG are double buffer structure, each of which makes a pair with register
buffer.
The setting of the bit TA01RUN<TA0RDE> determines whether TA0REG’s double
buffer structure is enabled or disabled. It is disabled if <TA0RDE> = 0 and enabled if
<TA0RDE> = 1.
When the double buffer is enabled, data is transferred from the register buffer to the
timer register when a 2n overflow occurs in PWM mode, or at the start of the PPG cycle
in PPG mode. Hence the double buffer cannot be used in timer mode.
(When using the double buffer, method of renewing timer register is only overflow in
PWM mode or frequency agreement in PPG mode.)
A reset initializes <TA0RDE> to 0, disabling the double buffer. To use the double
buffer, write data to the timer register, set <TA0RDE> to 1, and write the following
Timer registers 0 (TA0REG)
Matching detection PPG cycle
B
2n overflow of PWM
Shift trigger
Selector
S
A
Write to TA0REG
Register buffer 0
Write
TA01RUN<TA0RDE>
Internal data bus
Figure 3.12.5 Configuration of timer register (TA0REG)
Note: The same memory address is allocated to the timer register and the register buffer 0. When
<TA0RDE> = 0, the same value is written to the register buffer 0 and the timer register;
when <TA0RDE> = 1, only the register buffer 0 is written to.
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(4) Comparator (CP0, CP1)
The comparator compares the value in an up counter with the value set in a timer
register. If they match, the up counter is cleared to 0 and an interrupt signal (INTTA0
or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is
inverted at the same time.
Note: If a value smaller than the up-counter value is written to the timer register while the timer is counting up, this will
cause the timer to overflow and an interrupt cannot be generated at the expected time. (The value in the timer
register canbe changed without any problem if the new value is larger than the up-counter value.) In 16-bit
interval timer mode, be sure to write to both TA0REG and TA1REG in this order (16 bits in total), The compare
circuit will not function if only the lower 8 bits are set.
(5) Timer flip-flop (TA1FF)
The timer flip-flop (TA1FF) is a flip-flop inverted by the match detects signal (8-bit
comparator output) of each interval timer.
Whether inversion is enabled or disabled is determined by the setting of the bit
TA1FFCR<TA1FFIE> in the timer flip-flops control register. A reset clears the value
of TA1FF to 0. Writing 01 or 10 to TA1FFCR<TA1FFC1:0> sets TA1FF to 0 or 1.
Writing 00 to these bits inverts the value of TA1FF. (This is known as software
inversion.)
The TA1FF signal is output via the TA1OUT pin. When this pin is used as the timer
output, the timer flip-flop should be set beforehand using the port function registers.
The condition for TA1FF inversion varies with mode as shown below
8-bit interval timer mode
: UC0 matches TA0REG or UC1 matches TA1REG
(Select either one of the two)
16-bit interval timer mode
80bit PWM mode
: UC0 matches TA0REG or UC1 matches TA1REG
n
: UC0 matches TA0REG or a 2 overflow occurs
8-bit PPG mode
: UC0 matches TA0REG or UC0 matches TA1REG
Note: If an inversion by the match-detect signal and a setting change via the TMRA1 flip-flopcontrol register occur
simultaneously, the resultant operation varies depending on the situation, as shown below.
・
・
・
If an inversion by the match-detect signal and an inversion via the register occur simultaneously, the
flip-flop will be inverted only once.
If an inversion by the match-detect signal and an attempt to set the flip-flop to 1 via the register occur
simultaneously, the timer flip-flop will be set to 1.
If an inversion by the match-detect signal and an attempt to clear the flip-flop to 0 via the register occur
simultaneously the flip-flop will be cleared to 1.
Be sure to stop the timer before changing the flip-flop incersion setting.
If the setting is chaged while the timer is counting, proper operation cannot be obtained.
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3.12.3 SFR
TMRA01 RUN Register
7
6
5
4
3
2
1
0
Bit symbol
Read/Write
After Reset
Function
TA0RDE
R/W
I2TA01
TA01PRUN
TA1RUN
TA0RUN
TA01RUN
(1100H)
R/W
0
0
In IDLE2
mode
0
0
0
TMRA01
prescaler
Up counter Up counter
(UC1) (UC0)
Double
buffer
0: Disable
1: Enable
0: Stop
1: Operate
0: Stop and clear
1: Run (Count up)
TA0REG double buffer control
Count control
0
1
Disable
Enable
0
1
Stop and clear
Run (Count up)
Note: The values of bits 4 to 6 of TA01RUN are “1” when read.
TMRA23 RUN Register
7
6
5
4
3
2
1
0
Bit symbol
Read/Write
After Reset
Function
TA2RDE
R/W
I2TA23
TA23PRUN
TA3RUN
TA2RUN
TA23RUN
(1108H)
R/W
0
0
In IDLE2
mode
0
0
0
TMRA23
prescaler
Up counter Up counter
(UC3) (UC2)
Double
buffer
0: Disable
1: Enable
0: Stop
1: Operate
0: Stop and clear
1: Run (Count up)
TA3REG double buffer control
Count control
0
1
Disable
Enable
0
1
Stop and clear
Run (Count up)
Note: The values of bits 4 to 6 of TA23RUN are “1” when read.
Figure 3.12.6 Register for TMRA (1)
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TMRA45 RUN Register
7
6
5
4
3
2
1
0
Bit symbol
Read/Write
After Reset
Function
TA4RDE
R/W
I2TA45
TA45PRUN TA5RUN
TA4RUN
TA45RUN
(1110H)
R/W
0
0
In IDLE2
mode
0
0
0
TMRA45
prescaler
Up counter Up counter
(UC5) (UC4)
Double
buffer
0: Disable
1: Enable
0: Stop
1: Operate
0: Stop and clear
1: Run (Count up)
TA4REG double buffer control
Count control
0
1
Disable
Enable
0
1
Stop and clear
Run (Count up)
Note: The values of bits 4 to 6 of TA45RUN are “1” when read.
TMRA67RUN Register
7
6
5
4
3
2
1
0
Bit symbol
Read/Write
After Reset
Function
TA6RDE
R/W
I2TA67
TA67PRUN TA7RUN
TA6RUN
TA67RUN
(1118H)
R/W
0
0
In IDLE2
mode
0
0
0
TMRA67
prescaler
Up counter Up counter
(UC7) (UC6)
Double
buffer
0: Disable
1: Enable
0: Stop
1: Operate
0: Stop and clear
1: Run (Count up)
TA6REG double buffer control
Count control
0
1
Disable
enable
0
1
Stop and clear
Run (Count up)
Note: The values of bits 4 to 6 of TA67RUN are “1” when read.
Figure 3.12.7 Register for TMRA (2)
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0
TMRA01 Mode Register
7
6
5
4
3
2
1
TA01MOD
(1104H)
Bit symbol
Read/Write
After reset
Function
TA01M1
TA01M0
PWM01
PWM00
TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0
R/W
0
0
0
0
0
0
0
0
Operation mode
PWM cycle
00: Reserved
01: 26
Source clock for TMRA1
00: TA0TRG
01: φT1
Source clock for TMRA0
00: TA0IN pin
01: φT1
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode
10: 27
10: φT16
10: φT4
11: 28
11: φT256
11: φT16
TMRA0 input clock
<TA0CLK1:0>
00
01
10
11
TA0IN (External input)
φT1
φT4
φT16
TMRA1 input clock
<TA1CLK1:0>
TA01MOD<TA01M1:0>≠01 TA01MOD<TA01M1:0>=01
00
Comparator output
from TMRA0
Overflow output from TMRA0
01
10
11
φT1
(16-bit timer mode)
φT16
φT256
PWM cycle selection
<PWM01:00>
00
01
10
11
Reserved
26 × Clock source
27 × Clock source
28 × Clock source
TMRA01 operation mode selection
00
01
8 timer × 2ch
16-bit timer
<TA01MA1:0>
10
11
8-bit PPG
8-bit PWM (TMRA0),
8-bit timer (TMRA1)
Figure 3.12.8 Register for TMRA (4)
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0
TMRA23 Mode Register
7
6
5
4
3
2
1
TA23MOD
(110CH)
Bit symbol
Read/Write
After reset
Function
TA23M1
TA23M0
PWM21
PWM20
TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0
R/W
0
0
0
0
0
0
0
0
Operation mode
PWM cycle
00: Reserved
01: 26
10: 27
11: 28
TMRA3 clock for TMRA3
00: TA2TRG
01: φT1
TMRA2 clock for TMRA2
00: TA2IN pin
01: φT1
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode
10: φT16
10: φT4
11: φT256
11: φT16
TMRA2 input clock
00
01
10
11
TA2IN (External input)
φT1
<TA2CLK1:0>
φT4
φT16
TMRA3 input clock
TA23MOD<TA23M1:0>≠01 TA23MOD<TA23M1:0>=01
00
Comparator output
from TMRA2
Overflow output from TMRA2
<TA3CLK1:0>
01
10
11
φT1
(16-bit timer mode)
φT16
φT256
PWM cycle selection
<PWM21:20>
00
01
10
11
Reserved
26 × Clock source
27 × Clock source
28 × Clock source
TMRA23 operation mode selection
00
01
8 timer × 2ch
16-bit timer
<TA23MA1:0>
10
11
8-bit PPG
8-bit PWM (TMRA2),
8-bit timer (TMRA3)
Figure 3.12.9 Register for TMRA (5)
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0
TMRA45 Mode Register
7
6
5
4
3
2
1
TA45MOD
(1114H)
Bit symbol
Read/Write
After reset
Function
TA45M1
TA45M0
PWM41
PWM40
TA5CLK1 TA5CLK0 TA4CLK1 TA4CLK0
R/W
0
0
0
0
0
0
0
0
Operation mode
PWM cycle
00: Reserved
01: 26
10: 27
11: 28
TMRA5 clock for TMRA5
00: TA4TRG
01: φT1
TMRA4 clock for TMRA4
00: low-frequency clock
01: φT1
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode
10: φT16
10: φT4
11: φT256
11: φT16
TMRA4 input clock
<TA4CLK1:0>
00
01
10
11
low-frequency clock(fs)
φT1
φT4
φT16
TMRA5 input clock
TA45MOD<TA45M1:0>≠01 TA45MOD<TA45M1:0>=01
00
Comparator output
from TMRA4
Overflow output from TMRA4
<TA5CLK1:0>
01
10
11
φT1
(16-bit timer mode)
φT16
φT256
PWM cycle selection
<PWM41:40>
00
01
10
11
Reserved
26 × Clock source
27 × Clock source
28 × Clock source
TMRA45 operation mode selection
00
01
8 timer × 2ch
16-bit timer
<TA45MA1:0>
10
11
8-bit PPG
8-bit PWM (TMRA4),
8-bit timer (TMRA5)
Figure 3.12.10 Register for TMRA (6)
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0
TMRA67 Mode Register
7
6
5
4
3
2
1
TA67MOD
(111CH)
Bit symbol
Read/Write
After reset
Function
TA67M1
TA67M0
PWM61
PWM60
TA7CLK1 TA7CLK0 TA6CLK1 TA6CLK0
R/W
0
0
0
0
0
0
0
0
Operation mode
PWM cycle
00: Reserved
01: 26
10: 27
11: 28
TMRA7 clock for TMRA7
00: TA6TRG
01: φT1
TMRA6 clock for TMRA6
00: low-frequency clock
01: φT1
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode
10: φT16
10: φT4
11: φT256
11: φT16
TMRA6 input clock
00
01
10
11
low-frequency clock(fs)
φT1
<TA6CLK1:0>
φT4
φT16
TMRA1 input clock
TA67MOD<TA67M1:0>≠01 TA67MOD<TA67M1:0>=01
00
Comparator output
from TMRA6
Overflow output from TMRA6
<TA7CLK1:0>
01
10
11
φT1
(16-bit timer mode)
φT16
φT256
PWM cycle selection
<PWM61:60>
00
01
10
11
Reserved
26 × Clock source
27 × Clock source
28 × Clock source
TMRA67 operation mode selection
00
01
8 timer × 2ch
16-bit timer
<TA67MA1:0>
10
11
8-bit PPG
8-bit PWM (TMRA6),
8-bit timer (TMRA7)
Figure 3.12.11 Register for TMRA (7)
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TMRA1 Flip-Flop Control Register
7
6
5
4
3
2
1
0
TA1FFCR
(1105H)
Bit symbol
Read/Write
After reset
Function
TA1FFC1 TA1FFC0 TA1FFIE
TA1FFIS
R/W R/W
1
1
0
0
TA1FF
00: Invert TA1FF
01: Set TA1FF
10: Clear TA1FF
11: Don’t care
TA1FF
Read-
control for inversion
inversion select
modify-
write
0: Disable 0: TMRA0
1: Enable 1: TMRA1
instructions
are
prohibited.
Inversion signal for timer flip-flop 1 (TA1FF)
(Don’t care except in 8-bit timer mode)
0
1
Inversion by TMRA0
Inversion by TMRA1
TA1FFIS
Inversion of TA1FF
0
1
Disabled
Enabled
TA1FFIE
Control of TA1FF
00
01
10
11
Inverts the value of TA1FF (Software inversion)
Sets TA1FF to “1”
<TA1FFC1:0>
Clears TA1FF to “0”
Don’t care
Note: The values of bits 4 to 6 of TA1FFCR are “1” when read.
Figure 3.12.12 Register for TMRA (8)
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TMRA3 Flip-Flop Control Register
7
6
5
4
3
2
1
0
TA3FFCR
(110DH)
Bit symbol
Read/Write
After reset
Function
TA3FFC1 TA3FFC0 TA3FFIE
TA3FFIS
R/W R/W
1
1
0
0
Read-
modify-
write
00: Invert TA3FF
01: Set TA3FF
10: Clear TA3FF
11: Don’t care
TA3FF
TA3FF
control for inversion
inversion select
instructions
are
0: Disable 0: TMRA2
1: Enable 1: TMRA3
prohibited.
Inversion signal for timer flip-flop 3 (TA3FF)
(Don’t care except in 8-bit timer mode)
0
1
Inversion by TMRA2
Inversion by TMRA3
TA3FFIS
Inversion of TA3FF
0
1
Disabled
Enabled
TA3FFIE
Control of TA3FF
00
01
10
11
Inverts the value of TA3FF (Software inversion)
Sets TA3FF to “1”
<TA3FFC1:0>
Clears TA3FF to “0”
Don’t care
Note: The values of bits 4 to 6 of TA3FFCR are “1” when read.
Figure 3.12.13 Register for TMRA (9)
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TMRA5 Flip-Flop Control Register
7
6
5
4
3
2
1
0
TA5FFCR
(1115H)
Bit symbol
Read/Write
After reset
Function
TA5FFC1 TA5FFC0 TA5FFIE
TA5FFIS
R/W R/W
1
1
0
0
00: Invert TA5FF
01: Set TA5FF
10: Clear TA5FF
11: Don’t care
TA5FF
TA5FF
Read-
control for inversion
inversion select
modify-
write
0: Disable 0: TMRA4
1: Enable 1: TMRA5
instructions
are
prohibited.
Inversion signal for timer flip-flop 5 (TA5FF)
(Don’t care except in 8-bit timer mode)
0
1
Inversion by TMRA4
Inversion by TMRA5
TA5FFIS
Inversion of TA5FF
0
1
Disabled
Enabled
TA5FFIE
Control of TA5FF
00
01
10
11
Inverts the value of TA5FF (Software inversion)
Sets TA5FF to “1”
<TA5FFC1:0>
Clears TA5FF to “0”
Don’t care
Note: The values of bits 4 to 6 of TA5FFCR are “1” when read.
Figure 3.12.14 Register for TMRA (10)
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TMRA7 Flip-Flop Control Register
7
6
5
4
3
2
1
0
TA7FFCR
(111DH)
Bit symbol
Read/Write
After reset
Function
TA7FFC1 TA7FFC0 TA7FFIE
TA7FFIS
R/W R/W
1
1
0
0
00: Invert TA7FF
01: Set TA7FF
10: Clear TA7FF
11: Don’t care
TA7FF
TA7FF
Read-
control for inversion
inversion select
modify-
write
0: Disable 0: TMRA6
1: Enable 1: TMRA7
instructions
are
prohibited.
Inversion signal for timer flip-flop 7 (TA7FF)
(Don’t care except in 8-bit timer mode)
0
1
Inversion by TMRA6
Inversion by TMRA7
TA7FFIS
Inversion of TA7FF
TA7FFIE
0
1
Disabled
Enabled
Control of TA7FF
00
01
10
11
Inverts the value of TA7FF (Software inversion)
Sets TA7FF to “1”
<TA7FFC1:0>
Clears TA7FF to “0”
Don’t care
Note: The values of bits 4 to 6 of TA7FFCR are “1” when read.
Figure 3.12.15 Register for TMRA (11)
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Timer Registers
7
6
5
4
3
2
1
0
TA0REG
(1102H)
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
−
−
−
−
−
−
−
−
W
0
0
0
0
0
0
0
0
TA1REG
(1103H)
−
−
−
−
−
−
−
−
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
TA2REG
(110AH)
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
0
TA3REG
(110BH)
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
0
TA4REG
(1112H)
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
0
TA5REG
(1113H)
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
0
TA6REG
(111AH)
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
0
TA7REG
(111BH)
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
0
Note: All registers are prohibited to execute read-modify-write instruction.
Figure 3.12.16 TMRA Registers
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3.12.4 Operation in Each Mode
(1) 8-bit timer mode
Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers.
a. Generating interrupts at a fixed interval (Using TMRA1)
To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop
TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and
TA1REG register respectively. Then, enable the interrupt INTTA1 and start TMRA1
counting.
Example: To generate an INTTA1 interrupt every 20 us at fc = 50 MHz, set each register as
follows;
* Clock state
Clcok gear :
1/1
Prescaler of clock gear : 1/2
MSB
LSB
7
–
0
6
X
0
5
X
X
4
X
X
3
–
0
2
–
1
1
0
0
–
X
TA01RUN
TA01MOD
←
←
Stop TMRA1 and clear it to 0.
Select 8-bit timer mode and select φT1 (0.16 μs at f = 50
X
C
MHz) as the input clock.
TA1REG
INTETA1
TA01RUN
←
0
1
1
1
0
1
1
X
1
X
–
1
–
1
0
–
1
1
–
–
Set TA1REG to 20 μs ÷ φT1 = 125(7DH)
Enable INTTA1 and set it to level 5.
Start TMRA1 counting.
←
←
X
–
X
X
X: Don't Care、−: No change
Select the input clock using Table 3.12.2.
Note:
The input clocks for TMRA0 and TMRA1 are different from as follows.
TMRA0: TA0IN input, φT1, φT4 or φT16.
TMRA1: Match output of TMRA0, φT1, φT16, and φT256.
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b. Generating a 50% duty ratio square wave pulse
The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its
status output via the timer output pin (TA1OUT).
Example: To output a 3.2μs square wave pulse from the TA1OUT pin at f = 50 MHz,
C
use the following procedure to make the appropriate register settings. This
example uses TMRA1; however, either TMRA0 or TMRA1 may be used.
* Clock state
Clcok gear :
1/1
Prescaler of clock gear : 1/2
7
−
0
6
X
0
5
4
3
−
0
2
−
1
1
0
0
−
TA01RUN
TA01MOD
←
←
X
X
X
X
Stop TMRA1 and clear it to “0”.
X
X
Select 8-bit timer mode and select φT1 (0.16 μs at f = 50
C
MHz) as the input clock.
TA1REG
←
←
0
0
0
0
1
1
0
0
1
1
0
1
Set the timer register to 3.2 μs ÷ φT1 ÷ 2 = 0AH
Clear TA1FF to “0” and set it to invert on the match detect
signal from TMRA1.
TA1FFCR
X
X
X
X
PM
←
←
←
−
−
−
X
X
X
X
X
X
X
X
X
X
X
−
−
−
1
0
1
1
X
X
−
Set PM1 to function as the TA1OUT pin.
Start TMRA1 counting.
PMFC
TA01RUN
X: Don’t care, −: No change
φT1
TA01RUN
<TA01RUN>
Bit7 to Bit2
Bit1
Up
counter
Bit0
0
1
2
3
0
1
2
3
0
1
2
3
0
Comparator
timing
Comparator output
(Match detect)
INTTA1
UC1 clear
TA1FF
TA1OUT
1.6 μs at f = 50 MHz
C
Figure 3.12.17 Square Wave Output Timing Chart (50% duty)
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c. Making TMRA1 count up on the match signal from the TMRA0 comparator
Select 8-bit timer mode and set the comparator output from TMRA0 to be the
input clock to TMRA1.
Comparator output
(TMRA0 match)
TMRA0 up counter
(when TA0REG = 5)
1
2
3
1
4
5
1
2
3
2
4
5
1
2
3
TMRA1 up counter
(when TA1REG = 2)
1
TMRA1 match output
Figure 3.12.18 TMRA1 Count Up on Signal from TMRA0
(2) 16 bit timer mode
Pairing the two 8-bit timers TMRA0 and TMRA1 configures a 16-bit interval timer.
To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together,
set TA01MOD<TA01M1:0> to 01.
In 16-bit timer mode, the overflow output from TMRA0 is used as the input clock for
the relationship between the timer (Interrupt) cycle and the input clock selection.
Example: To generate an INTTA1 interrupt every 0.13 s at fSYS = 50 MHz, set the timer registers
TA0REG and TA1REG as follows:
* Clock state
Clcok gear :
1/1
Prescaler of clock gear : 1/2
If φT16 (2.6 μs at fSYS = 50 MHz) is used as the input clock for counting, set the following
value in the registers: 0.13 s ÷ 2.6 μs = 50000 = C350H; e.g. set TA1REG to C3H and
TA0REG to 50H.
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The comparator match signal is output from TMRA0 each time the up counter UC0
matches TA0REG, though the up counter UC0 is not be cleared.
In the case of the TMRA1 comparator, the match detect signal is output on each
comparator pulse on which the values in the up counter UC1 and TA1REG match.
When the match detect signal is output simultaneously from both the comparator
TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt
INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop
TA1FF is inverted.
Example: When TA1REG = 04H and TA0REG = 80H
Value of up counter
(UC1, UC0)
0080H
0180H
0280H
0380H
0480H
0080H
TMRA0 comparator
match detect signal
TMRA1 comparator
match detect signal
Interrupt INTTA0
Interrupt INTTA1
Inversion
Timer output TA1OUT
Figure 3.12.19 Timer Output by 16-Bit Timer Mode
(3) 8-bit PPG (Programmable pulse generation) output mode
Square wave pulses can be generated at any frequency and duty ratio by TMRA0.
The output pulses may be active-low or active-high. In this mode TMRA1 cannot be
used.
TMRA0 outputs pulses on the TA1OUT pin.
t
t
H
L
<TA1FFC1:0> = “10”
t
t
t
t
L
H
<TA1FFC1:0> = “01”
Example: <TA1FFC1:0> = “01”
TA0REG and UC0 match
(Interrupt INTTA0)
TA1REG and UC0 match
(Interrupt INTTA1)
TA1OUT
TA0REG
TA1REG
Figure 3.12.20 8-Bit PPG Output Waveforms
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In this mode a programmable square wave is generated by inverting the timer
output each time the 8-bit up counter (UC0) matches the value in one of the timer
registers TA0REG or TA1REG.
The value set in TA0REG must be smaller than the value set in TA1REG.
Although the up counter for TMRA1 (UC1) is not used in this mode,
TA01RUN<TA1RUN> should be set to 1 so that UC1 is set for counting.
Figure 3.12.21 shows a block diagram representing this mode.
TA1OUT
TA01RUN<TA0RUN>
Selector
TA0IN
8-bit
up counter
(UC0)
TA1FFCR<TA1FFIE>
φT1
φT4
φT16
TA1FF
Inversion
TA01MOD<TA0CLK1:0>
INTTA0
Comparator
Comparator
INTTA1
Selector
TA0REG
Shift trigger
Register buffer
TA0REG-WR
TA01RUN<TA0RDE>
TA1REG
Internal data bus
Figure 3.12.21 Block Diagram of 8-Bit PPG Output Mode
If the TA0REG double buffer is enabled in this mode, the value of the register buffer
will be shifted into TA0REG each time TA1REG matches UC0.
Use of the double buffer facilitates the handling of low-duty waves (when duty is
varied).
Match with TA0REG
and up counter
(Up counter = Q )
(Up counter = Q )
1
2
Match with TA1REG
Shift from register buffer
TA0REG
(Value to be compared)
Q
1
Q
2
Q
2
Q
3
Register buffer
TA0REG (Register buffer)
write
Figure 3.12.22 Operation of Register Buffer
Note: The values that can be set in TAxREG renge from 01h to 00h (equivalent to 100h). If the maximum value 00h
is set , the match-detect signal goes active when the up-counter overfolws.
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Example: To generate 1/4 duty 31.25 kHz pulses (at f = 50 MHz)
C
32 μs
* Clock state
Clcok gear :
1/1
Prescaler of clock gear : 1/2
Calculate the value which should be set in the timer register.
To obtain a frequency of 31.25 kHz, the pulse cycle t should be: t = 1/31.25kHz = 32 μs
φT1 = 0.16 μs (at 50 MHz);
32 μs ÷ 0.16 μs = 200
Therefore set TA1REG to 200 (C8H)
The duty is to be set to 1/4: t × 1/4 = 32 μs × 1/4 = 8 μs
8 μs ÷ 0.16 μs = 50
Therefore, set TA0REG = 50 = 32H.
7
−
1
0
1
X
6
X
0
0
1
X
5
X
X
0
4
X
X
0
3
−
X
1
1
0
2
−
X
0
0
1
1
0
0
1
0
1
0
0
1
0
0
X
TA01RUN
TA01MOD
TA0REG
TA1REG
TA1FFCR
←
←
←
←
←
Stop TMRA0 and TMRA1 and clear it to “0”.
Set the 8-bit PPG mode, and select φT1 as input clock.
Write 32H.
Write C8H.
0
0
X
X
Set TA1FF, enabling both inversion and the double buffer.
Writing 10 provides negative logic pulse.
PM
←
←
←
−
−
1
X
X
X
X
X
X
X
X
X
X
X
−
−
−
1
0
1
1
X
X
1
Set PM1 as the TA1OUT pin.
PMFC
TA01RUN
Start TMRA0 and TMRA1 counting.
X: Don't care, −: No change
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(4) 8-bit PWM (Pulse width modulation) output mode
This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum
resolution of 8 bits can be output.
When TMRA0 is used the PWM pulse is output on the TA1OUT pin (Shared with
PM1). TMRA1 can also be used as an 8-bit timer.
The timer output is inverted when the up counter (UC0) matches the value set in
the timer register TA0REG or when 2n counter overflow occurs (n = 6, 7 or 8 as
specified by TA01MOD<PWM01:00>). The up counter UC0 is cleared when 2n counter
overflow occurs.
The following conditions must be satisfied before this PWM mode can be used.
Value set in TA0REG < Value set for 2n counter overflow
Value set in TA0REG ≠ 0
TA0REG and
UC0 match
2n
overflow
(INTTA0 interrupt)
TA1OUT
t
PWM
(PWM cycle)
Figure 3.12.23 8-Bit PWM Waveforms
Figure 3.12.24 shows a block diagram representing this mode.
TA1OUT
TA1FF
TA01RUN<TA0RUN>
TA0IN
φT1
φT4
TA1FFCR
<TA1FFIE>
8-bit up counter
Selector
Clear
(UC0)
φT16
Inversion
2n overflow
control
TA01MOD<TA0CLK1:0>
TA01MOD
<PWM01:00>
Overflow
Comparator
TA0REG
INTTA0
Selector
Shift trigger
TA0REG-WR
Register buffer
TA01RUN<TA0RDE>
Internal data bus
Figure 3.12.24 Block Diagram of 8-Bit PWM Mode
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In this mode the value of the register buffer will be shifted into TA0REG if 2n
overflow is detected when the TA0REG double buffer is enabled.
Use of the double buffer facilitates the handling of low duty ratio waves.
Match with TA0REG
2n overflow
Up counter = Q
Up counter = Q
2
1
Shift into TA0REG
TA0REG
(Value to be compared)
Q
1
Q
2
Q
2
Q
3
Register buffer
TA0REG (Register buffer)
write
Figure 3.12.25 Register Buffer Operation
Example: To output the following PWM waves on the TA1OUT pin (at f = 50 MHz).
C
16.0 μs
20.48 μs
* Clock state
Clcok gear :
1/1
Prescaler of clock gear : 1/2
To achieve a 20.48μs PWM cycle by setting φT1 to 0.16 μs (at f = 50 MHz):
C
20.48 μs ÷ 0.16 μs = 128
2n= 128
Therefore n should be set to 7.
Since the low level period is 16.0 μs when φT1 = 0.16 μs,
set the following value for TAREG:
16.0 μs ÷ 0.16 μs = 100 = 64H
MSB
LSB
7
6
X
1
5
X
1
4
X
0
3
−
X
2
−
X
1
0
0
1
TA01RUN
TA01MOD
←
←
−
−
Stop TMRA0 and clear it to 0
Select 8-bit PWM mode (cycle: 27) and select φT1 as the
1
0
input clock.
TA0REG
←
←
0
1
1
0
0
1
1
0
0
1
0
Write 64H.
TA1FFCR
X
X
X
X
X
Clear TA1FF to 0, enable the inversion and double buffer.
PM
←
←
←
−
−
1
X
X
X
X
X
X
X
X
X
X
X
−
−
−
1
0
1
−
0
X
1
Set PM1 as the TA1OUT pin.
Start TMRA0 counting.
PMFC
TA01RUN
X: Don't care, −: No change
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Table 3.12.3 PWM Cycle
Clock gear Prescaler of
PWM cycle
selection
SYSCR1
clock gear
SYSCR0
<PRCK>
TAxxMOD<PWMx1:0>
27(x128)
26 (x64)
28(x256)
<GEAR2:0>
TAxxMOD<TAxCLK1:0>
TAxxMOD<TAxCLK1:0>
TAxxMOD<TAxCLK1:0>
φT1(x2)
φT4(x8) φT16(x32) φT1(x2)
φT4(x8) φT16(x32) φT1(x2)
φT4(x8)
8192/fc
φT16(x32)
000(x1)
001(x2)
010(x4)
011(x8)
100(x16)
000(x1)
001(x2)
010(x4)
011(x8)
100(x16)
512/fc
1024/fc
2048/fc
4096/fc
8192/fc
2048/fc
4096/fc
8192/fc
16384/fc
32768/fc
2048/fc
4096/fc
8192/fc
16384/fc
32768/fc
65536/fc
131072/fc
32768/fc
65536/fc
131072/fc
262144/fc
524288/fc
1024/fc
2048/fc
4096/fc
8192/fc
16384/fc
4096/fc
8192/fc
16384/fc
32768/fc
65536/fc
4096/fc
8192/fc
16384/fc
32768/fc
65536/fc
131072/fc
262144/fc
65536/fc
131072/fc
262144/fc
524288/fc
2048/fc
4096/fc
32768/fc
65536/fc
16384/fc
32768/fc
65536/fc
131072/fc
32768/fc
65536/fc
131072/fc
262144/fc
524288/fc
0(x2)
1(x8)
8192/fc
16384/fc
32768/fc
65536/fc
16384/fc
32768/fc
65536/fc
131072/fc
8192/fc
131072/fc
262144/fc
524288/fc
131072/fc
262144/fc
524288/fc
1048576/fc
2097152/fc
16384/fc
32768/fc
8192/fc
16384/fc
32768/fc
8192/fc
1/fc
x2
16384/fc
32768/fc
65536/fc
131072/fc
16384/fc
32768/fc
65536/fc
262144/fc 1048576/fc 131072/fc
(5) Settings for each mode
Table 3.12.4 shows the SFR settings for each mode.
Table 3.12.4 Timer Mode Setting Registers
Register Name
TA01MOD
TA1FFCR
TA1FFIS
<Bit Symbol>
Function
<TA01M1:0>
Timer Mode
<PWM01:00>
PWM Cycle
<TA1CLK1:0>
<TA0CLK1:0>
Upper Timer Input
Clock
Lower Timer
Input Clock
Timer F/F Invert Signal
Select
Lower timer
match
External clock
φT1, φT4, φT16
(00, 01, 10, 11)
0: Lower timer output
1: Upper timer output
8-bit timer × 2 channels
00
−
φT1, φT16, φT256
(00, 01, 10, 11)
External clock
φT1, φT4, φT16
(00, 01, 10, 11)
External clock
φT1, φT4, φT16
(00, 01, 10, 11)
External clock
φT1, φT4, φT16
(00, 01, 10, 11)
16-bit timer mode
01
10
−
−
−
−
−
−
−
8-bit PPG × 1 channel
8-bit PWM × 1 channel
26, 27, 28
11
11
−
(01, 10, 11)
φT1, φT16, φT256
8-bit timer × 1 channel
−
−
Output disabled
(01, 10, 11)
−: Don’t care
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3.13 16 bit timer / Event counter (TMRB)
The TMP92CZ26A incorporates two multifunctional 16-bit timer/event counter (TMRB0,
TMRB1) which have the following operation modes:
•
•
•
16 bit interval timer mode
16 bit event counter mode
16 bit programmable pulse generation mode (PPG)
Can be used following operation modes by capture function.
Frequency measurement mode
•
•
Pulse width measurement mode
Timer/event counter consists of a 16-bit up counter, two 16-bit timer registers (One of them
with a double-buffer structure), a 16-bit capture registers, two comparators, a capture input
controller, a timer flip-flop and a control circuit.
Timer/event counter is controlled by an 11-byte control SFR.Each channel(TMRB0,TMRB1)
operate independently.In this section, the explanation describes only for TMRB0 because each
channel is identical operation except for the difference as follows;
Table 3.13.1 Difference between TMRB0 and TMRB1
Channel
TMRB0
TMRB1
Specification
External clock/
TB0IN0
TB1IN0
capture trigger input pins
(Shared with PP4)
(Shared with PP5)
External
pins
Timer flip-flop output pins
TB0OUT0
TB1OUT0
(Shared with PP6)
(Shared with PP7)
Timer run register
Timer mode register
Timer flip-flop
TB0RUN (1180H)
TB0MOD (1182H)
TB1RUN (1190H)
TB1MOD (1192H)
TB0FFCR (1183H)
TB1FFCR (1193H)
control register
TB0RG0L (1188H)
TB0RG0H (1189H)
TB0RG1L (118AH)
TB0RG1H (118BH)
TB0CP0L (118CH)
TB0CP0H (118DH)
TB0CP1L (118EH)
TB0CP1H (118FH)
TB1RG0L (1198H)
TB1RG0H (1199H)
TB1RG1L (119AH)
TB1RG1H (119BH)
TB1CP0L (119CH)
TB1CP0H (119DH)
TB1CP1L (119EH)
TB1CP1H (119FH)
SFR
(Address)
Timer register
Capture register
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3.13.1 Block diagram
Figure 3.13.1 Block diagram of TMRB0
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Figure 3.13.2 Block diagram of TMRB1
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3.13.2 Operation
(1) Prescaler
The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (φT0)
is selected by the register SYSCR0<PRCK> of clock gear. This prescaler can be
started or stopped using TB0RUN<TB0RUN>. Counting starts when <TB0RUN> is
set to “1”; the prescaler is cleared to “0” and stops operation when <TB0RUN> is
cleared to “0”.
The resolution of prescaler is showed in the Table 3.13.2.
Table 3.13.2 Prescaler Clock Resolution
Clock gear
selection
Prescaler of
clock gear
SYSCR0
Timer counter input clock
Prescaler of TMRB
TBxMOD<TBxCLK1:0>
φT4(1/8)
−
SYSCR1
<GEAR2:0>
<PRCK>
φT1(1/2)
fc/8
φT16(1/32)
fc/128
1/1
1/2
1/4
1/8
fc/32
fc/64
fc/16
fc/256
1/2
1/8
fc/32
fc/128
fc/256
fc/512
fc/128
fc/256
fc/512
fc/1024
fc/2048
fc/512
fc/64
fc/1024
fc/2048
fc/512
1/16
1/1
1/2
1/4
1/8
1/16
fc/128
fc/32
fc
1/2
fc/64
fc/1024
fc/2048
fc/4096
fc/8192
fc/128
fc/256
fc/512
(2) Up counter (UC10)
UC10 is a 16-bit binary counter which counts up pulses input from the clock
specified by TB0MOD<TB0CLK1:0>.
Any one of the prescaler internal clocks φT1, φTB0 and φT16 or an external clock
input via the TB0IN0 pin can be selected as the input clock. Counting or stopping and
clearing of the counter is controlled by TB0RUN<TB0RUN>.
When clearing is enabled, the up counter UC10 will be cleared to zero each time its
value matches the value in the timer register TB0RG1H/L. Clearing can be enabled or
disabled using TB0MOD<TB0CLE>.
If clearing is disabled, the counter operates as a free running counter.
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(3) Timer registers (TB0RG0H/L, TB0RG1H/L)
These two 16-bit registers are used to set the interval time. When the value in the
up counter UC10 matches the value set in this timer register, the comparator match
detect signal will go active.
Setting data for both upper and lower timer registers is needed. For example, using
2-byte data transfer instruction or using 1-byte data transfer instruction twice for
lower 8 bits and upper 8 bits in order.
(The compare circuit will not operate if only the lower 8 bits are written. Be sure to
write to both timer registers (16 bits) from the lower 8 bits followed by the upper 8
bits.)
The TB0RG0H/L timer register has a double-buffer structure, which is paired with
register buffer 10. The value set in TB0RUN<TB0RDE> determines whether the
double-buffer structure is enabled or disabled: it is disabled when <TB0RDE> = “0”,
and enabled when <TB0RDE> = “1”.
When the double buffer is enabled, data is transferred from the register buffer 10 to
the timer register when the values in the up counter (UC10) and the timer register
TB0RG1H/L match.
The double buffer circuit incorporates two flags to indicate whether or not data is
written to the lower 8 bits and the upper 8 bits of the register buffer, respectively.
Only when both flags are set can data be transferred from the register buffer to the
timer register by a match between the up-counter UC10 and the timer register
TB0RG1. This data transfer is performed so long as 16-bit data is written in the
register buffer regardless of the register buffer to the timer register unexpectedly as
explained below.
For example, let us assume that an interrupt occurs when only the lower 8 bits (L1)
of the register buffer data (H1L1) have been written and the interrupt routine
includes writes to all 16 bits in the register buffer and a transfer of the data to the
timer register. In this case, if the higher 8 bits (H1) are written after the interrupt
routine is completed, only the flag for the higher 8 bits will be set, the flag for the
lower 8 bits having been cleared in the interrupt routine. Therefore, even if a match
occurs between UC10 and TB0RG1, no data transfer will be performed.
Then, in an attempt to set the next set of data (H2L2) in the register buffer, when
the lower 8 bits (L2) are written, this will cause the flag for the lower 8 bits to be set as
well as the flag for the higher 8 bits which has been set by writing the previous data
(H1). If a match between UC10 and TB0RG1 occurs before the higher 8 bits (H2) are
written, this will cause unexpected data (H1L2) to be sent to the timer register instead
of the intended data (H2L2).
To avoid such transfer timing problems due to interrupts, the DI instruction
(disable interrupts) and the EI (enable interrupts) can be executed before and after
setting data in the register buffer, respectively.
After a reset, TB0RG0H/L and TB0RG1H/L are undefined. If the 16-bit timer is to
be used after a reset, data should be written to it beforehand.
On a reset <TB0RDE> is initialized to “0”, disabling the double buffer. To use the
double buffer, write data to the timer register, set <TB0RDE> to “1”, then write data
to the register buffer 10 as shown below.
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TB0RG0H/L and the register buffer 10 both have the same memory addresses
(1188H and 1189H) allocated to them. If <TB0RDE> = “0”, the value is written to both
the timer register and the register buffer 10. If <TB0RDE> = “1”, the value is written
to the register buffer 10 only.
The addresses of the timer registers are as follows:
TMRB0
TB0RG0H/L
TB0RG1 H/L
Upper 8 bits
(TB0RG0H)
Lower 8 bits
(TB0RG0L)
Upper 8 bits
(TB0RG1H)
Lower 8 bits
(TB0RG1L)
1189H
1188H
118BH
118AH
TMRB1
TB1RG0 H/L
TB1RG1 H/L
Upper 8 bits
(TB1RG0H)
Lower 8 bits
(TB1RG0L)
Upper 8 bits
(TB1RG1H)
Lower 8 bits
(TB1RG1L)
1199H
1198H
119BH
119AH
The timer registers are write-only registers and thus cannot be read.
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(4) Capture registers (TB0CP0H/L, TB0CP1H/L)
These 16-bit registers are used to latch the values in the up counter (UC10).
Data in the capture registers should be read all 16 bits. For example, using a 2-byte
data load instruction or two 1-byte data load instructions. The least significant byte is
read first, followed by the most significant byte.
(during capture is read, capture operation is prohibited. In that case, the lower 8
bits should be read first, followed by the 8 bits.)
The addresses of the capture registers are as follows;
TMRB0
TB0CP0H/L
TB0CP1H/L
Upper 8 bits
(TB0CP0H)
Lower 8 bits
(TB0CP0L)
Upper 8 bits
(TB0CP1H)
Lower 8 bits
(TB0CP1L)
118DH
118CH
118FH
118EH
TMRB1
TB1CP0H/L
TB1CP1H/L
Upper 8 bits
(TB1CP0H)
Lower 8 bits
(TB1CP0L)
Upper 8 bits
(TB1CP1H)
Lower 8 bits
(TB1CP1L)
119DH
119CH
119FH
119EH
The capture registers are read-only registers and thus cannot be written to.
(5) Capture input and external interrupt control
This circuit controls the timing to latch the value of up-counter UC10 into
TB0CP0H/L and TB0CP1H/L, and generates external interrupt.The latch timing of
capture register and selection of edge for external interrupt is controlled by
TB0MOD<TB0CPM1:0>.
The value in the up-counter (UC10) can be loaded into a capture register by
software. Whenever 0 is written to TB0MOD<TB0CP0I>, the current value in the up
counter (UC10) is loaded into capture register TB0CP0H/L. It is necessary to keep the
prescaler in RUN mode (e.g., TB0RUN<TB0PRUN> must be held at a value of 1).
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(6) Comparators (CP10, CP11)
CP10 and CP11 are 16-bit comparators which compare the value in the up counter
UC10 with the value set in TB0RG0H/L or TB0RG1H/L respectively, in order to detect
a match. If a match is detected, the comparator generates an interrupt (INTTB00 or
INTTB01 respectively).
(7) Timer flip-flops (TB0FF0, TB0FF1)
These flip-flops are inverted by the match detect signals from the comparators and
the latch signals to the capture registers. Inversion can be enabled and disabled for
each element using TB0FFCR<TB0C0T1, TB0E1T1, TB0E0T1>.
After a reset the value of TB0FF0 is undefined. If “00” is written to TB0FFCR
<TB0FF0C1:0> or <TB0FF1C1:0>, TB0FF0 will be inverted. If “01” is written to the
capture registers, the value of TB0FF0 will be set to “1”. If “10” is written to the
capture registers, the value of TB0FF0 will be set to “0”.
Note: If an inversion by the match-detect signal and a setting change via the TB0FFCR register occurs
simultaneously, the resultant operation varies depending on the situation, as shown below.
•
•
•
If an inversion by the match-detect signal and an inversion via the register occur simultaneously, the
flip-flop will be inverted only once.
If an inversion by the match-detect siganl and an attempt to set the flip-flop to 1 via the register occur
simultaneously, the flip-flop will be set to 1.
If an inversion by the match-detect signal and an attmept to cleare the flip-flop to 0 via the register
occur simultanerously, the flip-flop will be cleared to 0.
If an inversion by match-detect signal and inversion disable setting occur
simultaneously, two case (it is inverted and it is not inverted) are occurred. Therefore,
if changing inversion control (inversion enable/disable), stop timer operation
beforehand.
The values of TB0FF0 and TB0FF1 can be output via the timer output pins
TB0OUT0 (which is shared with PP6) and TB0OUT1 (which is shared with PP7).
Timer output should be specified using the port P function register.
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3.13.3 SFR
TMRB0 RUN Register
7
6
5
4
3
2
1
0
Bit symbol
Read/Write
After Reset
TB0RDE
R/W
−
R/W
0
I2TB0
R/W
0
TB0PRUN
TB0RUN
R/W
0
TB0RUN
(1180H)
R/W
0
0
Double
Always
In IDLE2
mode
TMRB0
Up counter
(UC10)
buffer
write “0”
prescaler
Function
0: Stop and clear
1: Run (Count up)
0: disable
1: enable
0: Stop
1: Operate
Count operation
0
1
Stop and clear
Count up
<TB0PRUN>, <TB0RUN>
Note: The 1, 4 and 5 of TB0RUN are read as “1” value.
TMRB1 RUN Register
7
6
5
4
3
2
1
0
Bit symbol
Read/Write
After Reset
TB1RDE
R/W
−
R/W
0
I2TB1
R/W
0
TB1PRUN
TB1RUN
R/W
0
TB1RUN
(1190H)
R/W
0
0
Double
Always
In IDLE2
mode
TMRB1
Up counter
(UC12)
buffer
write “0”
prescaler
Function
0: disable
1: enable
0: Stop
0: Stop and clear
1: Run (Count up)
1: Operate
Count operation
0
1
Stop and clear
Count up
<TB1PRUN>, <TB1RUN>
Note: The 1, 4 and 5 of TB1RUN are read as “1” value.
Figure 3.13.3 Register for TMRB (1)
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TMRB0 Mode Register
7
−
6
−
5
4
3
2
1
0
TB0MOD
(1182H)
Bit symbol
Read/Write
After Reset
Function
TB0CP0I TB0CPM1 TB0CPM0 TB0CLE
TB0CLK1 TB0CLK0
R/W
W*
R/W
0
0
0
1
0
0
0
0
Capture timing
00:Disable
Software
Control
Prohibit
read-
modify-
write
Always write “0”.
TMRB0 source clock
00: TB0IN0 input
01: φT1
capture control
0:Execute
Up counter
0:Disable
1:Enable
INT6 occurs at
rising edge
01:TB0IN0 ↑
INT6 occurs at
rising edge
1:Undefined
10: φT4
11: φT16
10: TB0IN0 ↑ TB0IN0 ↓
INT6 occurs at
falling edge
11: TA1OUT ↑
TA1OUT ↓
INT6 occurs at rising
edge
TMRB0 source clock
<TB0CLK1:0>
00
01
10
11
TB0IN0 pin input
φT1
φT4
φT16
Control clearing for up counter (UC10)
0
Disable
<TB0CLE>
1
Enable clearing by match with TB0RG1
Capture/interrupt timing
Capture control
INT6 control
INT6 occurs at the rising
edge of TB0IN0
00
01
Disable
Capture to TB0CP0H/L at rising edge of TB0IN0
Capture to TB0CP0H/L at rising edge of TB0IN0
Capture to TB0CP1H/L at falling edge of TB0IN0
INT6 occurs at the rising
edge of TB0IN0
<TB0CPM1:0>
10
11
Capture to TB0CP0H/L at rising edge of TA1OUT
Capture to TB0CP1H/L at falling edge of TA1OUT
INT6 occurs at the rising
edge of TB0IN0
Software capture
<TB0CP0I>
0
1
The value of up counter is captured to TB0CP0H/L
Undefined
Figure 3.13.4 Register for TMRB (2)
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0
TMRB1 Mode Register
7
−
6
−
5
4
3
2
1
TB1MOD
(1192H)
Bit symbol
Read/Write
After Reset
Function
TB1CP0I TB1CPM1 TB1CPM0 TB1CLE
TB1CLK1 TB1CLK0
R/W
W*
R/W
0
0
0
1
0
0
0
0
Capture timing
00:Disable
Software
Control
Prohibit
read-
modify-
write
Always write “0”.
TMRB1 source clock
00: TB1IN0 input
01: φT1
capture control
0:Execute
Up counter
0:Disable
1:Enable
INT7 occurs at
rising edge
01:TB1IN0 ↑
INT7 occurs at
rising edge
1:Undefined
10: φT4
11: φT16
10: TB1IN0 ↑ TB1IN0 ↓
INT7 occurs at
falling edge
11: TA3OUT ↑
TA3OUT ↓
INT7 occurs at rising
edge
TMRB1 source clock
<TB1CLK1:0>
00
01
10
11
TB1IN0 pin input
φT1
φT4
φT16
Control clearing for up counter (UC12)
0
Disable
<TB1CLE>
1
Enable clearing by match with
TB1RG1H/L
Capture/interrupt timing
Capture control
INT7 control
INT7 occurs at the rising
edge of TB1IN0
00
01
Disable
Capture to TB1CP0H/L at rising edge of TB1IN0
Capture to TB1CP0H/L at rising edge of TB1IN0
Capture to TB1CP1H/L at falling edge of TB1IN0
INT7 occurs at the rising
edge of TB1IN0
<TB1CPM1:0>
10
11
Capture to TB1CP0H/L at rising edge of TA3OUT
Capture to TB1CP1H/L at falling edge of TA3OUT
INT7 occurs at the rising
edge of TB1IN0
Software capture
<TB1CP0I>
0
1
The value of up counter is captured to TB1CP0H/L
Undefined (Note)
Figure 3.13.5 Register for TMRB (3)
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TMRB0 Flip-Flop Control Register
7
−
6
−
5
4
3
2
1
0
TB0FFCR
(1183H)
Bit symbol
Read/Write
After Reset
Function
TB0C1T1
TB0C0T1
TB0E1T1
TB0E0T1
TB0FF0C1 TB0FF0C0
W*
R/W
W*
1
1
0
0
0
0
1
1
TB0FF0 inversion trigger
0: Disable trigger
Control TB0FF0
00: Invert
01: Set
Prohibit
read-
modify-
write
Always write “11”
1: Enable trigger
10: Clear
11: Undefined
When
When
When UC10 When UC10
*Always read as “11”.
capture
UC10 to
capture
UC10 to
matches
with
matches
with
*Always read as “11”.
TB0CP1H/L TB0CP0H/L TB0RG1H/L TB0RG0H/L
Timer flip-flop control(TB0FF0)
00
Invert
01
10
11
Set to “11”
<TB0FF0C1:0>
Clear to “00”
Undefined (Always read as “11”)
TB0FF0 control
Inverted when UC10 value matches the valued in TB0RG0H/L
0
1
Disable trigger
Enable trigger
<TB0E0T1>
TB0FF0 control
Inverted when UC10 value matches the valued in TB0RG1H/L
0
1
Disable trigger
Enable trigger
<TB0E1T1>
TB0FF0 control
Inverted when UC10 value is captured into TB0CP0H/L
0
1
Disable trigger
Enable trigger
<TB0C0T1>
TB0FF0 control
Inverted when UC10 value is captured into TB0CP1H/L
0
1
Disable trigger
Enable trigger
<TB0C1T1>
Figure 3.13.6 Register for TMRB (4)
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TMRB1 Flip-Flop Control Register
7
−
6
−
5
4
3
2
1
0
TB1FFCR
(1193H)
Bit symbol
Read/Write
After Reset
Function
TB1C1T1
TB1C0T1
TB1E1T1
TB1E0T1
TB1FF0C1 TB1FF0C0
W*
R/W
W*
1
1
0
0
0
0
1
1
TB1FF0 inversion trigger
0: Disable trigger
Control TB1FF0
00: Invert
01: Set
Prohibit
read-
modify-
write
Always write “11”
1: Enable trigger
10: Clear
11: Don’t care
When
When
When UC12 When UC12
*Always read as “11”.
capture
UC12 to
capture
UC12 to
matches
with
matches
with
*Always read as “11”.
TB1CP1H/L TB1CP0H/L TB1RG1H/L TB1RG0H/L
Timer flip-flop control(TB1FF0)
00
Invert
01
10
11
Set to “11”
Clear to “00”
Don’t care
<TB1FF0C1:0>
TB1FF0 control
Inverted when UC12 value matches the valued in TB1RG0H/L
0
1
Disable trigger
Enable trigger
<TB1E0T1>
TB1FF0 control
Inverted when UC12 value matches the valued in TB1RG1H/L
0
1
Disable trigger
Enable trigger
<TB1E1T1>
TB1FF0 control
Inverted when UC12 value is captured into TB1CP0H/L
0
1
Disable trigger
Enable trigger
<TB1C0T1>
TB1FF0 control
Inverted when UC12 value is captured into TB1CP1H/L
0
1
Disable trigger
Enable trigger
<TB1C1T1>
Figure 3.13.7 Register for TMRB (5)
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7
6
5
4
3
2
1
0
TB0RG0L
(1188H)
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
bit Symbol
Read/Write
After reset
−
−
−
−
−
−
−
−
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
TB0RG0H
(1189H)
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
0
TB0RG1L
(118AH)
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
0
TB0RG1H
(118BH)
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
0
TB1RG0L
(1198H)
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
0
TB1RG0H
(1199H)
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
0
TB1RG1L
(119AH)
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
0
TB1RG1H
(119BH)
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
0
Note: All registers are prohibited to execute read-modify-write instruction.
Figure 3.13.8 Register for TMRB (6)
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3.13.4 Operation in Each Mode
(1) 16 bit timer mode
Generating interrupts at fixed intervals
In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The
interval time is set in the timer register TB0RG1H/L.
7
–
6
0
1
5
X
0
4
X
0
3
–
2
–
0
1
X
0
0
0
0
TB0RUN
INTETB0
←
←
Stop TMRB0
X
X
Enable INTTB01and set interrupt level 4.
Disable INTTB00
TB0FFCR
TB0MOD
←
←
1
0
1
0
0
1
0
0
0
0
0
1
1
*
1
*
Disable the trigger
Select internal clock for input and
disable the capture function.
Set the interval time
(16 bits).
(** = 01, 10, 11)
TB0RG1
TB0RUN
←
←
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
0
X
X
–
1
X
1
Start TMRB0.
X: Don't care, −: No change
(2) 16 bit event counter mode
In 16 bit timer mode as described in above, the timer can be used as an event
counter by selecting the external clock (TB0IN0 pin input) as the input clock. Up
counter (UC10) counts up at the rising edge of TB0IN0 input. To read the value of
the counter, first perform “software capture” once and read the captured value.
7
–
6
0
X
–
1
5
X
–
–
0
4
X
1
1
0
3
–
–
–
X
2
–
–
–
0
1
X
–
–
0
0
0
X
X
0
TB0RUN
PPCR
←
←
←
←
Stop TMRB0
X
–
Set PP4 to input mode for TB0IN0
PPFC
INTETB0
X
Enable INTTB01 and sets interrupt level 4
Disable INTTB00
TB0FFCR
TB0MOD
TB0RG1
←
←
←
1
0
*
1
0
*
0
1
*
0
0
*
0
0
*
0
1
*
1
0
*
1
0
*
Disable trigger
Select TB0IN0 as the input clock
Set the number of counts
(16 bit)
*
*
*
*
*
*
*
*
TB0RUN
←
–
0
X
X
–
1
X
1
Start TMRB0
X: Don't care, −: No change
When used as an event counter, set the prescaler in RUN mode.
(TB0RUN <TB0PRUN> = “1”)
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(3) 16-bit programmable pulse generation (PPG) output mode
Square wave pulses can be generated at any frequency and duty ratio. The output
pulse may be either low active or high active.
The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is to be
enabled by the match of the up counter UC10 with timer register TB0RG0H/L or
TB0RG1H/L and to be output to TB0OUT0. In this mode the following conditions
must be satisfied.
(Value set in TB0RG0) < (Value set in TB0RG1)
Match with TB0RG0
(INTTB00 interrupt)
Match with TB0RG1
(INTTB01 interrupt)
TB0OUT0 pin
Figure 3.13.9 Programmable Pulse Generation (PPG) Output Waveforms
When the TB0RG0H/L double buffer is enabled in this mode, the value of register
buffer 10 will be shifted into TB0RG0H/L at match with TB0RG1H/L. This feature
facilitates the handling of low-duty waves.
Match with TB0RG0H/L
Match with TB0RG1H/L
Up conter = Q
Up counter = Q
2
1
Shift into the TB0RG1H/L
TB0RG0H/L
(Value to be compared)
Q
1
Q
2
Q
2
Q
3
Register buffer 10
Write into the TB0RG0H/L
Figure 3.13.10 Operation of double buffer
Note: The values that can be set in TBxRGx range from 0001h to 0000h (equivalent to 10000h). If the maximum
value 000h is set, the match-detect signal goes active when the up-counter overflows.
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The following block diagram illustrates this mode.
TB0OUT0 (PPG output)
TB0RUN<TB0RUN>
Selector
TB0IN0
φT1
F/F
(TB0FF0)
16-bit up counter
UC10
Clear
φT4
φT16
Match
16-bit comparator
TB0RG0H/L
16-bit comparator
Selector
TB0RG0-WR
Register buffer 0
TB0RG1H/L
TB0RUN<TB0RDE>
Internal data bus
Figure 3.13.11 Block Diagram of 16-Bit Mode
The following example shows how to set 16-bit PPG output mode:
7
0
*
6
0
*
5
X
*
4
X
*
3
–
*
2
–
*
1
X
*
0
0
*
TB0RUN
←
←
Disable the TB0RG0 double buffer and stop TMRB0.
TB0RG0
TB0RG1
TB0RUN
Set the duty ratio
*
*
*
*
*
*
*
*
(16 bit)
←
←
*
*
*
*
*
*
*
*
Set the frequency
*
*
*
*
*
*
*
*
(16 bit)
1
0
X
X
–
0
X
0
Enable the TB0RG0H/L double buffer.
(The duty and frequency are changed on an INTTB01
interrupt.)
TB0FFCR
TB0MOD
←
←
X
0
X
0
0
1
0
0
1
0
1
1
1
*
0
*
Set the mode to invert TB0FF0 at the match with
TB0RG0H/L/TB0RG1H/L. Set TB0FF0 to 0.
Select the internal clock as the input clock and disable
the capture function.
(** = 01, 10, 11)
Set PP6 to function as TB0OUT0
Start TMRB0.
PPFC
←
←
–
1
1
0
–
–
–
–
–
1
–
X
1
TB0RUN
X
X
X
X: Don't care, −: No change
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(4) Application examples of capture function
Used capture function, they can be applied in many ways, for example;
1. One-shot pulse output from external trigger pulse
2. Frequency measurement
3. Pulse width measurement
1. One-shot pulse output from external trigger pulse
Set the up counter UC10 in free-running mode with the internal input clock,
input the external trigger pulse from TB0IN0 pin, and load the value of up
counter into capture register TB0CP0H/L at the rising edge of the TB0IN0 pin.
When the interrupt INT6 is generated at the rising edge of TB0IN0 input, set
the TB0CP0H/L value (c) plus a delay time (d) to TB0RG0H/L (=c+d), and set the
above set value (c+d) plus a one-shot pulse width (p) to TB0RG1H/L (=c+d+p).
The TB0FFCR<TB0E1T1, TB0E0T1> register should be set “11” and that the
TB0FF0 inversion is enabled only when the up counter value matches
TB0RG0H/L or TB0RG1H/L. When interrupt INTTB01 occurs, this inversion will
be disabled after one-shot pulse is output.
Set the counter in free-running mode.
Count clock
(Prescaler output clock)
c
c + d + p
c + d
TB0IN0 pin input
(External trigger pulse)
Load to capture registesr 0 (TB0CP0H/L)
INT6 occured
Match with TB0RG0H/L
Match with TB0RG1H/L
Timer output pin TB0OUT0
Inversion
enable
INTTB01 occured
Disable inversion
caused by loading into
TB0CP0H/L
Inversion
enable
Delay time
(d)
Pulse width
(p)
Figure 3.13.12 One-shot Pulse Output (with delay)
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Example: To output 2ms one-shot pulse with 3ms delay to the external trigger pulse to
TB0IN0pin
*Clock state
System clock :
fSYS
Prescaler clock :
fSYS/4
Main setting
Free-running
Count with φT1
TB0MOD
TB0FFCR
←
←
X
X
X
X
1
0
0
0
1
0
0
0
0
1
1
0
Load to TB0CP0H/L at the rising edge of TB0IN0
Clear TB0FF0 to “0”
Disable TB0FF0 inversion
PPFC
←
–
1
–
–
–
–
–
X
Select PP6 as TB0OUT0 pin (port setting)
INTE56
←
←
←
X
X
–
1
0
0
0
0
0
0
X
X
X
–
–
0
1
–
0
–
0
1
Enable INT6
INTETB0
TB0RUN
Disable INTTB00, INTTB01
Start TMRB0
X
X
Setting in INT6 routine
TB0RG0
TB0RG1
TB0FFCR
←
←
←
TB0CP0 + 3ms/φT1
TB0RG0 + 2ms/φT1
X
X
–
–
1
1
0
–
0
–
0
Enable TB0FF0 inversion when the up counter value
matches TB0RG0H/L or TB0RG1H/L
Enable INTTB01
INTETB0
←
X
1
0
0
X
Setting in INTTB01 routine
TB0FFCR
INTETB0
←
←
X
X
X
0
–
0
–
0
0
0
0
–
0
–
0
Disable TB0FF0 inversion when the up counter value
matches TB0RG0H/L or TB0RG1H/L
Disable INTTB01
X
X: Don't care, −: No change
When delay time is unnecessary, invert timer flip-flop TB0FF0 when the up counter
value is loaded into capture register (TB0CP0H/L), and set the TB0CP0H/L value (c)
plus the one –shot pulse width (p) to TB0RG1H/L when the interrupt INT6 occurs.
The TB0FF0 inversion should be enabled when the up counter (UC10) value matched
TB0RG1H/L, and disabled when generating the interrupt INTTB01.
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Count clock
(Prescaler output clock )
c
c + p
TB0IN0 iput
(External trigger pulse)
Load into capture register 0 (TB0CP0H/L)
INT6 occured
Load into capture register 1 (TB0CP1H/L)
INTTB01 occured
Match with TB0RG1H/L
Inversion enable
Timer output pin TB0OUT0
Pulse width
Enable inversioncaused by
loading to TB0CP0H/L
(p)
Disable inversion caused by loading into
TB0CP1H/L
Figure 3.13.13 One-shot Pulse Output (without delay)
2. Frequency measurement
The frequency of the external clock can be measured in this mode. The clock is
input through the TB0IN0 pin, and its frequency is measured by the 8 bit timers
TMRA01 and the 16 bit timer/event counter (TMRB0).
The TB0IN0 pin input should be selected for the input clock of TMRB0. Set to
TB0MOD<TB0CPM1:0>=”11”. The value of the up counter is loaded into the
capture register TB0CP0H/L at the rising edge of the timer flip-flop TA1FF of
8bit timers (TMRA01), and TB0CP1H/L at its falling edge.
The frequency is calculated by the difference between the loaded values in
TB0CP0H/L and TB0CP1H/L when the interrupt (INTTA0 or INTTA1) is
generated by either 8 bit timer.
Count clock
(TB0IN0 pin input)
C2
C2
C1
TA1FF
C1
C1
Loading to TB0CP0H/L
C2
Loading to TB0CP1H/L
INTTA0/INTTA1
Figure 3.13.14 Frequency Measurement
For example, if the value for the level 1 width of TA1FF of the 8 bit timer is set
to 0.5[s] and the difference between TB0CP0H/L and TB0CP1H/L is 100, the
frequency will be 100/0.5[s] =200[Hz].
Note: The frequency in this examole is calculated with 50% duty.
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3. Pulse width measurement
This mode allows measuring the H level width of an external pulse. While
keeping the 16 bit timer/event counter counting (free-running) with the
internal clock input, the external pulse is input through the TB0IN0 pin. Then
the capture function is used to load the UC10 values into TB0CP0H/L and
TB0CP1H/L at the rising edge and falling edge of the external trigger pulse
respectively. The interrupt INT6 occurs at the falling edge of TB0IN0.
The pulse width is obtained from the difference between the values of
TB0CP0H/L and TB0CP1H/L and the internal clock cycle.
For example, if the internal clock is 0.8[us] and the difference between
TB0CP0H/L and TB0CP1H/L is 100, the pulse width will be 100 × 0.8[us] =80us
Additionally, the pulse width which is over the UC10 maximum count time
specified by the clock source can be measured by changing software.
Count clock
(Prescaler ouptut clock)
C2
C1
TB0IN0 pin input
(External pulse)
C1
C1
Loading to TB0CP0H/L
C2
C2
Loading to TB0CP1H/L
INT6
Figure 3.13.15 Pulse Width Measurement
Note:Only in this pulse width measuring mode(TB0MOD<TB0CPM1:0> “10”), external interrupt INT6 occurs at the
falling edge of TB0IN0 pin input. In other modes, it occurs at the rising edge.
The width of L level can be measured by multiplying the difference between the
first C1 and the second C0 at the second INT6 interrupt and the internal
clock cycle together.
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3.14
Serial Channels (SIO)
TMP92CZ26A includes 1 serial I/O channel (SIO0). For both channels either UART mode
(Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected.
And, SIO0 includes data modulator that supports the IrDA 1.0 infrared data communication
specification.
• I/O interface mode
Mode 0: For transmitting and receiving I/O data using
the synchronizing signal SCLK for extending
Mode 1:
Mode 2:
Mode 3:
7-bit data
8-bit data
9-bit data
• UART mode
In mode 1 and mode 2, a parity bit can be added. Mode 3 has a wakeup function for making
the master controller start slave controllers via a serial link (A multi-controller system).
Figure 3.14.1 is block diagrams for each channel.
SIO0 is compounded mainly prescaler, serial clock generation circuit, receiving buffer and
control circuit, transmission buffer and control circuit.
•
Mode 0 (I/O interface mode)
Bit0
1
2
3
4
5
6
7
Transfer direction
•
Mode 1 (7-bit UART mode)
No parity
Parity
Start Bit0
Start Bit0
1
1
2
2
3
3
4
4
5
5
6
6
Stop
Parity Stop
•
•
Mode 2 (8-bit UART mode)
No parity
Parity
Start Bit0
Start Bit0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
Stop
Parity Stop
Mode 3 (9-bit UART mode)
Start Bit0
Start Bit0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
Stop
Bit8 Stop
Wakeup
When bit8 = 1, Address (Select code) is denoted.
When bit8 = 0, Data is denoted.
Figure 3.14.1 Data Formats
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3.14.1 Block Diagram
Prescaler
φT0
2
4
8 16 32 64
φT2 φT8 φT32
Serial clock generation circuit
BR0CR<BR0CK1:0>
TA0TRG
(from TMRA0)
BR0CR
BR0ADD
<BR0S3:0> <BR0K3:0>
φT0
φT2
φT8
φT32
UART
mode
SIOCLK
BR0CR
<BR0ADDE>
Baud rate generator
SC0MOD0
<SC1:0>
SC0MOD0
<SM1:0>
f
IO
÷2
SCLK0
SCLK0
I/O interface mode
SC0CR
<IOC>
I/O interface mode
INT request
INTRX0
INTTX0
Transmision
counter
(UART only ÷ 16)
Serial channel
interrupt control
SC0MOD0
<WU>
Receive counter
(UART only ÷ 16)
RXDCLK
TXDCLK
SC0MOD0
<RXE>
Receive
control
Transmission
control
CTS0
SC0CR
SC0MOD0
<CTSE>
<PE>
<EVEN>
RXD0
Receive buffer 1 (Shift register)
Parity control
TXD0
RB8 Receive buffer 2 (SC0BUF)
Error flag
SC0CR
TB8 Transmission buffer (SC0BUF)
<OERR> <PERR> <FERR>
Internal data bus
Figure 3.14.2 Block Diagram
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3.14.2 Operation of Each Circuit
(1) Prescaler
There is a 6-bit prescaler for generating a clock to SIO0. The prescaler can be run by
selecting the baud rate generator as the serial transfer clock.
Table 3.14.1 shows prescaler clock resolution into the baud rate generator.
Table 3.14.1 Prescaler Clock Resolution to Baud Rate Generator
Clock gear
SYSCR1
<GEAR2:0>
Clock Resolution
-
-
φT0
φT2
φT8
φT32
000(1/1)
001(1/2)
f
f
/4
f
f
/16
/32
f
/64
f
f
/256
SYS
SYS
SYS
SYS
SYS
SYS
SYS
/8
f
f
f
/128
/256
/512
/512
SYS
SYS
SYS
010(1/4)
011(1/8)
100(1/16)
f
f
f
/16
/32
/64
f
/64
f
f
f
/1024
/2048
/4096
fc
1/4
SYS
SYS
SYS
SYS
SYS
SYS
SYS
f
f
/128
/256
SYS
SYS
f
/1024
SYS
XXX:Don’t care
The baud rate generator selects between 4-clock inputs: φT0, φT2, φT8, and φT32
among the prescaler outputs.
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(2) Baud rate generator
The baud rate generator is the circuit which generates transmission/receiving clock
and determines the transfer rate of the serial channels.
The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is generated by
the 6-bit prescaler which is shared by the timers. One of these input clocks is selected
using the BR0CR<BR0CK1:0> field in the baud rate generator control register.
The baud rate generator includes a frequency divider, which divides the frequency
by 1 or N + (16 − K)/16 to 16 values, determining the transfer rate.
The transfer rate is determined by the settings of BR0CR<BR0ADDE, BR0S3:0>
and BR0ADD<BR0K3:0>.
• In UART mode
When BR0CR<BR0ADDE> = 0
The settings BR0ADD<BR0K3:0> are ignored. The baud rate generator divides
the selected prescaler clock by N, which is set in BR0CK<BR0S3:0>. (N = 1, 2, 3 ...
16)
When BR0CR<BR0ADDE> = 1
The N + (16 − K)/16 division function is enabled. The baud rate generator
divides the selected prescaler clock by N + (16 – K)/16 using the value of N set in
BR0CR<BR0S3:0> (N = 2, 3 ... 15) and the value of K set in BR0ADD<BR0K3:0>
(K = 1, 2, 3 ... 15)
Note: If N = 1 or N = 16, the N + (16 − K)/16 division function is disabled. Clear
BR0CR<BR0ADDE> to 0.
• In I/O interface mode
The N + (16 − K)/16 division function is not available in I/O interface mode. Clear
BR0CR<BR0ADDE> to 0 before dividing by N.
The method for calculating the transfer rate when the baud rate generator is used is
explained below.
•
In UART mode
Input clock of baud rate generator
Frequency divider for baud rate generator
Baud rate =
÷ 16
•
In I/O interface mode
Input clock of baud rate generator
Frequency divider for baud rate generator
Baud rate =
÷ 2
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• Integer divider (N divider)
For example, when the source clock frequency (fc) is 19.6608 MHz, the input
clock is φT2, the frequency divider N (BR0CR<BR0S3:0>) = 8, and
BR0CR<BR0ADDE> = 0, the baud rate in UART Mode is as follows:
*Clock state
System clock
Prescaler clock
:
:
1/1
1/2
fC/16
8
= 19.6608106 × 106 ÷ 16 ÷ 8 ÷ 16 = 9600 (bps)
÷ 16
Baud Rate =
Note: The N + (16 – K) / 16 division function is disabled and setting BR0ADD
<BR0K3:0> is invalid.
• N+(16-K)/16 divider (UART Mode only)
Accordingly, when the source clock frequency (fc) = 15.9744 MHz, the input
clock is φT2, the frequency divider
N
(BR0CR<BR0S3:0>)
=
6,
K
(BR0ADD<BR0K3:0>) = 8, and BR0CR <BR0ADDE> = 1, the baud rate in UART
Mode is as follows:
*Clock state
System clock
Prescaler clock
:
:
1/1
1/2
fC /16
8
16
Baud Rate =
÷ 16 = 15.9744 × 106 ÷ 16÷ (6 +
) ÷ 16
(16 – 8)
16
6 +
= 9600 (bps)
Table 3.14.2 show examples of UART Mode transfer rates.
Additionally, the external clock input is available in the serial clock. (Serial
Channel 0). The method for calculating the baud rate is explained below:
• In UART Mode
Baud rate = external clock input frequency ÷ 16
It is necessary to satisfy (external clock input cycle) ≥ 4/fSYS
• In I/O Interface Mode
Baud rate = external clock input frequency
It is necessary to satisfy (external clock input cycle) ≥ 16/fSYS
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Table 3.14.2 Transfer Rate Selection
Unit (kbps)
(When baud rate generator is used and BR0CR<BR0ADDE> = 0)
Input Clock
φT0
(fSYS/4)
φT2
φT8
φT32
fSYS [MHz]
( fSYS/16) (fSYS/64) (fSYS/256)
Frequency Divider N
7.3728
1
3
6
A
C
F
1
2
4
5
8
0
6
9
2
3
5
6
8
C
F
1
3
6
A
C
F
115.200
38.400
19.200
11.520
9.600
28.800
9.600
7.200
2.400
1.200
0.720
0.600
0.480
9.600
4.800
2.400
1.920
1.200
0.600
7.200
4.800
28.800
19.200
11.520
9.600
7.200
4.800
3.840
72.000
24.000
12.000
7.200
6.000
4.800
1.800
0.600
0.300
0.180
0.150
0.120
2.400
1.200
0.600
0.480
0.300
0.150
1.800
1.200
7.200
4.800
2.880
2.400
1.800
1.200
0.960
18.000
6.000
3.000
1.800
1.500
1.200
↑
↑
4.800
↑
2.880
↑
2.400
↑
7.680
1.920
9.8304
153.600
76.800
38.400
30.720
19.200
9.600
38.400
19.200
9.600
↑
↑
↑
7.680
↑
4.800
↑
2.400
44.2368
115.20
76.800
460.800
307.200
184.320
153.600
115.200
76.800
61.440
1152.000
384.000
192.000
115.200
96.000
76.800
28.800
19.200
115.200
76.800
46.080
38.400
28.800
19.200
15.360
288.000
96.000
48.000
28.800
24.000
19.200
↑
58.9824
↑
↑
↑
↑
↑
↑
73.728
↑
↑
↑
↑
↑
Note: Transfer rates in I/O interface mode are eight times faster than the values given above.
Timer out clock (TA0TRG) can be used for source clock of UART mode only.
Calculation method the frequency of TA0TRG
Frequency of TA0TRG =
Baud rate × 16
Note: In case of I/O interface mode, prohibit to use TA0TRG for source clock.
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(3) Serial clock generation circuit
This circuit generates the basic clock for transmitting and receiving data.
• In I/O Interface Mode
In SCLK Output Mode with the setting SC0CR<IOC> = 0, the basic clock is
generated by dividing the output of the baud rate generator by 2, as described
previously.
In SCLK Input Mode with the setting SC0CR<IOC> = 1, the rising edge or falling edge
will be detected according to the setting of the SC0CR<SCLKS> register to generate
the basic clock.
• In UART Mode
The SC0MOD0 <SC1:0> setting determines whether the baud rate generator clock,
the internal clock fIO, the match detect signal from timer TMRA0 or the external clock
(SCLK0) is used to generate the basic clock SIOCLK.
(4) Receiving counter
The receiving counter is a 4-bit binary counter used in UART Mode, which counts up
the pulses of the SIOCLK clock. It takes 16 SIOCLK pulses to receive 1 bit of data;
each data bit is sampled three times - on the 7th, 8th and 9th clock cycles.
The value of the data bit is determined from these three samples using the majority
rule.
For example, if the data bit is sampled respectively as 1, 0 and 1 on 7th, 8th and 9th
clock cycles, the received data bit is taken to be 1. A data bit sampled as 0, 0 and 1 is
taken to be 0.
(5) Receiving control
• In I/O Interface Mode
In SCLK Output Mode with the setting SC0CR<IOC> = 0, the RXD0 signal is
sampled on the rising or falling edge of the shift clock which is output on the SCLK0
pin, according to the SC0CR<SCLKS> setting.
In SCLK Input Mode with the setting SC0CR<IOC> = 1, the RXD0 signal is sampled
on the rising or falling edge of the SCLK0 input, according to the SC0CR<SCLKS>
setting
• In UART Mode
The receiving control block has a circuit, which detects a start bit using the majority
rule. Received bits are sampled three times; when two or more out of three samples
are 0, the bit is recognized as the start bit and the receiving operation commences.
The values of the data bits that are received are also determined using the majority
rule.
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(6) The Receiving Buffers
To prevent Overrun errors, the Receiving Buffers are arranged in a double-buffer
structure.
Received data is stored one bit at a time in Receiving Buffer 1 (which is a shift
register). When 7 or 8 bits of data have been stored in Receiving Buffer 1, the stored
data is transferred to Receiving Buffer 2 (SC0BUF); these causes an INTRX0
interrupt to be generated. The CPU only reads Receiving Buffer 2 (SC0BUF). Even
before the CPU reads receiving Buffer 2 (SC0BUF), the received data can be stored in
Receiving Buffer 1. However, unless Receiving Buffer 2 (SC0BUF) is read before all
bits of the next data are received by Receiving Buffer 1, an overrun error occurs. If an
Overrun error occurs, the contents of Receiving Buffer 1 will be lost, although the
contents of Receiving Buffer 2 and SC0CR<RB8> will be preserved.
SC0CR<RB8> is used to store either the parity bit - added in 8-Bit UART Mode - or
the most significant bit (MSB) - in 9-Bit UART Mode.
In 9-Bit UART Mode the wake-up function for the slave controller is enabled by
setting SC0MOD0<WU> to 1; in this mode INTRX0 interrupts occur only when the
value of SC0CR<RB8> is 1.
SIO interrupt mode is selectable by the register SIMC.
Note1: The double buffer structure does not support SC0CR<RV08>.
Note2: If the CPU reads receive buffer 2 while data is being transferred from receive buffer 1 to receive buffer 2,
the data may not be read properly. To avoid this situation, a read of receive buffer 2 should be triggered by
a receive interrupt.
(7) Notes for Using Receive Interrupts
• Receive interrupts can be detected either in level or edge mode. For details, see the
description of the SIO/SEI receive interrupt mode select register SIMC in the
section on interrupts.
• When receive interrupts are set to level mode, once an interrupt occurs, the same
interrupt will occur repeatedly even after control has jumped to the interrupt
routine unless interrupts are disabled.
(8) Transmission counters
The transmission counter is a 4-bit binary counter which is used in UART Mode and
which, like the receiving counter, counts the SIOCLK clock pulses; a TXDCLK pulse is
generated every 16 SIOCLK clock pulses.
SIOCLK
TXDCLK
15 16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
Figure 3.14.3 Generation of the transmission clock
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(8) Transmission controller
• In I/O Interface Mode
In SCLK Output Mode with the setting SC0CR<IOC> = 0, the data in the
Transmission Buffer is output one bit at a time to the TXD0 pin on the rising edge or
falling of the shift clock which is output on the SCLK0 pin, according to the
SC0CR<SCLKS> setting.
In SCLK Input Mode with the setting SC0CR<IOC> = 1, the data in the Transmission
Buffer is output one bit at a time on the TXD0 pin on the rising or falling edge of the
SCLK0 input, according to the SC0CR<SCLKS> setting.
• In UART Mode
When transmission data sent from the CPU is written to the Transmission Buffer,
transmission starts on the rising edge of the next TXDCLK.
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Handshake function
CTS0
Serial Channels 0 has a
pin. Use of this pin allows data can be sent in units of
one frame; thus, Overrun errors can be avoided. The handshake functions is enabled
or disabled by the SC0MOD <CTSE> setting.
CTS0
When the
pin goes High on completion of the current data send, data
CTS0
transmission is halted until the
pin goes Low again. However, the INTTX0
Interrupt is generated, it requests the next data send to the CPU. The next data is
written in the Transmission Buffer and data sending is halted.
Though there is no RTS pin, a handshake function can be easily configured by setting
any port assigned to be the RTS function. The RTS should be output "High" to request
send data halt after data receive is completed by software in the RXD interrupt
routine.
TMP92CZ26A
TMP92CZ26A
TXD
RXD
RTS (Any port)
Receiver
CTS0
Sender
Figure 3.14.4 Handshake function
Timing to writing to the
transmission buffer
CTS0
Send is suspended
from (1) and (2)
(1)
(2)
14
13
15
16
1
2
3
14
15
16
1
2
3
SIOCLK
TXDCLK
TXD
Start bit
bit0
Note 1: (1) If the CTS0 signal goes High during transmission, no more data will be sent after completion of the
current transmission.
Note 2: (2) Transmission starts on the first falling edge of the TXDCLK clock after the
signal has fallen.
CTS0
CTS0
Figure 3.14.5
(Clear to send) Timing
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(9) Transmission buffer
The transmission buffer (SC0BUF) shifts out and sends the transmission data
written from the CPU form the least significant bit (LSB) in order. When all the bits
are shifted out, the transmission buffer becomes empty and generates an INTTX0
interrupt.
(10) Parity control circuit
When SC0CR<PE> in the serial channel control register is set to 1, it is possible to
transmit and receive data with parity. However, parity can be added only in 7-bit
UART mode or 8-bit UART mode. The SC0CR<EVEN> field in the serial channel
control register allows either even or odd parity to be selected.
In the case of transmission, parity is automatically generated when data is written
to the transmission buffer SC0BUF. The data is transmitted after the parity bit has
been stored in SC0BUF<TB7> in 7-bit UART mode or in SC0MOD0<TB8> in 8-bit
UART mode. SC0CR<PE> and SC0CR<EVEN> must be set before the transmission
data is written to the transmission buffer.
In the case of receiving, data is shifted into receiving buffer 1, and the parity is
added after the data has been transferred to receiving buffer 2 (SC0BUF), and then
compared with SC0BUF<RB7> in 7-bit UART mode or with SC0CR<RB8> in 8-bit
UART mode. If they are not equal, a parity error is generated and the SC0CR<PERR>
flag is set.
(11) Error flags
Three error flags are provided to increase the reliability of data reception.
1. Overrun error <OERR>
If all the bits of the next data item have been received in receiving buffer 1
while valid data still remains stored in receiving buffer 2 (SC0BUF), an overrun
error is generated.
The below is a recommended flow when the overrun error is generated.
(INTRX interrupt routine)
1) Read receiving buffer
2) Read error flag
3) If <OERR> = 1
then
a) Set to disable receiving (Write 0 to SC0MOD0<RXE>)
b) Wait to terminate current frame
c) Read receiving buffer
d) Read error flag
e) Set to enable receiving (Write 1 to SC0MOD0<RXE>)
f) Request to transmit again
4) Others
Note: Overrun errors are generated only with regard to receive buffer 2 (SC0BUF). Thus, if SC0CR<RB8> is not
read, no overrun error will occur.
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2. Parity error <PERR>
The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is
compared with the parity bit received via the RXD pin. If they are not equal, a
parity error is generated.
Note: The parity error flag is cleared every time it is read. However, if a parity error is detected w¥twice in
succession and the parity error flag is read between the two parity errors, it may seem as if the flag had not
been cleared. To avoid this situation, a read of the parity error flag should be riggered by a receive interrupt.
3. Framing error <FERR>
The stop bit for the received data is sampled three times around the center. If
the majority of the samples are 0, a Framing error is generated.
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(12) Timing generation
a. In UART Mode
Receiving
Mode
9-Bit
8-Bit, 7-Bit + Parity, 7-Bit
8-Bit + Parity
(Note)
(Note)
Interrupt timing
Center of last bit
(bit 8)
Center of last bit
(parity bit)
Center of stop bit
Center of stop bit
Center of stop bit
Framing error timing
Parity error timing
Center of stop bit
Center of stop bit
Center of last bit
(parity bit)
―
Overrun error timing
Center of last bit
(bit 8)
Center of last bit
(parity bit)
Center of stop bit
Note1: In 9-Bit and 8-Bit + Parity Modes, interrupts coincide with the ninth bit pulse.
Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to be
transferred) to allow checking for a framing error.
Note2: The higher the transfer rate, the later than the middle receive interrupts and errors occur.
Transmitting
Mode
9-Bit
8-Bit + Parity
8-Bit, 7-Bit + Parity, 7-Bit
Interrupt timing
Just before stop bit is Just before stop bit is Just before stop bit is
transmitted transmitted transmitted
b. I/O interface
Transmission
Interrupt
SCLK Output Mode
SCLK Input Mode
Immediately after rise of last SCLK signal Rising Mode, or
immediately after fall in Falling Mode. (See Figure 3.14.14.)
Timing used to transfer received to data Receive Buffer 2 (SC0BUF)
(i.e. immediately after last SCLK). (See Figure 3.14.15.)
Timing used to transfer received data to Receive Buffer 2 (SC0BUF)
(i.e. immediately after last SCLK). (See Figure 3.14.16.)
timing
Receiving
Interrupt
timing
SCLK Output Mode
SCLK Input Mode
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3.14.3 SFR
7
6
5
4
3
2
1
0
Bit symbol
Read/Write
After Reset
TB8
CTSE
RXE
WU
SM1
SM0
SC1
SC0
SC0MOD0
(1202H)
R/W
0
0
0
0
0
0
0
0
Transfer
data bit 8
Hand shake Receive
Wake up
function
0: disable
1: enable
Serial Transmission
Mode
00: I/O interface Mode 00: TMRA0 trigger
Serial transmission clock
(UART)
function
0: Receive
disable
0: CTS
disable
1: CTS
enable
01: 7-bit UART Mode
10: 8-bit UART Mode
11: 9-bit UART Mode
01: Baud rate
Function
generator
1: Receive
enable
10: Internal clock fIO
11: External clcok
(SCLK0 input)
Serial transmission clock source (UART)
00 TMRA0 match detect signal
01 Baud rate generator
10 Internal clock fIO
11 External clock (SCLK0 input)
Note: The clock selection for the I/O
interface mode is controlled by the
serial bontrol register (SC0CR).
Serial Transmission Mode
00 I/O Interface Mode
01
10
11
7-bit mode
8-bit mode
9-bit mode
UART mode
Wake-up function
9-Bit UART
Other Modes
Don’t care
Interrupt generated
whenever data is received
Interrupt generated only
when RB8 = 1
0
1
Receiving Function
0
1
Receive disabled
Receive enabled
Handshake function (/CTS pin)
0
1
Disabled (always transferable)
Enabled
Transmission data bit 8
Figure 3.14.6 Serial Mode Control Register (channel 0, SC0MOD0)
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7
RB8
R
6
EVEN
5
PE
4
3
PERR
2
FERR
1
0
IOC
bit Symbol
Read/Write
OERR
SCLKS
SC0CR
(1201H)
R/W
R (cleared to 0 when read)
R/W
After Reset Undefined
Received
0
0
0
0
0
0
0
Parity
Parity
0: SCLK0
0: baud rate
generator
1: SCLK0
pin input
Prohibit
to Read
modify
Write
data bit 8
0: odd
addition
1: error
1: even
0: disable
1: enable
Function
1: SCLK0
Overrun
Parity
Framing
I/O interface input clock selection
0
1
Baud rate generator
SCLK0 pin input
Edge selection for SCLK pin (Input / Output Mode)
Transmits and receivers
data on rising edge of SCLK0.
0
Transmits and receivers
1
data on falling edge SCLK0.
Framing Error flag
Cleared to 0
Parity Error flag
when read
Overrun Error flag
Parity addition enables
0
1
Disabled
Enabled
Even parity addition/check
0
1
Odd parity
Even parity
Received data 8
Note: As all error flags are cleared after reading, do not test only a single bit with a bit-testing
instruction.
Figure 3.14.7 Serial Control Register (channel 0, SC0CR)
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7
6
5
4
3
2
1
0
Bit symbol
Read/Write
After Reset
−
BR0ADDE BR0CK1
BR0CK0
BR0S3
BR0S2
BR0S1
BR0S0
BR0CR
(1203H)
R/W
0
Always
write “0”
0
0
0
0
0
0
0
+(16−K)/16 00: φT0
division 01: φT2
0: Disable 10: φT8
Divided frequency setting
Function
1: Enable 11: φT32
Setting the input clock of baud rate generator
+(16−K)/16 division enable
0
1
Disable
Enable
00
01
10
11
Internal clock φT0
Internal clock φT2
Internal clock φT8
Internal clock φT32
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
BR0K3
BR0K2
BR0K1
BR0K0
R/W
BR0ADD
(1204H)
0
0
0
0
Sets frequency divisor “K”
(divided by N + (16-K) / 16)
Function
Sets baud rate generator frequency divisor
BR0CR<BR0ADDE> = 1
BR0CR<BR0ADDE> = 0
0001 (N = 1) (UART only)
to
BR0CR
0000(N = 16)
0010 (N = 2)
<BR0S3:0>
or
to
BR0ADD
1111(N = 15)
0001 (N = 1) 1111 (N = 15)
<BR0K3:0>
0000(N = 16)
0000
Disable
Disable
Disable
Divided by N
0001(K = 1)
to
Divided by
N + (16-K) /16
1111(K = 15)
Note1:Availability of +(16-K)/16 division function
N
UART mode
I/O mode
2 to 15
1 , 16
○
×
×
×
The baud rate generator can be set “1” in UART mode and disable +(16-K)/16 division function.Don’t use in I/O
interface mode.
Note2:Set BR0CR <BR0ADDE> to 1 after setting K (K = 1 to 15) to BR0ADD<BR0K3:0> when +(16-K)/16 division function is
used. Writes to unused bits in the BR0ADD register do not affext operation, and undefined data is read from these
unused bits.
Figure 3.14.8 Baud rate generator control (channel 0, BR0CR, BR0ADD)
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7
6
5
4
3
2
1
0
(Transmission)
(Receiving)
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
SC0BUF
(1200H)
7
6
5
4
3
2
1
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
Note: Prohibit read modify write for SC0BUF.
Figure 3.14.9 Serial Transmission/Receiving Buffer Registers (channel 0, SC0BUF)
7
6
5
4
3
2
1
0
Bit symbol
Read/Write
After Reset
I2S0
R/W
FDPX0
R/W
SC0MOD1
(1205H)
0
0
IDLE2
0: Stop
1: Run
duplex
0: half
1: full
Function
Figure 3.14.10 Serial Mode Control Register 1 (channel 0, SC0MOD1)
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3.14.4
Operation in each mode
(1) Mode 0 (I/O Interface Mode)
This mode allows an increase in the number of I/O pins available for transmitting
data to or receiving data from an external shift register.
This mode includes the SCLK output mode to output synchronous clock SCLK and
SCLK input mode to input external synchronous clock SCLK.
Output extension
TMP92CZ26A
Input extension
TMP92CZ26A
Shift register
Shift register
A
B
C
D
E
F
A
B
C
D
E
F
TXD
SI
RXD
QH
SCLK
Port
SCK
RCK
SCLK
Port
CLOCK
S/ L
G
H
G
H
TC74HC595 or equivalent
TC74HC165 or equivalent
Figure 3.14.11 SCLK Output Mode connection example
Output extension
TMP92CZ26A
Input extension
Shift register
TMP92CZ26A
Shift register
A
B
C
D
E
F
A
B
C
D
E
F
TXD
SCLK
Port
SI
RXD
QH
SCK
RCK
SCLK
Port
CLOCK
S/ L
G
H
G
H
TC74HC595 or equivalent
External clock
TC74HC165 or equivalent
External clock
Figure 3.14.12 Example of SCLK Input Mode Connection
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a. Transmission
In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and
SCLK0 pins respectively each time the CPU writes the data to the Transmission Buffer.
When all data is output, INTES0 <ITX0C> will be set to generate the INTTX0 interrupt.
Timing to write
transmisison data
SCLK0 output
(<SCLKS> = 0:
rising edge mode)
(Internal clock
timing)
SCLK0 output
(<SCLKS> = 1:
falling edge mode)
TXD0
Bit0
Bit1
Bit6
Bit7
ITX0C
(INTTX0 interrupt
request)
Figure 3.14.13 Transmitting Operation in I/O Interface Mode (SCLK0 Output Mode)
In SCLK Input Mode, 8-bit data is output on the TXD0 pin when the SCLK0 input
becomes active after the data has been written to the Transmission Buffer by the
CPU.
When all data is output, INTES0 <ITX0C> will be set to generate INTTX0
interrupt.
SCLK0 input
(<SCLKS> = 0:
rising edge mode)
SCLK0 input
(<SCLKS> = 1:
falling edge mode)
TXD0
Bit0
Bit1
Bit5
Bit6
Bit7
ITX0C
(INTTX0 intterrupt
reqest)
Figure 3.14.14 Transmitting Operation in I/O Interface Mode (SCLK0 Input Mode)
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b.
Receiving
In SCLK Output Mode the synchronous clock is output on the SCLK0 pin and the
data is shifted to Receiving Buffer 1. This is initiated when the Receive Interrupt flag
INTES0<IRX0C> is cleared as the received data is read. When 8-bit data is received,
the data is transferred to Receiving Buffer 2 (SC0BUF) following the timing shown
below and INTES0<IRX0C> is set to 1 again, causing an INTRX0 interrupt to be
generated.
Setting SC0MOD0<RXE> to 1 initiates SCLK0 output.
IRX0C
(INTRX0 interrupt
request)
SCLK0 output
(<SCLKS> = 0:
rising edge mode)
SCLK0 output
(<SCLKS> = 1:
falling edge mode)
RXD0
Bit0
Bit1
Bit6
Bit7
Figure 3.14.15 Receiving operation in I/O Interface Mode (SCLK0 Output Mode)
In SCLK Input Mode the data is shifted to Receiving Buffer 1 when the SCLK input
goes active. The SCLK input goes active when the Receive Interrupt flag INTES0
<IRX0C> is cleared as the received data is read. When 8-bit data is received, the data
is shifted to Receiving Buffer 2 (SC0BUF) following the timing shown below and
INTES0 <IRX0C> is set to 1 again, causing an INTRX0 interrupt to be generated.
SCLK0 input
(<SCLKS> = 0:
rising edge mode)
SCLK0 input
(<SCLKS> = 1:
falling edge mode)
RXD1
Bit1
Bit5
Bit6
Bit7
IRX0C
(INTRX0 interrupt request)
Figure 3.14.16 Receiving Operation in I/O interface Mode (SCLK0 Input Mode)
Note: The system must be put in the Receive Enable state (SC0MOD0<RXE> = 1) before data can be received.
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c. Transmission and Receiving (Full Duplex Mode)
When Full Duplex Mode is used, set the Receive Interrupt Level to 0 and set enable
the level of transmit interrupt(1 to 6). Ensure that the program which transmits the
interrupt reads the receiving buffer before setting the next transmit data.
The following is an example of this:
Example:
Channel 0, SCLK output
Baud rate = 9600 bps
fsys = 2.4576 MHz
Main routine
7
6
0
5
0
4
1
3
2
0
1
0
0
0
INTES0
X
X
Set the INTTX0 level to 1.
Set the INTRX0 level to 0.
P9CR
X
−
−
−
−
0
−
*
X
−
−
1
−
0
−
*
X
X
−
X
−
0
1
*
X
X
−
X
−
1
−
*
X
X
0
X
−
1
−
*
1
1
0
X
−
0
−
*
0
X
−
X
0
0
−
*
1
1
−
X
0
0
−
*
Set P90, P91 and P92 to function as the TXD0,
RXD0 and SCLK0 pins respectively.
Select I/O interface mode.
P9FC
SC0MOD0
SC0MOD1
SC0CR
Select full duplex mode.
SCLK0 output mode, select rising edge
Baud rate = 9600 bps.
BR0CR
SC0MOD0
SC0BUF
Enable receiving.
Set the transmit data and start.
INTTX0 interrupt routine
A
←
SC0BUF
Read the receiving buffer.
Set the next transmit data.
CC
SC0BUF
X: Don't care, −: No change
*
*
*
*
*
*
*
*
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(2) Mode 1 (7-bit UART Mode)
7-Bit UART Mode is selected by setting the Serial Channel Mode Register
SC0MOD0<SM1:0> field to 01.
In this mode a parity bit can be added. Use of a parity bit is enabled or disabled by the
setting of the Serial Channel Control Register SC0CR<PE> bit; whether even parity
or odd parity will be used is determined by the SC0CR<EVEN> setting when
SC0CR<PE> is set to 1 (enabled).
Setting example: When transmitting data of the following format, the control
registers should be set as described below.
Even
Start Bit0
1
2
3
4
5
6
parity
Transmission direction (Transmission rate: 2400 bps at f
= 19.6608 MHz)
SYS
7
X
−
X
−
0
X
*
6
X
−
0
1
0
1
*
5
X
X
−
1
1
0
*
4
X
X
X
−
0
0
*
3
X
X
0
−
1
X
*
2
−
−
1
−
0
0
*
1
−
X
0
−
0
0
*
0
1
1
1
−
0
0
*
P9CR
←
←
←
←
←
←
←
Set P90 to function as the TXD0 pin.
P9FC
SC0MOD0
SC0CR
BR0CR
INTES0
SC0BUF
Select 7-bit UART mode.
Add even parity.
Set the transfer rate to 2400 bps.
Enable the INTTX0 interrupt and set it to interrupt level 4.
Set data for transmission.
X: Don't care, −: No change
(3) Mode 2 (8-Bit UART Mode)
8-Bit UART Mode is selected by setting SC0MOD0<SM1,SM0> to 10. In this mode a
parity bit can be added (use of a parity bit is enabled or disabled by the setting of
SC0CR<PE>); whether even parity or odd parity will be used is determined by the
SC0CR<EVEN> setting when SC0CR<PE> is set to 1 (enabled).
Setting example: When receiving data of the following format, the control
registers should be set as described below.
Odd
Start Bit0
1
2
3
4
5
6
7
Stop
= 19.6608 MHz)
parity
Transmission direction (Transmission rate: 9600 bps at f
SYS
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Main routine
7
X
−
−
−
0
X
6
X
−
−
0
0
1
5
X
X
1
1
0
0
4
X
X
−
−
1
0
3
X
X
1
−
1
X
2
−
−
0
−
0
0
1
0
X
0
−
0
0
0
−
−
1
−
0
0
P9CR
←
←
←
←
←
←
Set P91 to function as the RXD0 pin.
P9FC
SC0MOD0
SC0CR
BR0CR
INTES0
Enable receiving in 8-bit UART mode.
Add odd parity.
Set the transfer rate to 9600 bps.
Enable the INTTX0 interrupt and set it to interrupt
level 4.
Interrupt routine
A
←
SC0CR AND 00011100
CC
Check for errors
if A
≠ 0 then ERROR
CC
A
←
SC0BUF
Read the received data
CC
X: Don't care, −: No change
(4) Mode 3 (9-Bit UART Mode)
9-Bit UART Mode is selected by setting SC0MOD0<SM1:0> to 11. In this mode
parity bit cannot be added.
In the case of transmission the MSB (9th bit) is written to SC0MOD0<TB8>. In the
case of receiving it is stored in SC0CR<RB8>. When the buffer is written and read, the
MSB is read or written first, before the rest of the SC0BUF data.
Wake-up function
In 9-Bit UART Mode, the wake-up function for slave controllers is enabled by
setting SC0MOD0<WU> to 1. The interrupt INTRX0 can only be generated
when<RB8> = 1.
TXD
RXD
TXD
RXD
TXD
RXD
TXD
RXD
Master
Slave1
Slave 2
Slave 3
Note: The TXD pin of each slave controller must be in Open-Drain Output Mode.
Figure 3.14.17 Serial Link using Wake-up function
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Protocol
1. Select 9-Bit UART Mode on the master and slave controllers.
2. Set the SC0MOD0<WU> bit on each slave controller to 1 to enable data receiving.
3. The master controller transmits data one frame at a time. Each frame includes an 8-bit
select code which identifies a slave controller. The MSB (bit 8) of the data (<TB8>) is
set to 1.
7
8
Start Bit0
1
2
3
4
5
6
Stop
Select code of slave controller
“1”
4. Each slave controller receives the above frame. Each controller checks the above select
code against its own select code. The controller whose code matches clears its <WU>
bit to 0.
5. The master controller transmits data to the specified slave controller (the controller
whose SC0MOD0<WU> bit has been cleared to 0). The MSB (bit 8) of the data
(<TB8>) is cleared to 0.
7
Bit8
“0”
Start Bit0
1
2
3
4
5
6
Stop
Data
6.
The other slave controllers (whose <WU> bits remain at 1) ignore the received data
because their MSBs (bit 8 or <RB8>) are set to 0, disabling INTRX0 interrupts.
The slave controller whose <WU> bit = 0 can also transmit to the master controller. In
this way it can signal the master controller that the data transmission from the
master controller has been completed.
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Setting example: To link two slave controllers serially with the master controller using the
internal clock fIO as the transfer clock.
TXD
RXD
TXD
RXD
TXD
RXD
Master
Slave1
Slave 2
Select code
00000001
Select code 00001010
• Setting the master controller
Main routine
P9CR
P9FC
←
←
X X X X X − 0 1
− X X X − X 1
Set P90 and P91 to function as the TXD0 and RXD0 pins
respectively.
−
INTES0
←
X 1 0 0 X 1 0 1
Enable the INTTX0 interrupt and set it to Interrupt Level 4.
Enable the INTRX0 interrupt and set it to Interrupt Level 5.
SC0MOD0 ← 1 0 1 0 1 1 1 0
SC0BUF
← 0 0 0 0 0 0 0 1
Set f as the transmission clock for 9-Bit UART Mode.
IO
Set the select code for slave controller 1.
Interrupt routine (INTTX0)
SC0MOD0 ← 0 − −
SC0BUF
← * * *
−
−
−
−
−
Set TB8 to 0.
*
*
*
*
*
Set data for transmission.
• Setting the slave controller
Main routine
P9CR
P9FC
←
←
←
←
X X X X X − 0 1
− X X X − X 1
Select P91 and P90 to function as the RXD0 and TXD0 pins
respectively (open-drain output).
−
P9FC2
INTES0
X X X X X X X 1
X 1 0 0 X 1 0 0
Enable INTRX0 and INTTX0.
SC0MOD0 ← 0 0 1 1 1 1 1 0
Set <WU> to 1 in 9-Bit UART Transmission Mode using fSYS as
the transfer clock.
Interrupt routine (INTRX0)
Acc ← SC0BUF
if Acc =Select code
Then SC0MOD0 ← − − − 0 − − − − Clear <WU> to 0.
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3.14.5 Support for IrDA
SIO0 includes support for the IrDA 1.0 infrared data communication specification.
Figure 3.14.8 shows the block diagram.
TXD0
Transmisison
data
IR modulator
IR transmitter & LED
IR receiver
IR output
IR input
SIO0
Modem
RXD0
Receive
data
IR demodulator
TMP92CZ26A
Figure 3.14.18 Block Diagram
(1) Modulation of the transmission data
When the transmit data is 0, the modem outputs 1 to TXD0 pin with either 3/16 or
1/16 times for width of baud-rate. The pulse width is selected by the SIRCR<PLSEL>.
When the transmit data is 1, the modem outputs 0.
Transmission
data
Start
0
1
0
0
1
1
0
0
Stop
TXD0 pin
Figure 3.14.19 Transmission example
(2) Modulation of the receive data
When the receive data is the effective width of pulse “1”, the modem outputs “0” to
SIO0. Otherwise the modem outputs “1” to SIO0. The effective pulse width is selected
by SIRCR<SIRWD3 to SIRWD0>.
RXD0 pin
Receive data
Start
1
0
0
1
0
1
1
0
Stop
Figure 3.14.20 Receiving example
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(3) Data format
The data format is fixed as follows:
• Data length:
8-bit
none
1bit
• Parity bits:
• Stop bits:
(4) SFR
Figure 3.14.21 shows the control register SIRCR. Set the data SIRCR during SIO0
is stopping. The following example describes how to set this register:
1) SIO setting
↓
; Set the SIO to UART Mode.
2) LD (SIRCR), 07H
3) LD (SIRCR), 37H
↓
; Set the receive data pulse width to 16×.
; TXEN, RXEN Enable the Transmission and receiving.
4) Start transmission
and receiving for SIO0
; The modem operates as follows:
y SIO0 starts transmitting.
y IR receiver starts receiving.
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(5) Notes
1. Baud rate for IrDA
When IrDA is operated, set 01 to SC0MOD0<SC1:0> to generate
baud-rate.
The setting except above (TA0TRG, fIO and SCLK0-input) cannot be used.
2. The pulse width for transmission
Table 3.14.3 Baud rate and pulse width specifications
Rate Tolerance
(% of rate)
Pulse Width
(minimum)
Pulse Width
(typical)
Pulse width
(maximum)
Baud Rate
Modulation
2.4 kbps
9.6 kbps
RZI
RZI
RZI
RZI
RZI
RZI
±0.87
±0.87
±0.87
±0.87
±0.87
±0.87
1.41 μs
1.41 μs
1.41 μs
1.41 μs
1.41 μs
1.41 μs
78.13 μs
19.53 μs
9.77 μs
4.88 μs
3.26 μs
1.63 μs
88.55 μs
22.13 μs
11.07 μs
5.96 μs
4.34 μs
2.23 μs
19.2 kbps
38.4 kbps
57.6 kbps
115.2 kbps
The infra-red pulse width is specified either baud rate T× 3/16 or 1.6 μs (1.6 μs is equal to
3/16 pulse width when baud rate is 115.2 kbps).
The TMP92CZ26A has the function selects the pulse width of Transmission either 3/16 or
1/16. But 1/16 pulse width can be selected when the baud rate is equal or less than 38.4
kbps.
As the same reason, + (16 − k)/16 division function in the baud rate generator of SIO0 can
not be used to generate 115.2 kbps baud rate.
Also when the 38.4 kbps and 1/16 pulse width, + (16-K)/16 division function can not be used.
Table 3.14.4 Baud rate and pulse width for (16 – K) / 16 division function
Baud Rate
Pulse Width
115.2 Kbps 57.6 Kbps 38.4 Kbps 19.2 Kbps
9.6 Kbps
2.4 Kbps
○
−
○
×
○
○
○
○
○
○
T × 3/16
× (Note)
T × 1/16
−
○: Can be used (16 − K)/16 division function
×: Cannot be used (16 − K)/16 division function
−: Cannot be set to 1/16 pulse width
Note: Can be used (16 − K)/16 division function at a special condition.
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0
7
6
5
4
3
2
1
Bit symbol
PLSEL
RXSEL
TXEN
RXEN
SIRWD3
SIRWD2
SIRWD1
SIRWD0
SIRCR
(1207H) Read/Write
After reset
R/W
0
0
Receive
data
0
0
0
0
0
0
Select
transmit
Transmit
0: disable
Receive
0: disable
1: enable
Select receive pulse width
Set effective pulse width for equal or more than 2x ×
(value + 1) + 100ns
Can be set
pulse width 0: “H” pulse 1: enable
0: 3/16
1: 1/16
Function
1: “L” pulse
: 1 to 14
Can not be set : 0, 15
Select receive pulse width
Formula: Effective pulse width ≥ 2x × (value + 1) + 100ns
x = 1/fFPH
0000
0001
to
Cannot be set
Equal or more than 4x + 100ns
1110
1111
Equal or more than 30x + 100ns
Can not be set
Receive (recovery) operation
0
Disable receiving operation
(Received data is ignored)
Enabled receiving operation
1
Transmit (modulation) operation
0
Disabled transmission operation
(Input from SIO is ignored)
1
Enabled transmission operation
Select transmit pulse width
0
1
3/16 pulse width
1/16 pulse width
Figure 3.14.21 IrDA Control Register
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3.15 Serial Bus Interface (SBI)
The TMP92CZ26A has a 1-channel serial bus interface which an I2C bus mode. This circuit
2
supports only I C bus mode (Multi master).
The serial bus interface is connected to an external device through PV6 (SDA) and PV7 (SCL)
in the I2C bus mode.
Each pin is specified as follows.
PVFC2<PV7F2, PV6F2>
11
PVCR<PV7C, PV6C>
11
PVFC<PV7F, PV6F>
11
I2C bus mode
3.15.1 Configuration
INTSBI interrupt request
SCL
SCK
SIO
clock
control
Input/
output
control
PV6
Divider
f
/4
SYS
(SDA)
SO
SI
SIO
data control
Transfer
control
circuit
I2C bus
clock
PV7
sync. +
control
(SCL)
Noise
canceller
Shift
register
I2C bus
data control
Noise
canceller
SDA
SBICR2/
SBISR
I2CAR
SBIDBR
SBICR0, 1
SBIBR0
I2C bus
address
register
SBI data
buffer
register
SBI control
register 2/
SBI status
register
SBI control
register 0, 1
SBI baud rate
register 0
Figure 3.15.1 Serial bus interface (SBI)
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3.15.2 Serial Bus Interface (SBI) Control
The following registers are used to control the serial bus interface and monitor the
operation status.
z
z
z
z
z
z
z
Serial bus interface control register 0 (SBICR0)
Serial bus interface control register 1 (SBICR1)
Serial bus interface control register 2 (SBICR2)
Serial bus interface data buffer register (SBIDBR)
I2C bus address register (I2CAR)
Serial bus interface status register (SBISR)
Serial bus interface baud rate register 0 (SBIBR0)
3.15.3 The Data Formats in the I2C Bus Mode
The data formats in the I2C bus mode is shown below.
(a) Addressing format
1
8 bits
Slave address
1
1 to 8 bits
Data
1 to 8 bits
Data
1
1
R
/
W
A
C
K
A
C
K
A
C
K
S
P
1 or more
(b) Addressing format (with restart)
8 bits
1
1
1 to 8 bits
Data
8 bits
1 to 8 bits
Data
1
1
R
/
A
C
K
A
C
K
R
A
C
K
A
C
K
S
Slave address
1
S
Slave address
1
P
/
W
W
1 or more
1 or more
(c) Free data format (data transferred from master device to slave device)
1
8 bits
Data
1 to 8 bits
Data
1 to 8 bits
Data
1
1
A
C
K
A
C
K
A
C
K
S
P
1
1 or more
S:
Start condition
R/ W :
ACK:
P:
Direction bit
Acknowledge bit
Stop condition
Figure 3.15.2 Data format in the I2C bus mode
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3.15.4 I2C Bus Mode Control Register
The following registers are used to control and monitor the operation status when using
the serial bus interface (SBI) in the I2C bus mode.
Serial Bus Interface Control Register 0
7
6
5
4
3
2
1
0
−
−
−
−
−
−
−
Bit symbol
Read/Write
After Reset
Function
SBIEN
R/W
0
SBICR0
(1247H)
R
0
0
0
0
0
0
0
SBI
Always read “0”.
Prohibit
Read-
modify-
Write
operation
0 : disable
1 : enable
<SBIEN> : When using SBI, <SBIEN> should be set “1” (SBI operation enable) before setting each register of SBI
module.
Figure 3.15.3 Registers for the I2C bus mode
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0
Serial Bus Interface Control Register 1
7
6
5
4
3
2
1
SCK0/
Bit symbol
BC2
BC1
BC0
ACK
SCK2
SCK1
−
SBICR1
(1240H)
SWRMON
Read/Write
After Reset
Function
R/W
0
R/W
0
R
1
R/W
R/W
0
0
0
0
0/1(Note2)
Prohibit
Read-
modify-
write
Number of transferred bits
(Note 1)
Always
read as
Internal serial clock selection and
software reset monitor
Acknowledge
mode
specification “1”.
0: Not
generate
1: Generate
Internal serial clock selection <SCK2:0> at write
=80MHz (Output to SCL pin), Clock gear = fc/1
f
SYS
000
n = 4
n = 5
n = 6
n = 7
n = 8
n = 9
n = 10
−
−
−
−
001
010
011
100
101
110
111
System Clock: f
SYS
(=80MHz)
68 kHz
36 kHz
18 kHz
Clock Gear : fc/1
fSYS/4
fscl =
[Hz]
n
2 + 35
(Reserved) (Reserved)
Software reset state monitor <SWRMON> at read
0
1
During software reset
(Initial Data)
Acknowledge mode specification
0
1
Not generate clock pulse for acknowledge signal
Generate clock pulse for acknowledge signal
Number of bits transferred
<ACK> = 0
<ACK> = 1
Number of
<BC2:0>
Number of
Bits
Bits
clock pulses
clock pulses
000
001
010
011
100
101
110
111
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
9
2
3
4
5
6
7
8
8
1
2
3
4
5
6
7
Note1: For the frequency of the SCL line clock, see 3.15.5 (3) Serial clock.
Note2: The initial data of SCK0 is “0”, the initialdata of SWRMON is “1” if SBI operation is enable
(SBICR0<SBIEN>=“1”). If SBI operation is disable (SBICR0<SBIEN>=“0”), the initialdata of SWRMON is “0”.
2
2
Note3: This I C bus circuit does not support Fast-mode, it supports the Standard mode only. Although the I C bus
2
circuit itself allows the setting of a baud rate over 100kbps, the compliance with the I C specification is not
guaranteed in that case.
Figure 3.15.4 Registers for the I2C bus mode
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Serial Bus Interface Control Register 1
7
6
5
4
3
2
1
0
SBICR2 Bit symbol
MST
TRX
BB
PIN
SBIM1
SBIM0
SWRST1
SWRST0
(1243H)
Read/Write
After reset
Function
W
W (Note 1)
W (Note 1)
0
0
0
1
0
0
0
0
Prohibit
Read-
modify-
write
Master/Slave Transmitter Start/Stop Cancel
Serial bus interface
Software reset generate
selection
0:Slave
/Receiver
selection
condition
INTSBI
operating mode selection write “10” and “01”, then
Generation interrupt
0:Generate request
(Note 2)
an internal reset signal is
generated.
1:Master
00: Port mode
0:Receiver
1:Transmitter
stop
condition 1:Cancel
0:Don’t care 01: (Reserved)
10: I2C Bus mode
1:Generate
start
interrupt 11: (Reserved)
request
condition
Serial bus interface operating mode selection (Note2)
00 Port Mode (Serial Bus Interface output disabled)
01 Reserved
10 I2C Bus Mode
11 Reserved
Note 1: Reading this register functions as SBISR register.
Note 2: Switch a mode to port mode after confirming that the bus is free.
Switch a mode between I2C bus mode and port mode after confirming that input signals via port are
high-level.
Figure 3.15.5 Registers for the I2C bus mode
Table 3.15.1Resolution of base clock
@f
= 80MHz
SYS
Clock Gear
<GEAR1:0>
Base Clock
Resolution
2
f
/2 (50ns)
000(fc)
001(fc/2)
010(fc/4)
011(fc/8)
100(fc/16)
SYS
3
f
/2 (0.1us)
SYS
SYS
4
f
/2 (0.2us)
5
f
f
/2 (0.4us)
SYS
SYS
6
/2 (0.8us)
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Serial Bus Interface Status Register
7
6
5
4
3
2
1
0
SBISR
Bit symbol
Read/Write
After reset
Function
MST
TRX
BB
PIN
AL
AAS
AD0
LRB
(1243H)
R
0
0
0
1
INTSBI
interrupt
request
monitor
0
0
0
0
Master/
Transmitter/ I2C bus
Arbitration Slave
GENERAL Last
Prohibit
Read-modif
y-write
Slave status Receiver
status
lost
address
CALL
received bit
monitor
0:Slave
1:Master
status
monitor
0:Free
1:Busy
detection
monitor
match
detection
monitor
monitor
0: 0
monitor
detection
monitor
0: Interrupt 0: −
requested 1: Detected
1: Interrupt
1: 1
0:Receiver
1:Tranmitter
0: Undetected
1: Detected
0: Undetected
1: Detected
canceled
Last received bit monitor
0
1
Last received bit was 0
Last received bit was 1
GENERAL CALL detection monitor
0
1
Undetected
GENERAL CALL detected
Slave address match detection monitor
0
Slave address don’t match or Undetected
Slave address match or GENERAL
CALL detected
1
Arbitration lost detection monitor
0
1
−
Arbitration lost
Note1: Writing in this register functions as SBICR2.
Note2: The initialdata SBISR<PIN> is “1” if SBI operation is enable (SBICR0<SBIEN>=“1”). If SBI operation is disable
(SBICR0<SBIEN>=“0”), the initialdata of SBISR<PIN> is “0”.
Figure 3.15.6 Registers for the I2C bus mode
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Serial Bus Interface Baud Rate Register 0
7
6
5
4
3
2
1
0
SBIBR0
(1244H)
Prohibit
Bit symbol
Read/Write
After reset
Function
−
W
I2SBI
R/W
0
−
−
−
R
1
−
−
−
R/W
0
1
1
1
1
0
Read-modify
-write
Always
read “0”
IDLE2
Always read as “1”
Always
write “0”.
0: Stop
1: Run
Operation during IDLE 2 mode
0
1
Stop
Operation
Serial Bus Interface Data Buffer Register
7
6
5
4
3
2
1
0
SBIDBR
(1241H)
Bit symbol
Read/Write
After reset
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R (received)/W (transfer)
Undefined
Prohibit
Read-modify
-write
Note1: When writing transmitted data, start from the MSB (bit 7).Receiving data is placed from LSB(bit0).
Note2: SBIDBR can’t be read the written data because of it has buffer for writing and buffer for reading
individually.Therefore Read modify write instruction (e.g.“BIT” instruction ) is prohibitted.
Note3:Written data to SBIDBR is cleared by INTSBI signal.
I2C Bus Address Register
7
6
5
4
3
2
1
0
I2CAR
Bit symbol
Read/Write
After reset
Function
SA6
SA5
SA4
SA3
SA2
SA1
SA0
ALS
(1242H)
R/W
Prohibit
0
0
0
0
0
0
0
0
Read-modify
-write
Slave address selection for when device is operating as slave device
Address
recognition
mode
specification
Address recognition mode specification
0
1
Slave address recognition
Non slave address recognition
Figure 3.15.7 Registers for the I2C bus mode
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3.15.5 Control in I2C Bus Mode
(1)
Acknowledge Mode Specification
When slave address is matched or detecting GENERAL CALL, and set the
SBICR1<ACK> to “1”, TMP92CZ26A operates in the acknowledge mode. The
TMP92CZ26A generates an additional clock pulse for an Acknowledge signal when
operating in Master Mode. In the transmitter mode during the clock pulse cycle, the
SDA pin is released in order to receive the acknowledge signal from the receiver. In
the receiver mode during the clock pulse cycle, the SDA pin is set to the Low in order
to generate the acknowledge signal.
Clear the <ACK> to “0” for operation in the Non-Acknowledge Mode; The
TMP92CZ26A does not generate a clock pulse for the Acknowledge signal when
operating in the Master Mode.
(2)
(3)
Number of transfer bits
The SBICR1<BC2:0> is used to select a number of bits for next transmitting and
receiving data.
Since the <BC2:0> is cleared to 000 as a start condition, a slave address and direction
bit transmission are executed in 8 bits. Other than these, the <BC2:0> retains a
specified value.
Serial clock
a. Clock source
The SBICR1 <SCK2:0> is used to select a maximum transfer frequency outputted
on the SCL pin in Master Mode. Set the baud rates, which have been calculated
according to the formula below, to meet the specifications of the I2C bus, such as the
smallest pulse width of tLOW,
t
t
1/fscl
HIGH
LOW
SBICR1<SCK2:0>
n
000
001
010
011
100
101
110
4
5
t
t
= (2n-1+ 29)/(f
/4)
/4)
LOW
SYS
6
= (2n 1 + 6)/(f
−
7
HIGH
SYS
8
fscl = 1/(t
+ t )
HIGH
LOW
9
10
f
/4
SYS
n
=
2
+ 35
Figure 3.15.8 Clock source
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b. Clock synchronization
In the I2C bus mode, in order to wired-AND a bus, a master device which pulls down
a clock line to low-level, in the first place, invalidate a clock pulse of another master
device which generates a high-level clock pulse. The master device with a high-level
clock pulse needs to detect the situation and implement the following procedure.
The TMP92CZ26A has a clock synchronization function for normal data transfer even
when more than one master exists on the bus.
The example explains the clock synchronization procedures when two masters
simultaneously exist on a bus.
Wait counting high-level
width of a clock pulse
Start counting high-level width of a clock pulse
Internal SCL output
(Master A)
Reset a counting of
high-level width of a
clock pulse
Internal SCL output
(Master B)
SCL pin
a
b
c
Figure 3.15.9 Clock synchronization
As Master A pulls down the internal SCL output to the Low level at point “a”,
the SCL line of the bus becomes the Low-level. After detecting this situation,
Master B resets a counter of High-level width of an own clock pulse and sets the
internal SCL output to the Low-level.
Master A finishes counting Low-level width of an own clock pulse at point “b” and
sets the internal SCL output to the High-level. Since Master B holds the SCL line
of the bus at the Low-level, Master A wait for counting high-level width of an own
clock pulse. After Master B finishes counting low-level width of an own clock
pulse at point “c” and Master A detects the SCL line of the bus at the High-level,
and starts counting High-level of an own clock pulse. The clock pulse on the bus is
determined by the master device with the shortest High-level width and the
master device with the longest Low-level width from among those master devices
connected to the bus.
(4)
(5)
Slave address and address recognition mode specification
When the TMP92CZ26A is used as a slave device, set the slave address <SA6:0> and
<ALS> to the I2CAR. Clear the <ALS> to “0” for the address recognition mode.
Master/Slave selection
Set the SBICR2<MST> to “1” for operating the TMP92CZ26A as a master device.
Clear the SBICR2<MST> to “0” for operation as a slave device. The <MST> is cleared
to “0” by the hardware after a stop condition on the bus is detected or arbitration is
lost.
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(6)
Transmitter/Receiver selection
Set the SBICR2<TRX> to “1” for operating the TMP92CZ26A as a transmitter.
Clear the <TRX> to “0” for operation as a receiver.
In Slave Mode,
z
Data with an addressing format is transferred
z
z
A slave address with the same value that an I2CAR
A GENERAL CALL is received (all 8-bit data are “0” after a start condition)
The <TRX> is set to “1” by the hardware if the direction bit (R/W ) sent from the
master device is “1”, and is cleared to “0” by the hardware if the bit is “0”.
In the Master Mode, after an Acknowledge signal is returned from the slave device,
the <TRX> is cleared to “0” by the hardware if a transmitted direction bit is “1”, and is
set to “1” by the hardware if it is “0”. When an Acknowledge signal is not returned, the
current condition is maintained.
The <TRX> is cleared to “0” by the hardware after a stop condition on the I2C bus is
detected or arbitration is lost.
(7)
Start/Stop condition generation
When the SBISR<BB> is “0”, slave address and direction bit which are set to
SBIDBR are output on a bus after generating a start condition by writing “1” to the
SBICR2 <MST, TRX, BB, PIN>. It is necessary to set transmitted data to the data
buffer register (SBIDBR) and set “1” to <ACK> beforehand.
SCL pin
SDA pin
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0
R/ W
Acknowledge
signal
Start condition
Slave address and the direction bit
Figure 3.15.10 Start condition generation and slave address generation
When the <BB> is “1”, a sequence of generating a stop condition is started by
writing “1” to the <MST, TRX, PIN>, and “0” to the <BB>. Do not modify the contents
of <MST, TRX, BB, PIN> until a stop condition is generated on a bus.
SCL pin
SDA pin
Stop condition
Figure 3.15.11 Stop condition generation
The state of the bus can be ascertained by reading the contents of SBISR<BB>.
SBISR<BB> will be set to 1 if a start condition has been detected on the bus, and will
be cleared to 0 if a stop condition has been detected.
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(8)
Interrupt service requests and interrupt cancellation
When a serial bus interface interrupt request (INTSBI) occurs, the SBICR2 <PIN>
is cleared to “0”. During the time that the SBICR2<PIN> is “0”, the SCL line is pulled
down to the Low level.
The <PIN> is cleared to “0” when a 1-word of data is transmitted or received. Either
writing/reading data to/from SBIDBR sets the <PIN> to “1”.
The time from the <PIN> being set to “1” until the SCL line is released takes t
.
LOW
In the address recognition mode (<ALS> = “0”), <PIN> is cleared to “0” when the
received slave address is the same as the value set at the I2CAR or when a GENERAL
CALL is received (all 8-bit data are “0” after a start condition). Although
SBICR2<PIN> can be set to “1” by the program, the <PIN> is not clear it to “0” when it
is written “0”.
(9)
Serial bus interface operation mode selection
SBICR2<SBIM1:0> is used to specify the serial bus interface operation mode. Set
SBICR2< SBIM1:0> to “10” when the device is to be used in I2C Bus Mode after
confirming pin condition of serial bus interface to “H”.
Switch a mode to port after confirming a bus is free.
(10) Arbitration lost detection monitor
Since more than one master device can exist simultaneously on the bus in I2C Bus
Mode, a bus arbitration procedure has been implemented in order to guarantee the
integrity of transferred data.
In case set start condition bit with bus is busy, start condition is not output on SCL
and SDA pin, but arbitration lost is generated.
Data on the SDA line is used for I2C bus arbitration.
The following shows an example of a bus arbitration procedure when two master
devices exist simultaneously on the bus. Master A and Master B output the same data
until point “a”. After Master A outputs “L” and Master B, “H”, the SDA line of the bus
is wire-AND and the SDA line is pulled down to the Low-level by Master A. When the
SCL line of the bus is pulled up at point b, the slave device reads the data on the SDA
line, that is, data in Master A. A data transmitted from Master B becomes invalid. The
state in Master B is called “ARBITRATION LOST”. Master B device which loses
arbitration releases the internal SDA output in order not to affect data transmitted
from other masters with arbitration. When more than one master sends the same data
at the first word, arbitration occurs continuously after the second word.
Figure 3.15.12 Arbitration lost
SCL pin
Internal SDA output
(Master A)
Internal SDA output
(Master B)
Internal SDA output becomes 1 after arbitration has been lost.
SDA pin
a
b
The TMP92CZ26A compares the levels on the bus’s SDA line with those of the internal
SDA output on the rising edge of the SCL line. If the levels do not match, arbitration is
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lost and SBISR<AL> is set to “1”.
When SBISR<AL> is set to “1”, SBISR<MST, TRX> are cleared to “00” and the mode is
switched to Slave Receiver Mode. Thus, clock output is stopped in data transfer after
setting <AL>=“1”.
SBISR<AL> is cleared to “0” when data is written to or read from SBIDBR or when
data is written to SBICR2.
1
2
3
4
5
6
7
8
9
1
2
3
4
Internal
SCL output
Master
A
D7A D6A D5A D4A D3A D2A D1A D0A
Stop the clock pulse
D7A’ D6A’ D5A’ D4A’
Internal
SDA output
Internal
SCL output
1
2
3
4
Master
B
Internal
D7B D6B
Keep Internal SDA output to high-level as losing arbitration
SDA output
<AL>
<MST>
<TRX>
Accessed to
SBIDBR or SBICR2
Figure 3.15.13 Example of when TMP92CZ26A is a master device B
(D7A = D7B, D6A = D6B)
(11) Slave address match detection monitor
SBISR<AAS> is set to “1” in Slave Mode, in Address Recognition Mode (i.e. when
I2CAR<ALS> = “0”), when a GENERAL CALL is received, or when a slave address
matches the value set in I2CAR. When I2CAR<ALS> = “1”, SBISR<AAS> is set to “1”
after the first word of data has been received. SBISR<AAS> is cleared to “0” when
data is written to or read from the data buffer register SBIDBR.
(12) GENERAL CALL detection monitor
SBISR<AD0> is set to “1” in Slave Mode, when a GENERAL CALL is received (all
8-bit received data is “0”, after a start condition). SBISR<AD0> is cleared to “0” when
a start condition or stop condition is detected on the bus.
(13) Last received bit monitor
The SDA line value stored at the rising edge of the SCL line is set to the
SBISR<LRB>. In the acknowledge mode, immediately after an INTSBI interrupt
request is generated, an acknowledge signal is read by reading the contents of the
SBISR<LRB>.
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(14) Software Reset function
The software Reset function is used to initialize the SBI circuit, when SBI is rocked
by external noises, etc.
An internal Reset signal pulse can be generated by setting SBICR2<SWRST1:0> to
“10” and “01”. This initializes the SBI circuit internally. All command registers and
status registers are initialized as well.
SBICR1<SWRMON>is automatically set to “1” after the SBI circuit has been
initialized.
Note: If the software reset is executied , operation selection is reset, and its mode is set to port mode from I2C
mode.
(15) Serial Bus Interface Data Buffer Register (SBIDBR)
The received data can be read and transferred data can be written by reading or
writing the SBIDBR.
In the master mode, after the start condition is generated the slave address and the
direction bit are set in this register.
(16) I2CBUS Address Register (I2CAR)
I2CAR<SA6:0> is used to set the slave address when the TMP92CZ26A functions as
a slave device.
The slave address output from the master device is recognized by setting the
I2CAR<ALS> to “0”. The data format is the addressing format. When the slave
address is not recognized at the <ALS> = “1”, the data format is the free data format.
(17) Setting register for IDLE2 mode operation (SBIBR0)
SBIBR0<I2SBI> is the register setting operation/stop during IDLE2-mode.
Therefore, setting <I2SBI> is necessary before the HALT instruction is executed.
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3.15.6 Data Transfer in I2C Bus Mode
(1) Device initialization
Set the SBICR1<ACK, SCK2:0>, Set SBIBR1 to “1” and clear bits 7 to 5 and 3 in the
SBICR1 to “0”.
Set a slave address <SA6:0> and the <ALS> (<ALS> = “0” when an addressing format)
to the I2CAR.
For specifying the default setting to a slave receiver mode, clear “0” to the <MST, TRX,
BB> and set “1” to the <PIN>, “10” to the <SBIM1:0>.
7 6 5 4 3 2 1 0
SBICR1 ← 0 0 0 X 0 X X X
I2CAR
← X X X X X X X X
Set acknowledge and SCL clock.
Set slave address and address recognition mode.
Set to slave receiver mode.
SBICR2 ← 0 0 0 1 1 0 0 0
Note: X: Don’t care
(2) Start condition and slave address generation
a. Master Mode
In the Master Mode, the start condition and the slave address are generated as
follows.
Check a bus free status (when <BB> = “0”).
Set the SBICR1<ACK> to “1” (Acknowledge Mode) and specify a slave address
and a direction bit to be transmitted to the SBIDBR.
When SBICR2<BB> = “0”, the start condition are generated by writing “1111” to
SBICR2<MST, TRX, BB, PIN>. Subsequently to the start condition, nine clocks
are output from the SCL pin. While eight clocks are output, the slave address and
the direction bit which are set to the SBIDBR. At the 9th clock, the SDA line is
released and the acknowledge signal is received from the slave device.
An INTSBI interrupt request occurs at the falling edge of the 9th clock. The
<PIN> is cleared to “0”. In the Master Mode, the SCL pin is pulled down to the
Low-level while <PIN> is “0”. When an interrupt request occurs, the <TRX> is
changed according to the direction bit only when an acknowledge signal is
returned from the slave device.
Setting in main routine
7 6 5 4 3 2 1 0
← SBISR
Reg.
Reg.
← Reg. e 0x20
if Reg.
Then
≠ 0x00
Wait until bus is free.
SBICR1 ← X X X 1 X X X X
SBIDBR1 ← X X X X X X X X
SBICR2 ← 1 1 1 1 1 0 0 0
Set to acknowledgement mode.
Set slave address and direction bit.
Generate start condition.
In INTSBI interrupt routine
INTCLR ← 0X2a
Process
Clear the interrupt request
End of interrupt
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b. Slave Mode
In the Slave Mode, the start condition and the slave address are received.
z
After the start condition is received from the master device, while eight clocks are
output from the SCL pin, the slave address and the direction bit that are output
from the master device are received.
When a GENERAL CALL or the same address as the slave address set in I2CAR
is received, the SDA line is pulled down to the Low-level at the 9th clock, and the
acknowledge signal is output.
An INTSBI interrupt request occurs on the falling edge of the 9th clock. The
<PIN> is cleared to “0”. In Slave Mode the SCL line is pulled down to the
Low-level while the <PIN> = “0”.
SCL pin
SDA pin
1
A6
2
3
4
5
6
7
8
9
A5
A4
A3
A2
A1
A0
R/
ACK
W
Acknowledge
signal from a
slave device
Start condition
Slave address + Direction bit
<PIN>
INTSBI
interrupt request
Output of master
Output of slave
Figure 3.15.14 Start condition generation and slave address transfer
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(3) 1-word Data Transfer
Check the <MST> by the INTSBI interrupt process after the 1-word data transfer is
completed, and determine whether the mode is a master or slave.
a. If <MST> = “1” (Master Mode)
Check the <TRX> and determine whether the mode is a transmitter or
receiver.
When the <TRX> = “1” (Transmitter mode)
Check the <LRB>. When <LRB> is “1”, a receiver does not request data.
Implement the process to generate a stop condition (Refer to 3.15.6 (4)) and
terminate data transfer.
When the <LRB> is “0”, the receiver is requests new data. When the next
transmitted data is 8 bits, write the transmitted data to SBIDBR. When the next
transmitted data is other than 8 bits, set the <BC2:0> <ACK> and write the
transmitted data to SBIDBR. After written the data, <PIN> becomes “1”, a serial
clock pulse is generated for transferring a new 1-word of data from the SCL pin,
and then the 1-word data is transmitted. After the data is transmitted, an
INTSBI interrupt request occurs. The <PIN> becomes “0” and the SCL line is
pulled down to the Low-level. If the data to be transferred is more than one word
in length, repeat the procedure from the <LRB> checking above.
INTSBI interrupt
if MST = 0
Then shift to the process when slave mode
if TRX = 0
Then shift to the process when receiver mode.
if LRB = 0
Then shift to the process that generates stop condition.
7 6 5 4 3 2 1 0
SBICR1
← X X X X X X X X
Set the bit number of transmit and ACK.
Write the transmit data.
SBIDBR ← X X X X X X X X
End of interrupt
Note: X: Don’t care
SCL
SDA
1
2
3
4
5
6
7
8
9
Write to SBIDBR
D7 D6
D5
D4
D3
D2
D1
D0
ACK
Acknowledge
signal from a
receiver
<PIN>
INTSBI
interrupt request
Output from master
Output from slave
Figure 3.15.15 Example in which <BC2:0> = “000” and <ACK> = “1” in transmitter mode
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When the <TRX> is “0” (Receiver mode)
When the next transmitted data is other than 8 bits, set <BC2:0> <ACK> and
read the received data from SBIDBR to release the SCL line (data which is read
immediately after a slave address is sent is undefined). After the data is read,
<PIN> becomes “1”.
Serial clock pulse for transferring new 1 word of data is defined SCL and
outputs “L” level from SDA pin with acknowledge timing.
An INTSBI interrupt request then occurs and the <PIN> becomes “0”, Then the
TMP92CZ26A pulls down the SCL pin to the Low-level. The TMP92CZ26A
outputs a clock pulse for 1-word of data transfer and the acknowledge signal each
time that received data is read from the SBIDBR.
Read SBIDBR
SCL pin
SDA pin
<PIN>
1
2
3
4
5
6
7
8
9
D7
D6
D5
D4
D3
D2
D1
D0
ACK
New D7
Acknowledge signal
to a transmitter
INTSBI
interrupt request
Output from Master
Output from Slave
Figure 3.15.16 Example of when <BC2:0> = “000”, <ACK> = “1” in receiver mode
In order to terminate the transmission of data to a transmitter, clear <ACK> to
“0” before reading data which is 1-word before the last data to be received. The
last data word does not generate a clock pulse as the Acknowledge signal. After
the data has been transmitted and an interrupt request has been generated, set
<BC2:0> to “001” and read the data. The TMP92CZ26A generates a clock pulse
for a 1-bit data transfer. Since the master device is a receiver, the SDA line on the
bus remains High. The transmitter interprets the High signal as an ACK signal.
The receiver indicates to the transmitter that data transfer is complete.
After the one data bit has been received and an interrupt request been generated,
condition generation) and terminates data transfer.
1
2
3
4
5
6
7
8
1
SCL pin
SDA pin
<PIN>
D7
D6
D5
D4
D3
D2
D1
D0
Acknowledge signal
sent to a transmitter
INTSBI
interrupt request
“0” → <ACK>
“001” → <BC2:0>
Read SBIDBR
Read SBIDBR
Output of Master
Output of Slave
Figure 3.15.17 Termination of data transfer in master receiver mode
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Example: In case receive data N times
INTSBI interrupt (After transmitting data)
7 6 5 4 3 2 1 0
SBICR1 ← X X X X X X X X
Set the bit number of receive data and ACK.
Load the dummy data.
Reg.
← SBIDBR
End of interrupt
INTSBI interrupt (Receive data of 1st to (N−2) th)
7 6 5 4 3 2 1 0
Reg.
← SBIDBR
Load the data of 1st to (N−2)th.
End of interrupt
INTSBI interrupt ((N−1) th Receive data)
7 6 5 4 3 2 1 0
SBICR1 ← X X X 0 0 X X X
Not generate acknowledge signal
Reg.
← SBIDBR
Load the data of (N−1)th
End of interrupt
INTSBI interrupt (Nth Receive data)
7 6 5 4 3 2 1 0
SBICR1 ← 0 0 1 0 0 X X X
Generate the clock for 1bit transmit
Receive the data of Nth.
Reg.
← SBIDBR
End of interrupt
INTSBI interrupt (After receiving data)
The process of generating stop condition
End of interrupt
Finish the transmit of data
Note: X: Don’t care
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b. If <MST> = 0 (Slave Mode)
In the slave mode the TMP92CZ26A operates either in normal slave mode or in
slave mode after losing arbitration.
In the slave mode, an INTSBI interrupt request occurs when the TMP92CZ26A
receives a slave address or a GENERAL CALL from the master device, or when a
GENERAL CALL is received and data transfer is complete, or after matching
received address. In the master mode, the TMP92CZ26A operates in a slave mode
if it losing arbitration. An INTSBI interrupt request occurs when a word data
transfer terminates after losing arbitration. When an INTSBI interrupt request
occurs the <PIN> is cleared to “0” and the SCL pin is pulled down to the Low-level.
Either reading/writing from/to the SBIDBR or setting the <PIN> to “1” will
release the SCL pin after taking t
time.
LOW
Check the SBISR<AL>, <TRX>, <AAS>, and <AD0> and implements processes
according to conditions listed in the next table.
Example: In case matching slave address in slave receive mode, direction bit is “1”.
INTSBI interrupt
if TRX = 0
Then shift to other process
if AL = 1
Then shift to other process
if AAS = 0
Then shift to other process
7 6 5 4 3 2 1 0
SBICR1
SBIDBR
← X X X 1 X X X X
Set the bit number of transmit.
Set the data of transmit.
← X X X X X X X X
Note: X: Don’t care
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Table 3.15.2 Operation in the slave mode
Conditions
<TRX> <AL> <AAS> <AD0>
Process
The TMP92CZ26A loses arbitration
when transmitting a slave address and
receives a slave address for which the
value of the direction bit sent from
another master is “1”.
Set the number of bits a word in
<BC2:0> and write the transmitted data
to SBIDBR
1
1
1
0
0
In Salve Receiver Mode, the
TMP92CZ26A receives a slave address
for which the value of the direction bit
sent from the master is “1”.
1
Check the <LRB> setting. If <LRB> is
set to “1”, set <PIN> to “1” since the
receiver win no request the data which
follows. Then, clear <TRX> to “0” to
release the bus. If <LRB> is cleared to
“0”, set <BC2:0> to the number of bits in
a word and write the transmitted data to
SBIDBR since the receiver requests
next data.
0
In Salve Transmitter Mode, a single
word of is transmitted.
0
0
The TMP92CZ26A loses arbitration
when transmitting a slave address and
receives a slave address or GENERAL
CALL for which the value of the direction
bit sent from another master is “0”.
The TMP92CZ26A loses arbitration
when transmitting a slave address or
data and terminates word data transfer.
In Slave Receiver Mode, the
1
0
1
0
1/0
0
1
Read the SBIDBR for setting the <PIN>
to “1” (reading dummy data) or set the
<PIN> to “1”.
0
TMP92CZ26A receives a slave address
or GENERAL CALL for which the value
of the direction bit sent from the master
is “0”.
1/0
1/0
0
In Slave Receiver Mode, the
Set <BC2:0> to the number of bits in a
word and read the received data from
SBIDBR.
TMP92CZ26A terminates receiving
word data.
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TMP92CZ26A
(4) Stop condition generation
When SBISR<BB> = “1”, the sequence for generating a stop condition start by
writing “1” to SBICR2<MST, TRX, PIN> and “0” to SBICR2<BB>. Do not modify the
contents of SBICR2<MST, TRX, PIN, BB> until a stop condition has been generated
on the bus. When the bus’s SCL line has been pulled Low by another device, the
TMP92CZ26A generates a stop condition when the other device has released the SCL
line and SDA pin rising.
7 6 5 4 3 2 1 0
SBICR2 ← 1 1 0 1 1 0 0 0
Generate stop condition.
Stop condition
“1” →<MST>
“1” →<TRX>
“0” →<BB>
“1” →<PIN>
Internal SCL
SCL pin
SDA Pin
<PIN>
<BB> (Read)
Figure 3.15.18 Stop condition generation (Single master)
“1” →<MST>
“1” →<TRX>
“0” →<BB>
“1” →<PIN>
Stop condition
Internal SCL
SCL Pin
The case of pulled low
by another device
SDA Pin
<PIN>
<BB> (Read)
Figure 3.15.19 Stop condition generation (Multi master)
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TMP92CZ26A
(5) Restart
Restart is used during data transfer between a master device and a slave device to
change the data transfer direction.
The following description explains how to restart when the TMP92CZ26A is in
Master Mode.
Clear SBICR2<MST, TRX, and BB> to 0 and set SBICR2<PIN> to 1 to release the
bus. The SDA line remains High and the SCL pin is released. Since a stop condition
has not been generated on the bus, other devices assume the bus to be in busy state.
And confirm SCL pin, that SCL pin is released and become bus-free state by
SBISR<BB> = “0” or signal level “1” of SCL pin in port mode. Check the <LRB> until it
becomes 1 to check that the SCL line on a bus is not pulled down to the low-level by
other devices. After confirming that the bus remains in a free state, generate a start
condition using the procedure described in (2).
In order to satisfy the set-up time requirements when restarting, take at least 4.7 μs of
waiting time by software from the time of restarting to confirm that the bus is free
until the time to generate the start condition.
7 6 5 4 3 2 1 0
SBICR2 ← 0 0 0 1 1 0 0 0
if SBISR<BB> ≠ 0
Release the bus
Check if SCL pin is released.
Then
if SBISR<LRB> ≠ 1
Check if SCL pin of other device is “L” level.
Then
4.7 μs Wait
SBICR1 ← X X X 1 X X X X
SBIDBR ← X X X X X X X X
SBICR2 ← 1 1 1 1 1 0 0 0
Set acknowledgement mode.
Set the slave address and direction bit.
Generate start condition.
Note: X: Don’t care
“0” → <MST>
“0” → <TRX>
“0” → <BB>
“1” → <PIN>
“1” → <MST>
“1” → <TRX>
“1” → <BB>
“1” → <PIN>
4.7 μs (Min)
Start condition
SCL line
Internal SCL
output
9
SDA line
<LRB>
<BB>
<PIN>
Figure 3.15.20 Timing chart for generate restart
Note: Don’t write <MST> = “0”, when <MST> = “0” condition. (Cannot be restarted)
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TMP92CZ26A
3.16 USB Controller
3.16.1 Outline
This USB controller (UDC) is designed for various serial links to construct USB system.
The outline is as follows:
(1) Compliant with USB rev1.1
(2) Full-speed: 12 Mbps (Not supported low-speed (1.5 Mbps))
(3) Auto bus enumeration with 384-byte descriptor RAM
(4) Supported 3 kinds of transfer type: Control, interrupt and bulk
Endpoint 0:
Endpoint 1:
Endpoint 2:
Endpoint 3:
Control
64 bytes × 1-FIFO
64 bytes × 2-FIFO
64 bytes × 2-FIFO
8 bytes × 1-FIFO
BULK (out)
BULK (in)
Interrupt (in)
(5) Built-in DPLL which generates sampling clock for receive data
(6) Detecting and generating SOP, EOP, RESUME, RESET and TIMEOUT
(7) Encoding and decoding NRZI data
(8) Inserting and discarding stuffed bit
(9) Detecting and checking CRC
(10) Generating and decoding packet ID
(11) Built-in power management function
(12) Supported dual packet mode
Note1:TMP92CZ26A don’t have special terminal that control pull-up resister for D+pin. So, need to add external
switch and control it.
Note2:There are some difference between our specification and USB 1.1. Refer and check “3.16.11 Notice and
restrictions at first”.
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3.16.1.1 System Configuration
The USB controller (UDC) is consisted of following 3 blocks.
1. 900/H1 CPU I/F
2. UDC core block (DPLL, SIE, IFM and PWM), request controller, descriptor RAM
and 4 endpoint FIFO
3. USB transceiver
About above “1.” is explained at 3.16.2, and “2.” is 3.16.3.
UDC
Descriptor RAM
384 bytes
Request controller
ADDRESS
900/H1 CPU
WR
interface
RD
UDC core
Endpoint 0:
FIFO (64 bytes × 1)
I/F
PWM
Endpoint 1:
FIFO (64 bytes × 2)
FIFO
manager
DPLL
Endpoint 2:
FIFO (64 bytes × 2)
IFM
D+
USB
transceiver
SIE
D−
Endpoint 3:
FIFO (8 bytes × 1)
Figure 3.16.1 UDC Block Diagram
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3.16.1.2 Example
USB host
USB device
USB host
TMP92CZ26A
USB
USB
VCC
VSS
Connector Connector
X1
X2
GND
VBUS
INTx (detect rising)
PorTXX
10MHz
R6
R7
USB
cable
X1USB
R1
48MHz
D+
R2
R3
R8
R9
D−
R5
R4
OFF at
“H”
OFF at
"H"
If using USB controller in TMP92CZ26A, above setting is needed.
1) Pull-up of D+ pin
・ In the USB standard, in Full Speed connection, D+ pin must be set to pull-up.
And this pull-up is needed ON/OFF control by S/W.
Recommendation value: R1=1.5kΩ
2) Add cascade resistor of D+, D-signal
・ In the USB standard, in D+, D- signal, cascade resistor must be added to each
signal. Recommendation value : R2=27Ω, R3=27Ω
3) Flow current provision of the Connector connection and D+ pin, D- pin
・ In D+, D- pin of TMP92CZ26A, level must be fixed for flow current provision
when not using (it is not connect to host). In this case, it is showed that method of
controlling the pull-down resistor for fixed level by using detection signal of
connector connection.
Recommendation value: R4=10kΩ, R5=10kΩ
・ It is showed as example of the connector connection detection that method of
detecting by using VBUS (5V voltage).
Note: If rising of waveform is solw, recommned that likely baffering for waveform.
Recommendation value: R6=60kΩ, R7=100kΩ
(VBUS reducing current when suspend<500μA)
4) Connect oscillator of 10MHz to X1,X2, or input 48MHz clock to X1USB
・ If using USB by using the combination external 10MHz oscillator and internal,
Stage of external hub which can be used is restricted by the precision of internal
(Max 3 stages).
・ If 5 stages connection is needed for external hub, it is needed that input 48MHz
clock from X1USB pin (Restriction ≤±2500ppm.)
5) HOST side pull-down resistor
・ In the USB regulation, set pull-down D+ pin and D- signal at USB_HOST side.
Recommendation value: R8=15kΩ, R9=15kΩ
Note: Above connection and resistor etc, is example. Operation is not guranteed. Please confirm the
newest USB standar and the operation on your setting.
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TMP92CZ26A
3.16.2 900/H1 CPU I/F
The 900/H1 CPU I/F is a bridge between 900/H1 CPU and UDC and it mainly works
following operations.
•
•
•
INTUSB (interrupt from UDC) generation
A bridge for SFR
USB clock control (48 MHz)
3.16.2.1 SFRs
The 900/H1 CPU I/F have following SFRs to control UDC and USB transceiver.
• USB control
USBCR1
(USB control register 1)
• USB interrupt control
USBINTFR1
USBINTFR2
USBINTFR3
USBINTFR4
USBINTMR1
USBINTMR2
USBINTMR3
USBINTMR4
(USB interrupt flag register 1)
(USB interrupt flag register 2)
(USB interrupt flag register 3)
(USB interrupt flag register 4)
(USB interrupt mask register 1)
(USB interrupt mask register 2)
(USB interrupt mask register 3)
(USB interrupt mask register 4)
Figure 3.16.2 900/H1 CPU I/F SFR
Address
Read/Write
SFR Symbol
07F0H
07F1H
07F2H
07F3H
07F4H
07F5H
07F6H
07F7H
07F8H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
USBINTFR1
USBINTFR2
USBINTFR3
USBINTFR4
USBINTMR1
USBINTMR2
USBINTMR3
USBINTMR4
USBCR1
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3.16.2.2 USBCR1 Register
This register is used to set USB clock enables, transceiver enable etc.
7
TRNS_USE
R/W
6
WAKEUP
R/W
5
4
3
2
1
SPEED
R/W
1
0
USBCLKE
R/W
bit Symbol
Read/Write
After reset
USBCR1
(07F8H)
0
0
0
Function
•
•
TRNS_USE
0: Disable USB transceiver
1: Enable USB transceiver
(Bit7)
Set to “1” for TMP92CZ26A.
WAKEUP (Bit6)
0: −
1: Start remote-wakeup-function
When the remote-wakeup-function is needed, at first check the
Current_Config<REMOTE WAKEUP>.
If the <REMOTE WAKEUP> = “1” (means SUSPEND-status), write “1”,
and “0” to <WAKEUP> after checking by this, remote-wakeup-function will be
started.
If the <REMOTE WAKEUP> = “0” or EP0, 1, 2, 3_STATUS<SUSPEND> =
“0”, don’t write “1” to <WAKEUP>.
•
•
SPEED
1: Full speed (12 MHz)
0: Reserved
(Bit1)
This bit selects USB speed.
Set to “1” for TMP92CZ26A.
USBCLKE
(Bit0)
0: Disable USB clock
1: Enable USB clock
This bit controls to supply USB clock.
The USB clock (named “fUSB”: 48MHz) is generated by an internal PLL.
When the USB is started to use, write “1” to <USBCLKE> after confirmed the
lock up of PLL is terminated.
And when the PLL is stopped, stop PLL after writing “0” to <USBCLKE>.
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TMP92CZ26A
3.16.2.3 USBINTFRn, MRn Register
These SFRs control to generate INTUSB (only one interrupt to CPU) because the
UDC outputs 23 interrupt source.
The USBINTMRn are mask registers and the USBINTFRn are flag registers. In
the INTUSB routine, execute operations according to generated interrupt source after
checking USBINTFRn.
The below is the common specification for all MASK and FLAG registers.
(Common spec for all mask and flag registers.)
Mask register
Interrupt source
(Set by rising edge)
Flag register
Writing “0” to flag register
A
B
C
D
A: The flag register is not set because mask register = “1”.
B: The flag register is not set because interrupt souce changes “1” → “0”.
C: The flag register is set because mask register = “0” and interrupt souce changes “0” → “1”.
D: The flag register is reset to “0” by writing “0” to flag register.
Note 1:Both “INTUSB generated number” and “bit number which is set to flag register” are not always equal. In the
INTUSB interrupt routine, clear FLAG register (USBINTFRn) after checking it. The interrupt request flag, which
is occurred between jump to the INTUSB interrupt routine and read flag register (USBINTFRn), is kept in
interrupt controller.
Therefore, after returning from the interrupt routine, CPU jumps to INTUSB interrupt routine again. And
when read the flag register (USBINTFRn), none of the bits are set to “1”. For this case, special software is
needed in order not to finish as error routine.
Note 2:When USBINTMRn or USBINTFRn is written, disable INTUSB (write 00H to INTEUSB register) before it.
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7
6
5
INT_SUS
R/W
0
4
INT_RESUME
R/W
3
INT_CLKSTOP
R/W
2
INT_CLKON
R/W
1
0
INT_URST_STR
bit Symbol
Read/Write
After reset
Function
INT_URST_END
USBINTFR1
(07F0H)
R/W
0
R/W
0
Prohibit
to read
modify
write
0
0
0
When read 0: Not generate interrupt
1: Generate interrupt
When write 0: Clear flag
1: −
Note: Above interrupts can release Halt state from IDLE2 and IDLE1 mode. (STOP mode can not be released)
*Those 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode. Therefore, the system of low power
dissipation can be built. However, the way of use is limited as below.
Shift to IDLE1 mode :
Execute Halt instruction when the flag of INT_SUS or INT_CLKSTOP is “1” ( SUSPEND state )
Release from IDLE1 mode :
Release Halt state by the request of INT_RESUME or INT_CLKON ( request of release SUSPEND )
Release Halt state by the request of INT_URST_STR or INT_URST_END ( request of RESET )
•
•
INT_URST_STR (Bit7)
This is a flag for INT_URST_STR (“USB reset” start - interrupt).
This is set to “1” when the UDC started to receive “USB reset” signal from
USB-host.
An application program has to initialize whole UDC by this interrupt.
INT_URST_END (Bit6)
This is a flag for INT_URST_END (“USB reset” end - interrupt).
This is set to “1” when the UDC receive “USB reset end” signal from
USB-host.
•
•
•
INT_SUS (Bit5)
This is a flag for INT_SUS (suspend - interrupt).
This is set to “1” when USB change to “suspend status”.
INT_RESUME (Bit4)
This is a flag for INT_RESUME (resume - interrupt).
This is set to “1” when USB change to “resume status”.
INT_CLKSTOP (Bit3)
This is a flag for INT_CLKSTOP (enable stopping clock supply - interrupt).
This is set to “1” when USB enable stopping clock supply after changing to
“suspend status”.
•
INT_CLKON (Bit2)
This is a flag for INT_CLKON (enabled starting clock supply - interrupt).
This is set to “1” when USB enable starting clock supply after change to
“resume status”.
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0
7
EP1_FULL_A
R/W
6
EP1_Empty_A
R/W
5
EP1_FULL_B
R/W
4
EP1_Empty_B
R/W
3
EP2_FULL_A
R/W
2
EP2_Empty_A
R/W
1
bit Symbol
Read/Write
After reset
Function
EP2_FULL_B
EP2_Empty_B
USBINTFR2
(07F1H)
R/W
0
R/W
0
0
0
0
0
0
0
Prohibit
to read
modify
write
When read 0: Not generate interrupt
1: Generate interrupt
When write 0: Clear flag
1: −
Note: Above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode can not be released.)
7
EP3_FULL_A
R/W
6
EP3_Empty_A
R/W
5
EP3_FULL_B
R/W
4
EP3_Empty_B
R/W
3
2
1
0
bit Symbol
Read/Write
After reset
Function
USBINTFR3
(07F2H)
0
0
0
0
Prohibit
to read
modify
write
When read
0: Not generate interrupt
1: Generate interrupt
0: Clear flag
When write
1: −
Note: Above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode can not be released.)
•
•
EPx_FULL_A/B:
(When transmitting)
This is set to “1” when CPU full write data to FIFO_A/B.
(When receiving)
This is set to “1” when UDC full receive data to FIFO_A/B.
EPx_Empty_A/B:
(When transmitting)
This is set to “1” when FIFO become empty after transmission.
(When receiving)
This is set to “1” when FIFO become empty after CPU read all data from FIFO.
Note: The flag of EPx_FULL_A/B and EPx_Empty_A/B are not status flag. Therefore, check DATASET
register if the FIFO-status is needed.
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0
7
INT_SETUP
R/W
6
INT_EP0
R/W
0
5
INT_STAS
R/W
0
4
INT_STASN
R/W
3
INT_EP1N
R/W
0
2
INT_EP2N
R/W
0
1
INT_EP3N
R/W
0
bit Symbol
Read/Write
After reset
Function
USBINTFR4
(07F3H)
0
0
Prohibit
to read
modify
write
When read
0: Not generate interrupt
1: Generate interrupt
When write 0: Clear flag
1: −
Note: Above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode can not be released.)
•
•
INT_SETUP (Bit7)
This is a flag for INT_SETUP (setup - interrupt).
This is set to “1” when the UDC receive request that S/W (software) control
is needed from USB host.
By S/W (INT_SETUP routine), at first, read device request of 8-bytes from
UDC and execute operation according to each request.
INT_EP0 (Bit6)
This is a flag for INT_EP0 (received data of the data phase for Control
transfer type - interrupt).
This is set to “1” when the UDC receive data of the data phase for Control
transfer type. At the Control write transfer, data reading from FIFO is needed
if this interrupt occur. At the Control read transfer, transmission data writing
to FIFO is needed if this interrupts occurred.
By host may don’t assert “ACK” of last packet in the data stage. In that case,
this interrupt cannot be generated. So, ignore this interrupt of after last
packet data was written in the data stage because the transmission data
number is specified by the host, or it depends on the capacity of the device.
•
INT_STAS (Bit5)
This is a flag for INT_STAS (status stage end - interrupt).
This is set to “1” when the status stage end.
If this interrupt is generated, it means that request ended normally.
If this interrupt is not generated and INT_SETUP is generated,
EP0_STATUS <STAGE_ERR> is set to “1” and it means that request didn’t
end normally.
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•
INT_STASN (Bit4)
This is a flag for INT_STASN (change host status stage - interrupt).
This is set to “1” when the USB host change to status stage at the Control
read transfer type. This interrupt is needed if data length is less than
wLength (specified by the host).
But if the USB host change to status stage, this interrupt is always
generated because of this signal is designed by using NAK of first packet. So,
to avoid that this interrupt always generate, use mask register USBINTMRn.
Disable this interrupt before data of last payload is written.
•
INT_EPxN (Bit3, 2, 1)
This is a flag for INT_EPxN (NAK acknowledge to the USB host -
interrupt).
This is set to “1” when the Endpoint1, 2 and 3 transmit NAK.
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TMP92CZ26A
7
6
5
MSK_SUS
R/W
1
4
MSK_RESUME
R/W
3
2
MSK_CLKON
R/W
1
0
bit Symbol
Read/Write
After reset
Function
MSK_URST_STR
MSK_URST_END
MSK_CLKSTOP
USBINTMR1
(07F4H)
R/W
1
R/W
1
R/W
1
1
1
0: Be not masked 1: Be masked
•
•
•
•
•
•
MSK_URST_STR (Bit7)
This is a mask register for USBINTFR1<INT_URST_STR>.
MSK_URST_END (Bit6)
This is a mask register for USBINTFR1<INT_URST_END>.
MSK_SUS (Bit5)
This is a mask register for USBINTFR1<INT_SUS>.
MSK_RESUME (Bit4)
This is a mask register for USBINTFR1<INT_RESUME>.
MSK_CLKSTOP (Bit3)
This is a mask register for USBINTFR1<INT_CLKSTOP>.
MSK_CLKON (Bit2)
This is a mask register for USBINTFR1<INT_CLKON>.
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0
7
EP1_MSK_FA
R/W
6
EP1_MSK_EA
R/W
5
EP1_MSK_FB
R/W
4
EP1_MSK_EB
R/W
3
EP2_MSK_FA
R/W
2
EP2_MSK_EA
R/W
1
bit Symbol
Read/Write
After reset
Function
EP2_MSK_FB
EP2_MSK_EB
USBINTMR2
(07F5H)
R/W
1
R/W
1
1
1
1
1
1
1
0: Be not masked 1: Be masked
•
EP1/2_MSK_FA/FB/EA/EB
This is a mask register for USBINTFR2<EPx_FULL_A/B> or
<EPx_Empty_A/B>.
7
EP3_MSK_FA
R/W
6
EP3_MSK_EA
R/W
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
USBINTMR3
(07F6H)
1
1
0: Be not masked
1: Be masked
•
EP3_MSK_FA/FB/EA/EB:
This is a mask register for USBINTFR3<EP3_FULL_A> or
<EP3_Empty_A>.
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0
7
MSK_SETUP
R/W
6
MSK_EP0
R/W
1
5
MSK_STAS
R/W
4
MSK_STASN
R/W
3
MSK_EP1N
R/W
2
MSK_EP2N
R/W
1
bit Symbol
Read/Write
After reset
Function
MSK_EP3N
USBINTMR4
(07F7H)
R/W
1
1
1
1
1
1
0: Be not masked
1: Be masked
•
•
•
•
•
•
•
MSK_SETUP (Bit7)
This is a mask register for USBINTFR4<INT_SETUP>.
MSK_EP0 (Bit6)
This is a mask register for USBINTFR4<INT_EP0>.
MSK_STAS (Bit5)
This is a mask register for USBINTFR4<INT_STAS>.
MSK_STASN (Bit4)
This is a mask register for USBINTFR4<INT_STASN>.
MSK_EP1N (Bit3)
This is a mask register for USBINTFR4<INT_EP1N>.
MSK_EP2N (Bit2)
This is a mask register for USBINTFR4<INT_EP2N>.
MSK_EP3N (Bit1)
This is a mask register for USBINTFR4<INT_EP3N>.
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3.16.3 UDC CORE
3.16.3.1 SFRs
The UDC CORE has following SFRs to control UDC and USB transceiver.
a) FIFO
Endpoint 0 to 3 FIFO register
b) Device request
bmRequestType
wValue_L
register
register
register
register
bRequest
wValue_H
wIndex_H
wLength_H
register
register
register
register
wIndex_L
wLength_L
c) Status
Current_Config
StandardRequest
EPx_STATUS
register
register
register
USB_STATE
Request
register
register
d) Setup
EPx_BCS
register
register
register
EPx_SINGLE
Request Mode
PortStatus
register
register
register
Standard Request Mode
Descriptor RAM
e) Control
EPx_MODE
COMMAND
register
register
register
EOP
register
register
register
INT_ Control
USBREADY
Setup Received
f) Others
ADDRESS
register
register
register
register
register
DATASET
register
register
register
register
EPx_SIZE_L_A
EPx_SIZE_L_B
FRAME_L
EPx_SIZE_H_A
EPx_SIZE_H_B
FRAME_H
USBBUFF TEST
92CZ26A-379
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TMP92CZ26A
Figure 3.16.3 UDC CORE SFRs (1/3)
Address
Read/Write
SFR Symbol
0500H
0501H
0502H
0503H
R/W
R/W
R/W
R/W
Descriptor RAM0
Descriptor RAM1
Descriptor RAM2
Descriptor RAM3
067DH
067EH
067FH
0780H
0781H
0782H
0783H
*0784H
*0785H
*0786H
*0787H
*0788H
0789H
078AH
078BH
*078CH
*078DH
*078EH
*078FH
0790H
0791H
0792H
0793H
*0794H
*0795H
*0796H
*0797H
0798H
0799H
079AH
079BH
*079CH
*079DH
*079EH
*079FH
07A1H
07A2H
07A3H
*07A4H
*07A5H
*07A6H
*07A7H
*07A8H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
Descriptor RAM381
Descriptor RAM382
Descriptor RAM383
ENDPOINT0
ENDPOINT1
ENDPOINT2
ENDPOINT3
ENDPOINT4
ENDPOINT5
ENDPOINT6
ENDPOINT7
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
EP1_MODE
EP2_MODE
EP3_MODE
EP4_MODE
EP5_MODE
EP6_MODE
EP7_MODE
EP0_STATUS
EP1_STATUS
EP2_STATUS
EP3_STATUS
EP4_STATUS
EP5_STATUS
EP6_STATUS
EP7_STATUS
EP0_SIZE_L_A
EP1_SIZE_L_A
EP2_SIZE_L_A
EP3_SIZE_L_A
EP4_SIZE_L_A
EP5_SIZE_L_A
EP6_SIZE_L_A
EP7_SIZE_L_A
EP1_SIZE_L_B
EP2_SIZE_L_B
EP3_SIZE_L_B
EP4_SIZE_L_B
EP5_SIZE_L_B
EP6_SIZE_L_B
EP7_SIZE_L_B
Reserved
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
–
Note: “*” is not used at TMP92CZ26A.
92CZ26A-380
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TMP92CZ26A
Figure 3.16.4 UDC CORE SFRs (2/3)
Address
Read/Write
SFR Symbol
07A9H
07AAH
07ABH
*07ACH
*07ADH
*07AEH
*07AFH
07B1H
07B2H
07B3H
*07B4H
*07B5H
*07B6H
*07B7H
07C0H
07C1H
07C2H
07C3H
07C4H
07C5H
07C6H
07C7H
07C8H
07C9H
07CAH
07CBH
07CCH
07CDH
07CEH
07CFH
07D0H
07D1H
*07D1H
07D3H
*07D4H
*07D5H
07D6H
*07D7H
07D8H
07D9H
*07DAH
*07DBH
*07DCH
*07DDH
07DEH
07DFH
R
R
EP1_SIZE_H_A
EP2_SIZE_H_A
EP3_SIZE_H_A
EP4_SIZE_H_A
EP5_SIZE_H_A
EP6_SIZE_H_A
EP7_SIZE_H_A
EP1_SIZE_H_B
EP2_SIZE_H_B
EP3_SIZE_H_B
EP4_SIZE_H_B
EP5_SIZE_H_B
EP6_SIZE_H_B
EP7_SIZE_H_B
bmRequestType
bRequest
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
wValue_L
R
wValue_H
R
wIndex_L
R
wIndex_H
R
wLength_L
R
wLength_H
W
Setup Received
Current_Config
Standard Request
Request
R
R
R
R
DATASET1
R
DATASET2
R
USB_STATE
EOP
W
W
COMMAND
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
EPx_SINGLE1
EPx_SINGLE2
EPx_BCS1
EPx_BCS2
Reserved
INT_Control
Reserved
Standard Request Mode
Request Mode
Reserved
Reserved
Reserved
Reserved
ID_CONTROL
ID_STATE
R
Note: “*” is not used at TMP92CZ26A.
92CZ26A-381
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TMP92CZ26A
Figure 3.16.5 UDC CORE SFRs (3/3)
Address
Read/Write
SFR Symbol
07E0H
07E1H
07E2H
07E3H
*07E4H
*07E5H
07E6H
*07E7H
07E8H
R/W
R
Port_Status
FRAME_L
FRAME_H
ADDRESS
Reserved
R
R
–
–
Reserved
R/W
–
USBREADY
Reserved
W
Set Descriptor STALL
Note: “*” is not used at TMP92CZ26A.
92CZ26A-382
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TMP92CZ26A
3.16.3.2 EPx_FIFO Register (x: 0 to 3)
This register is prepared for each endpoint independently.
This is the window register from or to FIFO RAM.
In the auto bus enumeration, the request controller in UDC set mode, which is
defined at endpoint descriptor for each endpoint automatically. By this, each endpoint
is set to voluntary direction.
7
6
5
4
3
2
1
0
Endpoint0
(0780H)
bit Symbol
Read/Write
After reset
EP0_DATA7
EP0_DATA6
EP0_DATA5
EP0_DATA4
EP0_DATA3
EP0_DATA2
EP0_DATA1
EP0_DATA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
7
6
5
4
3
2
1
0
Endpoint1
(0781H)
bit Symbol
Read/Write
After reset
EP1_DATA7
EP1_DATA6
EP1_DATA5
EP1_DATA4
EP1_DATA3
EP1_DATA2
EP1_DATA1
EP1_DATA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
7
6
5
4
3
2
1
0
Endpoint2
(0782H)
bit Symbol
Read/Write
After reset
EP2_DATA7
EP2_DATA6
EP2_DATA5
EP2_DATA4
EP2_DATA3
EP2_DATA2
EP2_DATA1
EP2_DATA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
7
6
5
4
3
2
1
0
Endpoint3
(0783H)
bit Symbol
Read/Write
After reset
EP3_DATA7
EP3_DATA6
EP3_DATA5
EP3_DATA4
EP3_DATA3
EP3_DATA2
EP3_DATA1
EP3_DATA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Note: Read or write these window registers by using load instruction of 1 byte because of each register have only 1
byte address. Don’t use load instruction of 2 bytes or 4 bytes.
The device request that received from the USB host is stored to following 8-byte
registers.
The 8-byte registers are bmRequestType, bRequest, wValue_L, wValue_H,
wIndex_L, wIndex_H, wLength_L and wLength_H. They are updated whenever new
SETUP token is received from host...
When the UDC receive without error, INT_SETUP interrupt is asserted and it
means the new device request has been received.
And there is a request which is operated automatically by UDC. It depends on
received request.
In that case, the UDC don’t assert INT_SETUP interrupt. A request which the UDC
is operating now can be checked by reading STANDARD_REQUEST_FLAG and
REQUEST_FLAG.
92CZ26A-383
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3.16.3.3 bmRequestType Register
This register shows the bmRequestType field of device request.
7
6
5
4
3
2
1
0
bmRequestType
(07C0H)
bit Symbol
Read/Write
After reset
DIRECTION
REQ_TYPE1 REQ_TYPE0 RECIPIENT4 RECIPIENT3 RECIPIENT2 RECIPIENT1 RECIPIENT0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0: from host to device
1: from device to host
DIRECTION (Bit7)
00: Standard
01: Class
REQ_TYPE [1:0] (Bit6 to bit5)
RECEIPIENT [4:0] (Bit4 to bit0)
10: Vendor
11: (Reserved)
00000: Device
00001: Interface
00010: Endpoint
00011: etc.
Others: (Reserved)
3.16.3.4 bRequest Register
This register shows the bRequest field of device request.
7
6
5
4
3
2
1
0
bRequest
(07C1H)
bit Symbol
Read/Write
After reset
REQUEST7
REQUEST6
REQUEST5
REQUEST4
REQUEST3
REQUEST2
REQUEST1
REQUEST0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
(Standard)
(Printer class)
00000000: GET_STATUS
00000000: GET_DEVICE_ID
00000001: GET_PORT_STATUS
00000010: SOFT_RESET
00000001: CLEAR_FEATURE
00000010: Reserved
00000011: SET_FEATURE
00000100: Reserved
00000101: SET_ADDRESS
00000110: GET_DESCRIPTOR
00000111: SET_DESCRIPTOR
00001000: GET_CONFIGURATION
00001001: SET_CONFIGURATION
00001010: GET_INTERFACE
00001011: SET_INTERFACE
00001100: SYNCH_FRAME
92CZ26A-384
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TMP92CZ26A
3.16.3.5 wValue Register
There are 2 registers; the wValue_L register and wValue_H register. wValue_L
shows the lower-byte of wValue field of device request and wValue_H register shows
upper byte.
7
6
5
4
3
2
1
0
wValue_L
(07C2H)
bit Symbol
Read/Write
After reset
VALUE_L7
VALUE_L6
VALUE_L5
VALUE_L4
VALUE_L3
VALUE_L2
VALUE_L1
VALUE_L0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
7
6
5
4
3
2
1
0
wValue_H
(07C3H)
bit Symbol
Read/Write
After reset
VALUE_H7
VALUE_H6
VALUE_H5
VALUE_H4
VALUE_H3
VALUE_H2
VALUE_H1
VALUE_H0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
3.16.3.6 wIndex Register
There are 2 registers, the wIndex_L register and wIndex_H register. the wIndex_L
register shows the lower byte of wIndex field of device request and wIndex_H register
shows upper byte.
These are usually used to transfer index or offset.
7
6
5
4
3
2
1
0
wIndex_L
(07C4H)
bit Symbol
Read/Write
After reset
INDEX_L7
INDEX_L6
INDEX_L5
INDEX_L4
INDEX_L3
INDEX_L2
INDEX_L1
INDEX_L0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
7
6
5
4
3
2
1
0
wIndex_H
(07C5H)
bit Symbol
Read/Write
After reset
INDEX_H7
INDEX_H6
INDEX_H5
INDEX_H4
INDEX_H3
INDEX_H2
INDEX_H1
INDEX_H0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
3.16.3.7 wLength Register
There are 2 registers, the wLength_L register and wLength_H register. the
wLength_L register shows the lower-byte of wLength field of device request and
wLength_H register shows upper byte.
In case of data phase, these registers show byte number to transfer.
7
6
5
4
3
2
1
0
wLength_L
(07C6H)
bit Symbol
Read/Write
After reset
LENGTH_L7 LENGTH_L6 LENGTH_L5
LENGTH_L4
LENGTH_L3
LENGTH_L2
LENGTH_L1
LENGTH_L0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
7
6
5
4
3
2
1
0
wLength_H
(07C7H)
bit Symbol
Read/Write
After reset
LENGTH_H7 LENGTH_H6 LENGTH_H5 LENGTH_H4 LENGTH_H3 LENGTH_H2 LENGTH_H1 LENGTH_H0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
92CZ26A-385
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3.16.3.8 Setup Received Register
This register informs for the UDC that an application program recognized
INT_SETUP interrupt.
7
D7
W
0
6
D6
W
0
5
D5
W
0
4
D4
W
0
3
D3
W
0
2
D2
W
0
1
D1
W
0
0
D0
W
0
SetupReceived
(07C8H)
bit Symbol
Read/Write
After reset
If this register is accessed by an application program, the UDC release to disabling
access to EP0’s FIFO RAM because the UDC recognized the device request is received.
This is to protect data stored in EP0 in the time from continuous request has been
asserted to an application program recognized INT_SETUP interrupt.
Therefore, write “00H” to this register when the device request in INT_SETUP
routine is recognized.
Note : When EP0_FIFO is accessed register after wrote to this register, the recovery time of 2clock at 12MHz is
needed.
3.16.3.9 Current_Config Register
This register shows the present value that is set by SET_CONFIGURATION and
SET_INTERFACE.
7
6
5
4
3
2
1
0
Current_Config
(07C9H)
bit Symbol
Read/Write
After reset
REMOTEWAKEUP
ALTERNATE[1] ALTERNATE[0] INTERFACE[1] INTERFACE[0]
CONFIG[1]
CONFIG[0]
R
0
R
0
R
0
R
0
R
0
R
0
R
0
CONFIG[1:0] (Bit1 to bit0)
00: UNCONFIGURED
01: CONFIGURED1
10: CONFIGURED2
Set to UNCONFIGURED by the host.
Set to CONFIGURED 1 by the host.
Set to CONFIGURED 2 by the host.
INTERFACE[1:0] (Bit3 to bit2)
00: INTERFACE0
01: INTERFACE1
10: INTERFACE2
Set to INTERFACE 0 by the host.
Set to INTERFACE 1 by the host.
Set to INTERFACE 2 by the host.
ALTERNATE[1:0] (Bit5 to bit4)
00: ALTERNATE0
01: ALTERNATE1
10: ALTERNATE2
Set to ALTERNATE 0 by the host.
Set to ALTERNATE 1 by the host.
Set to ALTERNATE 2 by the host.
REMOTE WAKEUP (Bit7)
0: Disable
1: Enable
Disabled remote wakeup by the host.
Enabled remote wakeup by the host.
Note1: Config, INTERFACE and ALTERNATE each support 3 kinds (0,1 and 2).
Note2: If each request is controlled by S/W, this register is not set.
92CZ26A-386
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3.16.3.10 Standard Request Register
This register shows the standard request that is executing now.
A bit which is set to “1” shows present executing request.
7
6
5
4
3
2
1
0
Standard Recuest
(07CAH)
bit Symbol S_INTERFACE G_INTERFACE S_CONFIG
G_CONFIG G_DESCRIPT S_FEATURE C_FEATURE
G_STATUS
Read/Write
After reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
S_INTERFACE
G_INTERFACE
S_CONFIG
(Bit 7) : SET_INTERFACE
(Bit 6) : GET_INTERFACE
(Bit 5) : SET_CONFIGRATION
(Bit 4) : GET_CONFIGRATION
(Bit 3) : GET_DESCRIPTOR
(Bit 2) : SET_FEATURE
G_CONFIG
G_DESCRIPT
S_FEATURE
C_FEATURE
G_STATUS
(Bit 1) : CLEAR_FEATURE
(Bit 0) : GET_STATUS
3.16.3.11 Request Register
This register shows the device request that is executing now.
A bit which is set to “1” shows present executing request.
7
6
5
4
3
2
CLASS
R
1
0
Request
(07CBH)
bit Symbol
Read/Write
After reset
SOFT_RESET G_PORT_STS G_DEVICE_ID
VENDOR
ExSTANDARD STANDARD
R
0
R
0
R
0
R
0
R
0
R
0
0
SOFT_RESET
G_PORT_STS
G_DEVICE_ID
VENDOR
(Bit 6) : SOFT_RESET
(Bit 5) : GET_PORT_STATUS
(Bit 4) : GET_DEVICE_ID
(Bit 3) : Vender class request
(Bit 2) : Class request
CLASS
ExSTANDARD
(Bit 1) : Not support auto Bus Enumeration
(SET_DESCRIPTOR, SYNCH_FRAME)
(Bit 0) : Standard request
STANDARD
92CZ26A-387
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3.16.3.12 DATASET Register
This register shows whether FIFO has data or not.
The application program can be checked it by accessing this register that whether
FIFO has data or not.
In the receiving status, when valid data transfer from USB host finished, bit which
correspond to applicable endpoint is set to “1” and generate interrupt. And, when
application read data of 1-packet, this bit is cleared to “0”. In the transmitting status,
when it terminated that 1-packet data transfer to FIFO, this bit is set to “1”. And when
valid data is transferred to USB host, this bit is cleared to “0” and generates interrupt.
7
6
5
4
3
2
1
0
DATASET1
(07CCH)
bit Symbol
Read/Write
After reset
EP3_DSET_B EP3_DSET_A EP2_DSET_B EP2_DSET_A EP1_DSET_B EP1_DSET_A
EP0_DSET_A
R
0
R
0
R
0
R
0
R
0
R
0
R
0
7
6
5
4
3
2
1
0
DATASET2
(07CDH)
bit Symbol
Read/Write
After reset
EP7_DSET_B EP7_DSET_A EP6_DSET_B EP6_DSET_A EP5_DSET_B EP5_DSET_A EP4_DSET_B EP4_DSET_A
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Note: DATASET1<EP3_DSET_B>, DATASET2 registers are not used at TMP92CZ26A.
•
Single packet mode
(DATASET1: Bit0, bit2, bit4 and bit6
DATASET2: Bit0, bit2, bit4 and bit6)
These bits show whether FIFO of applicable endpoint has data or not.
In endpoint of receiving mode, if bit 1 of applicable endpoint is “1”, data that
should be read exist to FIFO. Access EPx_SIZE register, and grasp size of data
that should be read, and read data of its size. When this bit is “0”, data that
should be read does not exist.
In endpoint of transmitting mode, if bit of applicable endpoint is “0”, CPU can
be transferred data under the payload. If its bit is “1”, because of FIFO have
transfer waiting data, transfer data to FIFO in UDC after applicable bit was
cleared to “0”. When short-packet is transferred, access EOP register after
writing transmission data to applicable endpoint.
•
Dual packet mode
(DATASET1: Bit3, bit5 and bit7 DATASET2: Bit1, bit3 bit5 and bit7)
These bits become effective in the dual packet mode. This mode has FIFO of
2-packets.
Each packet (called packet-A, packet-B) has DATASET-bit.
In isochroous transfer, it shows data transfer that can access in present frame
the packet. This is different from above one. In this case, the bit that whether A
or B is set to “1”, it is renewed according as shifting flame.
92CZ26A-388
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Note1: In the receiving mode, if bits that A-packet and B-packet of applicable endpoint are “1”, read data that
packet-number should be received, after checking DATASIZE<PACKET_ACTIVE>.
Note2: In the transmitting mode, if the both A and B bits are not “1”, it means that there are space in FIFO. So, write
data for payload or less to FIFO. If transmission become short-packet, write “0” to EOP<EPn_EOPB> after
writing data to the FIFO. The maximum size that can be written to A or B packet is same with maximum
payload size. If the both A and B bits are “0”, continuous writing of double maximum payload size are available.
Note3: In the dual packet transmitting mode, if both A and B packet are empty and EOP<EPn_EOPB> is written “0”,
the NULL-data is set to FIFO. In the single mode, the NULL-data is also set to FIFO if the above operation is
executed by A packet don’t have data state.
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3.16.3.13 EPx_STATUS Register (x: 0 to 7)
These registers are status registers for each endpoint. The <SUSPEND> is common
for all endpoint.
7
7
7
7
7
7
7
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
TOGGLE
SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
EP0_STATUS
(0790H)
R
0
R
0
R
1
R
1
R
1
R
0
R
0
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
TOGGLE
SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
EP1_STATUS
(0791H)
R
0
R
0
R
1
R
1
R
1
R
0
R
0
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
TOGGLE
SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
EP2_STATUS
(0792H)
R
0
R
0
R
1
R
1
R
1
R
0
R
0
6
5
4
3
2
1
0
EP3_STATUS
(0793H)
bit Symbol
Read/Write
After reset
TOGGLE
SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
R
0
R
0
R
1
R
1
R
1
R
0
R
0
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
TOGGLE
SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
EP4_STATUS
(0794H)
R
0
R
0
R
1
R
1
R
1
R
0
R
0
6
5
4
3
2
1
0
EP5_STATUS bit Symbol
TOGGLE
SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
(0795H)
Read/Write
R
0
R
0
R
1
R
1
R
1
R
0
R
0
After reset
6
5
4
3
2
1
0
bit Symbol
TOGGLE
SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
EP6_STATUS
(0796H)
Read/Write
After reset
R
0
R
0
R
1
R
1
R
1
R
0
R
0
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
TOGGLE
SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
EP7_STATUS
(0797H)
R
0
R
0
R
1
R
1
R
1
R
0
R
0
Note: EP4, 5, 6 and 7_STATUS registers are not used TMP92CZ26A.
TOGGLE Bit (Bit6)
This bit shows status of toggle sequence bit.
0: TOGGLE
1: TOGGLE
Bit0
Bit1
SUSPEND (Bit5)
This bit shows status of power management of UDC.
0: RESUME
In the SUSPEND status, some limitation about accessing to
UDC is needed.
1: SUSPEND
For the detail, refer 3.10.9.
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STATUS [2:0]
(Bit4 to bit2)
These bits show status of endpoint of UDC.
The status show whether transfer it or not, or show result of
transfer. . These are depending on transfer type.
(For the Isochronous transfer type, refer 3.10.6.)
000: READY
Receiving:
Device can be received.
In the endpoint 1 to 7, this register is initialized to “READY” by setting transfer type at
SET_CONFIGURATION.
In the endpoint 0, this register is initialized to “READY” by detecting USB reset from
the host.
This is initialized to “READY” by terminating the status stage without error.
Basically, this is same with “Receiving”.
Transmitting:
But in transmitting, when data for transmission is set to FIFO and answer to token
from host and transfer data to host collect and received ACK, status register is not
change, and it keeps “READY”. In this case, EPx_Empty_A or EPx_Empty_B
interrupt show terminates transfer correctly.
001: DATAIN
UDC set to DATAIN and generates EPx_FULL_A or EPx_FULL_B interrupt when
data is received from the host without error.
010: FULL
Refer 3.10.8 (2) Details for the STATUS register.
011: TX_ERR
After transfer data to IN token from host, UDC set TX-ER to status register when it is
not received “ACK” from host. In this case, an interrupt is not generated. The hosts
re-try and transfer IN token to this.
100: RX_ERR
101: BUSY
UDC set RX_ERR to status register without transmitting “ACK” to host when an error
(like a CRC-error) is detected in data of received token. In this case, an interrupt is
not generated. The hosts re-try and transfer IN token to this.
This status is used only for the control transfer type and it is set when a token of
status-stage is received from the host after terminated data-stage.
When status-stage can be finished, terminate correctly and returns to READY. This is
not used in the Bulk and interrupts transfer type.
110: STALL
This status shows that applicable endpoint is STALL status.
This status, return STALL-handshake except SETUP-token. In the control endpoint,
returns to READY from stall condition when SETUP-token is received.
In the other endpoint, returns to READY when initialization command of FIFO is
received.
(Note) In Automatically answer of Set_Interface request, request to interface 4 to 6
may not become to request error. If this is problem, in Set_Interface request answer,
set Standard Request Mode <S_INTERFACE> to “1” and use software.
111: INVALID
This status shows that applicable endpoint is UNCONFIGURED status.
In this status, the UDC has no reaction when token is received from the host.
By reset, all endpoint set to INVALID status. Only endpoint 0 returns to READY by
receiving USB-reset. Applicable endpoint returns to READY by configured.
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FIFO_DISABLE (Bit1)
This bit symbol shows FIFO status except EP0.
0: FIFO enabled
1: FIFO disabled
If the FIFO is set to disabled, the UDC transmits NAK
handshake forcibly for the all transfer. Disabled or enabled is set
by COMMAND register. This bit is cleared to “0” when transfer
type is changed.
STAGE_ERROR (Bit0)
This bit symbol shows that status stage is not terminated
correctly. ERROR is set when a status stage is not terminated
correctly and new SETUP token is received.
0: SUCCESS
1: ERROR
When this bit is “1”, this bit is cleared to “0” by read
EP0_STATUS register. This bit is not cleared even if normal
control transfer or other transfer is executed after. To clear, read
this bit. When software transaction is finished and UDC writes
EOP register, UDC shifts to status register and
waits
termination of status stage. In this case, if software is needed to
confirm that status stage is terminated correctly, when a new
request flag is received, it can be confirmed that whether last
request terminate correctly or not. And during request routine in
software, when new request flag is asserted, it can be confirmed
that whether last request is canceled or not halfway.
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3.16.3.14 EPx_SIZE Register (x: 0 to 7)
These registers have following function.
a) In the receiving, showing data number for 1 packet which was received correctly.
b) In the transmitting, it shows payload size. But it shows length value when short
packet is transferred.
This register is not needed to read when it is transmitting.
c) Showing dual packet mode and effective packet.
Each endpoint has H (High)-register that shows upper bit 9 to bit7 of data size and L
(Low) register which shows lower bit 6 to bit0 and control bit of FIFO.
And each H/L register has 2-set for dual-packet mode.
By reset, these are initialized to maximum payload size.
7
6
5
4
3
2
1
0
EP0_SIZE_L_A bit Symbol
PKT_ACTIVE DATASIZE6
DATASIZE5
DATASIZE4
DATASIZE3
DATASIZE2
DATASIZE1
DATASIZE0
(0798H)
Read/Write
R
1
R
0
R
0
R
0
R
1
R
0
R
0
R
0
After reset
7
6
5
4
3
2
1
0
EP1_SIZE_L_A
bit Symbol
PKT_ACTIVE DATASIZE6
DATASIZE5
DATASIZE4
DATASIZE3
DATASIZE2
DATASIZE1
DATASIZE0
(0799H)
Read/Write
R
1
R
0
R
0
R
0
R
1
R
0
R
0
R
0
After reset
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PKT_ACTIVE DATASIZE6
DATASIZE5
DATASIZE4
DATASIZE3
DATASIZE2
DATASIZE1
DATASIZE0
EP2_SIZE_L_A
(079AH)
R
1
R
0
R
0
R
0
R
1
R
0
R
0
R
0
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PKT_ACTIVE DATASIZE6
DATASIZE5
DATASIZE4
DATASIZE3
DATASIZE2
DATASIZE1
DATASIZE0
EP3_SIZE_L_A
(079BH)
R
1
R
0
R
0
R
0
R
1
R
0
R
0
R
0
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PKT_ACTIVE DATASIZE6
DATASIZE5
DATASIZE4
DATASIZE3
DATASIZE2
DATASIZE1
DATASIZE0
EP4_SIZE_L_A
(079CH)
R
1
R
0
R
0
R
0
R
1
R
0
R
0
R
0
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PKT_ACTIVE DATASIZE6
DATASIZE5
DATASIZE4
DATASIZE3
DATASIZE2
DATASIZE1
DATASIZE0
EP5_SIZE_L_A
(079DH)
R
1
R
0
R
0
R
0
R
1
R
0
R
0
R
0
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PKT_ACTIVE DATASIZE6
DATASIZE5
DATASIZE4
DATASIZE3
DATASIZE2
DATASIZE1
DATASIZE0
R
1
R
0
R
0
R
0
R
1
R
0
R
0
R
0
EP6_SIZE_L_A
(079EH)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PKT_ACTIVE DATASIZE6
DATASIZE5
DATASIZE4
DATASIZE3
DATASIZE2
DATASIZE1
DATASIZE0
R
1
R
0
R
0
R
0
R
1
R
0
R
0
R
0
EP7_SIZE_L_A
(079FH)
Note EP4,5,6,7_SIZE_L_A registers are not used at TMP92CZ26A.
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7
7
7
7
7
7
7
6
6
6
6
6
6
6
5
5
5
5
5
5
5
4
4
4
4
4
4
4
3
3
3
3
3
3
3
2
1
0
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
EP1_SIZE_L_B
(07A1H)
R
0
R
0
R
0
2
1
0
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
EP2_SIZE_L_B
(07A2H)
R
0
R
0
R
0
2
1
0
EP3_SIZE_L_B
(07A3H)
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
R
0
R
0
R
0
2
1
0
EP4_SIZE_L_B
(07A4H)
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
R
0
R
0
R
0
2
1
0
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
EP5_SIZE_L_B
(07A5H)
R
0
R
0
R
0
2
1
0
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
EP6_SIZE_L_B
(07A6H)
R
0
R
0
R
0
2
1
0
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
EP7_SIZE_L_B
(07A7H)
R
0
R
0
R
0
Note EP3,4,5,6,7_SIZE_L_B registers are not used at TMP92CZ26A.
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7
7
7
7
7
7
7
6
6
6
6
6
6
6
5
5
5
5
5
5
5
4
4
4
4
4
4
4
3
3
3
3
3
3
3
2
1
0
EP1_SIZE_H_A
(07A9H)
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
R
0
R
0
R
0
2
1
0
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
EP2_SIZE_H_A
(07AAH)
R
0
R
0
R
0
2
1
0
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
EP3_SIZE_H_A
(07ABH)
R
0
R
0
R
0
2
1
0
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
EP4_SIZE_H_A
(07ACH)
R
0
R
0
R
0
2
1
0
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
R
0
R
0
R
0
EP5_SIZE_H_A
(07ADH)
2
1
0
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
R
0
R
0
R
0
EP6_SIZE_H_A
(07AEH)
2
1
0
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
R
0
R
0
R
0
EP7_SIZE_H_A
(07AFH)
Note EP4,5,6,7_SIZE_H_A registers are not used at TMP92CZ26A.
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EP1_SIZE_H_B
(07B1H)
7
7
7
7
7
7
7
6
6
6
6
6
6
6
5
5
5
5
5
5
5
4
4
4
4
4
4
4
3
3
3
3
3
3
3
2
1
0
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
R
0
R
0
R
0
2
1
0
EP2_SIZE_H_B
(07B2H)
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
R
0
R
0
R
0
2
1
0
EP3_SIZE_H_B
(07B3H)
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
R
0
R
0
R
0
2
1
0
EP4_SIZE_H_B
(07B4H)
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
R
0
R
0
R
0
2
1
0
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
EP5_SIZE_H_B
(07B5H)
R
0
R
0
R
0
2
1
0
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
EP6_SIZE_H_B
(07B6H)
R
0
R
0
R
0
2
1
0
EP7_SIZE_H_B
(07B7H)
bit Symbol
Read/Write
After reset
DATASIZE9
DATASIZE8
DATASIZE7
R
0
R
0
R
0
Note EP3,4,5,6,7_SIZE_H_B registers are not used at TMP92CZ26A.
DATASIZE[9:7] (H register: Bit2 to bit0)
DATASIZE[6:0] (L register: Bit6 to bit0)
In receiving, data number that 1 packet received
from the host is shown. This is renewed when a data
from the host is received with no error.
PKT_ACTIVE (L register: Bit7)
When dual-packet mode is selected, this bit show
packet that can be accessed. In this case, the UDC
accesses packets that divide FIFO (Packet A and
Packet B) mutually. When FIFO in UDC is accessed by
CPU, refer to this bit. If receiving endpoint, start
reading from packet that this bit is “1”. In single-packet
mode, this bit is no meaning because of the packet-A is
always used.
1: OUT_ENABLE
0: OUT_DISABLE
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3.16.3.15 FRAME Register
This register shows frame number which is issued with SOF token from the host
and is used for Isochronous transfer type.
Each HIGH and LOW registers show upper and lower bits.
7
−
6
T[6]
R
5
T[5]
R
4
T[4]
R
3
T[3]
R
2
T[2]
R
1
T[1]
R
0
T[0]
R
FRAME_L
(07E1H)
bit Symbol
Read/Write
After reset
R
0
0
0
0
0
0
0
0
7
T[10]
R
6
T[9]
R
5
T[8]
R
4
T[7]
R
3
2
1
0
bit Symbol
Read/Write
After reset
CREATE
FRAME_STS1 FRAME_STS0
FRAME_H
(07E2H)
R
0
R
1
R
0
0
0
0
0
T[10:7] (H register: Bit7 to bit4)
T[6:0] (L register: Bit6 to bit0)
These bits are renewed when SOF-token is received.
And it shows frame-number.
CREATE (H register: Bit2)
These bits show enable function that generate SOF
SOF automatically from UDC. This is used for the case of
receiving error of SOF token.
0: DISABLE
1: ENABLE
This function is set by accessing COMMAND register.
By reset, this bit is initialized to “0”.
FRAME STS[1:0]
(H register: Bit1 and bit0)
These bits show the status whether a frame number
that is shown FRAME register is correct or not. At the
LOST status, a correct frame number is undefined.
0: BEFORE
1: VALID
2: LOST
If this register is “VALID”, number that is shown to
FRAME register is correct.
If this register is “BEFORE”, when SOF auto
generation, BEFORE condition shows it from USB host
controller inside that from SOF generation time to receive
SOF token. Correct value as frame-number is value that is
selected from FRAME register value.
3.16.3.16 ADDRESS Register
This register shows device address which is specified by the host in bus
enumeration.
By reading this register, a present address can be confirmed.
7
6
A6
R
5
A5
R
4
A4
R
3
A3
R
2
A2
R
1
A1
R
0
A0
R
bit Symbol
Read/Write
After reset
ADDRESS
(07E3H)
0
0
0
0
0
0
0
ADDRESS [6:0] (Bit6 to bit0)
The UDC compares this register and address in all packet
ID, and UDC judges whether it is an effective transaction or
not.
This is initialized to “00H” by USB reset.
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3.16.3.17 EOP Register
This register is used when a dataphase of control transfer type terminate or when a
short packet is transmitting of bulk-IN, interrupt-IN.
7
6
5
4
3
2
1
0
EOP
(07CFH)
bit Symbol
Read/Write
After reset
EP7_EOPB
EP6_EOPB
EP5_EOPB
EP4_EOPB
EP3_EOPB
EP2_EOPB
EP1_EOPB
EP0_EOPB
W
1
W
1
W
1
W
1
W
1
W
1
W
1
W
1
Note: EOP<EP7_EOPB, EP6_EOPB, EP5_EOPB, EP4_EOPB> registers are not used at TMP92CZ26A.
In a dataphase of control transfer type, write “0” to <EP0_EOPB> when all
transmission data is written to the FIFO, or read all receiving data from the FIFO.
UDC is terminated status stage by this signal.
When short packet is transmitted by using bulk-IN or interrupt-IN endpoint, use
this for terminate writing transmission data. In this case, write “0” to <EP0_EOPB> of
writing endpoint. Write “1” to another bit.
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3.16.3.18 Port Status Register
This register is used when a request of printer class is received.
In case of request of GET_PORT_STATUS, the UDC operates automatically by
using this data.
7
6
5
4
Select
W
3
NotError
W
2
1
0
bit Symbol
Read/Write
After reset
Reserved7
Reserved6
PaperError
Reserved2
Reserved1
Reserved0
Port Status
(07E0H)
W
0
W
0
W
0
W
0
W
0
W
0
1
1
Note: TMP92CZ26A don’t use this register because of not support to printer-class.
The data should be written before receiving request.
Write “0” to <Reserved> bit of this register. This register is initialized to “18H” by
reset.
3.16.3.19 Standard Request Mode Register
This register set answer for Standard Request either answer automatically in
Hardware or control in software. Each bit mean kind of request.
When this register is set applicable bit to “0”, answer is executed automatically by
hardware. When this register is set applicable bit to “1”, answer is controlled by
software. If request is received during hardware control, interrupt signal (INT_SETUP,
INT_EP0, INT_STAS, INT_STAN) is set to disable. If request is received during
software control, interrupt signal is asserted, and it is controlled by software.
7
S_Interface
R/W
6
G_Interface
R/W
5
S_Config
R/W
0
4
G_Config
R/W
0
3
G_Descript
R/W
2
S_Feature
R/W
1
C_Feature
R/W
0
G_Status
R/W
0
bit Symbol
Read/Write
After reset
Standard Request Mode
(07D8H)
0
0
0
0
0
S_Intetface
G_Interface
S_Config
(Bit 7) : SET_INTERFACE
(Bit 6) : GET_INTERFACE
(Bit 5) : SET_CONFIGRATION
(Bit 4) : GET_CONFIGRATION
(Bit 3) : GET_DESCRIPTOR
(Bit 2) : SET_FEATURE
G_Config
G_Descript
S_Feature
C_Feature
G_Status
(Bit 1) : CLEAR_FEATURE
(Bit 0) : GET_STATUS
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3.16.3.20 Request Mode Register
This register set answer for Class Request either answer automatically in Hardware
or control in software. Each bit mean kind of request.
When this register is set applicable bit to “0”, answer is executed automatically by
hardware. When this register is set applicable bit to “1”, answer is controlled by
software. If request is received during hardware control, interrupt signal (INT_SETUP,
INT_EP0, INT_STAS, INT_STATUSN) is set to disable. If request is received during
software control, interrupt signal is asserted, and it is controlled by software.
7
6
Soft_Reset
R/W
5
G_Port_Sts
R/W
4
G_DeviceId
R/W
3
2
1
0
bit Symbol
Read/Write
After reset
Request Mode
(07D9H)
0
0
0
Note: TMP92CZ26A don’t use this register because of printer-class is not support automatic answer.
-
(Bit 7)
(Bit 6)
(Bit 5)
(Bit 4)
: Reserved
Soft_Reset
G_Port_Sts
G_Config
G_Descript
: SOFT_RESET
: GET_PORT_STATUS
: GET_DEVICE_ID
(Bit 3 to 0) : Reserved
Note1: SET_ADDRESS request is supported by only auto-answer .
Note2: SET_DESCRIPTOR and SYNCH_FRAME are controlled by only software .
Note3: Vendor Request and Class Request (Printer Class and so on) are controlled by only software.
Note4: INT_SETUP, EP0, STAS and STASN interrupts assert only when it is software-control.
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3.16.3.21 COMMAND Register
This register sets COMMAND at each endpoint. This register can be set selection of
endpoint in bit6 to bit4 and kind of COMMAND in bit3 to bit0.
COMMAND for endpoint that is supported is ignored.
7
6
EP[2]
W
5
EP[1]
W
4
EP[0]
W
3
2
1
0
COMMAND
(07D0H)
bit Symbol
Read/Write
After reset
Command[3] Command[2] Command[1]
Command[0]
W
0
W
0
W
0
W
0
0
0
0
Note: When writing to this register, the recovery time of 2clock at 12MHz is needed. If writing continuously, insert
dummy instruction more than 250 ns.
EP [2:0] (Bit6 to bit4)
000: Select endpoint 0
001: Select endpoint 1
010: Select endpoint 2
011: Select endpoint 3
COMMAND [3:0] (Bit3 to bit0)
0000: Reserved
0001: Reserved
0010: SET_DATA0
This COMMAND clear toggle sequence bit of applicable endpoint (EP0 to EP3).
If this COMMAND is inputted, it set toggle sequence bit of applicable endpoint to “0”
compulsively. Data toggle for transfer is renewed automatically by UDC. However, if
setting toggle sequence bit of endpoint to “0” compulsively, this COMMAND execution
need. If control transfer type and Isochronous transfer type, execution this COMMND
don’t need because of controlling in hardware.
0011: RESET
This COMMAND reset applicable endpoint (EP0 to EP3).
If this COMMAND is inputted, applicable endpoint is initialized. CLEAR_FEATURE
request stall endpoint. When this stall is cleared, execute this COMMAND. (This
command doesn’t affect to transfer mode.)
This command Initialize following item.
・Clear toggle sequence bit of applicable endpoint.
・Clear STALL of applicable endpoint.
・Set to FIFO_ENABLE condition.
0100: STALL
This COMMAND set applicable endpoint to STALL (EP0 to EP3).
If STALL handshake must be return as answer for device request, execute this
command.
0101: INVALID
This COMMAND set condition to prohibition using applicable endpoint (EP1 to EP3).
If UDC detect USB_RESET signal from USB host, it set all endpoint (except endpoint 0)
to prohibition using it automatically. If Config and Interface are changed by device
request, set endpoint that is not used to prohibit using.
0110: CREATE_SOF
0111: FIFO_DISABLE
This COMMAND set quasi-SOF generation function to enable (EP0).
Default is set to disable, it need using for Isochronous transfer.
This COMMAND set FIFO of applicable endpoint to disable (EP1 to EP3).
If this command is set from external, all of transfer for applicable endpoint returns NAK.
When it is set from external if during receiving packet, this becomes valid from next
token. This command doesn’t affect packet that is transferring.
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1000: FIFO_ENABLE
This COMMAND set FIFO of applicable endpoint to enable (EP1 to EP3).
If FIFO is set to disable by FIFO_DISABLE COMMAND, this command is used for
release disable condition. If during receiving packet, this becomes valid from next token.
If USB_RESET is detected from host and RESET COMMAND execute and transfer
mode is set by using SET_CONFIG and SET_INTERFACE request, applicable
endpoint become FIFO_ENABLE condition.
1001: INIT_DESCRIPTOR This COMMAND is used if descriptor RAM is rewritten during operates system (EP0).
If UDC detect USB_RESET from host controller, it read content of descriptor RAM
automatically, and it set various setting.
If descriptor RAM is changed during operates system, it must read setting again.
Therefore, execute this command. Case of connects to USB host, this function start
reading automatically. Therefore, don’t have to execute this command.
1010: FIFO_CLEA
This COMMAND initializes FIFO of applicable endpoint (EP1 to EP3).
However, EPx_STATUS<TOGGLE> is not initialized.
If resetting by software, execute this COMMAND.
This command Initialize following item.
・Clear STALL of applicable endpoint.
・Set to FIFO_ENABLE condition.
1011: STAL_CLEAR
This COMMAND clear STALL of applicable endpoint (EP1 to EP3).
If clearing only STALL of endpoint, execute this COMMAND.
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3.16.3.22 INT_Control Register
INT_STASN interrupt is disabled and enabled by value that is written to this
register.
This is initialized to disable by external reset. When setup packet is received, it
becomes to disable.
7
6
5
4
3
2
1
0
Status_nak
R/W
INT_Control
(07D6H)
bit Symbol
Read/Write
After reset
0
In control read transfer, if host terminate dataphase in small data length (smaller
than data length that is specified to wLength by host), device side and stage
management cannot be synchronized. Therefore, INT_STASN interrupt inform that
shift to status stage.
If this interrupt don’t need, it can set to disable because of this interrupt is asserted
every status stage.
STATUS_NAK (Bit0)
0: INT_STATSN interrupt disable
1: INT_STATSN interrupt enable
3.16.3.23 USB STATE Register
This register shows device state of present for connection with USB host.
7
6
5
4
3
2
Configured
R/W
1
0
Default
R
USB STATE
(07CEH)
bit Symbol
Read/Write
After reset
Addressed
R
0
0
1
Inside UDC, answer for each Device Request is managed by referring this bits
(Configured, Addressed and Default). If transaction for SET_CONFIG request is
executed by using software, write present state to this register. If host appointconfig0,
this becomes Unconfigured. And returning to Addressed state is needed. Therefore, if
host appoint config0, write bit2 to “0”.
When Configured bit (Bit2) is written “0”, Addressed bit (bit 1) is set automatically
by hardware. When host appoint config value that supported by device, device must
execute mode setting of each endpoint by using value that is appointed by
endpoint-descriptor in the config-descriptor. After finish mode setting, set Configured
bit (Bit2) to “1” before access EOP register. When this bit is set to “1”, Addressed bit
(Bit1) is set to “0” automatically.
Bit2 to bit0
000: Default
010: Addressed
100: Configured
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3.16.3.24 EPx_MODE Register (x: 1 to 3)
This register sets transfer mode of endpoint (EP1 to EP3).
If transaction of SET_CONFIG and SET_INTERFACE are set to software control,
this control must use appointed config or interface. When it is setting mode, access
this register.
7
7
7
6
6
6
5
Payload[2]
R/W
4
3
2
Mode[1]
R/W
0
1
Mode[0]
R/W
0
0
Direction
R/W
bit Symbol
Read/Write
After reset
Payload[1] Payload[0]
EP1_MODE
(0789H)
R/W
0
R/W
0
0
0
5
Payload[2]
R/W
4
3
2
Mode[1]
R/W
0
1
Mode[0]
R/W
0
0
Direction
R/W
bit Symbol
Read/Write
After reset
Payload[1] Payload[0]
EP2_MODE
(078AH)
R/W
0
R/W
0
0
0
5
Payload[2]
R/W
4
3
2
Mode[1]
R/W
0
1
Mode[0]
R/W
0
0
Direction
R/W
bit Symbol
Read/Write
After reset
Payload[1] Payload[0]
EP3_MODE
(078BH)
R/W
0
R/W
0
0
0
There is limitation to timing that can be written.
If transaction for SET_CONFIG and SET_INTERFACE are set to software control,
after received INT_SETUP interrupt, finish writing before access EOP register. This
register prohibits writing when it is other timing, and it is ignored.
DIRECTION (Bit0)
0: OUT
1: IN
Direction of from host to device
Direction of from device to host
MODE [1:0] (Bit2 and bit1)
00: Control transfer type
01: Isochronous transfer type
10: Bulk transfer type or interrupt transfer type
11: Interrupt (No toggle)
Note: If setting endpoint that is set to Isochronous transfer mode to “no use”, after changed to
Isochronous mode, set to “no use” by COMMAND register.
PAYLOAD [2:0] (Bit3, bit4 and bit5)
000:
8 bytes
001: 16 bytes
010: 32 bytes
011: 64 bytes
0100:128 bytes
0101:256 bytes
0110:512 bytes
0111:1023 bytes (Note1, 2)
Note1: Max packet size of Isochronous transfer type is 1023 bytes.
Note2: If except 8, 16, ..., 1023 was set to wMaxPacketSize of descriptor, Payload
more than descriptor value is set by auto-answer of Set_Configration and
Set_Interface.
Others (Bit6 and bit7) Reserved
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3.16.3.25 EPx_SINGLE Register
This register sets mode of FIFO in each endpoint (SINGLE/DUAL).
7
6
5
4
3
2
1
0
EPx_SINGLE1
(07D1H)
bit Symbol
Read/Write
After reset
EP3_SELECT EP2_SELECT EP1_SELECT
EP3_SINGLE EP2_SINGLE EP1_SINGLE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Note: Endpoint 3 support only SINGLE mode at TMP92CZ26A.
Bit number
0: No use
1: EP1_SINGLE
2: EP2_SINGLE
3: EP3_SINGLE
4: No use
5: EP1_SELECT
6: EP2_SELECT
7: EP3_SELECT
When EPx_SELECT bit is “1”, EPx_SINGLE bit become valid in following content.
0: DUAL mode 1: SINGLE mode
If set ting content of EPx_SINGLE bit to valid, set EPx_SELECT bit to “1”.
0: Invalid
1: Valid
3.16.3.26 EPx_BCS Register
This register set mode that access to FIFO in each endpoint.
7
6
5
4
3
EP3_BCS
R/W
2
EP2_BCS
R/W
1
EP1_BCS
R/W
0
EPx_BCS1
(07D3H)
bit Symbol
Read/Write
After reset
EP3_SELECT EP2_SELECT EP1_SELECT
R/W
0
R/W
0
R/W
0
0
0
0
Bit number
0: No use
1: EP1_BCS
2: EP2_BCS
3: EP3_BCS
4: No use
5: EP1_SELECT
6: EP2_SELECT
7: EP3_SELECT
Always write “1” to EPx_BCS bit.
0: Reserved
1: CPU access
If setting content of EPx_BCS bit to valid, set EPx_SELECT bit to “1”.
0: Invalid
1: Valid
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3.16.3.27 USBREADY Register
This register informs finishing writing data to descriptor RAM on UDC.
After assigned data to descriptor RAM, write “0” to bit0.
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
USBREADY
USBREADY
(07E6H)
R/W
0
USBREADY (Bit0)
0: Writing to descriptor RAM was finished.
1: Writing to descriptor RAM is enable.
(However, when during connecting to host, writing to descriptor RAM is prohibited.)
USB host
TMP92CZ26A
VCC
VSS
GND
CPU
UDC
PortXX
R1 = 1.5 kΩ
D+
15 kΩ
R2
R3
D−
15 kΩ
VDD
INTXX
PortXX
(Pull-up on/off)
Write signal
Descriptor RAM access
Device ID RAM
Register in USB
USBREADY registera access
Detect level of VDD signal from USB cable, and execute initialize sequence. In this
case, UDC disable detecting USB_RESET signal until USBREADY register is written
“0” after released USB_RESET.
If pull-up resister on D+ signal is controlled by using control signal, when pull-up
resister is connected to host in OFF condition, this condition is equivalent condition
with USB_RESET signal by pull-down resister in host side. Therefore UDC isn’t
detected in USB_RESET until write “0” to USBREADY register
Note1: Pull-up resister and control switch are needed at external of TMP92CZ26A.
Note2: Above setting is example when communication. It is needed special circuit for prevent flow current at
connector connect detection , no-use, no connection.
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3.16.3.28 Set Descriptor STALL Register
This register sets whether returns STALL automatically in data stage or status
stage for Set Descriptor Request.
7
6
5
4
3
2
1
0
Set Descriptor STALL
(07E8H)
bit Symbol
Read/Write
After reset
S_D_STALL
W
0
Bit0: S_D_STALL
0: Software control (Default)
1: Automatically STALL
3.16.3.29 Descriptor RAM Register
This register is used for store descriptor to RAM. Size of descriptor is 384 bytes.
However, when storing descriptor, write according to descriptor RAM structure
sample.
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
Descriptor RAM
(0500H)
bit Symbol
Read/Write
After reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(067FH)
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
This register can Read/Write only following timing; before detect USB_RESET,
during processing SET_DESCRIPTOR request.
SET_DESCRIPTOR request processes from INT_SETUP assert until access EOP
register.
If there is rewriting request of descriptor in SET_DESCRIPTOR, process request
following sequence.
1) Read descriptor that is transferred by SET_DESCRIPTOR requests every packet.
2) When reading descriptor number of last packet finished, write all descriptors to
RAM for descriptor.
3) When writing finished, execute INIT_DESCRIPTOR of COMMAND register.
4) When all process finished, access EOP register, and finish status stage.
5) When INT_STAS is received, it shows normal finish of status stage.
If USB_RESET is detected, it starts reading automatically. Therefore, when it
connect to host, executing of INIT_DESCRIPTOR command is not needed.
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3.16.4 Descriptor RAM
This area stores descriptor that is defined in USB. Device, Config, Interface, Endpoint
and String descriptor must set to RAM by using following format.
Device descriptor
18 bytes
Config 1 descriptor
(Interfaces, endpoints)
Under 255 bytes
Config 2 descriptor
(Interfaces, ENDPOINT)
Under 255 bytes
String0 length
String1 length
String2 length
String3 length
1 byte
1 byte
1 byte
1 byte
String0 descriptor
String1 descriptor
String2 descriptor
String3 descriptor
Under 63 bytes
Under 63 bytes
Under 63 bytes
Under 63 bytes
Note 1: If String Descriptor is supported, set StringxLength area to size0. No support String Dedcriptor
is returned STALL.
Note 2: Config Descriptior refers to descriptor sample.
Note 3: Sequencer in UDC decides Config number, Interface number and Endpoint number. Therefore,
if supporting Endpoint number is small, assign address according as priority.
Note 4: This function become effective only case of store descriptor as RAM.
Note 5: RAM size is total 384 bytes.
Note 6: Possible timing in RD/WR of descriptor RAM is only before detect USB_RESET and processing
SET_DESCRIPTOR request. (Prohibit access except this timing.)
Writing must finish before connect to USB host and processing SET_DESCRIPTOR request.
SET_DESCRIPTOR request processes from INT_SETUP assert until access EOP register.
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Descriptor RAM setting example:
Data Description
Address
Description
Device Descriptor
12H
500H
501H
502H
503H
504H
505H
506H
507H
508H
509H
50AH
50BH
50CH
50DH
50EH
50FH
510H
511H
bLength
01H
00H
01H
00H
00H
00H
08H
6CH
04H
01H
10H
00H
01H
00H
00H
00H
01H
bDescriptorType
bcdUSB (L)
Device Descriptor
USB Spec 1.00
bcdUSB (H)
IFC’s specify own
bDeviceClass
bDeviceSubClass
bDeviceProtocol
bMaxPacketSize0
bVendor (L)
Toshiba
bVendor (H)
IdProduct (L)
IdProduct (H)
bcdDevice (L)
bcdDevice (H)
bManufacture
IProduct
Release 1.00
bSerialNumber
bNumConfiguration
Config1 Descriptor
512H
513H
514H
515H
516H
517H
518H
519H
51AH
09H
02H
4EH
00H
01H
01H
00H
A0H
31H
BLength
bDescriptorType
wtotalLength (L)
wtotalLength (H)
bNumInterfaces
bConfigurationValue
iConfiguration
bmAttributes
Config Descriptor
78 bytes
Bus powered-remote wakeup
98 mA
MaxPower
Interface0 Descriptor AlternateSetting0
51BH
51CH
51DH
51EH
51FH
520H
521H
522H
523H
09H
04H
00H
00H
01H
07H
01H
01H
00H
bLength
bDescriptorType
bInterfaceNumber
bAlternateSetting
bNumEndpoint
bInterfaceClass
bInterfaceSubClass
bInterfaceProtocol
iInterface
Interface Descriptor
AlternateSetting0
Endpoint1 Descriptor
524H
525H
526H
527H
528H
529H
52AH
07H
05H
01H
02H
40H
00H
00H
bLength
bDescriptorType
bEndpointAddress
bmAttributes
Endpoint Descriptor
OUT
BULK
wMaxPacketSize (L)
wMaxPacketSize (H)
bInterval
64 bytes
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Address Data
Description
Description
Interface0 Descriptor AlternateSetting1
52BH
52CH
52DH
52EH
52FH
530H
531H
532H
533H
09H
04H
00H
01H
02H
07H
01H
02H
00H
bLength
bDescriptorType
bInterfaceNumber
bAlternateSetting
bNumEndpoints
bInterfaceClass
bInterfaceSubClass
bInterfaceProtocol
iInterface
Interface Descriptor
AlternateSetting1
Endoint1 Descriptor
534H
535H
536H
537H
538H
539H
53AH
07H
05H
01H
02H
40H
00H
00H
bLength
bDescriptorType
bEndpointAddress
bmAttributes
Endpoint Descriptor
OUT
BULK
wMaxPacketSize (L)
wMaxPacketSize (H)
bInterval
64 bytes
Endpoint2 Descriptor
53BH
53CH
53DH
53EH
53FH
540H
541H
07H
05H
82H
02H
40H
00H
00H
bLength
bDescriptorType
bEndpointAddress
bmAttributes
Endpoint Descriptor
IN
BULK
64 bytes
wMaxPacketSize (L)
wMaxPacketSize (H)
bInterval
Interface0 Descriptor AlternateSetting2
542H
543H
544H
545H
546H
547H
548H
549H
54AH
09H
04H
00H
02H
03H
FFH
00H
FFH
00H
bLength
bDescriptorType
bInterfaceNumber
bAlternateSetting
bNumEndpoints
bInterfaceClass
bInterfaceSubClass
bInterfaceProtocol
iInterface
Interface Descriptor
AlternateSetting2
Endpoint1 Descriptor
54BH
54CH
54DH
54EH
54FH
550H
551H
07H
05H
01H
02H
40H
00H
00H
bLength
bDescriptorType
bEndpointAddress
bmAttributes
Endpoint Descriptor
OUT
BULK
wMaxPacketSize (L)
wMaxPacketSize (H)
bInterval
64 bytes
Endpoint2 Descriptor
552H
553H
554H
555H
556H
557H
558H
07H
05H
82H
02H
40H
00H
00H
bLength
bDescriptorType
bEndpointAddress
bmAttributes
Endpoint Descriptor
IN
BULK
64 bytes
wMaxPacketSize (L)
wMaxPacketSize (H)
bInterval
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Address DATA
Description
Description
Endpoint3 Descriptor
559H
55AH
55BH
55CH
55DH
55EH
55FH
07H
05H
83H
03H
08H
00H
01H
bLength
bDescriptorType
bEndpointAddress
bmAttributes
Endpoint Descriptor
IN
Interrupt
8 bytes
wMaxPacketSize (L)
wMaxPacketSize (H)
bInterval
1 ms
String Descriptor Length Setup Area
560H
561H
562H
563H
04H
10H
00H
00H
bLength
bLength
bLength
bLength
Length of String Descriptor0
Length of String Descriptor1
Length of String Descriptor2
Length of String Descriptor3
String Descriptor0
564H
565H
566H
567H
04H
bLength
03H
09H
04H
bDescriptorType
bString
String Descriptor
Language ID 0x0409
bString
String Descriptor1
10H
568H
569H
56AH
56BH
56CH
56DH
56EH
56FH
570H
571H
572H
573H
574H
575H
576H
577H
bLength
bDescriptorType
bString
bString
bString
bString
bString
bString
bString
bString
bString
bString
bString
bString
bString
bString
03H
00H
54H
00H
6FH
00H
73H
00H
68H
00H
69H
00H
62H
00H
61H
String Descriptor
(Toshiba)
T
o
s
h
i
b
a
String Descriptor2
String Descriptor3
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3.16.5 Device Request
3.16.5.1 Standard request
UDC support automatically answer in standard request.
(1) GET_STATUS Request
This request returns status that is appointed of receive side, automatically.
bmRequestType
bRequest
wValue
0
wIndex
wLength
2
Data
10000000B
10000001B
10000010B
GET_STATUS
0
Device, interface or
endpoint status
Interface
endpoint
Request to device returns following information according to priority of little
endian.
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
Remote
wakeup
Self
power
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
• Remote wakeup
It returns present remote wakeup setting.
This bit is set or reset by SET_FEATURE or
CLEAR_FEATURE request. Default is value that is set to
bmAttributes field in Config descriptor.
It returns present power supply setting. This bit return Self
or Bus Power according to value that is set to bmAttributes
field in Config descriptor.
• Self power
Request to interface returns 00H of number of 2 bytes.
Request to endpoint returns in according to priority of little endian following
information.
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
HALT
D8
0
D15
0
D14
0
D13
0
D12
0
D11
0
D10
0
D9
0
It return halts status of endpoint that is selected.
• HALT
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(2) CLEAR_FEATURE request
This request clears or disables particular function.
bmRequestType
bRequest
wValue
wIndex
wLength
0
Data
None
00000000B
00000001B
00000010B
CLEAR_
FEATURE
Feature
selector
0
Interface
endpoint
• Reception side device
Feature selector: 1
Present remote wakeup setting is disabled.
STALL state
Feature selector: except 1
• Reception side interface
STALL state
• Reception side end point
Feature selector: 0
Halt of applicable endpoint is cleared.
STALL state
Feature selector: except 0
Note: If it request to endpoint that is not exist, it stall.
(3) SET_FEATURE request
This request set or enables particular function.
bmRequestType
bRequest
wValue
wIndex
wLength
0
Data
None
00000000B
00000001B
00000010B
SET_
FEATURE
Feature
selector
0
Interface
endpoint
• Reception side device
Feature selector: 1
Present remote wakeup setting is disabled.
STALL state
Feature selector: except 1
• Reception side interface
STALL state
• Reception side end point
Feature selector: 0
Halt of applicable endpoint
STALL state
Feature selector: except 0
Note: If it request to endpoint that is not exist, it stall.
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(4) SET_ADDRESS request
This request set device address. Following request answer by using this device
address.
Answer of request is used present device address until status stage of this
request finish normally.
bmRequestType
00000000B
bRequest
wValue
wIndex
0
wLength
0
Data
None
SET_ADDRESS Device Address
(5) GET_DESCRIPTOR request
This request returns appointed descriptor.
bmRequestType
10000000B
bRequest
wValue
wIndex
wLength
Data
GET_
DESCRIPTOR
Descriptor type
and Descriptor
index
0
or
Descriptor
length
Descriptor
Language ID
• Device
Device transmits device descriptor that is stored to descriptor RAM.
• Config
Config transmits config descriptor that is stored to descriptor RAM.
At this point, it transmits not only config descriptor but also
interface and endpoint descriptor.
• String
String transmits string descriptor of index that is appointed lower
byte of wValue field.
Note: Decriptor of short data length in wLength and descriptor length is transmitted by automatically answer of
Get_Descriptor.
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(6) SET_DESCRIPTOR request
This request sets or enables particular function.
bmRequestType
00000000B
bRequest
wValue
wIndex
wLength
Data
SET_
Descriptor type
and
0
or
Descriptor
length
Descriptor
Descriptor
Descriptor index
Language ID
Automatically answer of this request does not support.
According to INT_SETUP interrupt, if receiving request was discerned as
SET_DESCRIPTOR request, take back data after it confirmed EP0_DSET_A bit
of DATASET register is “1”. When finishing, access EOP register, and write “0” to
EP0_EOPB bit. Therefore, status stage finish. Transaction is same with vendor
request.
Pleas refer to vendor request section.
(7) GET_CONFIGURATION request
This request returns configuration value of present device.
bmRequestType
10000000B
bRequest
wValue
0
wIndex
0
wLength
1
Data
GET_
CONFIG
Configuration
value
If it is not configured, it returns “0”. If configuration, it returns configuration
value.
(8) SET_CONFIGURATION request
This request sets device configuration.
bmRequestType
00000000B
bRequest
wValue
wIndex
0
wLength
0
Data
None
SET_
CONFIG
Configuration
value
It configured in value that is appointed by using lower byte of wValue field.
When this value is “0”, it is not configured.
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(9) GET_INTERFACE request
This request returns AlternateSetting value that is set by appointed interface.
bmRequestType
10000001B
bRequest
wValue
0
wIndex
Interface
wLength
1
Data
GET_
INTERFACE
Alternate
setting
If there is not appointed interface, it become to STALL state.
(10) SET_INTERFACE request
This request selects AlternateSetting in appointed interface.
bmRequestType
00000001B
bRequest
wValue
wIndex
Interface
wLength
0
Data
None
SET_
INTERFACE
Alternate
setting
If there is not appointed interface, it become STALL state.
(11) SYNCH_FRAME request
This request transmits synchronous frame of endpoint.
bmRequestType
10000010B
bRequest
wValue
0
wIndex
wLength
2
Data
SYNCH_FRAME
Endpoint
Frame No.
Automatically answer of this request does not support.
According to INT_SETUP interrupt, if receiving request was discerned as
SYNCH_FRAME request, write data of 2byte in Frame No after it confirmed
EP0_DSET_A bit of DATASET register is “0”. When finishing, access EOP register,
and write “0” to EP0_EOPB bit. Therefore, status stage finish. It can be used only
in case of endpoint support isochronous transfer type and support this request.
Transaction is same with vendor request.
Pleas refer to vendor request section.
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3.16.5.2 Printer Class Request
UDC does not support “Automatic answer” of printer class request.
Transaction for Class request is the same as vendor request; answering to
INT_SETUP interrupt.
3.16.5.3 Vendor request (Class request)
UDC doesn’t support “Automatic answer” of Vendor request.
According to INT_SETUP interrupt, access register that device request is stored,
and discern receiving request. If this request is vendor request, control UDC from
external, and execute transaction for Vendor request.
Below is explanation for case of data phase is transmitting (Control read), and
case of data phase is receiving (Control write).
(a) Control Read request
bmRequestType
110000xxB
bRequest
wValue
wIndex
wLength
Data
Vender peculiar
Vender peculiar
Vender peculiar
Vender peculiar
(Expire 0)
Vendor data
When INT_SETUP is received, judge contents of receiving request by
bmRequestType, bRequest, wValue, wIndex and wLength registers. And execute
transaction for each request. As application, access Setup_Received register after
request was judged. And it must inform that INT_SETUP interrupt was
recognized to UDC.
After transmitting data prepared in application, access DATASET register, and
confirm EP0_DSET_A bit is “0”. After confirming, write data FIFO of endpoint 0.
If transmitting data more than payload, write data after it confirmed whether a
bit of EP0_DSET_A in DATASET register is “0”. (INT_ENDPOINT0 interrupt is
can be used.) If writing all data finished, write “0” to EP0 bit of EOP register.
When UDC receive it, status stage finish automatically.
And when UDC finish status stage normally, INT_STATUS interrupt is
asserted. If finishing status stage normally is recognized to external application,
manage this stage by using this interrupt signal. If status stage cannot be
finished normally and during status stage, maybe new SETUP token is received.
In this case, when INT_SETUP interrupt signal is asserted, “1” is set to
STAGE_ERROR bit of EP0_STATUS register. And it informs it to external that
status stage cannot be finished normally.
And maybe dataphase finish in data number that is short than value showed
to wLength by protocol of control read transfer type in USB. If application
program is configured by using only wLength value, transaction for it cannot be
when host shift to status stage without arriving at expecting data number. At this
point, shifting to status stage can be confirmed by using INT_STATUSNAK
interrupt signal. (However, releasing mask of STATUS_NAK bit by using
interrupt control register is needed.) In Vendor Request, this problem will not
generate because of receiving buffer size is set to host controller by driver,
actually.
Note: In every host, data (data that is transmitted from device by payload of 8 bytes) may be
recognized to short packet until confirming payload size of device side. And it may become to above
case on the exterior. Therefore, if controlling standard request by using software, be careful.)
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(b) Control write/request
There is no dataphase
bmRequestType
010000xxB
bRequest
wValue
wIndex
wLength
0
Data
None
Vendor peculiar
Vendor peculiar
Vendor peculiar
When INT_SETUP is received, judge contents of receiving request by
bmRequestType, bRequest, wValue, wIndex, wLength registers. And execute
transaction for each request. As application, access Setup_Received register
after request was judged. And it must inform that INT_SETUP interrupt was
recognized to UDC. If transaction of application finished, write “0” to EP0 bit
of EOP register. When UDC receive it, status stage finish automatically.
There is dataphase
bmRequestType
bRequest
wValue
wIndex
wLength
Data
010000xxB
Vendor peculiar
Vendor peculiar
Vendor peculiar
Vendor peculiar
(Except for 0)
Vendor data
When INT_SETUP is received, judge contents of receiving device request
by bmRequestType, bRequest, wValue, wIndex, wLength registers. And
execute transaction for each request. As application, access Setup_Received
register after request was judged. And it must inform that INT_SETUP
interrupt was recognized to UDC.
After receiving data prepared in application, access DATASET register, and
confirm EP0_DSET is “1”. After confirming, read data FIFO of endpoint 0. If
receiving data more than payload, write data after it confirmed whether a bit
of EP0_DSET_A in DATASET register is “1”. (INT_ENDPOINT0 interrupt is
can be used.) If reading all data finish, write “0” to EP0 bit of EOP register.
When UDC receive it, status stage finished automatically.
And when UDC finish status stage normally, INT_STATUS interrupt is
asserted. If finishing status stage normally is recognized to external
application, manage this stage by using this interrupt signal. If status stage
cannot be finished normally and during status stage, maybe new SETUP
token is received. In this case, when INT_SETUP interrupt signal is asserted,
“1” is set to STAGE_ERROR bit of EP0_STATUS register. And it informs it to
external that status stage cannot be finished normally.
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Below is control flow in UDC watch from application.
Start up
Setting each EP mode
in Set_Config (Interface)
IDLE
Standard request
Printerclass request
Enumeration
Judge request RD
Access to SetupReceived register
Control RD transfer
Control WR transfer
Get_Vendor_Request
transaction
Set_Vendor_Request
transaction
EP0 bit = 1
Check
EP0 bit = 0
EP0 bit = 0
EP0 bit = 1
Receive
judgement
Transmit
Check
judgement
DATASET
register
DATASET
register
Total_Length
Total_Length
Total = 0
Total ≥ payload
Total < payload
Total > payload
Total ≤ payload
Not
transaction
Total = 0
WR number of payload
to EP0_FIFO register
Total = Total − payload
WR number of rest data
to EP0_FIFO
Total = 0
RD number of payload
from EP0_FIFO register from EP0_FIFO
Total = Total − payload
RD number of rest data
Total = 0
Receive
except
INT_STATUS
WR “0” only EP0 bit0 of
EOP register
Abnormal
finish
Status finish
transacrion in UDC
Normal
finish
Receive
INT_STAS
Figure 3.16.6 Control Flow in UDC Watch from Application
Note 1:There is not special case in this flow such as overlap receive SETUP packet.
Please refer to chaptor 4.5.2.3.
Note 2:This flow shows various request. However, transaction can be divided every each interrupt.
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3.16.6 Transfer mode and Protocol Transaction
UDC perform automatically in hardware as follows;
•
•
•
•
•
•
Receive packet
Judge address endpoint transfer mode
Error process
Confirm toggle bit CRC of data receiving packet
Generate including toggle bit CRC of data transmitting packet
Handshake answer
(1) Protocol outline
Format of USB packet is showed to below. This is processed during transmission and
receiving by hardware into UDC.
•
•
•
SYNC field
This field always exists first of each packet, and input data and internal CLK is
synchronized in UDC.
Packet identification field (PID)
This field follows on SYNC field at every USB packet. UDC judge PID type and
judge transfer type by decoding this cord.
Address field
UDC confirms whether this function was appointed or not from host by using
this field. UDC compares with address that was set to ADDRESS register. If an
address accords with it, UDC continues process. If an address doesn’t accord, UDC
ignores this token.
•
•
Endpoint field
If sub-channels more than two is needed in field of 4 bits, it decides it function.
UDC can be supported endpoint except for control endpoint (max 7 endpoint).
Token for endpoint that is permitted is ignored.
Frame number field
Field of 11 bits is added +1 at every frame by host. This field follows to SOF token
that is transmitted in first of each frame, and frame number is appointed. UDC
reads content of this field when SOF token is received, and it sets frame number to
FRAME register.
•
•
Data field
This field is data of unit byte in 0 to 1023 bytes. When receiving it, UDC
transfers only part of this data to FIFO, after CRC was confirmed, interrupt signal
is asserted. And UDC informs finishing transferring data to FIFO. When
transmitting, following IN token, data of FIFO is transferred. Finally, data CRC
field is attached.
CRC function
Token is attached 5 bits, data is attached CRC of 15 bits. UDC compares CRC of
received data with attached CRC automatically. When transmission, CRC is
generated automatically and it is transmitted. This function may be compared by
various transfer modes.
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(2) Transfer mode
UDC support transfer mode in FULL speed.
•
FULL speed device
Control transfer type
Interrupt transfer type
Bulk transfer type
Isochronous transfer type
Following is explanation of UDC operation in each transfer mode.
Explanation of data flow is explanation until FIFO.
(a) Bulk transfer type
Bulk transfer type warrants transferring no error between host and function by
using detect error and retry. Basically, 3 phases (token, data and handshake are
used) are used. However, if flow control and STALL condition, data phase is
changed to hand shake phase, and it become to 2 phases. UDC holds status of
every each endpoint, and it control flow control in hardware. Each endpoint
condition can be confirmed by using EPx_STATUS register.
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(a-1) Transmission bulk mode
Below is transaction format of bulk transfer during transmitting.
•
•
•
Token: IN
Data: DATA0/DATA1, NAK, STALL
Handshake: ACK
Control flow
Below is control-flow when UDC receive IN token.
1. Token packet is received and address endpoint number error is confirmed, and it
checks whether conform applicable endpoint transfer mode with IN token. If it
doesn’t conform, state return to IDLE.
2. Condition of EPx_STATUS register is confirmed.
•
•
INVALI condition: State return to IDLE.
STAL condition: Stall handshake is returned and state return to IDLE.
FIFO condition is confirmed, if data number of 1 packet is not prepared, NAK
handshake is returned, and state return to IDLE.
If data number of 1 packet is prepared to FIFO, it shifts to 3.
3. Data packet is generated.
Data packet generated by using toggle bit register in UDC.
Next, it transfers data from FIFO of internal UDC to SIE, and data packet is
generated. At this point, it confirms transferred data number. And if there is more
than max payload size of each endpoint, bit stuff error is generated, and finish
transfer. And STATUS becomes to STALL.
4. CRC bit (counted transfer data of FIFO from first to last) is attached to last.
5. When ACK handshake from host is received,
•
•
•
•
Clear FIFO.
Clear DATASET register.
Renew toggle bit, and prepare for next.
Set STATUS to READY.
UDC finishes normally. FIFO can be received next data.
If it is time out without receiving ACK from host,
•
•
Set STATUS to TX_ERR.
Put back addles pointer of FIFO.
Execute above setting. And wait next retry keeping FIFO data.
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IDLE
Receive IN token
ConfirmToken packet
Error
•
•
•
•
•
PID
Address
Endpoint
Transfer mode
Error
Invalid
OK
Confirm Handshake answer
Stall
•
Confirm STATUS register (Status)
Confirm DATASET register
FIFO empty
•
OK
More than MAX
payload
Generate DATA PID
• Attach DATA0/DATA1
• Confirm Datasize register
Transmit NAK
Transmit STALL
OK
Bit stuff error
Set STATUS at STALL
Transmit data
OK
Attach CRC
OK
Time out
• Set STATUS to TX_ERR
• Put back addless pointer of FIFO
Wait ACK
to host
Receive ACK
Normal finish transaction
• Clear FIFO
• Clear DATASET register
• Renew toggle bit
• Set STATUS to READY
Figure 3.16.7 Control Flow in UDC (Bulk transfer type (transmission)/Interrupt transfer type (transmission))
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(a-2) Receiving bulk mode
Below is transaction format receiving bulk transfer type. It has to follow below.
•
•
•
Token: OUT
Data: DATA0/DATA1
Handshake: ACK, NAK, STALL
Control flow
Below is control-flow when UDC receive IN token.
1. Token packet is received and address endpoint number error is confirmed, and it
checks whether conform applicable endpoint transfer mode with OUT token. If it
doesn’t conform, state return to IDLE.
2. Condition of status register is confirmed.
•
•
INVALID condition: State return to IDLE.
STALL condition: When dataphase finish, stall handshake is returned
and state return to IDLE, and data is canceled.
FIFO condition is confirmed, if data number of 1 packet is not prepared, present
transferred data is canceled, NAK handshake is returned after dataphase, and
state return to IDLE.
3. Data packet is received.
Data is transferred from SIE of internal UDC to FIFO. At this point, it confirms
transferred data number. And if there is more than max payload size of each
endpoint, STATUS become to STALL and state return to IDLE. ACK handshake
doesn’t return.
4. After last data was transferred, and compare counted CRC with transferred CRC.
If it doesn’t conform, it sets STATUS to RX_ERR and state return to IDLE. At this
point it doesn’t return ACK.
After retry, when next data is received normally, STATUS changes to DATIN. If it
doesn’t accord data toggle, it was judged don’t take ACK in last loading. And now
loading is regarded retry of last loading and data cancel. Set STATUS as RX_ERR,
return to host and return IDLE. FIFO address pointer returns. And it can be
received next data.
5. If CRC compare with toggle and it finished normally, ACK handshake is returned.
Bellow is process in UDC.
•
•
•
•
Set transfer data number to DATASIZE register.
Set DATASET register.
Renew toggle bit, and prepare for next.
Set STATUS to READY.
UDC finishes normally.
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IDLE
Receive OUT token
Error
Confirm Token packet
• PID
• Address
• Endpoint
• Transfer mode
• Error
Invalid
OK
Confirm Status
• Confirm STATUS register (status)
• Confirm FIFO’s condition
Stall
FIFO empty
Error transaction
OK
• Set STATUS at
RX_ERR
• Put back FIFO
address pointer
Except data PID
Time out
Generate DATA PID
• DATA0/DATA1
• Time out
• Toggle check
OK
Toggle error
• Set STATU Sat RX_ERR
• Put back FIFO address
pointer
• Retry recognition clean
data
Cancel data
Cancel data
Error
transaction
• Set status to
stall
Receive data
• Error
• Confirm receiving data
number
Data communication of
more than payload
OK
Transmit ACK
Transmit NAK
Transmit STALL
OK
Retry transaction
Normal finish transaction
• Set transfer data number to DATASIZE
register
• Set DATASET register
• Renew toggle bit
• Set STATUS to DATAIN
Figure 3.16.8 Control Flow in UDC (Bulk transfer type (Receiving))
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(b) Interrupt transfer type
Interrupt transfer type use transaction format same with transmission bulk
transfer.
When transmission by using toggle bit, hardware setting and answer in UDC
are same with transmission bulk transfer. Interrupt transfer can be transferred
without using toggle bit. In this case, if ACK handshake from host is not received,
toggle bit is renewed, and finish normally. UDC clears FIFO for next transfer.
(b-1) Interrupt transmitting mode (Toggle mode)
UDC operation is same with bulk transmission mode. Please refer to section
(a).
(b-2) Interrupt transmission mode (Not toggle mode)
This is same bulk transmission mode basically. However, if ACK handshake
from host is not received, transaction is different.
After transmit data packet,
When ACK handshake from host is received,
•
•
•
•
Clear FIFO.
Clear DATASET register.
Renew toggle bit and prepare for next.
Set STATUS to READY.
UDC finishes normally by above transaction. FIFO can be received next data.
If it is time out without receiving ACK from host,
•
•
•
•
Clear FIFO.
Clear DATASET register.
Renew toggle bit and prepare for next.
Set STATUS to TX_ERR.
Execute above setting. This setting is same with except STATUS.
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(c) Control transfer type
Control transfer type is configured in below three stages.
Setup stage
Data stage
Status stage
•
•
•
Data stage is skipped sometimes. Each stage is configured in one or plural
transaction. UDC executes each transaction while managing of three stages in
hardware. Control transfer type has below 3 type by whether there is data stage
or not, or direction.
•
•
•
Control read transfer type
Control write transfer type
Control write transfer type (Not data stage)
UDC answers automatically about standard request in hardware. Class request,
vendor request have to intervening CPU on controlling UDC.
Below is control flow in UDC and control flow in intervening CPU.
(c-1) Setup stage
Setup stage is same with transmission bulk transaction except case of token ID
become to SETUP.
However, control flow in UDC differ it.
•
•
•
Token: SETUP
Data: DATA 0
Handshake: ACK
Control flow
Below is control flow in UDC when SETUP token is received.
1. SETUP token packet is received and address, endpoint number and error
are confirmed. And it checks whether applicable endpoint is the control
transfer mode.
2. STATUS register state is confirmed.
State return to IDLE only it is INVALID state.
In bulk transfer mode, receiving data is enabled by STATUS registers value
and FIFO condition. However, in SETUP stage, STATUS is returned to
READY and accessing from CPU to FIFO is prohibited always, and internal
FIFO of endpoint 0 is cleared. And it prepares for following dataphase.
If CPU accesses Setup Received registers in UDC, it recognizes as Device
request is received, and accessing from CPU to EP0 is enabled.
There is this function for receiving it if new request is received in during
present device request is not finishing normally.
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3. Data packet is received.
Device request of 8 bytes from SIE in UDC is transferred to below
request register.
•
•
•
•
•
bmRequestType register
bmRequest register
wValue register
wIndex register
wLength register
4. After last data was transferred, and compare counted CRC with
transferred CRC. If it doesn’t conform, it sets STATUS to RX_ERR and
state return to IDLE. At this point it doesn’t return ACK, and host retry.
5. If CRC compare with toggle and it finish normally, ACK handshake is
returned to host. Bellow is process in UDC.
•
Receiving device request is judged whether software control or
hardware control, if request need control in software, request is
informed receiving to external by asserting INT_SETUP interrupt.
If using hardware, INT_SETUP interrupt is not asserted.
•
•
•
According to stage control flow, prepare for next stage.
Set STATUS to DATAIN.
Set toggle bit to “1”.
Setup stage finishes by above.
8-byte data that is transferred by this SETUP stage is device request.
CPU must process correspond it device request.
UDC detects following contents only from data of 8 bytes, and it manages
stage in hardware.
•
•
There is data stage or not
Data stage direction
It judges control read transfer type, control write transfer type, control
write transfer type (not data phase) by them.
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IDLE
Receive SETUP token
Confirm Token packet
Error
•
•
•
•
•
PID
Address
Endpoint
Transfer mode
Error
Invalid
Error transaction
•
•
Set STATUS to RX_ERR
Put back FIFO address point
OK
Confirm Status
• Confirmation STATUS register (Status)
OK
Except DATA0 PID
Confirm DATA PID
•
•
DATA0
Time out
Time out
OK
Error, more than payload data comunication
Receive data
Error
•
•
Confirm receving data
number
OK
Transmit ACK
OK
Normal finish transaction
• Set DATASET register
• Assert INT_SETUP and request flag
• According to stage flow, prepare for next stage
• Set STATUS to DATAIN
• Set toggle bit to 1
Figure 3.16.9 Control Flow in UDC (Setup stage)
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(c-2) Data stage
Data stage is configured by one or plural transaction base on toggle sequence.
Transaction is same with format transmission or receiving bulk transaction.
However, below is difference.
•
•
Toggle bit start from “1” by SETUP stage.
It judges whether right or not by comparing IN and OUT token with
direction bit of device request. If token that direction is reverse was
received, it is recognized as status stage.
•
INT_ENDPOINT0 interrupt is asserted.
(c-3) Status stage
Status stage is configured 0-data-length packet with DATA1’s PID and
handshake behinds IN or OUT token. It uses transaction that direction different
with preceding stage.
Combination is below.
•
•
•
Control read transfer type: OUT
Control write transfer type: IN
Control write transfer type (not dataphase): IN
UDC processes status stage base of control flow in control transfer type. At this
point, CPU must write “0” to EP0 bit of EOP register in last transaction for status
stage finish normally.
Below is detail of status stage.
(c-3-1) IN status stage
Below is IN status stage transaction format.
•
•
•
Token: IN
Data: DATA1 (0 data length), NAK, STALL
Handshake: ACK
Control flow
Below is transaction flow of IN status stage in UDC.
1. Token packet is received and address, endpoint number and error are
confirmed. If it doesn’t conform, state return to IDLE. If status stage
is enabled base on stage control flow in UDC, advance next stage.
2. STATUS register state is confirmed.
•
•
INVALID condition: State return to IDLE.
STALL condition: Stall handshake is returned and state return
to IDLE.
It confirm whether EOP register is accessed or not by external. If it
is not accessing, NAK handshake is returned for continue control
transfer. And state return to IDLE.
3. If EOP register is accessed was confirmed, 0-data-length data packet
and CRC are transmitted.
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4. If ACK handshake from host is received,
•
•
Set STATU to READY.
Assert INT_STATUS interrupt.
It finishes normally by above transaction.
If it is time out without receiving ACK from host,
•
Set STATUS register to TX_ERR and state return IDLE. And wait
restring status stage.
At this point, if new SETUP stage is started without status stage finish
normally, UDC sets error to STATUS register.
(c-3-2) OUT status stage
Below is transaction format of OUT status stage.
•
•
•
Token: OUT
Data: DATA1 (0 data length)
Handshake: ACK, NAK, STALL
Control flow
Below is transaction flow of OUT status stage in UDC.
1. Token packet is received and address, endpoint number and error are
confirmed. If it doesn’t conform, state return to IDLE. If status stage
is enabled base on stage control flow in UDC, advance next stage.
2. STATUS register state is confirmed.
•
•
INVALID condition: State return to IDLE.
STALL condition: Data is cleared, stall handshake is returned,
and state return to IDLE.
It confirm whether EOP register is accessed or not by external. If it is
not accessing, NAK handshake is returned for continue control
transfer. And state return to IDLE.
3. If EOP register is accessed was confirmed, 0-data-length data packet
and CRC are received.
4. If there is not error in data, ACK handshake is transmitted to host.
•
•
Set STATUS to READY.
Assert INT_STATUS interrupt.
It finishes normally by above transaction.
If there is error in data, ACK handshake is not returned.
•
Set RX_ERR to STATUS register and return to IDLE. It waits retrying
status stage.
At this point, if new SETUP stage is started without status stage finish
normally, UDC sets error to STATUS register. Sequence of this protocol refers
to section supplement.
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(c-4) Stage management
UDC manages each stage of control transfer by hardware.
Each stage is changed by receiving token from USB host, or CPU accesses
register. Each stage in control transfer type has to process combination software.
UDC detect following contents from 8-byte data in SETUP stage. (It contents is
showed to following.) And, stage is managed by judging control transfer type.
•
•
There is data stage or not
Data stage direction
Control read transfer type is jugged control write transfer type, control write
transfer type (No data stage) by them.
Below are various conditions for changing stage in control transfer.
If receiving token for next stage from host before switching next stage from
state of internal UDC, NAK handshake is returned and BUSY is informed to USB
host. In all control transfer type, if SETUP token is received from host always,
present transaction is stopped, and it switches SETUP stage in UDC. CPU receive
new INT_SETUP even if it is processing previous control transfer.
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Stage change condition of control read transfer type
1. Receive SETUP token from host
•
•
Start setup stage in UDC.
Receive data in request normally and judge. And assert INT_SETUP
interrupt to external.
•
Change data stage into the UDC.
2. Receive IN token from host
•
•
•
•
CPU receive request from request register every INT_SETUP
interrupt.
Judge request and access Setup Received register for inform that
recognized INT_SETUP interrupt to UDC.
According to Device request, monitor EP0 bit of DATASET register,
and write data to FIFO.
If UDC is set data of payload to FIFO or CPU set short packet
transfer in EOP register, EP0 bit of DATASET register is set.
•
•
•
UDC transfers data that is set to FIFO to host by IN token interrupts.
When CPU finish transaction, it writes “0” to EP0 bit of EOP register.
Change status stage in UDC.
3. Receive OUT token from host.
•
•
Return ACK to OUT token, and state change to IDLE in UDC.
Assert INT_STATUS interrupt to external.
These changing conditions are shown in Figure 3.16.10.
SETUP DATA0 ACK
IN
NAK
IN DATA1 ACK
IN DATA0 ACK
OUT DATA1 ACK
INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
DATASET register
BRD
BWR
bmRequestType register
bRequest register
wValue register
Setup Received register
EP0_FIFO (Rest data)
EOP register
EP0_FIFO (WR of payload)
wIndex register
wLength register
Figure 3.16.10 The Control Flow in UDC (Control Read Transfer Type)
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Stage change condition of control write transfer type
1. Receive SETUP token from host.
•
•
Start setup stage in UDC.
Receive data in request normally and judge. And assert INT_SETUP
interrupt to external.
•
Change data stage in UDC.
2. Receive OUT token from host.
•
•
•
CPU receive request from request register every INT_SETUP
interrupt.
Judge request and access Setup Received register for inform that
recognized INT_SETUP interrupt to UDC.
Receive dataphase data normally, and set EP0 bit of DATASET
register.
•
•
•
•
CPU receives data in FIFO by setting DATASET.
CPU process receiving data by device request.
When CPU finish transaction, it writes “0” to EP0 bit of EOP register.
Change status stage in UDC.
3. Receive IN token from host.
•
Return data packet of 0 data to IN token, and state change to IDLE in
UDC.
•
Assert INT_STATUS interrupt to external when receive ACK for 0
data packet.
These changing conditions are shown in Figure 3.16.11.
SETUP DATA0 ACK OUT DATA1 ACK OUT DATA0 NAK OUT DATA0 ACK
IN
NAK
IN DATA1 ACK
INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
DATASET register
BRD
BWR
bmRequestType register
Setup Received register
EP0_FIFO (Rest data)
EP0_FIFO (RD of payload)
EOP register
bRequest register
wValue register
wIndex register
wLength register
Figure 3.16.11 The Control Flow in UDC (Control Write Transfer Type)
In control read transfer type, transaction number of data stage do not always
accord with data number that is apppointed by device request. Therefore, CPU
can be processd by using INT_STATUSNAK interrupt. However, when class and
vendor request is used, be accord wLength value with data transfer number in
data phase. By this setting, using this interrupt is not need. Data stage data can
be confirmed by accessing DATASIZE register.
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Stage change condition of control write (no data stage) transfer type
1. Receive SETUP token from host
•
•
Start setup stage in UDC.
Receive data in request normally and judge. And assert INT_SETUP
interrupt to external.
•
Change data stage in UDC.
2. Receive IN token from host
•
CPU receive request from request register every INT_SETUP
interrupt.
•
Judge request and access Setup Received register for inform that
recognized INT_SETUP interrupt to UDC.
•
•
•
•
CPU process receiving data by device request.
When CPU finish transaction, it writes “0” to EP0 bit of EOP register.
Change status stage in UDC.
Return data packet of 0 data to IN token, and state change to IDLE in
UDC.
•
Assert INT_STATUS interrupt to external when receive ACK for 0
data packet.
These change condition is Figure 3.16.12.
SETUP DATA0 ACK
IN
NAK
IN DATA1 ACK
INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
DATASET register
BRD
BWR
bmRequestType register
Setup Received register
EOP register
bRequest register
wValue register
wINdex register
wLength register
Figure 3.16.12 The Control Flow in UDC (Control Write Transfer Type not Dataphase)
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(d) Isochronous transfer type
Isochronous transfer type is guaranteed transfer by data number that is limited
every each frame.
However, this transfer don’t retry when error occurs. Therefore, Isochronous
transfer type transfer only 2 phases (token, data) and it doesn’t use handshake
phase. And data PID for data phase is DATA0 always because of this transaction
doesn’t support toggle sequence. Therefore, UDC doesn’t confirm when data PID
is receiving mode.
Isochronous transfer type process data every frame. Therefore, all transaction
for finish transfer use receiving SOF token. UDC use FIFO that is divided into
two in Isochronous transfer type.
(d-1) Isochronous transmission mode
Isochronous transfer type format in transmitting is below transaction format.
•
•
Token: IN
Data: DATA0
Control flow
Isochronous transfer type is frame management. And data that write to
FIFO in endpoint is transmitted by IN token in next frame.
Below are two conditions in FIFO of Isochronous transmission mode
transferring.
X. FIFO for storing data that transmits to host in present frame
(DATASET register bit = 1)
Y. FIFO for storing data for transmitting host in next frame
(DATASET register bit = 0)
FIFO that is divided into two (packet A and packet B) conditions is whether
X condition or Y condition. Below flow is explained as X Condition (packet A),
Y Condition (packet B) in present frame.
X and Y conditions change one after the other by receiving SOF.
Below is control flow in UDC when receiving IN token.
1. Token packet is received and address endpoint number error is confirmed,
and it checks whether conform applicable endpoint transfer mode with
IN token. If it doesn’t conform, state return to IDLE.
2. Condition of status register is confirmed.
•
INVALID condition: State return to IDLE.
3. Data packet is generated.
Data packet is generated. At this point, data PID attach DATA0
always. Next, data is transferred from FIFO (X condition) of packet A in
UDC to SIE. And it generate DATA packet.
4. CRC bit (counted transfer data of FIFO from first to last) is attached to
last.
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5. Below is transaction when SOF token from host is received.
•
Change the packet A’s FIFO from X Condition to Y Condition. And
clear data.
•
•
•
•
Change the packet B from Y Condition to X Condition.
Set frame number to frame register.
Assert SOF and inform that frame is incremented to external.
DATASET register clears packet A bit and it sets packet B bit
arrangement loading in present frame.
•
Set STATUS to READY.
UDC finishes normally by above transaction.
Packet A’s FIFO can be received next data.
In renewed frame, Packet A’s FIFO interchange packet B’s FIFO, and
transaction is used same flow.
If SOF token is not received by error and so on, this data is lost because of
frame is not renewed. Nothing problem in receiving PID and if frame data is
received with CRC error, USB sets LOST to STATUS on FRAME register, and
frame number is not renewed. However, in this case, SOF is asserted and
FIFO condition is renewed. If SOF token is received without transmit and
transfer Isochronous in frame, UDC clears FIFO (X Condition) and sets
STATUS to FULL.
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IDLE
Receive IN token
Confirm Token packet
•
•
•
•
•
PID
Error
Address
Endpoint
Transfer mode
Error
OK
Confirm Status
Invalid
•
Confirm STATUS register (status)
OK
Generate DATA PID
•
•
Attach DATA0
Confirm DATASIZE register
OK
Receive SOF
without transmitting data
Clear X condition (A)
Set FULL to STATUS
Transmit data
Set LOST to FRAME register
Not renew FRAME number
Assert SOF
Error transaction
Attach CRC
BANK B transaction
• Assert SOF
IDLE
• Clear transmitting FIFO BANK A in preceding frame
• Clear DATASET register’s BANK A bit
• Set DATASET register’s BANK B bit
(Finish a write in previous frame)
ReceiveSOF
• FRAME noread
• BANK shift
Shift FIFO BANKs
every receive SOF
• Set STATUS to READY
• Wait data for transmitting next frame (BANK A)
Not receive SOF
Not renewal frame number
loss data
BANK A transaction
• Assert SOF
• Clear transmitting FIFO BANK B in preceding
frame
• Clear DATASET register’s BANK B bit
• Set DATASET register’s BANK A bit
(Finish a write in previous frame)
• Set STATUS to READY
Figure 3.16.13 Control Flow in UDC (Isochronous transfer type (Transmission))
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(d-2) Isochronous receiving mode
Isochronous transfer type format in receiving is below transaction format.
•
•
Token: OUT
Data: DATA0
Control flow
Isochronous transfer type is frame management. And data that is written to
FIFO by OUT token is received to CPU in next frame.
Below are two conditions in FIFO of Isochronous receiving mode
transferring
X. FIFO for storing data that received from host in present frame
(DATASET register bit = 0)
Y. FIFO for storing data for transmitting host in previous frame
(DATASET register bit = 1)
FIFO that is divided into two (packet A and packet B) conditions is whether
X condition or Y condition. Below flow is explained as X Condition (packet A),
Y Condition (packet B) in present frame.
X and Y conditions change one after the other by receiving SOF.
Below is control flow in UDC when receiving OUT token.
All transaction is processed by hardware.
1. Token packet is received and address endpoint number error is confirmed,
and it checks whether conform applicable endpoint transfer mode with
OUT token. If it doesn’t conform, state return to IDLE.
2. Condition of status register is confirmed.
•
INVALID condition: State return to IDLE.
3. Data packet is received.
Data is transferred from SIE into the UDC to packet A’s FIFO (X
Condition).
4. After last data was transferred, and compare counted CRC with
transferred CRC. When transfer finish, result is reflected to STATUS.
However, data is stored FIFO, data number that packet A is received is
set to DATASIZE register of packet A.
5. Below is transaction when SOF token from host is received.
•
•
Change the packet A’s FIFO from X Condition to Y Condition.
Change the packet B from Y Condition to X Condition, and clear data.
Prepare for next transfer.
•
•
•
Set frame number to frame register.
Assert SOF and inform that frame is incremented to external.
DATASET register set packet A bit and it clear packet B bit
arrangement loading in present frame.
•
If CRC comparison result agree it, DATAIN is set to STATUS. If
result doesn’t agree, RX_ERR is set to STATUS.
UDC finishes normally by above transaction.
CPU takes back packet A’s data.
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In renewed frame, Packet A’s FIFO interchange packet B’s FIFO, and
transaction is used same flow.
If SOF token is not received by error and so on, this data is lost because of
frame is not renewed. Nothing problem in receiving PID and if frame data is
received with CRC error, USB sets LOST to STATUS on FRAME register, and
frame number is not renewed. However, in this case, SOF is asserted and
FIFO condition is renewed. If SOF token is received without transmit and
transfer Isochronous in frame, UDC clears FIFO (X Condition) and sets
STATUS to FULL.
These are shown in Figure 3.16.14.
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IDLE
Receive OUT token
Confirm Token packet
•
•
•
•
•
PID
Error
Address
Endpoint
Transfer mode
Error
OK
Invalid
Confirm Status
Confirming STATUS register (status)
OK
Confirm DATA PID
Error, time out exept data PID
•
•
Time out
Error
OK
Receive SOF nothing
transmitting data
Clear X Condition (A)
Error, receiving data more than payload.
Receiving data
•
•
Error
Receive receiving data
Error transaction
Set STATUS to RX ERR
BANK B transaction
IDLE
•
•
Assert SOF
Set data size received preceding frame to
DATASIZE register in BANK A
Receive SOF
•
•
Frame no read
Shift BANK
•
•
•
Set BANK A bit in DATASET register
Clear BANK B bit in DATASET register
Shift FIFO BANK
every receive SOF
Set STATUS to DATAIN
(But if error generate, set RX_ERR)
Not receive SOF
Not renew frame number
loss data
BANK A transaction
•
•
Assert SOF
Set data size received preceding frame to
DATASIZE register in BANK B
•
•
Set BANK B bit in DATASET register
Clear BANK A bit in DATASET register
•
Set STATUS to DATAIN
(But if error generate, set RX_ERR)
Figure 3.16.14 Control Flow in UDC (Isochronous transfer type (Receiving))
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3.16.7 Bus Interface and Access to FIFO
(1) CPU bus interface
UDC prepares two types of FIFO access, single packet and dual packet. In single
packet mode, FIFO capacity that is implemented by hardware is used as big FIFO. In
dual packet mode, FIFO capacity that is divided into two is used as two FIFOs. And it
uses as independent FIFO. Even if UDC is transmitting and receiving to USB host, it
can be used bus efficient by to possible load to FIFO.
But control transfer type receives only single packet mode.
Epx_SINGLE signal in dual packet mode must be fixed to “0”. If this signal is fixed to
“0”, FIFO register runs in single mode.
Sample: If you use endpoint 1 to dual packet of payload 64 bytes.
EP1_FIFO size
EP1_SINGLE signal
EP1 Descriptor setting
Direction
:
Prepare 128 bytes
:
Hold 0
:
:
:
Optional
64 bytes
Optional
Max payload size
Transfer mode
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(a) Single packet mode
This is data sequence of single packet mode when CPU bus interface is used.
Main of this chapter is access to FIFO. Data sequence with USB host refer to
chapter 5.
Endpoint 0 can’t be changed mode for exclusive single packet mode. Single
packet and dual packet of endpoint 1 to 3 can change by setting Epx_SINGLE
register. When transferring, don’t change packet.
Wait receiving data
IDLE
Receive valid data
DATASET register
• Set bit of EPx_D SET_A
• Assert EPx_DATASET signal
DATASET = 0
Interrupt by EPx_FULLA
Check DATASET register
DATASET register
• Check bit of EPx_DSET_A
DATASET = 1
SIZE register
• Size of SIZE_A_L confirmation
• Size of SIZE_A_H confirmation
RD receiving data of size in
appricable endpoint
• Clear receiving data in FIFO
• Clear applicable bit of DATASET
register
Figure 3.16.15 Receiving Sequence in Single Packet Mode
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Below is transmitting sequence in single packet mode.
Wait transmission event
IDLE
Transmission event
DATASET = 0
DATASET register
• Check bit of EPx_DSET_A
DATASET = 1
Distinction
transmitting
Wait transmitting
rest data
Transmitting number > payload
Transmitting number < payload
• WR of payload to applicable endpoint
• WR of transmitting number applicable endpoint
• Total = Total − payload
• Total = 0
EOP register
If transmitting number reach to
payload, applicable bit of
DATASET register is set 1
WR 0 to only bit of applicable endpoint
If transmitting finish normally,
it clears applicable bit of DATASET.
Wait transmitting
• Must access to EOP register in transmitting
short packet.
Wait IN token
• This is used showing to the closing control
transfer type.
If you access to endpoint 0, you must to
access in closing control transfer type.
Finish
transmitting
Figure 3.16.16 Transmitting Sequence in Single Packet Mode
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(b) Dual packet mode
In dual packet mode, FIFO is divided into A and B packet, it is controlled
according to priority in hardware. It can be performed at once, transmitting and
receiving data to USB host and exchanges to external of UDC. When it reads out
data from FIFO for receiving, confirm condition of two packets, and consider the
order of priority. If it has received data to two packets, UDC outputs from first
receiving data by FIFO that can be accessed are common in two packets.
DATASIZE register is prepared every packet A and packet B. First, CPU must
recognize data number of first receiving packet by PACKET_ACTIVE bit. If
PACKET_ACTIVE bit was set to 1, that packet is received, first. Packet A and
packet B set data turn about always.
Below is this sequence.
Wait receiving data
IDLE
Receiving valid data
DATASET register
• Set bit of EPx_DSET_A (B)
• Assert EPx_DATASET signal
DATASET = 0
Interrupt by EPx_FULL_A (B)
Check DATASET register
DATASET register
• Check bit of EPx_DSET_A
• Check bit of EPx_DSET_B
DATASET = 1
SIZE register
• Confirm Size of SIZE_A_L
• Confirm Size of SIZE_A_H
• Confirm Size of SIZE_B_L
• Confirm Size of SIZE_B_H
• Read size of receiving data from applicable endpoint
• There is below 3 cases by setting bit of DATASET
Only A: Read number of sizeA register
Only B: Read number of sizeB register
Both of A and B: Read number of sizeA + B register
• Clear receiving data in FIFO
• Clear applicable bit in DATASET register
Figure 3.16.17 Receiving Sequence in Dual Packet Mode
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When it writes data to FIFO in transmitting, confirm condition of two packets,
and consider the order of priority. When transfer data number is set, set to which
packet A and packet B, judge by PACKET_ACTIVE bit. Packet that bit is set to 0 is
bit that transfer now.
In transmitting and receiving, logic of PACKET_ACTIVE bit is reversed.
Therefore, please caution in transmitting.
Below is this sequence.
Wait transmitting event
IDLE
Interrupt by EPx_EMPTY_A (B)
Check DATASET register
Transmitting event
DATASET = 0
DATASETregister
• Check bit of EPx_DSET_A
• Check bit of EPx_DSET_B
DATASET = 1
Transmittind
data distinction
Wait
transmitting
rest data
Transmitting number < payload × 2
• Write number of transmitting
number
Transmitting number > payload × 2
• Write number of payload × 2 in
applicable endpoint
• Total = 0
• Total = Total − payload × 2
EOP register
If transmitting number reach to
payload, DATASET set 1 to
applicable bit of register
Write 0 to only bit of applicable
endpoint
If transmitting finish normally,
It clears applicable
Wait transmitting
bit of DATASET.
• Accessing to EOP register is needed in
transmitting short packet
Wait IN token
• Control transfer type is only single mode
Finish
transmitting
Figure 3.16.18 Transmitting Sequence in Dual Packet Mode
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(c) Issuance of NULL packet
If transmitting NULL packet, by input L pulse from EPx_EOPB signal, data of 0
length is set to FIFO, and it can be transferred NULL packet to IN token.
But if it set NULL data to FIFO, it is valid only case of SET signal is L level
condition (case of FIFO is empty). If it answer to receiving IN token by using NULL
packet in a certain period, it is answered by keeping EPx_EOPB signal to L level.
However, if mode is dual packet mode, EPx_DATASET signal assert L level for
showing space of data. Therefore, data condition (both data have not data) cannot
be confirmed from external.
Note: NULL packet can be set also accessing EOP register.
Example:
NULL packet
completion of
transmitting
DATASET_A
DATASET_B
EPx_EOPB
NULL Neglect NULL
NULL
NULL
B
NULL
A
A
B
A
(2) Interrupt control
Interrupt signal is prepared. This function use adept system.
Detail refers to 3.10.2 900/H1 CPU I/F.
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3.16.8 USB Device answer
USB controller (UDC) sets various register and initialization in UDC in detecting of
hardware reset, detecting of USB bus reset, and enumeration answer.
Below is explaining about each condition.
(1) Condition in detect in bus reset.
When UDC detects bus reset on USB signal line, it initializes internal register, and it
prepares enumeration operation from USB host. After detect in USB reset, UDC sets
ENDPOINT0 to control transfer type 8-byte payload and default address for using
default pipe. And endpoint except for it is prohibited.
Register name
Initial value
40H
ENDPOINT STATUS
EP0
Except for EP0
5CH
(2) Detail of STATUS register
Status register that was prepared every endpoint shows condition of every endpoint
in UDC.
Each condition affects transfer various USB. Condition changing in each transfer
type refers to chapter 5.
EPx_STATUS register value is 0 to 3, and it shows conditions of below. 0 to 4 are
result of various transfers. It can be confirmed previous result that is transferred to
endpoint by confirming from external of UDC.
0
1
2
3
4
READY
DATAIN
FULL
TX_ERR
RX_ERR
These conditions mean that endpoint operate normally. Meaning that is showed is
different every transfer mode. Therefore, please refer to below each transfer mode
column.
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ISO transfer mode
Below is transfer condition of frame before one. Receiving SOF renews this.
OUT (RX)
IN (TX)
Initial
READY
READY
DATAIN
RXERR
READY
FULL
Not transfer
Finish normally
Detect in error
READY
TXERR
Transfer mode of except ISO transfer
This is result previous transfer. When transfer finish, this is renewed.
OUT, SETUP
IN
Initial
READY
DATAIN
READY
RXERR
READY
READY
READY
TXERR
Transfer finish normally
Status stage finish
Transfer error
“Initial” is that renew RESET, USB reset, Current_Config register. In detect error, it
doesn’t generate EPx_DATASET except toggle transfer mode and Isochronous transfer
mode of interrupt.
5 to 7 in showing of status register mean that endpoint is special condition.
5
BUSY
BUSY generate only endpoint of control transfer. If UDC transfer in control writes transfer,
when CPU isn’t finishing enumeration transaction, and if it receive ID of status stage from
USB host, BUZY is set. STATUS is BUZY until CPU finishes enumeration transaction and
EP0 bit of EOP register is written 0 in UDC. If CPU enumeration transaction finishes and
EP0 bit of EOP register is written 0 and status stage from USB host finish normally, it
displays READY.
Please refer to 5.2.3 in chapter 5.
6
7
STALL
STALL show that endpoint is STALL condition.
This condition generate if it violates protocol or error in bus enumeration. If return endpoint
to condition that transfer can normally, device request of USB is needed. This request
returns condition normally. But control endpoint returns to condition normally by receiving
SETUP token. And it become to SETUP stage.
INVALID
This condition shows condition that endpoint can’t be used. UDC sets condition that isn’t
appointed in ENDPOINT to INVALID condition, and it ignores all of token for this endpoint.
In initializing, this condition generate always. When UDC detects hardware reset, it sets all
endpoint to INVALID condition. Next, if USB reset is received, endpoint 0 only is renewed to
READY. Other endpoint that is defined on disruptor, is renewed if SET_CONFIG request
finish normally.
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3.16.9 Power Management
USB controller (UDC) can be switched from optional resume condition (turn on the power
supply condition) to suspend (Suspension) condition, and it can be returned from suspends
condition to turn on the power supply condition.
This function can be set to low electricity consumption by operating CLK supplying for
UDC.
(1) Switch to suspend condition
USB host can be set USB device to suspend condition by keeping on IDLE state.
UDC switches to suspend condition by below process.
•
UDC switches to suspend condition if it detect IDLE state of more than 3 ms on
USB signal. At this point, set SUSPEND bit of STATUS register to “1”.
•
After switch to suspend condition, if besides pass away 2 ms, UDC renews
USBINTFR1<INT_SUS> from “0” to “1”. After USBINTFR1<INT_CLKSTOP>
was renewed from “0” to “1”, set USBCR1<USBCLKE> to “0”, and be stopped
supply of CLK (USB_CLK).
In this condition, all register value into the UDC is kept. However, accessing from
external can’t be accessed except reading of STATUS register, Current_Config
register, and USBINTFR1, USBINTFR2, USBINTMR1, USBINTMR2 and
USBCR1
(2) Return from suspend condition by host resume
Way to UDC change from suspend condition to resume condition have two type;
resume condition output from USB host and remote wakeup.
When activity of bus on USB signal restore by resume condition output from USB,
UDC reset SUSPEND output from “1” to “0”, and it resets SUSPEND bit of STATUS
register from “0”. And it resumed system. Resume condition output from this host keep
on no less than during 10 ms. Therefore effective protocol occurring on USB signal line
is after pass away this time.
(3) Return from suspend condition by remote wakeup
Remote wakeup is system for prompt resume from suspending USB device to USB
host. Remote wakeup isn’t supported by condition. And remote wakeup is limited using
from USB host by bus enumeration.
Function of remote wakeup in UDC can be used when it is permitted.
Setting remote wakeup by bus can be confirmed bit7 of Current_Config register.
When this bit is “1”, remote wakeup can be used. Remote wakeup doesn’t disable in
this bit. Therefore, if this bit show disable, must not set remote wakeup. If it fill the
conditions, output resume condition output to USB host by writing
USBCR1<WAKEUP> from “1” to “0” of UDC in suspend condition. And it prompts
resume from UDC to host. After UDC changes to suspend condition, during 2 ms ignore
WAKEUP
input.
Therefore,
remote
wakeup
become
effective
by
USBINTFR1<INT_SUS> was set to “1”.
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(4) Low power consumption by control of CLK input signal
When UDC switches to suspend condition, it stops CLK and switches to low power
consumption condition. But as system, this function enables besides low power
consumption by stopping source of CLK that is supplied from external. CLK that
supply to UDC can be controlled clock supply to USB by using
USBINTFR1<INT_SUS> and <INT_CLKSTOP>.
If UDC switches to suspend condition, USBINTFR1<INT_SUS> is set to “1”, and
<INT_CLKSTOP> is set to “1”. After confirmation, stop supply CLK (USBCLK) by
setting “0” to USBCR1<USBCLKE>. If SUSPEND signal is set to “0” by resuming from
host, supply normal CLK to UDC within 3 ms.
When it uses remote wakeup, supplying stable CLK to UDC before using is needed.
When it uses doublers circuit as generation source, above control is needed.
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3.16.10 Supplement
(1) External access flow to USB communication
a) Normally movement
SETUP DATA0 ACK
IN
NAK
IN DATA1 ACK
IN DATA0 ACK
OUT DATA1 ACK
INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
EP0 FIFO access
Request access
Setup Received access
EOP register access
b) Stage error
SETUP DATA0 ACK
IN
NAK
IN DATA1 ACK
IN DATA0 ACK SETUP DATA0 ACK
INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
EP0 FIFO access
Request access
Setup Received access
EOP register access
Stage error bit
Normal
Stage error
Normal
STATUS register read
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(2) Register beginning value
Beginning Value
Beginning Value
OUTSIDE Reset USB_RESET
Beginning Value
Beginning Value
Register Name
Register Name
OUTSIDE Reset USB_RESET
bmRequestType
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x18
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Hold
Hold
Hold
INT control
0x00
0x00
0x01
0x00
0x1C
0x88
0x08
0x00
0x00
0x00
0x02
0x00
0x00
0x00
0x01
0x00
Hold
0x01
0x00
0x1C
0x88
0x08
0x00
0x00
0x00
0x02
0x00
Hold
Hold
0x00
bRequest
USBBUFF_TEST
USB state
wValue_L
wValue_H
EPx_MODE
EPx_STATUS
EPx_SIZE_L_A
EPx_SIZE _L_B
EPx_SIZE_H_A
EPx_SIZE_H_B
FRAME_L
wIndex_L
wIndex_H
wLength_L
wLength_H
Current_Config
Standard request
Request
FRAME_H
DATASET
ADRESS
Port Status
EPx_SINGLE
EPx_BCS
Standard request mode
Request mode
ID_STATE
Note 1:Above initial value is value that is initialized by external reset, USB_RESET. This value may differs display
value by various condition.
Please refer to register configure of chapter 2.
Note 2:Initial value of EPx_SIZE_L_A, EPx_SIZE_L_B, EPx_SIZE_H_A, EPx_SIZE_H_B registers differ by size of
FIFO.
EP0_STATUS register is initialized to 0x00 after received USB_RESET.
Note 3:Initial value of ID_STATE register is initialized by external reset, BRESET. When USB_RESET signal is
received from host, it isinitialized to 0x00.
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(3) USB control flow chart
(a) Transaction for standard request (Outline flowchart (Example))
USB interrupt
Call USBINT0 function
Judge Interrupt
SETUP
transaction
ENDPOINT 0
transaction
STATUS
transaction
STATUS NAK
transaction
ENDPOINT 1
transaction
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(b) Condition change
Turn on power supply
Initialization transaction
Normal finish/No transaction
Waiting USB
interrupt condition
Transmit Request
error/
Receive USB token
Transaction error/
Transmit STALL
Request
transaction
condition
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(c) Device request and various request judgment
Start
Get request data
Judge Request
Standard request
CLEAR_FEATURE
SET_FEATURE
Class request
* Error for not
support
Vendor request
Error transaction
* Error for not
support
GET_STATUS
SET_ADDRESS
SET_CONFIGURATION
GET_CONFIGURATION
SET_INTERFACE
GET_INTERFACE
SYNCH_FRAME
GET_DESCRIPTOR
End
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(c-1) CLEAR_FEATURE request transaction
Start
No
Is request right？
Yes
Judge Recipient
Device
Endpoint
Error transaction
Disable remote
wakeup setting
Clear stall setting
Finish transaction
End
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(c-2) SET_FEATURE request transaction
Start
No
Is request right?
Yes
Judge Recipient
Device
Endpoint
Error transaction
Enable remote
wakeup setting
Set stall
Finish transaction
End
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(c-3) GET_STATUS request transaction
Start
No
Is request right?
Yes
Judge Recipient
Device
Interface
Endpoint
Set stall information
Error transaction
Set self power
supply information
Set 0 x 0 0 data of
2 bytes
Finish transaction
End
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(c-4) SET_CONFIGRATION request transaction
Start
No
Is request right？
Yes
No
Is EP0 stall？
Yes
No
Is assignment
value valid？
Yes
No
Is state valid？
Yes
Set assignment
configuration value
Error transaction
Clear stall flag
Finish transaction
End
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(c-5) GET_CONFIGRATION request transaction
Start
No
Is request right?
Yes
No
Is state valid?
Yes
Set present configuraion
value
Error transaction
Finish transaction
End
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(c-6) SET_INTERFACE request transaction
Start
No
Is request right?
Yes
Is EP0 stall?
Yes
No
No
No
Is assignment
value valid?
Yes
Is state valid?
Yes
Set each endpoint to
assignmented configuration
value.
Error transaction
Finish transaction
End
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(c-7) SYNCH_FRAME request transaction
Start
No
Is request right?
Yes
Is EP0 stall?
Yes
No
No
No
Is assignment
value valid?
Yes
Is state valid?
Yes
Set altrenate setting value
to present transmitting data.
Error transaction
Finish transaction
End
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(c-8) SYNCH_FRAME request transaction
Start
No
Is request right?
Yes
Error transaction
Finish transaction
End
(c-9) SET_DESCRIPTOR request transaction
Start
No
Is request right?
Yes
Error transaction
Finish transaction
End
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(c-10) GET_DESCRIPTOR request transaction
Start
No
Is request right?
Yes
No
Is EP0 stall?
Yes
No
Is assignment
value valid?
Yes
No
Is state valid?
Yes
Config
String
Device
Error transaction
Set device
descriptor
information.
Set config
descriptor
information.
Set string
descriptor
information.
Write information to
FIFO[EP0_fifowrite ( )]
End
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(c-11) Data read transaction to FIFO by EP0
Start
No
Is request right?
Yes
Stage information = data stage
Read data from FIFO
STATUS_NAK interrupt disable
Stage information = stataus stage
Finish transaction
STATUS_NAK interrupt enable
Data read from FIFO
All data number
renew transfer address
End
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(c-12) Data write transaction to FIFO by EP0
Start
No
Is request right?
Set transmitting size to SIZE
register
Yes
Stage information = data stage
Write data to FIFO
STATUS_NAK interrupt enable
Set data size to SIZE register
No
Is data number decided
time of payload size?
Yes
STATUS_ NAK interrupt disable
Write data to FIFO
Stage information = status stage
All data number
renew former transfer address
Finish transaction
End
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(c-13) Beginning setting transaction of microcontroller
Start
Interrupt disable
Set Stack point
Set Various interrupt
Clear vRAM
UDC initialization[UDC_INIT]
USB farm initialization[USB_INIT]
Interrupt enable
Main transaction[main ( )]
(c-14) Begining setting transaction of UDC
Start
USBC reset transaction
End
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(c-15) Beginning transaction of USB farm changing number
Start
Renew stage information
Renew current information
Renew support information
Invalid EP except EP0
Various flag Intialization
End
(c-16) Set DEVICE_ID data to DEVICE_ID of UDC
Start
Set DEVICE_ID data to
DEVICE_ID_RAM area.
End
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(c-17) Descriptor data set transaction
Start
Set descriptor data to
DESC_RAM area.
End
(c-18) USB interrupt transaction
Start
Read INT register
Judge Interrupt
Setup interrupt
transaction
Endpoint 0 interrupt
Status_NAK interrupt
Status_interrupt
Others
[Proc_ ENDPOINT]
[Proc_STATUSNAKINT]
[Proc_STATUSINT]
Error
transaction
[Proc_SETUPINT]
Judge Request transaction
[STATUS_judge]
End
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(c-19) Dummy function for not using maskable interrupts.
Transaction performs nothing, therefore outline flow is skipping.
•
(c-20) Request judgment transaction. If transaction result is error, it puts STALL
command.
Start
No
Is request right?
Yes
Error transaction
End
(c-21) SETUP stage transaction
Start
No
Is request right?
Yes
Stage information = SETUP stage
Request transaction
End
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(c-22) Perform endpoint 0 transaction in except for SETUP stage.
Start
Judge Stage
Data stage
Status stage
Others
Error transaction
GET system request
[EP0_fifowrite]
Finish normally
SET system request
[EP0_fiforead]
End
(c-23) Status stage interrupt transaction
Start
No
Status stage?
Yes
Normal finish
transaction
Error transaction
End
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(c-24) STATUS_NAK interrupt transaction
Start
No
Data stage?
Yes
Normal finish
transaction
Error transaction
End
(c-25) This transaction is no transaction by USB transaction perform in
interrupts.
Start
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(c-26) Getting descriptor information (reration of standard request)
Start
Get device information
on descriptor
No
Is config within
support?
Yes
Get config information
on descriptor
No
Interface is within
support in config present.
Yes
Get device information on
descriptor
Increment count to next config
information
End
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3.16.11 Points to Note and Restrictions
1. Limitation of writing to COMMAND register in special timing
When “STALL” command is issued, ENDPOINT status might be shift to “INVALID”.
To avoid this problem, keep the below routine.
a. BULK (IN/OUT)
In case issue STALL command to endpoint in BULK transfer, be sure to issue
STALL command after stop RD/WR accessing to endpoint; that is UDC returns
NAK in the response of token from host. INT_EPxNAK should be used to detect
NAK transmit.
b. CONTROL OUT with data stage (software response)
If STALL needs to be set for endpoint 0 judging from request after receiving
INT_SETUP interrupt, access to SetupReceived register. After that, issue STALL
command after detecting INT_ENDPOINT0 interrupt.
c. CONTROL OUT without data stage (software response)
If STALL needs to be set for endpoint 0 judging from request after receiving
INT_SETUP interrupt, issue STALL command before access to eop register.
d. CONTROL IN(software response)
If STALL needs to be set for endpoint 0 judging from request after receiving
INT_SETUP interrupt, issue STALL command before set the first transmit data
to host.
2. Limitation of EPx_STATUS<STATUS2:0> when execute USB_RESET command
EPx_STATUS<STATUS2:0> may indicates different condition, if execute
USB_RESET command to the endpoint in the process of token. To avoid this
phenomenon, do not RESET the endpoint in transferring. (It is available in the process
of request that needs USB_RESET to that endpoint.)
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3. When generating toggle error of device controller
a. UDC operation
If USB host fail to receive ACK transmitted from UDC in OUT transfer, USB
host transmits the same data to UDC again. When the FIFO is available to receive,
UDC detects toggle error because of detecting the same data(having the same
toggle as the data which is received just before) and returns ACK. UDC rejects it
because the data have already received normally. While, if FIFO is not available,
UDC returns NAK and informs USB host that is unable to receive.
4. If using USB device controller in TMP92CZ26A, the crystal oscillator (USB standard ≤
10 MHz±2500ppm) is recommended. And in this case, the stage of external hub can be
used until max 3 stages by the precision of this USB device controller and the internal
clock. If USB compliance (USB logo) is needed, the 5 stages connection is needed for
external hub. And it is needed that input 48MHz clock from X1USB pin (USB standard
≤ ±2500ppm.)
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3.17 SPIC (SPI Controller)
SPIC is a Serial Peripheral Interface Controller that supports only master mode.
It can be connected to SD card, MMC (Multi Media Card) etc. in SPI mode.
The features are as follows;
1) 32 byte –FIFO (Transmit / Receive)
2) Generate CRC7 and CRC16 (Transmit / Receive data)
3) Baud Rate: 20Mbps max
4) Connect several SD cards and MMC. (Use other output port for /SPCS pin as /CS)
5) Use as general clock synchronous SIO.
MSB/LSB-first, 8/16bit data length, rising/falling edge
6) 2 Interrupts: INTSPITX (Trans interruption), INTSPIRX (receive interruption)
Select Read/Mask for interrupts: RFUL, TEMP, REND and TEND
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3.17.1 Block diagram
It shows block diagram and connection to SD card in Figure 3.17.1.
SD Card
SPIC (SPI Controller)
100KΩ
SPCLK
Baud rate
Generator
fSYS
SCLK
16bit
16bit
100KΩ
100KΩ
100KΩ
SPCS
SPDO
CS
DI
16bit
SPDI
16bit
16bit
DO
16bit
Port
INTSPI
WP (Write Protect)
CD (Card Detect)
INTn
Note1: SPCLK, SPCS , SPDO and SPDI pins are set to input port (Port PR3, PR2, PR1, PR0) by reset.
These signals are needed pull-up resister to fix voltage level, could you adjust resistance value for your final
set.
Note2: Please use general input port or interrupt signal for WP (Write Protect) and CD (Card Detect).
Figure 3.17.1 Block diagram and Connection example
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3.17.2 SFR
SFR of SPIC are as follows.These area connected to CPU with 16 bit data bus.
(1) SPIMD(SPI Mode setting register)
SPIMD register is for operation mode or clock etc.
SPIMD Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After Reset
SWRST
XEN
R/W
0
CLKSEL2 CLKSEL1 CLKSEL0
SPIMD
(820H)
W
0
R/W
1
0
0
Software SYSCK
Reset 0: disable
Select Baud Rate(Note1)
000:Reserved 100:f
Prohibit to
Read
/8
SYS
Modify
Write
001: f
010: f
011: f
/2
/3
/4
101: f
/16
0: don’t care 1: enable
1: Reset
SYS
SYS
SYS
SYS
SYS
SYS
Function
110: f
111: f
/64
/256
15
LOOPBACK
14
MSB1ST
13
DOSTAT
12
11
TCPOL
10
RCPOL
9
TDINV
8
RDINV
bit Symbol
Read/Write
After Reset
(821H)
R/W
1
R/W
0
1
0
0
0
0
LOOPBACK Start bit for SPDO pin
Synchronous Synchronous Invert data
Invert data
During
Test mode
0:disbale
1:enable
Transmit /
Receive
0:LSB
state
clock edge
during
clock edge
during
During
(no transmit)
0:fixed to ”0”
1:fixed to ”1”
transmitting receiving
Function
transmitting receiving
0: disable
1: enable
0: disable
1: enable
1:MSB
0: fall
0: fall
1: rise
1: rise
Note: Maximum speed of this SD card is 20Mbps in SD card SPI mode.
When setting the baud rates, select less than 20Mbps according to the operation speed of CPU (f
).
SYS
Figure 3.17.2 SPIMD register
(a) <LOOPBACK>
Because Internal SPDO can be input to internal SPDI, it can be used as test.
Set <XEN>=1 and <LOOPBACK>=1, outputs clock from SPCLK pin regardless of
operation of transmit/receive.
Please change the setting when transmitting/receiving is not in operation.
SPDO pin
SPDI pin
Transmitting data
Receiving data
B
A
Y
SPIMD<LOOPBACK>
Figure 3.17.3 <LOOPBACK> Function
(b) <MSB1ST>
Select the start bit of transmit/receive data
Please don't change the setting of this register when transmitting/receiving is in
operation.
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(c) <DOSTAT>
Set the status of SPDO pin when data communication is not operating (after
transmitting or during receiving).
Please don't change the setting of this register when transmitting/receiving is in
operation.
(d) <TCPOL>
Select the edge of synchronous clock.
Please change the setting when <XEN>bit is “0”. And set the same value as <RCPOL>.
SPCLK pin (<TCPOL> = “0”)
SPCLK pin (<TCPOL>= “1”)
SPDO pin
MSB
Bit7
LSB
Bit0
Bit3
Bit1 Bit2
Bit4
Figure 3.17.4 <TCPOL> Register Function
(e) <RCPOL>
Select the edge of synchronous clock during receiving.
Please change the setting during SPIMD<XEN>= “0”. And set the same value as
<TCPOL>.
SPCLK pin (<RCPOL>=”0”)
SPCLK pin (<RCPOL>=”1”)
LSB
Bit0
MSB
SPDI pin
Bit1
Bit4
Bit3
Bit2
Figure 3.17.5 <TCPOL>Register Function
(f) <TDINV>
Select logical invert/no invert when outputs transmitted data from SPDO pin.
Please don't change the setting of this register when transmitting/receiving is in
operation.
(g) <RDINV>
Select logical invert/no invert for received data from SPDI pin.
Please don't change the setting of this register when transmitting/receiving is in
operation.
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(h) <SWRST>
This bit is for Software reset of transmit/receive FIFO pointer. Write SPICT<TXE> to
“0” at <XEN>="1", and stop transmitting. After that, by writing <SWRST> to “1”, the
read/write pointer of transmit/receive FIFO are initialized.
When writing SPICT<TXE> to “0”, stops transmission after the UNIT data in
transmitting is transmitted. Write <SWRST> to“1”, the data in the transmit FIFO
becomes to invalid.
The data in the transmit shift register is cleared simultaneously. Therefore, the data is
not output if transmit is restarted after executed software reset.
Please do not write <SWRST> to “1” during transmission. In case of receiving, the
received data in the receive FIFO buffer becomes invalid. However, the UNIT data in
receiving is loaded to receive FIFO as valid data.
In case of sequential receive, receiving operates sequentially even if the data of receive
buffer becomes invalid. Therefore, stops receive operation by writing
SPICT<RXE>=“0”after finishing to receive all the data in receiving. And all the receive
operation is stopped by writing <SWRST>=“1”after checking no UNIT data in receiving
(namely after REND interrupt or the time to receive 1UNIT).
During receiving, do not write <SWRST>=“1”.
Software reset can be executed by 1 shot operation; writing <SWRST>=“1” (needless to
write <SWRST>=“0”). Writing <XEN>=“1”and <SWRST>=“1”simultaneously is permitted.
(i) <XEN>
Enable/disable control of root clock this SPI controller.
(j) <CLKSEL2:0>
Select baud rate. Baud rate is created from fSYS and settings are in under table.
Please change the setting when transmitting/receiving are not in operation.
Note: When setting the baud rates, select less than 20Mbps according to the operation speed of CPU (f
).
SYS
Table 3.17.1 Example of Baud Rate
Baud Rate [Mbps]
fSYS =60MHz
fSYS =80MHz
<CLKSEL2:0>
−
20
−
f
/2
/3
SYS
−
20
f
f
f
SYS
SYS
SYS
15
/4
7.5
10
/8
3.75
5
f
f
/16
/64
/256
SYS
SYS
0.9375
0.234375
1.25
0.3125
f
SYS
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(2) SPICT(SPI Control Register)
SPICT register is for data length or CRC etc.
SPICT Register
7
CEN
6
5
4
3
TXE
2
FDPXE
1
0
RXE
bit Symbol
Read/Write
After Reset
SPICT
(822H)
SPCS_B
UNIT16
TXMOD
R/W
0
RXMOD
R/W
R/W
R/W
R/W
R/W
0
1
0
0
0
0
0
Alignment in
Full duplex
/SPCS pin
Data length Transmit
Transmit
control
Receive
Mode
Receive
control
communication
control
0: output “0” 0: 8bit
1: output “1” 1: 16bit
mode
0: disable
1: enable
Function
0: disable
1: enable
0: UNIT
0: disable
0: UNIT
0: disable
1:Sequential 1: enable
1:Sequential 1: enable
15
CRC16_7_B
14
13
12
11
10
9
8
bit Symbol
Read/Write
After Reset
CRCRX_TX_B CRCRESET_B
(823H)
R/W
0
0
0
CRC select CRC data
CRC
0: Transmit calculate
0: CRC7
1: CRC16
1: receive
register
0:Reset
1:Release
Reset
Function
Figure 3.17.6 SPICT Register
(a) <CRC16_7_B>
Select CRC7 or CRC16 to calculate.
(b) <CRCRX_TX_B>
Select input data to CRC calculation circuit.
(c) <CRCRESET_B>
Initialize CRC calculate register.
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The process that calculating CRC16 of transmits data and sending CRC next to
transmit data is explained as follows.
(1) Set SPICT <CRC16_7_B> to select CRC7 or CRC16 and <CRCRX_TX_B> to select
calculating data.
(2) To reset SPICR register, write “1” after write<CRCRESET_B> to "0".
(3) Write transmit data to SPITD register, and wait for finish transmission all data.
(4) Read SPICR register, and obtain the result of CRC calculation.
(5) Transmit CRC which is obtained in (4) by the same way as (3).
CRC calculation of receive data is the same process.
Start
<CRC16_7_B>="1",
<CRCRX_TX_B>="0"
<CRCRESET_B>="0"→"1"
Transmit all data
Read CRC from SPICR
Write CRC in SPITD and send
Finish
Figure 3.17.7 Flow chart of CRC calculation process
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(d) <CEN>
Select enable/disable of the pin for SD card or MMC.
When the card isn’t inserted or no-power supply to DVcc, penetrated current is flowed
because SPDI pin becomes floating. In addition, current is flowed to the card
becauseSPCS , SPCLK and SPDO pin output “1”. This register can avoid these matters.
If write <CEN> to “0” with PRCR and PRFC selecting SPCS , SPCLK, SPDO and SPDI
signal, SPDI pin is prohibited to input (avoiding penetrated current) and SPCS , SPCLK,
SPDO pin become high impedance.
Please write <CEN>=“1” after card is inserted, supply power to Vcc of card and supply
clock to this circuit (SPIMD<XEN>=“1”).
(e) <SPCS_B>
Set the value that outputs to SPCS pin.
(f) <UNIT16>
Select the length of transmit/receive data. Data length is described as UNIT downward.
Please don't change the setting of this register when transmitting/receiving is in
operation.
(g) <FDPXE>
Select whether using alignment function for transmit/receive per UNIT during full
duplex.
Please don't change the setting of this register when transmitting/receiving is in
operation.
(h)<TXMOD>
Select UNIT/Sequential transmission. During transmission, it is prohibited to change
the transmission mode; Sequential→UNIT, UNIT → Sequential.
For UNIT transmit, the data in transmit FIFO is invalid. TEMP interrupt generates
when the data is shifted from transmit data register (SPITD) to transmit buffer.
For sequential transmit, 32 bytes of the data in FIFO is valid. TEMP interrupt
generates when the space of the FIFO becomes 16 bytes size and 32 bytes.
(i)<TXE>
Set enable/disable of transmit. Transmission starts when set to “1”after writing
transmit data to transmit FIFO or set to “1” before writing transmit data to transmit
FIFO. During transmission, it is possible to change enable/disable. If cleared to “0” during
transmission, transmission is stopped after finishing transmitting the UNIT data in
transmitting.
(j)<RXMOD>
Select UNIT/Sequential receives. During receiving, it is prohibited to change receiving
mode; Sequential→UNIT, UNIT → Sequential
In UNIT receive mode, receive FIFO is invalid and RFUL interrupt generates when the
received data is shifted from receive buffer to receive data register (SPIRD).
In sequential receive mode, receive FIFO is valid and RFUL interrupt generates when
16 and 32 bytes of the data is loaded to the FIFO.
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(k) <RXE>
In UNIT receive mode, receives only 1 UNIT data by writing “1”.
When reading receive data register (SPIRD) with the condition “1”, receives one time
additionally.
In sequential mode, receiving is kept sequentially until FIFO becomes full by writing
“1”. During receiving, it is possible to change enable/disable. If writing “0”during
receiving, receiving is stopped after finishing receiving the UNIT data in receiving.
[Transmit/Receive operation mode]
This SPI Controller supports 6 operations as below.
These are selected in <FDPXE>, <RXMOD>, <RXE>, <TXMOD>, <TXE> registers.
Table 3.17.2 Transmit/Receive operation mode
Operation mode
Register setting
Description
<FDPXE> <TXMOD> <TXE> <RXMOD> <RXE>
(1) UNIT transmit
0
0
0
0
1
0
1
x
x
0
1
1
x
x
1
x
x
0
1
0
x
x
1
1
1
Transmit written data per UNIT
(2) Sequential transmit
(3) UNIT receive
Transmit written data in FIFO sequentially
Receive only 1 UNIT of data
(4) Sequential receive
(5) UNIT transmit/receive
Receive automatically if buffer has space
Transmit/receive 1 UNIT of data with aligning
transmit/receive data per each UNIT
Transmit/receive sequentially with aligning
transmit/receive data per each UNIT
(6)Sequential transmit/receive
1
1
1
1
1
x: don’t care
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Difference points between UNIT transmission and Sequential transmission
UNIT transmit mode can be selected by writing SPICT<TXMOD>= “0”.
The transmit FIFO is invalid in UNIT transmit mode. The UNIT transmit starts when writing
UNIT data with the condition SPICT<TXE>= “1” or writing SPICT<TXE>= “1” after writing
1UNIT data in the transmit buffer. During transmission, it is prohibited to change the
transmission mode;
For UNIT transmit, TEMP interrupt generates when the data is shifted from transmit data
register (SPITD) to transmit buffer. TEND interrupt generates when the UNIT transmit is
finished.
Sequential transmit mode can be selected by writing SPICT<TXMOD>= “1”. 32bytes of the
FIFO becomes valid in sequential transmit mode. Writing data in transmit FIFO every 16
bytes is always needed. If writing other than 16 bytes, TEMP interrupt does not generate
normally.
The written transmit data is shifted by turn with the condition SPICT<TXE>= “1”. Or shifted
by turn when writing SPICT<TXE>= “1” after writing data in transmit FIFO.
The transmission is kept executing as long as data exists. Therefore the transmission can be
kept sequentially while the transmit FIFO (32 bytes size) has no space. During transmission,
it is prohibited to change;
Sequential transmit→UNIT transmit
UNIT transmit → Sequential transmit
During transmission, it is possible to change enable/disable. If writing SPICT<TXE>= “0”
during transmission, transmission is stopped after finishing to transmit the UNIT data in
transmitting.
TEMP interrupt generates when the space of FIFO becomes 16 and 32 bytes size. TEND
interrupt generates when the UNIT transmit is finished.
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Difference points between UNIT receive and Sequential receive
UNIT receive is the mode that receiving only 1 UNIT data. UNIT receive mode can be
selected by writing SPICT<RXMOD>= “0”.
The receive FIFO is invalid in the UNIT receive mode. By writing SPICT<RXE>= “1”,
receives 1UNIT data, loads received data in receive data register (SPIRD) and then stop
receiving. Reading (SPIRD) register should be executed after writing SPICT<RXE>= “0”. If
reading (SPIRD) register with the condition SPICT<RXE>= “1” 1 UNIT data is received again.
During receiving, it is prohibited to change;
Sequential receive→UNIT receive
UNIT receive → Sequential receive
RFUL and REND interrupts generate when UNIT receiving is finished.
Sequential receive is the mode that receiving the data sequentially and automatically when
receive FIFO has space. Sequential receive is selected by writing SPICT<RXMOD>= “1”.
The 32 bytes size of receive FIFO becomes valid in sequential receive mode. Reading the data
in receive FIFO every 16 bytes is always needed. If reading other than 16 bytes, RFUL
interrupt does not generate normally.
Received data is loaded to receive FIFO by writing SPICT<RXE>= “1”.
Receiving next data is kept automatically unless data receive FIFO becomes full (32bytes).
Therefore receiving is not stopped every UNIT but kept sequentially. During receiving, it is
prohibited to change receiving mode;
If writing SPICT<RXE>= “0” during receiving, receiving is stopped after finishing to receive
the UNIT data in receiving.
RFUL interrupt generates when 16 and 32 bytes of the data is loaded to the FIFO. REND
interrupt generates when receiving 32 bytes size of the data is finished.
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Transmit/Receive
When transmitting or receiving, write <FDPXE>= “1”
Writing <FDPXE>= “1” first, and SPICT<RXE>= “1” and keep waiting state for starting
UNIT receiving. When writing SPICT<RXE>= “1”after <ALGNEN>= “1”, receiving does not
start right away. This is because the data to transmit at the same time has not been prepared.
Transmit/receive start when writing the data to (SPITD) register with the condition <TXE>=
“1”.
The waveform of each transmit/receive operation is as follows;
Start
Start
receiving
transmitting
Transmitter
SPCLK output
SPDI input
LS
Bit1
Bit2
Bit4
Receiver
SPCLK output
SPDO output
LSB
Bit0
Bit1
Bit7
Bit5
Bit6
Bit2 Bit3
Bit4
Note: If transmit/receive are not operated simultaneously, please communicate with the condition <FDPXE>=”0”.
Figure 3.17.8 Transmit/Receive
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(3) Interrupt
In INTC (interrupt controller), interrupt is divided roughly into 2 kinds; transmit interrupt
(INTSPITX) and receive interrupt (INTSPIRX). Besides in this SPI circuit, there are 4 kinds of
interrupts; 2 transmit interrupts 2 receive interrupts.
・ Transmit interrupt
TEMP (Empty interrupt of transmit FIFO) and TEND (End interrupt of transmit).
As for TEMP interrupt, the timing of generation differs according to transmit mode;
UNIT/sequential.
If transmit is sequencial, writing the data to transmit FIFO every 16 bytes is always needed. If
writing other than 16 bytes, TEMP interrupt does not generate normally.
UNIT transmit mode
TEMP interrupt generates when the data is shift from transmit data register (SPITD) to
transmit buffer since transmit FIFO is invalid.
TEND interrupt generates when the last UNIT transmit is finished (the falling edge of the
last bit clock) with the FIFO empty.
Sequential transmit mode
TEMP interrupt generates from 2 phenomenon. One is when the space of FIFO becomes 16
bytes size and the other 32 bytes size.
TEND interrupt generates when the last UNIT transmit is finished (the falling edge of the
last bit clock) with the FIFO empty.
・ Receive interrupt
RFUL (Receive FIFO interrupt) and REND (Receive finish interrupt).
As for RFUL interrupt, the timing of generation differs according to receive mode;
UNIT/sequential.
If transmit is sequencial, reading the data from receive FIFO every 16 bytes is always needed.
If reading other than 16 bytes, RFUL interrupt does not generate normally.
UNIT receive
RFUL interrupt generates the same timing as REND since the receive FIFO becomes invalid.
RFUL and REND interrupt generate when the data is shifted from receive buffer to receive data
register (SPIRD).
Sequential receive
RFUL interrupt generates from 2 phenomenon. One is when 16 bytes size of data is loaded to
receive FIFO and the other 32 bytes size of data.
REND interrupt generates when the receive FIFO becomes full (32bytes).
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(3-1) SPIST (SPI Status Register)
SPIST shows 4 statuses.
SPIST Register
7
6
5
4
3
TEMP
2
1
TEND
0
REND
SPIST
(824H)
bit Symbol
Read/Write
After reset
R
1
R
1
0
Transmit FIFO
Status
Transmit
Receive
Status
Status
0: during
0: during
0: no space
1: having
space
transmission
receiving
Function
or having
or not having
receiving
transmission
data
1: finish
data
1: finish or not
having space
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
(825H)
Function
Figure 3.17.9 SPIST Register
(a) <TEMP>
For UNIT transmission, it is cleared to “0” when valid data exists in transmit register
(SPITD). It is set to “1” when no valid data exists.
For Sequential transmission, it is set to “1” when no valid data exists in transmit buffer.
(b) <TEND>
This bit is cleared to “0” when valid data to transmit exists in the shift register/FIFO buffer
or when transmission. It is set to “1” when no valid data exists in the transmit data
register/FIFO buffer and finish transmitting all the data.
(c) <REND>
For UNIT receiving, it is set to “1” when finish receiving and valid data was loaded to
receive data register (when valid data exists). It is cleared to “0” when no valid data exists
in receive register (SPIRD). It is set to “1” when no valid data exists or during receiving.
For Sequential receiving, it is set to “1” when valid data of 32 bytes exist in receive FIFO
after finish receiving last data. It is cleared to “0” even if having space of 1byte.
RFUL flag does not exist because meaning is the same with REND flag.
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(3-2) SPIIE(SPI Interrupt Enable Register)
SPIIE register is for enable 4 interrupts.
SPIIE Register
7
6
5
4
3
2
1
0
SPIIE
(82CH)
bit Symbol
Read/Write
After Reset
TEMPIE
RFULIE
TENDIE
RENDIE
R/W
0
0
0
0
TEMP
RFUL
TEND
REND
interrupt
0:enable
1:disable
interrupt
0:enable
1:disable
interrupt
0:enable
1:disable
interrupt
0:enable
1:disable
Function
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After Reset
(82DH)
Function
Figure 3.17.10 SPIIE Register
(a) <TEMPIE>
Set enable/disable of TEMP interrupt.
(b)<RFULIE>
Set enable/disable of RFUL interrupt.
(c)<TENDIE>
Set enable/disable of TEND interrupt.
(d)<RENDIE>
Set enable/disable of REND interrupt.
Note: As for 4 interrupts; 2 transmit interrupts (INTSPITX; TEMP, TEND) and 2 receive interrupts (INTSPIRX; RFUL,
REND), it should be selected one from TEMP and TEND, one from RFUL and REND when using
simultaneously. (Please do not select TEMP and TEND simultaneously. Or RFUL and REND simultaneously.)
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(4) SPICR (SPI CRC Register)
CRC result of Transmit/Receive data is set to SPICR register.
SPICR Register
7
6
5
4
3
2
1
0
SPICR
(826H)
bit Symbol
Read/Write
After Reset
CRCD7
CRCD6
CRCD5
CRCD4
CRCD3
CRCD2
CRCD1
CRCD0
R
0
0
0
0
0
0
0
0
CRC result register [7:0]
Function
15
CRCD15
14
CRCD14
13
CRCD13
12
CRCD12
11
CRCD11
10
CRCD10
9
8
bit Symbol
Read/Write
After Reset
CRCD9
CRCD8
(827H)
R
0
0
0
0
0
0
0
0
CRC result register [15:8]
Function
Figure 3.17.11 SPICR Register
(a) <CRCD15:0>
The result which is calculated according to the setting; SPICT<CRC16_7_b>,
<CRCRX_TX_B> and <CRCRESET_B>, are loaded to this register.
In case CRC16, all bits are valid.
In case CRC7, lower 7 bits are valid.
The flow will be showed to calculate CRC16 of received data for instance by flowchart.
Firstly, initialize CRC calculation register by writing <CRCRESET_B>= “1” after
setting <CRC16_7_b>= “1”, <CRCRX_TX_B>=”0”, <CRCRESET_B>= “0”.
Next, finish transmitting all bits to calculate CRC by writing data in SPITD register.
Please sense SPIST<TEND> to confirm whether receiving is finished.
If read SPICR register after finishing, CRC16 of received data can be read.
Note: CRC is generated in I/O point. Please take care soft ware process to compare the CRC when
used FIFO.
TMP92CZ26A
SPI slave
100KΩ
SPDO
SPDI
DI
16bit
16bit
100KΩ
DO
CRC generation point
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(5) SPITD (SPI Transmit Data Register)
SPITD0, SPITD1 registers are for writing transmitted data.
SPITD0 Register
7
TXD7
6
TXD6
5
TXD5
4
TXD4
3
TXD3
2
TXD2
1
TXD1
0
TXD0
bit Symbol
Read/Write
After reset
SPITD0
(830H)
R/W
0
0
0
0
0
0
0
0
Transmit data register [7:0]
Function
15
TXD15
14
TXD14
13
TXD13
12
TXD12
11
TXD11
10
TXD10
9
TXD9
8
TXD8
bit Symbol
Read/Write
After reset
(831H)
R/W
0
0
0
0
0
0
0
0
Transmit data register [15:8]
Function
SPITD1 Register
7
TXD7
6
TXD6
5
TXD5
4
TXD4
3
TXD3
2
TXD2
1
TXD1
0
TXD0
bit Symbol
Read/Write
After reset
SPITD1
(832H)
R/W
0
0
0
0
0
0
0
0
Transmit data register [7:0]
Function
15
TXD15
14
TXD14
13
TXD13
12
TXD12
11
TXD11
10
TXD10
9
TXD9
8
TXD8
bit Symbol
Read/Write
After reset
(833H)
R/W
0
0
0
0
0
0
0
0
Transmit data register [15:8]
Function
Figure 3.17.12 SPITD Register
This bit is for writing transmitted data. When read, the last written data is read. The data is
overwritten if write next data with transmit FIFO is not empty.
Transmit register exist 4bytes. Therefore, it is possible writing by using 4byte instruction
(use DMA together it etc.)
However, when write data (Destination address), writing the data from 830 addresses is
always needed.
Method of writing data (instruction) is restricted. Please refer to following table.
Transmit
data
Instruction
example
UNIT transmission
(No using FIFO)
Sequential transmission
(Using FIFO)
write size
1byte
2 byte
1 byte
2 byte
transmission
transmission
transmission transmission
<unit16>=0
<unit16>=1
<unit16>=0
<unit16>=1
○
×
×
×
○
×
×
○
○
1byte write
2byte write
4byte write
ld (0x830),a
Prohibit
○
ld (0x830),wa
ld (0x830),xwa
○
○: All data that written by CPU is transmitted
×: Invalid data that except for written by CPU is transmitted
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(6) SPIRD (SPI Receive Data Register)
SPIRD0, SPIRD1 registers are for reading received data.
SPIRD0 Register
7
RXD7
6
RXD6
5
RXD5
4
RXD4
3
RXD3
2
RXD2
1
RXD1
0
RXD0
SPIRD0
(834H)
bit Symbol
Read/Write
After reset
R
0
0
0
0
0
0
0
0
Function
Receive data register [7:0]
15
RXD15
14
RXD14
13
RXD13
12
RXD12
11
RXD11
10
RXD10
9
RXD9
8
RXD8
bit Symbol
Read/Write
After reset
Function
(835H)
R
0
0
0
0
0
0
0
0
Receive data register [15:8]
SPIRD1 Register
7
RXD7
6
RXD6
5
RXD5
4
RXD4
3
RXD3
2
RXD2
1
RXD1
0
RXD0
SPIRD1
(836H)
bit Symbol
Read/Write
After reset
Function
R
0
0
0
0
0
0
0
0
Receive data register [7:0]
15
RXD15
14
RXD14
13
RXD13
12
RXD12
11
RXD11
10
RXD10
9
RXD9
8
RXD8
bit Symbol
Read/Write
After reset
Function
(837H)
R
0
0
0
0
0
0
0
0
Receive data register [15:8]
Figure 3.17.13 SPIRD register
This bit is for reading received data. When read, read it after confirming status of RFUL or
REND. The data is overwritten if write next data with transmit FIFO is not empty.
Receive register exist 4bytes. Therefore, it is possible reading by using 4byte instruction (use
DMA together it etc.)
However, when read data basically, read the data from 834 addresses. (There is exception)
Method of reading data (instruction) is restricted. Please refer to following table.
Receive
data
Instruction
example
UNIT receiving
(No using FIFO)
Sequential receiving
(Using FIFO)
read size
1byte
2 byte
receiving
<unit16>=1
○
1 byte
receiving
<unit16>=0
2 byte
receiving
<unit16>=1
receiving
<unit16>=0
○
1byte read
ld a,(0x834)
ld a,(0x835)
ld wa,(0x834)
ld xwa,(0x834)
Prohibit
Prohibit
○
Prohibit
Prohibit
○
×
○
△*1
○
2 byte read
4 byte read
△*2
△*3
○
○
○: Read only valid data when CPU is reading.
△: Read valid data + invalid data when CPU is reading. Invalid data must be deleted after read.
×: Read only invalid data when CPU is reading.
*1: 834 address = valid data, 835 address = Invalid data,
*2: 834 address = valid data, 835 address = Invalid data, 836 address = Invalid data, 837 address = Invalid data
*3: 834 address = valid data, 835 address = valid data, 836 address = Invalid data, 837 address = Invalid data
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•
Note of FIFO buffer
There are following notes in this SPIC.
1) Transmit
・ Data is overwritten if write data with condition transmit FIFO buffer is FULL.
Interrupt and transmission are not executed normally because write-pointer in FIFO
becomes abnormal condition. Therefore, manage number of writing by using software.
・ If transmit is sequential, writing the data to transmit FIFO every 16 bytes is always
needed. If writing other than 16 bytes, TEMP interrupt does not generate normally.
Note: If transmitting it by except 16 byte, use UNIT transmitting.
2) Receive
・ If read data with condition receive FIFO is empty, undefined data is read. Interrupt
and receiving are not executed normally because read-pointer in FIFO becomes
abnormal condition. Therefore, manage number of reading by using software.
・ If receive is sequential, reading the data from receive FIFO every 16 bytes is always
needed. If reading other than 16 bytes, RFUL interrupt does not generate normally.
Note: If transmitting it by except 16 byte, use UNIT receiving.
3) CRC
CRC is generated in I/O point. Please take care soft ware process to compare the CRC when used FIFO.
Ex. Sequential receive
1. Start sequential receive
2. finish valid data receive (FIFO_Full)
3. disable receive
4. valid data read from FIFO to temporary buffer(internal RAM)
5. CRC1 read from CRC generator in SPI circuit
6. CRC2 receive (enable UNIT receive from SD-CARD)
7. compare CRC1 and CRC2
Note: Above 2 to 4 process can be used DMAC, however it must stop sequential receive (process 3)
before to get CRC2 form SD-CARD.
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TMP92CZ26A
3.18 I2S (Inter-IC Sound)
The TMP92CZ26A incorporates serial output circuitry that is compliant with the I2S format.
This function enables the TMP92CZ26A to be used for digital audio systems by connecting an
LSI for audio output such as a DA converter.
The I2S unit has the following features:
Table 3.18.1 I2S Operation Features
Item
Number of Channels
Format
Description
2 channels
I2S-format compliant
Right-justified and left-justified formats supported
Stereo / monaural
Master transmission only
Pins used
1. I2SnCKO (clock output)
2. I2SnDO (output)
3. I2SnWS (Word Select output)
WS frequency
Data transfer rate
Transmission buffer
Direction of data
Data length
Refer to “Setting the transfer clock generator and Word Select signal”.
64 bytes x 2
MSB-first or LSB-first selectable
8 bits or 16 bits
Clock edge
Rising edge or falling edge
INTI2Sn
Interrupt
(64-byte FIFO empty interrupt)
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3.18.1 Block Diagram
The I2S unit contains two channels: channel 0 and channel 1. Each channel can be controlled
and made to output independently.
Figure 3.18.1 shows a block diagram for I2S channel 0.
I2S0CTL
<CLKS0>
f
SYS
8-bit
I2SCKO
Control
I2S0CKO
I2S0WS
Counter
f
I2S
I2S0C
I2S0CTL
<CK07:00>
<EDGE0,TXE0,I2SCLKE0>
6-bit
I2SWS
Control
Counter
I2S0C
I2S0CTL
<DTFMT01:00,
WLVL0>
<WS05:00>
Clock Generator
INTI2S0
I2S0CTL
<DIR0>
0
1
31
0
1
31
Data Selector
Interrupt
32bit
64-byte FIFO0 64-byte FIFO1
(2 bytes×32)
(2 bytes×32)
Control
I2S0DO
FIFO Control
I2S0CTL
Write Pointer
Read Pointer
<DTFMT01:00>
<DIR0>
<BIT0>
Request Signal Output to ADC
(Supported in channel 0 only)
Figure 3.18.1 I2S Block Diagram
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3.18.2 SFRs
The I2S unit is provided with the following registers. These registers are connected to the
CPU via a 32-bit data bus. The transmission buffers I2S0BUF and I2S1BUF must be accessed
using 4-byte load instructions.
I2S0 Control Register
7
6
5
4
3
2
1
0
I2S0CTL
(1808H)
bit Symbol
Read/Write
After reset
TXE0
R/W
*CNTE0
R/W
DIR0
R/W
0
BIT0
R/W
0
DTFMT01 DTFMT00 SYSCKE0
R/W
0
R/W
0
R/W
0
0
0
Counter
control
0: Clear
1: Start
Bit length Output format
System
clock
Transmission
Transmissio
n start bit
0:MSB
00: I2S 10: Right
Function
0: Disable
1: Enable
0: Stop
1: Start
0: 8 bits
1: 16 bits 01: Left 11: Reserved
1:LSB
15
14
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
CLKS0
R/W
FSEL0
R/W
TEMP0
R
WLVL0
R/W
EDGE0
R/W
0
CLKE0
R/W
0
(1809H)
0
0
1
0
Source
clock
Stereo
/monaural
WS level
Data output Clock
clock edge operation
(after
Transmissio
n FIFO state
0: Low left
Function 0: f
1: f
0: Stereo
0: Data
1: High left 0: Falling
1: Rising
transmis-
sion)
SYS
1: Monaural 1: No data
PLL
0: Enable
1: Disable
I2S0 Divider Value Setting Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
CK07
R/W
0
CK06
R/W
0
CK05
R/W
0
CK04
R/W
0
CK03
R/W
0
CK02
R/W
0
CK01
R/W
0
CK00
R/W
0
I2S0C
(180AH)
Divider value for CK signal (8-bit counter)
15
14
13
12
11
10
9
8
Bit symbol
Read/Write
After reset
WS05
R/W
0
WS04
R/W
0
WS03
R/W
0
WS02
R/W
0
WS01
R/W
0
WS00
R/W
0
(180BH)
Function
Divider value for WS signal (6-bit counter)
I2S0 Buffer Register
10
15
14
13
12
11
9
8
7
6
5
4
3
2
1
0
I2S0BUF
(1800H)
bit Symbol
Read/Write
After reset
Function
B015
B014 B013 B012 B011 B010
B009 B008 B007 B006
B005 B004 B003 B002 B001 B000
W
Read-modify-
write
instructions
cannot be
used.
Undefined
Transmission buffer register (FIFO)
26 25 24 23 22 21
31
30
29
28
27
20
19
18
17
16
bit Symbol
Read/Write
After reset
Function
B031
B030
B09
B028 B027 B026
B025 B024 B023 B022
B021 B020 B019 B018 B017 B016
W
Undefined
Transmission buffer register (FIFO)
Figure 3.18.2 I2S Channel 0 Control Registers
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I2S1 Control Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
TXE1
R/W
*CNTE1
R/W
DIR1
R/W
0
BIT1
R/W
DTFMT11 DTFMT10 SYSCKE1
I2S1CTL
(1818H)
R/W
R/W
0
R/W
0
0
0
0
0
Counter
control
Bit length
Output format
System
clock
Transmission
Transmission
start bit
00: I2S
01: Left 11: Reserved
10: Right
0: Disable
1: Enable
Function
0: Stop
1: Start
0: MSB
1: LSB
0: 8 bits
1:16 bits
0: Clear
1: Start
14
15
13
12
11
10
9
8
bit Symbol
Read/Write
After reset
CLKS1
R/W
FSEL1
R/W
TEMP1
WLVL1
R/W
EDGE1
R/W
0
CLKE1
R/W
0
R
1
(1819H)
0
0
0
Source
clock
Stereo
/monaural
WS level
Data output Clock
Transmission
FIFO state
clock edge operation
0: Low left 0: Falling
1: High left 1: Rising
(after
Function 0: f
1: f
0: Stereo
0: Data
transmis-
sion)
SYS
1: Monaural 1: No data
PLL
0: Enable
1: Disable
I2S1 Divider Value Setting Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
CK17
R/W
0
CK16
R/W
0
CK15
R/W
0
CK14
R/W
0
CK13
R/W
0
CK12
R/W
0
CK11
R/W
0
CK10
R/W
0
I2S1C
(181AH)
Divider value for CK signal (8-bit counter)
15
14
13
12
11
10
9
8
(181BH)
Bit symbol
Read/Write
After reset
WS15
R/W
0
WS14
R/W
0
WS13
R/W
0
WS12
R/W
0
WS11
R/W
0
WS10
R/W
0
Function
Divider value for WS signal (6-bit counter)
I2S1 Buffer Register
10
15
14
13
12
11
9
8
7
6
5
4
3
2
1
0
I2S1BUF
(1810H)
bit Symbol
Read/Write
After reset
Function
B115
B114 B113 B112 B111 B110
B109 B108 B107 B106
B105 B104 B103 B102 B101 B100
W
Undefined
Read-modify-
write
instructions
cannot be
used.
Transmission buffer register (FIFO)
26 25 24 23 22 21
31
30
29
28
27
20
19
18
17
16
bit Symbol
Read/Write
After reset
Function
B131
B130 B129 B128 B127 B126
B125 B124 B123 B122
B121 B120 B119 B118 B117 B116
W
Undefined
Transmission buffer register (FIFO)
Figure 3.18.3 I2S Channel 1 Control Registers
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3.18.3 Description of Operation
(1) Settings the transfer clock generator and Word Select signal
In the I2S unit, the clock frequencies for the I2SnCKO and I2SnWS signals are
generated using the system clock (fSYS) as a source clock. The system clock is divided
by a prescaler and a dedicated clock generator to set the transfer clock and sampling
frequency.
The counters are started by setting I2SnCTL<CNTEn> to “1” and are stopped and
cleared by setting <CNTEn> to “0”.
A) Clock generator
・ 8-bit counter
This is an 8-bit counter that generates the I2SnCKO signal by dividing the clock
selected by I2SnCTL<CLKSn>.
・ 6-bit counter
This is a 6-bit counter that generates the I2SnWS signal by dividing the
I2SnCKO signal.
B) Word Select
・ Word Select signal (I2SnWS)
The I2SnWS signal is used to distinguish the position of valid data and whether
left data or right data is being transmitted in the I2S format. This signal is clocked
out in synchronization with the data transfer clock. In only channel 0, this signal
can be used as an AD conversion trigger signal for the ADC. How valid data is to
be output in relation to the WS signal can be specified as I2S format, left-justified,
or right-justified. In only channel 0, an interrupt request can be output to the ADC
on the rising edge of the WS signal. (This is controlled by the ADC’s control
register.)
(2) Data format
This circuit support I2S format, left justify and right justify format by setting
I2SnCTL<DTFMTn1:n0> register. And support stereo and monaural both, controlled
by I2SnCTL<FSELn> register.
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Left Data
Right Data
I2SnWS
I2SnCKO
I2S format
I2SnDO
Stereo
LSB
LSB
MSB
LSB
MSB
MSB
MSB
MSB
LSB
Valid data
Valid Data
Monaural
LSB
Valid Data
LSB
Left justify
I2SnDO
Stereo
MSB
MSB
MSB
MSB
MSB
LSB
Valid Data
Valid Data
LSB
Monaural
Valid Data
Right justify
I2SnDO
Stereo
LSB
MSB
MSB
MSB
LSB
LSB
LSB
Valid Data
Valid Data
Valid Data
Monaural
LSB
Figure 3.18.4 Output Format
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(2) Setting example for the clock generator (8-bit counter/6-bit counter)
The clock generator generates the reference clock for setting the data transfer speed
and sampling frequency.
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
CK07
R/W
0
CK06
R/W
0
CK05
R/W
0
CK04
R/W
0
CK03
R/W
0
CK02
R/W
0
CK01
R/W
0
CK00
R/W
0
I2S0C
(180AH)
Divider value for CK signal (8-bit counter)
15
14
13
12
11
10
9
8
Bit symbol
Read/Write
After reset
WS05
R/W
0
WS04
R/W
0
WS03
R/W
0
WS02
R/W
0
WS01
R/W
0
WS00
R/W
0
(180BH)
Function
Divider value for WS signal (6-bit counter)
• Setting the transfer clock I2SnCKO
The transfer clock is generated by dividing the clock selected by I2SnCTL
<CLKSn>. An 8-bit counter is provided to divide the source clock by 3 to 256. (The
divider value cannot be set to 1 or 2.)
Note: The transfer clock must not exceed 10 MHz. Make sure that the transfer clock is set to within 10
MHz by an appropriate combination of source clock frequency and divider value.
8-bit counter set value
00000000
Divider value
256
1
00000001
11111111
255
When fSYS = 60 MHz and I2SnC<CKn7:0> = 150, the data transfer speed is set as follows:
I2SnCKO = fSYS/150
= 60 [MHz]/150 = 400 [kbps]
Note: It is recommended that the value to be set in I2SnC<CKn7:0> be an even number. Although it is possible to
set an odd number, the clock duty of the CK signal does not become 50%. Setting an odd number causes
the High width of the I2SnCK0 signal to become longer by one fsys or fPLL pulse than the Low width. (When
<EDGE> = 0, the Low width becomes longer than the High width.)
• Setting the sampling frequency WS
The sampling frequency is set by dividing the transfer clock (CK) described above.
A 6-bit counter is provided to divide the transfer clock by 16 to 64. (The divider
value cannot be set to 1 to 15.)
6-bit counter set value
000000
Divider value
64
1
000001
111111
63
When fSYS = 60 MHz, I2SnC<CKn7:0> = 150, and I2SnC<WSn5:0> = 50, the sampling frequency is set as
follows:
I2SnCKO = fSYS / 150 / 50
= 60 [MHz] / 150 / 50 = 8 [kHz]
Based on the above, the transfer clock is set to 400 kbps, and the sampling frequency is set to 8 kHz in this
example.
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Note 1: The value to be set in I2SnC<WSn5:0> must be 16 or larger (18 or larger for I2S transfer) when the data
length is 8 bits and 32 or larger (34 or larger for I2S transfer) when the data length is 16 bits.
Note 2: It is recommended that the value to be set in I2SnC<WSn5:0> be an even number. Although it is
possible to set an odd number, the clock duty of the WS signal does not become 50%. Setting an odd
number causes the High width of the WS signal to become longer by one I2SnCK0 pulse than the Low
width.
• Special function
As a special function available only in channel 0, the rising edge of the WS signal
can be used as an AD conversion start trigger for the AD converter in this LSI.
Setting I2S0CTL<SYSKE0>=1 and I2S0CTL<CNTE0>=1 enables the WS signal to
be sent to the AD converter. This can be done regardless of the setting of
I2S0CTL<TXE0>.
For details about AD conversion using the WS signal, refer to the chapter on the
AD converter.
(3) FIFO buffer and data format
The I2S unit is provided with a 128-byte FIFO buffer (32-bit wide x 32-entry). The data
written to the 4 bytes (32 bits) of the I2SnBUF register is written to this FIFO buffer. This
FIFO must be written in units of 4 bytes. It is also necessary to consider the output order
and to distinguish between right data and left data.
To write data to the I2SnBUF register, be sure to use a 4-byte load instruction. If a
1-byte load instruction is used, invalid data will be transmitted. In case of using 1-byte or
2-byte transmission instruction, FIFO buffer isn't renewed and transmission isn't started.
And window addresses are 1800H (channel 0) and 1810H (channel1).
Write Data Size
Example instruction
8-bit width
16-bit width
1-byte access
ld (0x1800),a
Not allowed
Not allowed
OK
Not allowed
Not allowed
OK
2-byte access
4-byte access
ld (0x1800),wa
ld (0x1800),xwa
Also note that data must be written in units of 64 bytes using the following sequence:
4-byte load instruction × 16 times = 64-byte data write
If data is not written in units of 64 bytes, interrupts cannot be generated at the normal
timing.
The I2SnCTL<TEMPn> flag is set to “1” when the FIFO buffer for each channel contains
no valid data. If there is even one byte of valid data in the FIFO, the flag is cleared to “0”.
(The <TEMPn> flag is set to “1” as soon as the last valid data in the FIFO is sent to the
transmission shift register.)
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The following shows how written data is output under various conditions.
When I2SnCTL<WLVLn> = 0
I2SnBUF register
Output order
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MSB-first 16 bits
2’nd Data
4’th Data
2’nd Data
3’rd Data
LSB-first 16 bits
MSB-first 8 bits
LSB-first 8 bits
3’rd Data
4’th Data
9
15
14
13
12
11
10
8
7
6
5
4
3
2
1
0
MSB-first 16 bits
LSB-first 16 bits
1’st Data
2’nd Data
1’st Data
1’st Data
MSB-first 8 bits
LSB-first 8 bits
1’st Data
2’nd Data
When I2SnCTL<WLVLn> = 1
I2SnBUF register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Output order
1’st Data
3’rd Data
MSB-first 16 bits
LSB-first 16 bits
1’st Data
4’th Data
MSB-first 8 bits
LSB-first 8 bits
4’th Data
3’rd Data
9
15
14
13
12
11
10
8
7
6
5
4
3
2
1
0
MSB-first 16 bits
LSB-first 16 bits
2’nd Data
2’nd Data
2’nd Data
MSB-first 8 bits
LSB-first 8 bits
1’st Data
2’nd Data
1’st Data
Note: In case of using monaural setting, and change right / left: I2SnCTL<WLVLn>, data output order change
off 1'st data and 2'nd data.
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3.18.4 Detailed Description of Operation
(1) Connection example
Figure 3.18.5 shows an example of connections between the TMP92CZ26A and an
external LSI (DA converter) using channel 0.
TMP92CZ26A
(Transmit)
(Receive)
PF2/I2S0WS
PF0/I2SCKO
WS
CK
PF1/I2SDO
DATA
Example: DA converter
Note:
After reset, PF0 to PF2 are placed in a high-impedance state. Connect each pin with a pull-up or pull-down resistor
as necessary.
Figure 3.18.5 Connection Example between the TMP92CZ26A and an External LSI
(2) Operation procedure
The I2S unit incorporates a 128-byte FIFO buffer that is divided into two 64-byte units.
Whenever each 64-byte buffer space becomes empty, an INTI2Sn interrupt is generated.
The next data to be transmitted should be written to the FIFO in the interrupt routine.
Example settings and timing diagram are shown below.
(Example settings) I2S0WS = 8 KHz, I2SnCKO = 400 kHz, data transmission on the rising edge (at f
(Main routine)
= 50 MHz)
SYS
7
X
X
−
1
X
0
0
*
6
−
X
X
0
X
0
X
*
5
−
−
−
0
1
X
X
*
4
−
−
−
1
1
0
X
*
3
X
−
−
0
0
1
X
*
2
0
−
1
1
0
0
0
*
*
*
*
0
0
1
0
−
1
1
1
0
0
*
*
*
*
0
0
0
1
−
1
0
0
1
0
*
*
*
*
1
0
INTEI2S01
PFCR
Set interrupt level.
Set pins: PF0 (I2S0CKO), PF1 (I2S0DO), PF2 (I2S0WS)
PFFC
I2S0SC
Divider value N=150
Divider value K=50
I2S0CTL
I2S0BUF
Set transmit mode (I2S mode, MSB-first, 16-bit).
Falling edge, WS=0 Left, clock stop.
Write left and right data to FIFO (4 bytes x 32 = 128 bytes).
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
I2S0CTL
1
0
0
X
X
X
0
X
1
X
Start transmission.
(INTI2S Interrupt Routine)
I2S0BUF
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Write left and right data to FIFO (4 bytes x 16 = 64 bytes).
X: Don't care, −: No change
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FIFO write
<TXE>
1
2
3
4
31
32
33
I2SnWS pin
I2SnCKO pin
I2SnDO pin
INTI2Sn
Overall Timing Diagram
I2SnWS pin
400kHz
MSB
I2SnCKO pin
I2SnDO pin
LSB
Bit0
MSB
Bit15 Bit14
LSB
LSB
Bit0
MSB
Bit15
Bit15 Bit14
Detailed Timing Diagram
Figure 3.18.6 Timing Diagrams (I2S FMT/Stereo/16bit/MSB first)
(3) Considerations for using the I2S unit
1) INTI2Sn generation timing
Every 4bytes data trance from FIFO buffer to shift register per one time.
An INTI2Sn interrupt is generated under two conditions. One is when there are 64
bytes of empty space in the FIFO (after 61- 64th byte has been transferred to the shift
register). The other is when the FIFO becomes completely empty (after 125 - 128th
byte has been transferred to the shift register). Therefore, INTI2Sn indicates that
there are 64 bytes or 128 bytes of empty space in the FIFO, enabling the next data to
be written.
The FIFO must be written in units of 64 bytes. Since the FIFO can contain 128 bytes
of data, I2S output can be performed continuously as long as there are 64 bytes of data
in the FIFO. It is also possible to check the FIFO state by using the
I2SnCTL<TEMPn> flag.
2) I2SnCTL<TXEn>
Transmission is started by setting I2SnCTL <TXEn> to “1”. Once <TXEn> is set to
“1”, transmission is continued automatically as long as the FIFO contains the data to
be transmitted. While <TXE> is set to “1” (transmission in progress), the other bits in
the I2SnCTL register must not be changed.
To stop transmission, make sure that the FIFO is empty by checking the
I2SnCTL<TEMPn> flag. Then, after waiting for two periods of the I2SWS signal (after
all the data has been transmitted), set <TXEn> to “0”. In case monaural setting, make
sure that the FIFO is empty by checking the I2SnCTL<TEMPn> flag. Then, after
waiting for four periods of the I2SWS signal (after all the data has been transmitted),
set <TXEn> to “0”.
If <TXEn> is set to “0” while data is being transmitted, the transmission is stopped
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immediately. At the same time, the read and write pointers of the FIFO, the data in
the output shift register and the clock generator are all cleared. (However, when
I2SnCTL<CNTEn>=1, the clock generator is not cleared. To clear the clock generator,
I2SnCTL<CNTEn> must be set to “0”). Therefore, if transmission is stopped and then
resumed, no data will be output.
The WS signal stops at Low level and the CK signal stops at Low level when the
rising edge is selected and at High level when the falling edge is selected.
3) I2SnCTL<CNTEn>
I2SnCTL<CNTEn> is used to control the clock generator (8-bit counter, 6-bit
counter) for generating the I2SnCKO and I2SnWSOsignals.
Setting I2SnCTL<CNTEn> to “1” starts the counters, and setting this bit to “0”
stops the counters. Normally, I2S data transmission is executed by setting both
I2SnCTL<TXEn> and <CNTEn> to “1”. When transmission is stopped by setting
I2SnCTL<TXEn> to “0” with I2SnCTL<CNTEn>=1, the clock generator is not cleared.
To clear the clock generator, I2SnCTL<CNTEn> must be set to “0”.
4) FIFO buffer
The I2S unit is provided with a 128-byte FIFO. Although it is not necessary to use all
128 bytes in the FIFO, data should basically be written in units of 64 bytes using an
INTI2Sn interrupt as a trigger. If data is written to the FIFO without waiting for an
INTI2Sn interrupt or in units other than 64 bytes, interrupts cannot be generated
properly.
If the last set of data, for which an interrupt is not needed, contains less than 64
bytes, set I2SnCTL<TXEn> to “0” to stop the transmission after writing the data, then
checking that the <TEMPn> flag is set to “1”, and waiting for two I2SWS periods (i.e.,
after all the data has been transmitted). In case monaural setting, make sure that the
FIFO is empty by checking the I2SnCTL<TEMPn> flag. Then, after waiting for four
periods of the I2SWS signal (after all the data has been transmitted), set <TXEn> to
“0”.
5) I2SnBUF
When writing data to the I2SnBUF register, be sure to use long-word data load
instructions. Word data load or byte data load instructions cannot be used.
Examples)
ld
ld
ld
(I2SnBUF), xwa;
(I2SnBUF), wa;
(I2SnBUF), a;
OK
NG
NG
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3.19 LCD Controller (LCDC)
The TMP92CZ26A incorporates an LCD controller (LCDC) for controlling an LCD driver
LSI (LCD module). This LCDC supports display sizes from 64 × 64 to 640 × 480 dots for
monochrome, grayscale, and 4096-color display and from 64 × 64 to 320 × 320 dots for color
display using 65536 or more colors. The supported LCD driver (LCD module) types are
STN (Super Twisted Nematic) and digital RGB input TFT (Thin Film Transistor).
•
STN support
With LCD drivers supporting STN, an 8-bit data interface is used to realize monochrome,
4-graysale, 16-grayscale, 64-grayscale, 256-color, 4096-color display.
After required settings such as the operation mode, display RAM start address, and LCD
size (common, segment) are made in the I/O registers, the start register is set to enable the
LCDC. The LCDC outputs a bus request to the CPU, reads data from the display RAM,
converts the data as necessary, and writes it to a dedicated FIFO buffer.
•
TFT support
With LCD drivers supporting digital RGB input TFT, an 8- to 24-bit data interface is
used to realize 4096-color, 65536-color, 262144-color, and 16777216-color display. The data
transfer method is the same as in the case of STN.
The LCDC controls LCD display operations using 8-bit RGB (R3:G3:B2), 12-bit RGB
(R4:G4:B4), 16-bit RGB (R5:G6:B5), 18-bit RGB (R6:G6:B6), or 24-bit RGB (R8:G8:B8)
display data, the shift clock LCP0 for capturing data, the frame signal LFR, the data load
signal LLOAD, and the LDIV signal for indicating the inversion of data output. The LDIV
signal can be used effectively in reducing noise and power consumption.
The LCDC also has horizontal synchronization signal LHSYNC and vertical
synchronization signal LVSYNC for controlling gate drivers, and three programmable OE
pins for supporting various signals of the TFT driver to be used.
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TMP92CZ26A
3.19.1 LCDC Features according to LCD Driver Type
Table 3.19.1 LCDC Features according to LCD Driver Type
(This table assumes the connection with a TOSHIBA-made LCD driver.)
Shift Register Type
LCD Driver
TFT
STN
Monochrome, 4/16/64 grayscale levels
256/4096 colors
Display colors
256/4096/65536/262144/16777216 colors
For 65536 colors or less
Rows (Commons):
64, 96, 128, 160, 200, 240, 320, 480
Columns (Segments):
Rows (Commons):
64, 96, 120, 128, 160, 200, 240, 320, 480
Columns (Segments):
64, 120, 128, 160, 240, 320, 480, 640
64, 128, 160, 240, 320, 640
Number of pixels that can be
displayed
For 65536 colors or more
Rows (Commons):
64, 96, 128, 160, 200, 240, 320, 480
Columns (Segments):
–
64, 128, 160, 240, 320
Horizontal flip, vertical flip, horizontal and vertical flip, 90-degree rotation
(supported for QVGA size, 65536 colors only)
A sub window can be inserted.
Data rotation function
PIP function support
Source data bus width
(SRAM, SDRAM)
Destination data bus width
(LCD driver)
16 bits (32 bits: internal RAM)
16 bits (32 bits: internal RAM)
8 bits
8 to 24 bits
Maximum transfer rate
(VRAM read)
4.17 ns/byte at internal RAM
(at fSYS = 80 MHz)
To be connected to LCD driver data bus.
・ 8-bit mode: LD7 to LD0
・TFT mode: LD23 to LD0
LCD driver data bus:
LD23 to LD0 pins
Data shift clock for TFT source driver
Shift clock pulse output pin 0. To be connected to
column driver’s CP pin. The LCD driver latches the
data bus value on the falling edge of this pin.
Latch pulse output pin. To be connected to the LCD
driver’s LP pin. The display data in the LCD driver’s
output line register is updated on the rising edge of
this pin.
LCP0 pin
Vertical shift clock for TFT gate driver
LHSYNC pin
LLOAD pin
Enable signal for TFT source driver to load data
to TFT panel
N/A
N/A
LGOE0 to LGOE2
pins
Adjustment signal for TFT gate driver’s gate
control signal
LCD alternate signal output pin. To be connected
to column/row driver’s FR pin.
LCD alternate signal output pin. To be connected to
column/row driver’s FR pin.
LFR pin
This signal indicates the start of shift clock
capture by TFT gate driver.
LVSYNC pin
Frequency that sets LCD refresh rate
This signal indicates the inversion of data. To be
connected to TFT source driver having the data
inversion function.
LDIV pin
N/A
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3.19.2 SFRs
LCDMODE0 Register
7
6
5
4
3
2
1
0
bit Symbol
SCPW1
R/W
1
SCPW0
R/W
1
MODE3
R/W
0
MODE2
R/W
0
MODE1
R/W
0
MODE0
R/W
0
RAMTYPE1 RAMTYPE0
LCDMODE0
(0280H)
Read/Write
After reset
R/W
R/W
0
0
Display RAM
LD bus transfer speed
SCPW2= 0
00: 2-clk
Mode selection
0000: Reserved
0001: SR (mono)
0010: SR (4-gray)
0011: Reserved
0100: SR (16-gray)
1000: Reserved
1001: Reserved
00: Internal RAM
01: External SRAM
10: SDRAM
01: 4-clk
1010: TFT (256-color)
1011: TFT (4096-color)
1100: TFT (64K-color)
10: 8-clk
11: 16-clk
Function
SCPW2= 1
00: 6-clk
11: Reserved
0101: SR (64-gray) 1101:TFT(256K-,16M-color)
0110: STN (256-color) 1110 : Reserved
0111:STN (4096-color)1111: Reserved
01: 12-clk
10: 24-clk
11: 48-clk
Note: When SDRAM is used as the LCDC’s display RAM, it can only be accessed by “burst 1-clock access”.
LCDMODE1 Register
7
LDC2
R/W
0
6
LDC1
R/W
0
5
LDC0
R/W
0
4
LDINV
R/W
0
3
2
1
0
bit Symbol
Read/Write
After reset
AUTOINV INTMODE FREDGE
SCPW2
LCDMODE1
(0281H)
R/W
0
R/W
0
W
0
W
0
Data rotation function
LD bus
inversion
Auto bus
inversion
0: Disable
Interrupt
selection
LFR edge LD bus
Trance
(Supported for 64K-color: 16bps
only)
0: LHSYNC Speed
Front Edge
000: Normal
100: 90-degree 0: Normal 1: Enable
0:LLOAD
Function
001: Horizontal flip 101: Reserved 1: Invert
010: Vertical flip 110: Reserved
011: Horizontal & vertical flip
111: Reserved
(Valid only 1:LVSYNC 1:LHSYNC 0: normal
for TFT) Rear Edge 1: 1/3
Note: <LDINV>=1 inverts all output data on the LD bus. However, the LDIV signal that indicates the inversion of
output data by auto bus inversion remains unchanged.
LCD Size Setting Register
7
COM3
R/W
0
6
COM2
R/W
0
5
COM1
R/W
0
4
COM0
R/W
0
3
SEG3
R/W
0
2
SEG2
R/W
0
1
SEG1
R/W
0
0
SEG0
R/W
0
bit Symbol
Read/Write
After reset
LCDSIZE
(0284H)
Common setting
0000: Reserved
0001: 64
Segment setting
0000: Reserved
0001: 64
1000: 320
1000: Reserved
1001: Reserved
1010: Reserved
1011: Reserved
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved
1001: 480
0010: 96
1010: Reserved
1011: Reserved
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved
0010: 128
Function
0011: 120
0011: 160
0100: 128
0100: 240
0101: 160
0101: 320
0110: 200
0110: 480
0111: 240
0111: 640
Note: Although the TMP92CZ26A contains 288 Kbytes of RAM that can be used as display RAM, it may not be
enough depending on display size and color mode.
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LCD Control 0 Register
7
PIPE
R/W
0
6
5
FRMON
R/W
0
4
–
3
2
DLS
1
0
bit Symbol
Read/Write
After reset
ALL0
R/W
LCP0OC
START
R/W
0
LCDCTL0
(0285H)
R/W
0
R/W
R/W
0
0
0
PIP
Segment
data
FR divide Always
FR signal
LCP0(Note LCDC
function
setting
write “0”
LCP0/Line 0: Always operation
selection
output
0:Disable
1:Enable
0: Normal
1: Always
output “0”
0: Disable
1: Enable
1: At valid 0: Stop
0:Line
data only
LLOAD
1: Start
Function
1:LCP0
width
0: At setting
in register
1: At valid
data only
Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of <LCP0OC> bit.
LCD Control 1 Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
LCP0P
R/W
LHSP
R/W
LVSP
R/W
LLDP
R/W
LVSW1
R/W
LVSW0
R/W
LCDCTL1
(0286H)
After reset
1
0
LHSYNC
phase
1
LVSYNC
phase
0
0
0
LCP0
LLOAD
LVSYNC
phase
phase
enable time control
00: 1 clock of LHSYNC
01: 2 clocks of LHSYNC
10: 3 clocks of LHSYNC
11: Reserved
Function
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
1: Falling
LCD Control 2 Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
LGOE2P
R/W
LGOE1P
R/W
LGOE0P
R/W
LCDCTL2
(0287H)
0
0
0
LGOE2
phase
LGOE1
phase
LGOE0
phase
Function
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
1: Falling
Divide FRM 0 Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
FMP3
FMP2
FMP1
FMP0
FML3
FML2
FML1
FML0
LCDDVM0
(0283H)
R/W
0
0
0
0
0
0
0
0
LCP0 DVM (bits 3-0)
LHSYNC DVM (bits 3-0)
Divide FRM 1 Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
FMP7
FMP6
FMP5
FMP4
FML7
FML6
FML5
FML4
LCDDVM1
(0288H)
R/W
0
0
0
0
0
0
0
0
LCP0 DVM (bits 7-4)
LHSYNC DVM (bit 7-4)
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LCD LHSYNC Pulse Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
LH7
LH6
LH5
LH4
LH3
LH2
LH1
LH0
LCDHSP
(028AH)
W
0
0
0
0
0
0
0
0
LHSYNC period (bits 7–0)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
LH15
LH14
LH13
LH12
LH11
LH10
LH9
LH8
(028BH)
W
0
0
0
0
0
0
0
0
LHSYNC period (bits 15-8)
LCD V SYNC Pulse Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
LVP7
LVP6
LVP5
LVP4
LVP3
LVP2
LVP1
LVP0
LCDVSP
(028CH)
W
0
0
0
0
0
0
0
0
LVSYNC period (bits 7-0)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
LVP9
LVP8
(028DH)
W
0
0
LVSYNC period
(bits 9-8)
Function
LCD LVSYNC Pre Pulse Register
7
6
PLV6
5
PLV5
4
PLV4
3
PLV3
W
2
PLV2
1
PLV1
0
PLV0
bit Symbol
Read/Write
After reset
Function
LCDPRVSP
(028EH)
0
0
0
0
0
0
0
Front dummy LVSYNC (bits 6-0)
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7
7
6
HSD6
5
HSD5
4
HSD4
3
HSD3
2
HSD2
1
HSD1
0
HSD0
bit Symbol
Read/Write
After reset
Function
LCDHSDLY
(028FH)
W
0
0
0
0
0
0
0
LHSYNC delay (bits 6-0)
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PDT
R/W
0
LDD6
LDD5
LDD4
LDD3
LDD2
LDD1
LDD0
LCDLDDLY
(0290H)
W
0
0
0
0
0
0
0
LLOAD delay (bits 6-0)
Data output
timing
0: Sync with
LLOAD
Function
1: 1 clock later
than LLOAD
7
7
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
OE0D6
OE0D5
OE0D4
OE0D3
OE0D2
OE0D1
OE0D0
LCDO0DLY
(0291H)
W
0
0
0
0
0
0
0
OE0 delay (bits 6-0)
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
OE1D6
OE1D5
OE1D4
OE1D3
OE1D2
OE1D1
OE1D0
LCDO1DLY
(0292H)
W
0
0
0
0
0
0
0
OE1 delay (bits 6-0)
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
OE2D6
OE2D5
OE2D4
OE2D3
OE2D2
OE2D1
OE2D0
LCDO2DLY
(0293H)
W
0
0
0
0
0
0
0
OE2 delay (bits 6-0)
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7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
HSW7
HSW6
HSW5
HSW4
HSW3
HSW2
HSW1
HSW0
LCDHSW
(0294H)
W
0
0
0
0
0
0
0
0
LHSYNC width (bits 7-0)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
LDW7
LDW6
LDW5
LDW4
LDW3
LDW2
LDW1
LDW0
LCDLDW
(0295H)
W
0
0
0
0
0
0
0
0
LLOAD width (bits 7-0)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
O0W7
O0W6
O0W5
O0W4
O0W3
O0W2
O0W1
O0W0
LCDHO0W
(0296H)
W
0
0
0
0
0
0
0
0
LGOE0 width (bits 7-0)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
O1W7
O1W6
O1W5
O1W4
O1W3
O1W2
O1W1
O1W0
LCDHO1W
(0297H)
W
0
0
0
0
0
0
0
0
LGOE1 width (bits 7-0)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
O2W7
O2W6
O2W5
O2W4
O2W3
O2W2
O2W1
O2W0
LCDHO2W
(0298H)
W
0
0
0
0
0
0
0
0
LGOE2 width (bits 7-0)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
O2W9
O2W8
O1W9
O1W8
O0W8
LDW9
LDW8
HSW8
LCDHWB8
(0299H)
W
0
0
0
0
0
0
0
0
LGOE2 width (bits 9-8) LGOE1 width (bits 9-8)
LGOE0
LLOAD width (bits 9-8)
LHSYNC
width (bit 8)
Function
width (bit 8)
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LCD Main Area Start Address Register
7
LMSA7
R/W
0
6
LMSA6
R/W
0
5
LMSA5
R/W
0
4
LMSA4
R/W
0
3
LMSA3
R/W
0
2
LMSA2
R/W
0
1
LMSA1
R/W
0
0
bit Symbol
Read/Write
After reset
LSAML
(02A0H)
Function
LCD main area start address (A7-A1)
7
LMSA15
R/W
0
6
LMSA14
R/W
0
5
LMSA13
R/W
0
4
LMSA12
R/W
0
3
LMSA11
R/W
0
2
LMSA10
R/W
0
1
LMSA9
R/W
0
0
LMSA8
R/W
0
bit Symbol
Read/Write
After reset
LSAMM
(02A1H)
Function
LCD main area start address (A15-A8)
7
LMSA23
R/W
0
6
LMSA22
R/W
1
5
LMSA21
R/W
0
4
LMSA20
R/W
0
3
LMSA19
R/W
0
2
LMSA18
R/W
0
1
LMSA17
R/W
0
0
LMSA16
R/W
0
bit Symbol
Read/Write
After reset
LSAMH
(02A2H)
Function
LCD main area start address (A23-A16)
Note: When assigned internal RAM as VRAM, A1 signal cannot be used. Every 4bytes setting is needed.
LCD Sub Area Start Address Register
7
6
5
4
3
2
1
0
LSSA7
LSSA6
LSSA5
LSSA4
LSSA3
LSSA2
LSSA1
bit Symbol
Read/Write
After reset
LSASL
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
(02A4H)
Function
LCD sub area start address (A7-A1)
7
LSSA15
R/W
0
6
LSSA14
R/W
0
5
LSSA13
R/W
0
4
LSSA12
R/W
0
3
LSSA11
R/W
0
2
LSSA10
R/W
0
1
LSSA9
R/W
0
0
LSSA8
R/W
0
bit Symbol
Read/Write
After reset
LSASM
(02A5H)
Function
LCD sub area start address (A15-A8)
7
LSSA23
R/W
0
6
LSSA22
R/W
1
5
LSSA21
R/W
0
4
LSSA20
R/W
0
3
LSSA19
R/W
0
2
LSSA18
R/W
0
1
LSSA17
R/W
0
0
LSSA16
R/W
0
bit Symbol
Read/Write
After reset
LSASH
(02A6H)
Function
LCD sub area start address (A23-A16)
Note: When assigned internal RAM as VRAM, A1 signal cannot be used. Every 4bytes setting is needed.
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LCD Sub Area HOT Point Register (X-dir)
7
SAHX7
R/W
0
6
SAHX6
R/W
0
5
SAHX5
R/W
0
4
SAHX4
R/W
0
3
SAHX3
R/W
0
2
SAHX2
R/W
0
1
SAHX1
R/W
0
0
SAHX0
R/W
0
bit Symbol
Read/Write
After reset
Function
LSAHX
(02A8H)
LCD sub area HOT point (7-0)
7
6
5
4
3
2
1
SAHX9
R/W
0
0
SAHX8
R/W
0
bit Symbol
Read/Write
After reset
(02A9H)
LCD sub area HOT
point (9-8)
Function
LCD Sub Area HOT Point Register (Y-dir)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
SAHY7
R/W
0
SAHY6
R/W
0
SAHY5
R/W
0
SAHY4
R/W
0
SAHY3
R/W
0
SAHY2
R/W
0
SAHY1
R/W
0
SAHY0
R/W
0
LSAHY
(02AAH)
LCD sub area HOT point (7-0)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
SAHY8
R/W
(02ABH)
0
LCD sub
area HOT
point (8)
Function
LCD Sub Area Display Segment Size Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
SAS7
R/W
0
SAS6
R/W
0
SAS5
R/W
0
SAS4
R/W
0
SAS3
R/W
0
SAS2
R/W
0
SAS1
R/W
0
SAS0
R/W
0
LSASS
(02ACH)
LCD sub area segment size (7-0)
7
6
5
4
3
2
1
SAS9
R/W
0
0
SAS8
R/W
0
bit Symbol
Read/Write
After reset
(02ADH)
LCD sub area segment
size (9-8)
Function
LCD Sub Area Display Common Size Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
SAC7
R/W
0
SAC6
R/W
0
SAC5
R/W
0
SAC4
R/W
0
SAC3
R/W
0
SAC2
R/W
0
SAC1
R/W
0
SAC0
R/W
0
LSACS
(02AEH)
LCD sub area common size (7-0)
7
6
5
4
3
2
1
0
SAC8
R/W
0
bit Symbol
Read/Write
After reset
Function
(02AFH)
LCD sub area common size (8)
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3.19.3 Description of Operation
3.19.3.1 Outline
After the required settings such as the operation mode, display data memory address,
color mode, and LCD size are specified, the start register is set to start the LCDC
operation.
The LCDC issues a bus request to the CPU. When the bus is granted, the LCDC
reads data of the display size from the display RAM, stores the data in the FIFO
buffer in the LCDC, and then returns the bus to the CPU.
The display data in the FIFO buffer is transferred to the LCD driver via a dedicated
bus (LD pin). At this time, control pins (such as LCP0) that are connected to the LCD
driver also output specified waveforms in synchronization with the transfer of display
data.
Note: While display RAM data is being read, the CPU operation is halted by the internal BUSREQ signal.
Therefore, the CPU stop time must be taken into account in programming.
External SDRAM, SRAM, or internal RAM (288 Kbytes) can be used as the display
RAM. Since the internal RAM allows very fast accesses (32-bit bus, 2-1-1-1 read/write),
it enables data transfer to the LCD driver (DMA operation) with the minimum CPU
stop time. Using the internal RAM also greatly reduces power consumption during
LCD display.
3.19.3.2
Display Memory Mapping
Since the number of bits needed to display one pixel varies even for the same display
size depending on the selected color mode, the required display RAM size also varies
with each color mode. (The color mode can be selected from a range of monochrome to
16777216 colors.)
In monochrome mode, one pixel of display data corresponds to one bit of display RAM
data. Likewise, the number of display RAM data used for displaying one pixel in each
color mode is as follows:
4-grayscale
1 pixel = 2 bits
1 pixel = 4 bits
1 pixel = 6 bits
1 pixel = 8 bits
1 pixel = 12 bits
16-grayscale
64-grayscale
STN 256-color
STN 4096-color
STN 65536-color 1 pixel = 16 bits
STN 256K-color 1 pixel = 16 bits (not 18 bits)
STN 16M-color
1 pixel = 24 bits
For example, a 320-segment x 240-common display in 4-grayscale mode requires
19200 bytes of display RAM space (320 × 240 × 2 = 152600 bits = 19200 bytes).
For details, refer to “Memory Map Image and Data Output in Each Display Mode”
later in this chapter.
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3.19.3.3
Basic Operation
The following diagram shows the basic timings of the waveforms generated by the
LCDC and adjustable elements. The adjustable elements for each signal include enable
time, phase, and delay time.
The signals used and their connections and settings vary with the LCD driver type
(STN/TFT) and specifications to be used.
Signal Name
Frame period (Refresh rate)
(Phase control)
LVSYNC signal
(Enable width control)
(Enable width control)
(Enable width control)
(Phase control)
LHSYNC signal
LLOAD signal
(Phase control)
LGOEn signal
(Enable width control)
(Phase control)
(Delay control)
(Delay control)
LFR signal (FREDGE=0)
(Frame divide control)
(Line)
(Line divide)
(Dot divide)
(Dot)
LFR signal (FREDGE=1)
DLS=0 (Line inversion)
(Line divide)
(Dot divide)
LLOAD signal
LLOAD signal details
(Valid data output)
LCP0 signal
(Only at valid data output)
(Always output)
(Phase control)
LD23-LD0 signal
LDINV signal
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3.19.3.4
Reference Clock LCP0
LCP0 is used as the reference clock for all the signals in the LCDC.
This section explains how to set the frequency (period) of the LCP0 signal.
The LCP0 clock speed (LD bus transfer speed) is determined by selecting TFT or STN
and setting LCDMODE0<SCPW1:0> and LCDMODE1<SWPW2>. The clock speed should
be selected to meet the characteristics of the LCD driver to be used.
The LCP0 period can be selected from four types: fSYS/2, fSYS/4, fSYS/8, fSYS/16, fSYS/24 and
fSYS/48.
Internal signal (fsys)
LCP0
fsys / 2
fsys / 4
LD23-LD0
LCP0
LD23-LD0
LCP0
fsys /48
LD23-LD0
Figure 3.19.1 LCP Frequency Selection
Minimum speed
The LCP0 period needs to be short enough to prevent the next line signal from
overlapping the current line signal.
The transfer speed of display data must be set to suit the refresh rate; otherwise data
cannot be transferred properly. Set the data transfer speed so that each transfer
completes within the LHSYNC period.
STN monochrome/grayscale
:
:
:
Segment size / 8 × LCP0 [s: period] < LHSYNC [s: period] STN color
Segment size × 3 / 8 LCP0 [s: period] < LHSYNC [s: period]
Segment size × LCP0 [s: period] < LHSYNC [s: period]
STN color
TFT
Maximum speed
If the LCP0 period is too short, the data to be transferred to the LCD driver cannot be
prepared in time, causing wrong data to be transferred. The maximum transfer speed
is limited by the operation mode and display RAM type (bus width, wait condition, and
so on). If the data rotation function is used, the transfer speed must be slower.
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LCP0 Setting Range Table
Conditions
fSYS
: 60 MHz
Display size (color)
: up to 320 × 320
Display size (monochrome/grayscale) : up to 640 × 480
Note: This table shows the range of LCP0 settings that can be made under the conditions shown above. If the
CPU clock speed, display size, or refresh rate is changed, the LCP0 range also changes.
Display RAM
Display Mode
External
SRAM
(0 waits)
External SRAM
(N waits)
Internal RAM
SDRAM
f
/4 tof
/8 to f
/16 (up to 2 waits)
SYS
SYS
STN monochrome
Refresh cycle = 70 Hz
f
/2
SYS
f
/2
SYS
f
SYS
/2
SYS
SYS
f
f
f
/16 (up to 6 waits)
SYS
SYS
to f
/16
to f
/16
to f
/16
SYS
f
/16 (up to 14 waits)
SYS
STN 4-grayscale
Refresh cycle = 70 Hz
STN 16-grayscale
Refresh cycle = 140 Hz
STN 64-grayscale
Refresh cycle = 200 Hz
STN 256-color
f
/2
SYS
/2
SYS
f
/2
SYS
/2
SYS
f
/2
f
/4 to f
/8 (up to 2 waits)
SYS
SYS
SYS
SYS
SYS
to f
/16
/8
to f
f
to f
/16
/8
to f
/16
/8
f
/8 (up to 6 waits)
SYS
SYS
f
f
/4
/8 to f
/16 (up to 2 waits)
SYS
SYS
SYS
SYS
SYS
to f
to f
f
/16 (up to 6 waits)
SYS
SYS
f
/4
f
/4
f
/4
f
/4 (up to 1 wait)
SYS
SYS
SYS
SYS
f
/2
f
/2
f
/4
/8 to f
/16 (up to 2 waits)
SYS
SYS
SYS
SYS
SYS
Refresh cycle = 70 Hz
to f
/16
/16
to f
/16
/16
to f
/16
/16
f
/16 (up to 6 waits)
SYS
SYS
SYS
SYS
f
f
/4 to f
/8 to f
SYS
/16 (up to 2 waits)
/16 (up to 6 waits)
SYS
SYS
SYS
SYS
STN 4K-color
Refresh cycle = 70 Hz
f
/2
f
/2
f
SYS
/4
SYS
SYS
to f
to f
to f
SYS
SYS
SYS
f
/16 (up to 14 waits)
f
f
/4 to f
/8 to f
/16 (up to 2 waits)
/16 (up to 6 waits)
SYS
SYS
SYS
SYS
TFT 4K-color
Refresh cycle = 70 Hz
f
/2
SYS
f
/2
SYS
f
SYS
/2
SYS
SYS
to f
/16
/16
To f
/16
/16
to f
/16
/16
SYS
f
/16 (up to 14 waits)
SYS
f
f
/4 to f
/8 to f
/16 (up to 2 waits)
/16 (up to 6 waits)
SYS
SYS
SYS
SYS
TFT 64K-color
Refresh cycle = 70 Hz
f
/2
SYS
f
/2
SYS
f
SYS
/2
SYS
SYS
to f
to f
to f
SYS
f
/16 (up to 14 waits)
SYS
f
f
/4 to f
/8 to f
/16 (up to 2 waits)
/16 (up to 6 waits)
SYS
SYS
SYS
SYS
TFT 64K-color
+ rotation operation
f
/2
SYS
f
/2
SYS
f
SYS
/2
SYS
SYS
to f
/16
/16
/16
to f
/16
/16
/16
to f
/16
/16
/16
SYS
f
/16 (up to 14 waits)
SYS
TFT 256K-color
Refresh cycle = 70 Hz
f
/2
SYS
f
/2
SYS
f
/4
f
/8 to f
/16 (up to 2 waits)
SYS
SYS
SYS
SYS
SYS
to f
to f
to f
f
/16 (up to 2 waits)
SYS
SYS
f
f
/4 to f
/8 to f
/16 (up to 2 waits)
/16 (up to 2 waits)
SYS
SYS
SYS
SYS
TFT 16M-color
Refresh cycle = 70 Hz
f
/2
SYS
f
/2
SYS
f
SYS
/2
SYS
SYS
to f
to f
to f
SYS
f
/16 (up to 2 waits)
SYS
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Example 1: When fSYS = 10 MHz, STN mode, LCDMODE0<SCPW1:0> = 01
Internal reference clock LCP0 = fSYS / 8 = 10 MHz / 8 = 1.25 [MHz]
LCP0 period = 1 / 1.25 [MHz] = 0.8 [μS]
Example 2: when fSYS = 60 MHz, TFT mode, LCDMODE0<SCPW1:0> = 11
Internal reference clock LCP0 = fSYS / 16 = 60 MHz / 16 = 3.75 [MHz]
LCP0 period = 1 / 3.75 [MHz] = 266 [nS]
LCDMODE0 Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
SCPW1
R/W
1
SCPW0
R/W
1
MODE3
R/W
0
MODE2
R/W
0
MODE1
R/W
0
MODE0
R/W
0
RAMTYPE1 RAMTYPE0
LCDMODE0
(0280H)
R/W
R/W
0
0
Display RAM
LD bus transfer speed
Mode selection
0000: Reserved
0001: SR (mono)
0010: SR (4-gray)
0011: Reserved
0100: SR (16-gray)
0101: SR (64-gray)
1000: Reserved
SCPW2= 0
00: 2-clk
00: Internal RAM
(32-bit)
1001: Reserved
1010: TFT (256-color)
1011: TFT (4096-color)
1100: TFT (64K-color)
1101: TFT(256K-,16M-color)
01: 4-clk
01: External SRAM
10: SDRAM
10: 8-clk
Function
11: 16-clk
SCPW2= 1
00: 6-clk
11: Reserved
0110: STN (256-color) 1110: Reserved
0111: STN (4096-color) 1111: Reserved
01: 12-clk
10: 24-clk
11: 48-clk
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LCDCTL0 <LCP0OC> is used to control the output timing of the LCP0 signal. When
<LCP0OC>=0, the LCP0 signal is always output. When <LCP0OC>=1, the LCP0
signal is output only when valid data is output.
LCP0 signal LCP0OC=1
LCP0 signal LCP0OC=0
LCD Control 0 Register
7
PIPE
R/W
0
6
ALL0
R/W
0
5
4
3
2
1
LCP0OC
R/W
0
START
R/W
0
bit Symbol
Read/Write
After reset
FRMON
R/W
–
R/W
DLS
R/W
LCDCTL0
(0285H)
0
0
0
0
Always
write “0”
PIP function Segment
data
Frame divide
setting
FR signal
LCP0/Line
selection
LCP0 (Note) LCDC
0: Always
output
operation
0: Disable
1: Enable
0: Normal
1: Always
output “0”
0: Disable
1: Enable
1: At valid
data only
LLOAD
0: Stop
1: Start
0: Line
Function
1: LCP0
width
0: At setting
in register
1: At valid
data only
Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of <LCP0OC> bit.
The phase of the LCP0 signal can be inverted by the setting of LCDCTL1<LCP0P>.
LVSYNC
LHSYNC
LLOAD
LGOEn
LFR
All signal changes
LCP0
LCP0P=0
LCP0P=1
LCP0
LD23-LD0
LCD Control 1 Register
7
LCP0P
R/W
1
6
5
4
3
2
1
LVSW1
R/W
0
LVSW0
R/W
0
bit Symbol
LHSP
R/W
LVSP
R/W
LLDP
R/W
LCDCTL1
(0286H)
Read/Write
After reset
0
1
0
0
LCP0
LHSYNC
phase
LVSYNC
phase
LLOAD
phase
LVSYNC
phase
enable time control
00 : 1 clock of LHSYNC
01 : 2 clocks of LHSYNC
10 : 3 clocks of LHSYNC
11 : Reserved
Function
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
1: Falling
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3.19.3.5
Refresh Rate
The period of the horizontal synchronization signal LHSYNC is defined as the
product of the value set in LCDHSP<LH15:0> and the LCP0 clock period.
The value to be set in LCDHSP<LH15:0> is obtained as follows:
TFT
Segment size + number of dummy clocks (*)
STN
Monochrome/grayscale : (Segment size / 8) + number of dummy clocks (*)
Color
: (Segment size × 3 / 8) + number of dummy clocks (*)
LHSYNC [s: period] = LCP0 [s: period] × (<LH15:0> + 1)
LCD LHSYNC Pulse Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
LH7
LH6
LH5
LH4
LH3
LH2
LH1
LH0
LCDHSP
(028AH)
W
0
0
0
0
0
0
0
0
LHSYNC period (bits 7–0)
7
6
5
4
3
2
1
0
(028BH)
bit Symbol
Read/Write
After reset
Function
LH15
LH14
LH13
LH12
LH11
LH10
LH9
LH8
W
0
0
0
0
0
0
0
0
LHSYNC period (bits 15-8)
The period of the vertical synchronization signal LVSYNC is defined as the product of
the value set in LCDVSP<LV9:0> and the LHSYNC period.
The value to be set in LCDVSP<LV9:0> is obtained as follows:
TFT
Common size + number of dummy clocks (*)
STN
Common size + number of dummy clocks (*)
(A minimum of one dummy clock must be inserted in the back
porch.)
LVSYNC [s: period] = LHSYNC [s: period] × (<LV9:0> + 1)
= LCP0 [s: period] × (<LH15:0> + 1) × (<LV9:0> + 1)
LCD V SYNC Pulse Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
LVP7
LVP6
LVP5
LVP4
LVP3
LVP2
LVP1
LVP0
LCDVSP
(028CH)
W
0
7
0
6
0
5
0
0
0
2
0
0
LVSYNC period (bits 7-0)
4
3
1
0
(028DH)
bit Symbol
Read/Write
After reset
Function
LVP9
LVP8
W
0
0
LVSYNC period (bits 9-8)
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Note: At least two LCP0 pulses
must be inserted.
• Insertion of dummy clocks
Reference LHSYNC
(Delay=0)
LVSYNC
LHSYNC
(with delay)
LCP0
LD23-0
Vertical Front Porch
Horizontal Front
Porch
Horizontal back
Porch
Vertical back Porch
The above is a conceptual diagram showing the data (LD23-0), shift clock (LCP0),
horizontal synchronization signal (LHSYNC), and vertical synchronization signal
(LVSYNC) on the LCD panel.
The front porch and back porch as shown above should be taken into consideration in
setting LCDHSP<LH15:0> and LCDVSP<LV9:0> explained earlier.
Note 1: The horizontal back porch must be set so that “data transfer” plus “LCP0 × 2 clocks” are completed
within one period of the reference clock LHSYNC (with 0 delay), as defined by the following equation:
Delay time (LLOAD) + number of data transfer times + 2 < LHSYNC (LCP0 pulse count)
Note 2: The vertical back porch must have a minimum of one dummy clock.
(*) TFT driver
The recommended number of dummy clocks is specified by each TFT driver (or LCD module). Refer to the
specifications of the TFT driver (LCD module) to be used.
(*) STN driver
For an STN driver, the refresh rate can be set accurately by adjusting the value of the horizontal back porch. If the
desired refresh rate cannot be obtained by the horizontal back porch, it can be further adjusted by the vertical back porch.
For details, refer to the setting example to be described later in this section.
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•
Setting method
The front dummy LHSYNC (vertical front porch) not accompanied by valid data in
the total of LHSYNC period in the LVSYNC period is defined by the value set in
LCDPRVSP<PLV6:0>.
Front dummy LHSYNC (vertical front porch) = <PLV6:0>
The back dummy LHSYNC (vertical back porch) is defined as follows:
(<LVP9:0> + 1) − (valid LHSYNC: common size) − (front dummy LHSYNC:
<PLV6:0>)
The vertical back porch must have a minimum of one dummy clock.
The front dummy LCP0 (horizontal front porch) not accompanied by valid data in the
total number of LCP0 clocks in the LHSYNC period is defined by the value set in
LCDLDDLY<LDD6:0>.
Front dummy LCP0 (horizontal front porch) = <LDD6:0>
The back dummy LCP0 (horizontal back porch) is defined as follows:
(<LH15:0> + 1) − (valid LCP0: segment size) − (front dummy LCP0: <LDD6:0>)
Note 1: The back dummy LCP0 (horizontal back porch) must have a minimum of two LCP0 clocks.
Note 2: The delay time that is set in LCDLDDLY<LDD6:0> is counted based on LHSYNC (with 0 delay).
7
6
5
4
3
LDD3
W
2
1
0
LCDLDDLY
(0290H)
bit Symbol
Read/Write
After reset
PDT
R/W
0
LDD6
LDD5
LDD4
LDD2
LDD1
LDD0
0
0
0
0
0
0
0
Data output
timing
LLOAD delay (bits 6-0)
0: Sync with
LLOAD
Function
1: 1 clock later
than LLOAD
Example 1) Setting the refresh rate to 200 Hz under the following conditions:
fSYS = 30 MHz, STN mode, 320-segment × 240-common, 4096-color display,
LCDMODE0<SCPW1:0> = 00
Internal reference clock LCP0 = fSYS / 4 = 30 [MHz] / 4 = 7.5 [MHz]
Therefore, LCP0 period = 1 / 7.5 [MHz] = 0.133 [μS]
Condition 1: Refresh rate = 200 Hz, Refresh cycle = 5 [ms
Condition 2: LH = <LH15:0> ≥ (320×3/8) − 1 = 119
Condition 3: LV = <LVP9:0> ≥ 240 − 1
When <LVP9:0> = 239 (minimum value):
LVSYNC [s: period]
= LHSYNC [s: period] × (<LVP9:0> + 1)
= LCP0 [s: period] × (<LH15:0> + 1) × (<LVP9:0> + 1)
5 [ms]
= (1 / 7.5 [MHz]) × (LH + 1) ×240
= (5 × 10 -3) × (7.5 × 10 6) / 240
= 156.25
LH + 1
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3.19.3.6
Signal Settings
Signal Name
LCP0 signal
Valid LHSYNC
(Common size)
LVSYNC signal
Front dummy LHSYNC
(Vertical front porch)
Back dummy LHSYNC
(Vertical back porch)
LHSYNC signal
LGOEn signal
FR signal
LLOAD signal
LLOAD signal
LCP0 signal
LD23-LD0 signal
LDINV signal
The above diagram shows the typical timings of the signals controlled by the LCDC.
This section explains how to control each of these signals.
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1. LVSYNC Signal
The period of the vertical synchronization signal LVSYNC indicates the time for each
screen update (refresh rate). The LVSYNC period is defined as an integral multiple of
the period of the horizontal synchronization signal LHSYNC.
The LVSYNC period is calculated as the product of the value set in LCDVSP<LV 9:0>
and the LHSYNC period. The value to be set in LCDVSP<LV9:0> should be “common
size + number of dummy clocks” or larger for TFT and STN.
LVSYNC [s: period]
= LHSYNC [s: period] × (<LVP9:0> + 1)
= LCP0 [s: period] × (<LH15:0> + 1) × (<LVP9:0> + 1)
LCD V SYNC Pulse Register
7
6
5
4
3
2
1
0
LCDVSP
(028CH)
bit Symbol
Read/Write
After reset
Function
LVP7
LVP6
LVP5
LVP4
LVP3
LVP2
LVP1
LVP0
W
0
7
0
6
0
5
0
0
0
2
0
0
LVSYNC period (bits 7-0)
4
3
1
0
(028DH)
bit Symbol
Read/Write
After reset
LVP9
LVP8
W
0
0
LVSYNC period
(bits 9-8)
Function
The enable width of the LVSYNC signal can be specified as 1 clock, 2 clocks, or 3
clocks of LHSYNC in LCDCTL1<LVSW1:0>.
The phase of the LVSYNC signal can be inverted by the setting of LCDCTL1
<LVSP>.
Refresh rate
(Enable width control)
LVSP=0
(Phase control)
LVSP=1
LVSYNC signal
LCD Control 1 Register
7
LCP0P
R/W
1
6
5
4
3
2
1
LVSW1
R/W
0
LVSW0
R/W
0
bit Symbol
Read/Write
After reset
LHSP
R/W
LVSP
R/W
LLDP
R/W
LCDCTL1
(0286H)
0
1
0
0
LCP0
LHSYNC
phase
LVSYNC
phase
LLOAD
phase
LVSYNC
phase
enable time control
00 : 1 clock of LHSYNC
01 : 2 clocks of LHSYNC
10 : 3 clocks of LHSYNC
11 : Reserved
Function
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
1: Falling
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2. LHSYNC Signal
The period of the horizontal synchronization signal LHSYNC corresponds to one line
of display. The LHSYNC period is defined as an integral multiple of the reference
clock signal LCP0.
The LHSYNC period is defined as the product of the value set in LCDHSP<LH15:0 >
and the LCP0 clock period. The value to be set in LCDHSP<LH15:0 > should be
“segment size + number of dummy clocks” or larger for TFT. In the case of STN, the
minimum value of LCDHSP<LH15:0 > is:
Monochrome/grayscale
Color
: (Segment size / 8) + number of dummy clocks
: (Segment size × 3 / 8) + number of dummy clocks
LHSYNC [s: period] = LCP0 [s: period] × (<LH15:0> + 1)
LCD LHSYNC Pulse Register
7
6
5
4
3
2
1
0
LCDHSP
(028AH)
bit Symbol
Read/Write
After reset
Function
LH7
LH6
LH5
LH4
LH3
LH2
LH1
LH0
W
0
0
0
0
0
0
0
0
LHSYNC period (bits 7-0)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
LH15
LH14
LH13
LH12
LH11
LH10
LH9
LH8
(028BH)
W
0
0
0
0
0
0
0
0
LHSYNC period (bits 15-8)
The enable width of the LHSYNC signal can be specified by LCDHSW<HSW9:0>. It
is also possible to set the delay time for the LVSYNC signal in units of LCP0 pulses.
LHSYNC signal
(Enable width control)
(Phase control)
(Delay control)
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TMP92CZ26A
The enable width of the LHSYNC signal is set using LCDHSW<HSW8:0>. It can be
specified in a range of 1 to 512 pulses of the LCP0 clock.
The enable width is represented by the following equation:
Enable width = <HSW8:0> + 1
Thus, when LCDHSW<HSW8:0> is set to “0”, the enable width is set as one pulse of
the LCP0 clock.
Signal Name
LCP0
LHSYNC signal
High width setting
LCP0 clock = 1, 2, 3 … 512 pulses
LCDHSW Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
HSW7
HSW6
HSW5
HSW4
HSW3
HSW2
HSW1
HSW0
LCDHSW
(0294H)
W
0
0
0
0
0
0
0
0
LHSYNC width (bits 7-0)
7
6
5
4
3
2
1
0
LCDHWB8
(0299H)
bit Symbol
Read/Write
After reset
O2W9
O2W8
O1W9
O1W8
O0W8
LDW9
LDW8
HSW8
W
0
0
0
0
0
0
0
0
LGOE2 width (bits 9-8) LGOE1 width (bits 9-8)
LGOE0
width (bit 8)
LLOAD width (bits 9-8)
LHSYNC
width (bit 8)
Function
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As shown in the diagram below, delay time of 0 to 127 pulses of the LCP0 clock can be
inserted in the LHSYNC signal.
Delay time = <HSD6:0>
Signal Name
LCP0 signal
LVSYNC signal
Reference LHSYNC
(with 0 delay)
LHSYNC signal
Delay control 1
LCDHSDLY Register
7
6
5
4
3
HSD3
W
2
1
0
bit Symbol
Read/Write
After reset
Function
HSD6
HSD5
HSD4
HSD2
HSD1
HSD0
LCDHSDLY
(028FH)
0
0
0
0
0
0
0
LHSYNC delay (bits 6-0)
The phase of the LHSYNC signal can be inverted by the setting of LCDCTL1
<LVSP>.
LHSYNC period
LHSYNC signal
(Enable width control)
LHSP=0
(Phase control)
LHSP=1
LCD Control 1 Register
7
LCP0P
R/W
1
6
5
4
3
2
1
LVSW1
R/W
0
LVSW0
R/W
0
LCDCTL1
(0286H)
bit Symbol
Read/Write
After reset
LHSP
R/W
LVSP
R/W
LLDP
R/W
0
1
0
0
LCP0
LHSYNC
phase
LVSYNC
phase
LLOAD
phase
LVSYNC
phase
enable time control
00 : 1 clock of LHSYNC
01 : 2 clocks of LHSYNC
10 : 3 clocks of LHSYNC
11 : Reserved
Function
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
1: Falling
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3. LLOAD Signal
The LLOAD signal is used to control the timing for the LCD driver to receive display
data. The period of the LLOAD signal synchronizes to one line of display. It is defined
as an integral multiple of the reference clock LCP0.
Refresh rate
Front dummy LHSYNC
(Vertical front porch)
Back dummy LHSYNC
(Vertical back porch)
LLOAD: Common size
(Valid data)
LVSYNC signal
LHSYNC signal
LLOAD signal
LD23-LD0 signal
LLOAD signal
LLOAD signal LCDLDDLY<PDT> = 1
LCP0 signal
LD23-LD0 signal
LDINV signal
The LHSYNC signal and LLOAD signal differs in that the LHSYNC signal is output
all the time whereas the LLOAD signal is output only at valid data lines (commons).
Display data is output in synchronization with the LLOAD signal. Therefore, if a
delay is inserted in the LLOAD signal through the LCDLDDLY register, data output
is also delayed.
Also note that when LCDLDDLY<PDT>=1 , data is output one LCP0 clock later than
the LLOAD signal.
LCDLDDLY<PDT>=0: Data is output in synchronization with the LLOAD signal.
LCDLDDLY<PDT>=1: Data is output one LCP0 clock later than the LLOAD signal.
The delay time for the LLOAD signal is controlled based on LCDLDDLY<PDT>=1.
Therefore, even if the delay time is set to “0” with LCDLDDLY<PDT>=0, the LLOAD
signal is output with a delay of one LCP0 clock. Be careful about this point.
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The number of pulses in the front dummy LHSYNC (vertical front porch) is specified
by LCDPRVSP<PLV6:0>. This delay time can be set in a range of 0 to 127 pulses of
the LCP0 clock.
Front dummy LHSYNC = <PLV6:0>
LCD LVSYNC Pre Pulse Register
7
6
5
4
3
2
1
0
LCDPRVSP
(028EH)
bit Symbol
Read/Write
After reset
Function
PLV6
PLV5
PLV4
PLV3
W
PLV2
PLV1
PLV0
0
0
0
0
0
0
0
Front dummy LVSYNC (bits 6-0)
The back dummy LHSYNC (vertical back porch) is defined as follows:
(<LVP9:0> + 1) − (valid LHSYNC: common size) − (front dummy LHSYNC:
<PLV6:0>)
Signal Name
LCP0
LLOAD signal
High width setting
LCP0 clock = 1, 2, 3 … 1023 pulses (<PDT>=0) / 1024 pulses (<PDT>=1)
Note: The vertical back porch must be set to “1” or longer in all the cases (STN/TFT).
The enable width of the LLOAD signal is determined depending on the
LCDCTL0<LCP0OC> setting, as shown below.
LCDCTL0<LCP0OC> = 0 : Output at setting value in (LCDDLW) <LDW9:0>
LCDCTL0<LCP0OC> = 1 : Output at valid data
LCD Control 0 Register
7
PIPE
R/W
0
6
ALL0
R/W
0
5
4
3
2
1
LCP0OC
R/W
0
START
R/W
0
bit Symbol
Read/Write
After reset
FRMON
R/W
–
R/W
DLS
R/W
LCDCTL0
(0285H)
0
0
0
0
Always
write “0”
PIP function Segment
data
Frame divide
setting
FR signal
LCP0/Line
selection
LCP0 (Note) LCDC
0: Always
output
operation
0: Disable
1: Enable
0: Normal
1: Always
output “0”
0: Disable
1: Enable
1: At valid
data only
LLOAD
0: Stop
1: Start
0: Line
Function
1: LCP0
width
0: At setting
in register
1: At valid
data only
Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of <LCP0OC> bit.
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The enable width of the LLOAD signal is specified using LCDLDW<LDW9:0>. It can
be set in a range of 0 to 1024 pulses of the LCP0 clock.
The actual enable width is determined depending on the LCDLDDLY<PDT> setting,
as shown below.
Enable width = <LDW9:0> + 1 (when <PDT> = 1, <LDW9:0>=0 is prohibited)
Enable width = <LDW9:0>
(when <PDT> = 0)
LCDLDW Register
7
6
5
4
3
2
1
0
LCDLDW bit Symbol
LDW7
LDW6
LDW5
LDW4
LDW3
LDW2
LDW1
LDW0
(0295H)
Read/Write
After reset
Function
W
0
0
0
0
0
0
0
0
LLOAD width (bits 7-0)
7
6
5
4
3
2
1
0
LCDHWB8
(0299H)
bit Symbol
Read/Write
After reset
O2W9
O2W8
O1W9
O1W8
O0W8
LDW9
LDW8
HSW8
W
0
0
0
0
0
0
0
0
LGOE2 width (bits 9-8) LGOE1 width (bits 9-8)
LGOE0
width
(bit 8)
LLOAD width (bits 9-8) LHSYNC
Function
width
(bit 8)
When LCDCTL0<LCP0OC>=1, the enable width of the LLOAD signal is shown
below.
LLOAD LCDLDDLY<PDT> = 0
LLOAD LCDLDDLY<PDT> = 1
LCP0
LD23-LD0
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As shown in the diagram below, delay time of 0 to 127 pulses of the LCP0 clock can be
inserted in the LLOAD signal.
Delay time = <LDD6:0>
Signal Name
LCP0 signal
LLVSYNC signal
LHSYNC signal
(Internal reference signal)
LLOAD signal
Delay control
Note: The delay time for the LLOAD signal is controlled based on LCDLDDLY<PDT>=1. Therefore, even if the
delay time is set to”0” with LCDLDDLY<PDT>=0, the LLOAD signal is output with a delay of one LCP0
clock. Be careful about this point.
LCDLDDLY Register
7
PDT
R/W
0
6
LDD6
5
LDD5
4
LDD4
3
LDD3
W
2
LDD2
1
LDD1
0
LDD0
bit Symbol
Read/Write
After reset
LCDLDDLY
(0290H)
0
0
0
0
0
0
0
Data output
timing
LLOAD delay (bits 6-0)
0: Sync with
LLOAD
Function
1: 1 clock later
than LLOAD
The phase of the LLOAD signal can be inverted by the setting of LCDCTL1 <LLDP>.
LLOAD period
(Enable width control)
LLDP=0
LLDP=1
(Phase control)
LLOAD signal
LCD Control 1 Register
7
LCP0P
R/W
1
6
LHSP
5
LVSP
4
LLDP
3
2
1
LVSW1
R/W
0
LVSW0
R/W
0
bit Symbol
Read/Write
After reset
LCDCTL1
(0286H)
R/W
R/W
R/W
0
1
0
0
LCP0
LHSYNC
phase
LVSYNC
phase
LLOAD
phase
LVSYNC
phase
enable time control
00 : 1 clock of LHSYNC
01 : 2 clocks of LHSYNC
10 : 3 clocks of LHSYNC
11 : Reserved
Function
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
1: Falling
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4. LGOE0 to LGOE2 Signals
The LCDC has three signals (LGOE0 to LGOE2) that can be controlled like the
LHSYNC signal. For these signals, the enable width, delay time, and phase timing can
be adjusted as shown below.
Signal Name
LCP0
LGOE0 signal
LGOE1 signal
LGOE2 signal
High width setting
LGOE0: LCP0 clock = 1, 2, 3 … 512 pulses
LGOE1: LCP0 clock = 1, 2, 3 … 1024 pulses
LGOE2: LCP0 clock = 1, 2, 3 … 1024 pulses
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
O0W7
O0W6
O0W5
O0W4
O0W3
O0W2
O0W1
O0W0
LCDHO0W
(0296H)
W
0
0
0
0
0
0
0
0
LGOE0 width (bits 7-0)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
O1W7
O1W6
O1W5
O1W4
O1W3
O1W2
O1W1
O1W0
LCDHO1W
(0297H)
W
0
0
0
0
0
0
0
0
LGOE1 width (bits 7-0)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
O2W7
O2W6
O2W5
O2W4
O2W3
O2W2
O2W1
O2W0
LCDHO2W
(0298H)
W
0
0
0
0
0
0
0
0
LGOE2 width (bits 7-0)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
O2W9
O2W8
O1W9
O1W8
O0W8
LDW9
LDW8
HSW8
LCDHWB8
(0299H)
W
0
0
0
0
0
0
0
0
LGOE2 width (bits 9-8) LGOE1 width (bits 9-8)
LGOE0
width
(bit 8)
LLOAD width (bits 9-8) LHSYNC
Function
width
(bit 8)
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Signal Name
LCP0 signal
LVSYNC signal
LHSYNC signal
(Internal reference signal)
LGOE0 signal
Delay control
7
bit Symbol
Read/Write
After reset
Function
6
5
4
3
OE0D3
W
2
1
0
LCDO0DLY
(0291H)
OE0D6
OE0D5
OE0D4
OE0D2
OE0D1
OE0D0
0
0
0
0
0
0
0
OE0 delay (bits 6-0)
3
7
6
5
4
2
1
0
LCDO1DLY bit Symbol
OE1D6
OE1D5
OE1D4
OE1D3
OE1D2
OE1D1
OE1D0
(0292H)
Read/Write
After reset
Function
W
0
0
0
0
0
0
0
OE1 delay (bits 6-0)
3
7
6
5
4
2
1
0
LCDO2DLY
(0293H)
bit Symbol
Read/Write
After reset
Function
OE2D6
OE2D5
OE2D4
OE2D3
OE2D2
OE2D1
OE2D0
W
0
0
0
0
0
0
0
OE2 delay (bits 6-0)
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LGOEn signal
LGOEnP=0
LGOEnP=1
(Phase control)
LCD Control 2 Register
7
6
5
4
3
2
1
0
LCDCTL2
bit Symbol
Read/Write
After reset
LGOE2P
LGOE1P
LGOE0P
(0287H)
R/W
R/W
0
R/W
0
0
LGOE2
phase
LGOE1
LGOE0
phase
phase
Function
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
1: Falling
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5. LFR Signal
The LFR (frame) signal is used to control the direction of bias the LCD driver applies
on liquid crystal cells. With small screens in monochrome mode, the polarity of the LFR
signal is normally inverted in synchronization with each screen display. With large
screens or when grayscale or color mode is used, the polarity is inverted at shorter
intervals to adjust the display quality.
When LCDCTL0<FRMON>=“1” and LCDCTL0<DLS> = “0”, the LFR signal is
inverted at intervals of “LHSYNC x N” (LHSYNC: internal reference signal with 0
delays). The “N” value is specified in LCDDVM0<FML3:0> and LCDDVM1<FML7:4>.
When <DLS>="0" and <FREDGE>=0, LFR signal synchronous with front edge of
LHSYNC signal, and when <DLS>="0" and <FREDGE>=1, LFR signal synchronous
with rear edge of LHSYNC signal.
When LCDCTL0<FRMON> is set to “0” to disable the frame divide function, the LFR
signal is inverted in synchronization with the LVSYNC period.
Enabling this function does not affect the waveform and timing of the LVSYNC
signal. (The refresh rate is not changed.)
Note1: The effect of this function varies with the characteristics of the LCD driver and LCD panel to be used.
Note2: LFR signal delaies synchronous with LHSYNC signal.
Generally, setting a prime number (3, 5, 7, 11, 13 and so on) as the “N” value produces better results.
LVSYNC
LFR
<FREDGE>=0
<FRMON> = 0
N
N
LHSYNC
LFR
<FREDGE>=0
<FRMON>= 1
<FMP7:0> = N
<FML7:0> = any
<DLS> = 0
LFR
<FREDGE>=1
<FRMON> = 0
LFR
<FREDGE>=1
<FRMON>= 1
<FMP7:0> = N
<FML7:0> = any
<DLS> = 0
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When LCDCTL0<FRMON>=1 and LCDCTL0<DLS>=1, frame output is inverted at
intervals set in LCDDVM0<FML3:0> and the LFR signal is inverted at intervals of
“LCP0 × M”. The “M” value is specified in LCDDVM0<FMP7:4>.
When <DLS>="1" LFR signal synchronous with front edge of LHSYNC signal.
So, prohibit to set <FREDGE>=1, always need to set <FREDGE>=0.
LVSYNC
LHSYNC
N
LHSYNC (Expansion)
M
M
LCP0
LFR
<FREDGE>=0
<FRMON> = 1
<FMP7:0> = N
<FML7:0> = M
<DLS> = 1
Note prohibit to set <FREDGE>=1, always need to set <FREDGE>=0.
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LCD Control 0 Register
7
PIPE
R/W
0
6
5
4
3
2
1
0
LCDCTL0
(0285H)
bit Symbol
Read/Write
After reset
ALL0
R/W
FRMON
R/W
–
R/W
DLS
R/W
LCP0OC
R/W
START
R/W
0
0
0
0
0
0
PIP
function
Segment
data
Frame
divide
setting
Always
write “0”
LFR signal
LCP0/line
selection
0:Line
LCDC
operation
LCP0 (Note)
0: Always
output
setting
0:Disable 0: Normal
0: Stop
1: Start
1: At valid
data only
LLOAD
1:Enable
1: Always 0: Disable
output “0” 1: Enable
1:LCP0
Function
width
0: At setting
in register
1: At valid
data only
Note: When select STN mode, LCP0 is output at valid data only regardless of the setting of <LCP0OC> bit.
Divide FRM 0 Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
FMP3
FMP2
FMP1
FMP0
FML3
FML2
FML1
FML0
LCDDVM0
(0283H)
R/W
R/W
0
0
0
0
0
0
0
0
LCP0 DVM (bits 3-0) (M)
LHSYNC DVM (bits 3-0) (N)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
FMP7
FMP6
FMP5
FMP4
FML7
FML6
FML5
FML4
LCDDVM1
(0284H)
0
0
0
0
0
0
0
0
LCP0 DVM (bits7-4) (M)
LHSYNC DVM (bits 7-4) (N)
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6. LD Bus
The data to be transferred to the LCD driver is output via a dedicated bus (LD23 to
LD0). The output format can be selected according to the input method of the LCD
driver to be used.
The LCDC reads data of the size corresponding to the specified LCD size from the
display RAM and transfers it to the external LCD driver via the data bus pin dedicated
to the LCD. Thus, the LCDC automatically issues a bus request to the CPU (to stop
CPU operation) when it needs to read data from the display RAM. The bus occupancy
rate of the LCDC varies depending on the display mode and the speed at which data is
read from the display RAM.
Valid Data Read Time
Valid Data Read Time
Display RAM
Bus Width
tLRD(ns/bytes)
(fSYS clocks/bytes)
at fSYS = 60 MHz
16.6
External SRAM
Internal RAM
16-bit
32-bit
(2 + number of waits) / 2
**1/4
**4.16
External SDRAM
16-bit
*1/2
*8.33
Note: When SDRAM is used, additional 9 clocks are needed as overhead time for reading each common (line)
data. When internal RAM is used, additional 1 clock is needed as overhead time for reading each common
(line) data. Additional 1 clock of overhead time is also needed when a change of blocks occur in the
internal RAM even if the common (line) remains the same.
The time the CPU stops operating while data for one common (line) is being
transferred is defined as tSTOP, which is represented by the following equation:
tSTOP = (SegNum × K / 8) × tLRD
SegNum: Number of display segments
: Number of bits needed for displaying one pixel
K
Monochrome display
4-grayscale display
16-grayscale display
256-color display
K=1
K=2
K=4
K=8
4096-color display
65536-color display
262144-/16777216-color display
K=12
K=16
K=24
Note: When SDRAM is used, overhead time is added as follows:
t
STOP [S] = ( SegNum × K / 8 ) × tLRD + ((1 / fSYS ) × 8 )
The bus occupancy rate indicates the proportion of the one common (line) update time tLP occupied by tSTOP and
is calculated by the following equation:
CPU bus occupancy rate = tSTOP [s] / LHSYNC [s: period]
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•
Memory Map Image and Data Output in Each Display Mode
STN monochrome (1-pixel display data = 1-bit memory data)
Display Memory
Address 0
Address 1
Address 2
Address 3
LSB
D0
MSB
D31
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LD Bus Output
8-bit type
LD0 0 → 8 …
LD1 1 → 9 …
LD2 2 → 10 …
LD3 3 → 11 …
LD4 4 → 12 …
LD5 5 → 13 …
LD6 6 → 14 …
LD7 7 → 15 …
Note: When setting 240 segment, 256 segment size of data is required.
●STN 4-grayscale (1-pixel display data = 2-bit memory data)
Display Memory
Address 0
Address 1
Address 2
Address 3
LSB
D0
MSB
D31
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
LD Bus Output
8-bit type
LD0
LD1
LD2
LD3
LD4
1 - 0 → 17-16 …
3 - 2 → 19-18 …
5 - 4 → 21-20 …
7- 6 → 23-22 …
9- 8 → 25-24 …
LD5 11-10 → 27-26 …
LD6 13-12 → 29-28 …
LD7 15-14 → 31-30 …
Figure 3.19.2 Memory Map Image and Data Output in STN Monochrome/4-Grayscale Mode
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STN 16-grayscale (1-pixel display data = 4-bit memory data)
Display Memory
Address 0
Address 1
Address 2
Address 3
LSB
D0
MSB
D31
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Address 4
Address 5
Address 6
Address 7
LSB
D0
MSB
D31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
LD Bus Output
8-bit type
LD0 3-0 → 35-32 …
LD1 7-4 → 39-36 …
LD2 11-8 → 43-40 …
LD3 15-12 → 47-44 …
LD4 19-16 → 51-48 …
LD5 23-20 → 55-52 …
LD6 27-24 → 59-56 …
LD7 31-28 → 63-60 …
Figure 3.19.3 Memory Map Image and Data Output in STN 8-/16-Grayscale Mode
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STN 64-grayscale (1-pixel display data = 6-bit memory data)
Display Memory
Address 0
Address 1
Address 2
Address 3
LSB
D0
MSB
D31
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Address 4
Address 5
Address 6
Address 7
LSB
D0
MSB
D31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Address 8
Address 9
Address 10
Address 11
LSB
D0
MSB
D31
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
LD Bus Output
8-bit type
LD0
5-0
→ 53-48
→ 59-54
→ 65-60
→ 71-66
→ 77-72
→ 83-78
→ 89-84
→ 95-90
LD1
11-6
LD2
17-12
23-18
29-24
35-30
41-36
47-42
LD3
LD4
LD5
LD6
LD7
Figure 3.19.4 Memory Map Image and Data Output in STN 64-Grayscale Mode
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STN 256-color (1-pixel display data = 8-bit memory data (R: 3 bits, G: 3 bits, B: 2 bits))
Display Memory
Address 0
Address 1
Address 2
Address 3
LSB
D0
MSB
D31
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0
G0
B0
R1
G1
B1
R2
G2
B2
R3
G3
B3
Address 4
Address 5
Address 6
Address 7
LSB
D0
MSB
D31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7
LD Bus Output
8-bit type
LD0 2-0(R0) → 23-22(B2) …
LD1 5-3(G0) → 26-24(R3) …
LD2 7-6(B0) → 29-27(G3) …
LD3 10-8(R1) → 31-30(B3) …
LD4 13-11(G1) → 34-32(R4) …
LD5 15-14(B1) → 37-35(G4) …
LD6 18-16(R2) → 39-38(B4) …
LD7 21-19(G2) → 42-40(R5) …
Figure 3.19.5 Memory Map Image and Data Output in STN 256-Color Mode
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STN 4096-color (12 bpp: R: 4 bits, G: 4 bits, B: 4 bits)
Display Memory
Address 0
Address 1
Address 2
Address 3
LSB
D0
MSB
D31
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
B0 R1 G1 B1 R2 G2
R0
G0
Address 4
Address 5
Address 6
Address 7
LSB
D0
MSB
D31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
B2
R3
G3
B3
R4
G4
B4
R5
LD Bus Output
8-bit type
LD0 3-0(R0) → 35-32(B2)…
LD1 7-4(G0) → 39-36(R3)…
LD2 11-8(B0) → 43-40(G3)…
LD3 15-12(R1) → 47-44(B3)…
LD4 19-16(G1) → 51-48(R4)…
LD5 23-20(B1) → 55-52(G4)…
LD6 27-24(R2) → 59-56(B4)…
LD7 31-28(G2) → 63-60(R5)…
Figure 3.19.6 Memory Map Image and Data Output in STN 4096-Color Mode
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TFT 256-color (1-pixel display data = 8-bit memory data (R: 3 bits, G: 3 bits, B: 2 bits)
Display Memory
Address 0
Address 1
Address 2
Address 3
LSB
D0
MSB
D31
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0
G0
B0
R1
G1
B1
R2
G2
B2
R3
G3
B3
Address 4
Address 5
Address 6
Address 7
LSB
D0
MSB
D31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
R4
G4
B4
R5
G5
B5
R6
G6
B6
R7
G7
B7
12bit (TFT)
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
0(R0)
1(R0)
2(R0)
3(G0)
4(G0)
5(G0)
6(B0)
7(B0)
12(R1)
→
→
→
→
→
→
→
→
…
…
…
…
…
…
…
…
13(R1)
14(R1)
15(G1)
16(G1)
17(G1)
18(B1)
19(B1)
Figure 3.19.7 Memory Map Image and Data Output in TFT 256-Color Mode
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TFT 4096-color (1-pixel display data = 12-bit memory data (R: 4 bits, G: 4 bits, B: 4 bits)
Display Memory
Address 0
Address 1
Address 2
Address 3
LSB
D0
MSB
D31
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0
G0
Address 4
B0
R1
G1
B1
Address 6
R2
G2
Address 7
Address 5
LSB
D0
MSB
D31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
B2
R3
G3
B3
R4
G4
B4
R5
12-bit TFT
LD0 0(R0) → 12(R1) …
LD1 1(R0) → 13(R1) …
LD2 2(R0) → 14(R1) …
LD3 3(R0) → 15(R1) …
LD4 4(G0) → 16(G1) …
LD5 5(G0) → 17(G1) …
LD6 6(G0) → 18(G1) …
LD7 7(G0) → 19(G1) …
LD8 8(B0) → 20(B1) …
LD9 9(B0) → 21(B1) …
LD10 10(B0) → 22(B1) …
LD11 11(B0) → 23(B1) …
Figure 3.19.8 Memory Map Image and Data Output in TFT 4096-Color Mode
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TFT 65536-color (16 bpp: R: 5 bits, G: 6 bits, B: 5 bits)
Display Memory
Address 0
Address 1
Address 2
Address 3
LSB
D0
MSB
D31
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0
G0
B0
R1
G1
B1
Address 7
Address 4
Address 5
Address 6
LSB
D0
MSB
D31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
R2
G2
B2
R3
G3
B3
16-bit TFT
LD0 0(R0) → 16(R1) …
LD1 1(R0) → 17(R1) …
LD2 2(R0) → 18(R1) …
LD3 3(R0) → 19(R1) …
LD4 4(R0) → 20(R1) …
LD5 5(G0) → 21(G1) …
LD6 6(G0) → 22(G1) …
LD7 7(G0) → 23(G1) …
LD8 8(G0) → 24(G1) …
LD9 9(G0) → 25(G1) …
LD10 10(G0) → 26(G1) …
LD11 11(B0) →27(B1) …
LD12 12(B0) → 28(B1) …
LD13 13(B0) → 29(B1) …
LD14 14(B0) → 31(B1) …
LD15 15(B0) → 32(B1) …
Figure 3.19.9 Memory Map Image and Data Output in TFT 65536-Color Mode
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TFT 262144-/16777216-color (24 bpp: R: 8 bits, G: 8 bits, B: 8 bits)
Display Memory
Address 0
Address 1
Address 2
Address 3
LSB
D0
MSB
D31
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0
Address 4
G0
B0
R1
Address 5
Address 6
Address 7
LSB
D0
MSB
D31
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
G2
B2
R3
G3
24-bit TFT
18-bit TFT
LD18 0(R0) → 24(R1) …
LD19 1(R0) → 25(R1) …
LD0 2(R0) → 26(R1) …
LD1 3(R0) → 27(R1) …
LD2 4(R0) → 28(R1) …
LD3 5(R0) → 29(R1) …
LD4 6(R0) → 30(R1) …
LD5 7(R0) → 31(R1) …
LD20 8(G0) → 32(G1) …
LD21 9(G0) → 33(G1) …
LD6 10(G0) → 34(G1) …
LD7 11(G0) → 35(G1) …
LD8 12(G0) → 36(G1) …
LD9 13(G0) → 37(G1) …
LD10 14(G0) → 38(G1) …
LD11 15(G0) → 39(G1) …
LD22 16(B0) → 40(B1) …
LD23 17(B0) → 41(B1) …
LD12 18(B0) → 42(B1) …
LD13 19(B0) → 43(B1) …
LD14 20(B0) → 44(B1) …
LD15 21(B0) → 45(B1) …
LD16 22(B0) → 46(B1) …
LD17 23(B0) → 47(B1) …
LD0
LD1
LD2
LD3
LD4
LD5
2(R0) →26(R1) …
3(R0) →27(R1) …
4(R0) →28(R1) …
5(R0) →29(R1) …
6(R0) →30(R1) …
7(R0) →31(R1) …
LD6
LD7
LD8
LD9
LD10
LD11
10(G0) → 34(G1) …
11(G0) → 35(G1) …
12(G0) → 36(G1) …
13(G0) → 37(G1) …
14(G0) → 38(G1) …
15(G0) → 39(G1) …
LD12
LD13
LD14
LD15
LD16
LD17
18(B0) → 42(B1) …
19(B0) → 43(B1) …
20(B0) → 44(B1) …
21(B0) → 45(B1) …
22(B0) → 46(B1) …
23(B0) → 47(B1) …
Note: The display RAM data format for 18 bpp is the same as that for 24 bpp. When 18 bpp is used, the least significant
bit should be disabled by port setting.
Figure 3.19.10 Memory Map Image and Data Output in TFT 262144-/16777216-Color Mode
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7. LDIV Signal
The <LDINV> and <AUTOINV> bits of the LCDMODE1 register are used to control
the LDIV signal as well as data output. The LDIV signal indicates the inversion of all
the LD bus signals.
When LCDMODE1<LDINV>=1, all display data is forcefully inverted and the LDIV
signal is also driven high. When LCDMODE1<AUTOINV>=1, the data that has just
been transferred and the data to be transferred next are compared. If there are more
changed bits than unchanged bits (for example, 7 or more bits are changed when using
a 12-bit bus, and 5 or more bits are changed when using a 8-bit bus), the data is
inverted and the LDIV signal is also driven high. This function can be used with TFT
source drivers having the data inversion function to reduce radiated noise and power
consumption due to high-speed data inversion.
If <LDINV> and <AUTOINV> are both set to “1” at the same time, <LDINV> is given
priority and <AUTOINV> is disabled.
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3.19.4 Interrupt Function
The LCDC has two types of interrupts.
One is generated synchronous with the LLOAD signal and the other is generated
synchronous with the LLOAD signal that is output immediately after the LVSYNC
signal.
LCDMODE1<INTMODE> is used to switch between these two types of interrupts.
LVSYNC
LHSYNC
LLOAD
D15-0(VRAM Read)
Interrupt request
LCDMODE1<INTMODE>=0
Interrupt request
LCDMODE1<INTMODE>=1
When LCDMODE1<INTMODE>=0, an interrupt request is generated at the start of
each VRAM read before the LLOAD generates (once in each LLOAD period).
When LCDMODE1<INTMODE>=1, an interrupt request is generated at the start of
VRAM read before the first LLOAD generates (once in each LVSYNC period).
**The interrupt request generates when reading the data from VRAM at once. Since
reading from VRAM is executed by DMA with bus request to the CPU, DMA operation
is given priority. Thus CPU accepts interrupt immediately after reading the data from
VRAM.
LCDMODE1 Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
LDC2
R/W
0
LDC1
R/W
0
LDC0
R/W
0
LDINV
AUTOINV
INTMODE
FREDGE
SCPW2
LCDMODE1
(0281H)
R/W
0
R/W
0
R/W
0
W
0
W
0
Data rotation function
LD bus
inversion
Auto bus
inversion
Interrupt
selection
LFR edge
LD bus
Trance
(Supported for 64K-color: 16 bps
only)
0: LHSYNC Speed
Front Edge
000: Normal
100: 90-degree 0: Normal
0: Disable
1: Enable
(Valid only
for TFT)
0:LLOAD
Function
001: Horizontal flip 101: Reserved 1: Invert
1:LVSYNC 1:LHSYNC 0: normal
Rear Edge 1: 1/3
010: Vertical flip
011: Vertical &
horizontal flip
110: Reserved
111: Reserved
Note: The LCDMODE1<INTMODE> setting must not be changed while the LCDC is operating. Be sure to set
LCDCTL0<START> to “0” to stop the LCDC operation before changing the interrupt setting.
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3.19.5 Special Functions
3.19.5.1 PIP (Picture in Picture) Function
The TMP92CZ26A includes a PIP (Picture in Picture) function that allows a different
screen to be displayed over the screen currently being displayed on the LCD.
The PIP function manages the address space of display memory by dividing it into
“main screen” and “sub screen”. For the main screen, the display size and start address
are specified as in the case of the normal screen display. For the sub screen, the display
size and start address are also specified for determining the position and size of the sub
screen.
When the HOT point (upper-left corner) and segment/common size are set for the sub
screen and the PIP function is enabled by setting LCDCTL0 <PIPE> to “1”, the sub
screen is displayed over the main screen.
HOT Point
LCD Panel (PIP OFF)
LCD Panel (PIP ON)
Main Area
Start Address
Note: This is just an image of
memory map and doesn’t describe
the image of bit map.
Sub Area
Start Address
VRAM Memory Map
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The table below shows the HOT point locations that can be specified.
*VRAM Access
HOT_Point(Y_dir)
HOT_Point(X_dir)
Monochrome display
4-grayscale display
16-grayscale display
64-grayscale display
256-color display
16bit
32bit
16bit
32bit
16bit
32bit
16bit
32bit
16bit
32bit
16bit
32bit
16bit
32bit
16bit
32bit
16bit
32bit
In units of 16 dots
In units of 32 dots
In units of 8 dots
In units of 16 dots
In units of 4 dots
In units of 8 dots
In units of 8 dots
In units of 16 dots
In units of 2 dots
In units of 4 dots
In units of 4 dots
In units of 8 dots
In units of 1 dots
In units of 2 dots
In units of 8 dots
In units of 16 dots
In units of 2 dots
In units of 4 dots
In units of
1 line
4K-color display
64K-color display
STN
256K-color display
TFT
256k/16M-color display
Note 1: The “VRAM Access” colomn shows the bus size for accessing the display RAM. When external RAM is
used, the bus size depends on the bit width of the external RAM to be used. When the internal RAM is
used VRAM is always accessed via a 32-bit bus.
Note 2: The same RAM must be used for both the main and sub areas.
The table below shows the HOT point segment and common sizes that can be
specified.
*VRAM Access
Segment size
Common size
Minimum size
units
Monochrome display
4-grayscale display
16-grayscale display
64-grayscale display
256-color display
16bit
32bit
16bit
32bit
16bit
32bit
16bit
32bit
16bit
32bit
16bit
32bit
16bit
32bit
16bit
32bit
16bit
32bit
32 dots
64 dots
16 dots
32 dots
8 dots
In units of 16 dots
In units of 32 dots
In units of 8 dots
In units of 16 dots
In units of 4 dots
In units of 8 dots
In units of 8 dots
In units of 16 dots
In units of 2 dots
In units of 4 dots
In units of 4 dots
In units of 8 dots
In units of 1 dots
In units of 2 dots
In units of 8 dots
In units of 16 dots
In units of 2 dots
In units of 4 dots
16 dots
16 dots
32 dots
4 dots
In units of
1 line
8 dots
4K-color display
8 dots
16 dots
2 dots
64K-color display
4 dots
STN
16 dots
32 dots
4 dots
256K-color display
TFT
256k/16M-color display
8 dots
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LCD Main Area Start Address Register
7
6
5
4
3
2
1
0
LSAML
(02A0H)
bit Symbol
Read/Write
After reset
LMSA7
R/W
0
LMSA6
R/W
0
LMSA5
R/W
0
LMSA4
R/W
0
LMSA3
R/W
0
LMSA2
R/W
0
LMSA1
R/W
0
Function
LCD main area start address (A7-A0)
7
LMSA15
R/W
6
LMSA14
R/W
5
LMSA13
R/W
4
LMSA12
R/W
3
LMSA11
R/W
2
LMSA10
R/W
1
LMSA9
R/W
0
0
LMSA8
R/W
0
LSAMM
(02A1H)
bit Symbol
Read/Write
After reset
0
0
0
0
0
0
Function
LCD main area start address (A15-A8)
7
6
5
4
3
2
1
0
LSAMH
(02A2H)
bit Symbol
Read/Write
After reset
LMSA23
R/W
0
LMSA22
R/W
1
LMSA21
R/W
0
LMSA20
R/W
0
LMSA19
R/W
0
LMSA18
R/W
0
LMSA17
R/W
0
LMSA16
R/W
0
Function
LCD main area start address (A23-A16)
LCD Sub Area Start Address Register
7
6
5
4
3
2
1
0
LSASL
(02A4H)
bit Symbol
Read/Write
After reset
LSSA7
R/W
0
LSSA6
R/W
0
LSSA5
R/W
0
LSSA4
R/W
0
LSSA3
R/W
0
LSSA2
R/W
0
LSSA1
R/W
0
Function
LCD sub area start address (A7-A1)
7
LSSA15
R/W
0
6
LSSA14
R/W
0
5
LSSA13
R/W
0
4
LSSA12
R/W
0
3
LSSA11
R/W
0
2
LSSA10
R/W
0
1
LSSA9
R/W
0
0
LSSA8
R/W
0
LSASM
(02A5H)
bit Symbol
Read/Write
After reset
Function
LCD sub area start address (A15-A8)
7
6
5
4
3
2
1
0
LSASH
(02A6H)
bit Symbol
Read/Write
After reset
LSSA23
R/W
0
LSSA22
R/W
1
LSSA21
R/W
0
LSSA20
R/W
0
LSSA19
R/W
0
LSSA18
R/W
0
LSSA17
R/W
0
LSSA16
R/W
0
Function
LCD sub area start address (A23-A16)
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LCD Sub Area HOT Point Register (X-dir)
7
SAH7
R/W
0
6
SAH6
R/W
0
5
SAH5
R/W
0
4
SAH4
R/W
0
3
SAH3
R/W
0
2
SAH2
R/W
0
1
SAH1
R/W
0
0
SAH0
R/W
0
LSAHX
(02A8H)
bit Symbol
Read/Write
After reset
Function
LCD sub area HOT point (7-0)
7
6
5
4
3
2
1
SAH9
R/W
0
0
SAH8
R/W
0
(02A9H)
bit Symbol
Read/Write
After reset
Function
LCD sub area HOT point (9-8)
LCD Sub Area HOT Point Register (Y-dir)
7
SAHY7
R/W
0
6
SAHY6
R/W
0
5
SAHY5
R/W
0
4
SAHY4
R/W
0
3
SAHY3
R/W
0
2
SAHY2
R/W
0
1
SAHY1
R/W
0
0
SAHY0
R/W
0
LSAHY
(02AAH)
bit Symbol
Read/Write
After reset
Function
LCD sub area HOT point (7-0)
7
6
5
4
3
2
1
0
(02ABH)
bit Symbol
Read/Write
After reset
SAHY8
R/W
0
LCD sub
area HOT
point
Function
(9-8)
Note: The HOT point should be set in units of the specified number of dots, which is determined by the display
color mode and display RAM access data bus width.
LCD Sub Area Display Segment Size Register
7
SAS7
R/W
0
6
SAS6
R/W
0
5
SAS5
R/W
0
4
SAS4
R/W
0
3
SAS3
R/W
0
2
SAS2
R/W
0
1
SAS1
R/W
0
0
SAS0
R/W
0
LSASS
(02ACH)
bit Symbol
Read/Write
After reset
Function
LCD sub area segment size (7-0)
7
6
5
4
3
2
1
SAS9
R/W
0
0
SAS8
R/W
0
(02ADH)
bit Symbol
Read/Write
After reset
Function
LCD sub area segment size (9-8)
Note: The segment size should be set in units of the specified number of dots, which is determined by the display
color mode and display RAM access data bus width.
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LCD Sub Area Display Common Size Register
7
SAC7
R/W
0
6
SAC6
R/W
0
5
SAC5
R/W
0
4
SAC4
R/W
0
3
SAC3
R/W
0
2
SAC2
R/W
0
1
SAC1
R/W
0
0
SAC0
R/W
0
LSACS
(02AEH)
bit Symbol
Read/Write
After reset
Function
LCD sub area common size (7-0)
7
6
5
4
3
2
1
0
SAC8
R/W
0
(02AFH)
bit Symbol
Read/Write
After reset
Function
LCD sub area common size (8)
Note: The common size should be set in units of 1 line.
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3.19.5.2
Display Data Rotation Function
When display RAM data is output to the LCD driver (LCDD), the data output
direction can be automatically rotated by hardware to meet the specifications of the
LCDD (or LCD module) to be used.
Table 3.19.2 Operation Conditions
Item
Vertical/Horizontal Flip Function
90-Degree Rotation Function
320×240 →240 × 320
64K colors (16 bpp)
TFT, STN
Display size
Color mode
320 × 240
64K colors (16 bpp)
TFT, STN
Supported LCDD
Display RAM
Internal RAM, external SRAM
Internal RAM, external SRAM
1. Horizontal and Vertical Flip Function
Display RAM image
Normal display
Horizontally flipped
Vertically flipped
Horizontally and vertically flipped
The display RAM image shown above uses the data scan method for the normal
display screen so that data is read from the display RAM and written to the LCDD from
left to right and top to bottom.
The data on the LCD screen appears as “horizontally flipped” if data is read from the
display RAM from left to right and top to bottom and written to the LCDD from right to
left and top to bottom.
Likewise, the data on the LCD screen appears as “vertically flipped” if data is written
to the LCDD from left to right and bottom to top, or as “horizontally and vertically
flipped” if the data is written to the LCDD from right to left and bottom to top.
The horizontal and vertical flip function enables the output of display data to meet
the specifications of each LCDD without the need to rearrange the display RAM data.
In other words, the screen display can be flipped horizontally and vertically without
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the need to rewrite the display RAM data.
2. 90-Degree Rotation Function
Display RAM Image (QVGA 320×240)
QVGA (320×240)
Portrait-type QVGA (240×320)
(when this function is used)
The display RAM image above shows typical data of QVGA size (320 segments × 240
commons: landscape type). If the LCDD to be used is of landscape type, the data can be
written to the LCDD without any problem.
If the LCDD to be used is of portrait type (240 segments × 320 commons), the data
cannot be displayed properly.
This function enables the orientation of each display image to be rotated 90 degrees
without the need to change the display RAM data.
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3. Setting Method
The <LDC2:0> bits in the LCDMODE1 register are used to set the display data
rotation function.
LCDMODE1 Register
7
6
5
4
3
2
1
0
bit Symbol
LDC2
LDC1
LDC0
R/W
0
LDINV
R/W
AUTOINV
R/W
INTMODE FREDGE
SCPW2
LCDMODE1
(0281H)
Read/Write
After reset
R/W
0
R/W
0
R/W
0
W
0
W
0
0
0
Data rotation function
LD bus
Auto bus
Interrupt
selection
LFR edge LD bus
Trance
(Supported for 64K-color: 16 bps
only)
inversion inversion
0: LHSYNC Speed
Front Edge
000: Normal
100: 90-degree
0: Disable
1: Enable
(Valid for
TFT only)
0:LLOAD
0: Normal
1: Invert
Function
001: Horizontal flip 101: Reserved
010: Vertical flip 110: Reserved
011: Horizontal and vertical flip
111: Reserved
1:LVSYNC 1:LHSYNC 0: normal
Rear Edge 1: 1/3
Note: The <LDC2:0> setting must not be changed while the LCDC is operating. Be sure to set
LCDCTL0<START> to “0” to stop the LCDC operation before changing <LDC2:0>.
When the horizontal and vertical flip function or 90-degree rotation function is used,
the display RAM start address of main/sub area should be set differently from when
in normal mode, as shown in the table below.
Mode
Setting Point
Display RAM Start Address
Setting Example
Normal
Point A
Point B
Point A
Point B
Point B
00000h
257FEh
00000h
257FEh
257FEh
90-degree rotation
Horizontal flip
Vertical flip
Horizontal and vertical flip
How to calculate the point B address:
(320×240×16/8)- 2 = 153600 - 2
= 153598 [decimal]
= 257FE [hex]
Point A
Point B
Display RAM Image (QVGA 320 × 240)
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3.19.5.3
Considerations for Using the LCDC
1． If the operation mode is changed while the LCDC is operating, a maximum of
one frame may not be displayed properly. Although this degree of disturbance
does not normally pose any problem (e.g. no response on LCD, display not
visible to human eyes), the actual operation largely depends on the conditions
such as the LCD driver, LCD panel, and frame frequency to be used. It is
therefore recommended that operation checks be performed under the actual
conditions.
2． The LCDMODE1<LDC2:0> setting must not be changed while the LCDC is
operating. Be sure to set LCDCTL0<START> to “0” to stop the LCDC operation
before changing <LDC2:0>.
3． The LCDC obtains the bus from the CPU when it has some operation to
perform. Since the TMP92CZ26A includes other units that act as bus masters
such as HDMA and SDRAMC, it is necessary to estimate the bus occupancy
rate of each bus master in advance. For details, see the chapter on HDMA.
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3.19.6 Setting Example
STN
•
COM001
240COM×80SEG
LCD (Color Panel)
COM240
COM001
T6C13B
TMP92CZ26
(240-row Driver)
VDD
VSS
VDD
O001
VSS
DIR
TEST
Di7-Di0
DUAL
240COM×240SEG
LCD (Monochrome Panel)
SCP
S/C
VCCL/R, V0L/R,
V1L/R, V4L/R,
V5L/R
O240
COM240
LVSYNC
LCP0
LHSYNC
SCP
LP
LFR
port
FR
/DSPOF
DI7～DI0
LD7～LD0
EIO1
EIO2
open
VDD
VSS
VSS
T6C13B
(240-column Driver)
Note: The LCD drive power for LCD display must be supplied from an external circuit.
Figure 3.19.11 STN-Type LCD Driver Connection Example
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•
TFT
JBT6L78-AS
(162-gate Driver)
VDD
VSS
VDD
U/D
TEST1
TEST2
VSS
92CZ26
G1
G1
160SEG×3(RGB)×162COM
LCD
LGOE2-0
OE3-1
G162
G162
LVSYNC
CPH
LOAD
DI/O
LCP0
LLOAD
CPH
LOAD
open
LFR
LHSYNC
DO/I
DO/I
DI/O
DA5-2
DA5-0
DB5-0
DC5-0
LD23~LD0
DB5-2
DC5-2
Control Signal
D15～D0
A0～A23
VDD
VSS
Display Memory
(SDRAM or SRAM)
JBT6L77-AS×2
(80×RGB Source Driver)
Note: The LCD drive power for LCD display must be supplied from and external circuit.
Figure 3.19.12 TFT-Type LCD Driver Connection Example
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3.20 Touch Screen Interface (TSI)
The TMP92CZ26A has an interface for 4-terminal resistor network touch-screen.
This interface supports two procedures: an X/Y position measurement and touch detection.
Each procedure is performed by setting the TSI control register (TSICR0 and TSICR1) and
using an internal AD converter.
3.20.1 Touch-Screen Interface Module Internal/External Connection
TMP92CZ26A
Y-
MY
Touch
Screen
X+
MX
PY
PX
X-
Y+
External Capacitors
Figure 3.20.1External connection of TSI
Touch screen control
AVCC
AVSS
PXEN
PYEN
Dec.
SPX
SPY
MXEN
MYEN
INT4
INT4
P97
PTST
(PY)
P96/INT4
(PX)
TSI7
PXD (typ.50kΩ)
AD converter
PG3/AN3
(MY)
AN3
AN2
PG2/AN2
(MX)
AVCC
AVSS
SMY
SMX
VREFH
VREFL
VREFH
VREFL
Figure 3.20.2 Internal block diagram of TSI
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3.20.2 Touch Screen Interface (TSI) Control Register
TSI control register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
TSI7
R/W
0
INGE
R/W
0
PTST
TWIEN
R/W
0
PYEN
R/W
0
PXEN
R/W
0
MYEN
R/W
0
MXEN
TSICR0
(01F0H)
R
0
R/W
0
0: Disable Input gate Detection INT4
SPY
SPX
SMY
SMX
1: Enable control of condition
Port 96,97 0: no
interrupt
0 : OFF
1 : ON
0 : OFF
1 : ON
0 : OFF
1 : ON
0 : OFF
1 : ON
Function
control
0: Enable
touch
0: Disable
1: Enable
1: Disable 1: touch
PXD (internal pull-down resistor) ON/OFF setting
<PXEN>
0
1
<TSI7>
OFF
ON
OFF
OFF
0
1
De-bounce time setting register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
DBC7
DB1024
R/W
0
DB256
R/W
0
DB64
R/W
0
DB8
R/W
0
DB4
R/W
0
DB2
R/W
0
DB1
R/W
0
TSICR1
(01F1H)
R/W
0
0: Disable
1: Enable
1024
256
64
8
4
2
1
De-bounce time is set by “(N*64-16) / fSYS”-formula.
Function
“N” is sum of number which is set to “1” in bit6 to bit 0. Note3:
Note1: Since an internal clock is used for de-bounce circuit, when IDLE1, STOP mode or PCM condition, the de-bounce
circuit don’t operate and also interrupt which through this circuit is not generated. When IDLE1, STOP mode or PCM
condition, set this circuit to disable (Write “0” to TSICR1<DBC7>) before entering HALT state.If de-bounce time is set
to “0”, signal is received after counting the 6-system clock (f
) from the condition that this circuit is set to disable.
SYS
Note2: During converting the analog input-data by using AD converter, the current flow to the normal C-MOS input-gate.
Therefore, provide its current by setting TSICR0<INGE>.If the middle voltage is inputted, cut the input-signal to
C-MOS logic (P96,P97) by settig this bit.
Note3: TSICR0<PTST> is that confirming initial pen-touch. When the input-signal to C-MOS logic is blocked by
TSICR0<INGE>, this bit is always “1”. Please be careful.
Ex:
TSICR1=95H →N = 64 + 4 + 1 = 69
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3.20.3 Touch detection procedure
A Touch detection procedure shows procedure until a pen is touched by the screen and it is
detected.
By touching, TSI generates interrupt (INT4) and this procedure will terminate. After an X/Y
position measuring procedure is terminated, return to this procedure and wait for next touch.
When touch is waiting, set SPY-switch to ON, and set other 3 switches (SMY, SPX and SMX)
to OFF. The pull-down resistor that is connected to P96/INT4/PX pin is set to ON.
During waiting a touch, the internal resistors of X and Y-direction are not connected.
Therefore, P96/INT4/PX pin’s level is set to Low by internal pull-down register (PXD) and INT4
isn’t generated.
When pen was touched, the internal resistors of X and Y-direction are connected. Therefore,
P96/INT4/PX pin’s level is set to High by internal pull-down register (PXD) and INT4 is
generated.
And the de-bounce-circuit is prepared for avoiding that INT4 of plural times generate by
one-time touch. When de-bounce-time is set to TSICR1 register, the pulse of time less than its
time is ignored.
The circuit detects the rising of signal, counts-up the time of the counter which is set, after
count, receive the signal internal. During counting, when the signal is set to Low, counter is
cleared. And the state become to state of waiting a rising edge.
TSICR1
TSICR0<TWIEN>, IIMC<I4EDGE>, P9FC<P96F>
Enables INT4,
And select the Rising
De-bounce circuit
INT4
P96/INT4 pin
or Falling of INT4
F/F
TSICR0
<PTST>
Figure 3.20.3 Block diagram of de-bounce circuit
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P96/INT4 pin
Reset the counter for de-bounce time
Start the counter for de-bounce time
de-bounce time de-bounce time
de-bounce time
INT4
INT4 is generated by matching counter and
specified de-bounce time.
After pen is de-touched, INT4 can be issued
again.
INT4 isn’t generated by matching counter and specified
de-bounce time because of it is an edge-type interrupt.
Figure 3.20.4 Timing diagram of de-bounce circuit
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3.20.4 X/Y position measuring procedure
In the INT4 routine, execute an X/Y position measuring procedure like below.
<X position measurement>
At first, set both SPX, SMX-switches to ON, and set SPY, SMY-switches to OFF.
By this setting, analog-voltage which shows the X-position will be inputted to PG3/MY/AN3
pin.
The X-position can be measured by converting this voltage to digital code with AD converter.
<Y position measurement>
Next, set both SPY, SMY-switches to ON, and set SPX, SMX-switches to OFF.
By this setting, analog-voltage that shows the Y-position will be inputted to PG2/MX/AN2
pin.
The Y-position can be measured by converting this voltage to digital code with AD converter.
The above analog-voltage that is inputted to AN3 or AN2-pin can be calculated. It is a ratio
between resistance-value in TMP92CZ26A and resistance-value in touch screen shown in
Therefore, if the pen touches a corner area on touch screen, analog-voltage will not be to 3.3V
or 0.0V. As a notice, since each resistor has an uneven, consider about it. And it is recommended
that an average code among a few times AD conversion will be adopted as a correct code.
[Calculation for analog input voltage to AN2 or AN3-pin : (E1)]
AVCC=3.3V
SPY (SPX)
ON-resistor: Rpy (Rpx)
typ.10Ω
E1 = ((R2+Rmy) / (Rpy+Rty+Rmy)) × AVCC [V]
Ex.) The case of AVCC=3.3V, Rpy=Rmy=10Ω, R1=400Ω and
R2=100Ω
E1 = ((100+10) / (10+400+100+10) × 3.3
R1
R2
Touch screen resistor
: Rty (Rtx)
A value depends on
a touch screen.
= 0.698V
Note1: A Y-position can be calculated in the same way though above
formula is for X-position.
Note2: Rty = R1+R2.
AN2 (AN3)-pin
Touch-point
SMY (SMX)
ON-resistor: Rmy (Rmx)
typ.10Ω
Figure 3.20.5 Calculation analog voltage
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3.20.5 Flow chart for TSI
(2) X/Y Position
Measurement Procedure
(1) Touch Detection Procedure
Main Routine:
INT4 Routine:
TSICR0←98H
TSICR1←XXH (voluntary)
(a)
<X position measurement>
･TSICR0←C5H
･AD conversion for AN3
(b)
(c)
･Store the result
Execute Main Routine
<Y position measurement>
･TSICR0←CAH
･AD conversion for AN2
･Store the result
Execute an operation
By using X/Y-position
Yes
Still touched?
TSICR0<PTST> = 1?
No
Return to Main Routine
Figure 3.20.6 Flow chart for TSI
Following pages explain each circuit condition of (a), (b) and (c) in above flow chart.
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(a) Main routine (condition of waiting INT4 interrupt)
(p9fc)<P96F>, <P97F>= “1”
(inte34)
:
:
Set P96 to int4/PX, set P97 to PY
Set interrupt level of INT4
(tsicr0)=98h
ei
:
:
Pull-down resistor on, SPY on, Interrupt-set<TWIEN>
Enable interrupt
TMP92CZ26A
Touch screen control
AVCC
PXEN
PYEN
MXEN
MYEN
INT4
ON
SPX
Dec.
SPY
(PY/P97)
PTST
Y+
Touch
Screen
(PX/P96/INT4)
X+
ON
TSI7
X-
PXD (typ.50kΩ)
(MY/PG3)
AD Converter
Y-
AN3
AN2
(MX/PG2)
AVCC
AVSS
SMY
SMX
VREFH
VREFL
VREFH
VREFL
AVSS
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(b) X position measurement (Start AD conversion)
(tsicr0)=c5h
:
:
Set SMX, SPX to ON. Set the input gate of P97, P96 to OFF.
(admod1)=b0h
Set to AN3.
(admod0)=08h
:
Start AD conversion.
TMP92CZ26A
Touch screen control
AVCC
PXEN
PYEN
MXEN
ON
SPX
Dec.
SPY
(PY/P97)
PTST
MYEN
INT4
Y+
Touch
Screen
(PX/P96/INT4)
(MY/PG3)
TSI7
X-
X+
PXD (typ.50kΩ)
AD Converter
Y-
AN3
AN2
(MX/PG2)
AVCC
AVSS
SMY
SMX
ON
VREFH
VREFL
VREFH
VREFL
AVSS
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(c) Y position measurement(Start AD conversion)
(tsicr0)=cah
:
:
:
Set SMX, SPX to ON. Set the input gate of P97, P96 to OFF.
(admod1)=a0h
(admod0)=08h
Set to AN2.
Start AD conversion.
TMP92CZ26A
Touch screen control
AVCC
PXEN
PYEN
MXEN
MYEN
INT4
ON
Dec.
SPX
SPY
(PY/P97)
PTST
Y+
Touch
(PX/P96/INT4)
Screen
TSI7
X-
X+
PXD (typ.50kΩ)
(MY/PG3)
(MX/PG2)
AD Converter
AN3
AN2
Y-
AVCC
AVSS
SMY
SMX
ON
VREFH
VREFL
VREFH
VREFL
AVSS
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3.20.6 Note
1. De-bounce circuit
The system clock of CPU is used in de-bounce circuit. Therefore, de-bounce circuit is not
operated when clock is not supplied to CPU (IDLE1, STOP mode or PCM mode). And, an
interrupt which through the de-bounce circuit is not generated.
When started from IDLE1, STOP or PCM mode by using TSI, set the de-bounce circuit to
disable before a condition become to HALT or PCM mode. (TSICR1<DBC7>="0")
2. Port setting
During conversion the middle voltage of 0V~AVcc by using AD converter, the middle
voltage is inputted to a normal C-MOS input-gate (P96 and P97), too.
Therefore, provide the flow current for P96 and P97 by using TSICR0<INGE>. In this case
(TSICR0<INGE>="1"), when the input to C-MOS logic is cut, TSICR0<PTST> for confirming
a first pen touch is always set to “1”. Please be careful.
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3.21 Real time clock (RTC)
3.21.1 Function description for RTC
1) Clock function (hour, minute, second)
2) Calendar function (month and day, day of the week, and leap year)
3) 24 or 12-hour (AM/PM) clock function
4) +/- 30 second adjustment function (by software)
5) Alarm function (Alarm output)
6) Alarm interrupt generate
3.21.2 Block diagram
16 Hz Clock
32 KHz
Divider
Clock
1 Hz Clock
Alarm Register
ALARM
INTRTC
Alarm
Selector
Carry hold
(1s)
Comparator
Clock
ALARM
Address
Bus
Internal data bus
Adjust
R/W Control
D0~D7
RD WR
Address
Figure 3.21.1 RTC block diagram
Note1: The Christian era year column:
This product has year column toward only lower two columns. Therefore the next year
in 99 works as 00 years. In system to use it, please manage upper two columns with
the system side when handle year column in the Christian era.
Note2: Leap year:
A leap year is the year, which is divisible with 4, but the year, which there is exception,
and is divisible with 100, is not a leap year. However, the year is divisible with 400, is a
leap year. But there is not this product for the correspondence to the above exception.
Because there are only with the year that is divisible with 4 as a leap year, please cope
with the system side if this function is problem.
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3.21.3 Control registers
Table 3.21.1 PAGE 0 (Timer function) registers
Symbol Address Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Function
Read/Write
SECR
MINR
1320H
1321H
40 sec 20 sec
40 min 20 min
20 hours/
10 sec
10 min
8 sec
8 min
4 sec
4 min
2 sec
2 min
1 sec
1 min
Second column
Minute column
R/W
R/W
R/W
HOURR 1322H
10 hours
8 hours
4 hours
W2
2 hours
W1
1 hour
W0
Hour column
PM/AM
DAYR 1323H
Day of the week
column
R/W
DATER 1324H
MONTHR 1325H
YEARR 1326H
Day 20
Day 10
Oct.
Day 8
Aug.
Day 4
Apr.
Day 2
Feb.
Day 1
Jan.
Day column
R/W
R/W
R/W
Month column
Year column
Year 80 Year 40 Year 20 Year 10
Year 8
Year 4 Year 2 Year 1
(Lower two columns)
PAGER 1327H
RESTR 1328H
PAGE
setting
PAGE register
W, R/W
W only
Interrupt
enable
Adjustment Clock
Alarm
function
enable enable
1Hz
16Hz
Clock
reset
Alarm
reset
Always write “0”
Reset register
enable enable
Note:
As for SECR, MINR, HOURR, DAYR, MONTHR, YEARR of PAGE0, current state is read read it.
Table 3.21.2 PAGE1 (Alarm function) registers
Symbol Address Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Function
Read/Write
SECR
MINR
1320H
1321H
R/W
R/W
R/W
40 min 20 min
20 hours/
10 min
8 min
4 min
4 hours
W2
2 min
2 hours
W1
1 min
1 hour
W0
Minute column
Hour column
HOURR 1322H
10 hours
8 hours
PM/AM
DAYR 1323H
Day of the week
column
R/W
DATER 1324H
MONTHR 1325H
YEARR 1326H
PAGER 1327H
Day 20
Day 10
Day 8
Day 4
Day 2
Day 1
24/12
Day column
24-hour clock mode
Leap-year mode
R/W
R/W
LEAP1 LEAP0
PAGE
R/W
PAGE register
W, R/W
Interrupt
enable
Adjustment Clock
function
Alarm
enable enable
setting
RESTR 1328H
1Hz
16Hz
W only
Clock
reset
Alarm
reset
Always write “0”
Reset register
enable enable
Note:
As for SECR, MINR, HOURR, DAYR, MONTHR, YEARR of PAGE1, current state is read read it.
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3.21.4 Detailed explanation of control register
RTC is not initialized by reset. Therefore, all registers must be initialized at the
beginning of the program.
(1) Second column register (for PAGE0 only)
7
6
5
4
3
2
1
0
SECR
(1320H)
Bit symbol
Read/Write
After reset
Function
SE6
SE5
SE4
SE3
R/W
SE2
SE1
SE0
Undefined
"0" is read.
40 sec.
column
20 sec.
column
10 sec.
column
8 sec.
column
4 sec.
column
2 sec.
column
1 sec.
column
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0 sec
1 sec
2 sec
3 sec
4 sec
5 sec
6 sec
7 sec
8 sec
9 sec
10 sec
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
:
:
:
:
:
0
0
0
1
1
0
1
0
0
0
0
0
1
0
19 sec
20 sec
0
0
1
1
0
1
1
0
0
0
0
0
1
0
29 sec
30 sec
0
1
1
0
1
0
1
0
0
0
0
0
1
0
39 sec
40 sec
1
1
0
0
0
1
1
0
0
0
0
0
1
0
49 sec
50 sec
1
0
1
1
0
0
1
59 sec
Note: Do not set the data other than showing above.
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(2) Minute column register (for PAGE0/1)
7
6
5
4
3
2
1
0
MINR
(1321H)
Bit symbol
Read/Write
After reset
Function
MI6
MI5
MI4
MI3
R/W
MI2
MI1
MI0
Undefined
"0" is read.
40 min,
column
20 min,
column
10 min,
column
8 min,
column
4 min,
column
2 min,
column
1 min,
column
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0 min
1 min
2 min
3 min
4 min
5 min
6 min
7 min
8 min
9 min
10 min
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
:
:
:
:
:
0
0
0
1
1
0
1
0
0
0
0
0
1
0
19 min
20 min
0
0
1
1
0
1
1
0
0
0
0
0
1
0
29 min
30 min
0
1
1
0
1
0
1
0
0
0
0
0
1
0
39 min
40 min
1
1
0
0
0
1
1
0
0
0
0
0
1
0
49 min
50 min
1
0
1
1
0
0
1
59 min
Note: Do not set the data other than showing above.
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(3) Hour column register (for PAGE0/1)
1. In case of 24-hour clock mode (MONTHR<MO0>= “1”)
7
6
5
4
3
2
1
0
HOURR
(1322H)
Bit symbol
Read/Write
After reset
Function
HO5
HO4
HO3
HO2
HO1
HO0
R/W
Undefined
"0" is read.
20 hour
column
10 hour
column
8 hour
column
4 hour
column
2 hour
column
1 hour
column
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0 o’clock
1 o’clock
2 o’clock
0
0
:
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
0
8 o’clock
9 o’clock
10 o’clock
:
:
0
1
1
0
1
0
0
0
0
0
1
0
19 o’clock
20 o’clock
1
0
0
0
1
1
23 時
Note: Do not set the data other than showing above.
2.
In case of 24-hour clock mode (MONTHR<MO0>= “0”)
7
6
5
4
3
2
1
0
HOURR
(1322H)
Bit symbol
Read/Write
After reset
Function
HO5
HO4
HO3
HO2
HO1
HO0
R/W
Undefined
"0" is read.
10 hour
column
8 hour
column
4 hour
column
2 hour
column
1 hour
column
PM/AM
0 o’clock
(AM)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
0
1
1
0
1 o’clock
2 o’clock
0
0
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
9 o’clock
10 o’clock
11 o’clock
0 o’clock
(PM)
1
0
0
0
0
1
1 o’clock
Note: Do not set the data other than showing above.
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(4) Day of the week column register (for PAGE0/1)
7
6
5
4
3
2
1
0
DAYR
(1323H)
Bit symbol
Read/Write
After reset
Function
WE2
WE1
R/W
WE0
Undefined
W1
"0" is read.
W2
W0
0
0
0
0
1
1
1
0
0
1
0
1
0
1
0
Sunday
Monday
0
1
1
0
0
1
Tuesday
Wednesday
Thursday
Friday
Saturday
Note: Do not set the data other than showing
above.
(5) 日桁レジスタ(PAGE0/1)
7
6
5
4
3
2
1
0
DATER
(1324H)
Bit symbol
Read/Write
After reset
Function
DA5
DA4
DA3
DA2
DA1
DA0
R/W
Undefined
Day 8 Day 4
"0" is read.
Day 20
Day 10
Day 2
Day 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
0
0
0
0
1st day
2nd day
3rd day
4th day
:
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
0
1
9th day
10th day
11th day
:
:
0
1
1
0
1
0
0
0
0
0
1
0
19th day
20th day
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
1
0
1
29th day
30th day
31st day
Note1: Do not set the data other than showing above.
Note2: Do not set the day which is not existed. (ex: 30th Feb)
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(6) Month column register (for PAGE0 only)
7
6
5
4
3
2
1
0
MONTHR Bit symbol
MO4
MO4
MO2
R/W
MO1
MO0
(1325H)
Read/Write
After reset
Function
Undefined
4 months
"0" is read.
10 months
8 months
2 months
1 month
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
January
February
March
0
0
1
1
1
1
0
0
0
0
0
April
May
June
July
August
September
October
November
December
Note: Do not set the data other than showing above.
(7) Select 24-hour clock or 12-hour clock (for PAGE1 only)
7
6
5
4
3
2
1
0
MONTHR Bit symbol
MO0
R/W
(1325H)
Read/Write
After reset
Function
Undefined
1: 24-hour
0: 12-hour
"0" is read.
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(8) Year column register (for PAGE0 only)
7
6
5
4
3
2
1
0
YEARR
(1326H)
Bit symbol
Read/Write
After reset
Function
YE7
YE6
YE5
YE4
YE3
YE2
YE1
YE0
R/W
Undefined
80 Years
40 Years
20 Years
10 Years
8 Years
4 Years
2 Years
1 Year
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
:
0
0
0
0
0
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
1
99 years
00 years
01 years
02 years
03 years
04 years
05 years
0
0
0
0
0
0
1
0
0
1
1
0
0
1
99 years
Note: Do not set the data other than showing above.
(9) Leap-year register (for PAGE1 only)
7
6
5
4
3
2
1
0
YEARR
(1326H)
Bit symbol
Read/Write
After reset
Function
LEAP1
LEAP0
R/W
Undefined
00: leap-year
01: one year after leap-year
10: two years after leap-year
11: three years after leap-year
"0" is read.
0
0
1
Current year is leap-year
0
1
1
Current is next year of a leap
year
0
1
Current is two years of a leap
year
Current is three years of a
leap year
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(10) PAGE register (for PAGE0/1)
7
6
5
4
3
2
1
0
PAGER
(1327H)
Bit symbol
Read/Write
After reset
INTENA
R/W
0
ADJUST
W
ENATMR
ENAALM
PAGE
R/W
R/W
Undefined
ALARM
Undefined
Undefined
Read-modify Function
(Note)
TIMER
write
instruction
are
Interrupt
1: Enable
0: Disable
1: Adjust
1: Enable
0: Disable
1: Enable
0: Disable
“0” is read. PAGE
selection
“0” is read.
prohibited
Note:
Pleas keep the setting order below and don’t set same time.
(Set difference time to Clock/Alarm setting and interrupt setting)
(Example) Clock setting/Alarm setting
ld (pager), 0ch
:
:
Clock, Alarm enable
Interrupt enable
ld
(pager), 8ch
0
Select Page0
PAGE
1
Select Page1
0
1
Don’t care
Adjust sec. counter.
When set this bit to “1” the sec. counter become
to “0” when the value of sec. counter is 0 – 29.
And in case that value of sec. counter is 30-59,
min. counter is carried and become sec.
ADJUST
counter to "0". Output Adjust signal during 1
cycle of f
. After being adjusted once, Adjust
SYS
is released automatically.
(PAGE0 only)
(11) Reset register (for PAGE0/1)
7
6
5
4
3
2
1
0
RESTR
(1328H)
Bit symbol
Read/Write
After reset
DIS1Hz
DIS16Hz
RSTTMR
RSTALM
RE3
RE2
RE1
RE0
W
Undefined
Read-modify Function
write
instruction
are
1:Clock
reset
1: Alarm
reset
0: 1 Hz
0: 16 Hz
Always write “0”
prohibited
0
1
Unused
RSTALM
RSTTMR
<DIS1HZ>
Reset alarm register
0
1
Unused
Reset timer register
(PAGER)
<DIS1HZ>
Source signal
<ENAALM>
1
0
1
1
1
0
0
Alarm
1Hz
1
0
16Hz
Others
Output “0”
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3.21.5 Operational description
(1) Reading timer data
There is the case, which reads wrong data when carry of the inside counter happens
during the operation which clock data reads. Therefore please read two times with the
following way for reading correct data.
Start
PAGER<PAGE> = “0” ,
Select PAGE0
Read the clock data
(1st)
Read the clock data
(2nd)
NO
1st data = 2nd data
YES
END
Figure 3.21.2 Flowchart of timer data read
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(2) Timing of INTRTC and Clock data
When time is read by interrupt, read clock data within 0.5s(s) after generating
interrupt. This is because count up of clock data occurs by rising edge of 1Hz pulse
cycle.
ALARM
INTRTC
1s counter
(Internal signal)
0
56
57
58
59
1
2
3
4
1s count UP
(Internal signal)
Figure 3.21.3 Timing of INTRTC and Clock data
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(3) Writing timer data
When there is carry on the way of write operation, expecting data can not be wrote
exactly. Therefore, in order to write in data exactly please follow the below way.
1.
Resetting a divider
In RTC inside, there are 15-stage dividers, which generates 1Hz clock from
32,768 KHz. Carry of a timer is not done for one second when reset this divider. So
write in data at this interval.
Start
PAGER<PAGE> = “0”
Select PAGE0
RESTR<RSTTMR> = “1”
Divider reset
Note)
This period is within
0.5 secound.
Write the clock data
End
Figure 3.21.4 Flowchart of data write
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2.
Disabling the timer
Carry of a timer is prohibited when write “0” to PAGER<ENATMR> and can
prevent malfunction by 1s Carry hold circuit. During a timer prohibited, 1s Carry
hold circuit holds one sec. carry signal, which is generated from divider. After
becoming timer enable state, output the carry signal to timer and revise time and
continue operation. However, timer is late when timer-disabling state continues
for one second or more. During timer disabling, pay attention with system power
is downed. In this case the timer is stopped and time is delayed.
Start
Disable the clock
Note:
This period is within
0.5 secound.
Read the clock data
Enable the clock
End
Figure 3.21.5 Flowchart of Clock disable
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3.21.6 Explanation of the interrupt signal and alarm signal
Can use alarm function by setting of register of PAGE1 and output either of three signals
ALARM
from
pin as follows by write “1” to PAGER<PAGE>. INTRTC outputs 1shot pulse
when the falling edge is detected. RTC is not initializes by RESET. Therefore, when clock or
alarm function is used, clear interrupt request flag in INTC (interrupt controller).
(1) In accordance of alarm register and the timer, output “0”.
(2) Output clock of 1Hz.
(3) Output clock of 16Hz.
(1) In accordance with alarm register and a clock, output “0”
When value of a clock of PAGE0 accorded with alarm register of PAGE1 with a state
of PAGER<ENAALM>= “1”, output “0” to ALARM pin and occur INTRTC.
Follows are ways using alarm.
Initialization of alarm is done by writing in “1” at RESTR<RSTALM>, setting value
of all alarm becomes don’t care. In this case, always accorded with value of a clock and
request INTRTC interrupt if PAGER<ENAALM> is “1”.
Setting alarm min., alarm hour, alarm day and alarm the day week are done by
writing in data at each register of PAGE1.
When all setting contents accorded, RTC generates INTRTC interrupt, if
PAGER<INTENA><ENAALM> is “1”. However, contents (don't care state) which does
not set it up is considered to always accord.
The contents, which set it up once, cannot be returned to don't care state in
independence. Initialization of alarm and resetting of alarm register set to don’t care.
The following is an example program for outputting alarm from ALARM -pin at noon
(PM12:00) every day.
LD
LD
LD
LD
LD
LD
(PAGER), 09H
(RESTR), D0H
(DAYR), 01H
(DATAR),01H
(HOURR), 12H
(MINR), 00H
;
;
;
Alarm disable, setting PAGE1
Alarm initialize
W0
1 day
;
;
;
;
;
Setting 12 o’clock
Setting 00 min
Set up time 31 μs (Note)
Alarm enable
LD
(PAGER), 0CH
(PAGER), 8CH
( LD
Interrupt enable )
When CPU is operated by high frequency oscillation, it may take a maximum of one
clock at 32 kHz (about 30us) for the time register setting to become valid. In the above
example, it is necessary to set 31us of set up time between setting the time register and
enabling the alarm register.
Note: This set up time is unnecessary when you use only internal interruption.
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(2) When output clock of 1Hz
RTC outputs clock of 1Hz to
ALARM
pin by setting up PAGER<ENAALM>= “0”,
RESTR<DIS1HZ>= “0”, <DIS16HZ>= “1”. And RTC generates INTRC interrupt by
falling edge of the clock.
(3) When output clock of 16Hz
ALARM
RTC outputs clock of 16Hz to
pin by setting up PAGER<ENAALM>= “0”,
RESTR<DIS1HZ>= “1”, <DIS16HZ>= “0”. And RTC generates INTRC interrupt by
falling edge of the clock.
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3.22 Melody / Alarm generator (MLD)
TMP92CZ26A contains melody function and alarm function, both of which are output from
the MLDALM pin. Five kind of fixed cycles interrupt is generate by using 15bit counter, which
is used for alarm generator.
Features are as follows.
1) Melody generator
The Melody function generates signals of any frequency (4Hz- 5461Hz) based on low-speed
clock (32.768 KHz) and outputs the signals from the MLDALM pin.
By connecting a loud speaker outside, Melody tone can easily sound.
2) Alarm generator
The Alarm function generates eight kinds of alarm waveform having a modulation frequency
(4096Hz) determined by the low-speed clock (32.768 KHz). And this waveform is able to invert
by setting a value to a register.
By connecting a loud speaker outside, Alarm tone can easily sound.
Five kinds of fixed cycles (1Hz, 2Hz, 64Hz, 512Hz, 8192Hz) INTERRUPT are generated by
using a counter that is used for alarm generator.
This section is constituted as follows.
3.22.1 Block diagram
3.22.2 Control registers
3.22.3 Operational Description
3.22.3.1 Melody generator
3.22.3.2 Alarm generator
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3.22.1 Block Diagram
Reset
[Melody Generator]
Internal data bus
MELFH, MELFL register
Comparator (CP0)
MELOUT
F/F
MELFH
<MELON>
Invert
Stop and Clear
Clear
Low-speed
clock
12bit counter (UC0)
INTALM0 (8192Hz)
INTALM1 (512 Hz)
INTALM2 (64 Hz)
INTALM3 (2 Hz)
INTALM4 (1 Hz)
Edge
detectior
INTALM
15bit conter (UC1)
4096 Hz
ALMINT
<IALM4E:0E>
8bit counter
(UC2)
MELALMC<FC1:0>
MELOUT
Invert
Selector
MLDALM pin
Alarm wave form
generator
ALMOUT
MELALMC
<ALMINV>
MELALMC
<MELALM>
ALM register
[Alarm Generator]
Internal data bus
Reset
Figure 3.22.1MLD Block Diagram
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3.22.2 Control registers
ALM register
7
6
5
4
3
2
1
0
ALM
(1330H)
bit Symbol
Read/Write
After reset
Function
AL8
AL7
AL6
AL5
AL4
AL3
AL2
AL1
R/W
0
0
0
0
0
0
0
0
Setting alarm pattern
MELALMC register
7
FC1
6
FC0
5
ALMINV
R/W
4
−
3
−
2
1
0
MELALM
R/W
MELALMC
(1331H)
bit Symbol
Read/Write
After reset
−
R/W
0
−
R/W
0
R/W
R/W
0
R/W
0
0
0
0
0
Free-run counter
control
Alarm
Always write “0”
Select
Output
Wavefor
m invert
00: Hold
Wavefor
m
Function
01: Restart
10: Clear
1:INVERT
0: Alarm
1: Melody
11: Clear & Start
Note1: MELALMC<FC1> is read always “0”.
Note2: When setting MELALMC register except <FC1:0> during the free-run counter is running, <FC1:0> is kept “01”.
MELFL register
7
6
5
4
3
2
1
0
MELFL
(1332H)
bit Symbol
Read/Write
After reset
Function
ML7
ML6
ML5
ML4
ML3
ML2
ML1
ML0
R/W
0
0
0
0
0
0
0
0
Setting melody frequency (lower 8bit)
MELFH register
7
MELON
R/W
0
6
5
4
3
ML11
2
ML10
1
ML9
0
ML8
MELFH
(1333H)
bit Symbol
Read/Write
After reset
R/W
0
0
0
0
Control
melody
counter
Setting melody frequency(upper 4bit)
Function
0: Stop &
Clear
1: Start
ALMINT register
7
6
5
4
3
2
1
0
ALMINT
(1334H)
bit Symbol
Read/Write
−
IALM4E
IALM3E
IALM2E
IALM1E
IALM0E
R/W
R/W
After reset
0
0
0
0
0
0
Always
1:INTALM4 1:INTALM3 1:INTALM2 1:INTALM1 1:INTALM0
write “0”
Function
(1Hz)
(2Hz)
(64Hz)
enable
(512Hz)
enable
(8192Hz)
enable
enable
enable
Note: INTALM0 to INTALM4 prohibit that set to enable at same time. If setting to enable, set only 1.
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3.22.3 Operational Description
3.22.3.1 Melody generator
The Melody function generates signals of any frequency (4Hz-5461Hz) based on
low-speed clock (32.768KHz) and outputs the signals from the MLDALM pin.
By connecting a loud speaker outside, Melody tone can easily sound.
(Operation)
At first, MELALMC<MELALM> have to be set as “1” in order to select melody waveform
as output waveform from MLDALM. Then melody output frequency has to be set to 12-bit
register MELFH, MELFL.
Followings are setting example and calculation of melody output frequency.
(Formula for calculating of melody waveform frequency)
@fs = 32.768 [kHz]
Melody output waveform
Setting value for melody
f
[Hz] = 32768/ (2 × N + 4)
MLD
N = (16384/ f
) − 2
MLD
(Note: N = 1~4095 (001H~FFFH), 0 is not acceptable)
(Example program)
In case of outputting “A” musical scale (440Hz)
LD
LD
LD
(MELALMC), −−XXXXX1B
(MELFL), 23H
;
;
;
Select melody waveform
N = 16384/440 − 2 = 35.2 = 023H
Start to generate waveform
(MELFH), 80H
(Refer: Basic musical scale setting table)
Scale
Frequency
[Hz]
Register
Value: N
C
D
E
F
264
297
330
352
396
440
495
528
03CH
035H
030H
02DH
027H
023H
01FH
01DH
G
A
B
C
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3.22.3.2
Alarm generator
The Alarm function generates eight kinds of alarm waveform having a modulation
frequency 4096Hz determined by the low-speed clock (32.768 KHz). And this waveform is
reversible by setting a value to a register.
By connecting a loud speaker outside, Alarm tone can easily sound.
Five kind of fixed cycles (1Hz, 2Hz, 64Hz, 512Hz, 8192Hz) interrupt be generate by using
a counter which is used for alarm generator.
(Operation)
At first, MELALMC<MELALM> have to be set as “0” in order to select alarm waveform
as output waveform from MLDALM. Then “10” be set on MELALMC<FC1:0> register, and
clear internal counter. Finally alarm pattern has to be set on 8-bit register of ALM. If it is
inverted output-data, set <ALMINV> as invert.
Followings are example program, setting value of alarm pattern and waveform of each
setting value.
(Setting value of alarm pattern)
Setting value
for ALM
Alarm waveform
register
00H
01H
02H
04H
08H
10H
20H
40H
80H
Other
“0” fixed
AL1 pattern
AL2 pattern
AL3 pattern
AL4 pattern
AL5 pattern
AL6pattern
AL7 pattern
AL8 pattern
Undefined
(Do not set)
(Example program)
In case of outputting AL2 pattern (31.25ms/8 times/1sec)
LD
(MELALMC), C0H
;
;
;
Set output alarm waveform
Free-run counter start
Set AL2 pattern, start
LD
(ALM), 02H
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Example: Waveform of alarm pattern for each setting value: not invert)
AL1 pattern
(Continuous output)
Modulation frequency (4096 Hz)
8
1
2
1
AL2 pattern
(8 times/1 sec)
31.25 ms
1
1 秒
AL3 pattern
(once)
500 ms
1
2
2
1
1
AL4 pattern
(Twice/1 sec)
62.5 ms
1
1 sec
3
AL5 pattern
(3 times/1 sec)
62.5 ms
1
1 sec
AL6 pattern
(1 times)
62.5 ms
1
2
AL7 pattern
(Twice)
62.5 ms
AL8 pattern
(Once)
250 ms
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TMP92CZ26A
3.23 Analog-Digital Converter (ADC)
This LSI has a 6-channel, multiplexed-input, 10-bit successive-approximation Analog-Digital
converter (ADC).
Figure 3.23.1 shows a block diagram of the AD converter.
The 6-analog input channels (AN0-AN5) can be used as general-purpose inputs.
Note1: Ensure that the AD converter has halted before executing HALT instruction to place the
TMP92CZ26A in IDLE2, IDLE1, STOP or PCM mode to reduce power consumption current.
Otherwise, the TMP92CZ26A might go into a standby mode while the internal analog
comparator is still enable state.
Note2: The power consumption current is reduced by setting ADMOD1<DACON> to “0” in the ADC
has been stopped.
Internal data bus
ADS
ADMOD1
ADMOD0
ADMOD2
ADMOD3
ADMOD4/5
HTSEL/HHTRGE
TSEL/HTRGE
ITM/LAT
Scan
repeat
AD Monitor
Function control
Channel
selection
control circuit
AD Monitor function interrupt
INTADM
AD start control
ADTRG
End Busy Start
Normal AD
Converter Control
Circuit
Busy
End
Start
TRMB/ I2S
Complete interrupt AD
INTADHP
High-Priority AD
Converter Control
Normal AD Conversion
complete interrupt
INTAD
AN5 (PG5)
AN4 (PG4)
Compare register
1 and 2
ADTRG, AN3 (PG3)
AN2 (PG2)
Sample
Hold
+
Compare circuit
1&2
AN1 (PG1)
−
AN0 (PG0)
A / D Conversion
Result Register
ADREG0L~5L
ADREG0H~5H
Comparator
High-Priority AD
Conversion
Result Register
ADREGSPH/L
VREF
VREFH
VREFL
D/A Converter
Figure 3.23.1 ADC Block Diagram
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3.23.1 Control register
The AD converter has 6-mode control registers (ADMOD0, ADMOD1, ADMOD2,
ADMOD3, ADMOD4 and ADMOD5) and 6-conversion result high/low register pairs
(ADREG0H/L ∼ ADREG5H/L). The results of high-priority AD conversion are stored in the
ADREGSPH/L.
Figure 3.23.2 to Figure 3.23.11 show the registers available in the AD converter.
AD Mode Control Register 0 (Normal conversion control)
7
EOS
R
6
BUSY
R
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
I2AD
ADS
HTRGE
R/W
TSEL1
TSEL0
ADMOD0
(12B8H)
0
0
0
0
0
0
0
Normal AD
conversion
end flag
Normal AD
conversion
BUSY Flag
AD
Start Normal
AD conversion
0: Don’t Care
Normal AD
conversion at
Hard ware
trigger
Select Hard ware trigger
conversion
when
Function
00: INTTB00 interrupt
01: Reserved
0:During
IDLE2 mode 1:Start
conversion
sequence
or before
starting
0:Stop
AD conversion 0: Disable
10:
ADTRG
conversion
1:During
conversion
0: Stop
1: Enable
11: Reserved
1: Operate
Always read
as”0”.
1:Complete
conversion
sequence
Figure 3.23.2 AD Conversion Registers
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AD Mode Control Register 1 (Normal conversion control)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
DACON
ADCH2
ADCH1
ADCH0
LAT
ITM
REPEAT
SCAN
ADMOD1
(12B9H)
R/W
0
0
0
0
0
0
0
0
DAC
and Analog input channel select
Latency
Interrupt
Repeat mode Scan mode
VREF
application
control
0: No Wait
1:Start after
reading
conversion
result store
Register of
last channel
specification
when
conversion
channel fixed
repeat mode
specification
0: Single
conversion
1: Repeat
conversion
specification
0: Channel
fixed mode
1: Channel
scan mode
Function
Specify AD conversion interrupt for Channel Fixed
Repeat Conversion mode
Channel Fixed Repeat Conversion Mode
<SCAN> = “0”, <REPEAT> = “1”
0
1
Generates interrupt every conversion
Generated interrupt every fourth conversion
Next SCAN start timing control for the channel
scan repeat mode
Channel Scan Repeat mode
(<SCAN> = 1, <REPEAT> = 1)
0
1
No Wait
Start after read last of conversion result
store Register
Analog input channel select
<SCAN>
0:
Channel
fixed
1:
Channel scanned
<ADCH2:0>
000
001
010
011
100
101
110
111
AN0
AN1
AN2
AN0
AN0→AN1
AN0→AN1→AN2
AN3(note) AN0→AN1→AN2→AN3 (note)
AN4
AN5
Reserved
Reserved
AN0→AN1→AN2→AN3→AN4 (note)
AN0→AN1→AN2→AN3→AN4→AN5 (note)
Note: When using PG3 pin as
, it cannot be set.
ADTRG
DAC & VREF application control
0
DAC & VREF off
(Set before into STOP mode)
DAC & VREF on
1
(Set to “1” before starting conversion)
Figure 3.23.3 AD Converter Related Register
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AD Mode Control Register 2 (High-priority conversion control)
7
HEOS
R
6
HBUSY
R
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
HADS
HHTRGE
HTSEL1
HTSEL0
ADMOD2
(12BAH)
R/W
0
0
0
0
0
0
High-priority
AD conversion AD conversion
sequence
FLAG
High-priority
Start
High-priority
AD conversion 00: INTTB10 interrupt
at Hard ware
trigger
0: Disable
1: Enable
Select Hard ware trigger
High-priority
AD conversion
0: Don’t Care
1: Start AD
BUSY Flag
01: Reserved
10:
ADTRG
11: I2S Sampling Counter
Output
0: During
0:Stop
conversion
conversion
conversion
1:During
conversion
sequence
or before
starting
Always read
as”0”.
1: Complete
conversion
sequence
AD Mode Control Register 3 (High-priority conversion control)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
−
R/W
0
HADCH2 HADCH1 HADCH0
R/W
−
R/W
0
ADMOD3
(12BBH)
0
0
0
Always write
High-priority analog input channel select
Always write
“0”.
“0”.
Analog input channel select
Analog input
channel when
High-priority
conversion
AN0
<HADCH2:0>
000
001
010
011
100
101
110
111
AN1
AN2
AN3(note)
AN4
AN5
Reserved
Reserved
Note: When using PG3 pin as
, it cannot be set.
ADTRG
Figure 3.23.4 AD Conversion Registers
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0
AD Mode Control Register 4 (AD Monitor function control)
7
6
5
4
3
2
1
bit Symbol
Read/Write
After reset
Function
CMEN1
R/W
CMEN0
R/W
CMP1C
CMP0C
IRQEN1
IRQEN0
CMPINT1 CMPINT0
ADMOD4
(12BCH)
R/W
R
R
0
0
0
0
0
0
0
0
AD Monitor
function1
0: Disable
1: Enable
AD Monitor
function0
0: Disable
1: Enable
Generation
condition of
AD monitor
function
Generation
condition of
AD monitor
function
AD monitor
AD monitor
Status of
AD monitor
function
Status of
AD monitor
function
function
function
interrupt 1
0: Disable
1: Enable
(Note)
interrupt 0
0: Disable
1: Enable
(Note)
interrupt 1
0: No
interrupt 0
0: No
interrupt 1
0: less than
1: Greater
interrupt 0
0: less than
1: Greater
generation
generation
1: Generation 1: Generation
than or Equal than or Equal
Note: When AD monitor function interrupts generate, it is cleared automatically and it is set to
disable condition.
AD Mode Control Register 5 (AD Monitor function control)
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
CMCH2
CM1CH1 CM1CH0
R/W
CM0CH2 CM0CH1 CM0CH0
R/W
ADMOD5
(12BDH)
0
0
0
0
0
0
Select analog channel for AD monitor function 1
Select analog channel for AD monitor function 0
000: AIN0
001: AIN1
010: AIN2
011: AN3
100: AN4
000: AIN0
001: AIN1
010: AIN2
011: AN3
100: AN4
101: AN5
101: AN5
110: Reserved
111: Reserved
110: Reserved
111: Reserved
Note1: When converting AD in hard ware trigger by setting <HHTRGE> and <HTRGE>to “1”, set
PGFC<PG3F> to “1” (as ADTRG) in case of external TRG before enabling it. When using
an INTTBx0 of 16-bit timer, first set the <TSEL1:0> or <HTSEL1:0> bit to “00” when the
timer is not operating. Then, set the <HHTRGE> and <HTRGE> to “1” and enable trigger
operation. Finally, operate the timer so that AD conversion will be initiated at constant
intervals.
Note 2: When disabling an external trigger (ADTRG ) for AD conversion, first clear the <HHTRGE> or
<HTRGE> bit to “0”, and clear the PGFC<PG3F> to “0”, thus configuring port G as a
general-purpose port.
Note 3: When starting AD by using external trigger (ADTRG), it can be started after enabling
(<HHTRGE> = “1” or <HTRGE> = “1”) and 3 clock at fSYS was executed. AD is not started
when before that time.
Note 4: When chaging compare register value of AD Monitor function, change it after setting AD
Monitor function to disable(ADMOD4<CMEN1:0>=”0”).
Figure 3.23.5 AD Conversion Registers
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0
AD Conversion Result Register 0 Low
7
6
5
4
3
2
1
OVR0
R
bit Symbol
Read/Write
After reset
Function
ADR01
ADR00
ADR0RF
ADREG0L
(12A0H)
R
R
0
0
0
0
Overrun flag
AD conversion
result store
Store Lower 2 bits of
AN0 AD conversion
result
0:No generate flag
1: Generate
1: Stored
AD Conversion Result Register 0 High
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
ADR09
ADR08
ADR07
ADR06
ADR05
ADR04
ADR03
ADR02
ADREG0H
(12A1H)
R
0
0
0
0
0
0
0
0
Store Upper 8 bits of AN0 AD conversion result
AD Conversion Result Register 1 Low
7
6
5
4
3
2
1
OVR1
R
0
bit Symbol
Read/Write
After reset
Function
ADR11
ADR10
ADR1RF
ADREG1L
(12A2H)
R
R
0
0
0
0
Overrun flag
AD conversion
result store
Store Lower 2 bits of
AN1 AD conversion
result
0:No generate flag
1: Generate
1: Stored
AD Conversion Result Register 1 High
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
ADR19
ADR18
ADR17
ADR16
ADR15
ADR14
ADR13
ADR12
ADREG1H
(12A3H)
R
0
0
0
0
0
0
0
0
Store Upper 8 bits of AN1 AD conversion result
9
8
7
6
5
4
3
2
1
0
Channel X conversion result
ADREGxH
ADREGxL
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
•
•
Bits 5 ∼ 2 are always read as “0”.
Bit 0 is the AD conversion result store flag <ADRxRF>. When AD conversion result is stored, the flag is set to “1”.
When Lower register (ADRECxL) is read, this bit is cleared to “0”.
•
Bit 1 is the Overrun flag <OVRx>. This bit is set to “1” if a next conversion result is written to the ADREGxH/L
before both the ADREGxH and ADREGxL are read. This bit is cleared to “0” by reading Flag.
Figure 3.23.6 AD Conversion Registers
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AD Conversion Result Register 2 Low
7
6
5
4
3
2
1
OVR2
R
0
bit Symbol
Read/Write
After reset
Function
ADR21
ADR20
ADR2RF
ADREG2L
(12A4H)
R
R
0
0
0
0
Overrun flag
AD conversion
result store
Store Lower 2 bits of
AN2 AD conversion
result
0:No generate flag
1: Generate
1: Stored
AD Conversion Result Register 1 High
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
ADR29
ADR28
ADR27
ADR26
ADR25
ADR24
ADR23
ADR22
ADREG2H
(12A5H)
R
0
0
0
0
0
0
0
0
Store Upper 8 bits of AN2 AD conversion result
AD Conversion Result Register 3 Low
7
6
5
4
3
2
1
OVR3
R
0
bit Symbol
Read/Write
After reset
Function
ADR31
ADR30
ADR3RF
ADREG3L
(12A6H)
R
R
0
0
0
0
Overrun flag
AD conversion
result store
Store Lower 2 bits of
AN3 AD conversion
result
0:No generate flag
1: Generate
1: Stored
AD Conversion Result Register 3 High
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
ADR39
ADR38
ADR37
ADR36
ADR35
ADR34
ADR33
ADR32
ADREG3H
(12A7H)
R
0
0
0
0
0
0
0
0
Store Upper 8 bits of AN3 AD conversion result
9
8
7
6
5
4
3
2
1
0
Channel X conversion result
ADREGxH
ADREGxL
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
•
•
Bits 5 ∼ 2 are always read as “0”.
Bit 0 is the AD conversion result store flag <ADRxRF>. When AD conversion result is stored, the flag is set to “1”.
When Lower register (ADRECxL) is read, this bit is cleared to “0”.
•
Bit 1 is the Overrun flag <OVRx>. This bit is set to “1” if a next conversion result is written to the ADREGxH/L
before both the ADREGxH and ADREGxL are read. This bit is cleared to “0” by reading Flag.
Figure 3.23.7 AD Conversion Registers
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AD Conversion Result Register 4 Low
7
6
5
4
3
2
1
OVR4
R
0
ADREG4L
(12A8H)
bit Symbol
Read/Write
After reset
Function
ADR41
ADR40
ADR4RF
R
R
0
0
0
0
Overrun flag
AD conversion
result store
Store Lower 2 bits of
AN4 AD conversion
result
0:No generate flag
1: Generate
1: Stored
AD Conversion Result Register 4 High
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
ADR49
ADR48
ADR47
ADR46
ADR45
ADR44
ADR43
ADR42
ADREG4H
(12A9H)
R
0
0
0
0
0
0
0
0
Store Upper 8 bits of AN4 AD conversion result
AD Conversion Result Register 5 Low
7
6
5
4
3
2
1
OVR5
R
0
bit Symbol
Read/Write
After reset
Function
ADR51
ADR50
ADR5RF
ADREG5L
(12AAH)
R
R
0
0
0
0
Overrun flag
AD conversion
result store
Store Lower 2 bits of
AN5 AD conversion
result
0:No generate flag
1: Generate
1: Stored
AD Conversion Result Register 5 High
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
ADR59
ADR58
ADR57
ADR56
ADR55
ADR54
ADR53
ADR52
ADREG5H
(12ABH)
R
0
0
0
0
0
0
0
0
Store Upper 8 bits of AN5 AD conversion result
9
8
7
6
5
4
3
2
1
0
Channel X conversion result
ADREGxH
ADREGxL
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
•
•
Bits 5 ∼ 2 are always read as “0”.
Bit 0 is the AD conversion result store flag <ADRxRF>. When AD conversion result is stored, the flag is set to “1”.
When Lower register (ADRECxL) is read, this bit is cleared to “0”.
•
Bit 1 is the Overrun flag <OVRx>. This bit is set to “1” if a next conversion result is written to the ADREGxH/L
before both the ADREGxH and ADREGxL are read. This bit is cleared to “0” by reading Flag.
Figure 3.23.8 AD Conversion Registers
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0
High-priority AD Conversion Result Register SP Low
7
6
5
4
3
2
1
bit Symbol
Read/Write
After reset
Function
ADRSP1
ADRSP0
OVSRP ADRSPRF
ADREGSPL
(12B0H)
R
R
R
0
0
0
0
Overrun flag
AD conversion
Store Lower 2 bits of an
AD conversion result
result store
0:No generate flag
1: Generate
1: Stored
High-priority AD Conversion Result Register SP High
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
ADRSP9
ADRSP8
ADRSP7
ADRSP6
ADRSP5
ADRSP4
ADRSP3
ADRSP2
ADREGSPH
(12B1H)
R
0
0
0
0
0
0
0
0
Store Upper 8 bits of an AD conversion result
9
8
7
5
6
5
4
3
2
1
0
Channel X conversion result
ADREGxH
ADREGxL
7
6
4
3
2
1
0
7
6
5
4
3
2
1
0
•
•
Bits 5 ∼ 2 are always read as “0”.
Bit 0 is the AD conversion result store flag <ADRxRF>. When AD conversion result is stored, the flag is set to “1”.
When Lower register (ADRECxL) is read, this bit is cleared to “0”.
•
Bit 1 is the Overrun flag <OVRx>. This bit is set to “1” if a next conversion result is written to the ADREGxH/L
before both the ADREGxH and ADREGxL are read. This bit is cleared to “0” by reading Flag.
Figure 3.23.9 AD Conversion Registers
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0
AD Conversion Result Compare Criterion Register 0 Low
7
6
5
4
3
2
1
bit Symbol
Read/Write
After reset
Function
ADR21
ADR20
ADCM0REGL
(12B4H)
R/W
0
0
Store Lower 2 bits of an
AD conversion result
compare criterion
AD Conversion Result Compare Criterion Register 0 High
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
ADR29
ADR28
ADR27
ADR26
ADR25
ADR24
ADR23
ADR22
ADCM0REGH
(12B5H)
R/W
0
0
0
0
0
0
0
0
Store Upper 8 bits of an AD conversion result compare criterion
AD Conversion Result Compare Criterion Register 1 Low
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
ADR21
ADR20
ADCM1REGL
(12B6H)
R/W
0
0
Store Lower 2 bits of an
AD conversion result
compare criterion
AD Conversion Result Compare Criterion Register 1 High
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
ADR29
ADR28
ADR27
ADR26
ADR25
ADR24
ADR23
ADR22
ADCM1REGH
(12B7H)
R/W
0
0
0
0
0
0
0
0
Store Upper 8 bits of an AD conversion result compare criterion
Note: Disable the AD monitor function (ADMOD4<CMEN> = “0”) before attempting to set or modify
the value of these registers.
Figure 3.23.10 AD Conversion Registers
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AD Conversion Clock Setting Register
7
6
5
4
3
2
ADCLK2
R/W
1
ADCLK1
R/W
0
ADCLK0
R/W
bit Symbol
Read/Write
After reset
Function
−
ADCCLK
(12BFH)
R/W
0
0
0
0
Always
write “0”
Select clock for AD conversion
000 : Reserved 100 : fIO/4
001 : fIO/1
010 : fIO/2
011 : fIO/3
101 : fIO/5
110 : fIO/6
111 : fIO/7
Note1: AD conversion is executed at the clock frequency selected in the above register. To assure
conversion accuracy, however, the conversion clock frequency must not exceed 12MHz
MHz.
Note2: Don ‘t change the clock frequency while AD conversion is in progress.
Figure 3.23.11 AD Conversion Registers
<ADCLK2:0>
÷1 ∼ ÷7
fSYS
ADCLK
AD conversion
speed
<ADCLK2:0>
ADCLK
fIO(fSYS/2)
40MHz
10.0MHZ
8MHZ
12 μsec
15 μsec
12 μsec
16 μsec
100(fIO/4)
101(fIO/5)
011(fIO/3)
100(fIO/4)
10.0MHZ
7.5MHZ
30MHz
AD conversion speed can be calculated by following.
Conversion speed = 120 × (1/ADCLK)
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3.23.2 Operation
3.23.2.1
Analog Reference Voltages
The VREFH and VREFL pins provide the analog reference voltages for the ADC.
3.23.2.2
Analog Input Channel(s) selection
The Analog input channels used for AD conversion are selected as follows:
(1) Normal AD conversion
• Analog Input Channel Fixed mode (ADMOD1<SCAN> = “0”)
Setting ADMOD1<ADCH2:0> selects one of the input pins AN0 to AN5 as the input
channel.
• Analog Input Channel Scan Mode (ADMOD1<SCAN> = “1”)
Setting ADMOD1<ADCH2:0> selects one of the six scan modes.
(2) High-priority AD conversion
Setting ADMOD3<HADCH2:0> selects one of the eight input pins AN0 ∼ AN5.
On a Reset, ADMOD1<SCAN> is set to “0”, and ADMOD1<ADCH2:0> is initialized
to “000”. Thus pin AN0 is selected as the fixed input channel. Pins that are not used as
analog input channels can be used as standard input port pins.
If a high-priority AD conversion is triggered while a normal AD conversion is in
progress, the normal AD conversion sequence is suspended after converting data for
the current channel, to perform a high-priority AD conversion. After a high-priority
AD conversion is performed, the normal AD conversion sequence is resumed with that
channel.
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3.23.2.3 Starting an AD Conversion
The ADC supports two types of AD conversion: normal AD conversion and
high-priority AD conversion. The ADC initiates a normal AD conversion by software
when the ADMOD0<ADS> is set to “1”. It initiates a high-priority AD conversion by
software when the ADMOD2<HADS> is set to “1”. For a normal AD conversion,
ADMOD1<REPEAT, SCAN> select one of four conversion modes. For a high-priority
AD conversion, the ADC only supports Fixed-Channel Single Conversion mode.
The ADMOD0<TSEL1:0> and ADMOD2<HTSEL1:0> enable a hardware trigger for
a normal and high-priority AD conversion, respectively. When these bits are set to “10”,
a normal or high-priority AD conversion is triggered by a falling edge applied to
ADTRG pin. When ADMOD0<TSEL1:0> is set to “00”, a normal AD conversion is
triggered by INTTB00 of 16-Bit Timer interrupt. When ADMOD2<HTSEL1:0> is set
to “00”, a high-priority AD conversion is triggered by INTTB10 of 16-Bit Timer
interrupt. If this bit is “11”, it is triggered by I2S sampling block. Even when a
hardware trigger is enabled, software starting can be used.
When a normal AD conversion starts, the Busy flag (ADMOD0<BUSY>) is set to “1”.
When a high-priority AD conversion starts, the high-priority AD conversion busy flag
(ADMOD2<HBUSY>) is set to “1”. During a normal AD conversion, if a high-priority
AD conversion start, ADMOD0<BUSY> holds “1”.
When an AD conversion complete, ADMOD0<EOS> and ADMOD2<HEOS> is set to
“1”. These flags are cleared to “0” by reading these flags only.
During a normal AD conversion, writing a “1” to ADMOD0<ADS> causes the ADC
to abort any ongoing conversion immediately, and restart.
During a normal AD conversion, if normal AD conversion starting is enabled by
hard ware trigger, normal AD conversion is restarted when start condition from hard
ware trigger is satisfied. When restart is set, normal AD conversion is aborted
immediately.
During a normal AD conversion, if a high-priority AD conversion starts(writing a “1”
to ADMOD2<HADS> or a hard ware trigger occurs), the ADC aborts any ongoing
conversion immediately, and then start a high-priority AD conversion for the channel
specified by ADMOD3<HADCH2:0>. Upon the completion of the high-priority
conversion, the ADC stores the conversion result to ADREGSPH/L, and then resumes
the suspended normal conversion with that channel.
Note: It cannot overlap with three or more AD conversions.
Prohibition example 1 : In FIRST normal AD conversion
Æ (Before finished FIRST normal AD conversion) Started SECOND normal AD conversion
Æ (Before finished SECOND normal AD conversion) Started THIRD normal AD conversion
Prohibition example 2 : In FIRST normal AD conversion
Æ (Before finished FIRST normal AD conversion) Started SECOND normal AD conversion
Æ (Before finished SECOND normal AD conversion) Started THIRD high-priority AD conversion
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3.23.2.4
AD Conversion Modes and AD Conversion-End Interrupts
The ADC supports the following four conversion modes. For a normal AD conversion,
ADMOD0<1:0> select one of the four conversion modes. For a high-priority AD
conversion, the ADC only supports Channel Fixed Single Conversion mode.
a. Channel Fixed Single Conversion mode
b. Channel Scan Single Conversion mode
c. Channel Fixed Repeat Conversion mode
d. Channel Scan Repeat Conversion mode
(1) Normal AD conversion
ADMOD0<REPEAT, SCAN> select the conversion mode. Once a conversion is
started, the ADMOD0<BUSY> is set to “1”. The ADC generates the AD Conversion
End interrupt (INTAD) and sets the ADMOD0<EOS> to “1” at the end of the specified
conversion process.
a. Channel Fixed Single Conversion mode
This mode is selected by programming ADMOD0<REPEAT, SCAN> to “00”.
In this mode, the ADC performs a single conversion on a single selected
channel. When a conversion is completed, the ADC sets the ADMOD0<EOS>,
and generates the INTAD interrupt. ADMOD0<EOS> is cleared to “0” when it is
read.
b. Channel Scan Single Conversion mode
This mode is selected by programming ADMOD0<REPET, SCAN> to “01”. In
this mode, the ADC performs a single conversion on each of a selected group of
channels. When a single conversion sequence is completed, ADMOD0<EOS> is
set to “1”, and generates the INTAD interrupt. ADMOD0<EOS> is cleared to “0”
by reading this bit only.
c. Channel Fixed Repeat Conversion mode
This mode is selected by programming ADMOD0<REPET, SCAN> to “10”. In
this mode, the ADC repeatedly converts a single selected channel. When a
conversion process is completed, ADMOD0<EOS> is set to “1”.
ADMOD1<ITM> control INTAD interrupts generation in this mode. The
timing when ADMOD0<EOS> is set also depends on the ADMOD1<ITM>. The
EOCF bit is cleared when it is read. ADMOD0<EOS> is cleared to “0” by reading
this bit only.
If ADMOD1<ITM> is set to “0”, the ADC generates an interrupt after each
conversion. The results of conversion are always stored in the ADREGxH/L
register. The ADMOD0<EOS> is set to “1” when the ADC stores the results to the
ADREGxH/L.
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If ADMOD1<ITM> is set to “1”, the ADC generates an interrupt after every
four conversions. The results of conversions are sequentially stored in the
ADREG0H/L to ADREG3H/L registers, in that order. The ADMOD0<EOS> is set
to “1” when the ADC stores the results in the ADREG3H/L. The next conversion
results are again stored in the ADREG0, and so on. The ADMOD0<EOS> is
cleared to “0” by reading this bit only.
d. Channel Scan Repeat Conversion mode
This mode is selected by programming ADMOD0 <REPEAT, SCAN> to “11”. In
this mode, the ADC repeatedly converts the selected group of channels. When a
single conversion sequence is completed, the ADC sets ADMOD0<EOS> to “1”,
and generates the INTAD interrupt. ADMOD0<EOS> is cleared to “0” by reading
this bit only.
In continuous conversion modes (3) and 4)), clearing the ADMOD1<REPEAT>
stops the conversion sequence after the ongoing scan conversion process is
completed.
Shift to a standby mode (IDLE2 Mode with ADMOD0<I2AD> = “0”, IDLE1
Mode or STOP Mode) immediately stops operation of the AD converter even if AD
conversion is still in progress. Therefore, ADC may consume current even if
operation is stopped, depending on stop condition of ADC that switches to
standby mode. For avoiding this problem, Stop ADC before switching to standby
mode.
(2) High-priority AD conversion
For a high-priority AD conversion, the ADC only supports Channel Fixed Single
Conversion mode, regardless of the settings of ADMOD1<REPEAT, SCAN>.
When a conversion start condition is satisfied, the ADC performs a single conversion
on a single selected channel, which is specified with the ADMOD3<HADCH2:0>.
When a conversion is completed, the ADC sets ADMOD2<HEOS>to “1”. HEOS Flag is
cleared to “0” by reading this bit only.
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Interrupt Generation Timing and Flag Setting in Each AD Conversion Mode
Interrupt
Generation
Timing
ADMOD1
ITM
EOS set timing
(Note)
Conversion mode
REPEAT
0
SCAN
Channel Fixed
After a
After a
Single Conversion conversion
Mode
conversion
−
0
1
0
0
Channel Fixed
Repeat
After every
conversion
After every
conversion
Conversion Mode
1
After every
four
After every
four
conversions
conversions
Channel Scan
After a scan
After a scan
conversion
sequence
Single Conversion conversion
−
−
0
1
1
1
Mode
sequence
Channel Repeat
After each
After each
scan
Single Conversion scan
Mode conversion
sequence
conversion
sequence
Note: EOS is cleared to “0” by reading this bit only.
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3.23.2.5
High-Priority Conversion Mode
The ADC can perform a high-priority AD conversion while it is performing a normal
AD conversion sequence. A high-priority AD conversion can be started at software by
setting the ADMOD2<HADS> to “1”. It is also triggered by a hardware trigger if so
enabled using ADMOD2<HTSEL1:0>. If a high-priority AD conversion is triggered
during a normal AD conversion, the ADC aborts any ongoing conversion immediately,
and then begins a single high-priority AD conversion for the channel specified with the
ADMOD3<HADC2:0>. Upon the completion of the high-priority AD conversion, the
ADC stores the results of the conversion in the ADREGSPH/L, generates the
high-priority AD conversion interrupt (INTADHP), and then resumes the suspended
normal conversion with that channel. While a high-priority conversion is being
performed, a trigger for another high-priority conversion is ignored.
Example: In the case of a high-priority AD conversion for AN5 (ADMOD3<HADCH2:0>=”101”) is started durring a
normal AD conversion in channel scan repeat mode for AN0 to AN3 (ADMOD1<REPEAT,SCAN> = “11”、
ADMOD1<ADCH2:0> = “011”)
High-priority AD
conversion start trigger
Conversion channel
AN0
AN1
AN2
AN5
AN2
AN3
AN0
Abort conversion
for AN2
conversion for AN2
again
Start conversion for AN5
3.23.2.6
AD Monitor Function
When ADMOD4<CMEN1:0> is set to “1”, the AD monitor function is enabled. This
function generates an interrupt depending on condition of IRQEN1:0, when the
finished AD conversion of the channel which specified with the ADMOD5 register, if
the value of the AD conversion result register pair is greater or less (specified with
CMP1C:0C) than the value of the compare criterion register 0/1(ADCMxREGH/L).
The ADC performs this comparison each times it stores results to the specified AD
conversion result register and generate interrupt (INTADM) when condition is
satisfied. The conversion result register used for the AD monitor function is usually
not read in the program, so mind that its overrun flag <OVRn> and conversion result
store flag <ADRnRF> are always set.
If these are assigned to different channel, 2-analog channel can monitor “less” or
“grater”. And if these are assigned same analog channel, the watch that sets the range
of the voltage is possible.
3.23.2.7
AD Conversion Time
AD conversion of one time is 120 clocks that include sampling clock. The AD
conversion clock can be selected from 1/1 to 1/7 of fIO by ADCLK<ADCLK2:0>. To
assure conversion accuracy, the AD conversion clock frequency need to select 12 MHz
and under, i.e., AD conversion time need to select 10 µs and over.
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3.23.2.8
Storing and Reading the AD Conversion Result
Conversion results are stored into AD conversion result high/low register
(ADREG0H/L to ADREG5H/L).
In Channel Fixed Repeat Conversion mode, conversion results are stored into the
ADREG0H/L to ADREG3H/L sequentially.
In other modes, the AD conversion result of channel AN0, AN1, AN2, AN3, AN4, and
AN5 is stored in ADREG0H/L, ADREG1H/L, ADREG2H/L, ADREG3H/L,
ADREG4H/L, and ADREG5H/L respectively.
Table 3.23.1 shows the relationships between the analog input channels and the AD
conversion result registers.
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Table 3.23.1 Relationships between Analog Input Channels and AD Conversion Result Registers
AD Conversion Result Registers
Analog Input Channel
(Port G)
Channel Fixed Repeat
Conversion Mode
(every fourth conversion)
Conversion Modes
other than at right
AN0
AN1
AN2
AN3
AN4
AN5
ADREG0H/L
ADREG1H/L
ADREG2H/L
ADREG3H/L
ADREG4H/L
ADREG5H/L
ADREG0H/L
ADREG1H/L
ADREG2H/L
ADREG3H/L
Note: For detect a overrun error thoroughly, read the AD conversion result register high at first and
read the AD conversion result register low at second. If OVRn=”0” and ADRnRF=”1”, a
correct conversion result was obtained.
3.23.2.9
Data Polling
When the results of AD conversion are processed by means of data polling without
using interrupts, ADMOD0<EOS> should be polled. After confirming ADMOD0
<EOS>=”1”, read the AD conversion result register.
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Setting example:
1.
Convert the analog input voltage on the AN3 pin and write the result to memory address 2800H using the AD
interrupt(INTAD) processing routine.
Main routine
7
1
1
X
6
1
1
X
5
0
0
0
4
0
0
0
3
−
0
0
2
−
0
0
1
−
1
0
0
−
1
1
INTEAD
←
←
←
Enable INTAD and set it to interrupt level 4.
ADMOD1
ADMOD0
Set pin AN3 to be the analog input channel.
Start conversion in channel fixed single conversion mode.
Interrupt routine processing example
WA
← ADREG3
← > > 6
← WA
Read value of ADREG3L and ADREG3H into 16-bits
general-purpose register WA.
WA
Shift contents read into WA six times to right and zero fill
upper bits.
(2800H)
Write contents of WA to memory address 2800H.
2.
This example repeatedly converts the analog input voltages on the three pins AN0, AN1 and AN2, using channel
scan repeat conversion mode.
INTEAD
←
←
←
1
1
0
1
X
0
0
0
0
0
0
−
0
0
−
0
1
−
1
1
−
0
1
Disable INTAD.
ADMOD1
ADMOD0
Set pins AN0 to AN2 to be the analog input channels.
Start conversion in channel scan repeat conversion mode.
X
3. Convert the analog input voltage on the AN2 pin as a high-priority AD conversion, and write the result to memory
address 2A00H using the High-priority AD interrupt(INTADHP) processing routine.
Main routine
INTEAD
←
←
←
←
1
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
−
0
0
1
−
0
0
0
−
0
0
0
−
0
0
0
Enable INTADHP and set it to interrupt level 6.
DAC On.
ADMOD1
ADMOD3
ADMOD2
Set pin AN2 to be the analog input channel.
Start a high-priority AD conversion by software.
Interrupt routine processing example
WA
← ADREGSP
Read value of ADREGSPL and ADREGSPH into 16-bits
general-purpose register WA.
WA
← > > 6
Shift contents read into WA six times to right and zero fill
upper bits.
(2A00H)
← WA
Write contents of WA to memory address 2A00H.
4. Convert the analog input voltage on the AN4 pin as a normal AD conversion of a channel fixed single conversion
mode. And then if its conversion result is greater or equal than the value of (ADCM0REGL/H), write the result to
memory address 2C00H using the AD monitor function interrupt (INTADM) processing routine.
Main routine
INTEAD
←
←
←
−
0
0
−
0
0
−
0
1
−
0
0
1
1
0
0
0
0
1
0
0
1
0
0
Enable INTAD and set it to interrupt level 3.
ADMOD5
ADMOD4
Set the analog input channel AN4 for AD monitor function 0.
Enable the AD monitor function0 and AD monitor function
interrupt 0. Set “a conversion result ≥ AD conversion result
compare criterion register” for generation condition of monitor
function interrupt 0.
ADMOD1
ADMOD0
←
←
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
Set pin AN4 to be the analog input channel.
Start a normal AD conversion by software.
Interrupt routine processing example
WA
← ADREG4
← > > 6
← WA
Read value of ADREG4L and ADREG4H into 16-bits
general-purpose register WA.
WA
Shift contents read into WA six times to right and zero fill
upper bits.
(2C00H)
Write contents of WA to memory address 2C00H.
X : Don't care, − : No change
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3.24 Watchdog Timer (Runaway detection timer)
The TMP92CZ26A contains a watchdog timer of runaway detecting.
The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that
the CPU has started to malfunction (runaway) due to causes such as noise. When the watchdog
timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of
the malfunction.
Connecting the watchdog timer output to the reset pin internally forces a reset.
(The level of external
pin is not changed.)
RESET
3.24.1 Configuration
Figure 3.24.1 is a block diagram of the watchdog timer (WDT).
WDMOD<RESCR>
Reset control
RESET pin
Internal reset
INTWD interrupt
WDMOD
<WDTP1:0>
Selector
215 217 219 221
Q
Binary counter
(22 stages)
fIO
R
S
Reset
Internal reset
Write
B1H
Write
4EH
WDMOD
<WDTE>
WDT control register WDCR
Internal data bus
Figure 3.24.1 Block Diagram of Watchdog Timer
Note: It needs to care designing the total machine set, because Watchdog timer can’t operate completely by
external noise.
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3.24.2 Operation
The watchdog timer generates an INTWD interrupt when the detection time set in the
WDMOD<WDTP1:0> has elapsed. The watchdog timer must be cleared “0” in software
before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway
occurs) due to causes such as noise, but does not execute the instruction used to clear the
binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
The CPU will detect malfunction (runaway) due to the INTWD interrupt and in this case it
is possible to return to the CPU to normal operation by means of an anti-malfunction
program.
The watchdog timer begins operating immediately on release of the watchdog timer
reset.
The watchdog timer is halted in IDLE1 or STOP mode. The watchdog timer counter
continues counting during bus release (when BUSAK goes low).
When the device is in IDLE2 mode, the operation of WDT depends on the
WDMOD<I2WDT> setting. Ensure that WDMOD<I2WDT> is set before the device enters
IDLE2 mode.
The watchdog timer consists of a 22-stage binary counter which uses the clock (f ) as the
IO
input clock. The binary counter can output 215/ f , 217/ f , 219/f and 221/ f . Selecting one
IO
IO
IO
IO
of the outputs using WDMOD<WDTP1:0> generates a watchdog timer interrupt when an
overflow occurs.
WDT counter
WDT interrupt
n
Overflow
0
Write clear code
WDT clear
(Soft ware)
Figure 3.24.2 Normal Mode
The runaway detection result can also be connected to the reset pin internally.
In this case, the reset time will be 32 clocks (102.4 μs at f = 10 MHz) as shown in
OSCH
by two, where f
is generated by
IO
SYS
SYS
dividing the high-speed oscillator clock (f ) by sixteen through the clock gear function
OSCH
Overflow
WDT counter
WDT interrupt
n
Internal reset
32 clocks (102.4 μs at f
= 10 MHz)
OSCH
Figure 3.24.3 Reset Mode
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3.24.3 Control Registers
The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR.
(1) Watchdog timer mode registers (WDMOD)
1. Setting the detection time for the watchdog timer in <WDTP1:0>
This 2-bit register is used for setting the watchdog timer interrupt time used
when detecting runaway.
On a reset this register is initialized to WDMOD<WDTP1:0> = 00.
The detection time for WDT is 215/f [s]. (The number of system clocks is
IO
approximately 65, 536.)
2. Watchdog timer enable/disable control register <WDTE>
At reset, the WDMOD<WDTE> is initialized to “1”, enabling the watchdog
timer.
To disable the watchdog timer, it is necessary to clear this bit to “0” and to write
the disable code (B1H) to the watchdog timer control register (WDCR). This
makes it difficult for the watchdog timer to be disabled by runaway.
However, it is possible to return the watchdog timer from the disabled state to
the enabled state merely by setting <WDTE> to “1”.
3. Watchdog timer out reset connection <RESCR>
This register is used to connect the output of the watchdog timer with the
RESET terminal internally. Since WDMOD<RESCR> is initialized to 0 at reset, a
reset by the watchdog timer will not be performed.
(2) Watchdog timer control registers (WDCR)
This register is used to disable and clear the binary counter for the watchdog timer.
•
Disable control
The watchdog timer can be disabled by clearing WDMOD<WDTE> to 0 and then
writing the disable code (B1H) to the WDCR register.
WDCR
WDMOD
WDCR
←
←
←
0
0
1
1
−
0
0
−
1
0
X
1
1
X
0
1
−
0
1
−
0
0
0
1
Write the clear code (4EH).
Clear WDMOD <WDTE> to “0”.
Write the disable code (B1H).
•
•
Enable control
Set WDMOD<WDTE> to “1”.
Watchdog timer clear control
To clear the binary counter and cause counting to resume, write the clear code
(4EH) to the WDCR register.
WDCR
←
0
1
0
0
1
1
1
0
Write the clear code (4EH).
Note1: If it is used disable control, set the disable code (B1H) to WDCR after write the clear code (4EH) once. (Please
refer to setting example.)
Note2: If it is changed Watchdog timer setting, change setting after set to disable condition once.
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0
7
6
5
4
3
2
1
WDMOD
(1300H)
Bit symbol
Read/Write
After reset
Function
WDTE
WDTP1
R/W
0
WDTP0
I2WDT
RESCR
R/W
0
−
1
0
0
0
WDT control Select detecting time
IDLE2
1: Internally Always
connects write “0”
WDT out
to the
reset pin
1: Enable
00: 215/f
01: 217/f
10: 219/f
11: 221/f
0: Stop
IO
IO
IO
IO
1: Operate
Watchdog timer out control
0
1
−
Connects WDT out to a reset
IDLE2 control
0
1
Stop
Operation
Watchdog timer detection time
00 215/f (Approximately 819.2 μs at f = 40 MHz)
IO
IO
01 217/f (Approximately 3.276 ms at f = 40 MHz)
IO
IO
10 219/f (Approximately 13.107 ms at f = 40 MHz)
IO IO
11 221/f (Approximately 52.428 ms at f = 40 MHz)
IO
IO
Watchdog timer enable/disable control
0
1
Disabled
Enabled
Figure 3.24.4 Watchdog Timer Mode Register
7
6
5
4
3
2
1
0
WDCR
(1301H)
Bit symbol
Read/Write
After reset
Function
−
W
−
Read
-modify
B1H: WDT disable code
4EH: WDT clear code
-write
instruction is
prohibited
WDT disable/clear control
Disable code
B1H
4EH
Clear code
Others
Don’t care
Figure 3.24.5 Watchdog Timer Control Register
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3.25 Power Management Circuit (PMC)
The TMP92CZ26A incorporates a power management circuit (PMC) for managing power
supply in standby state as protective measures against leak current in fine-process products.
The following six power supply rails are available.
: AVCC & AVSS (for ADC)
･Analog power supply
: DVCC3A, 3B & DVSSCOM (for general pins)
: DVCC1A & DVSSCOM (for general circuits)
: DVCC1B & DVSSCOM (for RTC, PMC)
: DVCC1C & DVSS1C
･3V-A, 3V-B digital I/O power supply
･1.5V-A digital internal power supply
･1.5V-B digital internal power supply
･1.5V-C oscillation power supply
(for high-frequency oscillator, PLL)
Each power supply rail is independent of one another (VSS is partially shared).
Of the six power supply rails, those that are supplied in Power Cut Mode are the power
supply rail for external pins (DVCC-3A, DVCC-3B), the power supply rail for ADC (AVCC),
and the power supply rail for RTC and backup RAM (DVCC-1B). DVCC1A and DVCC1C
power supply rails are isolated internally with their signals cut off so that no flow-through
current will be generated in the LSI when the power is turned off.
• DVCC-3A, DVCC-3B
This 3V rail supplies power for holding external pins, controlling ON/OFF of external power
supplies, and interrupt input to release standby state.
• AVCC
This 3V rail supplies power in the touch panel interface for interrupt input to release
standby state.
• DVCC-1B
This 1.5V rail supplies power to the RTC, 16 Kbytes of RAM, and PMC.
DVCC-1C
DVCC-1A
DVCC-1B
AVCC
DVCC-3A,3B
TMP92CZ26A
INT
Port
Others
RAM 16KB
RTC
CPU, Other logic
& RAM 272 KB
ADC
Control
I/O
Reg
High-
OSC
I/O
PMC
Low-OSC
DVSS-COM
XT1
AVSS
DVSS-1C
XT2
Figure 3.25.1 Power Supply System
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3.25.1 SFR
7
6
5
4
3
2
1
0
bit symbol
Read/Write
After
PCM_ON
R/W
−
WUTM1
R/W
WUTM0
R/W
PMCCTL
(02F0H)
W
system
reset
0
0
0
0
After hot
reset
Data
retained
Power
Data
Data
−
retained
retained
Always
Warm-up time
Cut Mode
write “0”
00: 29 (15.625 ms)
01: 210 (31.25 ms)
10: 211 (62.5 ms)
Function
0: Disable
1: Enable
Always
read as “0” 11: 212 (125 ms)
Note: After wake-up interruption, internal wake-up timer count setting register value:<WUTM1:0>, and after about
77us, external PWE terminal change from low level to high level. Additionally after more about 92us, internal
reset signal will be released. We recommend to confirm actual performance on final set, because the time to
be stable all voltage level and power supply circuit are difference characteristics every final set.
The following operations are affected by the setting of the <PCM_ON> bit.
PCM_ON = 1
PCM_ON = 0
No interrupt
External interrupt input
Operation after reset
Interrupt
HOT_RESET signal assert
Startup depending on the AM1
and AM0 pins
−
Startup from boot ROM regardless
of the AM1 and AM0 pins and
jump to internal RAM area.
Operation after hot reset
Warm-up counter
−
A change in the PWE pin level is
used as a trigger to start counting
the low-frequency clock for
releasing HOT_RESET.
Counter stopped
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3.25.2 Detailed Description of Operation
This section explains the procedures for entering and exiting the Power Cut Mode.
• Entering the Power Cut Mode
When to enter the Power Cut Mode, the CPU needs to be operating in the internal RAM.
Low frequency clock (XT) must be enable condition.
It is also necessary to disable interrupt requests, stop DMA operations, WDT and AD
converter. Next, set the output pins to function as ports through the Pn, PnCR and PnDR
registers. At this time, PM7 should be set as PWE. Of the external interrupt pins, those to be
used for waking up from the Power Cut Mode should be set as input pins with interrupt
enabled.
About trigger of interruption, only rising edges are effective among selectable interruption
pins. When INT4 is used as TSI, the de-bounce circuit should be disabled.
Then, set the warm-up time for waking up from Power Cut Mode in PMCCTL<WUTM1:0>.
Write the wake-up program at addresses from 46000H to 49FFFH in the internal RAM.
Should be written all initialize sequence including WDT in this program.
Finally, stop the PLL and set PMCCTL<PCM_ON> to “1” to enter the Power Cut Mode.
At this time, the RESET (HOT_RESET) signal is asserted for all the circuits excluding
external I/O and PMC.
Note: As soon as PMCCTL<PCM_ON> is set to “1”, the power management signal (PWE) changes from “1” to “0”
and external power supplies are turned off.
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1. Prepare to shift Power Cut Mode
(1) Set the warm-up time: PMCCTL<WUTM1:0>
After wake-up interruption, internal wake-up timer count setting register
value:<WUTM1:0>, and after about 77us, external PWE terminal change from low
level to high level. Additionally after more about 92us, internal reset signal will be
released. We recommend to confirm actual performance on final set, because the
time to be stable all voltage level and power supply circuit are difference
characteristics every final set.
Warm-up time can be selected among 15.625ms, 31.25ms, 62,5ms and 125ms.
(2) Prepare the initial program after Warm-up (46000H∼49FFFH)
After wake-up, jump to Boot ROM, and Boot ROM process distinguish only bit 7
of PMCCTL register. All initialize setting including WDT setting must be written
in fixed RAM area (46000H∼49FFFH).
(3) Control of low frequency clock (XT)
Power Management Circuit operates by low frequency clock. Low frequency
clock (XT) must be enable condition
2. Operation Sequence
(1) Execution area of program must shift to internal RAM area.
Before shifting Power Cut Mode, it must stop all the source which might be
disturbed to shift Power Cut Mode.
a. Disable Watch Dog Timer operation
b. Disable A/D converter operation
c. Disable all DMA function
• Disable LCDC
• Auto refresh of SDRAM (We recommend to use self refresh mode)
• Disable DMAC
(2) Fix to port condition (Pn, PnCR, PnFC,PnDR)
Fix port condition and set external interrupt mode to wake-up trigger.
When INT4 is used as TSI, the de-bounce circuit should be disabled.
(3) Disable interruption (DI)
(4) Stop PLL operation
(5) Shift to Power Cut Mode (PMCCTL<PCM_ON>= “1”)
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• Exiting the Power Cut Mode
The Power Cut Mode can be exited by external or internal interruption. (It inhibits to exit
the Power Cut Mode by reset when DVCC1A is cut off. Reset must be asserted after supplying
power to DVCC1A and waiting for its voltage to fully stabilize.) The interrupts that can be
used to exit the Power Cut Mode are RTC interrupt, INT0 to INT7 (TSI interrupt) and
INTKEY interrupt.
Table 3.25.1 Wake-up triggers
Source
Symbol
Note
RTC
INTRTC
INT0
Only support "Rising Edge"
Only support "Rising Edge"
Only support "Rising Edge"
Only support "Rising Edge"
When TSI, need to disable de-bounce circuit
Only support "Rising Edge"
Only support "Rising Edge"
Only support "Rising Edge"
Only support "Rising Edge"
KI0~KI8
INT1
INT2
INT3
External
INT4
INT5
INT6
INT7
Key
INTKEY
Only support "Falling Edge"
When an interrupt request is accepted, the power management signals (PWE) changes from
“0” to “1” and power is supplied to each block that has been cut off. After the warm-up time set
in PMCCTL<WUTM1:0> has elapsed, HOT_RESET is automatically released and the CPU
starts up from the internal boot ROM regardless of the external AM pin state. All external
ports retain the state before entering the Power Cut Mode except for the PnDR setting which
is released upon release of HOT_RESET.
* Output pin Hi-Z state
* Input pin input gate OFF
→
→
“1” or “0” output
Input pin input gate ON
The internal boot ROM first checks the PMCCTL <PCM_ON> bit in the PMC. If this bit is
set to “1”, execution jumps to address 46000H in the internal RAM before making all initial
settings. The <PCM_ON> bit in the PMC is cleared to “0” by software.
Note 1: The interrupt that released the Power Cut Mode, whichever it is, does not activate any interrupt operation. Nor
is it possible to identify which interrupt released the Power Cut Mode.
Note 2:Once the PMCCTL<PCM_ON> bit is set to “1”, it remains in this state. To re-enter the Power Cut Mode, it is
necessary to set this bit to “0” once and then to “1” again. At this time, a minimum of 31 us must be inserted
between setting <PCM_ON> to “0” and “1”.
Note 3:Since the Power Cut Mode is exited using the boot ROM, some settings must be made by software. Be
careful about this point.
7
6
5
4
3
2
1
0
BROMCR Bit symbol
CSDIS
ROMLESS
VACE
(016CH)
Read/Write
After reset
Function
R/W
0
1
1
NAND Flash Boot ROM
Vector
area CS
output
0: Used
address
1: Not used
conversion
0: Disable
1: Enable
0: Enable
1: Disable
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3.25.3 Detailed Description of Timing
1. A maximum of 3 clocks (92 μs)
2. A maximum of 2.5 clocks (77 μs)
3. A minimum of 1 clock (31 μs) is
needed for entering PCM again.
are needed for entering PCM.
are needed from interrupt request.
CPU state transition
Normal
Power Cut Mode (PCM)
Warm-up 3CLK
Normal
XT2
PMCCTL<PCM_ON>
PWE pin
INTRTC
INT0-7, INTKEY
Interrupt enabled period
Internal HOT_RESET
Port state
Drive register active period
5. The drive register setting is
released a maximum of 1 clocks
(31 μs) after the end of warm-up.
1. This interrupt is
ignored.
4. These interrupts
are ignored.
Internal HOT_RESET assert to dead circuit only. (DVCC1A &DVCC1C circuit)
1. If it is set PMCCTL<PCM_ON>=“1”, shift the Power Cut Mode, however, it spends
3-clock times maximum (around 92μS) to shift from normal mode to Power Cut Mode.
And the wake-up triggers during this 3-clock times, are ignored.
2. It spends 2.5-clock times maximum (around 77μS) from the trigger to wake-up to rise-up
the PWE terminal.
3. After wake-up from Power Cut Mode, reset to "0" the PMCCTL<PCM_ON> bit by soft
ware. If you want to shift Power Cut Mode again, need to wait 1-clock time minimum
(around 31μS).
4. The wake-up triggers during waking-up, are ignored.
5. After Warm-up count, and spend 1-clock time (around 31μS), release the DRV setting of
every ports. After that, spends 2-clock time (around 62μS), release internal RESET
(Hot_Reset).
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Regulator
1.5V
Regulator
3.0V
SW en
Delay Circuit
SW en
SW en
0
S 1
TMP92CZ26A
AVCC
DVCC-1C DVCC-1A
DVCC-1B DVCC-3A,3B
Power On
RESET
RTC
CPU
LOW_OSC
RAM16kB
Power management
signal (PWE)
Other Logic
High_OSC
ADC
I/O
PMC
External interrupt
INT0-7
(INT4 also supports TSI.)
INTKEY
AVSS
DVSS-1C
DVSS-COM
XT1 XT2
Main
Power
Figure3.25.2 Example External Circuitry for Using the PMC
Figure3.25.2 shows an example of external circuitry for using the PMC.
In normal mode, the power management pin (PWE) outputs “1” and power is supplied to all
the blocks in the TMP92CZ26A.
In the Power Cut Mode, the power management pin (PWE) outputs “0” and power is cut off for
the internal circuitry excluding the CPU, part of internal RAM, AD converter and RTC to
reduce leak current. In the Power Cut Mode, power is supplied to only the I/O (including the AD
pins), TSI circuit, 16 Kbytes of internal RAM, low-frequency oscillation circuit, RTC and PMC.
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3.25.4 Notes of Power sequence
Power ON/Power OFF Sequence (Initial Power ON/Complete Power OFF)
•
In the power ON sequence (initial power ON), power must be supplied to internal circuits
first and then to external circuits, as shown below. In the power OFF sequence (complete
power OFF), power must be turned off from external circuits so that internal circuits are
turned off last.
Power ON
(DVCC1A, DVCC1B, DVCC1C) → (DVCC3A, DVCC3B, AVCC)
Power OFF
(AVCC, DVCC3A, DVCC3B) → (DVCC1C, DVCC1B, DVCC1A)
Power off
Power on
Power Cut Mode (PMC)
DVCC1A
DVCC1B
DVCC1C
Power increases and
Power decreases and
stabilizes within 100 ms.
stabilizes within 100 ms.
1.5V rails should be
3.0V rails should be
turned on first, followed
by 3.0V rails.
turned off first, followed by
1.5V rails.
DVCC3A
DVCC3B
AVCC
Oscillator Wake-up time to be stable
＋20 system clock
RESET
PWE terminal
Note1: Although it is possible to turn on or off 1.5V and 3.0V rails simultaneously, external pins may temporarily
become unstable in this case. Therefore, if there is any possibility that this would affect external devices
connected with the TMP92CZ26A, external power supplies should be turned on or off while internal power
supplies are stable, as shown in the diagram above.
Note2: In the power ON sequence, 3V rails must not be turned on before 1.5V rails. In the power OFF sequence, 3V
rails must not be turned off after 1.5V rails.
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3.25.5 Setting Example
Condition: Wake-up trigger=INT4(TSI)
org
002000h
ld
(syscr0),40h
;
;
;
;
;
;
;
Enable low frequency clock
Disable WDT
ldw
ldw
ldw
ldw
ld
(wdmod),0b100h
(admod0),0000h
(admod2),0000h
(admod4),0000h
(lcdctl0),00h
Disable AD converter
Disable DMA operation
ld
(pmfc),80h
Set PM7 port to PWE function
ld
ld
ld
(p9fc),40h
(inte34),50h
(tsicr1),00h
;
;
;
Set INT4 and set level
Disable de-bounce circuit
ld
ld
ld
(pllcr0), 00h
(pllcr1), 00h
(pmcctl),00h
;
;
Change CPU clock from PLL to fOSCH
Stop the PLL circuit
;
;
;
Set Warm-up time
di
ld
(pmcctl),80h
Enable <PCM_ON> = 1
Shift to Power Cut Mode
; After Wake-up
org
046000h
ld
(pmcctl),00h
;
Disable <PCM_ON> = 0
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3.26 Multiply and Accumulate Calculation Unit (MAC)
The TMP92CZ26A includes a multiply-accumulate unit (MAC) capable of 32-bit × 32-bit + 64-bit
arithmetic operations at high speed. The MAC has the following features:
・One-cycle execution for all MAC operations (excluding register access time)
・Three operation modes : 1) 64-bit + 32-bit × 32-bit
2) 64-bit − 32-bit × 32-bit
3) 32-bit × 32-bit − 64-bit
・Support for signed/unsigned operations
・Support for integer operations only
3.26.1 Registers
The MAC in the TMP92CZ26A has one control register and three data registers. These
registers are connected to the CPU via a 32-bit bus and can be accessed in one system clock
(fSYS).
3.26.1.1
Control Register
The control register is used to control the operation of the MAC.
MAC Control Register
7
6
MOPST
W
5
4
3
2
1
0
bit Symbol
MOVF
R/W
MSTTG2
MSTTG1
R/W
MSTTG0
MSGMD
R/W
MOPMD1 MOPMD0
R/W
Read/Write
After reset
MACCR
(1BFCH)
0
0
0
0
0
0
0
0
Prohibit
Read-modify
-write
Overflow
flag
Calculation
soft start
Calculation start trigger
Sign mode
Calculation mode
000: Write to MACMA<7:0>
0: Unsigned 00: 64 + 32×32
0: No
0:Don’t care 001: Write to MACMB<7:0>
1:Start 010: Write to MACMOR<7:0>
1: Signed
01: 64 − 32×32
10: 32×32 − 64
11: Reserved
Function
overflow
1: Overflow calculation
occurred
011: Write to MACMOR<39:32>
1xx: Write of “1” to <MOPST>
Note 1: <MOPST> is write-only and it is read as “0”.
Note 2: Writing “1xx” to <MSTTG2:0> and writing “1” to <MOPST> can be executed in the same write cycle.
Note 3: <MOVF> is fixed two system clocks (f ) after calculation is started.
SYS
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3.26.1.2
Data Registers
The data registers are arranged as shown below.
Data Registers
Bits<63:56> Bits<55:48> Bits<47:40> Bits<39:32> Bits<31:24> Bits<23:16> Bits<15:8>
Bits<7:0>
Multiplier A
MACMA
(1BE0H)
MACMB
(1BE4H)
MACORL
(1BE8H)
Register
Multiplier B
Register
MAC
(1BE3H)
(1BE7H)
(1BEBH)
(1BE2H)
(1BE6H)
(1BEAH)
(1BE1H)
(1BE5H)
(1BE9H)
MACORH
(1BECH)
Register
(1BEFH)
(1BEEH)
(1BEDH)
Note 1: After reset, all the registers are cleared to “0”.
Note 2: Read-modify-write instructions can be used on all the registers.
Note 3: All the registers can be accessed in long word, word, or byte units.
Note 4: When MACCR<MSTTG2:0> is set to “0”, “001”, “010” or “011” and the registers are written in word or byte units, the
<7:0> bits of each register must be written last.
Note 5: The MACORL register is fixed one system clock (f
) after calculation is started, and the MACORH register is fixed
SYS
two system clocks (f
) after calculation is started. Therefore, to read the MACOR register immediately after
SYS
calculation, be sure to read the MACORL register first.
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3.26.2 Description of Operation
(1) Calculation mode
The MAC has the following three types of calculation mode. The calculation mode to be used
is specified in MACCR<MOPMD1:0>. MACCR<MSMD> is used to select unsigned or signed
mode. The operation of each calculation mode is explained below.
(a) 64 + 32 × 32 mode
In this mode, the contents of the MACMA register and the MACMB register are
multiplied and the result is added to the contents of the MACOR register. Then, the result
is stored back in the MACOR register.
31
63
0
31
0
63
0
MACMB
MACMA
MACOR
+
×
MACOR
(b) 64 − 32 × 32 mode
In this mode, the contents of the MACMA register and the MACMB register are
multiplied and the result is subtracted from the contents of the MACOR register. Then, the
result is stored back in the MACOR register.
31
63
0
31
0
63
0
MACMB
MACMA
−
×
MACOR
MACOR
(c) 32 × 32 − 64 mode
In this mode, the contents of the MACMA register and the MACMB register are
multiplied and the contents of the MACOR register are subtracted from the result. Then,
the result is stored back in the MACOR register.
31
0
31
0
63
0
63
0
MACMB
MACMA
×
−
MACOR
MACOR
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(d) Sign mode
Both multiply-accumulate and multiply-subtract operations can be executed in unsigned
or signed mode.
In signed mode, the MACMA, MACMB, and MACOR registers become signed registers,
and the most significant bit is treated as the sign bit and the data set in each register is
represented in each sign mode.
Table 3.26.1 Data Range in Unsigned/Signed Mode
MACMA, MACMB Registers
0 ∼ 232−1
MACOR Register
0 ∼ 264−1
Unsigned
Signed
−231 ∼ +231-1
−263 ∼ +263−1
Use signed mode when the values to be set in the MACMA and MACMB registers are
signed (two’s complement) data. Even in unsigned mode it is possible to set signed (two’s
complement) data in the MACOR register to perform additions and subtractions in signed
mode.
(2)
Calculation start trigger
As a trigger to start calculation, writing to the MACMA, MACMB or MACOR register or
soft start (MACCR<MOPST>=1) can be selected in MACCR<MSTTG2:0>.
(3)
Overflow flag
to “1”. Once an overflow occurs, MACCR<MOVF> is held at “1” regardless of subsequent
calculation results. Since the overflow flag is not automatically cleared by a read operation, it
is necessary to write “0” to clear this flag.
Table 3.26.2 Overflow Definitions
Calculation Result
Sign Mode
MACCR<MOVF>
(MACOR register value)
MACOR > 264−1
0 ≤ MACOR ≤ 264−1
MACOR < 0
MACOR > 263−1
−263 ≤ MACOR ≤263−1
MACOR < −263
1
0
1
1
0
1
Signed
Unsigned
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3.26.3 Operation Examples
(1) Unsigned multiply-accumulate operation
The following shows a setting example for calculating “33333333 + 11111111 × 22222222”:
ld
(MACCR), 0x08
; Unsigned multiply-accumulate mode
Start calculation by write to MACMB.
ld
ld
ld
ld
ld
ld
ld
ld
ld
bit
jp
ld
xde, 0x00000000
xhl, 0x33333333
xix, 0x11111111
xiy, 0x22222222
(MACORL), xhl
(MACORH), xde
(MACMA), xix
(MACMB), xiy
xhl, (MACORL)
7, (MACCR)
; Write 33333333 to MACORL.
; Clear MACORH.
; Write 11111111 to MACMA.
; Write 22222222 to MACMB.
; Read lower result 0x41FDB975.
; Check over-flow error
Calculation start
nz, ERROR
; Go to error routine, if there is over-flow error
; Read upper result 0x02468ACF.
xde, (MACORH)
(2) Signed multiply-subtract operation
The following shows a setting example for calculating “33333333 − 11111111 × −22222222”:
ld
(MACCR), 0x25
; Signed multiply-subtract mode
Start calculation by write of “1” to <MOPST>.
ld
ld
ld
ld
ld
ld
ld
ld
set
ld
bit
jp
ld
xde, 0x00000000
xhl, 0x33333333
xix, 0x11111111
xiy, 0xDDDDDDDE
(MACORL), xhl
(MACORH), xde
(MACMA), xix
(MACMB), xiy
5, (MACCR)
; −22222222
; Write 33333333 to MACORL.
; Clear MACORH.
; Write 11111111 to MACMA.
; Write −22222222 to MACMB.
Calculation start
;
xhl, (MACORL)
7, (MACCR)
; Read lower result 0x41FDB975.
; Check over-flow error
nz, ERROR
; Go to error routine, if there is over-flow error
; Read upper result 0x02468ACF.
xde, (MACORH)
(3) Unsigned multiply-accumulate operation (two multiply-accumulate operations)
The following shows a setting example for calculating “(33333333 + 11111111 × 22222222) +
(11111111 × 44444444)”:
ld
(MACCR), 0x08
; Unsigned multiply-accumulate mode
Start calculation by write to MACMB.
ld
ld
ld
ld
ld
ld
ld
ld
ld
ld
ld
bit
jp
ld
xde, 0x00000000
xhl, 0x33333333
xix, 0x11111111
xiy, 0x22222222
xiz, 0x44444444
(MACORL), xhl
(MACORH), xde
(MACMA), xix
(MACMB), xiy
(MACMB), xiz
xhl, (MACORL)
7, (MACCR)
; Write 33333333 to MACORL.
; Clear MACORH.
; Write 11111111 to MACMA.
; Write 22222222 to MACMB.
; Write 44444444 to MACMB.
; Read lower result 0x5F92C5F9.
; Check over-flow error
Calculation start
Calculation start
nz, ERROR
; Go to error routine, if there is over-flow error
; Read upper result 0x06D3A06D.
xde, (MACORH)
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3.27 Debug Mode
The TMP92CZ26A includes a debug support unit (DSU) for enabling on-board debugging.
The DSU has 9 debug pins for interfacing with an external emulator via a DSU connector to be
mounted on the target board and a DSU connecting cable. For details about debugging, please
refer to the instruction manual of the emulation pod to be used.
This section provides product-specific explanations related to debug mode.
(1) Connection method
Target Board
DSU Connecting
Cable
TMP92CZ26A
EI_PODDATA
EI_SYNCLK
EI_PODREQ
EI_REFCLK
DSU
Connector
Emulation
Pod
Controller
PC
EI_TRGIN
EI_COMRESET
EO_MCUDATA
EO_MCUREQ
EO_TRGOUT
DBGE
Note: When connecting the TMP92CZ26A and an emulator in debug mode, place the DSU connector on the target
board as near (less than 5cm) to the TMP92CZ26A as possible. It is desirable that all the signals are same
length.
Recommend connector:
SAMTEC FTSH-110-01-DV-EJ
(2) How to enter debug mode
Debug mode can be entered by setting the DBGE pin to Low. To return to normal mode from
debug mode, be sure to set the DBGE pin to High and then reset the system using the RESET
pin. In details of debus mode, refer the manual of emulation POD.
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(3) Limitations in debug mode
Debug mode has the following limitations:
1) Target reset
While debugging is being performed, the system reset ( RESET pin) of the target
(microcontroller) must not be used to reset the controller and microcontroller. Instead,
reset should be performed from the controller. (For details, please refer to the instruction
manual of the emulation pod to be used.)
* If reset from the microcontroller by the RESET pin may clash the register information
and internal RAM data in the CPU, including not only programs but also breakpoint
and trace information.
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2) Pins
In debug mode, a total of 9 pins (PZ0 to PZ7 in Port Z and PU7 in Port U) are used to
connect the TMP92CZ26A with an emulator via a DSU probe for communicating with the
controller. For this reason, these 9 pins cannot be debugged. Therefore, if the port control
register of each pin is changed in debug mode, the register contents are changed but the
function of each pin remains the same.
Port Z Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
PZ7
PZ6
PZ5
PZ4
PZ3
PZ2
PZ1
PZ0
PZ
(0068H)
R/W
External pin data (Output latch is reset to “0”.)
Port Z Control Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PZ7C
PZ6C
PZ5C
PZ4C
PZ3C
PZ2C
PZ1C
PZ0C
PZCR
(006AH)
W
0
0
0
0
0
0
0
0
0: Input 1: Output
Port Z Function Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PZ7F
PZ6F
PZ5F
PZ4F
PZ3F
PZ2F
PZ1F
PZ0F
PZFC
(006BH)
W
0
0
0
0
0
0
0
0
0: Port
Port Z Drive Register
7
6
5
4
3
2
1
0
bit Symbol
Read/Write
After reset
Function
PZ7D
PZ6D
PZ5D
PZ4D
PZ3D
PZ2D
PZ1D
PZ0D
PZDR
(009AH)
R/W
1
1
1
1
1
1
1
1
Input/output buffer drive register for standby mode
Note: Although it is possible to write to shaded bits, writing to these bits has no effect (the DSU communication function is
given a higher priority).
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Port U Register
4
7
6
5
3
2
1
0
Bit Symbol
Read/Write
After reset
PU7
PU6
PU5
PU4
PU3
PU2
PU1
PU0
PU
(00A4H)
R/W
External pin data (Output latch is reset to “0”.)
Port U Control Register
7
PU7C
6
PU6C
5
PU5C
4
PU4C
3
PU3C
W
2
PU2C
1
PU1C
0
PU0C
Bit Symbol
Read/Write
After reset
Function
PUCR
(00A6H)
0
0
0
0
0
0
0
0
0: Input 1: Output
Port U Function Register
7
PU7F
6
PU6F
5
PU5F
4
PU4F
3
PU3F
W
2
PU2F
1
PU1F
0
PU0F
Bit Symbol
Read/Write
After reset
Function
PUFC
(00A7H)
0
0
0
0
0
0
0
0
0: Port 1: Data bus for LCDC (LD23 to LD16)
Note: When LD23 to LD16 are used, set <PUnC> to “1”.
Port U Drive Register
7
PU7D
6
PU6D
5
PU5D
4
PU4D
3
PU3D
R/W
1
2
PU2D
1
PU1D
0
PU0D
Bit Symbol
Read/Write
After reset
Function
PUDR
(009CH)
1
1
1
1
1
1
1
Input/output buffer drive register for standby mode
Note: Although it is possible to write to shaded bits, writing to these bits has no effect (the DSU communication function is
given a higher priority).
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3) Boot function
In this LSI, we support boot function, however, this boot function is not available in
debug mode. (It is inhibit to set DBGE =“0”, AM0=“1” and AM1=“1” at the same time.)
4) PMC function
In debug mode, the PMC function for cutting off the power supply to internal circuitry
and reducing standby current is not also available.
BROMCR Register Specifications in Debug Mode
7
6
5
4
3
2
1
0
BROMCR Bit symbol
CSDIS
ROMLESS
R/W
VACE
(016CH)
Read/Write
After reset
Function
1
1*
1/0
NAND
Flash area
CS output
Boot ROM
0: Used
1: Not used
Vector
address
conversion
0: Enable
1: Disable
0: Disable
1: Enable
7
6
5
4
3
2
−
1
0
bit symbol
PMCCTL
PCM_ON
WUTM1
WUTM0
(02F0H)
Read/Write
R/W
W
R/W
R/W
After
system
reset
0
0
0
0
After hot
reset
Data
retained
−
−
−
Power Cut
Mode
Always write
“0”.
Warm-up time
00: 29 (15.625 ms)
01: 210 (31.25 ms)
10: 211 (62.5 ms)
11: 212 (125 ms)
Function
0: Disable
1: Enable
Always read
ad “0”.
Note: Even if the <PCM_ON> bit is set to “1”, the Power Cut Mode cannot be entered (the external PWE pin is not set to “0”).
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5) Data bus occupancy
The TMP92CZ26A includes three controllers (LCD controller, SDRAM controller and
DMAC) that function as bus masters apart from the CPU. Therefore, it is necessary to
estimate the bus occupancy time of each bus master and control each function accordingly
to ensure proper operation of each function. (For details, please refer to the chapter on the
DMA controller.)
In debug mode, in addition to the operations of these bus masters, a steal program that
runs in the background must also be taken into account in programming. When the
program stops at a breakpoint (including step execution), the CPU operation is halted but
the LCD controller, SDRAM controller and DMA controller remain active. At this time, the
steal program also runs in the background. Once the steal program obtains the bus, it
occupies the bus for 80 times of debug transmission clock (LH_SYNCLK) maximum.
Therefore, in some cases, other DMA operations (LCD display, DMAC data transfer,
SDRAM refresh) may not be performed at desired timing.
Setup time 1
LHSYNC
LCP0
LD-bus
2
LCD DMA operation 1
Setup time 2
HDMA operation
(Worst case)
1
LCD DMA operation 2
Figure 3.27.1 Example of Data Bus Occupancy Timing in Non-Debug Mode
Figure 3.27.1 shows an example of data bus occupancy timing in non-debug mode,
depicting the LHSYNC signal, LCP0 signal, and LD-bus signal for transferring data from
the LCD controller to the LCD driver, and the LCD DMA operation timing for reading
data from the display RAM.
If HDMA is asserted immediately before the DMA operation for the LCD (LCD DMA
operation 1) is started, this operation must wait until HDMA is finished before it can be
performed (LCD DMA operation 2).
Taking the above into account, it is necessary to ensure that each LCD DMA operation is
finished before the next LCD driver output is started.
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Setup time 1
LHSYNC
LCP0
LD-bus
3
2
1
LCD DMA operation 1
Setup time 2
HDMA operation 1
(Worst case)
Steal operation
(Worst case)
LCD DMA operation 2
HDMA operation 2
Figure 3.27.2 Example of Data Bus Occupancy Timing in Debug Mode
Figure 3.27.2 shows an example of data bus occupancy timing in debug mode. If the steal
program issues a wait request immediately before the DMA operation for the LCD (LCD
DMA operation 1) and HDMA (HDMA operation 1) are asserted, these operations must
wait until the steal program is finished before they can be performed. (LCD DMA is given a
higher priority than HDMA in bus arbitration. This means that bus requests is
sued for LCD DMA and HDMA while the steal program is running are processed in the
order of LCD and HDMA (LCD DMA operation 2 → HDMA operation 2) regardless of the
order in which they are issued. )
Taking the above into account, it is necessary to ensure that each LCD DMA or HDMA
operation is finished before the next LCD driver output is started.
In other words, to avoid abnormal operation in debug mode, the maximum duration of
HDMA operation time must be set so that it does not interfere with LCD DMA operation.
Alternatively, the LHSYNC period should be adjusted to accommodate a wait request by
the steal program (80 times of transmission for debug clock: LH_SYNCLK), although this
slightly reduces the LCD display quality.
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4. Electrical Characteristics (Tentative)
4.1 Maximum Ratings
Symbol
Contents
Rating
Unit
DVCC3A
DVCC3B
DVCC1A
DVCC1B
DVCC1C
AVCC
-0.3 to 3.9
Power Supply Voltage
V
-0.3 to 3.0
-0.3 to 3.9
-0.3 ～DVCC3A/3B+0.3 (Note1)
V
Input Voltage
V
IN
-0.3 to AVCC + 0.3 (Note2)
IOL
Output Current (1pin)
Output Current (1pin)
Output Current (total)
15
mA
mA
mA
IOH
-15
Σ
80
-50
IOL
Σ
Output Current (total)
mA
mW
°C
IOH
P
Power Dissipation (Ta = 85°C)
Soldering Temperature (10s)
Storage Temperature
600
D
T
260
SOLDER
T
STG
-65 to 150
-0 to 70
°C
T
T
Operation Temperature
°C
OPR
Operation Temperature
(80MHz)
-0 to 50
°C
OPR
Note1: If setting it, don’t exceed the Maximum Ratings of DVCC3A (PV port and PW port are DVCC3B).
Note2: In PG0 to PG5, P96,P97,VREFH,VREFL maximum ratings for AVCC is applied.
Note3: The maximum ratings are rated values that must not be exceeded during operation, even for an instant. Any
one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its
performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when
designing products that include this device, ensure that no maximum rating value will ever be exceeded.
Point of note about solderability of lead free products (attach “G” to package name)
Test
parameter
Test condition
Note
Solderability
Solder bath temperature = 230°C, Dipping time = 5 seconds
The number of times = one, Use of R-type flux
Pass:
solderability rate until forming
≥ 95%
Solder bath temperature =245°C, Dipping time = 5 seconds
The number of times = one, Use of R-type flux (use of lead free)
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Condition
4.2 DC Electrical Characteristics
Symbol
Parameter
Min
Typ.
Max
Unit
General I/O
DVCC
3A
Power Supply Voltage
(DVCC=AVCC)
3.0
3.3
3.6
V
X1=6 to
10MHz
(DVSSCOM=AVSS=0V)
CPU CLK
(60MHz)
CPU CLK
(80MHz)
XT1=30
DVCC
1A
Internal Power A
to 34KHz
DVCC
1B
1.4
1.5
1.6
V
Internal Power B
DVCC
1C
High CLK oscillator and PLL Power
Input Low Voltage for
D0 to D7
P10 to P17 (D8 to 15), P60 to P67
P71 to P76, P90
3.0≦DVCC3A≦3.6
VIL0
−
0.3×DVCC3A
PC4 to PC7, PF0 to PF5
PG0 to PG5, PJ5 to PJ6
PN0 to PN7, PP1 to PP2
PR0 to PR3, PT0 to PT7
PU0 to PU7, PX5, PX7
Input Low Voltage for
PV0 to PV2, PV6 to PV7, PW0 to PW7
Input Low Voltage for
3.0≦DVCC3B≦3.6
VIL1
VIL2
–
–
0.3×DVCC3B
-0.3
V
0.25×
P91 to P92, P96 to P97, PA0 to PA7
PC0 to PC3, PP3 to PP5, PZ0 to PZ7,
RESET
3.0≦DVCC3A≦3.6
DVCC3A
Input Low Voltage for
0.1×DVCC3A
0.1×DVCC1C
0.15 ×DVCC3A
3.0≦DVCC3A≦3.6
1.4≦DVCC1C≦1.6
3.0≦DVCC3A≦3.6
VIL3
VIL4
VIL5
–
–
–
AM0 to AM1,
DBGE
Input Low Voltage for
X1
Input Low Voltage for
XT1
Note: Above power supply range is premised that all power supply of same system is equal.
(DVCC1A = DVCC1B = DVCC1C or DVCC3A = DVCC3B=AVCC)
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Condition
Symbol
Parameter
Min
Typ.
Max
Unit
Input High Voltage for
D0 to D7
P10 to P17 (D8 to 15), P60 to P67
P71 to P76, P90
0.7 ×
3.0≦DVCC3A≦3.6
VIH0
–
DVCC3A + 0.3
PC4 to PC7, PF0 to PF5
PG0 to PG5, PJ5 to PJ6
PN0 to PN7, PP1 to PP2
PR0 to PR3, PT0 to PT7
PU0 to PU7, PX5, PX7
Input High Voltage for
PV0 to PV2, PV6 to PV7, PW0 to PW7
Input High Voltage for
DVCC3A
0.7 ×
3.0≦DVCC3B≦3.6
VIH1
VIH2
–
–
DVCC3B + 0.3
DVCC3A + 0.3
DVCC3B
V
0.75×
P91 to P92, P96 to P97, PA0 to PA7
PC0 to PC3, PP3 to PP5, PZ0 to PZ7,
RESET
3.0≦DVCC3A≦3.6
DVCC3A
0.9×
Input High Voltage for
3.0≦DVCC3A≦3.6
1.4≦DVCC1C≦1.6
3.0≦DVCC3A≦3.6
VIH3
VIH4
VIH5
–
–
–
DVCC3A + 0.3
DVCC1C + 0.3
DVCC3A + 0.3
AM0 to AM1 ,
DBGE
DVCC3A
Input High Voltage for
0.9×DVCC1C
X1
Input High Voltage for
XT1
0.85×
DVCC3A
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Symbol
Parameter
Min
Typ.
Max
Unit
Condition
Output Low Voltage1
P90 to P92,
PC0 to PC3, PC7
PF0 to PF5, PK1 to PK7
PM1 to PM2, PM7
PN0 to PN7, PP1 to PP7
PV0 to PV7, PW0 to PW7,
PX5, PX7
IOL = 0.5mA, 3.0≦DVCC3A
IOL = 2mA, 3.0≦DVCC3A
IOH = -0.5mA, 3.0≦DVCC3A
IOH = -2mA, 3.0≦DVCC3A
VOL1
–
–
0.4
Output Low Voltage2
Except VOL1 output pin
Output High Voltage1
P90 to P92,
VOL2
VOH1
V
PC0 to PC3, PC7
PF0 to PF7, PK1 to PK7
PM1 to PM2, PM7
2.4
–
–
PN0 to PN7, PP1 to PP7
PV0 to PV7, PW0 to PW7
PX5, PX7
Output High Voltage2
Except VOL1 output pin
Output Low Voltage for
P96(PX), P97(PY)-pins
Output High Voltage for
P96(PX), P97(PY)-pins
Input Leakage Current
VOH2
VOL(T)
VOH(T)
–
–
–
0.2
IOL(T)=6.6mA
3.0≦DVCC3A≦3.6
VCC-0.2
–
IOH(T)=-6.6mA
0.0 ≦Vin ≦DVCC3A
ILI
–
–
0.02
0.05
±5
±10
μA
μA
0.2 ≦Vin ≦DVCC3A-0.2V
ILO
Output Leakage Current
Pull Up/Down Resistor for
RRST
CIO
30
50
70
10
KΩ
, PA0 to PA7, P96
RESET
Pin Capacitance
Schmitt Width for
–
–
pF
fc=1MHz
P91 to P92, P96 to P97,
3.0≦DVCC3A≦3.6
VTH
0.6
0.8
1.0
V
PA0 to PA7, PC0 to PC3, PP3 to PP5,
PZ0 to PZ7,
RESET
Note1 : Typical values are value that when Ta = 25°C and Vcc = 3.3 V unless otherwise noted.
Note2 : This data shows exept "debug mode"
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Symbol
Parameter
Min
Typ.
Max
Unit
Condition
−
15
45
0.5
28
12
34
0.4
21
30
60
1
45
23
45
0.8
34
DVCC3A,3B = 3.6V
DVCC1A,1B,1C = 1.6V
DVCC3A,3B = 3.6V
DVCC1A,1B,1C = 1.6V
DVCC3A,3B = 3.6V
DVCC1A,1B,1C = 1.6V
DVCC3A,3B = 3.6V
DVCC1A,1B,1C = 1.6V
NORMAL (note2)
PLL_ON
f
f
SYS=80MHz
−
−
−
IDLE2
mA
NORMAL (note2)
IDLE2
PLL_ON
SYS=60MHz
−
12
45
PLL_OFF
DVCC3A,3B = 3.6V
IDLE1
μA
fSYS =10MHz
200
3200
DVCC1A,1B,1C = 1.6V
Ta ≦70℃
35
30
DVCC3A=3.6V
DVCC3B=3.6V
AVCC=3.6V
6
Ta ≦50℃
ICC
Power Cut Mode
(WITH PMC function )
−
DVCC1A=0V
DVCC1B=1.6V
DVCC1C=0V
XT=32KHz
Ta ≦70℃
50
35
2
6
Ta ≦50℃
X=OFF
μA
Ta ≦70℃
35
30
DVCC3A=3.6V
DVCC3B=3.6V
AVCC3.6V
Ta ≦50℃
STOP
−
DVCC1A=1.6V
DVCC1B=1.6V
DVCC1C=1.6V
XT=OFF
Ta ≦70℃
800
600
200
Ta ≦50℃
X=OFF
Note1 : Typical values are value that when Ta = 25°C and Vcc = 3.3 V unless otherwise noted.
Note2 : ICC measurement conditions (NORMAL, SLOW):
All functions are operational; output pins except bus pin are open, and input pins are fixed. Bus pin CL=50pF
(Access toexternal memory at 8-waitsetting )
Note3: This data shows exept "debug mode"
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4.3 AC Characteristics
The Following all AC regulation is the measurement result in following condition, if unless otherwise noted.
AC measuring condition
Clock of top column in above table shows system clock frequency, and “T” shows system
•
clock period [ns].
Output level: High = 0.7×3AV , Low = 0.3×3AV
•
CC
CC
Input level: High = 0.9×3AV , Low = 0.1×3AV
•
CC
CC
Note: In table, “Variable” shows the regulation at DVCC3A=3.0V~3.6V, DVCC1A=DVCC1B=DVCC1C=1.4~1.6V.
4.3.1
No.
Basic Bus Cycle
Read cycle
Variable
Parameter
Symbol
80 MHz 60 MHz Unit
Min
Max
t
1
2
3
4
OSC period (X1/X2)
100
166.6
266.6
−
−
OSC
t
System clock period ( = T)
12.5
12.5
3.25
3.25
16.6
5.3
5.3
CYC
t
SDCLK low width
0.5T − 3
0.5T − 3
CL
t
SDCLK high width
CH
A0 ~ A23 valid → D0 ~ D15 input at 0
t
5-1
5-2
2.0T − 18.0
7
15.3
AD
waits
t
6.0T − 18.0
8.0T - 18.0
1.5T − 18.0
1.5T − 18.0
5.5T − 18.0
5.5T − 18.0
−
82
82
−
A0 ~ A23 valid
AD6
→ D0 ~ D15 input at 4 waits/6 waits
t
AD7
t
−
7
RD
RD falling → D0 ~ D15 input at 0 waits
6-1
6-2
t
0.75
−
−
RD
t
RD falling
73.6
−
RD6
ns
→ D0 ~ D15 input at 4 waits/6waits
t
50.75
8.75
58.75
1.25
1.25
0
RD7
RD low width at 0 waits
RD low width at 4 waits
t
7-1
7-2
8
1.5T − 10
14.9
81.3
3.3
3.3
0
RR
t
5.5T − 10
RR6
A0 ~ A23 valid
→
RD falling
t
0.5T − 5
AR
RD falling → SDCLK rising
t
9
0.5T − 5
RK
t
10 A0 ~ A23 valid → D0 ~ D15 hold
0
0
3
2
HA
RD rising →D0 ~ D15 hold
WAIT setup time
t
11
12
13
0
0
HR
t
3
5
TK
WAIT hold time
t
2
3
KT
t
14 Data byte control access time
RD high width
1.5T − 18.0
0.75
1.25
7
SBA
t
15
0.5T − 5
3.3
RRH
AC measuring condition
• Data_bus, Address_bus, various function control signal capacitance CL = 50 pF
Note: The operation guarantee temprature: 80MHz: Ta=0∼50°C, less than 60MHz: Ta=0∼70°C
92CZ26A-645
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TMP92CZ26A
Write cycle
Parameter
Variable
Min Max
No.
Symbol
80MHz 60MHz Unit
t
1.0T − 10.0
−
6.6
D0 ~ D15 valid
DW
16-1
→ WR xx rising at 0 waits
t
1.0T − 6.0
3.0T − 10.0
5.0T − 6.0
1.0T − 7.0
1.0T − 4.0
3.0T − 7.0
5.0T − 4.0
0.5T − 5.0
0.5T − 5.0
0.5T − 5.0
0.5T − 5.0
0.5T − 2.0
0.5T − 1.0
1.5T − 2.0
2.5T − 1.0
1.0T − 7.0
1.0T − 4.0
1.0T − 7.0
1.0T − 4.0
0.5T − 5.0
0.5T − 5.0
1.0T − 10.0
1.0T − 6.0
0.5T − 5.0
6.5
−
−
39.8
−
DW
t
D0 ~ D15 valid
DW4
16-2
17-1
17-2
→ WR xx rising at 2 waits/4 waits
t
56.5
−
DW6
t
9.6
−
WW
WR xx low width at 0 waits
t
8.5
−
WW
t
42.8
−
WW4
WR xx low width at 2 waits/4 waits
t
58.5
1.25
1.25
1.25
1.25
−
WW6
A0 ~ A23 valid
→
WR falling
t
18
19
20
21
3.3
3.3
3.3
3.3
6.3
−
AW
WR xx falling → SDCLK rising
t
WK
WR xx rising
WR xx rising
RD rising
→ A0 ~ A23 hold
→ D0 ~ D15 hold
→ D0 ~ D15 output
t
WA
t
WD
ns
t
RDO
22-1
22-2
t
5.25
−
RDO
t
22.9
−
RDO
RD rising
→ D0 ~ D15 output
t
30.25
−
RDO
t
9.6
−
SWP
23 Write width for SRAM
t
8.5
−
SWP
t
9.6
−
Data byte control ~ end of write
SBW
24
for SRAM
t
8.5
1.25
1.25
−
SBW
t
25 Address setup time for SRAM
26 Write recovery time for SRAM
3.3
3.3
6.6
−
SAS
t
SWR
t
SDS
27 Data setup time for SRAM
28 Data hold time for SRAM
t
6.5
1.25
SDS
t
3.3
SDH
AC measuring condition
Note: The operation guarantee Temperature: 80MHz: Ta=0∼50°C, less than 60MHz: Ta=0∼70°C
92CZ26A-646
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TMP92CZ26A
(1) Read cycle (0 waits)
t
OSC
X1
t
CYC
t
t
CH
CL
SDCLK
WAIT
t
t
KT
TK
A0~A23
CSn
t
AD
t
HA
R/ W
RD
t
t
RK
AR
t
HR
t
t
t
RRH
RR
RD
D0~D15
Data input
t
SBA
SRxxB
SRWR
Note1: The phase relation between X1 input signal and the other signals is undefined.
Note2: The above timing chart show an example of basic bus timing. The CSn , R/ W , RD , WRxx , SRxxB , SRWR
pins timing can be adjusted by memory controller timing adjust function.
92CZ26A-647
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TMP92CZ26A
(2) Write cycle (0 waits)
t
OSC
X1
t
CYC
t
t
CH
CL
SDCLK
WAIT
t
t
KT
TK
A0~A23
CSn
R/ W
t
t
t
WA
AW
WK
WRxx
t
t
SWR
WW
t
t
WD
DW
D0~D15
Data output
t
RDO
RD
SRxxB
SRWR
t
SDH
t
SBW
t
SDS
t
SAS
t
SWP
Note1: The phase relation between X1 input signal and the other signals is undefined.
Note2: The above timing chart show an example of basic bus timing. The CSn , R/ W , RD , WRxx , SRxxB , SRWR
pins timing can be adjusted by memory controller timing adjust function.
92CZ26A-648
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TMP92CZ26A
(3) Read cycle (1 wait)
SDCLK
WAIT
A0~A23
t
AD3
CSn
R/ W
RD
t
t
RR3
RD3
D0~D15
Data input
(4) Write cycle (1 wait)
SDCLK
WAIT
A0~A23
CSn
R/ W
WRxx
t
WW3
t
DW3
D0~D15
Data output
t
RDO
RD
92CZ26A-649
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TMP92CZ26A
4.3.2
Page ROM Read Cycle
(1) 3-2-2-2 mode
Variable
Max
Parameter
Symbol
80 MHz 60 MHz Unit
Min
System clock period ( = T)
t
12.5
266.6
12.5
7
16.6
15.2
31.8
1
2
3
4
5
6
CYC
t
t
t
2.0T − 18
3.0T − 18
A0, A1
→ D0 ~ D15 input
AD2
AD3
19.5
A2 ~ A23
RD falling
→ D0 ~ D15 input
ns
→ D0 ~ D15 input
2.5T − 18
13
0
24
0
RD3
A0 ~ A23 Invalid → D0 ~ D15 hold
RD rising → D0 ~ D15 hold
t
0
0
HA
t
0
0
HR
AC measuring condition
Note: The (a), (b) and (c) of “Symbol” in above table depend on the falling timing of RD pin. The falling timing of
RD pin is set by MEMCR0<RDTMG1:0> in memory controller. If MEMCR0<RDTMG1:0> is set to “00”, it
correspond with (a) in above table, and “01” is (b), “10” is (c).
SDCLK
t
CYC
A2~A23
A0~A1
+0
+1
+2
+3
CS2
RD
t
t
HA
t
t
t
t
AD2
AD3
AD2
AD2
HR
t
t
t
t
HA
RD3
HA
HA
Data
input
Data
input
Data
input
Data
input
D0~D15
92CZ26A-650
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TMP92CZ26A
4.3.3
SDRAM controller AC Characteristics
Variable
Parameter
Symbol
80 MHz 60 MHz Unit
Min
Max
Ref/Active to ref/active
T
12.5
87.5
25.0
87.5
12.5
25.0
12.5
25.0
37.5
87.5
12.5
25.0
12.5
−
16.6
116.2
33.2
116.2
16.6
33.2
16.6
33.2
49.8
116.2
16.6
33.2
16.6
3.3
−
<STRC[2:0]>=000
<STRC[2:0]>=110
<STRC[2:0]>=000
<STRC[2:0]>=110
<STRCD>=0
t
1
2
3
4
5
RC
command period
7T
Active to precharge
command period
2T
12210
t
RAS
7T
Active to read/write
command delay time
T
t
RCD
2T
T
<STRCD>=1
Precharge to active
command period
<STRP>=0
t
RP
2T
<STRP>=1
Active to active
3T
<STRC[2:0]>=000
<STRC[2:0]>=110
<STWR>=0
t
RRD
command period
7T
T
t
6
7
8
Write recovery time
CLK cycle time
WR
2T
<STWR>=1
t
T
CK
0.5T − 5
0.5T − 3
0.5T − 5
0.5T − 3
t
CLK high level width
CH
3.25
−
3.3
−
t
9
CLK low level width
CL
3.25
−
10-1a Access time from CLK(CL* =2)
<SRDS>=0(Read data shift OFF)
T − 16
T − 16
T − 6.5
T − 6.5
0.6
−
t
AC
AC
10-1b
10-2a Access time from CLK(CL* =2)
<SRDS>=1(Read data shift ON)
- 3.5
−
ns
10.1
−
t
t
10-2b
6
11 Output data hold time
0
0
0
OH
t
1Word/Single
Burst
0.5T − 4
0.5T − 4
2.25
2.25
2.5
−
3.3
3.3
6.6
2.3
−
DS
DS
12 Data-in set-up time
t
t
1Word/Single
T
−
10
DH
DH
DH
13 Data-in hold time
t
t
0.5T − 6
0.5T − 4
0.5T − 4
0.5T − 6
0.5T − 4
0.5T − 5
0.5T − 3
0.5T − 5
0.5T − 3
0.5T − 6
0.5T − 4
T
Burst
2.25
2.25
−
t
14 Address set-up time
15 Address hold time
4.3
2.3
−
AS
t
AH
2.25
−
3.3
−
t
16 CKE set-up time
CKS
3.25
−
3.3
−
t
t
17 Command set-up time
18 Command hold time
CMS
3.25
−
2.3
−
CMH
2.25
12.5
t
19 Mode register set cycle time
*CL: CAS latency
16.6
RSC
AC measuring condition
SDCLK pin CL = 30 pF, Other pins CL = 50 pF
92CZ26A-651
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TMP92CZ26A
(1) SDRAM read timing (1Word length read mode, <SPRE>=1)
t
CK
SDCLK
t
RCD
t
t
RP
RAS
t
t
CL
CH
SDxxDQM
t
t
t
CMS
CMS CMH
SDCS
SDRAS
SDCAS
SDWE
t
CMH
t
RRD
t
t
AH
AS
A0~A9
A10
Row
Row
Row
Column
t
t
AS
AH
A11~A15
D0~D15
t
t
AC
OH
Data input
92CZ26A-652
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TMP92CZ26A
(2) SDRAM write timing (Single write mode, <SPRE>=1)
t
CK
SDCLK
t
t
RP
t
RCD
WR
t
t
CL
CH
t
CMS
SDxxDQM
t
t
RRD
CMS
SDCS
SDRAS
SDCAS
SDWE
t
CMH
t
CMH
t
RAS
t
t
AH
AS
A0~A9
A10
Row
Column
t
t
AS
AH
Row
Row
A11~A15
D0~D15
t
t
DS
DH
Data output
92CZ26A-653
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TMP92CZ26A
(3) SDRAM burst read timing (Start burst cycle)
t
CK
SDCLK
t
CMS
SDxxDQM
t
t
MRD
RCD
SDCS
SDRAS
SDCAS
SDWE
t
t
CMH
CMS
t
t
CMS CMH
t
CMH
t
t
t
t
AS
t
AH
AH
AS
AS
027
Row
Column
A0~A9
Row
A10
A11~A15
0
Row
t
t
t
AC
AC
AC
Data
input
D0~D15
Data input
Data input
t
t
OH
OH
92CZ26A-654
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TMP92CZ26A
(4) SDRAM burst read timing (End burst timing)
t
CK
SDCLK
t
t
t
t
CMH
CMS
RP
SDxxDQM
t
t
t
CMH
CMS
CMS CMH
SDCS
SDRAS
SDCAS
SDWE
A0~A9
Column
t
AS
A10
A11~A15
D0~D15
Row
t
AC
Data input
Data input
t
t
OH
OH
92CZ26A-655
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TMP92CZ26A
(5) SDRAM initializes timing
t
CK
SDCLK
t
RC
SDxxDQM
t
CMS
SDCS
SDRAS
SDCAS
t
t
t
CMS
t
t
CMH
t
CMS CMH
CMH
CMS
t
CMH
SDWE
A0~A9
220
t
t
AH
AS
A10
A11~A15
0
92CZ26A-656
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TMP92CZ26A
(6) SDRAM refreshes timing
t
CK
SDCLK
t
RC
SDxxDQM
t
t
CMH
CMS
SDCS
SDRAS
SDCAS
SDWE
(7) SDRAM self refresh timing
t
CK
SDCLK
SDCKE
t
t
RC
CKS
t
CKS
SDxxDQM
SDCS
t
t
CMS CMH
SDRAS
SDCAS
SDWE
92CZ26A-657
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TMP92CZ26A
4.3.4
NAND Flash Controller AC Characteristics
Variable
80 MHz 60 MHz
No. Symbol
Parameter
Unit
(n=3) (n=3)
(m=3) (m=3)
Min
Max
t
1
2
Access cycle
(2 + n + m ) T
100
45
132
63
NC
t
NDRE
low level width
(1.5+ n) T − 12
RP
t
NDRE data access time
3
(1.5 + n) T − 15
41
60
REA
ns
t
t
4
5
6
7
Read data hold time
NDWE low level width
Write data setup time
Write data hold time
0
0
0
OH
(1.0 + n) T − 20
(1.0 + n) T − 20
(0.5 + m) T − 2
30
30
42
47
47
56
WP
t
DS
DH
t
AC measuring condition
Note1: The “n” in “Variable” means wait-number which is set to NDFMCR0<SPLW1:0>, and “m” means number which is
set to NDFMCR0<SPHW1:0>.
Example: If NDFMCR0<SPLW1:0> is set to “01”, n=1, tRP = (1.5 + n) T − 12 = 2.5T − 12
Note2: In above variable, the setting that result is minus can not use.
t
CYC
SPLW1:0="01"
SPHW1:0="01"
SDCLK
A0~A23
NDRE
t
RP
NDWE
Read
cycle
t
REA
t
OH
D0~D7
D0~D15
Data input
NDRE
NDWE
t
WP
Write
cycle
t
DS
t
DH
D0~D7
D0~D15
Data output
92CZ26A-658
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TMP92CZ26A
4.3.5
Serial channel timing
(1) SCLK input mode (I/O interface mode)
Variable
Parameter
Symbol
80 MHz 60 MHz Unit
Min
Max
t
SCLK cycle
16T
200
20
266
36.4
146
43
SCY
t
t
/2 − 4T − 30
Output data → SCLK rising/ falling
SCLK rising/ falling → Output data hold
SCLK rising/ falling → Input data hold
SCLK rising/ falling → Input data valid
Input data valid → SCLK rising/ falling
OSS
SCY
t
t
/2 + 2T -20
105
35
OHS
SCY
ns
t
2T + 10
HSR
t
t
− 20
180
20
246
20
SRD
SCY
t
20
RDS
(2) SCLK output mode (I/O interface mode)
Variable
Parameter
Symbol
80 MHz 60 MHz Unit
Min
Max
t
SCLK cycle (Programmable)
16T
8192T
200
60
266
93
93
0
SCY
t
t
t
/2 − 40
SCY
Output data → SCLK rising/ falling
SCLK rising/ falling → Output data hold
SCLK rising/ falling → Input data hold
SCLK rising/ falling → Input data valid
Input data valid → SCLK rising/ falling
OSS
t
/2 − 40
SCY
60
OHS
ns
t
0
0
HSR
t
t
− 1T − 50
137.5
62.5
199
66
SRD
SCY
t
1T + 50
RDS
t
SCY
SCLK
Output mode/
Input mode
SCLK
(Input mode)
t
t
OHS
OSS
Output data
TXD
0
0
1
1
2
3
t
RDS
t
SRD
t
HSR
Input data
RXD
2
3
Valid
Valid
Valid
Valid
92CZ26A-659
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TMP92CZ26A
4.3.6
Timer input pulse (TA0IN, TA2IN, TB0IN0, TB1IN0)
Variable
Parameter
Symbol
80 MHz 60 MHz Unit
Min
Max
t
Clock cycle
8T+100
4T + 40
4T + 40
200
90
234
107
107
VCK
ns
t
Low level pulse width
High level pulse width
VCKL
t
90
VCKH
4.3.7
Interrupt Operation
Parameter
Variable
Symbol
80 MHz 60 MHz Unit
Min
Max
t
INT0~INT7 low width
INT0~INT7 high width
2T + 40
65
65
74
74
INTAL
ns
t
2T + 40
INTAH
4.3.8 USB Timing (Full-speed)
= 3.3 ± 0.3 V/f
V
CC
= 48 MHz/Ta = 0 ~ 70°C
USB
Parameter
Symbol
Min
Max
Unit
t
D+, D− rising time
4
4
20
20
R
ns
V
t
D+, D− falling time
F
V
Output signal crossover voltage
1.3
2.0
CRS
AC measuring condition
Measuring
positoin
V
CC
TMP92CZ26A
R3 = 1.5 kΩ
R1 = 27 Ω
D+
R1 = 27 Ω
D−
R2 = 15 kΩ
CL = 50 pF
90%
90%
10%
D+, D−
V
CRS
10%
t
R
t
F
92CZ26A-660
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TMP92CZ26A
4.3.9
LCD Controller
Parameter
Variable
80 MHz 60 MHz
Symbol
Unit
(n=0)
(n=0)
Min
Max
LCP0 clock period
t
2T(n+1)
25
33.3
CW
LCP0 high width
t
T(n+1) − 5
T(n+1) − 5
7.5
7.5
5
11.6
11.6
9.1
CWH
(Include phase inversion)
LCP0 low width
t
CWL
(Include phase inversion)
Data valid → LCP0 falling
(Include phase inversion)
LCP0 falling → Data hold
(Include phase inversion)
Signal delay from LCP0 basic
changing point
ns
t
T(n+1) − 7.5
T(n+1) − 7.5
DSU
t
5
9.1
DHD
±20
±20
t
-20
20
GDL
(Include phase inversion)
t
CW
LCP0
t
t
t
CWH
CWL
t
DSU
DHD
LD0~LD23
LDINV
LD0~LD23 out
LDINV
t
GDL
LVSYNC
LHSYNC
FR
LLOAD
LGOE0
LGOE1
LGOE2
AC measuring condition
• CL = 50 pF (LCP0 only CL = 30 pF)
Note: The “n” in “Variable” show value that is set to LCDMODE0<SCPW1:0>.
Example: If LCDMODE0<SCPW1:0> = “01”, n=1, tRWP= 2T(n+1) = 2T
92CZ26A-661
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TMP92CZ26A
4.3.10 I2S Timing
Parameter
Variable
Max
Symbol
80 MHz 60 MHz Unit
Min
t
I2SCKO clock period
I2SCKO high width
t
100
35
35
35
42
100
35
35
35
42
CR
IC
t
0.5 t
− 15
HB
CR
CR
CR
ns
t
0.5 t
0.5 t
− 15
I2SCKO low width
LB
t
− 15
I2SDO, I2SWS setup time
I2SDO, I2SWS hold time
SD
t
0.5 t
CR
− 8
HD
t
CR
t
LB
t
HB
I2SCKO
I2SDO
I2SWS
t
t
t
SD
HD
HD
Note: The Maximum operation frequency of I2SCKO in I2S circuit is 10MHz. Don’t set I2SCKO to value more than 10MHz.
AC measuring condition
• I2SCKO, I2SDO and I2SWS pins CL
=
30 pF
92CZ26A-662
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TMP92CZ26A
4.3.11 SPI Controller
Parameter
Variable
Symbol
80MHz 60 MHz Unit
Min
Max
f
SPCLK frequency ( = 1/S)
SPCLK rising time
20
6
20
6
15
6
MHz
PP
t
r
t
f
SPCLK falling time
6
6
6
t
SPCLK low width
0.5S − 6
19
19
7
28
28
15
WL
t
SPCLK high width
0.5S − 6
WH
t
Output data valid → SPCLK rising
SPCLK rising/ falling
→ Output data hold
Input data valid
0.5S − 18
ODS
ns
t
0.5S − 10
15
5
23.4
5
ODH
t
5
5
IDS
→ SPCLK rising/ falling
SPCLK rising/ falling
→ Input data valid
t
5
5
IDH
AC measuring condition
• Clock of top column in above table shows system clock frequency, and “S” in “Variable” show
SPCLK clock cycle [ns].
• CL = 25 pF
f
PP
t
WL
t
f
0.7 V
SPCLK Output
CC
t
WH
(at SPIMD<TCPOL,RCPOL>= “11”)
0.2V
CC
SPCLK Output
(at SPIMD<TCPOL,RCPOL>= “00”)
t
r
t
ODS
t
ODH
SPDO Output
SPDI Input
t
t
IDH
IDS
92CZ26A-663
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TMP92CZ26A
4.4 AD Conversion Characteristics
Parameter
Symbol
Condition
Min
Typ.
Max
Unit
Analog reference voltage (+)
Analog reference voltage (−)
AD converter power supply
voltage
VREFH
VREFL
AVCC − 0.2
AVCC
DVSS
AVCC
DVSS
DVSS + 0.2
V
AVCC
DVCC3A/3B
DVCC3A/3B
DVSS
DVCC3A/3B
AD converter ground
AVSS
AVIN
DVSS
DVSS
VREFH
0.45
Analog input voltage
VREFL
Analog current for analog
reference voltage
IREFON
IREFOFF
<VREFON> = 1
0.38
1
mA
<VREFON> = 0
5
μA
Total error
E
T
(Quantize error of ±0.5 LSB is
included)
Conversion speed at 12uS
±2.0
±4.0
LSB
Note1: 1 LSB = (VREFH − VREFL)/1024[V]
Note2: Minimum frequency for operation
Minimum clock for AD converter operate is 3MHz. (Clock frequency that is seleted by Clock gear ≥ f
= 3MHz)
SYS
Note3: The power supply current from AVCC pin is included in the power supply current of VCC pin (ICC).
92CZ26A-664
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TMP92CZ26A
5. Table of Special function registers (SFRs)
The SFRs include the I/O ports and peripheral control registers allocated to the 8-Kbyte address
space from 000000H to 001FF0H.
(1) I/O Port
(13) Clock gear, PLL
(14) 8-bit timer
(2) Interrupt control
(3) Memory controller
(4) TSI(Touch screen I/F)
(5) SDRAM controller
(6) LCD controller
(7) PMC
(15) 16-bit timer
(16) SIO
(17) SBI
(18) AD converter
(19) Watchdog timer
(20)RTC(Real time clock)
(21)MLD(Melody/alarm generator)
(22)I2S
(8) USB controller
(9) SPI controller
(10) MMU
(11) NAND-Flash controller
(12) DMA controller
(23) MAC
Table layout
Symbol
Name
Address
7
6
1
0
Bit Symbol
Read/Write
Initial value after reset
Remarks
Note: “Prohibit RMW” in the table means that you cannot use RMW instructions on these register.
Example: When setting bit0 only of the register PxCR, the instruction “SET 0, (PxCR)” cannot be
used. The LD (transfer) instruction must be used to write all eight bits.
Read/Write
R/W:
R:
Both read and write are possible.
Only read is possible.
W:
Only write is possible.
W*:
Both read and write are possible (when this bit is read as1)
Prohibit RMW: Read modify write instructions are prohibited. (The EX, ADD, ADC, BUS,
SBC, INC, DEC, AND, OR, XOR, STCF, RES, SET, CHG, TSET, RLC,
RRC, RL, RR, SLA, SRA, SLL, SRL, RLD and RRD instruction are read
modify write instructions.)
R/W*:
Read modify write is prohibited when controlling the pull-up resistor.
92CZ26A-665
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TMP92CZ26A
Table 5.1 I/O Register Address Map
[1] Port (1/2)
Address
Name
Address
Name
Address
Name
Address
Name
0000H
1H
0010H P4
0020H P8
1H P8FC2
2H
0030H PC
1H
1H
2H
2H
2H PCCR
3H
3H P4FC
4H P5
5H
3H P8FC
4H P9
5H P9FC2
6H P9CR
7H P9FC
8H PA
9H
3H PCFC
4H P1
4H
5H
5H
6H P1CR
6H
6H
7H P1FC
8H
7H P5FC
8H P6
9H
7H
8H
9H
9H
AH
AH P6CR
BH P6FC
CH P7
DH
AH
AH
BH
BH PAFC
CH
BH
CH
CH PF
DH
DH
DH
EH
EH P7CR
FH P7FC
EH
EH PFCR
FH PFFC
FH
FH
Address
Name
Address
Name
Address
Name
Address
Name
0040H PG
0050H PK
0060H PP
0070H Reserved
1H
2H
1H
1H
1H Reserved
2H Reserved
3H Reserved
4H Reserved
5H Reserved
6H Reserved
7H Reserved
8H Reserved
9H Reserved
AH Reserved
BH Reserved
CH Reserved
DH Reserved
EH Reserved
FH Reserved
2H
2H PPCR
3H PPFC
4H PR
5H
3H PGFC
3H PKFC
4H PL
5H
4H
5H
6H
6H
6H PRCR
7H PRFC
8H PZ
9H
7H
7H PLFC
8H PM
9H
8H
9H
AH
AH
AH PZCR
BH
BH
BH PMFC
CH PN
DH
CH PJ
DH
CH
DH
EH PJCR
FH PJFC
EH PNCR
FH PNFC
EH
FH
92CZ26A-666
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TMP92CZ26A
[1] Port (2/2)
Address
0080H
Name
Address
Name
Address
Name
Address
Name
0090H PGDR
00A0H PT
1H
00B0H PX
1H
1H P1DR
1H
2H
2H
2H PTCR
3H PTFC
4H PU
2H PXCR
3H
3H PJDR
4H PKDR
5H PLDR
6H PMDR
7H PNDR
8H PPDR
9H PRDR
AH PZDR
BH PTDR
CH PUDR
DH PVDR
EH PWDR
FH PXDR
3H PXFC
4H
4H P4DR
5H P5DR
6H P6DR
7H P7DR
8H P8DR
9H P9DR
AH PADR
BH
5H
5H
6H PUCR
7H PUFC
8H PV
6H
7H
8H
9H PVFC2
AH PVCR
BH PVFC
CH PW
DH
9H
AH
BH
CH PCDR
DH
CH
DH
EH
EH PWCR
FH PWFC
EH
FH PFDR
FH
Note: Do not access no allocated name address.
92CZ26A-667
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TMP92CZ26A
[2] INTC
Address
Name
Address
Name
Address
Name
Address
Name
00D0H INTE12
00E0H INTESBIADM
1H INTESPI
00F0H INTE0
0100H DMA0V
1H INTE34
2H INTE56
3H INTE7
1H INTETC01
/INTEDMA01
2H INTETC23
/INTEDMA23
3H INTETC45
/INTEDMA45
4H INTETC67
5H SIMC
6H IIMC0
7H INTWDT
8H INTCLR
9H
1H DMA1V
2H DMA2V
3H DMA3V
2H Reserved
3H INTEUSB
4H INTETA01
5H INTETA23
6H INTETA45
7H INTETA67
8H INTETB0
9H INTETB1
AH
4H Reserved
5H INTEALM
6H Reserved
7H
4H DMA4V
5H DMA5V
6H DMA6V
7H DMA7V
8H DMAB
9H DMAR
AH DMASEL
BH
8H INTERTC
9H INTEKEY
AH INTELCD
BH INTEI2S01
CH INTENDFC
DH Reserved
EH INTEP0
FH INTEAD
AH IIMC1
BH
BH INTES0
CH
CH
CH
DH
DH
DH
EH
EH
EH
FH
FH Reserved
FH
[3] MEMC
[4] TSI
Address
Name
Address
Name
Address
Name
Address
Name
0140H B0CSL
0150H
1H
0160H
1H
01F0H TSICR0
1H B0CSH
2H MAMR0
3H MSAR0
4H B1CSL
5H B1CSH
6H MAMR1
7H MSAR1
8H B2CSL
9H B2CSH
AH MAMR2
BH MSAR2
CH B3CSL
DH B3CSH
EH MAMR3
FH MSAR3
1H TSICR1
2H
2H
2H Reserved
3H
3H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
4H
4H
5H
5H
6H
6H PMEMCR
7H
7H
8H BEXCSL
8H CSTMGCR
9H WRTMGCR
AH RDTMGCR0
BH RDTMGCR1
CH BROMCR
DH RAMCR
EH
9H BEXCSH
AH
BH
CH
DH
EH
FH
FH
Note: Do not access no allocated name address.
92CZ26A-668
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TMP92CZ26A
[5] SDRAMC
Address
Name
0250H SDACR
1H SDCISR
2H SDRCR
3H SDCMM
4H SDBLS
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
[6] LCDC
[7] PMC
Address
Name
Address
Name
Address
Name
Address
Name
0280H LCDMODE0
1H LCDMODE1
2H
0290H LCDHSDLY
1H LCDO0DLY
2H LCDO1DLY
3H LCDO2DLY
4H LCDHSW
5H LCDLDW
6H LCDHO0W
7H LCDHO1W
8H LCDHO2SW
9H LCDHWB8
AH
02A0H LSAML
02F0H PMCCTL
1H LSAMM
2H LSAMH
3H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
3H LCDDVM0
4H LCDSIZE
5H LCDCTL0
6H LCDCTL1
7H LCDCTL2
8H LCDDVM1
9H
4H LSASL
5H LSASM
6H LSASH
7H
8H LSAHX
9H LSAHX
AH LSAHY
BH LSAHY
CH LSASS
DH LSASS
EH LSACS
FH LSACS
AH LCDHSP
BH LCDHSP
CH LCDVSP
DH LCDVSP
EH LCDPRVSP
FH LCDHSDLY
BH
CH
DH
EH
FH
Note: Do not access no allocated name address.
92CZ26A-669
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TMP92CZ26A
[8] USBC (1/2)
Address
Name
Address
Name
Address
Name
Address
07A0H
Name
0500H Descriptor
to RAM
067FH (384 byte)
0780H ENDPOINT0
0790H EP0_STATUS
1H ENDPOINT1
1H EP1_STATUS
1H EP1_SIZE_L_B
2H ENDPOINT2
2H EP2_STATUS
2H EP2_SIZE_L_B
3H ENDPOINT3
3H EP3_STATUS
3H EP3_SIZE_L_B
4H
4H
4H
5H
5H
5H
6H
6H
6H
7H
7H
7H
8H
8H EP0_SIZE_L_A
8H
9H EP1_MODE
9H EP1_SIZE_L_A
9H EP1_SIZE_H_A
AH EP2_MODE
AH EP2_SIZE_L_A
AH EP2_SIZE_H_A
BH EP3_MODE
BH EP3_SIZE_L_A
BH EP3_SIZE_H_A
CH
DH
EH
FH
CH
DH
EH
FH
CH
DH
EH
FH
Address
Name
Address
Name
Address
Name
07B0H
1H EP1_SIZE_H_B
07C0H bmRequestType
1H bRequest
07D0H COMMAND
1H EPx_SINGLE1
2H EP2_SIZE_H_B
2H wValue_L
2H Reserved
3H EP3_SIZE_H_B
3H wValue_H
3H EPx_BCS1
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
4H wIndex_L
4H Reserved
5H wIndex_H
5H
6H wLength_L
7H wLength_H
8H SetupReceived
9H Current_Config
AH Standard Request
BH Request
6H INT_Control
7H
8H Standard Request Mode
9H Request Mode
AH
BH
CH DATASET1
DH DATASET2
EH USB STATE
FH EOP
CH
DH
EH ID_CONTROL
FH ID_STATE
Note: Do not access no allocated name address.
92CZ26A-670
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TMP92CZ26A
[8] USBC (2/2)
Address
Name
Address
Name
07E0H Port Status
07F0H USBINTFR1
1H FRAME_L
1H USBINTFR2
2H FRAME_H
2H USBINTFR3
3H ADDRESS
3H USBINTFR4
4H
4H USBINTMR1
5H
5H USBINTMR2
6H USBREADY
6H USBINTMR3
7H
7H USBINTMR4
8H Set Descriptor STALL
8H USBCR1
9H
AH
BH
CH
DH
EH
FH
9H
AH
BH
CH
DH
EH
FH
Note: Do not access no allocated name address.
92CZ26A-671
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TMP92CZ26A
[9] SPIC
Address
Name
Address
Name
0820H SPIMD
0830H SPITD0
1H SPIMD
2H SPICT
3H SPICT
4H SPIST
5H SPIST
6H SPICR
7H SPICR
8H
1H SPITD0
2H SPITD1
3H SPITD1
4H SPIRD0
5H SPIRD0
6H SPIRD1
7H SPIRD1
8H
9H
9H
AH
AH
BH
BH
CH SPIIE
DH SPIIE
EH
CH
DH
EH
FH
FH
[10] MMU
Address
Name
Address
Name
Address
Name
Address
Name
0880H LOCALPX
1H LOCALPX
2H LOCALPY
3H LOCALPY
4H LOCALPZ
5H LOCALPZ
6H
0890H LOCALRX
1H LOCALRX
2H LOCALRY
3H LOCALRY
4H LOCALRZ
5H LOCALRZ
6H
08A0H LOCALESX
1H LOCALESX
2H LOCALESY
3H LOCALESY
4H LOCALESZ
5H LOCALESZ
6H
08B0H LOCALOSX
1H LOCALOSX
2H LOCALOSY
3H LOCALOSY
4H LOCALOSZ
5H LOCALOSZ
6H
7H
7H
7H
7H
8H LOCALLX
9H LOCALLX
AH LOCALLY
BH LOCALLY
CH LOCALLZ
DH LOCALLZ
EH
8H LOCALWX
9H LOCALWX
AH LOCALWY
BH LOCALWY
CH LOCALWZ
DH LOCALWZ
EH
8H LOCALEDX
9H LOCALEDX
AH LOCALEDY
BH LOCALEDY
CH LOCALEDZ
DH LOCALEDZ
EH
8H LOCALODX
9H LOCALODX
AH LOCALODY
BH LOCALODY
CH LOCALODZ
DH LOCALODZ
EH
FH
FH
FH
FH
Note: Do not access no allocated name address.
92CZ26A-672
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TMP92CZ26A
[11] NAND-Flash controller
Address
Name
Address
Name
Address
Name
08C0H NDFMCR0
1H NDFMCR0
2H NDFMCR1
3H NDFMCR1
4H NDECCRD0
5H NDECCRD0
6H NDECCRD1
7H NDECCRD1
8H NDECCRD2
9H NDECCRD2
AH NDECCRD3
BH NDECCRD3
CH NDECCRD4
DH NDECCRD4
EH
08D0H NDRSCA0
1H NDRSCA0
2H NDRSCD0
3H
1FF0H NDFDTR0
1H NDFDTR0
2H NDFDTR1
3H NDFDTR1
4H NDRSCA1
5H NDRSCA1
6H NDRSCD1
7H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
8H NDRSCA2
9H NDRSCA2
AH NDRSCD2
BH
CH NDRSCA3
DH NDRSCA3
EH NDRSCD3
FH
FH
92CZ26A-673
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TMP92CZ26A
[12] DMAC
Address
Name
Address
Name
Address
Name
Address
Name
0900H HDMAS0
1H HDMAS0
2H HDMAS0
3H
0910H HDMAS1
1H HDMAS1
2H HDMAS1
3H
0920H HDMAS2
1H HDMAS2
2H HDMAS2
3H
0930H HDMAS3
1H HDMAS3
2H HDMAS3
3H
4H HDMAD0
5H HDMAD0
6H HDMAD0
7H
4H HDMAD1
5H HDMAD1
6H HDMAD1
7H
4H HDMAD2
5H HDMAD2
6H HDMAD2
7H
4H HDMAD3
5H HDMAD3
6H HDMAD3
7H
8H HDMACA0
9H HDMACA0
AH HDMACB0
BH HDMACB0
CH HDMAM0
DH
8H HDMACA1
9H HDMACA1
AH HDMACB1
BH HDMACB1
CH HDMAM1
DH
8H HDMACA2
9H HDMACA2
AH HDMACB2
BH HDMACB2
CH HDMAM2
DH
8H HDMACA3
9H HDMACA3
AH HDMACB3
BH HDMACB3
CH HDMAM3
DH
EH
EH
EH
EH
FH
FH
FH
FH
Address
Name
Address
Name
Address
Name
0940H HDMAS4
1H HDMAS4
2H HDMAS4
3H
0950H HDMAS5
1H HDMAS5
2H HDMAS5
3H
0970H
1H
2H
3H
4H HDMAD4
5H HDMAD4
6H HDMAD4
7H
4H HDMAD5
5H HDMAD5
6H HDMAD5
7H
4H
5H
6H
7H
8H HDMACA4
9H HDMACA4
AH HDMACB4
BH HDMACB4
CH HDMAM4
8H HDMACA5
9H HDMACA5
AH HDMACB5
BH HDMACB5
CH HDMAM5
8H
9H
AH
BH
CH Reserved
DH
EH
FH
DH
EH
FH
DH Reserved
EH HDMAE
FH HDMATR
92CZ26A-674
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TMP92CZ26A
[13] CGEAR, PLL
[14] 8-bit timer
Address
Name
Address
Name
Address
Name
10E0H SYSCR0
1100H TA01RUN
1110H TA45RUN
1H
1H SYSCR1
2H SYSCR2
3H EMCCR0
4H EMCCR1
5H EMCCR2
6H Reserved
7H
1H
2H TA0REG
3H TA1REG
4H TA01MOD
5H TA1FFCR
6H
2H TA4REG
3H TA5REG
4H TA45MOD
5H TA5FFCR
6H
7H
7H
8H PLLCR0
9H PLLCR1
AH
8H TA23RUN
9H
8H TA67RUN
9H
AH TA2REG
BH TA3REG
CH TA23MOD
DH TA3FFCR
EH
AH TA6REG
BH TA7REG
CH TA67MOD
DH TA7FFCR
EH
BH
CH
DH
EH
FH
FH
FH
[15] 16-bit timer
[16] SIO
[17] SBI
Address
Name
Address
Name
Address
Name
Address
Name
1180H TB0RUN
1H
1190H TB1RUN
1200H SC0BUF
1240H SBI0CR1
1H
1H SC0CR
1H SBI0DBR
2H TB0MOD
3H TB0FFCR
4H
2H TB1MOD
3H TB1FFCR
4H
2H SC0MOD0
2H I2C0AR
3H BR0CR
3H SBI0CR2/SBI0SR
4H BR0ADD
4H SBI0BR0
5H
5H
5H SC0MOD1
5H
6H
6H
6H
6H
7H
7H
7H SIRCR
7H SBI0CR0
8H TB0RG0L
9H TB0RG0H
AH TB0RG1L
BH TB0RG1H
CH TB0CP0L
DH TB0CP0H
EH TB0CP1L
FH TB0CP1H
8H TB1RG0L
9H TB1RG0H
AH TB1RG1L
BH TB1RG1H
CH TB1CP0L
DH TB1CP0H
EH TB1CP1L
FH TB1CP1H
8H
9H
AH
BH
CH
DH
EH
FH
8H
9H
AH
BH
CH
DH
EH
FH
Note: Do not access no allocated name address.
92CZ26A-675
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TMP92CZ26A
[18] 10-bit ADC
[19] WDT
Address
Name
Address
Name
Address
Name
12A0H ADREG0L
12B0H ADREGSPL
1H ADREGSPH
2H Reserved
3H Reserved
4H ADCM0REGL
5H ADCM0REGH
6H ADCM1REGL
7H ADCM1REGH
8H ADMOD0
9H ADMOD1
AH ADMOD2
BH ADMOD3
CH ADMOD4
DH ADMOD5
EH
1300H WDMOD
1H ADREG0H
2H ADREG1L
3H ADREG1H
4H ADREG2L
5H ADREG2H
6H ADREG3L
7H ADREG3H
8H ADREG4L
9H ADREG4H
AH ADREG5L
BH ADREG5H
CH Reserved
DH Reserved
EH Reserved
FH Reserved
1H WDCR
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH ADCCLK
FH
[20] RTC
[21] MLD
Address
Name
Address
Name
1320H SECR
1330H ALM
1H MINR
2H HOURR
3H DAYR
4H DATER
5H MONTHR
6H YEARR
7H PAGER
8H RESTR
9H
1H MELALMC
2H MELFL
3H MELFH
4H ALMINT
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
AH
BH
CH
DH
EH
FH
Note: Do not access no allocated name address.
92CZ26A-676
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TMP92CZ26A
[22] I2S
[23] MAC
Address
Name
Address
Name
Address
Name
Address
Name
1800H I2S0BUF
1810H I2S1BUF
1BE0H MACMA
1BF0H
1H
1H
2H
3H
4H
5H
6H
7H
1H
1H MACMA
2H MACMA
3H MACMA
4H MACMB
5H MACMB
6H MACMB
7H MACMB
8H MACORL
9H MACORL
AH MACORL
BH MACORL
CH MACORH
DH MACORH
EH MACORH
FH MACORH
2H
2H
3H
3H
4H
4H
5H
5H
6H
6H
7H
7H
8H I2S0CTL
9H I2S0CTL
AH I2S0C
BH I2S0C
CH
8H I2S1CTL
9H I2S1CTL
AH I2S1C
BH I2S1C
CH
8H
9H
AH
BH
CH MACCR
DH
DH
DH
EH
FH
EH
EH
FH
FH
Note: Do not access no allocated name address.
92CZ26A-677
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TMP92CZ26A
(1) I/O ports (1/11)
Symbol
Name
Address
7
6
5
4
3
2
1
0
P17
P16
P15
P14
P13
P12
P11
P10
P1
P4
P5
P6
PORT1
0004H
0010H
0014H
0018H
R/W
Data from external port (Output latch register is cleared to “0”)
P47
P46
P45
P44
P43
P42
P41
P40
PORT4
PORT5
PORT6
R/W
R/W
R/W
0
P57
0
P56
0
P55
0
P54
0
P53
0
P52
0
P51
0
P50
0
P67
0
P66
0
P65
0
P64
0
P63
0
P62
0
P61
0
P60
Data from external port (Output latch register is cleared to “0”)
P76
P75
P74
P73
R/W
P72
P71
P70
P7
PORT7
001CH
Data from external Data from external port Data from external port
port (Output latch
register is set to “1”)
(Output latch register is (Output latch register is
cleared to “0”) set to “1”)
1
P87
P86
P85
1
P84
P83
P82
P81
P80
P8
P9
PORT8
PORT9
0020H
0024H
R/W
1
1
1
1
0
1
1
P97
P96
P92
P91
R/W
P90
R
Data from external port
Data from external port
(Output latch register is set to “1”)
PA7
PA6
PA5
PC5
PA4
PA3
PA2
PA1
PA0
PC0
PF0
PA
PC
PORTA
PORTC
0028H
0030H
R
Data from external port
PC4 PC3
PC7
PC6
PC2
PC1
R/W
Data from external port (Output latch register is set to “1”)
PF5 PF4 PF3 PF2 PF1
PF7
R/W
R/W
Data from external port (Output latch register is set to “1”)
PF
PORTF
PORTG
003CH
0040H
1
PG5
PG4
PG3
PG2
PG1
PG0
PG
R
Data from external port
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
R/W
PJ
PORTJ
004CH
Data from external port
(Output latch register is
set to “1”)
1
1
1
1
1
1
PK7
PK6
PK5
PK4
PK3
PK2
PK1
PK0
PK
PL
PORTK
PORTL
PORTM
PORTN
0050H
0054H
0058H
005CH
R/W
R/W
0
PL7
0
PL6
0
PL5
0
PL4
0
PL3
0
PL2
0
PL1
0
PL0
0
0
0
0
0
0
PM2
0
PM1
0
PM7
R/W
1
PM
PN
R/W
1
PN2
1
PN1
PN7
PN6
PN5
PN4
PN3
PN0
R/W
Data from external port (Output latch register is cleared to “1”)
PP7
0
PP6
PP5
PP4
R/W
PP3
PP2
PP1
PP
PORTP
0060H
Data from external port
(Output latch register is cleared to “0”)
0
92CZ26A-678
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TMP92CZ26A
(1) I/O ports (2/11)
Symbol
Name
Address
7
6
5
4
3
2
1
0
PR3
PR2
PR1
PR0
R/W
Data from external port
(Output latch register is cleared to “0”)
PR
PORTR
0064H
PT7
PU7
PV7
PT6
PT5
PT4
PT3
PT2
PT1
PT0
PU0
PV0
PT
PU
PORTT
PORTU
00A0H
00A4H
R/W
Data from external port (Output latch register is cleared to “0”)
PU6 PU5 PU4 PU3 PU2 PU1
R/W
Data from external port (Output latch register is cleared to “0”)
PV6
PV4
PV3
PV2
R/W
PV1
R/W
PV
PORTV
00A8H
Data from external port
(Output latch register is
cleared to “0”)
Data from external port
(Output latch register is cleared to “0”)
PW7
PW6
PW5
PW4
PW3
PW2
PW1
PW0
PZ0
PW
PX
PZ
PORTW
PORTX
PORTZ
00ACH
00B0H
0068H
R/W
Data from external port (Output latch register is cleared to “0”)
PX5 PX4
PX7
R/W
R/W
Data from external port
(Output latch register is cleared to “0”)
PZ7 PZ6 PZ5 PZ4
PZ3
PZ2
PZ1
R/W
Data from external port (Output latch register is cleared to “0”)
92CZ26A-679
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TMP92CZ26A
(1) I/O ports (3/11)
Symbol Name
Address
7
6
5
4
3
2
1
0
P17C
P16C
P15C
P14C
P13C
P12C
P11C
P10C
PORT1
control
register
0006H
(Prohibit
RMW)
W
P1CR
0
0
0
0
0
0
0
0
0: Input
1:Output
P1F
W
PORT1
function
register
0007H
(Prohibit
RMW)
0/1
P1FC
0: Port
1: Data
bus
(D8~D15)
P47F
0/1
P46F
0/1
P45F
0/1
P44F
0/1
P43F
0/1
P42F
0/1
P41F
0/1
P40F
PORT4
function
register
0013H
(Prohibit
RMW)
W
P4FC
0/1
0: Port
1: Address bus (A0~A7)
P57F
0/1
P56F
0/1
P55F
P54F
P53F
0/1
P52F
P51F
0/1
P50F
0/1
PORT5
function
register
0017H
(Prohibit
RMW)
W
P5FC
P6CR
P6FC
0/1
0/1
0/1
0: Port
P65C
1: Address bus (A8~A15)
P67C
0
P66C
0
P64C
P63C
P62C
P61C
0
P60C
0
PORT6
control
register
001AH
(Prohibit
RMW)
W
0
0
0
0
0: Input
P64F
1: Output
P63F
P67F
0/1
P66F
0/1
P65F
P62F
P61F
0/1
P60F
0/1
PORT6
function
register
001BH
(Prohibit
RMW)
W
0/1
0: Port
P75C
W
0/1
0/1
0/1
1: Address bus (A16~A23)
P76C
W
P74C
W
P73C
W
P72C
W
P71C
W
0
0
0
0
0
0
0: Input
port,
0: Input
port
1: Output
0: Input
port
1: Output
port,
EA24
0: Input
port
1: Output
0: Input
port
1: Output
PORT7
001EH
0: Input
port,
WAIT
1:Output
port
P7CR
control
register
(Prohibit
RMW)
NDR/
B
1: Output
port,
EA25
port,
port,
port,
@
@
NDWE
NDRE
R/ W
<P72> = 0, <P71> = 0,
@
@
WRLL
WRLU
<P72> = 1
<P71> = 1
P76F
0
P75F
0
P74F
0
P73F
W
P72F
P71F
P70F
0
PORT7
function
register
001FH
(Prohibit
RMW)
0
0
0
P7FC
0: Port
1: WAIT
0: Port
0:Port
1: EA25
0:Port
1: EA24
0: Port
0: Port
1:
NDRE
0: Port
1: RD
1:NDR/
R/ W
,
1:
@
@
B
NDWE
<P72> = 0, <P71> = 0,
@
@
WRLL
WRLU
<P72> = 1
<P71> = 1
92CZ26A-680
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TMP92CZ26A
(1) I/O ports (4/11)
Symbol Name
Address
7
6
5
4
3
2
1
0
P87F
P86F
P85F
P84F
P83F
P82F
P81F
P80F
W
0
0
0
0
0
0
0
0
PORT8
function
register
0023H
(Prohibit
RMW)
0: Port
0: Port
0: Port
0: Port
1: CSZB
0: Port
1: CS3 ,
CSXA
0: Port,
CSZA
0: Port
1: CS1
0: Port
1: CS0
P8FC
1: <P87F2> 1: <P86F2> 1: CSZC
1: CS2
SDCS
,
P87F2
0
P86F2
0
P84F2
0
P82F2
P81F2
0
W
W
0
PORT8
function
fegister2
0021H
(Prohibit
RMW)
0: Output
port,
0:
0:
1:
0: Port,
CS3
0: <P81F>
1: SDCS
CSXB
CSZD
P8FC2
1:
ND1CE
ND0CE
CS2
1:
CSXA
1: CSZA ,
SDCS
P92C
0
0 Input
port,
P91C
W
P90C
0
0: Input
port,
1: Output
port,
TXD0
0
PORT9
control
register
0026H
(Prohibit
RMW)
0: Input
port,
RXD0
1: Output
port,
P9CR
CTS0
1: Output
port,
SCLK0
P96F
W
P92F
W
P90F
W
PORT9
function
register
0027H
(Prohibit
RMW)
0
0
0
P9FC
0: Input
port,
1:INT4
0:Port,
CTS0
1:SCLK0
0:Port
1:TXD0
–
W
0
–
W
0
P90FC2
W
0
PORT9
function
register2
0025H
(Prohibit
RMW)
P9FC2
Always
write “0”
Always
write “0”
0:CMOS
1:Open
-Drain
92CZ26A-681
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TMP92CZ26A
(1) I/O ports (5/11)
Symbol Name
Address
7
6
5
4
3
2
1
0
PA7F
PA6F
PA5F
PA4F
PA3F
PA2F
PA1F
PA0F
PORTA
function
register
002BH
(Prohibit
RMW)
W
W
PAFC
0
PC7C
0
0
PC6C
0
0
0
0
0
0
PC1C
0
0
PC0C
0
0: Key-in disable
1: Key-in enable
PC5C
PC4C
PC3C
PC2C
0
0
0
0
PORTC
control
register
0032H 0: Input
0: Input
port,
EA28
0: Input
0: Input
port,
EA26
0: Input
port,
INT3
0: Input
port,
INT2
1: Output
port,
0: Input
port,
INT1
1: Output
port,
TA0IN
0: Input
port,
INT0
1: Output
port,
port,
1: Output
port,
KO output
(Open
port,
PCCR
(Prohibit
RMW)
EA27
1: Output
port
1: Output
port
1: Output
port
1: Output
port,
TA2IN
-drain)
PC7F
PC6F
PC5F
PC4F
PC3F
PC2F
0
PC1F
PC0F
0
W
0
0: Port
1:KO
0
0: Port
1:EA28,
0
0:Port
0
0:Port
0
0
0: Port
1: INT1,
TA0IN
PORTC
function
register
0033H
(Prohibit
RMW)
0:Port
0: Port
1: INT2
0: Port
1:INT0
PCFC
1:EA27
1:EA26
1:INT3,
TA2IN
output
(Open
-Drain)
PF5C
0
PF4C
0
PF3C
PF2C
PF1C
0
PF0C
003EH
PORTF
control
register
W
PFCR
PFFC
(Prohibit
RMW)
0
0
0
PF0F
0
0: Input, 1: Output
PF7F
W
PF5F
PF4F
PF3F
PF2F
0
PF1F
W
003FH
PORTF
function
register
1
0
0
0
0
(Prohibit
RMW)
0: Output
port,
1: SDCLK
0:Port
0:Port
0:Port
0:Port
0:Port
0:Port
1:I2S1CKO
1:I2S1WS 1:I2S1DO 1:I2S1CKO 1:I2S0WS 1:I2S0DO
92CZ26A-682
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TMP92CZ26A
(1) I/O ports (6/11)
Symbol Name
Address
7
6
5
4
3
PG3F
W
2
1
0
0043H
PORTG
function
register
0
PGFC
(Prohibit
RMW)
0:Input
port,
AN3
1:
ADTRG
PJ6C
PJ5C
004EH
PORTJ
control
register
W
PJCR
PJFC
(Prohibit
RMW)
0
0
0:Input
PF6F
1: Output
PF5F
PF7F
0
PF4F
0
PF3F
0
PF2F
0
PF1F
0
PF0F
0
W
004FH
PORTJ
function
register
0
0
(Prohibit
RMW)
0: Port
0: Port
0: Port
0: Port
0: Port
0: Port
1:
0: Port
1:
0: Port
1:
1: SDCKE
PK7F
1:NDCLE
1: NDALE
1:
1:
,
,
,
SDWE
SRWR
SDCAS
SDRAS
SRLLB
SDLLDQM
SDLUDQM
SRLUB
PK1F
PK6F
PK5F
PK4F
PK3F
PK2F
PK0F
0053H
PORTK
function
register
W
PKFC
PLFC
(Prohibit
RMW)
0
0
0
0
0
0
0
0
0: Port
0: Port
0: Port
0: Port
0: Port
0: Port
0: Port
0: Port
1: LGOE2 1: LGOE1 1: LGOE0 1: LHSYNC 1: LVSYNC 1: LFR
1: LLOAD 1: LCP0
PL7F
0
PL6F
0
PL5F
PL4F
PL3F
PL2F
PL1F
0
PL0F
0
0057H
PORTL
function
register
W
(Prohibit
RMW)
0
0
0
0
0: Port
1: Data bus for LCDC (LD7~LD0)
PM7F
PM2F
W
PM1F
W
0
W
0
005BH
PORTM
function
register
0
PMFC
(Prohibit
RMW)
0: Port
1:PWE
0: Port
0: Port
1:
,
1:MLDALM
,TA1OUT
ALARM
MLDALM
92CZ26A-683
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TMP92CZ26A
(1) I/O ports (7/11)
Symbol Name
Address
7
6
5
4
3
2
1
0
PN7C
PN6C
PN5C
PN4C
PN3C
PN2C
PN1C
PN0C
005EH
PORTN
control
register
W
PNCR
PNFC
PPCR
(Prohibit
RMW)
0
0
0
0
0
0
0
0
0: Input 1: Output
PN7F
0
PN6F
0
PN5F
0
PN4F
PN3F
PN2F
0
PN1F
0
PN0F
0
005FH
PORTN
function
register
W
(Prohibit
RMW)
0
0
0:CMOS output 1:Open-Drain output
PP5C
PP4C
PP3C
PP2C
PP1C
0062H
PORTP
control
register
W
(Prohibit
RMW)
0
PP5F
0
0
0
0
PP2F
0
0
PP1F
0
0: Input 1: Output
PP3F
PP7F
0
PP6F
0
PP4F
W
0
0
0063H
PORTP
function
register
0: Port
0: Port
0: Port
0: Port
0: Port
1:
0: Port
0: Port
PPFC
(Prohibit
RMW)
1:
1:
1:
1:
1: TA5OUT 1: TA3OUT
TB1OUT0
TB0OUT0
TB1IN0@
TB0IN0@
TA7OUT@
<PP5C>=1 <PP4C>=1 <PP3C>=1
INT7@ INT6@ INT5@
<PP5C>=0 <PP4C>=0 <PP3C>=0
PR3C
PR2C
0
PR1C
0
PR0C
0
0066H
PORTR
control
register
W
PRCR
PRFC
(Prohibit
RMW)
0
0: Input, 1: Output
PR3F
PR2F
PR1F
PR0F
0
0067H
PORTR
function
register
W
(Prohibit
RMW)
0
0
0
0: Port
0: Port
0: Port
0: Port
1: SPCLK 1:
1: SPDO 1: SPDI
SPCS
PT7C
0
PT6C
0
PT5C
0
PT4C
PT3C
PT2C
PT1C
0
PT0C
0
PORTT
control
register
00A2H
(Prohibit
RMW)
W
PTCR
PTFC
0
0
0
PT2F
0
0: Input
PT4F
1: Output
PT3F
PT7F
0
PT6F
0
PT5F
0
PT1F
0
PT0F
0
PORTT
function
register
00A3H
(Prohibit
RMW)
W
0
0
0: Port 1: Data bus for LCDC (LD15~LD8)
92CZ26A-684
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TMP92CZ26A
(1) I/O ports (8/11)
Symbol Name
Address
7
6
5
4
3
2
1
0
PU7C
PU6C
PU5C
PU4C
PU3C
PU2C
PU1C
PU0C
PORTU
control
register
00A6H
(Prohibit
RMW)
W
PUCR
0
0
0
0
0
0
0
0
0: Input
PU4F
1: Output
PU3F
PU7F
PU6F
PU5F
PU2F
PU1F
PU0F
W
PORTU
function
register
00A7H
(Prohibit
RMW)
0
0
0
0
0
0
0
0
PUFC
0: Port
0: Port
0: Port
0: Port
1: LD20
0: Port
1: LD19
0: Port
0: Port
0: Port
1: LD23
PV7C
1: LD22
1: LD21@
<PU5C>=1
1: LD18
PV2C
1: LD17
1: LD16
PV0C
PV6C
PV1C
PORTV
00AAH
W
W
0
PVCR
PVFC
control
register
(Prohibit
RMW)
0
0
0
0
0: Input 1: Output
0: Input
1: Output
PV2F
0
PV1F
W
PV0F
PV7F
PV6F
W
PORTV
function
register
00ABH
(Prohibit
RMW)
0
0
0
0
0: Port
1: SCL
0: Port
1: SDA
0: Port
0: Port
0: Port
1:Reserved 1:Reserved 1: SCLK0@
<PV0C>=1
PW7C
PW6C
PW5C
0
PW4C
PW3C
PW2C
PW1C
PW0C
PORTW
00AEH
W
W
PWCR
PWFC
control
register
(Prohibit
RMW)
0
PW7F
0
0
PW6F
0
0
0
0
PW2F
0
0
PW1F
0
0
PW0F
0
0: Input
PW4F
1: Output
PW3F
PW5F
0
PORTW
function
register
00AFH
(Prohibit
RMW)
0
0
0: Port 1: Reserved
PX7C
PX5C
PORTX
00B2H
W
0
W
0
PXCR
control
register
(Prohibit
RMW)
0: Input
PX7F
1: Output
PX4F
PX5F
W
0
W
0
W
0
PORTX
function
register
00B3H
(Prohibit
RMW)
0:Port
0:Port
0:Port
PXFC
PZCR
1:Reserved
1: X1USB
input
1: CLKOUT
@<PX4>=0
LDIV
@<PX4>=1
PZ7C
0
PZ6C
0
PZ5C
0
PZ4C
PZ3C
PZ2C
0
PZ1C
0
PZ0C
0
PORTZ
006AH
W
control
register
(Prohibit
RMW)
0
0
0: Input
1: Output
92CZ26A-685
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TMP92CZ26A
(1) I/O ports (9/11)
Symbol
Name
Address
7
6
5
4
3
2
1
0
P17D
P16D
P15D
P14D
P13D
P12D
P11D
P10D
PORT1
drive
register
R/W
P1DR
P2DR
P3DR
P4DR
P5DR
0081H
0082H
0083H
0084H
0085H
1
P27D
1
1
P26D
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
P25D
P24D
R/W
P23D
P22D
P21D
1
P20D
1
PORT2
drive
register
1
1
1
1
Input/Output buffer drive register for standby mode
P37D
1
P36D
1
P35D
P34D
R/W
P33D
P32D
P31D
1
P30D
1
PORT3
drive
register
1
1
1
1
Input/Output buffer drive register for standby mode
P47D
1
P46D
1
P45D
P44D
R/W
P43D
P42D
P41D
1
P40D
1
PORT4
drive
register
1
1
1
1
Input/Output buffer drive register for standby mode
P57D
1
P56D
1
P55D
P54D
R/W
P53D
P52D
P51D
1
P50D
1
PORT5
drive
register
1
1
1
1
Input/Output buffer drive register for standby mode
P67D
1
P66D
1
P65D
P64D
R/W
1
P63D
P62D
P61D
1
P60D
1
PORT6
drive
register
P6DR
P7DR
P8DR
0086H
0087H
0088H
1
1
1
Input/Output buffer drive register for standby mode
P76D
1
P75D
P74D
P73D
R/W
1
P72D
P71D
1
P70D
1
PORT7
drive
register
1
1
1
Input/Output buffer drive register for standby mode
P87D
1
P86D
1
P85D
P84D
R/W
1
P83D
P82D
P81D
P80D
1
PORT8
drive
register
1
1
1
1
Input/Output buffer drive register for standby mode
P92D
P97D
P96D
P91D
R/W
1
P90D
R/W
PORT9
drive
1
1
1
1
P9DR
0089H
Input/Output buffer
drive register for
standby mode
register
Input/Output buffer drive register
for standby mode
PA7D
PA6D
PA5D
1
PA4D
R/W
PA3D
1
PA2D
PA1D
PA0D
PORTA
drive
register
PADR
PCDR
PFDR
008AH
008CH
008FH
1
PC7D
1
1
PC6D
1
1
1
1
PC1D
1
1
PC0D
1
Input/Output buffer drive register for standby mode
PC5D
PC4D
R/W
PC3D
PC2D
PORTC
drive
register
1
1
1
1
Input/Output buffer drive register for standby mode
PF7D
R/W
1
PF5D
PF4D
PF3D
R/W
PF2D
PF1D
1
PF0D
1
PORTF
drive
register
1
1
1
1
Input/Output buffer drive register for standby mode
92CZ26A-686
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TMP92CZ26A
(1) I/O ports (10/11)
Symbol
Name
Address
7
6
5
4
3
2
1
0
PG3D
PG2D
R/W
PORTG
drive
1
1
PGDR
0090H
register
Input/Output buffer
drive register for
standby mode
PJ7D
1
PJ6D
1
PJ5D
1
PJ4D
1
PJ3D
PJ2D
PJ1D
1
PJ0D
1
PORTJ
drive
register
R/W
PJDR
PKDR
PLDR
0093H
0094H
0095H
1
1
Input/Output buffer drive register for standby mode
PK7D
PK6D
PK5D
1
PK4D
R/W
PK3D
PK2D
PK1D
PK0D
PORTK
drive
register
1
PL7D
1
1
PL6D
1
1
1
1
1
PL1D
1
1
PL0D
1
Input/Output buffer drive register for standby mode
PL5D
PL4D
1
PL3D
PL2D
PORTL
drive
register
R/W
1
1
1
Input/Output buffer drive register for standby mode
PM2D
PM7D
R/W
1
PM1D
1
PORTM
drive
register
R/W
PMDR
PNDR
PPDR
0096H
0097H
0098H
1
Input/Output buffer drive register for standby mode
PN7D
PN6D
PN5D
PN4D
R/W
PN3D
PN2D
PN1D
PN0D
1
PORTN
drive
register
1
PP7D
1
1
PP6D
1
1
1
1
1
1
PP1D
1
Input/Output buffer drive register for standby mode
PP5D
PP4D
R/W
1
PP3D
PP2D
PORTP
drive
1
1
1
register
Input/Output buffer drive register for standby mode
PR3D
PR2D
PR1D
1
PR0D
1
R/W
PORTR
drive
PRDR
0099H
1
1
register
Input/Output buffer drive register for
standby mode
PT7D
PT6D
PT5D
1
PT4D
R/W
PT3D
PT2D
PT1D
PT0D
PORTT
drive
register
PTDR
PUDR
PVDR
009BH
009CH
009DH
1
PU7D
1
1
PU6D
1
1
1
1
1
PU1D
1
1
PU0D
1
Input/Output buffer drive register for standby mode
PU5D
PU4D
R/W
PU3D
PU2D
PORTU
drive
register
1
1
1
1
Input/Output buffer drive register for standby mode
PV7D
1
PV6D
1
PV4D
PV3D
PV2D
R/W
1
PV1D
1
PV0D
1
PORTV
drive
register
R/W
1
1
Input/Output buffer drive register for standby mode
92CZ26A-687
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TMP92CZ26A
(1) I/O ports (11/11)
Symbol
Name
Address
7
6
5
4
3
2
1
0
PW7D
PW6D
PW5D
PW4D
PW3D
PW2D
PW1D
PW0D
PORTW
drive
register
R/W
PWDR
PXDR
PZDR
009EH
009FH
009AH
1
1
1
1
1
1
1
1
Input/Output buffer drive register for standby mode
PX7D
R/W
1
PX5D
PX4D
PORTX
drive
register
1
1
Input/Output buffer drive register
for standby mode
PZ7D
PZ6D
PZ5D
PZ4D
R/W
PZ3D
1
PZ2D
1
PZ1D
1
PZ0D
1
PORTZ
drive
register
1
1
1
1
Input/Output buffer drive register for standby mode
92CZ26A-688
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TMP92CZ26A
(2) Interrupt control (1/4)
Symbol
Name
Address
7
6
5
4
3
2
I0M2
0
1
0
I0M0
0
−
INT0
−
−
−
−
−
−
I0C
R
I0M1
R/W
0
INTE0
INT0 enable 00F0H
Always write “0”
INT2
0
INT1
INT3
INT1 & INT2
00D0H
I2C
R
I2M2
I2M1
R/W
0
I2M0
0
I1C
R
I1M2
0
I1M1
R/W
0
I1M0
0
INTE12
INTE34
enable
0
0
0
INT4
INT3 & INT4
00D1H
I4C
R
I4M2
I4M1
R/W
0
I4M0
I3C
R
I3M2
I3M1
R/W
0
I3M0
enable
0
0
I6M2
0
0
I6M0
0
0
0
I5M2
0
0
I5M0
0
INT6
INT5
INT7
INT5 & INT6
00D2H
I6C
R
0
I6M1
R/W
0
I5C
R
0
I5M1
R/W
0
INTE56
INTE7
enable
−
INT7
−
−
−
−
−
−
I7C
R
0
I7M2
0
I7M1
R/W
0
I7M0
0
00D3H
enable
Always write “0”
INTTA1 (TMRA1)
INTTA0 (TMRA0)
INTTA0 &
INTTA1
enable
ITA1C
ITA1M2
ITA1M1
R/W
0
ITA1M0
0
ITA0C
ITA0M2
ITA0M1
R/W
0
ITA0M0
0
INTETA01
00D4H
R
0
R
0
0
0
INTTA3 (TMRA3)
INTTA2 (TMRA2)
INTTA2 &
INTTA3
enable
ITA3C
ITA3M2
ITA3M1
R/W
0
ITA3M0
ITA2C
ITA2M2
ITA2M1
R/W
0
ITA2M0
INTETA23
INTETA45
INTETA67
00D5H
00D6H
00D7H
R
0
R
0
0
0
ITA5M0
0
0
0
ITA4M0
0
INTTA5 (TMRA5)
INTTA4 (TMRA4)
INTTA4 &
INTTA5
enable
ITA5C
R
0
ITA5M2
ITA5M1
R/W
0
ITA4C
R
0
ITA4M2
ITA4M1
R/W
0
0
0
INTTA7 (TMRA7)
INTTA6 (TMRA6)
INTTA6 &
INTTA7
enable
ITA7C
R
0
ITA7M2
ITA7M1
R/W
0
ITA7M0
0
ITA6C
R
0
ITA6M2
ITA6M1
R/W
0
ITA6M0
0
0
0
INTTB01 (TMRB0)
INTTB00 (TMRB0)
INTTB00 &
INTTB01
enable
ITB01C
ITB01M2 ITB01M1 ITB01M0
R/W
ITB00C
ITB00M2 ITB00M1 ITB00M0
R/W
INTETB0
INTETB1
INTES0
00D8H
00D9H
00DBH
R
0
R
0
0
0
0
0
0
0
INTTB11 (TMRB1)
INTTB10 (TMRB1)
INTTB10 &
INTTB11
enable
ITB11C
ITB11M2 ITB11M1 ITB11M0
R/W
ITB10C
ITB10M2 ITB10M1 ITB10M0
R/W
R
0
R
0
0
0
0
ITX0M0
0
0
0
0
IRX0M0
0
INTTX0
INTRX0
INTRX0 &
INTTX0
enable
ITX0C
ITX0M2
ITX0M1
R/W
0
IRX0C
IRX0M2
IRX0M1
R/W
0
R
0
R
0
0
0
INTADM
IADM0C IADMM2 IADMM1 IADMM0
INTSBI
INTSBI &
INTADM
enable
ISBI0C
ISBIM2
ISBIM1
R/W
0
ISBIM0
0
INTESBI
ADM
00E0H
00E1H
R
0
R/W
0
R
0
0
0
0
INTSPITX
INTSPIRX
INTSPI
enable
ISPITC
ISPITM2 ISPITM1 ISPITM0
R/W
ISPIRC
ISPIRM2 ISPIRM1 ISPIRM0
R/W
INTESPI
R
0
R
0
0
0
0
0
0
0
92CZ26A-689
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TMP92CZ26A
0
(2) Interrupt control (2/4)
Symbol
Name
Address
7
6
5
4
3
2
1
−
INTUSB
INTUSB
enable
−
−
−
−
−
−
IUSBC
IUSBM2
IUSBM1
R/W
0
IUSBM0
0
INTEUSB
00E3H
R
0
Always write “0”
0
−
INTALM
INTALM
enable
−
−
−
−
−
−
IALMC
IALMM2
IALMM1
R/W
0
IALMM0
INTEALM
00E5H
R
0
Always write “0”
0
IRM2
0
0
−
INTRTC
INTRTC
enable
−
−
−
−
−
−
−
−
IRC
R
0
IRM1
R/W
0
IRM0
INTERTC
INTEKEY
INTELCD
INTEI2S01
00E8H
00E9H
00EAH
00EBH
00ECH
00EEH
00EFH
Always write “0”
0
−
INTKEY
IKM2
INTKEY
enable
−
−
−
−
−
IKC
R
0
IKM1
R/W
0
IKM0
Always write “0”
0
ILCDM2
0
0
−
INTLCD
INTLCD
enable
−
−
−
−
−
ILCD1C
ILCDM1
R/W
0
ILCDM0
R
0
Always write “0”
0
II2S0M0
0
INTI2S1
INTI2S0
II2S0M2
INTI2S0 &
INTI2S1
enable
II2S1C
R
0
II2S1M2
II2S1M1
R/W
0
II2S1M0
II2S0C
R
0
II2S0M1
R/W
0
0
0
0
IRDYM2
0
INTRSC
INTRDY
INTRSC &
INTENDFC INTRDY
enable
IRSCC
R
0
IRSCM2
IRSCM1
R/W
0
IRSCM0
IRDYC
R
0
IRDYM1 IRDYM0
R/W
0
0
0
0
IP0M0
0
−
INTP0
IP0M2
INTP0
INTEP0
−
−
−
−
−
−
IP0C
R
0
IP0M1
R/W
0
enable
Always write “0”
0
IADM2
0
INTADHP
INTAD
INTAD &
INTADHP
enable
IADHPC IADHPM2 IADHPM1 IADHPM0
IADC
R
0
IADM1
R/W
0
IADM0
0
INTEAD
R
0
R/W
0
0
0
92CZ26A-690
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TMP92CZ26A
(2) Interrupt control (3/4)
Symbol
Name
Address
7
6
5
4
3
2
1
0
INTTC1/INTDMA1
INTTC0/INTDMA0
ITC1C
ITC1M2 ITC1M1
ITC1M0
ITC0C
ITC0M2 ITC0M1
ITC0M0
INTTC0/INTDMA0 &
INTTC1/INTDMA1 00F1H
enable
INTETC01
/INTEDMA01
/IDMA1C /IDMA1M2 /IDMA1M1 /IDMA1M0 /IDMA0C /IDMA0M2 /IDMA0M1 /IDMA0M0
R
R
R/W
0
R/W
0
0
0
0
0
0
0
INTTC3/INTDMA3
ITC3M2 ITC3M1
INTTC2/INTDMA2
ITC2M2 ITC2M1
ITC3C
ITC3M0
ITC2C
ITC2M0
INTTC2/INTDMA2 &
INTTC3/INTDMA3 00F2H
enable
INTETC23
/INTEDMA23
/IDMA3C /IDMA3M2 /IDMA3M1 /IDMA3M0 /IDMA2C /IDMA2M2 /IDMA2M1 /IDMA2M0
R
R
R/W
0
R/W
0
0
0
0
0
0
0
INTTC5/INTDMA5
ITC5M2 ITC5M1
INTTC4/INTDMA4
ITC4M2 ITC4M1
ITC5C
ITC5M0
ITC4C
ITC4M0
INTTC4/INTDMA4 &
INTTC5/INTDMA5 00F3H
enable
INTETC45
/INTEDMA45
/IDMA5C /IDMA5M2 /IDMA5M1 /IDMA5M0 /IDMA4C /IDMA4M2 /IDMA4M1 /IDMA4M0
R
R
R/W
0
R/W
0
0
0
0
ITC7M0
0
0
0
0
ITC6M0
0
INTTC7 (DMA7)
INTTC6 (DMA6)
ITC7C
R
ITC7M2
ITC7M1
R/W
0
ITC6C
R
ITC6M2
ITC6M1
R/W
0
INTTC6 & INTTC7
00F4H
INTETC67
enable
0
0
0
0
−
W
−
W
IR0LE
W
0
0
1
SIO
interrupt mode
control
00F5H
(Prohibit
RMW)
Always
write “0” write “0”
Always
0: INTRX0
edge
mode
1: INTRX0
level
SIMC
mode
I5EDGE I4EDGE
I3EDGE
I2EDGE I1EDGE I0EDGE
I0LE
R/W
0
−
R/W
0
W
0
W
0
W
0
W
0
W
0
W
0
00F6H
(Prohibit INT5
RMW) edge
Interrupt
input mode control 0
IIMC0
INT4
edge
INT3
INT2
edge
INT1
INT0
edge
0: INT0
Always
edge
edge
edge mode
write “0”
0: Rising
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
1: Falling
0: Rising
0: Rising
1:INT0
level mode
1: Falling
1: Falling 1: Falling
−
INTWD
INTWD
enable
−
−
−
−
−
−
ITCWD
−
−
−
00F7H
00F8H
INTWDT
INTCLR
R
0
−
−
−
−
−
−
Always write “0”
CLRV5
0
CLRV4
0
CLRV3
CLRV2
CLRV1
CLRV0
CLRV7
0
CLRV6
W
Interrupt
clear control
(Prohibit
RMW)
0
0
0
0
0
Interrupt vector
I7EDGE I6EDGE
W
0
W
0
00FAH
Interrupt
input mode control 1
IIMC1
(Prohibit
RMW)
INT7
INT6
edge
edge
0: Rising
1: Falling
0: Rising
1: Falling
92CZ26A-691
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TMP92CZ26A
(2) Interrupt control (4/4)
Symbol
Name
Address
7
6
5
4
3
2
1
0
DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0
DMA0
start
vector
R/W
DMA0V
0100H
0
0
0
0
0
0
DMA0 start vector
DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0
R/W
DMA1
start
vector
DMA1V
DMA2V
0101H
0102H
0
0
0
0
0
0
DMA1 start vector
DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0
R/W
DMA2
start
vector
0
0
0
0
0
0
DMA2 start vector
DMA3V5 DMA3V4 DMA3V3 DMA3V2 DMA3V1 DMA3V0
R/W
DMA3
start
vector
DMA3V
DMA4V
0103H
0104H
0
0
0
0
0
0
DMA3 start vector
DMA4V5 DMA4V4 DMA4V3 DMA4V2 DMA4V1 DMA4V0
R/W
DMA4
start
vector
0
0
0
0
0
0
DMA4 start vector
DMA5V5 DMA5V4 DMA5V3 DMA5V2 DMA5V1 DMA5V0
R/W
DMA5
start
vector
DMA5V
DMA6V
DMA7V
DMAB
0105H
0106H
0107H
0108H
0
0
0
0
0
0
DMA5 start vector
DMA6V5 DMA6V4 DMA6V3 DMA6V2 DMA6V1 DMA6V0
R/W
DMA6
start
vector
0
0
0
0
0
0
DMA6 start vector
DMA7V5 DMA7V4 DMA7V3 DMA7V2 DMA7V1 DMA7V0
R/W
DMA7
start
vector
0
DBST5
0
0
DBST4
0
0
0
0
DBST1
0
0
DBST0
0
DMA7 start vector
DBST7
0
DBST6
0
DBST3
R/W
DBST2
DMA burst
0
0
1: DMA request on burst mode
DREQ7
0
DREQ6
0
DREQ5
0
DREQ5
0
DREQ4
R/W
DREQ3
DREQ2
0
DREQ1
0
0109H
(Prohibit
RMW)
DMA
request
DMAR
0
0
1: DMA request in software
DMASEL5 DMASEL4 DMASEL3 DMASEL2 DMASEL1 DMASEL0
R/W
Micro
0
0:Micro
DMA5
0
0: Micro
DMA4
0
0: Micro
DMA3
0
0: Micro
DMA2
0
0: Micro
DMA1
0
0: Micro
DMA0
DMASEL DMA/HDMA 010AH
Select
1:HDMA5 1:HDMA4 1:HDMA3 1:HDMA2 1:HDMA1 1:HDMA0
92CZ26A-692
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TMP92CZ26A
(3) Memory controller (1/4)
Symbol
Name
Address
7
6
5
4
3
2
1
0
B0WW3
B0WW2
B0WW1
B0WW0
B0WR3
B0WR2
B0WR1
B0WR0
R/W
0
0
1
0
0
0
1
0
Write waits
Read waits
BLOCK0
CS/WAIT
control
register
low
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
1101: 10 waits
1111: 16 waits
0010: 1 wait
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
0010: 1 wait
0140H
(Prohibit
RMW)
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
1110: 12 waits
0100: 20 waits
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
B0CSL
1101: 10 waits 1110: 12 waits
1111: 16 waits 0100: 20 waits
0011: 6 states +
pin input mode
0011: 6 states +
pin input mode
WAIT
WAIT
Others: Reserved
Others: Reserved
B0E
R/W
B0REC
B0OM1
B0OM0
R/W
B0BUS1
B0BUS0
0
BLOCK0
CS/WAIT
control
register
high
0
0
Dummy
cycle
0:No insert 10: Reserved
1: Insert
0
0
0
0141H
(Prohibit
RMW)
CS select
0: Disable
1: Enable
00: ROM/SRAM
01: Reserved
Data bus width
00: 8 bits
01: 16 bits
10: Reserved
11: Don’t set
B0CSH
B1CSL
B1CSH
11: Reserved
B1WW3
0
B1WW2
B1WW1
1
B1WW0
B1WR3
B1WR2
0
B1WR1
B1WR0
R/W
0
0
0
1
0
Write waits
Read waits
BLOCK1
CS/WAIT
control
register
low
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
0010: 1 waits
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
0010: 1 waits
0144H
(Prohibit
RMW)
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
1101: 10 waits 1110: 12 waits
1111: 16 waits 0100: 20 waits
1101: 10 waits 1110: 12 waits
1111: 16 waits 0100: 20 waits
0011: 6 states +
Others: Reserved
pin input mode
0011: 6 states +
Others: Reserved
B1OM1
pin input mode
WAIT
WAIT
B1E
R/W
B1REC
B1OM0
R/W
B1BUS1
B1BUS0
0
BLOCK1
CS/WAIT
control
register
high
0
0
Dummy
cycle
0:No
insert
0
0
0
0145H
(Prohibit
RMW)
CS select
0: Disable
1: Enable
00: ROM/SRAM
01: Reserved
10: Reserved
11: SDRAM
Data bus width
00: 8 bits
01: 16 bits
10: Reserved
11: Don’t set
1: Insert
B2WW3
0
B2WW2
B2WW1
1
B2WW0
B2WR3
B2WR2
0
B2WR1
B2WR0
R/W
0
0
0
1
0
Write waits
Read waits
BLOCK2
CS/WAIT
control
register
low
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
1101: 10 waits
1111: 16 waits
0010: 1 waits
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
1110: 12 waits
0100: 20 waits
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
1101: 10 waits
1111: 16 waits
0011: 6 states +
0010: 1 waits
0148H
(Prohibit
RMW)
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
1110: 12 waits
0100: 20 waits
B2CSL
0011: 6 states +
pin input mode
pin input mode
WAIT
WAIT
Others: Reserved
Others: Reserved
B2OM1
B2E
R/W
1
B2M
B2REC
0
B2OM0
R/W
B2BUS1
0
B2BUS0
1
BLOCK2
CS/WAIT
control
register
high
0
0
0
0149H
(Prohibit
RMW)
CS select 0:16 MB
0: Disable 1:Sets
Dummy
cycle
0:No
insert
1: Insert
00: ROM/SRAM
01: Reserved
10: Reserved
11: SDRAM
Data bus width
00: 8 bits
01: 16 bits
10: Reserved
11: Don’t set
B2CSH
1: Enable
area
92CZ26A-693
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TMP92CZ26A
0
(3) Memory controller (2/4)
Symbol
Name
Address
7
6
5
4
3
2
1
B3WW3
B3WW2
B3WW1
B3WW0
B3WR3
B3WR2
B3WR1
B3WR0
R/W
0
0
1
0
0
0
1
0
Write waits
Read waits
BLOCK3
CS/WAIT
control
register
low
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
0010: 1 waits
0001: 0 waits 0010: 1 waits
0101: 2 waits 0110: 3 waits
0111: 4 waits 1000: 5 waits
1001: 6 waits 1010: 7 waits
1011: 8 waits 1100: 9 waits
1101: 10 waits 1110: 12 waits
1111: 16 waits 0100: 20 waits
014CH
(Prohibit
RMW)
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
B3CSL
1101: 10 waits 1110: 12 waits
1111: 16 waits 0100: 20 waits
0011: 6 states +
pin input mode
0011: 6 states +
WAIT
Others: Reserved
pin input mode
WAIT
Others: Reserved
B3E
R/W
B3REC
B3OM1
B3OM0
B3BUS1 B3BUS0
R/W
0
BLOCK3
CS/WAIT
control
register
high
0
0
Dummy
cycle
0:No
insert
0
0
0
014DH
(Prohibit
RMW)
CS select
0: Disable
1: Enable
00: ROM/SRAM
01: Reserved
10: Reserved
11: Reserved
Data bus width
00: 8 bits
01: 16 bits
10: Reserved
11: Don’t set
B3CSH
BEXCSL
BEXCSH
1: Insert
BEXWW3 BEXWW2 BEXWW1 BEXWW0 BEXWR3 BEXWR2 BEXWR1 BEXWR0
R/W
0
0
1
0
0
0
1
0
Write waits
Read waits
BLOCK EX
CS/WAIT
control
register
low
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
0010: 1 waits
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
0001: 0 waits
0101: 2 waits
0111: 4 waits
1001: 6 waits
1011: 8 waits
0010: 1 waits
0110: 3 waits
1000: 5 waits
1010: 7 waits
1100: 9 waits
0158H
(Prohibit
RMW)
1101: 10 waits 1110: 12 waits
1111: 16 waits 0100: 20 waits
1101: 10 waits 1110: 12 waits
1111: 16 waits 0100: 20 waits
0011: 6 states +
pin input mode
0011: 6 states +
pin input mode
WAIT
WAIT
Others: Reserved
Others: Reserved
BEXREC BEXOM1 BEXOM0 BEXBUS1 BEXBUS0
R/W
BLOCK EX
CS/WAIT
control
register
high
0
Dummy
cycle
0:No
insert
0
0
0
0
0159H
(Prohibit
RMW)
00: ROM/SRAM
01: Reserved
10: Reserved
11: Reserved
Data bus width
00: 8 bits
01: 16 bits
10: Reserved
11: Don’t set
1: Insert
92CZ26A-694
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TMP92CZ26A
(3) Memory controller (3/4)
Symbol
Name
Address
7
6
5
4
3
2
1
0
M0V20
M0V19
M0V18
M0V17
M0V16
M0V15
M0V14-9
M0V8
Memory
address
mask
R/W
MAMR0
0142H
1
1
1
1
1
1
1
1
register 0
0: Compare enable
1: Compare disable
M0S23
M0S22
M0S21
M0S20
M0S19
M0S18
M0S17
M0S16
Memory
start
R/W
MSAR0
MAMR1
MSAR1
MAMR2
MSAR2
MAMR3
MSAR3
0143H
0146H
0147H
014AH
014BH
014EH
014FH
address
register 0
1
1
1
M1V19
1
1
1
1
M1V16
1
1
1
Set start address A23 to A16
M1V21
M1V20
M1V18
M1V17
MV15-9
M1V8
Memory
address
mask
R/W
1
1
1
1
1
1
register 1
0: Compare enable
1: Compare disable
M1S23
M1S22
M1S21
M1S20
M1S19
M1S18
M1S17
M1S16
Memory
start
address
register 1
R/W
1
1
1
M2V20
1
1
1
1
M2V17
1
1
1
Set start address A23 to A16
M2V22
M2V21
M2V19
M2V18
M2V16
M2V15
Memory
address
mask
R/W
1
M2S23
1
1
M2S22
1
1
1
1
M2S17
1
1
M2S16
1
register 2
0: Compare enable
1: Compare disable
M2S21
M2S20
M2S19
M2S18
Memory
start
address
register 2
R/W
1
M3V20
1
1
1
1
M3V17
1
Set start address A23 to A16
M3V22
1
M3V21
1
M3V19
M3V18
M3V16
1
M3V15
1
Memory
address
mask
R/W
1
1
register 3
0: Compare enable
1: Compare disable
M3S23
1
M3S22
1
M3S21
M3S20
M3S19
M3S18
M3S17
1
M3S16
1
Memory
start
address
register 3
R/W
1
1
1
1
Set start address A23 to A16
92CZ26A-695
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TMP92CZ26A
(3) Memory controller (4/4)
Symbol
Name Address
7
6
5
4
OPGE
R/W
0
3
2
1
PR1
0
PR0
OPWR1
OPWR0
Page
0
0
1
0
ROM
0166H
control
register
ROM
page
access
Wait number on page Byte number in a page
00: 1 CLK (n-1-1-1 mode) 00: 64 bytes
01: 2 CLK (n-2-2-2 mode) 01: 32 bytes
PMEMCR
0: Disable 10: 3 CLK (n-3-3-3 mode) 10: 16 bytes
1: Enable 11: Reserved
11: 8 bytes
TACSEL1 TACSEL0
R/W
TAC1
TAC0
0
R/W
Adjust for
Timing of
control
signal
0
0
0
Select area to
change timing
00:CS0
Select delay time(TAC)
00:0 × fSYS
01:1 × fSYS
CSTMGC
0168H
01:CS1
11:CS3
10:CS2
10:2 × fSYS
11:Reserved
TCWSEL1 TCWSEL0 TCWS1
TCWS0
R/W
TCWH1
TCWH0
0
Adjust for
0
0
0
0
0
Timing of
control
signal
Select area to
change timing
00:CS0
Select delay time(TCWS) Select delay time(TCWH)
WRTMGCRR
RDTMGCR0
RDTMGCR1
0169H
00:0.5 × fSYS
00:0.5 × fSYS
01:1.5 × fSYS
10:2.5 × fSYS
11:3.5 × fSYS
01:CS1 01:1.5 × fSYS
11:CS3 10:2.5 × fSYS
11:3.5 × fSYS
10:CS2
B1TCRS1
0
B1TCRS0
0
B1TCRH1
B1TCRH0
B0TCRS1
B0TCRS0
0
B0TCRH1
B0TCRH0
0
R/W
Adjust for
Timing of
control
signal
0
0
0
0
Select delay time(TCRS) Select delay time(TCRH) Select delay time(TCRS) Select delay time(TCRH)
016AH
00:0.5 × fSYS
01:1.5 × fSYS
10:2.5 × fSYS
11:3.5 × fSYS
00:0 × fSYS
01:1 × fSYS
10:2 × fSYS
11:3 × fSYS
00:0.5 × fSYS
01:1.5 × fSYS
10:2.5 × fSYS
11:3.5 × fSYS
00:0 × fSYS
01:1 × fSYS
10:2 × fSYS
11:3 × fSYS
B3TCRS1
B3TCRS0
0
B3TCRH1
B3TCRH0
0
B2TCRS1
B2TCRS0
0
B2TCRH1
B2TCRH0
0
R/W
Adjust for
Timing of
control
signal
0
0
0
0
Select delay time(TCRS) Select delay time(TCRH) Select delay time(TCRS) Select delay time(TCRH)
016BH
00:0.5 × fSYS
01:1.5 × fSYS
10:2.5 × fSYS
11:3.5 × fSYS
00:0 x× fSYS
01:1 × fSYS
10:2 × fSYS
11:3 × fSYS
00:0.5 × fSYS
01:1.5 × fSYS
10:2.5 × fSYS
11:3.5 × fSYS
00:0 × fSYS
01:1 × fSYS
10:2 × fSYS
11:3 × fSYS
CSDIS ROMLESS
R/W
VACE
1/0
1
0/1
Boot Rom
Control
register
Nand-Flash Boot
Vector
address
0: Disable
BROMCR
016CH
016DH
Area CS
Output
ROM
0: Use
0:enable 1: No use 1: Enable
1:disable
−
R/W
1
RAM
Control
register
RAMCR
Always
write “1”
92CZ26A-696
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TMP92CZ26A
(4) TSI
Symbol
Name
Address
01F0H
7
TSI7
R/W
0
6
INGE
R/W
0
5
PTST
R
4
TWIEN
R/W
0
3
PYEN
R/W
0
2
PXEN
R/W
0
1
0
MXEN
R/W
0
MYEN
R/W
0
0
TSI
control
register0
0: Disable Input gate Detection INT4
SPY
SPX
SMY
SMX
TSICR0
control of
Port
96,97
interrupt
control
1: Enable
condition
0 : OFF
1 : ON
0 : OFF
1 : ON
0 : OFF
1 : ON
0 : OFF
1 : ON
0: no
touch
0: Disable
1: Enable
0: Enable
1: Disable
1: touch
DBC7
DB1024
DB256
DB64
DB8
DB4
DB2
DB1
R/W
TSI
control
register1
0
0
0
0
0
8
0
4
0
2
0
1
TSICR1
01F1H
0: Disable
1: Enable
1024
256
64
De-bounce time is set by “(N*64-16) / f
”-formula.
SYS
“N” is sum of number which is set to “1” in bit6 to bit 0.
92CZ26A-697
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TMP92CZ26A
(5) SDRAM controller
Symbol
Name
Address
7
SRDS
6
−
5
4
3
SPRE
2
1
0
SMAC
R/W
SMUXW1 SMUXW0
R/W
1
0
0
0
0
0
Read
data shift write “0”
function
Always
Address multiplex
type
Read/Write
commands
SDRAM
controller
SDRAM
access
control
register
SDACR
0250H
00: Type A (A9- )
01: Type B (A10- )
10: Type C (A11- )
11: Reserved
0: Disable
1: Enable
0: Without
auto pre-
charge
0: Disable
1: Enable
1: With auto
precharge
STMRD
STWR
1
STRP
STRCD
R/W
STRC2
STRC1
0
STRC0
0
SDRAM
Command
Interval
1
1
1
1
TMRD
TWR
TRP
TRCD
TRC
SDCISR
0251H
Setting
000: 1 CLK 100: 5 CLK
001: 2 CLK 101: 6 CLK
010: 3 CLK 110: 7 CLK
011: 4 CLK 111: 8 CLK
Register
0: 1 CLK
1: 2 CLK
0: 1 CLK 0: 1 CLK
1: 2 CLK 1: 2 CLK
0: 1 CLK
1: 2 CLK
−
R/W
0
SSAE
SRS2
0
SRS1
R/W
0
SRS0
SRC
1
0
0
Always
write “0”
Self
Refresh interval
Auto
SDRAM
refresh
control
register
Refresh
auto
000: 47 states 100: 468 states
001: 78 states 101: 624 states
010: 156 states 110: 936 states
Refresh
SDRCR
0252H
exit
function
0:Disable
011: 312 states 111: 1248 states 1:Enable
0:Disable
1:Enable
SCMM2
0
SCMM1
R/W
0
SCMM0
0
Command issue
000: Don’t care
001: Initialization sequence
a. Precharge All command
b. Eight Auto Refresh commands
c. Mode Register Set command
010: Precharge All command
100: Reserved
SDRAM
command
register
SDCMM
0253H
101: Self Refresh Entry command
110: Self Refresh Exit command
Others: Reserved
SDBL5
0
SDBL4
0
SDBL3
0
SDBL2
SDBL1
SDBL0
0
0
0
SDRAM
HDRAM
burst length
register
For
HDMA5
HDMA burst length
For
HDMA4
For
HDMA3
For
HDMA2
For
HDMA1
For
HDMA0
SDBLS
0254H
0:1 Word Read / Single Write
1:Full Page Read / Burst Write
92CZ26A-698
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TMP92CZ26A
(6) LCD controller (1/6)
Symbol
Name
Address
7
6
5
4
3
2
1
0
RAMTYPE1 RAMTYPE0
SCPW1
SCPW0
MODE3
MODE2
MODE1
MODE0
R/W
0
0
1
1
0
0
0
0
LD bus transfer speed
Display RAM
Mode setting
SCPW2= 0
00: 2-clock
01: 4-clock
10: 8-clock
11: 16-clock
SCPW2= 1
00: 6-clock
01: 12-clock
10: 24-clock
11: 48-clock
0000 : Reserved
1000 : Reserved
1001 : Reserved
00: Internal RAM
01: External SRAM
10: SDRAM
0001 : SR (mono)
0010 : SR (4Gray)
0011 : Reserved
LCD
mode0
register
LCD
MODE0
0280H
1010 : TFT (256 color)
1011 : TFT (4096 color)
1100 : TFT (64k color)
11: Reserved
0100 : SR (16Gray)
0101 : SR (64Gray)
0110 : STN (256 color)
1101 : TFT256k,16M
(color)
1110 : Reserved
0111 : STN
(4096 color)
1111 : Reserved
LDC2
0
LDC1
0
LDC0
LDINV
0
AUTOINV INTMODE
FREDGE
SCPW2
R/W
W
0
W
0
0
0
0
Data rotation function
LD bus
Auto bus Interrupt
selection
FR edge
LD bus
LCD
mode1
register
transfer
speed
(Supported for 64K-color: 16bps only) Inversion inversion
0: LHSYNC
front edge
LCD
MODE1
0281H
0: Disable
1: enable
000: Normal
100: 90-degree
0:LLOAD
1:LHSYNC
back edge
0: Normal
001: Horizontal flip 101: Reserved
0: normal
1: 1/3
1:LVSYNC
1: Inversion (Valid only
for TFT)
010: Vertical flip
110: Reserved
111: Reserved
011: Horizontal & vertical flip
FMP3
FMP2
FMP1
0
FMP0
FML3
0
FML2
0
FML1
0
FML0
0
LCD
divide
frame0
register
R/W
R/W
LCDDVM0
LCDDVM1
0283H
0288H
0
FMP7
0
0
0
FMP4
0
LCP0 DVM (bits 3-0)
LHSYNC DVM (bits 3-0)
FMP6
FMP5
FML7
0
FML6
FML5
FML4
0
LCD
divide
frame1
register
0
0
0
0
LCP0 DVM (bits 7-4)
LHSYNC DVM (bit 7-4)
COM3
0
COM2
COM1
COM0
0
SEG3
0
SEG2
SEG1
SEG0
0
R/W
R/W
0
0
0
0
Common setting
0000 : reserved
0001 : 64
Segment setting
0000 : Reserved
0001 : 64
1000 : 320
1001 : 480
1000 : Reserved
1001 : Reserved
1010 : Reserved
1011 : Reserved
1100 : Reserved
1101 : Reserved
1110 : Reserved
1111 : Reserved
LCD size
register
LCDSIZE
0284H
0010 : 96
1010 : Reserved
1011 : Reserved
1100 : Reserved
1101 : Reserved
1110 : Reserved
1111 : Reserved
0010 : 128
0011 : 120
0100 : 128
0101 : 160
0110 : 200
0111 : 240
0011 : 160
0100 : 240
0101 : 320
0110 : 480
0111 : 640
PIPE
ALL0
FRMON
R/W
–
DLS
LCP0OC
R/W
START
0
0
0
0
0
0
0
PIP
Segment
Data
Always
write “0”
FR signal
LCP0
LCDC
FR divide
setting
function
LCP0/Line 0: Always operation
0:Disable
1:Enable
output
0:Normal
selection
LCD
control0
register
1: At valid
1: Always
output “0”
0:Line
0: Stop
1: Start
0: Disable
1: Enable
LCDCTL0
0285H
data only
LLOAD
width
1:LCP0
0: At setting
in register
1: At valid
data only
92CZ26A-699
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TMP92CZ26A
(6) LCD controller (2/6)
Symbol
Name
Address
7
LCP0P
R/W
1
6
LHSP
R/W
0
5
LVSP
R/W
1
4
LLDP
R/W
0
3
2
1
LVSW1
R/W
0
LVSW0
R/W
0
0
LCP0
LHSYNC LVSYNC LLOAD
LVSYNC
LCD
phase
phase
phase
phase
enable time control
00: 1 clock of LHSYNC
01: 2 clocks of LHSYNC
10: 3 clocks of LHSYNC
11: Reserved
LCDCTL1
control1
register
0286H
0:Rising
1:Falling
0:Rising
0:Rising
0:Rising
1: Falling 1: Falling 1: Falling
LGOE2P LGOE1P LGOE0P
R/W
0
0
0
LCD
control2
register
LGOE2
phase
LGOE1
phase
LGOE0
phase
LCDCTL2
0287H
0: Rising 0: Rising
0: Rising
1: Falling 1: Falling 1: Falling
LH7
0
LH6
0
LH5
0
LH4
0
LH3
0
LH2
0
LH1
0
LH0
0
LHSYNC
Pulse
W
LCDHSP
LCDHSP
LCDVSP
028AH
028BH
028CH
register
LHSYNC period (bits 7-0)
LH15
0
LH14
0
LH13
0
LH12
LH11
LH10
0
LH9
0
LH8
0
LHSYNC
Pulse
register
W
0
0
LHSYNC period (bits 15-8)
LVP7
0
LVP6
0
LVP5
0
LVP4
LVP3
LVP2
0
LVP1
0
LVP0
0
LVSYNC
Pulse
register
W
0
0
LVSYNC period (bits 7-0)
LVP9
LVP8
W
LVSYNC
Pulse
LCDVSP
028DH
0
0
register
LVSYNC period
(bits 9-8)
PLV6
0
PLV5
0
PLV4
0
PLV3
W
PLV2
0
PLV1
PLV0
LVSYNC
LCDPRVSP Pre Pulse
register
028EH
028FH
0
0
0
Front dummy LVSYNC (bits 6-0)
HSD6
0
HSD5
0
HSD4
HSD3
HSD2
HSD1
0
HSD0
0
LHSYNC
Delay
register
W
0
LCDHSDLY
0
0
LHSYNC delay (bits 6-0)
PDT
R/W
0
LDD6
0
LDD5
0
LDD4
LDD3
W
LDD2
LDD1
0
LDD0
0
0
0
0
Data output
timing
LLOAD
Delay
LCDLDDLY
0290H
register
0: Sync with
LLOAD
LLOAD delay (bits 6-0)
1: 1 clock
later than
LLOAD
92CZ26A-700
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TMP92CZ26A
(6) LCD controller (3/6)
Symbol
Name
Address
7
6
5
4
3
OE0D3
W
2
1
0
OE0D6
OE0D5
OE0D4
OE0D2
OE0D1
OE0D0
LGOE0
Delay
register
LCDO0DLY
0291H
0
0
0
0
OE1D5
0
0
0
0
OE0 delay (bits 6-0)
OE1D6
OE1D4
OE1D3
W
OE1D2
OE1D1
0
OE1D0
0
LGOE1
Delay
register
LCDO1DLY
LCDO2DLY
LCDHSW
LCDLDW
0292H
0293H
0294H
0295H
0
OE2D6
0
0
0
0
OE2D2
0
OE1 delay (bits 6-0)
OE2D5
0
OE2D4
0
OE2D3
W
OE2D1
0
OE2D0
0
LGOE2
Delay
register
0
OE2 delay (bits 6-0)
HSW7
HSW6
0
HSW5
0
HSW4
HSW3
HSW2
HSW1
HSW0
LHSYNC
Width
W
0
LDW7
0
0
0
0
0
LDW1
0
0
LDW0
0
register
Setting bit7-0 for LHSYNC Width
LDW6
0
LDW5
LDW4
0
LDW3
LDW2
LLOAD
width
register
W
0
O0W5
0
0
0
O0W2
0
LHSYNC width (bits 7-0)
O0W7
0
O0W6
0
O0W4
0
O0W3
O0W1
0
O0W0
0
LGOE0
width
register
W
LCDHO0W
0296H
0297H
0298H
0
LLOAD width (bits 7-0)
O1W7
O1W6
O1W5
O1W4
O1W3
O1W2
O1W1
O1W0
LGOE1
width
register
W
LCDHO1W
LCDHO2W
0
O2W7
0
0
O2W6
0
0
O2W5
0
0
0
0
O2W2
0
0
O2W1
0
0
O2W0
0
LGOE1 width (bits 7-0)
O2W4
O2W3
LGOE2
width
register
W
0
0
LGOE2 width (bits 7-0)
O2W9
0
O2W8
0
O1W9
0
O1W8
O0W8
LDW9
0
LDW8
0
HSW8
0
W
Bit8,9
for signal
width
0
0
LCDHWB8
0299H
LGOE2 width
(bits 9-8)
LGOE1 width
LGOE0
width
LLOAD width (bits 9-8)
LHSYNC
width
register
(bits 9-8)
(bit 8)
(bit 8)
92CZ26A-701
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TMP92CZ26A
(6) LCD controller (4/6)
Symbol
Name
Start
address
register
LCD main-L
Address
7
6
5
4
LMSA4
R/W
0
3
2
1
0
LMSA7
LMSA6
LMSA5
LMSA3
LMSA2
LMSA1
LSAML
02A0H
0
0
0
0
0
LMSA10
0
0
LCD main area start address (A7-A1)
LMSA15 LMSA14
LMSA13
LMSA12
LMSA11
LMA9
LMSA8
Start
address
register
R/W
LSAMM
LSAMH
LSASL
LSASM
LSASH
LSAHX
02A1H
02A2H
02A4H
02A5H
02A6H
02A8H
0
0
0
0
0
0
LMSA17
0
0
LMSA16
0
LCD main-M
LCD main area start address (A15-A8)
LMSA23 LMSA22
LMSA21
LMSA20
LMSA19
LMSA18
Start
address
register
R/W
0
1
0
0
0
0
LCD main-H
LCD main area start address (A23-A16)
LSSA7
LSSA6
LSSA5
LSSA4
R/W
0
LSSA3
LSSA2
LSSA1
0
Start
address
register
0
0
0
0
0
LSSA10
0
LCD sub-L
LCD sub area start address (A7-A1)
LSSA15
LSSA14
LSSA13
LSSA12
LSSA11
R/W
LSSA9
0
LSSA8
Start
address
register
0
LSSA23
0
0
LSSA22
1
0
0
0
0
LCD sub -M
LCD sub area start address (A15-A8)
LSSA21
LSSA20
LSSA19
R/W
LSSA18
LSSA17
0
LSSA16
Start
address
register
0
0
0
0
0
SAHX0
0
LCD sub -H
LCD sub area start address (A23-A16)
SAHX7
0
SAHX6
0
SAHX5
SAHX4
SAHX3
SAHX2
SAHX1
0
Hot point
register
LCD sub -X
R/W
0
0
0
0
LCD sub area HOT point (7-0)
SAHX9
SAHX8
0
Hot point
register
LCD sub -X
R/W
LSAHX
LSAHY
02A9H
02AAH
0
LCD sub area HOT
point (9-8)
SAHY7
0
SAHY6
0
SAHY5
0
SAHY4
0
SAHY3
0
SAHY2
0
SAHY1
0
SAHY0
0
Hot point
register
LCD sub -Y
R/W
LCD sub area HOT point (7-0)
SAHY8
R/W
0
Hot point
register
LSAHY
02ABH
LCD sub
area HOT
point (9-8)
LCD sub -Y
SAS7
0
SAS6
0
SAS5
0
SAS4
0
SAS3
0
SAS2
0
SAS1
0
SAS0
Segment
size
register
LCD sub
R/W
LSASS
LSASS
LSACS
02ACH
02ADH
02AEH
0
LCD sub area segment size (7-0)
SAS9
0
LCD sub area
segment size (9-8)
SAS8
Segment
size
register
LCD sub
R/W
0
SAC7
0
SAC6
0
SAC5
0
SAC4
0
SAC3
0
SAC2
0
SAC1
SAC0
Common
size
register
LCD sub
R/W
0
0
LCD sub area common size (7-0)
SAC8
R/W
0
Common
size
register
LCD sub
LSACS
02AFH
LCD sub
area
common
size (8)
92CZ26A-702
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TMP92CZ26A
(7) PMC
Symbol Name
Address
02A0H
7
6
5
4
3
2
−
1
0
PCM_ON
WUTM1
WUTM0
R/W
W
R/W
R/W
After system
reset
0
0
0
0
Data
retained
Data
retained
Data
retained
After Hot
reset
−
PMC
PMCCTL Control
Register
Power
Cut Mode
Always
write “0”
Warm-up time
00: 29 (15.625 ms)
01: 210 (31.25 ms)
10: 211 (62.5 ms)
11: 212 (125 ms)
0: Disable
1: Enable
Always
read as
“0”
92CZ26A-703
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TMP92CZ26A
(8) USB controller (1/6)
Symbol
Name
Address
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Descriptor
RAM 0
Descriptor RAM0
0500H
R/W
register
Undefined
D7
Undefined Undefined
D6 D5
Undefined
D4
Undefined
Undefined
D2
Undefined
D1
Undefined
D0
D3
Descriptor
RAM 1
register
Descriptor RAM1
Descriptor RAM2
Descriptor RAM3
0501H
0502H
0503H
R/W
Undefined
D7
Undefined Undefined
D6 D5
Undefined
D4
Undefined
Undefined
D2
Undefined
D1
Undefined
D0
D3
Descriptor
RAM 2
register
R/W
Undefined
D7
Undefined Undefined
D6 D5
Undefined
D4
Undefined
Undefined
D2
Undefined
D1
Undefined
D0
D3
Descriptor
RAM 3
register
R/W
Undefined
Undefined
Undefined Undefined
Undefined
Undefined
Undefined
Undefined
:
:
:
:
:
:
:
:
D7
D6
D5
D4
D3
D2
D1
D0
Descriptor
Descriptor RAM381 RAM 381
register
067DH
067EH
R/W
Undefined
D3
Undefined
D7
Undefined Undefined
D6 D5
Undefined
D4
Undefined
D2
Undefined
D1
Undefined
D0
Descriptor
Descriptor RAM382 RAM 382
register
R/W
Undefined
D7
Undefined Undefined
D6 D5
Undefined
D4
Undefined
Undefined
D2
Undefined
D1
Undefined
D0
D3
Descriptor
Descriptor RAM383 RAM 383
register
067FH
0780H
0781H
0782H
0783H
0789H
078AH
R/W
Undefined
Undefined
Undefined Undefined
Undefined
Undefined
Undefined
Undefined
EP0_DATA7 EP0_DATA6 EP0_DATA5 EP0_DATA4 EP0_DATA3 EP0_DATA2 EP0_DATA1 EP0_DATA0
R/W
Endpoint 0
Endpoint0
register
Undefined
Undefined Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
EP1_DATA7 EP1_DATA6 EP1_DATA5 EP1_DATA4 EP1_DATA3 EP1_DATA2 EP1_DATA1 EP1_DATA0
R/W
Endpoint 1
Endpoint1
register
Undefined
Undefined Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
EP2_DATA7 EP2_DATA6 EP2_DATA5 EP2_DATA4 EP2_DATA3 EP2_DATA2 EP2_DATA1 EP2_DATA0
R/W
Endpoint 2
Endpoint2
register
Undefined
Undefined Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
EP3_DATA7 EP3_DATA6 EP3_DATA5 EP3_DATA4 EP3_DATA3 EP3_DATA2 EP3_DATA1 EP3_DATA0
R/W
Endpoint 3
Endpoint3
register
Undefined
Undefined Undefined
Undefined
Undefined
Undefined
Undefined
Mode[0]
Undefined
Direction
Payload[2] Payload[1] Payload[0] Mode[1]
R/W
Endpoint 1
EP1_MODE
EP2_MODE
mode
register
0
0
0
0
0
0
Payload[2] Payload[1] Payload[0] Mode[1]
R/W
Mode[0]
Direction
Endpoint 2
mode
register
0
0
0
0
0
0
Payload[2] Payload[1] Payload[0] Mode[1]
R/W
Mode[0]
Direction
Endpoint 3
mode
EP3_MODE
078BH
register
0
0
0
0
0
0
92CZ26A-704
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TMP92CZ26A
(8) USB controller (2/6)
Symbol
Name
Address
7
6
5
4
3
STATUS[1]
R
2
1
0
TOGGLE
SUSPEND
STATUS[2]
STATUS[0] FIFO_DISABLE STAGE_ERR
Endpoint 0
status
EP0_STATUS
0790H
register
0
0
1
1
1
0
0
TOGGLE
SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
Endpoint 1
status
register
EP1_STATUS
EP2_STATUS
EP3_STATUS
0791H
0792H
0793H
R
0
0
1
1
1
0
0
TOGGLE
SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
Endpoint 2
status
register
R
0
0
1
1
1
0
0
TOGGLE
SUSPEND
STATUS[2]
STATUS[1]
STATUS[0] FIFO_DISABLE STAGE_ERR
Endpoint 3
status
R
register
0
0
1
1
1
0
0
Endpoint 0
size
register
Low A
PKT_ACTIVE
DATASIZE6
DATASIZE5
DATASIZE4
DATASIZE3
DATASIZE2
DATASIZE1
DATASIZE0
R
R
R
R
EP0_SIZE_L_A
EP1_SIZE_L_A
EP2_SIZE_L_A
EP3_SIZE_L_A
EP1_SIZE_L_B
EP2_SIZE_L_B
EP3_SIZE_L_B
EP1_SIZE_H_A
EP2_SIZE_H_A
EP3_SIZE_H_A
0798H
0799H
079AH
079BH
07A1H
07A2H
07A3H
07A9H
07AAH
07ABH
1
0
0
0
1
0
0
0
Endpoint 0
size
register
Low A
PKT_ACTIVE
DATASIZE6
DATASIZE5
DATASIZE4
DATASIZE3
DATASIZE2
DATASIZE1
DATASIZE0
1
0
0
0
1
0
0
0
Endpoint 2
size
register
Low A
PKT_ACTIVE
DATASIZE6
DATASIZE5
DATASIZE4
DATASIZE3
DATASIZE2
DATASIZE1
DATASIZE0
1
0
0
0
1
0
0
0
Endpoint 3
size
register
Low A
PKT_ACTIVE
DATASIZE6
DATASIZE5
DATASIZE4
DATASIZE3
DATASIZE2
DATASIZE1
DATASIZE0
1
0
0
0
1
0
0
0
Endpoint 1
size
register
Low B
PKT_ACTIVE
DATASIZE6
DATASIZE5
DATASIZE4
DATASIZE3
DATASIZE2
DATASIZE1
DATASIZE0
R
0
0
0
0
1
0
0
0
Endpoint 2
size
register
Low B
PKT_ACTIVE
DATASIZE6
DATASIZE5
DATASIZE4
DATASIZE3
DATASIZE2
DATASIZE1
DATASIZE0
R
0
0
0
0
1
0
0
0
Endpoint 3
size
register
Low B
PKT_ACTIVE
DATASIZE6
DATASIZE5
DATASIZE4
DATASIZE3
DATASIZE2
DATASIZE1
DATASIZE0
R
0
0
0
0
1
0
0
0
Endpoint 1
size
register
High A
DATASIZE9
DATASIZE8
DATASIZE7
R
0
0
0
Endpoint 2
size
register
High A
DATASIZE9
DATASIZE8
DATASIZE7
R
0
0
0
Endpoint 3
size
register
HighA
DATASIZE9
DATASIZE8
DATASIZE7
R
0
0
0
92CZ26A-705
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TMP92CZ26A
(8) USB controller (3/6)
Symbol
Name
Endpoint 1
size
register
High B
Address
7
6
5
4
3
2
1
DATASIZE8
R
0
DATASIZE9
DATASIZE7
EP1_SIZE_H_B
07B1H
0
0
0
Endpoint 2
size
register
High B
DATASIZE9
DATASIZE8
DATASIZE7
R
0
EP2_SIZE_H_B
EP3_SIZE_H_B
07B2H
07B3H
0
0
Endpoint 0
size
register
High B
DATASIZE9
DATASIZE8
DATASIZE7
R
0
0
0
DIRECTION
REQ_TYPE1
REQ_TYPE0
RECIPIENT4
RECIPIENT3
RECIPIENT2
RECIPIENT1
RECIPIENT0
bmRequest-
Type
R
R
R
R
R
bmRequestType
bRequest
07C0H
07C1H
07C2H
07C3H
07C4H
register
0
0
0
0
0
0
0
0
REQUEST7
REQUEST6
REQUEST5
REQUEST4
REQUEST3
REQUEST2
REQUEST1
REQUEST0
bRequest
register
0
0
0
0
0
0
0
0
VALUE_L7
VALUE_L6
VALUE_L5
VALUE_L4
VALUE_L3
VALUE_L2
VALUE_L1
VALUE_L0
wValue
register
Low
wValue_L
0
0
0
0
0
0
0
0
VALUE_H7
VALUE_H6
VALUE_H5
VALUE_H4
VALUE_H3
VALUE_H2
VALUE_H1
VALUE_H0
wValue
register
High
wValue_H
wIndex_L
0
0
0
0
0
0
0
0
INDEX_L7
INDEX_L6
INDEX_L5
INDEX_L4
INDEX_L3
INDEX_L2
INDEX_L1
INDEX_L0
wIndex
register
Low
0
0
0
0
0
0
0
0
INDEX_H7
INDEX_H6
INDEX_H5
INDEX_H4
INDEX_H3
INDEX_H2
INDEX_H1
INDEX_H0
wIndex
register
High
R
R
R
wIndex_H
wLength_L
wLength_H
07C5H
07C6H
07C7H
0
0
0
0
0
0
0
0
LENGTH_L7
LENGTH_L6
LENGTH_L5
LENGTH_L4
LENGTH_L3
LENGTH_L2
LENGTH_L1
LENGTH_L0
wLength
register
Low
0
0
0
0
0
0
0
0
LENGTH_H7
LENGTH_H6
LENGTH_H5
LENGTH_H4
LENGTH_H3
LENGTH_H2
LENGTH_H1
LENGTH_H0
wLength
register
High
0
0
0
0
0
0
0
0
92CZ26A-706
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TMP92CZ26A
(8) USB controller (4/6)
Symbol
Name Address
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
SetupRecei-
07C8H
SetupReceived
Current_Config
W
ved register
0
0
0
0
0
0
0
0
REMOTEWAKEUP
ALTERNATE[1] ALTERNATE[0] INTERFACE[1] INTERFACE[0]
CONFIG[1]
CONFIG[0]
Current_
R
0
R
Config
07C9H
07CAH
07CBH
07CCH
07CDH
07CEH
07CFH
07D0H
07D1H
07D3H
07D6H
register
0
0
0
0
0
0
S_INTERFACE G_INTERFACE S_CONFIG
G_CONFIG
G_DESCRIPT S_FEATURE
C_FEATURE
G_STATUS
Standard-
R
Standard Request Request
register
0
0
0
0
0
0
0
0
SOFT_RESET G_PORT_STS G_DEVICE_ID
VENDOR
CLASS
ExSTANDARD STANDARD
Request
Request
R
0
register
0
0
0
0
0
0
EP3_DSET_B
EP3_DSET_A EP2_DSET_B EP2_DSET_A EP1_DSET_B EP1_DSET_A
EP0_DSET_A
DATASET 1
DATASET1
R
R
0
register
0
0
0
0
0
0
EP7_DSET_B
EP7_DSET_A EP6_DSET_B EP6_DSET_A EP5_DSET_B EP5_DSET_A EP4_DSET_B EP4_DSET_A
DATASET 2
DATASET2
R
register
0
0
0
0
0
0
Configured
R/W
0
0
Addressed
Default
USB state
USB_STATE
R
register
0
0
1
EP7_EOPB
1
EP6_EOPB EP5_EOPB EP4_EOPB EP3_EOPB EP2_EOPB EP1_EOPB EP0_EOPB
W
EOP
EOP
register
1
1
1
1
1
1
1
EP[2]
EP[1]
EP[0]
Command[3] Command[2] Command[1] Command[0]
W
Command
COMMAND
register
0
0
0
0
0
0
0
EP3_SELECT EP2_SELECT EP1_SELECT
EP3_SINGLE EP2_SINGLE EP1_SINGLE
Endpoint 1
single
register
R/W
R/W
EPx_SINGLE1
EPx_BCS1
0
0
0
0
0
EP2_BCS
R/W
0
0
EP3_SELECT EP2_SELECT EP1_SELECT
EP3_BCS
EP1_BCS
Endpoint 1
BCS
register
R/W
0
0
0
0
0
Status_nak
R/W
Interrupt
control
INT_Control
register
0
S_Interface
0
G_Interface
0
S_Config
0
G_Config
G_Descript
0
S_Feature
0
C_Feature
0
G_Status
Standard
Request
mode
Standard Request
Mode
R/W
07D8H
07D9H
0
0
register
Soft_Reset G_Port_Sts G_DeviceId
R/W
Request
mode
Request Mode
register
0
0
0
92CZ26A-707
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TMP92CZ26A
(8) USB controller (5/6)
Symbol Name
Address
7
6
5
4
3
2
1
0
Reserved7
Reserved6
PaperError
Select
NotError
Reserved2
Reserved1
Reserved0
Port
W
R
Port Status
FRAME_L
FRAME_H
ADDRESS
USBREADY
status
register
07E0H
0
0
0
1
1
0
0
0
−
T[6]
T[5]
T[4]
T[3]
T[2]
T[1]
T[0]
Frame
register
Low
07E1H
07E2H
07E3H
07E6H
07E8H
0
0
0
0
0
0
0
0
T[10]
T[9]
T[8]
T[7]
CREATE FRAME_STS1 FRAME_STS0
R
Frame
register H
R
0
0
0
0
0
1
0
A6
A5
A4
A3
R
A2
A1
A0
Address
register
0
0
0
0
0
0
0
USBREADY
USB
ready
register
R/W
0
Set-
Descriptor
stall
S_D_STALL
Set Descriptor
STALL
W
0
register
INT_URST_STR INT_URST_END
INT_SUS
INT_RESUME INT_CLKSTOP
INT_CLKON
USB
interrupt
flag
R/W
07F0H
USBINTFR1
USBINTFR2
0
0
0
0
0
0
(Prohibit
RMW)
When read 0: Not generate interrupt When write 0: Clear flag
1: Generate interrupt 1: −
register 1
EP1_FULL_A
EP1_Empty_A EP1_FULL_B EP1_Empty_B EP2_FULL_A EP2_Empty_A EP2_FULL_B EP2_Empty_B
USB
interrupt
flag
R/W
07F1H
0
0
0
0
0
0
0
0
(Prohibit
RMW)
When read 0: Not generate interrupt When write 0: Clear flag
register 2
1: Generate interrupt
EP3_Empty_A EP3_FULL_B EP3_Empty_B
R/W
1: −
EP3_FULL_A
USB
interrupt
flag
0
0
0
0:Not generate interrupt
1:Generate interrupt
0: Clear flag
0
07F2H
USBINTFR3
(Prohibit
RMW)
When read
register 3
When write
1: −
INT_SETUP
INT_EP0
INT_STAS
INT_STASN
INT_EP1N
INT_EP2N
INT_EP3N
USB
interrupt
flag
R/W
0
07F3H
USBINTFR4
0
0
0
0
0
0
(Prohibit
RMW)
When read 0: Not generate interrupt When write 0: Clear flag
register 4
1: Generate interrupt
1: −
92CZ26A-708
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TMP92CZ26A
(8) USB controller (6/6)
Symbol Name Address
7
6
5
4
3
2
1
0
MSK_URST_STR MSK_URST_END
MSK_SUS
MSK_RESUME MSK_CLKSTOP MSK_CLKON
USB
interrupt
mask
R/W
USBINTMR1
USBINTMR2
07F4H
07F5H
1
1
1
1
1
EP2_MSK_FA
1
1
register 1
0: Be not masked 1: Be masked
EP1_MSK_FA
1
EP1_MSK_EA
EP1_MSK_FB
EP1_MSK_EB
EP2_MSK_EA EP2_MSK_FB EP2_MSK_EB
USB
interrupt
mask
R/W
1
1
1
1
1
1
register 2
0: Be not masked 1: Be masked
EP3_MSK_FA
EP3_MSK_EA
R/W
USB
interrupt
mask
1
1
USBINTMR3
07F6H
0: Be not masked
1: Be masked
register 3
MSK_SETUP
MSK_EP0
MSK_STAS
MSK_STASN
MSK_EP1N
MSK_EP2N
MSK_EP3N
USB
interrupt
mask
R/W
1
USBINTMR4
07F7H
07F8H
1
1
WAKEUP
0
1
1
1
1
register 4
0: Be not masked 1: Be masked
TRNS_USE
SPEED
USBCLKE
0
R/W
R/W
USB
control
register 1
0
1
USBCR1
Transceiver
0:disable
1:enble
Wake up
0: −
1:Start
92CZ26A-709
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TMP92CZ26A
(9) SPIC (1/2)
Symbol
Name
Address
7
6
XEN
R/W
0
5
4
3
2
1
0
SWRST
CLKSEL2 CLKSEL1 CLKSEL0
W
0
R/W
1
0
0
0820H
(Prohibit
RMW)
Software
reset
SYSCK
Select Baud Rate
0: disable
1: enable
000:Reserved 100: fSYS/8
0: don’t
care
001: fSYS/2
010: fSYS/3
011: fSYS/4
101: fSYS/16
110: fSYS/64
111: fSYS/256
1: Reset
SPI Mode
Setting
register
SPIMD
LOOPBACK MSB1ST DOSTAT
R/W
TCPOL
0
RCPOL
TDINV
RDINV
R/W
0
1
1
0
0
0
0821H
(Prohibit
RMW)
LOOPBACK Start bit for SPDO pin
Synchronous Synchronou Invert data Invert data
Test mode Transmit /
state
clock edge
during
s clock edge During
during transmitting receiving
During
0:disbale
1:enable
Receive
0:LSB
(no transmit)
0:fixed to ”0”
1:fixed to ”1”
transmitting receiving
0: disable
1: enable
0: disable
1: enable
1:MSB
0: fall
0: fall
1: rise
1: rise
CEN
0
SPCS_B
UNIT16
TXMOD
0
TXE
FDPXE
RXMOD
RXE
R/W
1
0
0
0
0
0
communica
tion
Data length Transmit
Transmit
control
Alignment
in
Receive
Mode
Receive
control
pin
SPCS
0822H
0: 8bit
mode
0: output
“0”
control
Full duplex
0: disable
1: enable
1: 16bit
0: UNIT
1:
0: disable
1: enable
0: UNIT
1:
0: disable
1: enable
0: disable
1: enable
1: output
“1”
Sequential
Sequential
SPI
SPICT
Control
register
CRC16_7_B CRCRX_TX_B CRCRESET_B
R/W
0
0
0
CRC select CRC data
CRC
0: Transmit calculate
0823H
0: CRC7
1: CRC16
1: receive
register
0:Reset
1:Release
Reset
TEMP
TEND
1
REND
R
1
R
0
Transmit
FIFO
Status
Transmit
Status
0: during
Receive
Status
0: during
0824H
transmission receiving
SPI
Status
register
0: no space
1: having
space
or having
or not having
SPIST
transmission receiving data
data
1: finish
1: finish or not
having space
0825H
082CH
082DH
TEMPIE
0
RFULIE
TENDIE
0
RENDIE
0
R/W
0
TEMP
RFUL
TEND
REND
SPI
interrupt
0:enable
1:disable
interrupt
0:enable
1:disable
interrupt
0:enable
1:disable
interrupt
0:enable
1:disable
Interrupt
enable
register
SPIIE
92CZ26A-710
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TMP92CZ26A
(9) SPIC (2/2)
Symbol
Name
Address
0826H
7
6
5
4
3
2
1
0
CRCD7
CRCD6
CRCD5
CRCD4
CRCD3
CRCD2
CRCD1
CRCD0
R
0
0
0
0
0
0
0
CRCD9
0
0
CRCD8
0
SPI
CRC
register
CRC result register [7:0]
SPICR
SPITD0
SPITD1
CRCD15 CRCD14 CRCD13 CRCD12 CRCD11 CRCD10
R
0827H
0830H
0831H
0832H
0833H
0
0
0
0
0
0
CRC result register [15:8]
TXD7
TXD6
TXD5
TXD4
TXD3
TXD2
TXD1
TXD0
R/W
0
0
0
0
0
0
0
0
SPI
transmission
data0
Transmit data register [7:0]
TXD15
TXD14
TXD13
TXD12
TXD11
TXD10
TXD9
TXD8
register
R/W
0
0
0
0
0
0
0
TXD1
0
0
TXD0
0
Transmit data register [15:8]
TXD7
TXD6
TXD5
TXD4
TXD3
TXD2
R/W
0
0
0
0
0
0
SPI
transmission
data1
Transmit data register [7:0]
TXD15
TXD14
TXD13
TXD12
TXD11
TXD10
TXD9
0
TXD8
0
register
R/W
0
RXD7
0
0
RXD6
0
0
RXD5
0
0
0
0
RXD2
0
Transmit data register [15:8]
RXD4
RXD3
RXD1
0
RXD0
0
R
0834H
0835H
0836H
0837H
0
0
SPI
receive
data0
Receive data register [7:0]
SPIRD0
RXD15
0
RXD14
0
RXD13
0
RXD12
RXD11
RXD10
0
RXD9
0
RXD8
0
register
R
0
0
Receive data register [15:8]
RXD7
0
RXD6
0
RXD5
0
RXD4
RXD3
RXD2
0
RXD1
0
RXD0
0
R
0
0
SPI
receive
data1
Receive data register [7:0]
SPIRD1
RXD15
0
RXD14
0
RXD13
0
RXD12
RXD11
RXD10
0
RXD9
0
RXD8
0
register
R
0
0
Receive data register [15:8]
92CZ26A-711
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TMP92CZ26A
(10) MMU (1/8)
Symbol
Name
Address
0880H
7
X7
6
X6
5
X5
4
X4
3
X3
2
X2
1
X1
0
X0
LOCALX
register
for
R/W
LOCALPX
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X
program
(“0” is disabled because of overlapped with Common-area.)
LXE
R/W
0
X8
R/W
0
LOCALX
register
for
LOCALPX
0881H LOCALX
BANK
Set BANK number for LOCAL-X
X8-X0 setting and CS
program
0:disable
1:enable
000000000∼011111111 CSXA
100000000∼111111111 CSXB
Y5
0
Y4
Y3
Y2
Y1
0
Y0
0
LOCALY
register
for
R/W
LOCALPY
LOCALPY
LOCALPZ
0882H
0
0
0
Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
program
LYE
R/W
0
LOCALY
register
for
0883H
LOCALY
BANK
0:disable
1:enable
program
Z7
Z6
0
Z5
0
Z4
0
Z3
0
Z2
0
Z1
0
Z0
0
LOCALZ
register
for
R/W
0884H
0885H
0
Set BANK number for LOCAL-Z
program
(“3” is disabled because of overlapped with Common-area.)
LZE
R/W
0
Z8
R/W
0
LOCALZ
register
for
LOCALPZ
LOCALZ
BANK
0:disable
1:enable
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
program
000000000∼001111111 CSZA 100000000∼101111111 CSZC
010000000∼011111111 CSZB 110000000∼111111111 CSZD
92CZ26A-712
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TMP92CZ26A
(10) MMU (2/8)
Symbol
Name
Address
0888H
7
X7
6
X6
5
X5
4
X4
3
X3
2
X2
1
X1
0
X0
LOCALX
register
for
R/W
LOCALLX
0
0
0
0
0
0
0
0
LCD
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
LXE
R/W
0
X8
R/W
0
LOCALX
register
for
LOCALLX
0889H LOCALX
BANK
Set BANK number for LOCAL-X
X8-X0 setting and CS
LCD
0:disable
1:enable
000000000∼011111111 CSXA
100000000∼111111111 CSXB
Y5
0
Y4
Y3
Y2
Y1
0
Y0
0
LOCALY
register
for
R/W
LOCALLY
088AH
0
0
0
Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
LCD
LYE
R/W
0
LOCALY
register
for
LOCALLY
LOCALLZ
088BH
LOCALY
BANK
0:disable
1:enable
LCD
Z7
Z6
0
Z5
0
Z4
0
Z3
0
Z2
0
Z1
0
Z0
0
LOCALZ
register
for
R/W
088CH
0
LCD
Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)
LZE
R/W
0
Z8
R/W
0
LOCALZ
register
for
LOCALLZ
088DH
LOCALZ
BANK
0:disable
1:enable
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
LCD
000000000∼001111111 CSZA 100000000∼101111111 CSZC
010000000∼011111111 CSZB 110000000∼111111111 CSZD
92CZ26A-713
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TMP92CZ26A
(10) MMU (3/8)
Symbol
Name
Address
0890H
7
X7
6
X6
5
X5
4
X4
3
X3
2
X2
1
X1
0
X0
LOCALX
register
for
R/W
LOCALRX
0
0
0
0
0
0
0
0
read
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
LXE
R/W
0
X8
R/W
0
LOCALX
register
for
LOCALRX
0891H LOCALX
BANK
Set BANK number for LOCAL-X
X8-X0 setting and CS
read
0:disable
1:enable
000000000∼011111111 CSXA
100000000∼111111111 CSXB
Y5
0
Y4
Y3
Y2
Y1
0
Y0
0
LOCALY
register
for
R/W
LOCALRY
0892H
0
0
0
Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
read
LYE
R/W
0
LOCALY
register
for
LOCALRY
LOCALRZ
0893H
LOCALY
BANK
0:disable
1:enable
read
Z7
Z6
0
Z5
0
Z4
0
Z3
0
Z2
0
Z1
0
Z0
0
LOCALZ
register
for
R/W
0894H
0
read
Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)
LZE
R/W
0
Z8
R/W
0
LOCALZ
register
for
LOCALRZ
0895H
LOCALZ
BANK
0:disable
1:enable
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
read
000000000∼001111111 CSZA 100000000∼101111111 CSZC
010000000∼011111111 CSZB 110000000∼111111111 CSZD
92CZ26A-714
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TMP92CZ26A
(10) MMU (4/8)
Symbol
Name
Address
7
6
5
4
3
2
1
0
X7
X6
X5
X4
X3
X2
X1
X0
LOCALX
register
for
R/W
LOCALWX
0898H
0
0
0
0
0
0
0
0
write
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
LXE
R/W
0
X8
R/W
0
LOCALX
register
for
LOCALWX
0899H LOCALX
BANK
Set BANK number for LOCAL-X
X8-X0 setting and CS
write
0:disable
1:enable
000000000∼011111111 CSXA
100000000∼111111111 CSXB
Y5
0
Y4
Y3
Y2
Y1
0
Y0
0
LOCALY
register
for
R/W
LOCALWY
089AH
0
0
0
Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
write
LYE
R/W
0
LOCALY
register
for
LOCALWY
LOCALWZ
089BH
LOCALY
BANK
0:disable
1:enable
write
Z7
Z6
0
Z5
0
Z4
0
Z3
0
Z2
0
Z1
0
Z0
0
LOCALZ
register
for
R/W
089CH
0
write
Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)
LZE
R/W
0
Z8
R/W
0
LOCALZ
register
for
LOCALWZ
089DH
LOCALZ
BANK
0:disable
1:enable
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
write
000000000∼001111111 CSZA 100000000∼101111111 CSZC
010000000∼011111111 CSZB 110000000∼111111111 CSZD
92CZ26A-715
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TMP92CZ26A
(10) MMU (5/8)
Symbol
Name
Address
08A0H
7
X7
6
X6
5
X5
4
X4
3
X3
2
X2
1
X1
0
X0
LOCALX
register
for DMA
source
R/W
LOCALESX
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
LXE
R/W
0
X8
R/W
0
LOCALX
register
for DMA
source
LOCALESX
08A1H LOCALX
BANK
Set BANK number for LOCAL-X
X8-X0 setting and CS
0:disable
1:enable
000000000∼011111111 CSXA
100000000∼111111111 CSXB
Y5
0
Y4
Y3
Y2
Y1
0
Y0
0
LOCALY
register
for DMA
source
R/W
LOCALESY
08A2H
0
0
0
Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
LYE
R/W
0
LOCALY
register
for DMA
source
LOCALESY
LOCALESZ
08A3H
LOCALY
BANK
0:disable
1:enable
Z7
Z6
0
Z5
0
Z4
0
Z3
0
Z2
0
Z1
0
Z0
0
LOCALZ
register
for DMA
source
R/W
08A4H
0
Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)
LZE
R/W
0
Z8
R/W
0
LOCALZ
register
for DMA
source
LOCALESZ
08A5H
LOCALZ
BANK
0:disable
1:enable
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
000000000∼001111111 CSZA 100000000∼101111111 CSZC
010000000∼011111111 CSZB 110000000∼111111111 CSZD
92CZ26A-716
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TMP92CZ26A
(10) MMU (6/8)
Symbol
Name
LOCALX
register
Address
08A8H
7
X7
6
X6
5
X5
4
X4
3
X3
2
X2
1
X1
0
X0
R/W
LOCALEDX
for DMA
0
0
0
0
0
0
0
0
destination
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
LXE
R/W
0
X8
R/W
0
LOCALX
register
for DMA
LOCALEDX
08A9H LOCALX
BANK
Set BANK number for LOCAL-X
X8-X0 setting and CS
destination
0:disable
1:enable
000000000∼011111111 CSXA
100000000∼111111111 CSXB
Y5
0
Y4
Y3
Y2
Y1
0
Y0
0
LOCALY
register
for DMA
R/W
LOCALEDY
08AAH
0
0
0
Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
destination
LYE
R/W
0
LOCALY
register
for DMA
LOCALEDY
LOCALEDZ
08ABH
LOCALY
BANK
0:disable
1:enable
destination
Z7
Z6
0
Z5
0
Z4
0
Z3
0
Z2
0
Z1
0
Z0
0
LOCALZ
register
for DMA
R/W
08ACH
0
destination
Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)
LZE
R/W
0
Z8
R/W
0
LOCALZ
register
for DMA
LOCALEDZ
08ADH
LOCALZ
BANK
0:disable
1:enable
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
destination
000000000∼001111111 CSZA 100000000∼101111111 CSZC
010000000∼011111111 CSZB 110000000∼111111111 CSZD
92CZ26A-717
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TMP92CZ26A
(10) MMU (7/8)
Symbol
Name
Address
08B0H
7
X7
6
X6
5
X5
4
X4
3
X3
2
X2
1
X1
0
X0
LOCALX
register
for DMA
source
R/W
LOCALOSX
0
0
0
0
0
0
0
0
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
LXE
R/W
0
X8
R/W
0
LOCALX
register
for DMA
source
LOCALOSX
08B1H LOCALX
BANK
Set BANK number for LOCAL-X
X8-X0 setting and CS
0:disable
1:enable
000000000∼011111111 CSXA
100000000∼111111111 CSXB
Y5
0
Y4
Y3
Y2
Y1
0
Y0
0
LOCALY
register
for DMA
source
R/W
LOCALOSY
08B2H
0
0
0
Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
LYE
R/W
0
LOCALY
register
for DMA
source
LOCALOSY
LOCALOSZ
08B3H
LOCALY
BANK
0:disable
1:enable
Z7
Z6
0
Z5
0
Z4
0
Z3
0
Z2
0
Z1
0
Z0
0
LOCALZ
register
for DMA
source
R/W
08B4H
0
Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)
LZE
R/W
0
Z8
R/W
0
LOCALZ
register
for DMA
source
LOCALOSZ
08B5H
LOCALZ
BANK
0:disable
1:enable
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
000000000∼001111111 CSZA 100000000∼101111111 CSZC
010000000∼011111111 CSZB 110000000∼111111111 CSZD
92CZ26A-718
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TMP92CZ26A
(10) MMU (8/8)
Symbol
Name
LOCALX
register
Address
08B8H
7
X7
6
X6
5
X5
4
X4
3
X3
2
X2
1
X1
0
X0
R/W
LOCALODX
for DMA
0
0
0
0
0
0
0
0
destination
Set BANK number for LOCAL-X (“0” is disabled because of overlapped with Common-area.)
LXE
R/W
0
X8
R/W
0
LOCALX
register
for DMA
LOCALODX
08B9H LOCALX
BANK
Set BANK number for LOCAL-X
X8-X0 setting and CS
destination
0:disable
1:enable
000000000∼011111111 CSXA
100000000∼111111111 CSXB
Y5
0
Y4
Y3
Y2
Y1
0
Y0
0
LOCALY
register
for DMA
R/W
LOCALODY
08BAH
0
0
0
Set BANK number for LOCAL-Y
(“3” is disabled because of overlapped with Common-area.)
destination
LYE
R/W
0
LOCALY
register
for DMA
LOCALODY
LOCALODZ
08BBH
LOCALY
BANK
0:disable
1:enable
destination
Z7
Z6
0
Z5
0
Z4
0
Z3
0
Z2
0
Z1
0
Z0
0
LOCALZ
register
for DMA
R/W
08BCH
0
destination
Set BANK number for LOCAL-Z (“3” is disabled because of overlapped with Common-area.)
LZE
R/W
0
Z8
R/W
0
LOCALZ
register
for DMA
LOCALODZ
08BDH
LOCALZ
BANK
0:disable
1:enable
Set BANK number for LOCAL-Z
Z8-Z0 setting and CS
destination
000000000∼001111111 CSZA 100000000∼101111111 CSZC
010000000∼011111111 CSZB 110000000∼111111111 CSZD
92CZ26A-719
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TMP92CZ26A
(11) NAND-Flash controller (1/4)
Symbol
Name Address
7
6
5
4
3
2
1
0
WE
ALE
CLE
CE0
CE1
ECCE
BUSY
ECCRST
R/W
0
0
0
0
0
0
0
0
WE
ALE
control
CLE
control
CE0
control
CE1
control
ECC
circuit
control
NAND
Flash
ECC
08C0H
(Prohibit
RMW)
enable
reset
control
state
0: Disable 0: “L” out 0: “L” out 0: “H” out 0: “H” out
1: Enable 1: “H” out 1: “H” out 1: “L” out 1: “L” out
0: Disable
1: Enable
1: Busy
0: −
0: Ready 1: Reset
*Always
read as
“0”.
NANDF
Control0
Register
NDFMCR0
SPLW1
0
SPLW0
0
SPHW1
R/W
SPHW0
0
RSECCL
RSEDN
0
RSESTA RSECGW
W
0
R/W
0
0
0
Reed-
Solomon
ECC
Strobe pulse width
Strobe pulse width
Reed-
Reed-
Reed-
Solomon
Solomon
Solomon
ECC
(Low width of NDRE ,
NDWE )
(High width of NDRE ,
NDWE )
08C1H
(Prohibit
RMW)
operation
0: Encode
(Write)
error
calculation
start
generator
latch
Inserted width
Inserted width
write
0: −
control
= (fSYS) × (set value)
= (fSYS) × (set value)
1: Decode
(Read)
0: Disable
1: Enable
1: Start
0: Disable
1: Enable
*Always
read as “0”.
INTERDY INTRSC
BUSW
R/W
ECCS
R/W
0
SYSCKE
R/W
R/W
0
R/W
0
0
0
Ready
Reed-
Data bus
width
ECC
Clock
control
interrupt
calculation
Solomon
08C2H
calculation
end
NANDF
NDFMCR1 Control1
Register
0: Disable
1: Enable
0:Hamming
1: Reed-
0: 8-bit
0: Disable
1: Enable
interrupt
1: 16-bit
0: Disable
1: Enable
STATE2
Solomon
STATE3
0
STATE1
0
STATE0
0
SEER1
SEER0
R
08C3H
0
Undefined Undefined
Status read (See the table below.)
ECCD7
0
ECCD6
ECCD5
ECCD4
ECCD3
ECCD2
0
ECCD1
ECCD0
R
08C4H
08C5H
08C6H
08C7H
0
0
0
0
0
0
NANDF
NDECCRD0 Code ECC
Register0
NAND Flash ECC Register (7-0) (7-0)
ECCD15 ECCD14 ECCD13 ECCD12 ECCD11 ECCD10
R
ECCD9
ECCD8
0
ECCD7
0
0
ECCD6
0
0
0
0
0
0
ECCD1
0
0
ECCD0
0
NAND Flash ECC Register (7-0) (15-8)
ECCD5
ECCD4
ECCD3
ECCD2
R
0
0
0
0
NANDF
NDECCRD1 Code ECC
Register1
NAND Flash ECC Register (7-0) (7-0)
ECCD15 ECCD14 ECCD13 ECCD12 ECCD11 ECCD10
R
ECCD9
0
ECCD8
0
0
0
0
0
0
0
NAND Flash ECC Register (7-0) (15-8)
92CZ26A-720
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TMP92CZ26A
(11) NAND-Flash controller (2/4)
Symbol
Name Address
7
6
5
4
3
2
1
0
ECCD7
ECCD6
ECCD5
ECCD4
ECCD3
ECCD2
ECCD1
ECCD0
R
08C8H
0
0
0
0
0
0
0
0
NANDF
NDECCRD2 Code ECC
Register2
NAND Flash ECC Register (7-0)
ECCD15 ECCD14 ECCD13 ECCD12 ECCD11 ECCD10
R
ECCD9
ECCD8
08C9H
08CAH
08CBH
08CCH
08CDH
0
ECCD7
0
0
ECCD6
0
0
0
0
0
0
0
NAND Flash ECC Register (15-8)
ECCD5
ECCD4
ECCD3
ECCD2
ECCD1
ECCD0
R
0
0
0
0
0
0
NANDF
NDECCRD3 Code ECC
Register3
NAND Flash ECC Register (7-0)
ECCD15 ECCD14 ECCD13 ECCD12 ECCD11 ECCD10
R
ECCD9
ECCD8
0
ECCD7
0
0
ECCD6
0
0
0
0
0
0
ECCD1
0
0
ECCD0
0
NAND Flash ECC Register (15-8)
ECCD5
ECCD4
ECCD3
ECCD2
R
0
0
0
0
NANDF
NDECCRD4 Code ECC
Register4
NAND Flash ECC Register (7-0)
ECCD15 ECCD14 ECCD13 ECCD12 ECCD11 ECCD10
R
ECCD9
0
ECCD8
0
0
0
0
0
0
0
NAND Flash ECC Register (15-8)
92CZ26A-721
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TMP92CZ26A
(11) NAND-Flash controller (3/4)
Symbol
Name Address
7
6
5
4
3
2
1
0
RS0A7
RS0A6
RS0A5
RS0A4
RS0A3
RS0A2
RS0A1
RS0A0
R
08D0H
0
0
0
0
0
0
0
0
RS0A8
0
NAND Flash Reed-Solomon Calculation Result Address Register (7-0)
RS0A9
NANDF
read solomon
Result
NDRSCA0
R
address
0
Register0
08D1H
NAND Flash
Reed-Solomon
Calculation Result
Address Register (9-8)
RS0D7
RS0D6
0
RS0D5
0
RS0D4
0
RS0D3
0
RS0D2
0
RS0D1
RS0D0
NANDF
R
read solomon
08D2H
NDRSCD0
NDRSCA1
NDRSCD1
NDRSCA2
NDRSCD2
Result data
0
RS1A7
0
0
0
Register0
NAND Flash Reed-Solomon Calculation Result Data Register (7-0)
RS1A6
RS1A5
RS1A4
RS1A3
RS1A2
RS1A1
RS1A0
0
R
08D4H
0
0
0
0
0
0
NAND Flash Reed-Solomon Calculation Result Address Register (7-0)
RS1A9
NANDF
read solomon
Result
RS1A8
R
address
0
0
Register1
08D5H
NAND Flash Reed-
Solomon Calculation
Result Address
Register (9-8)
RS1D7
0
RS1D6
0
RS1D5
0
RS1D4
0
RS1D3
0
RS1D2
0
RS1D1
RS1D0
0
NANDF
R
read solomon
08D6H
Result data
0
Register1
NAND Flash Reed-Solomon Calculation Result Data Register (7-0)
RS2A7
RS2A6
RS2A5
RS2A4
RS2A3
RS2A2
RS2A1
RS2A0
R
08D8H
0
0
0
0
0
0
0
0
NANDF
read solomon
Result
NAND Flash Reed-Solomon Calculation Result Address Register (7-0)
RS2A9
RS2A8
0
R
address
0
Register2
08D9H
NAND Flash Reed-
Solomon Calculation
Result Address
Register (9-8)
RS2D7
0
RS2D6
0
RS2D5
0
RS2D4
0
RS2D3
0
RS2D2
0
RS2D1
RS2D0
0
NANDF
R
read solomon
08DAH
Result data
0
Register2
NAND Flash Reed-Solomon Calculation Result Data Register (7-0)
92CZ26A-722
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TMP92CZ26A
(11) NAND-Flash controller (4/4)
Symbol
Name Address
7
6
5
4
3
2
1
0
RS3A7
RS3A6
RS3A5
RS3A4
RS3A3
RS3A2
RS3A1
RS3A0
R
08DCH
0
0
0
0
0
0
0
0
RS3A8
0
NANDF
read
NAND Flash Reed-Solomon Calculation Result Address Register (7-0)
RS3A9
solomon
Result
NDRSCA3
R
address
0
Register3
08DDH
NAND Flash Reed-
Solomon Calculation
Result Address
Register (9-8)
NANDF
read
RS2D7
RS2D6
0
RS2D5
0
RS2D4
0
RS2D3
0
RS2D2
0
RS2D1
RS2D0
R
NDRSCD3
solomon
Result data
Register3
08DEH
0
0
0
NAND Flash Reed-Solomon Calculation Result Data Register (7-0)
D6 D5 D4 D3 D2 D1
D7
D0
R/W
1FF0H
1FF1H
1FF2H
1FF3H
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
NAND-Flash Data Register (7-0)
NANDF
Data
NDFDTR0
D15
D14
D13
D12
D11
D10
D9
D8
Register0
R/W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
NAND-Flash Data Register (15-8)
D7
D6
D5
D4
D3
D2
D1
D0
R/W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
NAND-Flash Data Register (7-0)
NANDF
Data
NDFDTR1
D15
D14
D13
D12
D11
D10
D9
D8
Register1
R/W
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
NAND-Flash Data Register (15-8)
92CZ26A-723
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TMP92CZ26A
(12) DMAC (1/7)
Symbol
Name Address
7
6
5
4
3
2
1
0
D0SA7
D0SA6
D0SA5
D0SA4
D0SA3
D0SA2
D0SA1
D0SA0
R/W
0900H
0901H
0902H
0904H
0905H
0906H
0908H
0909H
090AH
090BH
0
0
0
0
0
0
0
0
Source address for DMA0 (7:0)
D0SA15
D0SA14
D0SA13
D0SA12
D0SA11
D0SA10
D0SA9
D0SA8
DMA
source
R/W
HDMAS0
address
Register0
0
0
0
0
0
0
0
0
Source address for DMA0 (15:8)
D0SA23
D0SA22
D0SA21
D0SA20
D0SA19
D0SA18
D0SA17
D0SA16
R/W
0
0
0
0
0
0
0
0
Source address for DMA0 (23:16)
D0DA7
D0DA6
D0DA5
D0DA4
D0DA3
D0DA2
D0DA1
D0DA0
R/W
0
0
0
0
0
0
0
0
Destination address for DMA0 (7:0)
D0DA15
D0DA14
D0DA13
D0DA12
D0DA11
D0DA10
D0DA9
D0DA8
DMA
R/W
destination
address
Register0
HDMAD0
0
0
0
0
0
0
0
0
Destination address for DMA0 (15:8)
D0DA23
D0DA22
D0DA21
D0DA20
D0DA19
D0DA18
D0DA17
D0DA16
R/W
0
0
0
0
0
0
0
0
Destination address for DMA0 (23:16)
D0CA7
D0CA6
D0CA5
D0CA4
D0CA3
D0CA2
D0CA1
D0CA0
R/W
DMA
0
0
0
0
0
0
0
0
Transfer
count
number A
Register0
Transfer count A [7:0] for DMA0
HDMACA0
D0CA15
D0CA14
D0CA13
D0CA12
D0CA11
D0CA10
D0CA9
D0CA8
R/W
0
D0CB7
0
0
D0CB6
0
0
0
0
0
0
D0CB1
0
0
D0CB0
0
Transfer count A [15:8] for DMA0
D0CB5
D0CB4
D0CB3
D0CB2
R/W
DMA
Transfer
count
0
0
0
0
Transfer count B [7:0] for DMA0
HDMACB0
D0CB15
0
D0CB14
0
D0CB13
D0CB12
D0CB11
D0CB10
D0CB9
0
D0CB8
0
number B
Register0
R/W
0
0
0
0
Transfer count B [15:8] for DMA0
D0M4
D0M3
D0M2
R/W
0
D0M1
0
D0M0
0
0
0
DMA transfer mode
Transfer data size
00: 1 byte
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
100: Source/destination INC
(MEM → MEM)
DMA
transfer
Mode
01: 2 bytes
10: 4 bytes
HDMAM0
090CH
11: Reserved
Register0
101: Source/destination DEC
(MEM → MEM)
110: Source/destination fixed
(I/O→ I/O)
111: Reserved
92CZ26A-724
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TMP92CZ26A
(12) DMAC (2/7)
Symbol
Name Address
7
6
5
4
3
2
1
0
D1SA7
D1SA6
D1SA5
D1SA4
D1SA3
D1SA2
D1SA1
D1SA0
R/W
0910H
0911H
0912H
0914H
0915H
0916H
0918H
0919H
091AH
091BH
0
0
0
0
0
0
0
0
Set source address for DMA1 (7:0)
D1SA15
D1SA14
D1SA13
D1SA12
D1SA11
D1SA10
D1SA9
D1SA8
DMA
source
R/W
HDMAS1
address
Register1
0
0
0
0
0
0
0
0
Set source address for DMA1 (15:8)
D1SA23
D1SA22
D1SA21
D1SA20
D1SA19
D1SA18
D1SA17
D1SA16
R/W
0
0
0
0
0
0
0
0
Set source address for DMA1 (23:16)
D1DA7
D1DA6
D1DA5
D1DA4
D1DA3
D1DA2
D1DA1
D1DA0
R/W
0
0
0
0
0
0
0
0
Set destination address for DMA1 (7:0)
D1DA15
D1DA14
D1DA13
D1DA12
D1DA11
D1DA10
D1DA9
D1DA8
DMA
R/W
destination
address
Register1
HDMAD1
0
0
0
0
0
0
0
0
Set destination address for DMA1 (15:8)
D1DA23
D1DA22
D1DA21
D1DA20
D1DA19
D1DA18
D1DA17
D1DA16
R/W
0
0
0
0
0
0
0
0
Set destination address for DMA1 (23:16)
D1CA7
D1CA6
D1CA5
D1CA4
D1CA3
D1CA2
D1CA1
D1CA0
R/W
DMA
0
0
0
0
0
0
0
0
Transfer
count
number A
Register1
Set transfer-count-number A for DMA1 (7:0)
HDMACA1
D1CA15
D1CA14
D1CA13
D1CA12
D1CA11
D1CA10
D1CA9
D1CA8
R/W
0
D1CB7
0
0
D1CB6
0
0
0
0
0
0
D1CB1
0
0
D1CB0
0
Set transfer-count-number A for DMA1 (15:8)
D1CB5
D1CB4
D1CB3
D1CB2
R/W
DMA
Transfer
count
0
0
0
0
Set transfer-count-number B for DMA1 (7:0)
HDMACB1
D0CB15
0
D0CB14
0
D0CB13
D0CB12
D0CB11
D0CB10
D0CB9
0
D0CB8
0
number B
Register1
R/W
0
0
0
0
Set transfer-count-number B for DMA1 (15:8)
D1M4
D1M3
D1M2
R/W
0
D1M1
0
D1M0
0
0
0
DMA transfer mode
Transfer data size
00: 1 byte
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
100: Source/destination INC
(MEM → MEM)
DMA
transfer
Mode
01: 2 bytes
10: 4 bytes
HDMAM1
091CH
11: Reserved
Register1
101: Source/destination DEC
(MEM → MEM)
110: Source/destination fixed
(I/O→ I/O)
111: Reserved
92CZ26A-725
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TMP92CZ26A
(12) DMAC (3/7)
Symbol
Name Address
7
6
5
4
3
2
1
0
D2SA7
D2SA6
D2SA5
D2SA4
D2SA3
D2SA2
D2SA1
D2SA0
R/W
0920H
0921H
0922H
0924H
0925H
0926H
0928H
0929H
092AH
092BH
0
0
0
0
0
0
0
0
Source address for DMA2 (7:0)
D2SA15
D2SA14
D2SA13
D2SA12
D2SA11
D2SA10
D2SA9
D2SA8
DMA
source
R/W
HDMAS2
address
Register2
0
0
0
0
0
0
0
0
Source address for DMA2 (15:8)
D2SA23
D2SA22
D2SA21
D2SA20
D2SA19
D2SA18
D2SA17
D2SA16
R/W
0
0
0
0
0
0
0
0
Source address for DMA2 (23:16)
D2DA7
D2DA6
D2DA5
D2DA4
D2DA3
D2DA2
D2DA1
D2DA0
R/W
0
0
0
0
0
0
0
0
Destination address for DMA2 (7:0)
D2DA15
D2DA14
D2DA13
D2DA12
D2DA11
D2DA10
D2DA9
D2DA8
DMA
R/W
destination
address
Register2
HDMAD2
0
0
0
0
0
0
0
0
Destination address for DMA2 (15:8)
D2DA23
D2DA22
D2DA21
D2DA20
D2DA19
D2DA18
D2DA17
D2DA16
R/W
0
0
0
0
0
0
0
0
Destination address for DMA2 (23:16)
D2CA7
D2CA6
D2CA5
D2CA4
D2CA3
D2CA2
D2CA1
D2CA0
R/W
DMA
0
0
0
0
0
0
0
0
Transfer
count
number A
Register2
Transfer count A [7:0] for DMA2
HDMACA2
D2CA15
D2CA14
D2CA13
D2CA12
D2CA11
D2CA10
D2CA9
D2CA8
R/W
0
D2CB7
0
0
D2CB6
0
0
0
0
0
0
D2CB1
0
0
D2CB0
0
Transfer count A [15:8] for DMA2
D2CB5
D2CB4
D2CB3
D2CB2
R/W
DMA
Transfer
count
0
0
0
0
Transfer count B [7:0] for DMA2
HDMACB2
D2CB15
0
D2CB14
0
D2CB13
D2CB12
D2CB11
D2CB10
D2CB9
0
D2CB8
0
number B
Register2
R/W
0
0
0
0
Transfer count A [15:8] for DMA2
D2M4
D2M3
D2M2
R/W
0
D2M1
0
D2M0
0
0
0
DMA transfer mode
Transfer data size
00: 1 byte
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
100: Source/destination INC
(MEM → MEM)
DMA
transfer
Mode
01: 2 bytes
10: 4 bytes
HDMAM2
092CH
11: Reserved
Register2
101: Source/destination DEC
(MEM → MEM)
110: Source/destination fixed
(I/O→ I/O)
111: Reserved
92CZ26A-726
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TMP92CZ26A
(12) DMAC (4/7)
Symbol
Name Address
7
6
5
4
3
2
1
0
D3SA7
D3SA6
D3SA5
D3SA4
D3SA3
D3SA2
D3SA1
D3SA0
R/W
0930H
0931H
0932H
0934H
0935H
0936H
0938H
0939H
093AH
093BH
0
0
0
0
0
0
0
0
Set source address for DMA3 (7:0)
D3SA15
D3SA14
D3SA13
D3SA12
D3SA11
D3SA10
D3SA9
D3SA8
DMA
source
R/W
HDMAS3
address
Register3
0
0
0
0
0
0
0
0
Set source address for DMA3 (15:8)
D3SA23
D3SA22
D3SA21
D3SA20
D3SA19
D3SA18
D3SA17
D3SA16
R/W
0
0
0
0
0
0
0
0
Set source address for DMA3 (23:16)
D3DA7
D3DA6
D3DA5
D3DA4
D3DA3
D3DA2
D3DA1
D3DA0
R/W
0
0
0
0
0
0
0
0
Set destination address for DMA3 (7:0)
D3DA15
D3DA14
D3DA13
D3DA12
D3DA11
D3DA10
D3DA9
D3DA8
DMA
R/W
destination
address
Register3
HDMAD3
0
0
0
0
0
0
0
0
Set destination address for DMA3 (15:8)
D3DA23
D3DA22
D3DA21
D3DA20
D3DA19
D3DA18
D3DA17
D3DA16
R/W
0
0
0
0
0
0
0
0
Set destination address for DMA3 (23:16)
D3CA7
D3CA6
D3CA5
D3CA4
D3CA3
D3CA2
D3CA1
D3CA0
R/W
DMA
0
0
0
0
0
0
0
0
Transfer
count
number A
Register3
Transfer count A [7:0] for DMA3
HDMACA3
D3CA15
D3CA14
D3CA13
D3CA12
D3CA11
D3CA10
D3CA9
D3CA8
R/W
0
D3CB7
0
0
D3CB6
0
0
0
0
0
0
D3CB1
0
0
D3CB0
0
Transfer count A [15:8] for DMA3
D3CB5
D3CB4
D3CB3
D3CB2
R/W
DMA
Transfer
count
0
0
0
0
Transfer count B [7:0] for DMA3
HDMACB3
D3CB15
0
D3CB14
0
D3CB13
D3CB12
D3CB11
D3CB10
D3CB9
0
D3CB8
0
number B
Register3
R/W
0
0
0
0
Transfer count B [15:8] for DMA3
D3M4
D3M3
D3M2
R/W
0
D3M1
0
D3M0
0
0
0
DMA transfer mode
Transfer data size
00: 1 byte
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
100: Source/destination INC
(MEM → MEM)
DMA
transfer
Mode
01: 2 bytes
10: 4 bytes
HDMAM3
093CH
11: Reserved
Register3
101: Source/destination DEC
(MEM → MEM)
110: Source/destination fixed
(I/O→ I/O)
111: Reserved
92CZ26A-727
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TMP92CZ26A
(12) DMAC (5/7)
Symbol
Name Address
7
6
5
4
3
2
1
0
D4SA7
D4SA6
D4SA5
D4SA4
D4SA3
D4SA2
D4SA1
D4SA0
R/W
0940H
0941H
0942H
0944H
0945H
0946H
0948H
0949H
094AH
094BH
0
0
0
0
0
0
0
0
Source address for DMA4 (7:0)
D4SA15
D4SA14
D4SA13
D4SA12
D4SA11
D4SA10
D4SA9
D4SA8
DMA
source
R/W
HDMAS4
address
Register4
0
0
0
0
0
0
0
0
Source address for DMA4 (15:8)
D4SA23
D4SA22
D4SA21
D4SA20
D4SA19
D4SA18
D4SA17
D4SA16
R/W
0
0
0
0
0
0
0
0
Source address for DMA4 (23:16)
D4DA7
D4DA6
D4DA5
D4DA4
D4DA3
D4DA2
D4DA1
D4DA0
R/W
0
0
0
0
0
0
0
0
Destination address for DMA4 (7:0)
D4DA15
D4DA14
D4DA13
D4DA12
D4DA11
D4DA10
D4DA9
D4DA8
DMA
R/W
destination
address
Register4
HDMAD4
0
0
0
0
0
0
0
0
Destination address for DMA4 (15:8)
D4DA23
D4DA22
D4DA21
D4DA20
D4DA19
D4DA18
D4DA17
D4DA16
R/W
0
0
0
0
0
0
0
0
Destination address for DMA4 (23:16)
D4CA7
D4CA6
D4CA5
D4CA4
D4CA3
D4CA2
D4CA1
D4CA0
R/W
DMA
0
0
0
0
0
0
0
0
Transfer
count
number A
Register4
Transfer count A [15:8] for DMA4
HDMACA4
D4CA15
D4CA14
D4CA13
D4CA12
D4CA11
D4CA10
D4CA9
D4CA8
R/W
0
D4CB7
0
0
D4CB6
0
0
0
0
0
0
D4CB1
0
0
D4CB0
0
Transfer count A [15:8] for DMA4
D4CB5
D4CB4
D4CB3
D4CB2
R/W
DMA
Transfer
count
0
0
0
0
Transfer count B [7:0] for DMA4
HDMACB4
D4CB15
0
D4CB14
0
D4CB13
D4CB12
D4CB11
D4CB10
D4CB9
0
D4CB8
0
number B
Register4
R/W
0
0
0
0
Transfer count B [15:8] for DMA4
D4M4
D4M3
D4M2
R/W
0
D4M1
0
D4M0
0
0
0
DMA transfer mode
Transfer data size
00: 1 byte
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
100: Source/destination INC
(MEM → MEM)
DMA
transfer
Mode
01: 2 bytes
10: 4 bytes
HDMAM4
094CH
11: Reserved
Register4
101: Source/destination DEC
(MEM → MEM)
110: Source/destination fixed
(I/O→ I/O)
111: Reserved
92CZ26A-728
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TMP92CZ26A
(12) DMAC (6/7)
Symbol
Name Address
7
6
5
4
3
2
1
0
D5SA7
D5SA6
D5SA5
D5SA4
D5SA3
D5SA2
D5SA1
D5SA0
R/W
0950H
0951H
0952H
0954H
0955H
0956H
0958H
0959H
095AH
095BH
0
0
0
0
0
0
0
0
Source address for DMA5 (7:0)
D5SA15
D5SA14
D5SA13
D5SA12
D5SA11
D5SA10
D5SA9
D5SA8
DMA
source
R/W
HDMAS5
address
Register5
0
0
0
0
0
0
0
0
Source address for DMA5 (15:8)
D5SA23
D5SA22
D5SA21
D5SA20
D5SA19
D5SA18
D5SA17
D5SA16
R/W
0
0
0
0
0
0
0
0
Source address for DMA5 (23:16)
D5DA7
D5DA6
D5DA5
D5DA4
D5DA3
D5DA2
D5DA1
D5DA0
R/W
0
0
0
0
0
0
0
0
Destination address for DMA5 (7:0)
D5DA15
D5DA14
D5DA13
D5DA12
D5DA11
D5DA10
D5DA9
D5DA8
DMA
R/W
destination
address
Register5
HDMAD5
0
0
0
0
0
0
0
0
Destination address for DMA5 (15:8)
D5DA23
D5DA22
D5DA21
D5DA20
D5DA19
D5DA18
D5DA17
D5DA16
R/W
0
0
0
0
0
0
0
0
Destination address for DMA5 (23:16)
D5CA7
D5CA6
D5CA5
D5CA4
D5CA3
D5CA2
D54CA1
D5CA0
R/W
DMA
0
0
0
0
0
0
0
0
Transfer
count
number A
Register5
Transfer count A [7:0] for DMA5
HDMACA5
D5CA15
D5CA14
D5CA13
D5CA12
D5CA11
D5CA10
D5CA9
D5CA8
R/W
0
D5CB7
0
0
D5CB6
0
0
0
0
0
0
D5CB1
0
0
D5CB0
0
Transfer count A [15:8] for DMA5
D5CB5
D5CB4
D5CB3
D5CB2
R/W
DMA
Transfer
count
0
0
0
0
Transfer count B [7:0] for DMA5
HDMACB5
D5CB15
0
D5CB14
0
D5CB13
D5CB12
D5CB11
D5CB10
D5CB9
0
D5CB8
0
number B
Register5
R/W
0
0
0
0
Transfer count B [15:8] for DMA5
D5M4
D5M3
D5M2
R/W
0
D5M1
0
D5M0
0
0
0
DMA transfer mode
Transfer data size
00: 1 byte
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
100: Source/destination INC
(MEM → MEM)
DMA
transfer
Mode
01: 2 bytes
10: 4 bytes
HDMAM5
095CH
11: Reserved
Register5
101: Source/destination DEC
(MEM → MEM)
110: Source/destination fixed
(I/O→ I/O)
111: Reserved
92CZ26A-729
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TMP92CZ26A
(12) DMAC (7/7)
Symbol
Name Address
7
6
5
4
3
2
1
0
DMAE5
DMAE4
DMAE3
DMAE2
DMAE1
DMAE0
R/W
DMA
enable
Register
HDMAE
097EH
0
0
0
0
0
0
DMA channel operation
0: Disable 1: Enable
DMATE
0
DMATR6 DMATR5 DMATR4 DMATR3 DMATR2 DMATR1 DMATR0
R/W
0
0
0
0
0
0
0
DMA
timer
Register
HDMATR
097FH
Maximum bus occupancy time setting
The value to be set in <DMATR6:0> should be obtained by
Timer
operation
“Maximum bus occupancy time / (256/f
)”.
0: Disable
1: Enable
SYS
“00H” cannot be set.
92CZ26A-730
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TMP92CZ26A
(13) Clock gear, PLL
Symbol
Name
Address
7
6
XTEN
5
4
3
2
WUEF
R/W
0
1
0
PRCK
R/W
0
USBCLK1
USBCLK0
R/W
0
1
0
System
clock
control
register0
Low
Select the clock of
USB(fUSB
Warm-up
timer
Select
)
-frequency
oscillator
circuit (fs)
Prescaler
clock
SYSCR0
10E0H
00: Disable
01: Reserved
10: X1USB
11: fPLLUSB
0: fSYS/2
1: fSYS/8
0: Stop
1:
Oscillation
GEAR2
1
Select gear value of high
frequency (fc)
GEAR1
R/W
0
GEAR0
0
System
clock
control
register1
SYSCR1
10E1H
000: fc
101: (Reserved)
001: fc/2
010: fc/4
011: fc/8
110: (Reserved)
111: (Reserved)
100: fc/16
−
CKOSEL WUPTM1 WUPTM0 HALTM1 HALTM0
R/W
0
1
0
1
1
0
System
clock
control
register2
Always
Select
Warm-Up Timer
00: Reserved
01: 28/inputted frequency 01: STOP mode
10:214/inputted frequency 10: IDLE1 mode
11:216/inputted frequency 11: IDLE2 mode
HALT mode
SYSCR2
10E2H
write “0”.
CLKOUT
00: Reserved
0: fSYS
1: fs
PROTECT
−
R/W
0
EXTIN
R/W
0
DRVOSCH DRVOSCL
R
0
R/W
1
R/W
1
EMC
control
register0
EMCCR0
10E3H
Always
Protect flag
0: OFF
1: External fc oscillator fs oscillator
write “0”.
clock
drive ability drive ability
1: NORMAL 1: NORMAL
1: ON
0: WEAK
0: WEAK
EMC
control
register1
EMCCR1
EMCCR2
10E4H
10E5H
Switching the protect ON/OFF by write to following 1st-KEY,2nd-KEY
1st-KEY: EMCCR1=5AH,EMCCR2=A5H in succession write
2nd-KEY: EMCCR1=A5H,EMCCR2=5AH in succession write
EMC
control
register2
FCSEL
R/W
LUPFG
R
0
0
PLL
control
register0
Select fc
clock
Lock-up
timer
PLLCR0
10E8H
0 : f
1 : f
Status flag
0 : not end
1 : end
OSCH
PLL
PLL0
0
PLL1
R/W
0
LUPSEL
PLLTIMES
R/W
0
0
Select the
number of
PLL
PLL0 for
CPU
PLL1 for
USB
Select
PLL
stage of
Lock up
counter
PLLCR1
control
register1
10E9H
0: Off
1: On
0: Off
1: On
0: ×12
0: 12 stage
(for PLL0)
1: ×16
1:13 stage
(for PLL1)
92CZ26A-731
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TMP92CZ26A
(14) 8-bit timer (1/2)
Symbol
Name
Address
7
TA0RDE
R/W
6
5
4
3
2
1
0
I2TA01 TA01PRUN TA1RUN TA0RUN
R/W
0
0
0
0
0
TMRA01
RUN
register
Double
IDLE2
TMRA01
prescaler
Up counter Up counter
(UC1) (UC0)
TA01RUN
1100H
buffer
0: Stop
1: Operate
0: Disable
1: Enable
0: Stop and clear
1: Run (Count up)
1102H
(Prohibit
RMW)
−
W
0
8-bit timer
register 0
TA0REG
TA1REG
1103H
(Prohibit
RMW)
−
W
0
8-bit timer
register 1
TA01M1
0
TA01M0
0
PWM01
PWM00 TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0
R/W
0
0
0
0
0
0
TMRA01
MODE
register
Operation mode
PWM cycle
Source clock for TMRA1 Source clock for TMRA0
TA01MOD
1104H
00: 8-bit timer mode
01: 16-bit timer mode 01: 26
00: Reserved
00: TA0TRG
01: φT1
00: TA0IN pin
01: φT1
10: 8-bit PPG mode
11: 8-bit PWM mode
10: 27
11: 28
10: φT16
10: φT4
11: φT256
11: φT16
TA1FFC1 TA1FFC0 TA1FFIE TA1FFIS
R/W
W
1
1
0
0
TMRA1
Flip-Flop
control
1105H
(Prohibit
RMW)
00: Invert TA1FF
01: Set TA1FF
10: Clear TA1FF
11: Don’t care
TA1FF
TA1FF
TA1FFCR
control for inversion
inversion select
register
0: Disable 0: TMRA0
1: Enable 1: TMRA1
TA2RDE
R/W
I2TA23 TA23PRUN TA3RUN TA2RUN
R/W
0
0
0
0
0
TMRA23
RUN
register
Double
IDLE2
TMRA23
prescaler
Up counter Up counter
(UC3) (UC2)
TA23RUN
1108H
buffer
0: Stop
1: Operate
0: Disable
1: Enable
0: Stop and clear
1: Run (Count up)
110AH
(Prohibit
RMW)
−
W
0
8-bit timer
register 2
TA2REG
TA3REG
110BH
(Prohibit
RMW)
−
W
0
8-bit timer
register 3
TA23M1
0
TA23M0
0
PWM21
PWM20 TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0
R/W
0
0
0
0
0
0
TMRA23
MODE
register
Operation mode
PWM cycle
Source clock for TMRA3 Source clock for TMRA2
TA23MOD
110CH
00: TA2TRG
01: φT1
00: Reserved
01: φT1
00: 8-bit timer mode
01: 16-bit timer mode 01: 26
00: Reserved
10: φT16
10: φT4
10: 8-bit PPG mode
11: 8-bit PWM mode
10: 27
11: 28
11: φT256
11: φT16
TA3FFC1 TA3FFC0 TA3FFIE TA3FFIS
R/W
W
1
1
0
0
TMRA3
Flip-Flop
control
110DH
(Prohibit
RMW)
00: Invert TA3FF
01: Set TA3FF
10: Clear TA3FF
11: Don’t care
TA3FF
TA3FF
TA3FFCR
control for inversion
inversion select
register
0: Disable 0: TMRA2
1: Enable 1: TMRA3
92CZ26A-732
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TMP92CZ26A
(14) 8-bit timer (1/2)
Symbol
Name
Address
7
TA4RDE
R/W
6
5
4
3
2
1
0
I2TA45 TA45PRUN TA5RUN TA4RUN
R/W
0
0
0
0
0
TMRA45
RUN
register
Double
IDLE2
TMRA45
prescaler
Up counter Up counter
(UC5) (UC4)
TA45RUN
1110H
buffer
0: Stop
1: Operate
0: Disable
1: Enable
0: Stop and clear
1: Run (Count up)
1112H
(Prohibit
RMW)
−
W
0
8-bit timer
register 4
TA4REG
TA5REG
1113H
(Prohibit
RMW)
−
W
0
8-bit timer
register 5
TA45M1
0
TA45M0
0
PWM41
PWM40 TA5CLK1 TA5CLK0 TA4CLK1 TA4CLK0
R/W
0
0
0
0
0
0
TMRA45
MODE
register
Operation mode
PWM cycle
Source clock for TMRA5 Source clock for TMRA4
TA45MOD
1114H
00: TA4TRG
01: φT1
00: 32KHz clock
01: φT1
00: 8-bit timer mode
01: 16-bit timer mode 01: 26
00: Reserved
10: φT16
10: φT4
10: 8-bit PPG mode
11: 8-bit PWM mode
10: 27
11: 28
11: φT256
11: φT16
TA5FFC1 TA5FFC0 TA5FFIE TA5FFIS
R/W
W
1
1
0
0
TMRA5
Flip-Flop
control
1115H
(Prohibit
RMW)
00: Invert TA5FF
01: Set TA5FF
10: Clear TA5FF
11: Don’t care
TA5FF
TA5FF
TA5FFCR
control for inversion
inversion select
register
0: Disable 0: TMRA4
1: Enable 1: TMRA5
TA6RDE
R/W
I2TA67 TA67PRUN TA7RUN TA6RUN
R/W
0
0
0
0
0
TMRA67
RUN
register
Double
IDLE2
TMRA67
prescaler
Up counter Up counter
(UC7) (UC6)
TA67RUN
1118H
buffer
0: Stop
1: Operate
0: Disable
1: Enable
0: Stop and clear
1: Run (Count up)
111AH
(Prohibit
RMW)
−
W
0
8-bit timer
register 2
TA6REG
TA7REG
111BH
(Prohibit
RMW)
−
W
0
8-bit timer
register 3
TA67M1
0
TA67M0
0
PWM61
PWM60 TA7CLK1 TA7CLK0 TA6CLK1 TA6CLK0
R/W
0
0
0
0
0
0
TMRA67
MODE
register
Operation mode
PWM cycle
Source clock for TMRA7 Source clock for TMRA6
TA67MOD
111CH
00: TA6TRG
01: φT1
00: 32KHz clock
01: φT1
00: 8-bit timer mode
01: 16-bit timer mode 01: 26
00: Reserved
10: φT16
10: φT4
10: 8-bit PPG mode
11: 8-bit PWM mode
10: 27
11: 28
11: φT256
11: φT16
TA7FFC1 TA7FFC0 TA7FFIE TA7FFIS
R/W
W
1
1
0
0
TMRA7
Flip-Flop
control
111DH
(Prohibit
RMW)
00: Invert TA7FF
01: Set TA7FF
10: Clear TA7FF
11: Don’t care
TA7FF
TA7FF
TA7FFCR
control for inversion
inversion select
register
0: Disable 0: TMRA6
1: Enable 1: TMRA7
92CZ26A-733
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TMP92CZ26A
(15) 16-bit timer (1/2)
Symbol
Name
Address
7
TB0RDE
R/W
6
−
R/W
5
4
3
I2TB0
R/W
0
2
TB0PRUN
R/W
1
0
TB0RUN
R/W
0
0
0
0
TMRB0
RUN
register
Always
write “0”.
Double
IDLE2
TMRB0
Up
counter
TB0RUN
1180H
buffer
0: Stop
prescaler
(UC10)
1: Operate
0: disable
1: enable
0: Stop and clear
1: Run (Count up)
−
−
TB0CP0I TB0CPM1 TB0CPM0 TB0CLE TB0CLK1 TB0CLK0
R/W
W*
1
R/W
0
0
0
0
0
0
0
Always write “00”.
Software
capture
control
0: Execute
1: Undefined
Control
Up
counter
0:Clear
Disable
1:Clear
Enable
TMRB1 source clock
00: TB0IN0 input
01: φT1
Capture timing
00: Disable
INT6 occurs at rising
edge
10: φT4
TMRB0
MODE
register
1182H
(Prohibit
RMW)
01: TB0IN0 ↑
11: φT16
TB0MOD
INT6 occurs at rising
edge
10: TB0IN0 ↑ TB0IN0 ↓
INT6 occurs at falling
edge
11:TA1OUT ↑
TA1OUT ↓
INT6 occurs at rising
edge
−
−
TB0CT1 TB0C0T1 TB0E1T1 TB0E0T1 TB0FF0C1 TB0FF0C0
R/W W*
W*
1
1
0
0
0
0
1
1
Always write “11”.
Control TB1FF0
00: Invert
01: Set
10: Clear
11: Don’t care
TB1FF0 inversion trigger
0: Disable trigger
TMRB0
Flip-Flop
control
1183H
(Prohibit
RMW)
TB0FFCR
TB0RG0L
*Always read as “11”.
1: Enable trigger
register
When
When
When UC10 When UC10
capture
UC10 to
capture
UC10 to
matches
with
matches
with
* Always read as “11”.
TB0CP1H/L TB0CP0H/L TB0RG1H/L TB0RG0H/L
16 bit timer
register 0
low
1188H
(Prohibit
RMW)
−
W
0
16 bit timer
TB0RG0H register 0
high
1189H
(Prohibit
RMW)
−
W
0
118AH
(Prohibit
RMW)
−
W
0
16 bit timer
TB0RG1L
register low
16 bit timer
TB0RG1H register 1
high
118BH
(Prohibit
RMW)
−
W
0
Capture
−
TB0CP0L
TB0CP0H
TB0CP1L
TB0CP1H
register 0
low
118CH
118DH
118EH
118FH
R
Undefined
Capture
register 0
high
−
R
Undefined
Capture
register 1
low
−
R
Undefined
Capture
register 1
high
−
R
Undefined
92CZ26A-734
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TMP92CZ26A
(15) 16-bit timer (2/2)
Symbol
Name
Address
7
TB1RDE
R/W
6
−
R/W
5
4
3
I2TB1
R/W
0
2
TB1PRUN
R/W
1
0
TB1RUN
R/W
0
0
0
0
TMRB1
RUN
register
Always
write “0”.
Double
IDLE2
TMRB0
Up
counter
TB1RUN
1190H
buffer
0: Stop
prescaler
(UC12)
0: disable
1: enable
1: Operate
0: Stop and clear
1: Run (Count up)
−
−
TB1CP0I TB1CPM1 TB1CPM0 TB1CLE TB1CLK1 TB1CLK0
R/W
W*
1
R/W
0
0
0
0
0
0
0
Always write “00”.
Software
capture
control
0: Execute
1:
Control
Up
TMRB1 source clock
00: TB1IN0 input
01: φT1
Capture timing
00: Disable
counter
0:Clear
Disable
1:Clear
Enable
INT7 occurs at rising
edge
10: φT4
TMRB1
MODE
register
1192H
(Prohibit
RMW)
01: TB1IN0 ↑
11: φT16
Undefined
TB1MOD
INT7 occurs at rising
edge
10: TB1IN0 ↑ TB1IN0 ↓
INT7 occurs at falling
edge
11:TA3OUT ↑
TA3OUT ↓
INT7 occurs at rising
edge
−
−
TB1CT1 TB1C0T1 TB1E1T1 TB1E0T1 TB1FF0C1 TB1FF0C0
R/W W*
W*
1
1
0
0
0
0
1
1
Always write “11”.
Control TB1FF0
00: Invert
01: Set
10: Clear
11: Don’t care
TB1FF0 inversion trigger
0: Disable trigger
TMRB1
Flip-Flop
control
1193H
(Prohibit
RMW)
TB1FFCR
TB1RG0L
*Always read as “11”.
1: Enable trigger
register
When
When
When UC12 When UC12
capture
UC12 to
capture
UC12 to
matches
with
matches
with
* Always read as “11”.
TB1CP1H/L TB0CP0H/L TB1RG1H/L TB1RG0H/L
16 bit timer
register 0
low
1198H
(Prohibit
RMW)
−
W
0
16 bit timer
TB1RG0H register 0
high
1199H
(Prohibit
RMW)
−
W
0
119AH
(Prohibit
RMW)
−
W
0
16 bit timer
TB1RG1L
register low
16 bit timer
TB1RG1H register 1
high
119BH
(Prohibit
RMW)
−
W
0
Capture
−
TB1CP0L
TB1CP0H
TB1CP1L
TB1CP1H
register 0
low
119CH
119DH
119EH
119FH
R
Undefined
Capture
register 0
high
−
R
Undefined
Capture
register 1
low
−
R
Undefined
Capture
register 1
high
−
R
Undefined
92CZ26A-735
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TMP92CZ26A
(16) UART/Serial channels
Symbol
Name
Address
7
6
5
4
3
2
1
0
Serial
channel 0
buffer
RB7
TB7
RB6
TB6
RB5
TB5
RB4
TB4
RB3
TB3
RB2
TB2
RB1
TB1
RB0
TB0
1200H
(Prohibit
RMW)
SC0BUF
R (Receive) /W (Transmission)
Undefined
register
RB8
R
Undefined
EVEN
0
PE
0
OERR
PERR
FERR
SCLKS
0
IOC
0
R/W
R (Cleared to 0 when read)
0
R/W
0
0
Serial
channel 0
control
1201H
(Prohibit
RMW)
Received Parity
Parity
addition
1: Error
Parity
0: SCLK0↑ 0:baud
SC0CR
data bit8
rate
generator
Overrun
Framing
0: Odd
1: SCLK0↓
register
0: Disable
1: Enable
1: Even
1: SCLK0
pin input
TB8
0
CTSE
0
RXE
WU
0
SM1
SM0
0
SC1
0
SC0
R/W
0
0
0
Serial
channel 0
mode 0
register
Transfer 0: CTS
data bit 8
Receive
Wake up 00: I/O interface Mode 00: TA0TRG
0: Disable 01: 7-bit UART Mode 01: Baud rate generator
0: Receive 1: Enable 10: 8-bit UART Mode 10: Internal clock φ1
SC0MOD0
1202H
disable function
1: CTS
enable disable
11: 9-bit UART Mode 11: External clock
1: Receive
enable
(SCLK0 input)
−
BR0ADDE BR0CK1 BR0CK0
BR0S3
R/W
BR0S2
0
BR0S1
0
BR0S0
0
Serial
channel 0
baud rate
control
0
0
0
0
0
Always
write “0”. division
(16−K) /16 00: φT0
Divided frequency “N” setting
0~F
BR0CR
1203H
01: φT2
10: φT8
11: φT32
register
0: Disable
1: Enable
BR0K3
0
BR0K2
0
BR0K1
0
BR0K0
0
Serial
channel 0
K setting
register
R/W
BR0ADD
1204H
1205H
Sets frequency divisor “K” (1~F)
I2S0
R/W
0
FDPX0
R/W
Serial
channel 0
mode 1
register
0
SC0MOD1
IDLE2
Duplex
0: Stop
1: Run
PLSEL
0: Half
1: Full
RXSEL
TXEN
0
RXEN
0
SIRWD3 SIRWD2 SIRWD1
R/W
SIRWD0
0
0
0
0
0
0
Select
transmit data
pulse
width
Receive
Transmit Receive
Select receive pulse width
IrDA
control
register
SIRCR
1207H
0: Disable 0: Disable Set the valid SIRR×D pulse width for equal or
0:“H” pulse
1: “L” pulse
more than
1: Enable 1: Enable
2x × (setting value + 1) + 100ns
Can be set: 1~14
0: 3/16
1: 1/16
Can not be set: 0, 15
92CZ26A-736
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TMP92CZ26A
(17) SBI
Symbol Name Address
7
6
5
4
3
2
1
0
SCK0
/SWRMON
BC2
BC1
BC0
ACK
−
SCK2
SCK1
R/W
0
R/W
0
R
1
R/W
R/W
0/1
Serial bus
1240H
0
0
0
0
interface
SBICR1
(Prohibit
RMW)
Always
read as “1”.
Number of transfer bits
Acknowledge
mode
Setting for the divisor value “n”
(When writing)
control
register 1
000: 8
011: 3
110: 6
001: 1
100: 4
111: 7
010: 2
101: 5
specification
0: Disable
1: Enable
000: 4
011: 7
110: 10
001: 5
100:8
111: (Reserved)
010: 6
101: 9
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SBI
1241H
buffer
SBIDBR
I2CAR
R (receive)/W (Transmit)
Undefined
(Prohibit
RMW)
register
SA6
0
SA5
0
SA4
0
SA3
SA2
SA1
0
SA0
0
ALS
0
R/W
I2C BUS
1242H
0
0
Address
register
(Prohibit
RMW)
Address
recognition
Slave Address setting
0: Enable
1: Disable
AD0/
SWRST1
R/W
LRB/
SWRST0
R/W
MST
TRX
BB
PIN
AL/SBIM1 AAS/SBIM0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
0
0
Serial bus
interface
status
SBISR
2
I C bus
status
monitor
INTSBI
request
monitor
Arbitration
Slave
General call Last receive
detection
monitor
Master/
Transmitter
When
read
lost detection Address
bit monitor
Slave status / Receiver
monitor
match
register
0: “0”
monitor
0:Slave
1:Master
status
detection
monitor
0: Free
1: Busy
0: Request
1: Cancel
0: −
0: Undetected
1: Detected
monitor
1: “1”
1243H
1: Detected
0: Receiver
0: Undetected
1: Detected
(Prohibit
RMW)
1:
Transmitter
Start/Stop
condition
Serial bus interface
operation mode selection
Software reset generate
write “10” and “01”, then an
internal reset signal is
generated.
Cancel
INTSBI
interrupt
request
Serial bus
interface
control
0: Stop
condition
00: Port mode
01: (Reserved)
10: I2C bus mode
11: (Reserved)
SBICR2
When
write
1: Busy
condition
0:Don’t care
register 2
1:Cancel
interrupt
request
−
W
0
I2SBI
R/W
0
−
−
−
−
−
−
R/W
Serial bus
interface
baud rate
register 0
R
1244H
1
1
1
1
1
0
SBIBR0
SBICR0
(Prohibit
RMW) Always
read “0”
IDLE2
0: Stop
1: Operate
Always read as “1”.
Always
write “0”.
SBIEN
R/W
−
−
−
−
−
−
−
R
Serial bus
interface
control
1247H
0
0
0
0
0
0
0
0
(Prohibit
SBI
Always read as “0”.
RMW)
operation
0:disable
1:enable
register 0
92CZ26A-737
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TMP92CZ26A
1 0
(18) AD converter (1/3)
Symbol
Name
Address
7
6
5
4
3
2
ADR01
ADR00
OVR0
ADR0RF
AD
R
R
R
conversion
result
0
0
0
0
ADREG0L
12A0H
Overrun flag
0:No generate result store flag
1: Generate
AD conversion
Store Lower 2 bits of
AN0 AD conversion
result
register 0 low
1: Stored
ADR09
ADR08
ADR07
0
ADR06
0
ADR05
0
ADR04
0
ADR03
ADR02
AD
conversion
result
R
ADREG0H
ADREG1L
ADREG1H
ADREG2L
ADREG2H
ADREG3L
ADREG3H
ADREG4L
ADREG4H
ADREG5L
ADREG5H
12A1H
12A2H
12A3H
12A4H
12A5H
12A6H
12A7H
12A8H
12A9H
12AAH
12ABH
0
ADR11
0
0
ADR10
0
0
0
register 0 high
Store Upper 8 bits of an AN0 conversion result
OVR1
R
ADR1RF
R
AD
R
conversion
result
0
0
Overrun flag
0:No generate result store flag
1: Generate
AD conversion
Store Lower 2 bits of
AN1 AD conversion
result
register 1 low
1: Stored
ADR19
ADR18
ADR17
0
ADR16
0
ADR15
0
ADR14
0
ADR13
ADR12
AD
conversion
result
R
0
ADR21
0
0
ADR20
0
0
0
register 1 high
Store Upper 8 bits of an AN1 conversion result
OVR2
R
ADR2RF
R
AD
R
conversion
result
0
0
Overrun flag
0:No generate result store flag
1: Generate
AD conversion
Store Lower 2 bits of
AN2 AD conversion
result
register 2 low
1: Stored
ADR29
ADR28
ADR27
0
ADR26
0
ADR25
0
ADR24
0
ADR23
ADR22
AD
conversion
result
R
0
ADR31
0
0
ADR30
0
0
0
register 2 high
Store Upper 8 bits of an AN2 conversion result
OVR3
R
ADR3RF
R
R
AD
conversion
result
0
0
Overrun flag
AD conversion
result store flag
Store Lower 2 bits of
AN3 AD conversion
result
register 3 low
0:No generate
1: Generate
1: Stored
ADR39
ADR38
ADR37
0
ADR36
0
ADR35
0
ADR34
0
ADR33
ADR32
AD
conversion
result
R
0
ADR4
0
0
ADR4
0
0
0
register 3 high
Store Upper 8 bits of an AN3 conversion result
OVR4
R
ADR4F
R
AD
conversion
result
R
0
0
Overrun flag
0:No generate result store flag
1: Generate
AD conversion
Store Lower 2 bits of
AN4 AD conversion
result
register 4
low
1: Stored
ADR49
ADR48
ADR47
0
ADR46
0
ADR45
0
ADR44
0
ADR43
ADR42
AD
conversion
result
R
0
ADR5
0
0
ADR5
0
0
0
register 4high
Store Upper 8 bits of an AN4 conversion result
OVR5
R
ADR5F
R
AD
R
conversion
result
0
0
Overrun flag
0:No generate result store flag
1: Generate
AD conversion
Store Lower 2 bits of
AN5 AD conversion
result
register 5 low
1: Stored
ADR59
ADR58
ADR57
0
ADR56
0
ADR55
0
ADR54
0
ADR53
ADR52
AD
conversion
result
R
0
0
0
0
register 5 high
Store Upper 8 bits of an AN5 conversion result
92CZ26A-738
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TMP92CZ26A
1 0
(18) AD converter (2/3)
Symbol
Name
Address
7
6
5
4
3
2
ADRSP1 ADRSP0
OVSRP ADRSPRF
High priority
Conversion
Register SP
low
R
R
R
ADREGSPL
12B0H
0
0
0
0
Overrun
1: Generate
AD conversion
result store flag
1: Stored
Store Lower 2 bits of an
AD conversion result
ADRSP9 ADRSP8 ADRSP7 ADRSP6 ADRSP5 ADRSP4 ADRSP3 ADRSP2
R
High priority
Conversion
Register SP
high
ADREGSPH
12B1H
12B4H
0
ADR21
0
0
ADR20
0
0
0
0
0
0
0
Store Upper 8 bits of an AD conversion result
AD
Conversion
Result
R/W
ADCM0REGL
Compare
Criterion
Register 0
Low
Store Lower 2 bits of an
AD conversion result
compare criterion
AD
ADR29
ADR28
ADR27
0
ADR26
0
ADR25
0
ADR24
0
ADR23
0
ADR22
0
Conversion
Result
R/W
0
0
ADCM0REGH
12B5H
12B6H
Compare
Criterion
Register 0
High
Store Upper 8 bits of an AD conversion result compare criterion
ADR20
AD
ADR21
0
Conversion
Result
R/W
0
Compare
Criterion
Register 1
Low
ADCM1REGL
Store Lower 2 bits of an
AD conversion result
compare criterion
ADR29
0
ADR28
0
ADR27
0
ADR26
0
ADR25
0
ADR24
0
ADR23
0
ADR22
0
AD
R/W
Conversion
Result
Compare
Criterion
Register 1
High
ADCM1REGH
12B7H
Store Upper 8 bits of an AD conversion result compare criterion
−
R/W
0
ADCLK2 ADCLK1 ADCLK0
R/W
0
R/W
0
R/W
0
AD
Conversion
Clock
Always
write “0”
Select clock for AD conversion
000 : Reserved 100 : fIO/4
ADCCLK
12BFH
Setting
Register
001 : fIO/1
010 : fIO/2
011 : fIO/3
101 : fIO/5
110 : fIO/6
111 : fIO/7
92CZ26A-739
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TMP92CZ26A
1 0
(18) AD converter (3/3)
Symbol
Name
Address
7
EOS
6
BUSY
5
4
I2AD
3
ADS
2
HTRGE
R/W
0
TSEL1
TSEL0
R
0
0
0
0
0
0
Normal AD
conversion
end flag
Normal AD
conversion
BUSY Flag
AD conversion Start Normal Normal AD
when AD conversion conversion at
IDLE2 mode 0: Don’t Care Hard ware
1:Start trigger
Select Hard ware trigger
AD mode
control
00: INTTB00 interrupt
01: Reserved
ADMOD0
12B8H
0:During
register 0
conversion 0:Stop
0: Stop
1: Operate
AD conversion 0: Disable
1: Enable
Always read
as”0”.
10:
ADTRG
11: Reserved
sequence
or before
conversion
1:During
conversion
starting
1:Complete
conversion
sequence
DACON
ADCH2
0
ADCH1
0
ADCH0
0
LAT
0
ITM
0
REPEAT
0
SCAN
0
R/W
0
AD mode
control
register 1
DAC and VREFAnalog input channel select
application
control
Latency
Interrupt
specification
when
Repeat mode Scan mode
0: No Wait
1:Start after
reading
conversion channel fixed 1: Repeat
result store repeat mode
Register of
specification
specification
0: Channel
fixed mode
1: Channel
conversion scan mode
ADMOD1
12B9H
0: Single
conversion
conversion
last channel
HEOS
HBUSY
0
HADS
HHTRGE HTSEL1
R/W
HTSEL0
0
R
0
0
0
0
High-priority
AD conversion conversion
sequence
FLAG
0: During
conversion
sequence
or before
starting
High-priority AD
Start
High-priority
AD conversion at Hard ware 01: Reserved
0: Don’t Care trigger 10:
High-priority
AD conversion 00: INTTB10 interrupt
Select Hard ware trigger
AD mode
control
BUSY Flag
ADMOD2
12BAH
ADTRG
11: I2S Sampling Counter
Output
0:Stop
1: Start AD
0: Disable
register 2
conversion
1:During
conversion
conversion 1: Enable
Always read
as”0”.
1: Complete
conversion
sequence
−
HADCH2 HADCH1 HADCH0
R/W
−
R/W
AD mode
control
register 3
ADMOD3
12BBH
0
0
0
0
Always
High-priority analog input channel
select
Always
write “0”.
write “0”.
CMEN1
CMEN0
CMP1C
CMP0C
IRQEN1
0
IRQEN0 CMPINT1 CMPINT0
R/W
0
0
0
0
0
0
0
AD Monitor
function1
AD Monitor
function0
Generation
condition of
AD monitor
function
Generation
condition of
AD monitor
function
AD monitor
function
AD monitor
function
Status of AD Status of AD
AD mode
control
register 4
monitor
monitor
ADMOD4
12BCH
interrupt 1
interrupt 0
function
interrupt 1
function
interrupt 0
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
0: Disable
interrupt 1
interrupt 0
0: No
0: No
1: Enable
(Note)
1: Enable
(Note)
0: less than
0: less than
generation
generation
1: Greater than 1: Greater than
or Equal or Equal
1: Generation 1: Generation
CMCH2
0
CM1CH1 CM1CH0
R/W
CM0CH2 CM0CH1 CM0CH0
R/W
0
0
0
0
0
AD mode
control
register 5
ADMOD5
12BDH
Select analog channel for AD monitor function 1
Select analog channel for AD monitor function
1
000: AIN0
001: AIN1
010: AIN2
011: AN3
100: AN4
101: AN5
110: Reserved
111: Reserved
000: AIN0
001: AIN1
010: AIN2
011: AN3
100: AN4
101: AN5
110: Reserved
111: Reserved
92CZ26A-740
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TMP92CZ26A
(19) Watchdog timer
Symbol Name
Address
7
6
WDTP1
R/W
0
5
4
3
2
1
0
−
WDTE
WDTP0
I2WDT
RESCR
R/W
0
1
0
0
0
WDT
mode
WDT
control
Select detecting time
1:Internally
connects
Always
write “0”.
WDMOD
WDCR
1300H
IDLE2
00: 215/f
register
IO
0: Stop
1: Enable 01: 217/f
10: 219/f
WDT out to
the reset pin
IO
IO
IO
1: Operate
11: 221/f
−
W
−
WDT
control
register
1301H
(Prohibit
RMW)
B1H: WDT disable code
4E: WDT clear code
92CZ26A-741
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TMP92CZ26A
(20) RTC (Real-Time Clock)
Symbol Name
Address
7
6
SE6
5
SE5
4
SE4
3
SE3
2
SE2
1
SE1
0
SE0
Second
SECR
R/W
1320H
register
Undefined
8 sec.
MI3
“0” is read 40 sec.
MI6
20 sec.
MI5
10 sec.
MI4
4 sec.
MI2
2 sec.
MI1
1 sec.
MI0
Minute
MINR
R/W
1321H
1322H
1323H
register
Undefined
8 min.
HO3
“0” is read 40 min.
20 min.
HO5
10 min.
HO4
4 min.
HO2
2 min.
HO1
1 min.
HO0
R/W
Undefined
Hour
HOURR
register
20 hours
(PM/AM)
“0” is read
10 hours
8 hours 4 hours
2 hours
1 hour
WE0
WE2
WE1
R/W
Day
DAYR
register
Undefined
W1
“0” is read
DA5
W2
W0
DA4
DA3
DA2
DA1
DA0
Date
DATER
R/W
Undefined
1324H
1325H
register
“0” is read
20 days
10 days
MO4
8 days
MO3
4 days
MO2
2 days
MO1
1 day
MO0
R/W
Undefined
4 month
PAGE0
PAGE1
“0” is read
10 month 8 month
“0” is read
2 month
1 month
0: Indicator
for 12
Month
MONTHR
register
hours
1: Indicator
for 24
hours
YE7
YE6
YE5
YE4
YE3
YE2
YE1
YE0
1326H
R/W
Undefined
PAGE0 80 years 40 years 20 years 10 years 8 years
4 years
2 years
1 year
Year
YEARR
PAGE1
“0” is read
Leap year setting
00: Leap year
register
01: One year after
10: Two years after
11: Three years after
INTENA
R/W
0
ADJUST ENATMR ENAALM
PAGE
R/W
Undefined
W
R/W
Page
register
1327H
(Prohibit
RMW)
Undefined
Undefined
PAGER
RESTR
TIMER
ALARM
1: Enable
0: Disable
RE2
Interrupt
“0” is read
1: Adjust
1: Enable
0: Disable
RE3
“0” is
read.
PAGE
1: Enable
0: Disable
selection
DIS1HZ DIS16HZ RSTTMR RSTALM
RE1
RE0
W
Reset
register
1328H
(Prohibit
RMW)
Undefined
1: Alarm
reset
1:Clock
reset
0: 1 Hz
0: 16 Hz
Always write “0”
92CZ26A-742
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TMP92CZ26A
(21) Melody/alarm generator
Symbol
Name
Address
7
6
5
4
3
2
1
0
AL8
AL7
AL6
AL5
AL4
AL3
AL2
AL1
Alarm-
pattern
register
R/W
ALM
1330H
0
0
0
0
0
0
0
0
Alarm pattern setting
FC1
0
Free run counter
control
00: Hold
01: Restart
10: Clear
FC0
0
ALMINV
−
−
−
−
MELALM
R/W
0
0
0
0
0
0
Melody/
alarm
control
register
Alarm
frequency
invert
Output
MELALMC
1331H
1332H
frequency
0: Alarm
1: Melody
Always write “0”.
1: Invert
11: Clear and start
ML7
ML6
ML5
0
ML4
0
ML3
0
ML2
0
ML1
ML0
Melody
frequency
L-register
R/W
MELFL
0
0
0
0
Melody frequency set (Low 8bit)
MELON
R/W
0
ML11
0
ML10
ML9
ML8
R/W
0
0
0
Melody
counter
control
0: Stop
and
Melody
frequency
H-register
MELFH
1333H
Melody frequency set (Upper 4 bits)
clear
1: Start
−
IALM4E
0
IALM3E
IALM2E
0
IALM1E
0
IALM0E
0
R/W
Alarm
interrupt
enable
register
0
0
ALMINT
1334H
1:INTALM4 1:INTALM3 1:INTALM2 1:INTALM1 1:INTALM0
Always
write “0”.
(1Hz)
(2Hz)
(64Hz)
enable
(512Hz)
enable
(8192Hz)
enable
enable
enable
92CZ26A-743
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TMP92CZ26A
(22) I2S (1/2)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Symbol
Name
Address
B015
B014 B013 B012 B011 B010
B009 B008 B007 B006
B005 B004 B003 B002 B001 B000
W
Undefined
I2S
Transmission buffer register (FIFO)
1800H
Transmission
Buffer
I2S0BUF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
(Prohibit
RMW)
B031
B030
B09
B028 B027 B026
B025 B024 B023 B022
B021 B020 B019 B018 B017 B016
Register0
W
Undefined
Transmission buffer register (FIFO)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
B115 B114
B113 B112 B111 B110
B109 B108 B107 B106
B105 B104 B103 B102 B101 B100
W
Undefined
I2S
1810H
Transmission
Buffer
Transmission buffer register (FIFO)
I2S1BUF
(Prohibit
RMW)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Register1
B131 B130 B129 B128 B127 B126
B125 B124 B123 B122
B121 B120 B119 B118 B117 B116
W
Undefined
Transmission buffer register (FIFO)
92CZ26A-744
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TMP92CZ26A
(22) I2S (2/2)
Symbol
Name
Address
1808H
7
TXE0
R/W
0
6
*CNTE0
R/W
0
5
4
DIR0
R/W
0
3
BIT0
R/W
0
2
1
0
DTFMT01 DTFMT00 SYSCKE0
R/W
0
R/W
0
R/W
0
Transmit Counter
Transmis Bit length Output format
sion start
BIT
System
clock
control
0: Clear
1: Start
0: Stop
1: Start
00: I2S
10: Right
0:Disable
1:Enable
0: 8 bits
1:16 bits
0:MSB
1:LSB
01: Left
11:Reserved
I2S
I2S0CTL
Control
Register0
CLKS0
R/W
0
FSEL0
R/W
TEMP0
WLVL0
R/W
0
EDGE0
R/W
0
CLKE0
R/W
R
1
0
0
Source
clock
Stereo
Condition of WS level Clock
Clock
1809H
transmission
edge for enable
/monaural
0: Stereo
1: Monaural
FIFO
data
output
0: fSYS
1: fPLL
(After trans-
mission)
0:Operate
1:Stop
0:low left
1:high left
0: data
0:Rising
1:Falling
1: None
data
CK07
0
CK06
0
CK05
0
CK04
CK03
CK02
0
CK01
CK00
R/W
180AH
180BH
I2S0
Divider
Value
Setting
Register
0
0
0
WS01
0
0
WS00
0
Divider value for CK signal (8-bit counter)
I2S0C
WS05
WS04
WS03
WS02
R/W
0
0
0
0
Divider value for WS signal (6-bit counter)
TXE1
R/W
0
*CNTE1
R/W
0
DIR1
R/W
0
BIT1
R/W
0
DTFMT11 DTFMT10 SYSCKE1
R/W
0
R/W
0
R/W
0
Transmit Counter
Transmis Bit length Output format
System
clock
10:
1818H
control
0: Clear
1: Start
sion start
BIT
0: Stop
1: Start
00: I2S
Right
0:Disable
0: 8 bits
1:16 bits
0:MSB
1:LSB
01: Left
1:Enable
11:Reserved
I2S
I2S1CTL
Control
Register1
CLKS1
R/W
0
FSEL1
R/W
TEMP1
WLVL1
R/W
0
EDGE1
R/W
0
CLKE1
R/W
R
1
0
0
Source
clock
Stereo
Condition of WS level Clock
Clock
1819H
transmission
edge for enable
/monaural
0: Stereo
1: Monaural
FIFO
data
output
0: fSYS
1: fPLL
(After trans-
mission)
0:Operate
1:Stop
0:low left
1:high left
0: data
0:Rising
1:Falling
1: None
data
CK17
0
CK16
0
CK15
0
CK14
CK13
CK12
0
CK11
CK10
R/W
181AH
181BH
I2S1
Divider
Value
Setting
Register
0
0
0
WS11
0
0
WS10
0
Set divide frequency for CK signal (8-bit counter)
I2S1C
WS15
WS14
WS13
WS12
R/W
0
0
0
0
Set divided frequency for WS signal (6-bit counter)
92CZ26A-745
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TMP92CZ26A
(23) MAC (1/2)
Symbol
Name Address
7
6
5
4
3
2
1
0
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
Data
register
Multiplier
A-LL
R/W
MACMA_LL
MACMA_LH
MACMA_HL
MACMA_HH
MACMB_LL
MACMB_LH
MACMB_HL
MACMB_HH
MACOR_LLL
MACOR_LLH
1BE0H
1BE1H
1BE2H
1BE3H
1BE4H
1BE5H
1BE6H
1BE7H
1BE8H
1BE9H
Undefined
Multiplier A data register [7:0]
MA15
MA23
MA31
MB7
MA14
MA22
MA30
MB6
MA13
MA12
MA11
MA10
MA9
MA8
MA16
MA24
MB0
Data
register
Multiplier
A-LH
R/W
Undefined
Multiplier A data register [15:8]
MA21
MA20
MA19
MA18
MA17
MA25
MB1
Data
register
Multiplier
A-HL
R/W
Undefined
Multiplier A data register [23:16]
MA29 MA28 MA27 MA26
Data
register
Multiplier
A-HH
R/W
Undefined
Multiplier A data register [31:24]
MB4 MB3
MB5
MB2
Data
register
Multiplier
B-LL
R/W
Undefined
Multiplier B data register [7:0]
MB15
MB14
MB13
MB12
MB11
MB10
MB9
MB8
Data
register
Multiplier
B-LH
R/W
Undefined
Multiplier B data register [15:8]
MB23
MB31
OR7
MB22
MB30
OR6
MB21
MB20
MB19
MB18
MB17
MB25
OR1
MB16
MB24
OR0
Data
register
Multiplier
B-HL
R/W
Undefined
Multiplier B data register [23:16]
MB29 MB28 MB27 MB26
Data
register
Multiplier
B-HH
R/W
Undefined
Multiplier B data register [31:24]
OR5 OR4 OR3 OR2
Data register
Multiply and
Accumulate
-LLL
R/W
Undefined
Multiply and Accumulate data register [7:0]
OR13 OR12 OR11 OR10
OR15
OR14
OR9
OR8
Data register
Multiply and
Accumulate
-LLH
R/W
Undefined
Multiply and Accumulate data register [15:8]
OR21 OR20 OR19 OR18
OR23
OR31
OR22
OR30
OR17
OR25
OR16
OR24
Data register
Multiply and
Accumulate
-LGL
R/W
Undefined
Multiply and Accumulate data register [23:16]
OR29 OR28 OR27 OR26
MACOR_LHL
MACOR_LHH
1BEAH
1BEBH
Data register
Multiply and
Accumulate
-LHH
R/W
Undefined
Multiply and Accumulate data register [31:24]
92CZ26A-746
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TMP92CZ26A
(23) MAC (2/2)
Symbol
Name Address
7
6
5
4
3
2
1
0
OR39
OR38
OR37
OR36
OR35
OR34
OR33
OR32
Data register
Multiply and
Accumulate
-HLL
R/W
Undefined
Multiply and Accumulate data register [39:32]
OR45 OR44 OR43 OR42
MACOR_HLL
1BECH
OR47
OR46
OR41
OR40
Data register
Multiply and
Accumulate
-HLH
R/W
Undefined
Multiply and Accumulate data register [47:40]
OR53 OR52 OR51 OR50
MACOR_HLH
1BEDH
OR55
OR63
OR54
OR62
OR49
OR57
OR48
OR56
Data register
Multiply and
Accumulate
-HHL
R/W
Undefined
Multiply and Accumulate data register [55:48]
OR61 OR60 OR59 OR58
MACOR_HHL
MACOR_HHH
1BEEH
1BEFH
Data register
Multiply and
Accumulate
-HHH
R/W
Undefined
Multiply and Accumulate data register [63:56]
MSTTG2 MSTTG1 MSTTG0 MSGMD MOPMD1 MOPMD0
MOVF
R/W
MOPST
W
0
R/W
0
R/W
0
R/W
0
0
0
0
0
Over flow
flag
Start
Select the trigger of start calculation
000: Write to MACMA[7:0]
Sign
mode
Calculation
Mode
MAC
Control
Register
calculation
control
MACCR
1BFCH
0:no
001: Write to MACMB[7:0]
0:Unsigned 00: 64 + 32 × 32
0:don’t care
1: Start
over flow
1:generate
over flow
010: Write to MACMOR[7:0]
011: Write to MACMOR[39:32]
1xx: Write “1” to <MOPST>
1:Signed
01: 64 − 32 × 32
10: 32 × 32 − 64
11: Reserved
calculation
92CZ26A-747
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TMP92CZ26A
6. Package
P-FBGA228-1515-0.80A5
TOP VIEW
BOTTOM VIEW
92CZ26A-748
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