Toshiba Camcorder MK6017MAP User Manual

TOSHIBA

Storage Device Division

MK6017MAP

(HDD2155)

HARD DISK DRIVE

PRODUCT SPECIFICATION

Rev 00

October 2000

DOCUMENT NUMBER

14603

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360014937

No.5T03670-2D

ＴＯＳＨＩＢＡ

2.5 inch Disk Drives MK6017MAP Product Specification

ＴＩＴＬＥ：

REV

No.

日付

DATE

記

事

部門

DEP.

担当

REVISED

A.Iwata

承認

APP’D

保管日

STGE.PER.

CONTENTS

Initial issue

D-SETSU2

M.Hattori

2000-10-06

No.

３６００１４９３７

ＴＯＳＨＩＢＡＣＯＲＰＯＲＡＴＩＯＮ

CONT.ON 503

PAGE No. 502

- 502 -

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360014937

ＳＡＦＥＴＹ

The hard disk drive and product specifications contain essential information for the protection

of users and others from possible injury and property damage and to ensure correct handling.

Please check that you fully understand the definition of the following messages (signs and

graphical symbols) before going on to read the text, and always follow the instructions.

Please describe requirements in the instruction manual of the product in which the drive is

mounted and ensure that users are made thoroughly aware of them.

IMPORTANT MESSAGES

Read this manual and follow its instructions. Signal words such as CAUTION and

NOTE, will be followed by important safety information that must be carefully reviewed.

Indicates a potentially hazardous situation which if not avoided, may

result in minor injury or property damage.

Gives you helpful information.

NOTE

LIMITATION OF LIABILITY

・Toshiba Corporation shall not be liable for any damage due to the fault or negligence

of users, fire, earthquake, or other accident beyond the control of Toshiba

Corporation.

・Toshiba Corporation shall not be liable for any incidental or consequential damages

including but not limited to change or loss of stored data, loss of profit, or

interruption of business, which are caused by use or non-usability of the product.

・Toshiba Corporation shall not be liable for any damage result from failure to comply

with the contents in the product specification.

・Toshiba Corporation shall not be liable for any damage based on use of the product

in combination with connection devices, software, or other devices provided by

Toshiba Corporation with the product.

- 503 -

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USAGE RESTRICTIONS

● Since the drive is not designed or manufactured to be used for a system including

equipment (*1) directly linked with human life, etc., Toshiba Corporation shall not

be liable for this type of use.

*1: Equipment directly linked with human life, etc. corresponds to the

following.

－Medical equipment such as life support systems, equipment used in

operations，etc.

● When the drive is to be used for a system including equipment (*2) linked with

human safety or having a serious influence on the safe maintenance of public

function, etc., special consideration (*3) must be given with regard to operation,

maintenance, and management of the system.

*2: A system including equipment linked with human safety or having a

serious influence on the safe maintenance of public function, etc.

corresponds to the following.

－A main equipment control system used in atomic power plants, a safety

protection based system used in atomic facilities, other important

safety lines and systems.

－An operation control system for mass transport, an air-traffic control

system.

*3: Special consideration means that a safety system (fool proof design, fail

safe design, redundancy design, etc.) is established as a result of

adequate consultation with Toshiba engineers.

- 504 -

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360014937

SAFETY

■ Do not disassemble, remodel or repair.

Disassembly, remodeling or repair may cause injury, failure, or data loss.

■ Do not drop.

Dropping may cause injury.

■ Do not touch sharp edges or pins of the drive.

Sharp protrusions etc. may cause injury.

Hold the drive by both sides when carrying it.

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360014937

SAFETY

Observe the following to prevent failure, malfunction or data loss.

NOTE

●Follow the specifications for 6. POWER SUPPLY (page516), 8. ENVIRONMENT (page 522,

523), etc. when using.

Failure to do so may cause damage to the drive.

●Observe cautions in 7.4 MOUNTING INSTRUCTION (page517) and 9.6 LOAD / UNLOAD

(page525 ) when handling, setting up, or using the drive.

●Take anti-static measures in order to avoid damage to the drive when handling it.

The drive uses parts susceptible to damage due to ESD (electrostatic discharge).

Wear ESD proof wrist strap in accordance with the usage specified when handling a drive that is not in an

anti-static protection bag.

●There is a certain probability of the drive causing failure including data error or data loss.

Take preventive steps such as backing up data etc. without exception in order to prevent loss etc. in cases

where data loss may result in loss or damage.

Please include this in the instruction manual etc. of the system in which this device is used and ensure that users

are made thoroughly aware of it.

●Inserting or pulling out the drive when the power is turned on may cause damage to the

drive.

Exchange the drive etc. after the power of HDD is turned off.

●Extreme shock to the drive may cause damage to it, data corruption, etc..

Do not subject the drive to extreme shock such as dropping, upsetting or crashing against other objects.

●Do not touch the top cover since application of force to it may cause damage to the drive.

●Do not stack the drive on another drive or on other parts etc. or stack them on top of it during

storage or transportation.

Shock or weight may cause parts distortion etc..

●Labels and the like attached to the drive are also used as a seal for maintenance of its

performance.

Do not remove them from the drive.

●Attachment of dielectric materials such as metal powder, liquid, etc. to live parts such as

printed circuit board patterns or pins etc. may cause damage to the drive.

Avoid attachment of these materials.

●Do not place objects which generate magnetic fields such as magnets, speakers, etc. near

the drive.

Magnetism may cause damage to the drive or data loss.

- 506 -

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360014937

TABLE OF CONTENTS

1. SCOPE ......................................................................................................................................................................... 511

2. GENERAL DESCRIPTION....................................................................................................................................... 511

3. KEY FEATURES........................................................................................................................................................ 513

4. BASIC SPECIFICATION .......................................................................................................................................... 514

5. PERFORMANCE ....................................................................................................................................................... 515

6. POWER REQUIREMENTS ...................................................................................................................................... 516

6.1

6.1.1

6.1.2

6.2

6.3

6.4

SUPPLY VOLTAGE .................................................................................................................................................. 516

Supply for Logic ............................................................................................................................................ 516

Supply for Motor ........................................................................................................................................... 516

POWER CONSUMPTION ........................................................................................................................................... 516

ENERGY CONSUMPTION EFFICIENCY...................................................................................................................... 516

POWER SEQUENCE ................................................................................................................................................. 516

7. MECHANICAL SPECIFICATIONS ........................................................................................................................ 517

7.1

7.2

7.3

7.4

7.4.1

7.4.2

DIMENSION............................................................................................................................................................. 517

WEIGHT.................................................................................................................................................................. 517

DRIVE ORIENTATION .............................................................................................................................................. 517

MOUNTING INSTRUCTIONS ..................................................................................................................................... 517

Screwing........................................................................................................................................................ 518

Installation .................................................................................................................................................... 518

8. ENVIRONMENTAL LIMITS ................................................................................................................................... 522

8.1

8.1.1

8.1.2

8.2

8.3

8.4

8.5

TEMPERATURE AND HUMIDITY .............................................................................................................................. 522

Temperature .................................................................................................................................................. 522

Humidity........................................................................................................................................................ 522

VIBRATION ............................................................................................................................................................. 522

SHOCK.................................................................................................................................................................... 522

ALTITUDE............................................................................................................................................................... 523

ACOUSTICS（SOUND POWER）............................................................................................................................. 523

8.6

8.7

SAFETY STANDARDS .............................................................................................................................................. 523

EMC ADAPTABILITY.............................................................................................................................................. 523

9. RELIABILITY ............................................................................................................................................................ 524

9.1

9.1.1

9.1.2

9.2

9.3

9.4

9.5

9.6

ERROR RATE .......................................................................................................................................................... 524

Non- Recoverable Error Rate........................................................................................................................ 524

Seek Error Rate ............................................................................................................................................. 524

MEAN TIME TO FAILURE (MTTF) .......................................................................................................................... 524

PRODUCT LIFE........................................................................................................................................................ 524

REPAIR ................................................................................................................................................................... 524

PREVENTIVE MAINTENANCE (PM)......................................................................................................................... 524

LOAD/UNLOAD....................................................................................................................................................... 525

10.

HOST INTERFACE ............................................................................................................................................... 526

10.1

CABLING ............................................................................................................................................................ 526

10.1.1

10.1.2

10.2

10.2.1

10.2.2

10.3

10.3.1

10.3.2

10.3.3

10.3.4

Interface Connector................................................................................................................................... 526

Cable ......................................................................................................................................................... 526

ELECTRICAL SPECIFICATION ............................................................................................................................... 527

Cable length and capacitance ................................................................................................................... 527

DC input/output Characteristics................................................................................................................ 527

INTERFACE CONNECTOR..................................................................................................................................... 528

ATA interface connector............................................................................................................................ 528

Pin Assignment.......................................................................................................................................... 529

Signal Treatment ....................................................................................................................................... 530

Series resistance ........................................................................................................................................ 531

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10.3.5

10.4

Signal Description .....................................................................................................................................531

HOST INTERFACE TIMING ...................................................................................................................................533

Program I/O Write Timing.........................................................................................................................533

Program I/O Read Timing .........................................................................................................................534

Single Word DMA Write Timing ................................................................................................................535

Single Word DMA Read Timing.................................................................................................................536

Multiword DMA Write Timing ...................................................................................................................537

Multiword DMA Read Timing....................................................................................................................538

Ultra DMA Timing.....................................................................................................................................539

Reset Timing...............................................................................................................................................548

GROUNDING........................................................................................................................................................548

ADDRESS DECODING ..........................................................................................................................................549

REGISTER DESCRIPTION......................................................................................................................................550

Data Register .............................................................................................................................................550

Error Register ............................................................................................................................................551

Features Register (Write Precompensation Register)................................................................................552

Sector Count Register ................................................................................................................................552

Sector Number Register .............................................................................................................................553

Cylinder Low Registers..............................................................................................................................553

Cylinder High Registers.............................................................................................................................553

Device/Head Register ................................................................................................................................554

Status Register ...........................................................................................................................................555

Command Register.....................................................................................................................................556

Alternate Status Register............................................................................................................................558

Device Control Register.............................................................................................................................558

Device Address register .............................................................................................................................558

COMMAND DESCRIPTIONS ..................................................................................................................................559

Nop (00h) ................................................................................................................................................560

Recalibrate (1xh).....................................................................................................................................560

Flush Cache (E7h) ..................................................................................................................................560

Read Sector (20h/21h) ............................................................................................................................561

Read Long (22h/23h) ..............................................................................................................................561

Write Sector (30h/31h)............................................................................................................................561

Write Long (32h/33h)..............................................................................................................................562

Read Verify (40h)....................................................................................................................................562

Write Verify (3Ch)...................................................................................................................................562

10.4.1

10.4.2

10.4.3

10.4.4

10.4.5

10.4.6

10.4.7

10.4.8

10.5

10.6

10.7

10.7.1

10.7.2

10.7.3

10.7.4

10.7.5

10.7.6

10.7.7

10.7.8

10.7.9

10.7.10

10.7.11

10.7.12

10.7.13

10.8

10.8.1

10.8.2

10.8.3

10.8.4

10.8.5

10.8.6

10.8.7

10.8.8

10.8.9

10.8.10

10.8.11

10.8.12

10.8.13

10.8.14

10.8.15

10.8.16

10.8.17

10.8.18

10.8.19

10.8.20

10.8.21

10.8.22

10.8.23

10.8.24

10.8.25

10.8.26

10.8.27

10.8.28

10.8.29

10.8.30

10.8.31

10.8.32

10.8.33

Format Track

(50h)...............................................................................................................................563

Seek (7xh)................................................................................................................................................564

Toshiba Specific.........................................................................................................................................564

Execute Diagnostics (90h) ......................................................................................................................564

Initialize Device Parameters (91h) .........................................................................................................565

Read Multiple (C4h)................................................................................................................................566

Write Multiple (C5h)...............................................................................................................................567

Set Multiple Mode (C6h).........................................................................................................................568

Read DMA (C8h/C9h).............................................................................................................................568

Write DMA (CAh/CBh) ...........................................................................................................................569

Power Control (Exh)...............................................................................................................................570

Read Buffer (E4h) ...................................................................................................................................572

Write Buffer (E8h)...................................................................................................................................572

Identify Device (ECh)..............................................................................................................................573

Set Max Address (F9h)............................................................................................................................586

Read Native Max Address

(F8h)...........................................................................................................586

Set Features (EFh)..................................................................................................................................587

SECURITY SET PASSWORD (F1h) .......................................................................................................588

SECURITY UNLOCK (F2h)....................................................................................................................589

SECURITY ERASE PREPARE (F3h)......................................................................................................589

SECURITY ERASE UNIT (F4h)..............................................................................................................590

SECURITY FREEZE LOCK (F5h)..........................................................................................................590

SECURITY DISABLE PASSWORD (F6h) ..............................................................................................591

SMART Function Set..................................................................................................................................592

10.9

SECURITY MODE FEATURE SET ..............................................................................................................................609

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10.9.1

10.9.2

10.9.3

10.9.4

10.9.5

Security mode default setting..................................................................................................................... 609

Initial setting of the user password............................................................................................................ 609

Security mode operation from power-on................................................................................................... 610

Password lost............................................................................................................................................. 611

Command Table ........................................................................................................................................ 612

SELF-MONITORING, ANALYSIS AND REPORTING TECHNOLOGY ......................................................................... 613

Attributes ................................................................................................................................................... 613

Attributes values........................................................................................................................................ 613

SMART function default setting................................................................................................................. 613

ADAPTIVE POWER MODE CONTROL ................................................................................................................... 614

Performance Idle....................................................................................................................................... 614

Active Idle.................................................................................................................................................. 614

Low Power Idle.......................................................................................................................................... 614

Transition time........................................................................................................................................... 614

RESET................................................................................................................................................................. 615

MASTER/SLAVE CONFIGURATION....................................................................................................................... 616

CACHE MEMORY................................................................................................................................................ 617

Cache Operations...................................................................................................................................... 617

Notes for write cache................................................................................................................................. 617

AUTOMATIC WRITE REALLOCATION .................................................................................................................. 617

10.10

10.10.1

10.10.2

10.10.3

10.11

10.11.1

10.11.2

10.11.3

10.11.4

10.12

10.13

10.14

10.14.1

10.14.2

10.15

11.

PROTOCOL............................................................................................................................................................ 618

11.1

11.2

11.3

11.4

11.5

11.6

PIO DATA IN COMMANDS ................................................................................................................................... 619

PIO DATA OUT COMMANDS................................................................................................................................ 620

NON-DATA COMMANDS...................................................................................................................................... 621

DMA DATA TRANSFER COMMANDS ................................................................................................................... 622

ULTRA DMA...................................................................................................................................................... 623

OTHER TIMINGS.................................................................................................................................................. 626

- 509 -

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Table of Figures

FIGURE 1

FIGURE 2

MK6017MAP DIMENSIONS.............................................................................................................................519

MOUNTING RECOMMENDATION......................................................................................................................521

FIGURE 3 ATA INTERFACE CONNECTOR..............................................................................................................................528

FIGURE 4

FIGURE 5

PASSWORD SET SECURITY MODE POWER-ON FLOW .......................................................................................610

USER PASSWORD LOST.....................................................................................................................................611

FIGURE 6 OPTIONAL JUMPER FOR MASTER/SLAVE ..............................................................................................................616

TABLE 7.4-1 DIMENSIONS ......................................................................................................................................................520

TABLE 10.3-1 SIGNAL PIN ASSIGNMENT...............................................................................................................................529

TABLE 10.3-2 SIGNAL TREATMENT......................................................................................................................................530

TABLE 10.6-1 REGISTER MAP ..............................................................................................................................................549

TABLE 10.6-2 DECODE LOGIC .............................................................................................................................................549

TABLE 10.7-1 DIAGNOSTIC MODE ERROR REGISTER ...............................................................................................................552

TABLE 10.7-2 COMMAND CODE ..........................................................................................................................................557

TABLE 10.8-1 IDENTIFY INFORMATION...................................................................................................................................574

TABLE 10.8-2 IDENTIFY INFORMATION (CONTINUED) ............................................................................................................575

TABLE 10.8-3 IDENTIFY INFORMATION (CONTINUED) ............................................................................................................576

TABLE 10.8-4 IDENTIFY INFORMATION (CONTINUED) ............................................................................................................577

TABLE 10.9-1 SECURITY MODE COMMAND ACTIONS.............................................................................................................612

TABLE 10.12-1 INITIALIZATION OF TASK FILE REGISTERS.......................................................................................................615

TABLE 11.6-1 OTHER TIMINGS. ..............................................................................................................................................626

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360014937

1. SCOPE

This document describes the specifications of the following model, MK6017MAP of 2.5- inch type

Winchester disk drives.

Factory Number

Sales Number

HDD2155

MK6017MAP

2. GENERAL DESCRIPTION

The MK6017MAP which is noted hereinafter as^‘‘MK6017MAP^’’or as‘‘ the drive ’’comprises

a series of intelligent disk drives .

The drive features an ATA-2 / 3 / 4 /5 interface embedded controller that requires a simplified adapter board

for interfacing to an AT or AT compatible bus. The drives employ Winchester technology and a closed loop

servo control system which have made high recording density of 34.6 M bit/mm (22.35G bit/in )and average

access time of 13 msec with highest reliability of 300,000 hours for MTTF (Mean Time to Failure) possible.

The drive is distinctive for its small and light body with 9.5mm height and 92 grams of weight.

The MK6017MAP consists of an HDA (Head Disk Assembly) and a printed circuit board. The HDA has a

sealed module which contains a disk spindle assembly, a head actuator assembly and an air filtration

system. This HDA adopts Winchester technology which enhances high reliability. The actuator is a rotary

voice coil motor which enables high-speed access.

The disk is driven directly by a DC spindle motor. Air filtration is provided by a high performance air filtration

system using both breather and circulation filters.

The drive provides a carriage lock mechanism which is activated automatically upon power down in order to

prevent head/media from being damaged when it is not operating or under shipment.

The printed circuit board which is set externally to the HDA and equipped with all the electric circuitry

necessary to operate the drive except the head drivers . The power supply and interface signal connectors

are mounted on the board. Only the head control IC’s are located within the HDA. The circuitry perform the

following functions:

Read/Write, Task File Control, Spindle Motor Control, Seek and Head Positioning Servo Control, Abnormal

Condition Detection and Shock Sensor Control.

- 511 -

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SAFETY

■Do not disassemble, remodel or repair.

Disassembly, remodeling or repair may cause injury,

failure, or data loss.

NOTE

●There is a certain probability of the drive causing failure including data error or data

loss.

Take preventive steps such as backing up data etc. without exception in order to

prevent loss etc. in cases where data loss may result in loss or damage.

●Do not touch the top cover since application of force to it may cause damage to the

drive.

●Do not stack the drive on another drive or on other parts etc. or stack them on top of

it during storage or transportation.

Shock or weight may cause parts distortion etc..

●Labels and the like attached to the drive are also used as hermetic sealing for

maintenance of its performance.

Do not remove them from the drive.

- 512 -

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3. KEY FEATURES

•

High capacity in smallest size

2.5inch-type 1platters accommodating formatted capacity of 6.007GB,

Slim ( 9.5 mm in height ) and light (92 gram in weight) design.

•

Fast access and fast transfer rate

Quick spin up of Spindle Motor

4 sec.

Average access time 13 msec enabled by optimized balance of a head actuator assembly and an efficiently

designed magnet of rotary VCM.

Bus transfer rate up to 66.7 megabytes per second and disk transfer 253 megabits maximum per second.

Read ahead cache and write cache enhancing system throughput.

•

Intelligent Interface

ATA-2/ATA-3/ATA-4/ATA-5 interface supported.

Ultra66 supported.

Quick address conversion in translation mode.

Translation mode which enables any drive configuration.

LBA (Logical Block Address) mode.

Single/Multi word DMA, Ultra-DMA modes and

Data integrity

Advanced PIO mode supported.

•

Automatic retries and corrections for read errors.

368 bit computer generated ECC polynomial with 17 bit five burst and 113 bit single burst on-the-fly error

correction capability or 17 bit seven burst and 161 bit single burst error correction capability at retry.

High reliability

Powerful self- diagnostic capability.

Shock detection with shock sensor circuit for high immunity against operating shock up to 1470 m/s

( 150 G ).

Automatic carriage lock secures heads on the ramp with high immunity against non operating shock up to

6,860 m/s (700G).

•

Low power consumption

Low power consumption by Adaptive Power Mode Control .

- 513 -

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4. BASIC SPECIFICATION

MODEL

MK6017MAP

6.007

Formatted Capacity( gigabytes )

Servo design method

Recording method

Recording density

Sector Servo

32/34 TC-MEEPR4+PP

Track / mm (TPI )

1667 (42.3k)

Bit / mm ( BPI )

20.8k (528k ) max.

Flux change / mm ( FRPI )

Number of disks

Number of data heads

Number of user data cylinders

Bytes per sector

22.1k(561k ) max.

24,800

512

- 514 -

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5. PERFORMANCE

Access time ( msec ) <*1>

Track to track seek <*2>

Average seek <*3>

Max. seek <*4>

Rotation speed ( RPM )

Average Latency Time ( msec )

Internal Transfer rate ( Mbits / sec )

4,200 + 0.1%

7.14

133.0～253.5

Host Transfer rate ( Mbytes / sec )

Ultra DMA mode

PIO mode

66.7

16.6

Sector Interleave

Track skew

1:1

Yes

Buffer size ( Kbytes )

Cache

256

Read Ahead Cache

Write Cache

4 sec ( Typical )

20 sec ( Maximum )

4 sec ( Typical )

20 sec ( Maximum )

Start time <*5>

( Up to Drive Ready)

Recovery time from Stand- by <*5>

Command Overhead ( msec )

<*1> Under the condition of normal voltage, 25 C normal temperature and bottom side down.

<*2> Average time to seek all possible adjacent track without head switching.

<*3> Weighted average time to travel between all possible combination of track calculated as below.

Weighted average access time = [ Sum of P(n)*t(n) ] / [ Sum of P(n) ], n = 1 to N.

Where,

P(n); Total number of seek for stroke n [ = 2*(N - n) ].

t(n); Average seek time for stroke n.

N ; Total number of tracks.

Average seek time to seek to stroke n is the average time to 1,000 seeks for stroke n, with random head

switch.

<*4> Average time for 1,000 full stroke seeks with random head switches.

<*5> Typical values are for the condition of normal voltage, 25 C normal temperature and placing bottom

side down. Maximum values are for all conditions specified in this document.

- 515 -

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6. POWER REQUIREMENTS

6.1 Supply Voltage

6.1.1 Supply for Logic

Allowable voltage

5V + 5%

Allowable noise/ripple

100 mV p-p or less

6.1.2 Supply for Motor

Allowable voltage

5V + 5%

Allowable noise/ripple

100 mV p-p or less

6.2 Power Consumption

Average (note 3)

Maximum (note 4)

Start

2.7 W Typical

2.3 W Typical

1.9 W Typical

0.78 W Typical

0.58 W Typical

0.25 W Typical

0.1 W Typical

5.6 W (note5)

3.8 W (note6)

3.0 W

Seek (note 7)

Read / Write(note 8)

Active idle (note 1)

Low power idle (note 9)

Stand- by (note 2)

Sleep

0.9 W

0.8 W

0.3 W

0.15 W

(note 1) Motor is rotating at normal speed but none of Read, Write or Seek is executed.

(note 2) Motor is not rotating and heads are unloaded on the ramp.

(note 3) Under normal condition ( 25 C, 101.3 kPa ( 1,013 mb ) ) and 5V + 0%.

(note 4) Under all the specified conditions.

(note 5) Only when motor start retry, it may last for 2 seconds.

(note 6) Peak value during seek operation

(note 7) The seek average current is specified based on three operations per 100 ms.

(note 8) The read/write current is specified based on three operations of 63 sector read/write per 100 ms.

(note 9) Motor is rotating at normal speed but heads are unloaded on the ramp.

6.3 Energy Consumption Efficiency

Energy consumption efficiency

Power consumption at Low power idle /

Average(W/GB)

0.097

Max.(W/GB) Classification

0.116

Capacity

Energy consumption efficiency is calculated in accordance with the law regarding efficiency of energy consumption

:Energy saving law,1979 law number 49.

Calculation of Energy consumption is dividing consumed energy by the capacity.

The consumed energy and capacity shall be measured and specified by the Energy saving low.

6.4 Power Sequence

If the 5V Logic is separated from 5V Motor, both lines should be turned on and off at the same time

within the time period of one second .

- 516 -

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7. MECHANICAL SPECIFICATIONS

7.1 Dimension

Width

Height

Depth

69.85mm ( 2.75” )

9.5 mm ( 0.37”)

100.0 mm ( 3.94” )

Figure 1 and Table 7.4-1 show an outline of the drive.

7.2 Weight

92gram(Typ.)

94gram(max.)

7.3 Drive Orientation

The drive can be installed in all axes (6 directions).

7.4 Mounting Instructions

SAFETY

NOTE

●Take anti-static measures in order to avoid damage to the drive when handling it.

The drive uses parts susceptible to damage due to ESD (electrostatic discharge).

Wear ESD proof wrist strap in accordance with the usage specified when

handling a drive that is not in an anti-static protection bag.

●Extreme shock to the drive may cause damage to it, data corruption, etc..

Do not subject the drive to extreme shock such as dropping, upsetting or crashing

against other objects.

●Do not place objects which generate magnetic fields such as magnets, speakers,

etc. near the drive.

Magnetism may cause damage to the drive or data loss.

- 517 -

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360014937

7.4.1 Screwing

Four screws should be tightened equally with 0.3 N m ( 3 kgf cm ) torque. The depth should be 3.0 mm

min. and 3.5 mm maximum.

7.4.2 Installation

①

②

③

④

The drive should be mounted carefully on the surface of 0.1mm or less flatness to avoid excessive

distortion.

In order to prevent short-circuit under any circumstances, the space of 0.5mm or more should be kept under

the PCB and the design have to be checked carefully (See fig. 2).

Enough space should be kept around the drive especially around the convex portion of HDA (See fig. 2) to

avoid any contact with other parts, which may be caused by receiving shock or vibration.

The temperature of the top cover and the base must always be kept under 60℃ to maintain the required

reliability. ( If the drive runs continuously or spins-up frequently, the temperature of the top cover may rise to

15℃ maximum. If the drive is used in ambient temperature of 45℃ or more, it should be kept where

adequate ventilation is available to keep the temperature of top cover under 60℃)

⑤

M3 mounting screw holes are tapped directly on the base for electrical grounding between the drive and the

base. In order to prevent the drive performance from being affected by the system noise, appropriate

evaluation should be conducted before deciding loading method.

⑥

⑦

Be sure not to cover the breathing hole ( See fig. 1) to keep the pressure inside the drive at a certain level.

Don’t apply any force to the top cover except to the screw areas ( See fig. 2) on top cover. The maximum

force to the specified area is 2N.

⑧

⑨

The drive contains several parts which may be easily damaged by ESD(Electric Static Discharge). Avoid

touching the interface connector pins and the surface of PCB. Be sure to use ESD proof wrist strap when

handling the drive.

A rattle heard when the drive is moved is not a sign of failure.

- 518 -

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360014937

UNIT: mm

Figure 1 MK6017MAP Dimensions

- 519 -

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360014937

SFF-8200 Rev1.1(*)

SFF-8201 Rev1.2

SFF-8212 Rev1.2

MK6017MAP

(Differences only)

Dimension

Millimeters

Inches

Millimeters

9.5

Inches

0.374

－

0.20

0.008

－

69.85

0.25

2.750

0.010

101.85 max

3.99

10.14

4.010 max

0.157

0.399

0.079

0.020

0.002

0.020

0.002

0.152

0.008

0.118

N/A

0.160

2.430

100.00 ±0.41

3.99 ±0.43

3.973 ±0.016

0.157 ±0.017

0.399 ±0.020

A10

A11

A12

A13

A14

A17

A18

A21

A22

A23

A26

A28

A29

A32

A34

A35

A36

A37

A38

A41

A50

A51

A52

A53

A54

10.14 ±0.51

2.00

0.50

0.05

0.50

0.05

3.86

0.20

3.00

4.07

61.72

61.72 ±0.30

2.430 ±0.012

N/A

1.00 min

8.00 max

60.20 min

8.00

3.00 min

2.50 min

14.00min

90.60min

14.00min

90.60min

10.24min

0.039 min

0.315 max

2.370 min

0.315

0.118 min

0.980 min

0.551min

3.567min

0.551min

3.567min

0.403min

5.00

3.50 min

14.00 ±0.30

90.60 ±0.30

14.00 ±0.30

90.60 ±0.30

10.24 ±0.51

0.197

0.137 min

0.551 ±0.012

3.567 ±0.012

0.551 ±0.012

3.567 ±0.012

0.403 ±0.020

(*)SFF-8200,8201,8212:Small Form Factor Standard

Table 7.4-1 Dimensions

- 520 -

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360014937

Figure 2 Mounting Recommendation

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360014937

8. ENVIRONMENTAL LIMITS

8.1 Temperature and Humidity

8.1.1 Temperature

Operating

5 C- 55 C

Gradient 15 C / Hour maximum

Non- operating

- 20 C- 60 C

Gradient 15 C / Hour maximum

Under shipment

- 40 C- 70 C

Gradient 30 C / Hour maximum

( Packed in Toshiba’s original shipping package. )

The temperature of top cover and base must be kept under 60℃ at any moment to maintain the desire

reliability.

8.1.2 Humidity

Operating

8%- 90% R.H. ( No condensation. )

Non- operating

Under shipment

Max. wet bulb

8%- 90% R.H. ( No condensation. )

5%- 90% R.H. ( Packed in Toshiba’s original shipping package. )

29 C (Operating)

40 C (Non- operating)

8.2 Vibration

Operating

9.8 m/s ( 1.0G )

5- 500 Hz

Sine wave sweeping 1 oct./ minute

No unrecoverable error.

25.4 mm p-p displacement.

5-10 Hz

Non operating

No unrecoverable error.

49 m/s ( 5.0G )

10- 500 Hz

Sine wave sweeping 1 oct./ minute

No unrecoverable error.

8.3 Shock

Operating

1,470 m/s

( 150G )

2 msec half sine wave

Repeated twice maximum / second

No unrecoverable error.

Non- operating

6,860 m/s ( 700G ) 1 msec half sine wave

1,960 m/s ( 200G ) 11 msec half sine wave

Repeated twice maximum / second

No unrecoverable error.

Under shipment

70 cm free drop

No unrecoverable error.

Apply shocks in each direction of the drive’s three

mutually perpendicular axes, one axis at a time.

( Packed in Toshiba’s original shipping package. )

- 522 -

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360014937

8.4 Altitude

Operating

Non operating

- 300 m to 3,000 m

- 400 m to 15,000 m

8.5 Acoustics（Sound Power）

36 dBA MAX.

39 dBA MAX.

For idle mode ( Spindle in rotating ).

For repetition of random seek with full cylinder read operation.

Measurements are to be taken in accordance with ISO 7779.

8.6 Safety Standards

The drive satisfies the following standards .

Underwriters Laboratories

Canadian Standard Association

TUV Rheinland

( UL ) 1950

( CSA ) C22.2 No.950

EN 60 950

8.7 EMC Adaptability

The drive satisfies the following standards .

EN50081-1

EN55022

1994 Class B

1995

EN61000-3-2

EN61000-3-3

EN61000-4-2

EN61000-4-3

ENV50204

1995

EN50082-1

1995

1998

1995

EN61000-4-4

EN61000-4-5

EN61000-4-6

1995

1996

EN61000-4-11 : 1994

- 523 -

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360014937

9. RELIABILITY

A failure is defined as an inability of the drive to perform its specified function described in the requirements

of this document when being operated under the normal conditions or conditions specified in this document.

However , damages caused by operation mistake, mishandling, accidents, system errors and other damages

that can be induced by the customers are not defined as failure.

9.1 Error Rate

9.1.1 Non- Recoverable Error Rate

1 error per 10 bits read

The defective sectors allocated to the spare locations in the factory are not counted in the error rate.

9.1.2 Seek Error Rate

1 error per 10 seeks

A seek error is a positioning error recoverable by a retry including recalibration.

9.2 Mean Time to Failure (MTTF)

A failure means that the drive can not execute the function defined in this document under the nominal

temperature, humidity and the other conditions specified in this document . Damages caused by operation

mistake, mishandling, system failure and other damages occurred under the conditions which are not

described in this document are not considered as the failure.

MTTF

300,000 hours

Conditions

Power on hours

Operating hours

Seek hours

2,800 hours ( 200 days x 14 hours ) / year)

600 hours ( 200 days x 3 hours ) / year)

1.30 x 10 seeks / month

Number of load / unload

Environment

70 times / hour ( 60,000 times / year )

Normal ( 25 C, 101.3 kPa ( 1,013 mb ) )

9.3 Product Life

5 years or 20,000 power on hours whichever comes earlier

9.4 Repair

A defective drive should be replaced. Parts and subassemblies should not be repaired individually .

9.5 Preventive Maintenance (PM)

No preventive maintenance is required.

- 524 -

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360014937

9.6 Load/Unload

Be sure to issue and complete the following commands for unloading before cutting off the power

supply.

300,000 times of normal Load / Unload can be performed by a command.

Unload is executed by the following commands :

Soft Reset

Standby

Standby Immediate

Sleep

・

If the power supply is cut when the head is on a media, Emergency Unload is performed by routing the

back-EMF of SPM to the voice coil. In this case, Emergency Unload is performed 20,000 times

maximum. Emergency Unload should be used only when the host-system cannot perform normal

operation.

- 525 -

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360014937

10. HOST INTERFACE

Related Standards

Information technology - AT Attachment Interface with Extensions (ATA-2)

X3T10.279-199x

Information technology - AT Attachment-3 Interface (ATA-3)

X3T10/2008D Revision 6 October 26, 1995

Information technology - AT Attachment with Packet Interface Extension (ATA -4)

T13/1153D Revision 17 October 30, 1997

Information technology - AT Attachment with Packet Interface-5 Interface-5 (ATA-5)

T13/1321D Revision 2

December 13, 1999

10.1 Cabling

10.1.1 Interface Connector

Drive side

Yamaichi GAP050K11617 or equivalent

connector

Recommended

host side connector

for board

for cable

straight type

: Berg 86455-044 86456-044

or equivalent

Berg 89361-044 or equivalent

10.1.2 Cable

The following table shows preferable twisted pair type of cable .

Standard diameter

Characteristics impedance

0.32 mm ( 28 AWG )

100- 132

Ω

- 526 -

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360014937

10.2 Electrical specification

10.2.1 Cable length and capacitance

0.46m MAX.

35pF MAX.

10.2.2 DC input/output Characteristics

10.2.2.1 Input

item

unit

value

2.0 to (supply voltage +0.5 )

-0.3 to 0.8

voltage high (note 1)

low

leak current

+ 10 (note 2)

µA

As non-connected logic voltage, input voltage level is from -0.3V to 0.5V.

(note 1) The max. input range of signal is from -0.3V to (supply voltage +0.5V )

(note 2) Except for signal lines pulled up as shown in Table 10.3.3-1

10.2.2.2 Output

item

voltage high

low

unit

value

2.4 min.

0.4 max.

note

IOH = - 1mA

IOL = 4mA

IOL = 8mA

- 527 -

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360014937

10.3 Interface connector

10.3.1 ATA interface connector

2.00

2.00 × 24 = 48.00

Polarity key

Figure 3 ATA interface connector

- 528 -

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360014937

10.3.2 Pin Assignment

The following table describes all of the pins on the Task File Interface.

Table 10.3-1 Signal pin assignment

PIN No.

SIGNALS

PIN No.

SIGNALS

- RESET

GROUND

DD 10

DD 11

DD 12

DD 13

DD 14

DD 15

KEY

GROUND

DMARQ

- DIOW

GROUND

STOP

-DIOR

GROUND

CSEL

-DMARDY

HSTROBE

IORDY

-DMARDY

-DSTROBE

-DMACK

INTRQ

GROUND

- IOCS16

DA 1

- PDIAG／-CBLID

DA 2

DA 0

- CS0

- CS1

- DASP

GROUND

+ 5V (MOTOR)

RESERVED

+ 5V (LOGIC)

GROUND

Note) Symbol (-) in front of signal name shows negative logic.

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360014937

10.3.3 Signal Treatment

Driver types and requirements for the signal pull- up and down are as follows. Resistor requirement is minimum for the host.

- IO16 is pulled up in the drive with certain value so that the Vol is obtained to run with a host that has large value of pull up

resistor. - CS0 and - CS1 are also pulled up for better noise immunity.

Table 10.3-2 Signal treatment

SIGNAL

- RESET

Driven by

host

TYPE

By host

By drive

10kΩPU

DD 0:15

DMARQ

- DIOR

bi-direction

drive

5.6 k Ω PD

host

-DMARDY

HSTROBE

- DIOW

host

STOP

IORDY

drive

1.0 k Ω PU

-DDMARDY

DSTROBE

CSEL

host

drive

host

GND

10 k Ω PU

- DMACK

INTRQ

10 k Ω PD

1.0 k Ω PU 1.2 k Ω PU

- IOCS16

DA 0:2

- PDIAG／-CBLID drive

10 k Ω PU

- CS0 - CS1

- DASP

host

drive

10 k Ω PU

TP = Totem Pole, TS = Tri-State, PD = Pull Down, PU = Pull-Up, OD = Open Drain

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360014937

10.3.4 Series resistance

Each signal has its own series resistance.

SIGNAL

-DIOR

SERIAL RESISTANCE VALUE

82Ω

-HDMARDY

HSTROBE

-DIOW

82Ω

STOP

-CS0, -CS1

DA0,DA1,DA2

-DMACK

82Ω

22Ω

DMARQ

INTRQ

IORDY

-DDMARDY

DSTROBE

DD０～DD15

33Ω

10.3.5 Signal Description

SIGNAL

- RESET

DIR.

DESCRIPTION

O (*1)

Reset signal from the host system; It shall be active low when system is

powered-up or when voltage fault is detected.

DD 15- 0

KEY

I/O

N/C

18- 3

16 bit bi- directional data bus between the host system and the drive. All 16 bits

are used for data transfer in the data register. The lower 8 bits, HD0- HD7, are

used for the other register and ECC access.

Pin position 20 has no connection pin, clipped on the drive and plugged on the

cable in order to ensure correct orientation of the cable and to avoid wrong

insertion.

DMARQ

DMA request signal is set by the drive to indicate that the DMA data transfer is

ready. The direction of the data transfer is controlled by write/read strobe signal

(HOST IOW or HOST IOR). This signal is used on a hand shake manner with -

DMACK.

- DIOW

STOP

Write strobe. The rising clocks data from the host data bus, HD0 through HD15 to

a register or data register of the drive.

Stop signal used by the host after the completion of Ultra DMA Burst.

Read strobe. When active low, this signal enables data from a register or the data

of the drive onto the host data bus, HD0 through HD15. The rising edge of

-HOST IOR latches on the data on the bus from the drive.

This signal is for reporting the drive that the host system is ready to accept Ultra

DMA data.

Strobe. HSTROBE indicates that the host transfers ULTRA DMA data. The rising

edge and the falling edge of HSTROBE enable the drive to latch the data.

IORDY reports host that the BUS is available.

- DIOR

-HDMARDY

HSTROBE

IORDY

-DDMARDY

-DDMARDY is asserted to indicate that the drive is ready to receive the Ultra DMA

data.

DSTROBE

Strobe. DSTROBE is asserted to indicate that the drive transfers Ultra DMA data.

The rising edge and falling edge of DSTROBE enable the host to latch the data.

- 531 -

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360014937

CSEL

This pin and J2 (see 10.7) are used to determine the drive address, Master or

Slave. When J2 is ground, the drive works as a Master and when J2 is open, the

drive works as a Slave. If CSEL is negated then the drive runs as master drive If

CSEL is asserted then the drive runs as slave drive.

- DMACK

INTRQ

Responding to DMARQ, this signal indicates that the host is ready to receive or

send the data.

Interrupt to the host system, enabled only when the drive is selected and the host

activates the - IEN bit in the Device Control register. When the - IEN bit is inactive

or the drive is not selected, this output is in a high impedance state, whether an

interrupt is set or not.

The interrupt is set when the IRQ bit is set by the drive CPU. IRQ is reset to zero

when host reads the Status register or a write to the command register or when

DRQ is negated.

- IOCS16

Indication to the host system that the 16 bit data register has been addressed and

that the drive is ready to send or receive a 16 bit data word (open drain).

Address line from the host system to select the registers of the drive.

In Master/Slave mode, this signal reports the presence of slave drive to master

drive and enables transmitting of diagnostic result between master drive and slave

drive

DA 1

- PDIAG

／CBLID

I/O

DA 0

DA 2

Address line from the host system to select the registers of the drive.

Chip select signal generated from the host address bus. This signal is used to

select one of the two groups of host accessible registers.

Chip select signal generated from the host address bus. This signal is used to

select one of the two groups of host accessible registers.

This is a signal from the drive used either to drive an external LED whenever the

drive is being accessed, or to report presence of the slave drive to the master

when the drive is in master/slave mode.

- CS0

- CS1

- DASP

RESERVED

+ 5V (LOGIC)

+ 5V

27,44

Reserved for future use. No connection.

Power line for logic and analog circuit.

Power line for driving motor.

(MOTOR)

GROUND

2,19

Ground between the drive and the host system.

22,24

26,30

40,43

(*1) ‘I’ is from the drive to the host system, ‘O’ is from the host system to the drive, and ‘I/O’ is bi-directional.

- 532 -

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360014937

10.4 Host Interface Timing

10.4.1 Program I/O Write Timing

DA2, DA1, DA0

-CS0, -CS1

t_ASW

t_AHW

t_AICSI

-DIOW

t_WE

t_WER

t_WCY

DD15∼DD0

t_CICSV

t_DS

t_DH

-IOCS16

t_AICSV

t_A

t_B

IORDY

Transfer mode

Symbol

t_ASW

t_DS

t_WE

t_DH

t_AHW

t_WER

t_WCY

t_CICSV

t_AICSV

t_AICSI

t_A

Meaning

165

600

125

100

Address Setup to -DOW Low

Data Setup to -DOW High

-DOW Pulse Width

Data Hold from -DOW High

ADDR Hold from -DOW High

-DOW Inactive

(min.)

(max.)

Write Cycle Time

383

240

180

n/a*

120

n/a*

-IOCS16 valid from -CS

-IOCS16 valid from address

-IOCS16 inactive from address

IORDY Setup time

1250

t_B

IORDY Pulse Width

1250

(*) -IOCS16 shall be specified in ATA-2 specifications. For other modes, this signal is invalid. The Drive

releases -IOCS16 within the time of t_AICSI, but how much time it takes to turn to inactive condition is

determined by pull up resistance, output impedance and line capacitance.

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360014937

10.4.2 Program I/O Read Timing

DA2, DA1, DA0

-CS0, -CS1

t_ASE

t_AHE

t_AICSI

-DIOR

t_RE

t_RDR

t_RDCY

DD15∼DD0

t_DAC

t_RDSE

t_DOH

t_CICSV

t_HDTS

-IOCS16

t_AICSV

t_RD

t_B

t_A

IORDY

Transfer mode

Symbol

t_ASE

t_DAC

t_RE

t_RDSE

t_DOH

t_HDTS

t_AHE

t_RDR

t_RDCY

t_CICSV

t_AICSV

t_AICSI

t_RD

Meaning

Address Setup to -DIOR Low

Data Valid from -DIOR Low

-DIOR Pulse Width

(min.)

(max.)

(min.)

(max.)

(min.)

(max.)

(min.)

(max.)

165

600

125

383

100

240

-DIOR data setup

Data Hold from -DIOR High

Data Tri-state from -DIOR High

ADDR Hold from -DIOR High

-DIOR Inactive

180

n/a*

Read Cycle Time

120

n/a*

-IOCS16 valid from -CS

-IOCS16 valid from address

-IOCS16 inactive from address

Read Data Valid to IORDY

IORDY Setup time

t_A

t_B

1250

IORDY Pulse Width

1250

(*) -IOCS16 is specified in ATA-2 specifications. For other modes, this signal is invalid. Drive releases

-IOCS16 within the time of t_AICSI, but how long it takes to turn to inactive condition is defined by pull up

resistance, output impedance and line capacitance.

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360014937

10.4.3 Single Word DMA Write Timing

t_O

DMARQ

t_C

-DMACK

t_I

t_J

-DIOW

t_D

DD15∼DD0

t_G

t_H

ATA-2 SPECIFICATIONS

Transfer mode

Meaning

Cycle time

DMACK to DMARQ delay

-DOW 16-bit

-DOW data setup

-DOW data hold

DMACK to -DOW setup

-DOW to DMACK hold

MODE 0

Min.

MODE 1

Min.

MODE 2

Min.

Symbol

Max.

200

Max.

100

Max.

t_C

t_D

t_G

t_H

t_I

960

480

240

480

250

240

100

120

t_J

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360014937

10.4.4 Single Word DMA Read Timing

t_O

DMARQ

-DMACK

t_C

t_I

t_J

-DIOR

t_D

DD15∼DD0

t_E

t_S

t_F

ATA-2 SPECIFICATION

Transfer mode

Meaning

Cycle time

DMACK to DMARQ delay

-DIOR 16-bit

-DIOR data access

-DIOR data hold

DMACK to -DIOR setup

-DIOR to DMACK hold

-DIOR setup

MODE 0

Min.

MODE 1

Min.

480

MODE 2

Min.

Symbol

Max.

200

Max.

100

Max.

t_C

t_D

t_E

t_F

t_I

960

240

480

240

120

250

t_D-t_E

150

t_J

t_S

t_D-t_E

- 536 -

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360014937

10.4.5 Multiword DMA Write Timing

DMARQ

-DMACK

t_O

t_L

t_I

t_D

t_K

t_J

-DIOW

DD15∼DD0

t_G

t_H

ATA/ATAPI-5 SPECIFICATIONS

Transfer mode

Meaning

Cycle time

DMACK to DMARQ delay

-DIOW 16-bit

-DIOW data setup

MODE 0

Min.

480

MODE 1

Min.

MODE 2

Symbol

Max.

---

Max.

---

Min.

Max.

t_C

t_D

t_G

t_H

t_I

t_J

t_K

t_L

150

120

---

215

100

-DIOW data hold

DMACK to -DIOW setup

-DIOW to DMACK hold

-DIOW negated pulse width

-DIOW to DMARQ delay

215

- 537 -

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360014937

10.4.6 Multiword DMA Read Timing

DMARQ

-DMACK

t_O

t_L

t_I

t_D

t_K

t_J

-DIOR

t_Z

t_E

DD15∼DD0

t_F

ATA/ATAPI-5 SPECIFICATIONS

Transfer mode

Meaning

Cycle time

DMACK to DMARQ delay

-DIOR 16-bit

-DIOR data access

-DIOR data hold

-DIOR to tristate

DMACK to -DIOR setup

-DIOR to DMACK hold

-DIOR negated pulse width

-DIOR to DMARQ delay

MODE 0

Min.

480

MODE 1

Min.

MODE 2

Symbol

Max.

---

Max. Min.

Max.

t_C

t_D

t_E

t_F

t_Z

t_I

t_J

t_K

t_L

150

120

---

215

150

120

- 538 -

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360014937

10.4.7 Ultra DMA Timing

Initiating an Ultra DMA data in burst

DMARQ

(device)

t_UI

DMACK-

(host)

t_FS

t_ACK

t_ENV

t_ZAD

STOP

(host)

t_FS

t_ACK

t_ENV

HDMARDY-

(host)

t_ZAD

t_ZIORDY

DSTROBE

(device)

t_AZ

t_VDS

t_DVH

DD(15:0)

t_ACK

DA0, DA1, DA2,

CS0-, CS1-

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360014937

Sustained Ultra DMA data in burst

t_2CYC

t_CYC

t_2CYC

DSTROBE

at device

t_DVH

t_DVS

DD(15:0)

at device

DSTROBE

at host

t_DH

t_DS

t_DH

t_DS

t_DH

DD(15:0)

at host

Host pausing an Ultra DMA data in burst

DMARQ

(device)

DMACK-

(host)

t_RP

STOP

(host)

t_SR

HDMARDY-

(host)

t_RFS

DSTROBE

(device)

DD(15:0)

(device)

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Device terminating an Ultra DMA data in burst

DMARQ

(device)

t_MLI

DMACK-

(host)

t_LI

t_ACK

t_LI

STOP

(host)

t_ACK

t_LI

HDMARDY-

(host)

t_SS

t_IORDYZ

DSTROBE

(device)

t_ZAH

t_AZ

t_DVS

t_DVH

DD(15:0)

CRC

t_ACK

DA0, DA1, DA2,

CS0-, CS1-

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Host terminating an Ultra DMA data in burst

DMARQ

(device)

t_LI

t_MLI

DMACK-

(host)

t_ZAH

t_AZ

t_RP

t_ACK

STOP

(host)

t_ACK

HDMARDY-

(host)

t_RFS

t_MLI

t_LI

t_IORDYZ

DSTROBE

(device)

t_DVS

t_DVH

DD(15:0)

CRC

t_ACK

DA0, DA1, DA2,

CS0-, CS1-

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Initiating an Ultra DMA data out burst

DMARQ

(device)

t_UI

DMACK-

(host)

t_ACK

t_ENV

STOP

(host)

t_ZIORDY

t_LI

t_UI

DDMARDY-

(device)

t_ACK

HSTROBE

(host)

t_DVS

t_DVH

DD(15:0)

(host)

t_ACK

DA0, DA1, DA2,

CS0-, CS1-

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Sustained Ultra DMA data out burst

t_2CYC

t_CYC

t_2CYC

HSTROBE

at host

t_DVH

t_DVS

DD(15:0)

at host

HSTROBE

at device

t_DH

t_DS

t_DH

t_DS

t_DH

DD(15:0)

at device

Device pausing an Ultra DMA data out burst

t_RP

DMARQ

(device)

DMACK-

(host)

STOP

(host)

t_SR

DDMARDY-

(device)

t_RFS

HSTROBE

(host)

DD(15:0)

(host)

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Host terminating an Ultra DMA data out burst

t_LI

DMARQ

(device)

t_MLI

DMACK-

(host)

t_LI

t_ACK

t_SS

STOP

(host)

t_LI

t_IORDYZ

DDMARDY-

(device)

t_ACK

HSTROBE

(host)

t_DVS

t_DVH

DD(15:0)

(host)

CRC

t_ACK

DA0, DA1, DA2,

CS0-, CS1-

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Device terminating an Ultra DMA data out burst

DMARQ

(device)

DMACK-

(host)

t_LI

t_MLI

t_ACK

STOP

(host)

t_RP

t_IORDYZ

DDMARDY-

(device)

t_RFS

t_MLI

t_ACK

t_DVH

t_ACK

t_LI

HSTROBE

(host)

t_DVS

DD(15:0)

(host)

CRC

DA0, DA1, DA2,

CS0-, CS1-

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ATA/ATAPI specifications

Transfer mode

MODE 0

MODE 1

MODE 2

MODE 3

MODE 4

Symbol

t_CYC

t2_CYC

t_DS

Meaning

Cycle time

Min.

Max.

Min. Max. Min.

Max. Min.

Max.

Min.

Max.

112

230

154

115

Two cycle time

Data setup time

t_DH

Data hold time

t_DVS

t_DVH

t_FS

t_LI

t_MLI

Data valid hold time

First STROBE time

Limit interlock time

Interlock time min.

Unlimited interlock

Allowed to release

Delay time

230

150

200

150

170

150

130

100

120

100

t_UI

t_AZ

t_ZAH

t_ZAD

t_ENV

t_SR

t_RFS

t_RP

Delay time

Envelope time

Strobe to DMARDY

Ready to final Strobe

Ready to pause

160

125

100

t_IORDYZ

t_ZIORDY

t_ACK

Pullup before IORDY

Wait before IORDY

Setup hold for DACK

Strobe to DREQ/Stop

t_SS

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10.4.8 Reset Timing

BUSY

t_N

- RESET

t_M

Symbol Meaning

Minimum Maximum Unit

Condition

t_M

t_N

RESET pulse width (Low)

RESET inactive to BSY active

µs

400

10.5 Grounding

HDA (Head Disk Assembly) and DC ground(ground pins on interface) are connected electrically each other.

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10.6 Address Decoding

The host addresses the drive using programmed I/O. In this method, the required register address should

be placed on the three host address lines, DA2 - DA0. An appropriate chip is selected and a read or write

strode (-DIOR / -DIOW) shall be given to the chip.

The following I/O map shows definitions of all the register addresses and functions for these I/O locations.

The descriptions of each register are shown in the next paragraph.

Table 10.6-1 Register map

Address

- CS0

- CS1 HA2 HA1 HA0 READ REGISTER

WRITE REGISTER

Invalid address

Data register

Error register

Invalid address

Data register

Features (Write precompensation)

Sector count

Sector number / LBA bit 0- 7

Cylinder low / LBA bit 8- 15

Cylinder high / LBA bit16- 23

Device head register

/ LBA bit 24- 27

Sector number / LBA bit0-7

Cylinder low / LBA bit8-15

Cylinder high / LBA bit16-23

Device head register

/ LBA bit 24-27

Status register

High impedance

Command register

Not used

Device control register

Not used

Alt. status register

Device address register¹

High impedance

“X” means “don't care”.

The host generates selection of two independent chips on the interface. The selected high order

chip ,-HOST CS1, is valid only when the host is accessing the address of alternate status register, digital

output register , and digital input register respectively. The low order chip, HOST CS0, is used to address all

other registers.

The following table shows the standard decode logic to connect with ISA (Industry Standard Architecture)

bus .

Table 10.6-2 Decode Logic

1F0-1F7

3F6,3F7

Decode

- CS0 = - ((- A9) (-A3)*(- AEN))

- CS1= -

(A9*A8*A7*A6*A5*A*A8*A7*A6*A5*A4*4)*(-A3)*(-

AEN)

170-177

376,377

- CS0= - ((- A9)*A8*(- A7)*A6*A5*A4*(- A3)*(- AEN)

- CS1= - (A9*A8*(- A7)*A6*A5*A4)*(- A3)*(- AEN)

The host data buses 15-8 are valid only when - IOCS16 is active.

•

- IOCS16 is asserted when interface address lines match to data register address. It does not turn active

during ECC bytes transfer for read or write long command (8 bit transfer).

ATA-2 Notes: This register is obsolete. A device is not supposed to respond to a read of this address. If a device does

respond, it shall be sure not to drive the DD7 signal to prevent possible conflict with floppy disk implementations.

The drive supports this register to maintain compatibility for ATA-1.

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10.7 Register Description

In the following register descriptions, unused write bit should be treated as “don't care”, and unused read bits

should be read as zeros.

10.7.1 Data Register

- CS0

DA2-DA0 : 0

Read / Write

There are seven commands which execute data transfer from/to this register of the sector buffer for Read

and Write operations. The sector table during Format command and the data associated with the Identify

Device command shall also be transferred to this register.

10.7.1.1 Read/Write command

The register provides a high speed 16 bit path into the sector buffer with PIO and DMA.

10.7.1.2 Read/Write Long command

When a Read/Write Long is issued, the ECC bytes are transferred by 8 bit operation.

10.7.1.3 Read/Write Buffer command

This command provides 16 bit path between host and data buffer in the drive.

10.7.1.4 Format command

This command provides a path for the parameter including interleave table in a sector length.

10.7.1.5 Identify Device command

Drive information is transferred during the execution of this command.

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10.7.1.6 Security commands

Password information is transferred during the execution of following four commands.

1) Disable password

2) Erase Unit

3) Set Password

4) Unlock

Data in the register and on the media correspond to each other as follows:

A15 - A8

A7 - A0

transfer

transfer 256

transfer 257

D512

D511

D2 --- D512 E1 --- E4

transfer 260

DATA REGISTER

DATA FLOW ON THE MEDIA

10.7.2 Error Register

- CS0

DA2-DA0 : 1

Read ONLY

10.7.2.1 Operational Mode

The following descriptions are bit definitions for the operational mode including the error information from the

last command. This command is valid only when the ERROR BIT (bit 0) is set.

ICRC

UNC

IDNF

MCR

ABRT

TK0NF AMNF

Bit 7

Bit 6

Interface CRC error was found during the transfer of Ultra DMA.

UNC (Uncorrectable Data Error) -- This bit indicates that an uncorrectable error has been encountered in the

data field during a read command.

Bit 5

MC (Media Changed) -- This bit is reserved for use by removable media devices and indicates that new

media is available to the operating system.

Bit 4

Bit 3

IDNF (ID Not Found) --The requested sector could not be found.

MCR (Media Change Requested) is reserved for use by removable media devices and indicates that a

request for media removal has been detected by the device.

Bit 2

ABRT (Aborted Command) -- This bit Indicates that the requested command has been aborted due to the

reason reported in the drive status register (Write Fault, Not Seek Complete, Drive Not Ready, or an invalid

command). The status registers and the error registers may be decoded to identify the cause.

TK0NF (Track 0 Not Found) -- This bit is set to indicate that the track 000 has not been found during a

Recalibrate command.

Bit 1

Bit 0

AMNF (AM Not Found) -- This bit is set to indicate that the required Data AM pattern on read operation has

not been found.

ATA-2 Notes: Prior to the development of ATA-2 standard, this bit was defined as BBK (Bad Block Detected) -- This bit was used to

indicate that the block mark was detected in the target’s ID field. The mark does not exist when shipping from the factory.The Mark

will be written by FORMAT command. Read or Write commands will not be executed in any data fields marked bad. The drive does

not support this bit.

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10.7.2.2 Diagnostic Mode

The drive enters diagnostic mode immediately after the power -on or after an Execute Diagnostics command.

Error bit in Status Register shall not be set in these cases. The following table shows bit values for the

diagnostic mode.

Table 10.7-1 Diagnostic mode error register

No errors

06-7F

Controller register error

Buffer RAM error

ECC device error

CPU ROM/RAM error

reserved

Slave drive error (see below)

When two drives are daisy-chained on the interface, the MASTER drive has valid error information for

diagnostic mode. When the SLAVE drive detects an error, 80H and OR value (01～04) diagnosed by the

MASTER are set to the code above mentioned.

10.7.3 Features Register (Write Precompensation Register)

- CS0

DA2-DA0 : 1

Write only

Write precompensation is automatically optimized by the drive internally. This register is used with Set

Features command.

10.7.3.1 Smart command

This command is used with the Smart commands to select subcommands.

10.7.4 Sector Count Register

- CS0

DA2-DA0 : 2

Read / Write

10.7.4.1 Disk Access command

The sector count register determines the number of sectors to be read or written for Read, Write, and Verify

commands. A 0 in the sector count register specifies a 256 sector transfer. After normal completion of a

command, the content shall be 0.

During a multi-sector operation, the sector count is decremented and the sector number is incremented. If

an error should occur during multi-sector operation, this command shows the number of remaining sectors in

order to avoid duplicated transfer.

10.7.4.2 Initialize Device Parameters command

This register determines number of sectors per track.

10.7.4.3 Power Control command

This register returns a value in accordance with the operation mode (idle mode or stand-by mode).

10.7.4.4 Set Features Command

If features register for this command is 03h, this register sets the data transfer mode.

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10.7.5 Sector Number Register

- CS0

DA2-DA0 : 3 Read / Write

The target logical sector number (starting from 1) for Read, Write, and Verify commands is set in this

host.

The starting sector number is set in this register for multi-sector operations. But when error occurs during

multi-sector transfer, it shows the number of the sector in which the error has been detected. During

multi-sector transfer, the number of the next sector to be transferred will not necessarily be shown.

In LBA mode, this register contains Bits 0 - 7 logical block address. After completion of a command, the

10.7.6 Cylinder Low Registers

- CS0

DA2-DA0 : 4

Read / Write

10.7.6.1 Disk Access command

Lower 8 bits of the starting cylinder number(starting from 0) for Read, Write, Seek, and Verify commands are

contained in these registers. After completion of the command or sector transfer, the current cylinder is

shown in this register.

In LBA mode, Bits 8 - 15 of the target address in logical block address are set in this register. After

completion of a command, the register is updated to reflect the current LBA Bits 0 - 7.

10.7.6.2 SMART commands

This register should be set to 4Fh for SMART commands

10.7.7 Cylinder High Registers

- CS0

DA2-DA0 : 5

Read / Write

10.7.7.1 Disk Access command

The high order 2 bits of the starting cylinder number (starting from 0) for Read, Write, Seek, and Verify

commands are set in this register. Together with Cylinder Low Register, it defines 0 to 1,023 cylinders.

After completion of the command or sector transfer, this register shows the current cylinder.

In LBA mode, Bits 16 - 23 of the target address in logical block address are contained in this register. After

completion of the command, it shows the Bits 0 - 7 of the last logical block address.

Cylinder High

Cylinder Low

7 6 5 4 3 2 1 0

Cylinder Bits

15 14 13 12 11 10

7 6 5 4 3 2 1 0

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10.7.7.2 SMART commands

This register should be set to C2h for SMART commands

10.7.8 Device/Head Register

- CS0

DA2-DA0 : 6

Read / Write

The value of this register is used to select the drive, Master or Slave, and head. On multiple sector

read/write operation that requires to cross track boundaries, the head select bit will be updated to reflect the

currently selected head number.

DEV

HS3

HS2

HS1

HS0

Bit 7

Bit 6

Bit 5

Bit 4

Reserved (recommended to set 1)

L (Select LBA mode) L=0: CHS mode. L=1: LBA mode.

Reserved (recommended to set 1)

DEV (Device Select):

- (Master/Slave mode) This bit is used to select the drive. DEV= 0 indicates the first fixed disk drive

(Master), and DEV= 1 indicates the second (Slave).

- (Single mode) should be 0. If this is 1, a drive is not selected but 00h shall be returned to status

Bit 3 -

Bit 0

HS3-HS0 (Head Select Bits) -- Bits 3 through 0 determine the required read/write head. Bit 0 is the

least-significant bit. If the L bit is equal to one (LBA Mode), the HS3 through HS0 bits contain bits 27

through 24 of the LBA.

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10.7.9 Status Register

-CS0

DA2-DA0:7

Read only

This register contains the command status. The contents of the register are updated at the completion of

each command and whenever the error occurs. The host system reads this register in order to acknowledge

the status and the result of each operation.

When the BSY bit (bit 7) is set, no other bits in the register are valid. And read/write operations of any other

resisters’ contents .

If the host reads this register when an interrupt is pending, interrupt request (INTRQ) is cleared in order to

work as Interrupt Acknowledge.

The bits of the status register are defined as below :

BSY

Bit 7

DRDY

DSC³

DRQ

CORR

IDX

ERR

BSY (Busy) -- This bit is set when Host Reset (HRST) line is activated or Software Reset (SRST) bit in

Device Control register is set or when the COMMAND register is written and until a command is

completed but when Data Request is set to 1, this bit shall be reset. The host shouldn’t write or read any

registers when BSY = 1.

Bit 6

DRDY (Drive ready) -- DRDY=1 when seek complete bit (bit 4) = 1, indicates that the drive is ready to

respond read, write, or seek command. DRDY=0 indicates that read , write and seek are negated. A

command execution shall be interrupted if Not-Ready condition occurs during a command execution and

will be reset until the next command whether the drive condition is Ready or Not Ready. Error bit is set on

this occasion and will be reset just after power on and set again after the drive begins revolving at normal

speed and gets ready to receive a command.

Bit 5

Bit 4

DF (Device Fault) -- DF=1 indicates that the drive has detected a fault condition during the execution of a

Read Write commands; read, write, and seek commands are negated and Error bit is set. DF is set to 1

until the next command, whether the device is in fault condition or not.

DSC³(Drive Seek Complete) -- DSC³= 1 indicates that a seek operation has been completed. DSC³ is

set to 0 when a command accompanied by a seek operation begins. If a seek is not complete, a

command is terminated and this bit is not changed until the Status Register is read by the host . This bit

remains reset immediately after power on until the drive starts revolving at a nominal speed and gets

ready to receive command.

Bit 3

Bit 2

DRQ (Data Request) -- DRQ=1 indicates that the sector buffer requires 1 sector of data during a Read or

Write command.

CORR (Corrected Data) -- CORR=1 indicates that the data read from the disk had an error but was

successfully corrected by the read retry. This bit is always set to 0 and does not interrupt multi-sector

operations.

Bit 1

Bit 0

IDX (Index) -- This bit is a pulse signal set to 1 per revolution of the disk. Intervals of the signal may vary

during read / write operation. Therefore, the host shouldn’t use IDX for timing purposes.

ERR (Error) -- ERR = 1 indicates that an error occurred during execution of the previous command .

The cause of the error is reported on the other bit or in the error register. The error bit can be reset by the

next command from the controller. When this bit is set , a multi-sector operation is negated.

ATA-2 Notes: Prior to ATA-2 standard, this bit indicated that the device was on track. This bit may be used for other purposes in

future standards. For compatibility the drive supports this bit as ATA-1 specifies. User is recommended not to use this bit.

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10.7.10 Command Register

- CS0

DA2-DA0 : 7

Write only

The command register accepts commands for the drive to perform fixed disk operations. Commands are

executed when the TASK FILE is loaded and the command register is written and only when:

The status is not busy (BSY is inactive).

and

DRDY (drive ready) is active.

Any code NOT defined in the following list causes an Aborted Command error. Interrupt request (INTRQ)

is reset when a command is written. The following are acceptable commands to the command register.

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Table 10.7-2 Command Code

Command Code

Command Name

Hex Value

PARAMETERS USED

DRV

Nop

00H

1xH

Recalibrate

Read Sector(s)

Read Long

Write Sector(s)

Write Long

Write Verify

20/21H

22/23H

30/31H

32/33H

3CH

40/41H

50H

7xH

90H

91H

B0H

C4H

Read Verify Sector(s)

Format Track

Seek

Execute Diagnostics

Initialize Device Parameters

SMART

Read Multiple

Write Multiple

Set Multiple Mode

Read DMA

Write DMA

Power Control

C5H

C6H

C8/C9H

CA/CBH

Stand-by Immediate

Idle Immediate

Stand-by

E0 / 94H

E1 / 95H

E2 / 96H

E3 / 97H

E5 / 98H

E6 / 99H

E4H

Idle

Check Power Mode

Sleep

Read Buffer

Flush Cache

Write Buffer

Identify Device

Set Features

Security

E7H

E8H

ECH

EFH

Set Password

Unlock

F1H

F2H

Erase Prepare

Erase Unit

F3H

F4H

Freeze

F5H

Disable Password

F6H

Read Native Max Address

Set Max Address

F8H

F9H

Note: O and X are defined as follows.

O = Must contain valid information for this command.

X = Don't care for this command.

L = “0” indicates normal read/ write. “1” indicates Long command ( ECC Byte transfer ).

Parameters are defined as follows.

SC = SECTOR COUNT register.

SN = SECTOR NUMBER register.

CY = CYLINDER LOW and CYLINDER HIGH register.

DRV = DRIVE SELECT bit (bit 4 in DRIVE/HEAD register)

HD = HEAD SELECT bits (bit 3-0 in DRIVE/HEAD register)

FT = FEATURES register (WRITE PRECOMPENSATION register)

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10.7.11 Alternate Status Register

- CS1

DA2-DA0 : 6

Read only

This register contains the same information as the status register in the Task File. The only difference is that

this register being read does not imply interrupt acknowledge or doesn’t reset a pending interrupt.

See the description of ‘‘ status resister’’ for definitions of the bit in this register.

10.7.12 Device Control Register

- CS1

DA2-DA0 : 6

Write only

This register contains the following two control bits.

----

SRST

- IEN

----

Bit 7-4

Bit 3

not used

Reserved (recommended to set 1)

Bit 2

SRST (Soft Reset) -- SRST= 1 indicates that the drive is held reset and sets BSY bit in Status

on the interface, this bit will reset both drives simultaneously , regardless of the selection by Device

address bit in DEVICE/HEAD register.

Bit 1

Bit 0

- IEN (Interrupt Enable) -- When -IEN = 0, and the drive is selected by Drive select bit in

DEVICE/HEAD register, the drive interrupt to the host is enabled. When this bit is set, the - INTRQ

pin will be in a high impedance state, whether a pending interrupt is found or not.

not used

10.7.13 Device Address register⁴

- CS1

DA2-DA0 : 7

read only

The device address register is a read-only register used for diagnostic purposes. The followings are

definitions of bits for this register:

RSVD

- WTG

- HS3

- HS2

- HS1

- HS0

- DS1

- DS0

Bit 7

Reserved -- high impedance

Bit 6

Bit 5 - Bit 2

- WTG (Write Gate) -- This bit is active when a Write to the disk is in progress.

- HS3 to - HS0 (Head Select bits) -- Bit 5 through 2 are one's complement of the binary coded address of

currently selected head which is shown by Head Select bit in SDH register.

- DS1 (Drive Select 1) -- -DS1=0, when SLAVE drive is selected and active.

- DS0 (Drive Select 0) -- -DS0=0, when single mode or MASTER drive in Master/Slave mode is selected

and active.

Bit 1

Bit 0

Note) The following facts should be taken into consideration when this resister is in use.

-WG reflects actual write gate in the drive, however, because of address transition or cache operation, there

is no direct connection with the data transferred between host and drive.

-HEAD SELECT represents one’s complement of the binary coded address of currently selected head, but

does not show actual selection of the head.

ATA-2 Notes: This register is obsolete. A device is not supposed to respond to a read of this address. If a device does

respond, it shall be sure not to drive the DD7 signal to prevent possible conflict with floppy disk implementations.

The drive supports this register to maintain compatibility for ATA-1.

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10.8 Command Descriptions

The drive interprets the commands written in the command register by the host system and executes them.

This table shows the drive’s response to the valid commands written in command-register.

Status register

DF CORR

Error register

UNC IDNF ABRT TK0NF

Command

DRDY

ERR

ICRC

AMNF

CHECK POWER MODE

√

EXECUTE DEVICE DIAGNOSTIC

See

Table 10.7-1

FLUSH CACHE

√

FORMAT TRACK

√

IDENTIFY DEVICE

IDLE

IDLE IMMEDIATE

INITIALIZE DEVICE PARAMETERS

READ BUFFER

√

READ DMA

√

READ LONG

READ MULTIPLE

READ NATIVE MAX ADDRESS

READ SECTOR(S)

READ VERIFY SECTOR(S)

RECALIBRATE

√

SECURITY DISABLE PASSWORD

SECURITY ERASE PREPARE

SECURITY ERASE UNIT

SECURITY FREEZE LOCK

SECURITY SET PASSWORD

SECURITY UNLOCK

SEEK

√

SET FEATURES

SET MAX ADDRESS

SET MULTIPLE MODE

SLEEP

√

SMART Enable/Disable Attribute

autosave

SMART DISABLE OPERATIONS

√

SMART ENABLE OPERATIONS

SMART RETURN STATUS

SMART Read Attribute Values

SMART Read Attribute Thresholds

SMART Save Attribute Values

SMART Execute OFF-LINE Immediate

STANDBY

√

STANDBY IMMEDIATE

WRITE BUFFER

√

WRITE DMA

√

WRITE LONG

WRITE MULTIPLE

WRITE SECTOR(S)

WRITE VERIFY

Invalid command code

√ = valid on this command

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10.8.1 Nop (00h)

0 0 0 0 0 0 0 0

drive no.

COMMAND CODE

NORMAL COMPLETION

no change

LBA

no change

The Nop command reports the status. The drive terminates the command with aborted error after receiving

this command.

10.8.2 Recalibrate⁵(1xh)

0 0 0 1 X X X X

COMMAND CODE

NORMAL COMPLETION

no change

drive no.

00H

no change

LBA

00H

This command will set BSY bit and move the R/W heads on the disk to cylinder 0. At the completion of a

seek , it revises the status, resets BSY and generates an interrupt.

10.8.3 Flush Cache (E7h)

COMMAND CODE

RESISTER SETTING

drive no.

This command reports the completion of a Write cache to the host. At the completion of a Write cache,

the drive revises the status, resets BSY and generates an interrupt.

ATA/ATAPI-4 defines this command as Vendor specific. The drive supports this command to maintain ATA-3, and the previous

models compatibility. User is recommended not to use this command.

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10.8.4 Read Sector (20h/21h)

0 0 1 0 0 0 L X

drive no.

starting cylinder

starting head

starting sector

no. of sector to read

COMMAND CODE

NORMAL COMPLETION

no change

last possible

00H

no change

LBA

staring address

last address

Setting BSY bit, the drive will seek to the target cylinder if the head is not on target track ( implied seek ), select

the head and begin to read the number of sector defined in SC register ( 1-256 ) starting from the target sector.

After finding ID of target sector and having 1 sector of data read into the buffer RAM, the drive sets DRQ in status

In case of multi-sector transfer, DRQ bit is reset and BSY is set after 1 sector transfer to prepare for the next

sector transfer.

An uncorrectable data can also be transferred but the subsequent operation will terminate at the cylinder, head,

and sector (or LBA) position in the TASK FILE register. When a sector is ready to be read by the host, an

interrupt is issued. After the last sector is read by the host, no interrupt is issued at the end of a command.

10.8.5 Read Long⁶(22h/23h)

If L bit =1, this command returns the requested data and associated ECC information . The data field

transfer is 16 bits wide, but the ECC information is accepted in only one byte (8 bits) at a time. Long

command is valid only for single sector transfer (SC=01).

10.8.6 Write Sector (30h/31h)

0 0 1 1 0 0 L X

COMMAND CODE

NORMAL COMPLETION

no change

drive no.

starting cylinder

starting head

starting sector

last possible

start sector

no. of sector to write

00H

no change

LBA

starting address

last possible

The drive seeks to the target cylinder and selects the head and begins to write to the number of sectors

defined in SC register (1-256) starting from the target sector. DRQ in status register is set as soon as the

command register is written and the buffer RAM receives the data transferred from the host . After 1 sector

is transferred to the buffer RAM, the drive resets DRQ, sets BSY and begins write operation. In case of

multi-sector transfer, it sets DRQ bit, resets BSY and generates Interrupt to inform host that it is ready to

transfer the next 1 sector of data. The drive will seek to the target cylinder if the head is not on the target

track (implied seek). After transferring the last data in the buffer, it resets BSY and issues an interrupt.

ATA/ATAPI-4 defines this command as Vendor specific. The drive supports this command to maintain ATA-3, and the previous

models compatibility. User is recommended not to use this command.

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If an error occurs during multi-sector transfer, it will terminate the transfer by setting error information in

status register and error register, without shifting into data transfer mode from the host. CY, HD, SN ( LBA)

registers show the address where error has occurred.

10.8.7 Write Long⁷(32h/33h)

If Long bit is “1”, this command write the data and the associated ECC data information supplied by the host.

The data field transfer is 16 bit wide, but the ECC information is accepted in only 8 bits.

10.8.8 Read Verify (40h)

0 1 0 0 0 0 0 0

COMMAND CODE

NORMAL COMPLETION

no change

drive no.

starting cylinder

starting head

starting sector

last possible

start sector

LBA

no. of sector to be read

starting address

00H

last address

This command is identical to a Read command except that DRQ bit is not set and no data is sent to the host.

This allows the system to verify the integrity of the drive. A single interrupt is generated upon completion of

a command or when an error occurs.

10.8.9 Write Verify⁸(3Ch)

0 0 1 1 1 1 0 0

COMMAND CODE

NORMAL COMPLETION

no change

drive no.

starting cylinder

starting head

starting sector

last possible

start sector

LBA

no. of sector to be written

starting address

00H

last address

This command is identical to a Write sector command except that verification is not performed. A Write

verify command transfers the number of sectors (1-256) defined in SC register from the host to the drive,

then the data is written on the media. The starting sector is defined in CY, HD, SN (LBA) registers.

Upon receipt of the command, the drive sets DRQ until one sector of data is transferred from the host, then

resets DRQ, sets BSY. In case of multi- sector transfer, it sets DRQ, resets BSY and generate an interrupt to

report the host that the host is ready to receive 1 sector of data. The drive will seek to the target track if the

R/W head is not on the target track (implied seek). Reaching the target sector, the command transfers the

ATA/ATAPI-4 defines this command as Vendor specific. The drive supports this command to maintain ATA-3, and the previous

models compatibility. User is recommended not to use this command.

ATA/ATAPI-4 defines this command as Vendor specific. The drive supports this command to maintain ATA-3 compatibility. User is

recommended not to use this command.

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sector data from the host to the media. After transferring the last data in the buffer, it sets BSY and issues an

Interrupt.

10.8.10 Format Track

(50h)

0 1 0 1 0 0 0 0

COMMAND CODE

NORMAL COMPLETION

no change

drive no.

cylinder to format

head to format

no change

01H

00H

no change

The track specified by the task file is formatted with ID and data fields according to the table transferred to

the buffer. This command is rejected in LBA mode with an Aborted command error reported.

DRQ in status register is set as soon as the command register is written, and the buffer RAM receives the

data transferred from the host. After 512 bytes are transferred into the buffer RAM, the drive resets DRQ,

sets BSY and begins format operation. The drive seeks to the target cylinder if the head is not on the target

track ( implied seek ). After completion of the command, it resets BSY and generates an interrupt.

Format table consists of the number of sectors ( 16 bits ) per track . Upper byte represents sector number,

and lower byte represents format type.

The drive supports only 00H format type. Intending to maintain compatibility with previous models, the drive

accepts any format type, but the function will not change.

Sector interleave is always set to one regardless of sector sequence in the format table. Data subsequent

to format table are handled as “Don't care”.

FORMAT TABLE ( FIRST 86 BYTES )

(Ex. 43 logical sector mode)

0001, 0002, 0003, 0004, 0005, 0006, 0007, 0008, 0009, 0013, 0015, 0016, 0017, 0018,.0019,

001A,.......0029, 002A, 002B

DON’T CARE ( 426 BYTES ATTACHED )

0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, 0000, ........... 0000, 0000, 0000.

ATA/ATAPI-4 defines this command as Vendor specific. The drive supports this command to maintain ATA-3, and the previous

models compatibility. User is recommended not to use this command.

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10.8.11 Seek (7xh)

0 1 1 1 X X X X

COMMAND CODE

NORMAL COMPLETION

no change

drive no.

cylinder to seek

head to seek

no change

LBA

address to seek

no change

This command moves the R/W heads to the cylinder specified in the task files. The drive sets BSY and

starts seek operation. After the completion of a seek operation, the drive asserts DSC¹⁰

and return the interrupt.

negates BSY ,

If CY, HD and SN registers show invalid address, “ID Not Found” error is reported and no seek operation

shall be executed. All commands related to data access possess Implied Seek function and don't need this

command.

10.8.12 Toshiba Specific

1 0 0 0 X X X X

1 0 0 1 1 0 1 0

1 1 1 1 0 0 0 0

1 1 1 1 0 1 1 1

1 1 1 1 1 0 1 X

1 1 1 1 1 1 X X

COMMAND CODE

These commands are only for factory use. Host must not issue them.

10.8.13 Execute Diagnostics (90h)

1 0 0 1 0 0 0 0

COMMAND CODE

NORMAL COMPLETION

OOH

O1H

This command enables the drive to execute following self-test and reports the results to the error register

described in Table 10.7.2-1.

(1) ROM checksum test

(2) RAM test

(3) Controller LSI register test

An interrupt is generated at the completion of this command.

When two drives are daisy-chained on the interface, both drives execute the self test and the MASTER drive

reports valid error information of the two drives.

ATA-2 Notes: Prior to ATA-2 standard, this bit indicated that the device was on track. This bit may be used for other purposes in

future standards. For compatibility the drive supports this bit as ATA-1 specifies. User is recommended not to use this bit.

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10.8.14 Initialize Device Parameters (91h)

1 0 0 1 0 0 0 1

drive number

COMMAND CODE

NORMAL COMPLETION

no change

total number of heads-1

number of sector per track

no change

This command specifies the number of sectors per track and the number of heads per cylinder to set head

switching point and cylinder increment point. Specified values affect Number of the current logical heads,

Number of logical sectors per track, which can be read by Identify Device Command.

On issuing this command, the content of CY register shall not be checked. This command will be terminated

with ABORT error when it is issued on a invalid HD or SC register setting ( SC register=0 or the combination

of HD and SC register exceeds the drive parameter.

Any drive access command should accompany correct HD, SN register with heads and sectors within the

number specified for this command. Otherwise, it results in “ID not found” error. If the number of heads

and drives is within the specified number, command gives parameter to convert an address to access into

Logical Block Address (LBA). ‘‘ ID Not Found’’error also occur when this LBA exceeds the total number

of user addressable sectors. The command does not affect LBA address mode.

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10.8.15 Read Multiple (C4h)

1 1 0 0 0 1 0 0

COMMAND CODE

NORMAL COMPLETION

no change

drive number

starting cylinder

starting head

last possible

00H

starting sector

number of sector to read

no change

LBA

starting address

last possible

The read multiple command performs similarly to the Read Sectors command except for the following

features. Interrupts are not issued on each sector, but on the transfer of each block which contains the

number of sectors defined by a Set Multiple Mode command or the default , if no intervening Set Multiple

command has been issued.

Command execution is identical to the Read Sectors operation except that the number of sectors defined by

a Set Multiple Mode command are transferred without interrupts. DRQ qualification of the transfer is required

only at the start of a data block transfer, not required for the transfer of each sector.

The block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple

Mode command, which shall be executed prior to the Read Multiple command.

When the Read Multiple command is issued, the Sector Count Register contains the number of required

sectors ( not the number of blocks or the block count ) . If the number of required sectors is not evenly

divisible by the block count, The redundant sectors are transferred during the final partial block transfer. The

partial block transfer shall be for N sectors, where

N = The redundant sector count ( block count )

If the Read Multiple command is attempted when Read Multiple command are disabled, the Read Multiple

operation shall be rejected with an Aborted Command error.

Disk errors occurred during Read Multiple command are posted at the beginning of the block or partial block

transfer, but DRQ is still set and the data, including corrupted data, shall be transferred as they normally

would .

The contents of the Command Block Registers following the transfer of a data block which has a sector in

error are undefined. The host should retry the transfer as individual requests to obtain valid error information.

Subsequent blocks or defective blocks are transferred only when the error is a correctable data error. All

other errors after the transfer of the block containing the error terminates the command . Interrupts are

generated when DRQ is set at the beginning of each block or partial block.

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10.8.16 Write Multiple (C5h)

1 1 0 0 0 1 0 1

COMMAND CODE

NORMAL COMPLETION

no change

drive number

starting cylinder

starting head

last possible

start sector

starting sector

number of sector to write

00H

no change

LBA

starting address

last possible

This command performs similarly to the Write Sectors command except for the following features. The Drive

sets BSY immediately upon receipt of the command, and interrupts are not issued on each sector but on the

transfer of each block which contains the number of sectors defined by Set Multiple Mode command or the

default if no intervening Set Multiple command has been issued.

Command execution is identical to the Write Sectors operation except that no interrupt is generated during

the transfer of number of sectors defined by the Set Multiple Mode command but generated for each block.

DRQ qualification of the transfer is required only for each data block, not for each sector.

The block count of sectors to be transferred without programming of intervening interrupts by the Set Multiple

Mode command, which shall be executed prior to the Write Multiple command.

When the Write Multiple command is issued, the host sets the number of sectors ( not the number of blocks

or the block count ) it requests in the Sector Count Register. If the number of required sectors is not evenly

divisible by the block count, the redundant sectors are transferred during the final partial block transfer. The

partial block transfer shall be for N sectors, where

N = The redundant sector count ( block count )

If the Write Multiple command is attempted when Write Multiple command are disabled, the Write Multiple

operation shall be rejected with an Aborted Command error.

Disk errors occurred during Write Multiple command are posted after the attempted disk write of the block or

partial block which are transferred. The Write Multiple command is terminated at the sector in error , even if it

was in the middle of a block. Subsequent blocks are not transferred after an error. Interrupts are generated

for each block or each sector, when DRQ is set .

After the transfer of a data block which contains a sector with error, the contents of the Command Block

Registers are undefined. The host should retry the transfer as individual requests to obtain valid error

information.

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10.8.17 Set Multiple Mode (C6h)

1 1 0 0 0 1 1 0

COMMAND CODE

NORMAL COMPLETION

no change

drive no.

no change

The number of sectors / block

no change

This command enables the drive to perform Read and Write Multiple operations and sets the block count for

these commands.

The Sector Count Register is loaded with the number of sectors per block. The drive supports 1,2,4,8 or16

sectors per block.

Upon receipt of the command, the drive sets BSY=1 and checks the content of Sector Count Register.

If the Sector Count Register contains a valid value and the block count is supported, the value is loaded for

all subsequent Read Multiple and Write Multiple commands. And these commands are enabled to be

executed. If a block count is not supported , this command shall be terminated with the report of an Aborted

Command error , and Read Multiple and Write Multiple commands are disabled.

If the Sector Count Register contains 0 when the command is issued, Read Multiple and Write Multiple

commands are disabled.

In case of software reset, the result depends on the setting of Set Feature command. If FT=66h, the mode

is not changed. If FT = CCh, the mode reverts to power on default (16 sectors).

10.8.18 Read DMA (C8h/C9h)

1 1 0 0 1 0 0 X

COMMAND CODE

NORMAL COMPLETION

no change

drive no.

starting cylinder

starting head

starting sector

last possible

00H

no. of sector to read

no change

LBA

staring address

last address

This command is basically identical to Sector command except following features.

•

Host initialize slave-DMA channel before issuing command.

- Data transfer is initiated by DMARQ and handled by slave-DMA channel in the host.

- Drive issues only one interrupt at the completion of each command to show the status is valid after data

transfer.

During DMA transfer phase, either BSY or DRQ is set to 1.

When a command is completed, CY, HD, SN register (LBA register) shows the sector transferred the latest.

If the drive detects unrecoverable error, the drive terminate the command and CY, HD, SN register (LBA

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10.8.19 Write DMA (CAh/CBh)

1 1 0 0 1 0 1 X

drive no.

starting cylinder

starting head

starting sector

no. of sector to write

COMMAND CODE

NORMAL COMPLETION

no change

last possible

00H

no change

LBA

staring address

last address

This command is basically identical to Sector command except following differences.

•

Host initialize slave-DMA channel before issuing command.

- Data transfer is initiated by DMARQ and handled by slave-DMA channel in the host.

- Drive issue only one interrupt at the completion of each command to show the status is valid after data

transfer.

During DMA transfer phase, either BSY or DRQ is set to 1.

When a command is completed, CY, HD, SN register (LBA register) shows the sector transferred the latest.

If the drive detects unrecoverable error, the drive terminates the command and CY, HD, SN register (LBA register)

shows the sector where error has occurred.

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10.8.20 Power Control (Exh)

1 1 1 0 X X X X

COMMAND CODE

NORMAL COMPLETION

no change

drive no.

no change

shown below

00/FFH (for E5/98 command)

no change (for other command)

no change

Power Control is a group of commands which controls low power mode in the drive. The drive has three

types of power mode:

Idle, Stand-by and Sleep mode

At the completion of disk access, the drive automatically enters the idle mode.

There are two ways to shift to the stand-by mode ( to stop rotation of spindle motor ).

By a command from the host

By internal timer

The internal timer is set by Stand-by or Idle command. The period is equivalent to SC x 5 seconds. If

Stand-by or Idle command is executed when SC=0 and the drive receives no access from host for 45

minutes, the drive automatically enters the stand-by mode.

If the drive receives disk access command from the host when it is in stand-by mode , the spindle starts

rotating and the drive executes read/write operation.

After power on, the spindle starts rotating and enters the idle mode. During idle or stand-by, READY bit is

set and the drive is ready to receive a command.

To be specific , there are four different sub-commands defined by lower 4 bits of command as follows. The

drive is in the idle mode and the auto stand-by ( timer setting:45 min.) when it is in default condition after

power- on.

10.8.20.1 Stand-by Immediate (E0/94)

SC=X (Don't care)

The drive enters the stand-by mode immediately by this command. If the drive is already in the stand-by

mode, it does no-operation and the stand-by timer doesn’t start .The drive issues an interrupt and reports the

host that the command has been completed before it virtually enters the stand-by mode .

10.8.20.2 Idle Immediate (E1/95)

SC=X

The drive enters the idle mode immediately by this command. If the drive is already in the idle mode, it does

no-operation. If stand-by timer is enabled, timer will start. After the drive enters the idle mode, the drive

issues interrupt to report the host that the command has been completed.

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10.8.20.3 Stand-by (E2/96)

When SC = 0, the drive goes into Stand-by mode and then into Idle mode. If the drive receives no access

during specified time period ( see the table below ), the drive enters stand-by mode.

When SC≠0, the drive enters stand-by mode and enables auto stand-by function. The value in SC register

will be converted to auto stand-by timer according to the following table.

Value in SC register

Setting

45 min.

1-255

(SC x 5) sec.

When the specified time period has passed, the drive enters stand-by mode. If a disk access command is

received during stand-by mode, the spindle starts rotating and the drive executes read/write operation. After

completing the command, the drive reset stand-by timer and the timer starts counting down.

10.8.20.4 Idle (E3/97)

When SC = 0, the drive enters Idle mode. If the drive receives no access during specified time period ( see

the table below ), the drive enters stand-by mode.

When SC≠0, the drive goes into idle mode and enables auto stand-by function. The value in SC register is

converted to the value of auto stand-by timer according to the following table.

Value in SC register

Setting

45 min.

1-255

(SC x 5) sec.

When the specified time period has expired, the drive enters the stand-by mode. If disk access command is

received during the stand-by mode, the spindle starts rotating and executes read/write operation. After

completing the command, The drive resets stand-by timer and the timer starts counting down.

Power on default setting is auto stand-by (timer setting:45 min.).

10.8.20.5 Check Power Mode (E5/98)

SC result value=00 indicates that the drive is in stand-by mode or going into stand-by mode or is shifting from

stand-by mode into idle mode.

SC result value=FFH indicates that the drive is in idle mode.

10.8.20.6 Sleep (E6/99)

When SC=X, the drive enters sleep mode immediately. After entering the sleep mode, the drive issues an

interrupt to report the host that the command has been completed. The drive recovers from sleep mode and

enters stand-by mode by receiving a reset.

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10.8.21 Read Buffer (E4h)

1 1 1 0 0 1 0 0

drive no.

COMMAND CODE

NORMAL COMPLETION

no change

00H

no change

This command transfers a specified sector of data ( 512 bytes) from the 128kB buffer in the drive to the host.

When this command is issued, the drive sets BSY, sets up the buffer for read operation, sets DRQ, resets

BSY, and generates an interrupt. The host reads up to 512 bytes of data from the buffer.

10.8.22 Write Buffer (E8h)

1 1 1 0 1 0 0 0

COMMAND CODE

NORMAL COMPLETION

no change

drive no.

no change

00H

no change

This command transfers a sector of data from the host to the specified 512 bytes of 128kB buffer of the

drive . When this command is issued, the drive will set up the buffer for write operation, and set DRQ. The

host may then write up to 512 bytes of data to the buffer.

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10.8.23 Identify Device (ECh)

1 1 1 0 1 1 0 0

drive no.

COMMAND CODE

NORMAL COMPLETION

no change

00H

no change

The identify device command requests the drive to transfer parameter information to the host. When the

command is issued, the drive sets BSY, stores the required parameter information in the sector buffer, sets

the DRQ bit, and issues an interrupt. The host may read the parameter information of the sector buffer. The

parameter words in the buffer are arranged as shown in Table10.8.23-1～3.

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Table 10.8-1 Identify Information

WORD

DESCRIPTION

Hex.

General configuration

0040

14-8

0=ATA device

Reserved

1=Removable cartridge device

1=Fixed device

5-3

1-0

Reserved

Response incomplete

Reserved

Number of default logical cylinders

[1*]

Specific configuration

Number of default logical heads

C837

[2*]

Reserved

0000

[3*]

Number of default logical sectors h logical track

7-9

10-19

Reserved

Serial Number (20 ASCII characters)

Reserved

Number of vendor specific ECC bytes transferred on READ/WRITE LONG

commands

0000

002E

23-26

27-46

Firmware Revision (8 ASCII characters)

Controller model # (40 ASCII characters)

15-8 80h

8010

7-0 00_H= READ/WRITE MULTIPLE command not implemented

01_H- FF_H= Maximum number of sectors that can be transferred per

interrupt

Reserved

Capabilities

15-14 Reserved

on READ/WRITE MULTIPLE commands

0000

0F00

13 1=Standby timer values as specified in ATA/ATAPI-5 specification are

supported

0=Standby timer values are vendor specific

12 Reserved

11 1=IOCHRDY supported

10 1=IOCHRDY can be disabled

7-0

Reserved

Capabilities

4001

0200

0 (Fixed)

1 (Fixed)

13-1

Reserved

1= a device specific Standby timer value minimum.

15-8 PIO data transfer cycle timing mode

7-0 Reserved

Reserved

0000

0007

15-3 Reserved

1=the fields reported word 88 are valid

0=the fields reported word 88 are not valid

1=the fields reported words 64-70 are valid

0=the fields reported words 64-70 are not valid

1=the fields reported words 54-58 are valid

0=the fields reported words 54-58 are not valid

Number of current cylinders

Number of current heads

XXXX

Number of current sectors per track

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Table 10.8-2 Identify Information (Continued)

WORD

DESCRIPTION

Hex.

57-58

Current capacity in sectors

XXXX

(Number of current cylinders * Number of current heads * Number of current

sectors per track)

15-9

Reserved

01XX

1=Multiple sector setting is valid

7-0

XXh=Current setting for number of sectors that can be transferred per

interrupt on R/W Multiple command

60-61

Total number of user addressable sectors (LBA mode only)

[5*]

XX07

15-8

7-0

15-8

7-0

15-8

7-0

Single word DMA transfer mode active

Single word DMA transfer mode supported ¹⁴

Multiword DMA transfer mode active

Multiword DMA transfer mode supported

reserved

XX07

0003

Advanced PIO Transfer Modes Supported

bit 7-2 Reserved

bit 1 = 1 PIO MODE 4 supported

bit 0 = 1 PIO MODE 3 supported

69-79

Minimum Multiword DMA Transfer Cycle Time Per Word (ns)

Manufacturer’s Recommended Multiword DMA Transfer Cycle Time

Minimum PIO Transfer Cycle Time Without Flow Control (ns)

Minimum PIO Transfer Cycle Time With IOCHRDY Flow Control

Reserved (for future command overlap and queuing)

Major version number

0078

0000

003E

0000h or FFFFh = device does not report version

15-4

Reserved for ATA-6~14

1=supports ATA/ATAPI-5

1=supports ATA/ATAPI-4

1=supports ATA-3

1=supports ATA-2

1=supports ATA-1

Reserved

Minor version number

0000h or FFFFh = device does not report version

Command set supported.

0000

7C6B

0000h or FFFFh = command set notification not supported

Reserved

1=NOP command supported

1=READ BUFFER command supported

1=WRITE BUFFER command supported

1=WRITE VERIFY command supported

1=Host Protected Area feature set supported

1=DEVICE RESET command supported

1=SERVICE interrupt supported

1=release interrupt supported

1=look-ahead supported

1=write cache supported

1=supports PACKET Command feature set

1=supports power management feature set

1=supports removable feature set

1=supports security feature set

1=supports SMART feature set

ATA-3 defines this field as “Vendor specific (obsolete)” To maintain compatibility between ATA-2, the drive supports this field as

specified in ATA-2. This field may be used for other purposes in future models.

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Table 10.8-3 Identify Information (Continued)

WORD

DESCRIPTION

Hex.

Command set supported.

0000h or FFFFh = command set notification not supported

4108

0 (Fixed)

1 (Fixed)

13-9

Reserved

1=Set MAX security extension supported

Reserved

1=SET FEATURES subcommand required to spin up after power-up

1=Power-Up in Standby feature set supported

1=Removable Media Status Notification feature set supported

1=Advanced Power Management feature set supported

1=CFA feature set supported

1=READ / WRITE DMA QUEUED supported

1=DOWNLOAD MICROCODE command supported

Command set/feature supported extension

4000

13-0

0 (Fixed)

1 (Fixed)

Reserved

Command set/feature enabled

XXXX

Reserved

1=NOP command supported

1=READ BUFFER command supported

1=WRITE BUFFER command supported

1=WRITE VERIFY command supported

1=Host Protected Area feature set supported

1=DEVICE RESET command supported

1=SERVICE interrupt enabled

1=release interrupt enabled

1=look -ahead enabled

1=write cache enabled

1=supports PACKET Command feature set

1=supports power management feature set

1=supports removable feature set

1=Security feature set enabled

1=SMART feature enabled

Command set/feature enabled

0X0X

15-9

Reserved

1=SET MAX security extension enabled by SET MAX SET

PASSWORD

Reserved

1=SET FEATURES subcommand required to spin-up after power-up

1=Power-Up In Standby feature set enabled

1=Removable Media Status Notification feature set enabled

1=Advanced Power Management feature set enabled

1=CFA feature set supported

1=READ / WRITE DMA QUEUED supported

1=DOWNLOAD MICROCODE command supported

Command set/feature default

4000

0 (Fixed)

1 (Fixed)

13-0 Reserved

15-8

7-0

Ultra DMA transfer mode selected

Ultra DMA transfer modes supported

XX1F

Time required for security erase unit completion

Reserved

Current Advanced Power Management setting

15-8 Reserved

00XX

0000

00XX

7-0 Current Advanced Power Management setting

set by Set Features Command

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360014937

Table 10.8-4 Identify Information (Continued)

WORD

DESCRIPTION

Master Password Revision Code

Hex.

XXXX

Hardware reset result. The conetnts of bits 12-0 of this word shall change only

during the execution of a hardware reset.

XXXX

0 (Fixed)

1 (Fixed)

1=device detected CBLID- above V_IH

0=device detected CBLID- below V_IL

Device 1 hardware reset result. Device 0 shall clear these bits to

zero.

12-8

Device 1 shall set these bits as follows :

Reserved.

0=Device 1 did not assert PDIAG-.

1=Device 1 asserted PDIAG-.

These bits indicate how Device 1 determined the device

number:

10-9

00=Reserved.

01=a jumper was used.

10=the CSEL signal was used.

11=some other method was used or the method is

unknown.

1 (Fixed)

7-0

Device 0 hardware reset result. Device 1 shall clear these bit to

zero.

Device 0 shall set these bills as follows:

Reserved.

0=Device 0 does not respond when Device 1 is selected.

1=Device 0 responds when Device 1 is selected.

0=Device 0 did not detect the assertion of DASP-.

1=Device 0 detected the assertion of DASP-.

0=Device 0 did not detect the assertion of PDIAG-.

1=Device 0 detected the assertion of PDIAG-.

0=Device 0 failed diagnostics.

1=Device 0 passed diagnostics.

These bits indicate how Device 0 determined the device

number:

2-1

00=Reserved.

01=a jumper was used.

10=the CSEL signa was used.

11=some other method was used or the method is

unknown.

1 (Fixed)

94-126

127

Reserved

0000

Removable Media Status Notification feature set supported

15-2 Reserved

1-0 00=Removable Media Status Notification feature set not supported

01=Removable Media Status Notification feature set supported

10=Reserved

11=Reserved

128

Security status

0XXX

15-9

7-6

Reserved

Security level 0=High, 1=Maximum

Reserved

1=Enhanced security erase supported

1=Security count expired

1=Security frozen

1=Security locked

1=Security enabled

1=Security supported

129-254

255

Reserved

Integrity word

0000

XXA5

15-8

7-0

Checksum

Signature

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360014937

Word descriptions:

WORD 0: General configuration

bit 15

bit 14-8

bit 7

bit 6

bit 5-3

0=ATA

Reserved

1=Removable cartridge

1=Fixed disk drive

Reserved

bit

bit 1-0

Response incomplete

Reserved

The value for this WORD is 0040h.

WORD 1: Logical cylinder number that user can access (in default mode) [*1]

WORD 2: Specific configuration

“37C8” : Device requires SET FEATURES subcommand to spin-up after power-up and IDENTIFY DEVICE

response is incomplete.

“738C” : Device requires SET FEATURES subcommand to spin-up after power-up and IDENTIFY DEVICE

response is complete.

“8C73” : Device does not requires SET FEATURES subcommand to spin-up after power-up and IDENTIFY

DEVICE response is incomplete.

“C837” : Device does not requires SET FEATURES subcommand to spin-up after power-up and IDENTIFY

DEVICE response is complete.

“All other valies” : Reserved

Power-up in Standby feature set is not supported.

The value for this WORD is C837h.

WORD 3: Logical head number that user can access (in default mode) [*2]

WORD 4-5: Reserved

WORD 6: The number of logical sector per track (in default mode) [*3]

Default Values : [*1],[*2],[*3]

Drive Type

MK6017MAP

－

[*1] : Word 1 [*2] : Word 3 [*3] : Word 6

12416

－

WORD 7-9: Reserved

WORD 10-19: Serial number

WORD 20-21: Reserved

WORD 22: Number of vendor specific ECC Bytes transferred to READ/WRITE LONG operation.

It is vendor specific ECC transfer length for READ/WRITE LONG commands, specified by SET

FEATURE command with FEATURES RESISTERS = 44H.

The value for this WORD is 002Eh.

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WORD 23-26: Firmware revision ( 8 ASCII characters )

WORD 27-46: Model name (40 ASCII characters)

Drive Type

MK6017MAP

TOSHIBA MK6017MAP_..._

－

“_” indicates ASCII space code.

WORD 47:

bit 15 - 8 shall be set to 80h

bit 7 - 0

Maximum number of sectors that can be transferred per interrupt on READ/WRITE MULTIPLE

commands.

The default value for this WORD is 8010h.

WORD 48: Reserved

WORD 49: Capabilities

bit 15-14 0=Reserved

bit 13

1=Standby timer value shall be as specified in ATA-/ ATAPI-5 specification

0=Standby timer value are vendor specific

Reserved (For advanced PIO mode support)

1=IORDY is supported.

1=IORDY function can be disabled.

shall be set to 1.

bit 12

bit 11

bit 10

bit

shall be set to 1.

bit 7- 0 Reserved

The value for this WORD is 0F00h.

WORD 50: Capabilities

bit 15

bit 14

(Fixed)

bit 13-1

Reserved

bit

1=device has a minimum Standby timer value that is device specific.

Standby timer value is set to 5 minutes or more. The value for this WORD is 4001h.

WORD 51: PIO data transfer cycle timing mode

bit 15- 8

bit 7- 0

PIO data transfer cycle timing mode

Reserved

The value returned in Bits 15-8 should fall into one of the mode 0 through mode.

Note: For backwards compatibility with BIOS written before Word 64 was defined for advanced modes, a

device reports in Word 51 the highest original PIO mode (i.e. PIO mode 0, 1, or 2) it can support.

The value for this WORD is 0200h.

WORD 52: Reserved

WORD 53:

bit15- 3

bit 2

Reserved

1= the fields reported in word

88 is valid

bit 1

1= the fields reported in words 64～70 are valid

bit 0

1= the fields reported in words 54～58 are valid

If the number of heads and sectors exceed the drive parameter, bit 0 and related WORD 54-58 shall be

cleared to 0. The default value for this WORD is 0007h.

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WORD 54: Number of current cylinders defined by INITIALIZE DEVICE PARAMETERS command

WORD 55: Number of current heads defined by INITIALIZE DEVICE PARAMETERS command

WORD 56: Number of current sectors/track defined by INITIALIZE DEVICE PARAMETERS command

WORD 57-58: Total number of sectors calculated by word 54 - 56

bit31-24 by word 58 bit 7- 0

bit23-16 by word 58 bit 15- 8

bit15- 8

bit 7- 0

by word 57 bit 7- 0

by word 57 bit 15- 8

The power on values for each models are.

Drive Type

MK6017MAP

－

[*4] : Word 57 - 58

11,733,120(B30880H)

－

WORD 59:

bit15- 9

Reserved

bit 8

1=bit 7- 0 shows number of sectors for multiple sector operation (multiple sector operation is

enabled by SET MULTIPLE command).

bit 7～0

The number of sectors transferred for XX_H=Write / Read multiple command with 1 Interrupt

( Current value shall be set by SET MULTIPLE command. The default value is 16 ).

The default value for this WORD is 0110h.

WORD 60-61: Maximum number of sectors that user can access in LBA mode

bit31-24

bit23-16

bit15- 8

bit 7- 0

by word 61 bit 7- 0

by word 61 bit 15- 8

by word 60 bit 7- 0

by word 60 bit 15- 8

The power on values for each models are.

Drive Type

MK6017MAP

－

[*5] : Word 60 – 61

11,733,120(B30880H)

－

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WORD 62: Mode information for single word DMA

bit15- 8

bit10

bit 9

bit 8

bit 7- 0

bit 2

Active mode

1=Mode 2 is active

1=Mode 1 is active

1=Mode 0 is active

Supported mode

1=mode 2 is supported

1=mode 1 is supported

1=mode 0 is supported

bit 1

bit 0

Support bit reflects setting by SET FEATURE command.

The default value for this WORD is 0007h.

WORD 63: Mode information for multiword DMA

bit15- 8

bit 10

bit 9

bit 8

bit 7- 0

bit 2

Active mode

1=Mode 2 is active

1=Mode 1 is active

1=Mode 0 is active

Supported mode

1=mode 2 is supported

1=mode 1 is supported

1=mode 0 is supported

bit 1

bit 0

Support bit reflects setting by SET FEATURE command.

The default value for this WORD is 0407h and the default figure is mode 2

WORD 64: Mode information for Advanced PIO transfer

bit 7- 0

bit 1

bit 0

Supported mode

1=mode 4 is supported

1=mode 3 is supported

The value for this WORD is 0003h.

WORD 65: Minimum multiword DMA transfer mode cycle time per word (ns)

If this bit is supported, word 53 bit 1 shall be set. The value for this WORD is 0078h (120ns).

WORD 66: Manufacturer recommended multiword DMA transfer cycle time

If the data transfer is requested in a shorter cycle time than this definition, the data transfer may be kept

pending with DMARQ low because data is not ready. The value for this WORD is 0078h (120ns).

WORD 67: Minimum PIO transfer cycle time without flow control (ns)

The Drive can guarantee correct data transfer without flow control in this cycle time or longer. If this bit is

supported, word 53 bit 1 is to be set. The drives which support PIO mode 3 or higher shall support this field

too. This figure shall not be less than 120. The value for this WORD is 0078h (120ns).

WORD 68: Minimum PIO transfer cycle time with IORDY flow control (ns)

If this bit is supported, word 53 bit 1 is to be set. The drive that support PIO mode 3 or higher shall support

this field too. This figure shall not be less than 120. The value for this WORD is 0078h (120ns).

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360014937

WORD 69-79: Reserved

WORD 80: Major version number

If not 0000h or FFFFh, the device claims compliance with the major version(s) as indicated by bits 1 - 5 being

equal to one. Values other than 0000h and FFFFh are bit significant. Since the ATA standards maintain

downward compatibility, a device may set more than one bit .

WORD 81: Minor version number

If an implementor claims that the revision of the standard they used to guide their implementation does not

need to be reported or if the implementation was based upon a standard prior to this revision of the standard,

Word 81 shall be 0000h or FFFFh.

WORD 82: Command sets supported

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

Reserved

NOP command supported

READ BUFFER command supported

WRITE BUFFER command supported

WRITE VERIFY command supported

Host Protected Area feature set supported

DEVICE RESET command supported

SERVICE interrupt supported

bit 8

bit 7

Release Interrupt supported

bit 6

Look Ahead supported

bit 5

Write Cache supported

bit 4

bit 3

bit 2

bit 1

PACKET feature set supported

The Power Management feature set is supported

The Removable feature set is supported

The security feature set is supported

The SMART feature set is supported

bit 0

The value for this WORD is 7C6Bh.

WORD 83: Features/Command sets supported

bit 15

bit 14

0 (Fixed)

1 (Fixed)

bit 13-9 Reserved

bit 8

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

1=Set MAX security extension supported

Reserved

1=SET FEATURES subcommand required to spin up after power-up

1=Power-Up in Standby feature set supported

1=Removable Media Status Notification feature set supported

Advanced Power Management feature set supported

1=CFA feature set supported

1=READ / WRITE DMA QUEUED supported

1=DOWNLOAD MICROCODE command supported

The value for this WORD is 4108h.

WORD 84: Features / Command sets supported

bit 15

bit 14

bit 13-0

0 (Fixed)

1 (Fixed)

Reserved

The value for this WORD is 4000h.

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WORD 85: Features / Command sets enable

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

Reserved

NOP command supported

READ BUFFER command supported

WRITE BUFFER command supported

WRITE VERIFY command supported

Host Protected Area feature set supported

DEVICE RESET command supported

SERVICE interrupt enabled

bit 8

bit 7

Release Interrupt enabled

bit 6

Look Ahead enabled

bit 5

Write Cache enabled

bit 4

bit 3

bit 2

bit 1

PACKET feature set supported

The Power Management feature set is enabled

The Removable feature set is supported

The security feature set is enabled

The SMART feature set is enabled

bit 0

The default value for this WORD is 7C68h

WORD 86: Features / Command sets enabled

bit 15-9

bit 8

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Reserved

1=SET MAX security extension enabled by SET MAX SET PASSWORD

Reserved

1=SET FEATURES subcommand required to spin-up after power-up

1=Power-Up In Standby feature set enabled

Removable Media Status Notification feature set enabled

Advanced power Management feature set enabled

CFA feature set supported

WRITE / READ DMA QUEUED command supported

DOWNLOAD MICROCODE supported

The default value for this WORD is 0008h.

WORD 87: Features / Command sets enabled

bit 15

bit 14

(Fixed)

bit 13-0 Reserved

The value for this WORD is 4000h.

WORD 88: Mode information for Ultra DMA

The active mode reflects the command change. .

bit 15-8 Active transfer mode

bit 12

bit 11

bit 10

1=Mode 4 is active

1=Mode 3 is active

1=Mode 2 is active

1=Mode 1 is active

1=Mode 0 is active

bit

bit 7-0 Supported mode

bit

1=Mode 4 is supported

1=Mode 3 is supported

1=Mode 2 is supported

1=Mode 1 is supported

1=Mode 0 is supported

The default value for this WORD is 001Fh

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WORD 89: The time period for Security Erase Unit command completion shall be set.

TIMER

ACTUAL VALUE

Not specified

1-254

255

( Timer ×2 ) minuites

> 508 minuites

WORD 90: Reserved

WORD 91: Current Advanced Power Management setting

bit 15-8

bit 7-0

Reserved

Current Advanced Power Management setting set by Set Features Command.

The default value for this WORD is0080h.

WORD 92: Master Password Revision Code

the value of the Master Password Revision Code set when the Master Password was last change. Valid

values are 0001h through FFFEh. A value of 0000h or FFFFh indicates that the Master Password Revision

is not supported.

WORD 93: Hardware configuration test results

bit 15

bit 14

bit 13

(Fixed)

1=device detected CBLID- above V_IH

0=device detected CBLID- below V_IL

bit12-8

Device 1 hardware reset result. Device 0 shall clear these bits to zero.

Device 1 shall set these bits as follows :

Reserved.

0=Device 1 did not assert PDIAG-.

1=Device 1 asserted PDIAG-.

10-9 These bits indicate how Device 1 determined the device number:

00=Reserved.

01=a jumper was used.

10=the CSEL signal was used.

11=some other method was used or the method is unknown.

(Fixed)

bit 7-0

Device 0 hardware reset result. Device 1 shall clear these bit to zero.

Device 0 shall set these bills as follows:

Reserved.

0=Device 0 does not respond when Device 1 is selected.

1=Device 0 responds when Device 1 is selected.

0=Device 0 did not detect the assertion of DASP-.

1=Device 0 detected the assertion of DASP-.

0=Device 0 did not detect the assertion of PDIAG-.

1=Device 0 detected the assertion of PDIAG-.

0=Device 0 failed diagnostics.

1=Device 0 passed diagnostics.

2-1 These bits indicate how Device 0 determined the device number:

00=Reserved.

01=a jumper was used.

10=the CSEL signa was used.

11=some other method was used or the method is unknown.

(Fixed)

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WORD 94-126: Reserved

WORD 127: Removable Media Status Notification feature set supported.

This function is not supported. The value for this WORD is 0000h.

WORD 128: Security status

bit 15-9

bit 8 the security level.

1=the security level is maximum

Reserved

0=the security level is high

bit 5 1=the Enhanced security erase unit feature supported

bit 4 the security count has expired.

1=the security count is expired and SECURITY UNLOCK and SECURITY ERASE UNIT are aborted

until receiving a power-on reset or hard reset.

bit 3 security frozen.

1=the drive is in security frozen mode.

bit 2 security locked.

1=the drive is in security locked mode.

bit 1 security enabled.

1=the security is enabled.

bit 0 security supported.

1=security is supported.

WORD 129-254: Reserved

WORD 255: Integrity word

The data structure checksum is the two s complement of the sum of all bytes in words 0 through 254 and the

byte consisting of bits 7:0 in word 255. Each byte shall be added with unsigned arismetic, and overflow

shall be ignored. The sum of all 512 bytes is zero when the checksum is correct.

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10.8.24 Set Max Address (F9h)

1 1 1 1 1 0 0 1

DRIVE No.

Max. cylinder number

Max. head number

COMMAND CODE

NORMAL COMPLETION

no change

LBA

no change

Max. sector number

00_H/ 01 _H(BITO: reserved bit)

Max. LBA

no change

This command specifies the the maximum address in a range of actual drive capacity. The values set in CY,

HD, SN registers indicate the maximum address that can be accessed. In CHS mode, the value of Read Native

Max Address command should be set in HD, SN register. Otherwise, the value shall be ignored and the value of

Read Max Address command will be used. If an LBA bit (DRV / HD register bit 6) is set, the value in LBA mode

shall be set. If the address exceeding the set value is accessed , “ ABORT ERROR “ error will be reported. This

set value affects the values of WORD 1, 54, 57, 58, 60, 61 of IDENTIFY DEVICE command.

This command shall be immediately preceded by Read Native Max Address command. Otherwise, it will be

terminated with “ ABORT ERROR ” .

If this command is issued twice with a volatile bit set to 1 after power-up or hardware reset, “ID Not Found

error” will be reported.

Volatile bit ( SC register bit 0 ) :

If this command is issued with a volatile bit set to 1, the set value of this command is valid after power-up or

hardware reset.

If this command is issued with a volatile bit cleared to 0, the set value of this command shall be cleared after

hard reset or power-on and the maximam value shall be the last value with a volatile bit set to 1.

10.8.25 Read Native Max Address (F8h)

1 1 1 1 1 0 0 0

DRIVE No.

COMMAND CODE

NORMAL COMPLETION

no change

maximum cylinder number

maximum head number

maximum sector number

maximum LBA

LBA

This command sets the maximum address in CY, HD, SN register. If LBA ( DRV / HD register bit6 ) is set to 1,

the maximum address shall be LBA value.

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10.8.26 Set Features (EFh)

1 1 1 0 1 1 1 1

COMMAND CODE

NORMAL COMPLETION

no change

DRIVE No.

no change

Mode Selection for Data Transfer(*2)

Features(*1)

no change

(*1) Features: FT register defines following selections.

02H

03H

05H

44H

55H

66H

82H

85H

AAH

BBH

CCH

others

Enable write cache feature

Select data transfer mode

Enable advanced power management

ECC length is 46 bytes during Read/Write Long command

Disable read look-ahead feature

Disable reverting to power on defaults by soft reset

Disable write cache feature

Disable advanced power management

Enable read look-ahead feature

ECC length is 4 bytes during Read/Write Long command

Enable reverting to power on defaults by soft reset

Invalid (reporting with Aborted Command Error)

(*2)Mode selection for data transfer is specified in sector count register. Upper 5 bits show transfer mode

and lower 3 bits show mode figure.

PIO default transfer mode

PIO default transfer mode, disable IORDY

PIO flow control transfer mode nnn

Single word DMA mode nnn

Multiword DMA mode nnn

Ultra DMA mode nnn

00000 000

00000 001

00001 nnn

00010 nnn

00100 nnn

01000 nnn

10000 nnn

Reserved

PIO default mode is mode 4 flow control. DMA default mode is Multiword word DMA mode 2.

The level of Advanced Power Management function is set in Sector count register.

C0h-FEh ……

Mode0 (Power save up to Performance Idle)

Mode1 (Power save up to Low Power Idle)

80h-BFh ……

01h-7Fh

00h,FFh

…… Mode2 (Power save up to Standby)

…… Aborted

Transition time of power save is changed dynamically in Mode1 and Mode2 due to Adaptive power control

function. The function level is set to Mode1 when Advanced Power Management function is disabled.

If FT register has any other value, the drive rejects the command with Abort Command error.

Default settings after power on or hard reset are:

Data transfer mode of Multiword DMA mode 2, PIO mode 4 flow control,

4 bytes ECC, look-ahead read enabled, write cache enabled, advanced power management enabled,

READ/WRITE Multiple command enabled (16 sectors)

and reverting to power on defaults by soft reset disabled.

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360014937

10.8.27 SECURITY SET PASSWORD (F1h)

1 1 1 1 0 0 0 1

DRIVE No.

COMMAND CODE

NORMAL COMPLETION

no change

This command requests a transfer of a sector of data from the host including the information specified in the

table below. The function of this command is decided by the transferred data.

Security Set Password information

Word

Content

Control word

Bits 15-9

Bits 8

Reserved

Security level

0=High

1=Maximum

Bits 7-1

Bit 0

Reserved

Identifier

0=set user password

1=set master password

1-16

17-255

Password ( 32 bytes )

Reserved

The settings of the identifier and security level bits interact as shown in the table below.

Identifier and security level

Identifier

User

Level

High

Command result

The password supplied with the command will be saved as the new user password. The

lock function will be enabled by the next power-on. The drive can then be unlocked by either

the user password or the previously set master password.

Master

User

High

Maximum

This combination will set a master password but will not enable the lock function.

The password supplied with the command will be saved as the new user password. The

lock function will be enabled by the next power-on. The drive can only be unlocked by the

user password. The master password previously set is still stored in the drive but will not be

used to unlock the drive.

Master

Maximum

This combination will set a master password but will not enable the lock function

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10.8.28 SECURITY UNLOCK (F2h)

1 1 1 1 0 0 1 0

DRIVE No.

COMMAND CODE

NORMAL COMPLETION

no change

This command requests the host to transfer a sector of data including ones described in the table below .

Security Unlock Information

Word

Content

Control word

Bit 15-1

Bit 0

Reserved

Identifier 0=compare user password

1=compare master password

1-16

17-255

Password (32 bytes)

Reserved

If the Identifier bit is set to master and the drive is in high security level, then the supplied password will be

compared with the stored master password. If the drive is in maximum security level, then the SECURITY

UNLOCK command will be rejected.

If the Identifier bit is set to user, the drive compares the supplied password with the stored user password.

If the drive fails in comparing passwords, then the drive returns an abort error to the host and decrements the

unlock counter. This counter is initially set to five and will be decremented for each mismatched passwords

when SECURITY UNLOCK is issued and the drive is locked. When this counter is zero, SECURITY

UNLOCK and SECURITY ERASE UNIT commands are aborted until the next power-on reset or hard reset.

SECURITY UNLOCK commands issued when the drive is unlocked have no effect on the unlock counter.

10.8.29 SECURITY ERASE PREPARE (F3h)

1 1 1 1 0 0 1 1

DRIVE No.

COMMAND CODE

NORMAL COMPLETION

no change

The SECURITY ERASE PREPARE command must be issued immediately before the SECURITY ERASE

UNIT command to enable the drive erase and unlock. This command can prevent accidental erasure of the

drive.

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10.8.30 SECURITY ERASE UNIT (F4h)

1 1 1 1 0 1 0 0

DRIVE No.

COMMAND CODE

NORMAL COMPLETION

no change

This command must be issued immediately after the SECURITY ERASE PREPARE command.

This command requests to transfer a sector of data from the host including the data specified in the following

table. If the password does not match, the drive rejects the command with an Aborted command error.

Security Erase Unit Information

Word

Content

Control word

Bit 15-1

Bit 0

Reserved

Identifier 0=compare user password

1=compare master password

1-16

17-255

Password (32 bytes)

Reserved

The SECURITY ERASE UNIT command erases all user data. The SECURITY ERASE PREPARE command

must be completed immediately prior to the SECURITY ERASE UNIT command, otherwise, the SECURITY

ERASE UNIT command shall be aborted..

This command disables the drive lock function, however, the master password is still stored internally within

the drive and may be reactivated later when a new user password is set.

10.8.31 SECURITY FREEZE LOCK (F5h)

1 1 1 1 0 1 0 1

DRIVE No.

COMMAND CODE

NORMAL COMPLETION

no change

The SECURITY FREEZE LOCK allows the drive to enter frozen mode. After the completion of this command,

any other commands that update the drive lock functions are rejected. The drive recovers from the frozen

mode by power-on reset or hard reset. If SECURITY FREEZE LOCK is issued when the drive is in frozen

mode, the drive executes the command and remains in frozen mode.

Following commands are rejected when the drive is in SECURITY FREEZE LOCK mode.

•

SECURITY SET PASSWORD

SECURITY UNLOCK

SECURITY DISABLE PASSWORD

SECURITY ERASE UNIT

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10.8.32 SECURITY DISABLE PASSWORD (F6h)

1 1 1 1 0 1 1 0

DRIVE No.

COMMAND CODE

NORMAL COMPLETION

no change

This command can be executed only when the drive is in unlocked mode. When the drive is in locked mode,

the drive rejects the command with an Aborted command error.

The SECURITY DISABLE PASSWORD command requests a transfer of a single sector of data from the host

including the information specified in the following table. Then the drive checks the transferred password. If

the user password or the Master password match the given password, the drive disables the lock function.

This command does not change the Master password which may be reactivated later by setting a user

password.

Security Disable Information

Word

Content

Control word

Bit 15-1

Bit 0

Reserved

Identifier 0=compare user password

1=compare master password

1-16

17-255

Password (32 bytes)

Reserved

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10.8.33 SMART Function Set

This command has a number of separate functions which can be selected via the Feature Register when the

command is issued. The subcommands and their respective codes are listed below.

Subcommand

Code

SMART READ ATTRIBUTE VALUES

SMART READ ATTRIBUTE THRESHOLDS

SMART ENABLE/DISABLE AUTOSAVE

SMART SAVE ATTRIBUTE VALUES

SMART EXECUTE OFF-LINE IMMIDIATE

SMART READ LOG SECTOR

D0h

D1h

D2h

D3h

D4h

D5h

D6h

D8h

D9h

DAh

DBh

SMART WRITE LOG SECTOR

SMART ENABLE OPERATIONS

SMART DISABLE OPERATIONS

SMART RETURN STATUS

SMART ENABLE/DISABLE AUTOMATIC OFF-LINE

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10.8.33.1 SMART Read Attribute values

1 0 1 1 0 0 0 0

COMMAND CODE

NORMAL COMPLETION

no change

DRIVE No.

C24Fh

no change

00h

no change

01h

D0h

This command transfers SMART data as 512 byte data. Upon receipt of this command, the drive sets BSY,

sets the SMART data on the buffer. Then, it sets DRQ, resets BSY, issue an interrupt to report that the drive

is ready to transfer data.

Byte

0-1

Description

Data structure revision number

2-361

362

1st-30th Individual attribute data

Off-line data collection status

Self-test execution status

363

364-365

366

Total time in seconds to complete off-line data collection activity

Reserved

367

Total time in seconds to complete off-line data collection activity

SMART capability

368-369

370

Error logging capability

7=1 Reserved

1= Device error logging supported

371

372

Reserved

Short self-test routine recommended polling time (in minutes)

Extended self-test routine recommended polling time (in

Reserved

373

374-510

511

Data structure Checksum

BYTE 0-1: Data structure revision number

0 0 0 6 h is set

BYTE 2-361: Individual attribute data

The following table defines 12BYTE data for each Attribue data.

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Byte

Description

1-2

Attribute ID number 01 - FFh

Status flag

bit 0 (pre-failure/advisory bit)

bit 0 = 0: If attribute value is less than the threshold, the drive is in advisory

condition.

Product life period may expired.

bit 0 = 1: If attribute value is less than the threshold, the drive is in pre-failure

condition. The drive may have failure.

bit 1 (on-line data collection bit)

bit 1= 0: Attribute value shall be changed during off-line data collection

operation.

bit 1= 1: Attribute value shall be changed during normal operation.

bit 2 (Performance Attribute bit)

bit 3 (Error rate attribute bit)

bit 4 (Event Count Attribute bit)

bit 5 (Self-Preserving Attribute bit)

bit 6-15 Reserved

Attribute value 01h-FDh

00h, FEh, FFh = Not in use

01h = Minimum value

64h = Initial value

Fdh = Maximum value

Worst Ever normalized Attribute Value

( valid values from 01h-FEh )

5-10

Raw Attribute Value

Attribute specific raw data

( FFFFFFh - reserved as saturated value )

Reserved ( 00h )

Attribute Name

Indicates that entry in the data structure is not used

Read Error Rate

Throughput Performance

Spin Up Time

Start/Stop Count

Reallocated Sector Count

Seek Time performance

Power-On hours Count

Spin Retry Count

Drive Power Cycle Count

CRC Error Count

Disk Shift

Loaded Hours

Load Retry Count

Load Friction

Load Cycle Count

Load in Time

Power-off Retract Count

Write Head

199

220

222

223

224

225

226

228

240

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BYTE 362: Off-line data collection status

Value

00h or 80h

01h

Definition

Off-line data collection activity was never started.

Reserved

02h or 82h

03h

Off-line data collection activity was completed without error.

Reserved

04h or 84h

05h or 85h

06h or 86h

07h-FFh

Off-line data collection activity was suspended by an interrupting command from host.

Off-line data collection activity was aborted by an interrupting command from host.

Off-line data collection activity was aborted by the device with a fatal error.

Reserved

BYTE 363: Self-test execution status

The self-test execution status byte reports the execution status of the self-test routine.

Bits 0-3 (Percent Self-Test Remaining) The value in these bits indicates an approximation of the

percent of the self-test routine remaining until completion in ten percent increments. Valid values

are

0 through 9. A value of 0 indicates the self-test routine is complete.

total test time remaining.

A value of 9 indicates 90% of

Bits 4-7 (Self-test Execution Status) The value in these bits indicates the current Self-test

Status .

Execution

Self-test execution status values

Value

Description

The previous self-test routine completed without error or no self-test has ever been run

The self-test routine was aborted by the host

The self-test routine was interrupted by the host with a hard or soft reset

A fatal error or unknown test error occurred while the device was executing its self-test

routineand the device was unable to complete the self-test routine.

The previous self-test completed having a test element that failed and the test element

that failed is not known.

The previous self-test completed having the electrical element of the test failed.

The previous self-test completed having the servo (and/or seek) test element of the test

failed.

8-14

The previous self-test completed having the read element of the test failed.

Reserved.

Self-test routine in progress.

BYTE 364-365: Total time

The time for off-line data collection operation ( sec.)

BYTE 366: Reserve

BYTE 367: Off-line data collection capability

bit 0 (Execute off-line immediate implemented bit)

bit0 = 1

bit0 = 0

SMART EXECUTE OFF-LINE IMMEDIATE command supported.

SMART EXECUTE OFF-LINE IMMEDIATE command NOT supported

This bit is set to 1

bit 1 Reserved

bit 2 (abort/restart off-line by host)

bit2 = 1

bit2 = 0

If another command is issued, off-line data collection operation is aborted.

If another command is issued, off-line data collection operation is interrupted and then

the operation will be continued.

bit 3 (off-line read scanning implemented bit)

If this bit is cleared to zero, the device does not support off-line read scanning. If this bit is set to

one, the device supports off-line read scanning. This bit is set to 1.

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bit 4 (self-test implemented bit)

If this bit is cleared to zero, the device does not implement the Short and Extended self-test routines. If this

bit is set to one, the device implements the Short and Extended self-test routines. This bit is set to 1.

bits 5-7 (reserved).

This bit is set to 1

BYTE 368-369: SMART capability

bit 0 (power mode SMART data saving capabilities bit)

bit0 = 1

bit0 = 0

SMART data is saved before Power save mode changes.

SMART data is NOT saved before Power save mode changes.

This bit shall be set to 1

bit 1 (SMART data autosave after event capability bit)

This bit is fixed to 1

bit 2-15 Reserved

BYTE 370 Reserved

BYTE 372-373: Self-test routine recommended polling time

The self-test routine recommended polling time shall be equal to the number of minutes that is the minimum

recommended time before which the host should first poll for test completion status. Actual test time could

be several times this value. Polling before this time could extend the self-test execution time or abort the test

depending on the state of bit 2 of the off-line data capability bits.

BYTE 374-510: Reserved

BYTE 511: Data structure checksum

Checksum of the first 511 byte

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10.8.33.2 SMART Read Attribute thresholds

1 0 1 1 0 0 0 0

DRIVE No.

COMMAND CODE

NORMAL COMPLETION

no change

C24Fh

no change

00h

no change

01h

D1h

This command transfers attribute thresholds of the drive as 512 byte data.

Upon receipt of the command, the drive sets BSY, sets SMART data on the buffer, then, sets DRQ, resets

BSY and issues an interrupt to report to the host that data transfer is ready.

Byte

0-1

2-361

362-510

511

Descriptions

Data structure revision number

1st-30th Individual attribute threshold data

Reserved

Data structure checksum

BYTE 0-1: Data structure revision number

The value for this byte is 0005h.

BYTE 2-361: Individual attribute threshold data

Individual attribute threshold data consists of 12 byte data. ( See the following fig.)

Byte

Description

Attribute ID number

Attribute Threshold

00h= Always passed

01h= Minimum value

01h - FFh

FDh= Maximum value

FEh, FFh= Not in use

Reserved

2-11

BYTE 362-510: Reserved

BYTE 511: Data structure checksum

The checksum of the first 511 byte.

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10.8.33.3 SMART Enable Disable Attribute Autosave

1 0 1 1 0 0 0 0

DRIVE No.

COMMAND CODE

NORMAL COMPLETION

no change

C24Fh

no change

00h/F1h

D2h

no change

This command enables and disables the attribute autosave function within the drive. This command allow the

drive to automatically save its updated attribute values to the attribute data sector at mode transition or cause

the autosave feature to be disabled. The state of the attribute autosave feature (either enabled or disabled)

will be preserved by the drive across power cycles.

A value of zero written by the host into the drive’s Sector Count register before issuing this command may

disable this function. Disabling this feature does not preclude the drive from saving attribute values to the

attribute data sector during other normal save operations.

A value of F1h written by the host into the drive’s Sector Count register before issuing this command will

cause this function to be enabled. Any other non-zero value written by the host into this register before issuing

this command will not change the state of the attribute autosave feature.

Upon receipt of the command from the host, the drive sets BSY, enables or disables the autosave function ,

clears BSY and asserts INTRQ.

10.8.33.4 SMART Save Attribute Values

1 0 1 1 0 0 0 0

DRIVE No.

COMMAND CODE

NORMAL COMPLETION

no change

C24Fh

no change

D3h

no change

This command immediately saves changed attribute values. Upon receipt of the command, the drive sets BSY,

saves the attribute values, clears BSY and issues an interrupt.

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10.8.33.5 SMART Execute Off-line Immediate

1 0 1 1 0 0 0 0

DRIVE No.

C24Fh

Subcommand specific

D4h

COMMAND CODE

NORMAL COMPLETION

no change

This command causes the device to immediately initiate the activities that collect SMART data in an

off-line mode and then save this data to the device's non-volatile memory, or execute a self-diagnostic test

routine in either captive or off-line mode.

The sector Number register shall be set to specify the operation to be executed.

SMART EXECUTE OFF-LINE IMMEDIATE Sector Number register values

Value

Description of subcommand to be executed

Execute SMART off-line routine immediately in off-line mode

Execute SMART Short self-test routine immediately in off-line mode

Execute SMART Extended self-test routine immediately in off-line mode

Reserved

Abort off-line mode self-test routine

Reserved

Execute SMART Short self-test routine immediately in captive mode

Execute SMART Extended self-test routine immediately in captive mode

3-126

127

128

129

130

131-255 Reserved

10.8.33.5.1 Off-line mode

The following describes the protocol for executing a SMART EXECUTE OFF-LINE IMMEDIATE

subcommand routine (including a self-test routine) in the off-line mode.

a) The device executes command completion before executing the subcommand routine.

b) After clearing BSY to zero and setting DRDY to one after receiving the command, the device shall not set

BSY nor clear DRDY during execution of the subcommand routine.

c) If the device is in the process of performing the subcommand routine and is interrupted by any new

command from the host except a SLEEP, SMART DISABLE OPERATIONS, SMART EXECUTE

OFF-LINE IMMEDIATE, or STANDBY IMMEDIATE command, the device suspends or aborts the

subcommand routine and service the host within two seconds after receipt of the new command. After

servicing the interrupting command from the host the device may immediately re-initiate or resume the

subcommand routine without any additional commands from the host.

d) If the device is in the process of performing a subcommand routine and is interrupted by a SLEEP

command from the host, the device may abort the subcommand routine and execute the SLEEP

command. If the device is in the process of performing any self-test routine and is interrupted by a

SLEEP command from the host, the device shall abort the subcommand routine and execute the SLEEP

command.

e) If the device is in the process of performing the subcommand routine and is interrupted by a SMART

DISABLE OPERATIONS command from the host, the device shall suspend or abort the subcommand

routine and service the host within two seconds after receipt of the command. Upon receipt of the next

SMART ENABLE OPERATIONS command the device may, either re-initiate the subcommand routine or

resume the subcommand routine from where it had been previously suspended.

f) If the device is in the process of performing the subcommand routine and is interrupted by a SMART

EXECUTE OFF-LINE IMMEDIATE command from the host, the device shall abort the subcommand

routine and service the host within two seconds after receipt of the command. The device shall then

service the new SMART EXECUTE OFF-LINE IMMEDIATE subcommand.

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g) If the device is in the process of performing the subcommand routine and is interrupted by a STANDBY

IMMEDIATE or IDLE IMMEDIATE command from the host, the device shall suspend or abort the

subcommand routine, and service the host within two seconds after receipt of the command. After receiving

a new command that causes the device to exit a power saving mode, the device shall initiate or resume the

subcommand routine without any additional commands from the host unless these activities were aborted by

the host.

h) While the device is performing the subcommand routine it shall not automatically change power states (e.g.,

as a result of its Standby timer expiring).

If an error occurs while a device is performing a self-test routine the device may discontinue the testing and place

the test results in the Self-test execution status byte.

10.8.33.5.2 Captive mode

When executing a self-test in captive mode, the device sets BSY to one and executes the self-test routine after

receipt of the command. At the end of the routine the device places the results of this routine in the Self-test

execution status byte and executes command completion. If an error occurs while a device is performing the

routine the device may discontinue its testing, place the results of this routine in the Self-test execution status

byte, and complete the command.

10.8.33.5.3 SMART off-line routine

This routine shall only be performed in the off-line mode. The results of this routine are placed in the Off-line

data collection status byte.

10.8.33.5.4 SMART Short self-test routine

Depending on the value in the Sector Number register, this self-test routine may be performed in either the

captive or the off-line or mode. This self-test routine should take on the order of ones of minutes to complete.

10.8.33.5.5 SMART Extended self-test routine

Depending on the value in the Sector Number register, this self-test routine may be performed in either the

captive or the off-line or mode. This self-test routine should take on the order of tens of minutes to complete.

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10.8.33.6 SMART Read Log Sector

COMMAND CODE

1 0 1 1 0 0 0 0

NORMAL COMPLETION

no change

DRIVE No.

C24Fh

no change

00h

no change

Log Sector Address

01h

D5h

This command returns the indicated log sector contents to the host.

Sector number indicates the log sector to be returned as described in the following Table.

Log Sector

Log sector address

Content

Reserved

SMART error log

Reserved

SMART self-test log

Reserved

Host vendor specific

Reserved

R/W

00h

01h

02h-05h

06h

07h-7Fh

80h-9Fh

A0h-FFh

Key −

RO –Log is read only by the host.

R/W –Log is read or written by the host.

VS –Log is vendor specific thus read/write ability is vendor specific.

10.8.33.6.1 Error log sector

The following Table defines the 512 bytes that make up the SMART error log sector.

SMART error log sector

Byte

Descriptions

SMART error log version

Error log index

2-91

First error log data structure

Second error log data structure

Third error log data structure

Fourth error log data structure

Fifth error log data structure

Device error count

92-181

182-271

272-361

362-451

452-453

454-510

511

Reserved

Data structure checksum

10.8.33.6.2 Error log version

The value of the SMART error log version byte is set to 01h.

10.8.33.6.3 Error log data structure

An error log data structure shall be presented for each of the last five errors reported by the device. These error

log data structure entries are viewed as a circular buffer. That is, the first error shall create the first error log data

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structure; the second error, the second error log structure; etc. The sixth error shall create an error log data

structure that replaces the first error log data structure; the seventh error replaces the second error log structure,

etc. The error log pointer indicates the most recent error log structure. If fewer than five errors have occurred, the

unused error log structure entries shall be zero filled. The following table describes the content of a valid error log

data structure.

Error log data structure

Byte

Descriptions

n –n+11

First command data structure

Second command data structure

Third command data structure

Fourth command data structure

Fifth command data structure

Error data structure

n+12 –n+23

n+24 –n+35

n+36 – n+47

n+48 – n+59

n+60 – n+89

10.8.33.6.4 Command data structure

The fifth command data structure shall contain the command or reset for which the error is being reported. The

fourth command data structure should contain the command or reset that preceded the command or reset for

which the error is being reported, the third command data structure should contain the command or reset

preceding the one in the fourth command data structure, etc. If fewer than four commands and resets preceded

the command or reset for which the error is being reported, the unused command data structures shall be zero

filled, for example, if only three commands and resets preceded the command or reset for which the error is

being reported, the first command data structure shall be zero filled. In some devices, the hardware

implementation may preclude the device from reporting the commands that preceded the command for which the

error is being reported or that preceded a reset. In this case, the command data structures are zero filled.

If the command data structure represents a command or software reset, the content of the command data

structure shall be as shown in the following Table.

Command data structure

Byte

Descriptions

Content of the Device Control register when the Command register was written.

Content of the Features register when the Command register was written.

Content of the Sector Count register when the Command register was written.

Content of the Sector Number register when the Command register was written.

Content of the Cylinder Low register when the Command register was written.

Content of the Cylinder High register when the Command register was written.

Content of the Device/Head register when the Command register was written.

Content written to the Command register.

Timestamp

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

n+9

n+10

n+11

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10.8.33.6.5 Error data structure

The error data structure shall contain the error description of the command for which an error was reported

as described in the following table.

Error data structure

Byte

n+1

n+2

n+3

n+4

n+5

n+6

n+7

Descriptions

Content of the Device Control register after command completion occurred.

Content of the Error register after command completion occurred.

Content of the Sector Count register after command completion occurred.

Content of the Sector Number register after command completion occurred.

Content of the Cylinder Low register after command completion occurred.

Content of the Cylinder High register after command completion occurred.

Content of the Device/Head register after command completion occurred.

Content written to the Status register after command completion occurred.

Extended error information

n+8 - n+26

n+27

n+28

n+29

State

Life timestamp (least significant byte)

Life timestamp (most significant byte)

Extended error information shall be vendor specific.

State shall contain a value indicating the state of the device when command was written to the Command

State field values

Value

x0h

x1h

State

Unknown

Sleep

x2h

Standby

x3h

x4h

x5h-xAh

xBh-xFh

Active/Idle with BSY cleared to zero

Executing SMART off-line or self-test

Reserved

Vendor unique

The value of x is vendor specific and may be different for each state.

Sleep indicates the reset for which the error is being reported was received when the device was in the

Sleep mode.

Standby indicates the command or reset for which the error is being reported was received when the

device was in the Standby mode.

Active/Idle with BSY cleared to zero indicates the command or reset for which the error is being reported

was received when the device was in the Active or Idle mode and BSY was cleared to zero.

Executing SMART off-line or self-test indicates the command or reset for which the error is being reported

was received when the device was in the process of executing a SMART off-line or self-test.

Life timestamp shall contain the power-on lifetime of the device in hours when command completion

occurred.

10.8.33.6.6 Device error count

The device error count field shall contain the total number of errors attributable to the device that have

been reported by the device during the life of the device. These errors shall include UNC errors, IDNF

errors for which the address requested was valid, servo errors, write fault errors, etc. This count shall not

include errors attributed to the receipt of faulty commands such as commands codes not implemented by

the device or requests with invalid parameters or invalid addresses. If the maximum value for this field is

reached, the count shall remain at the maximum value when additional errors are encountered and logged.

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10.8.33.6.7 Data structure checksum

The data structure checksum is the two's complement of the sum of the first 511 bytes in the data structure.

Each byte shall be added with unsigned arithmetic, and overflow shall be ignored. The sum of all 512 bytes will

be zero when the checksum is correct. The checksum is placed in byte 511.

10.8.33.6.8 Self-test log sector

The following Table defines the 512 bytes that make up the SMART self-test log sector.

Self-test log data structure

Byte

0-1

2-25

26-49

.....

Descriptions

Self-test log data structure revision number

First descriptor entry

Second descriptor entry

............

482-505

506-507

508

Twenty-first descriptor entry

Vendor specific

Self-test index

509-510

511

Reserved

Data structure checksum

10.8.33.6.9 Self-test log data structure revision number

The value of the self-test log data structure revision number is set to 0001h.

10.8.33.6.10 Self-test log descriptor entry

This log is viewed as a circular buffer. The first entry shall begin at byte 2, the second entry shall begin at byte

26, and so on until the twenty-second entry, that shall replace the first entry. Then, the twenty-third entry shall

replace the second entry, and so on. If fewer than 21 self-tests have been performed by the device, the unused

descriptor entries shall be filled with zeroes.

The content of the self-test descriptor entry is shown in the following Table.

Self-test log descriptor entry

Byte

Descriptions

Content of the Sector Number

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

Content of the self-test execution status

Life timestamp (least significant byte).

Life timestamp (most significant byte).

Content of the self-test failure checkpoint

Failing LBA(least significant byte).

Failing LBA(next least significant byte).

Failing LBA(next most significant byte).

Failing LBA(most significant byte).

n+9 - n+23 Vendor specific.

Content of the Sector Number register shall be the content of the Sector Number register when the nth self-test

subcommand was issued.

Content of the self-test execution status byte shall be the content of the self-test execution status byte when the

nth self-test was completed

Life timestamp shall contain the power-on lifetime of the device in hours when the nth self-test subcommand was

completed.

Content of the self-test failure checkpoint byte shall be the content of the self-test failure checkpoint byte when

the nth self-test was completed.

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The failing LBA shall be the LBA of the uncorrectable sector that caused the test to fail. If the device

encountered more than one uncorrectable sector during the test, this field shall indicate the LBA of the

first uncorrectable sector encountered. If the test passed or the test failed for some reason other than an

uncorrectable sector, the value of this field is undefined.

10.8.33.6.11 Self-test index

The self-test index shall point to the most recent entry. Initially, when the log is empty, the index shall be

set to zero. It shall be set to one when the first entry is made, two for the second entry, etc., until the 22nd

entry, when the index shall be reset to one.

10.8.33.6.12 Data structure checksum

The data structure checksum is the two's complement of the sum of the first 511 bytes in the data

structure. Each byte shall be added with unsigned arithmetic, and overflow shall be ignored. The sum of

all 512 bytes is zero when the checksum is correct. The checksum is placed in byte 511.

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10.8.33.7 SMART Write Log Sector

1 0 1 1 0 0 0 0

COMMAND CODE

NORMAL COMPLETION

no change

DRIVE No.

C24Fh

no change

00h

no change

Log Sector Address

01h

D6h

This command writes an indicated number of 512 byte data sectors to the indicated log.

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10.8.33.8 SMART Enable Operations

1 0 1 1 0 0 0 0

COMMAND CODE

NORMAL COMPLETION

no change

DRIVE No.

C24Fh

no change

D8h

no change

This command enables access to all SMART capabilities of the drive. Prior to receipt of this command,

Parameters for drive failure prediction are neither monitored nor saved by the drive. The state of SMART

(either enabled or disabled) will be preserved by the drive across power cycles. Once enabled, the receipt of

subsequent SMART ENABLE OPERATIONS commands don’t affect any of the parameters for drive failure

prediction.

Upon receipt of this command from the host, the drive sets BSY, enables SMART capabilities and functions,

clears BSY and asserts INTRQ.

10.8.33.9 SMART Disable Operations

1 0 1 1 0 0 0 0

DRIVE No.

COMMAND CODE

NORMAL COMPLETION

no change

C24Fh

no change

D9h

no change

This command disables all SMART capabilities within the drive including any and all timer functions related

exclusively to this function. After receipt of this command the drive may disable all SMART operations.

Parameters for drive failure prediction will no longer be monitored or saved by the drive. The state of

SMART (either enabled or disabled) will be preserved by the drive across power cycles.

Upon receipt of the SMART DISABLE OPERATIONS command from the host, the drive sets BSY, disables

SMART capabilities and functions, clears BSY and asserts INTRQ.

After receipt of this command by the drive, all other SMART commands, except for SMART ENABLE

OPERATIONS, are disabled and invalid and will be aborted by the drive (including SMART DISABLE

OPERATIONS commands) with an Aborted command error.

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10.8.33.10 SMART Return Status

1 0 1 1 0 0 0 0

COMMAND CODE

NORMAL COMPLETION

no change

DRIVE No.

C24Fh

C24Fh/2CF4h

no change

DAh

If an impending failure is not predicted, the drive sets the Cylinder Low register to 4Fh and the Cylinder High

Cylinder High register to 2Ch.

This command is used to communicate the reliability status of the drive to the host’s request. Upon receipt of

this command the drive sets BSY, saves any parameters monitored by the drive to non-volatile memory and

checks the drive condition.

10.8.33.11 SMART Enable/Disable Automatic Off-line

1 0 1 1 0 0 0 0

DRIVE No.

COMMAND CODE

NORMAL COMPLETION

no change

C24Fh

no change

00h/F8h

DBh

no change

This subcommand enables and disables the optional feature that causes the device to perform the set of off-line

data collection activities that automatically collect attribute data in an off-line mode and then save this data to the

device’s non-volatile memory. This subcommand may either cause the device automatically initiate or resume

performance of its off-line data collection activities; or this command may cause the automatic off-line data

collection feature to be disabled.

A value of zero written by the host into the device’s Sector Count register before issuing this subcommand shall

cause the feature to be disabled. Disabling this feature does not preclude the device from saving attribute values

to non-volatile memory during some other normal operation such as during a power-on or power-off sequence or

during an error recovery sequence.

A value of F8h written by the host into the device’s Sector Count register before issuing this command shall

cause this feature to be enabled. Any other non-zero value written by the host into this register before issuing this

subcommand is vendor specific.

Automatic off-line data collection is executed every 24 power-on hours.

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10.9 Security Mode Feature Set

The Security mode features allow the host to implement a security password system to prevent

unauthorized access to the disk drive.

•

Following Commands are supported for this feature set .

SECURITY SET PASSWORD

SECURITY UNLOCK

SECURITY ERASE PREPARE

SECURITY ERASE UNIT

SECURITY FREEZE LOCK

SECURITY DISABLE PASSWORD

Parameter word for the Security mode feature set is described in IDENTIFY DEVICE response Word 128.

10.9.1 Security mode default setting

The drive is shipped with the master password set to 20h value (ASCII blanks) and the lock function disabled.

The system manufacturer/dealer may set a new master password by using the SECURITY SET PASSWORD

command, without enabling the lock function.

10.9.2 Initial setting of the user password

When a user password is set, the drive automatically enters lock mode by the next powered-on .

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10.9.3 Security mode operation from power-on

In locked mode, the drive rejects media access commands until a SECURITY UNLOCK command is

successfully completed.

Power-on

Locked mode

UNLOCK

ERASE

PREPARE

Media access

Non-media

access

Password

match?

ERASE

UNIT

Reject

Command

Execute

Command

Yes

Unit erased

Unlock

mode

Lock function disabled

Normal operation, all

commands are available

FREEZE LOCK

Normal operation,

Frozen mode commands

are available

Figure 4

Password set security mode power-on flow

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10.9.4 Password lost

If the user password is lost and High level security is set, the drive does not allow the user to access any data.

However, the drive can be unlocked using the master password.

If the user password is lost and Maximum security level is set, it is impossible to access data. However, the

drive can be unlocked using the ERASE UNIT command with the master password. The drive will erase all

user data and unlock the drive.

User password lost

High

Level?

UNLOCK with master password

Normal operation

Maximum

ERASE PREPARE

ERASE UNIT

with master password

Normal operation

but data lost

Figure 5

User password lost

If both the user password and the master password are lost, the drive cannot be in normal operation mode.

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10.9.5 Command Table

This command table shows the drive’s response to commands when the Security Function is enabled.

Table 10.9-1 Security mode command actions

Command

CHECK POWER MODE

EXECUTE DEVICE DIAGNOSTICS

FLUSH CACHE

Locked mode

Unlocked mode

Frozen mode

FORMAT TRACK

IDENTIFY DEVICE

IDLE

IDLE IMMEDIATE

INITIALIZE DEVICE PARAMETERS

NOP

READ BUFFER

READ DMA

READ LONG

READ MULTIPLE

READ NATIVE MAX ADDRESS

READ SECTORS

READ VERIFY

RECALIBRATE

SECURITY DISABLE PASSWORD

SECURITY ERASE PREPARE

SECURITY ERASE UNIT

SECURITY FREEZE LOCK

SECURITY SET PASSWORD

SECURITY UNLOCK

SEEK

SET FEATURES

SET MAX ADDRESS

SET MULTIPLE MODE

SLEEP

SMART

STANDBY

STANDBY IMMEDIATE

WRITE BUFFER

WRITE DMA

WRITE LONG

WRITE MULTIPLE

WRITE SECTORS

WRITE VERIFY

O: Drive executes command normally

X: Drive rejects command with an Aborted command error

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10.10 Self-Monitoring, Analysis and Reporting Technology

Self-monitoring, analysis and reporting technology (SMART) is the function to protect user data and to

minimize the likelihood of unscheduled system downtime that may be caused by predictable degradation

and/or fault of the drive. By monitoring and storing the critical performance and calibration parameters,

SMART drives attempt to predict the likelihood of near-term degradation or fault condition. The host system

warns the user of the impending risk of data loss and advises the user of appropriate action by informing the

host system of the negative reliability .

SMART commands use a single command code and are differentiated by the value placed in the Features

The Commands supported by this feature set are:

•

SMART READ ATTRIBUTE VALUES

SMART READ ATTRIBUTE THRESHOLDS

SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE

SMART EXECUTE OFF-LINE IMMEDIATE

SMART ENABLE OPERATIONS

SMART DISABLE OPERATIONS

SMART RETURN STATUS

10.10.1 Attributes

Attributes are the specific performance or calibration parameters that are used in analyzing the status of the

drive. Attributes are selected by the drive manufacturer based on that attribute’s ability to predict degrading or

faulty conditions for that particular drive. The specific set of attribute being used and the identity of these

attributes is vendor specific and proprietary.

10.10.2 Attributes values

Attribute values are used to measure the relative reliability of individual performance or calibration attributes.

10.10.3 SMART function default setting

The drives are shipped from the drive manufacturer’s factory with the SMART feature disabled. SMART

feature shall be enabled by the system manufacturer or the application.

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10.11 Adaptive Power Mode Control

Adaptive Power Mode Control is a function to reduce power consumption without performance degradation. The

drive supports the following Idle modes of 3 levels. The drive enters into idle mode adaptively in accordance with

the command pattern.

10.11.1 Performance Idle

The drive enters Performance Idle mode at the completion of a command from host. In this mode, electric

circuit and servo is ready to process the next command without delay.

10.11.2 Active Idle

Some of electric circuit and servo functions are powered off in this mode. The heads are stopped near the disk

center . If a shock is detected by Shock Sensor, the drive enters into Performance Idle mode automatically.

Power consumption for Active Idle mode is 55%～65% lower than that of Performance Idle mode. Command

processing time is approximately 35ms longer than that of Performance Idle mode.

10.11.3 Low Power Idle

In Low Power Idle mode, the heads are unloaded on the ramp and the spindle motor continues normal rotation.

Power consumption for Low Power Idle mode is 60%～70% lower than that of Performance Idle mode.

Command processing time is approximately 400ms longer than that of Performance Idle mode.

10.11.4 Transition time

For the current models without Adaptive Power Mode Control, transition time to Idle mode is Timer based. For

the new model, the transition time changes dynamically in accordance with the current command pattern.

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10.12 Reset

A RESET condition sets the drive ( or both drives in case of Master/Slave connection ) BSY, allowing the

drive to perform the specified initialization required for normal operation.

A RESET condition can be generated by both hardware and software. There are two hardware resets, one

is by the Host (- RESET) and the other is by the drive power sense circuitry. These resets are set high

when the system and the drive respectively acknowledge specified supply voltage ( See 6.1).

The other reset is software generated. The Host can write to the Device Control register and set the

reset bit. The host software condition will continue until the reset bit is set to zero.

Once the reset is negated and the drive is re-enabled, with BSY still active, the drive will perform

necessary hardware initialization, clear any previously programmed drive parameters and revert

to the defaults, load the Task File registers with their initial values, and then clear BSY. No interrupt

is generated when initialization is complete. The initial values ( hex ) for the Task File registers are

as follows.

Table 10.12-1 Initialization of Task File registers

POWER ON

HARDWARE RESET

SOFTWARE RESET

Data

Error

Sector Count

Sector Number

Cylinder Low

Cylinder High

Device/Head Register

Status/Alternate Status

Device address¹²

ECC Length

50 or 52

7E or FE

4 bytes

undefined

default

disable

enable

16 sectors

Multiword

DMA mode 2

PIO mode 4

flow control

50 or 52

7E or FE

4 bytes

undefined

default

disable

enable

50 or 52

7E or FE

no change(*1)

no change

no change (*1)

no change(*1)

Data Buffer

Addressing mode

Auto stand-by mode

Read Cache

Write Cache¹³

Multiple mode

DMA transfer mode

16 sectors

Multiword DMA mode

PIO transfer mode

PIO mode 4 flow

control

no change(*1)

(*1): Software reset settings are affected by set feature command.

ATA-2 Notes: This register is obsolete. It is recommended that a device not respond to a read of this address. If a

device does respond, it shall be sure not to drive the DD7 signal to prevent possible conflict with floppy disk

implementations.

The drive supports this register to maintain compatibility for ATA-1.

ATA-2 Notes: The default mode for write cache is “disable” after ATA-2. This is violation of ATA-2 specification. This setting can be

changed by factory.

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10.13 Master/Slave Configuration

Drive address shall be set by the optional jumper of interface connector.

The drive runs as Master drive when the jumper is open or if jumper plug is set to position B-D when

P28(CSEL) signal is low. The drive runs as Slave drive when the jumper plug is inserted into position C-D

or if jumper plug is set to position B-D when P28 (CSEL) signal is high. In case of two- drive

configuration, one shall be Master and the other should be Slave.

ATA /ATAPI specifies to use P28 with jumper plug set to position B-D. It is recommended to follow the

ATA / ATAPI specification.

Jumper

No Jumper

C-D Jumper

B-D Jumper

P28

Drive

Master Drive

Slave Drive

Master Drive

Slave Drive

LOW

HIGH

Prohibit A-B Jumper

Prohibit A-C Jumper

Polarity key

Figure 6 Optional jumper for Master/Slave

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10.14 Cache Memory

10.14.1 Cache Operations

(1) READ CACHE OPERATION

Receiving a read command, the data in the buffer memory are sent to the host without access to the disk

media as long as the object data reside in the buffer memory and the conditions for the drive’s read cache

operation are fulfilled.

If any of the conditions of the read cache operation is not fulfilled, the drive carries out read data operation

and the object data for the read command is read from the media and kept in the buffer and then the data is

transferred from the buffer to the host.

The following data required by the read command may continuously be read by the buffer under the drive’s

read ahead cache operation until the buffer available for read cache is full or the new command is received.

(2) WRITE CACHE OPERATION

Receiving a write command, the drive continuously receives the write data from the host until all data are

transferred or the buffer available for write cache is full, whether the data are written on the media or not. If all

data for the command are received, the drive reports completion of the command by negating BSY bit and

issuing INTERRUPT.

If the command which follows the write cache command is also a write command for succeeding block

address, the drive receives write data from host without waiting for the previously received data to be written

on the media. And the drive reports completion of the command when the buffer receives all the data.

If the command which follows the write cache command is not a write command, or the write command

which writes to non-succeeding block address, the drive waits for all the previously received write cache

command to be written on the media before executing the next command.

During a write cache operation, DASP (LED) signal line is kept “on” until all the data in the write buffer are

written on the media.

10.14.2 Notes for write cache

(1) Loss of data in write buffer

If write cache is enabled, hard reset or soft reset does not cause data loss . But power off immediate after

completion of the command may cause data loss, because actual writing of the data onto the media is not

completed at this moment. Therefore, it is recommended that any other command except write or read

command is executed and completion of the command is confirmed before powering off the drive. Stand-by

command can be helpful for this purpose.

(2) Error report

When write cache is enabled, any unrecoverable error encountered after the report of completion of a

command shall only be reported by the next command. Actual writing of the data onto the media may not be

completed at this moment. In this case, READY bit is negated to show that the error has occurred during

the write cache operation previously executed.

Address validity check is performed with actual media access . The error may be reported during the

execution of a command or after completion of a write cache command if the address the data has tried to

access is non-existent.

10.15 Automatic Write Reallocation

If the drive has difficulty in executing normal write operation due to unrecoverable errors such as ID NOT

FOUND, the sectors those show some errors may be reallocated automatically to continue normal operation

and secure the write data. This operation is helpful especially in write cache, when the completion of the

command is reported before actual writing to media. During write operation including this AWRE function,

DASP signal is kept‘‘ on ’’. This operation takes 20 seconds maximum to be completed, therefore, the

time-out period should be set longer than this value. If the next command is a write command, the data of

the first block will be transferred without any delay.

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11. Protocol

Commands can be grouped into different classes according to the protocols used for command execution.

The command classes with their associated protocols are defined below.

For all commands, the host first checks BSY bit and DRDY bit. If BSY＝1, the host should proceed no further

unless and until the BSY＝0, and the DRDY＝1.

Interrupts are cleared when host reads Status register, issues a reset, or writes to the Command register.

Interrupts are not cleared when host reads Alternate Status register.

A command shall only be interrupted with a hardware or software reset. The result of writing to the

command register while BSY＝1 or DRQ＝1 is unpredictable and may result in data corruption. Therefore,

a command should only be interrupted by a reset at times when the host judges that there is a problem, such

as receiving no response from a drive. Host programmers should set command time-out periods enough

long in order to avoid having effect on the device's ability to perform level retry and data recovery activities.

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11.1 PIO data in commands

Commands for this class are:

•

IDENTIFY DEVICE

READ BUFFER

READ LONG (with and without retry)

READ SECTOR(S) (with and without retry)

READ MULTIPLE

SMART Read Attribute Values

SMART Read Attribute Thresholds

PIO data in protocol:

a) The host writes any required command parameters to the Features, Sector Count, Sector Number, Cylinder

High, Cylinder Low and Device/Head registers.

b) The host writes the command code to the Command register.

c) For each sector ( or block ) of data to be transferred:

1) The drive sets BSY bit and prepares to transfer a sector (or block) of data to the host.

2) When a sector (or block) of data is available for transfer to the host, the drive sets the DRQ bit and clears

the BSY bit and asserts INTRQ.

3) After detecting INTRQ, the host reads the contents of the Status register.

4) The drive negates INTRQ in response to the Status register being read.

5) The host reads a sector (or block) of data via the Data register.

6) In response to a sector (or block) of data being transferred, the drive clears the DRQ bit.

d) For Read Long command, the execution will be as follows.

1) The drive sets the BSY bit and prepares to transfer the data to the host.

2) When a sector (or block) of data is available for transfer to the host, the drive sets the DRQ bit and clears

the BSY bit and asserts INTRQ.

3) After detecting INTRQ, the host reads the Status register.

4) The drive negates INTRQ in response to the Status register being read.

5) The host reads a sector (or block) of data via the Data register.

6) After the sector has been transferred to the host, the drive clears the DRQ bit.

7) When ECC data is available for transfer to the host, the drive sets the DRQ bit and clears the BSY bit.

8) In response to the DRQ bit being set, the host reads ECC data (8 bit) via the Data register.

9) After the ECC data has been transferred to the host, the drive clears the DRQ bit .

The Read Multiple command transfers one block ( the number of sectors defined by the Set Multiple

command ) of data for each interrupt. The other commands transfer one sector of data for each interrupt.

If the drive detects an invalid parameter in register setting, the drive clears BSY bit and sets the ERR bit in

the Status register and sets ABRT bit in the Error register and asserts INTRQ in order to terminate the

command execution.

If an uncorrectable error occurs, the drive will set DRQ bit and clear BSY bit and set ERR bit and stores the

error status in Error register and address the information of the error sector to Sector Number, Cylinder High,

Cylinder Low and Device/Head registers and asserts INTRQ.

If uncorrectable data error ( the UNC is set ) occurs, the drive will transfer a sector of the defective data to

the host. If the others error occur, the contents of the data to be transferred shall not be ensured. In both

cases, the host should complete transfer of the sector of data in response to INTRQ being asserted. In case

of Read Multiple command, the host should complete transfer of a block of data which includes the sector

with defective data.

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11.2 PIO data out commands

Commands for this class are:

•

(FORMAT TRACK)

WRITE BUFFER

WRITE LONG (with and without retry)

WRITE MULTIPLE

WRITE SECTOR(S) (with and without retry)

WRITE VERIFY

SECURITY DISABLE PASSWORD

SECURITY ERASE UNIT

SECURITY SET PASSWORD

SECURITY UNLOCK

PIO data out protocol:

a) The host writes any required command parameters to the Features, Sector Count, Sector Number, Cylinder

High, Cylinder Low and Device/Head registers.

b) The host writes the command code to the Command register.

c) The drive sets the BSY bit .

d) For each sector (or block) of data to be transferred:

1) When the drive is ready to receive a sector (or block) of data from the host, it sets the DRQ bit and clears

the BSY bit.

2) The host writes a sector (or block) of data via the Data Register.

3) After receiving the sector (or block) , the drive clears the DRQ bit and sets the BSY bit.

4) When the drive has finished processing the sector (or block) , it sets the DRQ bit and clears the BSY bit

and asserts INTRQ.

5) After detecting INTRQ, the host reads the Status register.

6) The drive negates INTRQ in response to the Status register being read.

e) For Write Long command, the execution will be as follows.

1) When the drive is ready to receive a sector of data from the host, the drive sets the DRQ bit and clears the

BSY bit.

2) The host writes a sector (or block) of data via the Data Register.

3) After receiving the sector (or block), the drive clears the DRQ bit and sets the BSY bit.

4) After the drive has finished processing the sector (or block) data , it sets the DRQ bit and clears the BSY

bit.

5) In response to the DRQ being set, the host transfers ECC data (8 bit) via the Data register.

6) When drive is ready to receive the data from the host, it sets the BSY bit.

7) When the drive has finished processing ECC data , the drive clears the BSY bit and asserts INTRQ.

8) After detecting INTRQ, the host reads the Status register.

The drive negates INTRQ in response to the Status register being read.

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The Write Multiple command transfers one block ( the number of sectors is defined by the Set Multiple

command ) of data for each interrupt. The other commands transfer one sector of data for each interrupt.

If the drive detects an invalid parameter in register setting, the drive clears the BSY bit and sets the ERR bit

in the Status register and sets the ABRT bit in the Error register and asserts INTRQ to terminate the

command execution.

If an unrecoverable error occurs, the drive sets the DRQ bit and clears the BSY bit and sets the ERR bit and

stores the error status in Error register and report the address information of the sector with error to Sector

Number, Cylinder High, Cylinder Low and Device/Head registers and asserts INTRQ.

11.3 Non-data commands

Commands for this class are:

•

CHECK POWER MODE

EXECUTE DEVICE DIAGNOSTICS

FLUSH CACHE

IDLE

IDLE IMMEDIATE

INITIALIZE DEVICE PARAMETERS

NOP

READ VERIFY SECTOR(S)

READ NATIVE MAX ADDRESS

RECALIBRATE

SEEK

SET FEATURES

SET MAX ADDRESS

SET MULTIPLE MODE

SLEEP

STANDBY

STANDBY IMMEDIATE

SECURITY ERASE PREPARE

SECURITY FREEZE LOCK

SMART Enable/Disable Attribute Autosave

SMART Save Attribute Values

SMART Executive Off-line Immediate

SMART Enable Operation

SMART Disable Operation

SMART Return Status

Non-data protocol:

a) The host writes any required command parameters to the Features, Sector Count, Sector Number, Cylinder

High, Cylinder Low and Device/Head registers.

b) The host writes the command code to the Command register.

c) The drive sets the BSY bit .

d) When the drive has finished processing a sector (or block) of data, it clears the BSY bit and asserts INTRQ.

e) In response to the INTRQ, the host reads the Status register.

f) The drive negates INTRQ in response to the Status register being read

See each command description for error report protocol.

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11.4 DMA data transfer commands

Commands for this class are:

•

READ DMA (with and without retry)

WRITE DMA (with and without retry)

Data transfers using DMA commands differ in two ways from PIO transfers:

data transfers are performed using the slave-DMA channel

the drive issues only one interrupt at the completion of each command

Initiation of the DMA transfer commands is identical to the READ SECTOR(S) or WRITE SECTOR(S)

commands except that the host initializes slave-DMA channel prior to issuing the command.

The interrupt handler for DMA transfers is different in that no intermediate sector interrupts are issued on

multi-sector transfer but issued only once at the completion of each command.

DMA data transfer protocol:

a) Host initializes the slave-DMA channel.

b) Host writes any required command parameters to the Features, Sector Count, Sector Number, Cylinder High,

Cylinder Low and Device/Head registers.

c) Host writes the command code to the Command register.

d) The drive sets the BSY bit .

e) The drive sets DMARQ, when it is ready to transfer data.

f) Host transfers the data using DMA transfer mode set by the Set Features command .

g) When all of the data has been transferred, the drive issues INTRQ.

h) The host resets the slave-DMA channel.

i) After detecting INTRQ, the host reads the Status register.

j) The drive negates INTRQ in response to the Status register being read.

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11.5 Ultra DMA

Ultra DMA protocol is used with Read DMA, and Write DMA commands. Ultra DMA modes are set by Set

features command. Since the setting after power-up ( Default setting ) is mode 2 of Multi Word DMA, Set

Features command shall be issued to be used in Ultra DMA mode.

An Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data out bursts. Each

Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and

the Ultra DMA burst termination phase. An Ultra DMA burst is defined as the period from an assertion of

DMACK- by the host to the subsequent negation of DMACK-. A recipient shall be prepared to receive at

least 2 data words.

Both the host and drive perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA

burst, the drive compares its CRC data to the data sent from the host. The drive requires an Ultra DMA burst

termination for each sector to compare CRC data to the data sent from the host.

1. Initiation phase

a) An Ultra DMA burst initiation phase begins with the assertion of DMARQ by the drive and ends when the

sender generates a STROBE edge to transfer the first data word.

b) An Ultra DMA burst is always requested by a drive asserting DMARQ.

c) A host indicates it is ready to initiate the requested Ultra DMA burst by asserting DMACK-.

d) A host shall never assert DMACK- without first detecting that DMARQ is asserted.

e) For Ultra DMA data in bursts: a drive may begin driving DD(15:0) after detecting that DMACK- is asserted,

STOP negated, and HDMARDY- is asserted.

f) After asserting DMARQ or asserting DDMARDY- for an Ultra DMA data out burst, the shall not negate

either signal until the first STROBE edge is generated.

g) After negating STOP or asserting HDMARDY- for an Ultra DMA data in burst, a host shall not change the

state of either signal until the first STROBE edge is generated.

2. Data transfer phase

a) The data transfer phase is in effect from after Ultra DMA burst initiation until Ultra DMA burst termination.

b) A recipient pauses an Ultra DMA burst by negating DMRDY- and resumes an Ultra DMA burst by

reasserting DMARDY-.

c) A sender pauses an Ultra DMA burst by not generating STROBE edges and resumes by generating

STROBE edges.

d) A recipient must not signal a termination request when a sender stops generating STROBE edges. In the

absence of a termination from the sender, the recipient should always negate DMARDY- and wait the

required period before signaling a termination request.

e) A sender may generate STROBE edges at greater than the minimum period specified by the enabled

Ultra DMA Mode . The sender should not generate STROBE edges at less than the minimum period

specified by the abled Ultra DMA Mode. A recipient should be able to receive data at the minimum period

specified by the enabled Ultra DMA Mode.

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3. Ultra DMA burst termination phase

a) Either a sender or a recipient may terminate an Ultra DMA burst.

b) Ultra DMA burst termination is not the same as command termination or completion. If an Ultra DMA

burst termination occurs before the command is complete, the command shall be completed by

initiation of a new Ultra DMA burst at some later time or aborted by the host issuing a hardware or

software reset to the drive.

c) An Ultra DMA shall be paused before a recipient requests a termination.

d) A host requests a termination by asserting STOP. A drive acknowledges a termination request by

negating DMARQ.

e) A drive requests a termination by negating DMARQ. A host acknowledges a termination request by

asserting STOP.

f) Once a sender requests a termination, it does not change the state of STROBE until the recipient

acknowledges the request. Then, if STROBE is not the asserted state, the sender returns STROBE to

the asserted state. No data shall be transferred on this transition of STROBE.

g) A sender returns STROBE to the asserted state whenever it detects a termination request from the

recipient. No data shall be transferred nor CRC calculated on this edge of DSTROBE.

h) Once a recipient requests a termination, it does not change DMARDY from the negated state for the

remainder of an Ultra DMA burst.

k) A recipient ignores a STROBE edge when DMARQ is negated or STOP is asserted.

CRC

Both the host and drive perform a CRC function during an Ultra DMA burst. the host and drive use 4ABAh

as an initial value. The host and the drive calculate CRC value during each STROBE edge of data transfer

using current value of CRC and transferred data with CRC polynomial. CRC function is not performed after

an Ultra DMA burst completion of STROBE set. At the completion of an Ultra DMA burst, the host reports

the CRC data on data bus and negates DMACK- to pass the result to the drive.

The drive compares the CRC data sent from the host. If the two values do not match, the drive reports an

error after at the end of the command. The generative polynomial for CRC is :

( X ) = X 16 + X 12 + X 5 + 1

The following figure shows an example of CRC generative logic ( ATA / ATAPI-5 )

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360014937

CRCOUT (15:0)

DD(15:0)

CRCIN (15:0:)

f1-f16

Combinational

Logic

Edge

Triggered

Device

Word

Clock

CRCIN0 = f16

CRCIN1 = f15

CRCIN2 = f14

CRCIN3 = f13

CRCIN4 = f12

CRCIN5 = f11 XOR f16

CRCIN6 = f10 XOR f15

CRCIN7 = f9 XOR f14

CRCIN8 = f8 XOR f13

CRCIN9 = f7 XOR f12

CRCIN10 = f6 XOR f11

CRCIN11 = f5 XOR f10

CRCIN12 = f4 XOR f9 XOR f16

CRCIN13 = f3 XOR f8 XOR f15

CRCIN14 = f2 XOR f7 XOR f14

CRCIN15 = f1 XOR f6 XOR f13

f1 = DD0 XOR CRCOUT15

f9 = DD8 XOR CRCOUT7 XOR f5

f2 = DD1 XOR CRCOUT14

f10 = DD9 XOR CRCOUT6 XOR f6

f3 = DD2 XOR CRCOUT13

f11 = DD10 XOR CRCOUT5 XOR f7

f4 = DD3 XOR CRCOUT12

f12 = DD11 XOR CRCOUT4 XOR f1 XOR f8

f13 = DD12 XOR CRCOUT3 XOR f2 XOR f9

f14 = DD13 XOR CRCOUT2 XOR f3 XOR f10

f15 = DD14 XOR CRCOUT1 XOR f4 XOR f11

f16 = DD15 XOR CRCOUT0 XOR f5 XOR f12

f5 = DD4 XOR CRCOUT11 XOR f1

f6 = DD5 XOR CRCOUT10 XOR f2

f7 = DD6 XOR CRCOUT9 XOR f3

f8 = DD7 XOR CRCOUT8 XOR f4

Notes:

1) f = feedback

2) DD = Data to or from the bus

3) CRCOUT = 16-bit edge triggered result (current CRC)

4) CRCOUT(15:0) are sent on matching order bits of DD(15:0)

5) CRCIN = Output of combinatorial logic (next CRC)

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360014937

11.6 Other timings

See HOST INTERFACE section for timings which are not shown here.

Function and Intervals

Timeout

•

POWER ON TIMINGS

From power on to BSY=1

From Power on to BSY=0, DRDY=1

SOFT RESET TIMINGS

From soft reset assertion (SRST=1) to BSY=1

From soft reset negation (SRST=0) to drive ready (BSY=0, DRDY=1)

HARD RESET TIMINGS

From hard reset assertion to BSY=1

From hard reset negation to drive ready (BSY=0, DRDY=1)

DATA IN COMMANDS

400 ns

31 s

maximum

400 ns

10 sec

maximum

400 ns

31 sec

maximum

From writing to command register to BSY=1

From BSY=1 to BSY=0, DRQ=1, INTRQ set (When the drive is in idle mode)

From BSY=1 to BSY=0, DRQ=1, INTRQ set (When the drive is in standby mode)

Drive Busy during data transfer

400 ns

20 sec

35 sec

5 µs

maximum

minimum

•

DATA OUT COMMANDS

From writing to command register to BSY=1

From BSY=1 to BSY=0, DRQ=1

Drive Busy during data transfer

400 ns

5 µs

maximum

minimum

maximum

From BSY=1 to INTRQ set (When the drive is in idle mode)

From BSY=1 to INTRQ set (When the drive is in standby mode)

NON-DATA COMMANDS

From writing to command register to BSY=1

From BSY=1 to INTRQ set (When the drive is in standby mode)

DMA DATA TRANSFER COMMANDS

From writing to command register to BSY=1

10 sec

25 sec

•

400 ns

17 sec

maximum

400 ns

maximum

Table 11.6-1 Other timings.

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