Texas Instruments Network Card TMS320C64x DSP User Manual
TMS320C64x DSP  
Video Port/VCXO Interpolated Control (VIC) Port  
Reference Guide  
Literature Number: SPRU629  
April 2003  
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Preface  
Read This First  
About This Manual  
This document describes the video port and VCXO interpolated control (VIC) port  
in the digital signal processors (DSPs) of the TMS320C6000 DSP family.  
Notational Conventions  
This document uses the following conventions.  
- Hexadecimal numbers are shown with the suffix h. For example, the  
following number is 40 hexadecimal (decimal 64): 40h.  
Related Documentation From Texas Instruments  
The following documents describe the C6000 devices and related support  
tools. Copies of these documents are available on the Internet at www.ti.com.  
Tip: Enter the literature number in the search box provided at www.ti.com.  
TMS320C6000 CPU and Instruction Set Reference Guide (literature  
number SPRU189) describes the TMS320C6000 CPU architecture,  
instruction set, pipeline, and interrupts for these digital signal processors.  
TMS320C6000 Peripherals Reference Guide (literature number SPRU190)  
describes the peripherals available on the TMS320C6000 DSPs.  
TMS320C6000 Technical Brief (literature number SPRU197) gives an  
introduction to the TMS320C62x and TMS320C67x DSPs, develop-  
ment tools, and third-party support.  
TMS320C64x Technical Overview (SPRU395) gives an introduction to the  
TMS320C64x DSP and discusses the application areas that are  
enhanced by the TMS320C64x VelociTI .  
TMS320C6000 Programmer’s Guide (literature number SPRU198)  
describes ways to optimize C and assembly code for the  
TMS320C6000 DSPs and includes application program examples.  
TMS320C6000 Code Composer Studio Tutorial (literature number  
SPRU301) introduces the Code Composer Studio integrated develop-  
ment environment and software tools.  
SPRU629  
Contents  
iii  
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Related Documentation From Texas Instruments / Trademarks  
Code Composer Studio Application Programming Interface Reference  
Guide (literature number SPRU321) describes the Code Composer  
Studio application programming interface (API), which allows you to  
program custom plug-ins for Code Composer.  
TMS320C6x Peripheral Support Library Programmer’s Reference  
(literature number SPRU273) describes the contents of the  
TMS320C6000 peripheral support library of functions and macros. It  
lists functions and macros both by header file and alphabetically,  
provides a complete description of each, and gives code examples to  
show how they are used.  
TMS320C6000 Chip Support Library API Reference Guide (literature  
number SPRU401) describes a set of application programming interfaces  
(APIs) used to configure and control the on-chip peripherals.  
Trademarks  
Code Composer Studio, C6000, C62x, C64x, C67x, TMS320C6000,  
TMS320C62x, TMS320C64x, TMS320C67x, and VelociTI are trademarks of  
Texas Instruments.  
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Contents  
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1  
Provides an overview of the video port peripheral in the digital signal processors (DSPs) of the  
TMS320C6000 DSP family. Included are an overview of the video port functions, FIFO configu-  
rations, and signal mapping.  
1.1  
1.2  
Video Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2  
Video Port FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5  
1.2.1 DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5  
1.2.2 Video Capture FIFO Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6  
1.2.3 Video Display FIFO Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9  
Video Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12  
Video Port Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13  
1.4.1 VDIN Bus Usage for Capture Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15  
1.4.2 VDOUT Data Bus Usage for Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16  
1.3  
1.4  
2
Video Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1  
Discusses the basic operation of the video port. Included is a discussion of the sources and  
typesofresets, interruptoperation, DMAoperation, externalclockinputs, videoportthroughput  
and latency, and the video port control registers.  
2.1  
Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
2.1.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
2.1.2 Peripheral Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
2.1.3 Software Port Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3  
2.1.4 Capture Channel Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3  
2.1.5 Display Channel Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4  
Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5  
DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6  
2.3.1 Capture DMA Event Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6  
2.3.2 Display DMA Event Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8  
2.3.3 DMA Size and Threshold Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10  
2.3.4 DMA Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11  
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12  
Video Port Functionality Subsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12  
2.5.1 Data Bus Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12  
2.5.2 FIFO Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13  
2.2  
2.3  
2.4  
2.5  
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2.6  
Video Port Throughput and Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13  
2.6.1 Video Capture Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13  
2.6.2 Video Display Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15  
Video Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16  
2.7.1 Video Port Control Register (VPCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17  
2.7.2 Video Port Status Register (VPSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20  
2.7.3 Video Port Interrupt Enable Register (VPIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21  
2.7.4 Video Port Interrupt Status Register (VPIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24  
2.7  
3
Video Capture Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1  
Discusses operation of the video capture port.  
3.1  
3.2  
Video Capture Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
BT.656 Video Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3  
3.2.1 BT.656 Capture Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3  
3.2.2 BT.656 Timing Reference Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4  
3.2.3 BT.656 Image Window and Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6  
3.2.4 BT.656 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8  
3.2.5 BT.656 FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9  
Y/C Video Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12  
3.3.1 Y/C Capture Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12  
3.3.2 Y/C Timing Reference Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12  
3.3.3 Y/C Image Window and Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13  
3.3.4 Y/C FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14  
BT.656 and Y/C Mode Field and Frame Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17  
3.4.1 Capture Determination and Notification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17  
3.4.2 Vertical Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19  
3.4.3 Horizontal Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22  
3.4.4 Field Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24  
3.4.5 Short and Long Field Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25  
Video Input Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26  
3.5.1 Input Filter Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26  
3.5.2 Chrominance Resampling Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27  
3.5.3 Scaling Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27  
3.5.4 Edge Pixel Replication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29  
Ancillary Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31  
3.6.1 Horizontal Ancillary (HANC) Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31  
3.6.2 Vertical Ancillary (VANC) Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31  
Raw Data Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32  
3.7.1 Raw Data Capture Notification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32  
3.7.2 Raw Data FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33  
3.3  
3.4  
3.5  
3.6  
3.7  
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3.8  
TSI Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37  
3.8.1 TSI Capture Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37  
3.8.2 TSI Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37  
3.8.3 TSI Capture Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38  
3.8.4 Synchronizing the System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38  
3.8.5 TSI Data Capture Notification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40  
3.8.6 Writing to the FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41  
3.8.7 Reading from the FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42  
Capture Line Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42  
3.9  
3.10 Capturing Video in BT.656 or Y/C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44  
3.10.1 Handling FIFO Overrun in BT.656 or Y/C Mode . . . . . . . . . . . . . . . . . . . . . . . . . 3-45  
3.11 Capturing Video in Raw Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46  
3.11.1 Handling FIFO Overrun Condition in Raw Data Mode . . . . . . . . . . . . . . . . . . . 3-47  
3.12 Capturing Data in TSI Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47  
3.12.1 Handling FIFO Overrun Condition in TSI Capture Mode . . . . . . . . . . . . . . . . . 3-48  
3.13 Video Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49  
3.13.1 Video Capture Channel x Status Register (VCASTAT, VCBSTAT) . . . . . . . . . 3-50  
3.13.2 Video Capture Channel A Control Register (VCACTL) . . . . . . . . . . . . . . . . . . . 3-53  
3.13.3 Video Capture Channel x Field 1 Start Register  
(VCASTRT1, VCBSTRT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58  
3.13.4 Video Capture Channel x Field 1 Stop Register  
(VCASTOP1, VCBSTOP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60  
3.13.5 Video Capture Channel x Field 2 Start Register  
(VCASTRT2, VCBSTRT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61  
3.13.6 Video Capture Channel x Field 2 Stop Register  
(VCASTOP2, VCBSTOP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-62  
3.13.7 Video Capture Channel x Vertical Interrupt Register  
(VCAVINT, VCBVINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63  
3.13.8 Video Capture Channel x Threshold Register  
(VCATHRLD, VCBTHRLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65  
3.13.9 Video Capture Channel x Event Count Register  
(VCAEVTCT, VCBEVTCT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67  
3.13.10 Video Capture Channel B Control Register (VCBCTL) . . . . . . . . . . . . . . . . . . 3-68  
3.13.11 TSI Capture Control Register (TSICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72  
3.13.12 TSI Clock Initialization LSB Register (TSICLKINITL) . . . . . . . . . . . . . . . . . . . . 3-74  
3.13.13 TSI Clock Initialization MSB Register (TSICLKINITM) . . . . . . . . . . . . . . . . . . . 3-75  
3.13.14 TSI System Time Clock LSB Register (TSISTCLKL) . . . . . . . . . . . . . . . . . . . . 3-76  
3.13.15 TSI System Time Clock MSB Register (TSISTCLKM) . . . . . . . . . . . . . . . . . . . 3-77  
3.13.16 TSI System Time Clock Compare LSB Register (TSISTCMPL) . . . . . . . . . . . 3-78  
3.13.17 TSI System Time Clock Compare MSB Register (TSISTCMPM) . . . . . . . . . 3-79  
3.13.18 TSI System Time Clock Compare Mask LSB Register (TSISTMSKL) . . . . . 3-80  
3.13.19 TSI System Time Clock Compare Mask MSB Register (TSISTMSKM) . . . . 3-81  
3.13.20 TSI System Time Clock Ticks Interrupt Register (TSITICKS) . . . . . . . . . . . . . 3-82  
3.14 Video Capture FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83  
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4
Video Display Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1  
Discusses the video display port.  
4.1  
Video Display Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2  
4.1.1 Image Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2  
4.1.2 Video Display Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5  
4.1.3 Sync Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7  
4.1.4 External Sync Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8  
4.1.5 Port Sync Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8  
BT.656 Video Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9  
4.2.1 Display Timing Reference Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9  
4.2.2 Blanking Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12  
4.2.3 BT.656 Image Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12  
4.2.4 BT.656 FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13  
Y/C Video Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16  
4.3.1 Y/C Display Timing Reference Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16  
4.3.2 Y/C Blanking Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17  
4.3.3 Y/C Image Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17  
4.3.4 Y/C FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17  
Video Output Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21  
4.4.1 Output Filter Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21  
4.4.2 Chrominance Resampling Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22  
4.4.3 Scaling Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22  
4.4.4 Edge Pixel Replication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23  
Ancillary Data Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25  
4.5.1 Horizontal Ancillary (HANC) Data Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25  
4.5.2 Vertical Ancillary (VANC) Data Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25  
Raw Data Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25  
4.6.1 Raw Mode RGB Output Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26  
4.6.2 Raw Data FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26  
Video Display Field and Frame Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30  
4.7.1 Display Determination and Notification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30  
4.7.2 Video Display Event Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32  
Display Line Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33  
Display Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35  
4.9.1 Interlaced BT.656 Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35  
4.9.2 Interlaced Raw Display Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39  
4.9.3 Y/C Progressive Display Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43  
4.2  
4.3  
4.4  
4.5  
4.6  
4.7  
4.8  
4.9  
4.10 Displaying Video in BT.656 or Y/C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47  
4.11 Displaying Video in Raw Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49  
4.11.1 Handling Underrun Condition of the Display FIFO . . . . . . . . . . . . . . . . . . . . . . . 4-51  
4.12 Video Display Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52  
4.12.1 Video Display Status Register (VDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53  
4.12.2 Video Display Control Register (VDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55  
4.12.3 Video Display Frame Size Register (VDFRMSZ) . . . . . . . . . . . . . . . . . . . . . . . . 4-60  
4.12.4 Video Display Horizontal Blanking Register (VDHBLNK) . . . . . . . . . . . . . . . . . 4-61  
4.12.5 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) . . . . . . . 4-62  
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4.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) . . . . . . . . 4-64  
4.12.7 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) . . . . . . . 4-65  
4.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) . . . . . . . . 4-67  
4.12.9 Video Display Field 1 Image Offset Register (VDIMGOFF1) . . . . . . . . . . . . . . 4-68  
4.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1) . . . . . . . . . . . . . . . . 4-70  
4.12.11 Video Display Field 2 Image Offset Register (VDIMGOFF2) . . . . . . . . . . . . . . 4-71  
4.12.12 Video Display Field 2 Image Size Register (VDIMGSZ2) . . . . . . . . . . . . . . . . 4-73  
4.12.13 Video Display Field 1 Timing Register (VDFLDT1) . . . . . . . . . . . . . . . . . . . . . . 4-74  
4.12.14 Video Display Field 2 Timing Register (VDFLDT2) . . . . . . . . . . . . . . . . . . . . . . 4-75  
4.12.15 Video Display Threshold Register (VDTHRLD) . . . . . . . . . . . . . . . . . . . . . . . . . 4-76  
4.12.16 Video Display Horizontal Synchronization Register (VDHSYNC) . . . . . . . . . 4-78  
4.12.17 Video Display Field 1 Vertical Synchronization Start Register  
(VDVSYNS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-79  
4.12.18 Video Display Field 1 Vertical Synchronization End Register  
(VDVSYNE1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80  
4.12.19 Video Display Field 2 Vertical Synchronization Start Register  
(VDVSYNS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-81  
4.12.20 Video Display Field 2 Vertical Synchronization End Register  
(VDVSYNE2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82  
4.12.21 Video Display Counter Reload Register (VDRELOAD) . . . . . . . . . . . . . . . . . . 4-83  
4.12.22 Video Display Display Event Register (VDDISPEVT) . . . . . . . . . . . . . . . . . . . 4-84  
4.12.23 Video Display Clipping Register (VDCLIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-85  
4.12.24 Video Display Default Display Value Register (VDDEFVAL) . . . . . . . . . . . . . . 4-86  
4.12.25 Video Display Vertical Interrupt Register (VDVINT) . . . . . . . . . . . . . . . . . . . . . 4-88  
4.12.26 Video Display Field Bit Register (VDFBIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89  
4.12.27 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) . . . . . . . . . . 4-90  
4.12.28 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) . . . . . . . . . . 4-92  
4.13 Video Display Registers Recommended Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94  
4.14 Video Display FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96  
5
General Purpose I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1  
Signals not used for video display or video capture can be used as general-purpose I/O signals.  
5.1  
GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2  
5.1.1 Video Port Peripheral Identification Register (VPPID) . . . . . . . . . . . . . . . . . . . . . 5-3  
5.1.2 Video Port Peripheral Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4  
5.1.3 Video Port Pin Function Register (PFUNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6  
5.1.4 Video Port Pin Direction Register (PDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8  
5.1.5 Video Port Pin Data Input Register (PDIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11  
5.1.6 Video Port Pin Data Output Register (PDOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 5-13  
5.1.7 Video Port Pin Data Set Register (PDSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15  
5.1.8 Video Port Pin Data Clear Register (PDCLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17  
5.1.9 Video Port Pin Interrupt Enable Register (PIEN) . . . . . . . . . . . . . . . . . . . . . . . . 5-19  
5.1.10 Video Port Pin Interrupt Polarity Register (PIPOL) . . . . . . . . . . . . . . . . . . . . . . 5-21  
5.1.11 Video Port Pin Interrupt Status Register (PISTAT) . . . . . . . . . . . . . . . . . . . . . . . 5-23  
5.1.12 Video Port Pin Interrupt Clear Register (PICLR) . . . . . . . . . . . . . . . . . . . . . . . . 5-25  
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6
VCXO Interpolated Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1  
Provides an overview of the VCXO interpolated control (VIC) port.  
6.1  
6.2  
6.3  
6.4  
6.5  
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2  
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3  
Operational Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3  
Enabling VIC Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5  
VIC Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5  
6.5.1 VIC Control Register (VICCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6  
6.5.2 VIC Input Register (VICIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8  
6.5.3 VIC Clock Divider Register (VICDIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9  
A
Video Port Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1  
Describes how to configure the video port in different modes with the help of examples. All  
examples in this appendix use the video port Chip Support Library (CSL).  
A.1 Example 1: Noncontinuous Frame Capture for 525/60 Format . . . . . . . . . . . . . . . . . . . . A-2  
A.2 Example 2: Noncontinuous Frame Display for 525/60 Format . . . . . . . . . . . . . . . . . . . . A-10  
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Figures  
1–1  
1–2  
1–3  
1–4  
1–5  
1–6  
1–7  
1–8  
1–9  
Video Port Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4  
BT.656 Video Capture FIFO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6  
8/10-Bit Raw Video Capture and TSI Video Capture FIFO Configuration . . . . . . . . . . . . . . 1-7  
Y/C Video Capture FIFO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8  
16/20-Bit Raw Video Capture FIFO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9  
BT.656 Video Display FIFO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9  
8/10-Bit Raw Video Display FIFO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10  
8/10 Bit Locked Raw Video Display FIFO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11  
16/20-Bit Raw Video Display FIFO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11  
1–10 Y/C Video Display FIFO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12  
2–1  
2–2  
2–3  
2–4  
2–5  
2–6  
3–1  
3–2  
3–3  
3–4  
3–5  
3–6  
3–7  
3–8  
3–9  
Capture DMA Event Generation Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7  
Display DMA Event Generation Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9  
Video Port Control Register (VPCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17  
Video Port Status Register (VPSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20  
Video Port Interrupt Enable Register (VPIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21  
Video Port Interrupt Status Register (VPIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24  
Video Capture Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7  
8-Bit BT.656 FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9  
10-Bit BT.656 FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10  
10-Bit BT.656 Dense FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11  
8-Bit Y/C FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14  
10-Bit Y/C FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15  
10-Bit Y/C Dense FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16  
VCOUNT Operation Example (EXC = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21  
HCOUNT Operation Example (EXC = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23  
3–10 HCOUNT Operation Example (EXC = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23  
3–11 Field 1 Detection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25  
3–12 Chrominance Resampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27  
3–13 1/2 Scaled Co-Sited Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28  
3–14 1/2 Scaled Chrominance Resampled Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28  
3–15 Edge Pixel Replication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29  
3–16 Capture Window Not Requiring Edge Pixel Replication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30  
3–17 8-Bit Raw Data FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34  
3–18 10-Bit Raw Data FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34  
3–19 10-Bit Dense Raw Data FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35  
3–20 16-Bit Raw Data FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35  
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3–21 20-Bit Raw Data FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36  
3–22 Parallel TSI Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38  
3–23 Program Clock Reference (PCR) Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39  
3–24 System Time Clock Counter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39  
3–25 TSI FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41  
3–26 TSI Timestamp Format (Little Endian) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41  
3–27 TSI Timestamp Format (Big Endian) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42  
3–28 Capture Line Boundary Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43  
3–29 Video Capture Channel x Status Register (VCASTAT, VCBSTAT) . . . . . . . . . . . . . . . . . . . 3-50  
3–30 Video Capture Channel A Control Register (VCACTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53  
3–31 Video Capture Channel x Field 1 Start Register (VCASTRT1, VCBSTRT1) . . . . . . . . . . 3-58  
3–32 Video Capture Channel x Field 1 Stop Register (VCASTOP1, VCBSTOP1) . . . . . . . . . . 3-60  
3–33 Video Capture Channel x Field 2 Start Register (VCASTRT2, VCBSTRT2) . . . . . . . . . . 3-61  
3–34 Video Capture Channel x Field 2 Stop Register (VCASTOP2, VCBSTOP2) . . . . . . . . . . 3-62  
3–35 Video Capture Channel x Vertical Interrupt Register (VCAVINT, VCBVINT) . . . . . . . . . . 3-63  
3–36 Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD) . . . . . . . . . . . . 3-66  
3–37 Video Capture Channel x Event Count Register (VCAEVTCT, VCBEVTCT) . . . . . . . . . . 3-67  
3–38 Video Capture Channel B Control Register (VCBCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68  
3–39 TSI Capture Control Register (TSICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72  
3–40 TSI Clock Initialization LSB Register (TSICLKINITL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74  
3–41 TSI Clock Initialization MSB Register (TSICLKINITM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75  
3–42 TSI System Time Clock LSB Register (TSISTCLKL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76  
3–43 TSI System Time Clock MSB Register (TSISTCLKM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77  
3–44 TSI System Time Clock Compare LSB Register (TSISTCMPL) . . . . . . . . . . . . . . . . . . . . . 3-78  
3–45 TSI System Time Clock Compare MSB Register (TSISTCMPM) . . . . . . . . . . . . . . . . . . . . 3-79  
3–46 TSI System Time Clock Compare Mask LSB Register (TSISTMSKL) . . . . . . . . . . . . . . . 3-80  
3–47 TSI System Time Clock Compare Mask MSB Register (TSISTMSKM) . . . . . . . . . . . . . . 3-81  
3–48 TSI System Time Clock Ticks Interrupt Register (TSITICKS) . . . . . . . . . . . . . . . . . . . . . . . 3-82  
4–1  
4–2  
4–3  
4–4  
4–5  
4–6  
4–7  
4–8  
4–9  
NTSC Compatible Interlaced Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3  
SMPTE 296M Compatible Progressive Scan Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3  
Interlaced Blanking Intervals and Video Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4  
Progressive Blanking Intervals and Video Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5  
Horizontal Blanking and Horizontal Sync Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6  
Vertical Blanking, Sync and Even/Odd Frame Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . 4-7  
Video Display Module Synchronization Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8  
BT.656 Output Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9  
525/60 BT.656 Horizontal Blanking Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9  
4–10 625/50 BT.656 Horizontal Blanking Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10  
4–11 Digital Vertical F and V Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11  
4–12 8-Bit BT.656 FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13  
4–13 10-Bit BT.656 FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14  
4–14 BT.656 Dense FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15  
4–15 Y/C Horizontal Blanking Timing (BT.1120 60I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16  
4–16 8-Bit Y/C FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18  
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Figures  
4–17 10-Bit Y/C FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19  
4–18 10-Bit Y/C Dense FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20  
4–19 Chrominance Resampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22  
4–20 2x Co-Sited Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23  
4–21 2x Interspersed Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23  
4–22 Output Edge Pixel Replication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23  
4–23 Luma Edge Replication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24  
4–24 Interspersed Chroma Edge Replication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24  
4–25 8-Bit Raw FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26  
4–26 10-Bit Raw FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27  
4–27 10-Bit Raw Dense FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27  
4–28 16-Bit Raw FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28  
4–29 20-Bit Raw FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28  
4–30 8-Bit Raw 3/4 FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29  
4–31 10-Bit Raw 3/4 FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29  
4–32 Display Line Boundary Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34  
4–33 BT.656 Interlaced Display Horizontal Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36  
4–34 BT.656 Interlaced Display Vertical Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38  
4–35 Raw Interlaced Display Horizontal Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40  
4–36 Raw Interlaced Display Vertical Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42  
4–37 Y/C Progressive Display Horizontal Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44  
4–38 Y/C Progressive Display Vertical Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-46  
4–39 Video Display Status Register (VDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53  
4–40 Video Display Control Register (VDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55  
4–41 Video Display Frame Size Register (VDFRMSZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60  
4–42 Video Display Horizontal Blanking Register (VDHBLNK) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-61  
4–43 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) . . . . . . . . . . . . . . . . . 4-63  
4–44 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) . . . . . . . . . . . . . . . . . 4-64  
4–45 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) . . . . . . . . . . . . . . . . . 4-66  
4–46 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) . . . . . . . . . . . . . . . . . 4-67  
4–47 Video Display Field 1 Image Offset Register (VDIMGOFF1) . . . . . . . . . . . . . . . . . . . . . . . 4-69  
4–48 Video Display Field 1 Image Size Register (VDIMGSZ1) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-70  
4–49 Video Display Field 2 Image Offset Register (VDIMGOFF2) . . . . . . . . . . . . . . . . . . . . . . . 4-71  
4–50 Video Display Field 2 Image Size Register (VDIMGSZ2) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-73  
4–51 Video Display Field 1 Timing Register (VDFLDT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74  
4–52 Video Display Field 2 Timing Register (VDFLDT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-75  
4–53 Video Display Threshold Register (VDTHRLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-76  
4–54 Video Display Horizontal Synchronization Register (VDHSYNC) . . . . . . . . . . . . . . . . . . . . 4-78  
4–55 Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1) . . . . . . . . . . 4-79  
4–56 Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) . . . . . . . . . . 4-80  
4–57 Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2) . . . . . . . . . . 4-81  
4–58 Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) . . . . . . . . . . 4-82  
4–59 Video Display Counter Reload Register (VDRELOAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-83  
4–60 Video Display Display Event Register (VDDISPEVT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-84  
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4–61 Video Display Clipping Register (VDCLIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-85  
4–62 Video Display Default Display Value Register (VDDEFVAL) . . . . . . . . . . . . . . . . . . . . . . . . 4-86  
4–63 Video Display Default Display Value Register (VDDEFVAL)—Raw Data Mode . . . . . . . 4-87  
4–64 Video Display Vertical Interrupt Register (VDVINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-88  
4–65 Video Display Field Bit Register (VDFBIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-89  
4–66 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) . . . . . . . . . . . . . . . . . . . . . 4-90  
4–67 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) . . . . . . . . . . . . . . . . . . . . . 4-92  
5–1  
5–2  
5–3  
5–4  
5–5  
5–6  
5–7  
5–8  
5–9  
Video Port Peripheral Identification Register (VPPID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3  
Video Port Peripheral Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4  
Video Port Pin Function Register (PFUNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6  
Video Port Pin Direction Register (PDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8  
Video Port Pin Data Input Register (PDIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11  
Video Port Pin Data Output Register (PDOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13  
Video Port Pin Data Set Register (PDSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15  
Video Port Pin Data Clear Register (PDCLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17  
Video Port Pin Interrupt Enable Register (PIEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19  
5–10 Video Port Pin Interrupt Polarity Register (PIPOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21  
5–11 Video Port Pin Interrupt Status Register (PISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23  
5–12 Video Port Pin Interrupt Clear Register (PICLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25  
6–1  
6–2  
6–3  
6–4  
6–5  
TSI System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2  
Program Clock Reference (PCR) Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3  
VIC Control Register (VICCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6  
VIC Input Register (VICIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8  
VIC Clock Divider Register (VICDIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9  
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Tables  
1–1  
1–2  
1–3  
1–4  
2–1  
2–2  
2–3  
2–4  
2–5  
2–6  
2–7  
2–8  
2–9  
3–1  
3–2  
3–3  
3–4  
3–5  
3–6  
3–7  
3–8  
3–9  
Video Capture Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13  
Video Display Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14  
VDIN Data Bus Usage for Capture Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15  
VDOUT Data Bus Usage for Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16  
Video Port Functional Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12  
Y/C Video Capture FIFO Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14  
Raw Video Display FIFO Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15  
Video Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16  
Video Port Control Register (VPCTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17  
Video Port Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19  
Video Port Status Register (VPSTAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20  
Video Port Interrupt Enable Register (VPIE) Field Descriptions . . . . . . . . . . . . . . . . . . . . . 2-21  
Video Port Interrupt Status Register (VPIS) Field Descriptions . . . . . . . . . . . . . . . . . . . . . 2-24  
Video Capture Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
BT.656 Video Timing Reference Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4  
BT.656 Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5  
Error Correction by Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5  
Common Video Source Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7  
BT.656 and Y/C Mode Capture Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18  
Vertical Synchronization Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20  
Horizontal Synchronization Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22  
Field Identification Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24  
3–10 Input Filter Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26  
3–11 Raw Data Mode Capture Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33  
3–12 TSI Capture Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40  
3–13 Video Capture Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49  
3–14 Video Capture Channel x Status Register (VCxSTAT) Field Descriptions . . . . . . . . . . . . 3-51  
3–15 Video Capture Channel A Control Register (VCACTL) Field Descriptions . . . . . . . . . . . . 3-53  
3–16 Video Capture Channel x Field 1 Start Register (VCxSTRT1) Field Descriptions . . . . . . 3-59  
3–17 Video Capture Channel x Field 1 Stop Register (VCxSTOP1) Field Descriptions . . . . . . 3-60  
3–18 Video Capture Channel x Field 2 Start Register (VCxSTRT2) Field Descriptions . . . . . . 3-61  
3–19 Video Capture Channel x Field 2 Stop Register (VCxSTOP2) Field Descriptions . . . . . . 3-62  
3–20 Video Capture Channel x Vertical Interrupt Register (VCxVINT) Field Descriptions . . . . 3-64  
3–21 Video Capture Channel x Threshold Register (VCxTHRLD) Field Descriptions . . . . . . . 3-66  
3–22 Video Capture Channel x Event Count Register (VCxEVTCT) Field Descriptions . . . . . 3-67  
3–23 Video Capture Channel B Control Register (VCBCTL) Field Descriptions . . . . . . . . . . . . 3-68  
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3–24 TSI Capture Control Register (TSICTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 3-73  
3–25 TSI Clock Initialization LSB Register (TSICLKINITL) Field Descriptions . . . . . . . . . . . . . 3-74  
3–26 TSI Clock Initialization MSB Register (TSICLKINITM) Field Descriptions . . . . . . . . . . . . 3-75  
3–27 TSI System Time Clock LSB Register (TSISTCLKL) Field Descriptions . . . . . . . . . . . . . . 3-76  
3–28 TSI System Time Clock MSB Register (TSISTCLKM) Field Descriptions . . . . . . . . . . . . 3-77  
3–29 TSI System Time Clock Compare LSB Register (TSISTCMPL) Field Descriptions . . . . 3-78  
3–30 TSI System Time Clock Compare MSB Register (TSISTCMPM) Field Descriptions . . . 3-79  
3–31 TSI System Time Clock Compare Mask LSB Register (TSISTMSKL)  
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80  
3–32 TSI System Time Clock Compare Mask MSB Register (TSISTMSKM)  
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81  
3–33 TSI System Time Clock Ticks Interrupt Register (TSITICKS) Field Descriptions . . . . . . 3-82  
3–34 Video Capture FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83  
3–35 Video Capture FIFO Registers Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83  
4–1  
4–2  
4–3  
4–4  
4–5  
4–6  
4–7  
4–8  
4–9  
Video Display Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2  
BT.656 Frame Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10  
Output Filter Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21  
Display Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31  
Video Display Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52  
Video Display Status Register (VDSTAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . 4-54  
Video Display Control Register (VDCTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 4-55  
Video Display Frame Size Register (VDFRMSZ) Field Descriptions . . . . . . . . . . . . . . . . . 4-60  
Video Display Horizontal Blanking Register (VDHBLNK) Field Descriptions . . . . . . . . . . 4-62  
4–10 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)  
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63  
4–11 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)  
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65  
4–12 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2)  
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-66  
4–13 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)  
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68  
4–14 Video Display Field 1 Image Offset Register (VDIMGOFF1) Field Descriptions . . . . . . . 4-69  
4–15 Video Display Field 1 Image Size Register (VDIMGSZ1) Field Descriptions . . . . . . . . . . 4-70  
4–16 Video Display Field 2 Image Offset Register (VDIMGOFF2) Field Descriptions . . . . . . . 4-72  
4–17 Video Display Field 2 Image Size Register (VDIMGSZ2) Field Descriptions . . . . . . . . . . 4-73  
4–18 Video Display Field 1 Timing Register (VDFLDT1) Field Descriptions . . . . . . . . . . . . . . . 4-74  
4–19 Video Display Field 2 Timing Register (VDFLDT2) Field Descriptions . . . . . . . . . . . . . . . 4-75  
4–20 Video Display Threshold Register (VDTHRLD) Field Descriptions . . . . . . . . . . . . . . . . . . 4-77  
4–21 Video Display Horizontal Synchronization Register (VDHSYNC) Field Descriptions . . . 4-78  
4–22 Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1)  
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-79  
4–23 Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)  
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80  
4–24 Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2)  
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-81  
4–25 Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2)  
Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82  
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4–26 Video Display Counter Reload Register (VDRELOAD) Field Descriptions . . . . . . . . . . . . 4-83  
4–27 Video Display Display Event Register (VDDISPEVT) Field Descriptions . . . . . . . . . . . . . 4-84  
4–28 Video Display Clipping Register (VDCLIP) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . 4-85  
4–29 Video Display Default Display Value Register (VDDEFVAL) Field Descriptions . . . . . . . 4-87  
4–30 Video Display Vertical Interrupt Register (VDVINT) Field Descriptions . . . . . . . . . . . . . . . 4-88  
4–31 Video Display Field Bit Register (VDFBIT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . 4-89  
4–32 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) Field Descriptions . . . . 4-91  
4–33 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) Field Descriptions . . . . 4-93  
4–34 Video Display Register Recommended Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94  
4–35 Video Display FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96  
4–36 Video Display FIFO Registers Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96  
5–1  
5–2  
5–3  
5–4  
5–5  
5–6  
5–7  
5–8  
5–9  
Video Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2  
Video Port Peripheral Identification Register (VPPID) Field Descriptions . . . . . . . . . . . . . . 5-3  
Video Port Peripheral Control Register (PCR) Field Descriptions . . . . . . . . . . . . . . . . . . . . 5-5  
Video Port Pin Function Register (PFUNC) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . 5-6  
Video Port Pin Direction Register (PDIR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 5-8  
Video Port Pin Data Input Register (PDIN) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . 5-12  
Video Port Pin Data Out Register (PDOUT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . 5-14  
Video Port Pin Data Set Register (PDSET) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . 5-16  
Video Port Pin Data Clear Register (PDCLR) Field Descriptions . . . . . . . . . . . . . . . . . . . . 5-18  
5–10 Video Port Pin Interrupt Enable Register (PIEN) Field Descriptions . . . . . . . . . . . . . . . . . 5-20  
5–11 Video Port Pin Interrupt Polarity Register (PIPOL) Field Descriptions . . . . . . . . . . . . . . . . 5-22  
5–12 Video Port Pin Interrupt Status Register (PISTAT) Field Descriptions . . . . . . . . . . . . . . . . 5-24  
5–13 Video Port Pin Interrupt Clear Register (PICLR) Field Descriptions . . . . . . . . . . . . . . . . . 5-26  
6–1  
6–2  
6–3  
6–4  
6–5  
6–6  
VIC Port Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3  
Example Values for Interpolation Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4  
VIC Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5  
VIC Control Register (VICCTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6  
VIC Input Register (VICIN) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8  
VIC Clock Divider Register (VICDIV) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9  
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Chapter 1  
Overview  
This chapter provides an overview of the video port peripheral in the digital  
signal processors (DSPs) of the TMS320C6000 DSP family. Included are an  
overview of the video port functions, FIFO configurations, and signal mapping.  
Topic  
Page  
1.1 Video Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2  
1.2 Video Port FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5  
1.3 Video Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12  
1.4 Video Port Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13  
1-1  
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Video Port  
1.1 Video Port  
The video port peripheral can operate as a video capture port, video display  
port, or transport stream interface (TSI) capture port. It provides the following  
functions:  
- Video capture mode:  
J
J
Capture rate up to 80 MHz.  
Two channels of 8/10-bit digital video input from a digital camera or  
analog camera (using a video decoder). Digital video input is in YCbCr  
4:2:2 format with 8-bit or 10-bit resolution multiplexed in ITU-R BT.656  
format.  
J
One channel of Y/C 16/20-bit digital video input in YCbCr 4:2:2 format  
on separate Y and Cb/Cr inputs. Supports SMPTE 260M,  
SMPTE 274M, SMPTE 296M, ITU-BT.1120, etc., as well as older  
CCIR601 interfaces.  
J
J
YCbCr 4:2:2 to YCbCr 4:2:0 horizontal conversion and ½ scaling in  
8-bit 4:2:2 modes.  
Direct interface for two channels of up to 10-bit or one channel of up to  
20-bit raw video from A/D converters.  
- Video display mode:  
J
J
Display rate up to 110 MHz.  
One channel of continuous digital video output. Digital video output is  
YCbCr 4:2:2 co-sited pixel data with 8/10-bit resolution multiplexed in  
ITU-R BT.656 format.  
J
J
One channel of Y/C 16/20-bit digital video output in YCbCr 4:2:2 format  
on separate Y and Cb/Cr outputs. (Supports SMPTE 260M,  
SMPTE 274M, SMPTE 296M, ITU-BT.1120, etc.)  
YCbCr 4:2:0 to YCbCr 4:2:2 horizontal conversion and 2× scaling of  
output in 8-bit 4:2:2 modes.  
J
J
Programmable clipping of BT.656 and Y/C mode output values.  
One channel of raw data output up to 20-bits for interface to RAM-  
DACs. Two channel synchronized raw data output.  
J
J
Synchronizes to external video controller or another video display port.  
Using the external clock, the frame timing generator provides  
programmable image timing including horizontal and vertical blank-  
ing, start of active video (SAV) and end of active video (EAV) code  
insertion, and horizontal and frame timing pulses.  
J
Generates horizontal and vertical synchronization and blanking  
signals and a frame synchronization signal.  
1-2  
Overview  
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Video Port  
- TSI capture mode: Transport stream interface (TSI) from a front-end  
device such as demodulator or forward error correction device in 8-bit  
parallel format at up to 30 Mbytes/sec.  
- The port generates up to three events per channel and one interrupt to the  
DSP.  
A high-level block diagram of the video port is shown in Figure 1–1. The port  
consists of two channels: A and B. A 5120-byte capture/display buffer is split-  
table between the two channels. The entire port (both channels) is always  
configured for either video capture or display only. Separate data pipelines  
control the parsing and formatting of video capture or display data for each of  
the BT.656, Y/C, raw video, and TSI modes.  
For video capture operation, the video port may operate as two 8/10-bit chan-  
nels of BT.656 or raw video capture; or as a single channel of 8/10-bit BT.656,  
8/10-bit raw video, 16/20-bit Y/C video, 16/20-bit raw video, or 8-bit TSI.  
For video display operation, the video port may operate as a single channel  
of 8/10-bit BT.656, 8/10-bit raw video, 16/20 bit Y/C video, or 16/20-bit raw  
video. It may also operate in a two channel 8/10-bit raw mode in which the two  
channels are locked to the same timing. Channel B is not used during single  
channel operation.  
This document describes the full feature set offered by a 20-bit video port  
implementation. Some devices may offer a subset of features such as video  
capture only or video display only. Also, some devices may limit the video port  
width to 8 or 10 bits. In this case, modes requiring wider video port widths such  
as 16-bit raw, 20-bit raw, and Y/C are not supported. See the device-specific  
datasheet for details and for I/O timing information.  
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Video Port  
Figure 1–1. Video Port Block Diagram  
Internal peripheral bus  
32  
Memory  
mapped  
registers  
VCLK1  
VCLK2  
VCTL1  
VCTL2  
VCTL3  
Timing and  
control logic  
DMA interface  
64  
BT.656 capture  
pipeline  
BT.656 display  
pipeline  
10  
20  
20  
8
10  
Y/C video  
capture pipeline  
Y/C video  
display pipeline  
VDIN[19–0]  
VDOUT[19–0]  
20  
20  
Capture/display  
buffer  
(2560 bytes)  
20  
20  
Raw video  
capture pipeline  
Raw video  
display pipeline  
TSI capture  
pipeline  
Channel A  
BT.656 capture  
pipeline  
Raw video  
display pipeline  
10  
10  
10  
Capture/display  
buffer  
(2560 bytes)  
Raw video  
capture pipeline  
10  
10  
VDOUT[19–10]  
VDIN[19–10]  
Channel B  
64  
DMA interface  
1-4  
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Video Port FIFO  
1.2 Video Port FIFO  
The video port includes a FIFO to store data coming into or out from the video  
port. The video port operates in conjunction with DMA transfers to move data  
between the video port FIFO and external or on-chip memory. You can pro-  
gram threshold settings so DMA events are generated when the video port  
FIFO reaches a certain fullness (for capture) or goes below a certain fullness  
(for display). DMAs required to service the FIFO are set up independently by  
youandarekeytocorrectoperationofthevideoport. TheFIFOsizeisrelative-  
ly large to allow time for DMAs to service the transfer requests, since devices  
typically have many peripheral interfaces often including multiple video ports.  
The following sections briefly describe the interaction with the DMA and differ-  
ent FIFO configurations used to support the various modes of the video port.  
1.2.1 DMA Interface  
Video port data transfers take place using DMAs. DMA requests are based on  
buffer thresholds. Since the video port does not directly source the transfer, it  
can not adjust the transfer size based on buffer empty/full status. This means  
the DMA transfer size is essentially fixed in the user-programmed DMA  
parameter table. The preferred transfer size is often one entire line of data,  
because this allows the most flexibility in terms of frame buffer line pitch (in  
RAM). Some modes of operation for the highest display rates may require  
more frequent DMA requests such as on a half or quarter line basis.  
All requests are based on buffer thresholds. In video capture mode, DMA  
requests are made whenever the number of samples in the buffer reaches the  
threshold value. In order to ensure that all data from a capture field/frame gets  
emptied from the buffer, the transfer size must be equal to the threshold and  
the total amount of field/frame data must be a multiple of the transfer size.  
For video display operation, DMA requests are made whenever there is at  
least the threshold number of doublewords free in the FIFO. This means that  
the transfer size must be equal to or smaller than the threshold so that it fits  
into the available space. The field/frame size must still be a multiple of the  
transfer size or there are pixels left in the buffer at the end of the field (which  
appear at the start of the next field).  
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Video Port FIFO  
1.2.2 Video Capture FIFO Configurations  
During video capture operation, the video port FIFO has one of four configura-  
tions depending on the capture mode. For BT.656 operation, the FIFO is split  
into channel A and B, as shown in Figure 1–2. Each FIFO is clocked indepen-  
dently with the channel A FIFO receiving data from the VDIN[9–0] half of the  
bus and the channel B FIFO receiving data from the VDIN[19–10] half of the  
bus. Each channel’s FIFO is further split into Y, Cb, and Cr buffers with sepa-  
rate write pointers and read registers (YSRCx, CBSRCx, and CRSRCx).  
Figure 1–2. BT.656 Video Capture FIFO Configuration  
Capture FIFO A  
YSRCA  
64  
8/10  
Y Buffer A (1280 bytes)  
VDIN[9–0]  
Cb Buffer A (640 bytes)  
Cr Buffer A (640 bytes)  
CBSRCA  
CRSRCA  
64  
64  
8/10  
8/10  
Capture FIFO B  
YSRCB  
64  
8/10  
Y Buffer B (1280 bytes)  
VDIN[19–10]  
CBSRCB  
CRSRCB  
Cb Buffer B (640 bytes)  
Cr Buffer B (640 bytes)  
64  
64  
8/10  
8/10  
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Video Port FIFO  
For 8/10-bit raw video, the FIFO is split into channel A and B, as shown in  
Figure 1–3. Each FIFO is clocked independently with the channel A FIFO  
receiving data from the VDIN[9–0] half of the bus and the channel B FIFO  
receiving data from the VDIN[19–10] half of the bus. Each channel’s FIFO has  
a separate write pointer and read register (YSRCx). The FIFO configuration  
is identical for TSI capture, but channel B is disabled.  
Figure 1–3. 8/10-Bit Raw Video Capture and TSI Video Capture FIFO Configuration  
Capture FIFO A  
VDIN[9–0]  
YSRCA  
8/10  
64  
Buffer A (2560 bytes)  
Capture FIFO B  
VDIN[19–10]  
YSRCB  
8/10  
64  
Buffer B (2560 bytes)  
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Video Port FIFO  
ForY/Cvideocapture, theFIFOisconfiguredasasinglechannelsplitintosep-  
arate Y, Cb, and Cr buffers with separate write pointers and read registers  
(YSRCA, CBSRCA, and CRSRCA). Figure 1–4 shows how Y data is received  
on the VDIN[9–0] half of the bus and Cb/Cr data is received on the  
VDIN[19–10] half of the bus and demultiplexed into the Cb and Cr buffers.  
Figure 1–4. Y/C Video Capture FIFO Configuration  
Capture FIFO  
YSRCA  
64  
VDIN[9–0]  
8/10  
Y Buffer (2560 bytes)  
CBSRCA  
CRSRCA  
64  
64  
8/10  
8/10  
Cb Buffer (1280 bytes)  
VDIN[19–10]  
Cr Buffer (1280 bytes)  
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Video Port FIFO  
For 16/20-bit raw video, the FIFO is configured as a single buffer, as shown  
in Figure 1–5. The FIFO receives 16/20-bit data from the VDIN[19–0] bus. The  
FIFO has a single write pointer and read register (YSRCA).  
Figure 1–5. 16/20-Bit Raw Video Capture FIFO Configuration  
Capture FIFO  
VDIN[19–0]  
16/20  
YSRCA  
64  
Data Buffer  
(5120 bytes)  
1.2.3 Video Display FIFO Configurations  
During video display operation, the video port FIFO has one of five configura-  
tions depending on the display mode. For BT.656 operation, a single output  
is provided on channel A, as shown in Figure 1–6, with data output on  
VDOUT[9–0]. The channel’s FIFO is split into Y, Cb, and Cr buffers with  
separate read pointers and write registers (YDSTA, CBDST, and CRDST).  
Figure 1–6. BT.656 Video Display FIFO Configuration  
Display FIFO  
YDSTA  
64  
8/10  
Y Buffer  
(2560 bytes)  
VDOUT[9–0]  
CBDST  
CRDST  
Cb Buffer  
(1280 bytes)  
64  
64  
8/10  
8/10  
Cr Buffer  
(1280 bytes)  
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Video Port FIFO  
For 8/10-bit raw video, the FIFO is configured as a single buffer as shown in  
Figure 1–7. The FIFO outputs data on the VDOUT[9–0] half of the bus. The  
FIFO has a single read pointer and write register (YDSTA).  
Figure 1–7. 8/10-Bit Raw Video Display FIFO Configuration  
Display FIFO  
VDOUT[9–0]  
8/10  
YDSTA  
64  
Data Buffer  
(5120 bytes)  
For locked raw video, the FIFO is split into channel A and B. The channels are  
locked together and use the same clock and control signals. Each channel  
uses a single buffer and write register (YDSTx) as shown in Figure 1–8.  
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Video Port FIFO  
Figure 1–8. 8/10 Bit Locked Raw Video Display FIFO Configuration  
Display FIFO A  
VDOUT[9–0]  
YDSTA  
64  
8/10  
Buffer A (2560 bytes)  
Display FIFO B  
VDOUT[19–10]  
YDSTB  
64  
8/10  
Buffer B (2560 bytes)  
For 16/20-bit raw video, the FIFO is configured as a single buffer, as shown  
in Figure 1–9. The FIFO outputs data on VDOUT[19–0]. The FIFO has a single  
read pointer and write register (YDSTA).  
Figure 1–9. 16/20-Bit Raw Video Display FIFO Configuration  
Display FIFO  
VDOUT[19–0]  
16/20  
YDSTA  
64  
Data Buffer (5120 bytes)  
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Video Port FIFO / Video Port Registers  
For Y/C video display, the FIFO is configured as a single channel split into sep-  
arate Y, Cb, and Cr buffers with separate read pointers and write registers  
(YDSTA, CBDST, and CRDST). Figure 1–10 shows how Y data is output on  
the VDOUT[9–0] half of the bus and Cb/Cr data is multiplexed and output on  
the VDOUT[19–10] half of the bus.  
Figure 1–10. Y/C Video Display FIFO Configuration  
Display FIFO  
VDOUT[9–0]  
YDSTA  
64  
8/10  
Y Buffer  
(2560 bytes)  
CBDST  
CRDST  
64  
64  
Cb Buffer  
(1280 bytes)  
VDOUT[19–10]  
8/10  
8/10  
Cr Buffer  
(1280 bytes)  
1.3 Video Port Registers  
The video port configuration register space is divided into several different  
sections with registers grouped by function including top-level video port  
control, video capture control, video display control, and GPIO.  
The registers for controlling the video port are in section 2.7.  
The registers for controlling the video capture mode of operation are shown  
in section 3.13. An additional space is dedicated for FIFO read pseudo-registers  
as shown in section 3.14. This space requires high-speed access and is not  
mapped to the register access bus.  
The registers for controlling the video display mode of operation are shown in  
section 4.12. An additional space is dedicated for FIFO write pseudo-registers  
as shown in section 4.14. This space requires high-speed access and is not  
mapped to the register access bus.  
The registers for controlling the general-purpose input/output (GPIO) are  
shown in section 5.1.  
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Video Port Pin Mapping  
1.4 Video Port Pin Mapping  
The video port requires 21 external signal pins for full functionality. Pin usage  
and direction changes depend on the selected operating mode. Pin functional-  
ity detail for video capture mode is listed in Table 1–1. Pin functionality detail  
for video display mode is listed in Table 1–2. All unused port signals (except  
VCLK1 and VCLK2) can be configured as general-purpose I/O (GPIO) pins.  
Table 1–1. Video Capture Signal Mapping  
Usage  
Raw Data Capture Mode  
BT.656 Capture Mode  
Video Port  
Signal  
Dual  
Channel  
Single  
Channel  
Y/C Capture  
TSI Capture  
Mode  
I/O  
8/10-Bit  
16/20-Bit  
Mode  
I/O  
VDIN[9–0]  
VDIN[9–0]  
VDIN[9–0]  
VDIN[9–0]  
VDIN[9–0]  
VDIN[7–0]  
VDATA[9–0]  
(In) Ch A  
(In) Ch A  
(In) (Y)  
(In) Ch A  
(In)  
(In)  
I/O  
I
VDIN[19–10]  
(In) Ch B  
Not Used  
VDIN[19–10]  
(In) (Cb/Cr)  
VDIN[19–10]  
(In) Ch B  
VDIN[19–10]  
Not Used  
VDATA[19–10]  
(In)  
VCLKINA (In) VCLKINA (In) VCLKINA (In) VCLKINA (In) VCLKINA (In) VCLKINA (In)  
VCLK1  
VCLK2  
VCTL1  
I/O VCLKINB (In)  
Not Used  
CAPENA/  
Not Used  
CAPENA/  
VCLKINB (In)  
Not Used  
Not Used  
I/O  
CAPENA  
(In)  
CAPENA  
(In)  
CAPENA  
(In)  
CAPENA  
(In)  
AVID/HSYNC AVID/HSYNC  
(In)  
(In)  
I/O  
I/O  
CAPENB  
(In)  
VBLNK/  
VSYNC (In)  
VBLNK/  
VSYNC (In)  
CAPENB  
(In)  
Not Used  
PACSTRT  
(In)  
VCTL2  
VCTL3  
Not Used  
FID  
(In)  
FID  
(In)  
FID (In)  
Ch A  
FID (In)  
Ch A  
PACERR  
(In)  
Legend: VCLKINA – Channel A capture clock; CAPENA – Channel A capture enable; VCLKINB – Channel B capture clock;  
CAPENB – Channel B capture enable; AVID – Active video; HSYNC – Horizontal synchronization; VBLNK – Vertical  
blanking; VSYNC – Vertical synchronization; FID – Field identification; PACSTRT – Packet start; PACERR – Packet  
error  
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Video Port Pin Mapping  
Table 1–2. Video Display Signal Mapping  
Usage  
Raw Data Display Mode  
16/20-Bit  
Video Port  
Signal  
BT.656  
Display Mode  
Y/C Display  
Mode  
8/10-Bit  
Dual Sync  
I/O  
8/10-Bit  
VDATA[9–0]  
I/O  
VDOUT[9–0]  
VDOUT[9–0]  
VDOUT[9–0]  
VDOUT[9–0]  
VDOUT[9–0]  
(Out)  
(Out) (Y)  
(Out)  
(Out)  
(Out) (Ch A)  
VDATA[19–10] I/O  
Not Used  
VDOUT[19–10]  
Not Used  
VDOUT[19–10]  
VDOUT[9–0]  
(Out) (Cb/Cr)  
(Out)  
(Out) (Ch B)  
VCLK1  
VCLK2  
VCTL1  
I
VCLKIN (In)  
VCLKIN (In)  
VCLKIN (In)  
VCLKIN (In)  
VCLKIN (In)  
I/O  
I/O  
VCLKOUT (Out)  
VCLKOUT (Out)  
VCLKOUT (Out)  
VCLKOUT (Out)  
VCLKOUT (Out)  
HSYNC/HBLNK/  
AVID/FLD (Out)  
or HSYNC (In)  
HSYNC/HBLNK/  
AVID/FLD (Out)  
or HSYNC (In)  
HSYNC/HBLNK/  
AVID/FLD (Out)  
or HSYNC (In)  
HSYNC/HBLNK/  
AVID/FLD (Out)  
or HSYNC (In)  
HSYNC/HBLNK/  
AVID/FLD (Out)  
or HSYNC (In)  
VCTL2  
VCTL3  
I/O  
VSYNC/VBLNK/  
VSYNC/VBLNK/  
VSYNC/VBLNK/  
VSYNC/VBLNK/  
VSYNC/VBLNK/  
CSYNC/FLD (Out) CSYNC/FLD (Out) CSYNC/FLD (Out) CSYNC/FLD (Out) CSYNC/FLD (Out)  
or VSYNC (In) or VSYNC (In) or VSYNC (In) or VSYNC (In) or VSYNC (In)  
I/O CBLNK/FLD (Out) CBLNK/FLD (Out) CBLNK/FLD (Out) CBLNK/FLD (Out) CBLNK/FLD (Out)  
or FLD (In) or FLD (In) or FLD (In) or FLD (In) or FLD (In)  
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Video Port Pin Mapping  
1.4.1 VDIN Bus Usage for Capture Modes  
The alignment and usage of data on the VDIN bus depends on the capture  
mode as shown in Table 1–3.  
Table 1–3. VDIN Data Bus Usage for Capture Modes  
Capture Mode  
BT.656  
Y/C  
Raw Data  
TSI  
Data Bus  
10-Bit  
8-Bit  
10-Bit  
8-Bit  
8-Bit  
10-Bit  
16-Bit  
20-Bit  
Mode  
VDIN19  
B
B
B
B
B
B
B
B
B
B
A
A
A
A
A
A
A
A
A
A
B
A (C)  
A (C)  
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
VDIN18  
VDIN17  
VDIN16  
VDIN15  
VDIN14  
VDIN13  
VDIN12  
VDIN11  
VDIN10  
VDIN9  
VDIN8  
VDIN7  
VDIN6  
VDIN5  
VDIN4  
VDIN3  
VDIN2  
VDIN1  
VDIN0  
B
B
B
B
B
B
B
A (C)  
A (C)  
A (C)  
A (C)  
A (C)  
A (C)  
A (C)  
A (C)  
A (C)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (C)  
A (C)  
A (C)  
A (C)  
A (C)  
A (C)  
A (C)  
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Legend: A – Channel A capture; A(C) Channel A chroma; A(Y) Channel A luma; B – Channel B capture  
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1.4.2 VDOUT Data Bus Usage for Display Modes  
The alignment and usage of data on the VDOUT bus depends on the display  
mode as shown in Table 1–4.  
Table 1–4. VDOUT Data Bus Usage for Display Modes  
Display Mode  
BT.656  
Y/C  
Dual Sync Raw Data  
Raw Data  
Data Bus  
10-Bit  
8-Bit  
10-Bit  
8-Bit  
8-Bit  
10-Bit  
16-Bit  
20-Bit  
VDOUT19  
A (C)  
A (C)  
(B)  
(B)  
A
A
A
A
A
A
A
A
A
VDOUT18  
VDOUT17  
VDOUT16  
VDOUT15  
VDOUT14  
VDOUT13  
VDOUT12  
VDOUT11  
VDOUT10  
VDOUT9  
VDOUT8  
VDOUT7  
VDOUT6  
VDOUT5  
VDOUT4  
VDOUT3  
VDOUT2  
VDOUT1  
VDOUT0  
A (C)  
A (C)  
A (C)  
A (C)  
A (C)  
A (C)  
A (C)  
A (C)  
A (C)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (C)  
A (C)  
A (C)  
A (C)  
A (C)  
A (C)  
A (C)  
(B)  
(B)  
(B)  
(B)  
(B)  
(B)  
(B)  
(B)  
(B)  
(B)  
(B)  
(B)  
(B)  
(B)  
(B)  
(B)  
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A (Y)  
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Legend: A – Channel A display; A(C) Channel A chroma; A(Y) Channel A luma; B – Optional locked channel B display  
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Chapter 2  
Video Port  
This chapter discusses the basic operation of the video port. Included is a  
discussion of the sources and types of resets, interrupt operation, DMA opera-  
tion, external clock inputs, video port throughput and latency, and the video  
port control registers.  
Topic  
Page  
2.1 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
2.2 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5  
2.3 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6  
2.4 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12  
2.5 Video Port Functionality Subsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12  
2.6 Video Port Throughput and Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13  
2.7 Video Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16  
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Reset Operation  
2.1 Reset Operation  
Thevideoporthasseveralsourcesandtypesofresets. Theactionsperformed  
by these resets and the state of the port following the resets is described in the  
following sections.  
2.1.1 Power-On Reset  
Power-on reset is an asynchronous hardware reset caused by a chip-level  
reset operation. The reset is initiated by a power-on reset input to the video  
port. When the input is active, the port places all I/Os (VD[19–0], VCTL1,  
VCTL2, VCTL3, and VCLK2) in a high-impedance state.  
2.1.2 Peripheral Bus Reset  
Peripheral bus reset is a synchronous hardware reset caused by a chip-level  
reset operation. The reset is initiated by a peripheral bus reset input to the video  
port. This reset can be used internally (continuously asserted) to disable the  
video port for low-power operation. When the input is active, the port does the  
following:  
- Places (keeps) all I/Os (VD[19–0], VCTL1, VCTL2, VCTL3, and VCLK2)  
in a high-impedance state.  
- Flushes the FIFOs (resets pointers)  
- Resets all port, capture, display, and GPIO registers to their default  
values. These may not complete until the appropriate module clock  
(VCLK1, VCLK2, STCLK) edges occur to synchronously release the logic  
from reset.  
- Clears PEREN bit in PCR to 0.  
- Sets VPHLT bit in VPCTL to 1.  
While the peripheral remains disabled (PEREN = 0):  
- VCLK1, VCLK2, and STCLK are gated off to save peripheral power.  
- Peripheral bus accesses are acknowledged (RREADY/WREADY  
returned) to prevent DMA lock-up. (Any value returned on reads, data  
accepted or discarded on writes.)  
- Peripheral bus MMR interface allows access to GPIO registers only (PID,  
PCR, PFUNC, PDIR, PIN, PDOUT, PDSET, PDCLR, PIEN, PIPOL,  
PISTAT, and PICLR).  
- Port I/Os (VD[19–0], VCTL1, VCTL2, VCTL3, and VCLK2) remain in a  
high-impedance state unless enabled as GPIO by the PFUNC bits.  
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Reset Operation  
If software sets the PEREN bit in PCR but the VPHLT bit in VPCTL remains  
set:  
- VCLK1, VCLK2, and STCLK are enabled to the port (allowing logic reset  
to complete).  
- Peripheral bus accesses are acknowledged (RREADY/WREADY  
returned) to prevent DMA lock-up. (Any value returned on reads, data  
accepted or discarded on writes.)  
- Peripheral bus MMR interface allows access to all registers.  
- Port I/Os (VD[19–0], VCTL1, VCTL2, VCTL3, and VCLK2) remain in a  
high-impedance state unless enabled as GPIO by the PFUNC bits.  
- VPCTL bits may be set (until the VPHLT bit is cleared).  
2.1.3 Software Port Reset  
A software port reset may be performed on the entire video port by setting the  
VPRST bit in VPCTL. This behaves identically to the peripheral bus reset  
except that it does not clear the PEREN bit in PCR. This reset:  
- Performs an asynchronous reset on all port logic (channel logic may stay  
in reset until port input clock pulses occur).  
- Self-clears the VPRST bit to 0 but leaves the VPHLT bit set.  
Once the port is configured and the VPHLT bit is cleared, the setting of other  
VPCTL bits (except VPRST) is disabled. The VCLK2 output may also be driven  
atthistime, ifdisplaymodeisselected. VCTL1–3mustremaininahigh-imped-  
ance state unless enabled as GPIO, since internal/external sync is selected  
through VDCTL.  
2.1.4 Capture Channel Reset  
A software reset may be performed on a single capture channel by setting the  
RSTCH bit in VCxCTL. This reset requires that the channel VCLKIN be trans-  
itioning. On capture channel reset:  
- No new DMA events are generated.  
- Peripheral bus accesses are acknowledged (RREADY returned) to prevent  
DMA lock-up. (Any value returned on reads)  
- Channel capture registers are set to their default values.  
- Channel capture FIFO is flushed (pointers reset).  
- The VCEN bit in VCxCTL is cleared to 0.  
- The RSTCH bit self-clears to 0 after completion of the above.  
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Reset Operation  
Once the port is configured and the VCEN bit is set, the setting of other  
VCxCTL bits (except VCEN, RSTCH, and BLKCAP) is prohibited and the  
capture counters begin counting. When BLKCAP is cleared, data capture and  
event generation may begin.  
2.1.5 Display Channel Reset  
A software reset may be performed on the display channel by setting the  
RSTCH bit in VDCTL. This reset requires that the channel VCLKIN be trans-  
itioning. On display channel reset:  
- No new DMA events are generated.  
- Peripheral bus accesses are acknowledged (WREADY returned) to prevent  
DMA lock-up. (Write data may be written into the FIFO or discarded.)  
- Channel display registers are set to their default values.  
- Channel display FIFO is flushed (pointers reset).  
- The VDEN bit in VDCTL is cleared to 0.  
- The RSTCH bit self-clears to 0 after completion of the above.  
Once the port is configured and the VDEN bit is set, the setting of other VDCTL  
bits (except VDEN, RSTCH, and BLKDIS) is prohibited and the display counters  
begin counting. Data outputs are driven (with default value, blanking, and  
control codes as appropriate and any control outputs are driven). When the  
BLKDIS bit is cleared, event generation may begin and FIFO data displayed.  
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Interrupt Operation  
2.2 Interrupt Operation  
ThevideoportcangenerateaninterrupttotheDSPcoreafteranyofthefollow-  
ing events occur:  
- Capture complete (CCMPx) bit is set.  
- Capture overrun (COVRx) bit is set.  
- Synchronization byte error (SERRx) bit is set.  
- Vertical interrupt (VINTxn) bit is set.  
- Short field detect (SFDx) bit is set.  
- Long field detect (LFDx) bit is set.  
- STC absolute time (STC) bit is set.  
- STC tick counter expired (TICK) bit is set.  
- Display complete (DCMP) bit is set.  
- Display underrun (DUND) bit is set.  
- Display complete not acknowledged (DCNA) bit is set.  
- GPIO interrupt (GPIO) bit is set.  
The interrupt signal is a pulse only and does not hold state. The interrupt pulse  
is generated only when the number of set flags in VPIS transitions from none  
to one or more. Another interrupt pulse is not generated by setting additional  
flag bits.  
Interrupts can be masked via the video port interrupt enable register (VPIE)  
using individual interrupt enables and the VIE global enable bit. The interrupts  
areclearedinthevideoportinterruptstatusregister(VPIS)usingtheindividual  
status bits. Writing a 1 to the appropriate bit clears the interrupt. The clearing  
of an interrupt flag reenables the generation of another interrupt pulse, if other  
flags are still set. In other words, pulse generation is reenabled by writing a 1  
to any set bit of VPIS.  
Upon receiving an interrupt you should:  
1) Read VPIS.  
2) Perform the service routine for whatever bits are set.  
3) Clear appropriate bits by writing a 1 to their VPIS locations.  
4) Upon return from the ISR, if VPIS bits have been (or remain) set, then  
another interrupt will occur.  
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DMA Operation  
2.3 DMA Operation  
The video port uses up to three DMA events per channel for a total of six  
possible events. Each DMA event uses a dedicated event output. The outputs  
are:  
- VPYEVTA  
- VPCbEVTA  
- VPCrEVTA  
- VPYEVTB  
- VPCbEVTB  
- VPCrEVTB  
2.3.1 Capture DMA Event Generation  
Capture DMA events are generated based on the state of the capture FIFO(s).  
If no DMA event is currently pending and the FIFO crosses the value specified  
by VCTHRLDn, a DMA event is generated. Once an event has been  
requested, another DMA event may not be generated until the servicing of the  
outstanding event has begun (as indicated by the first read of the FIFO by the  
DMA event service). If the capture FIFO level exceeds 2× the VCTHRLDn  
value before the requested DMA event completes, then another DMA event  
may be generated. Thus, up to one DMA event may be outstanding.  
An outgoing data counter counts data read by the DMA. This counter is loaded  
with the VCTHRLDn value whenever a new DMA service begins. The counter  
then counts down for each double-word read from the FIFO by the DMA. The  
DMA is complete when the counter reaches zero. Figure 2–1 shows the  
capture DMA event generation.  
For BT.656 and Y/C modes, there are three FIFOs, one for each of the Y, Cb,  
andCrcolorcomponents. EachFIFOgeneratesitsownDMAevent;therefore,  
the DMA event state and FIFO thresholds for each FIFO are tracked indepen-  
dently. The Cb and Cr FIFOs use  
a
threshold value of  
½ (VCTHRLDn + VCTHRLDn mod 2).  
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DMA Operation  
Figure 2–1. Capture DMA Event Generation Flow Diagram  
Empty FIFO  
Capture data, no  
DMA pending  
No  
FIFO ≥ threshold  
?
Yes  
Generate DMA event  
Capture data, DMA pend-  
ing, new events disabled  
No  
No  
Yes  
FIFO overflow  
Error  
Pending DMA begun  
?
?
Yes  
Capture data, DMA active,  
new events enabled  
No  
Yes  
No  
No  
FIFO ≥ 2x threshold  
FIFO overflow  
DMA complete  
?
?
?
Yes  
Yes  
Overflow error  
Generate DMA request  
Capture Data, DMA  
active & DMA pending  
No  
Yes  
No  
Yes  
Overflow error  
DMA complete  
?
FIFO overflow  
?
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DMA Operation  
Because the capture FIFOs may hold multiple thresholds worth of data, a  
problem arises at the boundaries between fields. Since Field 1 and Field 2  
may have different threshold values, the amount of data in the FIFO required  
to generate the DMA event changes depending on the current capture field  
and the field of any outstanding DMA requests. Similarly, the threshold value  
loaded in the outgoing data counter needs to change depending on which  
field’s DMA event is being serviced (not which field is currently being  
captured). To prevent confusion at the field boundaries, the VCxEVTCT regis-  
ter is programmed to indicate the number of events to generate for each field.  
An event counter tracks how many events have been generated and indicates  
which threshold value to use in event generation and in the outgoing data  
counter. After the last Field 1 event has been generated, the DMA logic looks  
for FIFO > THRSHLD1 + THRSHLD2 to pregenerate the first Field 2 event.  
Once the last Field  
1
event completes, the logic looks for  
FIFO > 2 × THRSHLD2 (assuming a Field 2 event is outstanding).  
Some initial devices may require THRSHLD1 and THRSHLD2 to be set to the  
same value. Check the latest device errata, if you want to use different thresh-  
olds for the two fields.  
2.3.2 Display DMA Event Generation  
Display DMA events are generated based on the amount of room available in  
the FIFO. The VDTHRLDn value indicates the level at which the FIFO has  
room to receive another DMA. If the FIFO has at least VDTHRLDn locations  
available, a DMA event is generated. Once a DMA event has been requested,  
another DMA event may not be generated until the servicing of the first DMA  
event has begun (as indicated by the first write to the FIFO by the DMA event  
service). If there is at least 2× the threshold space still available in the FIFO  
after the first DMA service is begun (and the display event counter has not  
expired) then another DMA event may be generated. Thus, up to one DMA  
request may be outstanding.  
An incoming data counter is loaded with the VDTHRLDn (or VDTHRLDn/2 for  
Cb and Cr FIFOs) value at the beginning of each DMA event service and  
countsdowntheincomingDMAdoublewordsWhenthecounterreaches0, the  
DMA event is complete. Figure 2–2 shows the display DMA event generation.  
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DMA Operation  
Figure 2–2. Display DMA Event Generation Flow Diagram  
Display data, no DMA  
pending  
EOF  
No  
Display data  
FIFO space  
threshold ?  
Yes  
Yes  
Field complete  
?
Yes  
Event counter  
expired ?  
EOF  
No  
End of field  
No  
No  
FIFO underrun  
?
Generate DMA event  
Yes  
Display data, DMA  
pending, new events  
disabled  
Underrun error  
Start of field  
FIFO empty  
No  
No  
Yes  
Pending DMA  
begun ?  
Underrun error  
FIFO underrun  
?
Generate DMA event,  
new events disabled  
Yes  
Yes  
Display data, DMA  
active, new events  
enabled  
Pending  
DMA begun ?  
Yes  
No  
No  
No  
No  
FIFO space  
2x threshold  
?
DMA complete  
?
FIFO underrun  
?
FIFO  
underrun ?  
No  
Yes  
Yes  
Yes  
Yes  
Underrun error  
Underrun error  
Event counter  
expired ?  
EOF  
No  
Generate DMA  
request  
Display Data, DMA active,  
and DMA pending  
No  
No  
Yes  
Yes  
Underrun error  
FIFO underrun  
?
DMA complete  
?
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DMA Operation  
A DMA event counter is used to track the number of DMA events generated  
in each field as programmed in the VDDISPEVT register. The DISPEVT1 or  
DISPEVT2 value (depending on the current display field) is loaded at the start  
of each field. The event counter then decrements with each DMA event gener-  
ation until it reaches 0, at which point no more DMA events are generated until  
the next field begins. Once the last line of data for a field has been requested,  
the DMA logic stops generating events until the field is complete in case the  
CPU needs to modify the DMA address pointers.  
For BT.656 and Y/C modes, there are three FIFOs, one for each of the Y, Cb,  
andCrcolorcomponents. EachFIFOgeneratesitsownDMAevent;therefore,  
the DMA event state and FIFO thresholds for each FIFO are tracked indepen-  
dently. (The Cb and Cr FIFOs use a threshold value of ½ VDTHRLD).  
2.3.3 DMA Size and Threshold Restrictions  
The video port FIFOs are 64-bits wide and always read or write 64 bits at a  
time. Forthisreason, DMAaccessesmustalwaysbeanevennumberofwords  
in length. It is expected that in most cases the threshold size is set to the line  
length (rounded up to the next doubleword). This always works because differ-  
ent lines are not packed together within a doubleword and the Cb and Cr  
thresholds (½ VCTHRLDx/VDTHRLD) are always rounded up to the double-  
word.  
For example, in 8-bit BT.656 capture mode with a line length of 712 (Y), setting  
the threshold to the line length results in a VCTHRLD of 712 pixels × 1 bytes/  
pixel × doubleword/8 bytes = 89 doublewords. The Cb and Cr FIFOs contain  
half the data (44.5 doublewords) so their thresholds are set to 45 double-  
words. Therefore, the Cb and Cr DMAs each transmit an extra 4 bytes at the  
end of each line.  
If a multihorizontal line length threshold is desired (2 lines, for example) then  
the chosen line length must round up to an even number of doublewords so  
that it is evenly divisible by 2. If this is not the case, then the Cb and Cr FIFO  
transfers are corrupted. For the multiline case, consider the same 8-bit BT.656  
capture mode with a line length of 712 (Y). If the threshold is set for 2 lines, this  
results in a VCTHRLD value of 2 × 89 = 178 doublewords. The actual Cb/Cr  
line length is 44.5 doublewords that requires a length of 45. To transfer 2 lines  
requires 2 × 45 = 90 doublewords. However, for this VCTHRLD, the DMA  
logic would calculate the Cb/Cr threshold size as 178/2 = 89 doublewords,  
which is 1 doubleword off. This can be corrected by increasing the line length  
to 720 pixels (and ignoring the extra captured pixels) or decreasing it to  
704 pixels.  
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DMA Operation  
Similarly if a subhorizontal line length is desired (½ line, for example), then the  
line length and threshold must be chosen such that the threshold is divisible  
by 2. (This can also be stated as the line length must be an even multiple of  
#DMAs/line × 8). Forthesublinecase, considerthe8-bitBT.656capturemode  
with a line length of 624 (Y). If the threshold is set for ½ the line length, this  
results in VCTHRLD = (624/2)/8 = 39 doublewords. The DMA logic would  
calculate the Cb/Cr threshold as 39/2 = 20 doublewords. However, two such  
Cb/Cr DMA events would result in a transfer of 40 doublewords, whichislarger  
than the actual Cb/Cr line length of (624/2)/8 = 39 doublewords. This can be  
corrected by changing the line size to 640 pixels or 608 pixels, or by changing  
the threshold to be 1/3 the line length (VCTHRLD = (624/3)/8 = 26 doublewords  
and the Cb/Cr threshold is 26/2 = 13 doublewords. 3 × 13 = 39 doublewords,  
which is exactly the Cb/Cr line length.)  
2.3.4 DMA Interface Operation  
When the video port is configured for capture (or TSI) mode, it only accepts  
read requests from the DMA interface. Write requests are false acknowledged  
(so the bus does not stall) and the data is discarded. When the video port is  
configured for display mode, it only accepts write requests. Read requests are  
false acknowledged (so the bus does not stall) and an arbitrary data value is  
returned.  
When the video port is in reset, is not enabled (PEREN bit cleared), halted  
(VPHALT bit is set), or the active mode is not enabled (VCEN or VDEN bit is  
cleared), then the port will false acknowledge all DMA accesses to prevent bus  
lockup.  
The video port DMA event generation logic is very tightly coupled to the DMA  
interface accesses. An incorrectly programmed DMA size causes the DMA  
and FIFO to become misaligned causing aberrations in the captured or  
displayed data and likely resulting in an eventual FIFO overflow or underflow.  
In the same manner, if another system DMA incorrectly addresses the video  
port during active capture or display, the video port has no way of determining  
that this is an errant DMA because all it monitors is a DMA access so it must  
perform the FIFO read or write. Such an errant DMA eventually causes the  
FIFO to be overread or overwritten.  
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Clocks / Video Port Functionality Subsets  
2.4 Clocks  
The video port has three external clock inputs as shown in Table 2–1. No  
synchronization is required between the clocks sourced by the external pins.  
VCLK1 and VCLK2 clock frequencies should be less than the DMA interface  
clock. On 64x devices, the DMA interface clock is typically ½ the CPU clock  
so this allows VCLK1 and VCLK2 to run at full frequency unless the 64x CPU  
is running at less than 220 MHz. STCLK should be less than the peripheral bus  
clock.  
Table 2–1. Video Port Functional Clocks  
Clock  
Source  
Frequency (MHz) Function  
VCLK1  
External pin  
13.5–110  
Clocks capture channel A and display logic and pin  
side of the FIFOs.  
VCLK2  
STCLK  
External pin  
External pin  
13.5–80  
Clocks capture channel B logic and FIFO pin side.  
Clocks TSI system time counter and tick counter.  
~ 27  
2.5 Video Port Functionality Subsets  
Thevideoportmaybeimplementedwithreducedfeaturesinlow-costdevices.  
2.5.1 Data Bus Width  
The standard port has a 20-bit VDATA bus. Lower-cost implementations may  
use a more narrow data bus at the expense of functionality. The following lists  
the choices and their effect on the design:  
- 20-bit – Full functionality.  
- 10-bit – Single channel (channel A) only (DCDIS bit in VPSTAT always  
set). Limits CMODE selection to 8/10-bit BT.656 and 8/10 bit raw capture  
modes. Limits DMODE selection to 8/10-bit BT.656, and 8/10 bit raw  
display. TSI capture mode may also be selected.  
- 8-bit – Single channel (channel A) only (DCDIS bit in VPSTAT always set).  
Limits CMODE selection to 8-bit BT.656 and 8-bit raw capture modes.  
Limits DMODE selection to 8-bit BT.656 and 8-bit raw display. TSI capture  
mode may also be selected.  
Selection of 8-bit or 10-bit mode limits port operation to a single channel. This  
selection also causes the removal of the channel B register file, channel B  
filters and other logic, and ½ of the FIFO.  
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Video Port Functionality Subsets / Video Port Throughput and Latency  
2.5.2 FIFO Size  
Some low-cost device implementations with narrow video ports width or  
restricted to lower video frequency operations may use a reduced FIFO size.  
FIFO size does not affect the DMA request mechanism. The selection of 8-bit  
or 10-bit port width automatically cuts the FIFO size in half with support for only  
a single channel of operation.  
2.6 Video Port Throughput and Latency  
Because of the large amount of buffering provided within the video port and  
the programmable threshold used to generate DMA events, the required DMA  
latency is difficult to calculate. Because video data is real time, the video port’s  
external interface may not be stalled so module throughput must be maintained.  
2.6.1 Video Capture Throughput  
In order to maintain throughput during video capture operation, the capture  
FIFO must be emptied at a faster rate than it is filled. The time to completely  
fill the capture FIFO may be represented by the formula t + n(t ), where t is  
F
H
F
the time to fill the FIFO with active samples, t is the horizontal blanking time,  
H
and n is the number of lines of active video that the FIFO can hold. Maximum  
throughput requirements for capture occur during HDTV resolution Y/C mode.  
The BT.1120 standard (1125 line/60 Hz mode) specifies a line size of 2200 Y  
samples (1920 active) and 1100 ea. Cb and Cr samples (960-ea. active) at a  
sample rate of 74.25 MHz. This means that the horizontal blanking time is  
280/74.25 MHz or 3.77 µs. In Y/C mode, the Y buffer is 2560 bytes and the  
Cr/Cb buffers are 1280 bytes each. The number of samples that the buffers  
can hold depends on the buffer packing mode as listed in Table 2–2.  
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Video Port Throughput and Latency  
Table 2–2. Y/C Video Capture FIFO Capacity  
Sample  
8-Bit  
10-Bit Dense  
10-Bit  
Y Samples  
2560  
1920  
1280  
Cb Samples  
Cr Samples  
1280  
1280  
960  
640  
640  
960  
Using these values and the formula above, the maximum time to empty the  
FIFO (t ) may be calculated for each case. The DMA output rate (r ) is then  
O
O
calculated as the FIFO size divided by t  
:
O
8-bit (n = 1):  
t
t
t
< t + n(t )  
< 2560/74.25 MHz + 1(3.77 µs)  
< 38.3 µs  
O
O
O
F
H
r
= t /5120 = 7.4 ns (134 MBytes/s)  
O
O
10-bit dense (n = 1): t < t + n(t )  
O
O
O
F
H
t
t
< 1920/74.25 MHz + 1(3.77 µs)  
< 29.63 µs  
r
= t /5120 = 5.79 ns (173 MBytes/s)  
O
O
10-bit (n = 0):  
t
t
t
< t + n(t )  
< 1280/74.25 MHz  
< 17.24 µs  
O
O
O
F
H
r
= t /5120 = 3.37 ns (297 MBytes/s)  
O
O
A DMA read throughput of at least 300 MBytes/s is required for the highest  
capture rate operation supported by 20-bit implementations of the video port.  
C64x devices including the video port typically have more than enough DMA  
bandwidth to support the highest throughput required by a single video port.  
However when using multiple high-bandwidth peripherals together, it is impor-  
tant to consider the total DMA throughput required by the peripherals being  
used concurrently.  
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Video Port Throughput and Latency  
2.6.2 Video Display Throughput  
Video display throughput may be calculated in a manner similar to video capture.  
In this case, the time to fill the display FIFO must be less than the time to empty  
the FIFO or underflow occurs. The 110 MHz display rate supports a maximum  
display resolution of 1280 × 1024 at 63 Hz (frame rate). This means that the  
horizontal blanking time is ~3.88 µs. The time to empty a completely full FIFO  
may be represented by the formula t + n(t ), where t is the time to empty the  
E
H
E
FIFO of active samples, t is the horizontal blanking time, and n is the number  
H
of lines of active video that the FIFO can hold. In raw display mode, the FIFO  
is 5120 bytes. The number of samples that the buffer can hold depends on the  
buffer packing mode as listed in Table 2–3.  
Table 2–3. Raw Video Display FIFO Capacity  
8-Bit  
5120  
10-Bit Dense  
10/16-Bit  
20-Bit  
Samples  
3840  
2560  
1280  
Using these values and the formula above, the maximum time to fill the FIFO  
(t ) may be calculated for each case. The DMA input rate (r ) is then calculated  
I
I
as the FIFO size divided by t :  
I
8-bit (n=4):  
t < t + n(t )  
I
E
H
t < 5120/110 MHz + 4(3.88 µs)  
I
t < 62.6 µs  
I
r = t /5120 = 12.12 ns (82.5 MBytes/s)  
I
I
10-bit dense (n=3): t < t + n(t )  
I
E
H
t < 3840/110 MHz + 3(3.88 µs)  
I
t < 46.55 µs  
I
r = t /5120 = 9.09 ns (110 MBytes/s)  
I
I
16-bit (n=2):  
20-bit (n=1):  
t < t + n(t )  
I
E
H
t < 2560/110 MHz + 2(3.88 µs)  
I
t < 31.03 µs  
I
r = t /5120 = 6.06 ns (165 MBytes/s)  
I
I
t < t + n(t )  
I
E
H
t < 1280/110 MHz + 1(3.88 µs)  
I
t < 15.52 µs  
I
r = t /5120 = 3.03 ns (330 MBytes/s)  
I
I
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Video Port Control Registers  
A DMA write throughput of at least 330 MBytes/s is required for the highest  
display rate operation supported by 20-bit implementations of the video port.  
C64x devices including the video port typically have more than enough DMA  
bandwidth to support this throughput requirement. However when using multi-  
ple high-bandwidth peripherals together, it is important to consider the total  
DMA throughput required by the peripherals being used concurrently.  
2.7 Video Port Control Registers  
The video port control registers are listed in Table 2–4. See the device-specific  
datasheet for the memory address of these registers.  
After enabling the video port in the peripheral configuration register  
(PERCFG), there should be a delay of 64 CPU cycles before accessing the  
video port registers.  
Table 2–4. Video Port Control Registers  
Acronym  
Register Name  
Section  
VPCTL  
Video Port Control Register  
2.7.1  
VPSTAT  
VPIE  
Video Port Status Register  
2.7.2  
2.7.3  
2.7.4  
Video Port Interrupt Enable Register  
Video Port Interrupt Status Register  
VPIS  
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Video Port Control Registers  
2.7.1 Video Port Control Register (VPCTL)  
The video port control register (VPCTL) determines the basic operation of the  
video port. The VPCTL is shown in Figure 2–3 and described in Table 2–5.  
Not all combinations of the port control bits are unique. The control bit encoding  
is shown in Table 2–6. Additional mode options are selected using the video  
capture channel A control register (VCACTL) and video display control register  
(VDCTL).  
Figure 2–3. Video Port Control Register (VPCTL)  
31  
16  
8
Reserved  
R-0  
15  
14  
13  
VPRST  
R/WS-0  
VPHLT  
R/WC-1  
Reserved  
R-0  
7
6
5
4
3
2
1
0
VCLK2P  
R/W-0  
VCT3P  
R/W-0  
VCT2P  
R/W-0  
VCT1P  
R/W-0  
Reserved  
R-0  
TSI  
DISP  
R/W-0  
DCHNL  
R/W-0  
R/W-0  
Legend: R = Read only; R/W = Read/Write; WC = Write a 1 to clear; WS = Write 1 to set, write of 0 has no effect; -n = value after  
reset  
Table 2–5. Video Port Control Register (VPCTL) Field Descriptions  
†
†
Bit  
field  
symval  
Value Description  
31–16 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
15  
VPRST  
Video port software reset enable bit. VPRST is set by writing a  
1. Writing 0 has no effect.  
NO  
0
1
RESET  
Flush all FIFOs and set all port registers to their initial values.  
VCLK1 and VCLK2 are configured as inputs and all VDATA  
and VCTL pins are placed in high impedance. Auto-cleared  
after reset is complete.  
†
For CSL implementation, use the notation VP_VPCTL_field_symval  
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Video Port Control Registers  
Table 2–5. Video Port Control Register (VPCTL) Field Descriptions (Continued)  
†
†
Bit  
field  
symval  
Value Description  
Video port halt bit. This bit is set upon hardware or software  
14  
VPHLT  
reset. The other VPCTL bits (except VPRST) can only be  
changed when VPHLT is 1. VPHLT is cleared by writing a 1.  
Writing 0 has no effect.  
NONE  
CLEAR  
–
0
1
0
13–8 Reserved  
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
7
VCLK2P  
VCLK2 pin polarity bit. Has no effect in capture mode.  
NONE  
0
1
REVERSE  
Inverts the VCLK2 output clock polarity in display mode.  
6
VCT3P  
VCTL3 pin polarity. Does not affect GPIO operation. If VCTL3  
pin is used as a FLD input on the video capture side, then the  
VCTL3 polarity is not considered; the field inverse is controlled  
by the FINV bit in the video capture channel x control register  
(VCxCTL).  
NONE  
0
1
ACTIVELOW  
Indicates the VCTL3 control signal (input or output) is active  
low.  
5
4
3
VCT2P  
VCTL2 pin polarity bit. Does not affect GPIO operation.  
NONE  
0
1
ACTIVELOW  
Indicates the VCTL2 control signal (input or output) is active  
low.  
VCT1P  
VCTL1 pin polarity bit. Does not affect GPIO operation.  
NONE  
0
1
ACTIVELOW  
Indicates the VCTL1 control signal (input or output) is active  
low.  
Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
†
For CSL implementation, use the notation VP_VPCTL_field_symval  
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Video Port Control Registers  
Table 2–5. Video Port Control Register (VPCTL) Field Descriptions (Continued)  
†
†
Bit  
field  
symval  
Value Description  
TSI capture mode select bit.  
2
TSI  
NONE  
0
1
TSI capture mode is disabled.  
TSI capture mode is enabled.  
CAPTURE  
1
0
DISP  
Display mode select bit. VDATA pins are configured for output.  
VCLK2 pin is configured as VCLKOUT output.  
CAPTURE  
DISPLAY  
0
1
Capture mode is enabled.  
Display mode is enabled.  
DCHNL  
Dual channel operation select bit. If the DCDIS bit in VPSTAT  
is set, this bit is forced to 0.  
SINGLE  
DUAL  
0
1
Single-channel operation is enabled.  
Dual-channel operation is enabled.  
†
For CSL implementation, use the notation VP_VPCTL_field_symval  
Table 2–6. Video Port Operating Mode Selection  
VPCTL Bit  
TSI  
DISP DCHNL  
Operating Mode  
0
0
0
1
x
0
1
x
x
Single channel video capture. BT.656, Y/C or raw mode as selected in VCACTL.  
Video capture B channel not used.  
0
0
1
Dual channel video capture. Either BT.656 or raw 8/10-bit as selected in  
VCACTL and VCBCTL. Option is available only if DCDIS is 0.  
Single channel video display. BT.656, Y/C or raw mode as selected in VDCTL.  
Video display B channel is only used for dual channel sync raw mode.  
Single channel TSI capture.  
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Video Port Control Registers  
2.7.2 Video Port Status Register (VPSTAT)  
The video port status register (VPSTAT) indicates the current condition of the  
video port. The VPSTAT is shown in Figure 2–4 and described in Table 2–7.  
Figure 2–4. Video Port Status Register (VPSTAT)  
31  
16  
Reserved  
R-0  
15  
4
3
2
1
0
Reserved  
R-0  
DCDIS HIDATA Reserved  
R-x R-x R-0  
Legend: R = Read only; -n = value after reset; -x = value is determined by chip-level configuration  
Table 2–7. Video Port Status Register (VPSTAT) Field Descriptions  
†
†
Bit  
field  
symval  
Value Description  
31–4 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
3
2
DCDIS  
Dual-channel disable bit. The default value is determined by the  
chip-level configuration.  
ENABLE  
DISABLE  
0
1
Dual-channel operation is enabled.  
Port muxing selections prevent dual-channel operation.  
HIDATA  
High data bus half. HIDATA does not affect video port operation  
but is provided to inform you which VDATA pins may be controlled  
by the video port GPIO registers. HIDATA is never set unless  
DCDIS is also set. The default value is determined by the  
chip-level configuration.  
NONE  
USE  
0
1
Indicates that another peripheral is using VDATA[9–0] and the  
video port channel A (VDIN[9–0] or VDOUT[9–0]) is muxed onto  
VDATA[19–10].  
1–0  
Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
†
For CSL implementation, use the notation VP_VPSTAT_field_symval  
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2.7.3 Video Port Interrupt Enable Register (VPIE)  
The video port interrupt enable register (VPIE) enables sources of the video  
port interrupt to the DSP. The VPIE is shown in Figure 2–5 and described in  
Table 2–8.  
Figure 2–5. Video Port Interrupt Enable Register (VPIE)  
31  
24  
Reserved  
R-0  
23  
22  
21  
20  
19  
18  
17  
16  
LFDB  
R/W-0  
SFDB  
R/W-0  
VINTB2  
R/W-0  
VINTB1  
R/W-0  
SERRB  
R/W-0  
CCMPB  
R/W-0  
COVRB  
R/W-0  
GPIO  
R/W-0  
15  
14  
13  
12  
11  
10  
9
8
Reserved  
R-0  
DCNA  
R/W-0  
DCMP  
R/W-0  
DUND  
R/W-0  
TICK  
R/W-0  
STC  
Reserved  
R-0  
R/W-0  
7
6
5
4
3
2
1
0
LFDA  
R/W-0  
SFDA  
R/W-0  
VINTA2  
R/W-0  
VINTA1  
R/W-0  
SERRA  
R/W-0  
CCMPA  
R/W-0  
COVRA  
R/W-0  
VIE  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 2–8. Video Port Interrupt Enable Register (VPIE) Field Descriptions  
†
†
Bit  
field  
symval  
Value Description  
31–24 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
23  
22  
21  
LFDB  
Long field detected on channel B interrupt enable bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
0
1
Interrupt is enabled.  
SFDB  
VINTB2  
Short field detected on channel B interrupt enable bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
0
1
Interrupt is enabled.  
Channel B field 2 vertical interrupt enable bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
0
1
Interrupt is enabled.  
†
For CSL implementation, use the notation VP_VPIE_field_symval  
SPRU629  
Video Port  
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Video Port Control Registers  
Table 2–8. Video Port Interrupt Enable Register (VPIE) Field Descriptions (Continued)  
†
†
Bit  
field  
symval  
Value Description  
Channel B field 1 vertical interrupt enable bit.  
20  
VINTB1  
SERRB  
CCMPB  
COVRB  
GPIO  
DISABLE  
ENABLE  
0
1
Interrupt is disabled.  
Interrupt is enabled.  
19  
18  
17  
16  
Channel B synchronization error interrupt enable bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
0
1
Interrupt is enabled.  
Capture complete on channel B interrupt enable bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
0
1
Interrupt is enabled.  
Capture overrun on channel B interrupt enable bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
0
1
Interrupt is enabled.  
Video port general purpose I/O interrupt enable bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
–
0
1
0
Interrupt is enabled.  
15  
14  
Reserved  
DCNA  
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
Display complete not acknowledged bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
0
1
Interrupt is enabled.  
13  
12  
11  
DCMP  
DUND  
TICK  
Display complete interrupt enable bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
0
1
Interrupt is enabled.  
Display underrun interrupt enable bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
0
1
Interrupt is enabled.  
System time clock tick interrupt enable bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
0
1
Interrupt is enabled.  
†
For CSL implementation, use the notation VP_VPIE_field_symval  
2-22  
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Video Port Control Registers  
Table 2–8. Video Port Interrupt Enable Register (VPIE) Field Descriptions (Continued)  
†
†
Bit  
field  
symval  
Value Description  
System time clock interrupt enable bit.  
10  
STC  
DISABLE  
ENABLE  
–
0
1
0
Interrupt is disabled.  
Interrupt is enabled.  
9–8  
Reserved  
LFDA  
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
7
Long field detected on channel A interrupt enable bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
0
1
Interrupt is enabled.  
6
5
4
3
2
1
0
SFDA  
Short field detected on channel A interrupt enable bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
0
1
Interrupt is enabled.  
VINTA2  
VINTA1  
SERRA  
CCMPA  
COVRA  
VIE  
Channel A field 2 vertical interrupt enable bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
0
1
Interrupt is enabled.  
Channel A field 1 vertical interrupt enable bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
0
1
Interrupt is enabled.  
Channel A synchronization error interrupt enable bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
0
1
Interrupt is enabled.  
Capture complete on channel A interrupt enable bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
0
1
Interrupt is enabled.  
Capture overrun on channel A interrupt enable bit.  
Interrupt is disabled.  
DISABLE  
ENABLE  
0
1
Interrupt is enabled.  
Video port global interrupt enable bit. Must be set for interrupt to be  
sent to DSP.  
DISABLE  
ENABLE  
0
1
Interrupt is disabled.  
Interrupt is enabled.  
†
For CSL implementation, use the notation VP_VPIE_field_symval  
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Video Port Control Registers  
2.7.4 Video Port Interrupt Status Register (VPIS)  
The video port interrupt status register (VPIS) displays the status of video port  
interrupts to the DSP. The interrupt is only sent to the DSP if the corresponding  
enable bit in VPIE is set. All VPIS bits are cleared by writing a 1, writing a 0 has  
no effect. The VPIS is shown in Figure 2–6 and described in Table 2–9.  
Figure 2–6. Video Port Interrupt Status Register (VPIS)  
31  
24  
Reserved  
R-0  
23  
22  
21  
20  
19  
18  
17  
16  
LFDB  
SFDB  
R/WC-0  
VINTB2  
R/WC-0  
VINTB1  
R/WC-0  
SERRB  
R/WC-0  
CCMPB  
R/WC-0  
COVRB  
R/WC-0  
GPIO  
R/WC-0  
R/WC-0  
15  
Reserved  
R-0  
14  
13  
12  
11  
10  
9
8
DCNA  
R/WC-0  
DCMP  
R/WC-0  
DUND  
R/WC-0  
TICK  
STC  
Reserved  
R-0  
R/WC-0  
R/WC-0  
7
6
5
4
3
2
1
0
LFDA  
R/WC-0  
SFDA  
R/WC-0  
VINTA2  
R/WC-0  
VINTA1  
R/WC-0  
SERRA  
R/WC-0  
CCMPA  
R/WC-0  
COVRA  
R/WC-0  
Reserved  
R-0  
Legend: R = Read only; WC = Write 1 to clear, write of 0 has no effect; -n = value after reset  
Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions  
Bit  
field  
symval  
Value Description  
31–24 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
23  
LFDB  
Long field detected on channel B interrupt detected bit. (A long  
field is only detected when the VRST bit in VCBCTL is cleared to  
0; when VRST = 1, a long field is always detected.)  
BT.656 or Y/C capture mode – LFDB is set when long field  
detection is enabled and VCOUNT is not reset before  
VCOUNT = YSTOP + 1.  
Raw data mode, or TSI capture mode or display mode – Not used.  
No interrupt is detected.  
NONE  
0
1
CLEAR  
Interrupt is detected. Bit is cleared.  
†
For CSL implementation, use the notation VP_VPIS_field_symval  
2-24  
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Video Port Control Registers  
Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued)  
Bit  
field  
symval  
Value Description  
Short field detected on channel B interrupt detected bit.  
22  
SFDB  
BT.656 or Y/C capture mode – SFDB is set when short field  
detection is enabled and VCOUNT is reset before  
VCOUNT = YSTOP.  
Raw data mode, or TSI capture mode or display mode – Not used.  
No interrupt is detected.  
NONE  
0
1
CLEAR  
Interrupt is detected. Bit is cleared.  
21  
20  
19  
VINTB2  
VINTB1  
SERRB  
Channel B field 2 vertical interrupt detected bit.  
BT.656 or Y/C capture mode – VINTB2 is set when a vertical  
interrupt occurred in field 2.  
Raw data mode or TSI capture mode – Not used.  
No interrupt is detected.  
NONE  
0
1
CLEAR  
Interrupt is detected. Bit is cleared.  
Channel B field 1 vertical interrupt detected bit.  
BT.656 or Y/C capture mode – VINTB1 is set when a vertical  
interrupt occurred in field 1.  
Raw data mode or TSI capture mode – Not used.  
No interrupt is detected.  
NONE  
0
1
CLEAR  
Interrupt is detected. Bit is cleared.  
Channel B synchronization error interrupt detected bit.  
BT.656 or Y/C capture mode – Synchronization parity error on  
channel B. An SERRB typically requires resetting the channel  
(RSTCH) or the port (VPRST).  
Raw data mode or TSI capture mode – Not used.  
No interrupt is detected.  
NONE  
0
1
CLEAR  
Interrupt is detected. Bit is cleared.  
†
For CSL implementation, use the notation VP_VPIS_field_symval  
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Video Port Control Registers  
Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued)  
Bit  
field  
symval  
Value Description  
Capture complete on channel B interrupt detected bit. (Data is not  
18  
CCMPB  
in memory until the DMA transfer is complete.)  
BT.656 or Y/C capture mode – CCMPB is set after capturing an  
entire field or frame (when F1C, F2C, or FRMC in VCBSTAT are  
set) depending on the CON, FRAME, CF1, and CF2 control bits in  
VCBCTL.  
Raw data mode – RDFE is not set, CCMPB is set when FRMC in  
VCBSTAT is set (when the data counter = the combined  
VCYSTOP/VCXSTOP value).  
TSI capture mode – CCMPB is set when FRMC in VCBSTAT is set  
(when the data counter = the combined VCYSTOP/VCXSTOP  
value).  
NONE  
0
1
No interrupt is detected.  
CLEAR  
Interrupt is detected. Bit is cleared.  
17  
16  
COVRB  
Capture overrun on channel B interrupt detected bit. COVRB is set  
when data in the FIFO was overwritten before being read out (by  
the DMA).  
NONE  
0
1
No interrupt is detected.  
CLEAR  
Interrupt is detected. Bit is cleared.  
Video port general purpose I/O interrupt detected bit.  
No interrupt is detected.  
GPIO  
NONE  
CLEAR  
–
0
1
0
Interrupt is detected. Bit is cleared.  
15  
14  
Reserved  
DCNA  
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
Display complete not acknowledged. Indicates that the F1D, F2D,  
or FRMD bit that caused the display complete interrupt was not  
cleared prior to the start of the next gating field or frame.  
NONE  
0
1
No interrupt is detected.  
CLEAR  
Interrupt is detected. Bit is cleared.  
†
For CSL implementation, use the notation VP_VPIS_field_symval  
2-26  
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Video Port Control Registers  
Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued)  
Bit  
field  
symval  
Value Description  
Display complete. Indicates that the entire frame has been driven  
13  
DCMP  
out of the port. The DMA complete interrupt can be used to  
determine when the last data has been transferred from memory to  
the FIFO.  
DCMP is set after displaying an entire field or frame (when F1D,  
F2D or FRMD in VDSTAT are set) depending on the CON,  
FRAME, DF1, and DF2 control bits in VDCTL.  
NONE  
0
1
No interrupt is detected.  
CLEAR  
Interrupt is detected. Bit is cleared.  
Display underrun. Indicates that the display FIFO ran out of data.  
No interrupt is detected.  
12  
11  
DUND  
TICK  
NONE  
0
1
CLEAR  
Interrupt is detected. Bit is cleared.  
System time clock tick interrupt detected bit.  
BT.656, Y/C capture mode or raw data mode – Not used.  
TSI capture mode –TICK is set when the TCKEN bit in TSICTL is  
set and the desired number of system time clock ticks has  
occurred as programmed in TSITICKS.  
NONE  
0
1
No interrupt is detected.  
CLEAR  
Interrupt is detected. Bit is cleared.  
10  
STC  
System time clock interrupt detected bit.  
BT.656, Y/C capture mode or raw data mode – Not used.  
TSI capture mode – STC is set when the system time clock  
reaches an absolute time as programmed in TSISTCMPL and  
TSISTCMPM registers and the STEN bit in TSICTL is set.  
NONE  
CLEAR  
–
0
1
0
No interrupt is detected.  
Interrupt is detected. Bit is cleared.  
9–8  
Reserved  
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
†
For CSL implementation, use the notation VP_VPIS_field_symval  
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Video Port Control Registers  
Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued)  
Bit  
field  
symval  
Value Description  
Long field detected on channel A interrupt detected bit. (A long  
7
LFDA  
field is only detected when the VRST bit in VCACTL is cleared to  
0; when VRST = 1, a long field is always detected.)  
BT.656 or Y/C capture mode – LFDA is set when long field  
detection is enabled and VCOUNT is not reset before  
VCOUNT = YSTOP + 1.  
Raw data mode, or TSI capture mode or display mode – Not used.  
No interrupt is detected.  
NONE  
0
1
CLEAR  
Interrupt is detected. Bit is cleared.  
6
SFDA  
Short field detected on channel A interrupt detected bit.  
BT.656 or Y/C capture mode – SFDA is set when short field  
detection is enabled and VCOUNT is reset before  
VCOUNT = YSTOP.  
Raw data mode, or TSI capture mode or display mode – Not used.  
No interrupt is detected.  
NONE  
0
1
CLEAR  
Interrupt is detected. Bit is cleared.  
5
VINTA2  
Channel A field 2 vertical interrupt detected bit.  
BT.656, or Y/C capture mode or any display mode – VINTA2 is set  
when a vertical interrupt occurred in field 2.  
Raw data mode or TSI capture mode – Not used.  
No interrupt is detected.  
NONE  
0
1
CLEAR  
Interrupt is detected. Bit is cleared.  
4
VINTA1  
Channel A field 1 vertical interrupt detected bit.  
BT.656, or Y/C capture mode or any display mode – VINTA1 is set  
when a vertical interrupt occurred in field 1.  
Raw data mode or TSI capture mode – Not used.  
No interrupt is detected.  
NONE  
0
1
CLEAR  
Interrupt is detected. Bit is cleared.  
†
For CSL implementation, use the notation VP_VPIS_field_symval  
2-28  
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Video Port Control Registers  
Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued)  
Bit  
field  
symval  
Value Description  
Channel A synchronization error interrupt detected bit.  
3
SERRA  
BT.656 or Y/C capture mode – Synchronization parity error on  
channel A. An SERRA typically requires resetting the channel  
(RSTCH) or the port (VPRST).  
Raw data mode or TSI capture mode – Not used.  
No interrupt is detected.  
NONE  
0
1
CLEAR  
Interrupt is detected. Bit is cleared.  
2
CCMPA  
Capture complete on channel A interrupt detected bit. (Data is not  
in memory until the DMA transfer is complete.)  
BT.656 or Y/C capture mode – CCMPA is set after capturing an  
entire field or frame (when F1C, F2C, or FRMC in VCASTAT are  
set) depending on the CON, FRAME, CF1, and CF2 control bits in  
VCACTL.  
Raw data mode – If RDFE bit is set, CCMPA is set when F1C,  
F2C, or FRMC in VCASTAT is set (when the data counter = the  
combined VCYSTOP/VCXSTOP value) depending on the CON,  
FRAME, CF1, and CF2 control bits in VCACTL. If RDFE bit is not  
set, CCMPA is set when FRMC in VCASTAT is set (when the data  
counter = the combined VCYSTOP/VCXSTOP value).  
TSI capture mode – CCMPA is set when FRMC in VCASTAT is set  
(when the data counter = the combined VCYSTOP/VCXSTOP  
value).  
NONE  
0
1
No interrupt is detected.  
CLEAR  
Interrupt is detected. Bit is cleared.  
1
0
COVRA  
Capture overrun on channel A interrupt detected bit. COVRA is set  
when data in the FIFO was overwritten before being read out (by  
the DMA).  
NONE  
CLEAR  
–
0
1
0
No interrupt is detected.  
Interrupt is detected. Bit is cleared.  
Reserved  
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
†
For CSL implementation, use the notation VP_VPIS_field_symval  
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Chapter 3  
Video Capture Port  
Video capture works by sampling video data on the input pins and saving it to  
the video port FIFO. When the amount of captured data reaches a  
programmed threshold level, a DMA is performed to move data from the FIFO  
into DSP memory. In some cases, color separation is performed on the incoming  
video data requiring multiple FIFOs and DMAs to be used.  
The video port enables capture of both interlaced and progressive scan data.  
Interlaced capture can be performed on either a field-by-field or a frame-by-  
frame basis. A capture window specifies the data to be captured within each  
field. Frameandfieldsynchronizationcanbeperformedusingembeddedsync  
codes or configurable control inputs allowing glueless interface to various  
encoders and ADCs.  
Topic  
Page  
3.1 Video Capture Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
3.2 BT.656 Video Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3  
3.3 Y/C Video Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12  
3.4 BT.656 and Y/C Mode Field and Frame Operation . . . . . . . . . . . . . . . 3-17  
3.5 Video Input Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26  
3.6 Ancillary Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31  
3.7 Raw Data Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32  
3.8 TSI Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37  
3.9 Capture Line Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42  
3.10 Capturing Video in BT.656 or Y/C Mode . . . . . . . . . . . . . . . . . . . . . . . . 3-44  
3.11 Capturing Video in Raw Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46  
3.12 Capturing Data in TSI Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47  
3.13 Video Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49  
3.14 Video Capture FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83  
3-1  
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Video Capture Mode Selection  
3.1 Video Capture Mode Selection  
The video capture module operates in one of nine modes as listed in  
Table 3–1. The transport stream interface (TSI) selection is made using the  
TSI bit in the video port control register (VPCTL). The CMODE bits are in the  
video capture channel x control register (VCxCTL). The Y/C and 16/20-bit raw  
capture modes may only be selected for channel A and only if the DCHNL bit  
in VPCTL is cleared to 0.  
When operating as a raw video capture channel, no data selection or data  
interpretation is performed. The 16/20-bit raw capture mode is designed to  
accept data from A/D converters with resolution higher than eight bits (used,  
for example, in medical imaging).  
Table 3–1. Video Capture Mode Selection  
TSI Bit  
CMODE Bits Mode  
Description  
0
000  
001  
010  
011  
100  
8-Bit ITU-R BT.656 Digital video input is in YCbCr 4:2:2 with 8-bit  
Capture  
resolution multiplexed in ITU-R BT.656 format.  
0
0
0
0
10-Bit ITU-R  
BT.656 Capture  
Digital video input is in YCbCr 4:2:2 with 10-bit  
resolution multiplexed in ITU-R BT.656 format.  
8-Bit Raw Capture Raw 8-bit data capture at sampling rates up to  
80 MHz.  
10-Bit Raw Capture Raw 8-bit or 10-bit data capture at sampling rates up  
to 80 MHz.  
8-Bit Y/C Capture  
Digital video input is in YCbCr 4:2:2 with 8-bit  
resolution on parallel Y and Cb/Cr multiplexed  
channels.  
0
101  
10-Bit Y/C Capture Digital video input is in YCbCr 4:2:2 with 10-bit  
resolution on parallel Y and Cb/Cr multiplexed  
channels.  
0
0
1
110  
111  
010  
16-Bit Raw Capture Raw 16-bit data capture at sampling rates up to  
80 MHz.  
20-Bit Raw Capture Raw 20-bit data capture at sampling rates up to  
80 MHz.  
TSI Capture  
8-bit parallel TSI capture at rates up to 30 MHz.  
3-2  
Video Capture Port  
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BT.656 Video Capture Mode  
3.2 BT.656 Video Capture Mode  
The BT.656 capture mode captures 8-bit or 10-bit 4:2:2 luma and chroma data  
multiplexed into a single data stream. Video data is conveyed in the order  
Cb,Y,Cr,Y,Cb,Y,Cr, etc. where the sequence Cb,Y,Cr refers to co-sited luma  
and chroma samples and the following Y value corresponds to the next lu-  
minance sample. The data stream is demultiplexed and each component is  
written in packed form into separate FIFOs for transfer into Y, Cb, and Cr buff-  
ers in DSP memory. (This is commonly called planar format.) The packing and  
order of the samples is determined by the sample size (8-bit or 10-bit) and the  
selected endianess of the DSP.  
The ITU-BT.656 standard provides for either 8-bit or 10-bit component sam-  
ples. When 10-bit samples are used, the 2 least significant bits are considered  
fractional values. Thus for 8-bit operation, input data is aligned to the most sig-  
nificant bits (9–2) of the input and the two least-significant bits are ignored.  
In BT.656 video capture mode, data bytes in which the 8 most significant bits  
are all set to 1 (FF.0h, FF.4h, FF.8h, FF.Ch) or are all set to 0 (00.0h, 00.4h,  
00.8h, 00.Ch) are reserved for data identification purposes and consequently,  
only 254 of the possible 256 8-bit words (or 1016 of 1024 10-bit words) may  
be used to express signal value.  
3.2.1 BT.656 Capture Channels  
In dual channel operation, the video port can support capture of two BT.656  
data streams or one BT.656 data stream and one raw data stream. In the latter  
case, theBT.656streammayoccuroneitherChannelAorChannelB. Ineither  
case, the BT.656 stream(s) must have embedded timing reference codes and  
the appropriate VCTL input must be used as a CAPEN signal.  
If the port is configured for single channel operation, capture will take place on  
Channel A only. The unused half of the VDATA bus may be used for GPIO or  
for another peripheral function. For single channel operation, non-standard  
BT.656 data streams without embedded timing reference codes are supported  
through the use of the timing control (VCTL) input signals.  
SPRU629  
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BT.656 Video Capture Mode  
3.2.2 BT.656 Timing Reference Codes  
For standard digital video, there are two reference signals, one at the begin-  
ning of each video data block (start of active video, SAV), and one at the end  
of each video block (end of active video, EAV). (Technically each line begins  
with the SAV code and ends just before the subsequent EAV code.) Each  
timing reference signal consists of a four sample sequence in the following for-  
mat: FF.Ch 00.0h 00.0h XY.0h. (The FFh and 00h values are reserved for use  
in these timing reference signals.) The first three bytes are a fixed preamble.  
The fourth byte contains information defining field identification, the state of  
field blanking and state of line blanking. The assignment of these bits within  
the timing reference signal is listed in Table 3–2. Note that the two least-signifi-  
cant bits should be ignored even during 10-bit operation.  
Table 3–2. BT.656 Video Timing Reference Codes  
st  
nd  
rd  
th  
1
Byte  
2
Byte  
(00h)  
3
Byte  
4
Byte  
Data Bit  
(FFh)  
(00h)  
(XYh)  
9 (MSB)  
1
0
0
0
0
0
0
0
0
x
x
0
1
†
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
x
x
0
0
0
0
0
0
0
x
x
F (field)  
‡
V (vertical blanking)  
§
H (horizontal blanking)  
P3 (protection bit 3)  
P2 (protection bit 2)  
P1 (protection bit 1)  
P0 (protection bit 0)  
x
x
†
‡
§
F = 0 during Field 1; F = 1 during Field 2  
V = 0 elsewhere; V = 1 during field blanking  
H = 0 in SAV; H = 1 in EAV  
P0, P1, P2, and P3: Depends on F, V, and H state.  
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BT.656 Video Capture Mode  
Bits P0, P1, P2, and P3 have different states depending on the state of bits F,  
V, and H as shown in Table 3–3.  
Table 3–3. BT.656 Protection Bits  
Line Information Bits  
Protection Bits  
F
V
H
P3  
P2  
P1  
P0  
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
1
0
0
1
The protection bits allow the port to implement a DEDSEC (double error detec-  
tion, single error correction) function on the received video timing reference  
code. The corrected values for the F, H, and V bits based on the protection bit  
values are shown in Table 3–4. The – entries indicate detected double bit  
errors that cannot be corrected. Detection of these errors causes the SERRx  
bit in the video port interrupt status register (VPIS) to be set.  
Table 3–4. Error Correction by Protection Bits  
Received F, V, and H Bits  
Received  
000  
001  
010  
011  
100  
101  
110  
111  
P –P Bits  
3
0
0000  
000  
000  
000  
–
000  
–
–
111  
0001  
0010  
0011  
0100  
0101  
0110  
000  
000  
–
–
–
–
–
111  
011  
–
–
–
111  
101  
–
111  
–
111  
–
–
010  
–
100  
–
–
111  
–
000  
–
–
011  
–
–
110  
–
001  
011  
–
100  
100  
–
111  
011  
–
011  
011  
–
–
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BT.656 Video Capture Mode  
Table 3–4. Error Correction by Protection Bits (Continued)  
Received F, V, and H Bits  
Received  
000  
001  
010  
011  
100  
101  
110  
111  
P –P Bits  
3
0
0111  
100  
–
–
011  
100  
100  
100  
–
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
000  
–
–
–
–
–
–
–
101  
–
110  
–
–
111  
101  
–
001  
101  
–
010  
010  
010  
110  
–
–
–
101  
–
101  
101  
–
–
010  
–
010  
–
010  
110  
110  
110  
–
001  
001  
–
110  
–
110  
–
001  
–
001  
011  
–
001  
101  
–
–
–
–
–
001  
010  
100  
–
3.2.3 BT.656 Image Window and Capture  
The BT.656 format is an interlaced format consisting of two fields. The video  
port allows capture of one or both fields. The captured image is a subset of  
each field and can be larger or smaller than the active video region. The cap-  
tured image position is defined by the VCxSTRT1 and VCxSTOP1 registers  
for field 1, and the VCxSTRT2 and VCxSTOP2 registers for field 2. The  
VCXSTART and VCXSTOP bits set the horizontal window position for the field  
relative to the HCOUNT pixel counter. The VCYSTART and VCYSTOP bits set  
the vertical position relative to the VCOUNT line counter. This is shown in  
Figure 3–1.  
HCOUNT increments on every chroma sample period (every other VCLKIN  
rising edge) for which capture is enabled. Once VCOUNT = VCYSTART, line capture  
begins when HCOUNT = VCXSTART. It continues until HCOUNT = VCXSTOP. A  
field’s capture is complete when HCOUNT = VCXSTOP and  
VCOUNT = VCYSTOP.  
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BT.656 Video Capture Mode  
Figure 3–1. Video Capture Parameters  
Hcount=0  
Ycount=1  
Ystart  
Xstart  
Xstop  
Capture Image  
Ystop  
Field 1  
Ystop  
Ycount=1  
Ystart  
Xstart  
Xstop  
Capture Image  
Field 2  
Table 3–5 shows common digital camera standards and the number of fields  
per second, number of active lines per field, and the number of active pixels  
per line.  
Table 3–5. Common Video Source Parameters  
Number of Active Lines  
(Field 1/Field 2)  
Video Source  
Number of Active Pixels  
Field Rate (Hz)  
square pixel  
60Hz/525 lines  
240/240  
244/243  
288/288  
288/288  
640  
60  
BT.601  
60 Hz/525 lines  
720  
768  
720  
60  
50  
50  
square pixel  
50Hz/625 lines  
BT.601  
50 Hz/625 lines  
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BT.656 Video Capture Mode  
For the BT.656 video capture mode, the FIFO buffer is divided into three sec-  
tions (three buffers). One section is 1280 bytes deep and is dedicated for stor-  
age of Y data samples. The other two sections are dedicated for storage of Cb  
andCrdatasamples, respectively. ThebuffersforCbandCrsamplesareeach  
640 bytes deep. The incoming video data stream is separated into Y, Cb, and  
Cr data streams, scaled (if selected), and the Y, Cb, and Cr buffers are filled.  
Each of the three buffers has a memory-mapped location associated with it;  
YSRC, CBSRC, and CRSRC. The YSRC, CBSRC, and CRSRC locations are  
read only and are used by DMAs to access video data samples stored in the  
FIFOs.  
If video capture is enabled (BLKCAP bit in VCxCTL is cleared), pixels in the  
capture window are captured in the Y, Cb, and Cr buffers. The video capture  
moduleusestheYEVT, CbEVT, andCrEVTeventstonotifytheDMAcontroller  
to copy data from the capture buffers to the DSP memory. The number of  
doublewords required to generate the events is set by the VCTHRLDn bits in  
VCxTHRLD. On every YEVT, the DMA should move data from the Y buffer to  
DSP memory using the YSRC location as the source address. On every  
CbEVT, the DMA should move data from the Cb buffer to DSP memory using  
the CBSRC location as the source address. On every CrEVT, the DMA should  
move data from the Cr buffer to DSP memory using the CRSRC location as  
the source address. Note that transfer size from the Cb and Cr buffers is half  
of the transfer size from the Y buffer since for every four Y samples, there are  
two Cb and two Cr samples.  
3.2.4 BT.656 Data Sampling  
Incomingdata(includingtimingcodes)aresampledandtheHCOUNTcounter  
advanced only on clock cycles for which the CAPEN input is active. Inputs  
when CAPEN is inactive are ignored. The timing reference codes are recognized  
only when three sequential samples with CAPEN valid are the FFh, 00h, 00h  
sequence. A non-00h sample after the FFh or after the first 00h causes the  
timing reference recognition logic to be reset and to look for FFh again.  
(Unsampled data; those with CAPEN inactive; in the middle of a timing reference  
do not cause the recognition logic to be reset since these are not considered  
to be valid inputs.)  
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BT.656 Video Capture Mode  
3.2.5 BT.656 FIFO Packing  
Captured data is always packed into 64-bits before being written into the cap-  
ture FIFO(s). The packing and byte ordering is dependant upon the capture  
data size and the device endian mode. For little-endian operation (default),  
data is packed into the FIFO from right to left; for big-endian operation, data  
is packed from left to right.  
The 8-bit BT.656 mode uses three FIFOs for color separation. Four samples  
are packed into each word as shown in Figure 3–2.  
Figure 3–2. 8-Bit BT.656 FIFO Packing  
VCLKINA / VCLKINB  
Cb 0  
Y 0  
Cr 0  
Y 1  
Cb 1  
Y 2  
Cr 1  
Y 3  
24  
Cb 2  
Y 4  
Cr 2  
Y 5  
8
VDIN[9–2] / VDIN[9–12]  
63  
56 55  
48 47  
40 39  
32 31  
23  
16 15  
7
0
Y 31  
Y 23  
Y 15  
Y 7  
Y 30  
Y 22  
Y 14  
Y 6  
Y 29  
Y 28  
Y 27  
Y 26  
Y 25  
Y 24  
Y 16  
Y 8  
Y 21  
Y 13  
Y 5  
Y 20  
Y 12  
Y 4  
Y 19  
Y 11  
Y 3  
Y 18  
Y 10  
Y 2  
Y 17  
Y 9  
Y 1  
Y 0  
Y FIFO  
63  
63  
56 55  
48 47  
40 39  
32 31  
32 31  
24 23  
16 15  
8
8
7
7
0
0
Cb 15  
Cb 7  
Cb 14  
Cb 6  
Cb 13  
Cb 5  
Cb 12  
Cb 4  
Cb 11  
Cb 3  
Cb 10  
Cb 2  
Cb 9  
Cb 1  
Cb 8  
Cb 0  
Cb FIFO  
Cr FIFO  
56 55  
48 47  
40 39  
24 23  
16 15  
Cr 15  
Cr 7  
Cr 14  
Cr 6  
Cr 13  
Cr 5  
Cr 12  
Cr 4  
Cr 11  
Cr 3  
Cr 10  
Cr 2  
Cr 9  
Cr 1  
Cr 8  
Cr 0  
Little-Endian Packing  
63  
56 55  
48 47  
40 39  
32 31  
24 23  
16 15  
8
7
0
Y 24  
Y 16  
Y 8  
Y 25  
Y 17  
Y 9  
Y 26  
Y 18  
Y 10  
Y 2  
Y 27  
Y 19  
Y 11  
Y 3  
Y 28  
Y 20  
Y 12  
Y 4  
Y 29  
Y 21  
Y 13  
Y 5  
Y 30  
Y 22  
Y 14  
Y 6  
Y 31  
Y 23  
Y 15  
Y 7  
Y 0  
Y 1  
Y FIFO  
63  
63  
56 55  
47  
40 39  
32 31  
24 23  
16 15  
8
8
7
7
0
0
48  
Cb 8  
Cb 0  
Cb 9  
Cb 1  
Cb 10  
Cb 2  
Cb 11  
Cb 3  
Cb 12  
Cb 4  
Cb 13  
Cb 5  
Cb 14  
Cb 6  
Cb 15  
Cb 7  
Cb FIFO  
Cr FIFO  
56 55  
48 47  
40 39  
32 31  
24 23  
16 15  
Cr 8  
Cr 0  
Cr 9  
Cr 1  
Cr 10  
Cr 2  
Cr 11  
Cr 3  
Cr 12  
Cr 4  
Cr 13  
Cr 5  
Cr 14  
Cr 6  
Cr 15  
Cr 7  
Big-Endian Packing  
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Video Capture Port  
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BT.656 Video Capture Mode  
The 10-bit BT.656 mode uses three FIFOs for color separation. Two samples  
are packed into each word with zero or sign extension as shown in Figure 3–3.  
Figure 3–3. 10-Bit BT.656 FIFO Packing  
VCLKINA / VCLKINB  
VDIN[9–0] / VDIN[19–10] Cb 0 Y 0 Cr 0 Y 1 Cb 1 Y 2 Cr 1 Y 3 Cb 2 Y 4 Cr 2 Y 5  
63  
58 57  
48 47  
42 41  
3231  
26 25  
16 15  
10 9  
0
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Y 15  
Y 11  
Y 7  
Y 14  
Y 10  
Y 6  
Y 13  
Y 9  
Y 4  
Y 1  
Y 12  
Y 8  
Y 4  
Y 0  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Y 3  
Y 2  
0 / SE  
0 / SE  
0 / SE  
Y FIFO  
63  
63  
58 57  
58 57  
48 47  
48 47  
42 41  
42 41  
3231  
3231  
26 25  
26 25  
16 15  
16 15  
10 9  
10 9  
0
0
Cb 7  
Cb 3  
Cb 6  
Cb 2  
Cb 5  
Cb 1  
Cb 4  
Cb 0  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Cb FIFO  
Cr FIFO  
Cr 7  
Cr 3  
Cr 6  
Cr 2  
Cr 5  
Cr 1  
Cr 4  
Cr 0  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Little-Endian Packing  
63  
58 57  
48 47  
42 41  
3231  
26 25  
16 15  
10 9  
0
Y 12  
Y 8  
Y 4  
Y 0  
Y 13  
Y 9  
Y 4  
Y 1  
Y 14  
Y 10  
Y 6  
Y 15  
Y 11  
Y 7  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Y 2  
Y 3  
0 / SE  
Y FIFO  
63  
63  
58 57  
58 57  
48 47  
48 47  
42 41  
42 41  
3231  
3231  
26 25  
26 25  
16 15  
16 15  
10 9  
10 9  
0
0
Cb 4  
Cb 0  
Cb 5  
Cb 1  
Cb 6  
Cb 2  
Cb 7  
Cb 3  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Cb FIFO  
Cr FIFO  
Cr 4  
Cr 0  
Cr 5  
Cr 1  
Cr 6  
Cr 2  
Cr 7  
Cr 3  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Big-Endian Packing  
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BT.656 Video Capture Mode  
The 10-bit BT.656 dense mode uses three FIFOs for color separation. Three  
samples are packed into each word with zero extension to provide increased  
DMA bandwidth as shown in Figure 3–4.  
Figure 3–4. 10-Bit BT.656 Dense FIFO Packing  
VCLKINA / VCLKINB  
VDIN[9–0] / VDIN[19–10] Cb 0 Y 0 Cr 0 Y 1 Cb 1 Y 2 Cr 1 Y 3 Cb 0 Y 4 Cr 2 Y 5  
63 61  
00  
00  
00  
00  
52 51  
42 41  
32 31 29  
00  
00  
00  
00  
20 19  
10 9  
0
Y 23  
Y 17  
Y 22  
Y 16  
Y 10  
Y 4  
Y 21  
Y 15  
Y 9  
Y 20  
Y 14  
Y 8  
Y 19  
Y 13  
Y 7  
Y 18  
Y 12  
Y 6  
Y 11  
Y 5  
Y 3  
Y 2  
Y 1  
Y 0  
Y FIFO  
63 61  
00  
00  
52 51  
52 51  
42 41  
42 41  
32 31 29  
00  
00  
20 19  
20 19  
10 9  
10 9  
0
0
Cb 11  
Cb 5  
Cb 10  
Cb 4  
Cb 9  
Cb 3  
Cb 8  
Cb 2  
Cb 7  
Cb 1  
Cb 6  
Cb 0  
Cb FIFO  
Cr FIFO  
63 61  
00  
00  
32 31 29  
00  
00  
Cr 11  
Cr 5  
Cr 10  
Cr 4  
Cr 9  
Cr 3  
Cr 8  
Cr 2  
Cr 7  
Cr 1  
Cr 6  
Cr 0  
Little-Endian Packing  
63 61  
00  
00  
00  
00  
52 51  
42 41  
32 31 29  
20 19  
10 9  
0
Y 18  
Y 12  
Y 6  
Y 19  
Y 13  
Y 7  
Y 20  
Y 14  
Y 8  
00  
00  
00  
00  
Y 21  
Y 15  
Y 9  
Y 22  
Y 16  
Y 10  
Y 4  
Y 23  
Y 17  
Y 11  
Y 5  
Y 0  
Y 1  
Y 2  
Y 3  
Y FIFO  
63 61  
00  
00  
52 51  
52 51  
42 41  
42 41  
32 31 29  
00  
00  
20 19  
20 19  
10 9  
10 9  
0
0
Cb 6  
Cb 0  
Cb 7  
Cb 1  
Cb 8  
Cb 2  
Cb 9  
Cb 3  
Cb 10  
Cb 4  
Cb 11  
Cb 5  
Cb FIFO  
Cr FIFO  
63 61  
00  
00  
32 31 29  
00  
00  
Cr 6  
Cr 0  
Cr 7  
Cr 1  
Cr 8  
Cr 2  
Cr 9  
Cr 3  
Cr 10  
Cr 4  
Cr 11  
Cr 5  
Big-Endian Packing  
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Y/C Video Capture Mode  
3.3 Y/C Video Capture Mode  
The Y/C capture mode is similar to the BT.656 capture mode but captures 8  
or 10-bit 4:2:2 data on separate luma and chroma data streams. One data  
stream contains Y samples and the other stream contains multiplexed Cb and  
Cr samples co-sited with every other Y sample. The Y samples are written into  
a Y FIFO and the chroma samples are demultiplexed and written into separate  
Cb and Cr FIFOs for transfer into Y, Cb, and Cr buffers in DSP memory. The  
packing and order of the samples is determined by the sample size (8-bit or  
10-bit) and the device endian mode.  
The Y/C capture mode supports HDTV standards such as SMPTE260,  
SMPTE296, and BT.1120 with embedded EAV and SAV codes. It also supports  
SDTV YCbCr modes that use separate control signals (sometimes called  
CCIR601 mode)  
As with the BT.656 capture mode, data bytes where the 8 most-significant bits  
are all set to 1 (FF.0h, FF.4h, FF.8h, FF.Ch) or are all cleared to 0 (00.0h, 00.4h,  
00.8h, 00.Ch)arereservedfordataidentificationpurposesandconsequential-  
ly only 254 of the possible 256 8-bit words (or 1016 of 1024 10-bit words) may  
be used to express signal value.  
3.3.1 Y/C Capture Channels  
Because Y/C mode requires the entire VDATA bus, only single channel opera-  
tion is supported. If the DCHNL bit in VPCTL is set, then Y/C mode cannot be  
selected. Y/C capture takes place on channel A only. Both embedded timing  
references and external control inputs are supported.  
3.3.2 Y/C Timing Reference Codes  
Many high-resolution Y/C interface standards provide for embedded timing  
reference codes. These codes are identical to those used in the BT.656 stan-  
dard except that they appear on both the luma (Y) and chroma (CbCr) data  
streams in parallel.  
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Y/C Video Capture Mode  
3.3.3 Y/C Image Window and Capture  
The SDTV Y/C format (CCIR601) is an interlaced format consisting of two  
fields just like BT.656. HDTV Y/C formats may be interlaced or progressive  
scan. For interlaced capture, the capture windows are programmed identically  
to BT.656 mode. For progressive scan formats, only field1 is used.  
In Y/C mode, HCOUNT increments on every luma sample period (every  
VCLKINA rising edge) for which capture is enabled. Once YCOUNT = VCYSTART,  
line capture begins when HCOUNT = VCXSTART. It continues until  
HCOUNT = VCXSTOP.  
A
field’s  
capture  
is  
complete  
when  
HCOUNT = VCXSTOP and VCOUNT = VCYSTOP.  
For the Y/C video capture mode, the FIFO buffer is divided into three sections  
(three buffers). One section is 2560 bytes deep and is dedicated for storage  
of Y data samples. The other two sections are dedicated for storage of Cb and  
Cr data samples, respectively. The buffers for Cb and Cr samples are each  
1280 bytes deep. The incoming video data stream is separated into Y, Cb, and  
Cr data streams, scaled (if selected) and the Y, Cb, and Cr buffers are filled.  
Each of the three buffers has a memory-mapped location associated with it;  
YSRC, CBSRC, and CRSRC. The YSRC, CBSRC, and CRSRC locations are  
read only and are used by DMAs to access video data samples stored in the  
FIFOs. Reads must always be 64 bits.  
If video capture is enabled, pixels in the capture window are captured in the  
Y, Cb, and Cr buffers. The video capture module uses the YEVT, CbEVT, and  
CrEVT events to notify the DMA controller to copy data from the capture buff-  
ers to the DSP memory. The number of pixels required to generate the events  
is set by the VCTHRLDn bits in VCxTHRLD (the VCTHRLDn value must be an  
even number for Y/C mode). The capture module generates the events after  
VCTHRLDn new pixels have been received. On every YEVT, the DMA should  
move data from the Y buffer to DSP memory using the YSRC register as the  
source address. On every CbEVT, the DMA should move data from the Cb  
buffer to DSP memory using the CBSRC register as the source address. On  
every CrEVT, the DMA should move data from the Cr buffer to DSP memory  
using the CRSRC register as the source address. Note that transfer size from  
theCbandCrbuffersishalfofthetransfersizefromtheYbuffersinceforevery  
four Y samples, there are two Cb and two Cr samples.  
The three DMA events are generated simultaneously when VCTHRLDn is  
reached. Each event is reenabled when the first read of the respective FIFO  
by the requested DMA begins.  
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Video Capture Port  
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Y/C Video Capture Mode  
3.3.4 Y/C FIFO Packing  
Captured data is always packed into 64 bits before being written into the  
capture FIFO(s). The packing and byte ordering is dependant upon the  
capture data size and the device endian mode. For little-endian operation  
(default), data is packed into the FIFO from right to left; for big-endian opera-  
tion, data is packed from left to right.  
The 8-bit Y/C mode uses three FIFOs for color separation. Four samples are  
packed into each word as shown in Figure 3–5.  
Figure 3–5. 8-Bit Y/C FIFO Packing  
VCLKINA  
VDIN[9–2]  
Y 0  
Y 1  
Y 2  
Y 3  
Y 4  
Y 5  
Y 6  
Y 7  
Y 8  
Y 9 Y 10 Y 11  
Cb 4  
VDIN[19–12]  
Cr 0 Cb 1 Cr 1  
Cr 2  
Cr 3  
Cr 5  
Cb 0  
Cb 2  
Cb 3  
Cb 4  
Cb 5  
63  
56 55  
Y 31  
Y 23  
Y 15  
Y 7  
48 47  
40 39  
32 31  
24 23  
16 15  
8 7  
0
Y 30  
Y 29  
Y 21  
Y 13  
Y 5  
Y 28  
Y 27  
Y 26  
Y 25  
Y 17  
Y 9  
Y 24  
Y 16  
Y 8  
Y 22  
Y 14  
Y 6  
Y 20  
Y 12  
Y 4  
Y 19  
Y 11  
Y 3  
Y 18  
Y 10  
Y 2  
Y 1  
Y 0  
Y FIFO  
63  
63  
56 55  
Cb 15  
Cb 7  
48 47  
48 47  
40 39  
40 39  
3231  
3231  
24 23  
24 23  
16 15  
16 15  
8 7  
0
0
Cb 14  
Cb 6  
Cb 13  
Cb 5  
Cb 12  
Cb 4  
Cb 11  
Cb 3  
Cb 10  
Cb 2  
Cb 9  
Cb 1  
Cb 8  
Cb 0  
Cb FIFO  
Cr FIFO  
56 55  
Cr 15  
Cr 7  
8 7  
Cr 14  
Cr 6  
Cr 13  
Cr 5  
Cr 12  
Cr 4  
Cr 11  
Cr 3  
Cr 10  
Cr 2  
Cr 9  
Cr 1  
Cr 8  
Cr 0  
Little-Endian Packing  
63  
56 55  
Y 24  
Y 16  
Y 8  
Y 0  
48 47  
40 39  
32 31  
24 23  
16 15  
8 7  
0
Y 25  
Y 17  
Y 9  
Y 26  
Y 18  
Y 10  
Y 2  
Y 27  
Y 19  
Y 11  
Y 3  
Y 28  
Y 20  
Y 12  
Y 4  
Y 29  
Y 21  
Y 13  
Y 5  
Y 30  
Y 22  
Y 14  
Y 6  
Y 31  
Y 23  
Y 15  
Y 7  
Y 1  
Y FIFO  
63  
63  
56 55  
Cb 8  
Cb 0  
48 47  
48 47  
40 39  
40 39  
3231  
3231  
24 23  
24 23  
16 15  
16 15  
8 7  
0
0
Cb 9  
Cb 1  
Cb 10  
Cb 2  
Cb 11  
Cb 3  
Cb 12  
Cb 4  
Cb 13  
Cb 5  
Cb 14  
Cb 6  
Cb 15  
Cb 7  
Cb FIFO  
Cr FIFO  
56 55  
Cr 8  
Cr 0  
8 7  
Cr 9  
Cr 1  
Cr 10  
Cr 2  
Cr 11  
Cr 3  
Cr 12  
Cr 4  
Cr 13  
Cr 5  
Cr 14  
Cr 6  
Cr 15  
Cr 7  
Big-Endian Packing  
3-14  
Video Capture Port  
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Y/C Video Capture Mode  
The 10-bit Y/C mode uses three FIFOs for color separation. Two samples are  
packed into each word with zero or sign extension as shown in Figure 3–6.  
Figure 3–6. 10-Bit Y/C FIFO Packing  
VCLKINA  
VDIN[9–0] Y 0  
Y 1  
Y 2  
Y 3  
Y 4  
Y 5  
Y 6  
Y 7  
Y 8  
Y 9 Y 10 Y 11  
Cb 0  
Cb 2  
Cb 3  
Cb 4  
Cb 5  
VDIN[19–10]  
Cr 0 Cb 1 Cr 1  
Cr 2  
Cr 3  
Cr 4  
Cr 5  
63  
58 57  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
48 47  
42 41  
3231  
26 25  
16 15  
10 9  
0
Y 15  
Y 11  
Y 7  
Y 14  
Y 10  
Y 6  
Y 13  
Y 9  
Y 4  
Y 1  
Y 12  
Y 8  
Y 4  
Y 0  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Y 3  
Y 2  
Y FIFO  
63  
63  
58 57  
48 47  
48 47  
42 41  
42 41  
3231  
3231  
26 25  
26 25  
16 15  
16 15  
10 9  
10 9  
0
0
0 / SE  
0 / SE  
Cb 7  
Cb 3  
Cb 6  
Cb 2  
Cb 5  
Cb 1  
Cb 4  
Cb 0  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Cb FIFO  
Cr FIFO  
58 57  
0 / SE  
Cr 7  
Cr 3  
Cr 6  
Cr 2  
Cr 5  
Cr 1  
Cr 4  
Cr 0  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Little-Endian Packing  
63  
58 57  
48 47  
42 41  
3231  
26 25  
16 15  
10 9  
0
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Y 12  
Y 8  
Y 4  
Y 0  
Y 13  
Y 9  
Y 4  
Y 1  
Y 14  
Y 10  
Y 6  
Y 15  
Y 11  
Y 7  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Y 2  
Y 3  
Y FIFO  
63  
63  
58 57  
58 57  
48 47  
48 47  
42 41  
42 41  
3231  
3231  
26 25  
26 25  
16 15  
16 15  
10 9  
10 9  
0
0
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Cb 4  
Cb 0  
Cb 5  
Cb 1  
Cb 6  
Cb 2  
Cb 7  
Cb 3  
0 / SE  
0 / SE  
Cb FIFO  
Cr FIFO  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Cr 4  
Cr 0  
Cr 5  
Cr 1  
Cr 6  
Cr 2  
Cr 7  
Cr 3  
0 / SE  
0 / SE  
Big-Endian Packing  
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Video Capture Port  
3-15  
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Y/C Video Capture Mode  
The 10-bit Y/C dense mode uses three FIFOs for color separation. Three sam-  
ples are packed into each word with zero extension to provide increased DMA  
bandwidth as shown in Figure 3–7.  
Figure 3–7. 10-Bit Y/C Dense FIFO Packing  
VCLKINA  
VDIN[9–0] Y 0  
Y 1  
Y 2  
Y 3  
Y 4  
Y 5  
Y 6  
Y 7  
Y 8  
Y 9 Y 10 Y 11  
VDIN[19–10] Cb 0 Cr 0 Cb 1 Cr 1 Cb 2 Cr 2 Cb 3 Cr 3 Cb 4 Cr 4 Cb 5 Cr 5  
63 61  
00  
00  
00  
00  
5251  
4241  
3231 29  
00  
2019  
10 9  
0
Y 23  
Y 17  
Y 11  
Y 5  
Y 22  
Y 16  
Y 10  
Y 4  
Y 21  
Y 15  
Y 9  
Y 20  
Y 14  
Y 8  
Y 19  
Y 13  
Y 7  
Y 18  
Y 12  
Y 6  
00  
00  
00  
Y 3  
Y 2  
Y 1  
Y 0  
Y FIFO  
63 61  
00  
00  
5251  
5251  
4241  
4241  
3231 29  
00  
2019  
2019  
10 9  
10 9  
0
0
Cb 11  
Cb 5  
Cb 10  
Cb 4  
Cb 9  
Cb 3  
Cb 8  
Cb 2  
Cb 7  
Cb 1  
Cb 6  
Cb 0  
00  
Cb FIFO  
Cr FIFO  
63 61  
00  
00  
3231 29  
00  
Cr 11  
Cr 5  
Cr 10  
Cr 4  
Cr 9  
Cr 3  
Cr 8  
Cr 2  
Cr 7  
Cr 1  
Cr 6  
Cr 0  
00  
Little-Endian Packing  
63 61  
00  
00  
00  
00  
5251  
4241  
3231 29  
2019  
10 9  
0
Y 18  
Y 12  
Y 6  
Y 19  
Y 13  
Y 7  
Y 20  
Y 14  
Y 8  
00  
00  
00  
00  
Y 21  
Y 15  
Y 9  
Y 22  
Y 16  
Y 10  
Y 4  
Y 23  
Y 17  
Y 11  
Y 5  
Y 0  
Y 1  
Y 2  
Y 3  
Y FIFO  
63 61  
00  
00  
5251  
5251  
4241  
4241  
3231 29  
00  
2019  
2019  
10 9  
10 9  
0
0
Cb 6  
Cb 0  
Cb 7  
Cb 1  
Cb 8  
Cb 2  
Cb 9  
Cb 3  
Cb 10  
Cb 4  
Cb 11  
Cb 5  
00  
Cb FIFO  
Cr FIFO  
63 61  
00  
00  
3231 29  
00  
Cr 6  
Cr 0  
Cr 7  
Cr 1  
Cr 8  
Cr 2  
Cr 9  
Cr 3  
Cr 10  
Cr 4  
Cr 11  
Cr 5  
00  
Big-Endian Packing  
3-16  
Video Capture Port  
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BT.656 and Y/C Mode Field and Frame Operation  
3.4 BT.656 and Y/C Mode Field and Frame Operation  
Because DMAs are used to transfer data from the capture FIFOs to memory,  
there is a large amount of flexibility in the way that capture fields and frames  
are transferred and stored in memory. In some cases, for example a DMA  
structure can be created to provide a set of ping-pong or round-robin memory  
buffers to which a continuous stream of fields are stored without DSP interven-  
tion. In other cases, the DSP may need to modify DMA pointer addresses after  
each field or frame is captured. In some applications, only one field may be  
captured and the other ignored completely, or a frame may need to be ignored  
in order to have time to process a previous frame. The video port addresses  
these issues by providing programmable control over different aspects of the  
capture process.  
3.4.1 Capture Determination and Notification  
Thevideoporttreatsthecaptureofeveryfieldasaseparateoperation. Inorder  
to accommodate various capture scenarios, DMA structures, and processing  
flows, the video port employs a flexible capture and DSP notification method.  
This is programmed using the CON, FRAME, CF1, and CF2 bits in VCxCTL.  
The CON bit controls the capture of multiple fields or frames. When CON = 1,  
continuous capture is enabled, the video port captures incoming fields  
(assuming the VCEN bit is set) without the need for DSP interaction. It relies  
on a DMA structure with circular buffering capability to service the capture  
FIFOs. When CON = 0, continuous capture is disabled, the video port sets a  
field or frame capture complete bit (F1C, F2C, or FRMC) in VCxSTAT upon the  
capture of each field as determined by the state of the other capture control  
bits (FRAME, CF1, and CF2). Once the capture complete bit is set, at most,  
one more field or frame can be received before capture operation is halted.  
This prevents subsequent data from overwriting previous fields until the DSP  
has a chance to update DMA pointers or process those fields. When a capture  
halt occurs, the video port stops capturing data (for the halted field). It then  
checks the appropriate capture complete bit at the start of each subsequent  
field and resumes capture if the bit has been cleared.  
The CON, FRAME, CF1, and CF2 bits encode the capture operations as listed  
in Table 3–6.  
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Video Capture Port  
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BT.656 and Y/C Mode Field and Frame Operation  
Table 3–6. BT.656 and Y/C Mode Capture Operation  
VCxCTL Bit  
CON FRAME  
CF2  
CF1 Operation  
0
0
0
0
0
0
1
Reserved  
0
Noncontinuous field 1 capture. Capture only field 1. F1C is set after  
field 1 capture and causes CCMPx to be set. The F1C bit must be  
cleared by the DSP before capture can continue. (The DSP has the  
entire field 2 time to clear F1C before next field 1 begins.) Can also be  
used for single progressive frame capture. (The DSP has vertical  
blanking time to clear F1C before next frame begins.)  
0
0
0
0
1
1
0
1
Noncontinuous field 2 capture. Capture only field 2. F2C is set after  
field 2 capture and causes CCMPx to be set. The F2C bit must be  
cleared by the DSP before capture can continue. (The DSP has the  
entire field 1 time to clear F2C before next field 2 begins.)  
Noncontinuous field 1 and field 2 capture. Capture both fields. F1C is  
set after field 1 capture and causes CCMPx to be set. The F1C bit must  
be cleared by the DSP before another field 1 capture can occur. (The  
DSP has the entire field 2 time to clear F1C before next field 1 begins.)  
F2C is set after field 2 capture and causes CCMPx to be set. The F2C  
bit must be cleared by the DSP before another field 2 capture can  
occur. (The DSP has the entire field 1 time to clear F2C before next  
field 2 begins.)  
0
0
1
1
0
0
0
1
Noncontinuous frame capture. Capture both fields. FRMC is set after  
field 2 capture and causes CCMPx to be set. Capture halts upon  
completion of the next frame unless the FRMC bit is cleared. (The DSP  
has the entire next frame time to clear FRMC.)  
Noncontinuous progressive frame capture. Capture field 1. FRMC is set  
after field 1 capture and causes CCMPx to be set. Capture halts upon  
completion of the next frame unless the FRMC bit is cleared. (The DSP  
has the entire next frame time to clear FRMC.)  
0
0
1
1
1
1
0
1
Reserved  
Single frame capture. Capture both fields. FRMC is set after field 2  
capture and causes CCMPx to be set. Capture halts until the FRMC bit  
is cleared. (The DSP has the field 2 to field 1 vertical blanking time to  
clear FRMC.)  
1
1
0
0
0
0
0
1
Reserved  
Continuous field 1 capture. Capture only field 1. F1C is set after field 1  
capture and causes CCMPx to be set (CCMPx interrupt can be  
disabled). The video port continues capturing field 1 fields, regardless  
of the state of F1C.  
3-18  
Video Capture Port  
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BT.656 and Y/C Mode Field and Frame Operation  
Table 3–6. BT.656 and Y/C Mode Capture Operation (Continued)  
VCxCTL Bit  
CON FRAME CF2  
CF1  
Operation  
1
0
1
0
Continuous field 2 capture. Capture only field 2. F2C is set after field 2  
capture and causes CCMPx to be set (CCMPx interrupt can be  
disabled). The video port continues capturing field 2 fields, regardless  
of the state of F2C.  
1
1
0
1
1
0
1
0
Reserved  
Continuous frame capture. Capture both fields. FRMC is set after  
field 2 capture and causes CCMPx to be set (CCMPx interrupt can be  
disabled). The video port continues capturing frames, regardless of the  
state of FRMC.  
1
1
0
1
Continuous progressive frame capture. Capture field 1. FRMC is set  
after field 1 capture and causes CCMPx to be set (CCMPx interrupt can  
be disabled). The video port continues capturing frames, regardless of  
the state of FRMC. (Functions identically to continuous field 1 capture  
mode except the FRMC bit is used instead of the F1C bit.)  
1
1
1
1
1
1
0
1
Reserved  
Reserved  
3.4.2 Vertical Synchronization  
The video port uses a capture window to determine which incoming data samples  
to capture in each field. The capture module uses a vertical line counter  
(VCOUNT)totrackwhichvideolineiscurrentlybeingreceived. Thelinecount-  
er is compared to the appropriate capture window start (VCYSTART1 or  
VCYSTART2) and stop (VCYSTOP1 or VCYSTOP2) values for the current  
field to determine if the current line is within the capture window. In order to  
correctly align the capture window within the field, the capture module must  
know which line should correspond to the first line of the field, that is, when to  
reset the line counter. This point may vary depending on the type of capture  
being performed and the signals available for vertical synchronization. The  
video port allows the vertical counter reset trigger to be determined by  
programming the EXC and VRST bits in VCxCTL. The encoding of these bits  
is shown in Table 3–7. Note that VModes 2 and 3 are only available for single  
channel operation (channel A).  
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Video Capture Port  
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BT.656 and Y/C Mode Field and Frame Operation  
Table 3–7. Vertical Synchronization Programming  
VCxCTL Bit  
VMode  
EXC  
VRST Vertical Counter Reset Point  
0
0
0
1
0
First EAV with V=1 after EAV with V=0 – beginning of vertical blanking period.  
VCOUNT increments on each EAV.  
1
2
0
1
First EAV with V=0 after EAV with V=1 – first active line. VCOUNT  
increments on each EAV.  
On HCOUNT reset after VCTL2 input active edge – beginning of vertical  
blanking or vertical sync period. (VCTL2 must be configured as vertical  
control signal). VCOUNT increments when HCOUNT is reset.  
3
1
1
On HCOUNT reset after VCTL2 input inactive edge – end of vertical sync or  
first active scan line. (VCTL2 must be configured as vertical control signal).  
VCOUNT increments when HCOUNT is reset.  
VMode 0isusedforBT.656orY/Ccapture(withembeddedcontrol)andcorre-  
sponds to most digital video standards that number lines beginning with the  
start of vertical blanking. VMode 1 can also be used for BT.656 or Y/C capture  
but counts from the first active video line. This makes field detection more  
straightforward in some instances (see section 3.4.4) and allows the  
VCYSTARTn bit to be set to 1, but also has the effect of associating vertical  
blanking periods with the end of the previous field rather than the beginning  
of the current field. (This could be an issue when capturing VBI data.)  
VCOUNT operation for VMode 0 and VMode 1 is shown in Figure 3–8.  
VMode 2 and VMode 3 are used for BT.656 or Y/C capture without embedded  
EAV/SAV codes and allow alignment with either the active or inactive edge of  
the vertical control signal on VCTL2. This can be a VBLNK or VSYNC signal  
from the video decoder.  
3-20  
Video Capture Port  
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BT.656 and Y/C Mode Field and Frame Operation  
Figure 3–8. VCOUNT Operation Example (EXC = 0)  
VRST=0  
VRST=1  
FINV=0  
Field  
FINV=1  
Field  
FINV=0  
Field  
FINV=1  
Field  
V F Line  
VCOUNT  
VCOUNT  
0
1
1
1
1
1
1
1
1
1
0
0
525  
1
262  
1
1
2
2
1
243  
244  
245  
246  
247  
248  
2
1
2
2
3
3
4
4
Field 1 Blanking  
5
5
1
0
0
0
0
0
19  
20  
21  
19  
20  
21  
262  
1
2
1
1
2
2
Field 1 Active  
0
1
1
1
1
0
0
0
1
1
263  
264  
265  
266  
267  
263  
1
2
1
1
2
244  
245  
246  
247  
248  
2
3
Field 2 Blanking  
4
1
0
0
1
1
1
282  
283  
284  
19  
20  
21  
263  
1
1
2
2
1
2
Field 2 Active  
0
0
1
1
1
1
524  
525  
1
261  
262  
1
242  
243  
244  
1
2
2
1
2
1
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Video Capture Port  
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BT.656 and Y/C Mode Field and Frame Operation  
3.4.3 Horizontal Synchronization  
Horizontal synchronization determines when the horizontal pixel/sample  
counter is reset. The EXC and HRST bits in VCxCTL allow you to program the  
event that triggers the start of a line. The encoding of these bits is shown in  
Table 3–8.  
Table 3–8. Horizontal Synchronization Programming  
VCxCTL Bit  
EXC HRST Horizontal Counter Reset Point  
HMode  
0
0
0
1
0
EAV code (H=1) – beginning of horizontal blanking.  
1
2
0
1
SAV code (H=0) – Start of active video.  
VCTL1 input active edge – beginning of horizontal blanking or horizontal  
sync period. (VCTL1 must be configured as a horizontal control signal.)  
3
1
1
VCTL1 input inactive edge – first active pixel on line or end of horizontal  
sync. (VCTL1 must be configured as a horizontal control signal.)  
HMode 0isusedforBT.656orY/Ccapture(withembeddedcontrol)andcorre-  
sponds to the idea that each line begins with the horizontal blanking period.  
It does not align with most standards that start counting with the first active pixel;  
therefore, is only useful if capturing of HANC data before the SAV code is  
desired. HMode 1 is the default mode and corresponds to most digital video  
standards by making the first active pixel pixel0. It has the effect of associating  
horizontal blanking periods with the end of the previous line rather than the  
beginning of the line, but this is only an issue if you try to capture HANC data.  
Ineithermode, HCOUNTincrementsoneveryVCLKINedgeforY/Coperation  
and on every other VCLKIN edge for BT.656 operation but only when CAPEN  
is active. HCOUNT operation for HMode 0 and HMode 1 is shown in  
Figure 3–9.  
HMode 2 and HMode 3 are used for BT.656 or Y/C capture without embedded  
EAV/SAV code and allow alignment with either the beginning of the horizontal  
blanking period or the first active pixel, or the beginning or end of horizontal  
sync depending on the VCTL1 input. When VCTL1 is configured as a horizontal  
control input, no external CAPEN signal is available so the CAPEN signal is  
considered to always be active. HCOUNT operation for HMode 3 and  
HMode 4 is shown in Figure 3–10 for VCTL1 operating as either HSYNC or  
AVID.  
3-22  
Video Capture Port  
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BT.656 and Y/C Mode Field and Frame Operation  
Figure 3–9. HCOUNT Operation Example (EXC = 0)  
VCLKIN  
4
4
268  
1440  
Blanking  
Active Video  
VDIN[9–0]  
EAV Blanking Data  
720 721 722 723  
SAV  
EAV  
Next Line  
One Line  
EXC=0  
HRST=0  
718 719 720 721 722 723  
855 856 857  
0
1
2
HCOUNT  
EXC=0  
HRST=1  
One Line  
Next Line  
854 855 856 857  
0
1
856 857  
0
1
133 134 135 136 273 274  
HCOUNT  
VCOUNT  
n–1  
n
n+1  
Figure 3–10. HCOUNT Operation Example (EXC = 1)  
VCLKIN  
276  
1440  
Active Video  
Blanking  
VDIN[9–0]  
Blanking Data  
HSYNC  
EXC=1  
HRST=0  
842 843 844  
n–1  
857  
0
63 64  
119 120 121 122 123 124  
840 842 842 843 844  
776 777 778 779 780  
HCOUNT  
n
VCOUNT  
EXC=1  
HRST=1  
HCOUNT  
778 779 780  
793 794  
857  
0
55 56 57 58 59 60  
n–1  
n
VCOUNT  
AVID  
EXC=1  
HRST=0  
HCOUNT  
720 721 722  
735 736  
n–1  
799 800  
79 80  
855 856 857  
0
1
2
718 719 720 721 722  
n
VCOUNT  
EXC=1  
HRST=1  
HCOUNT  
0
1
2
15 16  
135 136 137 138 139 140  
856 857  
0
1
2
n
n+1  
VCOUNT  
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BT.656 and Y/C Mode Field and Frame Operation  
3.4.4 Field Identification  
In order to properly synchronize to the source data stream and capture the  
correct fields, field identification needs to be performed. Field identification is  
made using one of three methods: EAV, field indicator input, or field detect  
logic. The field identification method is determined by the EXC, FLDD, and  
FINV bits in VCxCTL.  
Table 3–9. Field Identification Programming  
VCxCTL Bit  
EXC FLDD Field Detect Method  
0
0
1
0
1
EAV code  
0
1
1
EAV code  
Use FID input  
Use field detect (from HSYNC and VSYNC inputs)  
In the BT.656 standard and in many Y/C standards, a field identification (F) bit  
is contained in EAV and SAV codes embedded in the data stream. In the EAV  
field detect method, the F bit in the EAV of the first line of every field ischecked.  
If F = 0, then the current field is defined as field 1. If F = 1, then the current field  
is defined as field 2. Depending on how the first line of a field is defined (as  
determined by the VRST bit in VCxCTL) and the video stream being captured,  
the F value at the start of a field may not reflect the actual field being supplied.  
The FINV bit in VCxCTL allows the detected field value to be inverted. (For  
example, in BT.656 525/60 operation, the F bit changes to 0 to indicate field 1  
on the fourth line of the field. If the VRST bit is cleared so the line counter begins  
counting at line 1 of the field (the first EAV where V is 1), then the F bit still indi-  
cates field 2 (F = 1) and needs to be inverted. If the VRST bit is set to start  
counting lines beginning with the first active line (the first EAV where V is 0),  
the F value will have already changed to indicate field 1 (F = 0) and no inver-  
sion is necessary.)  
The field indicator method uses the FID input directly to determine the current  
field. This is useful for Y/C data streams that do not have embedded EAV and  
SAV codes. The FID input is sampled at the start of each field. If FID = 0, then  
field 1 is starting; if FID = 1, then field 2 is starting. The start of each field is  
defined by the VRST bit in VCxCTL and is either the start or end of vertical  
blanking as determined by the VBLNK input. The FINV bit may be used in this  
method in systems where the FID input has the opposite polarity or where the  
field identification change lags the start of the field.  
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BT.656 and Y/C Mode Field and Frame Operation  
The field detect method uses HYSNC and VSYNC based field detect logic.  
This is used for BT.656 or Y/C systems that provide only HSYNC and VSYNC.  
The field detect logic samples the state of the HSYNC input on the VSYNC  
active edge. If HSYNC is active on the active VSYNC edge, then field 1 is  
detected; if HSYNC is inactive on the active VSYNC edge, then field 2 is detec-  
ted. Becauseofslighttimingvariations, theVSYNCtransitionmaynotcoincide  
exactly with the HSYNC transition. The detection logic should implement a  
±64 clock detection window around HSYNC. If both HSYNC and VSYNC  
leading edges occur within 64 cycles of each other, then field 1 is detected;  
otherwise, field 2 is assumed. This is shown in Figure 3–11 for active-low sync  
signals.  
Figure 3–11.Field 1 Detection Timing  
VCLKIN  
VSYNC#  
(VCTL2)  
64 Clocks  
64 Clocks  
HSYNC#  
(VCTL1)  
3.4.5 Short and Long Field Detect  
The short and long field detect logic is used to notify the DSP when a captured  
field shorter or longer than expected. Detection is enabled by the SFDE and  
LFDE bits in VCxCTL. The SFD and LFD bits in VPIS indicate when a short  
or long field occurred and trigger an interrupt to the DSP if enabled.  
If a vertical blanking period is detected before the end of the capture field, a  
short field is detected . If EAV is used for vertical sync (EXC = 0), then a short  
field is detected when an EAV with V = 1 occurs on or before  
VCOUNT = VCYSTOPn. If the VCTL2 input is used for vertical sync  
(EXC = 1), then a short field is detected if a VCTL2 active edge occurs before  
VCOUNT = VCYSTOPn.  
If a vertical blanking period occurs more than 1 line past the end of the capture  
field,  
a
long field is detected.  
A
long field is detected when  
VCOUNT = VCYSTOPn + 1. (A long field is only detected when the VRST bit  
in VCxCTL is cleared to 0; when VRST = 1, a long field is always detected.)  
Long field detection cannot be used if the capture window is a vertical subset  
of the field that crops lines at the bottom. Such a window would always result  
in a long field detection. If VCTL2 is used for vertical sync, then the VCTL2 sig-  
nal must represent VBLNK (vertical blank) for proper long field detect. If  
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Video Input Filtering  
VCTL2 is a VSYNC (vertical sync) input, then a long field is always detected.  
(Even if VCYSTOPn is set to the last active line, VCOUNT usually increments  
past VCYSTOPn + 1 while it counts the vertical front porch lines that occur  
prior to VSYNC active.)  
3.5 Video Input Filtering  
The video input filter performs simple hardware scaling and resampling on  
incoming 8-bit BT.656 or 8-bit Y/C data. Filtering hardware is always disabled  
during 10-bit or raw data capture modes. For proper filter operation, the  
channel’s EXC bit in VCxCTL must be cleared to 0 (embedded timing refer-  
ence codes used) and the CAPEN input must not go inactive during the active  
video window.  
3.5.1 Input Filter Modes  
The input filter has four modes of operation: no-filtering, ½ scaling, chrominance  
resampling, and ½ scaling with chrominance resampling. Filter operation is  
determined by the CMODE, SCALE, and RESMPL bits of VCxCTL.  
Table 3–10 shows the input filter mode selection. When 8-bit BT.656 or Y/C  
capture operation is selected (CMODE = x00), scaling is selected by setting  
the SCALE bit and chrominance resampling is selected by setting the  
RESMPL bit. If 8-bit BT.656 or Y/C capture is not selected (CMODE ≠ x00),  
filtering is disabled.  
Table 3–10. Input Filter Mode Selection  
VCxCTL Bit  
CMODE  
RESMPL SCALE Filter Operation  
x00  
0
0
1
1
x
x
x
0
1
0
1
x
x
x
No filtering  
x00  
x00  
x00  
x01  
x10  
x11  
½ scaling  
Chrominance resampling (full scale)  
½ scaling with chrominance resampling  
No filtering  
No filtering  
No filtering  
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Video Input Filtering  
3.5.2 Chrominance Resampling Operation  
Chrominance resampling computes chrominance values at sample points  
midway between the input luminance samples based on the input co-sited  
chrominance samples. This filter performs the horizontal portion of a conver-  
sion between YCbCr 4:2:2 format and YCbCr 4:2:0 format. The vertical portion  
of the conversion must be performed in software.  
The chrominance resampling filters calculate the implied value of Cb and Cr  
in between luminance sample points based upon nearby co-sited Cb and Cr  
samples. The resulting values are clamped to between 01h and FEh and sent  
to the Cb and Cr capture buffers. Chrominance resampling is shown in  
Figure 3–12.  
Figure 3–12. Chrominance Resampling  
a
b
c
d
e
f
g
h
i
j
k
l
YCbCr 4:2:2 co-sited  
input samples  
chroma-resampled  
capture results  
Cb’ = (–3Cb + 101Cb + 33Cb –3Cb ) / 128  
ef  
c
e
g
i
Luma (Y)  
–
Chroma (Cb/Cr)  
samples  
Cr’ = (–3Cr + 101Cr + 33Cr – 3Cr ) / 128  
ef  
c
e
g
i
sample  
3.5.3 Scaling Operation  
The ½-scaling mode is used to reduce the horizontal resolution of captured  
luminance and chrominance data by a factor of two. For applications that  
require only CIF or lower resolutions, this reduces the video capture buffer  
memory requirements (and the bandwidth needed to write the buffer) by a  
factor of two. Vertical scaling must be performed in software. (The bandwidth  
to load in the buffer is again reduced by 50% over the nonhorizontal scaled  
case.)  
The filtering for the luminance portion of the scaling filter changes depending  
on if chrominance resampling is also enabled. (By changing the luminance filter,  
the chrominance filters can remain the same.) The resulting values are  
clampedtobetween01handFEhandsenttotheY, Cb, andCrcapturebuffers.  
Scaling for co-sited capture is shown in Figure 3–13 and scaling for chromi-  
nance resampling is shown in Figure 3–14.  
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Video Input Filtering  
Figure 3–13. 1/2 Scaled Co-Sited Filtering  
a
b
c
d
e
f
g
h
i
j
k
l
YCbCr 4:2:2 co-sited  
input samples  
1/2 scaled co-sited  
capture results  
Y’ = (–3Y + 32Y + 70Y + 32Y – 3Y ) / 128  
h
e
g
h
i
k
Luma (Y)  
sample  
Chroma (Cb/Cr)  
–
–
samples  
Y’ = (–3Y + 32Y + 70Y + 32Y – 3Y) / 128  
f
c
e
f
g
i
Cb’ = (–1Cb + 17Cb + 17Cb – 1Cb ) / 32  
f
c
e
g
i
Cr’ = (–1Cr + 17Cr + 17Cr – 1Cr ) / 32  
f
c
e
g
i
Figure 3–14. 1/2 Scaled Chrominance Resampled Filtering  
j
a
b
c
d
e
f
g
h
i
k
l
YCbCr 4:2:2 co-sited  
input samples  
1/2 scaled  
chroma-resampled  
capture results  
Y’ = (–3Y + 32Y + 70Y + 32Y –3Y ) / 128  
g
d
f
g
h
j
Luma (Y)  
–
Chroma (Cb/Cr)  
samples  
–
sample  
Cb’ = (–1Cb + 17Cb + 17Cb – 1Cb ) / 32  
f
c
e
g
i
Cr’ = (–1Cr + 17Cr + 17Cr – 1Cr ) / 32  
f
c
e
g
i
Note that because input scaling is limited to ½, true CIF horizontal resolution  
is not achieved if the full BT.656 horizontal line (720 pixels) is captured. A CIF  
size line can be captured by selecting a 704 pixel-sized window within the  
BT.656 line. This window size and location on the line are programmed using  
the VCXSTARTn and VCXSTOPn bits.  
Note that when ½ scaling is selected, horizontal timing applies to the incoming  
data (before scaling). The VCTHRLD value applies to the data written into the  
FIFO after scaling.  
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Video Input Filtering  
3.5.4 Edge Pixel Replication  
Because the filters make use of preceding and trailing samples, filtering arti-  
facts can occur at the beginning of the BT.656 or Y/C active line because no  
samples exist before the SAV code, and at the end of the BT.656 active line  
because no samples exist after the EAV code. In order to minimize artifacts,  
the first m samples after sample 0 (where m is the maximum number of  
preceding samples used by any of the filters) are mirrored to the left of  
sample 0 and the last m samples before the last sample are mirrored to the  
right of the last sample.  
Figure 3–15 shows edge pixel replication assuming an m value of 3. Sample a  
is the first sample after the SAV code. Therefore, samples b–d are mirrored to  
the left of sample a to provide values for the filter calculations on the first few  
pixels in the line. Likewise, samples n – 1 to n – 3 are mirrored to the right of  
the last sample n to provide values for the last few pixels on the line.  
Note that edge pixel replication only comes into effect when the full BT.656  
stream is being captured. If VCXSTART is greater than 0, then only some of  
the leading edge replicated pixels are used by the filter. If VCXSTART is greater  
than m, then none of the leading edge replicated pixels are used. Similarly, if  
VCXSTOP is less than the number of samples before EAV, then none or only  
some of the trailing edge replicated pixels are used by the filters.  
Figure 3–15. Edge Pixel Replication  
SAV  
a
b
c
d
e
e
n – 4 n – 3 n – 2 n – 1  
n
n
EAV  
Active line  
d
c
b
a
b
c
d
n – 4 n – 3 n – 2 n – 1  
n – 1 n – 2 n – 3  
Leading edge replicated pixels  
Trailing edge replicated pixels  
Luma (Y)  
sample  
Chroma (Cb/Cr)  
samples  
–
–
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Video Input Filtering  
Figure 3–16 shows an example of a capture window that is smaller than the  
BT.656 active line. Sample a is the first sample in the horizontal capture  
window and sample n is the last sample. In this case, any filtering done on the  
first sample location uses the m leading edge captured pixels (m is 3 in this  
example), and any filtering done on the last sample location uses the m trailing  
captured pixels. (From an implementation standpoint, the mirroring and filter-  
ing can still begin and end with SAV and EAV, but the samples before  
VCXSTART or after VCXSTOP must not be saved to the YCbCr buffers.)  
Figure 3–16. Capture Window Not Requiring Edge Pixel Replication  
XSTART  
XSIZE  
SAV  
a–4 a–3a–2 a–1 a  
b
c
d
e
n–4 n–3 n–2 n–1 n n+1 n+2 n+3 n+4  
EAV  
Active line  
n–4 n–3 n–2 n–1 n n+1 n+2 n+3  
a–4 a–3 a–1 a  
b
c
d
e
Leading edge replicated pixels  
Trailing edge replicated pixels  
Chroma (Cb/Cr)  
Luma (Y)  
–
–
sample  
samples  
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Ancillary Data Capture  
3.6 Ancillary Data Capture  
The BT.656 and some Y/C specifications includes provision for carrying ancillary  
(nonvideo) data within the horizontal and vertical blanking regions. Horizontal  
ancillary (HANC) data appears between the EAV code and SAV codes. Vertical  
ancillary(VANC)data, alsocalledverticalblankinginterval(VBI)data, appears  
duringtheactivehorizontallineportionofverticallyblanking(forexample, after  
an SAV with V = 1).  
3.6.1 Horizontal Ancillary (HANC) Data Capture  
No special provisions are made for the capture of HANC data. HANC data may  
be captured using the normal video capture mechanism by programming  
VCXSTRT to occur before the SAV (when HCOUNT is reset by the EAV code)  
or by programming VCXSTOP to occur past the EAV code (when HCOUNT  
is reset by the SAV code). Note that the EAV code and any subsequent HANC  
data will still be YCbCr separated. Software must parse the Y, Cb, and Cr  
memory buffers to determine any HANC data presence and to reconstruct the  
HANC data. The VCTHRLD value and DMA size must be programmed to  
comprehend the additional samples. You must disable scaling and chroma re-  
sampling when including the capture of HANC data to prevent data corruption.  
3.6.2 Vertical Ancillary (VANC) Data Capture  
VANC(or VBI) data is commonly used for such features as teletext andclosed-  
captioning. No special provisions are made for the capture of VBI data. VBI  
data may be captured using the normal capture mechanism by programming  
VCYSTART to occur before the first line of active video on the first line of  
desired VBI data. (VCOUNT must be reset by an EAV with V = 1). Note that  
the VBI data will be YCbCr separated. Software must parse the Y, Cb, and Cr  
memory buffers to determine any VBI data presence and to reconstruct the  
VBI data. You must disable scaling and chroma resampling when the capture  
of VBI data is desired or the data will be corrupted by the filters.  
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Raw Data Capture Mode  
3.7 Raw Data Capture Mode  
In the raw data capture mode, the data is sampled by the interface only when  
the CAPEN signal is active. Data is captured at the rate of the sender’s clock,  
without any interpretation or start/stop of capture based on the data values.  
To ensure initial capture synchronization to the beginning of a frame, an  
optional setup synchronization enable (SSE) bit is provided in VCxSTRT1. If  
the SSE bit is set, then when the VCEN bit is set to 1, the video port will not  
start capturing data until after detecting two vertical blanking intervals. If the  
SSE bit is cleared to 0, capture begins immediately when the VCEN bit is set.  
The incoming digital video capture data is stored in the FIFO, which is 2560-bytes  
(in dual-channel operation) or 5120-bytes deep (in single-channel operation).  
The memory-mapped location YSRCx is associated with the Y buffer. The  
YSRCx location is a read-only register and is used to access video data  
samples stored in the buffer.  
The captured data set size is set byVCxSTOPn. The VCXSTOP and VCYSTOP  
bits set the 24-bits of data set size (VCXSTOP sets the lower 12 bits and  
VCYSTOP sets the upper 12 bits). Capture is complete and the appropriate  
F1C, F2C, or FRMC bit is set when the captured data size reaches the  
combined VCYSTOP and VCXSTOP value.  
The video port generates a YEVT after the specified number of new samples  
has been captured in the buffer. The number of samples required to generate  
YEVTx is programmable and is set in the VCTHRLDn bits of VCxTHRLD. On  
every YEVT, the DMA should move data from the buffer to the DSP memory.  
When moving data from the buffer to the DSP memory, the DMA should use  
the YSRCx location as a source address.  
3.7.1 Raw Data Capture Notification  
Raw data mode captures a single data packet of information using only  
CAPEN for control. Field information is available only for channel A operation  
using the FID input on VCTL3. If the RDFE bit in VCACTL is set, then the video  
port samples the FID input at the start of each data block (when DCOUNT = 0  
and CAPENA is active) to determine the current field. In this case, the CON,  
FRAME, CF1, and CF2 bits in VCxCTL are used in a manner identical to  
BT.656 mode (see section 3.4.1).  
For channel B operation or when the RDFE bit in VCACTL is not set, no field  
information is available. Some flexibility in capture and DSP notification is still  
provided in order to accommodate various DMA structures and processing  
flows. Each raw data packet is treated similar to a progressive scan video  
frame. The raw data mode uses the CON and FRAME bits of VCxCTL in a  
slightly different manner, as listed in Table 3–11.  
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Raw Data Capture Mode  
Table 3–11. Raw Data Mode Capture Operation  
VCxCTL Bit  
CON FRAME  
CF2  
CF1 Operation  
0
0
x
x
Noncontinuous frame capture. FRMC is set after data block capture  
and causes CCMPx to be set. Capture will halt upon completion of the  
next frame unless the FRMC bit is cleared. (DSP has the entire next  
frame time to clear FRMC.)  
0
1
1
0
x
x
x
x
Single frame capture. FRMC is set after data block capture and causes  
CCMPx to be set. Capture is halted until the FRMC bit is cleared.  
Continuous frame capture. FRMC is set after data block capture and  
causes CCMPx to be set (CCMPx interrupt can be disabled). The port  
will continue capturing frames regardless of the state of FRMC.  
1
1
x
x
Reserved  
The CON bit controls the capture of multiple frames. When CON = 1, continuous  
capture is enabled, the video port captures incoming frames (assuming the  
VCEN bit is set) without the need for DSP interaction. It relies on a DMA  
structure with circular buffering capability to service the capture FIFO. When  
CON = 0, continuouscaptureisdisabled, thevideoportsetstheframecapture  
complete bit (FRMC) in VCxSTAT upon the capture of each frame. Once the  
capture complete bit is set, at most, one more frame can be received before  
capture operation is halted (as determined by the FRAME bit state). This  
prevents subsequent data from overwriting previous frames until the DSP has  
a chance to update DMA pointers or process those frames.  
3.7.2 Raw Data FIFO Packing  
Captured data is always packed into 64-bits before being written into the  
capture FIFO(s). The packing and byte ordering is dependant upon the  
capture data size and the device endian mode. For little-endian operation  
(default), data is packed into the FIFO from right to left; for big-endian opera-  
tion, data is packed from left to right.  
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Raw Data Capture Mode  
The 8-bit raw-data mode stores all data in a single FIFO. Four samples are  
packed into each word as shown in Figure 3–17.  
Figure 3–17. 8-Bit Raw Data FIFO Packing  
VCLKINA / VCLKINB  
Raw 0 Raw 1 Raw 2 Raw 3 Raw 4 Raw 5 Raw 6 Raw 7 Raw 8 Raw 9 Raw 10 Raw 11  
VDIN[9–2] / VDIN[19–12]  
63  
63  
5655  
5655  
4847  
4847  
4039  
4039  
3231  
2423  
2423  
1615  
1615  
8 7  
0
0
Raw 15  
Raw 7  
Raw 14  
Raw 6  
Raw 13  
Raw 5  
Raw 12  
Raw 4  
Raw 11  
Raw 3  
Raw 10  
Raw 2  
Raw 9  
Raw 1  
Raw 8  
Raw 0  
Raw FIFO  
Raw FIFO  
Little-Endian Packing  
3231  
8 7  
Raw 8  
Raw 0  
Raw 9  
Raw 1  
Raw 10  
Raw 2  
Raw 11  
Raw 3  
Raw 12  
Raw 4  
Raw 13  
Raw 5  
Raw 14  
Raw 6  
Raw 15  
Raw 7  
Big-Endian Packing  
The 10-bit raw data mode stores all data into a single FIFO. Two samples are  
packed into each word with zero or sign extension as shown in Figure 3–18.  
Figure 3–18. 10-Bit Raw Data FIFO Packing  
VCLKINA / VCLKINB  
VDIN[9–0] / VDIN[19–10]  
Raw 0 Raw 1 Raw 2 Raw 3 Raw 4 Raw 5 Raw 6 Raw 7 Raw 8 Raw 9 Raw 10 Raw 11  
4847 4241 3231 2625 1615 10 9  
63 5857  
0
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Raw 15  
Raw 11  
Raw 7  
Raw 3  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Raw 14  
Raw 10  
Raw 6  
Raw 2  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Raw 13  
Raw 9  
Raw 5  
Raw 1  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Raw 12  
Raw 8  
Raw 4  
Raw 0  
Y FIFO  
Little-Endian Packing  
63  
5857  
4847  
4241  
3231  
2625  
1615  
10 9  
0
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Raw 12  
Raw 8  
Raw 4  
Raw 0  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Raw 13  
Raw 9  
Raw 5  
Raw 1  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Raw 14  
Raw 10  
Raw 6  
Raw 2  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Raw 15  
Raw 11  
Raw 7  
Raw 3  
Y FIFO  
Big-Endian Packing  
3-34  
Video Capture Port  
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Raw Data Capture Mode  
The 10-bit dense raw data mode stores all data into a single FIFO. Three sam-  
ples are packed into each word with zero extension as shown in Figure 3–19.  
Figure 3–19. 10-Bit Dense Raw Data FIFO Packing  
VCLKOUT  
Raw 0 Raw 1 Raw 2 Raw 3 Raw 4 Raw 5 Raw 6 Raw 7 Raw 8 Raw 9 Raw 10 Raw 11  
VDOUT[9–0]  
63 61  
5251  
4241  
3231 29  
2019  
10 9  
0
00  
00  
00  
00  
00  
00  
Raw 17  
Raw 11  
Raw 5  
Raw 16  
Raw 10  
Raw 4  
Raw 15  
Raw 9  
Raw 3  
Raw 14  
Raw 8  
Raw 2  
Raw 13  
Raw 7  
Raw 1  
Raw 12  
Raw 6  
Raw 0  
Y FIFO  
Little-Endian Unpacking  
63 61  
00  
00  
5251  
4241  
3231 29  
00  
2019  
10 9  
0
Raw 12  
Raw 6  
Raw 0  
Raw 13  
Raw 7  
Raw 1  
Raw 14  
Raw 8  
Raw 2  
Raw 15  
Raw 9  
Raw 3  
Raw 16  
Raw 10  
Raw 4  
Raw 17  
Raw 11  
Raw 5  
00  
00  
00  
Y FIFO  
Big-Endian Unpacking  
The 16-bit raw data mode stores all data into a single FIFO. Two samples are  
packed into each word as shown in Figure 3–20.  
Figure 3–20. 16-Bit Raw Data FIFO Packing  
VCLKINA  
Raw 0 Raw 1 Raw 2 Raw 3 Raw 4 Raw 5 Raw 6 Raw 7 Raw 8 Raw 9 Raw 10 Raw 11  
VDIN[19–12] / VDIN[9–2]  
63  
4847  
3231  
1615  
0
0
Raw 11  
Raw 7  
Raw 3  
Raw 10  
Raw 6  
Raw 2  
Raw 9  
Raw 5  
Raw 1  
Raw 8  
Raw 4  
Raw 0  
Raw FIFO  
Little-Endian Packing  
63  
4847  
3231  
1615  
Raw 8  
Raw 4  
Raw 0  
Raw 9  
Raw 5  
Raw 1  
Raw 10  
Raw 6  
Raw 2  
Raw 11  
Raw 7  
Raw 3  
Raw FIFO  
Big-Endian Packing  
SPRU629  
Video Capture Port  
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Raw Data Capture Mode  
The 20-bit raw data mode stores all data into a single FIFO. One sample is  
placed right justified in each word and zero or sign extended as shown in  
Figure 3–21.  
Figure 3–21. 20-Bit Raw Data FIFO Packing  
VCLKINA  
Raw 0 Raw 1 Raw 2 Raw 3 Raw 4 Raw 5 Raw 6 Raw 7 Raw 8 Raw 9 Raw 10 Raw 11  
VDIN[19–0]  
63  
5251  
3231  
19  
20  
0
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Raw 7  
Raw 5  
Raw 3  
Raw 1  
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Raw 6  
Raw 4  
Raw 2  
Raw 0  
Y FIFO  
Little-Endian Packing  
63  
5251  
3231  
2019  
0
0 / SE  
0 / SE  
0 / SE  
0 / SE  
Raw 6  
Raw 4  
Raw 2  
Raw 0  
0 / SE  
Raw 7  
Raw 5  
Raw 3  
Raw 1  
0 / SE  
0 / SE  
0 / SE  
Y FIFO  
Big-Endian Packing  
3-36  
Video Capture Port  
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TSI Capture Mode  
3.8 TSI Capture Mode  
The transport stream interface (TSI) capture mode captures MPEG-2 trans-  
port data.  
3.8.1 TSI Capture Features  
The video port TSI capture mode supports the following features:  
- Supports SYNC detect using the PACSTRT input from a front-end device.  
- Data capture at the rising edge of incoming VCLK1.  
- Parallel data reception.  
- Maximum data rate of 30 Mbytes/second.  
- Programmable packet size.  
- Hardware counter mechanism to timestamp incoming packet data.  
- Programmable filtering of packets with errors.  
- Interrupt to the DSP, based on absolute system time or system time clock  
cycles.  
The video port does not perform following functions; these functions should be  
performed in software:  
- PID filtering  
- Data parsing  
- De-scrambling of data  
3.8.2 TSI Data Capture  
Eight-bit parallel data is received on the input data bus. Data is captured on  
the rising edge of VCLKIN. The data consists typically of 188-byte packets,  
with the first byte a SYNC byte (also called a preamble). The capture packet  
length is determined by the value of VCASTOP.  
Data on the data bus is considered valid and captured only when the CAPEN  
signal is active. TSI data capture begins with a SYNC byte as indicated by  
PACSTRT (and CAPEN) active. (The SYNC byte may have any value.) Data  
is captured on each VCLK rising edge when CAPEN is active until the entire  
packet has been captured, irrespective of additional PACSTRT transitions.  
The end-of-packet condition occurs when the 24-bit capture byte counter (as  
reflected by the VCYPOS and VCXPOS bits of VCASTAT) equals the value in  
the VCYSTOP and VCXSTOP bits of VCASTOP. The captured data includes  
both SYNC byte and the data payload as shown in Figure 3–22.  
After a packet is captured, the video port waits for the next active PACSTRT  
tobegincaptureofanotherpacket. Receivedpacketdataispackedinto64bits  
before being written to the FIFO.  
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Video Capture Port  
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TSI Capture Mode  
Figure 3–22. Parallel TSI Capture  
VCLKIN  
CAPEN  
PACSTRT  
VDIN[9:2]  
Sync Byte  
Byte 1  
Byte 2  
Byte 3  
Byte 4  
Start Capture  
3.8.3 TSI Capture Error Detection  
The video port checks for two types of errors during TSI capture. The first is  
a packet error on the incoming packet as indicated by an active PACERR signal.  
If PACERR is active during any of the first eight bytes of a packet and error  
packet filtering is enabled (ERRFILT bit in TSICTL is set), then the video port  
will ignore (not capture) the incoming data until the next PACSTRT is received.  
If error packet filtering is not enabled or if PACERR becomes active sometime  
after the first eight bytes of the packet, the entire packet is captured and the  
PERR bit is set in the timestamp inserted at the end of the packet.  
The second error detected is an early PACSTRT error. This occurs when an  
active PACSTRT is detected before an entire packet (as determined by the  
packet size programmed in VCASTOP) has been captured. The port will con-  
tinue to capture the expected packet size but will set the PSTERR bit in the  
timestamp inserted at the end of the packet. After capture completion, the port  
will wait for a subsequent PACSTRT before beginning capture of another  
packet.  
3.8.4 Synchronizing the System Clock  
Synchronization is an important aspect of decoding and presenting data in  
real-time digital data delivery systems. This is addressed in MPEG-2 transport  
packets by transmitting timing information in the adaptation fields of selected  
data packets. This value serves as a reference for timing comparison in the  
receiving system. The program clock reference (PCR) header, shown in  
Figure 3–23, is a 48-bit field (six bits are reserved). A 42-bit value is  
transmitted within the 48-bit stream and consists of a 33-bit PCR field that  
represents a 90-kHz clock sample and a 9-bit PCR extension field that repre-  
sents a 27-MHz clock sample. The PCR indicates the expected time at the  
completion of reading the field from the bit stream at the transport decoder.  
The transport data packets are in-sync with the encoder time clock.  
3-38  
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TSI Capture Mode  
Figure 3–23. Program Clock Reference (PCR) Header Format  
47  
15 14  
9
8
0
PCR  
Reserved  
PCR extension  
The video port, in conjunction with the VCXO interpolated control (VIC), allows  
a combined hardware and software solution to synchronize the local system  
time clock (STC) with the encoder time clock reference transmitted in the bit  
stream.  
The video port maintains a hardware counter that counts the system time. The  
counter is driven by a system time clock (STCLK) input driven by an external  
VCXO. The counter is split into two fields: a 33-bit field (PCR base) that counts  
at 90 kHz and a 9-bit field (PCR extension) that counts at 27 MHz. The 9-bit  
counter counts from 0 to 299 at 27 MHz. Each time the 9-bit counter rolls over  
to 0, the 33-bit counter is incremented by 1. This is equivalent to the PCR time-  
stamp transmitted in the bit-stream. The 33-bit field can also be programmed  
to count at 27 MHz for compatibility with the MPEG-1 32-bit PCR, by setting  
the CTMODE bit in VCCTL to 1; in which case, the PCR extension portion of  
the counter is not used. Figure 3–24 shows the system time clock counter  
operation.  
Figure 3–24. System Time Clock Counter Operation  
CTMODE  
27 MHz  
STCLK  
1
0
Counter 233  
PCR Base  
90 kHz  
External VCXO  
Modulo 300  
PCR Extension  
On reception of a packet (during the sync byte), a snapshot of the counter is  
captured. This snapshot, or timestamp, is inserted in the receiving FIFO at the  
end of each data packet. Software uses this timestamp, to determine the devi-  
ation of the local system time clock from the encoder time clock. Any time a  
packet with a PCR header is received, the timestamp for that packet is  
compared with the PCR value by software. A PLL is implemented in software  
to synchronize the STCLK with the encoder time clock value in the PCR. This  
algorithm then drives the VIC, which drives the VDAC output to the external  
VCXO, which supplies STCLK.  
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TSI Capture Mode  
ThesystemtimeclockcounterisinitializedbysoftwarewiththePCRofthefirst  
packet with a PCR header. After initialization, the counter can be reinitialized  
by software upon detecting a discontinuity in subsequent packet PCR header  
values.  
The system time is made available to the DSP at any time through the system  
time clock registers (TSISTCLKL and TSISTCLKM). The DSP can program  
the video port to interrupt the DSP whenever a specific system time is reached  
or whenever a specific number of system time clock cycles have elapsed.  
3.8.5 TSI Data Capture Notification  
Since TSI mode captures only data packets, there is no need for field control.  
Some flexibility in capture and DSP notification is still provided in order to  
accommodate various DMA structures and processing flows. Each TSI data  
packetistreatedsimilartoaprogressivescanvideoframe. TheTSImodeuses  
the CON and FRAME bits of VCACTL in a slightly different manner, as listed  
in Table 3–12.  
The CON bit controls the capture of multiple packets. When CON = 1, continuous  
capture is enabled, the video port captures incoming data packets (assuming  
the VCEN bit is set) without the need for DSP interaction. It relies on a DMA  
structure with circular buffering capability to service the capture FIFO. When  
CON = 0, continuouscaptureisdisabled, thevideoportsetstheframecapture  
complete bit (FRMC) in VCASTAT upon the capture of each packet. Once the  
capture complete bit is set, at most, one more frame can be received before  
capture operation is halted (as determined by the FRAME bit state). This  
preventssubsequentdatafromoverwritingpreviouspacketsuntiltheDSPhas  
a chance to update DMA pointers or process those packets.  
Table 3–12. TSI Capture Mode Operation  
VCACTL Bit  
CON FRAME  
CF2  
CF1 Operation  
0
0
x
x
Noncontinuous packet capture. FRMC is set after packet capture and  
causes CCMPA to be set. Capture will halt upon completion of the next  
data packet unless the FRMC bit is cleared. (DSP has the entire next  
data packet time to clear FRMC.)  
0
1
1
0
x
x
x
x
Single packet capture. FRMC is set after packet capture and causes  
CCMPA to be set. Capture is halted until the FRMC bit is cleared.  
Continuous packet capture. FRMC is set after packet capture and  
causes CCMPA to be set (CCMPx interrupt can be disabled). The port  
will continue capturing packets regardless of the state of FRMC.  
1
1
x
x
Reserved  
3-40  
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TSI Capture Mode  
3.8.6 Writing to the FIFO  
The captured TSI packet data and the associated timestamps are written into  
the receive FIFO. The packet data is written first, followed by the timestamp.  
The FIFO controller controls both data writes and timestamp writes into the  
FIFO. The FIFO data packing is shown in Figure 3–25.  
Figure 3–25. TSI FIFO Packing  
VCLKIN  
TSI 0 TSI 1 TSI 2 TSI 3 TSI 4 TSI 5 TSI 6 TSI 7 TSI 8 TSI 9 TSI 10 TSI 11  
VDIN[9–2]  
63  
63  
5655  
4847  
4847  
4039  
32 31  
2423  
1615  
1615  
87  
87  
0
0
TSI 15  
TSI 7  
TSI 14  
TSI 6  
TSI 13  
TSI 5  
TSI 12  
TSI 4  
TSI 11  
TSI 3  
TSI 10  
TSI 2  
TSI 9  
TSI 1  
TSI 8  
TSI 0  
TSI FIFO  
TSI FIFO  
Little-Endian Packing  
5655  
4039 3231 2423  
TSI 8  
TSI 0  
TSI 9  
TSI 1  
TSI 10  
TSI 2  
TSI 11  
TSI 3  
TSI 12  
TSI 4  
TSI 13  
TSI 5  
TSI 14  
TSI 6  
TSI 15  
TSI 7  
Big-Endian Packing  
The data capture circuitry signals to the synchronizing circuit when to take a  
timestamp of the hardware counters. The FIFO write controller keeps track of  
number of bytes received in a packet. It multiplexes the timestamp data and  
the packet data onto the FIFO write data bus. The timestamp and packet error  
informationareinsertedaftereachpacketintheFIFOandmustusethecorrect  
endian byte ordering. The format for the timestamp is shown in Figure 3–26  
and Figure 3–27.  
Figure 3–26. TSI Timestamp Format (Little Endian)  
63  
62  
61  
42 41  
33 32  
PERR PSTERR  
Reserved  
PCR  
PCR extension  
PCR  
31  
0
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Video Capture Port  
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TSI Capture Mode / Capture Line Boundary Conditions  
Figure 3–27. TSI Timestamp Format (Big Endian)  
63  
31  
15  
56 55  
48 47  
40 39  
32  
16  
PCR(7–0)  
PCR(15–8)  
PCR(23–16)  
PCR(31–24)  
25  
24  
23  
18 17  
PCR extension (6–0)  
PCR32  
Reserved  
PCR ext (8–7)  
8
7
6
5
0
Reserved  
PERR PSTERR  
Reserved  
3.8.7 Reading from the FIFO  
The YSRCA location is associated with the TSI capture buffer. The YSRCA  
location is a read-only pseudo-register and is used to access the TSI data  
samples stored in the buffer.  
The captured data packet size is set by VCASTOP. The VCXSTOP and  
VCYSTOP bits set the 24-bits of TSI packet size (VCXSTOP sets the lower  
12 bits and VCYSTOP sets the upper 12 bits). Capture is complete and the  
FRMC bit is set when the data counter equals the combined VCYSTOP and  
VCXSTOP value.  
The video port generates a YEVT after the specified number of new samples  
has been captured in the buffer. The number of samples required to generate  
YEVT is programmable and is set in the VCTHRLD1 bits of VCATHRLD.  
VCTHRLD1 should be set to the packet size plus 8 bytes of timestamp. On  
every YEVT, the DMA should move data from the buffer to the DSP memory.  
When moving data from the buffer to the DSP memory, the DMA should use  
the memory address of the YSRCA location as a source address.  
3.9 Capture Line Boundary Conditions  
In order to simplify DMA transfers, FIFO doublewords must not contain data  
from more than one capture line. This means that a FIFO write must be  
performed whenever 8 bytes have been received or when the line complete  
condition (HCOUNT = VCXSTOP) occurs. Thus, every captured line begins  
on a doubleword boundary and non-doubleword length lines are padded at the  
end. An example is shown in Figure 3–28.  
3-42  
Video Capture Port  
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Capture Line Boundary Conditions  
In Figure 3–28 (8-bit Y/C mode), the line length is not a doubleword. When the  
condition HCOUNT = VCXSTOP occurs, the FIFO location is written even  
though 8 bytes have not been received. The next capture line then begins in  
the next FIFO location at byte 0. This operation extends to all capture modes.  
In the case of TSI and raw data modes, there are no lines. In these modes, a  
final write at the end of the packet must be performed when the packet data  
count equals the 24-bit combined value of VCXCOUNT and VCYCOUNT.  
Figure 3–28. Capture Line Boundary Example  
IPCOUNT = IMGHSIZE(78)  
VCLKOUT  
VDOUT[9–2]  
Y 72  
Y73  
Y 74  
Y 75  
Y 76  
Y 77 YDEF YDEF YDEF YDEF YDEF YDEF  
Cb 36 Cr 36 Cb 37 Cr 37 Cb 38 Cr 38 CbDEFCrDEFCbDEFCrDEFCbDEFCrDEF  
VDOUT[19–12]  
63  
5655  
4847  
4847  
4039  
4039  
3231  
3231  
2423  
2423  
1615  
1615  
8 7  
0
Y 7  
Y 6  
Y 5  
Y 77  
Y 69  
Y 1  
Y 73  
Y 65  
Line n+1  
Line n  
Y 4  
Y 76  
Y 68  
Y 3  
Y 75  
Y 67  
Y 2  
Y 74  
Y 66  
Y 0  
Y 72  
Y 64  
Y 71  
Y 70  
Y FIFO  
Cb FIFO  
Cr FIFO  
63  
63  
5655  
5655  
8 7  
8 7  
0
0
Cb 7  
Cr 7  
Cb 6  
Line n+1  
Line n  
Cb 5  
Cb 4  
Cb 3  
Cb 2  
Cb 1  
Cb 33  
Cb 0  
Cb 32  
Cb 38  
Cb 37  
Cb 36  
Cb 35  
Cb 34  
4847  
4039  
3231  
2423  
1615  
Cr 6  
Line n+1  
Line n  
Cr 5  
Cr 4  
Cr 3  
Cr 2  
Cr 1  
Cr 33  
Cr 0  
Cr 32  
Cr 38  
Cr 37  
Cr 36  
Cr 35  
Cr 34  
Little-Endian Packing  
63  
5655  
5655  
4847  
4847  
4039  
3231  
3231  
2423  
1615  
1615  
8 7  
0
Y 0  
Y 72  
Y 64  
Y 1  
Y 73  
Y 65  
Line n+1  
Line n  
Y 2  
Y 74  
Y 66  
Y 3  
Y 75  
Y 67  
Y 4  
Y 76  
Y 68  
Y 5  
Y 77  
Y 69  
Y 6  
Y 7  
Y 70  
Y 71  
Y FIFO  
Cb FIFO  
Cr FIFO  
63  
63  
4039  
2423  
8 7  
8 7  
0
0
Cb 0  
Cb 1  
Line n+1  
Line n  
Cb 2  
Cb 3  
Cb 4  
Cb 5  
Cb 6  
Cb 38  
Cb 7  
Cr 7  
Cb 32  
Cb 33  
Cb 34  
Cb 35  
Cb 36  
Cb 37  
5655  
4847  
4039  
3231  
2423  
1615  
Cr 0  
Cr 1  
Line n+1  
Line n  
Cr 2  
Cr 3  
Cr 4  
Cr 5  
Cr 6  
Cr 38  
Cr 32  
Cr 33  
Cr 34  
Cr 35  
Cr 36  
Cr 37  
Big-Endian Packing  
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Capturing Video in BT.656 or Y/C Mode  
3.10 Capturing Video in BT.656 or Y/C Mode  
In order to capture video in the BT.656 or Y/C format, the following steps are  
needed:  
1) Set the last pixel to be captured in VCxSTOP1 and VCxSTOP2 (set the  
VCXSTOP and VCYSTOP bits).  
2) Set the first pixel to be captured in VCxSTRT1 and VCxSTRT2 (set the  
VCXSTART and VCYSTART bits).  
3) Write to VCxTHRLD to set the capture threshold. Every time the number  
of received pixels reaches the number specified by the VCTHRLD1 bits,  
a YEVTx, CbEVTx, and CrEVTx are generated by the video capture  
module. The VCTHRLD1 bits value must be an even number.  
4) Configure a DMA channel to move data from YSRCx to a destination in  
the DSP memory. The channel transfers should be triggered by the  
YEVTx. The size of the transfers should be set to VCTHRLD1/4 for 8-bit  
mode, VCTHRLD1/2 for 10-bit mode, or VCTHRLD1/3 for dense 10-bit  
mode. (This is because 4, 2, or 3 pixels are packed per FIFO word and the  
DMA is moving 32-bit words from YSRCx to the memory). The DMA must  
start on a doubleword boundary and move an even number of words.  
5) Configure a DMA channel to move data from CBSRCx to a destination in  
the DSP memory. The channel transfers should be triggered by the  
CbEVTx. The size of the transfers should be set to VCTHRLD1/8 for 8-bit  
mode, VCTHRLD1/4 for 10-bit mode, or VCTHRLD1/6 for dense 10-bit  
mode. (This is because 4, 2, or 3 pixels are packed per FIFO word, the  
DMA is moving 32-bit words from CBSRCx to the memory, and there are  
half the number of pixels in the Cb FIFO as in the Y FIFO.) The DMA must  
start on a doubleword boundary and move an even number of words.  
6) Configure a DMA channel to move data from CRSRCx to a destination in  
the DSP memory. The channel transfers should be triggered by the  
CrEVTx. The size of the transfers should be set to VCTHRLD1/8 for 8-bit  
mode, VCTHRLD1/4 for 10-bit mode, or VCTHRLD1/6 for dense 10-bit  
mode. (This is because 4, 2, or 3 pixels are packed per FIFO word, the  
DMA is moving 32-bit words from CRSRCx to the memory, and there are  
half the number of pixels in the Cr FIFO as in the Y FIFO.) The DMA must  
start on a double-word boundary and move an even number of words.  
7) Write to the video port interrupt enable register (VPIE) to enable overrun  
(COVRx) and capture complete (CCMPx) interrupts, if desired.  
3-44  
Video Capture Port  
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Capturing Video in BT.656 or Y/C Mode  
8) Write to VCxCTL to:  
- Set capture mode (CMODE = 00x for BT.656 input, 10x for Y/C input).  
- Set desired field/frame operation (CON, FRAME, CF2, CF1 bits).  
- Set sync and field ID control (VRST, HRST, FDD, FINV, VCTL1 bits).  
- Set 10-bit pack mode (10BPK bits), if 10-bit operation is selected.  
- Enable scaling (SCALE and RESMPL bits), if desired and using 8-bit  
data.  
- Set VCEN bit to enable capture.  
9) Capture is enabled at the start of the first frame after VCEN = 1 and begins  
at the start of the first selected field. DMA events are generated as  
triggered by VCxTHRLD1. When a selected field has been captured  
(VCXPOS = VCXSTOP and VCYPOS = VCYSTOP), the F1C, F2C, or  
FRMC bits in VCxSTAT are set and cause the CCMPx bit in VPIS to be set.  
This generates a DSP interrupt, if the CCMPx bit is enabled in VPIE.  
10) If continuous capture is enabled, the video port begins capturing again at  
the start of the next selected field or frame. If noncontinuous field 1 and  
field 2 or frame capture is enabled, the next field or frame is captured,  
during which the DSP must clear the appropriate completion status bit or  
further capture is disabled. If single frame capture is enabled, capture is  
disabled until the DSP clears the FRMC bit.  
3.10.1 Handling FIFO Overrun in BT.656 or Y/C Mode  
In case of a FIFO overrun, the COVRx bit is set in VPIS. This condition initiates  
an interrupt to the DSP, if the overrun interrupt is enabled (setting the COVR  
bit in VPIE enables overrun interrupt).  
The overrun interrupt routine should set the BLKCAP bit in VCxCTL and it  
should reconfigure DMA channel settings. The DMA channel must be reconfi-  
gured for capture of the next frame since the current frame transfer failed. Set-  
ting the BLKCAP bit flushes the capture FIFO and blocks DMA events for the  
channel. As long as the BLKCAP bit is set, the video capture channel ignores  
the incoming data with exception of SAV and EAV codes but the internal counters  
continue counting.  
The BLKCAP bit should be cleared to 0 in order to continue capture. Clearing  
the BLKCAP bit takes effect in the subsequent video field (DMA events are still  
going to be blocked in the video field in which the BLKCAP bit is cleared.)  
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Video Capture Port  
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Capturing Video in Raw Data Mode  
3.11 Capturing Video in Raw Data Mode  
In order to capture video in the raw data mode, the following steps are needed:  
1) SetVCxSTOP1tospecifysizeofanimagetobecaptured(VCXSTOPsets  
the lower 12 bits and VCYSTOP sets the upper 12 bits of the captured  
image size in pixels).  
2) Write to VCxTHRLD to set the capture threshold. Every time the number  
of received pixels reaches the number specified by the VCTHRLD1 bits,  
a YEVTx is generated by the video capture module.  
3) Configure a DMA channel to move data from YSRCx to a destination in  
the DSP memory. The channel transfers should be triggered by the  
YEVTx. The size of the transfers should be set to VCTHRLD1/4 for 8-bit  
mode, VCTHRLD1/3 for dense 10-bit mode, VCTHRLD1/2 for 10-bit or  
16-bit mode, or VCTHRLD1 for 20-bit mode. The DMA must start on a  
doubleword boundary and move an even number of words.  
4) Write to the video port interrupt enable register (VPIE) to enable overrun  
(COVRx) and capture complete (CCMPx) interrupts, if desired.  
5) Write to VCxCTL to:  
- Set capture mode (CMODE = x1x for raw data mode).  
- Choose capture operation (CON, FRAME bits).  
- Set 10-bit pack mode (10BPK bits), if 10-bit operation is selected.  
- Enable raw data sync (RDS), if desired.  
- Set VCEN bit to enable capture.  
6) Capture starts when the ICAPEN signal is asserted and VCEN = 1. Data  
is captured on every VCLKINx rising edge when CAPENx is active. DMA  
events (YEVTx) are generated as triggered by VCxTHRLD1. When a  
complete data block has been captured (DCOUNT = VCYSTOP and  
VCXSTOP combined value), the FRMC bit in VCxSTAT is set causing the  
CCMPx bit in VPIS to be set. This generates a DSP interrupt, if CCMPx  
is enabled in VPIE.  
7) If continuous capture is enabled, the video port begins capturing again on  
the next VCLKIN rising edge when CAPEN is valid. If noncontinuous  
capture is enabled, the next data block is captured during which the DSP  
must clear the FRMC bit or further capture is disabled. If single frame  
capture is enabled, capture is disabled until the DSP clears the FRMC bit  
(at which point, raw data sync must again be performed if enabled).  
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Capturing Video in Raw Data Mode / Capturing Data in TSI Capture Mode  
3.11.1 Handling FIFO Overrun Condition in Raw Data Mode  
In case of a FIFO overrun, the COVRx bit is set in VPIS. This condition initiates  
an interrupt to the DSP, if the overrun interrupt is enabled (setting the COVRx  
bit in VPIE enables overrun interrupt).  
The overrun interrupt routine should set the BLKCAP bit in VCxCTL and it  
should reconfigure DMA channel settings. The DMA channel must be reconfi-  
gured for capture of the next frame since the current frame transfer failed. Set-  
ting the BLKCAP bit flushes the capture FIFO and blocks DMA events for the  
channel. As long as the BLKCAP bit is set, the video capture channel ignores  
the incoming data but the internal data counter continues counting.  
The BLKCAP bit should be cleared to 0 in order to continue capture. Clearing  
the BLKCAP bit takes effect in the subsequent frame after a raw data sync  
period is detected on CAPENx. (DMA events are still going to be blocked in  
the frame in which the BLKCAP bit is cleared.)  
3.12 Capturing Data in TSI Capture Mode  
In order to capture data in TSI capture mode, the following steps are needed:  
1) SetVCASTOP1tospecifysizeofadatapackettobecaptured(VCXSTOP  
sets the lower 12 bits and VCYSTOP sets the upper 12 bits of the data  
packet).  
2) Write to VCxTHRLD to set the capture threshold to the data packet size.  
Every time the number of received bytes reaches the number specified by  
the VCTHRLD1 bits, a YEVTx is generated by the video capture module.  
3) Configure a DMA channel to move data from YSRCA to a destination in  
the DSP memory. The channel transfers should be triggered by the  
VIDEVTA. The size of the transfers should be set to the data packet  
size + 8 bytes of timestamp information. The DMA must start on a double-  
word boundary and move an even number of words.  
4) Write to TSICTL to:  
- Set TSI capture mode (TCMODE = 0 for parallel data, 1 for serial data)  
- Select counter mode (TCMODE)  
- Enable error packet filtering (ERRFILT) if desired  
5) In Sigma-Delta peripheral:  
- Write to the SDCTL register to set the precision for the Sigma Delta  
module.  
- Write to the SDDIV register to set the divider value Sigma Delta inter-  
polation frequency.  
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Video Capture Port  
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Capturing Data in TSI Capture Mode  
6) Write to TSISTCMPL, TSISTCMPM, TSISTMSKL, and TSISTMSKM if  
needed to initiate an interrupt, based on STC absolute time.  
7) Write to TSITICKS if an interrupt is desired every x cycles of STC.  
8) Write to VPCTL to select TSI capture operation (TSI = 1).  
9) WritetoVPIEtoenableoverrun(COVRA)andcapturecomplete(CCMPA)  
interrupts, if desired.  
10) Write to VCACTL to set capture mode (CMODE = 010).  
11) Set VCEN bit in VCACTL to enable capture.  
12) Capture begins on the first VCLKINA rising edge when CAPENA and  
PACSTRT are valid. A DMA event is generated as triggered by  
VCATHRLD1. When the entire packet has been captured  
(DCOUNT = VCYSTOP and VCXSTOP combined value), the FRMC bit  
in VCASTAT is set causing the CCMPx bit in VPIS to be set. This gener-  
ates a DSP interrupt, if CCMPx is enabled in VPIE.  
13) If continuous capture is enabled, the video port begins capturing again on  
the next VCLKINA rising edge when CAPENA and PACSTRT are valid. If  
noncontinuous capture is enabled, the next data packet is captured during  
which the DSP must clear the FRMC bit or further capture is disabled. If  
single frame capture is enabled, capture is disabled until the DSP clears  
the FRMC bit.  
3.12.1 Handling FIFO Overrun Condition in TSI Capture Mode  
In case of a FIFO overrun, the COVRx bit is set in VPIS. This condition initiates  
an interrupt to the DSP, if the overrun interrupt is enabled (setting the COVRx  
bit in VPIE enables overrun interrupt).  
The overrun interrupt routine should set the BLKCAP bit in VCxCTL and it  
should reconfigure DMA channel settings. The DMA channel must be reconfi-  
gured for capture of the next frame since the current frame transfer failed. Set-  
ting the BLKCAP bit flushes the capture FIFO and blocks DMA events for the  
channel. As long as the BLKCAP bit is set, the video capture channel ignores  
the incoming data but the internal data counter continues counting.  
The BLKCAP bit should be cleared to 0 in order to continue capture. Clearing  
the BLKCAP bit takes effect on the next PACSTRT. (DMA events are still going  
to be blocked in the TSI packet in which the BLKCAP bit is cleared.)  
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Video Capture Registers  
3.13 Video Capture Registers  
The registers for controlling the video capture mode of operation are listed in  
Table 3–13. See the device-specific datasheet for the memory address of  
these registers.  
Table 3–13. Video Capture Control Registers  
Acronym  
Register Name  
Section  
VCASTAT  
Video Capture Channel A Status Register  
3.13.1  
VCACTL  
Video Capture Channel A Control Register  
Video Capture Channel A Field 1 Start Register  
Video Capture Channel A Field 1 Stop Register  
Video Capture Channel A Field 2 Start Register  
Video Capture Channel A Field 2 Stop Register  
Video Capture Channel A Vertical Interrupt Register  
Video Capture Channel A Threshold Register  
Video Capture Channel A Event Count Register  
Video Capture Channel B Status Register  
Video Capture Channel B Control Register  
Video Capture Channel B Field 1 Start Register  
Video Capture Channel B Field 1 Stop Register  
Video Capture Channel B Field 2 Start Register  
Video Capture Channel B Field 2 Stop Register  
Video Capture Channel B Vertical Interrupt Register  
Video Capture Channel B Threshold Register  
Video Capture Channel B Event Count Register  
TSI Capture Control Register  
3.13.2  
3.13.3  
3.13.4  
3.13.5  
3.13.6  
3.13.7  
3.13.8  
3.13.9  
3.13.1  
3.13.10  
3.13.3  
3.13.4  
3.13.5  
3.13.6  
3.13.7  
3.13.8  
3.13.9  
3.13.11  
3.13.12  
3.13.13  
3.13.14  
3.13.15  
VCASTRT1  
VCASTOP1  
VCASTRT2  
VCASTOP2  
VCAVINT  
VCATHRLD  
VCAEVTCT  
VCBSTAT  
VCBCTL  
VCBSTRT1  
VCBSTOP1  
VCBSTRT2  
VCBSTOP2  
VCBVINT  
VCBTHRLD  
VCBEVTCT  
TSICTL  
TSICLKINITL  
TSICLKINITM  
TSISTCLKL  
TSISTCLKM  
TSI Clock Initialization LSB Register  
TSI Clock Initialization MSB Register  
TSI System Time Clock LSB Register  
TSI System Time Clock MSB Register  
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Video Capture Port  
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Video Capture Registers  
Table 3–13. Video Capture Control Registers (Continued)  
Acronym  
Register Name  
Section  
TSISTCMPL  
TSI System Time Clock Compare LSB Register  
3.13.16  
TSISTCMPM  
TSISTMSKL  
TSISTMSKM  
TSITICKS  
TSI System Time Clock Compare MSB Register  
TSI System Time Clock Compare Mask LSB Register  
TSI System Time Clock Compare Mask MSB Register  
TSI System Time Clock Ticks Interrupt Register  
3.13.17  
3.13.18  
3.13.19  
3.13.20  
3.13.1 Video Capture Channel x Status Register (VCASTAT, VCBSTAT)  
The video capture channel x status register (VCASTAT, VCBSTAT) indicates  
the current status of the video capture channel. The VCxSTAT is shown in  
Figure 3–29 and described in Table 3–14.  
In BT.656 capture mode, the VCXPOS and VCYPOS bits indicate the  
HCOUNT and VCOUNT values, respectively, to track the coordinates of the  
most recently received pixel. The F1C, F2C, and FRMC bits indicate comple-  
tion of fields or frames and may need to be cleared by the DSP for capture to  
continue, depending on the selected frame capture operation (see section 3.4.1).  
In raw data and TSI modes, the VCXPOS and VCYPOS bits reflect the lower  
and upper 12 bits, respectively, of the 24-bit data counter that tracks the  
numberofreceiveddatasamples. TheFRMCbitindicateswhenanentiredata  
packet has been received and may need to be cleared by the DSP for capture  
to continue, depending on the selected frame operation (see section 3.7.1 and  
section 3.8.5).  
Figure 3–29. Video Capture Channel x Status Register (VCASTAT, VCBSTAT)  
31  
FSYNC  
R-0  
30  
29  
28  
27  
16  
0
FRMC  
F2C  
F1C  
VCYPOS  
R-0  
R/WC-0 R/WC-0 R/WC-0  
15  
13  
12  
VCFLD  
R-0  
11  
Reserved  
R-0  
VCXPOS  
R-0  
Legend: R = Read only; WC = Write 1 to clear, write of 0 has no effect; -n = value after reset  
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Video Capture Registers  
Table 3–14. Video Capture Channel x Status Register (VCxSTAT)  
Field Descriptions  
Description  
†
†
BT.656 or Y/C Mode Raw Data Mode  
TSI Mode  
Bit  
field  
symval  
Value  
31  
FSYNC  
Current frame sync bit.  
CLEARD  
SET  
0
VCOUNT = VINT1 or Not used.  
VINT2, as selected  
by the FSCL2 bit  
Not used.  
in VCxVINT.  
1
VCOUNT = 1  
in field 1.  
Not used.  
Not used.  
30  
FRMC  
Frame (data) captured bit. Write 1 to clear the bit, a write of 0  
has no effect.  
NONE  
0
1
Complete frame has Complete data  
Entire data packet  
has not been  
captured.  
not been captured.  
block has not  
been captured.  
CAPTURED  
CLEAR  
Complete frame has Complete data  
Entire data packet  
has been  
captured.  
been captured.  
block has been  
captured.  
29  
F2C  
Field 2 captured bit. Write 1 to clear the bit, a write of 0 has no  
effect.  
NONE  
0
1
Field 2 has not been Not used.  
captured.  
Not used.  
CAPTURED  
CLEAR  
Field 2 has been  
captured.  
Not used.  
Not used.  
28  
F1C  
Field 1 captured bit. Write 1 to clear the bit, a write of 0 has no  
effect.  
NONE  
0
1
Field 1 has not been Not used.  
captured.  
Not used.  
CAPTURED  
CLEAR  
Field 1 has been  
captured.  
Not used.  
Not used.  
†
For CSL implementation, use the notation VP_VCxSTAT_field_symval  
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Video Capture Port  
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Video Capture Registers  
Table 3–14. Video Capture Channel x Status Register (VCxSTAT)  
Field Descriptions (Continued)  
Description  
†
†
BT.656 or Y/C Mode Raw Data Mode  
TSI Mode  
Bit  
field  
symval  
Value  
27–16 VCYPOS OF(value)  
0–FFFh Current VCOUNT  
value and the line  
Upper 12 bits of  
the data counter.  
Upper 12 bits of  
the data counter.  
that is currently being  
received (within the  
current field).  
15–13 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
12  
VCFLD  
VCFLD bit indicates which field is currently being captured.  
The VCFLD bit is updated based on the field detection logic  
selected by the FLDD bit in VCACTL.  
NONE  
0
1
Field 1 is active.  
Field 2 is active.  
Not used.  
Not used.  
Not used.  
Not used.  
DETECTED  
11–0 VCXPOS OF(value)  
0–FFFh Current HCOUNT  
value. The pixel  
Lower 12 bits of  
the data counter.  
Lower 12 bits of  
the data counter.  
index of the last  
received pixel.  
†
For CSL implementation, use the notation VP_VCxSTAT_field_symval  
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Video Capture Registers  
3.13.2 Video Capture Channel A Control Register (VCACTL)  
Video capture is controlled by the video capture channel A control register  
(VCACTL) shown in Figure 3–30 and described in Table 3–15.  
Figure 3–30. Video Capture Channel A Control Register (VCACTL)  
31  
30  
29  
24  
RSTCH  
R/WS-0  
BLKCAP  
R/W-1  
Reserved  
R-0  
23  
22  
21  
20  
19  
18  
17  
16  
Reserved  
R-0  
RDFE  
R/W-0  
FINV  
R/W-0  
EXC  
FLDD  
R/W-0  
VRST  
R/W-1  
HRST  
R/W-0  
R/W-0  
15  
14  
13  
12  
11  
10  
9
8
VCEN  
R/W-0  
PK10B  
R/W-0  
LFDE  
R/W-0  
SFDE  
R/W-0  
RESMPL  
R/W-0  
Reserved  
R-0  
SCALE  
R/W-0  
7
6
5
4
3
2
0
CON  
R/W-0  
FRAME  
R/W-0  
CF2  
CF1  
Reserved  
R-0  
CMODE  
R/W-0  
R/W-1  
R/W-1  
Legend: R = Read only; R/W = Read/Write; WS = Write 1 to reset, write of 0 has no effect; -n = value after reset  
Table 3–15. Video Capture Channel A Control Register (VCACTL)  
Field Descriptions  
Description  
†
†
Bit  
field  
symval  
Value BT.656 or Y/C Mode  
Raw Data Mode  
TSI Mode  
31  
RSTCH  
Reset channel bit. Write 1 to reset the bit, a write of 0 has no  
effect.  
NONE  
0
1
No effect.  
RESET  
Resets the channel by blocking further DMA event generation  
and flushing the FIFO upon completion of any pending DMAs.  
Also clears the VCEN bit. All channel registers are set to their  
initial values. RSTCH is autocleared after channel reset is complete.  
†
‡
For CSL implementation, use the notation VP_VCACTL_field_symval  
For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.  
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Video Capture Port  
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Video Capture Registers  
Table 3–15. Video Capture Channel A Control Register (VCACTL)  
Field Descriptions (Continued)  
Description  
†
†
Bit  
field  
symval  
Value BT.656 or Y/C Mode  
Raw Data Mode  
TSI Mode  
30  
BLKCAP  
Block capture events bit. BLKCAP functions as a capture FIFO  
reset without affecting the current programmable register values.  
The F1C, F2C, and FRMC status bits, in VCASTAT, are not  
updated. Field or frame complete interrupts and vertical interrupts  
are also not generated.  
Clearing BLKCAP does not enable DMA events during the field  
where the bit is cleared. Whenever BLKCAP is set and then  
cleared, the software needs to clear the field and frame status  
bits (F1C, F2C, and FRMC) as part of the BLKCAP clear  
operation.  
CLEAR  
0
Enables DMA events in the video frame that follows the video  
frame where the bit is cleared. (The capture logic must sync to  
the start of the next frame after BLKCAP is cleared.)  
BLOCK  
1
0
Blocks DMA events and flushes the capture channel FIFOs.  
29–22 Reserved  
–
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
21  
RDFE  
Field identification enable bit. (Channel A only)  
DISABLE  
ENABLE  
0
1
Not used.  
Field identification Not used.  
is disabled.  
Not used.  
Field identification Not used.  
is enabled.  
20  
19  
FINV  
EXC  
Detected field invert bit.  
Detected 0 is field 1.  
Detected 0 is field 2.  
FIELD1  
FIELD2  
0
1
Not used.  
Not used.  
Not used.  
Not used.  
External control select bit. (Channel A only)  
EAVSAV  
EXTERN  
0
1
Use EAV/SAV codes.  
Not used.  
Not used.  
Not used.  
Not used.  
Use external control  
signals.  
†
‡
For CSL implementation, use the notation VP_VCACTL_field_symval  
For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.  
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Video Capture Registers  
Table 3–15. Video Capture Channel A Control Register (VCACTL)  
Field Descriptions (Continued)  
Description  
†
†
Bit  
field  
symval  
Value BT.656 or Y/C Mode  
Raw Data Mode  
TSI Mode  
18  
FLDD  
Field detect method bit. (Channel A only)  
st  
EAVFID  
FDL  
0
1
1
line EAV or FID  
Not used.  
Not used.  
Not used.  
input.  
Field detect logic.  
Not used.  
17  
VRST  
VCOUNT reset method bit.  
V1EAV  
V0EAV  
0
1
Start of vertical blank  
(1 V = 1 EAV or  
VCTL2 active edge)  
Not used.  
Not used.  
Not used.  
st  
End of vertical blank  
Not used.  
st  
(1 V = 0 EAV or  
VCTL2 inactive edge)  
16  
15  
HRST  
VCEN  
HCOUNT reset method bit.  
EAV  
SAV  
0
1
EAV or  
Not used.  
Not used.  
Not used.  
VCTL1 active edge.  
SAV or  
Not used.  
VCTL1 inactive edge.  
Video capture enable bit. Other bits in VCACTL (except RSTCH  
and BLKCAP bits) may only be changed when VCEN = 0.  
DISABLE  
ENABLE  
0
1
Video capture is disabled.  
Video capture is enabled.  
10-bit packing format select bit.  
14–13 PK10B  
ZERO  
0
Zero extend  
Sign extend  
Zero extend  
Sign extend  
Not used.  
Not used.  
SIGN  
1h  
2h  
DENSEPK  
Dense pack (zero  
extend)  
Dense pack (zero Not used.  
extend)  
–
3h  
Reserved  
Reserved  
Not used.  
†
‡
For CSL implementation, use the notation VP_VCACTL_field_symval  
For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.  
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Video Capture Registers  
Table 3–15. Video Capture Channel A Control Register (VCACTL)  
Field Descriptions (Continued)  
Description  
†
†
Bit  
field  
symval  
Value BT.656 or Y/C Mode  
Raw Data Mode  
TSI Mode  
12  
LFDE  
Long field detect enable bit.  
DISABLE  
ENABLE  
0
1
Long field detect  
is disabled.  
Not used.  
Not used.  
Not used.  
Long field detect  
is enabled.  
Not used.  
11  
10  
SFDE  
Short field detect enable bit.  
DISABLE  
ENABLE  
0
1
Short field detect  
is disabled.  
Not used.  
Not used.  
Not used.  
Short field detect  
is enabled.  
Not used.  
RESMPL  
Chroma resampling enable bit.  
DISABLE  
ENABLE  
0
1
Chroma resampling is  
disabled.  
Not used.  
Not used.  
Not used.  
Chroma is horizontally  
resampled from  
Not used.  
4:2:2 co-sited to  
4:2:0 interspersed  
before saving to  
chroma buffers.  
9
8
Reserved  
SCALE  
–
0
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
Scaling select bit.  
NONE  
HALF  
0
1
No scaling  
Not used.  
Not used.  
Not used.  
Not used.  
½ scaling  
‡
7
CON  
Continuous capture enable bit.  
Continuous capture is disabled.  
Continuous capture is enabled.  
DISABLE  
ENABLE  
0
1
†
‡
For CSL implementation, use the notation VP_VCACTL_field_symval  
For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.  
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Video Capture Registers  
Table 3–15. Video Capture Channel A Control Register (VCACTL)  
Field Descriptions (Continued)  
Description  
†
†
Bit  
field  
symval  
Value BT.656 or Y/C Mode  
Raw Data Mode  
TSI Mode  
‡
6
FRAME  
Capture frame (data) bit.  
NONE  
0
1
Do not capture frame.  
Do not capture Do not capture  
single data block.  
single packet.  
FRMCAP  
Capture frame.  
Capture single  
data block.  
Capture single  
packet.  
‡
5
4
CF2  
Capture field 2 bit.  
NONE  
0
1
Do not capture field 2.  
Do not capture  
field 2.  
Not used.  
Not used.  
FLDCAP  
Capture field 2.  
Capture field 2.  
‡
CF1  
Capture field 1 bit.  
Do not capture field 1.  
NONE  
0
Do not capture  
field 1.  
Not used.  
Not used.  
FLDCAP  
1
0
Capture field 1.  
Capture field 1.  
3
Reserved  
CMODE  
–
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
2–0  
Capture mode select bit.  
BT656B  
BT656D  
RAWB  
RAWD  
YCB  
0
Enables 8-bit BT.656 mode.  
Enables 10-bit BT.656 mode.  
Enables 8-bit raw data mode.  
Enables 10-bit raw data mode.  
Enables 16-bit Y/C mode.  
Enables 20-bit Y/C mode.  
Enables 16-bit raw mode.  
Enables 20-bit raw mode.  
Not used.  
Not used.  
8-bit TSI mode.  
Not used.  
Not used.  
Not used.  
Not used.  
Not used.  
1h  
2h  
3h  
4h  
5h  
6h  
7h  
YCD  
RAW16  
RAW20  
†
‡
For CSL implementation, use the notation VP_VCACTL_field_symval  
For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.  
SPRU629  
Video Capture Port  
3-57  
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Video Capture Registers  
3.13.3 Video Capture Channel x Field 1 Start Register (VCASTRT1, VCBSTRT1)  
The captured image is a subset of the incoming image. The video capture  
channel x field 1 start register (VCASTRT1, VCBSTRT1) defines the start of  
the field 1 captured image. Note that the size is defined relative to incoming  
data (before scaling). VCxSTRT1 is shown in Figure 3–31 and described in  
Table 3–16.  
InBT.656orY/Cmodes, thehorizontal(pixel)counterisreset(to0)bythehori-  
zontal event (as selected by the HRST bit in VCxCTL) and the vertical (line)  
counter is reset (to 1) by the vertical event (as selected by the VRST bit in  
VCxCTL). Field  
1
capture starts when HCOUNT = VCXSTART,  
VCOUNT = VCYSTART, and field 1 capture is enabled.  
In raw capture mode, the VCVBLNKP bits defines the minimum vertical blank-  
ing period. If CAPEN stays deasserted longer than VCVBLNKP clocks, then  
a vertical blanking interval is considered to have occurred. If the SSE bit is set  
when the capture first begins (the VCEN bit is set in VCxCTL), the capture  
does not start until two intervals are counted. This allows the video port to syn-  
chronize its capture to the top of a frame when first started.  
In TSI capture mode, the capture starts when the CAPEN signal is asserted,  
the FRMC bit (in VCxSTAT) is cleared, and a SYNC byte is detected.  
Figure 3–31. Video Capture Channel x Field 1 Start Register (VCASTRT1, VCBSTRT1)  
31  
28 27  
16  
0
Reserved  
R-0  
VCYSTART  
R/W-0  
15  
14  
12 11  
SSE  
Reserved  
R-0  
VCXSTART/VCVBLNKP  
R/W-0  
R/W-1  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
3-58  
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Video Capture Registers  
Table 3–16. Video Capture Channel x Field 1 Start Register (VCxSTRT1) Field Descriptions  
Description  
†
†
Bit  
field  
symval  
Value BT.656 or Y/C Mode  
Raw Data Mode  
TSI Mode  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
27–16 VCYSTART OF(value)  
15 SSE  
0–FFFh Starting line number.  
Not used.  
Not used.  
Startup synchronization enable bit.  
DISABLE  
ENABLE  
–
0
1
0
Not used.  
Not used.  
Startup  
synchronization is  
disabled.  
Not used.  
Startup  
synchronization is  
enabled.  
Not used.  
14–12 Reserved  
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
11–0 VCXSTART OF(value)  
0–FFFh VCXSTART bits define VCVBLNKP bits  
Not used.  
the starting pixel  
number. Must be an  
even number (LSB is  
treated as 0).  
define the minimum  
CAPEN inactive  
time to be  
interpreted as a  
vertical blanking  
period.  
VCVBLNKP  
†
For CSL implementation, use the notation VP_VCxSTRT1_field_symval  
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Video Capture Registers  
3.13.4 Video Capture Channel x Field 1 Stop Register (VCASTOP1, VCBSTOP1)  
The video capture channel x field 1 stop register (VCASTOP1, VCBSTOP1)  
defines the end of the field 1-captured image or the end of the raw data or TSI  
packet. VCxSTOP1 is shown in Figure 3–32 and described in Table 3–17.  
In raw capture mode, the horizontal and vertical counters are combined into  
a single counter that keeps track of the total number of samples received.  
In TSI capture mode, the horizontal and vertical counters are combined into  
a single data counter that keeps track of the total number of bytes received.  
The capture starts when a SYNC byte is detected. The data counter counts  
bytes as they are received. The FRMC bit (in VCxSTAT) gets set each time a  
packet has been received.  
Figure 3–32. Video Capture Channel x Field 1 Stop Register (VCASTOP1, VCBSTOP1)  
31  
28 27  
16  
Reserved  
R-0  
VCYSTOP  
R/W-0  
15  
12 11  
0
Reserved  
R-0  
VCXSTOP  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 3–17. Video Capture Channel x Field 1 Stop Register (VCxSTOP1) Field Descriptions  
Description  
†
†
Bit  
field  
symval  
Value BT.656 or Y/C Mode Raw Data Mode  
TSI Mode  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
27–16 VCYSTOP OF(value)  
0–FFFh Last captured line. Upper 12 bits of the Upper 12 bits of  
data size (in data  
samples).  
the data size (in  
data samples).  
15–12 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
11–0 VCXSTOP OF(value)  
0–FFFh Last captured pixel  
(VCXSTOP – 1).  
Lower 12 bits of the Lower 12 bits of  
data size (in data  
samples).  
the data size (in  
data samples).  
Must be an even  
value (the LSB is  
treated as 0).  
†
For CSL implementation, use the notation VP_VCxSTOP1_field_symval  
3-60  
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Video Capture Registers  
3.13.5 Video Capture Channel x Field 2 Start Register (VCASTRT2, VCBSTRT2)  
The captured image is a subset of the incoming image. The video capture  
channel x field 2 start register (VCASTRT2, VCBSTRT2) defines the start of  
the field 2 captured image. (This allows different window alignment or size for  
each field.) Note that the size is defined relative to incoming data (before  
scaling). VCxSTRT2 is shown in Figure 3–33 and described in Table 3–18.  
In BT.656 or Y/C modes, the horizontal (pixel) counter is reset by the horizontal  
event (as selected by the HRST bit in VCxCTL) and the vertical (line) counter  
is reset by the vertical event (as selected by the VRST bit in VCxCTL). Field 2  
capture starts when HCOUNT = VCXSTART, VCOUNT = VCYSTART, and  
field 2 capture is enabled.  
These registers are not used in raw data mode or TSI mode because their  
capture sizes are completely defined by the field 1 start and stop registers.  
Figure 3–33. Video Capture Channel x Field 2 Start Register (VCASTRT2, VCBSTRT2)  
31  
28 27  
16  
0
Reserved  
R-0  
VCYSTART  
R/W-0  
15  
12 11  
Reserved  
R-0  
VCXSTART  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 3–18. Video Capture Channel x Field 2 Start Register (VCxSTRT2) Field Descriptions  
Description  
†
†
Bit  
field  
symval  
Value BT.656 or Y/C Mode  
Raw Data Mode  
TSI Mode  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
27–16 VCYSTART OF(value)  
15–12 Reserved  
0–FFFh Starting line number.  
Not used.  
Not used.  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
11–0 VCXSTART OF(value)  
0–FFFh Starting pixel number.  
Must be an even number  
(LSB is treated as 0).  
Not used.  
Not used.  
†
For CSL implementation, use the notation VP_VCxSTRT2_field_symval  
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Video Capture Port  
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Video Capture Registers  
3.13.6 Video Capture Channel x Field 2 Stop Register (VCASTOP2, VCBSTOP2)  
The video capture channel x field 2 stop register (VCASTOP2, VCBSTOP2)  
defines the end of the field 2-captured image. VCxSTOP2 is shown in  
Figure 3–34 and described in Table 3–19.  
These registers are not used in raw data mode or TSI mode because their  
capture sizes are completely defined by the field 1 start and stop registers.  
Figure 3–34. Video Capture Channel x Field 2 Stop Register (VCASTOP2, VCBSTOP2)  
31  
28 27  
16  
Reserved  
R-0  
VCYSTOP  
R/W-0  
15  
12 11  
0
Reserved  
R-0  
VCXSTOP  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 3–19. Video Capture Channel x Field 2 Stop Register (VCxSTOP2) Field Descriptions  
Description  
†
†
Bit  
field  
symval  
Value BT.656 or Y/C Mode  
Raw Data Mode  
TSI Mode  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
27–16 VCYSTOP OF(value)  
15–12 Reserved  
0–FFFh Last captured line.  
Not used.  
Not used.  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
11–0 VCXSTOP OF(value)  
0–FFFh Last captured pixel  
(VCXSTOP – 1). Must be  
Not used.  
Not used.  
an even value (the LSB is  
treated as 0).  
†
For CSL implementation, use the notation VP_VCxSTOP2_field_symval  
3-62  
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Video Capture Registers  
3.13.7 Video Capture Channel x Vertical Interrupt Register (VCAVINT, VCBVINT)  
The video capture channel x vertical interrupt register (VCAVINT, VCBVINT)  
controls the generation of vertical interrupts in each field. VCxVINT is shown  
in Figure 3–35 and described in Table 3–20.  
In BT.656 or Y/C mode, an interrupt can be generated upon completion of the  
specified line in a field (end of line when VCOUNT = VINTn). This allows the  
softwaretosynchronizetotheframeorfield. Theinterruptcanbeprogrammed  
to occur in one or both fields (or not at all) using the VIF1 and VIF2 bits. The  
VINTn bits also determine when the FSYNC bit in VCxSTAT is cleared. If  
FSCL2 is 0, then the FSYNC bit is cleared in field 1 when VCOUNT = VINT1;  
if FSCL2 is 1, then the FSYNC bit is cleared in field 2 when VCOUNT = VINT2.  
Figure 3–35. Video Capture Channel x Vertical Interrupt Register (VCAVINT, VCBVINT)  
31  
30  
FSCL2 Reserved  
R-0  
29  
28 27  
16  
0
VIF2  
VINT2  
R/W-0  
R/W-0 R/W-0  
15  
14  
12 11  
VIF1  
R/W-0  
Reserved  
R-0  
VINT1  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
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Video Capture Registers  
Table 3–20. Video Capture Channel x Vertical Interrupt Register (VCxVINT)  
Field Descriptions  
Description  
†
†
Bit  
field  
symval  
Value BT.656 or Y/C Mode  
Raw Data Mode  
TSI Mode  
31  
VIF2  
Setting of VINT in field 2 enable bit.  
DISABLE  
ENABLE  
0
1
Setting of VINT in field 2 is  
disabled.  
Not used.  
Not used.  
Not used.  
Not used.  
Setting of VINT in field 2 is  
enabled.  
30  
FSCL2  
FSYNC bit cleared in field 2 enable bit.  
NONE  
0
1
FSYNC bit is not cleared.  
Not used.  
Not used.  
Not used.  
Not used.  
FIELD2  
FSYNC bit is cleared in  
field 2 instead of field 1.  
29–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
27–16 VINT2  
OF(value)  
0–FFFh Line that vertical interrupt  
Not used.  
Not used.  
occurs if VIF2 bit is set.  
15  
VIF1  
Setting of VINT in field 1 enable bit.  
DISABLE  
ENABLE  
–
0
1
0
Setting of VINT in field 1 is  
disabled.  
Not used.  
Not used.  
Not used.  
Setting of VINT in field 1 is  
enabled.  
Not used.  
14–12 Reserved  
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
11–0 VINT1  
OF(value)  
0–FFFh Line that vertical interrupt  
Not used.  
Not used.  
occurs if VIF1 bit is set.  
†
For CSL implementation, use the notation VP_VCxVINT_field_symval  
3-64  
Video Capture Port  
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Video Capture Registers  
3.13.8 Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD)  
The video capture channel x threshold register (VCATHRLD, VCBTHRLD)  
determines when DMA requests are sent. VCxTHRLD is shown in  
Figure 3–36 and described in Table 3–21.  
The VCTHRLD1 bits determine when capture DMA events are generated.  
Once the threshold is reached, generation of further DMA events is disabled  
until service of the previous event(s) begins (the first FIFO read by the DMA  
occurs).  
In BT.656 and Y/C modes, every two captured pixels represent 2 luma values  
in the Y FIFO and 2 chroma values (1 each in the Cb and Cr FIFOs). Depend-  
ing on the data size and packing mode, each value may be a byte (8-bit BT.656  
or Y/C), half-word (10-bit BT.656 or Y/C), or subword (dense pack 10-bit  
BT.656 or Y/C) within the FIFOs. Therefore, the VCTHRLD1 doubleword  
number represents 8 pixels in 8-bit modes, 4 pixels in 10-bit modes, or 6 pixels  
in dense pack 10-bit modes. Since the Cb and Cr FIFO thresholds are repre-  
sented by ½ VCTHRLD1, certain restrictions are placed on what VCTHRLD1  
values are valid (see section 2.3.3).  
In raw data mode, each data sample may occupy a byte (8-bit raw mode), half-  
word (10-bit or 16-bit raw mode), subword (dense pack 10-bit raw mode), or  
word (20-bit raw mode) within the FIFO, depending on the data size and pack-  
ing mode. Therefore, the VCTHRLD1 doubleword number represents 8 sam-  
ples, 4, samples, 6 samples, or 2 samples, respectively.  
In TSI mode, VCTHRLD1 represents groups of 8 samples with each sample  
occupying a byte in the FIFO.  
The VCTHRLD2 bits behave identically to VCTHRLD1, but are used during  
field 2 capture. It is only used if the field 2 DMA size needs to be different from  
the field 1 DMA size for some reason (for example, different captured line  
lengths in field 1 and field 2). If VT2EN is not set, then the VCTHRLD1 value  
is used for both fields.  
Note that the VCTHRLDn applies to data being written into the FIFO. In the  
case of 8-bit BT.656 or Y/C modes, this means the output of any selected filter.  
SPRU629  
Video Capture Port  
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Video Capture Registers  
Figure 3–36. Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD)  
31  
26 25  
16  
0
Reserved  
R-0  
VCTHRLD2  
R/W-0  
15  
10  
9
Reserved  
R-0  
VCTHRLD1  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 3–21. Video Capture Channel x Threshold Register (VCxTHRLD) Field Descriptions  
Description  
†
†
Bit  
field  
symval  
Value BT.656 or Y/C Mode Raw Data Mode  
TSI Mode  
31–26 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
25–16 VCTHRLD2 OF(value)  
0–3FFh Number of field 2  
doublewords  
Not used.  
Not used.  
required to generate  
DMA events.  
15–10 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
9–0  
VCTHRLD1 OF(value)  
0–3FFh Number of field 1  
Number of raw  
Number of  
doublewords  
data doublewords doublewords  
required to generate required to  
required to  
generate a DMA  
event.  
DMA events.  
generate a DMA  
event.  
†
For CSL implementation, use the notation VP_VCxTHRLD_VCTHRLDn_symval  
3-66  
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Video Capture Registers  
3.13.9 Video Capture Channel x Event Count Register (VCAEVTCT, VCBEVTCT)  
The video capture channel x event count register (VCAEVTCT, VCBEVTCT)  
is programmed with the number of DMA events to be generated for each  
capture field. VCxEVTCT is shown in Figure 3–37 and described in  
Table 3–22.  
An event counter tracks how many events have been generated and indicates  
which threshold value (VCTHRLD1 or VCTHRLD2 in VCxTHRLD) to use in  
event generation and in the outgoing data counter. Once the CAPEVTCTn  
number of events have been generated, the DMA logic switches to the other  
threshold value. See section 2.3.1.  
Figure 3–37. Video Capture Channel x Event Count Register (VCAEVTCT, VCBEVTCT)  
31  
28 27  
16  
Reserved  
R-0  
CAPEVTCT2  
R/W-0  
15  
12 11  
0
Reserved  
R-0  
CAPEVTCT1  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 3–22. Video Capture Channel x Event Count Register (VCxEVTCT) Field Descriptions  
Description  
†
†
Bit  
field  
symval  
Value BT.656 or Y/C Mode  
Raw Data Mode  
TSI Mode  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
27–16 CAPEVTCT2 OF(value)  
0–FFFh Number of DMA event  
sets (YEVT, CbEVT,  
Not used.  
Not used.  
CrEVT) to be generated  
for field 2 capture.  
15–12 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
11–0 CAPEVTCT1 OF(value)  
0–FFFh Number of DMA event  
sets (YEVT, CbEVT,  
Not used.  
Not used.  
CrEVT) to be generated  
for field 1 capture.  
†
For CSL implementation, use the notation VP_VCxEVTCT_CAPEVTCTn_symval  
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Video Capture Registers  
3.13.10 Video Capture Channel B Control Register (VCBCTL)  
Video capture is controlled by the video capture channel B control register  
(VCBCTL) shown in Figure 3–38 and described in Table 3–23.  
Figure 3–38. Video Capture Channel B Control Register (VCBCTL)  
31  
30  
29  
24  
RSTCH  
R/WS-0  
BLKCAP  
R/W-1  
Reserved  
R-0  
23  
21  
13  
20  
19  
18  
17  
16  
Reserved  
R-0  
FINV  
R/W-0  
Reserved  
R-0  
VRST  
R/W-1  
HRST  
R/W-0  
15  
14  
12  
11  
10  
9
8
VCEN  
R/W-0  
PK10B  
R/W-0  
LFDE  
R/W-0  
SFDE  
R/W-0  
RESMPL  
R/W-0  
Reserved  
R-0  
SCALE  
R/W-0  
7
6
5
4
3
2
1
0
CON  
R/W-0  
FRAME  
R/W-0  
CF2  
CF1  
Reserved  
R-0  
CMODE  
R/W-0  
R/W-1  
R/W-1  
Legend: R = Read only; R/W = Read/Write; WS = Write 1 to reset, write of 0 has no effect; -n = value after reset  
Table 3–23. Video Capture Channel B Control Register (VCBCTL)  
Field Descriptions  
Description  
†
†
Bit  
field  
symval  
Value BT.656 or Y/C Mode  
Raw Data Mode  
TSI Mode  
31  
RSTCH  
Reset channel bit. Write 1 to reset the bit, a write of 0 has no  
effect.  
NONE  
0
1
No effect.  
RESET  
Resets the channel by blocking further DMA event generation  
and flushing the FIFO upon completion of any pending DMAs.  
Also clears the VCEN bit. All channel registers are set to their  
initial values. RSTCH is autocleared after channel reset is complete.  
†
‡
For CSL implementation, use the notation VP_VCBCTL_field_symval  
For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.  
3-68  
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Video Capture Registers  
Table 3–23. Video Capture Channel B Control Register (VCBCTL)  
Field Descriptions (Continued)  
Description  
†
†
Bit  
field  
symval  
Value BT.656 or Y/C Mode  
Raw Data Mode  
TSI Mode  
30  
BLKCAP  
Block capture events bit. BLKCAP functions as a capture FIFO  
reset without affecting the current programmable register values.  
The F1C, F2C, and FRMC status bits, in VCBSTAT, are not  
updated. Field or frame complete interrupts and vertical interrupts  
are also not generated.  
Clearing BLKCAP does not enable DMA events during the field  
where the bit is cleared. Whenever BLKCAP is set and then  
cleared, the software needs to clear the field and frame status  
bits (F1C, F2C, and FRMC) as part of the BLKCAP clear  
operation.  
CLEAR  
0
Enables DMA events in the video frame that follows the video  
frame where the bit is cleared. (The capture logic must sync to  
the start of the next frame after BLKCAP is cleared.)  
BLOCK  
1
0
Blocks DMA events and flushes the capture channel FIFOs.  
29–21 Reserved  
–
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
20  
FINV  
Detected field invert bit.  
FIELD1  
FIELD2  
–
0
1
0
Detected 0 is field 1.  
Detected 0 is field 2.  
Not used.  
Not used.  
Not used.  
Not used.  
19–18 Reserved  
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
17  
VRST  
VCOUNT reset method bit.  
V1EAV  
V0EAV  
0
1
Start of vertical blank  
(1 V = 1 EAV or  
VCTL2 active edge)  
Not used.  
Not used.  
Not used.  
Not used.  
st  
End of vertical blank  
st  
(1 V = 0 EAV or  
VCTL2 inactive edge)  
†
‡
For CSL implementation, use the notation VP_VCBCTL_field_symval  
For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.  
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Video Capture Registers  
Table 3–23. Video Capture Channel B Control Register (VCBCTL)  
Field Descriptions (Continued)  
Description  
†
†
Bit  
field  
symval  
Value BT.656 or Y/C Mode  
Raw Data Mode  
TSI Mode  
16  
HRST  
HCOUNT reset method bit.  
EAV  
SAV  
0
1
EAV or  
VCTL1 active edge.  
Not used.  
Not used.  
Not used.  
SAV or  
Not used.  
VCTL1 inactive edge.  
15  
VCEN  
Video capture enable bit. Other bits in VCBCTL (except RSTCH  
and BLKCAP bits) may only be changed when VCEN = 0.  
DISABLE  
ENABLE  
0
1
Video capture is disabled.  
Video capture is enabled.  
10-bit packing format select bit.  
14–13 PK10B  
ZERO  
0
Zero extend  
Sign extend  
Zero extend  
Sign extend  
Not used.  
Not used.  
SIGN  
1h  
2h  
DENSEPK  
Dense pack (zero  
extend)  
Dense pack (zero Not used.  
extend)  
–
3h  
Reserved  
Reserved  
Not used.  
12  
11  
LFDE  
SFDE  
Long field detect enable bit.  
DISABLE  
ENABLE  
0
1
Long field detect  
is disabled.  
Not used.  
Not used.  
Not used.  
Long field detect  
is enabled.  
Not used.  
Short field detect enable bit.  
DISABLE  
ENABLE  
0
1
Short field detect  
is disabled.  
Not used.  
Not used.  
Not used.  
Short field detect  
is enabled.  
Not used.  
†
‡
For CSL implementation, use the notation VP_VCBCTL_field_symval  
For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.  
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Table 3–23. Video Capture Channel B Control Register (VCBCTL)  
Field Descriptions (Continued)  
Description  
†
†
Bit  
field  
symval  
Value BT.656 or Y/C Mode  
Raw Data Mode  
TSI Mode  
10  
RESMPL  
Chroma resampling enable bit.  
DISABLE  
ENABLE  
0
1
Chroma resampling is  
disabled.  
Not used.  
Not used.  
Not used.  
Not used.  
Chroma is horizontally  
resampled from  
4:2:2 co-sited to  
4:2:0 interspersed  
before saving to  
chroma buffers.  
9
8
Reserved  
SCALE  
–
0
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
Scaling select bit.  
NONE  
HALF  
0
1
No scaling  
Not used.  
Not used.  
Not used.  
Not used.  
½ scaling  
‡
7
6
CON  
Continuous capture enable bit.  
Continuous capture is disabled.  
Continuous capture is enabled.  
Capture frame (data) bit.  
DISABLE  
ENABLE  
0
1
‡
FRAME  
NONE  
0
1
Do not capture frame.  
Do not capture Do not capture  
single data block.  
single packet.  
FRMCAP  
Capture frame.  
Capture single  
data block.  
Capture single  
packet.  
‡
5
CF2  
Capture field 2 bit.  
Do not capture field 2.  
Capture field 2.  
NONE  
0
1
Not used.  
Not used.  
Not used.  
Not used.  
FLDCAP  
†
‡
For CSL implementation, use the notation VP_VCBCTL_field_symval  
For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.  
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Table 3–23. Video Capture Channel B Control Register (VCBCTL)  
Field Descriptions (Continued)  
Description  
†
†
Bit  
field  
symval  
Value BT.656 or Y/C Mode  
Raw Data Mode  
TSI Mode  
‡
4
CF1  
Capture field 1 bit.  
NONE  
0
1
0
Do not capture field 1.  
Capture field 1.  
Not used.  
Not used.  
Not used.  
Not used.  
FLDCAP  
3–2  
Reserved  
CMODE  
–
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
1–0  
Capture mode select bit.  
BT656B  
BT656D  
RAWB  
0
Enables 8-bit BT.656 mode.  
Enables 10-bit BT.656 mode.  
Enables 8-bit raw data mode.  
Enables 10-bit raw data mode.  
Not used.  
Not used.  
Not used.  
Not used.  
1h  
2h  
3h  
RAWD  
†
‡
For CSL implementation, use the notation VP_VCBCTL_field_symval  
For complete encoding of these bits, see Table 3–6, Table 3–11, and Table 3–12.  
3.13.11 TSI Capture Control Register (TSICTL)  
The transport stream interface capture control register (TSICTL) controls TSI  
capture operation. TSICTL is shown in Figure 3–39 and described in  
Table 3–24.  
The ERRFILT, STEN, and TCKEN bits may be written at any time. To ensure  
stable counter operation, writes to the CTMODE bit are disabled unless the  
system time counter is halted (ENSTC = 0).  
Figure 3–39. TSI Capture Control Register (TSICTL)  
31  
16  
Reserved  
R-0  
15  
6
5
4
3
2
1
0
Reserved  
R-0  
ENSTC TCKEN STEN CTMODE ERRFILT  
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0  
—
R-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
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Table 3–24. TSI Capture Control Register (TSICTL) Field Descriptions  
Description  
BT.656, Y/C Mode,  
or Raw Data Mode  
†
†
Bit  
field  
symval  
Value  
TSI Mode  
31–6 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
5
ENSTC  
System time clock enable bit.  
HALTED  
CLKED  
0
1
Not used.  
Not used.  
System time clock input is disabled (to  
save power). The system time clock  
counters and tick counter do not increment.  
System time input is enabled. The system  
time clock counters and tick counters are  
incremented by STCLK.  
4
3
2
TCKEN  
STEN  
Tick count interrupt enable bit.  
DISABLE  
SET  
0
1
Not used.  
Not used.  
Setting of the TICK bit is disabled.  
The TICK bit in VPIS is set whenever the  
tick count is reached.  
System time clock interrupt enable bit.  
DISABLE  
SET  
0
1
Not used.  
Not used.  
Setting of the STC bit is disabled.  
A valid STC compare sets the STC bit in  
VPIS.  
CTMODE  
Counter mode select bit.  
90KHZ  
STCLK  
0
1
Not used.  
The 33-bit PCR portion of the system time  
counter increments at 90 kHz (when PCRE  
rolls over from 299 to 0).  
Not used.  
The 33-bit PCR portion of the system time  
counter increments by the STCLK input.  
1
0
ERRFILT  
Reserved  
Error filtering enable bit.  
ACCEPT  
0
Not used.  
Packets with errors are received and the  
PERR bit is set in the timestamp inserted at  
the end of the packet.  
REJECT  
1
0
Not used.  
Packets with errors are filtered out (not  
received in the FIFO).  
–
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
†
For CSL implementation, use the notation VP_TSICTL_field_symval  
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3.13.12 TSI Clock Initialization LSB Register (TSICLKINITL)  
The transport stream interface clock initialization LSB register (TSICLKINITL)  
is used to initialize the hardware counter to synchronize with the system time  
clock. TSICLKINITL is shown in Figure 3–40 and described in Table 3–25.  
On receiving the first packet containing a program clock reference (PCR) and  
the PCR extension value, the DSP writes the 32 least-significant bits (LSBs)  
of the PCR into TSICLKINITL. This initializes the counter to the system time  
clock. TSICLKINITL should also be updated by the DSP whenever a disconti-  
nuity in the PCR field is detected.  
To ensure synchronization and prevent false compare detection, the software  
should disable the system time clock interrupt (clear the STEN bit in TSICTL)  
prior to writing to TSICLKINITL. All bits of the system time counter are initial-  
ized whenever either TSICLKINITL or TSICLKINITM are written.  
Figure 3–40. TSI Clock Initialization LSB Register (TSICLKINITL)  
31  
0
INPCR  
R/W-0  
Legend: R/W = Read/Write; -n = value after reset  
Table 3–25. TSI Clock Initialization LSB Register (TSICLKINITL) Field Descriptions  
Description  
BT.656, Y/C Mode,  
or Raw Data Mode  
†
Bit  
Field  
symval  
Value  
TSI Mode  
31–0 INPCR  
OF(value) 0–FFFF FFFFh Not used.  
Initializes the 32 LSBs of the  
system time clock.  
†
For CSL implementation, use the notation VP_TSICLKINITL_INPCR_symval  
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3.13.13 TSI Clock Initialization MSB Register (TSICLKINITM)  
The transport stream interface clock initialization MSB register (TSICLKINITM)  
is used to initialize the hardware counter to synchronize with the system time  
clock. TSICLKINITM is shown in Figure 3–41 and described in Table 3–26.  
On receiving the first packet containing a program clock reference (PCR)  
header, the DSP writes the most-significant bit (MSB) of the PCR and the 9-bit  
PCR extension into TSICLKINITM. This initializes the counter to the system  
time clock. TSICLKINITM should also be updated by the DSP whenever a  
discontinuity in the PCR field is detected.  
To ensure synchronization and prevent false compare detection, the software  
should disable the system time clock interrupt (clear the STEN bit in TSICTL)  
prior to writing to TSICLKINITM. All bits of the system time counter are initial-  
ized whenever either TSICLKINITL or TSICLKINITM are written.  
Figure 3–41. TSI Clock Initialization MSB Register (TSICLKINITM)  
31  
16  
Reserved  
R-0  
15  
10  
9
1
0
Reserved  
R-0  
INPCRE  
R/W-0  
INPCRM  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 3–26. TSI Clock Initialization MSB Register (TSICLKINITM) Field Descriptions  
Description  
BT.656, Y/C Mode,  
or Raw Data Mode  
†
†
Bit  
field  
symval  
Value  
TSI Mode  
31–10 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
9–1  
INPCRE  
OF(value)  
0–1FFh Not used.  
Initializes the extension portion of the  
system time clock.  
0
INPCRM OF(value)  
0–1  
Not used.  
Initializes the MSB of the system time  
clock.  
†
For CSL implementation, use the notation VP_TSICLKINITM_field_symval  
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3.13.14 TSI System Time Clock LSB Register (TSISTCLKL)  
The transport stream interface system time clock LSB register (TSISTCLKL)  
contains the 32 least-significant bits (LSBs) of the program clock reference  
(PCR). The system time clock value is obtained by reading TSISTCLKL and  
TSISTCLKM. TSISTCLKL is shown in Figure 3–42 and described in  
Table 3–27.  
TSISTCLKL represents the current value of the 32 LSBs of the base PCR that  
normally counts at a 90-kHz rate. Since the system time clock counter contin-  
ues to count, the DSP may need to read TSISTCLKL twice in a row to ensure  
an accurate value.  
Figure 3–42. TSI System Time Clock LSB Register (TSISTCLKL)  
31  
0
PCR  
R/W-0  
Legend: R/W = Read/Write; -n = value after reset  
Table 3–27. TSI System Time Clock LSB Register (TSISTCLKL) Field Descriptions  
Description  
BT.656, Y/C Mode,  
or Raw Data Mode  
†
Bit  
Field  
symval  
Value  
TSI Mode  
31–0 PCR  
OF(value) 0–FFFF FFFFh Not used.  
Contains the 32 LSBs of the  
program clock reference.  
†
For CSL implementation, use the notation VP_TSISTCLKL_PCR_symval  
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3.13.15 TSI System Time Clock MSB Register (TSISTCLKM)  
The transport stream interface system time clock MSB register (TSISTCLKM)  
contains the most-significant bit (MSB) of the program clock reference (PCR)  
and the 9 bits of the PCR extension. The system time clock value is obtained  
by reading TSISTCLKM and TSISTCLKL. TSISTCLKM is shown in  
Figure 3–43 and described in Table 3–28.  
The PCRE value changes at a 27-MHz rate and is probably not reliably read  
by the DSP. The PCRM bit normally changes at a 10.5-µHz rate (every  
26 hours).  
Figure 3–43. TSI System Time Clock MSB Register (TSISTCLKM)  
31  
16  
Reserved  
R-0  
15  
10  
9
1
0
Reserved  
R-0  
PCRE  
R/W-0  
PCRM  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 3–28. TSI System Time Clock MSB Register (TSISTCLKM) Field Descriptions  
Description  
BT.656, Y/C Mode,  
or Raw Data Mode  
†
†
Bit  
field  
symval  
Value  
TSI Mode  
31–10 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
9–1  
PCRE  
PCRM  
OF(value)  
0–1FFh Not used.  
Contains the extension portion of the  
program clock reference.  
0
OF(value)  
0–1  
Not used.  
Contains the MSB of the program clock  
reference.  
†
For CSL implementation, use the notation VP_TSISTCLKM_field_symval  
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3.13.16 TSI System Time Clock Compare LSB Register (TSISTCMPL)  
The transport stream interface system time clock compare LSB register  
(TSISTCMPL) is used to generate an interrupt at some absolute time based  
on the STC. TSISTCMPL holds the 32 least-significant bits (LSBs) of the  
absolute time compare (ATC). Whenever the value in TSISTCMPL and  
TSISTCMPM match the unmasked bits of the time kept by the STC hardware  
counter and the STEN bit in TSICTL is set, the STC bit in VPIS is set.  
TSISTCMPL is shown in Figure 3–44 and described in Table 3–29.  
To prevent inaccurate comparisons caused by changing register bits, the  
software should disable the system time clock interrupt (clear the STEN bit in  
TSICTL) prior to writing to TSISTCMPL.  
Figure 3–44. TSI System Time Clock Compare LSB Register (TSISTCMPL)  
31  
0
ATC  
R/W-0  
Legend: R/W = Read/Write; -n = value after reset  
Table 3–29. TSI System Time Clock Compare LSB Register (TSISTCMPL)  
Field Descriptions  
Description  
BT.656, Y/C Mode,  
or Raw Data Mode  
†
Bit  
Field  
symval  
Value  
TSI Mode  
31–0 ATC  
OF(value) 0–FFFF FFFFh Not used.  
Contains the 32 LSBs of the  
absolute time compare.  
†
For CSL implementation, use the notation VP_TSISTCMPL_ATC_symval  
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3.13.17 TSI System Time Clock Compare MSB Register (TSISTCMPM)  
The transport stream interface system time clock compare MSB register  
(TSISTCMPM) is used to generate an interrupt at some absolute time based  
on the STC. TSISTCMPM holds the most-significant bit (MSB) of the absolute  
time compare (ATC). Whenever the value in TSISTCMPM and TSISTCMPL  
match the unmasked bits of the time kept by the STC hardware counter and  
theSTENbitinTSICTLisset, theSTCbitinVPISisset. TSISTCMPMisshown  
in Figure 3–45 and described in Table 3–30.  
To prevent inaccurate comparisons caused by changing register bits, the  
software should disable the system time clock interrupt (clear the STEN bit in  
TSICTL) prior to writing to TSISTCMPM.  
Figure 3–45. TSI System Time Clock Compare MSB Register (TSISTCMPM)  
31  
1
0
Reserved  
R-0  
ATC  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 3–30. TSI System Time Clock Compare MSB Register (TSISTCMPM)  
Field Descriptions  
Description  
BT.656, Y/C Mode,  
or Raw Data Mode  
†
Bit  
Field  
symval  
Value  
TSI Mode  
31–1 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
0
ATC  
OF(value)  
0–1  
Not used.  
Contains the MSB of the absolute time  
compare.  
†
For CSL implementation, use the notation VP_TSISTCMPM_ATC_symval  
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3.13.18 TSI System Time Clock Compare Mask LSB Register (TSISTMSKL)  
The transport stream interface system time clock compare mask LSB register  
(TSISTMSKL) holds the 32 least-significant bits (LSBs) of the absolute time  
compare mask (ATCM). This value is used with TSISTMSKM to mask out bits  
during the comparison of the ATC to the system time clock for absolute time.  
The bits that are set to one mask the corresponding ATC bits during the  
compare. TSISTMSKL is shown in Figure 3–46 and described in Table 3–31.  
To prevent inaccurate comparisons caused by changing register bits, the  
software should disable the system time clock interrupt (clear the STEN bit in  
TSICTL) prior to writing to TSISTMSKL.  
Figure 3–46. TSI System Time Clock Compare Mask LSB Register (TSISTMSKL)  
31  
0
ATCM  
R/W-0  
Legend: R/W = Read/Write; -n = value after reset  
Table 3–31. TSI System Time Clock Compare Mask LSB Register (TSISTMSKL)  
Field Descriptions  
Description  
BT.656, Y/C Mode,  
or Raw Data Mode  
†
Bit  
Field  
symval  
Value  
TSI Mode  
31–0 ATCM  
OF(value) 0–FFFF FFFFh Not used.  
Contains the 32 LSBs of the  
absolute time compare mask.  
†
For CSL implementation, use the notation VP_TSISTMSKL_ATCM_symval  
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3.13.19 TSI System Time Clock Compare Mask MSB Register (TSISTMSKM)  
The transport stream interface system time clock compare mask MSB register  
(TSISTMSKM) holds the most-significant bit (MSB) of the absolute time  
compare mask (ATCM). This value is used with TSISTMSKL to mask out bits  
during the comparison of the ATC to the system time clock for absolute time.  
The bits that are set to one mask the corresponding ATC bits during the  
compare. TSISTMSKM is shown in Figure 3–47 and described in Table 3–32.  
To prevent inaccurate comparisons caused by changing register bits, the  
software should disable the system time clock interrupt (clear the STEN bit in  
TSICTL) prior to writing to TSISTMSKM.  
Figure 3–47. TSI System Time Clock Compare Mask MSB Register (TSISTMSKM)  
31  
1
0
Reserved  
R-0  
ATCM  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 3–32. TSI System Time Clock Compare Mask MSB Register (TSISTMSKM)  
Field Descriptions  
Description  
BT.656, Y/C Mode,  
or Raw Data Mode  
†
Bit  
Field  
symval  
Value  
TSI Mode  
31–1 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
0
ATCM  
OF(value)  
0–1  
Not used.  
Contains the MSB of the absolute time  
compare mask.  
†
For CSL implementation, use the notation VP_TSISTMSKM_ATCM_symval  
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3.13.20 TSI System Time Clock Ticks Interrupt Register (TSITICKS)  
The transport stream interface system time clock ticks interrupt register  
(TSITICKS) is used to generate an interrupt after a certain number of ticks of  
the 27-MHz system time clock. When the TICKCT value is set to X and the  
TCKEN bit in TSICTL is set, the TICK bit in VPIS is set every X + 1 STCLK  
cycles. Note that the tick interrupt counter and comparison logic function are  
separatefromthePCRlogicandalwayscountSTCLKcyclesregardlessofthe  
value of the CTMODE bit in TSICTL. TSITICKS is shown in Figure 3–48 and  
described in Table 3–33.  
A write to TSITICKS resets the tick counter 0. Whenever the tick counter  
reaches the TICKCT value, the TICK bit in VPIS is set and the counter resets  
to 0.  
To prevent inaccurate comparisons caused by changing register bits, the soft-  
ware should disable the tick count interrupt (clear the TCKEN bit in TSICTL)  
prior to writing to TSITICKS.  
Figure 3–48. TSI System Time Clock Ticks Interrupt Register (TSITICKS)  
31  
0
TICKCT  
R/W-0  
Legend: R/W = Read/Write; -n = value after reset  
Table 3–33.TSI System Time Clock Ticks Interrupt Register (TSITICKS) Field Descriptions  
Description  
BT.656, Y/C Mode,  
or Raw Data Mode  
†
Bit  
Field  
symval  
Value  
TSI Mode  
31–0 TICKCT OF(value) 0–FFFF FFFFh Not used.  
Contains the number of ticks of the  
27-MHz system time clock required  
to generate a tick count interrupt.  
†
For CSL implementation, use the notation VP_TSITICKS_TICKCT_symval  
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Video Capture FIFO Registers  
3.14 Video Capture FIFO Registers  
The capture FIFO mapping registers are listed in Table 3–34. These registers  
provide read access to the capture FIFOs. These pseudo-registers should be  
mapped into DSP memory space rather than configuration register space in  
order to provide high-speed access. See the device-specific datasheet for the  
memory address of these registers. The function of the video capture FIFO  
mapping registers is listed in Table 3–35.  
Table 3–34. Video Capture FIFO Registers  
Acronym  
Register Name  
YSRCA  
Y FIFO Source Register A  
Cb FIFO Source Register A  
Cr FIFO Source Register A  
Y FIFO Source Register B  
Cb FIFO Source Register B  
Cr FIFO Source Register B  
CBSRCA  
CRSRCA  
YSRCB  
CBSRCB  
CRSRCB  
Table 3–35. Video Capture FIFO Registers Function  
Capture Mode  
BT.656 or Y/C  
Raw Data  
TSI  
Register  
YSRCx  
Maps Y capture buffer into DSP memory.  
Maps data capture buffer Maps data capture buffer  
into the DSP memory.  
into the DSP memory.  
Not used.  
CBSRCx Maps Cb capture buffer into DSP memory. Not used.  
CRSRCx Maps Cr capture buffer into DSP memory. Not used.  
Not used.  
In BT.656 or Y/C capture mode, three DMAs move data from the Y, Cb, and  
Cr capture FIFOs to the DSP memory by using the memory-mapped YSRCx,  
CBSRCx, and CRSRCx registers. The DMA transfers are triggered by the  
YEVT, CbEVT, and CrEVT events, respectively.  
In raw capture mode, one DMA channel moves data from the Y capture FIFO  
to the DSP memory by using the memory-mapped YSRCx register. The DMA  
transfers are triggered by a YEVT event.  
The video port packs receive data into 64-bit words in the FIFO and the DMA  
should always move 64-bit-wide data from YSRCx, CBSRCx, and CRSRCx  
to the memory.  
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Chapter 4  
Video Display Port  
The video port peripheral can operate as a video capture port, video display  
port, or transport stream interface (TSI) capture port. This chapter discusses  
the video display port.  
Topic  
Page  
4.1 Video Display Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2  
4.2 BT.656 Video Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9  
4.3 Y/C Video Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16  
4.4 Video Output Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21  
4.5 Ancillary Data Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25  
4.6 Raw Data Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25  
4.7 Video Display Field and Frame Operation . . . . . . . . . . . . . . . . . . . . . . 4-30  
4.8 Display Line Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33  
4.9 Display Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35  
4.10 Displaying Video in BT.656 or Y/C Mode . . . . . . . . . . . . . . . . . . . . . . . . 4-47  
4.11 Displaying Video in Raw Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49  
4.12 Video Display Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52  
4.13 Video Display Registers Recommended Values . . . . . . . . . . . . . . . . . 4-94  
4.14 Video Display FIFO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96  
4-1  
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Video Display Mode Selection  
4.1 Video Display Mode Selection  
The video display module operates in one of three modes as listed in  
Table 4–1. The DMODE bits are in the video display control register (VDCTL).  
The Y/C and 16/20-bit raw display modes may only be selected if the DCDIS  
bit in the video port control register (VPCTL) is cleared to 0.  
Table 4–1. Video Display Mode Selection  
DMODE Bits  
Mode  
Description  
000  
8-Bit ITU-R BT.656  
Display  
Digital video output is in YCbCr 4:2:2 with 8-bit resolution  
multiplexed in ITU-R BT.656 format.  
001  
10-Bit ITU-R BT.656  
Display  
Digital video output is in YCbCr 4:2:2 with 10-bit resolution  
multiplexed in ITU-R BT.656 format.  
010  
011  
100  
8-Bit Raw Display  
10-Bit Raw Display  
8-Bit Y/C Display  
8-bit data output  
10-bit data output  
Digital video is output in YCbCr 4:2:2 with 8-bit resolution on  
parallel Y and Cb/Cr multiplexed channels.  
101  
10-Bit Y/C Display  
Digital video is output in YCbCr 4:2:2 with 10-bit resolution on  
parallel Y and Cb/Cr multiplexed channels.  
110  
111  
16-Bit Raw Display  
20-Bit Raw Display  
16-bit data output.  
20-bit data output.  
4.1.1 Image Timing  
Display devices generate interlaced images by controlling the vertical retrace  
timing. The video display module emits a data stream used to generate a  
displayed image. An NTSC-compatible interlaced image with field and line  
information is shown in Figure 4–1. A progressive-scan image (SMPTE 296M  
compatible) is shown in Figure 4–2.  
The active video area represents the pixels visible on the display. The active  
video area begins after the horizontal and vertical blanking intervals. The  
image area output by the video display module can be a subset of the active  
area. The relationship between frame, active video area, and image area is  
presented in Figure 4–3 for interlaced video and in Figure 4–4 for progressive  
video. The video display module generates timing for frames, active video  
areas within frames, and images within the active video area.  
4-2  
Video Display Port  
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Video Display Mode Selection  
Figure 4–1. NTSC Compatible Interlaced Display  
Field 1  
Field 2  
Line 20  
Line 21  
Line 22  
Line 282  
Line 283  
Line 284  
Line 261  
Line 262  
Line 523  
Line 524  
Line 525  
Line 263  
Figure 4–2. SMPTE 296M Compatible Progressive Scan Display  
Field 1  
Line 26  
Line 27  
Line 28  
Line 29  
Line 30  
Line 741  
Line 742  
Line 743  
Line 744  
Line 745  
SPRU629  
Video Display Port  
4-3  
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Video Display Mode Selection  
Figure 4–3. Interlaced Blanking Intervals and Video Areas  
Field 1 Vertical Blanking  
Field 1 Image Vertical Offset  
Field 1 Active Video  
Field 1 Image Width  
Field 2 Vertical Blanking  
Field 2 Image Vertical Offset  
Field 2 Active Video  
Field 2 Image Width  
4-4  
Video Display Port  
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Video Display Mode Selection  
Figure 4–4. Progressive Blanking Intervals and Video Area  
Field 1 Vertical Blanking  
Field 1 Image Vertical Offset  
Field 1 Active Video  
Field 1 Image Width  
4.1.2 Video Display Counters  
To generate the image timing, the video display module uses five counters:  
- Frame line counter (FLCOUNT)  
- Frame pixel counter (FPCOUNT)  
- Image line counter (ILCOUNT)  
- Image pixel counter (IPCOUNT)  
- Video clock counter (VCCOUNT)  
The frame line counter (FLCOUNT) counts the total number of lines per frame  
including vertical blanking intervals. The frame pixel counter (FPCOUNT)  
counts the total number of pixels per line including horizontal blanking inter-  
vals. FLCOUNT begins counting at the start of the vertical blanking interval of  
the first field. FPCOUNT begins counting at the end of the horizontal blanking  
intervalofeachline. Theyareresetwhentheyreachtheirstopvaluesasspeci-  
fied in the video display frame size register (VDFRMSZ).  
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Video Display Port  
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Video Display Mode Selection  
The image line counter (ILCOUNT) and the image pixel counter (IPCOUNT)  
track the visible image within the field. ILCOUNT begins counting at the first  
display image line in each field. IPCOUNT begins counting at the first dis-  
played image pixel on each line. They stop counting when they reach the  
image height and image width as specified in the video display field n image  
size register (VDIMGSZn).  
The video clock counter (VCCOUNT) counts VCLKIN transitions to determine  
when to increment FPCOUNT and IPCOUNT as determined by the video  
display mode. In Y/C mode, FPCOUNT and IPCOUNT increment on each  
VCLKIN rising edge. In BT.656 mode, FPCOUNT and IPCOUNT increment on  
every other VCLKIN rising edge. In raw mode, FPCOUNT and IPCOUNT  
increment on every 1 to 16 VCLKIN cycles as programmed by the INCPIX bits  
in the video display threshold register (VDTHRLD).  
FPCOUNT and FLCOUNT are compared to various values to determine when  
to assert and negate various control signals. The 12-bit FPCOUNT is used to  
determine where to enable and disable horizontal sync and blanking informa-  
tion along each scan line. The state of FPCOUNT is reflected in the VDXPOS  
bits of the video display status register (VDSTAT). Figure 4–5 shows how the  
horizontal blanking and horizontal synchronization signals are triggered.  
(HBLNK and HSYNC are shown active high).  
Figure 4–5. Horizontal Blanking and Horizontal Sync Timing  
718 719 720  
735 736  
799 800  
857  
0
1
FPCOUNT  
HBLNK  
HSYNC  
FPCOUNT = HBLNKSTOP  
FPCOUNT = HSYNCSTOP  
FPCOUNT = HBLNKSTART  
FPCOUNT = HSYNCSTART  
The 12-bit FLCOUNT counts which scan line is being generated. The  
FLCOUNT is reset to 1 after reaching the count specified in VDFRMSZ. (For  
BT.656 operation, the FRMHIGHT would be set to 525 (525/60 operation) or  
625 (625/50 operation).) The state of FLCOUNT is reflected in the VDYPOS  
bits of VDSTAT. Figure 4–6 shows how the vertical blanking, vertical synchro-  
nization, and field identification signals are triggered. (VBLNK and VSYNC are  
shown active high.)  
4-6  
Video Display Port  
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Video Display Mode Selection  
Note that the signals can transition at any place along the video line (specified  
by the XSTART and XSTOP bits of the appropriate registers). In this case,  
VBLNK starts at horizontal count VBLNKXSTART2 = 429 on scan line  
VBLNKYSTART2 = 263 (565/60 operation).  
Figure 4–6. Vertical Blanking, Sync and Even/Odd Frame Signal Timing  
One Frame  
One Line  
FLCOUNT  
VBLNK  
FLCOUNT = VBLNKYSTOP1 FLCOUNT = VBLNKYSTART2  
FPCOUNT = VBLNKXSTOP1 FPCOUNT = VBLNKXSTART2  
FLCOUNT = VBLNKYSTOP2  
FPCOUNT = VBLNKXSTOP2  
FLCOUNT = VBLNKYSTART1  
FPCOUNT = VBLNKXSTART1  
VSYNC  
FLCOUNT = VSYNCYSTOP1 FLCOUNT = VSYNCYSTART2 FLCOUNT = VSYNCYSTOP2  
FPCOUNT = VSYNCXSTOP1 FPCOUNT = VSYNCXSTART2 FPCOUNT = VSYNCXSTOP2  
FLCOUNT = VSYNCYSTART1  
FPCOUNT = VSYNCXSTART1  
FLD  
Field 1  
Field 2  
FLCOUNT = FLD1YSTART  
FPCOUNT = FLD1XSTART  
FLCOUNT = FLD2YSTART  
FPCOUNT = FLD2XSTART  
4.1.3 Sync Signal Generation  
The video display module must generate a number of control signals for both  
internal and external use. As seen in section 4.1.2, the HSYNC, HBLNK,  
VSYNC, VBLNK, and FLD signals are generated directly from the pixel and  
line counters and comparison registers. Several additional signals are also  
generated indirectly for use in external control.  
A composite blank (CBLNK) signal is generated as the logical-OR of the  
HBLNK and VBLNK signals. A composite sync (CSYNC) signal is also gener-  
ated as the logical-OR of the HSYNC and VSYNC signals. (This is not a true  
analog CSYNC, which must include serration pulses during VSYNC and  
equalization pulses during vertical front and back porch periods.) Finally, an  
active video (AVID) signal is generated. AVID is the inverted CBLNK signal  
indicating when active video data is being output.  
Up to three of the eight sync signals may be output on VCTL1, VCTL2, and  
VCTL3 as selected by the video display control register (VDCTL). Each signal  
may be output in its noninverted or inverted form, as selected by the VCTnP  
bits in the video port control register (VPCTL).  
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Video Display Port  
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Video Display Mode Selection  
4.1.4 External Sync Operation  
The video display module may be synchronized with an external video source  
using external sync signals. VCTL1 may be configured as an external horizon-  
tal sync input. When the external HSYNC is asserted, FPCOUNT is loaded  
with the HRLD value and VCCOUNT is loaded with the CRLD value. VCTL2  
may be configured as an external vertical sync input. When the external  
VSYNC is asserted during field 1, FLCOUNT is loaded with the VRLD value.  
Field determination is made using either VCTL3 as an external FLD input or  
by field detect logic using the VSYNC and HSYNC inputs.  
4.1.5 Port Sync Operation  
The video display module may be synchronized with the video display module  
of another video port on the device. This mode is provided to enable the output  
of 24-bit or 30-bit RGB data. (for example, 8 bits of R and 8 bits of G on video  
port 0 operating in dual-channel synced 8-bit raw mode, and 8 bits of B on  
video port 1 operating in 8-bit raw mode with VP1 synced to VP0.) The slave  
port must have the same VCLKIN and programmed register values as the  
master port. The master port provides the control signals necessary to reset  
the slave port counters so that they maintain synchronization. Each video port  
may only synchronize to the previous video port (the one with a lower number).  
An example for a three port device is shown in Figure 4–7.  
Figure 4–7. Video Display Module Synchronization Chain  
Video port 0  
display  
Video port 1  
display  
Video port 2  
display  
Can sync to  
Can sync to  
4-8  
Video Display Port  
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BT.656 Video Display Mode  
4.2 BT.656 Video Display Mode  
The BT.656 display mode outputs 8-bit or 10-bit 4:2:2 co-sited luma and chroma  
data multiplexed into a single data stream. Pixels are output in pairs with each  
pair consisting of two luma samples and two chroma samples. The chroma  
samples are associated with the first luma pixel of the pair. Output pixels are  
valid on the positive edge of VCLKOUT in the sequence CbYCrY as shown in  
Figure 4–8.  
Figure 4–8. BT.656 Output Sequence  
VCLKOUT  
Cb0  
Y0  
Cr0  
Y1  
Cb1  
Y2  
Cr1  
Y3  
Cb2  
Y4  
VDOUT[9–0]  
4.2.1 Display Timing Reference Codes  
The end active video (EAV) code and start active video (SAV) code are issued  
at the start of each video line. EAV and SAV codes have a fixed format. The  
format is shown in Table 3–2 (page 3-4). The EAV and SAV codes define the  
end and start of the horizontal-blanking interval, respectively, and they also  
indicate the current field number and the vertical blanking interval. The SAV  
and EAV codes have a 4-bit protection field to ensure valid codes. The video  
display module generates these protection bits as part of the SAV and EAV  
codes. Table 3–3 (page 3-5) shows possible combinations of valid SAV and  
EAV codes with their protection bits. The video display pipeline generates SAV  
and EAV sync codes and inserts them into the output video stream according  
to the BT.656 specification.  
The BT.656 line timing is shown in Figure 4–9 and Figure 4–10. Each line  
begins with an EAV code, a blanking interval, an SAV code, followed by the line  
of active video. The EAV code indicates the end of active video for the previous  
line, and the SAV code indicates the start of active video for the current line.  
Figure 4–9. 525/60 BT.656 Horizontal Blanking Timing  
One Line  
Next Line  
720 721 722 723  
855 856 857  
0
1
2
718 719 720 721 722 723  
FPCOUNT  
VCLKOUT  
4
268  
Blanking  
4
1440  
Active Video  
VDOUT[9–0]  
EAV  
Blanking Data  
SAV  
EAV  
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Video Display Port  
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BT.656 Video Display Mode  
Figure 4–10. 625/50 BT.656 Horizontal Blanking Timing  
One Line  
Next Line  
720 721 722 723  
861 862 863  
0
1
2
718 719 720 721 722 723  
FPCOUNT  
VCLKOUT  
4
280  
Blanking  
4
1440  
Active Video  
VDOUT[9–0]  
EAV Blanking Data  
SAV  
EAV  
SAV and EAV codes are identified by a 3-byte preamble of FFh, 00h, and 00h.  
This combination must be avoided in the video data output by the video port  
to prevent accidental generation of an invalid sync code. The video display  
module provides programmable maximum and minimum value clipping on the  
video data to prevent this possibility.  
The typical values for H, V, and F on different lines are shown in Table 4–2 and  
Figure 4–11.  
F and V are only allowed to change at EAV sequences. The EAV and SAV  
sequences must occupy the first four words and the last four words of the  
digital horizontal-blanking interval, respectively. The EAV code is inserted  
when FPCOUNT = HBLNKSTART. The SAV code is inserted when  
FPCOUNT = HBLNKSTOP.  
Table 4–2. BT.656 Frame Timing  
Line Number  
625/50  
525/60  
F
V
Description  
624–625  
1–3  
1
1
Vertical blanking for field 1, EAV/SAV code still indicates field 2.  
1–22  
4–19  
0
0
0
1
1
1
0
1
1
0
Vertical blanking for field 1. Change EAV/SAV code to field 1.  
Active video, field 1.  
23–310  
311–312  
313–335  
336–623  
20–263  
264–265  
266–282  
283–525  
Vertical blanking for field 2, EAV/SAV code still indicates field 1.  
Vertical blanking for field 2. Change EAV/SAV code to field 2.  
Active video, field 2.  
4-10  
Video Display Port  
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BT.656 Video Display Mode  
Figure 4–11.Digital Vertical F and V Transitions  
525 lines/60 Hz  
1(V = 1)  
625 lines/50 Hz  
1(V = 1)  
Line 1  
Line 4  
Blanking  
Blanking  
10 (V = X)  
20 (V = 0)  
23 (V = 0)  
Optional blanking  
Field 1  
(F = 0)  
Image: Field 1  
Field 1  
(F = 0)  
Image: Field 1  
Line  
313  
264 (V = 1)  
273 (V = X)  
311 (V = 1)  
336 (V = 0)  
Line 266  
Blanking  
Blanking  
Optional blanking  
Image: Field 2  
Blanking  
Field 2  
(F = 1)  
283 (V = 0)  
525 (V = 0)  
Field 2  
(F = 1)  
624 (V = 1)  
625 (V = 1)  
Image: Field 2  
Line 3  
Line 625  
H = 0 (SAV)  
H = 0 (SAV)  
H = 1 (EAV)  
H = 1 (EAV)  
H
H
H
H
LIne Number  
F
V
Line Number  
F
V
(EAV) (SAV)  
(EAV) (SAV)  
1–3  
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1–22  
0
1
1
1
1
1
1
1
0
0
0
0
0
0
4–19  
0
0
0
1
1
1
0
1
1
0
23–310  
311–312  
313–335  
336–623  
624–625  
0
0
1
1
1
0
0
1
0
1
20–263  
264–265  
266–282  
283–525  
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Video Display Port  
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BT.656 Video Display Mode  
4.2.2 Blanking Codes  
The time between the EAV and SAV code on each line represents the horizontal  
blanking interval. During this time, the video port outputs digital video blanking  
values. These values are 10.0h for luma (Y) samples and 80.0h for chroma  
(Cb/Cr) samples. These values are also output during the active line period of  
vertical blanking (between SAV and EAV when V = 1). In addition, if the DVEN  
bit in VDCTL is cleared to 0, the blanking values are output during the portion  
of active video lines that are not a part of the displayed image.  
4.2.3 BT.656 Image Display  
For BT.656 display mode, the FIFO buffer is divided into three sections. One  
FIFO is 2560-bytes deep and is used for the storage of Y output samples; the  
other two FIFOs are each 1280-bytes deep and are dedicated for storage of  
Cb and Cr samples. Each FIFO has a memory-mapped location associated  
with it; YDST, CBDST, and CRDST. The pseudo-registers are write-only and  
are used by DMAs to fill the FIFOs with output data. The video display module  
multiplexes the data from the three FIFOs to generate the output CbYCrY data  
stream.  
If video display is enabled, the video display module uses the YEVT, CbEVT,  
and CrEVT events to notify the DMA controller that data needs to be placed  
into the display FIFOs. The number of pixels required to generate the events  
is set by the VDTHRLD bits in VDTHRLD (VTHRLD must be an even number).  
The video display module generates the event signals when the display buffer  
holds less than the VDTHRLD number of pixels and the DEVTCT counter has  
not expired. On every YEVT, the DMA should move data from DSP memory  
to the Y buffer, using the Y FIFO destination register (YDST) content as the  
destination address. On every CbEVT, the DMA should move data from DSP  
memory to the Cb buffer, using the Cb FIFO destination register (CBDST)  
content as the destination address. On every CrEVT, the DMA should move  
data from DSP memory to the Cr buffer, using the Cr FIFO destination register  
(CRDST) content as the destination address. The DMA transfer size for the  
Y buffer is twice the size of the DMA for the Cb or Cr buffers.  
4-12  
Video Display Port  
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BT.656 Video Display Mode  
4.2.4 BT.656 FIFO Unpacking  
Display data is always packed into the FIFOs in 64-bit words and must be  
unpacked before being sent to the video display data pipeline. The unpacking  
and byte ordering is dependant upon the display data size and the device  
endian mode. For little-endian operation (default), data is unpacked from right  
to left; for big-endian operation, data is unpacked from left to right.  
The 8-bit BT.656 mode uses three FIFOs for color separation. Four samples  
are unpacked from each word as shown in Figure 4–12.  
Figure 4–12. 8-Bit BT.656 FIFO Unpacking  
VCLKOUT  
Cb 0  
Y 0  
Cr 0  
Y 1  
Cb 1  
Y 2  
Cr 1  
Y 3  
Cb 2  
Y 4  
Cr 2  
Y 5  
VDOUT[9–2]  
63  
5655  
Y 31  
4847  
4039  
3231  
2423  
1615  
8 7  
0
Y 30  
Y 29  
Y 28  
Y 27  
Y 26  
Y 25  
Y 24  
Y 16  
Y 8  
Y 23  
Y 15  
Y 7  
Y 22  
Y 14  
Y 6  
Y 21  
Y 13  
Y 5  
Y 20  
Y 12  
Y 4  
Y 19  
Y 11  
Y 3  
Y 18  
Y 10  
Y 2  
Y 17  
Y 9  
Y 1  
Y 0  
Y FIFO  
63  
63  
5655  
Cb 15  
4847  
4847  
4039  
4039  
3231  
3231  
2423  
2423  
1615  
1615  
8 7  
0
0
Cb 14  
Cb 6  
Cb 13  
Cb 5  
Cb 12  
Cb 4  
Cb 11  
Cb 3  
Cb 10  
Cb 2  
Cb 9  
Cb 1  
Cb 8  
Cb 0  
Cb 7  
Cb FIFO  
Cr FIFO  
5655  
Cr 15  
8 7  
Cr 14  
Cr 6  
Cr 13  
Cr 5  
Cr 12  
Cr 4  
Cr 11  
Cr 3  
Cr 10  
Cr 2  
Cr 9  
Cr 1  
Cr 8  
Cr 0  
Cr 7  
Little-Endian Unpacking  
63  
5655  
Y 24  
4847  
4039  
3231  
2423  
1615  
8 7  
0
Y 25  
Y 17  
Y 9  
Y 26  
Y 18  
Y 10  
Y 2  
Y 27  
Y 19  
Y 11  
Y 3  
Y 28  
Y 20  
Y 12  
Y 4  
Y 29  
Y 21  
Y 13  
Y 5  
Y 30  
Y 22  
Y 14  
Y 6  
Y 31  
Y 23  
Y 15  
Y 7  
Y 16  
Y 8  
Y 0  
Y 1  
Y FIFO  
63  
63  
5655  
Cb 8  
4847  
4847  
4039  
4039  
3231  
3231  
2423  
2423  
1615  
1615  
8 7  
0
0
Cb 9  
Cb 1  
Cb 10  
Cb 2  
Cb 11  
Cb 3  
Cb 12  
Cb 4  
Cb 13  
Cb 5  
Cb 14  
Cb 6  
Cb 15  
Cb 7  
Cb 0  
Cb FIFO  
Cr FIFO  
5655  
Cr 8  
8 7  
Cr 9  
Cr 1  
Cr 10  
Cr 2  
Cr 11  
Cr 3  
Cr 12  
Cr 4  
Cr 13  
Cr 5  
Cr 14  
Cr 6  
Cr 15  
Cr 7  
Cr 0  
Big-Endian Unpacking  
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BT.656 Video Display Mode  
For 10-bit BT.656 operation, two samples are unpacked from each word as  
shown in Figure 4–13.  
Figure 4–13. 10-Bit BT.656 FIFO Unpacking  
VCLKOUT  
Cb 0  
Y 0  
Cr 0  
Y 1  
4241  
Cb 1  
Y 2  
Cr 1  
Y 3  
2625  
Cb 2  
Y 4  
Cr 2  
Y 5  
10 9  
VDOUT[9–0]  
63  
5857  
4847  
3231  
1615  
0
Y 15  
Y 11  
Y 7  
Y 14  
Y 10  
Y 6  
Y 13  
Y 9  
Y 5  
Y 1  
Y 12  
Y 8  
Y 4  
Y 0  
Y 3  
Y 2  
Y FIFO  
63  
63  
5857  
5857  
4847  
4847  
4241  
4241  
3231  
3231  
2625  
2625  
1615  
1615  
10 9  
10 9  
0
0
Cb 7  
Cb 3  
Cb 6  
Cb 2  
Cb 5  
Cb 1  
Cb 4  
Cb 0  
Cb FIFO  
Cr FIFO  
Cr 7  
Cr 3  
Cr 6  
Cr 2  
Cr 5  
Cr 1  
Cr 4  
Cr 0  
Little-Endian Unpacking  
63  
5857  
4847  
4241  
3231  
2625  
1615  
10 9  
0
Y 12  
Y 8  
Y 4  
Y 0  
Y 13  
Y 9  
Y 5  
Y 1  
Y 14  
Y 10  
Y 6  
Y 15  
Y 11  
Y 7  
Y 2  
Y 3  
Y FIFO  
63  
63  
5857  
5857  
4847  
4847  
4241  
4241  
3231  
3231  
2625  
2625  
1615  
1615  
10 9  
10 9  
0
0
Cb 4  
Cb 0  
Cb 5  
Cb 1  
Cb 6  
Cb 2  
Cb 7  
Cb 3  
Cb FIFO  
Cr FIFO  
Cr 4  
Cr 0  
Cr 5  
Cr 1  
Cr 6  
Cr 2  
Cr 7  
Cr 3  
Big-Endian Unpacking  
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BT.656 Video Display Mode  
In 10-bit BT.656 dense-pack mode, three samples are unpacked from each  
word in the FIFO as seen in Figure 4–14.  
Figure 4–14. BT.656 Dense FIFO Unpacking  
VCLKOUT  
Cb 0  
5251  
Y 0  
Cr 0  
Y 1  
4241  
Cb 1  
Y 2  
Cr 1  
Y 3  
Cb 2  
2019  
Y 4  
Cr 2  
Y 5  
10 9  
VDOUT[9–0]  
63 61  
3231 29  
0
Y 23  
Y 17  
Y 11  
Y 5  
Y 22  
Y 21  
Y 15  
Y 9  
Y 20  
Y 14  
Y 8  
Y 19  
Y 18  
Y 12  
Y 6  
Y 16  
Y 10  
Y 4  
Y 13  
Y 7  
Y 3  
Y 2  
Y 1  
Y 0  
Y FIFO  
63 61  
63 61  
5251  
5251  
4241  
4241  
3231 29  
3231 29  
2019  
2019  
10 9  
10 9  
0
0
Cb 11  
Cb 5  
Cb 10  
Cb 4  
Cb 9  
Cb 3  
Cb 8  
Cb 2  
Cb 7  
Cb 1  
Cb 6  
Cb 0  
Cb FIFO  
Cr FIFO  
Cr 11  
Cr 5  
Cr 10  
Cr 4  
Cr 9  
Cr 3  
Cr 8  
Cr 2  
Cr 7  
Cr 1  
Cr 6  
Cr 0  
Little-Endian Unpacking  
63 61  
5251  
4241  
3231 29  
2019  
10 9  
0
Y 18  
Y 12  
Y 6  
Y 19  
Y 13  
Y 7  
Y 20  
Y 14  
Y 8  
Y 21  
Y 22  
Y 16  
Y 10  
Y 4  
Y 23  
Y 17  
Y 11  
Y 5  
Y 15  
Y 9  
Y 0  
Y 1  
Y 2  
Y 3  
Y FIFO  
63 61  
63 61  
5251  
5251  
4241  
4241  
3231 29  
3231 29  
2019  
2019  
10 9  
10 9  
0
0
Cb 6  
Cb 0  
Cb 7  
Cb 1  
Cb 8  
Cb 2  
Cb 9  
Cb 3  
Cb 10  
Cb 4  
Cb 11  
Cb 5  
Cb FIFO  
Cr FIFO  
Cr 6  
Cr 0  
Cr 7  
Cr 1  
Cr 8  
Cr 2  
Cr 9  
Cr 3  
Cr 10  
Cr 4  
Cr 11  
Cr 5  
Big-Endian Unpacking  
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Y/C Video Display Mode  
4.3 Y/C Video Display Mode  
The Y/C display mode is similar to the BT.656 display mode but outputs 8 or  
10-bit data on separate luma and chroma data streams. One data stream  
contains Y samples and the other stream contains multiplexed Cb and Cr  
samples co-sited with every other luminance sample. The Y samples are read  
fromtheYFIFOandtheCbandCrsamplesarereadfromtheCbandCrFIFOs  
and combined on the chroma output. The unpacking and order of the samples  
is determined by the sample size (8-bit or 10-bit) and the device endian mode.  
The Y/C display mode can generate HDTV standard output such as BT.1120,  
SMPTE260, or SMPTE296 with embedded EAV and SAV codes. It can also  
output separate control signals.  
Because 16 or 20 bits are used for data output, the Y/C output mode requires  
both halves of the video port data bus. If the DCHDIS bit in VPCTL is set, then  
Y/C mode cannot be selected.  
4.3.1 Y/C Display Timing Reference Codes  
The EAV and SAV embedded timing codes are identical to those output in  
BT.656 mode and timing is controlled in the same manner. In Y/C mode, how-  
ever, the codes must be output on both the Y and C data streams  
(VDOUT[9–0] and VDOUT[19–10]). An example of BT.1120 line timing is  
shown in Figure 4–15.  
Figure 4–15. Y/C Horizontal Blanking Timing (BT.1120 60I)  
One Line  
Next Line  
FPCOUNT  
VCLKOUT  
4
4
272  
1920  
Blanking  
Active Video  
VDOUT[9–0]  
EAV  
EAV  
Blanking Data  
SAV  
SAV  
EAV  
VDOUT[19–10]  
Blanking Data  
EAV  
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Y/C Video Display Mode  
4.3.2 Y/C Blanking Codes  
The time between the EAV and SAV code on each line represents the horizon-  
tal blanking interval. During this time, the video port outputs the digital video  
blanking values. These values are 10.0h for luma (Y) samples and 80.0h for  
chroma (Cb/Cr) samples. These values are also output during the active line  
period of vertical blanking (between SAV and EAV when V = 1), unless  
replaced by VBI data. In addition, if the DVEN bit in VDCTL is 0, the blanking  
values are output during the portion of active video lines that are not a part of  
the displayed image.  
4.3.3 Y/C Image Display  
Many of the standards supported by the Y/C display mode provide for both  
interlaced and progressive scan formats. For interlaced display, the display  
controls are programmed identically to BT.656 mode. For progressive scan  
formats, the frame size is programmed to the size of a single field and only  
field 1 is used.  
The Y/C display mode uses the same FIFO organization as the BT.656 display  
mode and generates DMA events in the same manner.  
4.3.4 Y/C FIFO Unpacking  
Display data is always packed into the FIFOs in 64-bit words and must be  
unpacked before being sent to the display data pipeline. The unpacking and  
byte ordering is dependant upon the display data size and the device endian  
mode. For little-endian operation (default), data is unpacked from right to left;  
for big-endian operation, data is unpacked from left to right.  
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Y/C Video Display Mode  
The 8-bit Y/C mode uses three FIFOs for color separation. Four samples are  
unpacked from each word as shown in Figure 4–16.  
Figure 4–16. 8-Bit Y/C FIFO Unpacking  
VCLKOUT  
Y 0  
Y 1  
Y 2  
Y 3  
Y 4  
Y 5  
Y 6  
Y 7  
Y 8  
Y 9  
Y 10  
Cb 5  
Y 11  
Cr 5  
VDOUT[9–2]  
VDOUT[19–12]  
5655  
Cb 0  
Cr 0  
Cb 1  
Cr 1  
Cb 2  
Cr 2  
Cb 3  
Cr 3  
Cb 4  
Cr 4  
63  
4847  
4039  
3231  
2423  
1615  
8 7  
0
Y 31  
Y 23  
Y 15  
Y 7  
Y 30  
Y 22  
Y 29  
Y 28  
Y 27  
Y 26  
Y 25  
Y 24  
Y 21  
Y 13  
Y 5  
Y 20  
Y 12  
Y 4  
Y 19  
Y 11  
Y 3  
Y 18  
Y 10  
Y 2  
Y 17  
Y 9  
Y 16  
Y 8  
Y 14  
Y 6  
Y 1  
Y 0  
Y FIFO  
63  
63  
5655  
5655  
4847  
4847  
4039  
4039  
3231  
3231  
2423  
2423  
1615  
1615  
8 7  
8 7  
0
0
Cb 15  
Cb 7  
Cb 14  
Cb 6  
Cb 13  
Cb 5  
Cb 12  
Cb 4  
Cb 11  
Cb 3  
Cb 10  
Cb 2  
Cb 9  
Cb 1  
Cb 8  
Cb 0  
Cb FIFO  
Cr FIFO  
Cr 15  
Cr 7  
Cr 14  
Cr 6  
Cr 13  
Cr 5  
Cr 12  
Cr 4  
Cr 11  
Cr 3  
Cr 10  
Cr 2  
Cr 9  
Cr 1  
Cr 8  
Cr 0  
Little-Endian Unpacking  
63  
5655  
4847  
4039  
3231  
2423  
1615  
8 7  
0
Y 24  
Y 16  
Y 8  
Y 25  
Y 17  
Y 9  
Y 26  
Y 18  
Y 10  
Y 2  
Y 27  
Y 19  
Y 11  
Y 3  
Y 28  
Y 20  
Y 12  
Y 4  
Y 29  
Y 21  
Y 13  
Y 5  
Y 30  
Y 22  
Y 14  
Y 6  
Y 31  
Y 23  
Y 15  
Y 7  
Y 0  
Y 1  
Y FIFO  
63  
63  
5655  
5655  
4847  
4847  
4039  
4039  
3231  
3231  
2423  
2423  
1615  
1615  
8 7  
8 7  
0
0
Cb 8  
Cb 0  
Cb 9  
Cb 1  
Cb 10  
Cb 2  
Cb 11  
Cb 3  
Cb 12  
Cb 4  
Cb 13  
Cb 5  
Cb 14  
Cb 6  
Cb 15  
Cb 7  
Cb FIFO  
Cr FIFO  
Cr 8  
Cr 0  
Cr 9  
Cr 1  
Cr 10  
Cr 2  
Cr 11  
Cr 3  
Cr 12  
Cr 4  
Cr 13  
Cr 5  
Cr 14  
Cr 6  
Cr 15  
Cr 7  
Big-Endian Unpacking  
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Y/C Video Display Mode  
For 10-bit operation, two samples are unpacked from each FIFO word. This  
is shown in Figure 4–17.  
Figure 4–17. 10-Bit Y/C FIFO Unpacking  
VCLKOUT  
VDOUT[9–0]  
Y 0  
Y 1  
Y 2  
Y 3  
Y 4  
Y 5  
Y 6  
Y 7  
Y 8  
Y 9  
Y 10  
Cb 5  
Y 11  
Cr 5  
Cb 0  
Cr 0  
4847  
Cb 1  
Cr 1  
Cb 2  
Cr 2  
Cb 3  
Cr 3  
Cb 4  
Cr 4  
1615  
VDOUT[19–10]  
63  
5857  
4241  
3231  
2625  
10 9  
0
Y 15  
Y 11  
Y 7  
Y 14  
Y 10  
Y 6  
Y 13  
Y 9  
Y 5  
Y 1  
Y 12  
Y 8  
Y 4  
Y 0  
Y 3  
Y 2  
Y FIFO  
63  
63  
5857  
5857  
4847  
4847  
4241  
4241  
3231  
3231  
2625  
2625  
1615  
1615  
10 9  
10 9  
0
0
Cb 7  
Cb 3  
Cb 6  
Cb 2  
Cb 5  
Cb 1  
Cb 4  
Cb 0  
Cb FIFO  
Cr FIFO  
Cr 7  
Cr 3  
Cr 6  
Cr 2  
Cr 5  
Cr 1  
Cr 4  
Cr 0  
Little-Endian Unpacking  
63  
5857  
4847  
4241  
3231  
2625  
1615  
10 9  
0
Y 12  
Y 8  
Y 4  
Y 0  
Y 13  
Y 9  
Y 5  
Y 1  
Y 14  
Y 10  
Y 6  
Y 15  
Y 11  
Y 7  
Y 2  
Y 3  
Y FIFO  
63  
63  
5857  
5857  
4847  
4847  
4241  
4241  
3231  
3231  
2625  
2625  
1615  
1615  
10 9  
10 9  
0
0
Cb 4  
Cb 0  
Cb 5  
Cb 1  
Cb 6  
Cb 2  
Cb 7  
Cb 3  
Cb FIFO  
Cr FIFO  
Cr 4  
Cr 0  
Cr 5  
Cr 1  
Cr 6  
Cr 2  
Cr 7  
Cr 3  
Big-Endian Unpacking  
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Y/C Video Display Mode  
In 10-bit Y/C dense-pack mode, three samples are unpacked from each word  
in the FIFO as seen in Figure 4–18.  
Figure 4–18. 10-Bit Y/C Dense FIFO Unpacking  
VCLKOUT  
Y 0  
Y 1  
Y 2  
Y 3  
Y 4  
Y 5  
Y 6  
Y 7  
Y 8  
Y 9  
Y 10 Y 11  
VDOUT[9–0]  
Cb 0 Cr 0 Cb 1 Cr 1 Cb 2 Cr 2 Cb 3 Cr 3 Cb 4 Cr 4 Cb 5 Cr 5  
VDOUT[19–10]  
63 61  
Y 23  
Y 17  
Y 11  
Y 5  
5251  
4241  
3231 29  
2019  
10 9  
0
Y 22  
Y 16  
Y 10  
Y 4  
Y 21  
Y 15  
Y 9  
Y 20  
Y 14  
Y 8  
Y 19  
Y 13  
Y 7  
Y 18  
Y 12  
Y 6  
Y 3  
Y 2  
Y 1  
Y 0  
Y FIFO  
63 61  
Cb 11  
Cb 5  
5251  
5251  
4241  
4241  
3231 29  
3231 29  
2019  
2019  
10 9  
10 9  
0
0
Cb 10  
Cb 4  
Cb 9  
Cb 3  
Cb 8  
Cb 2  
Cb 7  
Cb 1  
Cb 6  
Cb 0  
Cb FIFO  
Cr FIFO  
63 61  
Cr 11  
Cr 5  
Cr 10  
Cr 4  
Cr 9  
Cr 3  
Cr 8  
Cr 2  
Cr 7  
Cr 1  
Cr 6  
Cr 0  
Little-Endian Packing  
63 61  
Y 18  
Y 12  
Y 6  
5251  
4241  
3231 29  
2019  
10 9  
0
Y 19  
Y 13  
Y 7  
Y 20  
Y 14  
Y 8  
Y 21  
Y 22  
Y 16  
Y 10  
Y 4  
Y 23  
Y 17  
Y 11  
Y 5  
Y 15  
Y 9  
Y 0  
Y 1  
Y 2  
Y 3  
Y FIFO  
63 61  
Cb 6  
5251  
5251  
4241  
4241  
3231 29  
3231 29  
2019  
2019  
10 9  
10 9  
0
0
Cb 7  
Cb 1  
Cb 8  
Cb 2  
Cb 9  
Cb 3  
Cb 10  
Cb 4  
Cb 11  
Cb 5  
Cb 0  
Cb FIFO  
Cr FIFO  
63 61  
Cr 6  
Cr 7  
Cr 1  
Cr 8  
Cr 2  
Cr 9  
Cr 3  
Cr 10  
Cr 4  
Cr 11  
Cr 5  
Cr 0  
Big-Endian Packing  
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Video Output Filtering  
4.4 Video Output Filtering  
The video output filter performs simple hardware scaling and resampling on  
outgoing 8-bit BT.656 or 8-bit Y/C data. Filtering hardware is disabled during  
10-bit or raw data display modes.  
4.4.1 Output Filter Modes  
The output filter has four modes of operation: no-filtering, 2× scaling, chromi-  
nance resampling, and 2× scaling with chrominance resampling. Filter opera-  
tion is determined by the DMODE, SCALE, and RESMPL bits of the VDCTL.  
Table 4–3 shows the output filter mode selection. When 8-bit BT.656 or Y/C  
display operation is selected, (DMODE = x00), scaling is selected by setting  
the SCALE bit and chrominance resampling is selected by setting the  
RESMPL bit. If 8-bit BT.656 or Y/C display is not selected (DMODE ≠ x00),  
filtering is disabled.  
Table 4–3. Output Filter Mode Selection  
VDCTL Bit  
DMODE  
RESMPL SCALE Filter Operation  
x00  
0
0
1
1
x
x
x
0
1
0
1
x
x
x
No filtering  
x00  
x00  
x00  
x01  
x10  
x11  
2× scaling  
Chrominance resampling (full scale)  
2× scaling with chrominance resampling  
No filtering  
No filtering  
No filtering  
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Video Output Filtering  
4.4.2 Chrominance Resampling Operation  
Chrominance resampling computes chrominance values at sample points  
corresponding to output luminance samples based on the input interspersed  
chrominance samples. This filter performs the conversion between inter-  
spersed YCbCr 4:2:2 format and co-sited YCbCr 4:2:2 format. The vertical  
portion of the conversion from YCbCr 4:2:0 to interspersed YCbCr 4:2:2 must  
be performed in software.  
The chrominance resampling filters calculate the implied value of Cb and Cr  
co-sited with luminance sample points based upon nearby interspersed Cb  
and Cr samples. The resulting values are clamped to between 01h and FEh  
before being output. Chrominance resampling is shown in Figure 4–19.  
Figure 4–19. Chrominance Resampling  
a
b
c
d
e
f
g
h
i
j
k
l
YCbCr 4:2:2 interspersed  
source pixels  
YCbCr 4:2:2 co–sited  
output results  
Luma (Y)  
sample  
Chroma (Cb/Cr)  
samples  
Cb’ = (–3Cb + 33Cb + 101Cb – 3Cb )/128  
ab cd ef gh  
–
–
f
Cr’ = (–3Cr + 33Cr + 101Cr – 3Cr ) / 128  
f
ab cd ef gh  
4.4.3 Scaling Operation  
The 2×-scaling mode is used to double the horizontal resolution of output  
luminance and chrominance data. This allows processed CIF resolution images  
to be output at full size. Vertical scaling must be performed in software. Scaling  
for co-sited source is shown in Figure 4–20 and scaling for interspersed  
source is shown in Figure 4–21.  
For a co-sited source, the source luminance pixels are output unchanged for  
every even pixel (a, b, c, etc., in Figure 4–20). Odd luminance pixels (a’, b’, c’,  
etc.) are generated from neighboring source (even) pixels using a four tap fil-  
ter. The chrominance source pixels are output unchanged for every other even  
pixel (a, c, e, etc.). Other even output pixel (b, d, f, etc.) chrominance values  
are generated from neighboring source chrominance pixels using a four tap  
filter.  
For an interspersed source, the luminance is output identically to the co-sited  
case. Chrominance output is generated using a four tap filter with one of two  
different coefficient sets depending on which source chrominance pixel the  
output pixel is closest.  
Note that because input scaling is limited to 2x, full BT.656 width output is not  
achieved from CIF source images. The horizontal location of the reduced  
image can be adjusted using HOFFSET.  
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Video Output Filtering  
Figure 4–20. 2x Co-Sited Scaling  
a
b
c
c
d
d
e
e
f
f
g
g
YCbCr 4:2:2 co–sited  
source pixels  
a
a’  
b
b’  
c’  
d’  
e’  
f’  
2× upscaled output  
Y’ = Y  
b
b
Y’ = (–1Y + 17Y + 17Y – 1Y ) / 32  
d’  
Cb’ = Cb  
c
d
e
f
c
c
c
Cr’ = Cr  
c
Luma (Y)  
sample  
Chroma (Cb/Cr)  
samples  
Cb’ = (–1Cb + 17Cb + 17Cb – 1Cb ) / 32  
–
–
d
a
c
e
g
Cr’ = (–1Cr + 17Cr + 17Cr – 1Cr ) / 32  
d
a
c
e
g
Figure 4–21. 2x Interspersed Scaling  
YCbCr 4:2:2  
a
b
c
c
d
e
f
g
interspersed  
source pixels  
2x upscaled  
YCbCr 4:2:2  
g
a
a’  
b
b’  
c’  
d
d’  
e
e’  
f
f’  
h’  
co-sited output  
Y’ = Y  
Y’ = (–1Y + 17Y + 17Y – 1Y ) / 32  
a
a
e’  
d
e
f
g
Cb’ = (–3Cb + 101Cb + 33Cb  
ab cd  
3Cb ) / 128  
gh  
d
ef –  
ef –  
Cb’ = (–3Cb + 33Cb + 101Cb  
ab cd  
3Cb ) / 128  
gh  
gh  
e
ef –  
Cr’ = (–3Cr + 101Cr + 33Cr  
3Cr ) / 128  
d
ab  
cd  
gh  
Cr’ = (–3Cr + 33Cr + 101Cr  
3Cr ) / 128  
e
ab cd ef –  
Luma (Y)  
Chroma (Cb/Cr)  
samples  
–
–
sample  
4.4.4 Edge Pixel Replication  
Because four tap filters are used on the output, the first and last two pixels on  
each line must be mirrored. An example of how the filter uses the mirrored pixels  
for the luminance filter (2× co-sited) is shown in Figure 4–22.  
Figure 4–22. Output Edge Pixel Replication  
a
a
b
c
n–2  
n–1  
n
n
n
n–1  
Horizontal Image Size  
Trailing edge  
a
a’  
b
b’  
c
n–2 n–2’ n–1 n–1’  
n’  
replicated pixels  
Leading edge  
replicated pixel  
Y’ = Y Y’ = Y  
Y’ = Y  
Y’ = Y  
n
Y’  
n–2  
n–2  
=
a
a
b
b
c
c
n
Y’  
Y
n–1  
=
n–1  
Y
Y’ = ƒ(Y  
n’  
, Y , Y , Y  
Y’ ’ = ƒ(Y , Y , Y , Y )  
a’ a’ b’  
n–1  
n
n
n–1)  
a
c
Y’ = ƒ(Y , Y , Y , Y )  
b’ a’ b’ c’  
d
Y’  
= ƒ(Y  
, Y , Y , Y )  
n–1’  
n–2 n–1 n’  
n
Luma (Y)  
sample  
Chroma (Cb/Cr)  
samples  
–
–
Y’  
n–2’  
= ƒ(Y  
, Y , Y , Y )  
n–3 n–2 n–1’  
n
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Video Output Filtering  
Examples of luma edge and chroma edge replication for 2× interspersed to  
co-sited output are shown in Figure 4–23 and Figure 4–24, respectively.  
Figure 4–23. Luma Edge Replication  
a
a
b
c
x
y
y
z
z
z
y
Horizontal Image Size  
a
a’  
b
b’  
c
x
x’  
y’  
z’  
Trailing edge  
Leading edge  
replicated luma  
replicated luma  
Y’ = Y  
Y’ = Y  
b
Y’ = Y  
c
Y’ = Y  
x
Y’ = Y  
y
Y’ = Y  
z z  
a
a
b
c
x
y
Y’ = (–1Y + 17Y + 17Y – 1Y ) /32  
z’  
y
z
z
y
Y’ = (–1Y + 17Y + 17Y – 1Y ) /32  
b’  
a
b
c
d
Y’ = (–1Y + 17Y + 17Y – 1Y ) /32  
y’  
x
y
z
z
Y’ = (–1Y + 17Y + 17Y – 1Y ) /32  
x’  
w
x
y
z
Y’ = (–1Y + 17Y + 17Y – 1Y ) /32  
a’  
a
a
b
c
Figure 4–24. Interspersed Chroma Edge Replication  
cd  
ab  
a
ab  
b
c
cd  
d
w
wx  
x
x
y
yz  
z
z
yz  
wx  
Horizontal Image Size  
c’  
Leading edge  
replicated chroma  
samples  
Trailing edge  
a
a’  
b
b’  
c
d
w
w’  
x’  
y
y’  
z’  
replicated chroma  
samples  
Cb’ = (–3Cb + 33Cb + 101Cb –3Cb )/128  
a cd ab ab cd  
Cb’ = (–3Cb  
z wx  
+ 101Cb + 33Cb –3Cb )/128  
yz yz wz  
Cr’ = (–3Cr + 33Cr + 101Cr –3Cr )/128  
a
cd  
ab  
ab  
cd  
Cr’ = (–3Cr  
z
+ 101Cr + 33Cr –3Cb )/128  
wx yz yz wx  
Cb’ = (–3Cb + 101Cb + 33Cb –3Cb )/128  
Cb’ = (–3Cb + 33Cb  
+ 101Cb –3Cb )/128  
b
ab ab cd ef  
y
uv wx yz yz  
Cr’ = (–3Cr + 101Cr + 33Cr –3Cr )/128  
b ab ab cd ef  
Cr’ = (–3Cr + 33Cr + 101Cr –3Cb )/128  
wx  
y
uv yz yz  
Cb’ = (–3Cb + 101Cb  
+ 33Cb –3Cb )/128  
Cb’ = (–3Cb + 33Cb + 101Cb –3Cb )/128  
c ab ab cd ef  
x
uv wx yz yz  
Cr’ = (–3Cr + 33Cr + 101Cr –3Cr )/128  
c ab ab cd ef  
Cr’ = (–3Cr + 101Cr  
+ 33Cr –3Cr )/128  
x
uv wx yz yz  
Cb’ = (–3Cb + 101Cb + 33Cb –3Cb )/128  
d ab cd ef gh  
Cb’ = (–3Cb + 33Cb + 101Cb  
w st uv wx  
–3Cb )/128  
yz  
Cr’ = (–3Cr + 101Cr + 33Cr –3Cr )/128  
d ab cd ef gh  
Cr’ = (–3Cr + 33Cr + 101Cr  
–3Cr )/128  
w
st uv wx yz  
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Video Display Port  
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Ancillary Data Display / Raw Data Display Mode  
4.5 Ancillary Data Display  
Thefollowingsectionsdiscussancillarydatadisplay. Nospecialprevisionsare  
madeforthedisplayofhorizontalancillary (HANC)orverticalancillary(VANC),  
also called vertical blanking interval (VBI), data.  
4.5.1 Horizontal Ancillary (HANC) Data Display  
HANC data can be displayed using the normal video display mechanism by  
programming IMGHSIZEn to occur prior to the SAV code. The HANC data  
including the ancillary data header must be part of the YCbCr separated data  
in the FIFOs. The VCTHRLD value and DMA size must be programmed to  
comprehend the additional samples. You must disable scaling and chroma re-  
sampling when including the display of HANC data to prevent data corruption.  
4.5.2 Vertical Ancillary (VANC) Data Display  
VANC(or VBI) data is commonly used for such features as teletext andclosed-  
captioning. No special provisions are made for the display of VBI data. VBI  
data may be displayed using the normal display mechanism by programming  
IMGVOFF to occur before the first line of active video on the first line of desired  
VBI data. Note that the VBI data must be YCbCr separated. You must disable  
scaling and chroma resampling when the display of VBI data is desired or the  
data will be corrupted by the filters.  
4.6 Raw Data Display Mode  
The raw data display modes are intended to output data to a RAMDAC or other  
D/A-type device. This is typically RGB formatted data. No timing information  
is inserted into the output data stream; instead, selectable control signals are  
output to indicate timing. Raw data display includes a synchronized dual channel  
option. This allows channel B to output a separate data stream using the same  
clock and control as channel A. This mode is useful when used with a second  
video port in systems that require 24-bit to 30-bit RGB output.  
TherawdatamodeusesasingleFIFOof5120bytesforstorageofoutputdata.  
The FIFO is filled by DMAs writing to the Y FIFO destination register A  
(YDSTA). DMAs are requested using the YEVTA event. In raw sync mode  
(RSYNC bit is set), the FIFO is split into 2560-byte channel A and B buffers.  
The channel B FIFO is filled by DMAs using the Y FIFO destination register  
B (YDSTB) as a destination. Both YEVTA and YEVTB events are generated  
using the channel A timing control.  
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Raw Data Display Mode  
4.6.1 Raw Mode RGB Output Support  
The raw data display mode has a special pixel count feature that allows the  
FPCOUNTincrement rate to be set. FPCOUNT increments only whenINCPIX  
samples have been sent out. This option allows proper tracking of the display  
pixels when sending out sequential RGB samples. (INCPIX would be set to  
three in this case, to indicate that a single pixel is represented by three output  
samples.)  
Sequential RGB samples output are also supported through a special FIFO  
unpacking mode. When the 8-bit raw ¾ unpacking is selected (RGBX bit in  
VDCTL), three output bytes are selected from each word and the fourth byte  
is ignored. This allows the video port to correctly output data formatted as  
24-bit RGB (or RGBα) words in memory.  
4.6.2 Raw Data FIFO Unpacking  
Display data is always packed into the FIFOs in 64-bit words and must be  
unpacked before being sent to the display data pipeline. The unpacking and  
byte ordering is dependant upon the display data size and the device endian  
mode. For little-endian operation (default), data is unpacked from right to left;  
for big-endian operation, data is unpacked from left to right.  
The 8-bit raw mode uses a single data FIFO. Four samples are unpacked from  
each word as shown in Figure 4–25.  
Figure 4–25. 8-Bit Raw FIFO Unpacking  
VCLKOUT  
Raw 0 Raw 1 Raw 2 Raw 3 Raw 4 Raw 5 Raw 6 Raw 7 Raw 8 Raw 9 Raw 10 Raw 11  
VDOUT[9–2]  
63  
63  
5655  
4847  
4847  
4039  
4039  
3231  
2423  
2423  
1615  
1615  
8 7  
0
0
Raw 15  
Raw 14  
Raw 6  
Raw 13  
Raw 5  
Raw 12  
Raw 4  
Raw 11  
Raw 3  
Raw 10  
Raw 2  
Raw 9  
Raw 1  
Raw 8  
Raw 0  
Raw 7  
Raw FIFO  
Little-Endian Unpacking  
5655  
3231  
8 7  
Raw 8  
Raw 0  
Raw 9  
Raw 1  
Raw 10  
Raw 2  
Raw 11  
Raw 3  
Raw 12  
Raw 4  
Raw 13  
Raw 5  
Raw 14  
Raw 6  
Raw 15  
Raw 7  
Raw FIFO  
4-26  
Big-Endian Unpacking  
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Raw Data Display Mode  
For 10-bit operation, two samples are unpacked from each FIFO word. This  
is shown in Figure 4–26.  
Figure 4–26. 10-Bit Raw FIFO Unpacking  
VCLKOUT  
VDOUT[9–0]  
5857  
Raw 0 Raw 1 Raw 2 Raw 3 Raw 4 Raw 5 Raw 6 Raw 7 Raw 8 Raw 9 Raw 10 Raw 11  
63  
4847  
4241  
3231  
2625  
1615  
10 9  
0
Raw 15  
Raw 11  
Raw 7  
Raw 3  
Raw 14  
Raw 10  
Raw 6  
Raw 2  
Raw 13  
Raw 9  
Raw 5  
Raw 1  
Raw 12  
Raw 8  
Raw 4  
Raw 0  
Y FIFO  
Little-Endian Unpacking  
63  
5857  
4847  
4241  
3231  
2625  
1615  
10 9  
0
Raw 12  
Raw 8  
Raw 4  
Raw 0  
Raw 13  
Raw 9  
Raw 5  
Raw 1  
Raw 14  
Raw 10  
Raw 6  
Raw 2  
Raw 15  
Raw 11  
Raw 7  
Raw 3  
Y FIFO  
Big-Endian Unpacking  
In 10-bit raw dense-pack mode, three samples are unpacked from each word  
in the FIFO as seen in Figure 4–27.  
Figure 4–27. 10-Bit Raw Dense FIFO Unpacking  
VCLKOUT  
Raw 0 Raw 1 Raw 2 Raw 3 Raw 4 Raw 5 Raw 6 Raw 7 Raw 8 Raw 9 Raw 10 Raw 11  
VDOUT[9–0]  
63 61  
5251  
4241  
3231 29  
2019  
10 9  
0
Raw 17  
Raw 11  
Raw 5  
Raw 16  
Raw 10  
Raw 4  
Raw 15  
Raw 9  
Raw 3  
Raw 14  
Raw 8  
Raw 2  
Raw 13  
Raw 7  
Raw 1  
Raw 12  
Raw 6  
Raw 0  
Y FIFO  
Little-Endian Unpacking  
63 61  
5251  
4241  
3231 29  
2019  
10 9  
0
Raw 12  
Raw 6  
Raw 0  
Raw 13  
Raw 7  
Raw 1  
Raw 14  
Raw 8  
Raw 2  
Raw 15  
Raw 16  
Raw 10  
Raw 4  
Raw 17  
Raw 11  
Raw 5  
Raw 9  
Raw 3  
Y FIFO  
Big-Endian Unpacking  
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Raw Data Display Mode  
Figure 4–28 shows the 16-bit raw mode. Two samples are unpacked from  
each word of the FIFO.  
Figure 4–28. 16-Bit Raw FIFO Unpacking  
VCLKOUT  
Raw 0 Raw 1 Raw 2 Raw 3 Raw 4 Raw 5 Raw 6 Raw 7 Raw 8 Raw 9 Raw 10 Raw 11  
VDOUT[19–12]/VDOUT[9–2]  
63  
4847  
3231  
1615  
0
0
Raw 11  
Raw 10  
Raw 6  
Raw 2  
Raw 9  
Raw 5  
Raw 1  
Raw 8  
Raw 4  
Raw 0  
Raw 7  
Raw 3  
Raw FIFO  
Little-Endian Unpacking  
63  
4847  
3231  
1615  
Raw 8  
Raw 4  
Raw 9  
Raw 10  
Raw 6  
Raw 2  
Raw 11  
Raw 7  
Raw 3  
Raw 5  
Raw 1  
Raw 0  
Raw FIFO  
Big-Endian Unpacking  
The FIFO unpacking for 20-bit raw format is shown in Figure 4–29. One sample  
is unpacked from each word of the FIFO.  
Figure 4–29. 20-Bit Raw FIFO Unpacking  
VCLKOUT  
Raw 0 Raw 1 Raw 2 Raw 3 Raw 4 Raw 5 Raw 6 Raw 7 Raw 8 Raw 9 Raw 10 Raw 11  
VDOUT[19–0]  
63  
5251  
3231  
2019  
0
Raw 7  
Raw 5  
Raw 3  
Raw 1  
Raw 6  
Raw 4  
Raw 2  
Raw 0  
Y FIFO  
Little-Endian Unpacking  
3231  
63  
5251  
2019  
0
Raw 6  
Raw 4  
Raw 2  
Raw 0  
Raw 7  
Raw 5  
Raw 3  
Raw 1  
Y FIFO  
4-28  
Big-Endian Unpacking  
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Raw Data Display Mode  
In 8-bit raw ¾ mode, three samples are unpacked from the FIFO and the  
remaining byte is ignored. This is shown in Figure 4–30.  
Figure 4–30. 8-Bit Raw 3/4 FIFO Unpacking  
VCLKOUT  
VDOUT[9–2]  
5655  
Raw 0 Raw 1 Raw 2 Raw 3 Raw 4 Raw 5 Raw 6 Raw 7 Raw 8 Raw 9 Raw 10 Raw 11  
(B3)  
(R0)  
(G0)  
(B0)  
(R1)  
(G1)  
(B1)  
(R2)  
(G2)  
(B2)  
(R3)  
(G3)  
63  
4847  
4039  
3231  
2423  
1615  
8 7  
0
0
Raw 11 (B3)  
Raw 5 (B1)  
Raw 10 (G3)  
Raw 4 (G1)  
Raw 9 (R3)  
Raw 3 (R1)  
Raw 8 (B2)  
Raw 2 (B0)  
Raw 7 (G2)  
Raw 1 (G0)  
Raw 6 (R2)  
Raw 0 (R0)  
Raw FIFO  
Little-Endian Unpacking  
63  
5655  
4847  
4039  
3231  
2423  
1615  
8 7  
Raw 6 (R2)  
Raw 0 (R0)  
Raw 7 (G2)  
Raw 1 (G0)  
Raw 8 (B2)  
Raw 2 (B0)  
Raw 9 (R3)  
Raw 10 (G3)  
Raw 4 (G1)  
Raw 11 (B3)  
Raw 5 (B1)  
Raw 3 (R1)  
Raw FIFO  
Big-Endian Unpacking  
In 10-bit raw ¾ mode, three samples are unpacked from every doubleword of  
the FIFO and the remaining halfword is ignored. This is shown in Figure 4–31.  
Figure 4–31. 10-Bit Raw 3/4 FIFO Unpacking  
VCLKOUT  
Raw 0  
(R0)  
Raw 1 Raw 2 Raw 3 Raw 4 Raw 5 Raw 6 Raw 7 Raw 8 Raw 9 Raw 10 Raw 11  
(B3)  
VDOUT[9–0]  
(G0)  
(B0)  
(R1)  
(G1)  
(B1)  
(R2)  
(G2)  
(B2)  
(R3)  
(G3)  
63  
5857  
4847  
4241  
3231  
2625  
1615  
109  
0
0
Raw 5 (B1)  
Raw 2 (B0)  
Raw 4 (G1)  
Raw 1 (G0)  
Raw 3 (R1)  
Raw 0 (R0)  
Raw FIFO  
Little-Endian Unpacking  
63  
5857  
4847  
4241  
3231  
2625  
1615  
109  
Raw 3 (R1)  
Raw 0 (R0)  
Raw 4 (G1)  
Raw 1 (G0)  
Raw 5 (B1)  
Raw 2 (B0)  
Raw FIFO  
Big-Endian Unpacking  
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Video Display Field and Frame Operation  
4.7 Video Display Field and Frame Operation  
As a video source, the video port always outputs entire frames of data and  
transmits continuous video control signals. Depending on the DMA structure,  
however, the video port may need to interrupt the DSP on a field or frame basis  
to allow it to update video port registers or DMA parameters. To achieve this,  
the video port provides programmable control over the display process.  
4.7.1 Display Determination and Notification  
In order to accommodate various display scenarios, DMA structures, and  
processing flows, the video port employs a flexible display and DSP notifica-  
tion system. This is programmed using the CON, FRAME, DF1, and DF2 bits  
in VDCTL.  
The CON bit controls the display of multiple fields or frames. When CON = 1,  
continuous display is enabled, the video port displays outgoing fields (assuming  
the VDEN bit is set) without the need for DSP interaction. It relies on a single  
display buffer in memory or on a DMA structure with circular buffering capabili-  
ty to service the display FIFOs. When CON = 0, continuous display is  
disabled, the video port sets a field or frame display complete bit (F1D, F2D,  
or FRMD) in VDSTAT upon the display of each field as determined by the state  
of the other display control bits (FRAME, CD1, and CD2). Once the display  
complete bit is set, the processor must update the appropriate DMA parameters  
within the allotted time frame or a subsequent field or frame may output invalid  
data. In this case, the video port continues to generate DMA requests but it  
issues a DCNA (display complete not acknowledged) interrupt to indicate that  
the DMA parameters may not have been updated and bad data is being sent  
to the video port.  
When a field or frame has not been enabled for display, no DMA events are  
sent for that field or frame. The video port still generates all timings for the field  
but outputs the default data values rather than data from the display FIFO  
during the display image window.  
The CON, FRAME, DF1, and DF2 bits encode the display operations as listed  
in Table 4–4.  
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Video Display Field and Frame Operation  
Table 4–4. Display Operation  
VDCTL Bit  
CON FRAME  
DF2  
DF1 Operation  
0
0
0
0
0
0
1
Reserved  
0
Noncontinuous field 1 display. Display only field 1. F1D is set after  
field 1 display and causes DCMPx to be set. The F1D bit must be  
cleared by the DSP or a DCNA interrupt occurs. (The DSP has the en-  
tire field 2 time to clear F1D before next field 1 begins.) Can also be  
used for single progressive frame display (internal timing codes only).  
(The DSP has vertical blanking time to clear F1D before next frame  
begins.)  
0
0
0
0
1
1
0
1
Noncontinuous field 2 display. Display only field 2. F2D is set after  
field 2 display and causes DCMPx to be set. The F2D bit must be  
cleared by the DSP or a DCNA interrupt occurs. (The DSP has the en-  
tire field 1 time to clear F2D before next field 2 begins.)  
Noncontinuous field 1 and field 2 display. Display both fields. F1D is set  
after field 1 display and causes DCMPx to be set. The F1D bit must be  
cleared by the DSP before the next field 1 display or a DCNA interrupt  
occurs. (The DSP has the entire field 2 time to clear F1D before next  
field 1 begins.) F2D is set after field 2 display and also causes DCMPx  
to be set. The F2D bit must be cleared by the DSP before the next  
field 2 display or a DCNA interrupt occurs. (The DSP has the entire  
field 1 time to clear F2D before next field 2 begins.)  
0
0
1
1
0
0
0
1
Noncontinuous frame display. Display both fields. FRMD is set after  
field 2 display and causes DCMPx to be set. A DCNA interrupt occurs  
upon completion of the next frame unless the FRMD bit is cleared. (The  
DSP has the entire next frame time to clear FRMD.)  
Noncontinuous progressive frame display. Display field 1. FRMD is set  
after field 1 display and causes DCMPx to be set. A DCNA interrupt  
occurs upon completion of the next frame unless the FRMD bit is  
cleared. (The DSP has the entire next frame time to clear FRMD.) If  
external control signals are used, they must follow progressive format.  
0
0
1
1
1
1
0
1
Reserved  
Single frame display. Display both fields. FRMD is set after field 2 dis-  
play and causes DCMPx to be set. A DCNA interrupt occurs unless the  
FRMD bit is cleared. (The DSP has the field 2 to field 1 vertical blank-  
ing time to clear FRMD.)  
1
1
0
0
0
0
0
1
Reserved  
Continuous field 1 display. Display only field 1. F1D is set after field 1  
display and causes DCMPx to be set (DCMPx interrupt can be dis-  
abled). No DCNA interrupt occurs, regardless of the state of F1D.  
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Video Display Field and Frame Operation  
Table 4–4. Display Operation (Continued)  
VDCTL Bit  
CON FRAME  
DF2  
DF1  
Operation  
1
0
1
0
Continuous field 2 display. Display only field 2. F2D is set after field 2  
display and causes DCMPx to be set (DCMPx interrupt can be dis-  
abled). No DCNA interrupt occurs, regardless of the state of F2D.  
1
1
0
1
1
0
1
0
Reserved  
Continuous frame display. Display both fields. FRMD is set after field 2  
display and causes DCMPx to be set (DCMPx interrupt can be dis-  
abled. No DCNA interrupt occurs, regardless of the state of FRMD.  
1
1
0
1
Continuous progressive frame display. Display field 1. FRMD is set af-  
ter field 1 display and causes DCMPx to be set (DCMPx interrupt can  
be disabled). No DCNA interrupt occurs, regardless of the state of  
FRMD. (Functions identically to continuous field 1 display mode except  
the FRMD bit is used instead of the F1D bit.) If external control signals  
are used, they must follow progressive format.  
1
1
1
1
1
1
0
1
Reserved  
Reserved  
4.7.2 Video Display Event Generation  
The display FIFOs are filled using DMAs as requested by the video port DMA  
events. The VDTHRLD value indicates the level at which the FIFO has enough  
roomtoreceiveanotherDMAblockofdata. DependingonthesizeoftheDMA,  
the FIFO may have room for multiple transfers before reaching the VDTHRLD  
level. Once the threshold is reached, another DMA event is generated as soon  
as the FIFO again falls below the VDTHRLD level.  
Once an entire field worth of data has been sent to the FIFO, the video port  
may need to stop generating events in order to allow the DSP to change DMA.  
Since display may not yet be complete (the FIFO continues to empty after  
falling below VDTHRLD), a display event counter (DEVTCT) is provided to  
track the number of requested YEVT events. The counter is loaded with the  
number of events needed in a display field (DISPEVT1 or DISPEVT2) and is  
decremented each time the event is requested. Once the counter reaches 0,  
further display events are inhibited. At the start of the next field, DEVTCT is  
reloaded and display events are reenabled.  
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Display Line Boundary Conditions  
4.8 Display Line Boundary Conditions  
In order to simplify DMA transfers, FIFO doublewords do not contain data from  
more than one display line. This means that a FIFO read must be performed  
whenever 8-bytes have been output or when the line complete condition  
(IPCOUNT = IMGHSIZE) occurs. Thus, every display line begins on a double-  
word boundary and non-doubleword length lines are truncated at the end. An  
example is shown in Figure 4–32.  
In Figure 4–32 (8-bit Y/C mode), the line length is not a doubleword. When the  
condition IPCOUNT = IMGHSIZE occurs, the remaining bytes of the FIFO  
doubleword are ignored and the output switches to the default output value (or  
the EAV code followed by blanking, if the end of the active video line has been  
reached). The next display line then begins in the next FIFO location at byte 0.  
This operation extends to all display modes.  
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Display Line Boundary Conditions  
Figure 4–32. Display Line Boundary Example  
IPCOUNT = IMGSIZE(78)  
Line n  
VCLKOUT  
VDOUT[9–2]  
VDOUT[19–12]  
5655  
Y 72  
Y73  
Y 76  
Y 77  
Y 78  
Y 79  
Y 80  
Y 81  
Y 82  
Y 83  
Y 74  
Y 75  
Cb 36 Cr 36 Cb 37 Cr 37 Cb 38 Cr 38 Cb 39 Cr 39 Cb 40 Cr 40 Cb 41 Cr 41  
63  
63  
4847  
4039  
3231  
2423  
1615  
8 7  
0
Line n+1  
Line n  
Y 7  
Y 6  
Y 5  
Y 4  
Y 3  
Y 2  
Y 1  
Y 0  
Y 77  
Y 69  
Y 76  
Y 68  
Y 75  
Y 67  
Y 74  
Y 66  
Y 73  
Y 65  
Y 72  
Y 64  
Y 71  
Y 70  
Y FIFO  
5655  
5655  
4847  
4847  
4039  
4039  
3231  
3231  
2423  
2423  
1615  
1615  
8 7  
8 7  
0
0
Line n+1  
Line n  
Cb 7  
Cr 7  
Cb 6  
Cb 5  
Cb 4  
Cb 3  
Cb 2  
Cb 1  
Cb 0  
Cb 38  
Cb 37  
Cb 36  
Cb 35  
Cb 34  
Cb 33  
Cb 32  
Cb FIFO  
63  
Line n+1  
Line n  
Cr 6  
Cr 5  
Cr 4  
Cr 3  
Cr 2  
Cr 1  
Cr 0  
Cr 38  
Cr 37  
Cr 36  
Cr 35  
Cr 34  
Cr 33  
Cr 32  
Cr FIFO  
Little-Endian Packing  
63  
63  
5655  
4847  
4039  
3231  
2423  
1615  
8 7  
0
Line n+1  
Line n  
Y 0  
Y 1  
Y 2  
Y 3  
Y 4  
Y 5  
Y 6  
Y 7  
Y 72  
Y 64  
Y 73  
Y 65  
Y 74  
Y 66  
Y 75  
Y 67  
Y 76  
Y 68  
Y 77  
Y 69  
Y 70  
Y 71  
Y FIFO  
5655  
5655  
4847  
4847  
4039  
4039  
3231  
3231  
2423  
2423  
1615  
1615  
8 7  
8 7  
0
0
Line n+1  
Line n  
Cb 0  
Cb 1  
Cb 2  
Cb 3  
Cb 4  
Cb 5  
Cb 6  
Cb 7  
Cr 7  
Cb 32  
Cb 33  
Cb 34  
Cb 35  
Cb 36  
Cb 37  
Cb 38  
Cb FIFO  
63  
Line n+1  
Line n  
Cr 0  
Cr 1  
Cr 2  
Cr 3  
Cr 4  
Cr 5  
Cr 6  
Cr 32  
Cr 33  
Cr 34  
Cr 35  
Cr 36  
Cr 37  
Cr 38  
Cr FIFO  
Big-Endian Packing  
4-34  
Video Display Port  
SPRU629  
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Display Timing Examples  
4.9 Display Timing Examples  
The following are examples of display output for several modes of operation.  
4.9.1 Interlaced BT.656 Timing Example  
This section shows an example of BT.656 display output for a 704 × 408 inter-  
laced output image as might be generated by MPEG decoding.  
The horizontal output timing is shown in Figure 4–33. This diagram assumes  
that there is a two VCLK pipeline delay between the internal counter changing  
and the output on external pins. The actual delay can be longer or shorter as  
long as it is consistent within any display mode. The BT.656 active line is  
720-pixels wide. Figure 4–33 shows the 704-pixel image window centered in  
the screen that results in an IMGHOFFx of 8 pixels.  
The HBLNK and HSYNC signals are shown as they would be output for active-  
low operation. Note that only one of the two signals is actually available exter-  
nally. The HBLNK inactive edge occurs either on sample 856 coincident with  
the start of SAV or on sample 0 (after SAV) if the HBDLA bit is set. For true  
BT.656 operation, neither HBLNK nor HSYNC would be used.  
The IPCOUNT operation follows the description in section 4.1.2. IPCOUNT  
resets to 0 at the first displayed pixel (FPCOUNT = IMGHOFFx) and stops  
counting at the last displayed pixel (IPCOUNT = IMGHSIZEx). The operation  
during nondisplay time is not a requirement, it could continue counting until the  
next FPCOUNT = IMGHOFFx point or it could reset immediately after  
IMGHSIZEx or when FPCOUNT is reset.  
VDOUT shows the output data and switching between EAV, Blanking Data,  
SAV, Default Data, and FIFO Data. It is assumed that the DVEN bit in VDCTL  
is set to enable the default output.  
SPRU629  
Video Display Port  
4-35  
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Figure 4–33. BT.656 Interlaced Display Horizontal Timing Example  
VCLKIN  
268  
1440  
4
4
One Line  
Next Line  
720 721 722 723  
703 703 703 703  
735 736  
703 703  
799 800  
855 856 857  
703 703 703  
0
1
7
8
9
10  
2
710 711 712  
702 703 703  
718 719 720 721  
703 703 703 703  
FPCOUNT  
IPCOUNT  
0
1
703  
703 703  
703 703  
‡
)†  
VCTL1 (HBLNK  
§
§
†
VCTL1 (HSYNC)  
VCLKOUT  
Display Image  
Blanking  
Active Video  
VDOUT[9–0]  
EAV Blanking Data  
SAV  
EAV  
n + 1  
FLCOUNT  
n
n – 1  
FRMWIDTH = 858  
HBLNKSTART = 720  
HBLNKSTOP = 856  
IMGHOFF1 = 8  
IMGHSIZE1 = 704  
IMGHOFF2 = 8  
IMGHSIZE2 = 704  
HSYNCSTART = 736  
HSYNCSTOP = 800  
†
Assumes VCT1P bit in VPCTL is set to 1 (active-low output). HSYNC output when VCTL1S bit in VDCTL is set to 00,  
HBLNK output when VCTL1S bit is set 01.  
‡
§
HBLNK operation when HBDLA bit in VDHBLNK is set to 1.  
Diagram assumes a two VCLK pipeline delay between internal counters and output signals.  
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Display Timing Examples  
The interlaced BT.656 vertical output timing is shown in Figure 4–34. The  
BT.656 active field 1 is 244-lines high and active field 2 is 243-lines high. This  
example shows the 480-line image window centered in the screen. This  
results in an IMGVOFFn of 3 lines and also results in a nondata line at the end  
of field 1 due to its extra active line.  
The VBLNK and VSYNC signals are shown as they would be output for active-  
low operation. Note that only one of the two signals is actually available exter-  
nally. The VBLNK and VSYNC edges for field 1 occur at the end of an active  
line so their XSTART/XSTOP values are set to 720 (start of blanking). For  
field 2, VBLNK and VSYNC edges occur during the middle of the active  
horizontal line so their XSTART/XSTOP values are set to 360. Note that, from  
an analog standpoint, vertical blanking begins a half-line before digital blanking  
so that VBLNKYSTART2 is set to 263 (with VBLNKXSTART2 set to 360) while  
VBITSET2 is programmed to 264. For true BT.656 operation, neither VBLNK  
nor VSYNC would be used.  
The FLD output is setup to transition at the start of each analog field (start of  
vertical blanking). Since EAV[F] transitions on lines 4 and 266, this requires  
programming FBITCLR to 4, FBITSET to 266, FLD1YSTART to 1, and  
FLD2YSTART to 263. Note that FLD2XSTRT is 360 so that the field indicator  
output changes halfway through the line.  
The ILCOUNT operation follows the description in section 4.1.2. ILCOUNT  
resets to 1 at the first displayed line (FLCOUNT = VBLNKSTOPx + IMGVOFFx)  
and stops counting at the last displayed pixel (IPCOUNT = IMGVSIZEx). The  
operation during nondisplay time is not a requirement, it could continue count-  
ing until the next FLCOUNT = VBLNKSTOPx + IMGVOFFx point or it could  
reset immediately after IMGVSIZEx or when FLCOUNT is reset.  
The active horizontal output column shows the output data during the active  
portion of the horizontal line. It is assumed that the DVEN bit in VDCTL is set  
to enable the default output.  
SPRU629  
Video Display Port  
4-37  
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Display Timing Examples  
Figure 4–34. BT.656 Interlaced Display Vertical Timing Example  
Active  
Horizontal  
Output  
EAV  
ILCOUNT V F  
FLCOUNT  
525  
1
2
3
4
5
6
240  
240  
240  
240  
240  
240  
240  
0 1  
1 1  
1 1  
1 1  
1 0  
1 0  
1 0  
Blanking Value  
Blanking Value  
Blanking Value  
Blanking Value  
Blanking Value  
Blanking Value  
Blanking Value  
Field 1 Blanking  
19  
20  
21  
22  
23  
240  
240  
240  
240  
1
1 0  
0 0  
0 0  
0 0  
0 0  
0 0  
Blanking Value  
Default Value§  
Default Value§  
Default Value§  
FIFO Data  
Field 1 Active  
Field 1 Image  
2
FIFO Data  
239  
240  
240  
240  
240  
240  
240  
240  
240  
0 0  
0 0  
0 0  
1 0  
1 0  
1 1  
1 1  
1 1  
1 1  
FIFO Data  
FIFO Data  
262  
263  
264  
265  
266  
267  
268  
269  
Default Value§  
Blanking Value  
Blanking Value  
Blanking Value  
Blanking Value  
Blanking Value  
Blanking Value  
Field 2 Blanking  
282  
283  
284  
285  
286  
240  
240  
240  
240  
1
1 1  
0 1  
0 1  
0 1  
0 1  
0 1  
Blanking Value  
Default Value§  
Default Value§  
Default Value§  
FIFO Data  
Field 2 Active  
Field 2 Image  
2
FIFO Data  
524  
525  
1
239  
240  
240  
240  
0 0  
0 1  
1 1  
1 1  
FIFO Data  
FIFO Data  
Blanking Value  
Blanking Value  
IMGVOFF1 = 3  
VBLNKXSTART1 = 720  
VBLNKYSTART1 = 1  
VBLNKXSTOP1 = 720  
VBLNKYSTOP1 = 20  
VBLNKXSTART2 = 360  
VBLNKYSTART2 = 263  
VBLNKXSTOP2 = 360  
VBLNKYSTOP2 = 283  
VSYNCXSTART1 = 720  
VSYNCYSTART1 = 4  
VSYNCXSTOP1 = 720  
VSYNCYSTOP1 = 7  
FLD1XSTART = 720  
IMGVSIZE1 = 240  
IMGVOFF2 = 3  
FLD1YSTART = 1  
FLD2XSTART = 360  
FLD2YSTART = 263  
IMGVSIZE2 = 240  
FRMHEIGHT = 525  
VBITSET1 = 1  
VSYNCXSTART2 = 360  
VSYNCYSTART2 = 266  
VSYNCXSTOP2 = 360  
VSYNCYSTOP2 = 269  
FBITSET = 266  
FBITCLR = 4  
VBITCLR1 = 20  
VBITSET2 = 264  
VBITCLR2 = 283  
†
§
Assumes VCT2P bit in VPCTL is set to 1 (active-low output). VSYNC output when VCTL2S bit in VDCTL is set to 00, VBLNK  
output when VCTL2S bit is set 01.  
If DVEN bit in VDCTL is set to 1; otherwise, blanking value is output  
4-38  
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Display Timing Examples  
4.9.2 Interlaced Raw Display Example  
This section shows an example of raw display output for the same 704 × 408  
interlaced image.  
The horizontal output timing is shown in Figure 4–35. This diagram assumes  
that there is a two VCLK pipeline delay between the internal counter changing  
and the output on external pins. The actual delay can be longer or shorter as  
long as it is consistent within any display mode. The active line is 720-pixels  
wide. Figure 4–35 shows the 704-pixel image window centered in the screen  
that results in an IMGHOFFx of 8 pixels.  
The HBLNK and HSYNC signals are shown as they would be output for active-  
low operation. Note that only one of the two signals is actually available exter-  
nally. The HBLNK inactive edge occurs on sample 0.  
The IPCOUNT operation follows the description in section 4.1.2. IPCOUNT  
resets to 0 at the first displayed pixel (FPCOUNT = IMGHOFFx) and stops  
counting at the last displayed pixel (IPCOUNT = IMGHSIZEx). Both the  
IPCOUNT and FPCOUNT counters increment on every third VCLKIN rising  
edge, as programmed by the INCPIX bits in VDTHRLD with a value of 3.  
VDOUT shows the output data and switching between Default Data, and FIFO  
Data. Three values are output sequentially on VDOUT for each pixel count.  
Note that the default value is output during both the blanking and nondisplay  
image active video regions.  
SPRU629  
Video Display Port  
4-39  
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Figure 4–35. Raw Interlaced Display Horizontal Timing Example  
VCLKIN  
414  
2112  
One Line  
Next Line  
720 721  
703 703  
720 721  
703 703  
735 736  
703 703  
799 800  
703 703  
857  
0
1
7
8
0
9
1
711  
703  
712  
703  
719  
703  
FPCOUNT  
IPCOUNT  
703 703  
703  
703  
†
†
VCTL1 (HBLNK)  
VCTL1 (HSYNC)  
§
§
VCLKOUT  
Display Image  
Blanking  
Active Video  
VDOUT[19–0] §  
n – 1  
n
n + 1  
FLCOUNT  
FRMWIDTH = 858  
HBLNKSTART = 720  
HBLNKSTOP = 0  
IMGHOFF1 = 8  
IMGHSIZE1 = 704  
IMGHOFF2 = 8  
IMGHSIZE2 = 704  
HSYNCSTART = 736  
HSYNCSTOP = 800  
INCPIX = 3  
†
§
Assumes VCT1P bit in VPCTL is set to 1 (active-low output). HSYNC output when VCTL1S bit in VDCTL is set to 00,  
HBLNK output when VCTL1S bit is set 01.  
Diagram assumes a two VCLK pipeline delay between internal counters and output signals.  
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Display Timing Examples  
The vertical output timing for raw mode is shown in Figure 4–36. This example  
outputs the same 480-line window. Note that the raw display mode is typically  
noninterlaced for output to a monitor. This example shows the more complex  
interlaced case. The active field 1 is 242.5-lines high and active field 2 is  
242.5-lines high. This example shows the 480-line image window centered in  
the screen. This results in an IMGVOFF1 of 2 lines and an IMGVOFF2 of  
3 lines and also results in a nondata half-line at the end of field 1 and at the  
beginning of field 2 due to their noninteger line lengths.  
The VBLNK and VSYNC signals are shown as they would be output for active-  
low operation. Note that only one of the two signals is actually available exter-  
nally. The VBLNK and VSYNC edges for field 1 occur at the end of an active  
line so their XSTART/XSTOP values are set to 720 (start of blanking). For  
field 2, VBLNK and VSYNC edges occur during the middle of the active  
horizontal line so their XSTART/XSTOP values are set to 360.  
The FLD output is setup to transition at the start of each analog field (start of  
vertical blanking). There is no EAV[F] bit in raw mode, so FLD1YSTRT is set  
to 1, FLD2YSTART is set to 263, FBITCLR and FBITSET are ignored. Note  
that FLD2XSTRT is 360 so that the field indicator output changes halfway  
through the line.  
The active horizontal output column shows the output data during the active  
portion of the horizontal line. Note that in raw mode there is no blanking data  
value so the default value is output for the active portion of all nonimage  
window lines.  
SPRU629  
Video Display Port  
4-41  
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Display Timing Examples  
Figure 4–36. Raw Interlaced Display Vertical Timing Example  
Active  
Horizontal  
Output  
FLCOUNT  
ILCOUNT  
525  
1
2
3
4
5
6
240  
240  
240  
240  
240  
240  
240  
Default Value  
Default Value  
Default Value  
Default Value  
Default Value  
Default Value  
Default Value  
Field 1 Blanking  
19  
20  
21  
22  
23  
240  
240  
240  
240  
1
Default Value  
Default Value  
Default Value  
Default Value  
FIFO Data  
Field 1 Active  
Field 1 Image  
2
FIFO Data  
239  
240  
240  
240  
240  
240  
240  
240  
240  
FIFO Data  
FIFO Data  
262  
263  
264  
265  
266  
267  
268  
269  
Default Value  
Default Value  
Default Value  
Default Value  
Default Value  
Default Value  
Default Value  
Field 2 Blanking  
282  
283  
284  
285  
286  
240  
240  
240  
240  
1
Default Value  
Default Value  
Default Value  
Default Value  
FIFO Data  
Field 2 Active  
Field 2 Image  
2
FIFO Data  
524  
525  
1
239  
240  
240  
240  
FIFO Data  
FIFO Data  
Default Value  
Default Value  
IMGVOFF1 = 2  
VBLNKXSTART1 = 720  
VBLNKYSTART1 = 1  
VBLNKXSTOP1 = 720  
VBLNKYSTOP1 = 21  
VBLNKXSTART2 = 360  
VBLNKYSTART2 = 263  
VBLNKXSTOP2 = 360  
VBLNKYSTOP2 = 283  
VSYNCXSTART1 = 720  
FLD1XSTART = 720  
FLD1YSTART = 1  
IMGVSIZE1 = 240  
IMGVOFF2 = 3  
VSYNCYSTART1 = 4  
VSYNCXSTOP1 = 720  
VSYNCYSTOP1 = 7  
FLD2XSTART = 360  
FLD2YSTART = 263  
IMGVSIZE2 = 240  
FRMHEIGHT = 525  
VBITSET1 = n/a  
VBITCLR1 = n/a  
VBITSET2 = n/a  
VBITCLR2 = n/a  
VSYNCXSTART2 = 360  
VSYNCYSTART2 = 266  
VSYNCXSTOP2 = 360  
VSYNCYSTOP2 = 269  
FBITSET = n/a  
FBITCLR = n/a  
†
Assumes VCT2P bit in VPCTL is set to 1 (active-low output). VSYNC output when VCTL2S bit in VDCTL is set to 00, VBLNK  
output when VCTL2S bit is set 01.  
4-42  
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SPRU629  
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Display Timing Examples  
4.9.3 Y/C Progressive Display Example  
This section shows an example of progressive display operation. The output  
format follows SMPTE 296M-2001 specifications for a 1280 × 720/60 system.  
The example is for a 1264 × 716 progressive output image.  
The horizontal output timing is shown in Figure 4–37. This diagram assumes  
that there is a two VCLK pipeline delay between the internal counter changing  
and the output on external pins. The actual delay can be longer or shorter as  
long as it is consistent within any display mode. The SMPTE 296M 60-Hz  
active line is 1650-pixels wide. Figure 4–37 shows the 1264-pixel image  
window centered in the screen that results in an IMGHOFFx of 8 pixels.  
The HBLNK and HSYNC signals are shown as they would be output for active-  
low operation. Note that only one of the two signals is actually available exter-  
nally. The HBLNK inactive edge occurs either on sample 1646 coincident with  
the start of SAV or on sample 0 (after SAV) if the HBDLA bit is set. For true  
SMPTE 296M operation, neither HBLNK nor HSYNC would be used.  
The IPCOUNT operation follows the description in section 4.1.2. IPCOUNT  
resets to 0 at the first displayed pixel (FPCOUNT = IMGHOFFx) and stops  
counting at the last displayed pixel (IPCOUNT = IMGHSIZEx). The operation  
during nondisplay time is not a requirement, it could continue counting until the  
next FPCOUNT = IMGHOFFx point or it could reset immediately after  
IMGHSIZEx or when FPCOUNT is reset.  
VDOUT shows the output data and switching between EAV, Blanking Data,  
SAV, Default Data, and FIFO Data. It is assumed that the DVEN bit in VDCTL  
is set to enable the default output.  
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Video Display Port  
4-43  
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Figure 4–37. Y/C Progressive Display Horizontal Timing Example  
VCLKIN  
4
4
362  
1280  
One Line  
Next Line  
FPCOUNT  
IPCOUNT  
†
VCTL1 (HBLNK)  
VCTL1 (HSYNC)  
§
§
‡
†
VCLKOUT  
Display Image  
Active Video  
Blanking  
VDOUT[9–0] §  
VDOUT[19–0] §  
EAV Blanking Data  
SAV  
EAV  
n + 1  
n – 1  
n
FLCOUNT  
FRMWIDTH = 1650  
HBLNKSTART = 1280  
HBLNKSTOP = 1646  
IMGHOFF1 = 8  
HSYNCSTART = 1350  
HSYNCSTOP = 1430  
IMGHSIZE1 = 1264  
IMGHOFF2 = n/a  
IMGHSIZE2 = n/a  
†
Assumes VCT1P bit in VPCTL is set to 1 (active-low output). HSYNC output when VCTL1S bit in VDCTL is set to 00,  
HBLNK output when VCTL1S bit is set 01.  
‡
§
HBLNK operation when HBDLA bit in VDHBLNK is set to 1.  
Diagram assumes a two VCLK pipeline delay between internal counters and output signals.  
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Display Timing Examples  
The vertical output timing is shown in Figure 4–38. SMPTE 296M has a single  
active field 1 that is 720-lines high. This example shows the 716-line image  
window with an IMGVOFFn of 3 lines and also results in a nondata line at the  
end of the field.  
The VBLNK and VSYNC signals are shown as they would be output for active-  
low operation. Note that only one of the two signals is actually available exter-  
nally. The VBLNK and VSYNC edges occur at the end of an active line so their  
XSTART/XSTOP values are set to 1280 (start of blanking). The field 2 vertical  
timing start and stop registers are programmed to a value greater than 750.  
Since this value is never reached by FLCOUNT, no extra VBLNK or VSYNC  
transitions occur. For true SMPTE 296M operation, neither VBLNK nor  
VSYNC would be used.  
The FLD output is setup to transition low at the start of each frame. Since the  
FLD2YSTART value is never reached by FLCOUNT, the FLD output remains  
always low.  
The ILCOUNT operation follows the description in section 4.1.2. ILCOUNT  
resets to 1 at the first displayed line (FLCOUNT = VBLNKSTOPx + IMGVOFFn)  
and stops counting at the last displayed pixel (IPCOUNT = IMGVSIZEx). The  
operation during nondisplay time is not a requirement, it could continue count-  
ing until the next FLCOUNT = VBLNKSTOPx + IMGVOFFn point or it could  
reset immediately after IMGVSIZEx or when FLCOUNT is reset.  
The active horizontal output column shows the output data during the active  
portion of the horizontal line. It is assumed that the DVEN bit in VDCTL is set  
to enable the default output.  
SPRU629  
Video Display Port  
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Display Timing Examples  
Figure 4–38. Y/C Progressive Display Vertical Timing Example  
Active  
Horizontal  
Output  
EAV  
ILCOUNT V F  
FLCOUNT  
750  
1
2
3
4
5
6
716  
716  
716  
716  
716  
716  
716  
1 0  
1 0  
1 0  
1 0  
1 0  
1 0  
1 0  
Blanking Value  
Blanking Value  
Blanking Value  
Blanking Value  
Blanking Value  
Blanking Value  
Blanking Value  
Field 1 Blanking  
25  
26  
27  
28  
29  
716  
716  
716  
716  
1
1 0  
0 0  
0 0  
0 0  
0 0  
0 0  
Blanking Value  
§
§
§
Default Value  
Default Value  
Default Value  
FIFO Data  
Field 1 Active  
Field 1 Image  
2
FIFO Data  
715  
716  
716  
716  
716  
716  
716  
716  
716  
716  
0 0  
0 0  
0 0  
1 0  
1 0  
1 0  
1 0  
1 0  
1 0  
1 0  
FIFO Data  
FIFO Data  
Default Value  
Blanking Value  
Blanking Value  
Blanking Value  
Blanking Value  
Blanking Value  
Blanking Value  
Blanking Value  
744  
745  
746  
747  
748  
749  
750  
1
§
Field 1 Blanking  
IMGVOFF1 = 3  
VBLNKXSTART1 = 1280  
VBLNKYSTART1 = 746  
VBLNKXSTOP1 = 1280  
VBLNKYSTOP1 = 26  
VSYNCXSTART1 = 1280  
VSYNCYSTART1 = 1  
VSYNCXSTOP1 = 1280  
VSYNCYSTOP1 = 6  
FLD1XSTART = n/a  
IMGVSIZE1 = 716  
IMGVOFF2 = n/a  
IMGVSIZE2 = n/a  
FRMHEIGHT = 750  
VBITSET1 = 746  
VBITCLR1 = 26  
VBITSET2 = n/a  
VBITCLR2 = n/a  
FLD1YSTART = 1  
FLD2XSTART = n/a  
FLD2YSTART = > 750  
VBLNKXSTART2 = n/a  
VBLNKYSTART2 = > 750  
VBLNKXSTOP2 = n/a  
VBLNKYSTOP2 = > 750  
VSYNCXSTART2 = n/a  
VSYNCYSTART2 = > 750  
VSYNCXSTOP2 = n/a  
VSYNCYSTOP2 = > 750  
FBITSET = 1  
FBITCLR = > 750  
†
§
Assumes VCT2P bit in VPCTL is set to 1 (active-low output). VSYNC output when VCTL2S bit in VDCTL is set to 00, VBLNK  
output when VCTL2S bit is set 01.  
If DVEN bit in VDCTL is set to 1; otherwise, blanking value is output  
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Displaying Video in BT.656 or Y/C Mode  
4.10 Displaying Video in BT.656 or Y/C Mode  
In order to display video in the BT.656 or Y/C format, the following steps are  
needed:  
1) Set the frame size in VDFRMSZ. Set the number of lines per frame  
(FRMHIGHT) and the number of pixels per line (FRMWIDTH).  
2) Set the horizontal blanking in VDHBLNK. Specify the frame pixel counter  
value where horizontal blanking starts (HBLNKSTART) and pixel location  
where horizontal blanking stops (HBLNKSTOP).  
3) Set the V bit timing for field 1 in VDVBIT1. Specify the line where the V bit  
is set (VBITSET1) and the line where the V bit is cleared (VBITCLR1).  
4) If external VBLNK signal is needed, set the VBLNK start for field 1 in  
VDVBLKS1. Specify the frame line (VBLNKYSTART1) and frame pixel  
counter (VBLNKXSTART1) values for the pixel where VBLNK goes active  
for field 1. Set the VBLNK end for field 1 in VDVBLKE1. Specify the frame  
line (VBLNKYSTOP1) and frame pixel counter (VBLNKXSTOP1) values  
for the pixel where VBLNK goes inactive for field 1.  
5) Set the V bit timing for field 2 in VDVBIT2. Specify the line where the V bit  
is set (VBITSET2) and the line where the V bit is cleared (VBITCLR2).  
6) If external VBLNK signal is needed, set the VBLNK start for field 2 in  
VDVBLKS2. Specify the frame line (VBLNKYSTART2) and frame pixel  
counter (VBLNKXSTART2) values for the pixel where VBLNK goes active  
for field 2. Set the VBLNK end for field 2 in VDVBLKE2. Specify the frame  
line (VBLNKYSTOP2) and frame pixel counter (VBLNKXSTOP2) values  
for the pixel where VBLNK goes inactive for field 2.  
7) Set VDIMGSZn. Adjust the displayed image size by setting the HSIZE and  
VSIZE bits.  
8) Set VDIMOFF. Adjust the displayed image offset within the active video  
area (by setting HOFFSET and VOFFSET).  
9) Set the F bit timing in VDFBIT. Specify the line where the F bit is cleared  
(FBITCLR) and the line where the F bit is set (FBITSET).  
10) If external FLD output is required, set the video display field 1 timing.  
Specify the line and pixel where FLD goes inactive (VDFLDT1). Set the  
video display field 2 timing. Specify the line and pixel where FLD goes  
active (VDFLDT2).  
11) Set VDCLIP. Default values for video clipping are 16 for the lower clipping,  
235 for the higher clipping of the Y values, and 240 for the higher clipping  
of the Cb and Cr values.  
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Displaying Video in BT.656 or Y/C Mode  
12) Configure a DMA to move data from the Y buffer in the DSP memory to  
YDSTA (memory-mapped Y display FIFO). The transfers should be  
triggered by the YEVT.  
13) Configure a DMA to move data from the Cb buffer in the DSP memory to  
CBDST (memory-mapped Cb display FIFO). The transfers should be  
triggered by the CbEVT. The size of the transfers should be set to ½ the  
Y transfer size.  
14) Configure a DMA to move data from the Cr buffer in the DSP memory to  
CRDST (memory-mapped Cr display FIFO). The transfers should be  
triggered by the CrEVT. The size of the transfers should be set to ½ the  
Y transfer size.  
15) Set DISPEVT1 and DISPEVT2 bits in VDDISPEVT. Event count is total  
doublewords per field divided by total doublewords per Y DMA.  
16) Write to VPIE to enable underrun (DUND) and display complete (DCMP)  
interrupts, if desired.  
17) Write to VDTHRLD to set the display FIFO threshold (VDTHRLD bits).  
18) Write to VDCTL to:  
- Set display mode (DMODE = 00x for BT.656 output, 10x for Y/C  
output).  
- Set desired field/frame operation (CON, FRAME, DF1, DF2 bits).  
- Select control outputs (VCTL1S, VCTL2S, VCTL3S bits) or external  
sync inputs (HXS, VXS, FXS bits).  
- Enable scaling (SCALE and RESMPL bits), if desired and in 8-bit  
mode.  
- Select 10-bit unpacking mode (DPK bit), if appropriate.  
- Set VDEN bit to enable the display.  
19) Wait for 2 or more frame times, to allow the display counters and control  
signals to become properly synchronized.  
20) Write to VDCTL to clear the BLKDIS bit.  
21) Display is enabled at the start of the first frame after BLKDIS = 0 and  
begins with the first selected field. DMA events are generated as triggered  
by VDTHRLD and the DEVTCT counter. When a selected field has been  
displayed (FLCOUNT = FRMHEIGHT and FPCOUNT = FRMWIDTH),  
the appropriate F1D, F2D, or FRMD bits are set and cause the DCMP bit  
in VPIS to be set. This generates a DSP interrupt, if the DCMP bit is  
enabled in VPIE.  
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Displaying Video in Raw Data Mode  
22) If continuous display is enabled, the video port begins displaying again at  
the start of the next field or frame. If noncontinuous field 1 and field 2 or  
frame display is enabled, the next field or frame is displayed, during which  
the DSP must clear the appropriate completion status bit or a DCNA  
interrupt occurs and incorrect data may be output.  
4.11 Displaying Video in Raw Data Mode  
In order to display video in the raw data mode, the following steps are needed:  
1) Set the frame size in VDFRMSZ. Set the number of lines per frame  
(FRMHIGHT) and the number of pixels per line (FRMWIDTH).  
2) Set the horizontal blanking in VDHBLNK. Specify the frame pixel counter  
value where horizontal blanking starts (HBLNKSTART) and pixel location  
where horizontal blanking stops (HBLNKSTOP).  
3) Set the vertical blanking start for field 1 in VDVBLKS1. Specify the frame  
line (VBLNKYSTART1) and frame pixel counter (VBLNKXSTART1) values  
for the pixel where vertical blanking starts for field 1.  
4) Set the vertical blanking end for field 1 in VDVBLKE1. Specify the frame  
line (VBLNKYSTOP1) and frame pixel counter (VBLNKXSTOP1) values  
for the pixel where vertical blanking ends for field 1.  
5) Set the vertical blanking start for field 2 in VDVBLKS2. Specify the frame  
line (VBLNKYSTART2) and frame pixel counter (VBLNKXSTART2) values  
for the pixel where vertical blanking starts for field 2.  
6) Set the vertical blanking end for field 2 in VDVBLKE2. Specify the frame  
line (VBLNKYSTOP2) and frame pixel counter (VBLNKXSTOP2) values  
for the pixel where vertical blanking ends for field 2.  
7) Set the vertical synchronization start for field 1 in VDVSYNS1. Specify the  
frame line (VSYNCYSTART1) and frame pixel counter (VSYNCXSTART1)  
values for the pixel where vertical synchronization starts for field 1.  
8) Set the vertical synchronization end for field 1 in VDVSYNE1. Specify the  
frame line (VSYNCYSTOP1) and frame pixel counter (VSYNCXSTOP1)  
values for the pixel where vertical synchronization ends for field 1.  
9) Set the vertical synchronization start for field 2 in VDVSYNS2. Specify the  
frame line (VSYNCYSTART2) and frame pixel counter (VSYNCXSTART2)  
values for the pixel where vertical synchronization starts for field 2.  
10) Set the vertical synchronization end for field 2 in VDVSYNE2. Specify the  
frame line (VSYNCYSTOP2) and frame pixel counter (VSYNCXSTOP2)  
values for the pixel where vertical synchronization ends for field 2.  
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Displaying Video in Raw Data Mode  
11) Set the horizontal synchronization in VDHSYNC. Specify the frame pixel  
counter value for a pixel where HSYNC gets asserted (HSYNCYSTART)  
and width of the HSYNC pulse (HSYNCSTOP) in frame pixel clocks.  
12) Set the video display field 1 timing. Specify the first line and pixel of field 1  
in VDFLDT1.  
13) Set the video display field 2 timing. Specify the first line and pixel of field 2  
in VDFLDT2.  
14) Configure a DMA to move data from table in the DSP memory to YDSTA  
(memory-mapped display FIFO). The transfers should be triggered by the  
YEVT.  
15) Set DISPEVT1 and DISPEVT2 bits in VDDISPEVT. Event count is total  
doublewords per field divided by total doublewords per Y DMA.  
16) Write to VPIE to enable underrun (DUND) and display complete (DCMP)  
interrupts, if desired.  
17) Write to VDTHRLD to set the display FIFO threshold (VDTHRLD bits) and  
the FPCOUNT increment rate (INCPIX bit).  
18) Write to VDCTL to:  
- Set display mode (DMODE =01x for 8/10-bit output, 11x for 16/20 bit  
output).  
- Set desired field/frame operation (CON, FRAME, DF1, DF2 bits).  
- Select control outputs (VCTL1S, VCTL2S, VCTL3S bits) or external  
sync inputs (HXS, VXS, FXS bits).  
- Select 10-bit unpacking mode (DPK bit), if appropriate.  
- Set VDEN bit to enable the display.  
19) Wait for 2 or more frame times, to allow the display counters and control  
signals to become properly synchronized  
20) Write to VDCTL to clear the BLKDIS bit.  
21) Display is enabled at the start of the first frame after BLKDIS = 0 and  
begins with the first selected field. DMA events are generated as triggered  
by VDTHRLD and the DEVTCT counter. When a selected field has been  
displayed (FLCOUNT = FRMHEIGHT and FPCOUNT = FRMWIDTH),  
the appropriate F1D, F2D, or FRMD bits are set and cause the DCMP bit  
in VPIS to be set. This generates a DSP interrupt, if the DCMP bit is  
enabled in VPIE.  
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Displaying Video in Raw Data Mode  
22) If continuous display is enabled, the video port begins displaying again at  
the start of the next field or frame. If noncontinuous field 1 and field 2 or  
frame display is enabled, the next field or frame is displayed, during which  
the DSP must clear the appropriate completion status bit or a DCNA  
interrupt occurs and incorrect data may be output.  
4.11.1 Handling Underrun Condition of the Display FIFO  
A FIFO underrun occurs when the display FIFO is empty during an active  
display line because a pending DMA request failed to load the data in time. In  
case of a FIFO underrun condition, the DUND bit in VPIS is set. This condition  
initiates an interrupt to the DSP, if the underrun interrupt is enabled (the DUND  
bit in VPIE is set).  
Because video display is typically a continuous real-time output, data output  
is not halted when a FIFO underrun occurs. (To output a blanking of default  
value is just as catastrophic to a display as outputting an old data value.)  
Instead, the FIFO read pointer continues to advance and (old) data continues  
to be output from the FIFO. This means that if the pending DMA is only slightly  
late, the data transfer has a chance to catch the FIFO back up to the read  
pointer and correct data output resumes. If the pending DMA does not  
complete service within a threshold’s worth of output data, then the DMA  
request sequence is broken and the remainder of the display field is corrupted.  
The underrun interrupt routine should set the BLKDIS bit in VDCTL and it  
should reconfigure the DMA channel settings. Setting the BLKDIS bit flushes  
thechanneldisplayFIFOandpreventschannelDMAeventsfromreachingthe  
DMA controller. The DMA must be reconfigured correctly for the next frame  
display since the current frame transfer failed. The frame line and frame pixel  
counters continue counting and, from a pin standpoint, the video display module  
appears to continue to function normally (SAV/EAV codes are generated in the  
BT.656 or Y/C mode and the default data value is sent out). The BLKDIS bit  
should then be cleared to reenable DMA events. Clearing the BLKDIS bit does  
not enable DMA events during the frame where the bit is cleared. Clearing this  
bit to zero enables DMA events in the frame that follows the frame where the  
bit is cleared.  
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Video Display Registers  
4.12 Video Display Registers  
The registers for controlling the video display mode of operation are listed in  
Table 4–5. See the device-specific datasheet for the memory address of these  
registers.  
Table 4–5. Video Display Control Registers  
Acronym  
Register Name  
Section  
VDSTAT  
Video Display Status Register  
4.12.1  
VDCTL  
Video Display Control Register  
4.12.2  
VDFRMSZ  
VDHBLNK  
VDVBLKS1  
VDVBLKE1  
VDVBLKS2  
VDVBLKE2  
VDIMGOFF1  
VDIMGSZ1  
VDIMGOFF2  
VDIMGSZ2  
VDFLDT1  
Video Display Frame Size Register  
4.12.3  
Video Display Horizontal Blanking Register  
Video Display Field 1 Vertical Blanking Start Register  
Video Display Field 1 Vertical Blanking End Register  
Video Display Field 2 Vertical Blanking Start Register  
Video Display Field 2 Vertical Blanking End Register  
Video Display Field 1 Image Offset Register  
Video Display Field 1 Image Size Register  
Video Display Field 2 Image Offset Register  
Video Display Field 2 Image Size Register  
Video Display Field 1 Timing Register  
4.12.4  
4.12.5  
4.12.6  
4.12.7  
4.12.8  
4.12.9  
4.12.10  
4.12.11  
4.12.12  
4.12.13  
4.12.14  
4.12.15  
4.12.16  
4.12.17  
4.12.18  
4.12.19  
4.12.20  
4.12.21  
4.12.22  
4.12.23  
VDFLDT2  
Video Display Field 2 Timing Register  
VDTHRLD  
VDHSYNC  
VDVSYNS1  
VDVSYNE1  
VDVSYNS2  
VDVSYNE2  
VDRELOAD  
VDDISPEVT  
VDCLIP  
Video Display Threshold Register  
Video Display Horizontal Synchronization Register  
Video Display Field 1 Vertical Synchronization Start Register  
Video Display Field 1 Vertical Synchronization End Register  
Video Display Field 2 Vertical Synchronization Start Register  
Video Display Field 2 Vertical Synchronization End Register  
Video Display Counter Reload Register  
Video Display Display Event Register  
Video Display Clipping Register  
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Video Display Registers  
Table 4–5. Video Display Control Registers (Continued)  
Acronym  
Register Name  
Section  
VDDEFVAL  
Video Display Default Display Value Register  
4.12.24  
VDVINT  
VDFBIT  
VDVBIT1  
VDVBIT2  
Video Display Vertical Interrupt Register  
Video Display Field Bit Register  
4.12.25  
4.12.26  
4.12.27  
4.12.28  
Video Display Field 1 Vertical Blanking Bit Register  
Video Display Field 2 Vertical Blanking Bit Register  
4.12.1 Video Display Status Register (VDSTAT)  
Thevideodisplaystatusregister(VDSTAT)indicatesthecurrentdisplaystatus  
of the video port. The VDSTAT is shown in Figure 4–39 and described in  
Table 4–6.  
The VDXPOS and VDYPOS bits track the coordinates of the most-recently  
displayedpixel. TheF1D, F2D, andFRMDbitsindicatethecompletionoffields  
or frames and may need to be cleared by the DSP to prevent a DCNA interrupt  
from being generated, depending on the selected frame operation. The F1D,  
F2D, and FRMD bits are set when the final pixel from the appropriate field has  
been sent to the output pad.  
Figure 4–39. Video Display Status Register (VDSTAT)  
31  
30  
29  
28  
27  
16  
0
—
FRMD  
F2D  
F1D  
VDYPOS  
R-0  
R-0 R/WC-0 R/WC-0 R/WC-0  
15  
14  
13  
VBLNK VDFLD  
R-0 R-0  
12  
11  
Reserved  
R-0  
VDXPOS  
R-0  
Legend: R = Read only; WC = Write 1 to clear, write of 0 has no effect; -n = value after reset  
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Video Display Registers  
Table 4–6. Video Display Status Register (VDSTAT) Field Descriptions  
†
†
Bit  
field  
symval  
Value Description  
31  
Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
30  
29  
28  
FRMD  
Frame displayed bit. Write 1 to clear the bit, a write of 0 has  
no effect.  
NONE  
0
1
Complete frame has not been displayed.  
Complete frame has been displayed.  
DISPLAYED  
F2D  
F1D  
Field 2 displayed bit. Write 1 to clear the bit, a write of 0 has  
no effect.  
NONE  
0
1
Field 2 has not been displayed.  
Field 2 has been displayed.  
DISPLAYED  
Field 1 displayed bit. Write 1 to clear the bit, a write of 0 has  
no effect.  
NONE  
0
1
Field 1 has not been displayed.  
Field 1 has been displayed.  
DISPLAYED  
OF(value)  
27–16 VDYPOS  
0–FFFh Current frame line counter (FLCOUNT) value. Index of the  
current line in the current field being displayed by the  
module.  
15–14 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
13  
VBLNK  
Vertical blanking bit.  
EMPTY  
0
1
Video display is not in a vertical-blanking interval.  
Video display is in a vertical-blanking interval.  
NOTEMPTY  
12  
VDFLD  
VDFLD bit indicates which field is currently being displayed.  
The VDFLD bit is updated at the start of the vertical blanking  
interval of the next field.  
FIELD1ACT  
FIELD2ACT  
OF(value)  
0
1
Field 1 is active.  
Field 2 is active.  
11–0 VDXPOS  
0–FFFh Current frame pixel counter (FPCOUNT) value. Index of the  
most recently output pixel.  
†
For CSL implementation, use the notation VD_VDSTAT_field_symval  
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Video Display Registers  
4.12.2 Video Display Control Register (VDCTL)  
The video display is controlled by the video display control register (VDCTL).  
The VDCTL is shown in Figure 4–40 and described in Table 4–7.  
Figure 4–40. Video Display Control Register (VDCTL)  
31  
30  
29  
Reserved  
R-0  
28  
27  
24  
16  
RSTCH  
R/WS-0  
BLKDIS  
R/W-1  
PVPSYN  
R/W-0  
Reserved  
R-0  
23  
22  
21  
20  
19  
18 17  
FXS  
VXS  
HXS  
VCTL3S  
R/W-0  
VCTL2S  
R/W-0  
VCTL1S  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
15  
14  
13  
12  
11  
10  
9
8
VDEN  
R/W-0  
DPK  
RGBX  
R/W-0  
RSYNC  
R/W-0  
DVEN  
R/W-0  
RESMPL  
R/W-0  
Reserved  
R-0  
SCALE  
R/W-0  
R/W-0  
7
6
5
4
3
2
0
CON  
R/W-0  
FRAME  
R/W-0  
DF2  
DF1  
Reserved  
R-0  
DMODE  
R/W-0  
R/W-0  
R/W-0  
Legend: R = Read only; R/W = Read/Write; WS = Write 1 to reset, write of 0 has no effect; -n = value after reset  
Table 4–7. Video Display Control Register (VDCTL) Field Descriptions  
Description  
†
†
BT.656 and Y/C Mode  
Raw Data Mode  
Bit  
field  
symval  
Value  
31  
RSTCH  
Reset channel bit. Write 1 to reset the bit, a write of 0 has no effect.  
No effect.  
NONE  
0
1
RESET  
Resets the video display module and sets its registers to their  
initial values. Also clears the VDEN bit. The video display module  
automatically clears RSTCH after software reset is completed.  
†
‡
For CSL implementation, use the notation VP_VDCTL_field_symval  
For complete encoding of these bits, see Table 4–4.  
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Video Display Registers  
Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued)  
Description  
†
†
BT.656 and Y/C Mode  
Raw Data Mode  
Bit  
field  
symval  
Value  
30  
BLKDIS  
Block display events bit. BLKDIS functions as a display FIFO reset  
without affecting the current programmable register values.  
The video display module continues to function normally, the  
counters count, control outputs are generated, EAV/SAV codes are  
generated for BT.656 and Y/C modes, and default or blanking data  
is output during active display time. No data is moved to the  
display FIFOs because no events occur. The F1D, F2D, and  
FRMD bits in VDSTAT are still set when fields or frames are  
complete.  
CLEAR  
0
Clearing BLKDIS does not enable DMA events during the field in  
which the bit is cleared. DMA events are enabled at the start of the  
next frame after the one in which the bit is cleared. This allows the  
DMA to always be synced to the proper field.  
BLOCK  
1
0
Blocks DMA events and flushes the display FIFOs.  
29  
28  
Reserved  
PVPSYN  
–
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
Previous video port synchronization enable bit.  
DISABLE  
ENABLE  
0
1
Output timing is locked to preceding video port (VP2 is locked to  
VP1 or VP1 is locked to VP0, see Figure 4–7 on page 4-8).  
27–24 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
23  
FXS  
Field external synchronization enable bit.  
VCTL3 is an output.  
OUTPUT  
FSINPUT  
0
1
VCTL3 is an external field sync input.  
Vertical external synchronization enable bit.  
VCTL2 is an output.  
22  
VXS  
OUTPUT  
VSINPUT  
0
1
VCTL2 is an external vertical sync input.  
†
‡
For CSL implementation, use the notation VP_VDCTL_field_symval  
For complete encoding of these bits, see Table 4–4.  
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Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued)  
Description  
Raw Data Mode  
†
†
BT.656 and Y/C Mode  
Bit  
field  
symval  
Value  
21  
HXS  
Horizontal external synchronization enable bit.  
VCTL1 is an output.  
VCTL1 is an external horizontal sync input.  
VCTL3 output select bit.  
Output CBLNK  
OUTPUT  
HSINPUT  
0
1
20  
VCTL3S  
CBLNK  
FLD  
0
1
Output FLD  
19–18 VCTL2S  
VCTL2 output select bit.  
Output VSYNC  
VYSYNC  
VBLNK  
CSYNC  
FLD  
0
1h  
2h  
3h  
Output VBLNK  
Output CSYNC  
Output FLD  
17–16 VCTL1S  
VCTL1 output select bit.  
Output HSYNC  
HYSYNC  
HBLNK  
AVID  
0
1h  
2h  
3h  
Output HBLNK  
Output AVID  
FLD  
Output FLD  
15  
14  
VDEN  
DPK  
Video display enable bit. Other bits in VDCTL (except RSTCH and  
BLKDIS bits) may only be changed when VDEN = 0.  
DISABLE  
ENABLE  
0
1
Video display is disabled.  
Video display is enabled.  
10-bit packing format select bit.  
Normal 10-bit unpacking  
Dense 10-bit unpacking  
N10UNPK  
D10UNPK  
0
1
†
‡
For CSL implementation, use the notation VP_VDCTL_field_symval  
For complete encoding of these bits, see Table 4–4.  
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Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued)  
Description  
†
†
BT.656 and Y/C Mode  
Raw Data Mode  
Bit  
field  
symval  
Value  
13  
RGBX  
RGB extract enable bit.  
DISABLE  
ENABLE  
0
1
Not used.  
Not used.  
Perform ¾ FIFO unpacking.  
12  
11  
10  
RSYNC  
Second, synchronized raw data channel enable bit.  
DISABLE  
ENABLE  
0
1
Not used.  
Second, synchronized raw data  
channel is disabled.  
Not used.  
Second, synchronized raw data  
channel is enabled.  
DVEN  
Default value enable bit.  
BLANKING  
DV  
0
1
Blanking value is output during  
non-sourced active pixels.  
Not used.  
Not used.  
Default value is output during  
non-sourced active pixels.  
RESMPL  
Chroma resampling enable bit.  
DISABLE  
ENABLE  
0
1
Chroma resampling is disabled. Not used.  
Chroma is horizontally  
resampled from 4:2:0  
interspersed to 4:2:2 co-sited  
before output.  
Not used.  
9
8
Reserved  
SCALE  
–
0
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
Scaling select bit.  
NONE  
X2  
0
1
No scaling  
Not used.  
Not used.  
2× scaling  
‡
7
CON  
Continuous display enable bit.  
Continuous display is disabled.  
Continuous display is enabled.  
DISABLE  
ENABLE  
0
1
†
‡
For CSL implementation, use the notation VP_VDCTL_field_symval  
For complete encoding of these bits, see Table 4–4.  
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Table 4–7. Video Display Control Register (VDCTL) Field Descriptions (Continued)  
Description  
Raw Data Mode  
†
†
BT.656 and Y/C Mode  
Bit  
field  
symval  
Value  
‡
6
FRAME  
Display frame bit.  
NONE  
0
1
Do not display frame.  
Display frame.  
FRMDIS  
‡
5
4
DF2  
Display field 2 bit.  
Do not display field 2.  
Display field 2.  
NONE  
0
1
FLDDIS  
‡
DF1  
Display field 1 bit.  
Do not display field 1.  
Display field 1.  
NONE  
FLDDIS  
–
0
1
0
3
Reserved  
DMODE  
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
2–0  
Display mode select bit.  
BT656B  
BT656D  
RAWB  
RAWD  
YC16  
0
Enables 8-bit BT.656 mode.  
Enables 10-bit BT.656 mode.  
Enables 8-bit raw data mode.  
Enables 10-bit raw data mode.  
Enables 8-bit Y/C mode.  
1h  
2h  
3h  
4h  
5h  
6h  
7h  
YC20  
Enables 10-bit Y/C mode.  
Enables 16-bit raw data mode.  
Enables 20-bit raw data mode.  
RAW16  
RAW20  
†
‡
For CSL implementation, use the notation VP_VDCTL_field_symval  
For complete encoding of these bits, see Table 4–4.  
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4.12.3 Video Display Frame Size Register (VDFRMSZ)  
The video display frame size register (VDFRMSZ) sets the display channel  
frame size by setting the ending values for the frame line counter (FLCOUNT)  
and the frame pixel counter (FPCOUNT). The VDFRMSZ is shown in  
Figure 4–41 and described in Table 4–8.  
TheFPCOUNTstartsat0andcountstoFRMWIDTH–1beforerestarting. The  
FLCOUNT starts at 1 and counts to FRMHEIGHT before restarting.  
Figure 4–41. Video Display Frame Size Register (VDFRMSZ)  
31  
28 27  
16  
0
Reserved  
R-0  
FRMHEIGHT  
R/W-0  
15  
12 11  
Reserved  
R-0  
FRMWIDTH  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 4–8. Video Display Frame Size Register (VDFRMSZ) Field Descriptions  
†
†
Bit  
field  
symval  
Value  
Description  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
27–16 FRMHEIGHT OF(value)  
0–FFFh Defines the total number of lines per frame. The number is  
the ending value of the frame line counter (FLCOUNT).  
For BT.656 operation, the FRMHIGHT is set to 525  
(525/60 operation) or 625 (625/50 operation).  
15–12 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
11–0 FRMWIDTH  
OF(value)  
0–FFFh Defines the total number of pixels per line including blanking.  
The number is the frame pixel counter (FPCOUNT) ending  
value + 1.  
For BT.656 operation, the FRMWIDTH is typically 858 or  
864.  
†
For CSL implementation, use the notation VP_VDFRMSZ_field_symval  
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4.12.4 Video Display Horizontal Blanking Register (VDHBLNK)  
Thevideodisplayhorizontalblankingregister(VDHBLNK)controlsthedisplay  
horizontal blanking. The VDHBLNK is shown in Figure 4–42 and described in  
Table 4–9.  
Every time the frame pixel counter (FPCOUNT) is equal to HBLNKSTART,  
HBLNK is asserted. HBLNKSTART also determines where the EAV code is  
inserted in the BT.656 and Y/C output.  
Every time FPCOUNT = HBLNKSTOP, the HBLNK signal is deasserted (this  
is shown in Figure 4–5, page 4-6). In BT.656 and Y/C modes, HBLNKSTOP  
determines the SAV code insertion point and HBLNK deassertion point. The  
HBLNK inactive edge may optionally be delayed by 4 pixel clocks using the  
HBDLA bit.  
Figure 4–42. Video Display Horizontal Blanking Register (VDHBLNK)  
31  
28 27  
16  
0
Reserved  
R-0  
HBLNKSTOP  
R/W-0  
15  
14  
12 11  
HBDLA  
R/W-0  
Reserved  
R-0  
HBLNKSTART  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
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Table 4–9. Video Display Horizontal Blanking Register (VDHBLNK) Field Descriptions  
Description  
†
†
BT.656 and Y/C Mode  
Raw Data Mode  
Bit  
field  
symval  
Value  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0.  
A value written to this field has no effect.  
27–16 HBLNKSTOP  
OF(value)  
0–FFFh Location of SAV code and Ending pixel (FPCOUNT)  
HBLNK inactive edge  
within the line. HBLNK  
inactive edge may be  
optionally delayed by  
4 VCLKs.  
of blanking video area  
(HBLNK inactive) within  
the line.  
15  
HBDLA  
Horizontal blanking delay enable bit.  
NONE  
DELAY  
–
0
1
0
Horizontal blanking delay  
is disabled.  
Not used.  
HBLNK inactive edge is  
delayed by 4 VCLKs.  
Not used.  
14–12 Reserved  
Reserved. The reserved bit location is always read as 0.  
A value written to this field has no effect.  
11–0 HBLNKSTART OF(value)  
0–FFFh Location of EAV code and Starting pixel (FPCOUNT)  
HBLNK active edge within of blanking video area  
the line.  
(HBLNK active) within the  
line.  
†
For CSL implementation, use the notation VP_VDHBLNK_field_symval  
4.12.5 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)  
The video display field 1 vertical blanking start register (VDVBLKS1) controls  
the start of vertical blanking in field 1. The VDVBLKS1 is shown in Figure 4–43  
and described in Table 4–10.  
In raw data mode, VBLNK is asserted whenever the frame line counter  
(FLCOUNT) is equal to VBLNKYSTART1 and the frame pixel counter  
(FPCOUNT) is equal to VBLNKXSTART1 (this is shown in Figure 4–6,  
page 4-7).  
In BT.656 and Y/C mode, VBLNK is asserted whenever  
FLCOUNT = VBLNKYSTART1 and FPCOUNT = VBLNKXSTART1. This  
VBLNK output control is completely independent of the timing control codes.  
The V bit in the EAV/SAV codes for field 1 is controlled by the VDVBIT1 register.  
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Figure 4–43. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)  
31  
28 27  
16  
0
Reserved  
R-0  
VBLNKYSTART1  
R/W-0  
15  
12 11  
Reserved  
R-0  
VBLNKXSTART1  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 4–10. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)  
Field Descriptions  
Description  
†
†
BT.656 and Y/C Mode  
Raw Data Mode  
Bit  
field  
symval  
Value  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as  
0. A value written to this field has no effect.  
27–16 VBLNKYSTART1 OF(value)  
0–FFFh Specifies the line (in  
FLCOUNT) where  
Specifies the line (in  
FLCOUNT) where vertical  
blanking begins (VBLNK  
active edge) for field 1.  
VBLNK active edge  
occurs for field 1. Does  
not affect EAV/SAV V bit  
operation.  
15–12 Reserved  
–
0
Reserved. The reserved bit location is always read as  
0. A value written to this field has no effect.  
11–0 VBLNKXSTART1 OF(value)  
0–FFFh Specifies the pixel (in  
FPCOUNT) where  
Specifies the pixel (in  
FPCOUNT) where  
vertical blanking begins  
(VBLNK active edge) for  
field 1.  
VBLNK active edge  
occurs for field 1.  
†
For CSL implementation, use the notation VP_VDVBLKS1_field_symval  
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4.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)  
The video display field 1 vertical blanking end register (VDVBLKE1) controls  
the end of vertical blanking in field 1. The VDVBLKE1 is shown in Figure 4–44  
and described in Table 4–11.  
In raw data mode, VBLNK is deasserted whenever the frame line counter  
(FLCOUNT) is equal to VBLNKYSTOP1 and the frame pixel counter (FPCOUNT)  
is equal to VBLNKXSTOP1 (this is shown in Figure 4–6, page 4-7).  
In BT.656 and Y/C mode, VBLNK is deasserted whenever  
FLCOUNT = VBLNKYSTOP1 and FPCOUNT = VBLNKXSTOP1. This  
VBLNK output control is completely independent of the timing control codes.  
The V bit in the EAV/SAV codes for field 1 is controlled by the VDVBIT1 register.  
Figure 4–44. Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)  
31  
28 27  
16  
0
Reserved  
R-0  
VBLNKYSTOP1  
R/W-0  
15  
12 11  
Reserved  
R-0  
VBLNKXSTOP1  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
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Table 4–11. Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)  
Field Descriptions  
Description  
BT.656 and Y/C Mode Raw Data Mode  
†
†
Bit  
field  
symval  
Value  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as  
0. A value written to this field has no effect.  
27–16 VBLNKYSTOP1  
OF(value)  
0–FFFh Specifies the line (in  
FLCOUNT) where  
Specifies the line (in  
FLCOUNT) where vertical  
blanking ends (VBLNK  
inactive edge) for field 1.  
VBLNK inactive edge  
occurs for field 1. Does  
not affect EAV/SAV V bit  
operation.  
15–12 Reserved  
–
0
Reserved. The reserved bit location is always read as  
0. A value written to this field has no effect.  
11–0 VBLNKXSTOP1  
OF(value)  
0–FFFh Specifies the pixel (in  
FPCOUNT) where  
Specifies the pixel (in  
FPCOUNT) where  
vertical blanking ends  
(VBLNK inactive edge)  
for field 1.  
VBLNK inactive edge  
occurs for field 1.  
†
For CSL implementation, use the notation VP_VDVBLKE1_field_symval  
4.12.7 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2)  
The video display field 2 vertical blanking start register (VDVBLKS2) controls  
the start of vertical blanking in field 2. The VDVBLKS2 is shown in Figure 4–45  
and described in Table 4–12.  
In raw data mode, VBLNK is asserted whenever the frame line counter  
(FLCOUNT) is equal to VBLNKYSTART2 and the frame pixel counter (FPCOUNT)  
is equal to VBLNKXSTART2 (this is shown in Figure 4–6, page 4-7).  
In BT.656 and Y/C mode, VBLNK is asserted whenever  
FLCOUNT = VBLNKYSTART2 and FPCOUNT = VBLNKXSTART2. This  
VBLNK output control is completely independent of the timing control codes.  
The V bit in the EAV/SAV codes for field 2 is controlled by the VDVBIT2 register.  
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Figure 4–45. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2)  
31  
28 27  
16  
0
Reserved  
R-0  
VBLNKYSTART2  
R/W-0  
15  
12 11  
Reserved  
R-0  
VBLNKXSTART2  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 4–12. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2)  
Field Descriptions  
Description  
†
†
BT.656 and Y/C Mode  
Raw Data Mode  
Bit  
field  
symval  
Value  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as  
0. A value written to this field has no effect.  
27–16 VBLNKYSTART2 OF(value)  
0–FFFh Specifies the line (in  
FLCOUNT) where  
Specifies the line (in  
FLCOUNT) where vertical  
blanking begins (VBLNK  
active edge) for field 2.  
VBLNK active edge  
occurs for field 2. Does  
not affect EAV/SAV V bit  
operation.  
15–12 Reserved  
–
0
Reserved. The reserved bit location is always read as  
0. A value written to this field has no effect.  
11–0 VBLNKXSTART2 OF(value)  
0–FFFh Specifies the pixel (in  
FPCOUNT) where  
Specifies the pixel (in  
FPCOUNT) where  
vertical blanking begins  
(VBLNK active edge) for  
field 2.  
VBLNK active edge  
occurs for field 2.  
†
For CSL implementation, use the notation VP_VDVBLKS2_field_symval  
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4.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)  
The video display field 2 vertical blanking end register (VDVBLKE2) controls  
the end of vertical blanking in field 2. The VDVBLKE2 is shown in Figure 4–46  
and described in Table 4–13.  
In raw data mode, VBLNK is deasserted whenever the frame line counter  
(FLCOUNT) is equal to VBLNKYSTOP2 and the frame pixel counter (FPCOUNT)  
is equal to VBLNKXSTOP2 (this is shown in Figure 4–6, page 4-7).  
In BT.656 and Y/C mode, VBLNK is deasserted whenever  
FLCOUNT = VBLNKYSTOP2 and FPCOUNT = VBLNKXSTOP2. This  
VBLNK output control is completely independent of the timing control codes.  
The V bit in the EAV/SAV codes for field 2 is controlled by the VDVBIT2 register.  
Figure 4–46. Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)  
31  
28 27  
16  
0
Reserved  
R-0  
VBLNKYSTOP2  
R/W-0  
15  
12 11  
Reserved  
R-0  
VBLNKXSTOP2  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
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Table 4–13. Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)  
Field Descriptions  
Description  
†
†
BT.656 and Y/C Mode  
Raw Data Mode  
Bit  
field  
symval  
Value  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as  
0. A value written to this field has no effect.  
27–16 VBLNKYSTOP2  
OF(value)  
0–FFFh Specifies the line (in  
FLCOUNT) where  
Specifies the line (in  
FLCOUNT) where vertical  
blanking ends (VBLNK  
inactive edge) for field 2.  
VBLNK inactive edge  
occurs for field 2. Does  
not affect EAV/SAV V bit  
operation.  
15–12 Reserved  
–
0
Reserved. The reserved bit location is always read as  
0. A value written to this field has no effect.  
11–0 VBLNKXSTOP2  
OF(value)  
0–FFFh Specifies the pixel (in  
FPCOUNT) where  
Specifies the pixel (in  
FPCOUNT) where  
vertical blanking ends  
(VBLNK inactive edge)  
for field 2.  
VBLNK inactive edge  
occurs for field 2.  
†
For CSL implementation, use the notation VP_VDVBLKE2_field_symval  
4.12.9 Video Display Field 1 Image Offset Register (VDIMGOFF1)  
The video display field 1 image offset register (VDIMGOFF1) defines the  
field 1 image offset and specifies the starting location of the displayed image  
relative to the start of the active display. The VDIMGOFF1 is shown in  
Figure 4–47 and described in Table 4–14.  
The image line counter (ILCOUNT) is reset to 1 on the first image line (when  
FLCOUNT = VBLNKYSTOP1 + IMGVOFF1). If the NV bit is set, ILCOUNT is  
reset to 1 when FLCOUNT = VBLNKYSTOP1 – IMGVOFF1. Display image  
pixels are output in field 1 beginning on the line where ILCOUNT = 1. The  
default output values or blanking values are output during active lines prior to  
ILCOUNT = 1. For a negative offset, IMGVOFF1 must not be greater than  
VBLNKYSTOP1. The field 1 active image must not overlap the field 2 active image.  
The image pixel counter (IPCOUNT) is reset to 0 at the start of an active line  
image. Once ILCOUNT = 1, image pixels from the FIFO are output on each  
line in field 1 beginning when FPCOUNT = IMGHOFF1. If the NH bit is set,  
IPCOUNTis reset whenFPCOUNT = FRMWIDTH – IMGHOFF1. Thedefault  
output values or blanking values are output during active pixels prior to  
IMGHOFF1.  
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Figure 4–47. Video Display Field 1 Image Offset Register (VDIMGOFF1)  
31  
NV  
30  
28 27  
16  
0
Reserved  
R-0  
IMGVOFF1  
R/W-0  
R/W-0  
15  
NH  
14  
12 11  
Reserved  
R-0  
IMGHOFF1  
R/W-0  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 4–14. Video Display Field 1 Image Offset Register (VDIMGOFF1) Field Descriptions  
Description  
†
†
BT.656 and Y/C Mode  
Raw Data Mode  
Bit  
field  
symval  
Value  
31  
NV  
Negative vertical image offset enable bit.  
Not used.  
NONE  
0
1
NEGOFF  
Display image window  
begins before the first active  
line of field 1. (Used for VBI  
data output.)  
Not used.  
30–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
27–16 IMGVOFF1  
OF(value)  
0–FFFh Specifies the display image vertical offset in lines from the  
first active line of field 1.  
15  
NH  
Negative horizontal image offset.  
NONE  
0
1
Not used.  
Not used.  
NEGOFF  
Display image window  
begins before the start of  
active video. (Used for  
HANC data output.)  
14–12 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
11–0 IMGHOFF1 OF(value)  
0–FFFh Specifies the display image  
Specifies the display image  
horizontal offset in pixels  
horizontal offset in pixels  
from the start of each line of from the start of each line of  
active video in field 1. This  
must be an even number  
(the LSB is treated as 0).  
active video in field 1.  
†
For CSL implementation, use the notation VP_VDIMGOFF1_field_symval  
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4.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1)  
The video display field 1 image size register (VDIMGSZ1) defines the field 1  
image area and specifies the size of the displayed image within the active dis-  
play. The VDIMGSZ1 is shown in Figure 4–48 and described in Table 4–15.  
The image pixel counter (IPCOUNT) counts displayed image pixel output on  
each of the displayed image. Displayed image pixel output stops when  
IPCOUNT = IMGHSIZE1. The default output values or blanking values are  
output for the remainder of the active line.  
The image line counter (ILCOUNT) counts displayed image lines. Displayed  
image output stops when ILCOUNT = IMGVSIZE1. The default output values  
or blanking values are output for the remainder of the active field.  
Figure 4–48. Video Display Field 1 Image Size Register (VDIMGSZ1)  
31  
28 27  
16  
0
Reserved  
R-0  
IMGVSIZE1  
R/W-0  
15  
12 11  
Reserved  
R-0  
IMGHSIZE1  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 4–15. Video Display Field 1 Image Size Register (VDIMGSZ1) Field Descriptions  
Description  
†
†
BT.656 and Y/C Mode  
Raw Data Mode  
Bit  
field  
symval  
Value  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
27–16 IMGVSIZE1 OF(value)  
15–12 Reserved  
0–FFFh Specifies the display image height in lines.  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
11–0 IMGHSIZE1 OF(value)  
0–FFFh Specifies the display image  
Specifies the display image  
width in pixels. This number width in pixels.  
must be even (the LSB is  
treated as 0)  
†
For CSL implementation, use the notation VP_VDIMGSZ1_field_symval  
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4.12.11 Video Display Field 2 Image Offset Register (VDIMGOFF2)  
The video display field 2 image offset register (VDIMGOFF2) defines the  
field 2 image offset and specifies the starting location of the displayed image  
relative to the start of the active display. The VDIMGOFF2 is shown in  
Figure 4–49 and described in Table 4–16.  
The image line counter (ILCOUNT) is reset to 1 on the first image line (when  
FLCOUNT = VBLNKYSTOP2 + IMGVOFF2). If the NV bit is set, ILCOUNT is  
reset to 1 when FLCOUNT = VBLNKYSTOP2 – IMGVOFF2. Display image  
pixels are output in field 2 beginning on the line where ILCOUNT = 1. The  
default output values or blanking values are output during active lines prior to  
ILCOUNT = 1. For a negative offset, IMGVOFF2 must not be greater than  
VBLNKYSTOP2. The field 2 active image must not overlap the field 2 active image.  
The image pixel counter (IPCOUNT) is reset to 0 at the start of an active line  
image. Once ILCOUNT = 1, image pixels from the FIFO are output on each  
line in field 2 beginning when FPCOUNT = IMGHOFF2. If the NH bit is set,  
IPCOUNTisreset when FPCOUNT = FRMWIDTH – IMGHOFF2. Thedefault  
output values or blanking values are output during active pixels prior to  
IMGHOFF2.  
Figure 4–49. Video Display Field 2 Image Offset Register (VDIMGOFF2)  
31  
NV  
30  
28 27  
16  
0
Reserved  
R-0  
IMGVOFF2  
R/W-0  
R/W-0  
15  
NH  
14  
12 11  
Reserved  
R-0  
IMGHOFF2  
R/W-0  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
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Table 4–16. Video Display Field 2 Image Offset Register (VDIMGOFF2)  
Field Descriptions  
Description  
†
†
BT.656 and Y/C Mode  
Raw Data Mode  
Bit  
field  
symval  
Value  
31  
NV  
Negative vertical image offset enable bit.  
Not used.  
NONE  
0
1
NEGOFF  
Display image window  
begins before the first active  
line of field 2. (Used for VBI  
data output.)  
Not used.  
30–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
27–16 IMGVOFF2  
OF(value)  
0–FFFh Specifies the display image vertical offset in lines from the  
first active line of field 2.  
15  
NH  
Negative horizontal image offset.  
NONE  
0
1
Not used.  
Not used.  
NEGOFF  
Display image window  
begins before the start of  
active video. (Used for  
HANC data output.)  
14–12 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
11–0 IMGHOFF2 OF(value)  
0–FFFh Specifies the display image  
Specifies the display image  
horizontal offset in pixels  
horizontal offset in pixels  
from the start of each line of from the start of each line of  
active video in field 2. This  
must be an even number  
(the LSB is treated as 0).  
active video in field 2.  
†
For CSL implementation, use the notation VP_VDIMGOFF2_field_symval  
4-72  
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Video Display Registers  
4.12.12 Video Display Field 2 Image Size Register (VDIMGSZ2)  
The video display field 2 image size register (VDIMGSZ2) defines the field 2  
image area and specifies the size of the displayed image within the active dis-  
play. The VDIMGSZ2 is shown in Figure 4–50 and described in Table 4–17.  
The image pixel counter (IPCOUNT) counts displayed image pixel output on  
each of the displayed image. Displayed image pixel output stops when  
IPCOUNT = IMGHSIZE2. The default output values or blanking values are  
output for the remainder of the active line.  
The image line counter (ILCOUNT) counts displayed image lines. Displayed  
image output stops when ILCOUNT = IMGVSIZE2. The default output values  
or blanking values are output for the remainder of the active field.  
Figure 4–50. Video Display Field 2 Image Size Register (VDIMGSZ2)  
31  
28 27  
16  
0
Reserved  
R-0  
IMGVSIZE2  
R/W-0  
15  
12 11  
Reserved  
R-0  
IMGHSIZE2  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 4–17. Video Display Field 2 Image Size Register (VDIMGSZ2) Field Descriptions  
Description  
†
†
BT.656 and Y/C Mode  
Raw Data Mode  
Bit  
field  
symval  
Value  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
27–16 IMGVSIZE2 OF(value)  
15–12 Reserved  
0–FFFh Specifies the display image height in lines.  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
11–0 IMGHSIZE2 OF(value)  
0–FFFh Specifies the display image  
Specifies the display image  
width in pixels. This number width in pixels.  
must be even (the LSB is  
treated as 0)  
†
For CSL implementation, use the notation VP_VDIMGSZ2_field_symval  
SPRU629  
Video Display Port  
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Video Display Registers  
4.12.13 Video Display Field 1 Timing Register (VDFLDT1)  
The video display field 1 timing register (VDFLDT1) sets the timing of the field  
identification signal. The VDFLDT1 is shown in Figure 4–51 and described in  
Table 4–18.  
In raw data mode, the FLD signal is deasserted to indicate field 1 display  
whenever the frame line counter (FLCOUNT) is equal to FLD1YSTART and  
the frame pixel counter (FPCOUNT) is equal to FLD1XSTART (this is shown  
in Figure 4–6, page 4-7).  
In BT.656 and Y/C mode, the FLD signal is deasserted to indicate field 1 dis-  
play whenever FLCOUNT = FLD1YSTART and FPCOUNT = FLD1XSTART.  
The FLD output is completely independent of the timing control codes. The  
F bit in the EAV/SAV codes is controlled by the VDFBIT register.  
Figure 4–51. Video Display Field 1 Timing Register (VDFLDT1)  
31  
28 27  
16  
0
Reserved  
R-0  
FLD1YSTART  
R/W-0  
15  
12 11  
Reserved  
R-0  
FLD1XSTART  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 4–18. Video Display Field 1 Timing Register (VDFLDT1) Field Descriptions  
†
†
Bit  
field  
symval  
Value  
Description  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0.  
A value written to this field has no effect.  
27–16 FLD1YSTART OF(value)  
0–FFFh Specifies the first line of field 1. (The line where FLD is  
deasserted.)  
15–12 Reserved  
–
0
Reserved. The reserved bit location is always read as 0.  
A value written to this field has no effect.  
11–0 FLD1XSTART OF(value)  
0–FFFh Specifies the pixel on the first line of field 1 where the FLD  
output is deasserted.  
†
For CSL implementation, use the notation VP_VDFLDT1_field_symval  
4-74  
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Video Display Registers  
4.12.14 Video Display Field 2 Timing Register (VDFLDT2)  
The video display field 2 timing register (VDFLDT2) sets the timing of the field  
identification signal. The VDFLDT2 is shown in Figure 4–52 and described in  
Table 4–19.  
In raw data mode, the FLD signal is asserted whenever the frame line counter  
(FLCOUNT) is equal to FLD2YSTART and the frame pixel counter (FPCOUNT)  
is equal to FLD2XSTART (this is shown in Figure 4–6, page 4-7).  
In BT.656 and Y/C mode, the FLD signal is asserted to indicate field 2 display  
whenever FLCOUNT = FLD2YSTART and FPCOUNT = FLD2XSTART. The  
FLD output is completely independent of the timing control codes. The F bit  
in the EAV/SAV codes is controlled by the VDFBIT register.  
Figure 4–52. Video Display Field 2 Timing Register (VDFLDT2)  
31  
28 27  
16  
0
Reserved  
R-0  
FLD2YSTART  
R/W-0  
15  
12 11  
Reserved  
R-0  
FLD2XSTART  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 4–19. Video Display Field 2 Timing Register (VDFLDT2) Field Descriptions  
†
†
Bit  
field  
symval  
Value  
Description  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0.  
A value written to this field has no effect.  
27–16 FLD2YSTART OF(value)  
0–FFFh Specifies the first line of field 2. (The line where FLD is  
asserted.)  
15–12 Reserved  
–
0
Reserved. The reserved bit location is always read as 0.  
A value written to this field has no effect.  
11–0 FLD2XSTART OF(value)  
0–FFFh Specifies the pixel on the first line of field 2 where the FLD  
output is asserted.  
†
For CSL implementation, use the notation VP_VDFLDT2_field_symval  
SPRU629  
Video Display Port  
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Video Display Registers  
4.12.15 Video Display Threshold Register (VDTHRLD)  
The video display threshold register (VDTHRLD) sets the display FIFO thresh-  
old to determine when to load more display data. The VDTHRLD is shown in  
Figure 4–53 and described in Table 4–20.  
The VDTHRLDn bits determines how much space must be available in the  
display FIFOs before the appropriate DMA event may be generated. The  
Y FIFO uses the VDTHRLDn value directly while the Cb and Cr values use  
½ the VDTHRLDn value rounded up to the next doubleword  
(1/2 (VDTHRLDn + VTHRLDn mod 2). The DMA transfer size must be less  
than the value used for each FIFO. Typically, VDTHRLDn is set to the horizontal  
line length rounded up to the next doubleword boundary. For nonline length  
thresholds, the display data unpacking mechanism places certain restrictions  
of what VDTHRLDn values are valid (see section 2.3.3).  
The VDTHRLD2 bits behaves identically to VDTHRLD1, but are used during  
field 2 capture. It is only used if the field 2 DMA size needs to be different from  
the field 1 DMA size for some reason (for example, different display line  
lengths in field 1 and field 2).  
In raw display mode, the INCPIX bits determine when the frame pixel counter  
(FPCOUNT) is incremented . If, for example, each output value represents the  
R, G, or B portion of a display pixel, then the INCPIX bits are set to 3h so that  
the pixel counter is incremented only on every third output clock. An INCPIX  
value of 0h represents a count of 16 rather than 0.  
Figure 4–53. Video Display Threshold Register (VDTHRLD)  
31  
26 25  
16  
0
Reserved  
R-0  
VDTHRLD2  
R/W-0  
15  
12 11  
Reserved  
R-0  
10  
9
INCPIX  
R/W-0001  
VDTHRLD1  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
4-76  
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Video Display Registers  
Table 4–20. Video Display Threshold Register (VDTHRLD) Field Descriptions  
Description  
BT.656 and Y/C Mode Raw Data Mode  
†
†
Bit  
field  
symval  
Value  
31–26 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
25–16 VDTHRLD2 OF(value)  
0–3FFh Field 2 threshold. Whenever Field 2 threshold. Whenever  
there are at least VDTHRLD there are at least VDTHRLD  
doublewords of space in the doublewords of space in the  
Y display FIFO, a new Y  
DMA event may be  
display FIFO, a new Y DMA  
event may be generated.  
generated. Whenever there  
are at least ½ VDTHRLD  
doublewords of space in the  
Cb or Cr display FIFO, a  
new Cb or Cr DMA event  
may be generated.  
15–12 INCPIX  
OF(value)  
0–Fh  
Not used.  
FPCOUNT is incremented  
every INCPIX output clocks.  
11–10 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
9–0  
VDTHRLD1 OF(value)  
0–3FFh Field 1 threshold. Whenever Field 1 threshold. Whenever  
there are at least VDTHRLD there are at least VDTHRLD  
doublewords of space in the doublewords of space in the  
Y display FIFO, a new Y  
DMA event may be  
display FIFO, a new Y DMA  
event may be generated.  
generated. Whenever there  
are at least ½ VDTHRLD  
doublewords of space in the  
Cb or Cr display FIFO, a  
new Cb or Cr DMA event  
may be generated.  
†
For CSL implementation, use the notation VP_VDTHRLD_field_symval  
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Video Display Port  
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Video Display Registers  
4.12.16 Video Display Horizontal Synchronization Register (VDHSYNC)  
The video display horizontal synchronization register (VDHSYNC) controls  
the timing of the horizontal synchronization signal. The VDHSYNC is shown  
in Figure 4–54 and described in Table 4–21.  
Generation of the horizontal synchronization is shown in Figure 4–5,  
page 4-6. The HSYNC signal is asserted to indicate the start of the horizontal  
sync pulse whenever the frame pixel counter (FPCOUNT) is equal to HSYNC-  
START. The HSYNC signal is deasserted to indicate the end of the horizontal  
sync pulse whenever FPCOUNT = HSYNCSTOP.  
Figure 4–54. Video Display Horizontal Synchronization Register (VDHSYNC)  
31  
28 27  
16  
0
Reserved  
R-0  
HSYNCSTOP  
R/W-0  
15  
12 11  
Reserved  
R-0  
HSYNCSTART  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 4–21. Video Display Horizontal Synchronization Register (VDHSYNC)  
Field Descriptions  
†
†
Bit  
field  
symval  
Value  
Description  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0.  
A value written to this field has no effect.  
27–16 HSYNCSTOP OF(value)  
15–12 Reserved  
0–FFFh Specifies the pixel where HSYNC is deasserted.  
–
0
Reserved. The reserved bit location is always read as 0.  
A value written to this field has no effect.  
11–0 HSYNCSTART OF(value)  
0–FFFh Specifies the pixel where HSYNC is asserted.  
†
For CSL implementation, use the notation VP_VDHSYNC_field_symval  
4-78  
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Video Display Registers  
4.12.17 Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1)  
The video display field 1 vertical synchronization start register (VDVSYNS1)  
controls the start of vertical synchronization in field 1. The VDVSYNS1 is  
shown in Figure 4–55 and described in Table 4–22.  
Generation of the vertical synchronization is shown in Figure 4–6, page 4-7.  
The VSYNC signal is asserted whenever the frame line counter (FLCOUNT)  
is equal to VSYNCYSTART1 and the frame pixel counter (FPCOUNT) is equal  
to VSYNCXSTART1.  
Figure 4–55. Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1)  
31  
28 27  
16  
Reserved  
R-0  
VSYNCYSTART1  
R/W-0  
15  
12 11  
0
Reserved  
R-0  
VSYNCXSTART1  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 4–22. Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1)  
Field Descriptions  
†
†
Bit  
field  
symval  
Value  
Description  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as  
0. A value written to this field has no effect.  
27–16 VSYNCYSTART1 OF(value)  
0–FFFh Specifies the line where VSYNC is asserted for  
field 1.  
15–12 Reserved  
–
0
Reserved. The reserved bit location is always read as  
0. A value written to this field has no effect.  
11–0 VSYNCXSTART1 OF(value)  
0–FFFh Specifies the pixel where VSYNC is asserted in  
field 1.  
†
For CSL implementation, use the notation VP_VDVSYNS1_field_symval  
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Video Display Port  
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Video Display Registers  
4.12.18 Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)  
The video display field 1 vertical synchronization end register (VDVSYNE1)  
controls the end of vertical synchronization in field 1. The VDVSYNE1 is  
shown in Figure 4–56 and described in Table 4–23.  
Generation of the vertical synchronization is shown in Figure 4–6, page 4-7.  
TheVSYNCsignalisdeassertedwhenevertheframelinecounter(FLCOUNT)  
is equal to VSYNCYSTOP1 and the frame pixel counter (FPCOUNT) is equal  
to VSYNCXSTOP1.  
Figure 4–56. Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)  
31  
28 27  
16  
0
Reserved  
R-0  
VSYNCYSTOP1  
R/W-0  
15  
12 11  
Reserved  
R-0  
VSYNCXSTOP1  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 4–23. Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)  
Field Descriptions  
†
†
Bit  
field  
symval  
Value  
Description  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as  
0. A value written to this field has no effect.  
27–16 VSYNCYSTOP1 OF(value)  
0–FFFh Specifies the line where VSYNC is deasserted for  
field 1.  
15–12 Reserved  
–
0
Reserved. The reserved bit location is always read as  
0. A value written to this field has no effect.  
11–0 VSYNCXSTOP1 OF(value)  
0–FFFh Specifies the pixel where VSYNC is deasserted in  
field 1.  
†
For CSL implementation, use the notation VP_VDVSYNE1_field_symval  
4-80  
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Video Display Registers  
4.12.19 Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2)  
The video display field 2 vertical synchronization start register (VDVSYNS2)  
controls the start of vertical synchronization in field 2. The VDVSYNS2 is  
shown in Figure 4–57 and described in Table 4–24.  
Generation of the vertical synchronization is shown in Figure 4–6, page 4-7.  
The VSYNC signal is asserted whenever the frame line counter (FLCOUNT)  
is equal to VSYNCYSTART2 and the frame pixel counter (FPCOUNT) is equal  
to VSYNCXSTART2.  
Figure 4–57. Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2)  
31  
28 27  
16  
Reserved  
R-0  
VSYNCYSTART2  
R/W-0  
15  
12 11  
0
Reserved  
R-0  
VSYNCXSTART2  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 4–24. Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2)  
Field Descriptions  
†
†
Bit  
field  
symval  
Value  
Description  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as  
0. A value written to this field has no effect.  
27–16 VSYNCYSTART2 OF(value)  
0–FFFh Specifies the line where VSYNC is asserted for  
field 2.  
15–12 Reserved  
–
0
Reserved. The reserved bit location is always read as  
0. A value written to this field has no effect.  
11–0 VSYNCXSTART2 OF(value)  
0–FFFh Specifies the pixel where VSYNC is asserted in  
field 2.  
†
For CSL implementation, use the notation VP_VDVSYNS2_field_symval  
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Video Display Registers  
4.12.20 Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2)  
The video display field 2 vertical synchronization end register (VDVSYNE2)  
controls the end of vertical synchronization in field 2. The VDVSYNE2 is  
shown in Figure 4–58 and described in Table 4–25.  
Generation of the vertical synchronization is shown in Figure 4–6, page 4-7.  
The VSYNC signal is deasserted whenever the frame line counter (FLCOUNT)  
is equal to VSYNCYSTOP2 and the frame pixel counter (FPCOUNT) is equal  
to VSYNCXSTOP2.  
Figure 4–58. Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2)  
31  
28 27  
16  
0
Reserved  
R-0  
VSYNCYSTOP2  
R/W-0  
15  
12 11  
Reserved  
R-0  
VSYNCXSTOP2  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 4–25. Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2)  
Field Descriptions  
†
†
Bit  
field  
symval  
Value  
Description  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as  
0. A value written to this field has no effect.  
27–16 VSYNCYSTOP2 OF(value)  
0–FFFh Specifies the line where VSYNC is deasserted for  
field 2.  
15–12 Reserved  
–
0
Reserved. The reserved bit location is always read as  
0. A value written to this field has no effect.  
11–0 VSYNCXSTOP2 OF(value)  
0–FFFh Specifies the pixel where VSYNC is deasserted in  
field 2.  
†
For CSL implementation, use the notation VP_VDVSYNE2_field_symval  
4-82  
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Video Display Registers  
4.12.21 Video Display Counter Reload Register (VDRELOAD)  
When external horizontal or vertical synchronization are used, the video  
display counter reload register (VDRELOAD) determines what values are  
loaded into the counters when an external sync is activated. The VDRELOAD  
is shown in Figure 4–59 and described in Table 4–26.  
Figure 4–59. Video Display Counter Reload Register (VDRELOAD)  
31  
28 27  
16  
0
Reserved  
R-0  
VRLD  
R/W-0  
15  
12 11  
CRLD  
R/W-0  
HRLD  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 4–26. Video Display Counter Reload Register (VDRELOAD) Field Descriptions  
†
†
Bit  
field  
symval  
Value  
Description  
31–28 Reserved  
27–16 VRLD  
15–12 CRLD  
11–0 HRLD  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
OF(value)  
OF(value)  
OF(value)  
0–FFFh Value loaded into frame line counter (FLCOUNT) when  
external VSYNC occurs.  
0–Fh  
Value loaded into video clock counter (VCCOUNT) when  
external HSYNC occurs.  
0–FFFh Value loaded into frame pixel counter (FPCOUNT) when  
external HSYNC occurs.  
†
For CSL implementation, use the notation VP_VDRELOAD_field_symval  
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Video Display Registers  
4.12.22 Video Display Display Event Register (VDDISPEVT)  
The video display display event register (VDDISPEVT) is programmed with  
the number of DMA events to be generated for display field 1 and field 2. The  
VDDISPEVET is shown in Figure 4–60 and described in Table 4–27.  
Figure 4–60. Video Display Display Event Register (VDDISPEVT)  
31  
28 27  
16  
0
Reserved  
R-0  
DISPEVT2  
R/W-0  
15  
12 11  
Reserved  
R-0  
DISPEVT1  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 4–27. Video Display Display Event Register (VDDISPEVT) Field Descriptions  
Description  
†
†
BT.656 and Y/C Mode  
Raw Data Mode  
Bit  
field  
symval  
Value  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
27–16 DISPEVT2 OF(value)  
0–FFFh Specifies the number of DMA Specifies the number of DMA  
event sets (YEVT, CbEVT,  
CrEVT) to be generated for  
field 2 output.  
events (YEVT) to be  
generated for field 2 output.  
15–12 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
11–0 DISPEVT1 OF(value)  
0–FFFh Specifies the number of DMA Specifies the number of DMA  
event sets (YEVT, CbEVT,  
CrEVT) to be generated for  
field 1 output.  
events (YEVT) to be  
generated for field 1 output.  
†
For CSL implementation, use the notation VP_VDDISPEVT_DISPEVTn_symval  
4-84  
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Video Display Registers  
4.12.23 Video Display Clipping Register (VDCLIP)  
The video display clipping register (VDCLIP) is shown in Figure 4–61 and  
described in Table 4–28.  
The video display module in the BT.656 and Y/C modes performs program-  
mable clipping. The clipping is performed as the last step of the video pipeline.  
It is applied only on the image areas defined by VDIMGSZn and VDIMGOFFn  
inside the active video area (blanking values are not clipped).  
VDCLIP allows output values to be clamped within the specified values. The  
default values are the BT.601-specified peak black level of 16 and peak white  
level of 235 for luma and the maximum quantization levels of 16 and 240 for  
chroma. For 10-bit operation, the clipping is applied to the 8 MSBs of the value  
with the 2 LSBs cleared. (For example, a Y value of FF.8h is clipped to EB.0h  
and a Y value of 0F.4h is clipped to 10.0h.)  
Figure 4–61. Video Display Clipping Register (VDCLIP)  
31  
24 23  
16  
0
CLIPCHIGH  
CLIPCLOW  
R/W-1111 0000  
R/W-0001 0000  
15  
8
7
CLIPYHIGH  
CLIPYLOW  
R/W-1110 1011  
R/W-0001 0000  
Legend: R/W = Read/Write; -n = value after reset  
Table 4–28. Video Display Clipping Register (VDCLIP) Field Descriptions  
Description  
†
†
BT.656 and Y/C Mode  
Raw Data Mode  
Bit  
field  
symval  
Value  
31–24 CLIPCHIGH OF(value)  
23–16 CLIPCLOW OF(value)  
15–8 CLIPYHIGH OF(value)  
0–FFh  
A Cb or Cr value greater than  
CLIPCHIGH is forced to the  
CLIPCHIGH value.  
Not used.  
0–FFh  
A Cb or Cr value less than  
CLIPCLOW is forced to the  
CLIPCLOW value.  
Not used.  
0–FFh  
A Y value greater than CLIPYHIGH is Not used.  
forced to the CLIPYHIGH value.  
7–0  
CLIPYLOW OF(value)  
0–FFh  
A Y value less than CLIPYLOW is  
forced to the CLIPYLOW value.  
Not used.  
†
For CSL implementation, use the notation VP_VDCLIP_field_symval  
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Video Display Registers  
4.12.24 Video Display Default Display Value Register (VDDEFVAL)  
The video display default display value register (VDDEFVAL) defines the  
default value to be output during the portion of the active video window that is  
not part of the displayed image. The VDDEFVAL is shown in Figure 4–62 for  
the BT.656 and Y/C modes and in Figure 4–63 for the raw data mode, and  
described in Table 4–29.  
The default value is output during the nonimage display window portions of the  
active video. This is the region between ILCOUNT = 0 and  
ILCOUNT = IMGVOFFn vertically, and between IPCOUNT = 0 and  
IPCOUNT = IMGHOFFn horizontally. In BT.656 mode, CBDEFVAL,  
YDEFVAL, and CRDEFVAL are multiplexed on the output in the standard  
CbYCrY manner. In Y/C mode, YDEFVAL is output on the VDOUT[9–0] bus  
and CBDEFVAL and CRDEFVAL are multiplexed on the VDOUT[19–10] bus.  
In all cases, the default values are output on the 8 MSBs of the bus ([9–2] or  
[19–12]) and the 2 LSBs ([1–0] or [11–10]) are driven as 0s.  
In raw data mode, the least significant 8, 10, 16, or 20 bits of DEFVAL are  
output depending on the bus width. The default value is also output during the  
horizontal and vertical blanking periods in raw data mode.  
The default value is also output during the entire active video region when the  
BLKDIS bit in VDCTL is set and the FIFO is empty.  
Figure 4–62. Video Display Default Display Value Register (VDDEFVAL)  
31  
24 23  
16  
0
CRDEFVAL  
R/W-0  
CBDEFVAL  
R/W-0  
15  
8
7
Reserved  
R/W-0  
YDEFVAL  
R/W-0  
Legend: R/W = Read/Write; -n = value after reset  
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Video Display Registers  
Figure 4–63. Video Display Default Display Value Register (VDDEFVAL)—Raw Data Mode  
31  
20 19  
16  
Reserved  
R/W-0  
DEFVAL  
R/W-0  
15  
0
DEFVAL  
R/W-0  
Legend: R/W = Read/Write; -n = value after reset  
Table 4–29. Video Display Default Display Value Register (VDDEFVAL) Field Descriptions  
Description  
†
†
BT.656 and Y/C Mode  
Raw Data Mode  
Bit  
field  
symval  
Value  
31–24 CRDEFVAL OF(value)  
0–FFh  
Specifies the 8 MSBs of the Not used.  
default Cr display value.  
‡
31–20 Reserved  
–
0
Not used.  
Reserved. The reserved bit  
location is always read as 0.  
A value written to this field  
has no effect.  
‡
19–0  
DEFVAL  
OF(value)  
0–FFFFFh Not used.  
Specifies the default raw  
data display value.  
23–16 CBDEFVAL OF(value)  
0–FFh  
Specifies the 8 MSBs of the Not used.  
default Cb display value.  
15–8 Reserved  
–
0
Reserved. The reserved bit Not used.  
location is always read as 0.  
A value written to this field  
has no effect.  
7–0  
YDEFVAL  
OF(value)  
0–FFh  
Specifies the 8 MSBs of the Not used.  
default Y display value.  
†
‡
For CSL implementation, use the notation VP_VDDEFVAL_field_symval  
Raw data mode only.  
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Video Display Registers  
4.12.25 Video Display Vertical Interrupt Register (VDVINT)  
The video display vertical interrupt register (VDVINT) controls the generation  
of vertical interrupts in field 1 and field 2. The VDVINT is shown in Figure 4–64  
and described in Table 4–30.  
An interrupt can be generated upon completion of the specified line in a field  
(when FLCOUNT = VINTn). This allows the software to synchronize itself to  
the frame or field. The interrupt can be programmed to occur in one, both, or  
no fields using the VIF1 and VIF2 bits.  
Figure 4–64. Video Display Vertical Interrupt Register (VDVINT)  
31  
30  
28 27  
16  
0
VIF2  
R/W-0  
Reserved  
R-0  
VINT2  
R/W-0  
15  
14  
12 11  
VIF1  
R/W-0  
Reserved  
R-0  
VINT1  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 4–30. Video Display Vertical Interrupt Register (VDVINT) Field Descriptions  
†
†
Bit  
field  
VIF2  
symval  
Value  
Description  
31  
Vertical interrupt (VINT) in field 2 enable bit.  
DISABLE  
ENABLE  
–
0
1
0
Vertical interrupt (VINT) in field 2 is disabled.  
Vertical interrupt (VINT) in field 2 is enabled.  
30–28 Reserved  
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
27–16 VINT2  
OF(value)  
0–FFFh Line where vertical interrupt (VINT) occurs, if VIF2 bit is set.  
15  
VIF1  
Vertical interrupt (VINT) in field 1 enable bit.  
DISABLE  
ENABLE  
–
0
1
0
Vertical interrupt (VINT) in field 1 is disabled.  
Vertical interrupt (VINT) in field 1 is enabled.  
14–12 Reserved  
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
11–0 VINT1  
OF(value)  
0–FFFh Line where vertical interrupt (VINT) occurs, if VIF1 bit is set.  
†
For CSL implementation, use the notation VP_VDVINT_field_symval  
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Video Display Registers  
4.12.26 Video Display Field Bit Register (VDFBIT)  
The video display field bit register (VDFBIT) controls the F bit value in the EAV  
and SAV timing control codes. The VDFBIT is shown in Figure 4–65 and  
described in Table 4–31.  
The FBITCLR and FBITSET bits control the F bit value in the EAV and SAV  
timing control codes. The F bit is cleared to 0 (indicating field 1 display) in the  
EAV code at the beginning of the line whenever the frame line counter (FLCOUNT)  
is equal to FBITCLR. It remains a 0 for all subsequent EAV/SAV codes until  
the EAV at the beginning of the line when FLCOUNT = FBITSET where it  
changes to 1 (indicating field 2 display). The F bit operation is completely inde-  
pendent of the FLD control signal.  
For interlaced operation, FBITCLR and FBITSET are typically programmed  
such that the F bit changes coincidently with or some time after the V bit transi-  
tions from 1 to 0 (as determined by VBITCLR1 and VBITCLR2 in VDVBITn).  
For progressive scan operation no field 2 output occurs, so FBITSET should  
be programmed to a value greater than FRMHEIGHT so that the condition  
FLCOUNT = FBITSET never occurs and the F bit is always 0.  
Figure 4–65. Video Display Field Bit Register (VDFBIT)  
31  
28 27  
16  
0
Reserved  
R-0  
FBITSET  
R/W-0  
15  
12 11  
Reserved  
R-0  
FBITCLR  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 4–31. Video Display Field Bit Register (VDFBIT) Field Descriptions  
Description  
†
†
BT.656 and Y/C Mode  
Raw Data Mode  
Bit  
field  
symval  
Value  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
27–16 FBITSET OF(value)  
0–FFFh Specifies the first line with an EAV of  
Not used.  
F = 1 indicating field 2 display.  
15–12 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
11–0 FBITCLR OF(value)  
0–FFFh Specifies the first line with an EAV of  
Not used.  
F = 0 indicating field 1 display.  
†
For CSL implementation, use the notation VP_VDFBIT_field_symval  
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4.12.27 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1)  
The video display field 1 vertical blanking bit register (VDVBIT1) controls the  
V bit value in the EAV and SAV timing control codes for field 1. The VDVBIT1  
is shown in Figure 4–66 and described in Table 4–32.  
The VBITSET1 and VBITCLR1 bits control the V bit value in the EAV and SAV  
timing control codes. The V bit is set to 1 (indicating the start of field 1 digital  
vertical blanking) in the EAV code at the beginning of the line whenever the  
frame line counter (FLCOUNT) is equal to VBITSET1. It remains a 1 for all  
EAV/SAV codes until the EAV at the beginning of the line on when  
FLCOUNT = VBITCLR1 where it changes to 0 (indicating the start of the  
field 1 digital active display). The V bit operation is completely independent of  
the VBLNK control signal.  
The VBITSET1 and VBITCLR1 bits should be programmed so that FLCOUNT  
becomes set to 1 during field 1 vertical blanking. The hardware only starts  
generating field 1 EDMA events when FLCOUNT = 1.  
Figure 4–66. Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1)  
31  
28 27  
16  
0
Reserved  
R-0  
VBITCLR1  
R/W-0  
15  
12 11  
Reserved  
R-0  
VBITSET1  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
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Table 4–32. Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1)  
Field Descriptions  
Description  
†
†
BT.656 and Y/C Mode  
Raw Data Mode  
Bit  
field  
symval  
Value  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
27–16 VBITCLR1 OF(value)  
0–FFFh Specifies the first line with an EAV of Not used.  
V = 0 indicating the start of field 1  
active display.  
15–12 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
11–0 VBITSET1 OF(value)  
0–FFFh Specifies the first line with an EAV of Not used.  
V = 1 indicating the start of field 1  
vertical blanking.  
†
For CSL implementation, use the notation VP_VDVBIT1_field_symval  
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4.12.28 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2)  
The video display field 2 vertical blanking bit register (VDVBIT2) controls the  
V bit in the EAV and SAV timing control words for field 2. The VDVBIT2 is  
shown in Figure 4–67 and described in Table 4–33.  
The VBITSET2 and VBITCLR2 bits control the V bit value in the EAV and SAV  
timing control codes. The V bit is set to 1 (indicating the start of field 2 digital  
vertical blanking) in the EAV code at the beginning of the line whenever the  
frame line counter (FLCOUNT) is equal to VBITSET2. It remains a 1 for all  
EAV/SAV codes until the EAV at the beginning of the line on when  
FLCOUNT = VBITCLR2 where it changes to 0 (indicating the start of the  
field 2 digital active display). The V bit operation is completely independent of  
the VBLNK control signal.  
For correct interlaced operation, the region defined by VBITSET2 and  
VBITCLR2 must not overlap the region defined by VBITSET1 and VBITCLR1.  
For progressive scan operation, VBITSET2 and VBITCLR2 should be  
programmed to a value greater than FRMHEIGHT.  
Figure 4–67. Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2)  
31  
28 27  
16  
0
Reserved  
R-0  
VBITCLR2  
R/W-0  
15  
12 11  
Reserved  
R-0  
VBITSET2  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
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Table 4–33. Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2)  
Field Descriptions  
Description  
†
†
BT.656 and Y/C Mode  
Raw Data Mode  
Bit  
field  
symval  
Value  
31–28 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
27–16 VBITCLR2 OF(value)  
0–FFFh Specifies the first line with an EAV of Not used.  
V = 0 indicating the start of field 2  
active display.  
15–12 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
11–0 VBITSET2 OF(value)  
0–FFFh Specifies the first line with an EAV of Not used.  
V = 1 indicating the start of field 2  
vertical blanking.  
†
For CSL implementation, use the notation VP_VDVBIT2_field_symval  
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Video Display Registers Recommended Values  
4.13 Video Display Registers Recommended Values  
Sample recommended values (decimal) for video display registers for BT.656  
output are given in Table 4–34.  
Table 4–34. Video Display Register Recommended Values  
Register  
Field  
525/60 Value  
625/50 Value  
VDFRMSZ  
FRMWIDTH  
858  
864  
FRMHEIGHT  
HBLNKSTART  
525  
720  
856  
625  
720  
862  
VDHBLNK  
VDVBLKS1  
VDVBLKE1  
VDVBLKS2  
VDVBLKE2  
VDFLDT1  
HBLNKSTOP  
†
720  
†
720  
VBLNKXSTART1  
VBLNKYSTART1  
VBLNKXSTOP1  
†
1
†
624  
†
720  
†
720  
†
20  
†
23  
VBLNKYSTOP1  
†
360  
†
360  
VBLNKXSTART2  
VBLNKYSTART2  
VBLNKXSTOP2  
†
263  
†
311  
†
360  
†
360  
†
283  
†
336  
VBLNKYSTOP2  
†
720  
†
720  
FLD1XSTART  
†
1
†
1
FLD1YSTART  
†
360  
†
360  
VDFLDT2  
FLD2XSTART  
†
263  
†
313  
FLD2YSTART  
VDHSYNC  
VDVSYNS1  
VDVSYNE1  
HSYNCSTART  
736  
800  
732  
782  
HSYNCSTOP  
†
720  
†
720  
VSYNCXSTART1  
VSYNCYSTART1  
VSYNCXSTOP1  
†
4
†
1
†
720  
†
360  
†
7
†
3
VSYNCYSTOP1  
†
Programming only required if external control signal is used.  
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Video Display Registers Recommended Values  
Table 4–34. Video Display Register Recommended Values (Continued)  
Register  
Field  
525/60 Value  
625/50 Value  
†
360  
†
360  
VDVSYNS2  
VSYNCXSTART2  
†
266  
†
313  
VSYNCYSTART2  
†
†
VDVSYNE2  
VDFBIT  
VSYNCXSTOP2  
360  
720  
†
269  
†
316  
VSYNCYSTOP2  
FBITCLR  
4
1
FBITSET  
266  
1
313  
624  
23  
VDVBIT1  
VDVBIT2  
VBITSET1  
VBITCLR1  
VBITSET2  
20  
264  
283  
311  
336  
VBITCLR2  
†
Programming only required if external control signal is used.  
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Video Display FIFO Registers  
4.14 Video Display FIFO Registers  
The display FIFO mapping registers are listed in Table 4–35. These registers  
provide DMA write access to the display FIFOs. These pseudo-registers  
should be mapped into DSP memory space rather than configuration register  
space in order to provide high-speed access. See the device-specific data-  
sheet for the memory address of these registers.  
The function of the video display FIFO mapping registers is listed in  
Table 4–36.  
Table 4–35. Video Display FIFO Registers  
Acronym  
Register Name  
YDSTA  
CBDST  
CRDST  
YDSTB  
Y FIFO Destination Register A  
Cb FIFO Destination Register  
Cr FIFO Destination Register  
Y FIFO Destination Register B  
Table 4–36. Video Display FIFO Registers Function  
Display Mode  
Register  
BT.656 or Y/C  
Raw Data  
YDSTx  
Maps Y display FIFO into the  
DSP memory.  
Maps data display buffer into  
the DSP memory.  
CBDST  
CRDST  
Maps Cb display FIFO into the  
DSP memory.  
Not used.  
Maps Cr display FIFO into the  
DSP memory.  
Not used.  
In BT.656 or Y/C display mode, three DMAs move data from the DSP memory  
to Y, Cb, and Cr display FIFOs by using the memory-mapped YDSTx, CBDST,  
and CRDST registers. The DMA transfers are triggered by the YEVT, CbEVT,  
and CrEVT events, respectively.  
In raw display mode, one DMA channel moves data from the DSP memory to  
the Y display FIFO by using the memory-mapped YDSTx register. The DMA  
transfers are triggered by a YEVT event.  
The video display FIFO registers are write-only locations. Reads of these  
addresses returns arbitrary values and do not affect the status of the display  
FIFOs.  
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Chapter 5  
General Purpose I/O Operation  
Signals not used for video display or video capture can be used as general-  
purpose input/output (GPIO) signals.  
Topic  
Page  
5.1 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2  
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GPIO Registers  
5.1 GPIO Registers  
The GPIO register set includes required registers such as peripheral identifi-  
cation and emulation control. The GPIO registers are listed in Table 5–1. See  
the device-specific datasheet for the memory address of these registers.  
Table 5–1. Video Port Registers  
Acronym  
Register Name  
Section  
VPPID  
Video Port Peripheral Identification Register  
5.1.1  
PCR  
Video Port Power Management Register  
Video Port Pin Function Register  
5.1.2  
5.1.3  
5.1.5  
5.1.6  
5.1.7  
5.1.8  
5.1.8  
5.1.9  
5.1.10  
5.1.11  
5.1.12  
PFUNC  
PDIR  
Video Port GPIO Direction Control Register 0  
Video Port GPIO Data Input Register  
Video Port GPIO Data Output Register  
Video Port GPIO Data Set Register  
PDIN  
PDOUT  
PDSET  
PDCLR  
PIEN  
Video Port GPIO Data Clear Register  
Video Port GPIO Interrupt Enable Register  
Video Port GPIO Interrupt Polarity Register  
Video Port GPIO Interrupt Status Register  
Video Port GPIO Interrupt Clear Register  
PIPOL  
PISTAT  
PICLR  
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5.1.1 Video Port Peripheral Identification Register (VPPID)  
The video port peripheral identification register (VPPID) is a read-only register  
used to store information about the peripheral. The VPPID is shown in  
Figure 5–1 and described in Table 5–2.  
Figure 5–1. Video Port Peripheral Identification Register (VPPID)  
31  
24 23  
16  
0
Reserved  
R-0  
TYPE  
R-0000 0001  
15  
8
7
CLASS  
REVISION  
†
R-0000 1001  
R-x  
Legend: R = Read only; -n = value after reset  
†
See the device-specific datasheet for the default value of this field.  
Table 5–2. Video Port Peripheral Identification Register (VPPID) Field Descriptions  
†
†
Bit  
field  
symval  
Value Description  
31–24 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
Identifies type of peripheral.  
Video port.  
23–16 TYPE  
OF(value)  
OF(value)  
OF(value)  
01h  
09h  
x
15–8 CLASS  
Identifies class of peripheral.  
Video  
7–0  
REVISION  
Identifies revision of peripheral.  
See the device-specific datasheet for the value.  
†
For CSL implementation, use the notation VP_VPPID_field_symval  
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5.1.2 Video Port Peripheral Control Register (PCR)  
The video port peripheral control register (PCR) determines operation during  
emulation. The video port peripheral control register is shown in Figure 5–2  
and described in Table 5–3.  
Normal operation is to not halt the port during emulation suspend. This allows  
a displayed image to remain visible during suspend. However, this will only  
work if one of the continuous capture/display modes is selected because non-  
continuous modes require CPU intervention for DMAs to continue indefinitely  
(and the CPU is halted during emulation suspend).  
When FREE = 0, emulation suspend can occur. Clocks and counters continue  
to run in order to maintain synchronization with external devices. The video  
port waits until a field boundary to halt DMA event generation, so that upon  
restart the video port can begin generating events again at the precise point  
it left off. After exiting suspend, the video port waits for the correct field bound-  
ary to occur and then reenables DMA events. The DMA pointers will be at the  
correct location for capture/display to resume where it left off. The emulation  
suspend operation is similar to the BLKCAP or BLKDISP operation with the  
difference being that BLKCAP and BLKDISP operations take effect immedi-  
ately rather than at field completion and rely on you to reset the DMA mecha-  
nism before they are cleared.  
There is no separate emulation suspend mechanism on the video capture  
side. The field and frame operation (see Table 3–6 on page 3-18) can be used  
as emulation suspend.  
Figure 5–2. Video Port Peripheral Control Register (PCR)  
31  
16  
Reserved  
R-0  
15  
3
2
1
0
Reserved  
R-0  
PEREN SOFT FREE  
R/W-0  
R-0  
R/W-1  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
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Table 5–3. Video Port Peripheral Control Register (PCR) Field Descriptions  
†
†
Bit  
field  
symval  
Value Description  
31–3 Reserved  
Reserved. The reserved bit location is always read as 0. A value  
written to this field has no effect.  
2
PEREN  
Peripheral enable bit.  
DISABLE  
ENABLE  
0
1
Video port is disabled. Port clock (VCLK1, VCLK2, STCLK) inputs  
are gated off to save power. DMA access to the video port is still  
acknowledged but indeterminate read data is returned and write  
data is discarded.  
Video port is enabled.  
1
SOFT  
Soft bit enable mode bit. This bit is used in conjunction with FREE  
bit to determine state of video port clock during emulation suspend.  
This bit has no effect if FREE = 1.  
STOP  
0
1
The current field is completed upon emulation suspend. After  
completion, no new DMA events are generated. The port clocks  
and counters continue to run in order to maintain synchronization.  
No interrupts are generated. If the port is in display mode, video  
control signals continue to be output and the default data value is  
output during the active video window.  
COMP  
SOFT  
Is not defined for this peripheral; the bit is hardwired to 0.  
0
FREE  
Free-running enable mode bit. This bit is used in conjunction with  
SOFT bit to determine state of video port during emulation suspend.  
0
1
Free-running mode is disabled. During emulation suspend, SOFT  
bit determines operation of video port.  
Free-running mode is enabled. Video port ignores the emulation  
suspend signal and continues to function as normal.  
†
For CSL implementation, use the notation VP_PCR_field_symval  
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5.1.3 Video Port Pin Function Register (PFUNC)  
The video port pin function register (PFUNC) selects the video port pins as  
GPIO. The PFUNC is shown in Figure 5–3 and described in Table 5–4. Each  
bit controls either one pin or a set of pins. When a bit is set to 1, it enables the  
pin(s) that map to it as GPIO. The GPIO feature should not be used for pins  
that are used as part of the capture or display operation. For pins that have  
been muxed out for use by another peripheral, the PFUNC bits will have no  
effect.  
The VDATA pins are broken into two functional groups: VDATA[9–0] and  
VDATA[19–10]. Thus, each entire half of the data bus must be configured as  
either functional pins or GPIO pins. In the case of single BT.656 or raw 8/10-bit  
mode, the upper 10 VDATA pins (VDATA[19–10]) can be used as GPIOs. If the  
video port is disabled, all pins can be used as GPIO.  
Figure 5–3. Video Port Pin Function Register (PFUNC)  
31  
23  
22  
21  
20  
19  
16  
Reserved  
R-0  
PFUNC22 PFUNC21 PFUNC20  
Reserved  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
15  
11  
10  
9
1
0
Reserved  
R-0  
PFUNC10  
R/W-0  
Reserved  
R-0  
PFUNC0  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 5–4. Video Port Pin Function Register (PFUNC) Field Descriptions  
†
†
Bit  
field  
symval  
Value Description  
31–23 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
22  
21  
PFUNC22  
PFUNC21  
PFUNC22 bit determines if VCTL3 pin functions as GPIO.  
Pin functions normally.  
NORMAL  
VCTL3  
0
1
Pin functions as GPIO pin.  
PFUNC21 bit determines if VCTL2 pin functions as GPIO.  
Pin functions normally.  
NORMAL  
VCTL2  
0
1
Pin functions as GPIO pin.  
†
For CSL implementation, use the notation VP_PFUNC_field_symval  
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Table 5–4. Video Port Pin Function Register (PFUNC) Field Descriptions (Continued)  
†
†
Bit  
field  
symval  
Value Description  
20  
PFUNC20  
PFUNC20 bit determines if VCTL1 pin functions as GPIO.  
Pin functions normally.  
NORMAL  
VCTL1  
–
0
1
0
Pin functions as GPIO pin.  
19–11 Reserved  
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
10  
PFUNC10  
PFUNC10 bit determines if VDATA[19–10] pins function as  
GPIO.  
NORMAL  
0
1
0
Pins function normally.  
VDATA10TO19  
Pins function as GPIO pin.  
9–1  
Reserved  
PFUNC0  
–
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
0
PFUNC0 bit determines if VDATA[9–0] pins function as  
GPIO.  
NORMAL  
0
1
Pins function normally.  
VDATA0TO9  
Pins function as GPIO pin.  
†
For CSL implementation, use the notation VP_PFUNC_field_symval  
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5.1.4 Video Port Pin Direction Register (PDIR)  
The video port pin direction register (PDIR) is shown in Figure 5–4 and  
described in Table 5–5. The PDIR controls the direction of IO pins in the video  
port for those pins set by PFUNC. If a bit is set to 1, the relevant pin or pin group  
acts as an output. If a bit is cleared to 0, the pin or pin group functions as an  
input. The PDIR settings do not affect pins where the corresponding PFUNC  
bit is not set.  
Figure 5–4. Video Port Pin Direction Register (PDIR)  
31  
24  
Reserved  
R-0  
23  
22  
21  
20  
19  
17  
16  
Reserved  
R-0  
PDIR22  
R/W-0  
PDIR21  
R/W-0  
PDIR20  
R/W-0  
Reserved  
R-0  
PDIR16  
R/W-0  
15  
13  
12  
11  
Reserved  
R-0  
10  
9
8
Reserved  
R-0  
PDIR12  
R/W-0  
PDIR10  
R/W-0  
Reserved  
R-0  
PDIR8  
R/W-0  
7
5
4
3
1
0
Reserved  
R-0  
PDIR4  
R/W-0  
Reserved  
R-0  
PDIR0  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 5–5. Video Port Pin Direction Register (PDIR) Field Descriptions  
†
†
Bit  
field  
symval  
Value Description  
31–23 Reserved  
–
0
Reserved. The reserved bit location is always read as 0.  
A value written to this field has no effect.  
22  
PDIR22  
PDIR22 bit controls the direction of the VCTL3 pin.  
Pin functions as input.  
VCTL3IN  
0
1
VCTL3OUT  
Pin functions as output.  
†
For CSL implementation, use the notation VP_PDIR_field_symval  
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Table 5–5. Video Port Pin Direction Register (PDIR) Field Descriptions (Continued)  
†
†
Bit  
field  
symval  
Value Description  
PDIR21 bit controls the direction of the VCTL2 pin.  
21  
PDIR21  
VCTL2IN  
0
1
Pin functions as input.  
Pin functions as output.  
VCTL2OUT  
20  
PDIR20  
PDIR20 bit controls the direction of the VCTL1 pin.  
Pin functions as input.  
VCTL1IN  
VCTL1OUT  
–
0
1
0
Pin functions as output.  
19–17 Reserved  
Reserved. The reserved bit location is always read as 0.  
A value written to this field has no effect.  
16  
PDIR16  
PDIR16 bit controls the direction of the VDATA[19–16]  
pins.  
VDATA16TO19IN  
VDATA16TO19OUT  
–
0
1
0
Pins function as input.  
Pins function as output.  
15–13 Reserved  
Reserved. The reserved bit location is always read as 0.  
A value written to this field has no effect.  
12  
PDIR12  
PDIR12 bit controls the direction of the VDATA[15–12]  
pins.  
VDATA12TO15IN  
VDATA12TO15OUT  
–
0
1
0
Pins function as input.  
Pins function as output.  
11  
10  
Reserved  
PDIR10  
Reserved. The reserved bit location is always read as 0.  
A value written to this field has no effect.  
PDIR10 bit controls the direction of the VDATA[11–10]  
pins.  
VDATA10TO11IN  
VDATA10TO11OUT  
–
0
1
0
Pins function as input.  
Pins function as output.  
9
Reserved  
Reserved. The reserved bit location is always read as 0.  
A value written to this field has no effect.  
†
For CSL implementation, use the notation VP_PDIR_field_symval  
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Table 5–5. Video Port Pin Direction Register (PDIR) Field Descriptions (Continued)  
†
†
Bit  
field  
symval  
Value Description  
PDIR8 bit controls the direction of the VDATA[9–8] pins.  
8
PDIR8  
VDATA8TO9IN  
VDATA8TO9OUT  
–
0
1
0
Pins function as input.  
Pins function as output.  
7–5  
Reserved  
PDIR4  
Reserved. The reserved bit location is always read as 0.  
A value written to this field has no effect.  
4
PDIR4 bit controls the direction of the VDATA[7–4] pins.  
Pins function as input.  
VDATA4TO7IN  
VDATA4TO7OUT  
–
0
1
0
Pins function as output.  
3–1  
Reserved  
PDIR0  
Reserved. The reserved bit location is always read as 0.  
A value written to this field has no effect.  
0
PDIR0 bit controls the direction of the VDATA[3–0] pins.  
Pins function as input.  
VDATA0TO3IN  
0
1
VDATA0TO3OUT  
Pins function as output.  
†
For CSL implementation, use the notation VP_PDIR_field_symval  
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5.1.5 Video Port Pin Data Input Register (PDIN)  
The read-only video port pin data input register (PDIN) is shown in Figure 5–5  
and described in Table 5–6. PDIN reflects the state of the video port pins.  
When read, PDIN returns the value from the pin’s input buffer (with appropriate  
synchronization) regardless of the state of the corresponding PFUNC or PDIR  
bit.  
Figure 5–5. Video Port Pin Data Input Register (PDIN)  
31  
24  
Reserved  
R-0  
23  
22  
PDIN22  
R-0  
21  
PDIN21  
R-0  
20  
19  
PDIN19  
R-0  
18  
PDIN18  
R-0  
17  
PDIN17  
R-0  
16  
Reserved  
R-0  
PDIN20  
R-0  
PDIN16  
R-0  
15  
PDIN15  
R-0  
14  
PDIN14  
R-0  
13  
PDIN13  
R-0  
12  
PDIN12  
R-0  
11  
PDIN11  
R-0  
10  
PDIN10  
R-0  
9
8
PDIN9  
R-0  
PDIN8  
R-0  
7
6
5
4
3
2
1
0
PDIN7  
R-0  
PDIN6  
R-0  
PDIN5  
R-0  
PDIN4  
R-0  
PDIN3  
R-0  
PDIN2  
R-0  
PDIN1  
R-0  
PDIN0  
R-0  
Legend: R = Read only; -n = value after reset  
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Table 5–6. Video Port Pin Data Input Register (PDIN) Field Descriptions  
†
†
Bit  
field  
symval  
Value Description  
31–23 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
PDIN22 bit returns the logic level of the VCTL3 pin.  
Pin is logic low.  
22  
21  
20  
PDIN22  
PDIN21  
PDIN20  
VCTL3LO  
VCTL3HI  
0
1
Pin is logic high.  
PDIN21 bit returns the logic level of the VCTL2 pin.  
Pin is logic low.  
VCTL2LO  
VCTL2HI  
0
1
Pin is logic high.  
PDIN20 bit returns the logic level of the VCTL1 pin.  
Pin is logic low.  
VCTL1LO  
VCTL1HI  
0
1
Pin is logic high.  
19–0 PDIN[19–0]  
PDIN[19–0] bit returns the logic level of the corresponding  
VDATA[n] pin.  
VDATAnLO  
0
1
Pin is logic low.  
Pin is logic high.  
VDATAnHI  
†
For CSL implementation, use the notation VP_PDIN_PDINn_symval  
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5.1.6 Video Port Pin Data Output Register (PDOUT)  
The video port pin data output register (PDOUT) is shown in Figure 5–6 and  
described in Table 5–7. The bits of PDOUT determine the value driven on the  
corresponding GPIO pin, if the pin is configured as an output. Writes do not  
affect pins not configured as GPIO outputs. The bits in PDOUT are set or  
cleared by writing to this register directly. A read of PDOUT returns the value  
of the register not the value at the pin (that might be configured as an input).  
An alternative way to set bits in PDOUT is to write a 1 to the corresponding bit  
of PDSET. An alternative way to clear bits in PDOUT is to write a 1 to the corre-  
sponding bit of PDCLR.  
PDOUT has these aliases:  
- PDSET — writing a 1 to a bit in PDSET sets the corresponding bit in  
PDOUT to 1; writing a 0 has no effect and keeps the bits in PDOUT  
unchanged.  
- PDCLR — writing a 1 to a bit in PDCLR clears the corresponding bit in  
PDOUT to 0; writing a 0 has no effect and keeps the bits in PDOUT  
unchanged.  
Figure 5–6. Video Port Pin Data Output Register (PDOUT)  
31  
24  
Reserved  
R-0  
23  
22  
21  
20  
19  
18  
17  
16  
Reserved  
R-0  
PDOUT22  
R/W-0  
PDOUT21  
R/W-0  
PDOUT20  
R/W-0  
PDOUT19  
R/W-0  
PDOUT18  
R/W-0  
PDOUT17  
R/W-0  
PDOUT16  
R/W-0  
15  
14  
13  
12  
11  
10  
9
8
PDOUT15  
R/W-0  
PDOUT14  
R/W-0  
PDOUT13  
R/W-0  
PDOUT12  
R/W-0  
PDOUT11  
R/W-0  
PDOUT10  
R/W-0  
PDOUT9  
R/W-0  
PDOUT8  
R/W-0  
7
6
5
4
3
2
1
0
PDOUT7  
R/W-0  
PDOUT6  
R/W-0  
PDOUT5  
R/W-0  
PDOUT4  
R/W-0  
PDOUT3  
R/W-0  
PDOUT2  
R/W-0  
PDOUT1  
R/W-0  
PDOUT0  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
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Table 5–7. Video Port Pin Data Out Register (PDOUT) Field Descriptions  
†
†
Bit  
field  
symval  
Value Description  
31–23 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
22  
21  
20  
PDOUT22  
PDOUT21  
PDOUT20  
PDOUT22 bit drives the VCTL3 pin only when the GPIO is  
configured as output.  
When reading data, returns the bit value in PDOUT22,  
does not return input from pin. When writing data, writes to  
PDOUT22 bit.  
VCTL3LO  
VCTL3HI  
0
1
Pin drives low.  
Pin drives high.  
PDOUT21 bit drives the VCTL2 pin only when the GPIO is  
configured as output.  
When reading data, returns the bit value in PDOUT21,  
does not return input from pin. When writing data, writes to  
PDOUT21 bit.  
VCTL2LO  
VCTL2HI  
0
1
Pin drives low.  
Pin drives high.  
PDOUT20 bit drives the VCTL1 pin only when the GPIO is  
configured as output.  
When reading data, returns the bit value in PDOUT20,  
does not return input from pin. When writing data, writes to  
PDOUT20 bit.  
VCTL1LO  
VCTL1HI  
0
1
Pin drives low.  
Pin drives high.  
19–0 PDOUT[19–0]  
PDOUT[19–0] bit drives the corresponding VDATA[19–0]  
pin only when the GPIO is configured as output.  
When reading data, returns the bit value in PDOUT[n],  
does not return input from pin. When writing data, writes to  
PDOUT[n] bit.  
VDATAnLO  
0
1
Pin drives low.  
Pin drives high.  
VDATAnHI  
†
For CSL implementation, use the notation VP_PDOUT_PDOUTn_symval  
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5.1.7 Video Port Pin Data Set Register (PDSET)  
The video port pin data set register (PDSET) is shown in Figure 5–7 and  
described in Table 5–8. PDSET is an alias of the video port pin data output reg-  
ister (PDOUT) for writes only and provides an alternate means of driving GPIO  
outputs high. Writing a 1 to a bit of PDSET sets the corresponding bit in  
PDOUT. Writing a 0 has no effect. Register reads return all 0s.  
Figure 5–7. Video Port Pin Data Set Register (PDSET)  
31  
24  
Reserved  
R-0  
23  
22  
PDSET22  
W-0  
21  
PDSET21  
W-0  
20  
19  
PDSET19  
W-0  
18  
PDSET18  
W-0  
17  
PDSET17  
W-0  
16  
Reserved  
R-0  
PDSET20  
W-0  
PDSET16  
W-0  
15  
PDSET15  
W-0  
14  
PDSET14  
W-0  
13  
PDSET13  
W-0  
12  
PDSET12  
W-0  
11  
PDSET11  
W-0  
10  
PDSET10  
W-0  
9
8
PDSET9  
W-0  
PDSET8  
W-0  
7
6
5
4
3
2
1
0
PDSET7  
W-0  
PDSET6  
W-0  
PDSET5  
W-0  
PDSET4  
W-0  
PDSET3  
W-0  
PDSET2  
W-0  
PDSET1  
W-0  
PDSET0  
W-0  
Legend: R = Read only; W = Write only; -n = value after reset  
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Table 5–8. Video Port Pin Data Set Register (PDSET) Field Descriptions  
†
†
Bit  
field  
symval  
Value Description  
31–23 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
22  
21  
20  
PDSET22  
PDSET21  
PDSET20  
Allows PDOUT22 bit to be set to a logic high without affect-  
ing other I/O pins controlled by the same port.  
NONE  
0
1
No effect.  
VCTL3HI  
Sets PDOUT22 (VCTL3) bit to 1.  
Allows PDOUT21 bit to be set to a logic high without affect-  
ing other I/O pins controlled by the same port.  
NONE  
0
1
No effect.  
VCTL2HI  
Sets PDOUT21 (VCTL2) bit to 1.  
Allows PDOUT20 bit to be set to a logic high without affect-  
ing other I/O pins controlled by the same port.  
NONE  
0
1
No effect.  
VCTL1HI  
Sets PDOUT20 (VCTL1) bit to 1.  
19–0 PDSET[19–0]  
Allows PDOUT[19–0] bit to be set to a logic high without  
affecting other I/O pins controlled by the same port.  
NONE  
0
1
No effect.  
VDATAnHI  
Sets PDOUT[n] (VDATA[n]) bit to 1.  
†
For CSL implementation, use the notation VP_PDSET_PDSETn_symval  
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5.1.8 Video Port Pin Data Clear Register (PDCLR)  
The video port pin data clear register (PDCLR) is shown in Figure 5–8 and  
described in Table 5–9. PDCLRisanaliasofthevideoportpindataoutputreg-  
ister (PDOUT) for writes only and provides an alternate means of driving GPIO  
outputs low. Writing a 1 to a bit of PDCLR clears the corresponding bit in  
PDOUT. Writing a 0 has no effect. Register reads return all 0s.  
Figure 5–8. Video Port Pin Data Clear Register (PDCLR)  
31  
24  
Reserved  
R-0  
23  
22  
PDCLR22  
W-0  
21  
PDCLR21  
W-0  
20  
19  
PDCLR19  
W-0  
18  
PDCLR18  
W-0  
17  
PDCLR17  
W-0  
16  
Reserved  
R-0  
PDCLR20  
W-0  
PDCLR16  
W-0  
15  
PDCLR15  
W-0  
14  
PDCLR14  
W-0  
13  
PDCLR13  
W-0  
12  
PDCLR12  
W-0  
11  
PDCLR11  
W-0  
10  
PDCLR10  
W-0  
9
8
PDCLR9  
W-0  
PDCLR8  
W-0  
7
6
5
4
3
2
1
0
PDCLR7  
W-0  
PDCLR6  
W-0  
PDCLR5  
W-0  
PDCLR4  
W-0  
PDCLR3  
W-0  
PDCLR2  
W-0  
PDCLR1  
W-0  
PDCLR0  
W-0  
Legend: R = Read only; W = Write only; -n = value after reset  
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Table 5–9. Video Port Pin Data Clear Register (PDCLR) Field Descriptions  
†
†
Bit  
field  
symval  
Value Description  
31–23 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
22  
21  
20  
PDCLR22  
PDCLR21  
PDCLR20  
Allows PDOUT22 bit to be cleared to a logic low without  
affecting other I/O pins controlled by the same port.  
NONE  
0
1
No effect.  
VCTL3CLR  
Clears PDOUT22 (VCTL3) bit to 0.  
Allows PDOUT21 bit to be cleared to a logic low without  
affecting other I/O pins controlled by the same port.  
NONE  
0
1
No effect.  
VCTL2CLR  
Clears PDOUT21 (VCTL2) bit to 0.  
Allows PDOUT20 bit to be cleared to a logic low without  
affecting other I/O pins controlled by the same port.  
NONE  
0
1
No effect.  
VCTL1CLR  
Clears PDOUT20 (VCTL1) bit to 0.  
19–0 PDCLR[19–0]  
Allows PDOUT[19–0] bit to be cleared to a logic low without  
affecting other I/O pins controlled by the same port.  
NONE  
0
1
No effect.  
VDATAnCLR  
Clears PDOUT[n] (VDATA[n]) bit to 0.  
†
For CSL implementation, use the notation VP_PDCLR_PDCLRn_symval  
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5.1.9 Video Port Pin Interrupt Enable Register (PIEN)  
The video port pin interrupt enable register (PIEN) is shown in Figure 5–9 and  
described in Table 5–10. The GPIOs can be used to generate DSP interrupts  
or DMA events. The PIEN selects which pins may be used to generate an  
interrupt. Only pins whose corresponding bits in PIEN are set may cause their  
corresponding PISTAT bit to be set.  
Interrupts are enabled on a GPIO pin when the corresponding bit in PIEN is  
set, thepinisenabledforGPIOinPFUNC, andthepinisconfiguredasaninput  
in PDIR.  
Figure 5–9. Video Port Pin Interrupt Enable Register (PIEN)  
31  
24  
Reserved  
R-0  
23  
22  
21  
20  
19  
18  
17  
16  
Reserved  
R-0  
PIEN22  
R/W-0  
PIEN21  
R/W-0  
PIEN20  
R/W-0  
PIEN19  
R/W-0  
PIEN18  
R/W-0  
PIEN17  
R/W-0  
PIEN16  
R/W-0  
15  
14  
13  
12  
11  
10  
9
8
PIEN15  
R/W-0  
PIEN14  
R/W-0  
PIEN13  
R/W-0  
PIEN12  
R/W-0  
PIEN11  
R/W-0  
PIEN10  
R/W-0  
PIEN9  
R/W-0  
PIEN8  
R/W-0  
7
6
5
4
3
2
1
0
PIEN7  
R/W-0  
PIEN6  
R/W-0  
PIEN5  
R/W-0  
PIEN4  
R/W-0  
PIEN3  
R/W-0  
PIEN2  
R/W-0  
PIEN1  
R/W-0  
PIEN0  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
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GPIO Registers  
Table 5–10. Video Port Pin Interrupt Enable Register (PIEN) Field Descriptions  
†
†
Bit  
field  
symval  
Value Description  
31–23 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
PIEN22 bit enables the interrupt on the VCTL3 pin.  
Interrupt is disabled.  
22  
21  
20  
PIEN22  
PIEN21  
PIEN20  
VCTL3LO  
VCTL3HI  
0
1
Pin enables the interrupt.  
PIEN21 bit enables the interrupt on the VCTL2 pin.  
Interrupt is disabled.  
VCTL2LO  
VCTL2HI  
0
1
Pin enables the interrupt.  
PIEN20 bit enables the interrupt on the VCTL1 pin.  
Interrupt is disabled.  
VCTL1LO  
VCTL1HI  
0
1
Pin enables the interrupt.  
19–0 PIEN[19–0]  
PIEN[19–0] bits enable the interrupt on the corresponding  
VDATA[n] pin.  
VDATAnLO  
0
1
Interrupt is disabled.  
VDATAnHI  
Pin enables the interrupt.  
†
For CSL implementation, use the notation VP_PIEN_PIENn_symval  
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5.1.10 Video Port Pin Interrupt Polarity Register (PIPOL)  
The video port pin interrupt polarity register (PIPOL) is shown in Figure 5–10  
and described in Table 5–11. The PIPOL determines the GPIO pin signal  
polarity that generates an interrupt.  
Figure 5–10. Video Port Pin Interrupt Polarity Register (PIPOL)  
31  
24  
Reserved  
R-0  
23  
22  
21  
20  
19  
18  
17  
16  
Reserved  
R-0  
PIPOL22  
R/W-0  
PIPOL21  
R/W-0  
PIPOL20  
R/W-0  
PIPOL19  
R/W-0  
PIPOL18  
R/W-0  
PIPOL17  
R/W-0  
PIPOL16  
R/W-0  
15  
14  
13  
12  
11  
10  
9
8
PIPOL15  
R/W-0  
PIPOL14  
R/W-0  
PIPOL13  
R/W-0  
PIPOL12  
R/W-0  
PIPOL11  
R/W-0  
PIPOL10  
R/W-0  
PIPOL9  
R/W-0  
PIPOL8  
R/W-0  
7
6
5
4
3
2
1
0
PIPOL7  
R/W-0  
PIPOL6  
R/W-0  
PIPOL5  
R/W-0  
PIPOL4  
R/W-0  
PIPOL3  
R/W-0  
PIPOL2  
R/W-0  
PIPOL1  
R/W-0  
PIPOL0  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
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GPIO Registers  
Table 5–11. Video Port Pin Interrupt Polarity Register (PIPOL) Field Descriptions  
†
†
Bit  
field  
symval  
Value Description  
31–23 Reserved  
–
0
Reserved. The reserved bit location is always read as 0.  
A value written to this field has no effect.  
22  
21  
20  
PIPOL22  
PIPOL21  
PIPOL20  
PIPOL22 bit determines the VCTL3 pin signal polarity  
that generates an interrupt.  
VCTL3ACTHI  
VCTL3ACTLO  
0
1
Interrupt is caused by a low-to-high transition on the  
VCTL3 pin.  
Interrupt is caused by a high-to-low transition on the  
VCTL3 pin.  
PIPOL21 bit determines the VCTL2 pin signal polarity  
that generates an interrupt.  
VCTL2ACTHI  
VCTL2ACTLO  
0
1
Interrupt is caused by a low-to-high transition on the  
VCTL2 pin.  
Interrupt is caused by a high-to-low transition on the  
VCTL2 pin.  
PIPOL20 bit determines the VCTL1 pin signal polarity  
that generates an interrupt.  
VCTL1ACTHI  
VCTL1ACTLO  
0
1
Interrupt is caused by a low-to-high transition on the  
VCTL1 pin.  
Interrupt is caused by a high-to-low transition on the  
VCTL1 pin.  
19–0 PIPOL[19–0]  
PIPOL[19–0] bit determines the corresponding VDATA[n]  
pin signal polarity that generates an interrupt.  
VDATAnACTHI  
0
1
Interrupt is caused by a low-to-high transition on the  
VDATA[n] pin.  
VDATAnACTLO  
Interrupt is caused by a high-to-low transition on the  
VDATA[n] pin.  
†
For CSL implementation, use the notation VP_PIPOL_PIPOLn_symval  
5-22  
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5.1.11 Video Port Pin Interrupt Status Register (PISTAT)  
The video port pin interrupt status register (PISTAT) is shown in Figure 5–11  
and described in Table 5–12. PISTAT is a read-only register that indicates the  
GPIO pin that has a pending interrupt.  
A bit in PISTAT is set when the corresponding GPIO pin is configured as an  
interrupt (the corresponding bit in PIEN is set, the pin is enabled for GPIO in  
PFUNC, and the pin is configured as an input in PDIR) and the appropriate  
transition (as selected by the corresponding PIPOL bit) occurs on the pin.  
Whenever a PISTAT bit is set to 1, the GPIO bit in VPIS is set. The PISTAT bits  
are cleared by writing a 1 to the corresponding bit in PICLR. Writing a 0 has  
no effect. Clearing all the PISTAT bits does not clear the GPIO bit in VPIS, it  
must be explicitly cleared. If any bits in PISTAT are still set when the GPIO bit  
is cleared, the GPIO bit is set again.  
Figure 5–11.Video Port Pin Interrupt Status Register (PISTAT)  
31  
24  
Reserved  
R-0  
23  
22  
PISTAT22  
R-0  
21  
PISTAT21  
R-0  
20  
19  
PISTAT19  
R-0  
18  
PISTAT18  
R-0  
17  
PISTAT17  
R-0  
16  
Reserved  
R-0  
PISTAT20  
R-0  
PISTAT16  
R-0  
15  
PISTAT15  
R-0  
14  
PISTAT14  
R-0  
13  
PISTAT13  
R-0  
12  
PISTAT12  
R-0  
11  
PISTAT11  
R-0  
10  
PISTAT10  
R-0  
9
8
PISTAT9  
R-0  
PISTAT8  
R-0  
7
6
5
4
3
2
1
0
PISTAT7  
R-0  
PISTAT6  
R-0  
PISTAT5  
R-0  
PISTAT4  
R-0  
PISTAT3  
R-0  
PISTAT2  
R-0  
PISTAT1  
R-0  
PISTAT0  
R-0  
Legend: R = Read only; -n = value after reset  
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GPIO Registers  
Table 5–12. Video Port Pin Interrupt Status Register (PISTAT) Field Descriptions  
†
†
Bit  
field  
symval  
Value Description  
31–23 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
22  
21  
20  
PISTAT22  
PISTAT21  
PISTAT20  
PISTAT22 bit indicates if there is a pending interrupt on the  
VCTL3 pin.  
NONE  
0
1
No pending interrupt on the VCTL3 pin.  
Pending interrupt on the VCTL3 pin.  
VCTL3INT  
PISTAT21 bit indicates if there is a pending interrupt on the  
VCTL2 pin.  
NONE  
0
1
No pending interrupt on the VCTL2 pin.  
Pending interrupt on the VCTL2 pin.  
VCTL2INT  
PISTAT20 bit indicates if there is a pending interrupt on the  
VCTL1 pin.  
NONE  
0
1
No pending interrupt on the VCTL1 pin.  
Pending interrupt on the VCTL1 pin.  
VCTL1INT  
19–0 PISTAT[19–0]  
PISTAT[19–0] bit indicates if there is a pending interrupt on  
the corresponding VDATA[n] pin.  
NONE  
0
1
No pending interrupt on the VDATA[n] pin.  
VDATAnINT  
Pending interrupt on the VDATA[n] pin.  
†
For CSL implementation, use the notation VP_PISTAT_PISTATn_symval  
5-24  
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GPIO Registers  
5.1.12 Video Port Pin Interrupt Clear Register (PICLR)  
The video port pin interrupt clear register (PICLR) is shown in Figure 5–12 and  
described in Table 5–13. PICLR is an alias of the video port pin interrupt status  
register (PISTAT) for writes only. Writing a 1 to a bit of PICLR clears the corre-  
sponding bit in PISTAT. Writing a 0 has no effect. Register reads return all 0s.  
Figure 5–12. Video Port Pin Interrupt Clear Register (PICLR)  
31  
24  
Reserved  
R-0  
23  
22  
PICLR22  
W-0  
21  
PICLR21  
W-0  
20  
19  
PICLR19  
W-0  
18  
PICLR18  
W-0  
17  
PICLR17  
W-0  
16  
Reserved  
R-0  
PICLR20  
W-0  
PICLR16  
W-0  
15  
PICLR15  
W-0  
14  
PICLR14  
W-0  
13  
PICLR13  
W-0  
12  
PICLR12  
W-0  
11  
10  
PICLR10  
W-0  
9
8
PICLR11  
W-0  
PICLR9  
W-0  
PICLR8  
W-0  
7
6
5
4
3
2
1
0
PICLR7  
W-0  
PICLR6  
W-0  
PICLR5  
W-0  
PICLR4  
W-0  
PICLR3  
W-0  
PICLR2  
W-0  
PICLR1  
W-0  
PICLR0  
W-0  
Legend: R = Read only; W = Write only; -n = value after reset  
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GPIO Registers  
Table 5–13. Video Port Pin Interrupt Clear Register (PICLR) Field Descriptions  
†
†
Bit  
field  
symval  
Value Description  
31–23 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
Allows PISTAT22 bit to be cleared to a logic low.  
No effect.  
22  
21  
20  
PICLR22  
PICLR21  
PICLR20  
NONE  
0
1
VCTL3CLR  
Clears PISTAT22 (VCTL3) bit to 0.  
Allows PISTAT21 bit to be cleared to a logic low.  
No effect.  
NONE  
0
1
VCTL2CLR  
Clears PISTAT21 (VCTL2) bit to 0.  
Allows PISTAT20 bit to be cleared to a logic low.  
No effect.  
NONE  
0
1
VCTL1CLR  
Clears PISTAT20 (VCTL1) bit to 0.  
Allows PISTAT[19–0] bit to be cleared to a logic low.  
No effect.  
19–0 PICLR[19–0]  
NONE  
0
1
VDATAnCLR  
Clears PISTAT[n] (VDATA[n]) bit to 0.  
†
For CSL implementation, use the notation VP_PICLR_PICLRn_symval  
5-26  
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Chapter 6  
VCXO Interpolated Control Port  
ThischapterprovidesanoverviewoftheVCXOinterpolatedcontrol(VIC)port.  
Topic  
Page  
6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2  
6.2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3  
6.3 Operational Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3  
6.4 Enabling VIC Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5  
6.5 VIC Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5  
6-1  
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Overview  
6.1 Overview  
The VCXO interpolated control (VIC) port provides single-bit interpolated  
VCXOcontrolwithresolutionfrom9bitstoupto16bits. Thefrequencyofinter-  
polation is dependent on the resolution needed.  
When the video port is used in transport stream interface (TSI) mode, the VIC  
port is used to control the system clock, VCXO, for MPEG transport stream  
(Figure 6–1).  
The VIC port supports following features:  
- Single-bit interpolated VCXO control  
- Programmable precision from 9 to 16 bits  
Figure 6–1. TSI System Block Diagram  
VDATA[7–0] (TSI data in)  
Satellite/  
cable  
decoder  
with  
FEC  
VCLK1 (TSI clock)  
VCTL1 (CAPENA)  
VCTL2 (PACSTRT)  
VCTL3 (PACERR)  
Video  
port A  
5V DC  
2.2 KΩ  
DSP  
VCXO  
27 MHz  
22 KΩ  
VCTL  
0.1  
µF  
VIC  
100 pF  
STCLK  
6-2  
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Interface / Operational Details  
6.2 Interface  
The pin list for VIC port is shown in Table 6–1 (pins are 3.3V I/Os).  
Table 6–1. VIC Port Interface Signals  
VIC Port Signal  
Direction Description  
VCTL  
Output  
Input  
VCXO control  
STCLK  
System time clock  
6.3 Operational Details  
Synchronization is an important aspect of decoding and presenting data in  
real-time digital data delivery systems. This is addressed in the MPEG trans-  
port packets by transmitting timing information in the adaptation fields of  
selected data packets. This serves as a reference for timing comparison in the  
receiving system. A sample of the 27-MHz clock, the program clock reference  
(PCR) header is shown in Figure 6–2, is transmitted within the bit stream,  
which indicates the expected time at the completion of reading the field from  
the bit stream at the transport decoder. The sample is a 42-bit field, 9 bits cycle  
from 0 to 299 at 27 MHz, while the other 33-bit field is incremented by 1 each  
time the 9-bit field reaches a value of 299. The transport data packets are in  
sync with the server system clock.  
Figure 6–2. Program Clock Reference (PCR) Header Format  
47  
15 14  
9
8
0
PCR  
Reserved  
PCR extension  
The video port in conjunction with the VIC port uses a combined hardware and  
software solution to synchronize the transport system time clock (STC) with  
the clock reference transmitted in the bitstream.  
The video port maintains a hardware counter that counts the system time. The  
counter is driven by system time clock (STCLK) input driven by an external  
VCXO, controlled by the VIC port.  
On reception of a packet, the video port captures a snapshot of the counter.  
Software uses this timestamp to determine the deviation of the system time  
clock from the server clock, and drives VCTL output of the VIC port to keep it  
synchronized.  
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Operational Details  
Any time a packet with a PCR is received, the timestamp for that packet is  
compared with the PCR value in software. A PLL is implemented in software  
to synchronize the STCLK with the system time clock. The DSP updates the  
VIC input register (VICIN) using the output from this algorithm, which in turn  
drives the VCTL output that controls the system time clock VCXO.  
If f is the frequency of PCRs in the incoming bit stream, the interpolation rate  
R of the VCTL output is given in Equation 6–1, where k is determined by the  
precision β specified by you.  
Equation 6–1. Relationship Between Interpolation Rate and Input Frequency  
R + kf  
Equation 6–2 gives the relation between k and the precision β.  
Equation 6–2. Relationship of Frequency Multiplier to Precision  
3
2
b
2
Ǹ
k u ( (p (2 * 1) )ń3)  
Table 6–2 gives some k and R values for different β’s with f fixed at 40 kHz.  
Once a suitable interpolation frequency is determined, the clock divider can  
be set.  
Table 6–2. Example Values for Interpolation Rate  
β
k
R
9
96.0  
3.8 MHz  
10  
11  
12  
13  
14  
15  
16  
151.0  
240.0  
381.0  
605.0  
960.0  
1523.0  
2418.0  
6.0 MHz  
9.6 MHz  
15.2 MHz  
24.2 MHz  
38.4 MHz  
60.9 MHz  
96.7 MHz  
6-4  
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Enabling VIC Port / VIC Port Registers  
6.4 Enabling VIC Port  
Perform the following steps to enable the VIC port.  
1) Clear the GO bit in the VIC control register (VICCTL) to 0.  
2) Set the PRECISION bits in VICCTL to the desired precision.  
3) Set the VIC clock divider register (VICDIV) bits to appropriate value based  
on the precision and interpolation frequency.  
4) Set the GO bit in VICCTL to 1.  
5) The VIC input register (VICIN) is written into every time a new input code  
is available for interpolation. Repeat step 3 as often as needed.  
6.5 VIC Port Registers  
The VIC port registers are listed in Table 6–3. See the device-specific data-  
sheet for the memory address of these registers.  
Table 6–3. VIC Port Registers  
Acronym  
Register Name  
Section  
VICCTL  
VIC Control Register  
6.5.1  
VICIN  
VIC Input Register  
6.5.2  
6.5.3  
VICDIV  
VIC Clock Divider Register  
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VIC Port Registers  
6.5.1 VIC Control Register (VICCTL)  
The VIC control register (VICCTL) is shown in Figure 6–3 and described in  
Table 6–4.  
Figure 6–3. VIC Control Register (VICCTL)  
31  
16  
Reserved  
R-0  
15  
4 3  
1
0
Reserved  
R-0  
PRECISION  
R/W-0  
GO  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 6–4. VIC Control Register (VICCTL) Field Descriptions  
†
†
Bit  
field  
symval  
Value Description  
31–4 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
3–1  
PRECISION  
0–7h Precision bits determine the resolution of the interpolation. The  
PRECISION bits can only be written when the GO bit is cleared  
to 0. If the GO bit is set to 1, a write to the PRECISION bits  
does not change the bits.  
16BITS  
15BITS  
14BITS  
13BITS  
12BITS  
11BITS  
10BITS  
9BITS  
0
16 bits  
15 bits  
14 bits  
13 bits  
12 bits  
11 bits  
10 bits  
9 bits  
1
2h  
3h  
4h  
5h  
6h  
7h  
†
For CSL implementation, use the notation VIC_VICCTL_field_symval  
6-6  
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VIC Port Registers  
Table 6–4. VIC Control Register (VICCTL) Field Descriptions (Continued)  
†
†
Bit  
field  
symval  
Value Description  
The GO bit can be written to at any time.  
0
GO  
0
0
The VICDIV and VICCTL registers can be written to without  
affecting the operation of the VIC port. All the logic in the VIC  
port is held in reset state and a 0 is output on the VCTL output  
line. A write to VICCTL bits as well as setting GO to 1 is allowed  
in a single write operation. The VICCTL bits change and the GO  
bit is set, disallowing any further changes to the VICCTL and  
VICDIV registers.  
1
1
The VICDIV and VICCTL (except for the GO bit) registers  
cannot be written. If a write is performed to the VICDIV or  
VICCTL registers when the GO bit is set, the values of these  
registers remain unchanged. If a write is performed that clears  
the GO bit to 0 and changes the values of other VICCTL bits, it  
results in GO = 0 while keeping the rest of the VICCTL bits  
unchanged. The VIC port is in its normal working mode in this  
state.  
†
For CSL implementation, use the notation VIC_VICCTL_field_symval  
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VIC Port Registers  
6.5.2 VIC Input Register (VICIN)  
The DSP writes the input bits for VCXO interpolated control in the VIC input  
register (VICIN). The DSP decides how often to update VICIN. The DSP can  
write to VICIN only when the GO bit in the VIC control register (VICCTL) is set  
to 1. The VIC module uses the MSBs of VICIN for precision values less than  
16. The VICIN is shown in Figure 6–4 and described in Table 6–5.  
Figure 6–4. VIC Input Register (VICIN)  
31  
16  
0
Reserved  
R-0  
15  
VICINBITS  
R/W-0  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 6–5. VIC Input Register (VICIN) Field Descriptions  
†
Bit  
Field  
symval  
Value  
Description  
31–16 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
15–0 VICINBITS OF(value)  
0–FFFFh The DSP writes the input bits for VCXO interpolated control  
to the VIC input bits.  
†
For CSL implementation, use the notation VIC_VICIN_VICINBITS_symval  
6-8  
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VIC Port Registers  
6.5.3 VIC Clock Divider Register (VICDIV)  
The VIC clock divider register (VICDIV) defines the clock divider for the VIC  
interpolation frequency. The VIC interpolation frequency is obtained by divid-  
ing the module clock. The divider value written to VICDIV is:  
ƪ
]
Divider + Round DCLKńR  
where DCLK is the CPU clock divided by 2, and R is the desired interpolation  
frequency. The interpolation frequency depends on precision β.  
The default value of VICDIV is 0001h; 0000h is an illegal value. The VIC module  
uses a value of 0001h whenever 0000h is written to this register.  
The DSP can write to VICDIV only when the GO bit in VICCTL is cleared to 0.  
If a write is performed when the GO bit is set to 1, the VICDIV bits remain  
unchanged. The VICDIV is shown in Figure 6–5 and described in Table 6–6.  
Figure 6–5. VIC Clock Divider Register (VICDIV)  
31  
16  
0
Reserved  
R-0  
15  
VICCLKDIV  
R/W-0001h  
Legend: R = Read only; R/W = Read/Write; -n = value after reset  
Table 6–6. VIC Clock Divider Register (VICDIV) Field Descriptions  
†
Bit  
Field  
symval  
Value  
Description  
31–16 Reserved  
–
0
Reserved. The reserved bit location is always read as 0. A  
value written to this field has no effect.  
15–0 VICCLKDIV OF(value)  
0–FFFFh The VIC clock divider bits define the clock divider for the  
VIC interpolation frequency.  
†
For CSL implementation, use the notation VIC_VICDIV_VICCLKDIV_symval  
SPRU629  
VCXO Interpolated Control Port  
6-9  
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Appendix A  
Video Port Configuration Examples  
This appendix describes how to configure the video port in different modes  
with the help of examples. All examples in this appendix use the video port  
Chip Support Library (CSL).  
Topic  
Page  
A.1 Example 1: Noncontinuous Frame Capture for 525/60 Format . . . . . A-2  
A.2 Example 2: Noncontinuous Frame Display for 525/60 Format . . . . A-10  
A-1  
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Example 1: Noncontinuous Frame Capture for 525/60 Format  
A.1 Example 1: Noncontinuous Frame Capture for 525/60 Format  
This is an example that explains how to configure the video port for 8-bit  
BT.656 noncontinuous frame capture on channel A for 525/60 format. See  
ITU–R BT.656-4 and video port specification (Figures 4–11, 4–33, 4–34, and  
Table 4–37) for more details on 525/60 format.  
/**********************************************************/  
/* Capture parameter definitions based on 525/60 format */  
/**********************************************************/  
#define VCA_HBLNK_SIZE  
/* (EAV/SAV inclusive)  
#define VCA_VBLNK1_SIZE  
#define VCA_VBLNK2_SIZE  
#define VCA_IMG_HSIZE1  
#define VCA_IMG_VSIZE1  
#define VCA_IMG_HSIZE2  
#define VCA_IMG_VSIZE2  
138 /* (858–720),horizontal blanking  
*/  
*/  
*/  
*/  
*/  
19 /* (20–1),v.blanking for field1  
19 /* (283–264),v.blanking for field2  
720 /* field1 horizontal image size  
244 /* (263–20+1), fld1 vertical image size */  
720 /* field2 horizontal image size */  
243 /* (525–283+1), fld2 vertical image size */  
/* Define field image sizes */  
#define VCA_IMAGE_SIZE1  
#define VCA_IMAGE_SIZE2  
(VCA_IMG_HSIZE1 * VCA_IMG_VSIZE1)  
(VCA_IMG_HSIZE2 * VCA_IMG_VSIZE2)  
/* ––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
/* Define channel A capture window co–ordinates for Field1 */  
/* ––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
/* HRST = 0, start of horizontal blanking */  
#define VCA_XSTART1  
(VCA_HBLNK_SIZE – 2/*EAV*/)  
/* VRST = 1, end of vertical blanking */  
#define VCA_YSTART1  
#define VCA_XSTOP1  
#define VCA_YSTOP1  
1
(VCA_XSTART1 + VCA_IMG_HSIZE1 – 1)  
(VCA_YSTART1 + VCA_IMG_VSIZE1 – 1)  
/* ––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
/* Define channel A capture window co–ordinates for Field2 */  
/* ––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
/* HRST = 0, start of horizontal blanking  
*/  
*/  
#define VCA_XSTART2  
(VCA_HBLNK_SIZE – 2/*EAV*/)  
/* VRST = 1, end of vertical blanking  
#define VCA_YSTART2  
#define VCA_XSTOP2  
#define VCA_YSTOP2  
1
(VCA_XSTART2 + VCA_IMG_HSIZE2 – 1)  
(VCA_YSTART2 + VCA_IMG_VSIZE2 – 1)  
/* Define threshold values in double–words. Both fields should  
/* same threshold value)  
#define VCA_THRLD_FIELD1 (VCA_IMG_HSIZE1/8) /* line length in  
#define VCA_THRLD_FIELD2 VCA_THRLD_FIELD1 /* double–words  
*/  
*/  
*/  
*/  
/* Define number of events to be generated for field1 and field2 */  
#define VCA_CAPEVT1  
#define VCA_CAPEVT2  
(VCA_IMAGE_SIZE1 / (VCA_VDTHRLD1 * 8))  
(VCA_IMAGE_SIZE2 / (VCA_VDTHRLD2 * 8))  
#define CAPCHA_FRAME_COUNT 5 /* in this example  
*/  
A-2  
Video Port Configuration Examples  
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Example 1: Noncontinuous Frame Capture for 525/60 Format  
/* –––––––––––––––––––––––––––––––––––––––––––– */  
/* EDMA parameters for capture Y event that are */  
/* specific to this example. */  
/* –––––––––––––––––––––––––––––––––––––––––––– */  
#define VCA_Y_EDMA_ELECNT (VCA_THRLD_FIELD1 * 2) /* because VCA_THRLD_FIELDn is  
in double–words and element size is 32–bit */  
#define VCA_Y_EDMA_FRMCNT ((VCA_CAPEVT1 + VCA_CAPEVT2) * CAPCHA_FRAME_COUNT)  
/******************************************************************/  
/* Description : 8–bit BT.656 non–continuous frame capture  
/*  
/* Some important field descriptions:  
/*  
/* CMODE = 000, 8–bit BT.656 mode  
/* CON = 0  
/* FRAME = 1, capture frame  
/* CF2 = 0  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
/* CF1 = 0, (8–bit non–continuous frame capture)  
/* SCALE = 0, no scaling  
/* RESMPL= 0, no resampling  
/* 10BPK = X, not used in 8–bit capture  
/* EXC = 0, use EAV/SAV codes  
/* VRST = 1, end of vertical blanking  
/* HRST = 0, start of horizontal blanking  
/* FLDD = 0, 1st line EAV or FID input  
/* FINV = 0, no field invert  
/* RDFE = X, used in Raw mode only(Enable field identification) */  
/* SSE = X, used in Raw mode only(Startup synch enable) */  
/******************************************************************/  
#include <csl_vp.h>  
#include <csl_edma.h>  
#include <csl_irq.h>  
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
/* global variable declarations  
*/  
/* ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
VP_Handle vpCaptureHandle; /* handle of vp that to be configured */  
Uint8 capChaAYSpace[]; /* buffer to store captured Y–data  
Uint8 capChaACbSpace[]; /* buffer to store captured Cb–data  
Uint8 capChaACrSpace[]; /* buffer to store captured Cb–data  
*/  
*/  
*/  
EDMA_Handle hEdmaVPCapChaAY;  
EDMA_Handle hEdmaVPCapChaACb;  
EDMA_Handle hEdmaVPCapChaACr;  
Int32 edmaCapChaAYTccNum = 0; /* EDMA tcc for Y channel  
Int32 edmaCapChaACbTccNum = 0; /* EDMA tcc for Cb channel  
Int32 edmaCapChaACrTccNum = 0; /* EDMA tcc for Cb channel  
*/  
*/  
*/  
volatile Uint32 capChaAFrameCount = 0; /* no of frames captured  
*/  
SPRU629  
Video Port Configuration Examples  
A-3  
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Example 1: Noncontinuous Frame Capture for 525/60 Format  
/* Error flags  
*/  
volatile Uint32 capChaAOverrun = 0;  
volatile Uint32 capChaASyncError = 0;  
volatile Uint32 capChaAShortFieldDetect = 0;  
volatile Uint32 capChaALongFieldDetect = 0;  
/* ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
/* Function  
/* Input(s)  
: bt656_8bit_ncfc  
: portNumber, video port number i.e. 0, 1 or 2.  
*/  
*/  
/* Description : Configures given video port for 8–bit BT.656 non– */  
/* continuos frame capture on channel A. */  
/* ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
void bt656_8bit_ncfc(int portNumber)  
{
/* Open video port for capture  
vpCaptureHandle = VP_open(portNumber, VP_OPEN_RESET);  
if(vpCaptureHandle == INV)  
*/  
test_exit(FAIL);  
/* Enable video port functionality in VP Peripheral  
/* Control Reg(PCR)  
*/  
*/  
VP_FSETH(vpCaptureHandle, PCR, PEREN, VP_PCR_PEREN_ENABLE);  
/* ––––––––––––––––––––– */  
/* Enable all interrupts */  
/* ––––––––––––––––––––– */  
/* Enable capture overrun interrupt(COVRA) for VP channel A  
VP_FSETH(vpCaptureHandle, VPIE, COVRA, VP_VPIE_COVRA_ENABLE);  
*/  
*/  
/* Enable capture complete interrupt(CCMPA) for VP channel A  
VP_FSETH(vpCaptureHandle, VPIE, CCMPA, VP_VPIE_CCMPA_ENABLE);  
/* Enable channel synchronization error interrupt(SERRA) for  
/* VP channel A  
*/  
*/  
VP_FSETH(vpCaptureHandle, VPIE, SERRA, VP_VPIE_SERRA_ENABLE);  
/* Enable short field detect interrupt(SFDA) for VP channel A  
VP_FSETH(vpCaptureHandle, VPIE, SFDA, VP_VPIE_SFDA_ENABLE);  
*/  
*/  
/* Enable video port global interrupt enable  
VP_FSETH(vpCaptureHandle, VPIE, VIE, VP_VPIE_VIE_ENABLE);  
/* –––––––––––––––––––––– */  
/* Setup all other fields */  
/* –––––––––––––––––––––– */  
/* Enable short field detect  
VP_FSETH(vpCaptureHandle, VCACTL, SFDE, VP_VCACTL_SFDE_ENABLE);  
*/  
*/  
/* Set last pixel to be captured in Field1 (VCA_STOP1 reg)  
VP_RSETH(vpCaptureHandle, VCASTOP1,  
VP_VCASTOP1_RMK(VCA_YSTOP1, VCA_XSTOP1));  
A-4  
Video Port Configuration Examples  
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Example 1: Noncontinuous Frame Capture for 525/60 Format  
/* Set last pixel to be captured in Field2 (VCA_STOP2 reg)  
VP_RSETH(vpCaptureHandle, VCASTOP2,  
*/  
*/  
*/  
*/  
*/  
VP_VCASTOP2_RMK(VCA_YSTOP2, VCA_XSTOP2));  
/* Set first pixel to be captured in Field1 (VCA_STRT1 reg)  
VP_RSETH(vpCaptureHandle, VCASTRT1, VP_VCASTRT1_RMK(VCA_YSTART1,  
VP_VCASTRT1_SSE_ENABLE, VCA_XSTART1));  
/* Set first pixel to be captured in Field2 (VCA_STRT2 reg)  
VP_RSETH(vpCaptureHandle, VCASTRT2,  
VP_VCASTRT2_RMK(VCA_YSTART2, VCA_XSTART2));  
/* Set threshold values  
VP_RSETH(vpCaptureHandle, VCATHRLD,  
VP_VCATHRLD_RMK(VCA_THRLD_FIELD2, VCA_THRLD_FIELD1));  
/* Set capture event–register values  
VP_RSETH(vpCaptureHandle, VCAEVTCT,  
VP_VCAEVTCT_RMK(VCA_CAPEVT2,VCA_CAPEVT1));  
/* Vertical interrupts (VCA_INT) are not enabled in this  
/* in this example.  
*/  
*/  
/* Set CMODE to 8–bit BT.656  
VP_FSETH(vpCaptureHandle, VCACTL, CMODE, VP_VCACTL_CMODE_BT656B);  
*/  
*/  
/* Set non–continuous frame capture  
VP_FSETH(vpCaptureHandle, VCACTL, CON, VP_VCACTL_CON_DISABLE);  
VP_FSETH(vpCaptureHandle, VCACTL, FRAME, VP_VCACTL_FRAME_FRMCAP);  
VP_FSETH(vpCaptureHandle, VCACTL, CF2, VP_VCACTL_CF2_NONE);  
VP_FSETH(vpCaptureHandle, VCACTL, CF1, VP_VCACTL_CF1_NONE);  
/* Let FDD and FINV to be their defaults  
*/  
*/  
/* Set VRST to end of vertical blanking  
VP_FSETH(vpCaptureHandle, VCACTL, VRST, VP_VCACTL_VRST_V0EAV);  
/* Set HRST to start of horizontal blanking  
*/  
VP_FSETH(vpCaptureHandle, VCACTL, HRST, VP_VCACTL_HRST_OF(0));  
/* 10–bit pack mode(10BPK bit) in this 8–bit example  
*/  
*/  
*/  
/* No (1/2) scaling and no chroma re–sampling in this example  
/* Enable video port interrupts  
IRQ_enable(vpCaptureHandle–>eventId);  
/* Setup Y, Cb and Cr EDMA channels  
setupVPCapChaAEDMA(portNumber);  
*/  
*/  
/* Clear VPHLT in VP_CTL to make video port function  
VP_FSETH(vpCaptureHandle, VPCTL, VPHLT, VP_VPCTL_VPHLT_CLEAR);  
SPRU629  
Video Port Configuration Examples  
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Example 1: Noncontinuous Frame Capture for 525/60 Format  
/* –––––––––––––– */  
/* enable capture */  
/* –––––––––––––– */  
/* set VCEN bit to enable capture  
VP_FSETH(vpCaptureHandle, VCACTL, VCEN, VP_VCACTL_VCEN_ENABLE);  
*/  
*/  
/* clear BLKCAP in VCA_CTL to enable capture DMA events  
VP_FSETH(vpCaptureHandle, VCACTL, BLKCAP,  
VP_VCACTL_BLKCAP_CLEAR);  
}
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
/* Function  
: VPCapChaAIsr  
*/  
/* Description : This capture ISR clears FRMC to continue capture */  
/*  
/*  
in this non–continuous mode and also clears other */  
status bits. */  
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
interrupt void VPCapChaAIsr(void)  
{
Uint32 vpis = 0;  
/* Get video port status register value  
vpis = VP_RGETH(vpCaptureHandle, VPIS);  
*/  
*/  
if(vpis & _VP_VPIS_CCMPA_MASK) /* capture complete  
{
/* Clear frame complete bit in VCX_CTL to  
/* continue capture in non–continuous mode  
VP_FSETH(vpCaptureHandle, VCASTAT, FRMC,  
VP_VCASTAT_FRMC_CLEAR);  
*/  
*/  
/* Clear CCMPA to enable next frame complete  
/* interrupts  
*/  
*/  
VP_FSETH(vpCaptureHandle, VPIS, CCMPA,VP_VPIS_CCMPA_CLEAR);  
capChaAFrameCount++; /* increment captured frame count  
}
*/  
*/  
if(vpis & _VP_VPIS_COVRA_MASK) /* overrun error  
{
capChaAOverrun++;  
VP_FSETH(vpCaptureHandle, VPIS, COVRA,VP_VPIS_COVRA_CLEAR);  
}
if(vpis & _VP_VPIS_SERRA_MASK) /* synchronization error  
*/  
{
capChaASyncError++;  
VP_FSETH(vpCaptureHandle, VPIS, SERRA,VP_VPIS_SERRA_CLEAR);  
}
A-6  
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Example 1: Noncontinuous Frame Capture for 525/60 Format  
if(vpis & _VP_VPIS_SFDA_MASK) /* short field detect  
{
*/  
*/  
capChaAShortFieldDetect++;  
VP_FSETH(vpCaptureHandle, VPIS, SFDA, VP_VPIS_SFDA_CLEAR);  
}
if(vpis & _VP_VPIS_LFDA_MASK) /* long field detect  
{
capChaALongFieldDetect++;  
VP_FSETH(vpCaptureHandle, VPIS, LFDA, VP_VPIS_LFDA_CLEAR);  
}
}
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
/* Function  
/* Input(s)  
: setupVPCapChaAEDMA  
: portNumber, video port number i.e. 0, 1 or 2.  
*/  
*/  
*/  
*/  
/* Description : Sets up EDMA channels for Y, U, V events for  
/* channel A capture.  
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
void setupVPCapChaAEDMA(Int32 portNumber)  
{
Int32 YEvent, UEvent, VEvent;  
/* get channelA Y, U, V EDMA event numbers  
switch(portNumber)  
*/  
{
case VP_DEV0: YEvent = EDMA_CHA_VP0EVTYA;  
UEvent = EDMA_CHA_VP0EVTUA;  
VEvent = EDMA_CHA_VP0EVTVA;  
break;  
case VP_DEV1: YEvent = EDMA_CHA_VP1EVTYA;  
UEvent = EDMA_CHA_VP1EVTUA;  
VEvent = EDMA_CHA_VP1EVTVA;  
break;  
case VP_DEV2: YEvent = EDMA_CHA_VP2EVTYA;  
UEvent = EDMA_CHA_VP2EVTUA;  
VEvent = EDMA_CHA_VP2EVTVA;  
break;  
}
/* Configure Y EDMA channel to move data from YSRCA  
/* (FIFO) to Y–data buffer, capChaAYSpace  
configVPCapEDMAChannel(&hEdmaVPCapChaAY, YEvent,  
&edmaCapChaAYTccNum,  
*/  
*/  
vpCaptureHandle–>ysrcaAddr,  
(Uint32)capChaAYSpace,  
VCA_Y_EDMA_FRMCNT,  
VCA_Y_EDMA_ELECNT);  
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Example 1: Noncontinuous Frame Capture for 525/60 Format  
/* Configure Cb EDMA channel to move data from CbSRCA  
/* (FIFO) to Cb–data buffer, capChaACbSpace  
configVPCapEDMAChannel(&hEdmaVPCapChaACb, UEvent,  
&edmaCapChaACbTccNum,  
*/  
*/  
vpCaptureHandle–>cbsrcaAddr,  
(Uint32)capChaACbSpace,  
VCA_Y_EDMA_FRMCNT,  
VCA_Y_EDMA_ELECNT/2); /* (1/2) of Y–samples  
*/  
/* Configure Cr EDMA channel to move data from CrSRCA  
/* (FIFO) to Cr–data buffer, capChaACrSpace  
configVPCapEDMAChannel(&hEdmaVPCapChaACr, VEvent,  
&edmaCapChaACrTccNum,  
*/  
*/  
vpCaptureHandle–>crsrcaAddr,  
(Uint32)capChaACrSpace,  
VCA_Y_EDMA_FRMCNT,  
VCA_Y_EDMA_ELECNT/2); /* (1/2) of Y–samples  
*/  
*/  
/* Enable three EDMA channels  
EDMA_enableChannel(hEdmaVPCapChaAY);  
EDMA_enableChannel(hEdmaVPCapChaACb);  
EDMA_enableChannel(hEdmaVPCapChaACr);  
}
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
/* Function : configVPCapEDMAChannel  
/*  
/* Input(s) : edmaHandle – pointer to EDMA handle.  
*/  
*/  
*/  
*/  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
eventId  
tccNum  
srcAddr  
dstAddr  
– EDMA eventId.  
– pointer to transfer complete number. */  
– source address for EDMA transfer. */  
– destination address for EDMA transfer */  
*/  
frameCount – frame count.  
elementCount – element count(32–bit element size). */  
*/  
/* Output(s): edmaHandle – edma Handle of the given event.  
*/  
/*  
/*  
/*  
tccNum  
– transfer complete code for the given */  
event.  
*/  
*/  
*/  
*/  
/* Description : Configures the given VP capture EDMA channel.  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
The source address update is fixed address mode  
because the captured data is read from the FIFO. */  
In this example, the destination address mode is */  
auto–increment. But, in real–time applications  
there is lot of flexibility in the way capture  
buffers can be managed like ping–pong and round  
robin,… etc.  
*/  
*/  
*/  
*/  
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
A-8  
Video Port Configuration Examples  
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Example 1: Noncontinuous Frame Capture for 525/60 Format  
void configVPCapEDMAChannel(EDMA_Handle *edmaHandle, Int32 eventId,  
Int32 *tccNum, Uint32 srcAddr,  
Uint32 dstAddr, Uint32 frameCount,  
Uint32 elementCount)  
{
Int32 tcc = 0;  
/* Open Y EVT EDMA channel  
*/  
*edmaHandle = EDMA_open(eventId, EDMA_OPEN_RESET);  
if(*edmaHandle == EDMA_HINV)  
test_exit(FAIL);  
/* allocate TCC for Y event  
if((tcc = EDMA_intAlloc(–1)) == –1)  
test_exit(FAIL);  
*/  
*/  
/* Configure EDMA parameters  
EDMA_configArgs(  
*edmaHandle,  
EDMA_OPT_RMK(  
EDMA_OPT_PRI_MEDIUM, /* medium priority  
EDMA_OPT_ESIZE_32BIT, /* Element size 32 bits  
*/  
*/  
*/  
EDMA_OPT_2DS_NO,  
EDMA_OPT_SUM_NONE,  
EDMA_OPT_2DD_YES,  
EDMA_OPT_DUM_INC,  
EDMA_OPT_TCINT_YES,  
/* 1–dimensional source(FIFO)  
/* fixed src address mode(FIFO) */  
/* 2–dimensional destination  
/* destination increment  
/* Enable transfer complete  
/* indication  
*/  
*/  
*/  
*/  
EDMA_OPT_TCC_OF(tcc & 0xF),  
EDMA_OPT_TCCM_OF(((tcc & 0x30) >> 4)),  
EDMA_OPT_ATCINT_NO,  
/* Disable Alternate Transfer  
/* Complete Interrupt  
*/  
*/  
EDMA_OPT_ATCC_OF(0),  
EDMA_OPT_PDTS_DISABLE, /* disable PDT(peripheral device */  
/* transfer) mode for source  
EDMA_OPT_PDTD_DISABLE, /* disable PDT mode for dest  
*/  
*/  
*/  
*/  
EDMA_OPT_LINK_NO,  
EDMA_OPT_FS_NO  
),  
/* Disable linking  
/* Array synchronization  
EDMA_SRC_RMK(srcAddr),  
EDMA_CNT_RMK(EDMA_CNT_FRMCNT_OF((frameCount – 1)),  
EDMA_CNT_ELECNT_OF(elementCount)),  
EDMA_DST_RMK(dstAddr),  
EDMA_IDX_RMK(EDMA_IDX_FRMIDX_OF((elementCount * 4)),  
EDMA_IDX_ELEIDX_OF(0)), /* note: 32–bit element size  
/* no RLD in 2D and no linking  
*/  
*/  
EDMA_RLD_RMK(EDMA_RLD_ELERLD_OF(0), EDMA_RLD_LINK_OF(0))  
);  
*tccNum = tcc;  
}
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Example 2: Noncontinuous Frame Display for 525/60 Format  
A.2 Example 2: Noncontinuous Frame Display for 525/60 Format  
This is an example that explains how to configure the video port for 8-bit  
BT.656 noncontinuous frame display for 525/60 format. See ITU–R BT.656–4  
and video port specification (Figures 4–11, 4–33, 4–34, and Table 4–37) for  
more details on 525/60 format. For simplicity, this example does not contain  
any margins; that is, both vertical and horizontal offsets are zero. In other  
words, both active area and image area are the same.  
/**********************************************************/  
/* Display parameter definitions based on 525/60 format */  
/**********************************************************/  
/* ––––––––––––––––– */  
/* Define frame size */  
/* ––––––––––––––––– */  
#define VD_FRM_WIDTH  
858 /* no of pixels per frame line  
*/  
/* including horizontal blanking */  
#define VD_FRM_HEIGHT  
#define VD_FRM_SIZE  
525 /* total noof lines per frame  
(VD_FRM_WIDTH * VD_FRM_HEIGHT)  
*/  
/* ––––––––––––––––––– */  
/* Horizontal blanking */  
/* ––––––––––––––––––– */  
#define VD_HBLNK_START  
#define VD_HBLNK_STOP  
720 /* starting location of EAV  
856 /* starting location of SAV  
(VD_HBLNK_STOP – VD_HBLNK_START +  
*/  
*/  
#define VD_HBLNK_SIZE  
2/*EAV*/) /* (138) EAV, SAV inclusive */  
/* –––––––––––––––––––––––––––– */  
/* Vertical blanking for field1 */  
/* –––––––––––––––––––––––––––– */  
#define VD_VBLNK_XSTART1 720 /* pixel on which VBLNK active  
/* edge occurs for field1  
#define VD_VBLNK_YSTART1 1 /* line on which VBLNK active  
/* edge occurs for field1  
*/  
*/  
*/  
*/  
#define VD_VBLNK_XSTOP1  
720 /* pixel on which VBLNK inactive */  
/* edge occurs for field1  
20 /* line on which VBLNK inactive  
/* edge occurs for field1  
*/  
*/  
*/  
#define VD_VBLNK_YSTOP1  
/* –––––––––––––––––––––––––––– */  
/* Vertical blanking for field2 */  
/* –––––––––––––––––––––––––––– */  
#define VD_VBLNK_XSTART1 360 /* pixel on which VBLNK active  
/* edge occurs for field2  
#define VD_VBLNK_YSTART1 263 /* line on which VBLNK active  
/* edge occurs for field2  
*/  
*/  
*/  
*/  
#define VD_VBLNK_XSTOP1  
360 /* pixel on which VBLNK inactive */  
/* edge occurs for field2  
283 /* line on which VBLNK inactive  
/* edge occurs for field2  
*/  
*/  
*/  
#define VD_VBLNK_YSTOP1  
A-10  
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Example 2: Noncontinuous Frame Display for 525/60 Format  
/* ––––––––––––––––––––––––––––––––––––––––––––––––– */  
/* Define vertical blanking bit(VD_VBITn) reg values */  
/* ––––––––––––––––––––––––––––––––––––––––––––––––– */  
#define VD_VBIT_SET1  
1 /* first line with an EAV with V=1  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
/* indicating the start of Field1  
/* vertical blanking  
20 /* first line with an EAV with V=0  
/* indicating the start of Field1  
/* active display  
#define VD_VBIT_CLR1  
#define VD_VBLNK1_SIZE  
#define VD_VBIT_SET2  
(VD_VBIT_CLR1 – VD_VBIT_SET1) /* 19 lines  
264 /* first line with an EAV with V=1  
/* indicating the start of Field2  
/* vertical blanking  
283 /* first line with an EAV with V=0  
/* indicating the start of Field2  
/* active display  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
#define VD_VBIT_CLR2  
#define VD_VBLNK2_SIZE  
(VD_VBIT_CLR2 – VD_VBIT_SET2) /* 19 lines  
/* –––––––––––– */  
/* Field timing */  
/* –––––––––––– */  
#define VD_FIELD1_XSTART 720 /* pixel on the first line of  
/* Field1 on which FLD ouput  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
/* is de–asserted  
#define VD_FIELD1_YSTART 1 /* line on which FLD is de–asserted  
#define VD_FIELD1_XSTART 360 /* pixel on the first line of  
/* Field1 on which FLD ouput  
/* is asserted  
#define VD_FIELD1_YSTART 263 /* line on which FLD is asserted  
/* –––––––––––––––––––––––––––––––––––– */  
/* Define field bit(VD_FBIT) reg values */  
/* –––––––––––––––––––––––––––––––––––– */  
#define VD_FBIT_CLR  
4 /* first line with an EAV with F=0  
/* indicating Field 1 display  
266 /* first line with an EAV with F=1  
/* indicating Field 2 display  
*/  
*/  
*/  
*/  
#define VD_FBIT_SET  
/* –––––––––––––––––––––––––––––––– */  
/* Define horzontal synchronization */  
/* –––––––––––––––––––––––––––––––– */  
#define VD_HSYNC_START  
#define VD_HSYNC_STOP  
736  
800  
/* –––––––––––––––––––––––––––––––––––––––––– */  
/* Define vertical synchronization for field1 */  
/* –––––––––––––––––––––––––––––––––––––––––– */  
#define VD_VSYNC_XSTART1 720  
#define VD_VSYNC_YSTART1 4  
#define VD_VSYNC_XSTOP1  
#define VD_VSYNC_YSTOP1  
720  
7
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Example 2: Noncontinuous Frame Display for 525/60 Format  
/* –––––––––––––––––––––––––––––––––––––––––– */  
/* Define vertical synchronization for field2 */  
/* –––––––––––––––––––––––––––––––––––––––––– */  
#define VD_VSYNC_XSTART2 360  
#define VD_VSYNC_YSTART2 266  
#define VD_VSYNC_XSTOP2  
#define VD_VSYNC_YSTOP2  
360  
269  
/* –––––––––––––––––––––––––––––––––––––––– */  
/* Define image offsets for both the fields */  
/* which are zero in this example  
*/  
/* –––––––––––––––––––––––––––––––––––––––– */  
#define VD_IMG_HOFF1  
#define VD_IMG_VOFF1  
#define VD_IMG_HOFF2  
#define VD_IMG_VOFF2  
0
0
0
0
/* ––––––––––––––––––––––––––––––––––––––––––––––––– */  
/* Define image active vertical and horizontal sizes */  
/* ––––––––––––––––––––––––––––––––––––––––––––––––– */  
#define VD_IMG_HSIZE1  
#define VD_IMG_VSIZE1  
#define VD_IMG_HSIZE2  
#define VD_IMG_VSIZE2  
720 /* field1 horizontal image size  
244 /* field1 vertical image size  
720 /* field2 horizontal image size  
243 /* field2 vertical image size  
*/  
*/  
*/  
*/  
/* Manipulate field1 and field2 image sizes  
*/  
#define VD_IMAGE_SIZE1  
#define VD_IMAGE_SIZE2  
(VD_IMG_HSIZE1 * VD_IMG_VSIZE1)  
(VD_IMG_HSIZE2 * VD_IMG_VSIZE2)  
/* Define threshold values in double–words. Both fields should  
/* have same threshold value  
*/  
*/  
*/  
*/  
#define VD_VDTHRLD1  
#define VD_VDTHRLD2  
(VD_IMG_HSIZE1/8) /* line length in  
VD_VDTHRLD1 /* double–words  
/* Define number of events to be generated for field1 and field2 */  
#define VD_DISPEVT1  
#define VD_DISPEVT2  
(VD_IMAGE_SIZE1 / (VD_VDTHRLD1 * 8))  
(VD_IMAGE_SIZE2 / (VD_VDTHRLD2 * 8))  
#define DISPLAY_FRAME_COUNT  
5 /* in this example  
*/  
/* –––––––––––––––––––––––––––––––––––––––––––– */  
/* EDMA parameters for display Y event that are */  
/* specific to this example.  
*/  
/* –––––––––––––––––––––––––––––––––––––––––––– */  
#define VD_Y_EDMA_ELECNT (VD_VDTHRLD1 * 2) /* VD_VDTHRLDn is in double–words  
and 32–bit element size */  
#define VD_Y_EDMA_FRMCNT ((VD_DISPEVT1 + VD_DISPEVT2) *  
DISPLAY_FRAME_COUNT)  
A-12  
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Example 2: Noncontinuous Frame Display for 525/60 Format  
/******************************************************************/  
/* Description : 8–bit BT.656 non–continuous frame display  
/*  
/* Some important field descriptions:  
/*  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
/* DMODE = 000, 8–bit BT.656 mode  
/* CON  
= 0  
/* FRAME = 1, display frame  
/* DF2  
/* DF1  
= 0  
= 0, (8–bit non–continuous frame display)  
/* SCALE = 0, no scaling  
/* RESMPL = 0, no resampling  
/* DPK  
= X, not used in 8–bit display  
/* RSYNC = X, used in Raw mode(Enable second synchronized raw  
/*  
/* RGBX = X, used in Raw mode(RGB extract enable. Perform  
/* 3/4 FIFO unpacking)  
data channel)  
/* VCTL1S = 00, output HSYNC  
/* VCTL2S = 00, output VSYNC  
/* VCTL3S = 0, output CBLNK  
/* HXS  
/* VXS  
/* FXS  
= 0, VCTL1 is an output  
= 0, VCTL2 is an output  
= 0, VCTL3 is an output  
/* PVPSYN = 0, no previous port synchronization  
/******************************************************************/  
#include ”csl_vp.h”  
#include ”csl_edma.h”  
#include ”csl_irq.h”  
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
/* global variable declarations  
*/  
/* ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
VP_Handle vpDisplayHandle; /* handle of vp that to be configured */  
Uint8 dispYSpace[]; /* Display Y–data buffer */  
Uint8 dispCbSpace[]; /* Display Cb–data buffer */  
Uint8 dispCrSpace[]; /* Display Cb–data buffer */  
EDMA_Handle hEdmaVPDispY;  
EDMA_Handle hEdmaVPDispCb;  
EDMA_Handle hEdmaVPDispCr;  
Int32 edmaDispYTccNum = 0; /* EDMA tcc for Y channel */  
Int32 edmaDispCbTccNum = 0; /* EDMA tcc for Cb channel */  
Int32 edmaDispCrTccNum = 0; /* EDMA tcc for Cb channel */  
volatile Uint32 displayFrameCount = 0; /* no of frames that are */  
/* displayed  
/* underrun error flag  
*/  
*/  
volatile Uint32 dispUnderrun = 0;  
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Example 2: Noncontinuous Frame Display for 525/60 Format  
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
/* Function  
/* Input(s)  
: bt656_8bit_ncfd  
: portNumber, video port number i.e. 0, 1 or 2.  
*/  
*/  
/* Description : Configures given video port for 8–bit BT.656 non– */  
/* continuous frame display. */  
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
void bt656_8bit_ncfd(int portNumber)  
{
/* Open video port for display  
*/  
vpDisplayHandle = VP_open(portNumber, VP_OPEN_RESET);  
if(vpDisplayHandle == INV)  
test_exit(FAIL);  
/* Enable video port functionality in VP Peripheral  
/* Control Reg(PCR)  
*/  
*/  
VP_FSETH(vpDisplayHandle , PCR, PEREN, VP_PCR_PEREN_ENABLE);  
/* Set this port to display mode  
*/  
VP_FSETH(vpDisplayHandle , VPCTL, DISP, VP_VPCTL_DISP_DISPLAY);  
/* ––––––––––––––––––––– */  
/* Enable all interrupts */  
/* ––––––––––––––––––––– */  
/* enable display complete interrupt  
VP_FSETH(vpDisplayHandle , VPIE, DCMP, VP_VPIE_DCMP_ENABLE);  
*/  
*/  
*/  
/* enable display underrun interrupt  
VP_FSETH(vpDisplayHandle , VPIE, DUND, VP_VPIE_DUND_ENABLE);  
/* enable video port global interrupt enable  
VP_FSETH(vpDisplayHandle , VPIE, VIE, VP_VPIE_VIE_ENABLE);  
/* –––––––––––––––––––– */  
/* Set all other fields */  
/* –––––––––––––––––––– */  
/* set frame size  
VP_RSETH(vpDisplayHandle , VDFRMSZ,  
VP_VDFRMSZ_RMK(VD_FRM_HEIGHT, VD_FRM_WIDTH));  
*/  
*/  
/* set horizontal blanking  
VP_RSETH(vpDisplayHandle , VDHBLNK,  
VP_VDHBLNK_RMK(VD_HBLNK_STOP, VP_VDHBLNK_HBDLA_NONE,  
VD_HBLNK_START));  
/* set vertical blanking start for field1  
VP_RSETH(vpDisplayHandle , VDVBLKS1,  
*/  
*/  
VP_VDVBLKS1_RMK(VD_VBLNK_YSTART1,VD_VBLNK_XSTART1));  
/* set vertical blanking end for field1  
VP_RSETH(vpDisplayHandle , VDVBLKE1,  
VP_VDVBLKE1_RMK(VD_VBLNK_YSTOP1, VD_VBLNK_XSTOP1));  
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Example 2: Noncontinuous Frame Display for 525/60 Format  
/* set vertical blanking start for field2  
VP_RSETH(vpDisplayHandle , VDVBLKS2,  
VP_VDVBLKS2_RMK(VD_VBLNK_YSTART2, VD_VBLNK_XSTART2));  
*/  
*/  
*/  
*/  
/* set vertical blanking end for field2  
VP_RSETH(vpDisplayHandle , VDVBLKE2,  
VP_VDVBLKE2_RMK(VD_VBLNK_YSTOP2, VD_VBLNK_XSTOP2));  
/* set vertical blanking bit register for field 1(VD_VBIT1)  
VP_RSETH(vpDisplayHandle , VDVBIT1,  
VP_VDVBIT1_RMK(VD_VBIT_CLR1, VD_VBIT_SET1));  
/* set vertical blanking bit register for field 2(VD_VBIT2)  
VP_RSETH(vpDisplayHandle , VDVBIT2,  
VP_VDVBIT2_RMK(VD_VBIT_CLR2, VD_VBIT_SET2));  
/* No image offsets in this example  
*/  
*/  
/* set image size for field1  
VP_RSETH(vpDisplayHandle , VDIMGSZ1,  
VP_VDIMGSZ1_RMK(VD_IMG_VSIZE1, VD_IMG_HSIZE1));  
/* set image size for field2  
VP_RSETH(vpDisplayHandle , VDIMGSZ2,  
VP_VDIMGSZ1_RMK(VD_IMG_VSIZE2, VD_IMG_HSIZE2));  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
/* set field1 timing  
VP_RSETH(vpDisplayHandle , VDFLDT1,  
VP_VDFLDT1_RMK(VD_FIELD1_YSTART, VD_FIELD1_XSTART));  
/* set field2 timing  
VP_RSETH(vpDisplayHandle , VDFLDT2,  
VP_VDFLDT2_RMK(VD_FIELD2_YSTART, VD_FIELD2_XSTART));  
/* set display field bit register(VD_FBIT)  
VP_RSETH(vpDisplayHandle , VDFBIT,  
VP_VDFBIT_RMK(VD_FBIT_SET, VD_FBIT_CLR));  
/* set horizontal sync control (VCTL1S)  
VP_RSETH(vpDisplayHandle , VDHSYNC,  
VP_VDHSYNC_RMK(VD_HSYNC_STOP, VD_HSYNC_START));  
/* set vertical sync start for field1 (VCTL2S)  
VP_RSETH(vpDisplayHandle , VDVSYNS1,  
VP_VDVSYNS1_RMK(VD_VSYNC_YSTART1,VD_VSYNC_XSTART1));  
/* set vertical sync end for field1 (VCTL2S)  
VP_RSETH(vpDisplayHandle , VDVSYNE1,  
VP_VDVSYNE1_RMK(VD_VSYNC_YSTOP1, VD_VSYNC_XSTOP1));  
/* set vertical sync start for field2 (VCTL2S)  
VP_RSETH(vpDisplayHandle , VDVSYNS2,  
VP_VDVSYNS2_RMK(VD_VSYNC_YSTART2,VD_VSYNC_XSTART2));  
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Example 2: Noncontinuous Frame Display for 525/60 Format  
/* set vertical sync end for field2 (VCTL2S)  
VP_RSETH(vpDisplayHandle , VDVSYNE2,  
*/  
VP_VDVSYNE2_RMK(VD_VSYNC_YSTOP2, VD_VSYNC_XSTOP2));  
/* Let clipping values to be their defaults (VD_CLIP)  
/* No need to set DEF_VAL and VD_RELOAD in this example  
*/  
*/  
*/  
/* set event register  
VP_RSETH(vpDisplayHandle , VDDISPEVT,  
VP_VDDISPEVT_RMK(VD_DISPEVT2, VD_DISPEVT1));  
/* Vertical interrupts are not used in this example (VD_VINT)  
*/  
*/  
/* set threshold value for DMA events  
VP_RSETH(vpDisplayHandle, VDTHRLD,  
VP_VDTHRLD_RMK(VD_VDTHRLD2,  
VP_VDTHRLD_INCPIX_DEFAULT, VD_VDTHRLD1));  
/* ––––––––––––––––––––––––––––––– */  
/* Set display control reg(VD_CTL) */  
/* ––––––––––––––––––––––––––––––– */  
/* set display mode(DMODE) to 8–bit BT.656  
VP_FSETH(vpDisplayHandle , VDCTL, DMODE, VP_VDCTL_DMODE_BT656B);  
*/  
*/  
/* set non–continuous frame display  
VP_FSETH(vpDisplayHandle , VDCTL, CON, VP_VDCTL_CON_DISABLE);  
VP_FSETH(vpDisplayHandle , VDCTL, FRAME, VP_VDCTL_FRAME_FRMDIS);  
VP_FSETH(vpDisplayHandle , VDCTL, DF2, VP_VDCTL_DF2_NONE);  
VP_FSETH(vpDisplayHandle , VDCTL, DF1, VP_VDCTL_DF1_NONE);  
/* let control outputs(VCTL1S, VCTL2S, VCTL3S, HXS, VXS, FXS)  
/* be their defaults i.e. VCTLxS are output control signals  
*/  
*/  
/* no scaling and no resampling in this example  
*/  
/* no need to bother about 10–bit unpacking mode(DPK bit)  
/* in this 8–bit example  
*/  
*/  
/* Set up Y, Cb and Cr EDMA channels  
setupVPDispEDMA(portNumber);  
*/  
*/  
*/  
/* Enable video port interrupts  
IRQ_enable(vpDisplayHandle –>eventId);  
/* clear VPHLT in VP_CTL to make video port function  
VP_FSETH(vpDisplayHandle , VPCTL, VPHLT, VP_VPCTL_VPHLT_CLEAR);  
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Example 2: Noncontinuous Frame Display for 525/60 Format  
/* –––––––––––––– */  
/* enable display */  
/* –––––––––––––– */  
/* set VDEN to enable display for loop–back  
VP_FSETH(vpBDisplayHandle, VDCTL, VDEN, VP_VDCTL_VDEN_ENABLE);  
*/  
*/  
/* clear BLKDIS in VD_CTL to enable display DMA events  
VP_FSETH(vpBDisplayHandle, VDCTL, BLKDIS, VP_VDCTL_BLKDIS_CLEAR);  
}
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
/* Function : VPDispIsr */  
/* Description : This display ISR clears FRMD to continue display */  
/*  
/*  
in this non–continuous mode and also clears other */  
status bits. */  
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
interrupt void VPDispIsr(void)  
{
Uint32 vpis = 0;  
vpis = VP_RGETH(vpDisplayHandle , VPIS);  
if(vpis & _VP_VPIS_DCMP_MASK) /* frame display complete  
{
*/  
*/  
/* Clear frame complete bit FRMD to continue display  
VP_FSETH(vpDisplayHandle , VDSTAT, FRMD,  
VP_VDSTAT_FRMD_CLEAR);  
/* clear DCMPA to enable next frame complete interrupts  
VP_FSETH(vpDisplayHandle , VPIS, DCMP, VP_VPIS_DCMP_CLEAR);  
*/  
*/  
*/  
displayFrameCount++; /* increment displayed frame count  
}
if(vpis & _VP_VPIS_DUND_MASK) /* underrun error  
{
dispUnderrun++;  
/* clear DUND to enable next underrun interrupts  
*/  
VP_FSETH(vpDisplayHandle , VPIS, DUND, VP_VPIS_DUND_CLEAR);  
}
}
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Example 2: Noncontinuous Frame Display for 525/60 Format  
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
/* Function  
/* Input(s)  
: setupVPDispEDMA  
: portNumber, video port number i.e. 0,1 or 2.  
*/  
*/  
*/  
*/  
/* Description : Sets up DMA channels for Y, U, V events for VP  
/* display.  
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– */  
void setupVPDispEDMA(Int32 portNumber)  
{
Int32 YEvent, UEvent, VEvent;  
/* get Y, U, V EDMA event numbers  
switch(portNumber)  
*/  
{
case VP_DEV0:YEvent = EDMA_CHA_VP0EVTYA;  
UEvent = EDMA_CHA_VP0EVTUA;  
VEvent = EDMA_CHA_VP0EVTVA;  
break;  
case VP_DEV1:YEvent = EDMA_CHA_VP1EVTYA;  
UEvent = EDMA_CHA_VP1EVTUA;  
VEvent = EDMA_CHA_VP1EVTVA;  
break;  
case VP_DEV2:YEvent = EDMA_CHA_VP2EVTYA;  
UEvent = EDMA_CHA_VP2EVTUA;  
VEvent = EDMA_CHA_VP2EVTVA;  
break;  
}
/* Configure Y EDMA channel to move data from  
/* Y–data buffer, dispYSpace to YDSTA (FIFO)  
configVPDispEDMAChannel(&hEdmaVPDispY, YEvent,  
&edmaDispYTccNum,  
*/  
*/  
(Uint32)dispYSpace,  
vpDisplayHandle –>ydstaAddr,  
VD_Y_EDMA_FRMCNT,  
VD_Y_EDMA_ELECNT);  
/* Configure Cb EDMA channel to move data from  
/* Cb–data buffer, dispCbSpace to CbDSTA (FIFO)  
configVPDispEDMAChannel(&hEdmaVPDispCb, UEvent,  
&edmaDispCbTccNum,  
*/  
*/  
(Uint32)dispCbSpace,  
vpDisplayHandle –>cbdstAddr,  
VD_Y_EDMA_FRMCNT,  
VD_Y_EDMA_ELECNT/2); /* (1/2) of Y  
*/  
/* Configure Cr EDMA channel to move data from  
/* Cr–data buffer, dispCrSpace to CrDSTA (FIFO)  
configVPDispEDMAChannel(&hEdmaVPDispCr, VEvent,  
&edmaDispCrTccNum,  
*/  
*/  
(Uint32)dispCrSpace,  
vpDisplayHandle –>crdstAddr,  
VD_Y_EDMA_FRMCNT,  
VD_Y_EDMA_ELECNT/2);  
A-18  
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Example 2: Noncontinuous Frame Display for 525/60 Format  
/* enable three EDMA channels  
*/  
EDMA_enableChannel(hEdmaVPDispY);  
EDMA_enableChannel(hEdmaVPDispCb);  
EDMA_enableChannel(hEdmaVPDispCr);  
}
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––  
/* Function : configVPDispEDMAChannel  
/*  
*/  
*/  
*/  
*/  
*/  
/* Input(s) : edmaHandle  
– pointer to EDMA handle.  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
eventId  
tccNum  
srcAddr  
dstAddr  
frameCount  
– EDMA eventId.  
– pointer to transfer complete number. */  
– source address for EDMA transfer. */  
– destination address for EDMA transfer */  
– frame count. */  
elementCount – element count(32–bit element size). */  
*/  
/* Output(s): edmaHandle  
– edma Handle of the given event.  
*/  
/*  
/*  
/*  
tccNum  
– transfer complete code for the given */  
event.  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
/* Description : Configures the given VP display EDMA channel.  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
The destination address update is fixed because  
the displayed data is write to the FIFO.  
In this example, the source address mode is  
auto–increment. But, in real–time applications  
there is lot of flexibility in the way display  
buffers can be managed like ping–pong and round  
robin,… etc.  
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––  
void configVPDispEDMAChannel(EDMA_Handle *edmaHandle,  
Int32 eventId, Int32 *tccNum,  
Uint32 srcAddr, Uint32 dstAddr,  
Uint32 frameCount, Uint32 elementCount)  
{
Int32 tcc = 0;  
/* Open Y event EDMA channel  
*edmaHandle = EDMA_open(eventId, EDMA_OPEN_RESET);  
*/  
*/  
if(*edmaHandle == EDMA_HINV)  
test_exit(FAIL);  
/* allocate TCC for Y event  
if((tcc = EDMA_intAlloc(–1)) == –1)  
test_exit(FAIL);  
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Example 2: Noncontinuous Frame Display for 525/60 Format  
/* Configure EDMA parameters  
EDMA_configArgs(  
*/  
*edmaHandle,  
EDMA_OPT_RMK(  
EDMA_OPT_PRI_MEDIUM, /* medium priority  
EDMA_OPT_ESIZE_32BIT, /* Element size 32 bits  
*/  
*/  
*/  
EDMA_OPT_2DS_YES,  
EDMA_OPT_SUM_INC,  
EDMA_OPT_2DD_NO,  
EDMA_OPT_DUM_NONE,  
EDMA_OPT_TCINT_YES,  
/* 2–dimensional source  
/* source address auto increment */  
/* 1–dimensional destination(FIFO) */  
/* fixed dest address mode(FIFO) */  
/* Enable transfer complete  
/* indication  
*/  
*/  
EDMA_OPT_TCC_OF(tcc & 0xF),  
EDMA_OPT_TCCM_OF(((tcc & 0x30) >> 4)),  
EDMA_OPT_ATCINT_NO,  
/* Disable Alternate Transfer  
/* Complete Interrupt  
*/  
*/  
EDMA_OPT_ATCC_OF(0),  
EDMA_OPT_PDTS_DISABLE, /* disable PDT(peripheral device */  
/* transfer) mode for source  
EDMA_OPT_PDTD_DISABLE, /* disable PDT mode for dest  
*/  
*/  
*/  
*/  
EDMA_OPT_LINK_NO,  
EDMA_OPT_FS_NO  
),  
/* Disable linking  
/* Array synchronization  
EDMA_SRC_RMK(srcAddr),  
EDMA_CNT_RMK(EDMA_CNT_FRMCNT_OF((frameCount – 1)),  
EDMA_CNT_ELECNT_OF(elementCount)),  
EDMA_DST_RMK(dstAddr),  
EDMA_IDX_RMK(EDMA_IDX_FRMIDX_OF((elementCount * 4)),  
EDMA_IDX_ELEIDX_OF(0)), /* note: 32–bit element size  
/* no RLD in 2D and no linking  
*/  
*/  
EDMA_RLD_RMK(EDMA_RLD_ELERLD_OF(0), EDMA_RLD_LINK_OF(0))  
);  
*tccNum = tcc;  
}
A-20  
Video Port Configuration Examples  
SPRU629  
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Index  
boundary conditions  
video capture 3-42  
video display 4-33  
A
ancillary data capture 3-31  
ancillary data display 4-25  
architecture 1-3  
BT.656 mode  
blanking codes 4-12  
BT.656 image display 4-12  
capture channels 3-3  
capture selection 3-18  
capturing video 3-44  
data sampling 3-8  
ATC bit  
in TSISTCMPL 3-78  
in TSISTCMPM 3-79  
ATCM bit  
display timing reference codes 4-9  
displaying video 4-47  
field and frame operation 3-17  
FIFO overrun 3-45  
in TSISTMSKL 3-80  
in TSISTMSKM 3-81  
B
BLKCAP bit  
FIFO packing 3-9  
FIFO unpacking 4-13  
image window and capture 3-6  
timing reference codes 3-4  
video capture 3-3  
in VCACTL 3-53  
in VCBCTL 3-68  
BLKDIS bit 4-55  
video display 4-9  
block diagrams  
16/20-bit raw video capture FIFO  
configuration 1-9  
16/20-bit raw video display FIFO  
configuration 1-11  
C
CAPEVTCT1 bits 3-67  
CAPEVTCT2 bits 3-67  
8/10-bit locked raw video display FIFO  
configuration 1-11  
8/10-bit raw video capture FIFO  
configuration 1-7  
8/10-bit raw video display FIFO  
configuration 1-10  
BT.656 video capture FIFO configuration 1-6  
BT.656 video display FIFO configuration 1-9  
system time clock counter 3-39  
TSI system 6-2  
capture channel reset 2-3  
capture line boundary conditions 3-42  
capture selection  
BT.656 mode 3-18  
raw data mode 3-33  
TSI capture mode 3-40  
Y/C mode 3-18  
capturing data in TSI capture mode 3-47  
capturing video  
BT.656 mode 3-44  
raw data mode 3-46  
Y/C mode 3-44  
TSI video capture FIFO configuration 1-7  
VIC port 6-2  
video port 1-4  
Cb FIFO destination register (CBDST) 4-96  
Cb FIFO source register (CBSRCx) 3-83  
Y/C video capture FIFO configuration 1-8  
Y/C video display FIFO configuration 1-12  
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CbDEFVAL bits 4-86  
CBDST 4-96  
D
DCDIS bit 2-20  
CBSRCx 3-83  
DCHNL bit 2-17  
CCMPA bit  
in VPIE 2-21  
in VPIS 2-24  
DCMP bit  
in VPIE 2-21  
in VPIS 2-24  
CCMPB bit  
DCNA bit  
in VPIE 2-21  
in VPIS 2-24  
in VPIE 2-21  
in VPIS 2-24  
CF1 bit  
DEFVAL bits 4-87  
in VCACTL 3-53  
in VCBCTL 3-68  
DF1 bit 4-55  
CF2 bit  
DF2 bit 4-55  
in VCACTL 3-53  
in VCBCTL 3-68  
DISP bit 2-17  
DISPEVT1 bits 4-84  
DISPEVT2 bits 4-84  
display channel reset 2-4  
display line boundary conditions 4-33  
display selection, video display mode 4-31  
CLASS bits 5-3  
CLIPCHIGH bits 4-85  
CLIPCLOW bits 4-85  
CLIPYHIGH bits 4-85  
CLIPYLOW bits 4-85  
clocks 2-12  
displaying video  
BT.656 mode 4-47  
raw data mode 4-49  
Y/C mode 4-47  
CMODE bits  
in VCACTL 3-53  
in VCBCTL 3-68  
DMA operation 2-6  
DMODE bits 4-55  
DPK 4-55  
CON bit 4-55  
in VCACTL 3-53  
in VCBCTL 3-68  
DUND bit  
in VPIE 2-21  
in VPIS 2-24  
COVRA bit  
in VPIE 2-21  
in VPIS 2-24  
DVEN 4-55  
COVRB bit  
in VPIE 2-21  
in VPIS 2-24  
E
ENSTC bit 3-72  
Cr FIFO destination register (CRDST) 4-96  
Cr FIFO source register (CRSRCx) 3-83  
CrDEFVAL bits 4-86  
ERRFILT bit 3-72  
examples  
noncontinuous frame capture for 525/60  
format A-2  
noncontinuous frame display for 525/60  
format A-10  
CRDST 4-96  
CRLD bits 4-83  
CRSRCx 3-83  
CTMODE bit 3-72  
EXC bit 3-53  
Index-2  
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F
G
GO bit 6-6  
F1C bit 3-50  
GPIO bit  
F1D bit 4-53  
in VPIE 2-21  
in VPIS 2-24  
F2C bit 3-50  
GPIO registers 5-2  
F2D bit 4-53  
FBITCLR bits 4-89  
FBITSET bits 4-89  
H
FIFO overrun  
HBDLA bit 4-61  
BT.656 mode 3-45  
raw data mode 3-47  
TSI capture mode 3-48  
video display 4-51  
Y/C mode 3-45  
HBLNKSTART bits 4-61  
HBLNKSTOP bits 4-61  
HIDATA bit 2-20  
HRLD bits 4-83  
HRST bit  
FIFO packing  
in VCACTL 3-53  
in VCBCTL 3-68  
BT.656 mode 3-9  
raw data mode 3-33  
TSI capture mode 3-41  
Y/C mode 3-14  
HSYNCSTART bits 4-78  
HSYNCSTOP bits 4-78  
HXS bit 4-55  
FIFO unpacking  
BT.656 mode 4-13  
raw data mode 4-26  
Y/C mode 4-17  
I
IMGHOFF1 bits 4-69  
IMGHOFF2 bits 4-71  
IMGHSIZE1 bits 4-70  
IMGHSIZE2 bits 4-73  
IMGVOFF1 bits 4-69  
IMGVOFF2 bits 4-71  
IMGVSIZE1 bits 4-70  
IMGVSIZE2 bits 4-73  
INCPIX bits 4-76  
FINV bit  
in VCACTL 3-53  
in VCBCTL 3-68  
FLD1XSTART bits 4-74  
FLD1YSTART bits 4-74  
FLD2XSTART bits 4-75  
FLD2YSTART bits 4-75  
FLDD bit 3-53  
INPCR bits 3-74  
FRAME bit 4-55  
in VCACTL 3-53  
in VCBCTL 3-68  
INPCRE bits 3-75  
INPCRM bit 3-75  
interrupt operation 2-5  
FREE bit 5-4  
FRMC bit 3-50  
FRMD bit 4-53  
FRMHEIGHT bits 4-60  
FRMWIDTH bits 4-60  
FSCL2 bit 3-63  
FSYNC bit 3-50  
FXS bit 4-55  
L
LFDA bit  
in VPIE 2-21  
in VPIS 2-24  
LFDB bit  
in VPIE 2-21  
in VPIS 2-24  
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LFDE bit  
PDSET 5-15  
in VCACTL 3-53  
in VCBCTL 3-68  
PDSETn bits 5-15  
PEREN bit 5-4  
peripheral bus reset 2-2  
PFUNC 5-6  
M
PFUNCn bits 5-6  
PICLR 5-25  
mode selection  
TSI capture 3-2  
video capture 3-2  
video display 4-2  
PICLRn bits 5-25  
PIEN 5-19  
PIENn bits 5-19  
PIPOL 5-21  
N
NH bit  
PIPOLn bits 5-21  
PISTAT 5-23  
in VDIMGOFF1 4-69  
in VDIMGOFF2 4-71  
PISTATn bits 5-23  
PK10B bits  
noncontinuous frame capture for 525/60 format  
example A-2  
in VCACTL 3-53  
in VCBCTL 3-68  
noncontinuous frame display for 525/60 format  
example A-10  
power-on reset 2-2  
PRECISION bit 6-6  
notational conventions iii  
program clock reference (PCR) header 3-39  
PVPSYN bit 4-55  
NV bit  
in VDIMGOFF1 4-69  
in VDIMGOFF2 4-71  
R
O
raw data mode 3-32, 4-25  
capture notification 3-32  
capture selection 3-33  
capturing video 3-46  
displaying video 4-49  
FIFO overrun 3-47  
overview 1-2  
VIC port 6-2  
video capture 3-1  
FIFO packing 3-33  
FIFO unpacking 4-26  
P
PCR 5-4  
RDFE bit 3-53  
registers  
PCR bits 3-76  
PCR header 3-39  
PCRE bits 3-77  
PCRM bit 3-77  
PDCLR 5-17  
PDCLRn bits 5-17  
PDIN 5-11  
GPIO 5-2  
peripheral control register (PCR) 5-4  
peripheral identification register (VPPID) 5-3  
pin data clear register (PDCLR) 5-17  
pin data input register (PDIN) 5-11  
pin data output register (PDOUT) 5-13  
pin data set register (PDSET) 5-15  
pin direction register (PDIR) 5-8  
pin function register (PFUNC) 5-6  
pin interrupt clear register (PICLR) 5-25  
pin interrupt enable register (PIEN) 5-19  
pin interrupt polarity register (PIPOL) 5-21  
pin interrupt status register (PISTAT) 5-23  
PDINn bits 5-11  
PDIR 5-8  
PDIRn bits 5-8  
PDOUT 5-13  
PDOUTn bits 5-13  
Index-4  
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registers (continued)  
VIC port 6-5  
TSI system time clock compare mask MSB  
register (TSISTMSKM) 3-81  
TSI system time clock compare MSB register  
(TSISTCMPM) 3-79  
TSI system time clock LSB register  
(TSISTCLKL) 3-76  
VIC clock divider register (VICDIV) 6-9  
VIC control register (VICCTL) 6-6  
VIC input register (VICIN) 6-8  
video capture 3-49  
Cb FIFO source register (CBSRCx) 3-83  
channel A control register (VCACTL) 3-53  
channel A event count register  
(VCAEVTCT) 3-67  
TSI system time clock MSB register  
(TSISTCLKM) 3-77  
TSI system time clock ticks interrupt register  
(TSITICKS) 3-82  
channel A field 1 start register  
(VCASTRT1) 3-58  
Y FIFO source register (YSRCx) 3-83  
video display 4-52  
channel A field 1 stop register  
(VCASTOP1) 3-60  
channel A field 2 start register  
(VCASTRT2) 3-61  
channel A field 2 stop register  
(VCASTOP2) 3-62  
channel A status register (VCASTAT) 3-50  
channel A threshold register  
(VCATHRLD) 3-65  
Cb FIFO destination register (CBDST) 4-96  
clipping register (VDCLIP) 4-85  
control register (VDCTL) 4-55  
counter reload register (VDRELOAD) 4-83  
Cr FIFO destination register (CRDST) 4-96  
default display value register  
(VDDEFVAL) 4-86  
display event register (VDDISPEVT) 4-84  
field 1 image offset register  
channel A vertical interrupt register  
(VCAVINT) 3-63  
channel B control register (VCBCTL) 3-68  
channel B event count register  
(VCBEVTCT) 3-67  
(VDIMGOFF1) 4-68  
field 1 image size register (VDIMGSZ1) 4-70  
field 1 timing register (VDFLDT1) 4-74  
field 1 vertical blanking bit register  
(VDVBIT1) 4-90  
channel B field 1 start register  
(VCBSTRT1) 3-58  
field 1 vertical blanking end register  
(VDVBLKE1) 4-64  
channel B field 1 stop register  
(VCBSTOP1) 3-60  
field 1 vertical blanking start register  
(VDVBLKS1) 4-62  
channel B field 2 start register  
(VCBSTRT2) 3-61  
field 1 vertical synchronization end register  
(VDVSYNE1) 4-80  
channel B field 2 stop register  
(VCBSTOP2) 3-62  
field 1 vertical synchronization start register  
(VDVSYNS1) 4-79  
channel B status register (VCBSTAT) 3-50  
channel B threshold register  
(VCBTHRLD) 3-65  
channel B vertical interrupt register  
(VCBVINT) 3-63  
Cr FIFO source register (CRSRCx) 3-83  
FIFO 3-83  
TSI clock initialization LSB register  
(TSICLKINITL) 3-74  
TSI clock initialization MSB register  
(TSICLKINITM) 3-75  
TSI control register (TSICTL) 3-72  
TSI system time clock compare LSB register  
(TSISTCMPL) 3-78  
field 2 image offset register  
(VDIMGOFF2) 4-71  
field 2 image size register (VDIMGSZ2) 4-73  
field 2 timing register (VDFLDT2) 4-75  
field 2 vertical blanking bit register  
(VDVBIT2) 4-92  
field 2 vertical blanking end register  
(VDVBLKE2) 4-67  
field 2 vertical blanking start register  
(VDVBLKS2) 4-65  
field 2 vertical synchronization end register  
(VDVSYNE2) 4-82  
field 2 vertical synchronization start register  
(VDVSYNS2) 4-81  
TSI system time clock compare mask LSB  
register (TSISTMSKL) 3-80  
field bit register (VDFBIT) 4-89  
FIFO 4-96  
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registers (continued)  
video display  
SERRA bit  
in VPIE 2-21  
in VPIS 2-24  
SERRB bit  
frame size register (VDFRMSZ) 4-60  
horizontal blanking register  
(VDHBLNK) 4-61  
horizontal synchronization register  
(VDHSYNC) 4-78  
in VPIE 2-21  
in VPIS 2-24  
SFDA bit  
recommended values 4-94  
status register (VDSTAT) 4-53  
in VPIE 2-21  
in VPIS 2-24  
threshold register (VDTHRLD) 4-76  
vertical interrupt register (VDVINT) 4-88  
Y FIFO destination register A (YDSTA) 4-96  
Y FIFO destination register B (YDSTB) 4-96  
video port 2-16  
SFDB bit  
in VPIE 2-21  
in VPIS 2-24  
SFDE bit  
in VCACTL 3-53  
in VCBCTL 3-68  
control register (VPCTL) 2-17  
interrupt enable register (VPIE) 2-21  
interrupt status register (VPIS) 2-24  
peripheral control register (PCR) 5-4  
peripheral identification register (VPPID) 5-3  
pin data clear register (PDCLR) 5-17  
pin data input register (PDIN) 5-11  
pin data output register (PDOUT) 5-13  
pin data set register (PDSET) 5-15  
pin direction register (PDIR) 5-8  
pin function register (PFUNC) 5-6  
pin interrupt clear register (PICLR) 5-25  
pin interrupt enable register (PIEN) 5-19  
pin interrupt polarity register (PIPOL) 5-21  
pin interrupt status register (PISTAT) 5-23  
status register (VPSTAT) 2-20  
SOFT bit 5-4  
software port reset 2-3  
SSE bit 3-58  
STC bit  
in VPIE 2-21  
in VPIS 2-24  
STEN bit 3-72  
T
TCKEN bit 3-72  
throughput and latency 2-13  
TICK bit  
in VPIE 2-21  
in VPIS 2-24  
related documentation from Texas Instruments iii  
reset operation 2-2  
TICKCT bits 3-82  
RESMPL 4-55  
trademarks iv  
RESMPL bit  
TSI bit 2-17  
in VCACTL 3-53  
in VCBCTL 3-68  
TSI capture control register (TSICTL) 3-72  
TSI capture mode 3-37  
capture selection 3-40  
capturing data 3-47  
REVISION bits 5-3  
RGBX 4-55  
RSTCH bit 4-55  
in VCACTL 3-53  
in VCBCTL 3-68  
data capture 3-37  
data capture notification 3-40  
error detection 3-38  
RSYNC 4-55  
features 3-37  
FIFO overrun 3-48  
mode selection 3-2  
reading from the FIFO 3-42  
synchronizing the system clock 3-38  
timestamp format (big endian) 3-42  
timestamp format (little endian) 3-41  
writing to the FIFO 3-41  
S
SCALE bit 4-55  
in VCACTL 3-53  
in VCBCTL 3-68  
Index-6  
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TSI clock initialization LSB register  
(TSICLKINITL) 3-74  
VBLNKYSTOP2 bits 4-67  
VCACTL 3-53  
TSI clock initialization MSB register  
(TSICLKINITM) 3-75  
VCAEVTCT 3-67  
VCASTAT 3-50  
VCASTOP1 3-60  
VCASTOP2 3-62  
VCASTRT1 3-58  
VCASTRT2 3-61  
VCATHRLD 3-65  
VCAVINT 3-63  
TSI system time clock compare LSB register  
(TSISTCMPL) 3-78  
TSI system time clock compare mask LSB register  
(TSISTMSKL) 3-80  
TSI system time clock compare mask MSB register  
(TSISTMSKM) 3-81  
TSI system time clock compare MSB register  
(TSISTCMPM) 3-79  
VCBCTL 3-68  
VCBEVTCT 3-67  
VCBSTAT 3-50  
VCBSTOP1 3-60  
VCBSTOP2 3-62  
VCBSTRT1 3-58  
VCBSTRT2 3-61  
VCBTHRLD 3-65  
VCBVINT 3-63  
TSI system time clock LSB register  
(TSISTCLKL) 3-76  
TSI system time clock MSB register  
(TSISTCLKM) 3-77  
TSI system time clock ticks interrupt register  
(TSITICKS) 3-82  
TSICLKINITL 3-74  
TSICLKINITM 3-75  
TSICTL 3-72  
VCEN bit  
in VCACTL 3-53  
in VCBCTL 3-68  
VCFLD bit 3-50  
VCLK2P bit 2-17  
VCT1P bit 2-17  
VCT2P bit 2-17  
VCT3P bit 2-17  
VCTHRLD1 bits 3-66  
VCTHRLD2 bits 3-66  
VCTL1S bits 4-55  
VCTL2S bits 4-55  
VCTL3S bits 4-55  
VCVBLNKP bits 3-58  
TSISTCLKL 3-76  
TSISTCLKM 3-77  
TSISTCMPL 3-78  
TSISTCMPM 3-79  
TSISTMSKL 3-80  
TSISTMSKM 3-81  
TSITICKS 3-82  
TYPE bits 5-3  
V
VCXO interpolated control (VIC) port registers 6-5  
VCXPOS bits 3-50  
VCXSTART bits  
in VCxSTRT1 3-58  
in VCxSTRT2 3-61  
VCXSTOP bits  
VBITCLR1 bits 4-90  
VBITCLR2 bits 4-92  
VBITSET1 bits 4-90  
VBITSET2 bits 4-92  
VBLNK bit 4-53  
in VCxSTOP1 3-60  
in VCxSTOP2 3-62  
VCYSTART bits  
in VCxSTRT1 3-58  
in VCxSTRT2 3-61  
VCYSTOP bits  
VBLNKXSTART1 bits 4-63  
VBLNKXSTART2 bits 4-66  
VBLNKXSTOP1 bits 4-64  
VBLNKXSTOP2 bits 4-67  
VBLNKYSTART1 bits 4-63  
VBLNKYSTART2 bits 4-66  
VBLNKYSTOP1 bits 4-64  
in VCxSTOP1 3-60  
in VCxSTOP2 3-62  
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VDCLIP 4-85  
VICCLKDIV bits 6-9  
VICCTL 6-6  
VDCTL 4-55  
VICDIV 6-9  
VDDEFVAL 4-86  
VDDISPEVT 4-84  
VDEN 4-55  
VICIN 6-8  
VICINBITS bits 6-8  
video capture  
VDFBIT 4-89  
FIFO configurations 1-6  
FIFO registers 3-83  
mode selection 3-2  
overview 3-1  
registers 3-49  
signal mapping 1-13  
throughput 2-13  
VDFLD bit 4-53  
VDFLDT1 4-74  
VDFLDT2 4-75  
VDFRMSZ 4-60  
VDHBLNK 4-61  
VDHSYNC 4-78  
VDIMGOFF1 4-68  
VDIMGOFF2 4-71  
VDIMGSZ1 4-70  
VDIMGSZ2 4-73  
VDRELOAD 4-83  
VDSTAT 4-53  
video capture channel A control register  
(VCACTL) 3-53  
video capture channel A event count register  
(VCAEVTCT) 3-67  
video capture channel A field 1 start register  
(VCASTRT1) 3-58  
video capture channel A field 1 stop register  
(VCASTOP1) 3-60  
VDTHRLD 4-76  
VDTHRLD1 bits 4-76  
VDTHRLD2 bits 4-76  
VDVBIT1 4-90  
video capture channel A field 2 start register  
(VCASTRT2) 3-61  
video capture channel A field 2 stop register  
(VCASTOP2) 3-62  
VDVBIT2 4-92  
video capture channel A status register  
(VCASTAT) 3-50  
VDVBLKE1 4-64  
VDVBLKE2 4-67  
VDVBLKS1 4-62  
VDVBLKS2 4-65  
VDVINT 4-88  
video capture channel A threshold register  
(VCATHRLD) 3-65  
video capture channel A vertical interrupt register  
(VCAVINT) 3-63  
VDVSYNE1 4-80  
VDVSYNE2 4-82  
VDVSYNS1 4-79  
VDVSYNS2 4-81  
VDXPOS bits 4-53  
VDYPOS bits 4-53  
VIC clock divider register (VICDIV) 6-9  
VIC control register (VICCTL) 6-6  
VIC input register (VICIN) 6-8  
video capture channel B control register  
(VCBCTL) 3-68  
video capture channel B event count register  
(VCBEVTCT) 3-67  
video capture channel B field 1 start register  
(VCBSTRT1) 3-58  
video capture channel B field 1 stop register  
(VCBSTOP1) 3-60  
video capture channel B field 2 start register  
(VCBSTRT2) 3-61  
VIC port  
video capture channel B field 2 stop register  
(VCBSTOP2) 3-62  
enabling 6-5  
features 6-2  
interface 6-3  
operational details 6-3  
overview 6-2  
registers 6-5  
video capture channel B status register  
(VCBSTAT) 3-50  
video capture channel B threshold register  
(VCBTHRLD) 3-65  
Index-8  
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video capture channel B vertical interrupt register  
(VCBVINT) 3-63  
video display field 2 image size register  
(VDIMGSZ2) 4-73  
video display field 2 timing register  
(VDFLDT2) 4-75  
video capture FIFO configurations 1-6  
video capture mode  
BT.656 3-3  
raw data 3-32  
TSI 3-37  
video display field 2 vertical blanking bit register  
(VDVBIT2) 4-92  
video display field 2 vertical blanking end register  
(VDVBLKE2) 4-67  
Y/C 3-12  
video display  
video display field 2 vertical blanking start register  
(VDVBLKS2) 4-65  
counters 4-5  
external sync operation 4-8  
FIFO configurations 1-9  
FIFO overrun 4-51  
FIFO registers 4-96  
image timing 4-2  
mode selection 4-2  
port sync operation 4-8  
registers 4-52  
video display field 2 vertical synchronization end  
register (VDVSYNE2) 4-82  
video display field 2 vertical synchronization start  
register (VDVSYNS2) 4-81  
video display field bit register (VDFBIT) 4-89  
video display FIFO configurations 1-9  
video display frame size register (VDFRMSZ) 4-60  
video display horizontal blanking register  
(VDHBLNK) 4-61  
recommended values 4-94  
signal mapping 1-14  
sync signal generation 4-7  
throughput 2-15  
video display horizontal synchronization register  
(VDHSYNC) 4-78  
video display clipping register (VDCLIP) 4-85  
video display control register (VDCTL) 4-55  
video display mode  
BT.656 4-9  
display selection 4-31  
display timing examples 4-35  
field and frame operation 4-30  
raw data 4-25  
video display counter reload register  
(VDRELOAD) 4-83  
video display default display value register  
(VDDEFVAL) 4-86  
Y/C 4-16  
video display display event register  
(VDDISPEVT) 4-84  
video display status register (VDSTAT) 4-53  
video display threshold register (VDTHRLD) 4-76  
video display field 1 image offset register  
(VDIMGOFF1) 4-68  
video display vertical interrupt register  
(VDVINT) 4-88  
video display field 1 image size register  
(VDIMGSZ1) 4-70  
video input filtering 3-26  
video output filtering 4-21  
video display field 1 timing register  
(VDFLDT1) 4-74  
video port  
block diagram 1-4  
clocks 2-12  
video display field 1 vertical blanking bit register  
(VDVBIT1) 4-90  
control registers 2-16  
DMA interface 1-5  
DMA operation 2-6  
FIFO configurations 1-5  
interrupt operation 2-5  
operating mode selection 2-19  
overview 1-2  
video display field 1 vertical blanking end register  
(VDVBLKE1) 4-64  
video display field 1 vertical blanking start register  
(VDVBLKS1) 4-62  
video display field 1 vertical synchronization end  
register (VDVSYNE1) 4-80  
video display field 1 vertical synchronization start  
register (VDVSYNS1) 4-79  
pin mapping 1-13  
reset operation 2-2  
throughput and latency 2-13  
video display field 2 image offset register  
(VDIMGOFF2) 4-71  
video port control register (VPCTL) 2-17  
SPRU629  
Index-9  
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Index  
video port FIFO 1-5  
VPCTL 2-17  
VPHLT bit 2-17  
VPIE 2-21  
video port interrupt enable register (VPIE) 2-21  
video port interrupt status register (VPIS) 2-24  
video port peripheral control register (PCR) 5-4  
VPIS 2-24  
video port peripheral identification register  
(VPPID) 5-3  
VPPID 5-3  
VPRST bit 2-17  
VPSTAT 2-20  
VRLD bits 4-83  
video port pin data clear register (PDCLR) 5-17  
video port pin data input register (PDIN) 5-11  
video port pin data output register (PDOUT) 5-13  
video port pin data set register (PDSET) 5-15  
video port pin direction register (PDIR) 5-8  
video port pin function register (PFUNC) 5-6  
video port pin interrupt clear register (PICLR) 5-25  
video port pin interrupt enable register (PIEN) 5-19  
VRST bit  
in VCACTL 3-53  
in VCBCTL 3-68  
VSYNCXSTART1 bits 4-79  
VSYNCXSTART2 bits 4-81  
VSYNCXSTOP1 bits 4-80  
VSYNCXSTOP2 bits 4-82  
VSYNCYSTART1 bits 4-79  
VSYNCYSTART2 bits 4-81  
VSYNCYSTOP1 bits 4-80  
VSYNCYSTOP2 bits 4-82  
VXS bit 4-55  
video port pin interrupt polarity register  
(PIPOL) 5-21  
video port pin interrupt status register  
(PISTAT) 5-23  
video port pin mapping 1-13  
video port status register (VPSTAT) 2-20  
VIE bit 2-21  
VIF1 bit  
in VCxVINT 3-63  
in VDVINT 4-88  
Y
VIF2 bit  
Y FIFO destination register A (YDSTA) 4-96  
Y FIFO destination register B (YDSTB) 4-96  
Y FIFO source register (YSRCx) 3-83  
in VCxVINT 3-63  
in VDVINT 4-88  
VINT1 bits  
in VCxVINT 3-63  
in VDVINT 4-88  
Y/C mode 3-12, 4-16  
blanking codes 4-17  
capture channels 3-12  
capture selection 3-18  
capturing video 3-44  
VINT2 bits  
in VCxVINT 3-63  
in VDVINT 4-88  
displaying video 4-47  
field and frame operation 3-17  
FIFO overrun 3-45  
FIFO packing 3-14  
FIFO unpacking 4-17  
image display 4-17  
VINTA1 bit  
in VPIE 2-21  
in VPIS 2-24  
VINTA2 bit  
in VPIE 2-21  
in VPIS 2-24  
image window and capture 3-13  
timing reference codes 3-12, 4-16  
VINTB1 bit  
in VPIE 2-21  
in VPIS 2-24  
YDEFVAL bits 4-86  
YDSTA 4-96  
VINTB2 bit  
YDSTB 4-96  
in VPIE 2-21  
in VPIS 2-24  
YSRCx 3-83  
Index-10  
SPRU629  
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