CDCM7005 (QFN Package)
Evaluation Module Manual
HPA/High Speed Communications
User’s Guide
2005
Clock Drivers
SCAU015
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EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any
machine, process, or combination in which such TI products or services might be or are used.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
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EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the supply voltage range of 3 V and 3.6 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
45°C. The EVM is designed to operate properly with certain components above 60°C as long
as the input and output ranges are maintained. These components include but are not limited
to linear regulators, switching transistors, pass transistors, and current sense resistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
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Preface
Read This First
About This Manual
This manual explains how to use the CDCM7005 evaluation module (EVM)
and provides guidelines to build the customer’s own systems. The manual
includes schematics, layout, bill of materials, and a software description.
How to Use This Manual
This document contains the following chapters:
- Chapter 1—Introduction
- Chapter 2—Quick Start
- Chapter 3—EVM Hardware
- Chapter 4—Serial Peripheral Interface (SPI) Software
- Chapter 5—Schematics, Board Layout, and Parts List
Related Documentation From Texas Instruments
- CDCM7005 Data Sheet, SCAS793, Texas Instruments
FCC Warning
This equipment is intended for use in a laboratory test environment only. It
generates, uses, and can radiate radio frequency energy and has not been
tested for compliance with the limits of computing devices pursuant to subpart
J of part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case the user at his own expense will be required to take whatever measures
may be required to correct this interference.
If You Need Assistance. . .
If you need assitance with this device, please email
iii
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Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
CDCM7005 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
2
3
Quick Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
EVM Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1
3.2
Board View and Connector Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2.1 Power Supply (P1, P2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2.2 Onboard Switches and Indicators (SW1−SW2, D1−D4) . . . . . . . . . . . . . . . . . . . 3-2
3.2.3 Programming Interfaces (J30, J31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2.4 Loop Filter (J32−J34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2.5 High-Speed Outputs and Inputs (J1−J4, J6−J11, J13, J14, J22, and J23) . . . 3-3
3.2.6 VCXO Inputs and Outputs (J16−J18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.2.7 AC-Coupling at PRI_REF (C1, R4, R6) and SEC_REF (C5, R13, R15) . . . . . 3-4
4
5
Serial Peripheral Interface (SPI) Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1
4.2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Application Level Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1
Application Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.1 Passive Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.1.2 External Active Loop Filter Using OPA341 . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
6
Parts List, Board Layouts, and Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1
6.2
6.3
Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
v
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Figures
3−1
4−1
5−1
5−2
6−1
6−2
6−3
6−4
6−5
6−6
Board View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Screen View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
CDCM7005 With a Passive Loop Filter Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
CDCM7005 With an External Active Loop Filter Using OPA341 . . . . . . . . . . . . . . . . . . . . . 5-3
Component View and Silkscreen (Top Side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Component View and Silkscreen (Bottom Side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Top Layer View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Bottom Layer View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Ground Plane View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
Power Layer View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Tables
3−1
Filter Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
vi
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Chapter 1
Introduction
The CDCM7005 is a high-performance, low phase noise and low skew clock
synchronizer that synchronizes an on-board voltage controlled crystal
oscillator (VC(X)O) frequency to an external reference clock. The device
operates up to 2.2 GHz. The PLL loop bandwidth and damping factor can be
adjusted to meet different system requirements by selecting the external
VC(X)O, loop filter components, frequency for PFD, and charge pump current.
Each of the five differential LVPECL and five LVCMOS pair outputs can be
programmed by a serial peripheral interface (SPI). The SPI allows individual
control of the frequency and enable/disable state of each output. As the
system requires external components like a loop filter and VC(X)O, this EVM
provides an easy method to evaluate and modify the performance and
parameters of the clock system in conjunction with the specific customer
application. Loop bandwidth can be selected as low as 10 Hz or less, allowing
the device to clean the system’s clock jitter.
In non PLL mode, the CDCM7005 can be used as a simple LVPECL or
LVCMOS buffer with divider options.
Topic
Page
1.1 CDCM7005 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1-1
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CDCM7005 Functional Block Diagram
1.1 CDCM7005 Functional Block Diagram
AVCC
VCC_CP
VCC
Selected REF Signal
STATUS_REF /
PRI_SEC_CLK
STATUS_VCXO
/ I_REF_CP
Manual &
Automatic
CLK Select
REF_SEL
freq. detect
> 2 MHz
PLL_LOCK
freq. detect
> 2 MHz
LOCK
PFD
HOLD
PRI_REF
SEC_REF
Progr. Divider
M
Progr. Delay
M
LVCMOS
210
Reference
Clock
Charge
Pump
CP_OUT
Feedback
Clock
Progr. Delay
N
Progr. Divider
212
N
Current
SPI LOGIC
CTRL_LE
CTRL_DATA
CTRL_CLK
Reference
PECL
LV
CMOS
to
LVCMOS
Y0A
Y0B
PD
LV
PECL
FB_MUX
RESET or
HOLD
LV
CMOS
LV
CMOS
Y1A
Y1B
LV
÷ 1
÷ 2
÷ 3
÷ 4
÷ 6
÷8
PECL
LV
CMOS
LV
CMOS
Y2A
Y2B
VCXO_IN
VCXO_IN
PECL
INPUT
LV
PECL
LV
CMOS
÷ 16
÷ 4
LV
CMOS
Y3A
Y3B
÷ 8
LV
P16−Div
PECL
P Divider
LV
CMOS
LV
CMOS
Bias Generator
CC
VBB
V
− 1.3 V
Y4A
Y4B
LV
PECL
LV
CMOS
GND
1-2
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Chapter 2
Quick Start
In order to setup the EVM quickly and to take some measurements at default
settings, the following actions are required:
- Supply 3.3 V to P1, LED D4 will be on.
- Apply a single-ended reference clock to the reference clock input
PRI_REF (pin A1) or SEC_REF (pin B1). For default setting, the reference
th
clock must be 1/8 of the VC(X)O frequency. If REF_SEL is set to 1, then
PRI_REF is selected. If REF_SEL is set to 0, then SEC_REF is selected.
This selection can be realized via J26 (header 1 and 2 is high; header 2
and 3 is low).
- Connect Y0/Y0B (or Y1/Y1B) to oscilloscope in order to check an output
signal. Ensure the oscilloscope has 50 Ω to ground termination.
After power up, D1 is on if there is a valid reference clock and D2 is on if there
is a valid VC(X)O clock for the CDCM7005. If D3 turns on, then the reference
clock and the VC(X)O clocks are phase locked.
2-1
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Chapter 3
EVM Hardware
This chapter discusses the EVM hardware.
Topic
Page
3.1 Board View and Connector Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3-1
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Board View and Connector Location
3.1 Board View and Connector Location
Figure 3−1. Board View
3.2 Hardware Configuration
This section describes the board configuration using on-board jumpers and
solder bridges.
3.2.1 Power Supply (P1, P2)
- Supply 3.3 V 10% on P1 and P2 using a stabilized external power supply.
WARNING: Never supply more than 3.6 V on P1.
J
3.2.2 Onboard Switches and Indicators (SW1−SW2, D1−D4)
- Push SW1 to enter the power-down mode of the CDCM7005 device. Then
all current sources are switched off, all outputs are switched into 3-state,
and all dividers (M, N, and P) are reset to default.
- Push SW2 to enter the reset mode of the device. The charge pump (CP)
is switched to 3-state and all counters (N, M, P) are rest to zero (the initial
divider settings are maintained in SPI.
- The three status outputs of the CDCM7005 are fed to LED indicators. D1
on indicates a valid reference input clock signal. D2 is on if the VC(X)O
input clock is valid and D3 turns on if the PLL has been locked.
- D4 indicates power supply
Note:
In case of a low input impedance of the VC(X)O control voltage input, there
is a possibility D3 may not turn on to indicate locking.
3-2
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Hardware Configuration
3.2.3 Programming Interfaces (J30, J31)
The SPI of the device is used for writing to the control register of the device.
It consists of three control lines CTRL_CLK, CTRL_DATA, and CTRL_LE.
There are four 30-bit wide RAM registers, which can be addressed by the two
LSBs of a transferred word. Every transmitted word must have 32 bits, starting
with MSB. After supplying power or activating the power-down mode, the
registers are loaded with the device default values internally (see the
CDCM7005 data sheet, SCAS793). However, if specific register settings are
required for any applications, there are two ways to program the device
externally:
- Connect the parallel port cable to the PC and EVM parallel port. This
needs control S/W (see Chapter 4).
3.2.4 Loop Filter (J32−J34)
The loop filter is one of the key elements determining the loop bandwidth of
the PLL. The loop filter converts the charge pump current into the control
voltage for the voltage controlled oscillator. The phase difference between the
input clocks of the phase frequency detector determines the width of the
charge pump output current pulses. These high frequency pulses are
transformed into a voltage to control the oscillator.
Basically, three types of loop filters are implemented on the EVM.
- Passive loop filter
- External active loop filter using an external low-noise OPA.
Filter types can be selected by soldering bridges J32−J34, see Table 3−1.
Control voltage of the VC(X)O can be measured at J9 or TP1. If an external
OPA is used, it needs to be switched on by connecting J34. For example,
passive filter operation is provided when pads 1 and 3 of J33 are solder bridged
and pads 1 and 3 of J32 are solder bridged.
Default setting: Passive Loop Filter
Table 3−1.Filter Configurations
Bridge
J33
Passive Filter
1−3
Active With An External OPA
1−2
Closed
1−2
J34
Open
J32
1−3
3.2.5 High-Speed Outputs and Inputs (J1−J4, J6−J11, J13, J14, J22, and J23)
The CDCM7005 drives five differential LVPECL outputs. All PECL outputs are
ac-coupled and terminated with 150 Ω to GND. This is in contrast to typical
LVPECL termination, which requires V − 2 V as termination voltage. The
CC
reason is to simplify the power supply scheme. The device output’s trace
impedance is 50 Ω and traces are matched in length. All outputs have options
for pullup and pulldown resistors.
EVM Hardware
3-3
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Hardware Configuration
When the CDCM7005 is powered up, it defaults to five LVPECL outputs.
However, this EVM is configured as follows:
- Y0 − Y2 = LVPECL
- Y3, Y4 = LVCMOS (in addition Y4 has an option for a custom filter)
The reference input clock signal has to be applied to J1 or J6. The reference
input clock signal can be sensed on J4. In this case, close the bridge J5 (the
oscilloscope’s 50 Ω may be used to terminate the 50-Ω trace). The reference
input clock sense line is matched to the LVPECL outputs line to avoid any
additional delay offset. The input is ac-coupled (C4).
3.2.6 VC(X)O Inputs and Outputs (J16−J18)
The CDCM7005 requires an external VC(X)O in order to complete the PLL
loop. The VC(X)O adjusts the frequency and phase depending on the control
voltage level coming from the loop filter and provide the input clock to the
LVPECL block.
Another option would be to use an external source via J16 and J18.
3.2.7 AC-Coupling at PRI_REF (C1, R4, R6) and SEC_REF (C5, R13, R15)
An ac-coupling is provided at PRI_REF and SEC_REF to ease the use of the
CDCM7005 with different signaling levels (LVCMOS, LVPECL, LVDS,...).
However, the ac-coupling will increase the PLL stabilization time after power
up due to transient effects. It also increases the switching time between
PRI_REF and SEC_REF in case of automatic reference clock switching.
Therefore, the ac-coupling must be removed for optimized system
performance (C1 and C5 has to be replaced with an 0-Ω resistor and R4, R6,
R13, and R15 have to be removed).
3-4
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Chapter 4
Serial Peripheral Interface (SPI) Software
This chapter discusses the serial peripheral interface software.
Topic
Page
4.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4-1
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Functional Description
4.1 Functional Description
Programming software here as described is intended for programming the in-
ternal control register of the CDCM7005. The software runs under Win-
dows98, NT, 2000, and XP. A quick installation is required prior to use. See the
Software Installation section.
There are several cases where programming is mandatory.
As a rule of thumb here are some examples:
- Use of active loop filter
- Change of divider ratio or disable of certain LVPECL/LVCMOS outputs
- Select between LVPECL or LVCMOS output
- Change of phase offset, (Delay M/N), or selection of 90’ or 180’ phase shift
- Change of charge pump output current.
- Widening the lock detect window
Figure 4−1. Screen View
4.2 Software Installation
Follow the steps below in order to install the SPI control software:
1) Run program setup.exe in the Installer folder
2) Reboot your computer
3) Run the Software from Start −> Programs −> CDCM7005_EVM −>
CDCM7005_EVM
4-2
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Chapter 5
Application Circuit Diagram
This chapter discusses the application circuit diagram.
Topic
Page
5.1 Application Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5-1
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Application Circuit Diagram
5.1 Application Circuit Diagram
The following applications sections the two loop filter configurations are
discussed.
5.1.1 Passive Loop Filter
The passive loop filter is a second order filter (two poles, one zero). The zero
is required for the overall loop stability. R1, C1, and C2 generate the dominant
pole of the system. A second pole is introduced by R2 and C3.
Figure 5−1. CDCM7005 With a Passive Loop Filter Configuration
Low-Pass Filter
R2
160 Ω
VC(X)O
491.52 MHz
V_CTRL
PECL_OUT_B
PECL_OUT
C3
100 nF
CDCM7005
PRI_REF
SEC_REF
R1
4.7 kΩ
C2
100 nF
CP_OUT
C1
22 µF
CTRL_LE
CTRL_DATA
CTRL_CLK
SPI
STATUS_REF
V
STATUS_VC(X)O
PLL_LOCK
V
CC
CC
10 nF
130 Ω
YnA
130 Ω
10 nF
VC(X)O_IN
VC(X)O_IN_B
YnB
R
82 Ω
R
82 Ω
R
150 Ω
R
150 Ω
5-2
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Application Circuit Diagram
5.1.2 External Active Loop Filter Using OPA341
Figure 5−2. CDCM7005 With a External Active Loop Filter Using OPA341
Low-Pass Filter
VC(X)O
R3
10 kΩ
491.52 MHz
PECL_OUT_B
PECL_OUT
V_CTRL
C3
100 nF
C2
10 µF
R2
4.7 kΩ
Vcc
Vcc
CDCM7005
PRI_REF
R5
10 kΩ
InN
SEC_REF
R1
180 Ω
OPA341
InP
Out
CP_OUT
R6
10 kΩ
C1
100 nF
CTRL_LE
CTRL_DATA
CTRL_CLK
STATUS_REF
STATUS_VC(X)O
PLL_LOCK
C1
100 nF
SPI
V
V
CC
CC
130 Ω
10 nF
10 nF
YnA
YnB
130 Ω
VC(X)O_IN
VC(X)O_IN
R
150 Ω
R
150 Ω
R
82 Ω
R
82 Ω
Application Circuit Diagram
5-3
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Chapter 6
Parts List, Board Layout, and Schematics
This chapter contains the parts list, board layout, and schematics for the
CDCM7005 EVM.
Topic
Page
6.1 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.3 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6-1
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Parts List
6.1 Parts List
Item QTY
Reference
Footprint
Part
Part Number
Panasonic
Designator
1
24
C1−C9, C12,
C13, C15, C17,
C26, C40, C41,
C46, C47, C53,
C54, C56−C58,
C66
smd_cap_0402
10 nF
ECJ−0EB1E103K
2
3
2
7
C72, C10
smd_cap_0402
smd_cap_0402
100 nF
100 pF
Panasonic
ECJ−0EB1E104K
Panasonic
ECJ−0EB1E101K
C11, C32,
C62−C64, C68,
C73
4
5
2
1
1
2
1
1
1
1
7
1
1
3
4
C14, C16
smd_cap_0402
smd_cap_0402
smd_cap_0603
smd_cap_0402
smd_cap_0402
smd_cap_0402
smd_cap_0402
smd_cap_0402
smd_cap_0805
smd_cap_1210
smd_cap_0402
smd_cap_0402
smd_cap_1210_pol
smd_cap_1210_pol
smd_cap_1210_pol
smd_cap_0402
0 Ω
1000 pF
1 µF
Panasonic
ERJ−2GE0R00X
Panasonic
ECJ−0EB1E102K
Panasonic
ECJ−1VF1C105Z
Panasonic
ECJ−0EB1A104K
Panasonic
ECJ−0EB1E103K
NU Rohm
MCH155A1R1CK
Panasonic
ECJ−0EC1H220J
NU Rohm
MCH155A1R1CK
Panasonic
ECP−U1C104MA5
Murata
GRM32ER71A226KE20L
Panasonic
ECJ−0EB1E104K
Panasonic
ECJ−0EF1H103Z
Panasonic
ECS−T1CC226R
Panasonic
ECS−T1CC226R
Panasonic
ECS−H1CC106R
Yageo
C18
6
C19
7
C20, C22
C21
0.1 µF
10 nF
8
9
C23
NU 1.1 pF
22 pF
10
11
12
13
14
15
16
C24
C25
NU 1 pF
0.1 µF
22 µF
C27−C29, C75,
C76, C79, C80
C30
C31
22 nF
C33−C35
10 nF
C36, C42, C48,
C49
22 µF
C49
22 µF
17
18
5
3
C37, C43, C50,
C55, C65
C38, C44, C51
10 µF
100 nF
04022F104Z7B20D
19
20
21
3
4
3
C39, C45, C52
C59−C61, C67
C69−C71
smd_cap_0402
smd_cap_0402
smd_cap_0402
33 nF
2.2 nF
10 pF
AVX 0402YD333KAT2A
AVX 0402YC223KAT2A
Panasonic
ECD−G0E100C
6-2
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Parts List
Part Number
Murata
Item QTY
Reference
Designator
Footprint
Part
10 µF
10 µF
NU
22
2
C74
C77
C78
smd_cap_1210
smd_cap_1210
smd_cap_0805
GRM32DR61E106KA12L
Murata
GRM32DR61E106KA12L
23
1
Panasonic
ECP−U1C104MA5
24
25
3
1
D1−D3
smd_led_1206
smd_led_1206
Amber
Lite−On LTST−C150AKT
D4
GREEN
Lite−On
LTST−C150KGKT
26
27
1
7
FLT1
ts−38s
TS−38S
Toyocom Filter
J1−J4, J6−J8
sma_alt
SMA
Johnson Comp
142−0701−841
28
29
1
9
J5
jumper2
sma_alt
HEADER 2
NU_SMA
J9−J11, J13,
J14, J16, J18,
J22, J23
Johnson Comp
142−0701−841
30
31
4
2
J12, J25, J26,
J27
hdr3_100ctr
HDR3
Header 3 pos, 0.1 ctr
J17, J15
smd_bridge_0402
SMD3P_BRIDGE Panasonic
ERJ−2GE0R00X
Header 2 pos, 0.1 ctr
SMD3P_BRIDGE Panasonic
ERJ−2GE0R00X
32
33
1
2
J19
jumper2
HDR2
J21, J20
smd_bridge_0402
34
35
3
1
J24, J28, J29
J30
jumper2
HDR2
Header 2 pos, 0.1 ctr
dcon25m
PARALLEL
PORT
SPC Technology
DB−25P−PCB
36
37
1
2
J31
jumper4
HDR4
Header 4 pos, 0.1 ctr
J33, J32
JUMPER3_SMD_WVIA_CD HDR 3_cdc7005 Use 0 W to short pins
C7005
(see assy dwg)
38
39
1
1
J34
L1
jumper2
HDR2
Header 3 pos, 0.1 ctr
smd_cap_0603
75 Ω at100 MHz Murata
BLM18BA750SN1D
Murata
40
41
42
43
1
2
3
1
L2
smd_cap_0603
smd_cap_0603
smd_cap_0603
smd_cap_0805
470 nH
180 nH
LQW18ANR47J00D
L4, L3
L5−L7
L8
Panasonic
ELJ−FJR18JF2
75 Ω at 100 MHz Murata
BLM18BA750SN1D
2.2 nH
J W Miller Magnetics
PM0805−2N2M
44
45
46
1
1
P1
P2
banana_jack
banana_jack
smd_res_0402
PWR_IN
GND
SPC Technologies 845R
SPC Technologies 845B
18
R1, R2, R7, R9,
R10, R11, R16,
R18−R20, R22,
R24, R26, R27,
R30, R35, R48,
R50
NU 100 Ω
Panasonic
ERJ−2RKF1000X
47
2
R3, R12
smd_res_0402
NU
Panasonic
ERJ−2GEJ510X
Parts List, Board Layout, and Schematics
6-3
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Parts List
Item QTY
Reference
Designator
Footprint
Part
Part Number
Panasonic
48
49
50
7
6
R4, R6, R13, R15,
R62, R63, R65
smd_res_0402
smd_res_0402
smd_res_0402
100 Ω
150 Ω
10 kΩ
ERJ−2RKF1000X
R5, R8, R14, R17,
R21, R23
R25, R57, R59,
R60, R68−R71,
R74, R75
Panasonic
ERJ−2RKF1500X
Panasonic
ERJ−2RKF1002X
10
51
52
53
54
55
2
4
R28, R45
smd_res_0402
smd_res_0402
smd_res_0402
smd_res_0402
smd_res_0402
NU 0 Ω
NU 150 Ω
130 Ω
0 Ω
Panasonic
ERJ−2GE0R00X
R29, R32, R49,
R80
Panasonic
ERJ−2RKF1500X
Panasonic
ERJ−2GEJ131X
2
R38, R31
10
2
R33, R34, R41,
R42, R82,−R87
Panasonic
ERJ−2GE0R00X
R43, R36
82 Ω
Panasonic
ERJ−2GEJ820X
56
57
2
2
R37, R44
R39, R40
smd_res_0402
smd_res_0402
NU
62 W
NU
Panasonic
ERJ−2GEJ620X
58
59
60
61
62
63
64
65
66
67
2
4
1
2
3
1
1
1
3
2
R47, R46
smd_res_0402
smd_res_0402
smd_res_0402
smd_res_0402
smd_res_0402
smd_res_0402
smd_cap_0402
smd_res_0402
smd_res_0402
switch_reset
NU 100
100 kΩ
160 Ω
Panasonic
ERJ−2RKF1000X
R51, R64, R66,
R67
Panasonic
ERJ−2RKF1003X
Panasonic
ERJ−2RKF1002X
R52
R53, R72
R54−R56
R58
4.7 kΩ
750
Panasonic
ERJ−2RKF1472X
Panasonic
ERJ−2GEJ131X
NU 12K 1%
1.5 kΩ
180 Ω
Panasonic
ERJ−2RKF4121X
R61
Panasonic
ERJ−2RKF1501X
Panasonic
ERJ−2RKF1472X
R73
R78, R79, R81
SW2, SW1
22 Ω
Panasonic
ERJ−2GEJ220X
KT11P3JM
SW
PUSHBUTTON
68
69
2
1
TP1, TP2
U2
testpin_30dia
mbga_pt8mm_64_skt
T POINT R
CDCM7005
Test point
Texas Instruments
CDCM7005
70
1
U3
soic14
SN74LV125
Texas Instruments
SN74LV125AD
71
72
1
1
U4
U5
soic_round_4
soic8
NU SGA−4586
NU Sirenza SGA−4586
Texas Instruments
OPA341UA
OPA341
73
74
75
1
4
4
VCXO1
MP3
VCXO_6
STAND OFF
SCREW
VCXO_6
Toyocom VCXO
Legs for PCB
Legs for PCB
MP2
6-4
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Parts List
6.2 Board Layout
Figure 6−1. Component View and Silkscreen (Top View)
Parts List, Board Layout, and Schematics
6-5
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Parts List
Figure 6−2. Component View and Silkscreen (Bottom View)
6-6
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Parts List
Figure 6−3. Top Layer View
Parts List, Board Layout, and Schematics
6-7
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Parts List
Figure 6−4. Bottom Layer View
6-8
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Parts List
Figure 6−5. Ground Plane View
Parts List, Board Layout, and Schematics
6-9
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Parts List
Figure 6−6. Power Layer View
6.3 Schematics
The following pages contain the schematics for the CDCM7005 (QFN
package).
6-10
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Parts List
2
2
2
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
1
1
1
2
2
1
2
1
2
1
1
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
2
2
2
1
2
1
2 1
2
Parts List, Board Layout, and Schematics
6-11
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Parts List
3
2
1
3
2
1
6-12
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Parts List
2
1
1
2
1
2
1
2
1
4
8
7
5
2
2
1
1
1
2
2
1
3
2
1
2
1 2
2
1
1
1
2
1
3
2
1
2
Parts List, Board Layout, and Schematics
6-13
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Parts List
2
1
O U T B
O U T
3
3
3
3
3
3
3
1
1
2
1
2
3
3
1
2
3
3
2
1
2
3
3
1
3
3
2
1
2
1
1
2
3
1
1
2
1
2 1
2
1
2
1
2
1
2
2
1
2
1
1
2
1
1
2
2
1
1
2
2
1
1
2
2
1
2
1
2
2 1
2
1
3
2 1
2
4
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
3
1
2
1
2
1
2
6-14
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Parts List
1
2
1
2
1
2
Parts List, Board Layout, and Schematics
6-15
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