Rev. 1.0, Sep. 2010
M391B5773DH0
M391B5273DH0
240pin Unbuffered DIMM
1.35V
based on 2Gb D-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
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All brand names, trademarks and registered trademarks belong to their respective owners.
ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved.
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Rev. 1.0
Unbuffered DIMM
datasheet
DDR3L SDRAM
Table Of Contents
240pin Unbuffered DIMM based on 2Gb D-die
1. DDR3L Unbuffered DIMM Ordering Information...........................................................................................................4
2. Key Features.................................................................................................................................................................4
3. Address Configuration ..................................................................................................................................................4
4. x72 DIMM Pin Configurations (Front side/Back side) ...................................................................................................5
5. Pin Description .............................................................................................................................................................6
6. SPD and Thermal Sensor for ECC UDIMMs ................................................................................................................6
7. Input/Output Functional Description..............................................................................................................................7
7.1 Address Mirroring Feature....................................................................................................................................... 8
7.1.1. DRAM Pin Wiring Mirroring.............................................................................................................................. 8
8. Function Block Diagram:...............................................................................................................................................9
9. Absolute Maximum Ratings ..........................................................................................................................................11
10. AC & DC Operating Conditions...................................................................................................................................11
11. AC & DC Input Measurement Levels..........................................................................................................................12
11.1 AC & DC Logic Input Levels for Single-ended Signals.......................................................................................... 12
Tolerances.................................................................................................................................................... 14
REF
11.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................................. 15
11.4 Slew Rate Definition for Single Ended Input Signals............................................................................................. 19
11.5 Slew rate definition for Differential Input Signals................................................................................................... 19
12. AC & DC Output Measurement Levels .......................................................................................................................19
12.1 Single Ended AC and DC Output Levels............................................................................................................... 19
12.2 Differential AC and DC Output Levels................................................................................................................... 19
13. IDD specification definition..........................................................................................................................................22
14. IDD SPEC Table.........................................................................................................................................................24
15. Input/Output Capacitance ...........................................................................................................................................25
16. Electrical Characteristics and AC timing.....................................................................................................................26
16.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin................................................................. 26
17. Timing Parameters by Speed Grade ..........................................................................................................................30
18. Physical Dimensions...................................................................................................................................................35
18.1 256Mbx8 based 256Mx72 Module (1 Rank) - M391B5773DH0............................................................................ 35
18.2 256Mbx8 based 512Mx72 Module (2 Ranks) - M391B5273DH0.......................................................................... 36
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Rev. 1.0
Unbuffered DIMM
datasheet
DDR3L SDRAM
1. DDR3L Unbuffered DIMM Ordering Information
Number of
Height
Part Number2
Density
Organization
Component Composition
Rank
M391B5773DH0-YF8/H9/K0
M391B5273DH0-YF8/H9/K0
2GB
4GB
256Mx64
512Mx72
256Mx8(K4B2G0846D-HY##)*9
256Mx8(K4B2G0846D-HY##)*18
1
2
30mm
30mm
NOTE :
1. "##" - F8/H9/K0
2. F8 - 1066Mbps 7-7-7 / H9 - 1333Mbps 9-9-9 / K0 - 1600Mbps 11-11-11
- DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)
- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)
2. Key Features
DDR3-800
6-6-6
2.5
DDR3-1066
7-7-7
DDR3-1333
9-9-9
1.5
DDR3-1600
Speed
Unit
11-11-11
1.25
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
1.875
7
ns
nCK
ns
6
9
11
15
13.125
13.125
37.5
13.5
13.5
36
13.75
13.75
35
15
ns
tRAS(min)
tRC(min)
37.5
52.5
ns
50.625
49.5
48.75
ns
•
•
JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) Power Supply
VDDQ = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
•
400MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin
•
•
•
•
•
8 independent internal bank
Programmable CAS Latency: 6,7,8,9,10,11
Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
Programmable CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600)
Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
•
•
•
Bi-directional Differential Data Strobe
On Die Termination using ODT pin
Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C
•
Asynchronous Reset
3. Address Configuration
Organization
Row Address
Column Address
Bank Address
Auto Precharge
256Mx8(2Gb) based Module
A0-A14
A0-A9
BA0-BA2
A10/AP
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Rev. 1.0
Unbuffered DIMM
datasheet
DDR3L SDRAM
4. x72 DIMM Pin Configurations (Front side/Back side)
Pin
Front
VREFDQ
VSS
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
Back
Pin
42
43
44
45
46
47
48
Front
Pin
162
163
164
165
166
167
168
Back
Pin
82
Front
DQ33
VSS
Pin
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
Back
VSS
VSS
1
NC
NC
VSS
2
DQ4
DQ5
VSS
NC
83
DM4
NC
VSS
3
DQ0
DQ1
VSS
CB6
CB7
VSS
84
DQS4
DQS4
VSS
VSS
4
CB2
CB3
VSS
85
5
DM0
NC
86
DQ38
DQ39
VSS
NC (TEST)3
Reset
6
DQS0
DQS0
VSS
87
DQ34
DQ35
VSS
VSS
DQ6
DQ7
VSS
7
NC
88
8
KEY
89
DQ44
DQ45
VSS
CKE1,NC1
VDD
9
DQ2
DQ3
VSS
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
NC
CKE0
VDD
BA2
NC
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
90
DQ40
DQ41
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
91
DQ12
DQ13
VSS
NC
A14
VDD
92
DM5
NC
DQ8
DQ9
VSS
93
DQS5
DQS5
VSS
VSS
94
VDD
A11
A7
DM1
NC
A12/BC
A9
95
DQ46
DQ47
VSS
DQS1
DQS1
VSS
96
DQ42
DQ43
VSS
VSS
VDD
97
VDD
A5
DQ14
DQ15
VSS
A8
A6
98
DQ52
DQ53
VSS
DQ10
DQ11
VSS
99
DQ48
DQ49
VSS
VDD
A4
100
101
102
103
104
VDD
DQ20
DQ21
VSS
A3
A1
DM6
NC
DQ16
DQ17
VSS
A2
DQS6
DQS6
VSS
VDD
VDD
VSS
CK1,NC2
VDD
DM2
NC
DQ54
DQ55
VSS
CK1,NC2
VDD
24
25
26
27
28
29
30
31
32
33
34
35
36
DQS2
DQS2
VSS
144
145
146
147
148
149
150
151
152
153
154
155
156
64
65
66
67
68
69
70
71
72
73
74
75
76
184
185
186
187
188
189
190
191
192
193
194
195
196
CK0
CK0
VDD
105
106
107
108
109
110
111
112
113
114
115
116
117
DQ50
DQ51
VSS
225
226
227
228
229
230
231
232
233
234
235
236
237
VSS
VDD
DQ22
DQ23
VSS
DQ60
DQ61
VSS
VREFCA
DQ18
DQ19
VSS
EVENT
A0
DQ56
DQ57
VSS
NC
VDD
VDD
DQ28
DQ29
VSS
DM7
NC
DQ24
DQ25
VSS
A10/AP
BA0
BA1
VDD
DQS7
DQS7
VSS
VSS
VDD
DM3
NC
RAS
S0
DQ62
DQ63
VSS
DQS3
DQS3
VSS
WE
DQ58
DQ59
VSS
VSS
VDD
CAS
VDD
VDDSPD
DQ30
DQ31
VSS
ODT0
A13
S1, NC1
DQ26
DQ27
VSS
SA0
SA1
SDA
VSS
VTT
ODT1, NC1
VDD
VDD
37
38
39
40
41
157
158
159
160
161
77
78
79
80
81
197
198
199
200
201
118
119
120
SCL
SA2
VTT
238
239
240
CB4
CB5
VSS
NC
VSS
CB0
CB1
VSS
NC
VSS
DQ36
DQ37
DM8
DQ32
NOTE :
NC = No Connect; NU = Not Used; RFU = Reserved Future Use
1. S1, ODT1, CKE1: Used for dual-rank UDIMMs; NC on single-rank UDIMMs
2. CK1,NC and CK1,NC : Used for dual-rank UDIMMs; not used on single-rank UDIMMs, but terminated
3. TEST (pin 167) used by memory bus analysis tools (unused on memory DIMMs)
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
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Rev. 1.0
Unbuffered DIMM
datasheet
DDR3L SDRAM
5. Pin Description
Pin Name
Description
Pin Name
SCL
Description
I2C serial bus clock for EEPROM
A0-A14
SDRAM address bus
SDRAM bank select
I2C serial bus data line for EEPROM
BA0-BA2
SDA
I2C serial address select for EEPROM
SDRAM core power supply
RAS
SDRAM row address strobe
SDRAM column address strobe
SDRAM write enable
SA0-SA2
VDD
*
CAS
VDDQ
*
WE
SDRAM I/O Driver power supply
SDRAM I/O reference supply
VREFDQ
VREFCA
VSS
S0, S1
DIMM Rank Select Lines
SDRAM clock enable lines
On-die termination control lines
DIMM memory data bus
DIMM ECC check bits
CKE0,CKE1
ODT0, ODT1
DQ0 - DQ63
CB0 - CB7
SDRAM command/address reference supply
Power supply return (ground)
VDDSPD
NC
Serial EEPROM positive power supply
Spare Pins(no connect)
SDRAM data strobes
Used by memory bus analysis tools
(unused on memory DIMMs)
DQS0 - DQS8
DQS0-DQS8
DM0-DM8
TEST
RESET
EVENT
VTT
(positive line of differential pair)
SDRAM differential data strobes
(negative line of differential pair)
Set DRAMs Known State
SDRAM data masks/high data strobes
(x8-based x72 DIMMs)
Reserved for optional temperature-sensing hardware
SDRAM I/O termination supply
Reserved for future use
SDRAM clocks
CK0, CK1
(positive line of differential pair)
SDRAM clocks
CK0, CK1
RFU
(negative line of differential pair)
NOTE :
* The V and V
pins are tied common to a single power-plane on these designs.
DD
DDQ
** DM8, DQS8 and DQS8 are for ECC UDIMM only.
6. SPD and Thermal Sensor for ECC UDIMMs
On DIMM thermal sensor will provide DRAM temperature readout through a integrated thermal sensor.
SCL
SDA
EVENT
WP/EVENT
SA0
R1
SA1
SA1
SA2
SA2
0 Ω
R2
0 Ω
SA0
NOTE :
1. Raw Cards D (1Rx8 ECC) and E (2Rx8 ECC) support a thermal sensor.
2. When the SPD and the thermal sensor are placed on the module, R1 is placed but R2 is not.
When only the SPD is placed on the module, R2 is placed but R1 is not.
[ Table 1 ] Temperature Sensor Characteristics
Temperature Sensor Accuracy
Grade
Range
Units
NOTE
Min.
Typ.
+/- 0.5
+/- 1.0
+/- 2.0
0.25
Max.
+/- 1.0
+/- 2.0
+/- 3.0
75 < Ta < 95
40 < Ta < 125
-20 < Ta < 125
-
-
-
-
-
-
-
B
°C
Resolution
°C /LSB
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Rev. 1.0
Unbuffered DIMM
datasheet
DDR3L SDRAM
7. Input/Output Functional Description
Symbol
Type
Function
CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive
edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of
crossing)
CK0-CK1
SSTL
CK0-CK1
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low
initiates the Power Down mode, or the Self-Refresh mode
CKE0-CKE1
SSTL
SSTL
Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the
command decoder is disabled, new command are ignored but previous operations continue. This signal provides for
external rank selection on systems with multiple ranks.
S0-S1
RAS, CAS, WE
ODT0-ODT1
SSTL
SSTL
RAS, CAS, and WE (ALONG WITH S) define the command being entered.
When high, termination resistance is enabled for all DQ, DQS, DQS and DM pins, assuming the function is enabled in the
Extended Mode Register Set (EMRS).
VREFDQ
VREFCA
Supply Reference voltage for SSTL 15 I/O inputs.
Supply Reference voltage for SSTL 15 command/address inputs.
Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For all current DDR3 unbuffered
VDDQ
Supply
DIMM designs, VDDQ shares the same power plane as VDD pins.
BA0-BA2
SSTL
SSTL
Selects which SDRAM bank of eight is activated.
During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)
During a Read or Write command cycle, Address input defines the column address, In addition to the column address,
AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a pre-
charge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used
to define which bank to precharge. A12(BC) is sampled during READ and WRITE commands to determine if burst chop
(on-the-fly) will be performed (HIGH, no burst chop; Low, burst chopped).
A0-A14
DQ0-DQ63
CB0-CB7
SSTL
SSTL
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data
during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches
the DQ and DQS loading.
DM0-DM81
Power and ground for DDR3 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on
these modules.
V
DD,VSS
Supply
SSTL
DQS0-DQS81
DQS0-DQS81
Data strobe for input and output data.
These signals and tied at the system planar to either VSS or VDDSPD to configure the serial SPD EERPOM address
range.
SA0-SA2
SDA
-
-
-
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor may be connected
from the SDA bus line to VDDSPD to act as a pull-up on the system board.
This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL
bus time to VDDSPD to act as a pull-up on the system board.
SCL
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable
from 3.0V to 3.6V.
VDDSPD
Supply
-
RESET
EVENT
The RESET pin is connected to the RESET pin on each DRAM. When low, all DRAMs are set to a know state.
This signal indicates that a thermal event has been detected in the thermal sensing device. The system should guarantee
the electrical level requirement is met for the EVENT pin on TS/SPD part
Output
NOTE :
1. DM8, DQS8 and DQS8 are for ECC UDIMM only.
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Rev. 1.0
Unbuffered DIMM
datasheet
DDR3L SDRAM
7.1 Address Mirroring Feature
There is a via grid located under the DRAMs for wiring the CA signals (address, bank address, command, and control lines) to the DRAM pins. The length
of the traces from the vias to the DRAMs places limitations on the bandwidth of the module. The shorter these traces, the higher the bandwidth. To extend
the bandwidth of the CA bus for DDR3 modules, a scheme was defined to reduce the length of these traces.
The pins on the DRAM are defined in a manner that allows for these short trace lengths. The CA bus pins in Columns 2 and 8, ignoring the mechanical
support pins, do not have any special functions (secondary functions). This allows the most flexibility with these pins. These are address pins A3, A4, A5,
A6, A7, A8 and bank address pins BA0 and BA1. Refer to Table . Rank 0 DRAM pins are wired straight, with no mismatch between the connector pin
assignment and the DRAM pin assignment. Some of the Rank 1 DRAM pins are cross wired as defined in the table. Pins not listed in the table are wired
straight.
7.1.1 DRAM Pin Wiring Mirroring
DRAM Pin
Connector Pin
Rank 0
A3
Rank 1
A4
A3
A4
A4
A3
A5
A5
A6
A6
A6
A5
A7
A7
A8
A8
A8
A7
BA0
BA1
BA0
BA1
BA1
BA0
Figure 1illustrates the wiring in both the mirrored and non-mirrored case. The lengths of the traces to the DRAM pins, is obviously shorter. The via grid is smaller as well.
Figure 1. Wiring Differences for Mirrored and Non-Mirrored Addresses
Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is read the same way. There are limi-
tations however. When writing to the internal registers with a "load mode" operation, the specific address is required. See the DDR3 UDIMM SPD specifi-
cation for these details. The controller must read the SPD and have the capability of de-mirroring the address when accessing the second rank.
SAMSUNG DDR3 dual rank UDIMM R/C B(2Rx8) and R/C E(2Rx8) Modules are using Mirrored Addresses mode.
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Rev. 1.0
Unbuffered DIMM
datasheet
DDR3L SDRAM
8. Function Block Diagram:
8.1 2GB, 256Mx72 ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs)
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D4
ZQ
ZQ
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
ZQ
ZQ
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D6
ZQ
ZQ
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D7
ZQ
ZQ
DQS8
DQS8
DM8
Serial PD
DM
CS DQS DQS
SCL
EVENT
SDA
EVENT
A0 A1
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
A2
SA0 SA1 SA2
ZQ
V
NOTE :
BA0 - BA2
A0 - A15
RAS
BA0-BA2 : SDRAMs D0 - D8
A0-A15 : SDRAMs D0 - D8
RAS : SDRAMs D0 - D8
CAS : SDRAMs D0 - D8
CKE : SDRAMs D0 - D8
WE : SDRAMs D0 - D8
ODT : SDRAMs D0 - D8
CK : SDRAMs D0 - D8
DDSPD
SPD
1. For each DRAM, a unique ZQ resistor is connected to
ground. The ZQ resistor is 240 Ohm +/- 1%
2. Refer to "SPD and Thermal sensor for ECC UDIMMs"
for SPD detail.
V
/V
D0 - D8
D0 - D8
D0 - D8
D0 - D8
DD DDQ
V
REFDQ
CAS
V
SS
CKE0
WE
V
REFCA
ODT0
CK0
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DDR3L SDRAM
8.2 4GB, 512Mx72 ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
S1
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D9
D4
D13
ZQ
ZQ
ZQ
ZQ
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
D10
D5
D14
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
ZQ
ZQ
ZQ
ZQ
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
D2
D11
D6
D15
I/O 6
I/O 6
I/O 7
I/O 7
ZQ
ZQ
ZQ
ZQ
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D12
D7
D16
ZQ
ZQ
ZQ
ZQ
DQS8
DQS8
DM8
Serial PD
DM
CS DQS DQS
DM
CS DQS DQS
SCL
EVENT
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
D17
SDA
EVENT
A0 A1
A2
SA0 SA1 SA2
ZQ
ZQ
BA0 - BA2
BA0-BA2 : SDRAMs D0 - D17
A0-A15 : SDRAMs D0 - D17
CKE : SDRAMs D9 - D17
CKE : SDRAMs D0 - D8
RAS : SDRAMs D0 - D17
CAS : SDRAMs D0 - D17
WE : SDRAMs D0 - D17
ODT : SDRAMs D0 - D8
ODT : SDRAMs D9 - D17
CK : SDRAMs D0 - D8
NOTE :
1. For each DRAM, a unique ZQ resistor is connected to
ground. The ZQ resistor is 240 Ohm +/- 1%
2. Refer to "SPD and Thermal sensor for ECC UDIMMs"
for SPD detail.
A0 - A15
CKE1
CKE0
RAS
V
DDSPD
SPD
V
/V
D0 - D17
D0 - D17
D0 - D17
D0 - D17
DD DDQ
V
REFDQ
CAS
V
WE
SS
V
ODT0
ODT1
CK0
REFCA
CK1
CK : SDRAMs D9 - D17
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DDR3L SDRAM
9. Absolute Maximum Ratings
9.1 Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
NOTE
VDD
Voltage on VDD pin relative to VSS
-0.4 V ~ 1.975 V
-0.4 V ~ 1.975 V
-0.4 V ~ 1.975 V
-55 to +100
V
1,3
VDDQ
Voltage on VDDQ pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
V
V
1,3
1
V
IN, VOUT
TSTG
°C
1, 2
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. V and V
must be within 300mV of each other at all times;and V
must be not greater than 0.6 x V
, When V and V
are less than 500mV; V
may be
DD
DDQ
REF
DDQ
DD
DDQ
REF
equal to or less than 300mV.
9.2 DRAM Component Operating Temperature Range
Symbol
Parameter
rating
Unit
NOTE
TOPER
Operating Temperature Range
0 to 95
°C
1, 2, 3
NOTE :
1. Operating Temperature T
is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document
OPER
JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main-
tained between 0-85°C under all operating conditions
3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the
following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. It is also possible to specify a component with 1X refresh (tREFI
to 7.8us) in the Extended Temperature Range.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature
Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.
10. AC & DC Operating Conditions
10.1 Recommended DC Operating Conditions (SSTL-15)
Rating
Symbol
Parameter
Operation Voltage
Units
NOTE
Min.
1.283
1.425
1.283
1.425
Typ.
1.35
1.5
Max.
1.45
1.35V
1.5V
V
V
V
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
VDD
Supply Voltage
1.575
1.45
1.35V
1.5V
1.35
1.5
VDDQ
Supply Voltage for Output
1.575
NOTE:
1. Under all conditions V
must be less than or equal to V
.
DDQ
DD
2. V
tracks with V . AC parameters are measured with V and V
tied together.
DDQ
DDQ
DD
DD
3. V & V
rating are determinied by operation voltage.
DDQ
DD
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DDR3L SDRAM
11. AC & DC Input Measurement Levels
11.1 AC & DC Logic Input Levels for Single-ended Signals
[ Table 2 ] Single Ended AC and DC input levels for Command and Address
DDR3-800/1066/1333/1600
Symbol
Parameter
Unit NOTE
Min.
Max.
1.35V
1,5a)
1,6a)
1,2
VIH.CA(DC90)
VIL.CA(DC90)
VIH.CA(AC160)
VREF + 90
VSS
VDD
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic lowM
mV
mV
mV
mV
mV
mV
VREF - 90
VREF + 160
Note 2
V
IL.CA(AC160)
IH.CA(AC135)
IL.CA(AC135)
VREF - 160
Note 2
1,2
V
VREF+135
Note 2
1,2
V
VREF-135
Note 2
1,2
Reference Voltage for ADD,
CMD inputs
V
REFCA(DC)
0.49*VDD
0.51*VDD
V
3,4
1.5V
1,5b)
VIH.CA(DC100)
VIL.CA(DC100)
VIH.CA(AC175)
VREF + 100
VSS
VDD
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
mV
mV
mV
mV
mV
mV
1,6b)
1,2,7
1,2,8
1,2,7
1,2,8
VREF - 100
VREF + 175
Note 2
V
IL.CA(AC175)
IH.CA(AC150)
IL.CA(AC150)
VREF - 175
Note 2
V
VREF+150
Note 2
V
VREF-150
Note 2
Reference Voltage for ADD,
CMD inputs
V
REFCA(DC)
0.49*VDD
0.51*VDD
V
3,4
NOTE :
1. For input only pins except RESET, V
= V
(DC)
REF
REFCA
2. See "Overshoot and Undershoot specifications" section.
3. The AC peak noise on V may not allow V to deviate from V
(DC) by more than ± 1% V (for reference : approx. ± 15mV)
REF
REF
REF
DD
4. For reference : approx. V /2 ± 15mV
DD
a)
b)
5. V (dc) is used as a simplified symbol for V
(
1.35V : DC90, 1.5V : DC100)
IH
IH.CA
a)
b)
6. V (dc) is used as a simplified symbol for V
(
1.35V : DC90, 1.5V : DC100)
IL
IL.CA
7. V (ac) is used as a simplified symbol for V
IH
(AC175) and V
(AC150); V
(AC175) value is used when V
+ 175mV is referenced and V
(AC150) value is
IH.CA
IH.CA
IH.CA
IH.CA
REF
used when VREF + 150mV is referenced.
8. V (ac) is used as a simplified symbol for V
(AC175) and V
(AC150); V
(AC175) value is used when V
- 175mV is referenced and V
(AC150) value is used
IL
IL.CA
IL.CA
IL.CA
REF
IL.CA
when V
- 150mV is referenced.
REF
- 12 -
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DDR3L SDRAM
[ Table 3 ] Single Ended AC and DC input levels for DQ and DM
DDR3-800/1066
DDR3-1333/1600
Symbol
Parameter
Unit NOTE
Min.
Max.
1.35V
Min.
Max.
1,5a)
1,6a)
1,2
VIH.DQ(DC90)
VIL.DQ(DC90)
VIH.DQ(AC160)
VREF + 90
VSS
VDD
VREF + 90
VSS
VDD
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
mV
mV
mV
mV
mV
mV
VREF - 90
VREF - 90
VREF + 160
Note 2
-
-
-
V
IL.DQ(AC160)
IH.DQ(AC135)
IL.DQ(AC135)
VREF - 160
Note 2
-
1,2
V
VREF + 135
VREF + 135
Note 2
Note 2
VREF - 135
1,2
V
VREF - 135
Note 2
Note 2
1,2
Reference Voltage for DQ,
DM inputs
VREFDQ(DC)
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
V
3,4
1.5V
1,5b)
VIH.DQ(DC100)
VIL.DQ(DC100)
VIH.DQ(AC175)
VREF + 100
VSS
VDD
VREF + 100
VSS
VDD
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
mV
mV
mV
mV
mV
mV
1,6b)
1,2,7
1,2,8
1,2,7
1,2,8
VREF - 100
VREF - 100
VREF + 175
NOTE 2
-
-
V
IL.DQ(AC175)
IH.DQ(AC150)
IL.DQ(AC150)
VREF - 175
NOTE 2
-
-
V
VREF + 150
VREF + 150
NOTE 2
NOTE 2
VREF - 150
V
VREF - 150
NOTE 2
NOTE 2
Reference Voltage for DQ,
DM inputs
VREFDQ(DC)
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
V
3,4
NOTE :
1. For input only pins except RESET, V
= V
(DC)
REF
REFDQ
2. See ’Overshoot/Undershoot Specification’ on page 18.
3. The AC peak noise on V may not allow V to deviate from V
(DC) by more than ± 1% V (for reference : approx. ± 15mV)
REF
REF
REF
b)
DD
4. For reference : approx. V /2 ± 15mV
DD
a)
5. V (dc) is used as a simplified symbol for V
(
1.35V : DC90, 1.5V : DC100)
IH
IH.CA
a)
b)
6. V (dc) is used as a simplified symbol for V
(
1.35V : DC90, 1.5V : DC100)
IL
IL.CA
7. V (ac) is used as a simplified symbol for V
(AC175), V
(AC150) ; V
(AC175) value is used when V
+ 175mV is referenced, V
(AC150) value is used
IH.DQ
IH
IH.DQ
IH.DQ
IH.DQ
REF
when V
+ 150mV is referenced.
REF
8. V (ac) is used as a simplified symbol for V
(AC175), V
(AC150) ; V
(AC175) value is used when V
- 175mV is referenced, V
(AC150) value is used when
IL
IL.DQ
IL.DQ
IL.DQ
REF
IL.DQ
V
- 150mV is referenced.
REF
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DDR3L SDRAM
11.2 V Tolerances
REF
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 2. It shows a valid reference voltage
REF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).
REF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of VREF. Fur-
thermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD
V
V
.
voltage
V
DD
V
SS
time
Figure 2. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF
.
This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise.
Timing and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
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DDR3L SDRAM
11.3 AC and DC Logic Input Levels for Differential Signals
11.3.1 Differential Signals Definition
tDVAC
VIH.DIFF.AC.MIN
VIH.DIFF.MIN
0.0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
Figure 3. Definition of differential ac-swing and "time above ac level" tDVAC
11.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)
DDR3-800/1066/1333/1600
Symbol
Parameter
1.35V
1.5V
unit
NOTE
min
+0.18
max
NOTE 3
min
+0.20
max
NOTE 3
VIHdiff
VILdiff
IHdiff(AC)
ILdiff(AC)
differential input high
differential input low
V
V
V
V
1
1
2
2
NOTE 3
-0.18
NOTE 3
-0.20
V
2 x (VIH(AC) - VREF
NOTE 3
)
2 x (VIH(AC) - VREF
NOTE 3
)
differential input high ac
differential input low ac
NOTE 3
NOTE 3
V
2 x (VIL(AC) - VREF
)
2 x (VIL(AC) - VREF)
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK - CK use V /V (AC) of ADD/CMD and V
; for DQS - DQS use V /V (AC) of DQs and V
; if a reduced ac-high or ac-low level is used for a signal group,
IH IL
REFCA
IH IL
REFDQ
then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS need to be within the respective limits (V (DC) max, V (DC)min) for single-ended sig-
IH
IL
nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"
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[ Table 4 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.35V)
tDVAC [ps] @ |VIH/Ldiff(AC)| = 320mV
Slew Rate [V/ns]
tDVAC [ps] @ |VIH/Ldiff(AC)| = 270mV
min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
max
min
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
max
> 4.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.0
2.0
1.8
1.6
1.4
1.2
1.0
< 1.0
[ Table 5 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.5V)
tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV
Slew Rate [V/ns]
tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV
min
75
57
50
38
34
29
22
13
0
max
min
175
170
167
163
162
161
159
155
150
150
max
> 4.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.0
2.0
1.8
1.6
1.4
1.2
1.0
< 1.0
0
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11.3.3 Single-ended Requirements for Differential Signals
Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every
half-cycle.
DQS, DQS have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle proceeding and follow-
ing a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD
signals, then these ac-levels apply also for the single-ended signals CK and CK .
V
or V
DDQ
DD
V
min
SEH
V
SEH
V
/2 or V
/2
DDQ
DD
CK or DQS
V
max
SEL
V
SEL
V
or V
SSQ
SS
time
Figure 4. Single-ended requirement for differential signals
Note that while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement
with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common
mode characteristics of these signals.
[ Table 6 ] Single ended levels for CK, DQS, CK, DQS
DDR3-800/1066/1333/1600
Symbol
Parameter
Unit
NOTE
Min
Max
(VDD/2)+0.175
Single-ended high-level for strobes
Single-ended high-level for CK, CK
Single-ended low-level for strobes
Single-ended low-level for CK, CK
NOTE 3
V
V
V
V
1, 2
1, 2
1, 2
1, 2
VSEH
(VDD/2)+0.175
NOTE 3
NOTE 3
(VDD/2)-0.175
(VDD/2)-0.175
VSEL
NOTE 3
NOTE :
1. For CK, CK use V /V (AC) of ADD/CMD; for strobes (DQS, DQS) use V /V (AC) of DQs.
IH IL
IH IL
2. V (AC)/V (AC) for DQs is based on V
; V (AC)/V (AC) for ADD/CMD is based on V
; if a reduced ac-high or ac-low level is used for a signal group, then the
REFCA
IH
IL
REFDQ
IH
IL
reduced level applies also here
3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS need to be within the respective limits (V (DC) max, V (DC)min) for single-ended sig-
IH
IL
nals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"
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DDR3L SDRAM
11.3.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input
signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signal to the mid level between of VDD and VSS
.
VDD
CK, DQS
VIX
VDD/2
VIX
VIX
CK, DQS
VSS
VSEH
VSEL
Figure 5. VIX Definition
[ Table 7 ] Cross point voltage for differential input signals (CK, DQS) : 1.35V
DDR3L-800/1066/1333/1600
Symbol
Parameter
Unit
NOTE
Min
-150
-150
Max
150
150
VIX
VIX
Differential Input Cross Point Voltage relative to VDD/2 for CK,CK
Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS
mV
mV
1
NOTE :
1. The relationbetween Vix Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + Vix(Min) - VSEL ≥ 25mV
VSEH - ((VDD/2) + Vix(Max)) ≥ 25mV
[ Table 8 ] Cross point voltage for differential input signals (CK, DQS) : 1.5V
DDR3-800/1066/1333/1600
Symbol
Parameter
Unit
NOTE
Min
-150
-175
-150
Max
150
175
150
mV
mV
mV
VIX
VIX
Differential Input Cross Point Voltage relative to VDD/2 for CK,CK
Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS
1
NOTE :
1. Extended range for V is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing V
IX
/ V
of at least V /2
SEL
SEH DD
±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns.
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11.4 Slew Rate Definition for Single Ended Input Signals
See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals.
See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.
11.5 Slew rate definition for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.
[ Table 9 ] Differential input slew rate definition
Measured
Description
Defined by
From
To
VIHdiffmin - VILdiffmax
Delta TRdiff
VILdiffmax
VIHdiffmin
Differential input slew rate for rising edge (CK-CK and DQS-DQS)
Differential input slew rate for falling edge (CK-CK and DQS-DQS)
VIHdiffmin - VILdiffmax
Delta TFdiff
VIHdiffmin
VILdiffmax
NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds
V
IHdiffmin
ILdiffmax
0
V
delta TFdiff
delta TRdiff
Figure 6. Differential input slew rate definition for DQS, DQS and CK, CK
12. AC & DC Output Measurement Levels
12.1 Single Ended AC and DC Output Levels
[ Table 10 ] Single Ended AC and DC output levels
Symbol Parameter
DDR3-800/1066/1333/1600
Units
NOTE
VOH(DC) DC output high measurement level (for IV curve linearity)
0.8 x VDDQ
0.5 x VDDQ
V
V
OM(DC) DC output mid measurement level (for IV curve linearity)
OL(DC) DC output low measurement level (for IV curve linearity)
OH(AC) AC output high measurement level (for output SR)
V
V
V
V
V
0.2 x VDDQ
V
VTT + 0.1 x VDDQ
VTT - 0.1 x VDDQ
1
1
V
OL(AC) AC output low measurement level (for output SR)
NOTE : 1. The swing of +/-0.1 x V
is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
DDQ
load of 25Ω to V =V
/2.
DDQ
TT
12.2 Differential AC and DC Output Levels
[ Table 11 ] Differential AC and DC output levels
Symbol
Parameter
DDR3-800/1066/1333/1600
Units
NOTE
VOHdiff(AC)
AC differential output high measurement level (for output SR)
+0.2 x VDDQ
V
1
VOLdiff(AC)
AC differential output low measurement level (for output SR)
-0.2 x VDDQ
V
1
NOTE : 1. The swing of +/-0.2xV
is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
DDQ
load of 25Ω to V =V
/2 at each of the differential outputs.
DDQ
TT
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12.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
for single ended signals as shown in below.
[ Table 12 ] Single ended Output slew rate definition
Measured
Description
Defined by
From
To
VOH(AC)-VOL(AC)
Delta TRse
VOL(AC)
VOH(AC)
Single ended output slew rate for rising edge
Single ended output slew rate for falling edge
VOH(AC)-VOL(AC)
Delta TFse
V
OH(AC)
VOL(AC)
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 13 ] Single ended output slew rate
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Operation
Voltage
Parameter
Symbol
Units
Min
Max
Min
Max
Min
Max
Min
Max
51)
5
51)
5
51)
5
51)
5
1.35V
1.5V
1.75
2.5
1.75
2.5
1.75
2.5
1.75
2.5
V/ns
V/ns
Single ended output slew rate SRQse
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals
For Ron = RZQ/7 setting
NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ
signals in the same byte lane are static (i.e they stay at either high or low).
- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the
remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
V
(AC)
(AC)
OHdiff
V
V
TT
OLdiff
delta TFdiff
delta TRdiff
Figure 7. Single-ended output slew rate definition
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12.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOH-
diff(AC) for differential signals as shown in below.
[ Table 14 ] Differential Output slew rate definition
Measured
Description
Defined by
From
To
VOHdiff(AC)-VOLdiff(AC)
Delta TRdiff
V
OLdiff(AC)
VOHdiff(AC)
Differential output slew rate for rising edge
Differential output slew rate for falling edge
VOHdiff(AC)-VOLdiff(AC)
Delta TFdiff
V
OHdiff(AC)
VOLdiff(AC)
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 15 ] Differential Output slew rate
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Operation
Voltage
Parameter
Symbol
Units
Min
Max
12
Min
Max
12
Min
Max
12
Min
Max
12
1.35V
1.5V
3.5
5
3.5
5
3.5
5
3.5
5
V/ns
V/ns
Single ended output slew rate SRQdiff
Description : SR : Slew Rate
10
10
10
10
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
diff : Differential Signals
For Ron = RZQ/7 setting
V
(AC)
(AC)
OHdiff
V
V
TT
OLdiff
delta TFdiff
delta TRdiff
Figure 8. Differential output slew rate definition
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13. IDD specification definition
Symbol
Description
Operating One Bank Active-Precharge Current
1)
CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between ACT and PRE;
IDD0
Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
2)
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
tern
Operating One Bank Active-Read-Precharge Current
1)
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between ACT, RD
IDD1
and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
2)
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
tern
Precharge Standby Current
1)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
IDD2N
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode
2)
Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Precharge Power-Down Current Slow Exit
1)
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
IDD2P0
2)
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
;
;
3)
ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit
Precharge Power-Down Current Fast Exit
1)
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
IDD2P1
IDD2Q
IDD3N
IDD3P
2)
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
3)
ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit
Precharge Quiet Standby Current
1)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
2)
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0
;
Active Standby Current
1)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode
2)
Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Active Power-Down Current
1)
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
2)
Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers ; ODT
Signal: stable at 0
Operating Burst Read Current
1)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between RD; Command, Address,
IDD4R
IDD4W
Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank
2)
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable
at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Operating Burst Write Current
1)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank
2)
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable
at HIGH; Pattern Details: Refer to Component Datasheet for detail pattern
Burst Refresh Current
1)
CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between REF; Command,
IDD5B
IDD6
Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC ; Output Buffer and
2)
RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Self Refresh Current: Normal Temperature Range
4)
5)
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled ; Self-Refresh Temperature Range (SRT): Normal ; CKE: Low; External clock: Off; CK and CK:
1)
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
2)
Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: FLOATING
6)
Self-Refresh Current: Extended Temperature Range (optional)
4)
5)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled ; Self-Refresh Temperature Range (SRT): Extended ; CKE: Low; External clock: Off; CK and CK:
IDD6ET
1)
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
2)
Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: FLOATING
Operating Bank Interleave Read Current
1)
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: CL-1; CS: High
IDD7
IDD8
between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and
the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT:
2)
Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
RESET Low Current
RESET : Low; External clock : off; CK and CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :
FLOATING
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NOTE :
1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
6) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
7) IDD current measure method and detail patterns are described on DDR3 component datasheet
8) VDD and VDDQ are merged on module PCB.
9) DIMM IDD SPEC is measured with Qoff condition
(IDDQ values are not considered)
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14. IDD SPEC Table
M391B5773DH0 : 2GB(256Mx72) Module
DDR3-1066
DDR3-1333
9-9-9
DDR3-1600
11-11-11
Symbol
7-7-7
Unit
NOTE
1.35V
270
360
90
1.5V
315
405
108
135
153
153
153
270
585
630
990
108
945
108
1.35V
315
405
90
1.5V
360
450
108
135
180
180
153
315
675
720
1035
108
1215
108
1.35V
1.5V
405
495
108
135
180
180
180
315
810
855
1080
108
1260
108
IDD0
IDD1
360
450
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1
1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
117
135
135
135
225
495
540
990
90
117
135
135
135
225
630
675
1035
90
135
153
153
153
270
720
810
1035
90
IDD2Q
IDD3P
IDD3N
IDD4R
1
1
1
IDD4W
IDD5B
IDD6
IDD7
900
90
1125
90
1170
90
1
IDD8
NOTE :
1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.
M391B5273DH0 : 4GB(512Mx72) Module
DDR3-1066
DDR3-1333
DDR3-1600
11-11-11
Symbol
7-7-7
9-9-9
Unit
NOTE
1.35V
405
495
180
234
270
270
270
360
630
675
1125
243
1035
243
1.5V
468
558
216
270
306
306
306
423
738
783
1143
216
1098
216
1.35V
450
540
180
234
270
270
270
360
765
810
1170
270
1260
270
1.5V
540
630
216
270
360
360
306
495
855
900
1215
216
1395
216
1.35V
513
603
180
270
306
306
306
423
873
963
1188
288
1323
288
1.5V
585
675
216
270
360
360
360
495
990
1035
1260
216
1440
216
IDD0
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1
1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
IDD2Q
IDD3P
IDD3N
IDD4R
1
1
1
IDD4W
IDD5B
IDD6
IDD7
1
IDD8
NOTE :
1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.
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15. Input/Output Capacitance
[ Table 16 ] Input/Output Capacitance
DDR3-800
Min Max
1.35V
DDR3-1066
DDR3-1333
DDR3-1600
Parameter
Symbol
Units NOTE
Min
Max
Min
Max
Min
Max
Input/output capacitance
CIO
CCK
1.5
0.8
0
2.5
1.6
0.15
1.3
0.2
0.3
0.5
1.5
0.8
0
2.5
1.6
0.15
1.3
0.2
0.3
0.5
1.5
2.3
1.2
2.3
TBD
TBD
1.3
pF
pF
pF
pF
pF
pF
pF
1,2,3
2,3
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance
(CK and CK)
TBD
TBD
0.75
TBD
TBD
TBD
TBD
TBD
1.3
TBD
TBD
0.75
TBD
TBD
TBD
Input capacitance delta
(CK and CK)
CDCK
2,3,4
Input capacitance
CI
0.75
0
0.75
0
2,3,6
(All other input-only pins)
Input/Output capacitance delta
(DQS and DQS)
CDDQS
CDI_CTRL
CDI_ADD_CMD
TBD
TBD
TBD
TBD
TBD
TBD
2,3,5
Input capacitance delta
-0.5
-0.5
-0.5
-0.5
2,3,7,8
2,3,9,10
(All control input-only pins)
Input capacitance delta
(all ADD and CMD input-only pins)
Input/output capacitance delta
CDIO
CZQ
-0.5
-
0.3
3
-0.5
-
0.3
3
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
pF
pF
2,3,11
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input/output capacitance of ZQ pin
2, 3, 12
1.5V
Input/output capacitance
CIO
CCK
1.5
0.8
0
3.0
1.6
0.15
1.5
0.2
0.3
0.5
1.5
0.8
0
2.7
1.6
0.15
1.5
0.2
0.3
0.5
1.5
0.8
0
2.5
1.4
1.4
0.8
0
2.3
1.4
pF
pF
pF
pF
pF
pF
pF
1,2,3
2,3
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance
(CK and CK)
Input capacitance delta
(CK and CK)
CDCK
0.15
1.3
0.15
1.3
2,3,4
Input capacitance
CI
0.75
0
0.75
0
0.75
0
0.75
0
2,3,6
(All other input-only pins)
Input capacitance delta
(DQS and DQS)
CDDQS
CDI_CTRL
CDI_ADD_CMD
0.15
0.2
0.15
0.2
2,3,5
Input capacitance delta
-0.5
-0.5
-0.5
-0.5
-0.4
-0.4
-0.4
-0.4
2,3,7,8
2,3,9,10
(All control input-only pins)
Input capacitance delta
0.4
0.4
(all ADD and CMD input-only pins)
Input/output capacitance delta
CDIO
CZQ
-0.5
-
0.3
3
-0.5
-
0.3
3
-0.5
-
0.3
3
-0.5
-
0.3
3
pF
pF
2,3,11
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input/output capacitance of ZQ pin
2, 3, 12
NOTE : This parameter is Component Input/Output Capacitance so that is different from Module level Capacitance.
1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS
2. This parameter is not subject to production test. It is verified by design and characterization.
The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with
, V , V , V applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). V =V =1.5V, V =V /2 and on-die
V
DD
DDQ
SS
SSQ
DD
DDQ
BIAS
DD
termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK
5. Absolute value of CIO(DQS)-CIO(DQS)
6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.
7. CDI_CTRL applies to ODT, CS and CKE
8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))
9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))
11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))
12. Maximum external load capacitance on ZQ pin: 5pF
- 25 -
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16. Electrical Characteristics and AC timing
[0 °C<T
≤95 °C, V
= 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V); V = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)]
DDQ DD
CASE
16.1 Refresh Parameters by Device Density
Parameter
Symbol
1Gb
110
7.8
2Gb
160
7.8
4Gb
300
7.8
8Gb
350
7.8
Units
ns
NOTE
All Bank Refresh to active/refresh cmd time
tRFC
0 °C ≤ TCASE ≤ 85°C
µs
Average periodic refresh interval
tREFI
85 °C < TCASE ≤ 95°C
3.9
3.9
3.9
3.9
µs
1
NOTE :
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in
this material.
16.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
DDR3-800
6-6-6
min
6
DDR3-1066
7-7-7
min
DDR3-1333
9-9-9
min
9
DDR3-1600
11-11-11
min
Bin (CL - tRCD - tRP)
Units
NOTE
Parameter
CL
7
11
tCK
ns
ns
ns
ns
ns
ns
tRCD
tRP
15
13.13
13.13
37.5
13.5
13.5
36
13.75
13.75
35
15
tRAS
tRC
37.5
52.5
10
50.63
7.5
49.5
6.0
48.75
6.0
tRRD
tFAW
40
37.5
30
30
16.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
[ Table 17 ] DDR3-800 Speed Bins
Speed
DDR3-800
6 - 6 - 6
CL-nRCD-nRP
Units
NOTE
Parameter
Symbol
tAA
min
15
max
Internal read command to first data
ACT to internal read or write delay time
PRE command period
20
ns
ns
tRCD
tRP
15
-
15
-
-
ns
ACT to ACT or REF command period
ACT to PRE command period
CL = 6 / CWL = 5
tRC
52.5
37.5
2.5
ns
tRAS
9*tREFI
3.3
ns
tCK(AVG)
ns
1,2,3
Supported CL Settings
6
5
nCK
nCK
Supported CWL Settings
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[ Table 18 ] DDR3-1066 Speed Bins
Speed
DDR3-1066
CL-nRCD-nRP
7 - 7 - 7
Units
NOTE
Parameter
Internal read command to first data
ACT to internal read or write delay time
PRE command period
Symbol
tAA
min
13.125
13.125
13.125
50.625
37.5
max
20
ns
ns
tRCD
-
tRP
-
-
ns
ACT to ACT or REF command period
ACT to PRE command period
tRC
ns
tRAS
9*tREFI
3.3
ns
CWL = 5
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
2.5
ns
1,2,3,5
1,2,3,4
4
CL = 6
CL = 7
CL = 8
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
Reserved
Reserved
ns
ns
1.875
1.875
<2.5
<2.5
ns
1,2,3,4,8
4
Reserved
ns
ns
1,2,3
Supported CL Settings
Supported CWL Settings
6,7,8
5,6
nCK
nCK
[ Table 19 ] DDR3-1333 Speed Bins
Speed
DDR3-1333
9 -9 - 9
CL-nRCD-nRP
Units
NOTE
Parameter
Symbol
tAA
min
max
Internal read command to first data
13.5 (13.125)8
13.5 (13.125)8
13.5 (13.125)8
49.5 (49.125)8
36
20
ns
ns
ACT to internal read or write delay time
PRE command period
tRCD
-
tRP
-
-
ns
ACT to ACT or REF command period
ACT to PRE command period
tRC
ns
tRAS
9*tREFI
3.3
ns
CWL = 5
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
2.5
ns
1,2,3,6
1,2,3,4,6
4
CL = 6
CL = 7
CL = 8
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5,6
CWL = 7
CWL = 5,6
CWL = 7
Reserved
Reserved
Reserved
ns
ns
ns
4
1.875
1.875
1.5
<2.5
<2.5
ns
1,2,3,4,6
1,2,3,4
4
Reserved
Reserved
ns
ns
ns
1,2,3,6
1,2,3,4
4
Reserved
Reserved
ns
ns
CL = 9
<1.875
ns
1,2,3,4,8
4
Reserved
Reserved
6,7,8,9
ns
CL = 10
ns
1,2,3
Supported CL Settings
Supported CWL Settings
nCK
nCK
5,6,7
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[ Table 20 ] DDR3-1600 Speed Bins
Speed
DDR3-1600
CL-nRCD-nRP
11-11-11
Units
NOTE
Parameter
Symbol
min
max
13.75
Intermal read command to first data
tAA
20
ns
ns
ns
ns
(13.125)8
13.75
ACT to internal read or write delay time
PRE command period
tRCD
tRP
-
-
-
(13.125)8
13.75
(13.125)8
48.75
ACT to ACT or REF command period
ACT to PRE command period
tRC
(48.125)8
tRAS
35
9*tREFI
3.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
nCK
nCK
CWL = 5
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
2.5
1,2,3,7
1,2,3,4,7
4
CL = 6
CWL = 6
CWL = 7, 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5,6
CWL = 7
CWL = 8
CWL = 5,6
CWL = 7
CWL = 8
CWL = 5,6,7
CWL = 8
Reserved
Reserved
Reserved
4
1.875
1.875
<2.5
<2.5
1,2,3,4,7
1,2,3,4,7
4
CL = 7
Reserved
Reserved
Reserved
4
1,2,3,7
1,2,3,4,7
1,2,3,4
4
CL = 8
CL = 9
Reserved
Reserved
Reserved
1.5
1.5
<1.875
<1.875
<1.5
1,2,3,4,7
1,2,3,4
4
Reserved
Reserved
CL = 10
CL = 11
1,2,3,7
1,2,3,4
4
Reserved
Reserved
1.25
1,2,3,8
Supported CL Settings
Supported CWL Settings
6,7,8,9,10,11
5,6,7,8
16.3.1 Speed Bin Table Notes
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Absolute Specification [TOPER; VDDQ = VDD = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)];
NOTE :
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements
from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guar-
anteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns],
rounding up to the next "SupportedCL".
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or
1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.
4. "Reserved" settings are not allowed. User must program a different value.
5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/
Characterization.
8. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example,
DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte
20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte
18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin
+ tRPmin=36ns+13.125ns) for DDR3-1333(CL9) and 48.125ns (tRASmin+tRPmin=35ns+13.125ns) for DDR3-1600(CL11).
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17. Timing Parameters by Speed Grade
[ Table 21 ] Timing Parameters by Speed Bin
Speed
Parameter
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
NOTE
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Clock Timing
tCK(DLL_OF
F)
Minimum Clock Cycle Time (DLL off mode)
8
-
8
-
8
-
8
-
ns
6
Average Clock Period
Clock Period
tCK(avg)
tCK(abs)
See Speed Bins Table
ps
ps
tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max +
tJIT(per)min
tJIT(per)max
tJIT(per)min
tJIT(per)max
tJIT(per)min
tJIT(per)max
tJIT(per)min
tJIT(per)max
Average high pulse width
tCH(avg)
tCL(avg)
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Average low pulse width
0.47
0.53
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
ps
Clock Period Jitter
tJIT(per)
-100
100
-90
90
-80
80
-70
70
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
tJIT(per, lck)
tJIT(cc)
-90
90
-80
80
-70
70
-60
60
ps
200
180
180
160
160
140
140
120
ps
Cycle to Cycle Period Jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
tJIT(cc, lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per)
tERR(11per)
tERR(12per)
ps
- 147
- 175
- 194
- 209
- 222
- 232
- 241
- 249
- 257
- 263
- 269
147
175
194
209
222
232
241
249
257
263
269
- 132
- 157
- 175
- 188
- 200
- 209
- 217
- 224
- 231
- 237
- 242
132
157
175
188
200
209
217
224
231
237
242
- 118
- 140
- 155
- 168
- 177
- 186
- 193
- 200
- 205
- 210
- 215
118
140
155
168
177
186
193
200
205
210
215
-103
-122
-136
-147
-155
-163
-169
-175
-180
-184
-188
103
122
136
147
155
163
169
175
180
184
188
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
Cumulative error across n = 13, 14 ... 49, 50 cycles
tERR(nper)
ps
24
Absolute clock HIGH pulse width
Absolute clock Low pulse width
Data Timing
tCH(abs)
tCL(abs)
0.43
0.43
-
-
0.43
0.43
-
-
0.43
0.43
-
-
0.43
0.43
-
-
tCK(avg)
tCK(avg)
25
26
DQS,DQS to DQ skew, per group, per access
DQ output hold time from DQS, DQS
DQ low-impedance time from CK, CK
DQ high-impedance time from CK, CK
tDQSQ
tQH
-
200
-
-
150
-
-
125
-
-
100
-
ps
tCK(avg)
ps
13
0.38
-800
-
0.38
-600
-
0.38
-500
-
0.38
-450
-
13, g
tLZ(DQ)
tHZ(DQ)
400
400
300
300
250
250
225
225
13,14, f
13,14, f
ps
1.35V
tDS(base)
AC160
90
75
40
25
-
-
-
-
-
-
-
-
-
-
-
-
-
ps
ps
ps
ps
ps
d, 17
d, 17
d, 17
d, 17
-
-
-
-
-
-
-
-
-
-
Data setup time to DQS, DQS referenced to
V
(AC)V (AC) levels
IH
IL
1.5V
tDS(base)
AC175
-
1.35V
tDH(base)
DC90
160
150
140
110
100
90
75
1.5V
65
1.35V
45
1.5V
55
45
25
Data hold time from DQS, DQS referenced to
(AC)V (AC) levels
V
IH
IL
tDH(base)
DC100
tDS(base)
AC135
Data setup time to DQS, DQS referenced to
(AC)V (AC) levels
V
IH
IL
tDS(base)
AC150
125
600
75
30
-
10
-
ps
ps
-
-
-
-
DQ and DM Input pulse width for each input
tDIPW
490
400
-
360
-
28
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[ Table 21 ] Timing Parameters by Speed Bin (Cont.)
Speed
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
NOTE
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Data Strobe Timing
DQS, DQS differential READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS differential output high time
DQS, DQS differential output low time
DQS, DQS differential WRITE Preamble
DQS, DQS differential WRITE Postamble
tRPRE
tRPST
tQSH
0.9
0.3
Note 19
0.9
0.3
Note 19
0.9
0.3
0.4
0.4
0.9
0.3
Note 19
0.9
0.3
0.4
0.4
0.9
0.3
Note 19
tCK
tCK
13, 19, g
11, 13, b
13, g
Note 11
Note 11
Note 11
Note 11
0.38
0.38
0.9
-
-
-
-
0.38
0.38
0.9
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK
tQSL
13, g
tWPRE
tWPST
0.3
0.3
tCK
DQS, DQS rising edge output access time from rising
CK, CK
tDQSCK
tLZ(DQS)
tHZ(DQS)
-400
-800
-
400
400
400
-300
-600
-
300
300
300
-255
-500
-
255
250
250
-225
-450
-
225
225
225
ps
ps
ps
13,f
DQS, DQS low-impedance time (Referenced from RL-
1)
13,14,f
12,13,14
DQS, DQS high-impedance time (Referenced from
RL+BL/2)
DQS, DQS differential input low pulse width
DQS, DQS differential input high pulse width
DQS, DQS rising edge to CK, CK rising edge
DQS,DQS falling edge setup time to CK, CK rising edge
DQS,DQS falling edge hold time to CK, CK rising edge
Command and Address Timing
tDQSL
tDQSH
tDQSS
tDSS
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.27
0.18
0.18
0.55
0.55
0.27
-
tCK
29, 31
30, 31
c
tCK
tCK(avg)
tCK(avg)
tCK(avg)
c, 32
c, 32
tDSH
0.2
-
0.2
-
0.2
-
-
DLL locking time
tDLLK
tRTP
512
-
-
512
-
-
512
-
-
512
-
-
nCK
internal READ Command to PRECHARGE Command
delay
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
e
Delay from start of internal write transaction to internal
read command
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
tWTR
-
-
-
-
e,18
e
WRITE recovery time
tWR
15
4
-
-
15
4
-
-
15
4
-
-
15
4
-
-
ns
Mode Register Set command cycle time
tMRD
nCK
max
(12nCK,15ns)
max
(12nCK,15ns)
max
(12nCK,15ns)
max
(12nCK,15ns)
Mode Register Set command update delay
tMOD
-
-
-
-
-
-
-
-
CAS# to CAS# command delay
tCCD
tDAL(min)
tMPRR
tRAS
4
1
4
4
4
nCK
nCK
nCK
ns
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
WR + roundup (tRP / tCK(AVG))
-
1
-
1
-
1
-
22
e
See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin”
max
(4nCK,10ns)
max
(4nCK,7.5ns)
max
(4nCK,6ns)
max
(4nCK,6ns)
ACTIVE to ACTIVE command period for 1KB page size
ACTIVE to ACTIVE command period for 2KB page size
tRRD
tRRD
-
-
-
-
-
-
-
-
e
e
max
(4nCK,10ns)
max
(4nCK,10ns)
max
(4nCK,7.5ns)
max
(4nCK,7.5ns)
Four activate window for 1KB page size
Four activate window for 2KB page size
tFAW
tFAW
40
50
-
-
37.5
50
-
-
30
45
-
-
30
40
-
-
ns
ns
e
e
1.35V
tIS(base)
AC160
215
200
285
275
365
140
125
210
200
290
80
1.5V
65
-
-
-
60
45
-
-
-
-
-
ps
ps
ps
ps
ps
b,16
b,16
-
-
-
-
-
-
Command and Address setup time to CK, CK refer-
enced to V (AC) / V (AC) levels
IH
IL
tIS(base)
AC175
1.35V
150
tIH(base)
DC90
130
120
185
b,16
Command and Address hold time from CK, CK refer-
enced to V (AC) / V (AC) levels
IH
IL
1.5V
140
tIH(base)
DC100
b,16
1.35V
205
tIS(base)
AC135
-
b,16,27
-
-
Command and Address setup time to CK, CK refer-
enced to V (AC) / V (AC) levels
IH
IL
1.5V
190
tIS(base)
AC150
350
900
275
780
-
-
170
560
-
-
ps
ps
b,16,27
28
-
-
-
-
Control & Address Input pulse width for each input
Calibration Timing
tIPW
620
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation short calibration time
tZQinitI
tZQoper
tZQCS
512
256
64
-
-
-
512
256
64
-
-
-
512
256
64
-
-
-
512
256
64
-
-
-
nCK
nCK
nCK
23
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Rev. 1.0
Unbuffered DIMM
datasheet
DDR3L SDRAM
[ Table 21 ] Timing Parameters by Speed Bin (Cont.)
Speed
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
NOTE
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Reset Timing
max(5nCK,
tRFC +
max(5nCK,
tRFC +
max(5nCK,
tRFC +
max(5nCK,
tRFC +
Exit Reset from CKE HIGH to a valid command
tXPR
-
-
-
-
10ns)
10ns)
10ns)
10ns)
Self Refresh Timing
max(5nCK,t
RFC +
10ns)
max(5nCK,t
RFC +
10ns)
max(5nCK,t
RFC +
10ns)
Exit Self Refresh to commands not requiring a locked
DLL
max(5nCK,t
RFC + 10ns)
tXS
-
-
-
-
Exit Self Refresh to commands requiring a locked DLL
tXSDLL
tCKESR
tDLLK(min)
-
-
tDLLK(min)
-
-
tDLLK(min)
-
-
tDLLK(min)
-
-
nCK
Minimum CKE low width for Self refresh entry to exit
timing
tCKE(min)+
1tCK
tCKE(min)+
1tCK
tCKE(min)+
1tCK
tCKE(min) +
1tCK
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down Entry (PDE)
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
tCKSRE
tCKSRX
-
-
-
-
-
-
-
-
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
Power Down Timing
Exit Power Down with DLL on to any valid com-
mand;Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
max
(3nCK,
7.5ns)
max
(3nCK,
7.5ns)
max
(3nCK,6ns)
max
(3nCK,6ns)
tXP
tXPDLL
tCKE
-
-
-
-
-
-
-
-
-
-
-
-
max
(10nCK,
24ns)
max
(10nCK,
24ns)
max
(10nCK,
24ns)
max
(10nCK,
24ns)
Exit Precharge Power Down with DLL frozen to com-
mands requiring a locked DLL
2
max
(3nCK,
7.5ns)
max
(3nCK,
5.625ns)
max
(3nCK,
5.625ns)
max
(3nCK,5ns)
CKE minimum pulse width
Command pass disable delay
tCPDED
tPD
1
-
1
-
1
-
1
-
nCK
tCK
Power Down Entry to Exit Timing
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
15
20
20
Timing of ACT command to Power Down entry
Timing of PRE command to Power Down entry
Timing of RD/RDA command to Power Down entry
tACTPDEN
tPRPDEN
tRDPDEN
1
1
-
-
-
1
1
-
-
-
1
1
-
-
-
1
1
-
-
-
nCK
nCK
RL + 4 +1
RL + 4 +1
RL + 4 +1
RL + 4 +1
WL + 4
+(tWR/
tCK(avg))
WL + 4
+(tWR/
tCK(avg))
WL + 4
+(tWR/
tCK(avg))
WL + 4
+(tWR/
tCK(avg))
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
tWRPDEN
tWRAPDEN
tWRPDEN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nCK
nCK
nCK
nCK
9
10
9
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
WL + 4
+WR +1
WL + 4
+WR +1
WL + 4
+WR +1
WL + 4 +WR
+1
WL + 2
+(tWR/
tCK(avg))
WL + 2
+(tWR/
tCK(avg))
WL + 2
+(tWR/
tCK(avg))
WL + 2
+(tWR/
tCK(avg))
Timing of WR command to Power Down entry
(BC4MRS)
Timing of WRA command to Power Down entry
(BC4MRS)
WL +2 +WR
+1
WL +2 +WR
+1
WL +2 +WR
+1
WL +2 +WR
+1
tWRAPDEN
tREFPDEN
10
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT Timing
1
-
-
1
-
-
1
-
-
1
-
-
20,21
tMRSPDEN tMOD(min)
tMOD(min)
tMOD(min)
tMOD(min)
ODT high time without write command or with write
command and BC4
ODTH4
ODTH8
tAONPD
4
6
2
-
-
4
6
2
-
-
4
6
2
-
-
4
6
2
-
-
nCK
nCK
ns
ODT high time with Write command and BL8
Asynchronous RTT turn-on delay (Power-Down with
DLL frozen)
8.5
8.5
8.5
8.5
Asynchronous RTT turn-off delay (Power-Down with
DLL frozen)
tAOFPD
tAON
2
8.5
400
0.7
0.7
2
8.5
300
0.7
0.7
2
8.5
250
0.7
0.7
2
8.5
225
0.7
0.7
ns
RTT turn-on
-400
0.3
0.3
-300
0.3
0.3
-250
0.3
0.3
-225
0.3
0.3
ps
7,f
8,f
f
RTT_NOM and RTT_WR turn-off time from ODTLoff
reference
tAOF
tCK(avg)
tCK(avg)
RTT dynamic change skew
tADC
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining
mode is programmed
tWLMRD
tWLDQSEN
tWLH
40
25
-
-
-
-
40
25
-
-
-
-
40
25
-
-
-
-
40
25
-
-
-
-
tCK
tCK
ps
3
3
DQS/DQS delay after tDQS margining mode is pro-
grammed
Write leveling setup time from rising CK, CK crossing
to rising DQS, DQS crossing
325
325
245
245
195
195
165
165
Write leveling hold time from rising DQS, DQS cross-
ing to rising CK, CK crossing
tWLH
ps
Write leveling output delay
Write leveling output error
tWLO
0
0
9
2
0
0
9
2
0
0
9
2
0
0
7.5
2
ns
ns
tWLOE
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Rev. 1.0
Unbuffered DIMM
datasheet
DDR3L SDRAM
17.1 Jitter Notes
Specific Note a
Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the
input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm,
another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
Specific Note b
These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition
edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is,
these parameters should be met whether clock jitter is present or not.
Specific Note c
These parameters are measured from a data strobe signal (DQS, DQS) crossing to its respective clock signal (CK, CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the
clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.
Specific Note d
Specific Note e
These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its respective data strobe signal
(DQS, DQS) crossing.
For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)},
which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the
device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge com-
mand at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.
Specific Note f
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input
clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = +
193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(der-
ated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to
tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the
min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <= 12,
and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.
Specific Note g
When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input
clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has
tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min +
tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) =
tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/
max usage!)
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Rev. 1.0
Unbuffered DIMM
datasheet
DDR3L SDRAM
17.2 Timing Parameter Notes
1. Actual value dependant upon measurement level definitions which are TBD.
2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register
5. Value must be rounded-up to next higher integer value
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. For definition of RTT turn-on time tAON see "Device Operation & Timing Diagram Datasheet"
8. For definition of RTT turn-off time tAOF see "Device Operation & Timing Diagram Datasheet".
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
10. WR in clock cycles as programmed in MR0
11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See "Device Operation & Timing
Diagram Datasheet.
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated
by TBD
13. Value is only valid for RON34
14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method.
15. tREFI depends on T
OPER
16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,
(DC) = V DQ(DC). For input only pins except RESET, V (DC)=V CA(DC).
V
REF
REF
REF
REF
See "Address/Command Setup, Hold and Derating" on component datasheet.
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,
(DC)= V DQ(DC). For input only pins except RESET, V (DC)=V CA(DC).
V
REF
REF
REF
REF
See "Data Setup, Hold and Slew Rate Derating" on component datasheet.
18. Start of internal write transaction is defined as follows ;
For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL
19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation & Timing Diagram
Datasheet"
20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down
IDD spec will not be applied until finishing those operations.
21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time
such as tXPDLL(min) is also required. See "Device Operation & Timing Diagram Datasheet".
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming
the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The
appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-
ject to in the application, is illustrated. The interval could be defined by the following formula:
ZQCorrection
(TSens x Tdriftrate) + (VSens x Vdriftrate)
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.
For example, if TSens = 1.5% /°C, VSens = 0.15% / mV, Tdriftrate = 1°C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calcu-
lated as:
0.5
~
~
= 0.133
128ms
(1.5 x 1) + (0.15 x 15)
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.
26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.
27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter-
nate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].
28. Pulse width of a input signal is defined as the width between the first crossing of V
(DC) and the consecutive crossing of V
(DC)
REF
REF
29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge.
30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.
31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
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Rev. 1.0
Unbuffered DIMM
datasheet
DDR3L SDRAM
18. Physical Dimensions
18.1 256Mbx8 based 256Mx72 Module (1 Rank) - M391B5773DH0
Units : Millimeters
133.35 ± 0.15
128.95
SPD
(2)
2.50
54.675
A
B
Max 4.0
47.00
71.00
1.270 ± 0.10
5.00
2x 2.10 ± 0.15
0.80 ± 0.05
0.2 ± 0.15
3.80
1.50±0.10
1.00
2.50
Detail A
Detail B
The used device is 256M x8 DDR3L SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B2G0846D-HY∗∗
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
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Rev. 1.0
Unbuffered DIMM
datasheet
DDR3L SDRAM
18.2 256Mbx8 based 512Mx72 Module (2 Ranks) - M391B5273DH0
Units : Millimeters
133.35 ± 0.15
128.95
SPD
(2)
2.50
54.675
A
B
Max 4.0
47.00
71.00
1.270 ± 0.10
5.00
2x 2.10 ± 0.15
0.80 ± 0.05
0.2 ± 0.15
3.80
1.50±0.10
1.00
2.50
Detail A
Detail B
The used device is 256M x8 DDR3L SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B2G0846D-HY∗∗
* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.
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