INTEGRATED CIRCUITS
DATA SHEET
TDA8767
12-bit high-speed Analog-to-Digital
Converter (ADC)
1999 Feb 16
Preliminary specification
Supersedes data of 1997 Jun 27
File under Integrated Circuits, IC02
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
ORDERING INFORMATION
PACKAGE
TYPE
SAMPLING
NUMBER
FREQUENCY (MHz)
NAME
DESCRIPTION
VERSION
TDA8767H/1
TDA8767H/2
TDA8767H/3
10
20
30
plastic quad flat package; 44 leads
(lead length 1.3 mm); body 10 × 10 × 1.75 mm
QFP44
SOT307-2
BLOCK DIAGRAM
V
V
V
V
V
V
CLK
36
TC
OE
CCA1 CCA2
CCA3 CCA4
CCD1 CCD2
2
9
3
41
37 15
18
19
21 D11
MSB
CLOCK DRIVER
22 D10
23 D9
24 D8
25 D7
26 D6
27 D5
28 D4
TDA8767
11
V
ref
AMP
CMOS
OUTPUTS
data outputs
42
V
I
ANALOG-TO-DIGITAL
CONVERTER
LATCHES
29 D3
30 D2
31 D1
32 D0
43
V
I
sample-
and-hold
39
LSB
SH
33
20
V
CCO
CMOS
OUTPUT
IN-RANGE
LATCH
IR
44
10
4
40
38
17
34
MBH142
AGND1 AGND2 AGND3 AGND4
analog ground
DGND1 DGND2
digital ground
OGND
Fig.1 Block diagram.
3
1999 Feb 16
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
PINNING
SYMBOL PIN
DESCRIPTION
not connected
SYMBOL PIN
DESCRIPTION
n.c.
1
2
3
4
5
6
7
8
9
D9
23 data output; bit 9
24 data output; bit 8
VCCA1
VCCA3
AGND3
n.c.
analog supply voltage 1 (+5 V)
analog supply voltage 3 (+5 V)
analog ground 3
D8
D7
25 data output; bit 7
26 data output; bit 6
27 data output; bit 5
28 data output; bit 4
29 data output; bit 3
30 data output; bit 2
31 data output; bit 1
32 data output; bit 0 (LSB)
33 output supply voltage (3 to 5.25 V)
34 output ground
D6
not connected
D5
n.c.
not connected
D4
n.c.
not connected
D3
n.c.
not connected
D2
VCCA2
AGND2
Vref
analog supply voltage 2 (+5 V)
D1
10 analog ground 2
11 reference voltage
12 not connected
D0
VCCO
OGND
n.c.
CLK
VCCD1
DGND1
SH
n.c.
n.c.
13 not connected
35 not connected
n.c.
14 not connected
36 clock input
VCCD2
n.c.
15 digital supply voltage 2 (+5 V)
16 not connected
37 digital supply voltage 1 (+5 V)
38 digital ground 1
DGND2
TC
17 digital ground 2
39 sample-and-hold enable input
(CMOS level; active HIGH)
18 output two’s complement
AGND4
VCCA4
VI
40 analog ground 4
OE
19 output enable input
(CMOS level; active LOW)
41 analog supply voltage 4 (+5 V)
42 complementary analog input voltage
43 analog input voltage
IR
20 in-range output
D11
D10
21 data output; bit 11 (MSB)
22 data output; bit 10
VI
AGND1
44 analog ground 1
1999 Feb 16
4
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
V
n.c.
1
2
33
CCO
V
V
32 D0
31 D1
30 D2
29 D3
CCA1
CCA3
3
4
AGND3
n.c.
5
TDA8767
n.c.
6
28
D4
7
27 D5
26 D6
25 D7
24 D8
23 D9
n.c.
n.c.
8
V
9
CCA2
10
11
AGND2
V
ref
MBH143
Fig.2 Pin configuration.
1999 Feb 16
5
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCCA
PARAMETER
analog supply voltage
CONDITIONS
MIN.
−0.3
−0.3
MAX.
+7.0
UNIT
note 1
note 1
note 1
V
V
V
VCCD
VCCO
∆VCC
digital supply voltage
output supply voltage
supply voltage difference
VCCA − VCCD
VCCO − VCCD
VCCA − VCCO
+7.0
+7.0
−0.3
−1.0
−1.0
−1.0
0.3
+1.0
+4.0
+4.0
VCCA
VCCD
V
V
V
V
V
VI
input voltage
referenced to AGND
Vi(p-p)
input voltage for differential clock
drive (peak-to-peak value)
−
IO
output current
−
−55
0
10
mA
°C
°C
°C
Tstg
Tamb
Tj
storage temperature
operating ambient temperature
junction temperature
+150
70
−
+150
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided that the supply
voltage differences ∆VCC are respected.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
VALUE (TYP.)
UNIT
thermal resistance from junction to ambient in free air
75
K/W
1999 Feb 16
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
CHARACTERISTICS
V
V
CCA = V2 to V44, V9 to V10, V3 to V4 and V41 to V40 = 4.75 to 5.25 V; VCCD = V37 to V38 and V15 to V17 = 4.75 to 5.25 V;
CCO = V33 to V34 = 3.0 to 5.25 V; AGND and DGND shorted together; Tamb = 0 to +70 °C; typical values measured at
VCCA = VCCD = 5 V and VCCO = 3.3 V; Vi(p-p) − Vi(p-p) = 2.0 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified.
SYMBOL
Supply
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
VCCD
VCCO
ICCA
analog supply voltage
digital supply voltage
output supply voltage
analog supply current
digital supply current
output supply current
4.75
4.75
3.0
−
−
−
5.0
5.25
5.25
5.25
tbf
V
5.0
3.3
40
V
V
mA
mA
mA
ICCD
22
tbf
ICCO
fclk = 20 MHz; fi = 4.43 MHz
12
tbf
Inputs
CLK (REFERENCED TO DGND)
VIL
VIH
IIL
LOW-level input voltage
0
−
−
−
−
−
2
0.8
VCCD
−
100
300
−
V
HIGH-level input voltage
LOW-level input current
HIGH-level input current
2.0
V
Vclk = 0.3VCCD
Vclk = 0.7VCCD
−400
−
−
−
−
µA
µA
µA
kΩ
pF
IIH
Vclk = VCCD
Zi
input impedance
input capacitance
fclk = 30 MHz
fclk = 30 MHz
Ci
2
−
TC; SH AND OE (REFERENCED TO DGND); see Tables 3 and 4
VIL
VIH
IIL
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
0
−
−
−
−
0.8
VCCD
−
V
2.0
−400
−
V
VIL = 0.3VCCD
VIH = 0.7VCCD
µA
µA
IIH
20
VI AND VI (REFERENCED TO AGND; see Tables 1 AND 2); Vref = VCCA − 2 V
IIL
LOW-level input current
HIGH-level input current
input impedance
Vi = Vi
−
−
−
−
10
10
10
2
−
−
−
−
µA
µA
kΩ
pF
IIH
Vi = Vi
Zi
fi = 4.43 MHz
fi = 4.43 MHz
VI = VI; output code 2047
Ci
input capacitance
Vios(d)
input offset voltage in
differential mode
V
V
V
CCA = 5 V
tbf
tbf
tbf
2.5
tbf
tbf
tbf
V
V
V
CCA = 4.75 V
CCA = 5.25 V
2.25
2.75
Vios(s)
input offset voltage in single VI = Vios(s); output
mode
code 2047
VCCA = 5 V
tbf
tbf
tbf
2.5
tbf
tbf
tbf
V
V
V
VCCA = 4.75 V
CCA = 5.25 V
2.25
2.75
V
1999 Feb 16
7
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
SYMBOL
Voltage controlled regulator input Vref (referenced to VCCA
Vref(FS) full scale fixed voltage VCCA = 5 V
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
)
−
−
−
−
3.175
2.0
−
V
Vi(p-p) − Vi(p-p) input voltage amplitude
differential mode
−
−
−
V
(peak-to-peak value)
single mode; Vi = 2.5 V
2.0
V
Iref
input current at Vref
10
µA
Outputs (referenced to DGND)
DIGITAL OUTPUTS D11 TO D0 AND IR (REFERENCED TO DGND)
VOL
VOH
IO
LOW-level output voltage
HIGH-level output voltage
output current in 3-state
IOL = 2 mA
0
−
−
−
0.5
V
IOH = −0.4 mA
0.5 V < VO < VCCO
VCCO − 0.5
−20
VCCD
+20
V
µA
Switching characteristics
CLOCK FREQUENCY fclk (see Fig.3)
fclk(min)
minimum clock frequency
SH = HIGH
SH = LOW
−
−
−
−
1
1
MHz
kHz
fclk(max)
maximum clock frequency
TDA8767H/1
10
20
30
8.5
8.5
−
−
−
−
−
−
−
−
−
−
MHz
MHz
MHz
ns
TDA8767H/2
TDA8767H/3
tCPH
tCPL
clock pulse width HIGH
clock pulse width LOW
ns
Analog signal processing; 50% clock duty factor; Vi − Vi = 2.0 V; Vref = VCCA − 2 V; see Table 1
LINEARITY
ILE
integral non-linearity
fclk = 4 MHz; ramp input
clk = 4 MHz; ramp input;
no missing codes
−
−
±3.0
±0.6
±4.0
±1
LSB
LSB
DLE
differential non-linearity
f
OFER
offset error
VCCA = VCCD = VCCO = 5 V; tbf
Tamb = 25 °C; Vi = Vi; output
code = 2047
−
−
tbf
tbf
LSB
LSB
GER
gain error amplitude; spread VCCA = VCCD = VCCO = 5 V; tbf
from device to device
Tamb = 25 °C; Vi − Vi = 2.0 V
BANDWIDTH (fclk = 30 MHz); note 1
B
analog bandwidth
−1 dB
−3 dB
full scale square wave;
note 3
−
−
−
9
−
−
−
MHz
MHz
ns
18
tbf
tSTLH
tSTHL
analog input settling time
LOW-to-HIGH transition
analog input settling time
HICH-to-LOW transition
full scale square wave;
note 3
−
tbf
−
ns
HARMONICS
THD
total harmonic distortion
fclk = 30 MHz; fi = 4.43 MHz;
note 2
−
−64
−
dB
1999 Feb 16
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
SIGNAL-TO-NOISE RATIO
S/N
signal-to-noise ratio
without harmonics;
fclk = 30 MHz; fi = 4.43 MHz
−
61
−
dB
Timing (CL = 15 pF); note 4; see Fig.3
tds
th
sampling delay time
output hold time
−
8
−
−
12
15
2
ns
ns
ns
ns
−
15
18
td
output delay time
VCCO = 4.75 V
−
VCCO = 3.15 V
3-state output delay times; see Fig.4
tdZH
tdZL
tdHZ
tdLZ
enable HIGH
enable LOW
disable HIGH
disable LOW
−
−
−
−
14
16
16
14
18
20
20
18
ns
ns
ns
ns
Notes to the characteristics
1. The −3 dB (or −1 dB) analog bandwidth is determined by the 3 dB (or 1 dB) reduction in the reconstructed output,
the input being a full-scale sine wave.
2. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:
F
THD = 20 log---------------------------------------------------------------------------------------------------------------
2
2
2
2
2
(2nd) + (3rd) + (4th) + (5th) + (6th)
F being the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.
3. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square wave signal) in order to sample the signal and obtain correct output data (see Fig.5).
4. Output data acquisition: the output data is available after the maximum delay of td.
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
Table 1 Output coding with differential inputs (typical values to AGND); VI(p-p) − VI(p-p) = 2.0 V; Vref = VCCA − 2 V
TWO’S COMPLEMENT
BINARY OUTPUTS
OUTPUTS
CODE
VI
VI
IR
D11 to D0
D11 to D0
underflow
<2.0
2.0
−
>3.0
3.0
−
0
1
1
↓
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 01
↓
1 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
↓
0
1
↓
−
−
2047
↓
2.5
−
2.5
−
1
↓
0 1 1 1 1 1 1 1 1 1 1 1
↓
1 1 1 1 1 1 1 1 1 1 1 1
↓
4094
4095
overflow
−
3.0
>3.0
−
2.0
<2.0
1
1
0
1 1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1
Table 2 Output coding with single input (typical values to AGND); VFS = 2.0 V (p-p); Vref = VCCA − 2 V
TWO’S COMPLEMENT
BINARY OUTPUTS
OUTPUTS
CODE
VI
IR
D11 to D0
D11 to D0
underflow
<1.5
1.5
−
0
1
1
↓
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 01
↓
1 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
↓
0
1
↓
−
2047
↓
2.5
−
1
↓
0 1 1 1 1 1 1 1 1 1 1 1
↓
1 1 1 1 1 1 1 1 1 1 1 1
↓
4094
4095
overflow
−
3.5
>3.5
1
1
0
1 1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1
Table 3 Mode selection
TC
0
OE
0
D0 to D11 and IR
binary; active
1
X(1)
0
two’s complement; active
high impedance
1
Note
1. Where: X = don’t care.
Table 4 Sample-and-hold selection
SH
SAMPLE-AND-HOLD
1
0
active
inactive; tracking mode
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
t
CPL
t
CPH
HIGH
50 %
LOW
CLK
sample N
sample N + 1
sample N + 2
V
l
t
t
ds
h
HIGH
50 %
LOW
DATA
D0 to D11
DATA
N - 2
DATA
N - 1
DATA
N
DATA
N + 1
t
d
MBG855
Fig.3 Timing diagram.
V
CCD
OE
50 %
0V
t
t
dHZ
dZH
HIGH
90 %
output
data
50 %
LOW
t
t
dLZ
dZL
HIGH
output
data
50 %
LOW
10 %
TEST
S1
V
CCD
t
t
t
t
V
dLZ
dZL
dHZ
dZH
CCD
3.3 kΩ
15 pF
V
CCD
S1
TDA8767
DGND
DGND
OE
MBH144
fOE = 100 kHz.
Fig.4 Timing diagram and test conditions of 3-state output delay time.
11
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
t
t
STLH
STHL
50 %
code 1023
V
I
50 %
code 0
5 ns
5 ns
CLK
50 %
50 %
MBD875
2 ns
2 ns
Fig.5 Analog input settling time diagram.
1999 Feb 16
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
APPLICATION INFORMATION
5 V
SH
mode
5 V
220 nF
100 nF
100 nF
(1)
V
V
1 : 1
I
IN
CLK
I
100 Ω
100 Ω
n.c.
5 V
100 nF
V
44 43 42 41 40 39 38 37 36 35 34
CCA
n.c.
1
2
33
32
31
30
29
28
27
26
25
24
23
R1
(2)
D0 (LSB)
D1
5 V
100 nF
3
4
D2
10
nF
4.7 µF
R2
n.c.
n.c.
n.c.
n.c.
5
D3
6
TDA8767H
D4
7
D5
8
D6
100 nF
5 V
9
D7
(3)
10
11
D8
D9
100 nF
V
ref
12 13 14 15 16 17 18 19 20 21 22
n.c.
n.c.
n.c.
MBH145
IR
D10
D11
(MSB)
n.c.
5 V
100 nF
chip select input (OE)
output format select (TC)
The analog, digital and output supplies should be separated and decoupled.
(1) At power-up a high level clock must be provided within less than 1 µs or a pull-up resistor must be connected between CLK and VCCD
.
(2) R1, and R2 must be determined in order to obtain a middle voltage of 2.5 V; see Table 1. To ensure a sufficient analog input stability, the minimum
current into these resistors must be about 1 mA.
(3) Vref must be decoupled to VCCA
.
Fig.6 Application diagram (differential input mode).
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
5 V
SH
mode
5 V
h
100 nF
100 nF
(1)
220 nF
V
I
IN
50 Ω
V
I
CLK
n.c.
5 V
50 Ω
50 Ω
100 nF
44 43 42 41 40 39 38 37 36 35 34
R1
n.c.
1
2
33
32
31
30
29
28
27
26
25
24
23
V
CCA
D0 (LSB)
D1
5 V
100 nF
4.7
µF
10
nF
(2)
R2
3
4
D2
n.c.
n.c.
n.c.
n.c.
5
D3
6
TDA8767H
D4
7
D5
8
D6
100 nF
5 V
9
D7
(3)
10
11
100 nF
D8
D9
V
ref
12 13 14 15 16 17 18 19 20 21 22
n.c.
n.c.
n.c.
MBH146
IR
D10
D11
(MSB)
n.c.
5 V
100 nF
chip select input OE
output format select TC
The analog, digital and output supplies should be separated and decoupled.
(1) At power-up a high level clock must be provided within less than 1 µs or a pull-up resistor must be connected between CLK and VCCD
.
(2) R1, and R2 must be determined in order to obtain a voltage of 2.5 V on VI and VI; see Table 1. To ensure a sufficient analog input stability, the
minimum current into these resistors must be about 1 mA.
(3) Vref must be decoupled to VCCA
.
Fig.7 Application diagram (single input mode).
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
PACKAGE OUTLINE
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
y
X
A
33
23
34
22
Z
E
e
H
E
E
A
2
A
(A )
3
A
1
w M
θ
b
p
L
p
pin 1 index
L
12
44
detail X
1
11
w M
Z
v
M
A
D
b
p
e
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
θ
1
2
3
p
E
p
D
E
max.
10o
0o
0.25 1.85
0.05 1.65
0.40 0.25 10.1 10.1
0.20 0.14 9.9 9.9
12.9 12.9
12.3 12.3
0.95
0.55
1.2
0.8
1.2
0.8
mm
2.10
0.25
0.8
1.3
0.15 0.15 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-02-04
97-08-01
SOT307-2
1999 Feb 16
15
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 Feb 16
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Feb 16
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
NOTES
1999 Feb 16
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Philips Semiconductors
Preliminary specification
12-bit high-speed Analog-to-Digital
Converter (ADC)
TDA8767
NOTES
1999 Feb 16
19
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5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1999
SCA62
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/750/03/pp20
Date of release: 1999 Feb 16
Document order number: 9397 750 04713
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