Philips Electronic Keyboard SA7016 User Manual

INTEGRATED CIRCUITS  
SA7016  
1.3GHz low voltage fractional-N  
synthesizer  
Product specification  
1999 Nov 04  
Supersedes data of 1999 Apr 20  
Philips  
Semiconductors  
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Philips Semiconductors  
Product specification  
1.3GHz low voltage fractional-N synthesizer  
SA7016  
GND  
4
13  
22–BIT SHIFT  
REGISTER  
CLOCK  
DATA  
2–BIT SHIFT  
REGISTER  
PUMP  
CURRENT  
SETTING  
14  
10  
9
PUMP  
BIAS  
CONTROL  
LATCH  
R
SET  
15  
ADDRESS DECODER  
LOAD SIGNALS  
STROBE  
V
DDCP  
LATCH  
COMP  
5
6
RFin+  
RFin–  
8
MAIN DIVIDER  
PHP  
PHASE  
DETECTOR  
AMP  
7
1
GND  
CP  
LATCH  
12  
LOCK  
REF  
in+  
REFERENCE  
DIVIDER  
REF  
in–  
11  
2
16  
PON  
TEST  
3
V
DD  
SR01506  
Figure 2. Block Diagram  
PINNING  
SYMBOL  
LOCK  
PIN  
1
DESCRIPTION  
Lock detect output  
Test (should be either grounded or  
TEST  
2
connected to V  
Digital supply  
Digital ground  
DD)  
V
3
4
DD  
GND  
RFin+  
RFin–  
5
RF input to main divider  
RF input to main divider  
Charge pump ground  
6
GND  
PHP  
7
CP  
8
Main normal chargepump  
Charge pump supply voltage  
V
DDCP  
9
R
10  
External resistor from this pin to ground  
sets the chargepump current  
SET  
REFin–  
REFin+  
CLOCK  
DATA  
11  
12  
13  
14  
15  
16  
Reference input  
Reference input  
Programming bus clock input  
Programming bus data input  
Programming bus enable input  
Power down control  
STROBE  
PON  
3
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Philips Semiconductors  
Product specification  
1.3GHz low voltage fractional-N synthesizer  
SA7016  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 134).  
SYMBOL  
PARAMETER  
MIN.  
MAX.  
UNIT  
V
V
Digital supply voltage  
Analog supply voltage  
–0.3  
–0.3  
–0.3  
–0.3  
–0.3  
+5.5  
+5.5  
+2.8  
V
V
V
V
V
V
DD  
DDCP  
V  
–V  
DD  
Difference in voltage between V  
V
(V  
V  
)
DDCP  
DDCP and DD  
DDCP  
DD  
V
Voltage at pins 1, 2, 5, 6, 11 to 16  
Voltage at pin 8, 9  
V + 0.3  
DD  
n
1
V
V
DDCP  
+ 0.3  
V  
Difference in voltage between GND and GND (these pins should –0.3  
be connected together)  
+0.3  
GND  
CP  
T
Storage temperature  
–55  
–40  
+125  
+85  
_C  
_C  
_C  
stg  
T
T
Operating ambient temperature  
Maximum junction temperature  
amb  
150  
j
Handling  
Inputs and outputs are protected against electrostatic discharge in  
normal handling. However, to be totally safe, it is desirable to take  
normal precautions appropriate to handling MOS devices.  
THERMAL CHARACTERISTICS  
SYMBOL  
PARAMETER  
VALUE  
120  
UNIT  
R
Thermal resistance from junction to ambient in free air  
K/W  
th j–a  
4
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Philips Semiconductors  
Product specification  
1.3GHz low voltage fractional-N synthesizer  
SA7016  
CHARACTERISTICS  
V
DDCP  
= V = +3.0V, T = +25°C; unless otherwise specified.  
DD  
amb  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Supply; pins 3, 9  
V
V
Digital supply voltage  
2.7  
2.7  
5.5  
5.5  
V
DD  
Analog supply voltage  
V
V
= V  
DD  
V
DDCP  
DDTotal  
Standby  
DDCP  
I
I
Synthesizer operational total supply current  
Total supply current in power-down mode  
= +3.0V  
6.2  
1
7.3  
mA  
µA  
DD  
logic levels 0 or VDD  
TBD  
RFin main divider input; pins 5, 6  
f
VCO input frequency  
350  
–18  
1300  
0
MHz  
VCO  
V
AC-coupled input signal level  
R
(external) = R = 50;  
dBm  
RFin(rms)  
in  
s
single-ended drive;  
max. limit is indicative  
@ 500 to 1300 MHz  
Z
Input impedance (real part)  
Typical pin input capacitance  
Main divider ratio  
f
f
= 1.2 GHz  
= 1.2 GHz  
625  
1.0  
IRFin  
VCO  
VCO  
C
65535  
4
pF  
IRFin  
main  
N
512  
f
Maximum loop comparison frequency  
indicative, not tested  
MHz  
PCmax  
Reference divider input; pins 11, 12  
f
Input frequency range from TCXO  
AC-coupled input signal level  
5
40  
MHz  
REFin  
VRFin  
single-ended drive;  
360  
1300  
mV  
PP  
max. limit is indicative  
Z
Input impedance (real part)  
Typical pin input capacitance  
Reference division ratio  
f
= 20 MHz  
= 20 MHz  
4
10  
1.0  
kΩ  
REFin  
REF  
REF  
C
R
f
pF  
REFin  
REF  
1023  
Charge pump current setting resistor input; pin 10  
R
V
External resistor from pin to ground  
Regulated voltage at pin  
6
7.5  
15  
kΩ  
SET  
R
=7.5 kΩ  
SET  
1.25  
V
SET  
Charge pump outputs (including fractional compensation pump); pin 8; R  
=7.5k, FC=80  
SET  
1
I
I
I
I
Charge pump current ratio to I  
Current gain I /I  
PH SET  
–15  
–10  
–10  
–10  
0.7  
+15  
+10  
+10  
+10  
%
%
%
nA  
V
CP  
SET  
Sink-to-source current matching  
Output current variation versus V  
Charge pump off leakage current  
V
PH  
V
PH  
V
PH  
=1/2 V  
.
MATCH  
ZOUT  
LPH  
DDCP  
2
in compliance range  
=1/2 V  
PH  
CC  
V
Charge pump voltage compliance  
V
–0.8  
PH  
DDCP  
5
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1999 Nov 04  
Philips Semiconductors  
Product specification  
1.3GHz low voltage fractional-N synthesizer  
SA7016  
SYMBOL  
PARAMETER  
= 7.5 k, CP=00)  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Phase noise (R  
SET  
Synthesizer’s contribution to close-in phase noise  
of 900 MHz RF signal at 1 kHz offset.  
GSM  
–90  
dBc/Hz  
f
f
= 13MHz, TCXO,  
= 1MHz  
REF  
COMP  
indicative, not tested  
L(f)  
Synthesizer’s contribution to close-in phase noise  
of 800 MHz RF signal at 1 kHz offset.  
TDMA  
–85  
dBc/Hz  
f
f
= 19.44MHz, TCXO,  
REF  
= 240kHz  
COMP  
indicative, not tested  
Interface logic input signal levels; pins 13, 14, 15, 16  
V
V
I
HIGH level input voltage  
LOW level input voltage  
Input leakage current  
0.7*V  
V +0.3  
DD  
V
IH  
IL  
DD  
–0.3  
–0.5  
0.3*V  
V
DD  
logic 1 or logic 0  
+0.5  
µA  
LEAK  
Lock detect output signal (in push/pull mode); pin 1  
V
V
LOW level output voltage  
HIGH level output voltage  
I
I
=2mA  
0.4  
V
V
OL  
sink  
=–2mA  
V
–0.4  
OH  
source  
DD  
NOTES:  
VSET  
1. I  
bias current for charge pumps.  
SET =  
RSET  
2. The relative output current variation is defined as:  
DIOUT  
(I2–I1)  
+ 2.  
; with V1 + 0.7V, V2 + VDDCP –0.8V (See Figure 3.)  
IOUT  
I(I2 ) I1)I  
CURRENT  
I
I
ZOUT  
2
I
1
V
PH  
V
1
V
2
I
2
I
1
SR00602  
Figure 3. Relative Output Current Variation  
6
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Product specification  
1.3GHz low voltage fractional-N synthesizer  
SA7016  
fractional accumulator and is nulled by the fractional compensation  
charge pump.  
FUNCTIONAL DESCRIPTION  
Main Fractional-N divider  
The reloading of a new main divider ratio is synchronized to the  
state of the main divider to avoid introducing a phase disturbance.  
The RFin inputs drive a pre-amplifier to provide the clock to the first  
divider stage. For single ended operation, the signal should be fed to  
one of the inputs while the other one is AC grounded. The  
pre-amplifier has a high input impedance, dominated by pin and pad  
capacitance. The circuit operates with signal levels from –18 dBm to  
0 dBm, and at frequencies as high as 1.3 GHz. The divider consists  
of a fully programmable bipolar prescaler followed by a CMOS  
counter. Total divide ratios range from 512 to 65536.  
Reference divider  
The reference divider consists of a divider with programmable  
values between 4 and 1023 followed by a three bit binary counter.  
The 3 bit SM (SA) register (see Figure 4) determines which of the 5  
output pulses are selected as the main (auxiliary) phase detector  
input.  
At the completion of a main divider cycle, a main divider output  
pulse is generated which will drive the main phase comparator. Also,  
the fractional accumulator is incremented by the value of NF. The  
accumulator works with modulo Q set by FMOD. When the  
accumulator overflows, the overall division ratio N will be increased  
by 1 to N + 1, the average division ratio over Q main divider cycles  
(either 5 or 8) will be  
Phase detector (see Figure 5)  
The reference and main (aux) divider outputs are connected to a  
phase/frequency detector that controls the charge pump. The pump  
current is set by an external resistor in conjunction with control bits  
CP0 and CP1 in the C-word (see Charge Pump table). The dead  
zone (caused by finite time taken to switch the current sources on or  
off) is cancelled by forcing the pumps ON for a minimum time at  
every cycle (backlash time) providing improved linearity.  
NF  
Nfrac + N )  
Q
The output of the main divider will be modulated with a fractional  
phase ripple. The phase ripple is proportional to the contents of the  
SM=”000”  
TO  
MAIN  
SM=”001”  
PHASE  
SM=”010”  
DETECTOR  
SM=”011”  
SM=”100”  
REFERENCE  
INPUT  
DIVIDE BY R  
/2  
/2  
/2  
/2  
SA=”100”  
SA=”011”  
SA=”010”  
TO  
AUXILIARY  
PHASE  
DETECTOR  
SA=”001”  
SA=”000”  
SR01415  
Figure 4. Reference Divider  
7
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Product specification  
1.3GHz low voltage fractional-N synthesizer  
SA7016  
V
CC  
P–TYPE  
CHARGE PUMP  
“1”  
P
D
Q
REF DIVIDER  
f
CLK  
REF  
R
R
R
I
τ
PH  
“1”  
D
N–TYPE  
CHARGE PUMP  
AUX/MAIN  
DIVIDER  
CLK  
N
Q
X
GND  
f
REF  
R
X
P
N
τ
τ
I
PH  
SR02103  
Figure 5. Phase Detector Structure with Timing  
8
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Product specification  
1.3GHz low voltage fractional-N synthesizer  
SA7016  
Main Output Charge Pumps and Fractional  
Compensation Currents (see Figure 6)  
The main charge pumps on pins PHP and PHI are driven by the  
main phase detector and the charge pump current values are  
The compensation is done by sourcing a small current, I  
, see  
COMP  
Figure 7, that is proportional to the fractional error phase. For proper  
fractional compensation, the area of the fractional compensation  
current pulse must be equal to the area of the fractional charge  
pump ripple. The width of the fractional compensation pulse is fixed  
to 128 VCO cycles, the amplitude is proportional to the fractional  
accumulator value and is adjusted by FDAC values (bits FC7–0 in  
the B-word). The fractional compensation current is derived from the  
main charge pump in that it follows all the current scaling through  
determined by the current at pin R  
in conjunction with bits CP0,  
SET  
CP1 in the B-word (see table of charge pump ratios). The fractional  
compensation is derived from the current at R , the contents of  
SET  
the fractional accumulator FRD and by the program value of the  
FDAC. The timing for the fractional compensation is derived from  
the main divider. The main charge pumps will enter speed up mode  
after the A-word is set and strobe goes High. When strobe goes  
Low, charge pump will exit speed up mode.  
external resistor setting, R , programming or speed-up operation.  
SET  
For a given charge pump,  
Principle of Fractional Compensation  
The fractional compensation is designed into the circuit as a means  
of reducing or eliminating fractional spurs that are caused by the  
I
= ( I  
/ 128 ) * ( FDAC / 5*128) * FRD  
PUMP  
COMP  
FRD is the fractional accumulator value.  
fractional phase ripple of the main divider. If I  
is the  
COMP  
The target values for FDAC are: 128 for FMOD = 1 (modulo 5) and  
80 for FMOD = 0 (modulo 8).  
compensation current and I  
charge pump:  
is the pump current, then for each  
PUMP  
I
= I  
+ I  
.
PUMP_TOTAL  
PUMP  
COMP  
REFERENCE R  
MAIN M  
DIVIDE RATIO  
N
N
2
N+1  
4
N
1
N+1  
DETECTOR  
OUTPUT  
3
0
ACCUMULATOR  
FRACTIONAL  
COMPENSATION  
CURRENT  
PULSE  
WIDTH  
MODULATION  
mA  
OUTPUT ON  
PUMP  
µA  
PULSE LEVEL  
MODULATION  
SR01416  
NOTE: For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output.  
2
Figure 6. Waveforms for NF = 2 Modulo 5 fraction = /  
5
FMOD  
f
MAIN DIVIDER  
N = 8042  
FRACTIONAL  
ACCUMULATOR  
RF  
1930.140 MHz  
NF  
240.016 kHz  
I
COMP  
I
PUMP  
f
LOOP FILTER  
& VCO  
REF  
240 kHz  
SR01682  
Figure 7. Current Injection Concept  
9
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Product specification  
1.3GHz low voltage fractional-N synthesizer  
SA7016  
Charge pump currents  
CP0  
0
I
I
PHP–SU  
PHP  
3xI  
1xl  
15xl  
SET  
SET  
SET  
SET  
1
5xl  
NOTES:  
1. I  
2. I  
=V  
/R : bias current for charge pumps.  
is the total current at pin PHP during speed up condition.  
SET  
PHP–SU  
SET SET  
Lock Detect  
Power-down mode  
The output LOCK maintains a logic ‘1’ when the auxiliary phase  
detector ANDed with the main phase detector indicates a lock  
condition. The lock condition for the main and auxiliary synthesizers  
is defined as a phase difference of less than "1 period of the  
frequency at the input REFin+, –. One counter can fulfill the lock  
condition when the other counter is powered down. Out of lock (logic  
‘0’) is indicated when both counters are powered down.  
The power-down signal can be either hardware (PON) or software  
(PD). The PON signal is exclusively ORed with the PD bits in  
B-word. If PON = 0, then the part is powered up when PD = 1. PON  
can be used to invert the polarity of the software bit PD. When the  
synthesizer is reactivated after power-down, the main and reference  
dividers are synchronized to avoid possibility of random phase  
errors on power-up.  
10  
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Philips Semiconductors  
Product specification  
1.3GHz low voltage fractional-N synthesizer  
SA7016  
data is latched into different working registers or temporary  
Serial programming bus  
registers. In order to fully program the synthesizer, 3 words must be  
sent: C, B, and A. Table 1 shows the format and the contents of  
each word. The D word is normally used for testing purposes. When  
sending the B-word, data bits FC7–0 for the fractional compensation  
DAC are not loaded immediately. Instead they are stored in  
temporary registers. Only when the A-word is loaded, these  
temporary registers are loaded together with the main divider ratio.  
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to  
program all counter divide ratios, fractional compensation DAC,  
selection and enable bits. The programming data is structured into  
24 bit words; each word includes 2 or 3 address bits. Figure 8  
shows the timing diagram of the serial input. When the STROBE  
goes active HIGH, the clock is disabled and the data in the shift  
register remains unchanged. Depending on the address bits, the  
Serial bus timing characteristics. See Figure 8.  
V
DD  
= V  
=+3.0V; T = +25°C unless otherwise specified.  
DDCP  
amb  
SYMBOL  
Serial programming clock; CLK  
PARAMETER  
MIN.  
TYP.  
MAX.  
UNIT  
t
t
Input rise time  
Input fall time  
Clock period  
10  
10  
40  
40  
ns  
ns  
ns  
r
f
T
100  
cy  
Enable programming; STROBE  
t
t
t
Delay to rising clock edge  
40  
ns  
ns  
ns  
START  
W
Minimum inactive pulse width  
Enable set-up time to next clock edge  
1/f  
COMP  
20  
SU;E  
Register serial input data; DATA  
t
t
Input data to clock set-up time  
Input data to clock hold time  
20  
20  
ns  
ns  
SU;DAT  
HD;DAT  
Application information  
t
t
t
r
t
SU;E  
SU;DAT  
HD;DAT  
t
f
T
cy  
CLK  
ADDRESS  
MSB  
LSB  
DATA  
STROBE  
t
w
t
START  
SR01417  
Figure 8. Serial Bus Timing Diagram  
11  
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Product specification  
1.3GHz low voltage fractional-N synthesizer  
SA7016  
Data format  
Table 1. Format of programmed data  
LAST IN  
MSB  
SERIAL PROGRAMMING FORMAT  
FIRST IN LSB  
p23  
p22  
p21  
p20  
../..  
../..  
p1  
p0  
Table 2. A word, length 24 bits  
LAST IN  
MSB  
LSB  
FIRST IN  
Address  
fmod Fractional-N  
Main Divider ratio  
Spare  
0
0
FM  
NF2 NF1  
NF0  
N15  
N14 N13  
N12  
N11 N10  
N9  
N8  
N7  
N6  
N5  
N4  
N3  
N2  
N1  
N0  
SP1  
SP2  
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
Default:  
A word select  
Fixed to 00.  
FM 0 = modulo 8, 1 = modulo 5.  
NF2..0 Fractional N Increment values 000 to 111.  
N0..N15, Main divider values 512 to 65535 allowed for divider ratio.  
Fractional Modulus select  
Fractional-N Increment  
N-Divider  
Table 3. B word, length 24 bits  
Address  
LOCK  
LO  
SPARE  
SP3  
0
REFERENCE DIVIDER  
PD  
CP  
FRACTIONAL COMPENSATION DAC  
0
1
R9  
R8  
R7  
R6  
R5  
R4  
R3  
R2  
R1  
R0  
MAIN CP0 FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0  
Default:  
0
0
0
1
0
1
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
B word select  
R-Divider  
Fixed to 01  
R0..R9, Reference divider values 4 to 1023 allowed for divider ration.  
CP0: Charge pump current ratio, see table of charge pump currents.  
Charge pump current  
Ratio  
Lock detect output  
Power down  
L0  
0
1
Main lock detect signal present at the LOCK pin (push/pull).  
Main lock detect signal present at the LOCK pin (open drain).  
When main loop is in power down mode, the lock indicator is low.  
Main = 1: power to main divider, reference divider, main charge pumps, Main = 0 to power down.  
FC7..0 Fractional Compensation charge pump current DAC, values 0 to 255.  
Fractional Compensation  
Table 4. D word, length 24 bits  
Address  
SYNTHESIZER TEST  
BITS  
SYNTHESIZER TEST BITS  
1
1
0
0
0
0
0
0
Tspu  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default:  
Tspu: Speed up = 1  
Forces the main charge pumps in speed-up mode all the time.  
NOTE: All test bits must be set to 0 for normal operation.  
12  
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Product specification  
1.3GHz low voltage fractional-N synthesizer  
SA7016  
600  
800  
600  
I
I
= 206.67 mA  
SET  
400  
200  
= 165.33 mA  
SET  
V
I
= 3.0 V  
dd  
400  
I
I
= 103.33 mA  
SET  
= 165.33 µA  
SET  
TEMP = 85°C  
= 51.67 mA  
200  
SET  
TEMP = 25°C  
TEMP = –40°C  
0
0
–200  
–400  
–600  
–800  
I
I
= 51.67 mA  
SET  
–200  
–400  
–600  
= 103.33 mA  
SET  
I
I
= 165.33 mA  
SET  
= 206.67 mA  
SET  
0
0.25 0.5 0.75  
1
1.25 1.5 1.75  
2
2.25 2.5 2.75  
3
0
0.25 0.5 0.75  
1
1.25 1.5 1.75  
2
2.25 2.5 2.75  
3
3.25 3.5  
COMPLIANCE VOLTAGE (V)  
COMPLIANCE VOLTAGE (V)  
SR01911  
SET  
SR01912  
Figure 9. Php Charge Pump Output vs. I  
Figure 10. Php Charge Pump Output vs. Temperature  
(CP = 0; V = 3.0 V; I = 165.33 mA)  
(CP = 0, TEMP = 25_C)  
DD  
SET  
250  
200  
150  
100  
50  
200  
150  
100  
50  
I
I
= 206.67 mA  
SET  
= 165.33 mA  
SET  
I
I
= 103.33 mA  
SET  
SET  
V
I
= 3.0 V  
dd  
= 165.33 µA  
SET  
= 51.67 mA  
TEMP = 85°C  
TEMP = 25°C  
TEMP = –40°C  
0
0
–50  
–100  
–150  
–200  
–250  
I
I
= 51.67 mA  
SET  
–50  
–100  
–150  
–200  
= 103.33 mA  
SET  
I
I
= 165.33 mA  
SET  
= 206.67 mA  
SET  
0
0.25 0.5 0.75  
1
1.25 1.5 1.75  
2
2.25 2.5 2.75  
3
0
0.25 0.5 0.75  
1
1.25 1.5 1.75  
2
2.25 2.5 2.75  
3
3.25 3.5  
SR01914  
COMPLIANCE VOLTAGE (V)  
COMPLIANCE VOLTAGE (V)  
SR01913  
SET  
Figure 11. Php Charge Pump Output vs. I  
Figure 12. Php Charge Pump Output vs. Temperature  
(CP = 1; V = 3.0 V; I = 165.33 mA)  
(CP = 1; TEMP = 25_C)  
DD  
SET  
3000  
2000  
1000  
0
3500  
2500  
1500  
I
I
= 206.67 mA  
SET  
= 165.33 mA  
SET  
I
= 103.33 mA  
SET  
SET  
TEMP = 85_C  
TEMP = 25_C  
TEMP = –40_C  
I
= 51.67 mA  
500  
0
–500  
I
I
= 51.67 mA  
SET  
–1000  
–2000  
–3000  
–1500  
–2500  
–3500  
= 103.33 mA  
SET  
I
I
= 165.33 mA  
SET  
= 206.67 mA  
SET  
0
0.25 0.5 0.75  
1
1.25 1.5 1.75  
2
2.25 2.5 2.75  
3
0
0.25 0.5 0.75  
1
1.25 1.5 1.75  
2
2.25 2.5 2.75  
3
3.25 3.5  
COMPLIANCE VOLTAGE (V)  
COMPLIANCE VOLTAGE (V)  
SR01915  
SR01916  
Figure 13. Php–su Charge Pump Output vs. I  
Figure 14. Php–su Charge Pump Output vs. Temperature  
(CP = 0; V = 3.0 V; I = 165.33 mA)  
SET  
(CP = 0; TEMP = 25_C)  
DD  
SET  
13  
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Philips Semiconductors  
Product specification  
1.3GHz low voltage fractional-N synthesizer  
SA7016  
1500  
1000  
800  
I
I
I
I
= 206.67 mA  
= 165.33 mA  
= 103.33 mA  
= 51.67 mA  
SET  
SET  
SET  
SET  
1000  
500  
600  
TEMP = 85_C  
400  
TEMP = 25_C  
200  
TEMP = –40_C  
0
0
I
I
= 51.67 mA  
–200  
–400  
–600  
–800  
–1000  
SET  
–500  
–1000  
–1500  
= 103.33 mA  
SET  
I
I
= 165.33 mA  
= 206.67 mA  
SET  
SET  
0
0.25 0.5 0.75  
1
1.25 1.5 1.75  
2
2.25 2.5 2.75  
3
0
0.25 0.5 0.75  
1
1.25 1.5 1.75  
2
2.25 2.5 2.75  
3
3.25 3.5  
SR01918  
COMPLIANCE VOLTAGE (V)  
COMPLIANCE VOLTAGE (V)  
SR01917  
Figure 15. Php–su Charge Pump Output vs. I  
Figure 16. Php–su Charge Pump Output vs. Temperature  
(CP = 1; V = 3.0 V; I = 165.33 mA)  
SET  
(CP = 1; TEMP = 25_C)  
DD  
SET  
0
–5  
0
–5  
V
V
= 5.50 V  
= 3.75 V  
DD  
DD  
–10  
–15  
–20  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
–60  
–10  
–15  
–20  
–25  
–30  
V
V
= 3.00 V  
= 2.70 V  
DD  
DD  
+85_C  
+25_C  
–35  
–40  
–45  
–50  
–40_C  
0
200  
400  
600  
800 1000 1200 1400 1600 1800 2000  
FREQUENCY (MHz)  
0
200  
400  
600  
800 1000 1200 1400 1600 1800 2000  
FREQUENCY (MHz)  
SR01930  
SR01929  
Figure 17. Main Divider Input Sensitivity vs. Frequency and  
Figure 18. Main Divider Input Sensitivity vs. Frequency and  
Supply Voltage (TEMP = 25_C)  
Temperature (V = 3.00 V)  
DD  
0
0
–5  
–5  
TEMP = +85_C  
V
V
= 5.00 V  
= 3.75 V  
DD  
DD  
–10  
TEMP = +25_C  
–10  
–15  
–20  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
–15  
TEMP = –40_C  
V
V
= 3.00 V  
= 2.70 V  
DD  
DD  
–20  
–25  
–30  
–35  
–40  
–45  
–50  
–55  
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70  
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70  
FREQUENCY (MHz)  
SR01921  
FREQUENCY (MHz)  
SR01922  
Figure 19. Reference Divider Input Sensitivity vs. Frequency  
Figure 20. Reference Divider Input Sensitivity vs. Frequency  
and Supply Voltage (TEMP = 25_C)  
and Temperature (V = 3.00 V)  
DD  
14  
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1999 Nov 04  
Philips Semiconductors  
Product specification  
1.3GHz low voltage fractional-N synthesizer  
SA7016  
8.5  
8
7.5  
7
6.5  
TEMP = +85_C  
6
TEMP = +25_C  
TEMP = –40_C  
5.5  
2.5  
3
3.5  
4
4.5  
5
5.5  
6
SUPPLY VOLTAGE (V)  
SR01931  
Figure 21. Current Supply Over V  
DD  
15  
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1999 Nov 04  
Philips Semiconductors  
Product specification  
1.3GHz low voltage fractional-N frequency  
synthesizer  
SA7016  
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm  
SOT403-1  
16  
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Philips Semiconductors  
Product specification  
1.3GHz low voltage fractional-N frequency  
synthesizer  
SA7016  
NOTES  
17  
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Philips Semiconductors  
Product specification  
1.3GHz low voltage fractional-N frequency  
synthesizer  
SA7016  
Data sheet status  
[1]  
Data sheet  
status  
Product  
status  
Definition  
Objective  
specification  
Development  
This data sheet contains the design target or goal specifications for product development.  
Specification may change in any manner without notice.  
Preliminary  
specification  
Qualification  
This data sheet contains preliminary data, and supplementary data will be published at a later date.  
Philips Semiconductors reserves the right to make chages at any time without notice in order to  
improve design and supply the best possible product.  
Product  
specification  
Production  
This data sheet contains final specifications. Philips Semiconductors reserves the right to make  
changes at any time without notice in order to improve design and supply the best possible product.  
[1] Please consult the most recently issued datasheet before initiating or completing a design.  
Definitions  
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one  
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or  
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended  
periods may affect device reliability.  
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips  
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or  
modification.  
Disclaimers  
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications  
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.  
RighttomakechangesPhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard  
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless  
otherwise specified.  
Philips Semiconductors  
811 East Arques Avenue  
P.O. Box 3409  
Copyright Philips Electronics North America Corporation 1999  
All rights reserved. Printed in U.S.A.  
Sunnyvale, California 94088–3409  
Telephone 800-234-7381  
Date of release: 11-99  
Document order number:  
9397 750 06565  
Philips  
Semiconductors  
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