Philips Computer Drive UDA1325 User Manual

INTEGRATED CIRCUITS

DATA SHEET

UDA1325

Universal Serial Bus (USB) CODEC

1999 May 10

Preliminary speciﬁcation

File under Integrated Circuits, IC01

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Philips Semiconductors

Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

All I²S inputs and I²S outputs support standard I²S-bus

format and the LSB justified serial data format with word

lengths of 16, 18 and 20 bits.

APPLICATIONS

• USB monitors

• USB speakers

Via the digital I/O module with its I²S input and output, an

external DSP can be used for adding extra sound

processing features for the audio playback channel.

• USB microphones

• USB headsets

• USB telephone/answering machines

• USB links in consumer audio devices.

The microcontroller is responsible for handling the

high-level USB protocols, translating the incoming control

requests and managing the user interface via general

purpose pins and an I²C-bus.

GENERAL DESCRIPTION

The ADAC enables the wide and continuous range of

playback sampling frequencies. By means of a Sample

Frequency Generator (SFG), the ADAC is able to

reconstruct the average sample frequency from the

incoming audio samples. The ADAC also performs the

playback sound processing. The ADAC consists of a

FIFO, an unique audio feature processing DSP, the SFG,

digital filters, a variable hold register, a Noise Shaper (NS)

and a Filter Stream DAC (FSDAC) with line output drivers.

The audio information is applied to the ADAC via the USB

processor or via the digital I²S input of the digital I/O

module.

The UDA1325 is a single chip stereo USB codec

incorporating bitstream converters designed for

implementation in USB-compliant audio peripherals and

multimedia audio applications. It contains a USB interface,

an embedded microcontroller, an Analog-to-Digital

Interface (ADIF) and an Asynchronous Digital-to-Analog

Converter (ADAC).

The USB interface consists of an analog front-end and a

USB processor. The analog front-end transforms the

differential USB data into a digital data stream. The USB

processor buffers the incoming and outgoing data from the

analog front-end and handles all low-level USB protocols.

The USB processor selects the relevant data from the

universal serial bus, performs an extensive error detection

and separates control information and audio information.

The control information is made accessible to the

microcontroller. At playback, the audio information

becomes available at the digital I²S output of the digital I/O

module or is fed directly to the ADAC. At recording, the

audio information is delivered by the ADIF or by the digital

I²S input of the I²S-bus interface.

The ADIF consists of an Programmable Gain Amplifier

(PGA), an Analog-to-Digital Converter (ADC) and a

Decimator Filter (DF). An Analog Phase Lock Loop (APLL)

or oscillator is used for creating the clock signal of the

ADIF. The clock frequency for the ADIF can be controlled

via the microcontroller. Several clock frequencies are

possible for sampling the analog input signal at different

sampling rates.

The wide dynamic range of the bitstream conversion

technique used in the UDA1325 for both the playback and

recording channel guarantees a high audio sound quality.

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME

DESCRIPTION

VERSION

UDA1325PS

UDA1325H

SDIP42

QFP64

plastic shrink dual in-line package; 42 leads (600 mil)

SOT270-1

SOT319-2

plastic quad ﬂat package; 64 leads (lead length 1.95 mm);

body 14 × 20 × 2.8 mm

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Philips Semiconductors

Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

QUICK REFERENCE DATA

SYMBOL

Supplies

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V_DDE

supply voltage periphery

supply voltage core

total supply current

4.75

5.0

5.25

3.6

tbf

V_DDI

3.0

−

3.3

I_DD(tot)

I_DD(tot)(ps)

µA

total supply current in power-saving note 1

mode

360

−

Dynamic performance DAC

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

f_s= 44.1 kHz; R_L= 5 kΩ

f_i= 1 kHz (0 dB)

−

−90

0.0032 0.01

−80

f_i= 1 kHz (−60 dB)

−30

3.2

−20

−

S/N

signal-to-noise ratio at bipolar zero A-weighted at code 0000H 90

dBA

V_o(FS)(rms)

full-scale output voltage

(RMS value)

V_DD= 3.3 V

−

0.66

−

Dynamic performance PGA and ADC

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

f_s= 44.1 kHz;

PGA gain = 0 dB

f_i= 1 kHz; (0 dB);

V_i= 1.0 V (RMS)

−

−85

0.0056 0.01

−80

f_i= 1 kHz (−60 dB)

−

−30

3.2

−20

10.0

−

S/N

signal-to-noise ratio

V_i= 0.0 V

dBA

General characteristics

f_i(s)

audio input sample frequency

operating ambient temperature

−

kHz

T_amb

°C

Note

1. Exclusive the IDDE current which depends on the components connected to the I/O pins.

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

BLOCK DIAGRAM

handbook, full pagewidth

P0.7 to P0.0

P2.0 to P2.7

CLK

D+

D−

8 (9)

6 (8)

7, 5, 3, 64,

62, 60, 58, 56

14, 16, 18, 20,

22, 23, 29, 30

(10) 9

(11) 10

(12) 11

(13) 12

(23) 32

(24) 33

(29) 38

(30) 39

(33) 42

(35) 44

DDI

SSI

24 (19)

SSX

SSE

XTAL1b 25 (20)

XTAL2b 26 (21)

ANALOG FRONT-END

USB-PROCESSOR

OSC

48 MHz

DDE

DDO

SSO

DDA1

SSA1

DDA2

SSA2

TIMING

28 (22)

52 (39)

53 (40)

DDX

DDA3

XTAL2a

OSC

ADC

ANALOG

PLL

XTAL1a 54 (41)

55 (42)

SSA3

GP2/DO 63 (4)

GP3/WSO 1 (5)

GP4/BCKO 2 (6)

GP1/DI 13 (14)

DIGITAL I/O

(17) 19 SCL

(18) 21 SDA

GP0/BCKI 17 (16)

GP5/WSI 15 (15)

MICRO-

CONTROLLER

PSEN 31

MUX

FIFO

DA 57 (1)

WS 59 (2)

BCK 61 (3)

SAMPLE

FREQUENCY

GENERATOR

AUDIO FEATURE

PROCESSING DSP

I S-BUS

INTERFACE

DECIMATOR

FILTER

(7) 4 SHTCB

(26) 35 TC

UPSAMPLE FILTERS

VARIABLE HOLD REGISTER

3rd-ORDER NOISE SHAPER

TEST

CONTROL

BLOCK

EA 48

ALE 50

(27) 36 RTCB

VINL 43 (34)

VINR 47 (36)

LEFT

Σ∆ ADC

PGA

UDA1325

LEFT

DAC

−

(25) 34 VOUTL

(28) 37 VOUTR

RIGHT

Σ∆ ADC

−

RIGHT

DAC

REFERENCE VOLTAGE

VRN 49 (37)

VRP 51 (38)

45, 46

n.c.

41 (32)

40 (31)

MGM108

ref(AD)

ref(DA)

The pin numbers given in parenthesis refer to the SDIP42 version.

Fig.1 Block diagram (QFP64 package).

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

PINNING

SYMBOL

I/O

DESCRIPTION

QFP64 SDIP42

GP3/WSO

GP4/BCKO

P0.5

−

I/O

general purpose pin 3 or word select output

general purpose pin 4 or bit clock output

Port 0.5 of the microcontroller

SHTCB

P0.6

shift clock of the test control block (active HIGH)

Port 0.6 of the microcontroller

I/O

D−

negative data line of the differential data bus, conforms to the USB

standard

P0.7

D+

−

I/O

Port 0.7 of the microcontroller

positive data line of the differential data bus, conforms to the USB

standard

V_DDI

−

digital supply voltage for core

digital ground for core

V_SSI

V_SSE

digital ground for I/O pads

V_DDE

−

digital supply voltage for I/O pads

general purpose pin 1 or data input

Port 2.0 of the microcontroller

general purpose pin 5 or word select input

Port 2.1 of the microcontroller

general purpose pin 0 or bit clock input

Port 2.2 of the microcontroller

serial clock line I²C-bus

GP1/DI

P2.0

I/O

−

GP5/WSI

P2.1

GP0/BCKI

P2.2

SCL

−

P2.3

Port 2.3 of the microcontroller

serial data line I²C-bus

SDA

P2.4

Port 2.4 of the microcontroller

Port 2.5 of the microcontroller

crystal oscillator ground (48 MHz)

crystal input (analog; 48 MHz)

crystal output (analog; 48 MHz)

48 MHz clock output signal

P2.5

−

V_SSX

−

XTAL1b

XTAL2b

CLK

V_DDX

−

supply crystal oscillator (48 MHz)

Port 2.6 of the microcontroller

Port 2.7 of the microcontroller

program store enable (active LOW)

supply voltage for operational ampliﬁer

operational ampliﬁer ground

P2.6

I/O

−

P2.7

−

PSEN

V_DDO

V_SSO

VOUTL

voltage output left channel

test control input (active HIGH)

asynchronous reset input of the test control block (active HIGH)

voltage output right channel

RTCB

VOUTR

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

SYMBOL

V_DDA1

I/O

DESCRIPTION

QFP64 SDIP42

−

analog supply voltage 1

analog ground 1

V_SSA1

V_ref(DA)

V_ref(AD)

V_DDA2

VINL

V_SSA2

n.c.

reference voltage output DAC

reference voltage output ADC

analog supply voltage 2

input signal left channel PGA

analog ground 2

−

not connected

n.c.

not connected

VINR

input signal right channel PGA

external access (active LOW)

negative reference input voltage ADC

address latch enable (active HIGH)

positive reference input voltage ADC

−

VRN

ALE

−

VRP

V_DDA3

XTAL2a

XTAL1a

V_SSA3

P0.0

−

supply voltage for crystal oscillator and analog PLL

crystal output (analog; ADC)

crystal input (analog; ADC)

−

I/O

crystal oscillator and analog PLL ground

Port 0.0 of the microcontroller

data Input (digital)

P0.1

−

I/O

Port 0.1 of the microcontroller

word select Input (digital)

P0.2

−

I/O

Port 0.2 of the microcontroller

bit clock Input (digital)

BCK

P0.3

−

I/O

Port 0.3 of the microcontroller

general purpose pin 2 or data output

Port 0.4 of the microcontroller

GP2/DO

P0.4

−

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

handbook, full pagewidth

GP3/WSO

GP4/BCKO

P0.5

51 VRP

50 ALE

49 VRN

48 EA

SHTCB

P0.6

47 VINR

46 n.c.

45 n.c.

44 V

D−

P0.7

D+

SSA2

43 VINL

42 V

DDI

UDA1325H

SSI

DDA2

41 V

40 V

39 V

38 V

SSE

ref(AD)

DDE

ref(DA)

SSA1

GP1/DI 13

P2.0 14

DDA1

GP5/WSI 15

P2.1 16

37 VOUTR

36 RTCB

35 TC

GP0/BCKI 17

P2.2 18

34 VOUTL

SCL 19

33 V

SSO

MGL349

Fig.2 Pin configuration (QFP64 package).

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

FUNCTIONAL DESCRIPTION

The Universal Serial Bus (USB)

Data and power is transferred via the USB over a 4-wire

cable. The signalling occurs over two wires and

point-to-point segments. The signals on each segment are

differentially driven into a cable of 90 Ω intrinsic

impedance. The differential receiver features input

sensitivity of at least 200 mV and sufficient common mode

rejection.

handbook, halfpage

SSA3

The analog front-end

XTAL1a

XTAL2a

The analog front-end is an on-chip generic USB

BCK

transceiver. It is designed to allow voltage levels up to V_DD

from standard or programmable logic to interface with the

physical layer of the USB. It is capable of receiving and

transmitting serial data at full speed (12 Mbits/s).

GP2/DO

GP3/WSO

GP4/BCKO

SHTCB

D−

DDA3

VRP

VRN

VINR

The USB processor

SSA2

The USB processor forms the interface between the

analog front-end, the ADIF, the ADAC and the

microcontroller. The USB processor consists of:

D+

VINL

DDI

DDA2

• A bit clock recovery circuit

UDA1325

SSI

ref(AD)

• The Philips Serial Interface Engine (PSIE)

• The Memory Management Unit (MMU)

• The Audio Sample Redistribution (ASR) module.

SSE

ref(DA)

DDE

SSA1

GP1/DI

GP5/WSI

GP0/BCKI

SCL

DDA1

Bit clock recovery

VOUTR

RTCB

The bit clock recovery circuit recovers the clock from the

incoming USB data stream using four times over-sampling

principle. It is able to track jitter and frequency drift

specified by the USB specification.

SDA

VOUTL

SSX

SSO

Philips Serial Interface Engine (PSIE)

XTAL1b

XTAL2b

DDO

The Philips SIE implements the full USB protocol layer.

It translates the electrical USB signals into data bytes and

control signals. Depending upon the USB device address

and the USB endpoint address, the USB data is directed

to the correct endpoint buffer. The data transfer could be

of bulk, isochronous, control or interrupt type.

DDX

MGM106

The functions of the PSIE include: synchronization pattern

recognition, parallel/serial conversion, bit

stuffing/de-stuffing, CRC checking/generation, PID

verification/generation, address recognition and

handshake evaluation/generation.

The amount of bytes/packet on all endpoints is limited by

the PSIE hardware to 8 bytes/packet, except for both

isochronous endpoints (336 bytes/packet).

Fig.3 Pin configuration (SDIP42 package).

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

Memory Management Unit (MMU) and integrated RAM The Analog-to-Digital Interface (ADIF)

The MMU and integrated RAM handle the temporary data

storage of all USB packets that are received or sent over

the bus.

The ADIF is used for sampling an analog input signal from

a microphone or line input and sending the audio samples

to the USB interface. The ADIF consists of a stereo

Programmable Gain Amplifier (PGA), a stereo

Analog-to-Digital Converter (ADC) and Decimation Filters

(DFs). The sample frequency of the ADC is determined by

the ADC clock (see Section “The clock source of the

analog-to-digital interface”). The user can also select a

digital serial input instead of an analog input. In this event

the sample frequency is determined by the continuous WS

The MMU and integrated RAM handle the differences

between data rate of the USB and the application allowing

the microcontroller to read and write USB packets at its

own speed.

The audio data is transferred via an isochronous data sink

endpoint or source endpoint and is stored directly into the

RAM. Consequently, no handshaking mechanism is used. clock with a range between 5 to 55 kHz. Digital serial input

is possible with four formats (I²S-bus, 16, 18 or 20 bits

LSB-justified).

Audio Sample Redistribution (ASR)

The ASR reads the audio samples from the MMU and

integrated RAM and distributes these samples equidistant

over a 1 ms frame period. The distributed audio samples

are translated by the digital I/O module to standard I²S-bus

format or 16, 18 or 20 bits LSB-justified I²S-bus format.

The ASR generates the bit clock output (BCKO) and the

Word Select Output signal (WSO) of the I²S output.

Programmable Gain Ampliﬁer circuit (PGA)

This circuit can be used for a microphone or line input.

The input audio signals can be amplified by seven different

gains (−3 dB, 0 dB, 3 dB, 9 dB, 15 dB, 21 dB and 27 dB).

The gain settings are given in Table 17.

The Analog-to-Digital Converter (ADC)

The 80C51 microcontroller

The stereo ADC of the UDA1325 consists of two 3rd-order

Sigma-Delta modulators. They have a modified

Ritchie-coder architecture in a differential switched

capacitor implementation. The oversampling ratio is 128.

Both ADCs can be switched off in power saving mode (left

and right separate). The ADC clock is generated by the

analog PLL or the ADC oscillator.

The microcontroller receives the control information

selected from the USB by the USB processor. It can be

used for handling the high-level USB protocols and the

user interfaces. The microcontroller does not handle the

audio stream.

The major task of the software process that is mapped

upon the microcontroller, is to control the different modules

of the UDA1325 in such a way that it behaves as a USB

device.

The Decimation Filter (DF)

The decimator filter converts the audio data from 128f_s

down to 1f_swith a word width of 8, 16 or 24 bits. This data

can be transmitted over the USB as mono or stereo in

1, 2 or 3 bytes/sample. The decimator filters are clocked

by the ADC clock.

The embedded 80C51 microcontroller is compatible with

the 80C51 family of microcontrollers described in the

80C51 family single-chip 8-bit microcontrollers of “Data

Handbook IC20”, which should be read in conjunction with

this data sheet.

The internal ROM size is 12 kbyte. The internal RAM size

is 256 byte. A Watchdog Timer is not integrated.

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

The clock source of the analog-to-digital interface

The clock source of the ADIF is the analog PLL or the ADC oscillator. The preferred clock source can be selected.

The ADC clock used for the ADC and decimation filters is obtained by dividing the clock signal coming from the analog

PLL or from the ADC oscillator by a factor Q.

Using the analog PLL the user can select 3 basic APLL clock frequencies (see Table 1).

By connecting the appropriate crystal the user can choose any clock signal between 8.192 and 14.08 MHz via the ADC

oscillator.

Table 1 The analog PLL clock output frequencies

APLL CLOCK

FCODE (1 AND 0)

FREQUENCY (MHz)

11.2896

8.1920

12.2880

11.2896

The dividing factor Q can be selected via the microcontroller. With this dividing factor Q the user can select a range of

ADC clock signals allowing several different sample frequencies (see Table 2).

Table 2 ADC clock frequencies and sample frequencies based upon using the APLL as a clock source

APLL CLOCK

DIVIDE FACTOR Q ADC CLOCK FREQUENCY (MHz) SAMPLE FREQUENCY (kHz)

FREQUENCY (MHz)

8.1920

11.2896

12.2880

4.096

2.048

1.024

0.512 (not supported)

5.6448

4 (not supported)

44.1

22.05

11.025

5.5125

2.8224

1.4112

0.7056

6.144

3.072

1.536

0.768

Table 3 ADC clock frequencies and sample frequencies based upon using the OSCAD as a clock source

OSCAD CLOCK

DIVIDE FACTOR Q ADC CLOCK FREQUENCY (MHz) SAMPLE FREQUENCY (kHz)

FREQUENCY (MHz)

(1)

f_osc

Q⁽²⁾

f_osc/(2Q)

f_osc/(256Q)⁽³⁾

Notes

1. The oscillator frequency (and therefore the crystal) of OSCAD must be between 8.192 and 14.08 MHz.

2. The Q factor can be 1, 2, 4 or 8.

3. Sample frequencies below 5 kHz and above 55 kHz are not supported.

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

The Asynchronous Digital-to-Analog Converter

(ADAC)

Table 4 Frequency domains for audio processing by the

DSP

The ADAC receives audio data from the USB processor or

from the digital I/O-bus. The ADAC is able to reconstruct

the sample clock from the rate at which the audio samples

arrive and handles the audio sound processing. After the

processing, the audio signal is upsampled, noise-shaped

and converted to analog output voltages capable of driving

a line output.

DOMAIN

SAMPLE FREQUENCY (kHz)

5 to 12

12 to 25

25 to 40

40 to 55

The upsampling ﬁlters and variable hold function

The ADAC consists of:

• A Sample Frequency Generator (SFG)

• FIFO registers

After the audio feature processing DSP two upsampling

filters and a variable hold function increase the

oversampling rate to 128f_s.

• An audio feature processing DSP

• Two digital upsampling filters and a variable hold

The noise shaper

A 3rd-order noise shaper converts the oversampled data

to a noise-shaped bitstream for the FSDAC. The in-band

quantization noise is shifted to frequencies well above the

audio band.

• A digital Noise Shaper (NS)

• A Filter Stream DAC (FSDAC) with integrated filter and

line output drivers.

The Sample Frequency Generator (SFG)

The Filter Stream DAC (FSDAC)

The SFG controls the timing signals for the asynchronous

digital-to-analog conversion. By means of a digital PLL,

the SFG automatically recovers the applied sampling

frequency and generates the accurate timing signals for

the audio feature processing DSP and the upsampling

filters.

The FSDAC is a semi-digital reconstruction filter that

converts the 1-bit data stream of the noise shaper to an

analog output voltage. The filter coefficients are

implemented as current sources and are summed at

virtual ground of the output operational amplifier. In this

way very high signal-to-noise performance and low clock

jitter sensitivity is achieved. A post filter is not needed

because of the inherent filter function of the DAC.

On-board amplifiers convert the FSDAC output current to

an output voltage signal capable of driving a line output.

The lock time of the digital PLL can be chosen (see

Table 8). While the digital PLL is not in lock, the ADAC is

muted. As soon as the digital PLL is in lock, the mute is

released as described in Section “Soft mute control”.

First-In First-Out (FIFO) registers

The FIFO registers are used to store the audio samples

temporarily coming from the USB processor or from the

digital I/O input. The use of a FIFO (in conjunction with the

SFG) is necessary to remove all jitter present on the

incoming audio signal.

The sound processing DSP

A DSP processes the sound features. The control and

mapping of the sound features is explained in Section

“Controlling the playback features of the ADAC”.

Depending on the sampling rate (f_s) the DSP knows four

frequency domains in which the treble and bass are

regulated. The domain is chosen automatically.

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

USB ENDPOINT DESCRIPTION

The UDA1325 has following six endpoints:

• USB control endpoint 0

• USB control endpoint 1

• USB status interrupt endpoint 1

• USB status interrupt endpoint 2

• Isochronous data sink endpoint

• Isochronous data source endpoint.

Table 5 Endpoint description

ENDPOINT

NUMBER

ENDPOINT

INDEX

MAX. PACKET

SIZE (BYTES)

ENDPOINT TYPE

control (default)

DIRECTION

out

control

out

interrupt

isochronous out

isochronous in

out

336

CONTROLLING THE PLAYBACK FEATURES

Controlling the playback features of the ADAC

The exchange of control information between the microcontroller and the ADAC is accomplished through a serial

hardware interface comprising the following pins:

L3_DATA: microcontroller interface data line

L3_MODE: microcontroller interface mode line

L3_CLK: microcontroller interface clock line.

See also the description of Port 3 of the 80C51 microcontroller.

Information transfer through the microcontroller bus is organized in accordance with the so-called ‘L3’ format, in which

two different modes of operation can be distinguished; address mode and data transfer mode.

The address mode is required to select a device communicating via the L3-bus and to define the destination registers

for the data transfer mode. Data transfer for the UDA1325 can only be in one direction, from microcontroller to ADAC to

program its sound processing features and other functional features.

ADDRESS MODE

The address mode is used to select a device (in this case the ADAC) for subsequent data transfer and to define the

destination registers. The address mode is characterized by L3_MODE being LOW and a burst of 8 pulses on L3_CLK,

accompanied by 8 data bits on L3_DATA. Data bits 0 and 1 indicate the type of the subsequent data transfer as shown

in Table 6.

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

Table 6 Selection of data transfer type

BIT1

BIT0

DATA TRANSFER TYPE

audio feature registers (volume left, volume right, bass and treble)

not used

control registers

not used

Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the ADAC

is 000101 (bits 7 to 2). In the event that the ADAC receives a different address, it will deselect its microcontroller interface

logic.

DATA TRANSFER MODE

The selection preformed in the address mode remains active during subsequent data transfers, until the ADAC receives

a new address command. The data transfer mode is characterized by L3_MODE being HIGH and a burst of 8 pulses on

L3_CLK, accompanied by 8 data bits. All transfers are bitwise, i.e. they are based on groups of 8 bits. Data will be stored

in the ADAC after the eight bit of a byte has been received. The principle of a multibyte transfer is illustrated in the figure

below.

halt

ndbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

MGD018

address

data byte #1

data byte #2

address

PROGRAMMING THE SOUND PROCESSING AND OTHER FEATURES

The sound processing and other feature values are stored in independent registers. The first selection of the registers is

achieved by the choice of data transfer type. This is performed in the address mode, bits 1 and 0 (see Table 6).

The second selection is performed by bit 7 and/or bit 6 of the data byte depending of the selected data transfer type.

Data transfer type ‘audio feature registers’

When the data transfer type ‘audio feature registers’ is selected 4 audio feature registers can be selected depending on

bits 7 and 6 of the data byte (see Table 7).

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Universal Serial Bus (USB) CODEC

UDA1325

Table 7 ADAC audio feature registers

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

VR5

VL5

VR4

VL4

BB4

TR4

VR3

VL3

BB3

TR3

VR2

VL2

BB2

TR2

VR1

VL1

BB1

TR1

VR0

VL0

BB0

TR0

volume right

volume left

bass

treble

The sequence for controlling the ADAC audio feature registers via the L3-bus is given in the figure below.

DATA_TRANSFER_TYPE

DEVICE ADDRESS = $5

dbook, full pagewidth

(L3_MODE = LOW)

L3_DATA

bit 0

bit 7

LEFT VOLUME; TREBLE

RIGHT VOLUME; BASS

ADDRESS

(L3_MODE = HIGH)

L3_DATA

bit 0

bit 7

L3_CLK

MGS270

Data transfer type ‘control registers’

When the data transfer type ‘control registers’ is selected 2 general control registers can be selected depending on bit 7

of the data byte (see Table 7).

The sequence for controlling the ADAC control registers via the L3-bus is given in the figure below.

DATA_TRANSFER_TYPE

DEVICE ADDRESS = $5

dbook, full pagewidth

(L3_MODE = LOW)

L3_DATA

bit 0

bit 7

ADDRESS

DATA OF THE CONTROL REGISTER

(L3_MODE = HIGH)

L3_DATA

bit 0

bit 7

L3_CLK

MGS269

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UDA1325

Table 8 ADAC general control registers

BIT

DESCRIPTION

reset ADAC

VALUE

COMMENT

Control register 0

0 = not reset

1 = reset

soft mute control

0 = not muted

1 = mutes

synchronous/asynchronous

channel manipulation

de-emphasis

0 = asynchronous

1 = synchronous

select 0

0 = L -> L, R -> R

1 = L -> R, R -> L

0 = de-emphasis off

1 = de-emphasis on

6 and 5 audio mode

00 = ﬂat mode

01 = min. mode

10 = min. mode

11 = max. mode

selecting bit

Control register 1

1 and 0 serial I²S-bus input format

00 = I²S-bus

01 = 16-bit LSB justiﬁed

10 = 18-bit LSB justiﬁed

11 = 20-bit LSB justiﬁed

3 and 2 digital PLL mode

00 = adaptive

01 = ﬁx state 1

10 = ﬁx state 2

11 = ﬁx state 3

select 00

digital PLL lock mode

0 = adaptive

1 = ﬁxed

select 1

6 and 5 digital PLL lock speed

00 = lock after 512 samples

select 00

01 = lock after 2048 samples

10 = lock after 4096 samples

11 = lock after 16348 samples

selecting bit

Soft mute control

When the mute (bit 1 of control register 0) is active for the playback channel, the value of the sample is decreased

smoothly to zero following a raised cosine curve. There are 32 coefficients used to step down the value of the data, each

one being used 32 times before stepping to the next. This amounts to a mute transition of 23 ms at f_s= 44.1 kHz. When

the mute is released, the samples are returned to the full level again following a raised cosine curve with the same

coefficients being used in reversed order.

The mute, on the master channel is synchronized to the sample clock, so that operation always takes place on complete

samples.

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

Volume control

The volume of the UDA1325 can be controlled from 0 dB down to −60 dB (in steps of 1 dB). Below −60 dB the audio

signal is muted (−∞ dB). The setting of 0 dB is always referenced to the maximum available volume setting. Independant

volume control of the left and right channel is possible (balance control).

Table 9 Volume settings right playback channel

VR5

VR4

VR3

VR2

VR1

VR0

VOLUME (dB)

...

−1

−2

−3

...

−59

−60

−∞

Table 10 Volume settings left playback channel

VL5

VL4

VL3

VL2

VL1

VL0

VOLUME (dB)

...

−1

−2

−3

...

−59

−60

−∞

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Universal Serial Bus (USB) CODEC

UDA1325

Treble control

For the playback channel, treble can be regulated in three audio modes: minimum, flat and maximum mode. In flat mode

the audio is not influenced. In minimum and maximum mode, the treble range is from 0 to 6 dB in steps of 2 dB.

The programmable treble filter is implemented digitally and has a fixed corner frequency of 3000 Hz for the minimum

mode and 1500 Hz for the maximum mode. Because of the exceptional amount of programmable gain, treble should be

used with adequate prior attenuation, using volume control.

Table 11 Treble settings

TREBLE (dB)

TR4

TR3

TR2

TR1

TR0

FLAT SET

MIN. SET

MAX. SET

...

Bass control

For the playback channel, bass can be regulated in three audio modes: minimum, flat and maximum mode. In flat mode

the audio is not influenced. In minimum mode the bass range is from 0 to approximately 14 dB in steps of 1.5 dB.

In maximum mode, the bass range is from 0 to approximately 24 dB in steps of 2 dB. The programmable bass filters are

implemented digitally and have a fixed corner frequency of 100 Hz for the minimum mode and 75 Hz for the maximum

mode. Because of the exceptional amount of programmable gain, bass should be used with adequate prior attenuation,

using volume control.

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Universal Serial Bus (USB) CODEC

UDA1325

Table 12 Bass boost settings

BASS (dB)

BB4

BB3

BB2

BB1

BB0

FLAT SET

MIN. SET

MAX. SET

...

1.1

1.7

1.1

1.7

2.4

3.6

2.4

3.6

3.7

5.4

3.7

5.4

5.2

7.4

5.2

7.4

6.8

9.4

6.8

9.4

8.4

11.3

13.3

15.2

17.3

19.2

21.2

23.2

8.4

10.2

11.9

13.7

De-emphasis

De-emphasis is controlled by bit 4 of control register 0. The de-emphasis filter can be switched on or off. The digital

de-emphasis filter is dimensioned to produce the de-emphasis frequency characteristics for the sample rate 44.1 kHz.

De-emphasis is synchronized to the sample clock, so that operation always takes place on complete samples.

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

Filter characteristics playback channel

The overall filter characteristic of the UDA1325 in flat mode is given in Fig.4 (de-emphasis off). The overall filter

characteristic of the UDA1325 includes the filter characteristics of the DSP in flat mode plus the filter characteristic of the

FSDAC (f_s= 44.1 kHz)

MGM110

−0

handbook, full pagewidth

−20

volume

(dB)

−40

−60

−80

−100

−120

−140

−160

100

f (kHz)

Fig.4 Overall filter characteristics of the UDA1325.

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

DSP extension port for enhanced playback audio processing

An external DSP can be used for adding extra sound processing features via the I²S inputs and outputs of the digital I/O

module. The UDA1325 supports the standard I²S-bus data protocol and the LSB-justified serial data input format with

word lengths of 16, 18 and 20 bits. Using the 4-pin digital I/O option the UDA1325 device acts as a master, controlling

the BCKO and WSO signals. Using the 6-pin digital I/O option GP2, GP3 and GP4 are output pins (master) and GP0,

GP1 and GP5 are input pins (slave).

The period of the WSO signal is determined by the number of samples in the 1 ms frame of the USB. This implies that

the WSO signal does not have a constant time period, but is jittery.

The characteristic timing of the I²S-bus signals is illustrated in Figs 5 and 6.

LEFT

handbook, full pagewidth

RIGHT

s;WS

h;WS

BCK(H)

BCK(L)

BCK

s;DAT

h;DAT

DATA

LSB

MSB

MGK003

Fig.5 Timing of digital I/O input signals.

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BCK

LEFT

RIGHT

>=8

DATA

MSB B2

LSB MSB B2

LSB MSB

INPUT FORMAT I S-BUS

RIGHT

LEFT

BCK

DATA

MSB B2

B15 LSB

LSB-JUSTIFIED FORMAT 16 BITS

MSB B2

B15 LSB

RIGHT

LEFT

BCK

DATA

LSB

MSB B2

B17

MSB B2

B17

LSB-JUSTIFIED FORMAT 18 BITS

LEFT

RIGHT

17 16

BCK

LSB

DATA

MSB B2

B19

MSB B2

B19

MGK002

LSB-JUSTIFIED FORMAT 20 BITS

Fig.6 Input formats.

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UDA1325

PORT DEFINITION 80C51

Port 1

Table 13 Port 1 of the 80C51 microcontroller

8 BIT PORT 1

LOW

no error

BIT

FUNCTION

ADAC_error

HIGH

COMMENT

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

error

GP1

GP2

GP3

GP4

GP5

SCL

SDA

general purpose pins

I²C-bus

Port 3

Table 14 Port 3 of the 80C51 microcontroller

8 BIT PORT 3

BIT

3.0

3.1

FUNCTION

ASR_error

LOW

HIGH

COMMENT

no error

error

suspend

PSIE_MMU_SUSPEND

no suspend

suspend input from USB interface

during normal operation or input from

restart circuit

3.2

3.3

GP0 (INT0_N)

general purpose pin

PSIE_MMU_INT (INT1_N)

interrupt input from USB interface

during normal operation or input from

restart circuit

3.4

3.5

3.6

3.7

PSIE_MMU_READY

L3_MODE

L3_CLK

L3_DATA

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UDA1325

MEMORY AND REGISTER SPACE 80C51

Overview registers

RESET

VALUE

ADDRESS

Port registers

Table 15 Register location and recommended values

after Power-on reset

80h

90h

A0h

B0h

FFh

RESET

VALUE

ADDRESS

0800h

0801h

1000h

1001h

1002h

1003h

2000h

4000h

4001h

PGA gain

ADIF control

I²C registers (SIO1 registers)

clock shop settings

reset control and APLL settings

IO selection register

power control

D8h

D9h

DAh

DBh

S1CON

S1STA

S1DAT

S1ADR

00h

ASR settings

Interrupts

data register PSIE

command register PSIE

The UDA1325 supports up to five (of maximal 7) interrupt

sources. Each interrupt source corresponds to an interrupt

vector in the CPU program memory address space:

Table 16 Special function register location

Source 0: vector 0003h external interrupt 0 (INT0_N)

Source 1: vector 000Bh Timer 0 interrupt

RESET

VALUE

ADDRESS

Source 2: vector 0013h external interrupt 1 (INT1_N)

Source 3: vector 001Bh Timer 1 interrupt

CPU registers

81h

82h

83h

D0h

E0h

F0h

Source 4: vector 0023h UART interrupt (not present)

Source 5: vector 002Bh Timer 2 interrupt (not present)

Source 6: vector 0033h I²C interrupt.

DPL

DPH

PSW

ACC

INTERRUPT ENABLE REGISTER (IE)

Each interrupt source can be individually enabled or

disabled by setting or clearing a bit in IE. This register also

contains a global interrupt enable bit (EA) which can be

cleared to disable all interrupts at once.

Interrupt registers

A8h

B8h

00h

Timer 0 and Timer 1 registers

Power On Value

88h

89h

8Ah

8Bh

8Ch

8Dh

T01CON

T01MOD

T0L

00h

EX0 (vector 0003h))

ET0 (vector 000Bh))

EX1 (vector 0013h)

ET1 (vector 001Bh)

ES0 (n.a.)

ET2 (n.a.)

ES1 (vector 0033h)

T1L

T0h

T1h

PCON registers

87h

PCON

00h

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UDA1325

Internal registers

Table 17 PGA gain registers

ADDRESS

COMMENTS

BIT

VALUE

0800h

PGA gain register

reserved

PGA input selection

0 (do not change it)

PGA gain right channel

5, 4 and 3 000 = −3 dB

001 = 0 dB

010 = 3 dB

011 = 9 dB

100 = 15 dB

101 = 21 dB

110 = 27 dB

111 = 27 dB

PGA gain left channel

2, 1 and 0 000 = −3 dB

001 = 0 dB

010 = 3 dB

011 = 9 dB

100 = 15 dB

101 = 21 dB

110 = 27 dB

111 = 27 dB

Table 18 ADIF control registers

ADDRESS

COMMENTS

BIT

VALUE

0801h

ADIF control register

reserved

number of bits per audio sample

to be transmitted to the host

6 and 5 00 = reserved

01 = 8 bits audio samples

10 = 16 bits audio samples

11 = 24 bits audio samples

0 = mono

mono/stereo selection

1 = stereo

selection audio input recording

channel

0 = digital serial audio input

1 = analog input

selection high-pass ﬁlter of

ADIF (DC-ﬁlter)

0 = high-pass ﬁlter off

1 = high-pass ﬁlter on

I²S-bus input serial input format

recording channel

1 and 0 00 = I²S-bus

01 = 16-bit LSB justiﬁed

10 = 18-bit LSB justiﬁed

11 = 20-bit LSB justiﬁed

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Table 19 Clock shop register

ADDRESS

COMMENTS

BIT

VALUE

1000h

clock shop settings

selection ADC clock source

0 = ADC clock from APLL

1 = ADC clock from OSCAD

divide factor Q

6 and 5 00 = ADC clock divided-by-1

01 = ADC clock divided-by-2

10 = ADC clock divided-by-4

11 = ADC clock divided-by-8

clock ADAC

0 = enable

1 = disable

clock 48 MHz internal

clock recovered by PSIE

ADC clock

0 = enable

1 = disable

0 = enable

1 = disable

0 = enable

1 = disable

OSCAD oscillator

0 = power on

1 = power off

Table 20 Reset control and APLL register

ADDRESS

reset control and APLL fcode (1 and 0)

settings clock frequency selection APLL

COMMENTS

BIT

VALUE

1001h

7 and 6 00 = 256 × 44.1 kHz

01 = 256 × 32 kHz

10 = 256 × 48 kHz

11 = 256 × 44.1 kHz

reserved

reset ADAC

0 = reset off

1 = reset on

reset MMU

0 = reset off

1 = reset on

reset digital I/O-interface

reset ADIF

0 = reset off

1 = reset on

0 = reset off

1 = reset on

reserved

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Table 21 I/O selection register

ADDRESS

COMMENTS

BIT

VALUE

1002h

I/O selection register

microcontroller control on

48 MHz oscillator

0 = UPC control disabled

(48 MHz oscillator is enabled)

1 = UPC control enabled

audio format

6 and 5 00 = 4-pins I²S

01 = 6-pins I²S

10 = 3-pins I²S (only input)

11 = 3-pins I²S (only input)

GP4 I/O if BIT0 = 1

GP3 I/O if BIT0 = 1

GP2 I/O if BIT0 = 1

GP1 I/O if BIT0 = 1

GP4 to GP1 function

0 = output

1 = input

0 = output

1 = input

0 = output

1 = input

0 = output

1 = input

0 = I²S usage

1 = general purpose usage

Table 22 Power control register

ADDRESS

COMMENTS

BIT

VALUE

1003h

power control register

analog modules

suspend input selection for P3.1

of the microcontroller

0 = suspend from USB interface

connected to P3.1 during

normal operation

1 = suspend from restart circuit

connected to P3.1 (e.g. after

power-down)

interrupt input selection for

P3.3 (INT1_N) of the

microcontroller

0 = interrupt from USB

interface connected to P3.3

during normal operation

1 = interrupt from restart circuit

connected to P3.3 (e.g. after

power-down)

power APLL

0 = power on

1 = power off

power FSDAC

power ADC left

power ADC right

power PGA left

power PGA right

0 = power on

1 = power off

0 = power on

1 = power off

0 = power on

1 = power off

0 = power on

1 = power off

0 = power on

1 = power off

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UDA1325

Table 23 ASR control register

ADDRESS

COMMENTS

robust word clock

BIT

VALUE

2000h

ASR control register

0 = off (not recommended)

1 = on (recommended)

6 and 5 00 = I²S-bus

01 = 16-bit LSB justiﬁed

serial I²S-bus output format

digital I/O interface

10 = 18-bit LSB justiﬁed

11 = 20-bit LSB justiﬁed

0 = mono phase inversal off

1 = mono phase inversal on

phase inversion (on right mono

output)

bits per sample modi

3 and 2 00 = reserved

01 = 8-bit audio

10 = 16-bit audio

11 = 24-bit audio

mono or stereo operation

ASR register start-up mode

0 = mono

1 = stereo

0 = stop (e.g. at alternate

setting with bandwidth equal to

zero)

1 = go

START-UP BEHAVIOUR AND POWER MANAGEMENT

Start-up of the UDA1325

After power-on (of V_DDA1), an internal Power-on reset signal becomes HIGH after a certain RC time. This RC time is

created by using the internal resistor (2 × 50 kΩ) divider for creating the reference voltage for the FSDAC in combination

with the capacitor connected externally to the V_REFDApin. The FSDAC and the internal resistor divider are supplied by

V_DDA1and V_SSA1. The RC time can be calculated using R = 25000 Ω and C = C_ref.

During 20 ms after Power-on reset becomes HIGH the UDA1325 has to initiate the internal registers. During this

initialisation, the user should prevent indicating the ‘connected’ status to the USB-host. This can be done by forcing the

DP-line LOW (i.e. via one of the GP pins).

Power Management

The total current drawn from the USB supply (for i.e. bus-powered operation of the UDA1325 application) must be less

than 500 µA in suspend mode. In order to reach that low current target, the total power dissipation of the UDA1325 can

be reduced by disabling all internal clocks and switching off all internal analog modules.

Important note: In order to make use of power reduction (Power-down mode) and be able to restart after power-down, a

number of precautions must be taken!

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Universal Serial Bus (USB) CODEC

UDA1325

AT INITIALISATION TIME

• Bit 7of the power control register (mux_ctrl_suspend) must be set to ‘1’, in order to connect the CLK_ON of the USB

processor with P3.1 of the microcontroller

• Bit 6 of the power control register (mux_ctrl_int1) must be set to ‘0’, in order to connect the PSIE_MMU_INT output pin

of the USB processor with P3.3 (INT1_N) of the microcontroller

• Bit 7of the I/O selection register must be set to ‘1’, in order to enable the power-on control of the 48 MHz crystal

oscillator automatically by the microcontroller.

IN NORMAL OPERATION MODE

In normal operation working mode, a suspend can be initiated by the falling edge of the CLK_ON output signal of the

USB processor. This falling edge comes about 2 ms after the rising edge of the PSIE_MMU_SUSPEND output signal of

the USB processor. At this moment, several actions should be taken by the microcontroller:

• All analog modules of the UDA1325 must be switched off; this can be done by setting bits 5 to 0 of the power control

• Bit 6 of the power control register (mux_ctrl_int1) must be set to ‘1’, in order to awake from power-down by the

CLK_ON signal of the USB processor

• Put all GP pins in the high or low state (depending of how they are used in the UDA1325 application)

• Put the microcontroller in Power-down mode. This can be done via the PCON register of the microcontroller. This

results in an automatically switching off the 48 MHz crystal oscillator and with that all internal clocks (if they are

enabled).

On the rising edge of the CLK_ON output signal, the 48 MHz crystal oscillator will be switched on automatically and with

that all internal clocks (if they are enabled). At the same time, a counter starts counting for 2048 clock cycles (170 µs).

This time is necessary for stabilising the 48 MHz clock of the 48 MHz crystal oscillator.

When the counter reaches its end value (after 2048 cycles), a rising edge will be detected on the P3.3 (INT1_N) of the

microcontroller. At this moment, following actions should be taken by the microcontroller:

• The Power-down mode of the microcontroller must be switched off

• Re-initialise all GP pins

• All analog modules of the UDA1325 must be switched on; this can be done by setting bits 5 to 0 of the power control

• Bit 6 of the power control register (mux_ctrl_int1) must be set to ‘0’, in order to connect the PSIE_MMU_INT output pin

of the USB processor again with P3.3 (INT1_N) of the microcontroller.

The UDA1325 is now back in its normal operation mode and can be put back in power reduction mode by the falling edge

of the CLK_ON signal of the USB processor.

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Universal Serial Bus (USB) CODEC

UDA1325

COMMAND SUMMARY

COMMAND NAME

RECIPIENT

CODING

DATA PHASE

Initialization commands

Set address/enable

Read address/enable

Set endpoint enable

Read endpoint enable

Set mode

device

D0h

D8h

F3h

write 1 byte

read 1 byte

write 1 byte

read 1 byte

write 1 byte

Data ﬂow commands

Read interrupt register

Select endpoint

device

F4h

00h

01h

read 1 byte

read 1 byte (optional)

read 1 byte

write 1 byte

read n bytes

write n bytes

none

control OUT

control IN

other endpoints

control OUT

00h + endpoint index

Get endpoint status

Set endpoint status

40h

control IN

41h

other endpoints

control OUT

40h + endpoint index

40h

control IN

41h

other endpoints

selected endpoint

40h + endpoint index

Read buffer

F0h

F1h

F2h

FAh

Write buffer

Acknowledge setup

Clear buffer

none

Validate buffer

none

General commands

Read current frame number

F5h

read 1 or 2 bytes

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Universal Serial Bus (USB) CODEC

UDA1325

COMMAND DESCRIPTIONS

Command procedure

Table 24

BIT

DESCRIPTION

Address

Enable

the value written becomes

the device address

This chapter describes the commands that can be used by

the microcontroller to control the USB processor. There

are three basic types of commands:

a ‘1’ enables this function

• Initialization commands

• Data flow commands

• General commands.

READ ADDRESS/ENABLE

Command: D0h.

Data: read 1 byte.

A command is represented by an 8 bit code. It can be

followed by one or more data write cycles or one or more

read cycles or a combination. The PSIE_MMU_READY

output connected to Port 3.4 of the microcontroller

indicates that the previous action (command write, data

read or data write) has completed. A new action can only

be initiated if PSIE_MMU_READY is TRUE. The data is

valid from the moment PSIE_MMU_READY becomes

TRUE.

The read address/enable command is used to read the

USB assigned address and the enable bit of the device.

The format of the data phase is the same as for the set

address/enable command.

SET ENDPOINT ENABLE

Command: D8h.

Data: write 1 byte.

The PSIE contains a number of interrupt registers, one for

each endpoint. Every time a transition occurs, the interrupt

flag for the involved endpoint is set. The PSIE_MMU_INT

connected to Port 3.3 is an OR function of all interrupt

registers.

The set endpoint enable command is used to set the

enable bits for the non default endpoints.

Power On Value

Initialization commands

Enable

Initialization commands are used during the enumeration

process of the USB network. They are used to set the USB

assigned address, enable endpoints and select the

configuration of the device.

Reserved

If the enable bit is ‘1’, the non default endpoints are

enabled, if ‘0’, the non default endpoints are disabled.

The function then only responds to the default control

endpoint.

SET ADDRESS/ENABLE

Command: D0h.

After bus reset, the enable bit is set to ‘0’.

Data: write 1 byte.

READ ENDPOINT ENABLE

Command: D8h.

The set address/enable command is used to set the USB

assigned address and enable the function. The device

always powers up disabled and should be enabled after a

bus reset.

Data: read 1 byte.

The read endpoint enable command is used to read the

enable bit for the non default endpoints of the function.

The format of the data phase is the same as for the set

endpoint enable command.

Power On Value

Address

Enable

SET MODE

Command: F3h.

Data: write 1 byte.

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

An interrupt is also generated after a bus reset. When the

interrupt register consists of all zeros, and an interrupt was

generated, there was a bus reset. The interrupt is cleared

when the interrupt register is read.

Reset value

Bus Reset

IsoOut

IsoIn

IntIsoOut

IntIsoIn

Power On Value

ErrorDebugMode

AlwaysPLLClock

Reserved

Control OUT

Control IN

Endpoint 1 OUT

Endpoint 1 IN

Endpoint 2 IN

Endpoint 3 IN

Endpoint 4 OUT

Endpoint 5 IN

Reset value: gives the value of the bits after Power-on

reset. Bus reset: a ‘F’ indicates that the value of the bit is

not changed during a bus reset. a ‘T’ indicates that during

a bus reset, the bit is reset to its reset value.

SELECT ENDPOINT

Table 25

Command: 00h + endpoint index.

Data: optional read 1 byte.

BIT

DESCRIPTION

IsoOut

IsoIn

ISO out endpoint can be

used

The select endpoint command initializes an internal

pointer to the start of the selected buffer. Optionally, this

command can be followed by a data read. Bit 0 is low if the

buffer is empty and high if the buffer is full. There is one

command for every endpoint.

ISO in endpoint can be

used

IntIsoOut

IntIsoIn

allow interrupt from ISO

out endpoint

allow interrupt from ISO in

endpoint

Power On Value

ErrorDebugMode

AlwaysPLLClock

Setting chip in debug

mode

Full/Empty

Reserved

the PLL clock must keep

on running

GET ENDPOINT STATUS

Data ﬂow commands

Command: 40h + endpoint index.

Data: read 1 byte.

Data flow commands are used to manage the data

transmission between the USB endpoints and the host.

Much of the data flow is initiated via the interrupt to the

microcontroller. The microcontroller uses these

commands to access the endpoint buffers and determine

whether the endpoint buffers have valid data.

The get endpoint status command is followed by one data

read that returns the status of the last transaction of the

selected endpoint. This command also resets the

corresponding interrupt flag in the interrupt register, and

clears the status, indicating that it was read. There is one

command for every endpoint.

READ INTERRUPT REGISTER

Command: F4h.

Data: read 1 byte.

Power On Value

The read interrupt register command returns the value of

the interrupt register. Every time a packet is received or

transmitted, an interrupt will be generated and a flag

specific to the physical endpoint will be set in the interrupt

flag.

Data Receive/Transmit

Error Code

Setup Packet

Data 0/1 Packet

Previous Status not Read

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

Table 26 Error codes

SET ENDPOINT STATUS

Command: 40h + endpoint index.

Data: write 1 byte.

ERROR

RESULT

CODE

0000

0001

no error

This command is used to stall or unstall an endpoint. Only

the least significant bit has a meaning. When the stalled bit

is equal to 1, the endpoint is stalled, when equal to 0, the

endpoint is unstalled. There is one command for every

endpoint.

PID encoding error; bits 7 to 4 in the PID

token are not the inversion of bits 3 to 0

0010

0011

PID unknown; PID encoding is valid, but PID

does not exist

unexpected packet; packet is not of the type

expected (token, data or acknowledge), or

SETUP token received on non-control

endpoint

A stalled control endpoint is automatically unstalled when

it receives a SETUP token, regardless of the contents of

the packet. If the endpoint should stay in stalled state, the

microcontroller should restall it.

0100

0101

0110

0111

1000

1001

1010

token CRC error

data CRC error

When a stalled endpoint is unstalled, it is also re-initialized.

This means that its buffer is flushed and the next DATA

PID that will be sent or expected (depending on the

direction of the endpoint) is DATA0.

time out error

babble error

unexpected end-of-packet

sent or received NAK

sent stall, a token was received, but the

endpoint was stalled

Power On Value

Stalled

Reserved

1011

overﬂow error, the received data packet was

larger then the buffer size of the selected

endpoint

1100

1101

1110

1111

sent empty packet (ISO only)

bitstuff error

READ BUFFER

Command: F0h.

Data: read n bytes (max. 10).

error in sync

wrong data PID

The read buffer command is followed by a number of data

reads, which returns the contents of the selected endpoint

data buffer. After each read, the internal buffer pointer is

incremented by 1.

Table 27

BIT

DESCRIPTION

Data receive/transmit

a ‘1’ indicates data has

been received or

transmitted successfully

The buffer pointer is not reset to the buffer start by the read

buffer command. This means that reading a buffer can be

interrupted by any other command (except for select

endpoint).

Error code

see Table 26

Setup packet

a ‘1’ indicates the last

received packet had a

SETUP token (this will

always read ‘0’ for IN

buffers)

Data 0/1 packet

a ‘1’ indicates the last

received packet had a

DATA 1 PID

Previous status not read

a ‘1’ indicates a second

event occurred before the

previous status was read

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

The data in the buffer are organized as follows:

Byte 0: transfer successful, number of data bytes (MSB)

Byte 1: number of data bytes (LSB)

Byte 2: data byte 0

acknowledged explicitly that it has seen the SETUP

packet.

If the microcontroller is reading the data from a SETUP

packet, and a new SETUP packet arrives, the device must

accept this new SETUP packet. So the data, currently

being read by the microcontroller, is overwritten with the

new packet. On the arrival of the new packet, the

commands validate buffer and clear buffer are disabled.

If the microcontroller has finished reading the data from

the buffer, it will try to clear the buffer. The device will

ignore this command, so the new SETUP packet in the

buffer is not cleared. The microcontroller will now detect

the interrupt of the new SETUP packet and will start

reading the new data in the buffer.

Byte 3: data byte 1

Byte 4: data byte 2

Byte 5: data byte 3

Byte 6: data byte 4

Byte 7: data byte 5

Byte 8: data byte 6

Byte 9: data byte 7.

Bytes 0 and 1 indicate the number of bytes in the buffer.

Byte 0 is the Most Significant Byte (MSB). Byte 1 is the

Least Significant Byte (LSB). Only bits 1 and 0 of byte 0

are used in the number of bytes indication.

A SETUP token can be followed by an IN token. After the

SETUP token, the microcontroller will start filling the IN

buffer. A SETUP token will clear the IN buffer. This avoids

the following problem: after a SETUP token, the

microcontroller fills the IN buffer. If the SETUP token is

followed by a SETUP token and shortly followed by an IN

token, the device will send the contents of the IN buffer to

the host. The IN buffer was filled after the first SETUP

token. That is why after a SETUP token the IN buffer is

cleared.

Bit 7 of byte 0 indicates if the transaction was successful

(bit 7 is ‘1’ if the transaction was successful). Bits 6 to 2 of

byte 0 are reserved.

WRITE BUFFER

Command: F0h.

If the microcontroller is still filling the buffer when the

second SETUP token arrives, the SETUP token will clear

the IN buffer. If the microcontroller has filled the IN buffer,

it will validate the buffer. So clearing the IN buffer on

receiving a SETUP token is not enough.

Data: write n bytes (max. 10).

The write buffer command is followed by a number of data

writes, which load the endpoint buffer. After each write, the

internal buffer pointer is incremented by 1.

If a SETUP token is received, the device will also disable

the validate buffer command for the IN buffer. If the

microcontroller needs to fill the buffer after a SETUP token,

the command acknowledge setup command must be sent

to enable the validate buffer command.

The buffer pointer is not reset to the buffer start by the write

buffer command. This means that writing a buffer can be

interrupted by any other command (except for select

endpoint).

The data must be organized in the same way as described

in the read buffer command. Bits 7 to 2 of byte 0 are

reserved and must be filled with zeros.

CLEAR BUFFER

Command: F2h.

Data: none.

ACKNOWLEDGE SETUP

Command: F1h.

Data: none.

When a packet is received completely, an internal

endpoint buffer full flag is set. All subsequent packets will

be refused by returning a NACK to the host. When the

microcontroller has read the data, it should free the buffer

by the clear buffer command. When the buffer is cleared,

new packets will be accepted.

The arrival of a SETUP packet flushes the IN buffer and

disables the validate buffer and clear buffer commands for

both IN and OUT endpoints.

The microcontroller needs to re-enable these commands

by the acknowledge setup command. This ensures that

the last SETUP packet stays in the buffer and no packet

can be sent back to the host until the microcontroller has

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

VALIDATE BUFFER

Command: FAh.

Data: none.

S1CON register

The CPU can read from and write to this 8-bit SFR.

Two bits are effected by the SIO1 hardware: the SI bit is

set when a serial interrupt is requested, and the STO bit is

cleared when a STOP condition is present on the I²C-bus.

The STO bit is also cleared when ENS1 = ‘0’. Reset

initializes S1CON to 00h.

When the microcontroller has written data into an IN buffer,

it should set the buffer full flag by the validate buffer

command. This indicates that the data in the buffer are

valid and can be sent to the host when the next IN token is

received.

Power On Value

General commands

READ CURRENT FRAME NUMBER

Command: F5h.

CR0

CR1

STO

STA

ENS1

CR2

Data: read 1 or 2 bytes.

This command is followed by one or two data reads and

returns the frame number of the last successfully received

SOF. The frame number is eleven bits wide. The frame

number is returned least significant byte first. In case the

user is only interested in the lower 8 bits of the frame

number only the first byte needs to be read.

CR2, 1 AND 0 - THE CLOCK RATE BITS

These three bits determine the serial clock frequency

when SIO1 is in a master mode.

The various serial rates are shown in Table 28.

I²C MASTER/SLAVE INTERFACE

Table 28 Serial clock rates (SCL line)

The I²C module implements a master/slave I²C-bus

interface with integrated shift register, shift timing

generation and slave address recognition. It is compliant

to the I²C-bus specification IC20/Jan92. I²C standard

mode (100 kHz SCL) and fast mode (400 kHz) are

supported. Low speed mode and extended 10 bit

addressing are unsupported.

I²C BIT FREQUENCY

CR2

CR1

CR0

(kHz)

1200

600

400

300

150

Characteristics of the I²C-bus

100

The I²C-bus is for 2-way, 2-line communication between

different ICs or modules. The two lines are a serial data

line (SDA) and a Serial Clock Line (SCL). Both lines must

be connected to V_DDEvia a pull-up resistor.

3.9 ... 501

The timing definition of the I²C-bus is given in Fig.7.

When the CR bits are ‘111’, the maximum bit rate for the

data transfer will be derived from the Timer 1 overflow rate

divided by 2 (i.e. every time the Timer 1 overflows, the

SCL signal will toggle).

Programmer’s view

For a detailed description of the I²C-bus protocol refer to

Philips Integrated Circuits Data Handbook IC20, 8XC552.

The programmer’s view of the I²C library function is -with

one exception- identical to that of the 8XC552

microcontroller. Only the bit rate frequency selection in

S1CON and the handling of the Timer 1 overflow

information deviates to accommodate 400 kHz operation.

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SDA

BUF

LOW

HD;STA

SCL

SU;STO

HD;STA

SU;STA

HD;DAT

HIGH

SU;DAT

MBC611

Fig.7 Definition of timing of the I²C-bus.

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

All digital I/Os

V_I/O

I_O

DC input/output voltage range

output current

−0.5

−

V_DDE

V_DDE= 5.0 V

Temperature values

T_j

junction temperature

−

125

+150

°C

T_stg

T_amb

storage temperature

−55

operating ambient temperature

Electrostatic handling

V_es

electrostatic handling

note 1

note 2

−3000

−300

−

+3000

+300

Notes

1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

2. Equivalent to discharging a 200 pF capacitor through a 2.5 µH series conductor.

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

R_th(j-a)

thermal resistance from junction to ambient

UDA1325PS

UDA1325H

in free air

K/W

RECOMMENDED OPERATING CONDITIONS

SYMBOL

V_DDE

V_DD

PARAMETER

supply voltage periphery (I/O)

MIN.

TYP.

MAX.

UNIT

4.75

3.0

5.0

3.3

5.25

3.6

supply voltage (core)

DC input voltage range

for D+ and D−

for VINL and VINR

for digital I/Os

V_I

0.0

−

V_DD

−

0.5V_DD

0.0

−

V_DDE

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

DC CHARACTERISTICS

V_DDE= 5.0 V; V_DD= 3.3 V; T_amb= 25 °C; f_osc= 48 MHz; f_s= 44.1 kHz; unless otherwise speciﬁed.

SYMBOL

Supplies

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

V_DDE

V_DDI

V_DDA1

V_DDA2

V_DDA3

V_DDO

V_DDX

I_DDE

digital supply voltage periphery

digital supply voltage core

analog supply voltage 1

4.75

5.0

5.25

3.0

−

3.3

3.7

39.0

3.6

8.0

0.9

3.0

1.2

200

1.2

3.6

−

9.0⁽²⁾

analog supply voltage 2

analog supply voltage 3

operational ampliﬁer supply voltage

crystal oscillator supply voltage

digital supply current periphery

digital supply current core

analog supply current 1

note 1

I_DDI

I_DDA1

I_DDA2

I_DDA3

I_DDO

I_DDX

analog supply current 2

analog supply current 3

operational ampliﬁer supply current

crystal oscillator supply current

total power dissipation

−

13.0⁽³⁾

−

P_tot

P_ps

total power dissipation in power

saving mode

note 4

−

Inputs/outputs D+ and D−

V_I

static DC input voltage

−0.5

2.8

−

V_DDI

3.6

V_O(H)

static DC output voltage HIGH

R_L= 15 kΩ

connected to GND

V_O(L)

I_LO

static DC output voltage LOW

R_L= 1.5 kΩ

connected to V_DD

−

0.3

high impedance data line output

leakage current

µA

V_I(diff)

differential input sensitivity

0.2

0.8

−

2.5

2.0

V_CM(diff)

V_SE(R)(th)

differential common mode range

single-ended receiver threshold

voltage

C_IN

transceiver input capacitance

pin to GND

−

Digital input pins

V_IL

V_IH

I_LI

LOW-level input voltage

−

0.3V_DDE

HIGH-level input voltage

input leakage current

input capacitance

0.7V_DDE

V_DDE

−

µA

C_I

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

PGA and ADC

V_ref(AD)

reference voltage PGA and ADC

−

0.5V_DDA2

V_DDA2

−

V_{ref(ADC)(pos)}positive reference voltage of the

ADC

V_{ref(ADC)(neg)}negative reference voltage of the

ADC

−

0.0

−

V_I(PGA)

DC input voltage VINL and VINR of

the PGA

0.5V_DDA2

12.5

R_I(PGA)

DC input resistance at VINL and

VINR of the PGA

kΩ

Filter stream DAC

V_ref(DA)reference voltage DAC

V_O(CM)

−

0.5V_DDA1

−

Ω

common mode output voltage

R_O(VOUT)

output resistance at VOUTL and

VOUTR

R_O(L)

C_O(L)

output load resistance

output load capacitance

2.0

−

kΩ

−

Notes

1. This value depends strongly on the application. The specified value is the typical value obtained using the application

diagram as illustrated in Fig.8.

2. At start-up of the OSCAD oscillator.

3. At start-up of the OSC48 oscillator.

4. Exclusive the IDDE current which depends on the components connected to the I/O pins.

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

AC CHARACTERISTICS

V_DDE= 5.0 V; V_DDI= 3.3 V; T_amb= 25 °C; f_osc= 48 MHz; f_s= 44.1 kHz; unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Driver characteristics D+ and D− (full-speed mode)

f_o(s)

t_r

audio sample output frequency

rise time

−

kHz

C_L= 50 pF

t_f

fall time

t_rf(m)

V_cr

rise/fall time matching (t_r/t_f)

output signal crossover voltage

driver output resistance

110

2.0

1.3

R_o(drive)

steady-state drive 28

Ω

Data source timings D+ and D− (full-speed mode)

f_i(s)

audio sample input frequency

full speed data rate

frame interval

−

kHz

Mbits/s

f_fs(D)

t_fr(D)

t_J1(diff)

11.97

12.00

1.0000

0.0

12.03

1.0005

+3.5

0.9995

source differential jitter to next

transition

−3.5

t_J2(diff)

source differential jitter for paired

transitions

−4.0

0.0

+4.0

t_W(EOP)

t_EOP(diff)

source end of packet width

160

−

175

differential to end of packet

transition skew

−2.0

+5.0

t_JR1

receiver data jitter tolerance to next

transition

−18.5

−9.0

0.0

−

+18.5

+9.0

−

t_JR2

receiver data jitter tolerance for

paired transitions

t_EOPR1

t_EOPR2

end of packet width at receiver

must reject as end of packet

end of packet width at receiver

must accept as end of packet

−

Serial input/output data timing

f_s

system clock frequency

−

MHz

kHz

f_i(WS)

t_r

word selection input frequency

rise time

−

t_f

fall time

t_BCK(H)

t_BCK(L)

t_s;DAT

t_h;DAT

t_s;WS

t_h;WS

bit clock HIGH time

bit clock LOW time

data set-up time

data hold time

word selection set-up time

word selection hold time

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

SDA and SCL lines for 100 kHz I²C devices

f_SCL

t_BUF

SCL clock frequency

−

100

kHz

bus free time between a STOP and

START condition

4.7

−

µs

t_HD;STA

hold time (repeated) START

condition

4.0

−

µs

t_LOW

LOW period of the SCL clock

HIGH period of the SCL clock

4.7

4.0

4.7

−

µs

t_HIGH

t_SU;STA

set-up time for a repeated START

condition

t_SU;STO

t_HD;DAT

t_SU;DAT

t_r

set-up time for STOP condition

data hold time

4.0

5.0

250

−

1000

µs

data set-up time

rise time of both SDA and SCL

signals

t_f

fall time of both SDA and SCL

signals

−

300

400

C_L(bus)

capacitive load for each bus line

Oscillator 1 (system clock)

f_osc

oscillator frequency

−

MHz

duty factor

g_m

transconductance

12.8

0.6

4.5

4.1

3.7

22.1

1.1

4.8

4.6

7.6

30.2

2.3

5.2

5.0

13.0

kΩ

R_o

output resistance

C_i(XTAL1a)

C_i(XTAL2a)

I_start

parasitic input capacitance XTAL1a

parasitic input capacitance XTAL2a

start-up current

Oscillator 2 (for ADC clock)

f_osc

oscillator frequency

8.192

−

14.08

−

MHz

duty cycle

g_m

transconductance

8.1

1.3

5.0

4.1

2.4

13.6

2.0

5.4

4.6

5.0

18.1

4.0

5.7

5.0

8.4

mA/V

kΩ

R_o

output resistance

C_i(XTAL1b)

C_i(XTAL2b)

I_start

parasitic input capacitance XTAL1b

parasitic input capacitance XTAL2b

start-up current

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

SYMBOL

Analog PLL (for ADC clock)

f_clk(PLL)PLL clock frequency

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

8.1920

11.2896

12.2880 MHz

duty factor

−

t_strt(PO)

start-up time after power-on

−

Power-on reset

(2)

t_su(PO)

power-on set-up-time

note 1

25C_ref

−

PGA and ADC

V_i(FS)(rms)

full-scale input voltage (RMS value) PGA gain = −3 dB

PGA gain = 0 dB

−

1414⁽³⁾

1000

708

355

178

−

PGA gain = 3 dB

PGA gain = 9 dB

PGA gain = 15 dB

PGA gain = 21 dB

PGA gain = 27 dB

C_i(PGA)

input capacitance of the PGA

−

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

f_s= 44.1 kHz at

input signal of

1 kHz; PGA

gain = 0 dB;

note 4

V_i(0 dB)

1.0 V (RMS)

−

0.640

−

−85

0.0056

−30

3.2

−80

0.01

−20

10.0

−

7.04

−

V_i(−60 dB)

S/N

α_ct

f_s

signal to noise ratio

V_i= 0.0 V

dBA

crosstalk between channels

sample frequency (128f_s)

digital output level

PGA gain = 0 dB

100

−

−2.0

MHz

dBFS

PGA gain = 0 dB,

V_i= 1 V (RMS)

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Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Filter stream DAC

RES

resolution

−

0.66

−

bits

V_o(FS)(rms)

full-scale output voltage

(RMS value)

V_DD= 3.3 V

−

SVRR

supply voltage ripple rejection at

f_ripple= 1 kHz

V_ripple(p-p)= 0.1 V

−

_DDAand V_DDO

∆V_o

α_ct

channel unbalance

maximum volume

−

0.03

−

crosstalk between channels

R_L= 5 kΩ

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

f_s= 44.1 kHz;

R_L= 5 kΩ; note 5

at input signal of

1 kHz (0 dB)

−

−90

0.0032

−30

3.2

−80

0.01

−20

at input signal of

1 kHz (−60 dB)

S/N

signal-to-noise ratio at bipolar zero A-weighting at

code 0000H

−

Notes

1. Strongly depends on the external decoupling capacitor connected to V_ref(DA)

2. C_refin µF.

3. Although a level of 1.414 V (RMS) would be required to optimal drive the ADC in this gain setting, this level can not

be used. Due to the 3.3 V supply voltage input, signals of 1.17 V (RMS) and higher will result in clipping.

4. Measured with the APLL as ADC clock source.

5. Measured with I²S-bus input as digital source.

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Philips Semiconductors

Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

APPLICATION INFORMATION

handbook, full pagewidth

R35

R27

1 Ω

C34

C32

47 µF

(16 V)

C38

C21

100 nF

(63 V)

100 nF

(63 V)

DDA2

SSA1

DDA1

SSA2

GP0/BCKI

GP5/WSI

GP1/DI

BCKI

digital

input

WSI

playback

BCK

digital

input

recording

R48

1.5 kΩ

USB

D−

22 Ω

R16

D+

UDA1325H

22 Ω

C16

10 nF

(50 V)

C18

22 pF

(63 V)

C17

22 pF

(63 V)

C15

10 nF

(50 V)

VINR

VINL

analog

input

recording

47 µF (16 V)

C22

47 µF (16 V)

C44

XTAL2b

1.5 µH

10 nF (63 V)

C38

12 pF (63 V)

48 MHz

XTAL1b

C37

12 pF (63 V)

XTAL2a

XTAL1a

ADC XTAL

18 pF

(50 V)

18 pF

(50 V)

A(ext)

BLM32A07

SSE

SSI

C25

DDI

DDE

C26

BLM32A07

100 nF

(63 V)

100 nF

(63 V)

D(ext)

BLM32A07

C24

C27

C47

C46

C45

100 µF

(16 V)

100 µF

(16 V)

100 µF

(16 V)

100 nF

(63 V)

100 nF

(63 V)

R17

1 Ω

R25

1 Ω

GND

MGM760

Fig.8 Application diagram UDA1325H (continued in Fig.9).

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Philips Semiconductors

Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

handbook, full pagewidth

R10

1 Ω

C11

47 µF

100 nF

(63 V)

(16 V)

C19

100 nF

(63 V)

VRN

VRP

SSA3

DDA3

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

74HCT373D

ALE

A10

A11

A12

A13

EEPM27128

100 nF

(50 V)

C24

GND

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

PSEN

100 nF

(50 V)

C25

GND

PGM

R28

4.7 kΩ

R20

(internal ROM)

(external ROM)

1 Ω

PTC

SCL

SDA

C36

100 nF

(63 V)

UDA1325H

PCF85116-3

R38

10 kΩ

R39

10 kΩ

SDA

SCL

(I²C-bus)

ref(DA)

ref(AD)

C29

100 nF

(63 V)

C41

47 µF

(16 V)

C28

100 nF

(63 V)

C31

47 µF

(16 V)

C35

VOUTR

VOUTL

47 µF (16 V)

analog

output

playback

C48

47 µF (16 V)

GP4/BCKO

GP3/WSO

GP2/DO

BCKO

WSO

digital

output

playback

RTCB

SHTCB

DDX

SSO

C33

DDO

SSX

C28

100 nF

(63 V)

100 nF

(63 V)

L13

BLM32A07

C39

C18

47 µF

100 nF

(63 V)

R43

1 Ω

R26

1 Ω

(16 V)

MGM761

Fig.9 Application diagram UDA1325H (continued from Fig.8).

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R35

1 Ω

R27

1 Ω

R10

1 Ω

C34

C32

C11

47 µF

100 nF

(63 V)

(16 V)

C38

C21

C19

R20 1 Ω

100 nF

(63 V)

100 nF

(63 V)

100 nF

(63 V)

DDA2

VRN

VRP

SSA1

DDA1

SSA2

SSA3

DDA3

C36

100 nF

(63 V)

PTC

SCL

SDA

GP0/BCKI

GP5/WSI

GP1/DI

BCKI

WSI

digital

input

playback

PCF85116-3

R38

10 kΩ

R39

10 kΩ

SDA

SCL

BCK

(I²C-bus)

BCK

digital

input

recording

ref(DA)

ref(AD)

C29

100 nF

(63 V)

C41

47 µF

(16 V)

C28

100 nF

(63 V)

C31

47 µF

(16 V)

USB

R48

1.5 kΩ

D−

C35

22 Ω

R16

VOUTR

VOUTL

D+

47 µF (16 V)

analog

output

playback

22 Ω

C16

10 nF

(50 V)

C18

22 pF

(63 V)

C17

22 pF

(63 V)

C15

C48

10 nF

(50 V)

UDA1325PS

47 µF (16 V)

VINR

VINL

analog

input

recording

47 µF (16 V)

C22

GP4/BCKO

GP3/WSO

GP2/DO

BCKO

WSO

47 µF (16 V)

digital

output

playback

1.5 µH

C44

XTAL2b

10 nF (63 V)

C38

12 pF (63 V)

C37

48 MHz

XTAL1b

RTCB

12 pF (63 V)

SHTCB

XTAL2a

XTAL1a

ADC XTAL

18 pF

(50 V)

18 pF

(50 V)

DDX

SSI

C25

DDI

SSE

C26

DDE

SSO

C33

DDO

SSX

C28

A(ext)

BLM32A07

100 nF

(63 V)

100 nF

(63 V)

100 nF

(63 V)

100 nF

(63 V)

BLM32A07

L13

BLM32A07

C39

C18

C24

C27

D(ext)

BLM32A07

C47

100 µF

(16 V)

C46

100 µF

(16 V)

C45

47 µF

100 nF

(63 V)

100 nF

(63 V)

100 nF

(63 V)

R43

1 Ω

R26

1 Ω

R17

1 Ω

R25

1 Ω

100 µF

(16 V)

GND

MGS271

Fig.10 Application diagram UDA1325PS.

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Philips Semiconductors

Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

PACKAGE OUTLINES

SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)

SOT270-1

(e )

w M

pin 1 index

10 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

max.

(1)

UNIT

min.

max.

1.3

0.8

0.53

0.40

0.32

0.23

38.9

38.4

14.0

13.7

3.2

2.9

15.80

15.24

17.15

15.90

5.08

0.51

4.0

1.778

15.24

0.18

1.73

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

90-02-13

95-02-04

SOT270-1

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Philips Semiconductors

Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

SOT319-2

(A )

w M

pin 1 index

detail X

w M

10 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max.

7^o

0^o

0.25 2.90

0.05 2.65

0.50 0.25 20.1 14.1

0.35 0.14 19.9 13.9

24.2 18.2

23.6 17.6

1.0

0.6

1.2

0.8

1.2

0.8

3.20

0.25

1.95

0.2

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

95-02-04

97-08-01

SOT319-2

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Philips Semiconductors

Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 230 °C.

SOLDERING

Introduction

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

WAVE SOLDERING

Conventional single wave soldering is not recommended

for surface mount devices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when

through-hole and surface mount components are mixed on

one printed-circuit board. However, wave soldering is not

always suitable for surface mount ICs, or for printed-circuit

boards with high population densities. In these situations

reflow soldering is often used.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal results:

• Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

Through-hole mount packages

SOLDERING BY DIPPING OR BY SOLDER WAVE

• For packages with leads on two sides and a pitch (e):

The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact

with the joints for more than 5 seconds. The total contact

time of successive solder waves must not exceed

5 seconds.

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

The device may be mounted up to the seating plane, but

the temperature of the plastic body must not exceed the

specified maximum storage temperature (T_stg(max)). If the

printed-circuit board has been pre-heated, forced cooling

may be necessary immediately after soldering to keep the

temperature within the permissible limit.

The footprint must incorporate solder thieves at the

downstream end.

• For packages with leads on four sides, the footprint must

be placed at a 45° angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

MANUAL SOLDERING

Apply the soldering iron (24 V or less) to the lead(s) of the

package, either below the seating plane or not more than

2 mm above it. If the temperature of the soldering iron bit

is less than 300 °C it may remain in contact for up to

10 seconds. If the bit temperature is between

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

300 and 400 °C, contact may be up to 5 seconds.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Surface mount packages

REFLOW SOLDERING

MANUAL SOLDERING

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

Several methods exist for reflowing; for example,

infrared/convection heating in a conveyor type oven.

Throughput times (preheating, soldering and cooling) vary

between 100 and 200 seconds depending on heating

method.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

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Philips Semiconductors

Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

Suitability of IC packages for wave, reﬂow and dipping soldering methods

SOLDERING METHOD

WAVE

REFLOW⁽¹⁾DIPPING

suitable⁽²⁾

not suitable

HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable⁽³⁾

MOUNTING

PACKAGE

Through-hole mount DBS, DIP, HDIP, SDIP, SIL

−

suitable

Surface mount

BGA, SQFP

suitable

−

PLCC⁽⁴⁾, SO, SOJ

LQFP, QFP, TQFP

SSOP, TSSOP, VSO

suitable

not recommended⁽⁴⁾⁽⁵⁾

not recommended⁽⁶⁾

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

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Philips Semiconductors

Preliminary speciﬁcation

Universal Serial Bus (USB) CODEC

UDA1325

DEFINITIONS

Data sheet status

Objective speciﬁcation

Preliminary speciﬁcation

Product speciﬁcation

This data sheet contains target or goal speciﬁcations for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

PURCHASE OF PHILIPS I²C COMPONENTS

Purchase of Philips I²C components conveys a license under the Philips’ I²C patent to use the

components in the I²C system provided the system conforms to the I²C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

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Philips Semiconductors – a worldwide company

Argentina: see South America

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +31 40 27 82785, Fax. +31 40 27 88399

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

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Tel. +64 9 849 4160, Fax. +64 9 849 7811

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210

Norway: Box 1, Manglerud 0612, OSLO,

Tel. +47 22 74 8000, Fax. +47 22 74 8341

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773

Pakistan: see Singapore

Belgium: see The Netherlands

Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,

Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,

Tel. +359 2 68 9211, Fax. +359 2 68 9102

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,

Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,

Tel. +1 800 234 7381, Fax. +1 800 943 0087

Romania: see Italy

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,

72 Tat Chee Avenue, Kowloon Tong, HONG KONG,

Tel. +852 2319 7888, Fax. +852 2319 7700

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Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Colombia: see South America

Tel. +65 350 2538, Fax. +65 251 6500

Czech Republic: see Austria

Slovakia: see Austria

Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Slovenia: see Italy

Tel. +45 33 29 3333, Fax. +45 33 29 3905

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,

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Tel. +55 11 821 2333, Fax. +55 11 821 2382

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Tel. +49 40 2353 60, Fax. +49 40 2353 6300

Spain: Balmes 22, 08007 BARCELONA,

Tel. +34 93 301 6312, Fax. +34 93 301 4107

Hungary: see Austria

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,

Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

India: Philips INDIA Ltd, Band Box Building, 2nd floor,

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Tel. +91 22 493 8541, Fax. +91 22 493 0966

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. +41 1 488 2741 Fax. +41 1 488 3263

Indonesia: PT Philips Development Corporation, Semiconductors Division,

Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,

Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,

TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. +353 1 7640 000, Fax. +353 1 7640 200

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,

Tel. +66 2 745 4090, Fax. +66 2 398 0793

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,

ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. +39 02 67 52 2531, Fax. +39 02 67 52 2557

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,

252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,

TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,

MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. +82 2 709 1412, Fax. +82 2 709 1415

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,

Tel. +1 800 234 7381, Fax. +1 800 943 0087

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. +60 3 750 5214, Fax. +60 3 757 4880

Uruguay: see South America

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Vietnam: see Singapore

Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Middle East: see Italy

Tel. +381 11 62 5344, Fax.+381 11 63 5777

For all other countries apply to: Philips Semiconductors,

Internet: http://www.semiconductors.philips.com

International Marketing & Sales Communications, Building BE-p, P.O. Box 218,

5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

SCA64

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

545002/750/01/pp52

Date of release: 1999 May 10

Document order number: 9397 750 02805

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