Maxim Switch MAX4888A User Manual

19-0770; Rev 0; 4/07  
5.0Gbps PCI Express Passive Switches  
/MX489A  
General Description  
Features  
The MAX4888A/MAX4889A high-speed passive switches  
route PCI Express® (PCIe) data between two possible  
destinations. The MAX4888A is a quad single-pole/dou-  
ble-throw (4 x SPDT) switch ideally suited for switching  
two half lanes of PCIe data between two destinations. The  
MAX4889A is an octal single-pole/double-throw (8 x  
SPDT) switch ideal for switching four half lanes of PCIe  
data between four destinations. The MAX4888A/  
MAX4889A feature a single digital control input (SEL) to  
switch signal paths.  
o Single 1.65V to 3.6V Power-Supply Voltage  
o Low Same-Pair Skew of 7ps  
o Low 120µA (Max) Quiescent Current  
o Supports PCIe Gen I and Gen || Data Rates  
o Flow-Through Pin Configuration for Ease of  
Layout  
o Industry-Compatible Pinout  
o Lead-Free Packaging  
The MAX4888A/MAX4889A are fully specified to oper-  
ate from a single 3.0V to 3.6V power supply and also  
operate down to +1.65V. The MAX4888A is available  
in a 3.5mm x 5.5mm, 28-pin TQFN package. The  
MAX4889A is available in a 3.5mm x 9.0mm, 42-pin  
TQFN package. Both devices operate over the -40°C to  
+85°C temperature range.  
Ordering Information/  
Selector Guide  
PIN-  
PACKAGE  
PKG  
CODE  
PART  
CONFIGURATION  
Applications  
Two  
Half Lanes  
Desktop Computers  
Servers/Storage Area Networks  
Laptops  
MAX4888AETI+ 28 TQFN-EP*  
T283555-1  
Four Half  
Lanes  
MAX4889AETO+ 42 TQFN-EP*  
T423590M-1  
Note: All devices are specified over the -40°C to +85°C operat-  
ing temperature range.  
+Denotes lead-free package.  
*EP = Exposed paddle.  
PCI Express is a registered trademark of PCI-Sig Corp.  
Typical Application Circuit appears at end of data sheet.  
Pin Configurations  
TOP VIEW  
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22  
24 23 22 21 20 19 18 17 16 15  
39  
40  
21 GND  
20 V+  
25  
26  
14 GND  
13 V+  
GND  
V+  
GND  
V+  
MAX4888A  
GND 41  
V+ 42  
MAX4889A  
19 GND  
18 V+  
GND 27  
V+ 28  
12 GND  
11 V+  
*EP  
*EP  
+
+
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
1
2
3
4
5
6
7
8
9
10  
TQFN  
TQFN  
*CONNECT EXPOSED PADDLE TO GROUND.  
________________________________________________________________ Maxim Integrated Products  
1
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5.0Gbps PCI Express Passive Switches  
/MX489A  
ELECTRICAL CHARACTERISTICS (continued)  
(V+ = 3.0V to 3.6V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V+ = 3.3V, T = +25°C.) (Note 2)  
A
A
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
DYNAMIC  
Turn-On Time  
t
V
V
or V  
or V  
= 1.0V, R = 50Ω, Figure 1  
90  
10  
50  
250  
50  
ns  
ns  
ps  
ON  
NO_  
NO_  
NC_  
NC_  
L
Turn-Off Time  
t
= 1.0V, R = 50Ω, Figure 1  
OFF  
L
Propagation Delay  
t
R = R = 50Ω, unbalanced, Figure 2  
PD  
S
L
R = R = 50Ω, unbalanced; skew between  
any two pairs, Figure 2  
S
L
Output Skew Between Pairs  
t
t
50  
10  
ps  
ps  
SK1  
SK2  
Output Skew Between Same  
Pair  
R = R = 50Ω, unbalanced; skew between  
S
L
two lines on same pair, Figure 2  
R = R = 50Ω,  
unbalanced,  
Figure 3  
S
L
1MHz < f < 100MHz  
-0.5  
-1.4  
On-Loss  
G
dB  
dB  
LOS  
CT1  
500MHz< f < 1.25GHz  
Crosstalk between  
any two pairs,  
f = 50MHz  
-53  
-32  
Crosstalk  
V
R = R = 50Ω,  
S
L
unbalanced,  
Figure 3  
f = 1.25GHz  
Signaling Data Rate  
Off-Isolation  
BR  
R = R = 50Ω  
5.0  
-56  
Gbps  
dB  
S
L
Signal = 0dBm,  
f = 10MHz  
V
R = R = 50Ω,  
ISO  
S
L
f = 1.25GHz  
-26  
Figure 3  
C
NO_/NC_(OFF)  
NO_/NC_ Off-Capacitance  
COM_ On-Capacitance  
LOGIC INPUT  
Figure 4  
Figure 4  
1
2
pF  
pF  
C
COM_(ON)  
Input-Logic Low  
V
0.5  
+1  
V
V
IL  
Input-Logic High  
V
1.4  
-1  
IH  
Input-Logic Hysteresis  
Input Leakage Current  
POWER SUPPLY  
V
100  
mV  
µA  
HYST  
I
V
V
= 0V or V+  
= 0V or V+  
IN  
SEL  
SEL  
Power-Supply Range  
V+  
I+  
1.65  
3.60  
60  
V
MAX4888A  
MAX4889A  
V+ Supply Current  
µA  
120  
Note 2: All units are 100% production tested at T = +85°C. Limits over the operating temperature range are guaranteed by design  
A
and characterization and are not production tested.  
Note 3: ΔR  
= R  
- R  
.
ON  
ON (MAX)  
ON (MIN)  
Note 4: Guaranteed by design. Not production tested.  
Note 5: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the  
specified analog signal range.  
_______________________________________________________________________________________  
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5.0Gbps PCI Express Passive Switches  
Typical Operating Characteristics  
(T = +25°C, unless otherwise noted.)  
A
ON-RESISTANCE vs. V  
(V+ = 1.8V)  
ON-RESISTANCE vs. V  
(V+ = 2.5V)  
COM  
COM  
ON-RESISTANCE vs. V  
COM  
10.0  
9.5  
9.0  
8.5  
8.0  
7.5  
7.0  
6.5  
6.0  
5.5  
5.0  
14  
12  
10  
8
14  
12  
10  
8
T
= +85°C  
T
= +85°C  
A
A
V+ = 1.8V  
T
= +25°C  
A
T
= +25°C  
A
V+ = 2.5V  
6
6
T
= -40°C  
A
4
4
V+ = 3.3V  
2
2
T
= -40°C  
A
0
0
-0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1  
(V)  
-0.1  
0
0.1 0.2 0.3 0.4 0.5 0.6  
(V)  
-0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3  
(V)  
V
V
V
COM  
COM  
COM  
ON-RESISTANCE vs. V  
(V+ = 3.3V)  
COM  
SUPPLY CURRENT vs. TEMPERATURE  
(MAX4889A)  
/MX489A  
LOGIC THRESHOLD vs. SUPPLY VOLTAGE  
14  
12  
10  
8
80  
70  
60  
50  
40  
30  
20  
10  
0
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
T
= +85°C  
A
T
= +25°C  
A
V
IH  
V+ = 3.3V  
V+ = 2.5V  
6
V
IL  
4
2
V+ = 1.8V  
T
= -40°C  
A
0
-0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1  
(V)  
-40  
-15  
10  
35  
60  
85  
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6  
SUPPLY VOLTAGE (V)  
V
TEMPERATURE (°C)  
COM  
TURN-ON/-OFF TIME vs. SUPPLY VOLTAGE  
240  
220  
200  
180  
160  
140  
120  
100  
80  
NO_ t  
ON  
NC_ t  
ON  
60  
NO_ t  
OFF  
40  
NC_ t  
OFF  
20  
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6  
SUPPLY VOLTAGE (V)  
4
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5.0Gbps PCI Express Passive Switches  
/MX489A  
Typical Operating Characteristics (continued)  
(T = +25°C, unless otherwise noted.)  
A
EYE DIAGRAM  
(V+ = 3.3V, f = 1.25GHz,  
EYE DIAGRAM  
(V+ = 2.5V, f = 1.25GHz,  
EYE DIAGRAM  
(V+ = 1.8V, f = 1.25GHz,  
600mV PRBS SIGNAL, R = R = 50Ω)  
600mV PRBS SIGNAL, R = R = 50Ω)  
600mV PRBS SIGNAL, R = R = 50Ω)  
P-P  
S
L
P-P  
S
L
P-P  
S
L
V
V
V
COM_+  
COM_+  
COM_+  
50mV/div  
50mV/div  
50mV/div  
V
V
V
COM_-  
COM_-  
COM_-  
50ps/div  
50ps/div  
50ps/div  
*PRBS = PSEUDORANDOM BIT SEQUENCE  
= GEN 1, 2.5Gbps; U1 = 400ps  
*PRBS = PSEUDORANDOM BIT SEQUENCE  
= GEN 1, 2.5Gbps; U1 = 400ps  
*PRBS = PSEUDORANDOM BIT SEQUENCE  
= GEN 1, 2.5Gbps; U1 = 400ps  
EYE DIAGRAM  
(V+ = 1.8V, f = 2.5GHz,  
EYE DIAGRAM  
(V+ = 2.5V, f = 2.5GHz,  
EYE DIAGRAM  
(V+ = 3.3V, f = 2.5GHz,  
††  
††  
††  
600mV PRBS SIGNAL, R = R = 50Ω)  
600mV PRBS SIGNAL, R = R = 50Ω)  
600mV PRBS SIGNAL, R = R = 50Ω)  
P-P  
S
L
P-P  
S
L
P-P  
S
L
V
V
V
COM_+  
COM_+  
COM_+  
50mV/div  
50mV/div  
50mV/div  
V
V
V
COM_-  
COM_-  
COM_-  
25ps/div  
25ps/div  
25ps/div  
*PRBS = PSEUDORANDOM BIT SEQUENCE  
= GEN 11, 5.0Gbps; U1 = 200ps  
*PRBS = PSEUDORANDOM BIT SEQUENCE  
= GEN 11, 5.0Gbps; U1 = 200ps  
*PRBS = PSEUDORANDOM BIT SEQUENCE  
= GEN 11, 5.0Gbps; U1 = 200ps  
††  
††  
††  
_______________________________________________________________________________________  
5
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5.0Gbps PCI Express Passive Switches  
Pin Description  
PIN  
NAME  
FUNCTION  
MAX4888A  
MAX4889A  
1, 10, 12, 14, 1, 4, 10, 14, 17,  
GND  
Ground  
20, 25, 27  
19, 21, 39, 41  
2
3, 9  
4
5
6
9
2
3
6
SEL  
N.C.  
COM1+  
COM1-  
COM2+  
COM2-  
Digital Control Input  
No Connection. Not internally connected.  
Analog Switch 1. Common Positive Terminal.  
Analog Switch 1. Common Negative Terminal.  
Analog Switch 2. Common Positive Terminal.  
Analog Switch 2. Common Negative Terminal.  
7
7
5, 8, 13, 18,  
20, 30,  
Positive-Supply Voltage Input. Connect V+ to a 1.65V to 3.6V supply voltage.  
Bypass V+ to GND with a 0.1µF capacitor placed as close to the device as possible  
(See the Board Layout section).  
8, 11, 13, 19,  
26, 28  
V+  
40, 42  
15  
16  
17  
18  
21  
22  
23  
24  
EP  
31  
32  
33  
34  
35  
36  
37  
38  
11  
12  
15  
16  
22  
23  
24  
25  
26  
27  
28  
29  
EP  
NO2-  
NO2+  
NO1-  
Analog Switch 2. Normally Open Negative Terminal.  
Analog Switch 2. Normally Open Positive Terminal.  
Analog Switch 1. Normally Open Negative Terminal.  
Analog Switch 1. Normally Open Positive Terminal.  
Analog Switch 2. Normally Closed Negative Terminal.  
Analog Switch 2. Normally Closed Positive Terminal.  
Analog Switch 1. Normally Closed Negative Terminal.  
Analog Switch 1. Normally Closed Positive Terminal.  
Analog Switch 3. Common Positive Terminal.  
NO1+  
NC2-  
/MX489A  
NC2+  
NC1-  
NC1+  
COM3+  
COM3-  
COM4+  
COM4-  
NO4-  
Analog Switch 3. Common Negative Terminal.  
Analog Switch 4. Common Positive Terminal.  
Analog Switch 4. Common Negative Terminal.  
Analog Switch 4. Normally Open Negative Terminal.  
Analog Switch 4. Normally Open Positive Terminal.  
Analog Switch 3. Normally Open Negative Terminal.  
Analog Switch 3. Normally Open Positive Terminal.  
Analog Switch 4. Normally Closed Negative Terminal.  
Analog Switch 4. Normally Closed Positive Terminal.  
Analog Switch 3. Normally Closed Negative Terminal.  
Analog Switch 3. Normally Closed Positive Terminal.  
Exposed Paddle. Connect EP to GND.  
NO4+  
NO3-  
NO3+  
NC4-  
NC4+  
NC3-  
NC3+  
EP  
6
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5.0Gbps PCI Express Passive Switches  
/MX489A  
Test Circuits/Timing Diagrams  
MAX4888A/MAX4889A  
3.3V  
V+  
t
t
< 5ns  
< 5ns  
r
f
V
IH  
LOGIC  
INPUT  
50%  
V
IL  
NO_  
COM_  
V
N_  
V
OUT  
OR NC_  
t
OFF  
R
L
C
L
SEL  
V
OUT  
0.9 x V  
0.9 x V  
OUT  
0UT  
GND  
LOGIC  
INPUT  
SWITCH  
OUTPUT  
0V  
t
ON  
C
V
INCLUDES FIXTURE AND STRAY CAPACITANCE.  
L
R
L
= V  
N_  
OUT  
(
)
ON  
R
L
+ R  
V
N_  
= V OR V  
NO_ NC_  
Figure 1. Switching Time  
_______________________________________________________________________________________  
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5.0Gbps PCI Express Passive Switches  
Test Circuits/Timing Diagrams (continued)  
3.3V  
V+  
MAX4888A/MAX4889A  
NO_+ OR  
NC_+  
R
R
S
COM  
COM  
_+  
IN+  
IN-  
OUT+  
OUT-  
RISE-TIME PROPAGATION DELAY = t  
OR t  
PLHY  
PLHX  
FALL-TIME PROPAGATION DELAY = t  
OR t  
PHLY  
PHLX  
R
R
L
t
=
DIFFERENCE IN PROPAGATION DELAY (RISE-FALL)  
BETWEEN ANY TWO PAIRS  
SK1  
SK2  
NO_- OR  
NC_-  
S
_-  
t
= | t - t | OR | t  
- t  
PHLX PLHY  
|
PLHX PHLY  
BETWEEN TWO LINES ON THE SAME PAIR  
L
SEL  
/MX489A  
t
INFALL  
t
INRISE  
10%  
1.5V  
90%  
90%  
V
IN+  
50%  
50%  
50%  
10%  
0V  
1.5V  
V
50%  
IN-  
0V  
t
t
OUTRISE  
OUTFALL  
10%  
t
t
PLHX  
PHLX  
1.5V  
90%  
90%  
V
OUT+  
50%  
50%  
10%  
0V  
1.5V  
50%  
50%  
V
OUT-  
0V  
t
t
PHLY  
PLHY  
Figure 2. Propagation Delay and Output Skew  
8
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5.0Gbps PCI Express Passive Switches  
/MX489A  
Test Circuits/Timing Diagrams (continued)  
0.1μF  
3.3V  
V+  
V
V
OUT  
OFF-ISOLATION = 20log  
ON-LOSS = 20log  
IN  
NETWORK  
ANALYZER  
V
50Ω  
50Ω  
OUT  
V
V
0V OR V+  
IN  
SEL  
V
IN  
COM_  
V
OUT  
MAX4888A/MAX4889A  
CROSSTALK = 20log  
NC_  
V
IN  
MEAS  
REF  
OUT  
NO_  
50Ω  
50Ω  
50Ω  
GND  
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.  
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH.  
ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_ TERMINAL ON EACH SWITCH.  
CROSSTALK IS MEASURED BETWEEN ANY TWO PAIRS.  
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.  
Figure 3. On-Loss, Off-Isolation, and Crosstalk  
two sets of eight lanes from a single 16-lane bus. The  
MAX4888A/MAX4889A feature a single digital control  
input (SEL) to switch signal paths.  
3.3V  
0.1μF  
The MAX4888A/MAX4889A are fully specified to oper-  
ate from a single 3.0V to 3.6V power supply and also  
operate down to 1.65V.  
V+  
COM_  
MAX4888A/MAX4889A  
SEL  
Digital Control Input (SEL)  
The MAX4888A/MAX4889A provide a single digital  
control input (SEL) to select the signal path between  
the COM__ and NO__/NC__ channels. The truth tables  
for the MAX4888A/MAX4889A are depicted in the  
Functional Diagrams/Truth Table section. Drive SEL  
rail-to-rail to minimize power consumption.  
V
IL  
OR V  
IH  
CAPACITANCE  
METER  
NC_ or  
NO_  
GND  
Analog Signal Levels  
The MAX4888A/MAX4889A accept standard PCIe sig-  
nals to a maximum of V+ - 1.2V. Signals on the COM_+  
channels are routed to either the NO_+ or NC_+ chan-  
nels, and signals on the COM_- channels are routed to  
either the NO_- or NC_- channels. The MAX4888A/  
MAX4889A are bidirectional switches, allowing COM__,  
NO__, and NC__ to be used as either inputs or outputs.  
Figure 4. Channel Off-/On-Capacitance  
Detailed Description  
The MAX4888A/MAX4889A high-speed passive switch-  
es route PCIe data between two possible destinations.  
The MAX4888A/MAX4889A are ideal for routing PCIe sig-  
nals to change the system configuration. For example, in  
a graphics application, the MAX4888A/MAX4889A create  
_______________________________________________________________________________________  
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5.0Gbps PCI Express Passive Switches  
Functional Diagrams/Truth Table  
V+  
V+  
MAX4888A  
MAX4889A  
COM1+  
COM1-  
NC1+  
NC1-  
NO1+  
NO1-  
NC2+  
NC2-  
NO2+  
NO2-  
COM1+  
COM1-  
NC1+  
NC1-  
NO1+  
NO1-  
NC2+  
NC2-  
NO2+  
NO2-  
NC3+  
NC3-  
NO3+  
NO3-  
NC4+  
NC4-  
NO4+  
NO4-  
COM2+  
COM2-  
COM2+  
COM2-  
/MX489A  
SEL  
COM3+  
COM3-  
GND  
COM__TO COM__TO  
NC__  
COM4+  
COM4-  
SEL  
NO__  
0
1
ON  
OFF  
OFF  
ON  
SEL  
GND  
10 ______________________________________________________________________________________  
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5.0Gbps PCI Express Passive Switches  
/MX489A  
Applications Information  
PCIe Switching  
The MAX4888A/MAX4889A primary applications are  
DATA  
DIRECTION  
aimed at reallocating PCIe lanes (see Figure 5). For  
example, in graphics applications, several manufacturers  
have found that it is possible to improve performance  
by a factor of nearly two by splitting a single 16-lane  
PCIe bus into two 8-lane buses. Two of the more promi-  
nent examples are SLI™ (Scaled Link Interface) and  
CrossFire™. The MAX4889A permits a computer  
motherboard to operate properly with a single 16-lane  
graphics card, and can later be updated to dual cards.  
The same motherboard can be used with dual cards  
where the user sets a jumper or a bit through software  
to switch between single- or dual-card operation.  
Common mode below 1V operation requirement.  
MAX4888A  
MAX4889A  
ONE LANE  
DATA IS ROUTED  
TO EITHER  
BOARD A OR B  
NOTE: ONLY ONE LANE IS SHOWN FOR CLARITY  
Board Layout  
High-speed switches require proper layout and design  
procedures for optimum performance. Keep design-  
controlled impedance PCB traces as short as possible  
or follow impedance layouts per the PCIe specification.  
Ensure that power-supply bypass capacitors are  
placed as close to the device as possible. Multiple  
bypass capacitors are recommended. Connect all  
grounds and the exposed pad to large ground planes.  
Common mode below 1V operation requirement.  
A
B
Figure 5. The MAX4888A/MAX4889A Used as a Single-Lane  
Switch  
Chip Information  
PROCESS: CMOS  
CrossFire is a trademark of ATI Technologies, Inc.  
SLI is a trademark of NVIDIA Corporation.  
______________________________________________________________________________________ 11  
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5.0Gbps PCI Express Passive Switches  
Typical Application Circuit  
PCIe GRAPHICS INTERFACE  
GRAPHICS  
CARD 1  
GRAPHICS  
CARD 2  
PCIe BUS  
COM1+  
COM1-  
COM2+  
COM2-  
COM3+  
COM3-  
COM4+  
COM4-  
NC1+  
LANE 0 TX  
NC1-  
NC2+  
NC2-  
NC3+  
NC3-  
NC4+  
NC4-  
NO1+  
NO1-  
NO2+  
NO2-  
NO3+  
NO3-  
NO4+  
NO4-  
LANE 1 TX  
LANE 2 TX  
LANE 3 TX  
MAX4889A  
/MX489A  
SEL  
CHANNEL SELECT  
COM1+  
COM1-  
COM2+  
COM2-  
COM3+  
COM3-  
COM4+  
COM4-  
NC1+  
NC1-  
NC2+  
NC2-  
NC3+  
NC3-  
NC4+  
NC4-  
NO1+  
NO1-  
NO2+  
NO2-  
NO3+  
NO3-  
NO4+  
NO4-  
LANE 0 RX  
LANE 1 RX  
LANE 2 RX  
LANE 3 RX  
MAX4889A  
SEL  
CHANNEL SELECT  
12 ______________________________________________________________________________________  
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5.0Gbps PCI Express Passive Switches  
/MX489A  
Package Information  
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information  
°
______________________________________________________________________________________ 13  
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5.0Gbps PCI Express Passive Switches  
Package Information (continued)  
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information  
°
/MX489A  
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are  
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.  
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600  
© 2007 Maxim Integrated Products  
is a registered trademark of Maxim Integrated Products., Inc.  
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