®
ICP-CM
Intel® Celeron® M Low
Power CPU Boards
Comp
USER’S MANUAL
Publication Number: PD00941013.001 AB
MAN-ICP-CM
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ICP-CM
Preface
®
Preface
Contents
Unpacking and Special Handling Instruc-
tions............................................... 6
Revision History............................... 7
Three Year Limited Warranty.............. 8
1.0 ICP-CM CPU........................... 1-3
1.01 Interfacing ............................................................................................... 1-4
1.02 Peripherals ............................................................................................... 1-4
1.03 Software .................................................................................................. 1-4
1.04 Graphics .................................................................................................. 1-4
1.1 Specifications ......................... 1-5
1.2 Functional Overview................. 1-7
Figure 1.20 ICP-CM Interfacing.................................................................................................. 1-7
Figure 1.21 ICP-CM Board Overview .......................................................................................... 1-8
1.3 Software................................ 1-9
1.31 Windows XP (Professional / Embedded) ................................................... 1-9
1.32 Windows 2000 (Professional) ................................................................... 1-9
1.33 Linux........................................................................................................ 1-9
1.34 VentureCom............................................................................................. 1-9
1.35 Windows CE........................................................................................... 1-10
1.36 VxWorks................................................................................................. 1-10
1.37 OS-9 x86 ............................................................................................... 1-10
1.38 QNX ...................................................................................................... 1-10
1.39 Jbed ....................................................................................................... 1-10
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Preface
ICP-CM
1.4 Hardware ............................. 1-11
1.41 Block Diagram........................................................................................ 1-11
Figure 1.41 Block Diagram....................................................................................................... 1-11
1.42 Connector Location ............................................................................... 1-12
Figure 1.42 Connector Locations .............................................................................................. 1-12
1.43 Connector Description ........................................................................... 1-12
Table 1.43 Connector Description ............................................................................................ 1-12
Table 1.43 Continued .............................................................................................................. 1-13
1.44 Front-Panel Features............................................................................... 1-13
Table 1.44 Front Panels ........................................................................................................... 1-13
Figure 1.44 Front-Panel Options .............................................................................................. 1-14
1.45 Interface Positions .................................................................................. 1-15
Figure 1.45 Interfaces .............................................................................................................. 1-15
1.46 Construction - 4HP Standard CPU .......................................................... 1-16
Figure 1.46 Construction of CPU with Heat-Sink Assembly ........................................................ 1-16
1.47 Construction - 8HP Standard CPU .......................................................... 1-17
Figure 1.47 Construction of CPU with Heat-Sink Assembly ........................................................ 1-17
1.48 Construction - 8HP Standard CPU with AGP........................................... 1-18
Figure 1.48 Construction of CPU with Heat-Sink Assembly ........................................................ 1-18
1.49 Power Requirements .............................................................................. 1-19
Table 1.49 ICP-CM Power Reqirements .................................................................................... 1-19
1.50 Power Consumption .............................................................................. 1-20
Figure 1.50 ICP-CM Power Consumption.................................................................................. 1-20
1.51 Thermal Considerations ......................................................................... 1-21
Table 1.51 ICP-CM Airflow Requirements ................................................................................. 1-21
2.0 Memory Map........................... 2-2
Figure 2.00 System Architecture ................................................................................................. 2-2
2.1 I/O Mapped Peripherals............. 2-4
Table 2.10 Legacy I/O Map (ISA Compatible) ............................................................................ 2-4
Table 2.10 Legacy I/O Map (ISA Compatible) Contd. ................................................................. 2-5
2.2 Memory Mapped Peripherals ..... 2-6
2.3 Interrupt Routing .................... 2-6
Table 2.30 PC-AT Interrupt Definitions ....................................................................................... 2-7
2.4 DMA Channel Descriptions ....... 2-7
Table 2.40 DMA Channel Description ........................................................................................ 2-7
2.5 Inova CM SMB Devices ............ 2-8
Table 2.50 SMB Devices............................................................................................................. 2-8
2.6 Inova CM PCI Device List ......... 2-9
Table 2.60 Legacy I/O Map (ISA Compatible) ............................................................................ 2-9
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ICP-CM
Preface
2.7 Interrupt Configuration .......... 2-10
Table 2.70 CompactPCI Bus Interrupts ..................................................................................... 2-10
®
2.8 Timer / Counter..................... 2-11
2.9 Watchdog............................. 2-11
3.0 CompactPCI J1/J2 Connectors . 3-2
3.01 CompactPCI Connector Naming.............................................................. 3-2
Figure 3.01 Naming Convention as per PICMG 2.0 R3.0 Specification ........................................ 3-2
3.02 CompactPCI J1 Connector ....................................................................... 3-2
Figure 3.02 J1- 32-Bit CompactPCI Bus Interface Connector ....................................................... 3-2
3.03 ICP-PM Connector J1 and J2 .................................................................... 3-2
Table 3.03 32-Bit CompactPCI J1 Pin Assignment....................................................................... 3-3
Table 3.04 32-Bit CompactPCI J2 Pin Assignment (Std. with Rear I/O (D)).................................. 3-4
Table 3.04 32-Bit CompactPCI J2 Pin Assignment (Std. - with Rear I/O (D)) - Contd. .................. 3-5
Table 3.05 Inova’s ICP-CM Rear I/O J2 (CPU) Integration ........................................................... 3-6
3.1 CompactPCI Backplane ............ 3-7
Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot .................................. 3-8
3.2 Interfaces............................... 3-9
3.21 J6 & J7 Ethernet ....................................................................................... 3-9
Figure 3.21 RJ45 Pinout ............................................................................................................. 3-9
Table 3.21 Ethernet Standards & Connector Signals ................................................................... 3-9
3.22 J17 VGA Interface ................................................................................... 3-10
3.23 Graphic Features (Chipset) ..................................................................... 3-10
Table 3.23a highlights just some of the features of the standard integrated video controller. ..... 3-10
Figure 3.23 High-Density D-Sub VGA Interface Pinout .............................................................. 3-11
Table 3.23b Video Output Connector Signals ........................................................................... 3-11
3.24 J19 USB Interface ................................................................................... 3-12
Figure 3.24 USB Interface Pinout.............................................................................................. 3-12
Table 3.24 USB Connector Signals ........................................................................................... 3-12
3.25 J10 Hot-Swap Interface .......................................................................... 3-13
3.26 SW1 Reset Button .................................................................................. 3-13
3.27 J9 CompactFlash Interface...................................................................... 3-13
3.28 Connecting the CM to the Inova ICP-HD3(-ND) .................................... 3-13
3.29 Connecting the CM to the Inova IPB-FPE12 ........................................... 3-13
3.30 Connecting the CM to a Slim-Line Floppy-Disk ...................................... 3-13
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A1 ICP-HD-3(-ND) CPU Extension.. A-2
A1.1 ICP-HD-3(-ND) Front-Panels (8HP or 12HP) ............................................. A-2
Figure A1.1 ICP-HD-3(-ND) CPU Front-Panels ............................................................................ A-2
A1.2 IDE Carrier Board ICP-HD-3(-ND) ............................................................. A-3
Figure A1.2 Interface Location of the ICP-HD-3(-ND) Module ..................................................... A-3
Table A1.2 Interface Description of the ICP-HD-3(-ND) Module .................................................. A-4
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Preface
ICP-CM
A2 ICP-HD-3(-ND) Interfaces......... A-5
A2.1 COM1 & COM2 Interfaces ...................................................................... A-5
Figure A2.1 COM1 & COM2 Interface Pinout ............................................................................. A-5
Table A2.1 COM1 & COM2 Connector Signals........................................................................... A-5
A2.2 Mouse & Keyboard Interfaces .................................................................. A-6
Figure A2.2 Mouse & Keyboard Interface Pinout ........................................................................ A-6
Table A2.2 Mouse & Keyboard Connector Signals....................................................................... A-6
Table A2.3 USB Connector Signals ............................................................................................. A-7
A2.3 USB 2.0 Interfaces .................................................................................... A-7
Figure A2.3 USB Interface Pinout................................................................................................ A-7
A2.4 EIDE Interface .......................................................................................... A-8
A2.5 Slim-Line Floppy Disk Interface................................................................. A-8
B1 IPB-FPE12 CPU Extension ........ B-2
B1.1 J13 Interface for LPT1 ............................................................................... B-2
B1.2 IPB-FPE12 Front-Panel (4HP or 12HP) ....................................................... B-2
Figure B1.2 IPB-FPE12 Stand-Alone or Integrated with CPU ........................................................ B-2
B1.3 LPT1 Piggyback........................................................................................ B-3
Figure B1.3 LPT1 Piggyback Board IPB-FPE12 ............................................................................. B-3
Table B1.3 IPB-FPE12 Connector Description .............................................................................. B-4
B1.4 LPT1 Interface .......................................................................................... B-4
Figure B1.4 LPT1 Interface Pinout .............................................................................................. B-4
Table B1.4 LPT1 Connector Signals ............................................................................................ B-4
C1 ITM-RIO CPU Extension ............ C-2
C1.1 ITM-RIO-D Configurations ....................................................................... C-2
Table C1.10 Valid Rear I/O Configurations ................................................................................. C-2
Table C1.11 Rear I/O Module Functionality ................................................................................ C-2
C1.2 ITM-RIO Rear-Panels (4HP or 8HP) ........................................................... C-3
Figure C1.2 The rear Panels of the Inova ITM-RIO-D-x................................................................ C-3
C1.3 ITM-RIO-D-x Transition Module ............................................................... C-4
Figure C1.3 Inova Rear I/O Transition Module ITM-RIO-D-x........................................................ C-4
Table C1.3 ITM-RIO-D-x Connector Description.......................................................................... C-5
C1.4 COM1 & COM2 Interfaces ...................................................................... C-6
Figure C1.4 COM1 & COM2 Interface Pinout............................................................................. C-6
Table C1.4 COM1 & COM2 Connector Signals .......................................................................... C-6
C1.5 LPT1 Interface.......................................................................................... C-7
Figure C1.5 LPT1 Interface Pinout .............................................................................................. C-7
Table C1.5 LPT1 Connector Signals ............................................................................................ C-7
C1.6 Mouse & Keyboard Interfaces .................................................................. C-8
Figure C1.6 Mouse & Keyboard Interface Pinout........................................................................ C-8
Table C1.6 Mouse & Keyboard Connector Signals ...................................................................... C-8
C1.7 VGA Interface .......................................................................................... C-9
Figure C1.7 VGA Interface Pinout ............................................................................................... C-9
Table C1.7 Video Output Connector Signals ............................................................................... C-9
C1.8 Fast Ethernet Interface ........................................................................... C-10
Figure C1.8 Fast Ethernet Interface Pinout ................................................................................ C-10
Table C1.8 Fast Ethernet Connector Signals.............................................................................. C-10
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ICP-CM
Preface
C1.9 USB Interface (USB 4) ............................................................................ C-11
Figure C1.9 USB Interface Pinout ............................................................................................. C-11
Table C1.9 USB Connector Signals ........................................................................................... C-11
®
C1.10 EIDE Interface ...................................................................................... C-12
C1.11 Slim-Line Floppy Disk Interface ............................................................ C-12
C1.12 ITM-RIO(C&D)-FHLU Extension ........................................................... C-13
Figure C1.12 ITM-RIO(C&D)-FHLU........................................................................................... C-13
D1 IPM-ATA CPU Extension .......... D-2
D1.1 rJ2 Interface ............................................................................................ D-2
Figure D1.1a Dedicated IPM-ATA Backplane ............................................................................... D-2
D1.1 rJ2 Interfaces (Contd.) ............................................................................ D-3
Figure D1.1b The Complete Connection Picture .......................................................................... D-3
D1.2 IPM-ATA-HD ........................................................................................... D-4
Figure D1.2 IPM-ATA-HD Board Layout ...................................................................................... D-4
Table D1.2 IPM-ATA-HD Jumper Description (CF Socket) ............................................................. D-4
D1.3 IPM-ATA-CF ............................................................................................ D-5
Figure D1.3 IPM-ATA-CF Board Layout ....................................................................................... D-5
Table D1.3 IPM-ATA-CF Jumper Description ................................................................................ D-5
D1.4 IPM-ATA-PCMCIA ................................................................................... D-6
Figure D1.4 IPM-ATA-PCMCIA Board Layout............................................................................... D-6
Table D1.4 IPM-ATA-PCMCIA Jumper Description ....................................................................... D-6
D1.5 Device Compatibility .............................................................................. D-7
Table D1.5 Compatibility List ..................................................................................................... D-7
E1 AGP-R7000 CPU Extension....... E-2
Table E1.00 AGP Piggyback Configurations ................................................................................. E-2
E1.1 Specifications ........................................................................................... E-3
E1.2 J4 Interface ............................................................................................... E-4
Figure E1.20 J4 on the Underside of the AGP-R7000 Piggyback ................................................... E-4
Table E1.20 J4 Pinout ................................................................................................................. E-5
Table E1.20 J4 Pinout - Contd. .................................................................................................... E-6
E1.3 J3 & J5 IBP-GS-MULTILINK (TFT) Interfaces............................................... E-7
Figure E1.30 J3 and J5 Topside Connectors for the Inova IPB-GS-MULTILINK ................................ E-7
Table E1.30 J3 & J5 Interface Pinout ........................................................................................... E-8
E1.4 J1 Front-Panel VGA/TMDS Interface.......................................................... E-9
Figure E1.40 Standard Front-Panel VGA/TMDS Interface ............................................................. E-9
Table E1.40 J1 Standard Front-Panel VGA/TMDS Pinout.............................................................. E-9
Table E1.41 J2 DIP Switch Settings - Digital TMDS (PanelLink) or DVI-D .................................... E-10
Table E1.42 J2 DIP Switch Settings - TFT (24Bit TTL/CMOS) ...................................................... E-10
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E1.5 Rear I/O VGA Interface ........................................................................... E-11
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Preface
ICP-CM
Unpacking and Special Handling
Instructions
This product has been designed for a long and fault-free life; nonetheless, its life expectancy can
be severely reduced by improper treatment during unpacking and installation.
Observe standard antistatic precautions when changing piggybacks, ROM devices, jumper set-
tings etc. If the product contains batteries for RTC or memory backup, ensure that the board is not
placed on conductive surfaces as these can cause short circuits, damage the batteries or disrupt
the conductive tracks on the board.
Do not exceed the specified operational temperature ranges of the board version ordered. If
batteries are present, their temperature restrictions must be taken into account.
Keep all the original packaging material for future storage or warranty shipments. If it is necessary
to store or ship the board, re-pack it as it was originally packed.
Before returning this product for repair, please ask for an RMA (Returned Material Authorization)
number by submitting an email and supply the following informa-
tion:
í
í
í
í
Company name, contact person, shipping address and invoice address
Product name and serial number
Failure or fault description
Clearly write the RMA number on the outside of the transportation carton.
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ICP-CM
Preface
Revision History
®
Revision History
Manual
Publication Number PD00941013.XXX
Issue Brief Description of Changes
PD00941013.001 Preliminary, First Release; All pages revised
MAN-ICP-CM
Date of Issue
Author
AB
26/07/2004
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Preface
ICP-CM
Three Year Limited Warranty
Inova Computers (‘Inova’) grant the original purchaser of Inova products the following hardware
warranty. No other warranties that may be granted or implied by anyone on behalf of Inova are
valid unless the consumer has the expressed written consent of Inova.
Inova warrants their own products (excluding software) to be free from defects in workmanship
and materials for a period of 36 consecutive months from the date of purchase. This warranty is
not transferable nor extendible to cover any other consumers or long term storage of the product.
This warranty does not cover products which have been modified, altered, or repaired by any
other party than Inova or their authorized agents. Furthermore, any product which has been, or
is suspected of being damaged as a result of negligence, misuse, incorrect handling, servicing or
maintenance; or has been damaged as a result of excessive current/voltage or temperature; or has
had its serial number(s), any other markings, or parts thereof altered, defaced, or removed will
also be excluded from this warranty.
A customer who has not excluded his eligibility for this warranty may, in the event of any claim,
return the product at the earliest possible convenience, together with a copy of the original proof
of purchase, a full description of the application it is used on, and a description of the defect; to
the original place of purchase.
Pack the product in such a way as to ensure safe transportation (we recommend the original
packing materials), whereby Inova undertakes to repair or replace any part, assembly or sub-
assembly at our discretion; or, to refund the original cost of purchase, if appropriate.
In the event of repair, refund, or replacement of any part, the ownership of the removed or
replaced parts reverts to Inova, and the remaining part of the original guarantee, or any new
guarantee to cover the repaired or replaced items, will be transferred to cover the new or repaired
items. Any extensions to the original guarantee are considered gestures of goodwill, and will be
defined in the “Repair Report” returned from Inova with the repaired or replaced item.
Other than the repair, replacement, or refund specified above, Inova will not accept any liability
for any further claims which result directly or indirectly from any warranty claim. We specifically
exclude any claim for damage to any system or process in which the product was employed, or
any loss incurred as a result of the product not functioning at any given time. The extent of
Inova’s liability to the customer shall not be greater than the original purchase price of the item
for which any claim exists.
Inova makes no warranty or representation, either expressed or implied, with respect to its prod-
ucts, reliability, fitness, quality, marketability or ability to fulfil any particular application or pur-
pose. As a result, the products are sold “as is,” and the responsibility to ensure their suitability for
any given task remains the purchaser’s. In no event will Inova be liable for direct, indirect, or
consequential damages resulting from the use of our hardware or software products, or docu-
mentation; even if we were advised of the possibility of such claims prior to the purchase of, or
during any period since the purchase of the product. Please remember that no Inova employee,
dealer, or agent are authorized to make any modification or addition to the above terms, either
verbally or in any other form written or electronically transmitted, without consent.
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ICP-CM
Product Overview
®
1
Product Overview
Overview Contents
1.0 ICP-CM CPU........................... 1-3
1.01 Interfacing ............................................................................................... 1-4
1.02 Peripherals ............................................................................................... 1-4
1.03 Software .................................................................................................. 1-4
1.04 Graphics .................................................................................................. 1-4
1.1 Specifications ......................... 1-5
1.2 Functional Overview................. 1-7
Figure 1.20 ICP-CM Interfacing.................................................................................................. 1-7
Figure 1.21 ICP-CM Board Overview .......................................................................................... 1-8
1.3 Software................................ 1-9
1.31 Windows XP (Professional / Embedded) ................................................... 1-9
1.32 Windows 2000 (Professional) ................................................................... 1-9
1.33 Linux........................................................................................................ 1-9
1.34 VentureCom............................................................................................. 1-9
1.35 Windows CE........................................................................................... 1-10
1.36 VxWorks................................................................................................. 1-10
1.37 OS-9 x86 ............................................................................................... 1-10
1.38 QNX ...................................................................................................... 1-10
1.39 Jbed ....................................................................................................... 1-10
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Product Overview
ICP-CM
1.4 Hardware ............................. 1-11
1.41 Block Diagram........................................................................................ 1-11
Figure 1.41 Block Diagram....................................................................................................... 1-11
1.42 Connector Location ............................................................................... 1-12
Figure 1.42 Connector Locations .............................................................................................. 1-12
1.43 Connector Description ........................................................................... 1-12
Table 1.43 Connector Description ............................................................................................ 1-12
Table 1.43 Continued .............................................................................................................. 1-13
1.44 Front-Panel Features............................................................................... 1-13
Table 1.44 Front Panels ........................................................................................................... 1-13
Figure 1.44 Front-Panel Options .............................................................................................. 1-14
1.45 Interface Positions .................................................................................. 1-15
Figure 1.45 Interfaces .............................................................................................................. 1-15
1.46 Construction - 4HP Standard CPU .......................................................... 1-16
Figure 1.46 Construction of CPU with Heat-Sink Assembly ........................................................ 1-16
1.47 Construction - 8HP Standard CPU .......................................................... 1-17
Figure 1.47 Construction of CPU with Heat-Sink Assembly ........................................................ 1-17
1.48 Construction - 8HP Standard CPU with AGP........................................... 1-18
Figure 1.48 Construction of CPU with Heat-Sink Assembly ........................................................ 1-18
1.49 Power Requirements .............................................................................. 1-19
Table 1.49 ICP-CM Power Reqirements .................................................................................... 1-19
1.50 Power Consumption .............................................................................. 1-20
Figure 1.50 ICP-CM Power Consumption.................................................................................. 1-20
1.51 Thermal Considerations ......................................................................... 1-21
Table 1.51 ICP-CM Airflow Requirements ................................................................................. 1-21
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ICP-CM
Product Overview
1.0 ICP-CM CPU
®
1
Cutting edge technology makes the Inova Socket mPGA479M, Celeron® M single-board compu-
ter the ideal controller for a wide range of embedded (low power) industrial automation, military,
medical, aerospace, imaging, telecommunications, process control and embedded/OEM applica-
tions. Without altering the design, Master or Slave ICP-CM CPUs can be operated in an industrial
environment through their ability to detect automatically the backplane system controller or pe-
ripheral slot. In addition, the ICP-CM family can communicate at very high speed with up to 255
x 7 cascaded peripherals like graphics, industrial I/O or fast data acquisition modules on inter-
linked passive backplanes.
The powerhouse in any application, Inova’s Socket mPGA479M based high-performance 3U Com-
pactPCI CPU is packed with a feature set unrivalled in industry on such a small scale. Configured
with up to 1GByte onboard 266MHz DDR SDRAM, the ICP-CM is the ideal choice for low-power,
high peromance computing tasks. In addition, enriched performance scalability is assured through
the latest Intel® Celeron® M ‘processors and board feature set. Conforming to the latest PICMG
CompactPCI specification the ICP-CM has a colourful feature set that includes rear I/O options,
choice of graphic components and flexible mass-storage expansion options.
Being of a true universal design, both 5.0 and 3.3V I/O signalling voltages are possible without
board modification. The auto-detect mechanism in the PCI/PCI bridge permits the same CPU to
operate as a system Master controller or reside in a peripheral slot. A Slave CM CPU is thus able to
communicate with the host controller through the bridge via the CompactPCI backplane (for
high-speed DMA for example) or front-panel TCP/IP.
The standard Inova ICP-CM configuration is ready to run - straight from the box. Utilizing the low-
power consumption and the high-performance of the Celeron processor enables truly embedded,
ruggedized industrial applications to be engineered utilizing the latest software available today.
512kByte of L2 cache backed by up to a 1GByte bank of soldered double-data rate (DDR) SDRAM
clocked at 266MHz ensures an efficient processor-level data throughput exceeding that of any
comparable product.
For hard-core ruggedized applications, and thanks to the miniaturisation of silicon components,
Inova’s engineers have squeezed in a Compact FLASH socket suitable for use by all 3rd party
Micro-Drive devices or solid-state FLASH that adhere to the interface standard.
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Serviceability and user friendliness feature throughout the CPU design and is highlighted in the
lack of on-board cabling - all interconnects are hard-wired. An optional dedicated hard disk carrier
with integrated COM ports, twin USB 2.0 and PS-2 mouse and keyboard interfaces connects
directly to the base CPU. Naturally, for space critical applications, these interfaces are available as
rear I/O - effectively extending the standard 160mm card by a further 80mm! Notebook hard
disks are selected for their high capacity, small footprint, rugged operating conditions and higher
operational temperature characteristics.
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Product Overview
ICP-CM
1.01 Interfacing
To satisfy today’s LAN-hungry industrial applications, Inova have implemented dual, independent
100BaseTx LAN Fast Ethernet interfaces as standard on the CPU’s front-panel - or fed to a rear I/O
transition module on the backplane. Connectivity is further enhanced through the integration of
the latest USB 2.0 serial interfaces that permit a number of readily available peripherals such as
mouse, keyboard, floppy drives and even CD-ROMs or printers to be utilized without compromizing
front panel width.
1.02 Peripherals
The ICP-CM supports standard PC peripherals – floppy disk, hard disk and CD ROM. Notebook
style hard disks may be connected directly to the base-board (2-slot) and possess their own front-
panel offering COM ports and combined PS-2 style connector for mouse and keyboard.
1.03 Software
The following operating systems are compatible with Inova’s CM, 3U CompactPCI CPU:
{
{
{
{
{
{
{
{
{
{
Linux
Windows® 2000
Windows® XP
Windows® NT® & VenturCom RTX® (Real-Time Extension) - On request
Windows® CE - On request
Windows® 9x - On request
Windriver VxWorks® - On request
QNX® - On request
Esmeralda Technology Jbed® (under development - On request)
Solaris x86 - On request
All readily available application software designed for operation on the standard x86 architecture
will execute without modification.
1.04 Graphics
Built in to the ICP-CM chipset is an analog VGA interface with BIOS configurable video RAM
allocation extracted from the system memory.
Inova have also developed a number of ATI Radeon R7000-based dedicated AGP plug-in modules
complete with video controller and RAM etc. for graphic intensive applications or to provide
greater display flexibility.
Ȣ
Depending on the selected module, MPEG-2 decoding, sound functions, GigaST R for distrib-
uted display communication, PanelLink or TFT flat-panel connectivity can be easily implemented.
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ICP-CM
Product Overview
1.1 Specifications
®
1
Processor
600MHz or 1.3GHz Socket mPGA479M mobile Intel Celeron M with 400MHz
PSB, 512kByte L2 cache, passive or active cooling
Memory
Either 256MByte or 1GByte soldered 266MHz DDR SDRAM
FLASH Socket
For CompactFlash devices (Flash & MicroDrives) providing >4GByte
mass-storage capacity
Phoenix BIOS
Ī LAN Boot
Ī USB Boot
Ī Quick Boot
Ī Quiet Boot
Ver. 4.x Rel. 6.0 Ī ACPI 2.0
Ī Multi Boot
Lithium cell for RTC (NV-RAM) with a lifetime > 10 years
Battery
SiS651 North Bridge supporting
Ī 400/533MHz FSB to CPU
Ī 333MHz, 64-bit DDR DRAM controller
Ī VGA interface (2048 x 1536 pixels)
Ī AGP 4x interface
Host Bridge
Ī Power management
SiS962
South Bridge
Ī PCI Bus 32-bit / 33MHz
Ī Mouse & keyboard controller
Ī Fast Ethernet
Ī USB 2.0
Ī AC97 bus (sound)
Ī LPC bus to Super I/O & BIOS
Ī IDE Controller (2 independent IDE channels - each supporting 2 devices)
Ī Ultra DMA 133 support
Ī Real-Time Clock
Ī Watchdog - programmable up to 256 hours; issues SMI or Reset
Ī Interrupt controller
Ī Power Management Unit
PC87393:
Super I/O
Ī Floppy Disk Controller, 1 Parallel Port (ECP, EPP), 2 serial COM Ports
Ī Watchdog
Onboard video controller (chipset) with:
Graphic Option Ī BIOS selectable video RAM allocation
Ī Support for MPEG-2 video playback
C
Ī Support for VESA standard super high resolution graphics modes
Ī Support for low-resolution modes (320x240, 512x384, 400x300)
Ī Supports VESA Display Power Management Signalling
Ī Supports Direct Draw Drivers
Ī Supports single video windows with overlay function
or AGP 4x Piggyback (R7000) with:
Ī 32MByte RAM
Ī 3D graphics, DVD & MPEG-2 support
Ī Multi-Display
Ī PanelLink & TFT support
Ȣ
Ī GigaST R support
Ī Sound support
Ī Dual View support under Microsoft Windows 9x, Windows 2000 & XP
Ī CRT / TFT resolutions up to 2048x1536
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ICP-CM
Fast Ethernet
PCI/PCI
Additional 82551 controller
Universal bridge (Master or Slave)
Ī Serialized interrupts
Ī Universal (3.3/5.0V) V I/O support
Ī 32-bit and Rear I/O
On-Board I/O
Rear I/O
Ī Dual 10/100 Mbit/s Fast Ethernet
Ī 1x front-panel 480Mbit/s, USB 2.0, (1x rear-panel 12Mbit/s, USB 1.1)
Ī VGA (chipset or AGP)
Standard to all CPU variants is option ‘D’:
Ī VGA (chipset or AGP if installed)
Ī Fast Ethernet ETH 1 (Intel 82551)
Ī USB 1.1
Ī PS-2 mouse & keyboard
Ī 2nd IDE channel (Master & Slave)
Ī Software configurable
Ī LPT1 or
Ī COM1 & COM2 or
Ī Floppy disk (A or B - BIOS selectable)
Ī Reset & Beeper
Mass Storage
Front-Panels
Connectors
CompactPCI
1.44MByte 3.5” floppy drive and EIDE (standard 40-pin header - 80-strand
ATA-5 compatible) supporting 2 pairs (Master/Slave) hard-disks or CD ROMs
8HP front-panel with 2x USB 2.0, COM1, COM2, combined PS-2 mouse &
keyboard; 12HP panel has LPT
USB (USB), 2x RJ45 (Ethernet), 9/15-pin D-Sub (Graphic piggyback) or 15-pin
high-density D-Sub (VGA)
Ī Universal (transparent/non-transparent) PCI/PCI bridge for Master/Slave
operation
Ī PICMG 2.0 R3.0, 32/64-bit, 33MHz system slot interface with 7 Master
(DMA) support.
Ī Full Hot-Swap according to PICMG2.1 R2.0
Mechanics
3U (100 x 160mm) x 21/42mm (4TE/8TE)
Typ. 15W
Power Cons.
Software Sup-
port
Windows®XP, Windows®2000, Windows®NT, Windows®9x, Linux, VxWorks®,
QNX®, OS9
Mass
220g (4TE)
MTBF
>220,000 hours @ 20°C
Oper. Temp.
0°C to +65°C (Std.) -40°C to +85°C (Opt.)
Passive cooling requires - refer to Table 1.51 for details
Storage Temp. -40°C to +85°C
Humidity
5% to 95% (non-condensing)
Three-year limited warranty
PICMG 2.0 R3.0; CE
Warranty
Conformance
*Notes: CPUs fitted with HD, FD or CD-ROM etc. have a max. operational temp. of 50°C.
Rear I/O D necessitates backplanes being PICMG 2.0 Rev. 3.0 compatible
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Product Overview
1.2 Functional Overview
®
1
Figure 1.20 ICP-CM Interfacing
Inova’s CPUs have been prepared for rear I/O operation. Currently RIO-D is supported with VGA,
single-channel Fast Ethernet, second EIDE channel, USB 1.1, mouse, keyboard, reset and loud-
speaker (beeper) and a software selectable choice between LPT1, COM1& COM2 or floppy drive.
C
Other rear I/O options may also be available (including customer specific) but are not referred to
in this user’s handbook. For OEM quantities and compatibility with existing 2.11 backplanes etc.
RIO-C1 could be considered - this is identical to rear I/o (D) except that the VGA, COM and PS-2
mouse options are not available. In order to take full advantage of the rear I/O features, the
CompactPCI backplane needs to support them. Inova provides two standard versions; the first has
the rear rP2 connector on the Master CPU slot only while the other has all slots fitted with rP2
connectors.
Be aware that boards using the PXI bus will experience signal conflict if used with any (includes
non Inova boards) CPU offering rear I/O - Therefore, in such cases always select a CPU board
configuration without rear I/O. Also, for compatibility with older backplane revisions (2.11), rear
I/O (C) should be selected if indeed rear I/O is required. CPUs configured with rear I/O (D) will not
work!
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ICP-CM
Figure 1.21 ICP-CM Board Overview
Socket mPGA479M
for 600MHz or
1.3GHz Celeron M
Processor
32-bit and rear I/O
256MB or
1GByte on-
board DDR
SDRAM
IDE, USB 2.0, COM,
PS-2, Floppy + LPT
Interfaces
CompactFlash
Socket
USB
2.0
Fast
Ethernet
Host Bridge
Fast
Ethernet
AGP 4x Socket for
Inova Graphic Module
Ȣ
VGA, GigaST R,
TMDS ( DVI ) or
TFT etc.
Reset Button & Hot-Swap LED
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Product Overview
1.3 Software
®
1
1.31 Windows XP (Professional / Embedded)
Windows XP (Professional / Embedded) contains many new technologies and features designed
for businesses of all sizes and for users who demand the most from their computers. It integrates
the strengths of Windows 2000 (Professional), such as standards-based security, manageability
and reliability, with Plug and Play convenience, simplified user interfacing, and innovative support
services. This combination creates the best desktop operating system for businesses. Whether
Windows XP (Professional) is installed on a single computer or deployed throughout a worldwide
network, this new operating system increases computing power while lowering the cost of own-
ership for desktop computers.
1.32 Windows 2000 (Professional)
Windows 2000 is highly reliable and available 32-bit OS which provides support for USB devices
and permits connection of peripherals without the need to reboot the system. Unlike Windows NT
4.0, support is also provided for the IEEE1394a (FireWire) devices. Finally, secure, wireless commu-
nication between two Windows 2000-based computers is possible using the popular IrDA infrared
protocol.
Removable storage devices such as DVD and Device Bay are supported as are new display devices
such as Accelerated Graphics Port (AGP), multiple video cards and monitors, OpenGL 1.2, DirectX®
7.0 API, and Video Port Extensions. With Plug and Play, automatic installation of new hardware is
possible with only minimal configuration. More than 12,000 devices support this functionality.
1.33 Linux
Being a modern operating system, Linux executes a 32-bit architecture, uses pre-emptive multi-
tasking, has protected memory, supports multiple users, and has rich support for networking,
including TCP/IP. Linux was originally written for Intel’s 386 architecture, but now runs on a wide
variety of hardware platforms including the full x86 family of processors as well as Alpha, SPARC,
and PowerPC.
Linux’s architecture also creates a more reliable and inherently stable system through the use of
protected memory and pre-emptive multitasking. Protected memory prevents an error in one
application from bringing down the entire system, and genuine multitasking means that a bottle-
neck in one application does not hold up the entire system. Linux also maintains a very clean
separation between user processes and kernel processes. While other server class operating sys-
tems use protected memory this feature is prone to failure if faulty applications are allowed to
invade kernel space with their processes.
C
1.34 VentureCom
Hard, real-time scalability and embedded operation extensions are required for Windows NT by
HAL modification for deterministic interrupt handling at multiple priority levels. This approach
achieves response times in the µs range and reduces hardware resource requirements while main-
taining full compatibility with the enormous range of standard software and device drivers written
for the Windows NT operating system.
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ICP-CM
1.35 Windows CE
Microsoft® Windows CE is an operating system designed for a wide variety of embedded systems
and products, from hand-held PCs and consumer electronic devices to specialized industrial con-
trollers and embedded communications devices. The Windows CE operating system has proved
itself capable of handling the most demanding 32-bit embedded applications by bringing the full
power of the Microsoft's 32-bit programming and operating systems technology to the embed-
ded systems designer. Windows CE is actually a collection of operating system modules and com-
ponents that can be selected and configured to meet the needs of a specific embedded applica-
tion or product.
1.36 VxWorks
WindRiver’s run-time system solution is a high-performance RTOS with a scalable microkernel and
sophisticated networking facilities - like TCP/IP networking across various media.
The open architecture provides efficient support of PC-based architectures. Flexible, intertask com-
munication, µs interrupt handling, POSIX 1003.1b real-time extensions, fast and flexible I/O sys-
tem etc. are some of the many key features.
1.37 OS-9 x86
Microware’s real-time operating system has a track record that has been proved in the industrial/
embedded market and has continued to provide reliable intelligence to sophisticated applica-
tions. OS-9 x86’s flexibility, modularity and reliability in conjunction with a rich driver structure
allow its use in I/O intensive applications.
1.38 QNX
This solution ports the Win32 API to a QNX kernel. The Win32 API aims to define a standard for
developing open systems applications that are optimized to run on ‘Wintel’ platforms. This oper-
ating system evolves around a small microkernel RTOS that produces a protected-mode, POSIX-
certified API. Being fully modular and scalable, this technology creates the smallest footprint that
is beneficial to high-end server applications.
1.39 Jbed
Esmertec’s Jbed is a new generation of real-time operating system. Java-based innovation provides
unprecedented safety and ease of use without compromising resource efficiency (native processor
speed) or hard real-time performance. In addition, advanced features are implemented such as
modularity, hot updates, deadline-driven scheduling admission testing as well as a fast and pro-
ductive cross-development.
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Product Overview
1.4 Hardware
®
1
1.41 Block Diagram
Figure 1.41 Block Diagram
This block diagram is applicable to all Inova’s CM-basedCPUs. Components and/or functionality
may change without notice.
C
Note
32-bit with or without Rear I/O (RIO)
configurations are possible. User’s of
NI peripheral cards should check to
see whether signal conflict is possible
with the RIO option selected. If in
doubt, select the CPU version without
RIO. The universal PCI/PCI bridge
allows the CPU to exist as a Master or
Slave. Recognition is automatic
depending on the CPU’s physical
position within a CompactPCI system.
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ICP-CM
1.42 Connector Location
Figure 1.42 Connector Locations
1.43 Connector Description
Table 1.43 Connector Description
Connector
Description
J1, J2
J4
CompactPCI Interface Connector
AGP 4x for Optional Inova Graphic Piggyback
J6
10BaseT/100BaseTx Fast Ethernet Interface ETH2 - [SiS 900 - chipset]
10BaseT/100BaseTx Fast Ethernet Interface ETH1 - [i82551]
CompactFlash Socket (MicroDrive or Flash)
J7
J9
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Product Overview
Table 1.43 Continued
®
1
Connector
Description
J11
Internal USB (1.1) interface for additional USB devices (USB 5)
J12, J13, J14 Hard Disk module, Mouse, Keyboard, COM, FD, USB 2.0 and LPT1 interfaces
J15
External USB 2.0 interface (USB 1)
J17
VGA interface (soldered D-Sub for onboard Chipset or from AGP piggyback)
Reset button switch
SW1
1.44 Front-Panel Features
Table 1.44 Front Panels
Interface
Description & Location
2x RJ45 connector common to all CPU front-panels
USB (2.0) connector on all CPU front-panels (USB 1)
Space for 15-Pin high-density D-Sub connector on all CPU front-panels
Push-button reset on all CPU front-panels
Ethernet
USB
VGA
Reset
Extended Front Panel Options - 8HP & 12HP
Mouse &
Keyboard
Single PS-2 style connector
USB
Two USB 2.0 connectors (USB 2 & USB 3)
9-Pin D-Sub
COM11)
COM21)
LPT1
9-Pin D-Sub
25-Pin D-Sub integrated within the 12HP panel only
Standard (notebook) header for slim-line floppy interface
C
Floppy
Note
1) The ICP-CM Hard Disk carrier -
ICP-HD3 (Refer to Appendix A) has
jumper selectable COM configurations
- either RS232 or RS485
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ICP-CM
Figure 1.44 Front-Panel Options
The front-panels shown in Figure 1.44 show the tremendous flexibility built into Inova’s CPU
concept. From left, the standard CPU is 4TE with dual Fast Ethernet, USB (2.0) and VGA graphic
Ȣ
connections. If, instead of VGA graphics, PanelLink or GigaST R is required then an AGP piggy-
back is installed on J4 for this purpose. TFT graphics are realised in a similar way except the front-
panel will be cut away (to the right of the VGA connector) to permit passage of the flat-band
ribbon cables.
If the application requires a PS/2 mouse, PS/2 keyboard, floppy, COM or LPT ports or if the CPU is
equipped with a hard disk, IDE FLASH or an adapter that accesses other devices attached to this
primary IDE channel, then an 8TE front-panel is selected. Both COM ports (jumper selectable to
be RS232 or RS485) are installed on Inova’s ICP-HD-3 carrier board as are the interfaces for the LPT
and slim-line FD.
The LPT interface is available on a dedicated panel shown to the right of Figure 1.44.
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1.45 Interface Positions
®
Figure 1.45 Interfaces
1
C
Figure 1.45 shows the typical positioning of the front panel extension modules for mouse, key-
board, COM1, COM2, and LPT interfaces.
Note
A hard disk, if installed, will generally
be fitted to the piggyback containing
the combined PS-2 mouse / keyboard,
USB2.0, COM1 and COM2 interfaces.
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ICP-CM
1.46 Construction - 4HP Standard CPU
This standard CPU configuration comprises:-
{
Passively cooled base with chipset VGA graphics, dual Fast Ethernet and single USB
2.0 interface for mouse, keyboard, FD, CD-ROM etc. The minimum airflow requirements
must be compatible with the selected ‘processor speed, CPU damage could result otherwise !
Figure 1.46 Construction of CPU with Heat-Sink Assembly
F
G
D
D
G
D
E
D
E
D
E
D
E
H
G
H
G
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Product Overview
1.47 Construction - 8HP Standard CPU
®
This standard CPU configuration comprises:-
1
{
Passively cooled base with chipset VGA graphics, dual Fast Ethernet, three USB
2.0 interfaces, combined PS-2 mouse / keyboard, COM1 and COM2 interfaces. Behind the
extended front-panel is a platform for any IDE HD or Flash device with additional interfac-
ing for FD and LPT - refer to Appendix A for further information. The minimum airflow
requirements must be matched with the selected ‘processor speed, CPU damage could
result otherwise !
Figure 1.47 Construction of CPU with Heat-Sink Assembly
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ICP-CM
1.48 Construction - 8HP Standard CPU with AGP
This standard CPU configuration comprises:-
{
Passively cooled base with AGP 4x Radeon R7000-based graphics, dual Fast Ether-
net, three USB 2.0 interfaces, combined PS-2 mouse / keyboard, COM1 and COM2 inter-
faces. Behind the extended front-panel is a platform for any IDE HD or Flash device with
additional interfacing for FD and LPT - refer to Appendix A for further information. The
minimum airflow requirements must be matched with the selected ‘processor speed, CPU
damage could result otherwise !
Figure 1.48 Construction of CPU with Heat-Sink Assembly
Note:
The dedicated carrier board - ICP-HD-3 is
mounted to the baseboard in exactly the
same fashion as illustrated in figure 1.47.
It has been omitted here for clarity.
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1.49 Power Requirements
®
This CPU board is a high-performance, low-power device and, as such, requires voltage, current
and power timing as defined in table 1.49 for correct operation. The Inova >70W PSUs fulfil these
requirements and reference should be made to this products’ data sheet and user’s manual.
1
Table 1.49 ICP-CM Power Reqirements
Supply Voltages
Signal
+5V
Voltage
IMAX
2.5A @ 600MHz
5.2A @ 1300MHz
5.0V +5%/-3%
3.3V +5%/-3%
+3.3V
V I/O
1.8A
0.5A
5.0V +5%/-3% or
3.3V +5%/-3%
Power Dissipation
Frequency
600MHz
PTOT (Typ.)
PTOT (Max.)
13.7W
17.5W
1300MHz
19.5W
31.3W
Power Sequencing
This CPU needs both the 5V and 3.3V lines to be switched simultaneously within a max.
allowable skew of 2ms. VI/O is assumed to be connected to either the +5V or +3.3V directly.
Symbol
tMIN
tMAX
-2ms
+2ms
t+5V_rising _to_+3.3V_rising
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ICP-CM
1.50 Power Consumption
The illustration provided in figure 1.50 is for reference only and serves to show the ‘typical-maxi-
mum’ power consumption of the ICP-CM CPU. Variations in ‘processor manufacture and onboard
silicon make accurate testing impossible and hence, the figures shown in this illustration are sub-
ject to fluctuation.
Note:
There is no such thing as a typical
application and so, the CPU power
consumption was measured with the
‘processor in idle state, in BIOS mode
(i.e. the OS power management
features were not being utilised) and
software stressed to 100%
To stress this CPU, the following software was installed:
Ī Microsoft Windows XP SP1,
Ī DirectX 9.0b,
Ī ATI Catalyst 3.9 video driver
on a 20GByte HD mounted on the baseboard (8HP with HD carrier) with 256Mbyte PC2100
memory and including the Radeon R7000 AGP piggyback with 32MByte video memory.
Figure 1.50 ICP-CM Power Consumption
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1.51 Thermal Considerations
®
Being a passively-cooled design, a purpose-built, thermally optimized heat-sink is all that removes
the heat from the CPU. The effective surface area of the radiator unit mounted on the single slot
(4HP) CPU version is less that of the 8HP CPU and therefore, necessitates more airflow (or air
circulation) to keep it cool. As a guideline, the figures published in table 1.51 show the minimum
airflow required to maintain stable operation. As the ambient temperature surrounding the CPU
increases, so the airflow must increase.
1
Conclusions that can be drawn from this table are:
Ī Single-slot CPUs should not be integrated in applications where the environmental temp. ex-
ceeds 65°C
Ī CPUs intended for use in applications running at high operational temperatures ~ 85°C should
be clocked at 600MHz. At greater speeds, the volume of air required to cool the core
becomes so great that conventional cooling fans cannot be used.
Table 1.51 ICP-CM Airflow Requirements
Ambient Air Temperature
Frequency
≤ 55°C
≤ 65°C
≤ 75°C
≤ 85°C
8HP
4HP
8HP
4HP
8HP
4HP
8HP
4HP
without
forced
cooling
0.15
m/s
0.4
m/s
0.5
m/s
0.5
m/s
0.6
m/s
0.75
m/s
600MHz
0.35
m/s
0.55
m/s
0.6
m/s
0.75
m/s
1300MHz
Key:
Not recommended
Note:
C
If the ambient temperature is greater
than 50°C, systems utilizing the benefit of
this Celeron M CPU cannot operate with
a standard hard-disk, floppy or CD-ROM
etc.
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ICP-CM
Configuration
®
Configuration
2
Configuration Con-
tents
2.0 Memory Map........................... 2-2
Figure 2.00 System Architecture ................................................................................................. 2-2
2.1 I/O Mapped Peripherals............. 2-4
Table 2.10 Legacy I/O Map (ISA Compatible) ............................................................................ 2-4
Table 2.10 Legacy I/O Map (ISA Compatible) Contd. ................................................................. 2-5
2.2 Memory Mapped Peripherals ..... 2-6
2.3 Interrupt Routing .................... 2-6
Table 2.30 PC-AT Interrupt Definitions ....................................................................................... 2-7
2.4 DMA Channel Descriptions ....... 2-7
Table 2.40 DMA Channel Description ........................................................................................ 2-7
2.5 Inova CM SMB Devices ............ 2-8
Table 2.50 SMB Devices............................................................................................................. 2-8
2.6 Inova CM PCI Device List ......... 2-9
Table 2.60 Legacy I/O Map (ISA Compatible) ............................................................................ 2-9
2.7 Interrupt Configuration .......... 2-10
Table 2.70 CompactPCI Bus Interrupts ..................................................................................... 2-10
2.8 Timer / Counter..................... 2-11
2.9 Watchdog............................. 2-11
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2.0 Memory Map
Figure 2.00 System Architecture
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Configuration
®
2
Note:
96kBytes are reserved for option ROM
space:
- USB Legacy (32kByte)
- Ethernet Boot (16kByte)
- PXE Boot (48kByte)
In addition, 3rd party devices can also
have their ‘space’ here such as addi-
tional networking cards, SCSI or
FireWire etc. The total available space
cannot exceed 96kByte.
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Configuration
ICP-CM
2.1 I/O Mapped Peripherals
The original PC-XT and PC-AT desktop computer (ISA bus) specification allows for 10-bit I/O
addressed peripherals. This permits peripheral boards to be I/O mapped from 0h to 3FFh.
CompactPCI systems permit the full 16-bit addressing capability of the Intel 80x86 ‘processors,
from 0h to 0FFFFh.
All Inova CPU boards include peripheral devices requiring I/O address space on board and hence
the BIOS automatically assigns the I/O address required by peripheral boards and PCI devices at
boot time based on the requirements of each device. The assigned addresses can be determined
by reading the configuration address space registers using special software tools.
Table 2.10 Legacy I/O Map (ISA Compatible)
I/O Address
$000 - $00F
$020 - $021
$040 - $043
$060
Description
8237 DMA controller #1
8259 Master Interrupt Controller
8254 Programmable Interval Timer #1
8042 Keyboard Controller
NMI Status
$061
$064
8042 Keyboard Controller
CMOS RAM, NMI Mask Reg., RTC
Debug
$070 - $071
$080
$081 - $08B
$0A0 - $0A1
$0C0 - $0DF
$0F0 - $0FF
$170 - $177
$1F0 - $1F7
$2F8 - $2FF
Low DMA page registers
8259 Slave Interrupt Controller
8237 DMA Controller #2
Coprocessor
*) Secondary Hard Disk Controller
*) Primary Hard Disk Controller
*) Serial Port (COM2)
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Configuration
Table 2.10 Legacy I/O Map (ISA Compatible) Contd.
®
I/O Address
$376-$377
Description
*) Secondary Hard Disk Controller
*) Parallel Port (LPT1) - Bi-Directional
*) Floppy Disk Controller
$378 - $37F
$3F0 - $3F7
$3F8 - $3FF
$3F6 - $3F7
$481 — $48B
$4D0 — $4D1
$778 - $77F
2
*) Serial Port (COM1)
*) Primary Hard Disk Controller
DMA High Page Register
Interrupt Unit Edge/Level Control Registers
LPT1 (ECP only)
PCI Configuration Address
(DWORD Access Only)
$CF8
$CFC
PCI Configuration Data
(DWORD Access Only)
Note:
*) Denotes Plug ‘n’ Play devices that
are configured during the BIOS POST.
Values shown are ISA compatible I/O
addresses for reference only.
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Configuration
ICP-CM
2.2 Memory Mapped Peripherals
PC-AT desktop computers (ISA bus) allow 24-bit memory addressed peripherals. This decoding
permits peripheral boards to be mapped in the Intel 80x86 memory map from 0h to 0FFFFFFh.
Inova’s CompactPCI systems allow the full 32-bit addressing capability of the Intel Pentium 4
range of ‘processors so that memory mapped peripheral devices may be mapped locally to the
‘processor board at any location in the memory map not being used by other devices (e.g. system
RAM.)
The BIOS automatically assigns memory addresses required by peripheral boards and PCI devices
at boot time based on the requirements of each device. The assigned addresses can be deter-
mined by reading the configuration address space registers using PCI software tools.
Note:
Devices not located on the CPU side of
the PCI/PCI bridge are not normally
accessible by DOS.
2.3 Interrupt Routing
The IBM-compatible architecture includes one (PC-XT) or two (PC-AT) programmable interrupt
controllers (Intel 8259A-compatible ‘PICs’) configured to set the priority of interrupt requests to
the CPU.
In the PC-AT architecture, one PIC is programmed as the ‘master’ with one input (IRQ2) being the
‘cascaded’ interrupt from the second ‘slave’ PIC.
This configuration allows for a total of 15 interrupt sources to the CPU. Table 2.3 shows the
interrupts with their corresponding vectors and sources as defined for AT PCs.
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ICP-CM
Configuration
Table 2.30 PC-AT Interrupt Definitions
®
Interrupt Request Interrupt Vector
Function/Assignment
Timer
IRQ0
IRQ1
IRQ2
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
70h
71h
72h
73h
74h
75h
76h
77h
Keyboard
2
Slave 8259
COM 2
IRQ31)
IRQ41)
COM 1
IRQ51)
IRQ6
Free for PCI
Floppy
IRQ71)
IRQ8
LPT1
Real-Time Clock
Free for PCI
Free for PCI
Free for PCI
Mouse
IRQ91)
IRQ10
IRQ111)
IRQ12
IRQ13
Co-processor
Hard Disk (IDE 0)
Hard Disk (IDE 1)
IRQ141)
IRQ151)
1) Entries may be reserved for ISA devices with the BIOS
2.4 DMA Channel Descriptions
The ICP-CM CPU can access the devices shown in table 2.4 through the specified DMA channels.
C
Table 2.40 DMA Channel Description
DMA Channel
Description
0
1
2
3
-
-
Floppy
LPT1 (ECP only)
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Configuration
ICP-CM
2.5 Inova CM SMB Devices
Table 2.50 shows the addressing of the SMB (System Management Bus) Devices
Table 2.50 SMB Devices
Address b[7:1]
0101 100
Device
LM87 (Temperature Monitor)
1010 000
EEPROM SPD DDR Bank 0
1010 101
EEPROM TOP EXTENSION (e.g. ICP-HD-3) ID
EEPROM RIO PANEL ID
1010 110
1010 111
EEPROM Vital Product Data / General Purpose
ICS952001 (Timing Hub)
1101 001
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ICP-CM
Configuration
2.6 Inova CM PCI Device List
®
Table 2.60 shows the available PCI devices both on-board and off-board (CompactPCI backplane).
It should be noted that the interrupt routing assumes a standard Inova backplane configuration
with a right-hand system slot.
Table 2.60 Legacy I/O Map (ISA Compatible)
2
Bus Device Function
No. Number Number
Device /
Vendor ID
Description
IRQ
0
0
0
0
0
0
0
0
0
0
0
0
1
2
2
2
2
2
2
2
0x00
0x01
0x02
0x03
0x03
0x03
0x03
0x02
0x02
0x04
0x08
0x09
0x00
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x00
0x00
0x00
0x00
0x01
0x02
0x03
0x05
0x07
0x00
0x00
0x00
0x00
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0651 1039 SiS651 Host Bridge
0001 1039 SiS651 Virtual PPB
0008 1039 SiS962 LPC
7001 1039 SiS962 USB0 OHCI
7001 1039 SiS962 USB1 OHCI
7001 1039 SiS962 USB2 OHCI
7002 1039 SiS962 USB0 EHCI
5518 1039 SiS962 IDE
7012 1039 SiS962 B/S Audio
0900 1039 SiS962 LAN
INTA# 0020 3388 PCI-PCI Bridge
INTB# 1229 8086 LAN 82551 (Fast Ethernet)
INTA# 6325 1039 AGP
CompactPCI Slot 8 1)
INTB#
INTC#
INTD#
INTA#
INTB#
INTC#
INTD#
CompactPCI Slot 7
CompactPCI Slot 6
C
CompactPCI Slot 5
CompactPCI Slot 4
CompactPCI Slot 3
CompactPCI Slot 2 [next to Master]
Bus No. 0 = On board; Bus No. 1 = AGP; Bus No. 2 = CompactPCI Bus
1) CompactPCI backplane numeration is based on a 7-slot backplane and refers to the logical (and
not physical) slot number
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ICP-CM
2.7 Interrupt Configuration
The CompactPCI specification defines a total of six interrupt signals on the backplane. INTA#
through INTD# are used to route interrupts from the CompactPCI boards to the PIC on the ‘proc-
essor board. The interrupt request level generated by the device depends on the backplane slot
number which the board is plugged into, and the interrupt signal which is driven by the particular
PCI device.
Note:
CompactPCI interrupts may be shared
by multiple sources
Table 2.70 CompactPCI Bus Interrupts
CompactPCI
Bus Interrupts
CompactPCI
Bus Interrupts
INTA#
INTB#
INTC#
INTD#
INTP
( IRQ14 )
(IRQ15) or Serialized
Interrupt -
INTS
Refer to BIOS
Documentation
ENUM#
Routed by BIOS
Note:
Interrupts INTA through INTS and
ENUM are System Master CPU inputs.
INTA and ENUM are outputs if the
CPU is in Peripheral Mode.
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ICP-CM
Configuration
2.8 Timer / Counter
®
The IBM-compatible architecture configures the programmable timer / counter (Intel 8254-com-
patible) devices for system-specific functions as shown in Table 2.80.
The BIOS programs Timer 0 to generate an interrupt approximately every 55ms (18.2 times per
second.) This interrupt, known as the system timer tick, updates the BIOS clock and turns off the
floppy disk motor drive after a few seconds of inactivity for example.
2
The BIOS featured in Inova’s CPUs programs the system timer tick for PC compatibility. The inter-
rupt generated by the timer creates an interrupt request on IRQ0 of the programmable interrupt
controller (PIC) which is serviced by the CPU as interrupt vector 08h.
In addition, Timer 1 and Timer 2 are also initialised by the BIOS as necessary for the specific
‘processor board functions.
Table 2.80 Timer and Counter Functions
Timer
Timer 0
Timer 1
Timer 2
Function/Assignment
System Timer, Periodic Interrupt (55 ms)
SDRAM Refresh
Speaker Frequency Generator
2.9 Watchdog
Two independent watchdog timers are implemented in the ICP-CM. The first timer, residing in the
SiS962 South-Bridge, has a range from 4ms to 255 hours and can issue either a Reset or SMI
(System Management Interrupt) upon expiry. The second timer in the Super I/O controller ranges
from 1 minute to 255 minutes and issues either a Reset, IRQ or SMI upon timeout.
C
Note:
An OS-specific driver is required to
configure the watchdog timer. Please
refer to the Inova WWW support
pages (http://www.inova-
computers.de/web/support/public/
index.html) for the latest versions or
contact Inova hotline support directly
for advice .
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ICP-CM
Interfaces
®
Interfaces
Interfaces Contents
3
3.0 CompactPCI J1/J2 Connectors . 3-2
3.01 CompactPCI Connector Naming.............................................................. 3-2
Figure 3.01 Naming Convention as per PICMG 2.0 R3.0 Specification ........................................ 3-2
3.02 CompactPCI J1 Connector ....................................................................... 3-2
Figure 3.02 J1- 32-Bit CompactPCI Bus Interface Connector ....................................................... 3-2
3.03 ICP-PM Connector J1 and J2 .................................................................... 3-2
Table 3.03 32-Bit CompactPCI J1 Pin Assignment....................................................................... 3-3
Table 3.04 32-Bit CompactPCI J2 Pin Assignment (Std. with Rear I/O (D)).................................. 3-4
Table 3.04 32-Bit CompactPCI J2 Pin Assignment (Std. - with Rear I/O (D)) - Contd. .................. 3-5
Table 3.05 Inova’s ICP-CM Rear I/O J2 (CPU) Integration ........................................................... 3-6
3.1 CompactPCI Backplane ............ 3-7
Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot .................................. 3-8
3.2 Interfaces............................... 3-9
3.21 J6 & J7 Ethernet ....................................................................................... 3-9
Figure 3.21 RJ45 Pinout ............................................................................................................. 3-9
Table 3.21 Ethernet Standards & Connector Signals ................................................................... 3-9
3.22 J17 VGA Interface ................................................................................... 3-10
3.23 Graphic Features (Chipset) ..................................................................... 3-10
Table 3.23a highlights just some of the features of the standard integrated video controller. ..... 3-10
Figure 3.23 High-Density D-Sub VGA Interface Pinout .............................................................. 3-11
Table 3.23b Video Output Connector Signals ........................................................................... 3-11
3.24 J19 USB Interface ................................................................................... 3-12
Figure 3.24 USB Interface Pinout.............................................................................................. 3-12
Table 3.24 USB Connector Signals ........................................................................................... 3-12
C
3.25 J10 Hot-Swap Interface .......................................................................... 3-13
3.26 SW1 Reset Button .................................................................................. 3-13
3.27 J9 CompactFlash Interface...................................................................... 3-13
3.28 Connecting the CM to the Inova ICP-HD3(-ND) .................................... 3-13
3.29 Connecting the CM to the Inova IPB-FPE12 ........................................... 3-13
3.30 Connecting the CM to a Slim-Line Floppy-Disk ...................................... 3-13
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ICP-CM
3.0 CompactPCI J1/J2 Connectors
The CompactPCI standard is electrically identical to the PCI local bus standard but has been en-
hanced to support rugged industrial environments and up to 8 slots. The standard is based upon
a 3U board size and uses a rugged pin-in-socket hard 2mm connector (IEC-1076-4-101.)
3.01 CompactPCI Connector Naming
Figure 3.01 Naming Convention as per PICMG 2.0 R3.0 Specification
3.02 CompactPCI J1 Connector
Figure 3.02 J1- 32-Bit CompactPCI Bus Interface Connector
1
11
15
25
e
d
c
b
a
PCB
3.03 ICP-PM Connector J1 and J2
Inova’s ICP-CM CPU board has been designed as a 32-bit (or 64-bit) system slot device able to
operate in either +5V or +3.3V (I/O) systems. The CompactPCI backplane connector is keyed
accordingly (yellow for +3.3V and blue for +5V.)
Note:
Do not remove the keys. An I/O board
operating at 5.0V and keyed accordingly
will cause a 3.3V configured system to fail
if the keys are removed.
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Table 3.03 32-Bit CompactPCI J1 Pin Assignment
®
Pin Nr
J1-25
J1-24
J1-23
J1-22
J1-21
J1-20
J1-19
J1-18
J1-17
J1-16
J1-15
J1-14
J1-13
J1-12
J1-11
J1-10
J1-09
J1-08
J1-07
J1-06
J1-05
J1-04
J1-03
J1-02
J1-01
Row A
+5V
Row B
Row C
ENUM#
V( I / O )
AD[3]
Row D
Row E
+5V
REQ64#
+3.3V
AD[0]
+5V
ACK64#
AD[1]
+5V
AD[4]
+3.3V
AD[2]
AD[5]
AD[7]
GND
+3.3V
AD[6]
M66EN
AD[11]
GND
+3.3V
AD[9]
AD[8]
C / BE[0]#
AD[10]
3
AD[12]
+3.3V
GND
V( I / O )
AD[14]
+3.3V
AD[15]
GND
AD[13]
SERR#
+3.3V
PAR
C / BE[1]#
PERR#
LOCK#
TRDY#
IPMB-SCL
GND
IPMB-SDA
V( I / O )
IRDY#
GND
DEVSEL#
+3.3V
STOP#
GND
FRAME#
KEY AREA
AD[18]
AD[21]
AD[17]
GND
AD[16]
+3.3V
GND
AD[20]
GND
AD[25]
GND
CLK0
GND
INTP
+5V
C / BE[2]#
AD[19]
AD[22]
AD[24]
AD[27]
AD[31]
GNT0#
INTS
C / BE[3] GND (IDSEL)
AD[23]
V( I / O )
AD[28]
+3.3V
AD[26]
AD[30]
REQ0#
-
GND
AD[29]
GND
-
RST#
C
UPS1)
INTA#
GND
INTB#
+5V
-
V( I / O )
INTC#
TMS
INTD#
TD1
TCK
+5V
TD0
TRST#
+12V
+5V
1) Reserved for use for Inova’s Uninterruptible Power Supply (UPS)
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ICP-CM
Table 3.04 32-Bit CompactPCI J2 Pin Assignment (Std. with Rear I/O (D))
Pin Nr
J2-22
Row A
(GA4)
CLK6
Row B
(GA3)
GND
Row C
(GA2)
Row D
(GA1)
Row E
(GA0)
J2-21
ETH1_TXF+
ATA_A0
ETH1_TXF-
GND
ATA_CS0#
ATA_RST#
ETH1_RXF-
J2-20
CLK5
GND
J2-19
GND
GND
ATA_A1
ETH1_RXF+
LPT_STB#
-
LPT_PE
FD_WRDATA#
COM1_RXD
J2-18
J2-17
J2-16
J2-15
J2-14
J2-13
J2-12
J2-11
J2-10
J2-09
J2-08
ATA_A2
PRST#
GND
REQ6#
GND
ATA_CS1#
GNT6#
COM1_TXD
LPT_AFD#
FD_DENSEL VGA_VSYNC
COM1_CTS
LPT_D0
FD_INDEX#
COM1_RTS
LPT_ACK#
FD_DR1#
COM1_DCD
DEG#
KB_CLK
GNT5#
LPT_ERR#
FD_HDSEL#
COM1_DSR
GND
FAL#
REQ5#
VGA_R
ATA_D1
GND
LPT_D1
FD_TRK0#
COM1_DTR
LPT_SLCT
FD_WGATE#
COM1_RI
+5V (1.5A)
V(I/O)
ATA_D0
ATA_D2
ATA_D3
ATA_D5
ATA_D6
ATA_D8
ATA_D9
LPT_INIT
FD_DIR#
COM2_TXD
VGA_HSYNC
ATA_IOW#
GND
LPT_D2
FD_WP#
COM2_RXD
USB4_D+
SMB_DAT
USB4_D-
V(I/O)
LPT_SLCTIN
FD_STEP#
COM2_CTS
ATA_D4
VGA_G
ATA_D7
GND
LPT_D3
FD_RDATA#
COM2_RTS
ATA_IOR#
PM_DAT
LPT_D4
FD_DSKCHG#
COM2_DCD
LPT_D5
FD_MSEN0
COM2_DSR
ATA_IRQ15 ATA_DMARQ
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Interfaces
Table 3.04 32-Bit CompactPCI J2 Pin Assignment (Std. - with Rear I/O (D)) - Contd.
®
Pin Nr
Row A
Row B
Row C
Row D
Row E
LPT_BUSY
FD_MTR1#
COM2_DTR
J2-07
PM_CLK
SMB_CLK
ATA_D10
ATA_D11
LPT_D6
FD_DRATE0
COM2_RI
J2-06
J2-05
KB_DAT ATA_DMACK
VGA_B
ATA_D12
ATA_D14
LPT_D7
FD_MSEN1
-
3
64EN#
V(I/O)
ATA_D13
ATA_IORDY
#
GNT3#
SYSEN#
REQ1#
SPEAKER4)
GND
J2-04
J2-03
J2-02
J2-01
V(I/O)
CLK4
CLK2
CLK1
GND
ATA_D15
GNT4#
REQ3#
REQ2#
REQ4#
GNT2#
GNT1#
CLK3
GND
C
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ICP-CM
Table 3.05 Inova’s ICP-CM Rear I/O J2 (CPU) Integration
Option
RIO(C1)
No
RIO(D)
Yes
VGA
Fast Ethernet
Intel 82551
Yes
Intel 82551
Yes
USB 1.1
PS-2 Mouse & Keyboard
2nd IDE Channel
Reset & Beeper
Keyboard Only
Yes
Yes
Yes
Yes
Yes
LPT1
Software Selectable
Software Selectable
Software Selectable
Software Selectable
Software Selectable
Software Selectable
COM1 & COM2
Floppy Disk (A or B)
The rear I/O options described here do not detract from the latest PICMG 2.0 R3.0 specification.
1.) The VGA option in table 3.05 is from the chipset or mounted AGP piggyback - chipset video
should not be used in parallel with the front I/O option. Doing could cause possible damage to
the CPU board. If both front and rear VGA are required, then the AGP piggyback graphic option
should be used which may also permit different video information to be displayed.
2.) The single channel Fast Ethernet option in table 3.05 is ETH 1 on the front-panel i.e. the
dedicated Intel 82551 controller. If the rear I/O option is used then the front-panel connection
must not be used. Doing so will disrupt the communication leading to spurious results.
3.) If the mouse, keyboard, LPT or COM ports are used in rear I/O applications then they should
not be used from the front-panel. Communicating from both mouse and keyboard sources is
physically possible but is not recommended! The front panel COM port connections are disabled
If using the rear I/O COM port option.
4.) The CPU boasts a number of USB connection possibilities - one USB 2.0 is on the front-panel,
one (USB 1.1) is just behind the panel for local device connection (custom), two (USB 2.0) are
embedded within the hard disk carrier and a final USB (1.1) port is routed to the rear I/O panel.
Note:
64-bit configurations cannot have rear
I/O! Version (D) is preferred and is there-
fore the standard configuration. Transi-
tion modules connect to the backplane
and provide the physical interfaces.
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Interfaces
3.1 CompactPCI Backplane
®
The form factor defined for CompactPCI boards is based upon the Eurocard industry standard.
Both 3U (100 mm by 160 mm) and 6U (233 mm by 100 mm) board sizes are defined. A Com-
pactPCI system is composed of up to eight CompactPCI cards. The CompactPCI backplane con-
sists of one System Slot, and up to seven Peripheral Slots.
The System Slot provides arbitration, clock distribution, and reset functions for all boards on the
bus. The System Slot is responsible for performing system initialization by managing each local
board’s IDSEL signal.
3
Physically, the System Slot may be located at either end of the backplane but Inova have placed
theirs on the right to cater for physical expansion due to heat-sink, hard disk, extended function-
ality etc. The Peripheral Slots may contain simple boards, intelligent slaves, or PCI bus masters.
Note:
Inova’s 3U CompactPCI Celeron M
CPU boards can be used as either
master or slave boards i.e. occupying
either the system slot or the peripheral
slot. The PCI / PCI bridge automati-
cally detects the CPU location within a
system.
Note:
Older backplane revisions (rev. 2.11)
cannot be used with Inova CPUs config-
ured for rear I/O (D). Attempting to do so
will cause the boot sequence to fail.
C
When installing the CPU in environments
where PXI peripheral boards are being
used, CPU versions without rear I/O must
be used. Otherwise, signal conflict will
occur on the J2 interface.
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ICP-CM
Figure 3.10 Inova’s 32-Bit CompactPCI 8-Slot Backplane - RH System Slot
Note:
The logical slots are different to the
physical slots. The slot marked with the
‘̅‘ is the System Slot and always as-
signed logical ‘1’. The neighbouring slot
is logical ‘2’!
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Interfaces
3.2 Interfaces
®
3.21 J6 & J7 Ethernet
J6 is a Fast Ethernet interface from the SiS chipset while J7 [ETH1] is an additional Fast Ethernet
from the dedicated on-board controller. Both RJ45 interfaces are available as standard on the CPU
front-panel and provide support for 10BaseT and 100BaseTX twisted pair standards.
Figure 3.21 RJ45 Pinout
3
Note:
Activity
Link
1
Users taking advantage of the CPU’s rear
I/O options are advised not to use the
front-panel interface [ETH1] if the rear
interface is being used. Possible damage
to the board could occur and data
integrity cannot be assured.
8
Table 3.21 Ethernet Standards & Connector Signals
Standard
Data Rate
Cable
Max. Length
IEEE802.3 10Base-T
Ethernet
10Mbit/2
2-pair Cat-5
100m
IEEE802.3u 100Base-Tx
Fast Ethernet
100Mbit/s
2-pair Cat-5
100m
Signal Description
Ethernet / Fast Ethernet
Pin No.
1
2
3
4
5
6
7
8
TX0+
C
TX0-
RX0+
RX0-
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ICP-CM
3.22 J17 VGA Interface
J17 is available on the CPU front-panel if this option is required and if this position is not already
Ȣ
occupied by an AGP piggyback for PanelLink (TFT) or GigaST R communication. The 15-pin
high-density D-Sub connector forms the physical interface for the video on the ICP-CM which is
integrated within the chipset.
The amount of graphic memory allocated to the chipset video option is defined in BIOS. Vesa
resolutions up to 2048 x 1536 pixels with 32-bit colour depth are supported. Hence the full VGA,
SVGA, XGA, SXGA, UXGA, HDTV and QXGA scales are covered.
3.23 Graphic Features (Chipset)
Table 3.23a highlights just some of the features of the standard integrated video controller.
Feature
Description
Supports single video windows with overlay function
Supports RGB555, RGB565, YUV422, and YUV420 video formats
Supports DVD sub-picture playback overlay
2x 120x128 video playback line buffers to support 1920x1080 video
Supports Direct Draw Drivers
Video Accelerator
Built-in 64x128 CRT FIFOs to support ultra high res. graphics
Programmable 24-bit true-colour RAMDAC up to 333MHz pixel clk
MPEG II video playback
High Integration
Built-in TV encoder interface
Supports 333MHz clock
Resolution, Colour & Frame Rate Supports VESA standard super high resolution graphics modes
Supports low-resolution modes (320x240, 512x384, 400x300)
Supports VESA Display Power Management Signalling
Power Management
Supports clock throttling for 2D engine and 3D engine
Multimedia Application
Supports RAMDAC snoop for multimedia applications
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Figure 3.23 High-Density D-Sub VGA Interface Pinout
®
5
1
10
6
15
11
Table 3.23b Video Output Connector Signals
3
Pin No.
Signal
1
2
3
4
Analog RED
Analog GREEN
Analog BLUE
N/C
5, 6, 7, 8 CRT Ground
9
+5V (DDC)
CRT Ground
N/C
10
11
12
13
14
15
DDC-SDA
HSYNC
VSYNC
DDC-SCL
C
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Interfaces
ICP-CM
3.24 J19 USB Interface
J19 is located as standard on the front panel. All standard USB 2.0 and 1.1 compatible devices can
be connected to this interface.
Figure 3.24 USB Interface Pinout
1
2
3
4
Table 3.24 USB Connector Signals
Pin No.
Signal
1
2
3
4
+5V
USB P0-
USB P0+
GND
Page3-12
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ICP-CM
Interfaces
3.25 J10 Hot-Swap Interface
®
This PCB-level interface is used for the front-panel integrated micro-switch and blue LED in ac-
cordance with the PICMG 2.1 R2.0 specifications.
3.26 SW1 Reset Button
The reset button allows the CPU to be reset in the event that it ‘hangs’ Performing a reset in this
manner is known as a ‘warm’ start as power is not removed from the peripherals (IDE etc.)
3
3.27 J9 CompactFlash Interface
CompactFlash™ cards are designed with flash technology, a nonvolatile storage solution that
does not require a battery to retain data indefinitely. CompactFlash storage cards are solid state,
meaning they contain no moving parts and their low power consumption means that they con-
sume only five percent the power required by small disk drives.
J9 is the standard CompactFlash interface and needs no further explanation.
3.28 Connecting the CM to the Inova ICP-HD3(-ND)
Appendix A provides more information on the ICP-HD3(-ND) and its derivatives. For the sake of
completeness however, the ICP-HD3(-ND) must only be attached / detached to / from the CM
base board without power applied i.e. with the CPU removed from the CompactPCI environment.
Since there aren’t any flat-band cables or similar, installation is remarkably simple. The whole
module plugs into the mating J12, J13 and J14 connectors.
3.29 Connecting the CM to the Inova IPB-FPE12
C
Appendix B provides more detailed information on the IPB-FPE12 module. However, for the sake
of completeness, the IPB-FPE12 connects directly to the ICP-HD3(-ND) module via a flex-cable.
There isn’t a direct connection possibility on the CPU base board itself.
3.30 Connecting the CM to a Slim-Line Floppy-Disk
Slim-line floppy disks connect directly to the ICP-HD3(-ND) via the standard header.
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Interfaces
ICP-CM
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Page3-14
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Appendix A
ICP-HD-3
®
ICP-HD-3
ICP-HD-3 Contents
A1 ICP-HD-3(-ND) CPU Extension.. A-2
A1.1 ICP-HD-3(-ND) Front-Panels (8HP or 12HP) ............................................. A-2
Figure A1.1 ICP-HD-3(-ND) CPU Front-Panels ............................................................................ A-2
A1.2 IDE Carrier Board ICP-HD-3(-ND) ............................................................. A-3
Figure A1.2 Interface Location of the ICP-HD-3(-ND) Module ..................................................... A-3
Table A1.2 Interface Description of the ICP-HD-3(-ND) Module .................................................. A-4
A2 ICP-HD-3(-ND) Interfaces......... A-5
A2.1 COM1 & COM2 Interfaces ...................................................................... A-5
Figure A2.1 COM1 & COM2 Interface Pinout ............................................................................. A-5
Table A2.1 COM1 & COM2 Connector Signals........................................................................... A-5
A2.2 Mouse & Keyboard Interfaces .................................................................. A-6
Figure A2.2 Mouse & Keyboard Interface Pinout ........................................................................ A-6
Table A2.2 Mouse & Keyboard Connector Signals....................................................................... A-6
Table A2.3 USB Connector Signals ............................................................................................. A-7
A2.3 USB 2.0 Interfaces .................................................................................... A-7
Figure A2.3 USB Interface Pinout................................................................................................ A-7
A2.4 EIDE Interface .......................................................................................... A-8
A2.5 Slim-Line Floppy Disk Interface................................................................. A-8
A
C
ICP-PM/CMAppendix-A
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ICP-HD-3
Appendix A
A1 ICP-HD-3(-ND) CPU Extension
Combined PS-2 mouse / keyboard, USB (2.0), COM ports, LPT, mass storage and slim-line FD
interfaces are supplied on the ICP-HD-3(-ND) - a CPU add-on board. Two versions exist - one is
supplied with a hard disk and one without. Both versions are functionally identical. The name
extension ‘-ND’ refers to the No Disk version!
All communication between the ICP-HD-3 and the host CPU is performed via rigid board connec-
tors - there aren’t any flex cables on the CPU board itself! This concept eliminates the risk of
incorrect device installation and ensures both mechanical and electrical stability.
A1.1 ICP-HD-3(-ND) Front-Panels (8HP or 12HP)
The Inova ICP-HD-3(-ND) interface is a mass-storage carrier board that is only available as a CPU
plug-in device with either an 8HP or 12HP front-panel as illustrated in figure A1.1.
Figure A1.1 ICP-HD-3(-ND) CPU Front-Panels
PageA-2
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Appendix A
ICP-HD-3
A1.2 IDE Carrier Board ICP-HD-3(-ND)
Figure A1.2 illustrates the construction of the integrated ICP-HD-3 carrier board and the location
of the interface connectors. Table A1.2 gives a description of these interfaces. Care should be
exercised when attaching the LPT interface to this carrier board. Here the connection is via a
length of flex cable between J11 of the carrier and J13 on the LPT module.
®
Note:
Damage to the CPU, hard-disk carrier
board or the LPT piggyback may
result if the flex cable is positioned
incorrectly. Inova will not accept
responsibility for negligent actions!
Position the blue side of the flex-cable
to the blue-flanked connector shown
below
Figure A1.2 Interface Location of the ICP-HD-3(-ND) Module
A
C
ICP-PM/CMAppendix-A
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ICP-HD-3
Appendix A
Table A1.2 Interface Description of the ICP-HD-3(-ND) Module
Connector
Description
Open:
COM1 is configured for RS232 communication
J1
Closed:
COM1 is configured for RS485 communication
Open:
COM2 is configured for RS232 communication
J2
Closed:
COM2 is configured for RS485 communication
J3
J4
J5
J6
J7
J8
J9
COM2 physical interface
Reset - shorting these pins causes the CPU to reset
PS-2 mouse & keyboard physical interface
USB 2.0 physical interface - USB2
COM1 physical interface
Slim-line floppy disk interface
Notebook style 2.5" IDE header for HD or Flash etc.
Open:
The CompactFlash on the CPU is Master
J10
Closed:
The CompactFlash on the CPU is Slave
J11
J12
J15
Flex cable interface for LPT1 (IPB-FPE12) module
Standard 3.5" EIDE interface [80-strand cable only!]
USB 2.0 physical interface - USB3
The accessibility / maintainability of the mounted hard disk is ensured through the two fixing
screw cutouts on the carrier board. A mounted hard disk is thus unable to shift or become dis-
lodged in any direction.
Note:
Any notebook-style IDE hard disk,
Flash device or similar mass-storage
unit can be connected here. However,
Inova recommend only those devices
from known manufacturers.
Connecting devices to both J9 and J12
simultaneously is not recommended. A
better configuration is to use Master
and Slave devices connected to J12
only or use the Rear I/O feature.
PageA-4
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Appendix A
ICP-HD-3
A2 ICP-HD-3(-ND) Interfaces
®
The carrier board serves not just to mount an IDE mass-storage device - it also provides the user
with a wealth of familiar standard PC interfaces.
A2.1 COM1 & COM2 Interfaces
The two COM ports feature a complete set of handshaking and modem control signals, maskable
interrupt generation and highspeed data transfer rates. The selection between the RS232 and
RS485 serial data communication standard is performed via J1 & J2 (COM1, COM2) illustrated in
Figure A1.2.
Note:
If the COM ports are used in rear I/O
applications then they should not be
used from the CPU front-panel.
The front panel COM port connections
are disabled automatically if using the
rear I/O COM port option.
Figure A2.1 COM1 & COM2 Interface Pinout
A
1
6
5
9
Table A2.1 COM1 & COM2 Connector Signals
Signal
Pin No.
RS232
DCD
RxD
TxD
RS485
C
1
2
3
4
5
6
7
8
9
Note:
RxD, TxD +
RxD, TxD -
The standard CPU configuration has both
COM ports set for RS232 communication.
DTR
GND
DSR
RTS
CTS
RI
However, this device can be configured to
observe a two-wire, non galvanically
separated, RS485 protocol. The data
direction is governed by controlling the
UART’s RTS signal.
ICP-PM/CMAppendix-A
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ICP-HD-3
Appendix A
A2.2 Mouse & Keyboard Interfaces
The physical PS-2 mouse & keyboard interface is brought out on this 8HP front-panel. Connector
pinout and description are provided in Figure A2.2 and Table A2.2 respectively.
Note:
If the mouse and keyboard ports are
used in rear I/O applications then they
should not be used from the front-
panel. Communicating from both
mouse and keyboard sources is physi-
cally possible but is not recommended!
Figure A2.2 Mouse & Keyboard Interface Pinout
5
3
6
4
1
2
Table A2.2 Mouse & Keyboard Connector Signals
Pin No.
Signal
Data - Keyboard
GND
Pin No.
Signal
1
3
5
2
4
6
Data - Mouse
+5V
Clock - Keyboard
Clock - Mouse
PageA-6
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Appendix A
ICP-HD-3
A2.3 USB 2.0 Interfaces
®
Standard to all ICP-HD-3 carrier board modules are the two USB (2.0) interfaces which are back-
ward compatible to USB 1.1 devices.
Figure A2.3 USB Interface Pinout
1
2
3
4
Table A2.3 USB Connector Signals
Pin No.
Signal
1
2
3
4
+5V
USB P0-
USB P0+
GND
A
C
ICP-PM/CMAppendix-A
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ICP-HD-3
Appendix A
A2.4 EIDE Interface
Standard to all ICP-HD-3 carrier board modules is the 3.5” EIDE hard-disk header. This has a
standard (commercial PC) pinout and requires no further mention here.
Note:
To conform with the UDMA 66 (or
higher) standards, only suitable,
commercially available 80-strand
ribbon cable should be used. Failure to
do so may result in data transmission
errors or even cause the CPU to crash!
A2.5 Slim-Line Floppy Disk Interface
Standard to all ICP-HD-3 carrier board modules is the slim-line floppy disk header. This has a
standard (commercial PC) pinout and requires no further mention here.
PageA-8
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Appendix B
IPB-FPE12
®
IPB-FPE12
IPB-FPE12 Contents
B1 IPB-FPE12 CPU Extension ........ B-2
B1.1 J13 Interface for LPT1 ............................................................................... B-2
B1.2 IPB-FPE12 Front-Panel (4HP or 12HP) ....................................................... B-2
Figure B1.2 IPB-FPE12 Stand-Alone or Integrated with CPU ........................................................ B-2
B1.3 LPT1 Piggyback........................................................................................ B-3
Figure B1.3 LPT1 Piggyback Board IPB-FPE12 ............................................................................. B-3
Table B1.3 IPB-FPE12 Connector Description .............................................................................. B-4
B1.4 LPT1 Interface .......................................................................................... B-4
Figure B1.4 LPT1 Interface Pinout .............................................................................................. B-4
Table B1.4 LPT1 Connector Signals ............................................................................................ B-4
B
C
ICP-P4/PM/CMAppendix-B
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IPB-FPE12
Appendix B
B1 IPB-FPE12 CPU Extension
The Inova IPB-FPE12 adds LPT functionality to any Inova Pentium M, Celeron M or Pentium 4(M)
CPU. The piggyback is available as a stand-alone device with its own 4HP front-panel or integrated
within a 12HP front-panel. The information documented here is valid regardless of the connection
choice.
B1.1 J13 Interface for LPT1
The control of the LPT interface is performed through the J11 connector on the CPU’s hard-disk
carrier board. The location of this connector may be determined by referring to Appendix A of this
User’s Manual. The flex cable connection and function of the LPT interface are discussed in this
section.
B1.2 IPB-FPE12 Front-Panel (4HP or 12HP)
The Inova IPB-FPE12 interface is a small piggyback available as a stand-alone device with its own
4HP front-panel or integrated with the CPU as in figure B1.2.
Figure B1.2 IPB-FPE12 Stand-Alone or Integrated with CPU
Note:
Although COM2 is shown on the left-
hand stand-alone front-panel, this
interface will not be present in the
delivered module. A dust cap replaces
the 9-pin D-Sub connector!
If an LPT or slim-line FD configured to
communicate via the rear I/O (RIO)
transition module then the LPT inter-
face cannot be used here. Trying to do
so will result in data corruption and
possible damage to the logic compo-
nents
©2004 Inova Computers GmbH
PageB-2
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Appendix B
IPB-FPE12
B1.3 LPT1 Piggyback
Figure B1.3 illustrates the construction of the stand-alone IPB-FPE12 piggyback and the upperside
location of the J13 connector. The same mechanical construction applies to the integrated ver-
sion. Care should be taken to ensure that pin 1 of J13 on the CPU base board is linked by an
appropriate length of flex cable to pin 1 on the ICP-HD-3 piggyback. To help with the orientation,
the connector flanks that are blue indicate the blue face of the flex-cable. Unmarked flanks indi-
cate the metallic connection of the flex-cable. Also, pin 1 has been highlighted by a red triangle.
®
Note:
Damage to the CPU, hard-disk carrier
board or the piggyback may result if
the flex cable is positioned incorrectly.
Inova will not accept responsibility for
negligent actions!
Figure B1.3 LPT1 Piggyback Board IPB-FPE12
B
C
Note:
The physical connection of the IPB-
FPE12 is electrically identical regard-
less of the nature of connection
(stand-alone or integrated!)
ICP-P4/PM/CMAppendix-B
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IPB-FPE12
Appendix B
Table B1.3 IPB-FPE12 Connector Description
Connector
Description
J13
LPT1
B1.4 LPT1 Interface
The physical LPT1 interface is either integrated into a 12HP CPU front-panel or available as a
separate 4HP unit. The piggyback located behind this interface connects to the hard-disk carrier
board (ICP-HD-3) mounted J13 connector.
Figure B1.4 LPT1 Interface Pinout
13
25
1
14
Table B1.4 LPT1 Connector Signals
Pin No.
Signal
Pin No.
Signal
1
3
STROBE
PD1
2
4
PD0
PD2
5
PD3
6
PD4
7
PD5
8
PD6
9
PD7
10
12
14
16
18-25
ACK
PE
11
13
15
17
BUSY
SLCT
ERROR
SLCTIN
AUTOFD
INIT
GND
©2004 Inova Computers GmbH
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Appendix C
ITM-RIO
®
ITM-RIO
ITM-RIO Contents
C1 ITM-RIO CPU Extension ............ C-2
C1.1 ITM-RIO-D Configurations ....................................................................... C-2
Table C1.10 Valid Rear I/O Configurations ................................................................................. C-2
Table C1.11 Rear I/O Module Functionality ................................................................................ C-2
C1.2 ITM-RIO Rear-Panels (4HP or 8HP) ........................................................... C-3
Figure C1.2 The rear Panels of the Inova ITM-RIO-D-x................................................................ C-3
C1.3 ITM-RIO-D-x Transition Module ............................................................... C-4
Figure C1.3 Inova Rear I/O Transition Module ITM-RIO-D-x........................................................ C-4
Table C1.3 ITM-RIO-D-x Connector Description.......................................................................... C-5
C1.4 COM1 & COM2 Interfaces ...................................................................... C-6
Figure C1.4 COM1 & COM2 Interface Pinout............................................................................. C-6
Table C1.4 COM1 & COM2 Connector Signals .......................................................................... C-6
C1.5 LPT1 Interface.......................................................................................... C-7
Figure C1.5 LPT1 Interface Pinout .............................................................................................. C-7
Table C1.5 LPT1 Connector Signals ............................................................................................ C-7
C1.6 Mouse & Keyboard Interfaces .................................................................. C-8
Figure C1.6 Mouse & Keyboard Interface Pinout........................................................................ C-8
Table C1.6 Mouse & Keyboard Connector Signals ...................................................................... C-8
C1.7 VGA Interface .......................................................................................... C-9
Figure C1.7 VGA Interface Pinout ............................................................................................... C-9
Table C1.7 Video Output Connector Signals ............................................................................... C-9
C
C1.8 Fast Ethernet Interface ........................................................................... C-10
Figure C1.8 Fast Ethernet Interface Pinout ................................................................................ C-10
Table C1.8 Fast Ethernet Connector Signals.............................................................................. C-10
C1.9 USB Interface (USB 4) ............................................................................ C-11
Figure C1.9 USB Interface Pinout ............................................................................................. C-11
Table C1.9 USB Connector Signals ........................................................................................... C-11
C
C1.10 EIDE Interface ...................................................................................... C-12
C1.11 Slim-Line Floppy Disk Interface ............................................................ C-12
C1.12 ITM-RIO(C&D)-FHLU Extension ........................................................... C-13
Figure C1.12 ITM-RIO(C&D)-FHLU........................................................................................... C-13
ICP-P4/PM/CMAppendix-C
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ITM-RIO
Appendix C
C1 ITM-RIO CPU Extension
The Inova Pentium 4(M), Pentium M or Celeron M CPUs are more than just a computing platform
- they are a complete, well thought-out concept. Nowhere is this more apparent than in the
colourful rear I/O selection. With a choice of three full-length (80mm) plug-in modules conform-
ing to the latest Inova rear I/O (D) specification and the rear I/O (C1) options, the major industrial
requirements have been satisfied.
C1.1 ITM-RIO-D Configurations
Rear I/O (D) is the standard configuration for the Pentium 4(M), Pentium M and Celeron M series
of high-performance CPUs. Table C1.10 illustrates the configurations stemming from one single
PCB layout - with backward compatibility to some of the features provided in the Inova rear I/O
(C) boards. Table C1.11 shows the functionality of the 4 Inova rear I/O compatible modules.
Table C1.10 Valid Rear I/O Configurations
Option
RIO(C1)
No
RIO(D)
Yes
Processor
PM CM
Controller
VGA
P4
Fast Ethernet
See Matrix
Yes
See Matrix
Yes
Intel
SiS
82551 82540EM 82551
USB 1.1
900
900
900
900
PS-2 Mouse & Keyboard
2nd IDE Channel
Reset & Beeper
Keyboard Only
Yes
Yes
RIO
82551
82551
Yes
LAN Networking Matrix
Yes
Yes
LPT1
Software Selectable
Software Selectable
Software Selectable
Software Selectable
Software Selectable
Software Selectable
COM1 & COM2
Floppy Disk (A or B)
Table C1.11 Rear I/O Module Functionality
Product
Name
VGA
Graphic
Fast
Ethernet
Mouse /
Keyboard Storage
Mass
Full
Length
USB
I/O
ITM-RIO-D-0
ITM-RIO-D-1
ITM-RIO-D-2
Yes
Yes
Yes
No
See Matrix
See Matrix
See Matrix
None
1.1
1.1
1.1
1.1
LPT1
Both
Both
Header
Header
Header
Header
Yes ( 80mm )
Yes (80mm )
Yes ( 80mm )
No (25mm )
COM1 &
COM2
FD-A
FD-A
Keyboard
No
ITM-RIO-
FHLU
All transition modules have reset and beeper pins
Auto-configuration RIO(D) feature can be overridden in BIOS. Settings MUST be made manually if equipped with RIO (C)
PageC-2
©2004 Inova Computers GmbH
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Appendix C
ITM-RIO
C1.2 ITM-RIO Rear-Panels (4HP or 8HP)
As with front-panel I/O, the physical interfaces from the ITM-RIO-D-x rear I/O module are brought
out to a face plate (rear panel). Figure C1.2 illustrates the three standard formats available (at time
of press.)
®
Figure C1.2 The rear Panels of the Inova ITM-RIO-D-x
C
The rear I/O options described here do not detract from the latest PICMG 2.0 R3.0 specification.
C
The VGA option in table C1.10 can be from either the chipset or the AGP piggyback option. Using
the chipset graphics for both front and rear I/O simultaneously is not advisable as the loading may
be too great. If both front and rear I/O VGA are required then the twin-engined, Radeon-based
AGP piggyback graphic option should be used.
The single channel Fast Ethernet option in table C1.10 is either ETH1 or ETH 2 on the front-panel
depending on the computer platform. If the rear I/O option is used then the front-panel connec-
tion must not be used. Doing so will disrupt the communication leading to spurious results.
If the mouse, keyboard and COM ports are used in rear I/O applications then they should not be
used from the front-panel. Communicating from both mouse and keyboard sources is physically
possible but is not recommended!
ICP-P4/PM/CMAppendix-C
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ITM-RIO
Appendix C
C1.3 ITM-RIO-D-x Transition Module
Figure C1.3 illustrates the construction of the ITM-RIO-D-x module. The connections are straight
forward and need little by way of explanation. None of the connectors can be incorrectly inserted
thanks to the mechanical keying of both plug and socket. Table C1.3 explains the significance of
the interfaces labelled in Figure C1.3.
Note:
Care should be exercised when insert-
ing the cables linking the COM, LPT,
EIDE and floppy etc. Only those cables
supplied by Inova Computers should
be used.
Figure C1.3 Inova Rear I/O Transition Module ITM-RIO-D-x
PageC-4
©2004 Inova Computers GmbH
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Appendix C
ITM-RIO
Table C1.3 ITM-RIO-D-x Connector Description
®
Connector
Description
J1
J2
J3
J4
J5
CompactPCI rear I/O connector
Standard 3.5" IDE header
Standard slim-line floppy disk interface
Beeper (loudspeaker)
Reset
Open:
Closed:
Open:
Closed:
LPT1
COM2 is configured for RS232 communication
COM2 is configured for RS485 communication
J7
J8
COM1 is configured for RS232 communication
COM1 is configured for RS485 communication
J9
J10
J11
J12
J13
J14
J15
COM2
VGA physical interface
COM1
USB physical interface (USB 4)
Fast Ethernet physical interface
PS-2 mouse & keyboard interface [only keyboard on ITM-RIO-D-2 ]
Note:
C
When setting up the rear I/O (D) the
following should be observed:
C
Either the LPT interface or the COM ports
or the floppy disk interface can be used
(not combined)
Only the required device should be
attached. Installing or attaching hard-
ware that is not required will prevent the
actual device from being configured.
Example: if a FD is physically attached
but the COM ports are required, then
these ports will not work even if they are
correctly configured in BIOS!
ICP-P4/PM/CMAppendix-C
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ITM-RIO
Appendix C
C1.4 COM1 & COM2 Interfaces
The two COM ports feature a complete set of handshaking and modem control signals, maskable
interrupt generation and highspeed data transfer rates. An 8HP rear-panel (Figure C1.2) brings
out the physical COM1 & COM2 interfaces.
Note:
If the COM ports are used in rear I/O
applications then they should not be
used from the CPU front-panel.
The front panel COM port connections
are disabled automatically if using the
rear I/O COM port option.
Figure C1.4 COM1 & COM2 Interface Pinout
1
5
9
6
Table C1.4 COM1 & COM2 Connector Signals
Signal
Pin No.
RS232
DCD
RxD
TxD
RS485
1
2
3
4
5
6
7
8
9
RxD, TxD +
RxD, TxD -
Note:
DTR
GND
DSR
RTS
CTS
RI
The standard CPU configuration has both
COM ports set for RS232 communication.
However, this device can be configured (J7
and J8) to observe a two-wire, non
galvanically separated, RS485 protocol.
The data direction is governed by control-
ling the UART’s RTS signal.
PageC-6
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Appendix C
ITM-RIO
C1.5 LPT1 Interface
The physical LPT1 interface of the rear I/O panel illustrated in Figure C1.2 connects to J9 on the
baseboard for.
®
Note:
If the LPT port is used in rear I/O
applications then it should not be
used from the front-panel. Communi-
cating from both sources is physically
possible but is not recommended!
Figure C1.5 LPT1 Interface Pinout
13
25
1
14
Table C1.5 LPT1 Connector Signals
Pin No.
Signal
Pin No.
Signal
1
3
STROBE
PD1
2
4
PD0
C
PD2
5
PD3
6
PD4
C
7
PD5
8
PD6
9
PD7
10
12
14
16
18-25
ACK
PE
11
13
15
17
BUSY
SLCT
ERROR
SLCTIN
AUTOFD
INIT
GND
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ITM-RIO
Appendix C
C1.6 Mouse & Keyboard Interfaces
The physical PS-2 keyboard interface is brought out on either a 4HP or 8HP rear -panel, the mouse
interface is only available on the 8HP version (Figure C1.2) Connector pinout and description are
provided in Figure C1.6 and Table C1.6 respectively.
Note:
If the mouse, keyboard ports are used
in rear I/O applications then they
should not be used from the front-
panel. Communicating from both
mouse and keyboard sources is physi-
cally possible but is not recommended!
Figure C1.6 Mouse & Keyboard Interface Pinout
5
3
6
4
1
2
Table C1.6 Mouse & Keyboard Connector Signals
Pin No.
Signal
Pin No.
Signal
1
3
5
Data
GND
CLK
2
4
6
N/C
+5V
N/C
PageC-8
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Appendix C
ITM-RIO
C1.7 VGA Interface
The VGA signals appearing on this interface are from the CPU chipset or AGP piggyback (if config-
ured for rear I/O signalling). Figure C1.7 and Table C1.7 provide the pinout and signal description
of this standard VGA interface respectively. With an AGP video piggyback installed, the video
image appearing on this rear I/O interface can be selected to be different to that appearing on the
front-panel. This is possible through (in this case) the piggyback’s dual independent Radeon 7000
graphics engines.
®
Note:
Using the chipset graphics for both
front and rear I/O simultaneously is
not advisable as the loading may be
too great. If both front and rear I/O
VGA are required then the twin-
engined, Radeon-based AGP piggy-
back graphic option should be used.
5
1
Figure C1.7 VGA Interface Pinout
10
6
15
11
Table C1.7 Video Output Connector Signals
Pin No.
Signal
1
2
3
4
Analog RED
Analog GREEN
Analog BLUE
N/C
C
C
5, 6, 7, 8 CRT Ground
9
+5V (DDC)
CRT Ground
N/C
10
11
12
13
14
15
DDC-SDA
HSYNC
VSYNC
DDC-SCL
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ITM-RIO
Appendix C
C1.8 Fast Ethernet Interface
Standard to all rear I/O (D) transition modules is the Fast Ethernet connection. Figure C1.8 and
Table C1.8 provide the pinout and signal description of this standard Ethernet interface respec-
tively. Although the LEDs feature on the Ethernet connector, these are not physically connected to
the rear I/O interface board. Instead, if this interface is used, communication traffic can still be
observed on the front-panel Ethernet connector!
Note:
The single channel Fast Ethernet
option in table C1.10 is either ETH 1
or ETH 2 on the front-panel depending
on the computer platform. If the rear
I/O option is used then the front-panel
connection using the same controller
must not be used. Doing so will
disrupt the communication leading to
spurious results.
Figure C1.8 Fast Ethernet Interface Pinout
8
1
Table C1.8 Fast Ethernet Connector Signals
Signal Description
Ethernet / Fast Ethernet
Pin No.
1
2
3
4
5
6
7
8
TX0+
TX0-
RX0+
RX0-
PageC-10
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Appendix C
ITM-RIO
C1.9 USB Interface (USB 4)
®
Standard to all rear I/O (D) transition modules is the peripheral USB (1.1) port. Figure C1.9 and
Table C1.9 provide the pinout and signal description of this standard Ethernet interface respec-
tively.
Figure C1.9 USB Interface Pinout
1
2
3
4
Table C1.9 USB Connector Signals
Pin No.
Signal
1
2
3
4
+5V
USB P2-
USB P2+
GND
C
C
ICP-P4/PM/CMAppendix-C
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ITM-RIO
Appendix C
C1.10 EIDE Interface
Standard to all rear I/O transition modules is the 3.5” EIDE hard-disk header. This has a standard
(commercial PC) pinout and requires no further mention here.
Note:
To conform with the ATA 5 standard,
only suitable, commercially available
80-strand ribbon cable should be
used. Failure to do so may result in
data transmission errors or even cause
the CPU to crash!
C1.11 Slim-Line Floppy Disk Interface
Standard to all rear I/O transition modules is the slim-line floppy disk header. This has a standard
(commercial PC) pinout and requires no further mention here.
PageC-12
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Appendix C
ITM-RIO
C1.12 ITM-RIO(C&D)-FHLU Extension
®
To further enhance the I/O and serviceability of their CPUs, Inova have introduced a rear I/O
module (figure C1.12) that connects to a CompactPCI connector on the rear of the Master Slot on
the backplane. All standard Inova backplanes are equipped with this R2 connector so that even if
the rear I/O functionality is not requested at time of order, it can be implemented at a later stage.
One of the advantages of this module (apart from its obvious size benefit) is its ability to attach a
3.5” IDE device (or Inova IPM-ATA Mass Storage Device) without direct connection to the CPU
base board. This facilitates servicing and allows a CPU for example, to be exchanged without
touching the software stored on the HD. Likewise, a hard-disk can be swapped without having to
disassemble the CPU! Two slim-line (notebook) floppy interfaces are implemented allowing the
module to be compatible with existing Inova PIII CPUs (with RIO(C)) as well as the P4, PM and CM
family.
The integration of USB (1.1) with both the standard connector and notebook style internal con-
nector facilitates the integration of commercially available FDs or similar devices. The signal de-
scription of the standard connector can be obtained by referring to page C - 11
Figure C1.12 ITM-RIO(C&D)-FHLU
C
C
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Appendix C
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Appendix D
IPM-ATA
®
IPM-ATA
IPM-ATA
D1 IPM-ATA CPU Extension .......... D-2
D1.1 rJ2 Interface ............................................................................................ D-2
Figure D1.1a Dedicated IPM-ATA Backplane ............................................................................... D-2
D1.1 rJ2 Interfaces (Contd.) ............................................................................ D-3
Figure D1.1b The Complete Connection Picture .......................................................................... D-3
D1.2 IPM-ATA-HD ........................................................................................... D-4
Figure D1.2 IPM-ATA-HD Board Layout ...................................................................................... D-4
Table D1.2 IPM-ATA-HD Jumper Description (CF Socket) ............................................................. D-4
D1.3 IPM-ATA-CF ............................................................................................ D-5
Figure D1.3 IPM-ATA-CF Board Layout ....................................................................................... D-5
Table D1.3 IPM-ATA-CF Jumper Description ................................................................................ D-5
D1.4 IPM-ATA-PCMCIA ................................................................................... D-6
Figure D1.4 IPM-ATA-PCMCIA Board Layout............................................................................... D-6
Table D1.4 IPM-ATA-PCMCIA Jumper Description ....................................................................... D-6
D1.5 Device Compatibility .............................................................................. D-7
Table D1.5 Compatibility List ..................................................................................................... D-7
C
D
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IPM-ATA
Appendix D
D1 IPM-ATA CPU Extension
Inova Plug-In Module (IPM-) offers the user the ability to exchange a hard-disk for example with-
out having to remove the CPU from the CompactPCI enclosure and then dismantle it etc. Cur-
rently, three units exist that provide industry with hard-disk, Compact FLASH, MicroDrive or ATA
PCMCIA format mass storage capability.
D1.1 rJ2 Interface
All IPM-ATA modules possess rJ2 for data communication between the CompactPCI backplane
and the mass storage unit(s) in question. Figure D1.1a illustrates the dedicated IPM-ATA backplane
and connectors.
Note:
The IPM-ATA modules can only be
used in CompactPCI systems that have
been prepared for rear I/O or have the
IDE signals available on the rear rP2
connector that are in accordance with
the specification for RIO. In addition,
the rear rP2 CompactPCI connector
must be present.
Figure D1.1a Dedicated IPM-ATA Backplane
PageD-2
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Appendix D
IPM-ATA
D1.1 rJ2 Interfaces (Contd.)
®
Standard 80-pin IDE ribbon-cable is used to connect rJ2 of the ITM-RIO modules to the IPM’s
dedicated backplane. The use of ribbon cable permits the mass-storage device(s) to be positioned
at any convenient location within the CompactPCI enclosure. Figure D1.1b shows the complete
configuration (CompactPCI to IPM-XXX)
Figure D1.1b The Complete Connection Picture
KEY:
C
1. IPM-ATA carrier board
2. Dedicated backplane with standard IDE header and power cord interface
3. Y-Cable for bringing the power from the CompactPCI backplane and to this and another device
4. Standard 80-strand, ATA-5 [UDMA-66 or higher] IDE ribbon cable (30cm)
5. Inova rear I/O module (ITM-RIO) with IDE connection
D
Note:
The IDE cabling used should conform to
at least ATA-5 standards (80-strand)
ICP-P4/PM/CMAppendix-D
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IPM-ATA
Appendix D
D1.2 IPM-ATA-HD
The IPM-ATA-HD has provision for one standard notebook (2.5”) EIDE device (FLASH or hard-disk)
and one Compact FLASH or MicroDrive site. Figure D1.2 illustrates the significant connectors for
this device while Table D1.2 indicates the jumper positions for the various Master/Slave device
configurations.
Figure D1.2 IPM-ATA-HD Board Layout
1
2
3
Note:
The hard disk is jumpered seperately for
Master / Slave operation
Table D1.2 IPM-ATA-HD Jumper Description (CF Socket)
CompactFlash
Jumper J6
or MicroDrive in J3
2-3
Master
Open
Slave
It should be noted that the secondary IDE channel (from rear I/O) only is available for use by the
IPM-ATA-HD (the primary is on the CPU board itself). Multi Master or multi Slave configurations
are not supported and will not work!
PageD-4
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Appendix D
IPM-ATA
D1.3 IPM-ATA-CF
The IPM-ATA-CF has provision for one or two standard Compact FLASH or MicroDrive devices.
Figure D1.3 illustrates the significant connectors for this device while Table D1.3 indicates the
jumper settings for the various Master/Slave device configurations.
®
Figure D1.3 IPM-ATA-CF Board Layout
1
2
3
Table D1.3 IPM-ATA-CF Jumper Description
CompactFlash
or MicroDrive in J3
CompactFlash
or MicroDrive in J4
Jumper J6
Jumper J7
2-3
Master
2-3
Master
C
Open
Slave
Open
Slave
D
It should be noted that the secondary IDE channel only (from rear I/O) is available for use by the
IPM-ATA-CF (the primary is on the CPU board itself). Multi Master or multi Slave configurations
are not supported and will not work!
ICP-P4/PM/CMAppendix-D
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IPM-ATA
Appendix D
D1.4 IPM-ATA-PCMCIA
The IPM-ATA-PCMCIA has provision for one standard ATA PCMCIA device and one Compact
FLASH or MicroDrive site. Figure D1.4 illustrates the significant connectors for this device while
Table D1.4 indicates the jumper settings for the various Master/Slave device configurations.
Figure D1.4 IPM-ATA-PCMCIA Board Layout
1
2
3
Table D1.4 IPM-ATA-PCMCIA Jumper Description
CompactFlash
or MicroDrive in J3
Jumper J8
Jumper J6
PCMCIA Device in J5
2-3
Master
2-3
Master
Open
Slave
Open
Slave
It should be noted that the secondary IDE channel only (from rear I/O) is available for use by the
IPM-ATA-PCMCIA (the primary is on the CPU board itself). Multi Master or multi Slave configura-
tions are not supported and will not work!
Note:
The PCMCIA device cannot and must
not be removed during use. To ex-
change or remove the device, first
power-down the system!
PageD-6
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Appendix D
IPM-ATA
D1.5 Device Compatibility
Because of the diversity of Compact FLASH devices available with different architectures and error
recovery routines etc. there is a strong possibility that some Master / Slave combinations will fail to
be recognised by the BIOS. To help highlight the problem, Inova have provided the test report
shown in Table D1.5 which should be regarded as a guide when choosing to pick-and-mix de-
vices. Should devices other than those from the manufacturers indicated in the table be chosen,
then it may be prudent that Inova be contacted prior to commissioning.
®
Table D1.5 Compatibility List
Position
Compact FLASH Card
IBM Microdrive DMDM-10340
Empty
Result
Test
Jumper
J3
J4
J3
J4
J3
J4
J3
J4
J3
J4
J3
J4
Master
1
Passed
-
M-Systems 64MByte Compact FLASH
Empty
Master
-
2
3
4
5
6
Passed
Passed
IBM Microdrive DMDM-10340
IBM Microdrive DMDM-10340
IBM Microdrive DMDM-10340
M-Systems 64MByte Compact FLASH
IBM Microdrive DMDM-10340
M-Systems 64MByte Compact FLASH
M-Systems 64MByte Compact FLASH
IBM Microdrive DMDM-10340
Slave
Master
Slave
Master
Master
Slave
Master
Slave
(incl. Strip Set Config.)
Passed
Failed: M-Systems not
detected in BIOS
Passed
Note:
C
This module only supports ATA PCMCIA
cards (memory) and cannot be used with
WLAN, modem, GPS etc. PCMCIA devices.
D
If one configuration seems not to work,
try swapping Master and Slave.
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IPM-ATA
Appendix D
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Appendix E
AGP-R7000
®
AGP-R7000
AGP-R7000
E1 AGP-R7000 CPU Extension....... E-2
Table E1.00 AGP Piggyback Configurations ................................................................................. E-2
E1.1 Specifications ........................................................................................... E-3
E1.2 J4 Interface ............................................................................................... E-4
Figure E1.20 J4 on the Underside of the AGP-R7000 Piggyback ................................................... E-4
Table E1.20 J4 Pinout ................................................................................................................. E-5
Table E1.20 J4 Pinout - Contd. .................................................................................................... E-6
E1.3 J3 & J5 IBP-GS-MULTILINK (TFT) Interfaces............................................... E-7
Figure E1.30 J3 and J5 Topside Connectors for the Inova IPB-GS-MULTILINK ................................ E-7
Table E1.30 J3 & J5 Interface Pinout ........................................................................................... E-8
E1.4 J1 Front-Panel VGA/TMDS Interface.......................................................... E-9
Figure E1.40 Standard Front-Panel VGA/TMDS Interface ............................................................. E-9
Table E1.40 J1 Standard Front-Panel VGA/TMDS Pinout.............................................................. E-9
Table E1.41 J2 DIP Switch Settings - Digital TMDS (PanelLink) or DVI-D .................................... E-10
Table E1.42 J2 DIP Switch Settings - TFT (24Bit TTL/CMOS) ...................................................... E-10
E1.5 Rear I/O VGA Interface ........................................................................... E-11
C
E
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AGP-R7000
Appendix E
E1 AGP-R7000 CPU Extension
The AGP-R7000 is an Inova AGP 4x ATI Radeon-based graphic extension for use with the ICP-P4,
ICP-P4(M), ICP-PM and ICP-CM CPUs. By utilizing the power of the ATI Radeon 7000 equipped
with 32MByte of SDRAM, a graphic performance improvement of some 50%1.) can be expected
when compared to the on board (chipset) solution. Able to drive analog VGA or PanelLink com-
Ȣ
patible monitors directly or connect to the IBP-GS-MULTILINK GigaST R transmitter with CAN
routing for long-distance digital data transfer, the AGP-R7000 suits the demands of modern indus-
trial (automation engineering) applications.
It is fabricated in 2 basic versions: Analog VGA or digital DVI-D (TMDS). Connectors J1, J3 and J5
are explained later in this section.
Table E1.00 AGP Piggyback Configurations
J1
(Front)
Rear I/O
J3 / J5
Option
CRT 1
-
TFT
TFT
TFT
TFT
TFT
Option 1
Option 2
Option 3
Option 4
Option 5
CRT 1
CRT 1
TMDS
TMDS
CRT 1
CRT 2
-
CRT 1
Note
The front and/or rear connected display
devices may be configured to show the
same or different (independent) video
content to TFT units by configuring the
driver software.
With the AGP installed, the onboard
(chipset) graphic is disabled.
Options 2 and 5 are preferred (standard).
Option 3, although possible, should only
be selected if CRT 1 is permanently
connected.
1.) OpenGL applications performed 83% faster with the AGP piggyback installed and memory efficiency increased by 14%
PageE-2
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Appendix E
AGP-R7000
E1.1 Specifications
®
Interface
AGP 4x (120-pin connector)
ATI Radeon with 32MByte RAM
Video
Controller
Screen Options Resolution
Colour Depth
32-bit
Refresh
72Hz
80Hz
60Hz
(TFT & VGA)
1920 x 1200
1920 x 1200
2048 x 1536
16-bit
16-bit
TMDS
1600 x 1200
24-bit
60Hz
Configuration DIP switch for DDC data or fixed resolution
User Interfaces 15-pin D-Sub for front-panel VGA or
15-pin D-Sub for front-panel TMDS (PanelLink)
Ȣ
2x27 pin ZIF connector for TFT (GigaST R)
Options
Front or rear-panel VGA1)
Front-panel TMDS and rear-panel VGA2)
Software
Support
Windows® 2000®, Windows® XP®
Power Req.
Mass
+3.3V (2W), +5V (2W) (typically)
40g (typically)
Oper. Temp.
0°C to +60°C
Storage Temp. -40°C to +85°C
Humidity
Warranty
5% to 95% (non-condensing) @ 40°C
Three-year limited warranty
1)
Two VGA monitors can be connected simultaneously with identical video information on both - the Radeon
graphics engine must be configured accordingly. An alternative is also available where the content appearing
on the 2nd display is different to that of the first. The disadvantage of this configuration is that if a monitor is
not connected to the front-panel (CRT1) the video content cannot be displayed on CRT2 (rear) until the OS has
been initialised and the video driver initialised. If a BIOS upgrade is required or the settings need to be altered
etc. then, without the CRT on the front-panel, the user will not see anything which makes the task almost
imposible!
C
2)
This is the only supported mode whereby (independent) video can be produced via the front DVI-D and a rear
connected analog (CRT) device.
Both options support TFT - video content can be selected to be the TMDS or CRT
E
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AGP-R7000
Appendix E
E1.2 J4 Interface
Communication to and from the host CPU is through J4 (refer to figure E1.20) - the AGP interface.
The video output, as discussed earlier, is hardware configured (at time of purchase) for different front
and rear panel modes - refer to table E1.00. The TFT option (J3/J5) is always present.
The J4 AGP interface on the graphic piggyback is electrically identical to AGP, but has a smaller form
factor and uses a different connector. Table E1.20 shows the pinout of this connector.
Figure E1.20 J4 on the Underside of the AGP-R7000 Piggyback
PageE-4
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Appendix E
AGP-R7000
Table E1.20 J4 Pinout
®
Pin No.
Signal
Pin No.
Signal
1
USB6+
2
GND
3
PC_BEEP
VCC3.3
SYNC
SDATA_OUT
INTB#
GND
4
USB6-
AC_RESET#
BITCLK
VCC5
5
6
7
8
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
SDATA_IN
INTA#
RST#
CLK
REQ#
ST0
GND
GNT#
VCC3.3
ST2
ST1
-
RBF#
VCC3.3
PIPE#
WBF#
SBA1
-
GND
SBA0
SBA2
GND
SB_STB
VCC3.3
SBA4
SBA3
SB_STB#
SBA5
SBA6
VCC3.3
SBA7
AD31
GND
AD30
C
AD29
AD28
AD27
GND
AD25
AD26
VDDQ1.5
AD_STB1
AD23
AD24
AD_STB1#
VDDQ1.5
C/BE3#
E
AD21
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AGP-R7000
Appendix E
Table E1.20 J4 Pinout - Contd.
Pin No.
Signal
Pin No.
Signal
61
63
GND
62
64
AD22
AD20
GND
AD19
65
AD17
66
67
C/BE2#
VDDQ1.5
IRDY#
DEVSEL#
-
68
AD18
AD16
69
70
71
72
FRAME#
VDDQ1.5
TRDY#
STOP#
PME#
73
74
75
76
77
GND
78
79
PERR#
SERR#
C/BE1#
VDDQ1.5
AD14
80
81
82
GND
83
84
PAR
85
86
AD15
87
88
AD13
89
AD12
90
VDDQ1.5
AD11
91
AD10
92
93
GND
94
AD9
95
AD8
96
C/BE0#
GND
97
AD_STB0
AD7
98
99
100
102
104
106
108
110
112
114
116
118
120
AD_STB0#
AD6
101
103
105
107
109
111
113
115
117
119
VDDQ1.5
AD5
AD4
AD3
VDDQ1.5
AD2
AD1
GND
AD0
VREFCG
VGA_R
VGA_G
GND
VREFGC
GND
HSYNC
VSYNC
VB_EN
VGA_B
PageE-6
©2004 Inova Computers GmbH
ICP-P4/PM/CMAppendix-E
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Appendix E
AGP-R7000
E1.3 J3 & J5 IBP-GS-MULTILINK (TFT) Interfaces
®
Ȣ
To address an almost unlimited number of cascaded digitally connected (GigaST R) TFT displays
Ȣ
with optional CAN control and PanelLink Slave connectivity, the Inova GigaST R transmitter pig-
gyback, IPB-GS-MULTILINK needs to be installed adjacent to the AGP piggyback. This connection
is made through connectors J3 and J5 on the upper side of the piggyback as shown in figure
E1.30. Table E1.30 gives the pinout of these two connectors.
The settings of the DIP switch (J2) are explained later.
Figure E1.30 J3 and J5 Topside Connectors for the Inova IPB-GS-MULTILINK
C
Also visible on the upper side of this piggyback are three labels - one (Label 1) shows the name of
the board, the second shows the product bar code (with manufacturing details, lot number and
ID number) and the third (Label 3) carries the revision number. The board revision is also printed
on the PCB.
E
ICP-P4/PM/CMAppendix-E
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AGP-R7000
Appendix E
Table E1.30 J3 & J5 Interface Pinout
J3 Connector
J5 Connector
Signal
Pin No.
1
Signal
Pin No.
1
D16_R0
D17_R1
GND
D0_B0
D1_B1
GND
2
2
3
3
4
D18_R2
D19_R3
GND
4
D2_B2
D3_B3
GND
5
5
6
6
7
D20_R4
D21_R5
GND
7
D4_B4
D5_B5
GND
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
D22_R6
D23_R7
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
D6_B6
D7_B7
GND
CLK
D8_G0
D9_G1
GND
GND
DE
GND
D10_G2
D11_G3
GND
HSYNC
GND
VSYNC
GND
D12_G4
D13_G5
GND
GND
GND
D14_G6
D15_G7
VCC5.0
VCC5.0
VCC5.0
VCC5.0
VCC3.3
VCC3.3
VCC3.3
VCC3.3
VCC3.3
Information on the GigaSTAR IPB-GS-MULTILINK can be found in the respective documentation.
PageE-8
©2004 Inova Computers GmbH
ICP-P4/PM/CMAppendix-E
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Appendix E
AGP-R7000
E1.4 J1 Front-Panel VGA/TMDS Interface
®
Standard analog VGA or digital (PanelLink) monitors can be connected to the AGP-R7000 via the
15-pin, D-Sub J1 interface. A bank of DIP switches (J2) enables the resolution of connected TFT or
TMDS displays to be set or permits the system software to access the DDC data from standard
analog or digital TMDS devices and set the resolution automatically.
Figure E1.40 shows the VGA/TMDS connector signals for the front-panel D-Sub connector and
tables E1.40 to E1.42 show the connector pinout and DIP switch settings respectively.
Figure E1.40 Standard Front-Panel VGA/TMDS Interface
5
1
Note:
A 3m length of 9-pin D-Sub to DVI-D
cable is supplied with each CPU config-
ured with this graphic option.
10
6
15
11
Table E1.40 J1 Standard Front-Panel VGA/TMDS Pinout
Pin No.
Analog (CRT) Signal
Digital (TMDS) Signal
1
2
Analog RED
TX2#
Analog GREEN
Analog BLUE
N/C
TX1#
3
TX0#
4
TXC#
DDC_DAT
GND
5
N/C (GND)
GND
6, 8
7
C
N/C (GND)
+5V
USB_D+
+5V
9
10
11
12
13
14
15
N/C (GND)
N/C
USB_D-
TX2
E
DDC_DAT
HSYNC
TX1
TX0
VSYNC
TXC
DDC_CLK
DDC_CLK
ICP-P4/PM/CMAppendix-E
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AGP-R7000
Appendix E
Table E1.41 J2 DIP Switch Settings - Digital TMDS (PanelLink) or DVI-D
SW3
OFF
OFF
OFF
OFF
ON
SW2
OFF
OFF
ON
SW1
OFF
ON
Resolution
Disabled
Comments
See Note Below
60Hz
640 x 480
OFF
ON
800 x 600
60Hz
ON
1024 x 768
1280 x 1024
60Hz
OFF
OFF
ON
OFF
ON
60Hz
ON
Reserved
ON
OFF
ON
Reserved
Reserved
ON
ON
Table E1.42 J2 DIP Switch Settings - TFT (24Bit TTL/CMOS)
SW6
OFF
OFF
OFF
OFF
ON
SW5
OFF
OFF
ON
SW4
OFF
ON
Resolution
Comments
Disabled
Reserved
OFF
ON
800 x 600
ON
1024 x 768
60Hz
Reserved
OFF
OFF
ON
OFF
ON
ON
Reserved
Reserved
Reserved
ON
OFF
ON
ON
ON
Note:
If an external DDC is found then the
switch settings SW1 to SW3 have no
effect. This applies to the digital TMDS
configuration only
PageE-10
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Appendix E
AGP-R7000
Note:
®
If the AGP piggyback is installed, the VGA
connector associated with the chipset
graphic must be removed. For this reason,
the AGP piggyback is NOT available as
an accessory to be added as an after
thought!
E1.5 Rear I/O VGA Interface
Refer to the rear I/O documentation for video interfacing connectivity.
C
E
ICP-P4/PM/CMAppendix-E
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