PRELIMINARY
Am79C930
PCnet™-Mobile
Single-Chip Wireless LAN Media Access Controller
DISTINCTIVE CHARACTERISTICS
■ Capable of supporting the IEEE 802.11 standard
parameters, and ISA Plug and Play
(draft)
configuration parameters
■ Supports the Xircom Netwave™ media access
■ Provides integrated Transceiver Attachment
Interface (TAI), supporting Frequency-Hopping
Spread Spectrum, Direct Sequence Spread
Spectrum, and infrared physical-layer
interfaces
control (MAC) protocols
■ Supports MAC layer functions
■ Individual 8-byte transmit and 15-byte receive
FIFOs
■ Antenna diversity selection support
■ Integrated intelligent 80188 processor for MAC
■ Fabricated with submicron CMOS technology
layer functions
with low operating current
■ Glueless PCMCIA bus interface conforming to
■ Supports dual 3 V and 5 V supply applications
PC Card standard—Feb. 1995
■ Low-power mode allows reduced power
consumption for critical battery-powered
applications
■ Full PCMCIA software interface support for PC
Card standard—Feb. 1995
■ Glueless ISA (IEEE P996) bus interface with full
■ 144-pin Thin Quad Flat Pack (TQFP) package
available for space-critical applications, such as
PCMCIA
support for Plug and Play release 1.0a
■ Glueless SRAM interface for MAC operations,
supporting up to 128 Kbytes of memory
■ JTAG Boundary Scan (IEEE 1149.1) test access
■ Glueless Flash memory interface, supporting
up to 128 Kbytes of non-volatile memory for
MAC control code, PCMCIA configuration
port for board-level production test
GENERAL DESCRIPTION
PCnet-Mobile (Am79C930) is the first in a series of mo-
bile networking products in AMD’s PCnet family. The
Am79C930 device is the first single-chip wireless LAN
media access controller (MAC) supporting the IEEE
802.11 (draft) standard and the Xircom Netwave™
MAC protocols. The Am79C930 device is designed to
have a flexible protocol engine to allow for industry
standard and proprietary protocols. Protocol firmware
for Xircom Netwave and IEEE 802.11 (draft) MAC pro-
tocols are supplied by AMD. It is pin-compatible with
the PCMCIA bus or the ISA (Plug and Play) bus
through a pin-strapping option.
transceiver attachment interface (TAI). The TAI sup-
ports frequency-hopping spread spectrum, direct
sequence spread spectrum, and infrared physical layer
interfaces. In addition, a power down function has been
incorporated to provide low standby current for power-
sensitive applications.
The Am79C930 device provides users with a media ac-
cess controller that has flexibility (i.e., bus interface,
protocol, and physical layer support) to allow the
design of multiple products using a single device. By
having all the necessary MAC functions on a single
chip, users only need to add memory and the physical
layer in order to deliver a fully functional wireless LAN
connection.
The Am79C930 device contains a PCMCIA/ISA bus
interface unit (BIU), a MAC control unit, and a
Publication# 20183 Rev: B Amendment/0
Issue Date: April 1997
This document contains information on a product under development at Advanced Micro Devices. The
information is intended to help you evaluate this product. AMD reserves the right to change or discontinue
work on this proposed product without notice.
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P R E L I M I N A R Y
BLOCK DIAGRAM
PCMCIA Mode
TRST
JTAG
Control
Block
TMS/T3
TDI/T1
TDO/T2
MOE
MWE
MA 16–0
MD 7–0
RXCIN
ANTSLT
ANTSLT
SAR6–0
ADIN2–1
ADREF
RXDATA
XCE
SCE
FCE
RXC
USER6–0
A14–0
D7–0
REG
SDCLK
SDDATA
SDSEL3–1
TXCMD
TXCMD
TXMOD
TXDATA
TXDATA
RXPE
Transceiver
Attachment
Interface
CA16–8
CAD 7–0
INT1
DRQ0
DRQ1
INT0
CE1
OE
Bus
Interface
Unit
MAC
Control
Unit
IORD
ALE
IOWR
RESET
WE
(PCMCIA)
(80188 core)
WR
TXPE
HFPE
SRDY
WAIT
HFCLK
LFPE
INPACK
IREQ
UCS
LCS
LFCLK
FDET
STSCHG
PMX2–1
LNK
RESET
ACT
CLKIN
TEST
PWRDWN
20183B-1
Am79C930
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BLOCK DIAGRAM
Bus Interface Unit
MD[7:0] MA[16:0]
System
Interrupt
Generator
IREQ
CA16
Latch
ALE
A14–0 or
LA23–17, SA16–0
CA15–8
CAD7–0
Address Buffer
Data Buffer
Bus
Multi-
plexer
D7–0
MIR0
MIR1
...
SIR0
SIR1
...
MIR15
SIR7
MOE
MWE
UCS
LCS
Slave
Control
PCMCIA
and ISA
Memory
and I/O
PCMCIA
or
ISA Control Signals
Slave
Control
and
Arbitration
for
Memory
Interface
Bus
SRDY
XCE
PCMCIA
Config Registers
FCE
Plug and Play
Control Module
TAICE
SCE
80188
ISA Memory Base
ISA I/O Base
Interrupt
Generator
INT1
RESET
CLKIN
20183B-2
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BLOCK DIAGRAM
Transceiver Attachment Interface Unit
Transceiver
Control
Signals
IRQ
Interrupt
Generator
Transceiver Interface
Unit Control
MD[7:0]
TIR0
TIR...
TIR31
TCR0
TCR...
TCR31
TX
RX
FIFO
FIFO
8
15
Bytes
Bytes
P->S
MUX
S->P
TAICE
Slave
C
R
C
Slave
Control
MA[4:0]
DRQ[1:0]
Control
Memory
Interface
Bus I/O
C
R
C
and DMA
FDET
SFD
Detect
RXCSEL
RXCIN
Count
M
U
X
MUX
C
Phylen
DPLL
RXD
TXD
TXC
÷80
÷40
÷5
÷10
÷20
BIAS
Suppress
M
U
X
Sleep
RESET
RXC
CLKIN
20183B-3
Am79C930
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P R E L I M I N A R Y
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
PCMCIA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Transceiver Attachment Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PCMCIA BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PCMCIA CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PCMCIA PIN SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PCMCIA PIN LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Listed By Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PCMCIA PIN FUNCTION SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PCMCIA Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ISA PLUG AND PLAY BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ISA Plug And Play . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ISA PLUG AND PLAY PIN LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Listed By Pin Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ISA PLUG AND PLAY PIN SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pins with Internal Pull Up or Pull Down Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Host System Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PCMCIA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ISA (IEEE P996) Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Clock Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
System Management Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TAI Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
IEEE 1149.1 Test Access Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Analog Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Digital Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Multi-Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Pin 1: USER2/LA19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin 2: USER3/SA16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Pin 3: USER4/LA17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin 45: STSCHG/BALE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin 90: USER0/RFRSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin 91: USER1/IRQ12/EXTCTS/EXINT188 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pin 92: USER7/IRQ11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pin 94: RXC/IRQ10/EXTA2DST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Pin 95: USER6/IRQ5/EXTSDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Pin 96: USER5/IRQ4/EXTCHBSY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Pin 98: ACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Pin 100: LNK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Pin 101: SDCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Pin 102: SDDATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Pin 103: SDSEL3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Pin 105: SDSEL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Pin 107: SDSEL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Pin 115: TXC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Pin 118: LFPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Pin 120: HFPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Pin 122: RXPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Pin 126: TXCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Pin 129: TXPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Pin 131: TXMOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Pin 132: ANTSLT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Pin 141: ANTSLT/LA23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Pin 142: TXCMD/LA21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Pin 143: TXDATA/LA20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Pin 144: LLOCKE/SA15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Basic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
System Bus Interface Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Memory Bus Interface Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Software Interface Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Network Interface Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Detailed Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Block Level Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PCMCIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
ISA (IEEE P996) Plug and Play Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Embedded 80188 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Media Access Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Medium Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SRAM Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Flash Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Transceiver Attachment Interface Unit Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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Bus Interface Unit Interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Transceiver Attachment Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
TX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
TX Power Ramp Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Am79C930-based TX Power Ramp Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Transceiver-Based TX Power Ramp Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
TX CRC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
TX Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Start of Frame Delimiter Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
RX Data Parallelization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
RX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
RX CRC Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
RX Status Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Bit Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
RSSI A/D Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Physical Header Accommodation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DC Bias Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Baud Determination Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Clear Channel Assessment Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Automatic Antenna Diversity Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
TXC As Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
IEEE 1149.1 Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Boundary Scan Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
TAP FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Supported Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Instruction Register and Decoding Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Other Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Power Down Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Applicability to IEEE 802.11 Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Am79C930 System Interface Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PCMCIA Mode Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PCMCIA Attribute Memory Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PCMCIA I/O Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
ISA Plug and Play Mode Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
ISA Plug and Play Memory Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
ISA Plug and Play I/O Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
ISA Plug and Play Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
MAC Firmware Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
MAC (80188 core) Memory Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
MAC (80188 core) Memory Resources Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
MAC (80188 core) Interrupt Channel Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
MAC (80188 core) DMA Channel Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DMA Channel Allocation In The 80188 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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P R E L I M I N A R Y
LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
RESET Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SWRESET (SIR0[7]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
CORESET (SIR0[6]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
PCMCIA COR SRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ISA PnP RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SRES (TIR0[5]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
System Interface Registers (SIR space) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SIR0: General Configuration Register (GCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SIR1: Bank Switching Select Register (BSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SIR2: Local Memory Address Register [7:0] (LMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SIR3: Local Memory Address Register [14:8] (LMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SIR4: I/O Data Port A (IODPA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SIR5: I/O Data Port B (IODPB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SIR6: I/O Data Port C (IODPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SIR7: I/O Data Port D (IODPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
MAC Interface Registers (MIR Space) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
MIR0: Processor Interface Register (PIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
MIR1: Power Up Clock Time [3:0] (PUCT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
MIR2: Power Down Length Count [7:0] (PDLC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
MIR3: Power Down Length Count [15:8] (PDLC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
MIR4: Power Down Length Count [22:16] (PDLC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
MIR5: Free Count [7:0] (FCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
MIR6: Free Count [15:8] (FCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
MIR7: Free Count [23:16] (FCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
MIR8: Flash Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
MIR9: TCR Mask STSCHG Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
MIR10: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
MIR11: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
MIR12: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
MIR13: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
MIR14: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
MIR15: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Transceiver Attachment Interface Registers (TIR Space) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
TIR0: Network Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
TIR1: Network Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
TIR2: Serial Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
TIR3: Fast Serial Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
TIR4: Interrupt Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
TIR5: Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
TIR6: Interrupt Unmask Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
TIR7: Interrupt Unmask Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
TIR8: Transmit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
TIR9: Transmit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
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P R E L I M I N A R Y
TIR10: TX FIFO Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
TIR11: Transmit Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
TIR12: Byte Count Register LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
TIR13: Byte Count Register MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
TIR14: Byte Count Limit LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
TIR15: Byte Count Limit MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
TIR16: Receiver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
TIR17: Receive Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
TIR18: RX FIFO Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
TIR19: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
TIR20: CRC32 Correct Byte Count LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
TIR21: CRC32 Correct Byte Count MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
TIR22: CRC8 Correct Byte Count LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
TIR23: CRC8 Correct Byte Count MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
TIR24: TCR Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
TIR25: Configuration Data Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
TIR26: Antenna Diversity and A/D Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
TIR27: Serial Approximation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
TIR28: RSSI Lower Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
TIR29: USER Pin Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
TIR30: Test Dummy Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
TIR31: TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
TAI Configuration Register space (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
TCR0: Network Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
TCR1: Transmit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
TCR2: Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
TCR3: Receive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
TCR4: Antenna Diversity Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
TCR5: TX Ramp Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
TCR6: TX Ramp Down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
TCR7: Pin Data A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
TCR8: Start Delimiter LSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
TCR9: Start Delimiter CSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
TCR10: Start Delimiter MSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
TCR11: Interrupt Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
TCR12: Interrupt Unmask Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
TCR13: Pin Configuration A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
TCR14: Pin Configuration B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
TCR15: Pin Configuration C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
TCR16: Baud Detect Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
TCR17: Baud Detect Lower Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
TCR18: Baud Detect Upper Limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
TCR19: Baud Detect Accept Count for Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
TCR20: Baud Detect Accept Count for Stop Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
TCR21: Baud Detect Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
TCR22: Baud Detect Accept Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
TCR23: Baud Detect Fail Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
10
Am79C930
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AMD
P R E L I M I N A R Y
TCR24: RSSI Sample Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
TCR25: RSSI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
TCR26: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
TCR27: TIP LED Scramble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
TCR28: Clear Channel Assessment Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
TCR29: Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
TCR30: Pin Function and Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
TCR31: Device Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
PCMCIA CCR Registers and PCMCIA CIS Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
PCMCIA Card Configuration and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
PCMCIA Card Information Structure (CIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
5.0 V Am79C930 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
3.3 V Am79C930 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
IEEE 1149.1 DC Characteristics (5.0 and 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.0 and 3.3 V PCMCIA Interface AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
PCMCIA MEMORY READ ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
PCMCIA MEMORY WRITE ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
PCMCIA I/O READ ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
PCMCIA I/O WRITE ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.0 AND 3.3 V ISA INTERFACE AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
ISA ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5.0 V MEMORY BUS INTERFACE AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
MEMORY BUS READ ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
MEMORY BUS WRITE ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
3.3 V MEMORY BUS INTERFACE AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
MEMORY BUS READ ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
MEMORY BUS WRITE ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.0 V TAI INTERFACE AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
3.3 V TAI INTERFACE AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.0 AND 3.3 V USER PROGRAMMABLE PINS AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 146
5.0 AND 3.3 V IEEE 1149.1 INTERFACE AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
ANALOG-TO-DIGITAL (A/D) CONVERTER CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Am79C930
11
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AMD
P R E L I M I N A R Y
TIMING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
PCMCIA Bus Interface Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
ISA Bus Interface Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Memory Bus Interface Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
CLOCK WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
TAI WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
PROGRAMMABLE INTERFACE WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
IEEE 1149.1 INTERFACE WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
AC TEST REFERENCE WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
5.0 V PCMCIA AC Test Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
3.3 V PCMCIA AC Test Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
5.0 V NON-PCMCIA AC Test Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
3.3 V NON-PCMCIA AC Test Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
APPENDIX A: Typical Am79C930 System Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
12
Am79C930
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P R E L I M I N A R Y
PCMCIA CONNECTION DIAGRAM
1
2
108
USER2
USER3
USER4
VDDM
XCE
MA11
VSSM
MA9
SAR0
SDSEL1
VSST
SDSEL2
VDDT
SDSEL3
ADDATA
SDCLK
LNK
VSST
ACT
VDDU1
USER5
USER6
RXC
VSSU1
USER7
USER1
USER0
VCC
TDI
TRST
TMS
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
3
4
5
6
7
8
9
MA8
MA13
MWE
MA14
MA16
MA15
MA12
VDDM
VCC
MA7
MA6
MA5
VSSM
MA4
MA3
MA2
MA1
MA0
MD0
MD1
VDDM
MD2
MD3
10
11
12
13
14
15
16
17
18
19
Am79C930
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
TDO
TCK
PMX1
PMX2
TEST
CLK20
PCMCIA
D3
D4
VSSP
D5
VSSM
MD4
MD5
MD6
MD7
35
36
D6
D7
20183B-4
Notes:
Pin 1 is marked for orientation.
NC = No Connection
Am79C930
13
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P R E L I M I N A R Y
PCMCIA PIN SUMMARY
Listed by Pin Number
Pin No.
1
Pin Name
USER2
Pin No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Pin Name
MA10
Pin No.
73
Pin Name
Pin No.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Pin Name
SAR1
D7
D6
D5
2
USER3
USER4
VDDM
XCE
MOE
SCE
FCE
D2
74
SAR2
3
75
SAR3
4
76
VSSP
D4
SAR4
5
77
SAR5
6
MA11
VSSM
MA9
D1
78
D3
SAR6
7
D0
79
PCMCIA
CLK20
TEST
PMX2
PMX1
TCK
TXC
8
VSSP
STSCHG
A0
80
VSST
9
MA8
81
LFCLK
LFPE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
MA13
MWE
MA14
MA16
MA15
MA12
VDDM
VCC
82
A1
83
HFCLK
HFPE
REG
A2
84
85
TDO
TXDATA
RXPE
INPACK
A3
86
TMS
87
TRST
TDI
RXDATA
RXCIN
VDDT
WAIT
A4
88
89
VCC
MA7
A7
90
USER0
USER1
USER7
VSSU1
RXC
TXCMD
VSS
MA6
VDDP
A12
VSS
91
MA5
92
FDET
VSSM
MA4
93
TXPE
RESET
A5
94
VSST
MA3
95
USER6
USER5
VDDU1
ACT
TXMOD
ANTSLT
PWRDWN
ADIN1
ADIN2
AVSS
MA2
A6
96
MA1
IREQ
WE
97
MA0
98
MD0
A14
A13
A8
99
VSST
LNK
MD1
100
101
102
103
104
105
106
107
108
VDDM
MD2
SDCLK
SDDATA
SDSEL3
VDDT
SDSEL2
VSST
SDSEL1
SAR0
ADREF
AVDD
IOWR
IORD
A9
MD3
VDD5
VSSM
MD4
VDDU2
ANTSLT
TXCMD
TXDATA
LLOCKE
A11
OE
MD5
MD6
A10
CE1
MD7
14
Am79C930
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P R E L I M I N A R Y
PCMCIA PIN LIST
Listed by Pin Name
Pin Name
Pin No.
Pin Name
HFPE
Pin No.
120
50
67
66
61
117
118
144
100
26
25
37
6
Pin Name
Pin No.
70
Pin Name
TXMOD
Pin No.
131
129
90
A0
46
47
OE
A1
INPACK
IORD
IOWR
IREQ
LFCLK
LFPE
LLOCKE
LNK
PCMCIA
PMX1
PMX2
PWRDWN
REG
79
TXPE
USER0
USER1
USER2
USER3
USER4
USER5
USER6
VCC
A10
A11
A12
A13
A14
A2
71
83
69
82
91
56
133
48
1
64
2
63
RESET
RXC
58
3
49
94
96
A3
51
RXCIN
RXDATA
RXPE
SAR0
124
123
122
108
109
110
111
112
113
114
39
95
A4
53
MA0
17
A5
59
MA1
VCC
89
A6
60
MA10
MA11
MA12
MA13
MA14
MA15
MA16
MA2
VDD5
VDDM
VDDM
VDDM
VDDP
VDDT
VDDT
VDDU1
VDDU2
VSS
139
4
A7
54
SAR1
A8
65
15
10
12
14
13
24
23
22
20
19
18
9
SAR2
16
A9
68
SAR3
29
ACT
98
SAR4
55
ADIN1
ADIN2
ADREF
ANTSLT
ANTSLT
AVDD
AVSS
CE1
134
135
137
132
141
138
136
72
SAR5
104
125
97
SAR6
SCE
MA3
SDCLK
SDDATA
SDSEL1
SDSEL2
SDSEL3
STSCHG
TCK
101
102
107
105
103
45
140
57
MA4
MA5
VSS
127
7
MA6
VSSM
VSSM
VSSM
VSSP
VSSP
VSST
VSST
VSST
VSST
VSSU1
WAIT
MA7
21
CLK20
D0
80
MA8
32
43
MA9
8
84
44
D1
42
MD0
27
28
30
31
33
34
35
36
38
11
TDI
88
76
D2
41
MD1
TDO
85
99
D3
78
MD2
TEST
81
106
116
130
93
D4
77
MD3
TMS
86
D5
75
MD4
TRST
87
D6
74
MD5
TXC
115
126
142
121
143
D7
73
MD6
TXCMD
TXCMD
TXDATA
TXDATA
52
FCE
40
MD7
USER7
WE
92
FDET
HFCLK
128
119
MOE
MWE
62
XCE
5
Am79C930
15
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P R E L I M I N A R Y
PCMCIA PIN FUNCTION SUMMARY
PCMCIA Pin Summary
No. of
Pins
15
8
Pin Name
A14–A0
Pin Function
Pin Style
PCMCIA address bus lines
PCMCIA data bus lines
PCMCIA bus RESET line
I
TS2
I
D7–D0
RESET
1
Card Enable 1—used to enable the D7–0 pins for PCMCIA Read and Write
accesses
1
CE1
I
Output Enable—used to enable the output drivers of the Am79C930 device for
PCMCIA Read accesses
1
1
1
OE
I
I
I
WE
REG
Write Enable—used to indicate that the current PCMCIA cycle is a write access
REG—used to indicate that the current PCMCIA cycle is to the Attribute
Memory space of the Am79C930 device
Input Acknowledge—used to indicate that the Am79C930 device will respond
to the current I/O read cycle
1
1
1
INPACK
WAIT
TS1
TS2
Wait—used to delay the termination of the current PCMCIA cycle
I/O Read—this signal is asserted by the PCMCIA host system whenever an
I/O read operation occurs
IORD
I/O Write—this signal is asserted by the PCMCIA host system whenever an
I/O write operation occurs
1
1
IOWR
IREQ
I
Interrupt Request—this line is asserted when the Am79C930 device needs
servicing from the software
PTS3
1
1
1
STSCHG
PCMCIA
PWRDWN
Status Change—PCMCIA output used only for WAKEUP signaling
PCMCIA mode—selects PCMCIA or ISA Plug and Play mode
Powerdown—indicates that device is in the power down mode
PTS1
I
TP1
Memory Address Bus—these lines are used to address locations in the Flash
device, the SRAM device, and an extra peripheral device that are contained
within an Am79C930-based design
17
8
MA16–0
MD7–0
FCE
TP1
TS1
TP1
Memory Data Bus—these lines are used to write and read data to/from Flash,
SRAM, and/or an extra peripheral device within an Am79C930-based design
Flash Chip Enable—this signal becomes asserted when the Flash device has
been addressed by either the 80188 core of the Am79C930 device or by the
software through the PCMCIA interface
1
SRAM Chip Enable—this signal becomes asserted when the SRAM device
has been addressed by either the 80188 core of the Am79C930 device or by
the software through the PCMCIA interface
1
1
SCE
XCE
TP1
TP1
eXtra Chip Enable—this signal becomes asserted when the extra peripheral
device has been addressed by the 80188 core of the Am79C930 device (XCE
is not accessible through the system interface)
Memory Output Enable—this signal becomes asserted during reads of devices
located on the memory interface bus
1
1
MOE
MWE
TP1
TP1
Memory Write Enable—this signal becomes asserted during writes to devices
located on the memory interface bus
1
1
TCK
TDI
Test Clock—this is the clock signal for IEEE 1149.1 testing
I
I
Test Data In—this is the data input signal for IEEE 1149.1 testing
16
Am79C930
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P R E L I M I N A R Y
PCMCIA PIN FUNCTION SUMMARY (continued)
PCMCIA Pin Summary (continued)
No. of
Pins
Pin Name
Pin Function
Pin Style
1
1
1
1
1
TDO
TMS
Test Data Out—this is the data output signal for IEEE 1149.1 testing
Test Mode Select—this is the test mode select for IEEE 1149.1 testing
Test Reset—this is the reset signal for IEEE 1149.1 testing
User-programmable pin
TS1
I
TRST
USER7
RXC
I
PTS3
PTS3
Receive Clock—provides decode receive clock
Test pin—when asserted, this pin places the Am79C930 device into a
nonstandard factory-only test mode
1
1
TEST
I
I
Clock input to drive BIU, 80188 core, and TAI, supplying network data rate
information
CLKIN
2
1
PMX1–2
TXC
Power Management Xtal—32-kHz Xtal input for sleep timer reference
Transmit Clock—may be configured either as input or output
I/XO
TS1
Low Frequency Power Enable—used to power up the low-frequency section of
the transceiver
1
LFPE
PTS1
1
1
LFCLK
Low Frequency Clock—a reference signal for the transceiver synthesizer
Low Frequency Synthesizer Lock—a programmable signal
TS1
LLOCKE
PTS1
High Frequency Power Enable—used to power up the high-frequency section
of the transceiver
1
HFPE
PTS1
1
2
2
HFCLK
High Frequency Clock—a reference signal for the transceiver synthesizer
Antenna Select—used to select between two antennas
TS1
PTS1
ANTSLT, ANTSLT
TXCMD, TXCMD
Transmit Command—used to select the transmit path in the transceiver
TP1, PTS1
Transmit Power Enable—used to power up the transmit section of the
transceiver
1
TXPE
TP1
2
1
1
1
1
1
1
1
3
1
1
TXDATA, TXDATA
TXMOD
RXPE
Transmit Data—supplies the transmit data stream to the transceiver
Transmit Modulation Enable—enables the modulation of transmit data
Receive Power Enable—enables the receive function of the transceiver
Receive Data—accepts receive data in NRZ format from the transceiver
Frame Detect—start of frame delimiter detection indication
TP1, PTS1
TP1
PTS1
I
RXDATA
FDET
TS1
RXCIN
Receive Clock Input—optional clock input that allows for an external PLL
Serial Data Clock—clock output used to access serial peripheral devices
Serial Data Data—data pin used to access serial peripheral devices
Serial Data Select—chip select outputs used to select serial peripheral devices
Activity LED—output capable of driving an LED
IPU
SDCLK
PTS1
PTS1
PTS1
PTS2
PTS2
SDDATA
SDSEL3–SDSEL1
ACT
LNK
Link LED—output capable of driving an LED
A/D Reference—an input that can be used to set the analog reference voltage
for the internal A/D converter
1
7
ADREF
I
Serial Approximation Register—supplies the value of the serial approximation
register used in the A/D converter
SAR6–SAR0
TS1
Am79C930
17
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P R E L I M I N A R Y
PCMCIA PIN FUNCTION SUMMARY (continued)
PCMCIA Pin Summary (continued)
No. of
Pins
Pin Name
ADIN1–2
Pin Function
Comparator—A/D comparator inputs
Pin Style
2
TS1
12
13
VCC
Power
I
I
GND
Ground
User-definable I/O pins with direct accessibility and control through TCR and
TIR registers
7
USER0–USER6
PTS3, PTS1
Output Driver Types
Name
Type
IOL
IOH
Load
50 pF
50 pF
120 pF
50 pF
50 pF
120 pF
120 pF
50 pF
TP1
TS1
Totem pole
Tri-state
4 mA
4 mA
24 mA
4 mA
12 mA
24 mA
24 mA
NA
–4 mA
–4 mA
–4 mA
–4 mA
–4 mA
–4 mA
–4 mA
NA
TS2
Tri-state
PTS1
PTS2
PTS3
OD2
XO
User-programmable tri-state
User-programmable tri-state
User-programmable tri-state
Open drain
Xtal amplifier output
Input Types
Name
I
Type
Size of Pullup
Size of Pulldown
Input
NA
>50K Ω
NA
NA
NA
IPU
IPD
Input with internal pullup device
Input with internal pulldown device
>50K Ω
18
Am79C930
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P R E L I M I N A R Y
ISA PLUG AND PLAY BLOCK DIAGRAM
TRST
JTAG
Control
Block
TMS/T3
TDI/T1
TDO/T2
MOE
MWE
MA 16–0
MD 7–0
RXCIN
ANTSLT
ANTSLT
SAR6–0
ADIN2–1
ADREF
RXDATA
XCE
SCE
FCE
RXC
LA23–17
SA126–0
SD7–0
AEN
SDCLK
SDDATA
SDSEL3–1
TXCMD
TXCMD
TXMOD
TXDATA
TXDATA
RXPE
IEEE
802.11
Network
CA16–18
CAD 7–0
INT1
Interface Unit
DRQ0
DRQ1
INT0
BALE
Bus
Interface Unit
(ISA
IEEE
802.11
MAC
MEMR
IOR
ALE
Plug and Play)
Control Unit
(80188 core)
IOW
RESET
MEMW
IOCHRDY
IRQ(X)
RFRSH
WR
RESET
TXPE
HFPE
SRDY
HFCLK
LFPE
UCS
LCS
LFCLK
FDET
LNK
PMX2–1
RESET
ACT
CLK20
TEST
PWRDWN
20183B-5
Am79C930
19
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P R E L I M I N A R Y
ISA PLUG AND PLAY CONNECTION DIAGRAM
1
2
LA19
SA16
LA17
VDDM
XCE
MA11
VSSM
MA9
SAR0
SDSEL1
VSST
SDSEL2
VDDT
SDSEL3
ADDATA
SDCLK
LNK
VSST
ACT
VDDU1
IRQ4
108
107
106
105
104
103
3
4
5
6
7
8
9
102
101
100
99
98
97
96
95
94
93
MA8
MA13
MWE
MA14
MA16
MA15
MA12
VDDM
VCC
MA7
MA6
MA5
VSSM
MA4
MA3
MA2
MA1
MA0
MD0
MD1
VDDM
MD2
MD3
10
11
12
13
14
IRQ5
IRQ10
VSSU1
IRQ11
IRQ12
RFRSH
VCC
TDI
TRST
TMS
15
16
17
18
19
92
91
90
89
Am79C930
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
TDO
TCK
PMX1
PMX2
TEST
CLK20
PCMCIA
SD3
SD4
VSSP
SD5
VSSM
MD4
MD5
MD6
MD7
SD6
SD7
35
36
20183B-6
Notes:
Pin 1 is marked for orientation.
NC = No Connection
20
Am79C930
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P R E L I M I N A R Y
ISA PLUG AND PLAY PIN LIST
Listed by Pin Number
Pin No.
1
Pin Name
LA19
Pin No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Pin Name
MA10
Pin No.
73
Pin Name
Pin No.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Pin Name
SAR1
SD7
SD6
SD5
2
SA16
LA17
VDDM
XCE
MOE
SCE
74
SAR2
SAR3
SAR4
SAR5
SAR6
TXC
3
75
4
FCE
76
VSSP
SD4
5
SD2
77
6
MA11
VSSM
MA9
SD1
78
SD3
7
SD0
79
PCMCIA
CLK20
TEST
PMX2
PMX1
TCK
8
VSSP
BALE
SA0
80
VSST
LFCLK
LFPE
9
MA8
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
MA13
MWE
MA14
MA16
MA15
MA12
VDDM
VCC
82
SA1
83
HFCLK
HFPE
TXDATA
RXPE
RXDATA
RXCIN
VDDT
TXCMD
VSS
AEN
84
SA2
85
TDO
LA22
SA3
86
TMS
87
TRST
TDI
IOCHRDY
SA4
88
89
VCC
MA7
SA7
90
RFRSH
IRQ12
IRQ11
VSSU1
IRQ10
IRQ5
MA6
VDDP
SA12
VSS
91
MA5
92
FDET
TXPE
VSST
TXMOD
ANTSLT
PWRDWN
ADIN1
ADIN2
AVSS
VSSM
MA4
93
RESET
SA5
94
MA3
95
MA2
SA6
96
IRQ4
MA1
IRQ9
MEMW
SA14
SA13
SA8
97
VDDU1
ACT
MA0
98
MD0
99
VSST
LNK
MD1
100
101
102
103
104
105
106
107
108
VDDM
MD2
SDCLK
SDDATA
SDSEL3
VDDT
SDSEL2
VSST
SDSEL1
SAR0
ADREF
AVDD
VDD5
VDDU2
LA23
IOW
MD3
IOR
VSSM
MD4
SA9
SA11
MEMR
SA10
LA18
MD5
LA21
MD6
LA20
MD7
SA15
Am79C930
21
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P R E L I M I N A R Y
ISA PLUG AND PLAY PIN LIST
Listed by Pin Name
Pin Name
ACT
Pin No.
98
Pin Name
MA11
Pin No.
6
Pin Name
Pin No.
47
Pin Name
SDSEL2
Pin No.
105
103
84
SA1
ADIN1
ADIN2
ADREF
AEN
134
135
137
48
MA12
MA13
MA14
MA15
MA16
MA2
15
10
12
14
13
24
23
22
20
19
18
9
SA10
SA11
SA12
SA12
SA13
SA14
SA15
SA16
SA2
71
SDSEL3
TCK
69
56
TDI
88
56
TDO
85
ANTSLT
AVDD
AVSS
BALE
CLK20
FCE
132
138
136
45
64
TEST
TMS
81
63
86
MA3
144
2
TRST
TXC
87
MA4
115
126
121
131
129
17
80
MA5
49
TXCMD
TXDATA
TXMOD
TXPE
VCC
40
MA6
SA3
51
FDET
HFCLK
HFPE
IOCHRDY
IOR
128
119
120
52
MA7
SA4
53
MA8
SA5
59
MA9
8
SA6
60
MD0
27
28
30
31
33
34
35
36
70
62
38
11
79
83
82
133
58
90
124
123
122
46
SA7
54
VCC
89
67
MD1
SA8
65
VDD5
VDDM
VDDM
VDDM
VDDP
VDDT
VDDT
VDDU1
VDDU2
VSS
139
4
IOW
66
MD2
SA9
68
IRQ10
IRQ11
IRQ12
IRQ4
94
MD3
SAR0
SAR1
SAR2
SAR3
SAR4
SAR5
SAR6
SCE
108
109
110
111
112
113
114
39
16
92
MD4
29
91
MD5
55
96
MD6
104
125
97
IRQ5
95
MD7
IRQ9
61
MEMR
MEMW
MOE
LA17
3
140
57
LA18
72
LA19
1
MWE
PCMCIA
PMX1
PMX2
PWRDWN
RESET
RFRSH
RXCIN
RXDATA
RXPE
SA0
SD0
43
VSS
127
7
LA20
143
142
50
SD1
42
VSSM
VSSM
VSSP
VSSP
VSST
VSST
VSST
VSST
VSSU1
XCE
LA21
SD2
41
32
LA22
SD3
78
44
LA23
141
117
118
100
26
SD4
77
76
LFCLK
LFPE
LNK
SD5
75
99
SD6
74
106
116
130
93
SD7
73
MA0
SDCLK
SDDATA
SDSEL1
101
102
107
MA1
25
MA10
37
5
22
Am79C930
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P R E L I M I N A R Y
ISA PLUG AND PLAY PIN SUMMARY
No. of
Pins
Pin Name
LA23–LA17
Pin Function
Pin Style
7
17
8
ISA upper address bus lines
ISA lower address bus lines
ISA data bus lines
I
SA16–SA0
SD7–SD0
RESET
I
TS2
I
1
RESET input
Memory Read—used to enable the output drivers of the Am79C930 device for
ISA bus memory read accesses
1
MEMR
I
Memory Write—used to indicate that the current ISA bus cycle is a memory
write access
1
1
1
1
1
MEMW
AEN
I
Address Enable—used to indicate that the current ISA bus I/O address is valid
I
Bus Address Latch Enable—used to indicate that the ISA address lines are
valid
BALE
I
IOCHRDY
IOR
I/O Channel Ready—used to delay the termination of the current ISA bus cycle
TS2
I
I/O Read—this signal is asserted by the ISA host system whenever an I/O read
operation occurs
I/O Write—this signal is asserted by the ISA host system whenever an I/O write
operation occurs
1
6
IOW
I
Interrupt Request—this line is asserted when the Am79C930 device needs
servicing from the software
IRQ4, 5, 9, 10, 11, 12
PTS3/OD2
1
1
1
RFRSH
Refresh—indicates that the current ISA bus cycle is a refresh operation
PCMCIA mode—selects PCMCIA or ISA Plug and Play mode
Powerdown—indicates that device is in the power down mode
I
I
PCMCIA
PWRDWN
TP1
Memory Address Bus—these lines are used to address locations in the Flash
device, the SRAM device, and an extra peripheral device that are contained
within an Am79C930-based design
17
8
MA16–0
MD7–0
FCE
TP1
TS1
TP1
Memory Data Bus—these lines are used to write and read data to/from Flash,
SRAM, and/or an extra peripheral device within an Am79C930-based design
Flash Chip Enable—this signal becomes asserted when the Flash device has
been addressed by either the 80188 core of the Am79C930 device or by the
software through the PCMCIA interface
1
SRAM Chip Enable—this signal becomes asserted when the SRAM device
has been addressed by either the 80188 core of the Am79C930 device or by
the software through the PCMCIA interface
1
1
SCE
XCE
TP1
TP1
eXtra Chip Enable—this signal becomes asserted when the extra peripheral
device has been addressed by the 80188 core of the Am79C930 device (XCE
is not accessible through the system interface)
Memory Output Enable—this signal becomes asserted during reads of devices
located on the memory interface bus
1
1
MOE
MWE
TP1
TP1
Memory Write Enable—this signal becomes asserted during writes to devices
located on the memory interface bus
1
1
1
1
1
TCK
TDI
Test Clock—this is the clock signal for IEEE 1149.1 testing
Test Data In—this is the data input signal for IEEE 1149.1 testing
Test Data Out—this is the data output signal for IEEE 1149.1 testing
Test Mode Select—this is the test mode select for IEEE 1149.1 testing
Test Reset—this is the reset signal for IEEE 1149.1 testing
I
I
TDO
TMS
TRST
TS1
I
I
Test pin—when asserted, this pin places the Am79C930 device into a
non-IEEE 1149.1 test mode
1
TEST
I
Clock input to drive BIU, 80188 core, and TAI, supplying network data rate
information
1
2
CLKIN
I
PMX1–2
Power Management Xtal—32-kHz Xtal input for sleep timer reference
I/XO
Am79C930
23
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P R E L I M I N A R Y
ISA PLUG AND PLAY PIN SUMMARY (continued)
No. of
Pins
Pin Name
Pin Function
Pin Style
1
1
1
1
TXC
Transmit Clock—may be configured either as input or output
TS1
Low Frequency Power Enable—used to power up the low-frequency section of
the transceiver
LFPE
PTS1
TS1
LFCLK
HFPE
Low Frequency Clock—a reference signal for the transceiver synthesizer
High Frequency Power Enable—used to power up the high-frequency section
of the transceiver
PTS1
1
1
1
HFCLK
ANTSLT
TXCMD
High Frequency Clock—a reference signal for the transceiver synthesizer
Antenna Select—used to select between two antennas
TS1
PTS1
TP1
Transmit Command—used to select the transmit path in the transceiver
Transmit Power Enable—used to power up the transmit section of the
transceiver
1
TXPE
TP1
1
1
1
1
1
1
1
1
3
1
1
TXDATA
TXMOD
RXPE
Transmit Data—supplies the transmit data stream to the transceiver
Transmit Modulation Enable—enables the modulation of transmit data
Receive Power Enable—enables the receive function of the transceiver
Receive Data—accepts receive data in NRZ format from the transceiver
Frame Detect—start of frame delimiter detection indication
TP1
TP1
PTS1
I
RXDATA
FDET
TS1
RXCIN
Receive Clock Input—optional clock input that allows for an external PLL
Serial Data Clock—clock output used to access serial peripheral devices
Serial Data Data—data pin used to access serial peripheral devices
Serial Data Select—chip select outputs used to select serial peripheral devices
Activity LED—output capable of driving an LED
IPU
SDCLK
SDDATA
SDSEL3–SDSEL1
ACT
PTS1
PTS1
PTS1
PTS2
PTS2
LNK
Link LED—output capable of driving an LED
A/D Reference—an input that can be used to set the analog reference voltage
for the internal A/D converter
1
7
ADREF
I
Serial Approximation Register—supplies the value of the serial approximation
register used in the A/D converter
SAR6–SAR0
TS1
2
ADIN1–2
VCC
Comparator—A/D comparator inputs
TS1
12
13
Power
I
I
GND
Ground
Output Driver Types
Name
Type
IOL
IOH
load
50 pF
50 pF
120 pF
50 pF
50 pF
120 pF
120 pF
NA
TP1
TS1
Totem pole
Tri-state
4 mA
–4 mA
–4 mA
–4 mA
–4 mA
–4 mA
–4 mA
–4 mA
NA
4 mA
TS2
Tri-state
24 mA
4 mA
PTS1
PTS2
PTS3
OD2
XO
User-programmable tri-state
User-programmable tri-state
User-programmable tri-state
Open drain
12 mA
24 mA
24 mA
Output
Xtal amplifier
Input Types
Name
I
Type
Size of Pullup
Size of Pulldown
Input
NA
>50K Ω
NA
NA
NA
IPU
IPD
Input with internal pullup device
Input with internal pulldown device
>50K Ω
24
Am79C930
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AMD
P R E L I M I N A R Y
Following the RESET operation, the Am79C930 firm-
ware or driver software should appropriately program
the D bits of TIR and TCR registers, and then set the FN
and EN bits of TIR and TCR registers to set the values
and directions of each of these programmable pins.
Once these operations have been performed, the soft-
ware should then program the INITDN bit of MIR9 in or-
der to disable all of the pull up and pull down devices.
Unused programmable pins should be programmed for
output mode, or may be left in the default high imped-
ance state if an external pull down or pull up device is left
connected to the pin. Unused programmable pins must
not be programmed for input mode with no external
source (pull-device or driver) connected and the INITDN
bit of MIR9 set to a 1, since this could lead to unaccept-
able levels of power consumption by the Am79C930 de-
vice. For more information on programmable pins, see
the Multi-Function Pins section.
PIN DESCRIPTIONS
Pins with Internal Pull Up or Pull
Down Devices
Several pins of the Am79C930 device include internal
pull up or pull down devices. With the exception of the
RESET pin, these pins are fully programmable as inputs
or outputs when the PCMCIA mode has been selected.
A subset of these pins is programmable when the ISA
Plug and Play mode has been selected. These pins will
come up after RESET in the high impedance state with
the pull up or pull down device actively determining the
value of the pin, unless an external driving source
overdrives the pull up or pull down device. VINITDN
bit (MIR9[2]) is used to turn off all pull up and pull
down devices.
The following list indicates those pins that contain pull
up and pull down devices:
Configuration Pins
PCMCIA
PCMCIA Mode
Pin Name
Internal Device
Type
Size of Internal
Device
PCMCIA/ISA Bus Interface Select
Input
USER[6]/IRQ5
USER[5]/IRQ4
USER[4]/LA17
USER[3]/SA16
USER[2]/LA19
USER[1]/IRQ12
USER[0]/RFRSH
LLOCKE/SA15
ANTSLT/LA23
TXDATA/LA20
TXCMD/LA21
RXC/IRQ10
USER7/IRQ11
LFPE
pull up
pull up
pull up
pull up
pull up
pull down
pull down
pull down
pull up
pull up
pull down
pull up
pull up
pull up
pull up
pull up
pull down
pull up
pull up
pull up
pull up
pull up
pull up
pull up
pull up
pull up
pull up
pull up
pull up
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
> 100K Ω
The value of this pin will asynchronously determine the
operating mode of the Am79C930 device, regardless of
the state of the RESET pin and regardless of the state of
the CLKIN pin. If the PCMCIA pin is tied to VCC, then the
Am79C930 controller will be programmed for PCMCIA
Bus Mode. If the PCMCIA pin is tied to VSS, then the
Am79C930 controller will be programmed for ISA Plug
and Play Bus Interface Mode.
HFPE
RXPE
ANTSLT
TXCMD
TXPE
SDCLK
SDDATA
SDSEL[3]
SDSEL[2]
SDSEL[1]
ACT
LNK
TXMOD
STSCHG/BALE
TXC
Am79C930
25
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P R E L I M I N A R Y
The functionality of the following pins is determined, at
least in part, by the connection of the PCMCIA pin:
D7–0
Data Bus
Input/Output
Signals D7 through D0 are the bidirectional data bus for
PCMCIA. The most significant bit is D7.
PCMCIA Mode
Pin Name
ISA Plug and Play Mode
Pin Name
USER6
USER5
USER4
USER3
USER2
USER1
USER0
A[14:0]
LLOCKE
D[7:0]
USER6/IRQ5
USER5/IRQ4
LA17
OE
Output Enable
Input
OE is an active low-output-enable input signal. OE is
used to gate memory read data from the Am79C930 de-
vice onto the PCMCIA data bus. OE should be deas-
serted during memory write cycles to the Am79C930
device. OE is used for Common memory accesses and
Attribute memory accesses.
SA16
LA19
USER1/IRQ12
RFRSH
SA[14:0]
SA15
INPACK
Input Acknowledge
Output
The INPACK signal is an active low signal. INPACK is
asserted when the Am79C930 device is selected and
the Am79C930 device can respond to an I/O read cycle
at the address currently on the address bus. This signal
is used by the host to control the enable of any input data
buffer between the card and the CPU. This signal will be
inactive until the card is configured.
SD[7:0]
LA18
CE1
OE
MEMR
MEMW
AEN
WE
REG
TXDATA
TXCMD
INPACK
ANTSLT
WAIT
LA20
IORD
I/O Read
LA21
Input
LA22
IORD is an active low signal. IORD is asserted by the
host system to indicate to the Am79C930 device that a
read from the Am79C930’s I/O space is being per-
formed. The Am79C930 device will not respond to the
IORD signal until it has been configured for I/O opera-
tion by the system.
LA23
IOCHRDY
BALE
STSCHG
IORD
IOR
IOWR
IOW
IOWR
IREQ
IRQ9
I/O Write
Input
RXC
RXC/IRQ10
USER7/IRQ11
IOWR is an active low signal. IOWR is asserted by the
host system to indicate to the Am79C930 device that a
write to the Am79C930’s I/O space is being performed.
TheAm79C930devicewillnotrespondtotheIOWR sig-
nal until it has been configured for I/O operation by
the system.
USER7
Host System Interface Pins
PCMCIA Bus Interface
A14–0
Address Bus
Input
IREQ
Interrupt Request
Output
Signals A0 through A14 are address-bus-input lines.
Signal A0 is always used because the data interface to
the Am79C930 is only 8-bits wide.
IREQ is an active low signal. IREQ is asserted by the
Am79C930 device to indicate to the host that software
service is required. IREQ can operate in the pulse mode
or level mode of operation as defined in the PCMCIA
specification. In pulse mode of operation, an interrupt is
signaled by the Am79C930 device by asserting a low-
going pulse of at least 0.5 microseconds (µs). In pulse
mode of operation, the inactive state (i.e., HIGH output)
is driven, not floated. In level mode of operation, an in-
terrupt is signaled by the Am79C930 device by assert-
ing a LOW level. In level mode of operation, the inactive
state (i.e., HIGH output) is driven, not floated.
CE1
Card Enable
Input
CE1 is an active low card enable input signal. CE1 is
used to enable even-numbered word address bytes. A0
is used to select between the even and odd numbered
bytes within the addressed word.
26
Am79C930
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D7–0
P R E L I M I N A R Y
Function Mode
REG
CE1
H
L
IORD IOWR
A0
X
L
OE
X
L
WE
X
Standby mode
X
H
H
H
H
L
X
H
H
H
H
H
H
H
H
L
X
H
H
H
H
H
H
H
H
H
H
L
High-Z
Common Memory Read Even Byte
Common Memory Read Odd Byte
Common Memory Write Even Byte
Common Memory Write Odd Byte
Attribute Memory Read Even Byte
Attribute Memory Read Odd Byte
Attribute Memory Write Even Byte
Attribute Memory Write Odd Byte
I/O Read Even Byte
H
H
L
Even Byte
Odd Byte
Even Byte
Odd Byte
Even Byte
Odd Byte
Even Byte
Odd Byte
Even Byte
Odd Byte
Even Byte
Odd Byte
L
H
L
L
L
H
H
L
L
H
L
L
L
H
H
L
L
L
H
L
L
L
L
H
H
H
H
H
H
L
L
H
L
L
L
L
H
H
H
H
I/O Read Odd Byte
L
L
L
H
L
I/O Write Even Byte
L
L
H
H
I/O Write Odd Byte
L
L
L
H
device from the PCMCIA data bus. WE should be deas-
serted during memory read cycles to the Am79C930.
WE is used for Common memory accesses and Attrib-
ute memory accesses.
REG
Attribute Memory Select
Input
REG is an active low-input signal that selects among At-
tributememoryandCommonmemoryintheAm79C930
device and the Am79C930-based PCMCIA card. When
REG is asserted, then the current access is to Attribute
memory or I/O. When REG is not asserted, then the cur-
rent access is to Common memory.
ISA (IEEE P996) Bus interface
LA23–17, SA16–0
Address Bus
Input
Signals SA0 through SA16 and LA17 through LA23
areaddress-bus-inputlineswhichenabledirectaddress
of up to 16 Mbytes of memory space in an ISA-based
Am79C930design. SignalSA0isalwaysused, because
the data interface to the Am79C930 is only 8-bits wide.
RESET
Reset
Input
RESET is an active high-input signal that clears the
Card Configuration Option Register CCOR) and places
the Am79C930 device into an unconfigured (PCMCIA-
Memory-Only Interface) state. This pin also causes a
RESET to be asserted to each of the Am79C930 core
function units (i.e., PCMCIA interface, CPU, and Trans-
ceiver Attachment Interface).
SD7–0
Data Bus
Input/Output
Signals SD7 through SD0 are the bidirectional data bus
for ISA. The most significant bit is SD7.
AEN
Address Enable
STSCHG
Status Change
Input
Output
AEN is driven LOW by the ISA host to indicate when an
I/O address is valid.
TheSTSCHG signal is an active low signal.STSCHG as
implemented in the Am79C930 device is only used for
the PCMCIA WAKEUP indication. The CHANGED bit
and the SIGCHG bit of the Card Configuration and
Status Register (CCSR) are not supported by the
Am79C930 device. The Pin Replacement Register is
not supported by the Am79C930 device.
BALE
Bus Address Latch Enable
Input
BALE is driven by the ISA host to indicate when the ad-
dress signal lines are valid.
WAIT
Extend Bus Cycle
IOCHRDY
I/O Channel Ready
Output
Output
The WAIT signal is an active low signal. WAIT is as-
serted by the Am79C930 device to delay completion of
the access cycle currently in progress.
The IOCHRDY signal is deasserted by the Am79C930
device at the beginning of a memory access in order
to delay completion of the memory access cycle then
in progress. The IOCHRDY signal is reasserted by
the Am79C930 device when the memory access
is completed.
WE
Write Enable
Input
WE is an active low write-enable input signal. WE is
used to strobe memory write data into the Am79C930
Am79C930
27
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P R E L I M I N A R Y
Memory Interface Pins
IOR
I/O Read
Input
MA16–0
Memory Address Bus
The IOR signal is made active by the ISA host in order to
Output
read data from the Am79C930 device’s I/O space.
Signals MA0 through MA16 are address-bus-output
lines which enable direct address of up to 128 Kbytes of
SRAM memory and 128 Kbytes of Flash memory in a
Am79C930-based application. The Am79C930 device
will drive these signals to Access memory locations
within the SRAM or the Flash memory.
IOW
I/O Write
Input
TheIOW signalismadeactivebytheISAhostinorderto
write data to the Am79C930 device’s I/O space.
MEMR
Memory Read
FCE
Input
Flash Memory Chip Enable
Output
The MEMR signal is made active by the ISA host in
order to read data from the Am79C930 device’s
memory space.
FCE is an active low chip enable output signal. FCE is
used to activate the Flash memory device’s control logic
and input buffers during accesses on the memory
interface bus.
MEMW
Memory Write
Input
MD7–0
Memory Data Bus
Input/Output
The MEMW signal is made active by the ISA host in
order to write data to the Am79C930 device’s
memory space.
Signals MD7 through MD0 are the bidirectional data bus
for the SRAM and the Flash memory. The most signifi-
cant bit is MD7.
IRQ[4,5,9–12]
Interrupt Request
Output
MOE
Memory Output Enable
Output
IRQ[x] is asserted by the Am79C930 device to indicate
to the host that software service is required. IRQ[x] is
held at the inactive level when no interrupt is requested.
Only one of the six IRQ[x] lines may be selected for use
at any one time. IRQ[x] outputs may be programmed for
edge or level operation. Edge or level programming is
part of the ISA Plug and Play initialization procedure.
When edge programming has been selected, then the
selected IRQ[x] pin is driven to a HIGH level to indicate
an active interrupt request, and the selected IRQ[x] pin
is driven to a low level to indicate an inactive interrupt re-
quest. When level programming has been selected,
then the selected IRQ[x] pin is driven to a LOW level and
the selected IRQ pin is floated to indicate an inactive
interrupt request (i.e., open drain operation). “Unused”
(i.e., unselected) IRQ[x] lines will be held in a
high impedance state, even when interrupt service
is requested.
MOE is an active low output that is used to gate the out-
puts of the SRAM and Flash memory device’s during
read cycles.
SCE
SRAM Chip Enable
Output
SCE is an active low chip enable output signal. SCE
is used to activate the SRAM device’s control logic and
input buffers during accesses on the memory
interface bus.
MWE
Memory Write Enable
Output
MWE isanactivelowoutputthatisusedtolatchaddress
and data information in the SRAM and Flash memory
devices during write cycles. Address information for
SRAM and Flash memory write cycles is valid on the
MA16–0 pins at the falling edge of MWE. Data informa-
tion for SRAM and Flash memory write cycles is valid on
the MD7–0 pins at the rising edge of MWE.
RESET
Reset
Input
RESET is an active high input signal. When driven to a
HIGH level, RESET causes the Am79C930 device to
immediately place all ISA bus outputs into a high imped-
ance state. This pin also causes a RESET to be as-
serted to each of the Am79C930 core function units (i.e.,
ISA interface state machine, 80188, and Transceiver
Attachment Interface).
XCE
eXtra Chip Enable
Output
XCE is an active low chip enable output signal. XCE is
used to activate a peripheral device’s control logic and
input buffers during accesses on the memory interface
bus. XCE is activated by appropriate signaling from the
80188 embedded core. XCE may not be activated
through the system interface. Sixteen bytes of address
range are allotted for use with the XCE signal.
RFRSH
Refresh
Input
The RFRSH signal is made active by the ISA host to in-
dicate that the current bus cycle is a refresh operation.
28
Am79C930
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Clock Pins
of TXC, allowing ample setup and hold time for valid
sampling of TXDATA with the rising edge of TXC.
CLKIN
System Clock
Input
Some systems may require that the Am79C930 device
deliver the transmit data according to a clock reference
that is external to the Am79C930 device. In such sys-
tems, the TXC pin may be configured as an input.
TXDATA will change on falling edges of TXC, allowing
ample setup and hold time for valid sampling of
TXDATA with the rising edge of TXC.
CLKIN is the clock input for the Am79C930 device’s
logic functions. CLKIN is used to drive the CLKIN input
of the embedded 80188 core. The BIU section uses the
CLKOUT signal from the 80188 embedded core as a
reference. The register interface portions of the TAI use
the CLKIN signal as a reference. The TAI uses a divided
version of this clock to obtain a reference clock for data
transmission, where the divisor value is selectable
through a register; this allows different data rates to be
set. The TAI DPLL clock recovery circuit will use a refer-
ence clock that is 20 times the selected data rate, when-
ever the ECLK bit of the Receiver Configuration
Register (TCR3) is set to a 0. This DPLL reference
clock is also derived from the CLKIN signal. When the
ECLK bit is set to 1, the TAI DPLL is not used, and the
incoming receive data stream is clocked with the RXCIN
signal. The highest frequency allowed at the CLKIN in-
put is 40 MHz.
System Management Pins
PWRDWN
Power Down
Output
PWRDWN is an active high output that indicates that the
Am79C930 device has been placed into a low power
mode to conserve power. While PWRDWN is asserted,
the internal clock that is routed to the 80188 embedded
core and the network interface (TAI section) has been
halted. PCMCIA CCRs and SIRs are still active while in
the low power mode.
USER[0–6]
User-Definable Pins
PMX[1–2]
Power Management Crystal
Input/Output
Input/Output
USER[0–6] are pins that are controlled directly through
TIR and TCR registers. These pins may serve as out-
puts, inputs or as I/O through the use of high-impedance
control and data bits in TIR and TCR registers. These
pins are available only in PCMCIA mode.
PMX[1–2] are the reference crystal inputs for the clock
that drives the power management logic. The nominal
frequency for this crystal input is 32 kHz.
RXCIN
Receive Clock In
Input
Note: Some of the TAI interface pins are similarly
programmable, thereby allowing some user-defined
functionality when using the ISA Plug and Play mode
of operation.
RXCIN is the reference clock input for the receive data
stream entering the Am79C930 device when the ECLK
bit of TCR2 is set to a 1. Rising edges of the RXCIN input
will mark valid sample points for the data arriving at the
RXDATA input.
TAI Interface Pins
ANTSLT
RXC
Antenna Select
Output
Receive Clock Out
Output
ANTSLT is an active high output that indicates to the
transceiver which antenna should be utilized for both
transmission and reception. ANTSLT allows for selec-
tion among two possible antennas.
RXC is the reference clock output for the receive data
stream that is derived either from the DPLL or from the
RXCIN pin, depending on the selected Am79C930 de-
vice configuration. This clock is provided for test pur-
poses only. This function is only available when the
Am79C930 device is programmed for the PCMCIA
mode of operation.
ANTSLT
Antenna Select
Output
ANTSLTisanactivelowoutputthatisthelogicalinverse
of the ANTSLT output. This signal is only available when
the Am79C930 device is configured for the PCMCIA
mode of operation.
TXC
Transmit Clock
Input/Output
TXC is the clock reference for data transmission at the
network interface. Some systems may require that the
Am79C930 device deliver the transmit data with a clock
for reference. In such systems, the TXC pin may be
configured as an output and the TXC signal will be
generatedbytheAm79C930deviceasaderivativefrom
the CLKIN input. TXDATA will change on falling edges
FDET
Frame Detect
Output
FDET is an active low output that indicates when the
Am79C930 device has located the Start of Frame De-
limiter in the receive or transmit data stream. This signal
Am79C930
29
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is deasserted when the RESET pin is issued or the CRC
reset bit is set to 1 (SIR0); when the TXS bit is set to 1
(TIR8) or the RXS bit is set to 1 (TIR16); when TXRES
bit set to 1 (TIR8), or the RXRES bit is set to 1 (TIR16), or
the SRES bit is set to 1 (TIR0).
PLL is used for clock recovery, then the RXDATA input
will expect valid data at rising edges of the RXCIN input.
External versus internal PLL use is determined through
the setting of the ECLK bit in TCR2.
RXPE
Receiver Power Enable
HFCLK
High Frequency Clock
Output
Output
RXPE isanactivelowoutputthatisusedtopowerupthe
receive section of the transceiver. This pin is directly
controllable through a TAI register and is also program-
mable as an I/O with read capability.
HFCLK provides a reference clock for a transceiver syn-
thesizer. The clock rate is equal to the clock rate of the
CLKIN signal when the CLKGT20 bit of MIR9 is set to 0,
and is equal to one-half the clock rate of the CLKIN sig-
nal when the CLKGT20 bit of MIR9 is set to 1. No phase
relationship to CLKIN is guaranteed. HFCLK will be
LOW whenever the HFPE signal is inactive.
TXCMD
Transmit Command
Output
TXCMD is an active low output that is used to enable the
transceiver’s transmission onto the medium. When
TXCMD is low, the transceiver should enable its trans-
mission function and disable its receive function. When
TXCMD is high, the transceiver should disable its
transmission function and return to receive functionality.
This pin is directly controlled by the transmit state
machine in the TAI and the TXCMD bit of TIR11. The
timing of the TXCMD signal is programmable from a TAI
register. The polarity of this pin is programmable from a
TAI register.
HFPE
High Frequency Power Enable
Output
HFPE is an active low output that is used to power up the
high-frequency VCO section of the transceiver. This pin
is directly controllable through a TAI register and is also
programmable as an I/O with read capability.
LFCLK
Low Frequency Clock
Output
LFCLK provides a reference clock for a transceiver syn-
thesizer. The clock rate is equal to the clock rate of the
CLKIN signal when the CLKGT20 bit of MIR9 is set to 0,
and is equal to one half the clock rate of the CLKIN sig-
nal when the CLKGT20 bit of MIR9 is set to 1. No phase
relationship to CLKIN is guaranteed. LFCLK will be
LOW whenever the LFPE signal is inactive.
TXCMD
Transmit Command
Output
TXCMD is an active high output that is the logical in-
verse of the TXCMD output. This signal is only available
when the Am79C930 device is configured for the
PCMCIA mode of operation.
LFPE
TXDATA
Transmit Data
Low Frequency Power Enable
Output
Output
LFPE is an active low output that is used to power up the
low-frequency synthesizer section of the transceiver.
This pin is directly controllable through a TAI register
and is also programmable as an I/O with read capability.
TXDATA is an output that provides the serial bit stream
for transmission, including preamble, SFD, PHY
header, MAC header, data and FCS field, or a subset
thereof. Data delivered from the MAC to the transceiver
is valid at the rising edge of TXC and changes on the fall-
ing edge of TXC. The value of the TXDATA pin is pro-
grammable to 1, 0, or “last bit transmitted” whenever the
transmit circuit is idle and during ramp up and ramp
down of the transceiver’s transmit circuits.
LLOCKE
Synthesizer Lock
Input
LLOCKE is a general-purpose input that can be used to
convey a transceiver’s synthesizer lock signal to the
80188 embedded controller. The value of the LLOCKE
pin is readable at a register bit in the TIR register space.
TXDATA
Transmit Data
Output
RXDATA
TXDATA is an output that is the logical inverse of the
TXDATA output. This signal is only available when the
Am79C930 device is configured for the PCMCIA mode
of operation. The value of the TXDATA pin is 0 when-
ever the transmit circuit is idle and during ramp up and
ramp down of the transmitter.
Receive Data
Input
RXDATA is an input that accepts the serial bit stream for
reception, including Preamble, SFD, PHY header, MAC
header, Data and FCS field. The RXDATA input stream
is expected to be NRZ data. Clock recovery is per-
formed internal to the Am79C930 device. If an external
30
Am79C930
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A/D converter. Only one input will be sampled at any
time for conversion by the internal Am79C930 device’s
A/D circuit. The input that will be converted by the
A/D circuit is determined by the setting of the SRCS bit
of the Antenna Diversity and A/D Control register in the
TAI (TIR26).
TXMOD
Transmit Modulation Enable
Output
TXMOD is an active low output that is used to enable the
transmit modulation function of the attached trans-
ceiver. Thispinisdirectlycontrolledbythetransmitstate
machine in the TAI and the TXMOD bit of TIR11. The
timing of the TXMOD signal is programmable from a TAI
register. The polarity of this pin is programmable from a
TAI register.
LNK
Link LED
Output
LNK is an active low open collector output that is directly
controllable through a TAI register. This pin is capable of
sinking the 12 mA necessary to drive a typical indicator
LED. This pin is directly controllable through a TAI regis-
ter and is also programmable as an I/O with read capa-
bility. This pin may also be programmed to actively drive
high output values. When an LED is connected to this
pin, then proper operation of this output requires a
pull-up device to be connected externally.
TXPE
Transmit Power Enable
Output
TXPE is an active low output that is used to enable the
transceiver’s transmission amplifier. WhenTXPE is low,
the transceiver should enable its transmission amplifier.
When TXPE is high, the transceiver should disable its
transmission amplifier. This pin is directly controlled by
the transmit state machine in the TAI and theTXPE bit of
the TIR11. The timing of the TXMOD signal is program-
mable from a TAI register. The polarity of this pin is pro-
grammable from a TAI register.
PWRDWN
Powerdown
Output
PWRDWN is an output that becomes active (HIGH)
when the Am79C930 device enters the power down
mode. This pin can be used to power down other sec-
tions of a Am79C930-based system design.
USER7
USER7
Input/Output
USER7 is a pin that may be directly controlled through
TIR and TCR register locations.
SAR[6–0]
Serial Approximation Register
Input/Output
Other Pins
SAR[6–0] are outputs that are used to deliver the value
of the internal A/D converter for use external to the
Am79C930 device. These pins are directly controllable
through a TAI register and are also programmable as
I/O pins with read capability.
ACT
Activity LED
Output
ACT is an active low open collector output that is directly
controllable through a TAI register. This pin is capable of
sinking the 12 mA necessary to drive a typical indicator
LED. This pin is directly controllable through a TAI regis-
ter and is also programmable as an I/O with read capa-
bility. This pin may also be programmed to actively drive
high output values. When an LED is connected to this
pin, then proper operation of this output requires a
pull-up device to be connected externally.
SDCLK
Serial Device Clock
Output
SDCLK is an output that is used to clock data on the
SDDATA output pin. This pin may be used in combina-
tion with the SDDATA andSDSEL output pins in order to
create an I2C serial device interface. This pin is directly
controllable through a TAI register and is also program-
mable as an I/O with read capability.
ADREF
A/D Reference
Input
ADREF is a single-ended analog input that is used by
the A/D conversion circuit. ADREF is the reference volt-
age that is fed to the resistor ladder of the D/A portion of
the A/D circuit. ADREF is used to determine the range of
sensitivity of the A/D circuit. The recommended value
for ADREF is 1.25 to 1.75 V. Note that ADREF is volt-
age-doubled before being used for internal A/D refer-
ence. For example, an ADREF value of 1.75 V will mean
that the A/D will give a max digital output value for an
ADIN input of 3.5 V or higher.
SDDATA
Serial Device Data
Input/Output
SDDATA is an I/O pin that may be used in conjunction
with the SDCLK and SDSEL pins in order to create an
I2C serial device interface. This pin is directly controlla-
ble through a TAI register and is also programmable as
an I/O with read capability.
SDSEL[1–3]
Serial Device Select
Output
SDSEL[1–3] are output pins that may be used in con-
junctionwiththeSDCLKandSDSEL pinsinordertocre-
ate an I2C serial device interface. These pins are directly
controllable through a TAI register and are also pro-
grammable as I/O pins with read capability.
ADIN[1–2]
A/D sample inputs
Input/Output
ADIN[1–2] are inputs that accept single-ended analog
input values for conversion by the internal Am79C930
Am79C930
31
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P R E L I M I N A R Y
supply voltage. Special attention should be paid to the
IEEE 1149.1 Test Access Port Pins
printed circuit board layout to avoid excessive noise on
the AVDD line.
TCK
Test Clock
Input
TCK is the clock input for the boundary scan test mode
operation. TCK frequency may be as high as 10 MHz.
TCK does not have an internal pull-up resistor and must
be connected to a valid TTL or CMOS level at all times.
TCK must not be left unconnected.
AVSS
Analog Ground (1 Pin)
Ground
There is one analog ground pin. This ground pin pro-
vides ground reference to the analog section of the
Am79C930 device. This pin must always be connected
to a ground supply. Special attention should be paid to
the printed circuit board layout to avoid excessive noise
on the AVSS line.
TDI
Test Data Input
Input
TDI is the test data input path to the Am79C930 device.
If left unconnected, this pin has a default value of HIGH.
VDD5
A/D Power (1 Pins)
Power
TDO
Test Data Output
There is one A/D power supply pin. This pin provides
power to the A to D converter circuit. This pin must
always be connected to a 5 V supply unless the A/D
function of the device is not required. If the A/D function
of the device is not required, then this pin may be con-
nected to either a 5 V supply or to a 3.3 V supply. How-
ever, all analog power pins (AVDD and VDD5) must be
connected to the same supply voltage. Special attention
should be paid to the printed circuit board layout to avoid
excessive noise on the VDD5 line.
Output
TDO is the test data output path from the Am79C930 de-
vice. TDO is tri-stated when the JTAG port is inactive.
TMS
Test Mode Select
Input
TMS is a serial input bit stream is used to define the spe-
cific boundary scan test to be executed. If left uncon-
nected, this pin has a default value of HIGH.
Digital Power Supply Pins
TRST
Test Reset
Input
VDDT
Transceiver Power (2 Pins)
When asserted, TRST will asynchronously reset the
IEEE 1149.1 state. The reset state of the IEEE 1149.1
state machine is FFh.
Power
There are two transceiver interface power supply pins.
These pins provide power to the transceiver interface
buffers and drivers on pins 98 through 133. These pins
maybeconnectedtoeithera5.0Vsupplyora3.3Vsup-
ply, but both of these pins must be connected to the
same supply voltage.
Test Pin
TEST
Test
Input
The TEST pin should be tied HIGH and is reserved for
internal factory test only.
VSST
Transceiver Ground (4 Pins)
Ground
Power Supply Pins
There are four transceiver interface ground pins. These
pins provide ground reference to the transceiver
interface buffers and drivers on pins 98 through 133. In
both 5 V and 3 V systems, these pins should be con-
nected to a ground supply.
Analog Power Supply Pins
AVDD
Analog Power (1 Pin)
Power
There is one analog 5 V supply pin. This supply pin pro-
vides power to the analog section of the Am79C930 de-
vice. This pin must always be connected to 5 V, unless
the A/D function of the device is not required. If the A/D
function of the device is not required, then this pin may
be connected to either a 5 V supply or to a 3.3 V supply.
Note: A/D must be disabled. However, all analog power
pins (AVDD and VDD5) must be connected to the same
VCC
Core Logic Power (2 Pins)
Power
There are two core logic power supply pins. These pins
provide power to the core logic and must always be
less than or equal to VDDT, VDDU1, VDDU2, VDDP,
and VDDM.
32
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VDDT, VDDU1,
VDDU2, VDDP,
VDDM
VSSP
Acceptable
AVDD, VDD5 Combination
PCMCIA Ground (2 Pins)
Ground
VCC
5 V
There are two PCMCIA ground pins. These pins provide
ground reference to the PCMCIA and Power Manage-
ment Crystal buffers and drivers on pins 41 through 83.
In both 5 V and 3 V systems, these pins should be con-
nected to a ground supply.
All at 5 V
All at 5 V
Both at 5 V
Both at 5 V
Both at 5 V
Yes
Yes
Yes
3 V
3 V
Any Combination
of 3 V and 5 V
3 V
5 V
5 V
All at 3 V
All at 3 V
Both at 5 V
Both at 5 V
Both at 5 V
Yes
No
VDDM
Memory Interface Power (3 Pins)
Power
Any Combination
of 3 V and 5 V
No
There are three Memory Interface power supply pins.
These pins provide power to the Memory Interface buff-
ers and drivers on pins 4 through 40. These pins may be
connected to either a 5.0 V supply or to a 3.3 V supply,
but all three of these pins must be connected to the
same supply voltage.
5 V
All at 5 V
Any
Combination
of 3 V and 5 V
No
Also, AVDD and VDD5 must be tied to 5 V, if A/D func-
tion is required. VDDT, VDDU1, VDDU2, VDDP, and
VDDM do not have to have the same voltage. If VCC =
3 V, any combination of 5 V or 3 V for VDDXX will work.
VSSM
Memory Interface Ground (3 Pins)
Ground
There are three Memory Interface ground pins. These
pins provide ground reference to the Memory Interface
buffers and drivers on pins 4 through 40. In both 5 V and
3 V systems, these pins should be connected to a
ground supply.
VSS
Core Logic Ground (2 Pins)
Ground
There are two core logic ground pins. These pins
provide ground reference to the core logic. In both 5 V
and 3 V systems, these pins should be connected to a
ground supply.
Multi-Function Pins
The Am79C930 device includes a number of pins which
have multiply-defined functions. The various functions
assigned to each of these pins is determined through
both device pin settings and through individual register
bit settings. This section explains the functional modes
of each of the multi-function pins and gives tables that
indicate the proper programming for each pin.
VDDU1
User Pin Power (1 Pin)
Power
There is one VDDU1 power supply pin. This pin pro-
vides power to the buffers and drivers on pins 84
through 96. This pin may be connected to either a 5 V
supply or to a 3.3 V supply.
Pins in this section are listed by pin number.
Where the PCMCIA pin is not listed in a table, it can be
inferred that the setting of the PCMCIA pin has no influ-
ence on the pin values.
VSSU1
Core Logic Ground (1 Pin)
Ground
There is one VSSU1 ground pin. This pin provides
ground reference to the buffers and drivers on pins 84
through 96. In both 5 V and 3 V systems, this pin should
be connected to a ground supply.
Under the column where pin directions are given in the
table, I = Input (high impedance), O = Output (totem
pole), OD = Open Drain.
Under the column where pin data is given in the table,
when the pin direction is given as Output, then the
pin data column indicates the source for the pin’s
output value.
VDDU2
User Pin Power (1 Pin)
Power
There is one VDDU2 power supply pin. This pin pro-
vides power to the buffers and drivers on pins 1 through
3 and pins 139 through 144. This pin may be connected
to either a 5 V supply or to a 3.3 V supply.
Under the column where pin data is given in the table,
when the pin direction is given as Input, then the pin data
column will indicate NA, since the source for the pin
value is external. Note that when any pin is configured
for an input function, the pin value is almost always
available at the pin data register. A note following each
table indicates the availability of the pin data with re-
spect to the pin data register bit.
VDDP
PCMCIA Power (1 Pin)
Power
There is one PCMCIA power supply pin. This pin pro-
vides power to PCMCIA and Power Management Crys-
tal buffers and drivers on pins 4l through 83. This
pin may be connected to either a 5 V supply or to a
3.3 V supply.
Note that in almost all cases, the pin data register bit will
always read the pin value, even if the pin is configured
Am79C930
33
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for an output function. This means that there are con-
figurations for which a read of the pin data register bit will
not reflect what has most recently been written to the pin
data register bit ( i.e., if a pin is configured as an output
with its data source as some internal circuit, then the
user may write the pin data bit with a given value, and a
read of this same bit will yield the output function value,
which may not necessarily match the value just written
to the data bit). This functionality is given as a note
following each table. Also note that for a few pins,
the read and write locations for the pin data are in
different places.
Note that a read of the USERDT[4] bit (TIR29[4]) will al-
ways give the current USER4/LA17 pin value, regard-
less of pin configuration setting.
Pin 45: STSCHG/BALE
The STSCHG/BALE pin may be configured for input op-
eration, output operation, or ISA BALE operation ac-
cording to the following table:
STSCHG/
BALE
STSCHG/
BALE
PCMCIA STSCHGFN
Pin
TCR15[0]
Pin Direction
Pin Data
0
X
I
NA
Pin 1: USER2/LA19
(BALE input
function)
The USER2/LA19 pin may be configured for input op-
eration, outputoperation, orISALA19operationaccord-
ing to the following table:
1
1
0
1
O
O
MIR9[0]
MIR9[0]
OR CCSR[4]
USER2/
LA19
USER2/
LA19
PCMCIA USER2EN
MIR9[0] is the STSCHGD bit. In PCMCIA mode,
STSCHGD basically acts like a UNMASKING function
for the STSCHG pin. STSCHGD can be used to prevent
the WAKEUP signal from the PCMCIA Card Configura-
tion and Status Register from being signaled on the
STSCHG pin. Note that if STSCHGFN is set to 1 and
STSCHGD is set to a 0, then the STSCHG pin will al-
ways be deasserted (i.e., it will be MASKED). With
STSCHGFN=1, writing a 1 to the STSCHGD bit will
UNMASK the WAKEUP status and allow it to be applied
to the STSCHG pin.
Pin
TCR14[2] Pin Direction
Pin Data
0
X
I
NA
(LA19 input function)
1
1
0
1
I
NA
O
TIR29[2]
Note that a read of the USERDT[2] bit (TIR29[2]) will al-
ways give the current USER2/LA19 pin value, regard-
less of pin configuration setting.
Pin 2: USER3/SA16
Note that the STSCHGD bit is automatically RESET to 0
whenever the WAKEUP bit of the PCMCIA Card Con-
figuration and Status Register is RESET to 0. Therefore,
the UNMASK bit (STSCHGD) needs to be set to
UNMASK (=1) for each new use of the WAKEUP signal.
The USER3/SA16 pin may be configured for input op-
eration, output operation, or ISA SA16 operation ac-
cording to the following table:
USER3/
SA16
USER3/
SA16
PCMCIA USER3EN
Pin
TCR14[3] Pin Direction
Pin Data
When STSCHGFN is set to 0, then the STSCHGD bit
will become an inverted source for the STSCHG
pin value.
0
X
I
NA
(SA16 input function)
1
1
0
1
I
NA
Note that a read of the STSCHGD bit (MIR9[0]) will al-
ways give the inverse of the current STSCHG/BALE pin
value, regardless of pin configuration setting.
O
TIR29[3]
Note that a read of the USERDT[3] bit (TIR29[3]) will al-
ways give the current USER3/SA16 pin value, regard-
less of pin configuration setting.
Pin 90: USER0/RFRSH
The USER0/RFRSH pin may be configured for input op-
eration, output operation, or ISA RFRSH operation ac-
cording to the following table:
Pin 3: USER4/LA17
The USER4/LA17 pin may be configured for input op-
eration, outputoperation, orISALA17operationaccord-
ing to the following table:
USER0/
RFRSH
Pin Direction
USER0/
RFRSH
Pin Data
PCMCIA USER0EN
Pin
TCR14[0]
USER4/
LA17
USER4/
LA17
0
X
I
NA
PCMCIA USER4EN
(RFRSH input
function)
Pin
TCR14[4] Pin Direction
Pin Data
0
X
I
NA
1
1
0
1
I
NA
(LA17 input function)
O
TIR29[0]
1
1
0
1
I
NA
O
TIR29[4]
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Note that a read of the USERDT[0] bit (TIR29[0]) will al-
waysgivethecurrentUSER0/RFRSHpinvalue, regard-
less of pin configuration setting.
Pin 91: USER1/IRQ12/EXTCTS/EXINT188
The USER1/IRQ12 pin may be configured for input
operation, output operation, or ISA IRQ12 operation ac-
cording to the following table:
USER1/
IRQ12
Pin Direction
USER1/
IRQ12
Pin Data
PCMCIA
Pin
USER1EN
TCR14[1]
IRQ Select
PnPx70
IRQ Type
PnPx71
0
0
0
0
1
1
X
X
0
1
0
1
Ch
Ch
≠Ch
≠Ch
X
2h
1h
X
O
OD
I
IRQ12
IRQ12
NA
X
O
I
TIR29[1]
NA
X
X
X
O
TIR29[1]
Note that a read of the USERDT[1] bit (TIR29[1]) will al-
ways give the current USER1/IRQ12 pin value, regard-
less of pin configuration setting.
tocontrolthestartoftheTXstatemachine, providedthat
Am79C930 device firmware has enabled the operation
by setting the TXS bit of TIR8.
In addition to the functionality listed above, the
USER1/IRQ12/EXTCTS/EXINT188 pin may be used to
enable the internal TX state machine. This capability is
controlled by the CTSEN bit of TCR7 and operates inde-
pendently of the table above and independently of the
U1INTCNT bits of TCR7. When the CTSEN bit of TCR7
is set to 1, then the value of the USER1/IRQ12/
EXTCTS/EXINT188 pin will be ANDed with the value of
the TXS bit of TIR8. The output of the AND gate will
then be used to determine the start of the TX state
machine. In this way, an external signal, through the
USER1/IRQ12/EXTCTS/EXINT188 input, can be used
In addition to the functionality listed above, the
USER1/IRQ12/EXTCTS/EXINT188 pin may be used to
produce interrupts to the 80188 embedded controller.
This capability is controlled by the U1INTCNT bits of
TCR7 and operates independently of the bits in the
table above and independently of the CTSEN bit of
TCR7.Interrupts that are routed through the
USER1/IRQ12/EXTCTS/EXINT188 pin are indicated in
the U1INT bit of TCR11. The following table lists the pro-
gramming options for using the USER1/IRQ12/
EXTCTS/EXINT188 pin as a source of external interrupt
to the 80188 controller.
U1INTCNT
TCR7[4:3]
USER1 Pin
Event
U1INT Bit
Result (TCR11[3])
00
01
10
11
X
0 => interrupt disabled
1 => interrupt signalled
1 => interrupt signalled
1 => interrupt signalled
reset default condition
rising edge
falling edge
rising or falling edge
Note that a read of the USER7DL bit (TIR29[7]) will al-
ways give the current USER7/IRQ11 pin value, regard-
less of pin configuration setting.
Pin 92: USER7/IRQ11
The USER7/IRQ11 pin may be configured for input op-
eration, output operation, or ISA IRQ11 operation ac-
cording to the following table:
USER7DL (TIR29[7]) gives the current value of the
USER7/IRQ11 pin.
USER7/
USER7/
PCMCIA
Pin
USER7FN
TC30[7]
USER7EN
TCR14[7]
IRQ Select
PnPx70
IRQ Type
PnPx71
IRQ11
Pin Direction
IRQ11
Pin Data
0
0
0
0
1
1
1
0
0
0
1
0
0
1
X
X
X
X
0
Bh
Bh
≠Bh
X
2h
1h
X
O
IRQ11
IRQ11
NA
OD
I
I
X
NA
X
X
I
NA
1
X
X
O
I
TIR29[7]
NA
X
X
X
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In addition to the functionality listed above, the RXC/
Pin 94: RXC/IRQ10/EXTA2DST
IRQ10/EXTA2DST pin may be used to control the start
of the A/D conversion process. When the UXA2DST
bit of TCR25 has been set to a 1, then the normal
internal state machine control of the A/D sample and
conversion procedure or a rising edge on the RXC/
IRQ10/EXTA2DST pin will trigger an A/D conversion
procedure. By allowing external control of the start of the
A/D conversion process, the EXTADTST input allows
synchronization of the internal A/D function to an exter-
nal circuit that desires to use the A/D converter.
The RXC/IRQ10 pin may be configured for input opera-
tion, output operation, ISA IRQ10 operation, and as an
output providing the RX clock information (whether de-
rived from the RXDATA stream through Am79C930
device DPLL operation or simply rerouted from the
RXCIN input) according to the following table:
Note that a read of the RXCD bit (TIR11[7]) will always
give the current RXC/IRQ10 pin value, regardless of pin
configuration setting.
RXC/
IRQ10
Pin Direction
RXC/
IRQ10
Pin Data
PCMCIA
Pin
RXCFN
TCR28[7]
RXCEN
TCR15[4]
IRQ Select
PnPx70
IRQ Type
PnPx71
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
X
X
0
1
X
0
1
X
Ah
Ah
≠Ah
≠Ah
X
2h
1h
X
O
OD
I
IRQ10
IRQ10
TIR11[7]
TIR11[7]
RXC
X
O
O
I
X
X
X
TIR11[7]
TIR11[7]
RXC
X
X
O
O
X
X
Pin 95: USER6/IRQ5/EXTSDF
The USER6/IRQ5/EXTSDF pin may be configured for
input operation, output operation, or ISA IRQ5 operation
according to the following table:
Note that a read of the USER6D bit (TIR11[6]) will al-
ways give the current USER6/IRQ5 pin value, regard-
less of pin configuration setting.
USER6/
IRQ5
Pin Direction
USER6/
IRQ5
Pin Data
PCMCIA
Pin
ENXSDF
TCR28[6]
USER6FN
TCR7[6]
USER6EN
TCR15[3]
IRQ Select
PnPx70
IRQ Type
PnPx71
0
0
0
0
0
0
0
1
1
1
1
X
X
0
0
0
0
1
0
0
X
0
0
0
0
1
1
X
X
X
X
X
X
0
1
0
1
X
0
1
X
5h
5h
≠5h
≠5h
X
X
2h
1h
X
I
O
OD
I
TIR11[6]
IRQ5
IRQ5
TIR11[6]
TIR11[6]
TIR11[6]
TIR11[6]
TIR11[6]
TIR11[6]
TIR11[6]
X
O
I
X
X
X
O
I
X
X
X
X
I
X
X
O
In addition to the functionality listed above, the
USER6/IRQ5/EXTSDF pin may be used to enable the
function of the RX state machine within the Am79C930
device. This capability is controlled by the ENXSDF bit
and the ENXCHBSY bit, both of TCR28. When the
ENXSDF bit and the ENXCHBSY bit of TCR28 are both
set to a 1 and either TCR28 bit 4 is set to 0 or an antenna
selection has been made, then the value of the
USER6/IRQ5/EXTSDF pin will be used to enable trans-
fers of RXD data into the RX FIFO, provided the
Am79C930 device firmware has previously enabled the
RX state machine by setting the RXS bit of TIR16. In
addition, theEXTSDFvaluewillbesenttotheSDFinter-
rupt bit of TIR5[2]. TIR5[2] will, if unmasked, produce an
interrupt to the 80188 embedded controller.
Note that setting the ENXSDF bit of TCR28 to a 1
will cause the USER6/IRQ5/EXTSDF pin to function as
an input, regardless of other control bit settings.
Pin 96: USER5/IRQ4/EXTCHBSY
The USER5/IRQ4 pin may be configured for input op-
eration, outputoperation, orISAIRQ4operationaccord-
ing to the table below.
Note that a read of the USER5D bit (TIR11[5]) will al-
ways give the current USER5/IRQ4/EXTCHBSY pin
value, regardless of pin configuration setting. In addition
to these bits, the USER5/IRQ4/EXTCHBSY pin may
be used to produce interrupts to the 80188 embedded
controller. This capability is controlled by the
36
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ENXCHBSY bit of TCR28 and the CHBSYU bit of
TIR5 and operates independently of the bits in the
table below.
This source of CCA information is controlled by the
ENXCHBSY bit of TCR28. When the ENXCHBSY bit of
TCR28 is set to a 1, then the value of the
USER5/IRQ4/EXTCHBSY pin will be fed directly to the
CHBSYC bit of TIR4, CHBSY bit of TIR26 and the BCF
bit of TIR5. If the CHBSYC interrupt is unmasked, it will
produce an interrupt to the 80188 embedded controller.
If the BCF interrupt is unmasked, it will produce an inter-
rupttothe80188embeddedcontroller. Notethatsetting
the ENXCHBSY bit of TCR28 to a 1 will cause the
USER5/IRQ4/EXTCHBYS pin to function as an input,
regardless of the settings of the other control
bits listed.
In addition to the functionality listed above, the
USER5/IRQ4/EXTCHBSY pin may be used as the
source for CCA information, instead of relying on the in-
ternal CCA logic of the Am79C930 device. When using
the external CCA information, CCA information from the
internal logic will be unavailable. External CCA informa-
tion will appear in the same register bit locations as in-
ternal CCA information, when enabled, so a change
from internal source to external source will be transpar-
ent to firmware (excepting the necessary change in the
ENXCHBSY bit value).
USER5/
IRQ4
Direction
USER5/
IRQ4
Pin Data
PCMCIA
Pin
ENXCHBSY
TCR28[5]
USER5FN
TCR7[5]
USER5EN
TCR15[2]
IRQ Select
PnPx70
IRQ Type
PnPx71
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
0
0
X
0
0
0
0
1
1
X
X
X
X
X
X
0
1
0
1
X
0
1
X
4h
4h
≠4h
≠4h
X
X
2h
1h
X
I
O
OD
I
TIR11[5]
IRQ4
IRQ4
TIR11[5]
TIR11[5]
TIR11[5]
TIR11[5]
TIR11[5]
TIR11[5]
TIR11[5]
X
O
I
X
X
X
O
I
X
X
X
X
I
X
X
O
Pin 98: ACT
The ACT pin may be configured for input or output op-
eration. The output drive may be programmed for totem
pole or open drain operation. ACT pin configuration is
accomplished according to the following table:
Note that a read of the ACT bit (TIR0[6]) will always
give the current ACT pin value, regardless of pin
configuration setting.
ACTEN
TCR15[1]
ACT
TIR0[6]
ACTDR
TCR27[3]
ACT Pin
Direction
ACT Pin
Value
0
1
1
1
1
X
0
1
0
1
X
0
0
1
1
I
NA
OD
OD
O
float
LOW
HIGH
LOW
reset default condition
O
Pin 100: LNK
The LNK pin may be configured for input or output op-
eration. The output drive may be programmed for totem
pole or open drain operation. LNK pin configuration is
accomplished according to the following table:
Note that a read of the LNK bit (TIR0[7]) will always
give the current LNK pin value, regardless of pin
configuration setting.
LNKEN
LNK
LNKDR
LNK Pin
LNK Pin
TCR13[7]
TIR0[7]
TCR27[4]
Direction
Value
0
1
1
1
1
X
0
1
0
1
X
0
0
1
1
I
NA
OD
OD
O
float
LOW
HIGH
LOW
reset default condition
O
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operation. SDCLKpinconfigurationisaccomplishedac-
Pin 101: SDCLK
cording to the following table:
The SDCLK pin may be configured for input or output
operation. Theoutputdrivemaybeprogrammedforreg-
ister-driven or auto-pulse generation. The auto-pulse
may be programmed for either active low or active high
Note that a read of the SDC bit (TIR2[2]) will always
give the current SDCLK pin value, regardless of pin
configuration setting.
SDCLKEN
TCR13[4]
SDCP
TIR2[3]
SDC
TIR2[2]
SDCLK Pin
Direction
SDCLK Pin
Value
0
1
1
1
1
X
0
1
0
1
X
0
0
1
1
I
NA
O
O
O
O
LOW
reset default condition
HIGH active pulse
HIGH
(when write to TIR2 occurs)
LOW active pulse
(when write to TIR2 occurs)
Pin 102: SDDATA
The SDDATA pin may be configured for input or output
operation. SDDATA pin configuration is accomplished
according to the following table:
Note that a read of the SDD bit (TIR2[0]) will always
give the current SDDATA pin value, regardless of pin
configuration setting.
SDDT
TIR2[1]
SDD
TIR2[0]
SDDATA Pin
Direction
SDDATA Pin
Value
0
0
1
0
1
X
O
O
I
LOW
HIGH
NA
reset default condition
Note that a read of the SDS[3] bit (TIR2[6]) will always
give the current SDSEL[3] pin value without inversion,
regardless of pin configuration setting.
Pin 103: SDSEL3
The SDSEL[3] pin may be configured for input or output
operation according to the following table:
SDSEL3EN
SDS[3]
SDSEL[3]
SDSEL[3]
TCR13[3]
TIR2[6]
Pin Direction
Pin Value
0
1
1
X
0
1
I
NA
O
O
HIGH
LOW
reset default condition
Note that a read of the SDS[2] bit (TIR2[5]) will always
give the current SDSEL[2] pin value without inversion,
regardless of pin configuration setting.
Pin 105: SDSEL2
The SDSEL[2] pin may be configured for input or output
operation according to the following table:
SDSEL2EN
SDS[2]
SDSEL[2]
SDSEL[2]
TCR13[2]
TIR2[5]
Pin Direction
Pin Value
0
1
1
X
0
1
I
NA
O
O
HIGH
LOW
reset default condition
Note that a read of the SDS[1] bit (TIR2[4]) will always
give the current SDSEL[1] pin value without inversion,
regardless of pin configuration setting.
Pin 107: SDSEL1
The SDSEL[1] pin may be configured for input or output
operation according to the following table:
SDSEL1EN
TCR13[1]
SDS[1]
TIR2[4]
SDSEL[1]
Pin Direction
SDSEL[1]
Pin Value
0
1
1
X
0
1
I
NA
O
O
HIGH
LOW
reset default condition
38
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synchronizing FIFO between the CRC generator and
the TXDATA pin that is used only in the TXC input mode.
This serial FIFO is 16 bits long and is used to allow for
slight mismatch between the internal TX state machine
reference clock and the external TXC input clock. It is
imperative in the TXC input mode that the Data Rate se-
lected with the Data Rate bits of TCR30 must match the
expected TXC clock rate from the transceiver. If these
rates do not match, then there is a risk of internal serial
FIFO error which, if it occurred, would be signaled
through the ATFU and ATFO interrupts of TCR11.
Pin 115: TXC
The TXC pin may be configured for input or output op-
eration according to the table below:
TXC input configuration is the reset default configura-
tion. This configuration allows an external transceiver to
control the clock that serves as the reference for the
transmit data. While in this configuration, the internal TX
state machine continues to operate with a reference
clock derived from a divided version of the CLKIN input.
Since the external TXC source is not driving the
Am79C930 device TX state machine, there exists a
TXCIN
TCR30[3]
TXC Pin
Direction
TXC Pin
Value
0
1
O
I
TXC
NA
(result of internal divide of CLKIN)
reset default condition
Pin 118: LFPE
The LFPE pin may be configured for input or output op-
eration according to the table below:
Note that the value of the LFPE bit (TIR0[1]) also affects
the value of the LFCLK pin.
Note that a read of the LFPE bit (TIR0[1]) will always
yield the inverted logical sense of the current LFPE pin
value, regardless of pin configuration setting.
LFPEEN
TCR13[6]
LFPE
TIR0[1]
CLKGT20
MIR9[7]
LFPE Pin
Direction
LFPE Pin
Value
LFCLK Pin
Value
0
1
1
1
X
0
1
1
X
X
0
1
I
NA
LOW
LOW
O
O
O
HIGH
LOW
LOW
reset default condition
CLKIN
CLKIN÷2
Pin 120: HFPE
The HFPE pin may be configured for input or output op-
eration according to the following table:
Note that the value of the HFPE bit (TIR0[0]) also affects
the value of the HFCLK pin.
Note that a read of the HFPE bit (TIR0[0]) will always
yield the inverted logical sense of the current HFPE pin
value, regardless of pin configuration setting.
HFPEEN
TCR13[5]
HFPE
TIR0[0]
CLKGT20
MIR9[7]
HFPE Pin
Direction
HFPE Pin
Value
HFCLK Pin
Value
0
1
1
1
X
0
1
1
X
X
0
1
I
NA
LOW
LOW
O
O
O
HIGH
LOW
LOW
reset default condition
CLKIN
CLKIN÷2
Note that a read of the RXP bit (TIR0[2]) will always yield
the inverted logical sense of the currentRXPE pin value,
regardless of pin configuration setting.
Pin 122: RXPE
The RXPE pin may be configured for input or output op-
eration according to the following table:
RXPELEN
TCR13[0]
RXP
TIR0[2]
RXPE Pin
Direction
RXPE Pin
Value
0
1
1
X
0
1
I
NA
O
O
HIGH
LOW
reset default condition
Am79C930
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Pin 126: TXCMD
The TXCMD pin may be configured to drive a trans-
ceiver control reference signal, using one of two timing
sources plus input from the TXCMD bit of TIR11
(TIR11[0]), according to the following table:
RCEN
TIR11[3]
TXCMD Pin
Direction
TXCMD Pin
Value
0
1
O
O
O_TX
TIR11[0] & T1
Transmit state machine generated signals T1, T2, T3,
TXP_ON and O_TX have the timing indicated in the
diagram in section Am79C930-Based TX Power
Ramp Control.
Pin 129: TXPE
The TXPE pin may be configured to drive a transceiver
controlreferencesignal, usingoneoftwotimingsources
plus input from the TXPE bit of TIR11 (TIR11[1]) and
the TXPEPOL bit of TCR27, according to the
following table:
Transmit state machine generated signals T1, T2, T3,
TXP_ON and O_TX have the timing indicated in the
diagram in section Am79C930-Based TX Power
Ramp Control.
RCEN
TIR11[3]
TXPEPOL
TCR27[1]
TXPE Pin
Direction
TXPE Pin
Value
0
0
1
1
0
1
0
1
O
O
O
O
TXP_ON
TXP_ON
TIR11[1] & T2
(& = logical ‘AND’)
(+ = logical ‘OR’)
TIR11[1] + T2
Pin 131: TXMOD
The TXMOD pin may be configured to drive a trans-
ceiver control reference signal, using input from the
TXMOD bit of TIR11 (TIR11[2]) and the TXMODPOL bit
of TCR27, according to the following table:
Transmit state machine generated signals T1, T2, T3,
TXP_ON and O_TX have the timing indicated in the
diagram in section Am79C930-Based TX Power
Ramp Control.
RCEN
TIR11[3]
TXMODPOL
TCR27[0]
TXMOD Pin
Direction
TXMOD Pin
Value
0
0
1
1
0
1
0
1
O
O
O
O
T3
T3
TIR11[2] & T3
(& = logical ‘AND’)
(+ = logical ‘OR’)
TIR11[2] + T3
Pin 132: ANTSLT
The ANTSLT pin may be configured to drive an inter-
nally generated antenna selection signal using the inter-
nal antenna diversity circuitry, or it may be controlled by
a register bit. Pin functionality is programmed according
to the following table:
If it is necessary to force ANTSLT to be always constant,
then program ANTS to 0 or userANTSLT pin, which can
be controlled by ANTSLTD (TCR7:[1]).
TX
ANTSEN
ANTEN
Mode
(TIR16[[3])
(TIR4:[7])
0
0
0
1
0
1
0
0
1
X
ANTSLT <= low
ANTSEL <= ANTS (TIR26:[4])
ANTSLT <= internal ANTSEL
ANTSLT <= low
X
X
Pin 141: ANTSLT/LA23
The ANTSLT/LA23 pin may be configured to operate as
input or output and may be configured to drive an
internally generated antenna selection reference signal
using the internal antenna diversity circuitry. Note that
40
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some functionality is only available in PCMCIA mode.
Pin functionality is programmed according to the follow-
ing table:
Note that a read of the ANTSLTD bit (TCR7[1]) will al-
ways give the current ANTSLT/LA23 pin value without
inversion, regardless of pin configuration setting.
ANTSLT/
LA23 Pin
Direction
ANTSLT/
LA23 Pin
Value
PCMCIA
Pin Value
ANTSEN
TIR26[3]
ANSLTLFN ANTSLTLEN
TCR30[7]
TCR15[7]
0
1
X
0
X
0
X
X
I
NA
(LA23 input function)
O
ANTSLT
(from internal antenna)
(diversity circuit)
1
1
1
X
X
1
1
1
0
0
1
X
I
NA
O
O
TCR7[1]
TIR26[4] (write)
TIR26[5] (read)
Pin 142: TXCMD/LA21
The TXCMD/LA21 pin may be configured to operate as
input or output and may be configured to drive a trans-
ceiver control reference signal using one of two timing
sources plus input from the TXCMD bit of TIR11
(TIR11[0]). Note that some functionality is only available
in PCMCIA mode.
Transmit state machine generated signals T1, T2, T3,
TXP_ON and O_TX have the timing indicated in the
diagram in section Am79C930-Based TX Power
Ramp Control.
Note that a read of the TXCMDT bit (TCR7[2]) will al-
ways give the current TXCMD/LA21 pin value without
inversion, regardless of pin configuration setting.
Pin functionality is programmed according to the
following table.
TXCMD/
LA21 Pin
Direction
TXCMD/
LA21 Pin
Value
PCMCIA
Pin Value
RCEN
TIR11[3]
TXCMFN
TCR30[5]
TXCMEN
TCR15[5]
0
1
1
1
1
X
0
1
1
1
X
X
0
1
1
X
X
X
0
I
NA
O_TX
(LA21 input function)
O
O
I
TIR11[0] + T1
NA
1
O
TCR7[2]
The TXDATA signal is the inverse of the TXDATA signal
which is the TX data drawn from the TX FIFO using the
internal TX state machine control.
Pin 143: TXDATA/LA20
The TXDATA/LA20 pin may be configured to operate as
input or output and may be configured to drive inverted
transmit data. Note that some functionality is only
available in PCMCIA mode. Pin functionality is pro-
grammed according to the following table:
Note that a read of the TXDATALD bit (TCR7[0]) will al-
ways give the current TXDATA/LA20 pin value without
inversion, regardless of pin configuration setting.
TXDATA/
LA20 Pin
Direction
TXDATA/
LA20 Pin
Value
PCMCIA
Pin Value
TXDLFN
TCR30[6]
TXDLEN
TCR15[6]
0
1
X
0
X
X
I
NA
(LA20 input function)
O
TXDATA
(from internal TX FIFO
using internal TX state machine timing)
1
1
1
1
0
1
I
NA
O
TCR7[0]
Pin 144: LLOCKE/SA15
The LLOCKE/SA15 pin may be configured to operate as
inputoroutput. Notethatsomefunctionalityisonlyavail-
able in PCMCIA mode. Pin functionality is programmed
according to the following table:
Note that a read of the LLOCKE bit (TIR11[4]) will al-
ways give the current LLOCKE/SA15 pin value without
inversion, regardless of pin configuration setting.
Am79C930
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LLOCKE/
SA15 Pin
Direction
LLOCKE/
SA15 Pin
Value
PCMCIA
Pin Value
LLOCKEN
TCR14[6]
0
1
1
X
0
1
I
I
NA
NA
(SA15 input function)
O
TIR11[4]
andTCR). Theseregistersarecontrolledthrough80188
firmware instructions.
FUNCTIONAL DESCRIPTION
Basic Functions
Detailed Functions
Block Level Description
Bus Interface Unit
System Bus Interface Function
The Am79C930 device is designed with a choice of two
system bus interfaces. The system designer may
choose between the PCMCIA bus and the ISA (IEEE
P996) bus with support for Plug and Play. Both inter-
faces support an 8-bit wide data bus. The system inter-
face is used by the host driver software to initialize the
Am79C930 device through a series of slave I/O ac-
cesses to the Am79C930 device. Device operation is
monitored by accessing Am79C930 registers through
the system bus interface. Network data is transferred
to/fromthedriverthroughslavememoryaccessesatthe
system bus interface. Network data is stored in the
SRAM that accompanies a complete Am79C930-
based design.
The Bus Interface Unit (BIU) supports either of two com-
mon interfaces: PCMCIA and ISA (IEEE P996) with
Plug and Play. The choice of interface is determined
through a pin strapping option via the PCMCIA pin.
Two sets of command and status registers exist within
the BIU. One set of registers is labeled System Interface
Registers (SIR). The SIR registers are used to control
the general function of the device by providing various
resets and by allowing some direct communication be-
tween the host system and the embedded 80188. The
SIR registers are visible to the system interface, but are
not visible to the 80188 embedded core. The second set
of BIU registers is the MAC Interface Registers (MIR).
The MIR registers are visible to the 80188 embedded
core, but are not visible from the system interface.
Some commands within each register set allow indirect
communication between the system interface and the
80188 core.
Memory Bus Interface Function
The Am79C930 device contains a memory bus inter-
face, which is used by the Am79C930 device to gain ac-
cess to Flash memory for fetching 80188 instructions
and to gain access to SRAM for fetching and storing
driver commands, network data, and for temporary vari-
able storage. Software driver transfers of network data
arepassedtotheAm79C930devicethroughthesystem
bus interface and will be automatically rerouted to the
memory bus interface in order to reach the SRAM.
Another set of registers is located in the Transceiver At-
tachment Interface Unit, the TIR registers. The TIR loca-
tions are visible through the BIU. These registers are
normally used by the 80188 core to control the Trans-
ceiver function; they are visible through the system
interface primarily for diagnostic purposes.
Software Interface Function
The software interface to the Am79C930 consists of a
set of 256K memory locations and 16 (or 40) I/O loca-
tions. 128K of these memory locations map directly to
an SRAM that is attached to the memory interface. An-
other 128K maps to a Flash memory device. Due to
overlapping address space as viewed by the 80188
embedded processor core, 128 bytes of the SRAM
space are not usable for driver function. Additional
registers exist in the Am79C930 device for use by
industry standard PCMCIA and ISA Plug and Play
configuration utilities.
The PCMCIA Card Configuration Registers and the set
of ISA Plug and Play registers are implemented in the
BIU. PCMCIA Card Information Structure and the ISA
Plug and Play Resource Data area are both mapped to
Flash space and are accessible through the system
interface of the BIU.
All Am79C930 registers are located in I/O space as
viewed from the system interface. There are no memory
resources located inside of the BIU unit, although there
are memory resources that are accessed through
the BIU. For a complete description of all resources
accessible inside of and through the BIU, see the Soft-
ware Access section.
Network Interface Function
The Am79C930 device can be connected to an IEEE
802.11 (draft) network via a flexible network interface.
The flexible network interface allows the user to define
much of the pin functionality in order to assist in accom-
modating the Am79C930 device to a number of different
network transceivers. Pin control is achieved through
Transceiver Attachment Interface (TAI) registers (TIR
For a complete description of all resources accessible
by the embedded 80188 processor, see the 80188
Firmware section.
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PCMCIA Interface — The Am79C930 device fully sup-
ports the PCMCIA standard, revision 2.1.
CE1) are automatically translated into the appropriate
memory interface signals (RD, WR).
The PCMCIA interface on the Am79C930 device sup-
ports both memory and I/O cycles. The data bus is 8 bits
in width. The address bus is 15 bits in width. Memory ac-
cesses are enabled by default at power up. I/O ac-
cesses are enabled only when the ConfIndex bits of the
The PCMCIA Card Configuration registers that are sup-
ported are the Configuration Option Register and the
Card Configuration and Status Register. These two reg-
isters are physically located in the Bus Interface Unit
and logically exist only in PCMCIA Attribute memory
space (i.e., they are not also mapped to Common
memory space.) They are located at Attribute memory
locations 0800h and 0802h, respectively. The location
of these registers is fixed. Therefore, the information
programmed into the CIS must give the value 2K
(=0800h) as the Card Configuration Registers Base
Address in the TPCC_RADR field of the
Configuration Tuple.
PCMCIA Configuration Option Register have
a
non-zero value. It is not possible to disable the memory
access response function. The Am79C930 device re-
quires 32K of Common memory space and 16 or 40
bytes of I/O space. Since all Am79C930-based memory
resources are also mapped into an I/O port, it is
possible to operate with a Common memory space allo-
cation of 0 bytes.
The Am79C930 device supports the Card Information
Structure and the Card Configuration Registers defined
in the PCMCIA 2.1 standard, by decoding 2K+4 bytes of
Attribute memory space. The first tuple of the Card Infor-
mation Structure must be located at PCMCIA Attribute
Memory location 0h. Note that in the Am79C930 device,
Attribute Memory locations 000h–07FFh are mapped to
the upper 1 Kbytes of the 128K Flash memory space
(i.e., Flash memory locations 1FC00h–1FFFFh). The
upper 1K–16 byte locations of the Flash memory device
must be reserved for PCMCIA Card Information Struc-
ture use. (The uppermost 16 bytes of the Flash memory
may not be used for PCMCIA CIS space, since the
80188 core will fetch its first instructions from these lo-
cations following a reset operation. These locations cor-
The PCMCIA Card Configuration registers are the only
writable PCMCIA Attribute memory locations within the
Am79C930, because these two registers do not corre-
spond to Flash memory locations, and these two loca-
tions are not CIS structures.
The Am79C930 device occupies either 16 bytes of I/O
space or 40 bytes of I/O space, depending upon the set-
ting of the EIOW bit (bit 2 of the BSS register (SIR1)).
The I/O space of the Am79C930 contains the General
Configuration Register, the Bank Switching Select
Register, and the set of 32 TIR registers. Additionally, all
Am79C930 resources are accessible through I/O ac-
cesses (i.e., all memory structures are accessible
through the Local Memory Address and I/O Data Ports).
respond
locations 7F0h–7FFh.)
to
PCMCIA
Attribute
memory
The Local Memory Address port (SIR2,3) plus SIR1[5:3]
function together as a pointer to the memory resources
of the Am79C930 device. SIR1[5] determines the de-
vice selected (SRAM or Flash) and SIR1[4:3] and
LMA[14:0] supply the address to the selected device
whenever the I/O Data Port is read or written. Whenever
any of the four I/O Data Ports is accessed, then the Lo-
cal Memory Address Port value is automatically incre-
mented by a value of 1.
Note that the Kbytes of Attribute memory
2
0000h–07FFh are mapped to only 1 Kbytes of Flash
memory. Since the PCMCIA specification indicates that
only even addressed bytes of Attribute memory are de-
fined to exist, only the even addressed 1K of the 2K At-
tribute memory space is actually physically present.
Odd addressed Attribute memory locations in the
Am79C930 device are undefined.
Because of the existence of the Local Memory Address
and I/O Data Ports, the Am79C930 device may be
used in an I/O only fashion. Appropriate configuration
information may be placed into the CIS space so that the
PCMCIA configuration utility will assign no memory
space to the Am79C930-based design. Note, however,
that the Am79C930 device will always respond to Com-
mon memory accesses that are directed to the
0000h–7FFFh range, if they occur in the PCMCIA slot in
which the Am79C930-based design resides. The
Common memory slave response function is always ac-
tive on the Am79C930 device; it is not possible to dis-
able this function. The Am79C930 device does not
attempt to interpret the ConfIndex value of the PCMCIA
Configuration Option Register except for purposes of
enabling the I/O slave response function.
While the Common memory space of the Am79C930
device only accommodates access to 32 Kbytes of
Common memory, the Am79C930 device uses device
select and bank select bits (bits 5:3 of the BSS
register (SIR1)) in order to access a total of 256K of
memory space.
When accessing Common memory resources through
PCMCIA common memory accesses, lower memory
addresses at the PCMCIA interface are passed directly
to the memory interface bus, and the Flash Memory
Chip Enable (FCE) or the SRAM Chip Enable (SCE) sig-
nal is asserted, depending upon the value of SIR1[5].
The upper two bits of the memory interface address bus
are set according to the value of SIR1[4:3]. The
PCMCIA memory access control signals (WE, OE,
Am79C930
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ISA (IEEE P996) Plug and Play Interface — The
Am79C930 device fully supports the ISA Plug and Play
specification, revision 1.0a.
When accessing Am79C930 memory resources
through ISA memory cycle accesses, the upper 9 bits of
the ISA memory address will be used to check for a
match of the address range assigned to the Am79C930
device by the Plug and Play configuration program (i.e.,
the Memory Base Address = MBA). (The Plug and Play
configuration program will have written a memory base
address value into the Memory Base Address regis-
ters—Plug and Play ports 40h and 41h—following sys-
tem boot up and auto-configuration.) The ISA Plug and
Play memory base address must be aligned to a 32K
boundaryinmemoryspace. Thisalignmentrequirement
should be included in the Resource Data that is pro-
grammed into the Flash device and read by the Plug and
Play configuration utility. These conditions must be sat-
isfied, since the Am79C930 device’s Bus Interface Unit
will use the upper 9 bits of the ISA memory address to
determine when an address match has been achieved.
The ISA Plug and Play interface on the Am79C930 de-
vice supports both memory and I/O cycles. The data bus
is 8 bits in width. The total system space required by the
Am79C930 device is 32 Kbytes and 16 bytes of I/O
space. Since all Am79C930-based memory resources
are also mapped into an I/O port, it is possible to operate
a Am79C930-based design with a system memory allo-
cation of 0 bytes.
When the 32K system memory option is selected, the
Am79C930 device uses device select and bank select
bits in the BSS register (SIR1) in order to allow system
access to a total of 256K of Am79C930 memory re-
sources. The total system I/O space required by the
Am79C930 device is 16 bytes. The 40-byte I/O option is
not available in the ISA Plug and Play mode of opera-
tion. The EIOW bit (bit 2 of the BSS register (SIR1)) will
be forced to 0 when the Am79C930 device has been
placed into ISA Plug and Play mode. The I/O space of
the Am79C930 device contains the General Configura-
tion Register, the Bank Switching Select Register, and
the set of 32 TIR registers. Additionally, all Am79C930
resources are accessible through I/O accesses (i.e., all
memory structures are accessible through the Local
Memory Address and Data Ports (SIR2,3,4,5,6,7)).
When accessing Am79C930 memory resources
through ISA system memory accesses and when the
upper bits of the ISA address are determined to match
the Am79C930 memory space, then the lower memory
addresses at the ISA interface are passed directly to the
memory interface bus, and the Flash Memory Chip En-
able (FCE) or the SRAM Chip Enable (SCE) signal is as-
serted, depending upon the value of SIR1[5]. The upper
two bits of the memory interface bus are set according to
the value of SIR1[4:3]. ISA memory access control sig-
nals (MEMR, MEMW) are automatically translated into
the appropriate memory interface signals (RD, WR).
The Local Memory Address port plus SIR1[5:3] function
together as a pointer to the memory resources of the
Am79C930 device. SIR1[5] determines the device se-
lected (SRAM or Flash) and SIR1[4:3] and LMA[14:0]
supply the address to the selected device whenever the
I/O Data Port is read or written. Whenever any of the
four I/O Data Ports is accessed, then the Local Memory
Address Port value is automatically incremented by a
value of “1.”
When accessing Am79C930 I/O resources through ISA
I/O cycle accesses, the upper 8 bits of the ISA system
address will be ignored. Only the lower 16 bits of ad-
dress will be used to check for a match of the address
range assigned to the Am79C930 device by the Plug
and Play configuration program (i.e., the I/O Base Ad-
dress = IOBA). (The Plug and Play configuration pro-
gram will have written an I/O base address value into the
I/O Base Address registers—Plug and Play ports 60h
and 61h—following system boot up and auto-configura-
tion.) The ISA Plug and Play I/O base address must be
aligned to a 16-byte boundary in I/O space. This align-
ment requirement should be included in the Resource
Data I/O Port Descriptor Base Alignment field that is
programmed into the Flash device and read by the Plug
and Play configuration utility. These conditions must be
satisfied for proper operation.
The Am79C930 device maps 1K–16 bytes of the upper
1K of the 128K of Flash memory space into the ISA Plug
and Play Resource Data structure. (The upper 16 bytes
of this space may not be used for ISA Plug and Play Re-
source Data, since this space is needed to store the first
instructionsthatwillbefetchedbythe80188corefollow-
ing the reset operation.) Byte 0 of the Am79C930 de-
vice’s Resource Data is mapped to location 1FC00h of
the Flash memory. Reads of the ISA Plug and Play Data
Resource register will automatically access Flash mem-
ory locations in the range 1FC00h through 1FFF0h.
Since all Flash memory locations are always accessible
through ordinary ISA memory accesses, ISA memory
accesses to locations MBA+7C00h – MBA+7FF0h will
sometimes correspond to the same physical locations
as ISA Plug and Play accesses to Resource Data bytes
000h – 3F0h (i.e., the correspondence will occur when
the device and bank select bits of SIR1 are pointing at
the upper quadrant of the 128K Flash memory
address space).
The Am79C930 device fully supports the Plug and Play
Auto-configuration scheme. The Plug and Play
ADDRESS port, WRITE_DATA port and READ_DATA
port are all supported, as well as 19 of the ISA Plug and
Play Registers. For more detail, see the ISA Plug and
Play section.
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Memory Interface
registers. This mode allows for 32K of SRAM/XCE/TAI/
BIU and 32K of Flash to reside in a single 64 Kbyte seg-
ment of 80188 memory space. This mode is selected
through a bit in the MIR0 register.
The memory interface is provided to support direct con-
nection of both a non-volatile memory (typically Flash
memory) and an SRAM and an additional peripheral de-
vice. Separate chip enables for Flash, SRAM, and an
extra peripheral device exist in the memory interface.
The 32K range of address space visible at the system
interface (either PCMCIA or ISA Plug and Play) maps to
a total of 256K of memory through the use of a device
select bit and bank switching bits in the Bank Switching
Select register (SIR1). 128K of space is reserved
for Flash memory and 128K of space is reserved for
SRAM. The 32 bytes of space reserved for the extra pe-
ripheral device are only accessible by the embedded
80188 core.
The TAI connects to only a portion of the memory inter-
face bus. Specifically, the lowest five address bits and
the entire data bus of the memory interface connect to
the TAI. A separate internal chip select signal for the TAI
exists to avoid confusion among slave devices. This sig-
nal is not available on the Am79C930 memory interface
bus, and therefore, memory interface cycles may be ob-
served for which neither the Flash chip enable, nor the
SRAM chip enable, nor the XCE signal is asserted.
Similar behavior is observed when the 80188 core is ac-
cessing registers which are located within the BIU.
The internal Transceiver Attachment Unit also resides
on the memory interface bus and uses 8 bytes (or 32)
bytes of I/O space as viewed by the system interface.
These same registers occupy 32 bytes of the SRAM’s
memory space (i.e., instead of I/O space) as viewed by
the embedded 80188 core. The MIR registers of the BIU
occupy an additional 16 bytes of SRAM space as
viewed by the embedded 80188 core. The MIR registers
are not visible to the system interface.
Embedded 80188
The embedded 80188 core provides the basic means
for implementing IEEE 802.11 (draft) MAC functionality.
The elements of the Am79C930 device that are involved
in MAC function include the 80188 core, the Flash mem-
ory, the SRAM memory, the timers within the 80188, the
sleep timer in the BIU, the Transceiver Attachment Unit,
and the associated busses and signaling that connect
the 80188 core to the BIU and the Transceiver
Attachment Unit.
The memory interface bus is shared between the sys-
tem interface and the embedded 80188 processor.
Memory interface bus sharing between the system in-
terface and the 80188 processor core is based upon an
equal priority delivered in a round robin fashion. When-
ever the system interface is accessing a device on the
memory interface bus, then the 80188 core is placed
intoreadywait. Wheneverthe80188coreisaccessinga
device on the memory interface bus, then the system in-
terface bus activity will be given a ready wait. When the
current memory interface bus master has completed its
cycle, then the other memory interface bus master will
be given control of the memory interface bus.
The Am79C930 device directly incorporates some of
the basic protocol requirements for operation of a IEEE
802.11 (draft) node. Other portions of the IEEE 802.11
(draft) MAC protocol need to be created with appropri-
ate firmware written to execute on the 80188 core.
With proper 80188 coding, the Am79C930 device
can be made to operate according to the
IEEE 802.11 (draft).
Media Access Management — The IEEE 802.11
(draft) protocol defines a media access mechanism
which permits all stations to access the channel with
equality. Synchronous time-bounded service and asyn-
chronoustime-boundedaccessservicearealsodefined
in the IEEE 802.11 (draft) specification. Any node can
attempt to contend for the channel by waiting for a pre-
determined time (Inter Frame Spacing) after the last ac-
tivity, and then waiting an additional random backoff
time before determining whether to attempt to transmit
on the media. If two or more nodes simultaneously con-
tend for the channel, their signals will interact causing
loss of data, defined as a collision. It is the responsibility
of the MAC to attempt to avoid and recover from a colli-
sion in order to insure data integrity for the end-to-end
transmission to the receiving station.
The 80188 memory accesses are directed toward
Flash, SRAM, the XCE peripheral device, TAI registers
(TIR/TCR), or BIU registers (MIR) according to theUCS
and LCS signals of the 80188 core. Normally, whenever
UCS is active during an 80188 memory access, the ac-
cess is directed toward the Flash memory; and when-
ever LCS is active during an 80188 memory access, the
access is directed toward the SRAM memory or the
XCE peripheral device or the TAI registers or BIU regis-
ters. Along with the UCS and LCS signals, 17 of the
80188 address lines are internally connected through
the BIU to the memory interface bus, allowing 256K of
memory to be addressed by the 80188. (128K of Flash
and 128K of SRAM/XCE/TAI/BIU may be addressed by
the 80188, for a total of 256K of memory.)
Medium Allocation
The IEEE 802.11 (draft) standard requires that each
Carrier Sense Multiple Access/Collision Avoidance
(CSMA/CA) MAC monitor the medium for traffic by
watching for carrier activity. When carrier is detected,
An alternate addressing mode will alias the upper
96 Kbytes of Flash memory into the upper 96 Kbytes of
SRAM space, while preserving the location of the lower
32K of SRAM, the XCE peripheral, and the TAI/BIU
Am79C930
45
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the media is considered busy and the MAC should defer
to the existing message. This function is implemented in
hardware in the TAI Unit.
2. The 80188 firmware must perform a write to the
80188 internal UMCS register and set the wait states
to 0 and set the READY control to “also use external
RDY” (i.e., set R2,R1,R0 to 000b). No other value
should be written to these bits. Note that the value
that will eventually be written to the BIU MIR9
register will cause the Am79C930 internal SRDY
signal to be asserted for the proper number of cycles
and will cause the 80188 to experience the
proper delay for the Flash memory device in the
Am79C930-based system.
Additionally, each station is required to implement a Net
Allocation Vector (NAV) in order to determine when the
medium is expected to be busy. The NAV is updated as
Request-to-Send (RTS), Send (CTS), and DATA
frames arrive at the station. RTS, CTS, and DATA
frames include a field that indicates the expected length
of the RTS-CTS-DATA-ACK exchange. The MAC uses
the value in this field to update the NAV and then defers
from initiating transmissions until the NAV has counted
down to zero. If any portion of the RTS-CTS-DATA-ACK
exchange is missing, then a MAC timer will timeout and
the NAV is reset to zero at that time. By refraining from
transmission while the NAV is non-zero, the MAC is
practicing collision avoidance.
3. The 80188 firmware must perform a write to the
Am79C930 internal MIR8 register and set the Flash-
WAIT bits to a value that is appropriate for the Flash
memory timing, given the Am79C930 CLKIN pin fre-
quency and the particular speed-grade of the Flash
memory used in the design.
NAV values may be maintained through use of one of
the 80188 timers. If there is no backoff in progress when
the NAV counter value times out, the firmware will initi-
ate transmission of a frame.
4. The 80188 firmware must perform a write to the
Am79C930 internal MIR9 register and set the
SRAMWAIT bits to a value that is appropriate for the
SRAM memory timing, given the Am79C930 CLKIN
pin frequency and the particular speed-grade of the
SRAM memory used in the design.
Initialization — Am79C930 device initialization is per-
formed by asserting the Am79C930 RESET input for
more than 14 clocks. Following the release of the
RESET signal, the Am79C930 device’s embedded
80188 core will exit the reset state. The embedded
80188 will then proceed with instruction fetching and
execution from memory location FFFF0h. The first fetch
will occur within 13 CLKIN clocks (= 6 and 1/2 80188
CPU clock cycles) of the release of the 80188 reset. The
80188 address FFFF0h will map to a Flash memory lo-
cation, sincetheUMCSregisterofthe80188corewillbe
set to FFF8h following reset. This UMCS value will en-
sure that the initial 80188 address fetch will cause an as-
sertion of the UCS signal, which will cause the memory
interface bus logic to select the Flash memory device.
80188 firmware must modify the value of the UMCS reg-
ister after the first few execution cycles in order to make
more than 1K of the Flash memory available to the
80188 core.
SRAM Memory Management — The 80188 core
accesses the SRAM memory by asserting its Lower
Chip Select (80188 LCS). (Actually, SRAM space is se-
lected whenever the 80188 memory access does not
activate the UCS signal. The internal Upper Chip Select
(UCS) signal is routed into the Bus Interface Unit, since
the 80188 core and the Bus Interface Unit must share
the memory interface bus. When UCS is not activated
for an 80188 transfer, the BIU unit assumes that SRAM
accesses are desired. Therefore, during 80188 ac-
cesses for which UCS is not asserted, SCE will be as-
serted, except for a section of lower memory space that
is redirected toward the TAI section of the Am79C930
device.) The SCE signal may be attached to the CE in-
put of an SRAM memory device external to the
Am79C930 device. Up to 128K of SRAM may be ad-
dressed by the 80188 core (with the exception that 64
bytes of SRAM space is mapped into internal
Am79C930 registers of the BIU and TAI.)
The 80188 firmware should make no access to MIR reg-
isters or to TAI registers (TIR and TCR) until the follow-
ing steps have been completed. Note that these steps
MUST be performed in the order given:
An alternative mapping scheme allows some portion of
the Flash memory to be mapped into a portion of LCS
space. (Normally, Flash memory is mappedonly toUCS
space.) Therefore, depending upon the mapping
scheme that is chosen, LCS may either access SRAM
plus BIU plus TAI space, orLCS may access a portion of
SRAM plus BIU plus TAI space plus a portion of Flash
memory space. For mapping details, see the section on
MAC Firmware Resources.
1. The 80188 firmware must perform a write to the
80188 internal LMCS register and set the wait states
to 0 and set the READY control to “also use external
RDY” (i.e., set R2,R1,R0 to 000b). No other value
should be written to these bits. Note that the value
that will eventually be written to the BIU MIR8
register will cause the Am79C930 internal SRDY
signal to be asserted for the proper number of cycles
and will cause the 80188 to experience the proper
delay for the SRAM memory device in the
Am79C930-based system.
Address values are delivered from the 80188 core to the
SRAM through the BIU and then to the Memory Address
Bus (signals MA[16:0]). AD [7:0] 80188 address signals
are latched inside of the BIU to allow system interface
46
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accesses to use the memory interface bus during the T1
and T2 cycles of the 80188 access. The Memory Ad-
dress Bus is internally shared between the 80188 core
and the BIU. This bus also attaches to the Transceiver
Attachment Unit as an input only.
thePCMCIAmodeofoperationhasbeenselected. Note
that the uppermost 16 bytes of Flash space are used by
the 80188 core to fetch initial instructions following a
reset operation of the Am79C930 device. Therefore,
these 16 bytes cannot be used for PCMCIA CIS. Note
that both the 80188 core and the system interface
(through Common Memory mapping) have access to
the PCMCIA CIS storage area, even though these loca-
tions should be reserved for PCMCIA CIS use.
Data values are delivered from the 80188 core to the
SRAM through the BIU and then to the Memory Data
Bus (signals MD[7:0]). This bus is shared by the BIU for
access to the SRAM and also attaches to the Trans-
ceiver Attachment Unit.
Transceiver Attachment Interface Unit
Management
Flash Memory Management
The 80188 core communicates with the TAI Unit
throughmemoryaccessesthatthe80188coreperforms
on the Memory Interface bus through the BIU. TIR regis-
ters are mapped to 32 byte locations of the SRAM
space, thereby rendering those 32 bytes of SRAM as
inaccessible to the 80188 core. Command and status
information for the TAI is passed through the TIR regis-
ters. Network data is passed to/from the TAI FIFOs with
DMA cycles. The TAI uses DMA channels 0 and 1 of the
80188 core. DMA channel 0 is used by the RX FIFO and
DMA channel 1 is used by the TX FIFO. The 80188 core
must activate its LCS signal to access the TIR registers,
just as in the case of SRAM accesses. As a result, the
TAI register set overlaps a very small portion of the
SRAM space. The TAI may send interrupts to the 80188
core through the INT0 interrupt.
The 80188 core accesses the Flash memory by assert-
ing its Upper Chip Select (80188 UCS) This signal
remains internal to the Am79C930 device. The internal
UCS signal is routed into the BIU, since the 80188 core
and the BIU must share the memory interface bus. The
BIU in turn produces the Memory Interface signal FCE
that may be attached to the CE input of a Flash memory
device external to the Am79C930 device.
An alternative mapping scheme allows some portion of
the Flash memory to be mapped into a portion of LCS
space. (Normally, Flash memory is mapped only toUCS
space.) Therefore, depending upon the mapping
scheme that is chosen, Flash memory may be visible
only in UCS space, or portions of Flash memory may be
visible in both LCS and UCS spaces. For mapping
details, see the section on MAC Firmware Resources.
Bus Interface Unit Interaction
The 80188 core communicates with the driver software
through a shared area of SRAM. When either the driver
software or the 80188 core modifies this area of SRAM,
an interrupt is generated to notify the receiving subunit.
Most command and status information for the adapter
may be passed to the driver through the shared SRAM.
However, a few physical registers do exist in the BIU to
facilitate the exchange of some very high level com-
mands, such as RESET, HALT, POWERDOWN and
INTERRUPT. Each subunit (device driver and 80188
core) is allotted its own set of BIU registers. The device
driver has access to eight System Interface Registers
(SIR) that reside in the BIU. The 80188 core has access
to 16 MAC Interface Registers (MIR) that reside in the
BIU. Communication of high-level command and status
information between the two subunits is indirectly
accomplished, in that modification of bits in the SIR
space will affect bits in the MIR space and vice versa,
but the device driver has no direct access to the MIR
space and the 80188 core has no direct access to the
SIR space.
Address values are delivered from the 80188 core to the
Flash memory through the BIU and then to the Memory
Address Bus (signals MA[16:0]). The Memory Address
Bus is shared between the 80188 core and the BIU. The
sharing uses a priority scheme where the requester al-
ways has higher priority than the current bus master.
This ensures that in the worst case the system interface
access will be delayed only by the length of a single
80188 access, and an 80188 access will be delayed at
most by the length of a single system interface access.
The requesting access is always held off by asserting
the local ready signal. The memory interface bus also
attaches to the TAI Unit. The TAI is a bus slave device; it
cannot act as a bus master.
Data values are delivered from the 80188 core to the
Flash memory through the BIU and then to the Memory
Data Bus (signals MD[7:0]). Up to 128K of Flash mem-
ory may be addressed by the 80188 core. Note that for
PCMCIA operation, the 1K–16 bytes of the upper 1K
locations may be used for the PCMCIA CIS, since these
locations are mapped to Attribute Memory space when
Am79C930
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selection of antennas. If automatic antenna selection is
Transceiver Attachment Interface Unit
not used, then the desired antenna selection is accom-
plished through the setting of appropriate bits in one of
the TIR registers.
The TAI Unit includes the following subfunctions:
TAI register set
TX FIFO
TX FIFO
TX data serialization
TX CRC32 generation
TX CRC8 generation
TX status reporting
RX preamble and Start of Frame detection
RX data deserialization
RX FIFO
RX CRC32 checking
RX CRC8 checking
RX status reporting
Bit ordering
The TAI contains individual FIFOs for RX and TX opera-
tions. The TX FIFO holds a maximum of 8 bytes. The TX
FIFO indicates a “not full” state by signaling a request for
data on the DRQ1 input of the 80188 embedded core.
The DRQ1 output of the TAI subunit is active if the TX
FIFO condition is met, regardless of the state of the TXS
bit of TIR8. TX FIFO DMA activity is prevented by dis-
abling the DMA1 controller in the 80188.
The TX FIFO holds a maximum of 8 bytes of data. Actual
TX FIFO byte count can be read from TIR9. Preamble
and Start of Frame Delimiter and any necessary PHY
subunit header information must be assembled by the
80188 core firmware and then loaded into the TX FIFO
for inclusion in the TX frame. The TAI subunit has
no built in capabilities for preamble, SFD, or PHY
header generation.
RSSI A/D circuit
Physical Header Accommodation
Encryption/decryption support
Data Scrambling
DC Bias Control
Baud Determination logic
CCA circuit
Antenna diversity logic
TX Power Ramp Control
The Am79C930 device includes state-controlled output
signals that may be used to perform transceiver power
sequencing. For transceivers that create their own
transmit power sequencing, a single input signal (CTS)
is provided to allow for smooth synchronization between
the Am79C930 device and the transceiver.
The TAI provides the necessary functionality to directly
connect to a variety of possible transceiver interface
styles. In the PCMCIA mode of operation, 24 pins are di-
rectly controllable through register access by the device
driver and the 80188 core firmware. These 24 pins may
be combined with the fixed function pins of the network
interface to create a customer-specific network inter-
face. In the ISA Plug and Play mode of operation, the
number of programmable pins is reduced to 10, while
the fixed function pins remain unchanged.
Am79C930-based TX Power Ramp Control — The
following is the description of the Am79C930 device’s
state-controlled output signals. The subsequent
section is a description of the CTS input signal and its
intended use.
The TAI is logically located on the Am79C930 memory
interface bus as a slave-only device. The TAI contains
64 registers that are used to configure operational pa-
rameters, to communicate commands, to pass data,
and to pass status. Thirty-two of the registers are di-
rectly accessible to the 80188 core and to the system
interface. These 32 registers are labeled TAI Interface
Registers (TIR). An additional 32 TAI registers are indi-
rectly accessible through an address and data port in
the TIR register set. These 32 registers are labeled TAI
Configuration Registers (TCR).
Once the TX start command has been issued to the TAI
by the 80188 core firmware (TXS bit of TIR8), a
sequence of transceiver enable signals will be gener-
ated in order to ramp up the power to the various sec-
tions of the transceiver (i.e., TXCMD, TXPE, TXMOD).
Once the final enable signal has been sent to the trans-
ceiver, the TAI will begin to remove data from the TX
FIFO. As each byte of data is removed from the TX
FIFO, the TAI subunit will serialize the byte and send the
individual bits of the data out the TXDATA pin at the
specified data transmission rate.
Data transfers from the RX FIFO are requested through
the internal 80188 core input DRQ0. Data transfers to
the TX FIFO are requested through the internal 80188
core input DRQ1. Interrupts from the TAI are requested
through the internal 80188 core input INT0.
Timing for the transmit ramp up and ramp down se-
quence is generated from 5 internal signals whose tim-
ing relationships may be directly controlled by register
programming (TCR5, TCR6). The following diagram il-
lustrates the relationships among the five internal sig-
nals and the registers that control them.
The TAI supplies an antenna select pin to allow for se-
lection between two possible antennas. The Am79C930
device has provision for both automatic and manual
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4 X TSCLK
TXS
TGAP1 X TBCLK
+ 2 X TSCLK
TGAP4 X TBCLK
+ 2 X TSCLK
T1
T2
TGAP2 X TBCLK
+ 2 X TSCLK
TGAP3 X TBCLK
+ 2 X TSCLK
2 X TSCLK
2 X TSCLK
T3
3 X TSCLK
7 X TSCLK
O_TX
TXP_ON
TXDATA
HDB X TBCLK
DRB X TBCLK
1st
Data Bit
Last
Data Bit
TX default bit
TX default bit
TSCLK = TCLKIN when
CLKGT20 = 0
TBCLK = TSCLK X 20
20183B-7
Figure 1. Transmitter Power Ramp Control
The values HDR, DRB, TGAP1, TGAP2, TGAP3, and
TGAP4 are programmable values that are stored in
TCR register locations TCR0, TCR5, and TCR6. All
other timings in the diagram are fixed with the values in-
dicated. The CLKGT20 control bit is located in MIR9[7].
Note that the TXCMD, TXPE, and TXMOD bits of TIR11
may also affect the values of the TXCMD, TXPE, and
TXMOD pins. See the individual descriptions of these
pins in the Multi-Function Pin section of this document
for more detail.
The timing of the five internal signals can be applied to
the external pins TXCMD, TXPE, and TXMOD in
either of two ways, depending upon the value pro-
grammed into the RCEN bit of TIR11 as shown in the
following table:
The polarity of TXMOD and TXPE are programmable. A
separate TXCMD signal (inverse polarity to TXCMD)
is available.
Pin
Timing Reference Timing Reference
Name
When RCEN=0
When RCEN=1
TXCMD
TXPE
O_TX
T1
T2
T3
TXP_ON
T3
TXMOD
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Transceiver-Based TX Power Ramp Control — The
CTS signal may be used to synchronize operations be-
tween the Am79C930 device and transceivers that wish
to perform their own transmit timing sequence. When
the CTS signal is enabled by setting the CTSEN bit of
TCR7 to a 1, then the CTS input acts as a gating signal
with respect to the start of the Am79C930 transmit op-
erations. An example of the use of the CTS signal would
be when a transceiver is in control of the decision to
transmit. The Am79C930 device must first indicate a de-
sire to transmit by asserting one of the user-definable
output pins to the transceiver and then by setting the
TXS bit of TIR8. These actions place the Am79C930 de-
vice’s transmit state machine in a “wait for CTS” state.
When the transceiver concludes that the medium is free
and a transmission may begin, then it asserts the CTS
signal to the Am79C930 device and the internal
transmit state machine will begin to send data to the
transceiver. For this application, the TXCMD signal
would indicate to the transceiver a desire to transmit,
and the multifunction pin USER1/IRQ12/EXTCTS/
INT188 would provide the return path to the Am79C930
device indicating the transceiver’s decision to proceed
with the transmission.
Start of Frame Delimiter Detection
Automatic Start of Frame Delimiter (SFD) detection is
built into the Am79C930 device’s TAI subunit. Start of
Frame Delimiter length may be defined as 0 bytes, 1
byte, 2 bytes or 3 bytes. The length of SFD is set with the
SD bits of TCR0. The pattern of the SFD is programma-
ble. The SFD registers TCR8, TCR9, and TCR10 are
programmed by the user with the SFD pattern to be
matched. Register status bits with associated interrupt
capability exist for both Antenna Lock and Start of
Frame Delimiter detected. The various register status
and interrupt unmask bits are located in TIR4, TIR5,
TIR7, TIR9, and TIR26. TheFDET output pin signals the
start of frame boundary to external logic and operates
during both RX and TX. Start of Frame Detection is al-
ways calculated based upon network ordering of bits
and is therefore independent of the setting of the WNS
bit (Big vs Little Endian bit ordering control) of TCR3.
The Start of Frame Delimiter search may be performed
by external logic, and the result passed into the
Am79C930 device through the USER6/IRQ5/EXTSDF/
EXTA2DST pin when the ENXSDF bit of TCR28 has
been set to 1. See the Multi-Function Pin section for
more detail.
TX CRC Generation
RX Data Parallelization
A CRC may be automatically calculated for each frame
that is transmitted. The CRC is automatically appended
to the end of the frame when an appropriate TIR bit has
been set. The CRC appended to the transmit frame de-
pends upon the setting of the TCRC bits of TIR8. Either
an 8-bit CRC or a 32-bit CRC may be appended. An op-
tion to append no CRC may also be selected. The CRC
that is selected may be changed on a per-frame basis.
When the CRC is appended to an outgoing frame, an in-
terrupt to the 80188 may be generated, depending upon
the setting of the CRCSU unmask bit of TIR6. The
CRCS bit of TIR4 always indicates when the CRC has
been appended to an outgoing frame, regardless of the
state of the CRCSU bit.
Once the RX Preamble and Start Of Frame Delimiter
have been located, subsequent bits in the serial RX data
stream are converted to parallel byte format and moved
into the RX FIFO. As the RX FIFO fills with data, the TAI
will request RX data byte removal by asserting the
DRQ0 input of the embedded 80188 core. The RXFC
bits of TIR17 contain the current byte count of the
RX FIFO.
RX FIFO
TAI contains individual FIFOs for RX and TX operations.
The RX FIFO indicates a non-empty state by signaling a
request for data on the DRQ0 input of the 80188 embed-
ded core. The DRQ0 output of the TAI subunit is active if
the RX FIFO condition is met, regardless of the state of
the RXS bit of TIR16. RX FIFO DMA activity
is prevented by disabling the DMA0 controller in
the 80188.
The CRC32 polynomial is X32+X26+X23+X22+X16
+X12+X11+X10+X8+X7+X5+X4+X2+X+1; the initial
condition of the CRC32 calculation is FFFF FFFFh; and
the final remainder of the CRC32 operation is
DEBB 20E3h.
The RX FIFO holds a maximum of 15 bytes of data. The
number of bytes of data residing in the RX FIFO is indi-
cated in TIR17. TAI automatically removes the Pream-
ble and Start of Frame Delimiter from the incoming
frame. Any PHY header that has been passed from the
transceivertotheAm79C930devicewillbepreservedin
the FIFO, provided that the PHY header is located after
the Preamble and SFD fields.
The CRC8 polynomial is X8+X5+X+1; the initial condi-
tion of the CRC8 calculation is FFh; and the final ex-
pected remainder of the CRC8 operation is 66h.
TX Status
TIR9 provides bits that indicate the current state of the
Am79C930 device with respect to the transmission of a
frame. Forexample, theTIR9bitsindicatethenumberof
bytes currently in the TX FIFO and whether or not the
transmission is active.
RX CRC Checking
CRCs are automatically checked on arriving frames.
Registers in the TAI indicate where CRC8 and CRC32
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values were found to be correct. These register values
can be used to determine the end of a received frame.
When good CRC values are found, these may be sig-
naled to the 80188 core through interrupt bits in TIR5.
operation is periodic, with the period being set with the
Antenna Diversity Timer register of TCR4.) The delay
from antenna switch to the beginning of the A/D conver-
sion operation is programmed in the RSSI Sample Start
register (TCR24). The converted RSSI value is then
compared against the RSSI Lower Limit value that is
programmed into TIR28. The current RSSI limit com-
parison test result may be read from the RSALT bit
(RSSI Above Limit) of TIR28. The result of this compari-
son test is fed to the CCA decision logic and to the Stop
Diversity decision logic when the URSSI bit of TCR28 is
set to 1.
The CRC32 polynomial is X32+X26+X23+X22+X16
+X12+X11+X10+X8+X7+X5+X4+X2+X+1; the initial
condition of the CRC32 calculation is FFFF FFFFh; and
the final remainder of the CRC32 operation is
DEBB 20E3h.
The CRC8 polynomial is X8+X5+X+1; the initial condi-
tion of the CRC8 calculation is FFh; and the final ex-
pected remainder of the CRC8 operation is 66h.
There are three submodes to the basic internal A/D
converter mode:
RX Status Reporting
TIR11 provides bits that indicate the current state of the
Am79C930 device with respect to the reception of a
frame. For example, the TIR11 bits indicate the number
of bytes currently in the RX FIFO and whether or not a
reception is active.
Internal_A mode disables the SAR pins (TCR25[5] =
ENSAR = 0)
Internal_B mode allows the converted value to be
driven onto the SAR pins. (TCR25[5] = ENSAR = 1)
Internal_C mode allows an external circuit to control
the timing of the A/D sample and convert operation in
order to synchronize the internal Am79C930 de-
vice’s A/D operation with the operations of an exter-
nal antenna selection scheme. This mode is
selected with the UXA2DST bit of TCR25[7].
Bit Ordering
Both Big and Little Endian support is available for trans-
mit and receive operations. The default mode is Little
Endian. The operational mode is selected with the WNS
bit of TCR3. Only FIFO data is affected by the WNS set-
ting. No other register information is swapped.
Normally, the A/D conversion starts when the Antenna
Dwell Timer counts down to the value programmed in
the Sample Start field of TCR24 (SS field). The antenna
dwell timer repeats its cycle every ADT[5:0] time steps,
forever. If a satisfactory antenna is found, then the an-
tenna switching ceases, but RSSI testing continues to
provide input to the CCA logic at the end of each “dwell.”
RSSI A/D Unit
Several modes of operation are possible with the
Am79C930 A/D subunit. The following two paragraphs
describe the basic internal mode of operation. Following
this description is a list of the additional modes and de-
scriptions of each. For programming information, refer
to the ADDA bit description under TIR26[2].
However, when UXADTST is set to 1, then the A/D con-
verter will sample and convert whenever a rising edge
appears on the USER6/IRQ5/EXTSDF/EXTA2DST pin.
The conversion process will occur over the time pro-
grammed in the TCR25 A2DT field. This function allows
an external circuit to synchronize the function of the
Am79C930 A/D converter to the external circuit’s peri-
odic requirements. A/D converted values will be avail-
able on the SAR output pins, provided that the ENSAR
bit of TCR25 has been set to a 1.
The TAI contains a configurable RSSI A/D unit that al-
lows externally supplied analog values to be converted
to 7-bit digital values. Two A/D analog input pins are pro-
vided(ADIN1, ADIN2). Theactiveinputmaybeselected
with the SRCS (Source Select) bit in TIR26. The conver-
sion time of the internal A/D converter is approximately
600 ns. The frequency of sample conversion is con-
trolled with the Antenna Diversity Timer register
(TCR4). A/D converter output values are available at the
SAR[6:0] output pins for external use. A/D converter
output values are available to firmware by reading from
TIR27. The result of the A/D conversion is used by inter-
nal logic to perform Clear Channel Assessment (CCA)
and Antenna Diversity tests. A reference input (ADREF)
is supplied which allows the user to set the upper range
limit on the A/D converter.
In addition to the internal A/D modes, there are two ex-
ternal modes, one for A/D and one for D/A:
External A/D mode causes the ADIN1 and ADIN2 pins
to become outputs, which are then used to control the
power cycling and conversion of an external A/D device.
The SAR pins are used as inputs in this mode to allow
the externally converted value to be driven back into the
Am79C930 device, so that it may be used in the CCA
and Antenna Diversity logic circuits. In this mode,
ADIN1 functions as the power control signal. ADIN1 be-
comes active at the beginning of the A/D cycle, with a
period as specified in the Antenna Diversity Timer
The RSSI A/D unit’s output may be used by the CCA
logic and by the Antenna Diversity logic, depending
upon the setting of the URSSI bit of TCR28. If the URSSI
bit is set to 1, then the A/D conversion process begins
after a programmable delay following an antenna
diversity antenna switching operation. (The switching
Am79C930
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register of TCR4. ADIN2 becomes active after ADIN1 by
the amount of delay specified in the RSSI Sample Start
time of TCR24. ADIN2 remains active for the time pro-
grammed in the A2DT register (TCR25). The converter
output should be connected to the SAR pins, which act
as inputs in this mode.
Baud Determination Logic
The TAI contains Baud Determination logic that sam-
ples the incoming bit stream to determine the data rate.
The result of the Baud Determination is used in making
decisions regarding Clear Channel Assessment and in
selecting an antenna. The Baud Determination logic
functions as follows:
External D/A mode allows the user to connect an exter-
nal D/A converter to the Am79C930 device. The SAR
pins function as outputs and values written to the SAR
register (TIR27) will be driven onto these pins for con-
version by the external D/A device.
Baud Determination testing is performed on a periodic
basis, where the period is determined by the Antenna
Diversity time of TCR4. Baud Determination is intended
to be alternately performed on up to two separate anten-
nas. The antenna diversity decision logic is coupled to
the Baud Determination logic in such a manner that
each successive set of Baud Determination tests is per-
formed on alternating antenna selections. Baud Deter-
mination continues for CCA when an antenna is chosen,
but baud detect results will not affect antenna selection
once an antenna has been locked. Baud detect tests
continue with the periodicity of the dwell timer. Antenna
diversity switching ceases when a satisfactory antenna
has been found. See the section on Automatic Antenna
Diversity logic for antenna selection criteria and testing.
Antenna selection testing resumes following the asser-
tion of either the RXRES bit (RX RESET) of TIR16 or the
RXS bit (RX Start) of TIR16. This action causes the
dwell timer to reset to the value found in TCR4 [5:0] and
then to resume.
The following table indicates the programming required
in order to effect each mode of the A/D section of the
Am79C930 device:
ADDA
ENEXT
ENSAR
UXA2DST
A/D
TIR26[2] TCR25[6] TCR25[5] TCR25[7]
mode
0
0
0
0
0
0
1
1
0
0
0
0
1
1
X
X
0
0
1
1
0
1
0
1
0
1
internal_A
reserved
internal_B
internal_C
external
0
1
X
X
X
X
reserved
reserved
D/A mode
Because antenna switching can cause transient noise
to appear at the RXD input of the Am79C930 device, the
start of Baud Determination testing is delayed for a pe-
riod of time immediately following the antenna switching
process. In order to accommodate different transceiver/
antenna settling times, the amount of test start delay is
programmable through the Baud Detect Start Timer of
TCR16. Therefore, the duty cycle of the Baud Determi-
nation test period (i.e., the portion of the period during
which Baud test measurements are performed) is equal
totheAntennaDiversitytimeofTCR4minusthevalueof
the Baud Detect Start time of TCR16, minus an addi-
tional three CLKIN periods (6 CLKIN periods if
CLKGT20=1). The three CLKIN periods are used for fi-
nal calculations of Baud Determination, Clear Channel
Assessment, andAntennaselectiononceasetofmeas-
urements has been taken and before a new cycle is al-
lowed to begin.
Physical Header Accommodation
The Am79C930 device can accommodate physical
header information by delaying the start of CRC8 and
CRC32 calculations on outgoing and incoming frames,
until a specified number of bytes beyond the Start of
Frame Detection has become asserted. The length of
the physical header may be anywhere from 0 to 15 bytes
as indicated by the value in the PFL bits of TCR3.
DC Bias Control
An optional DC bias control circuit exists within the
Am79C930 device. This circuit may be disabled through
software control. The circuit uses 16-bit block inversion
and bit stuffing to insure a proper DC balance to the out-
going signal on transmit. Receive signals will automati-
cally have the DC Bias Control removed before further
operations inside of the Am79C930 device. Bit stuffing
may begin with the first bit transmitted after SFD, or at
the beginning of a programmable number of byte times
following the SFD. Receive frames may be “de-stuffed”
inasimilarmanner. DCBiasControlmaybedisabledfor
transmit through a control bit located in TCR1. DC Bias
Control may be disabled for receive through a control bit
located in TCR3. Bit stuffing start control is located
in TCR2 [7].
The Baud Determination measurement process is con-
ducted as follows:
Two counters track the separation between adjacent
falling edges and adjacent rising edges of incoming
receive data. One counter measures the separation
between adjacent falling edges of incoming receive
data, and the other counter measures the separation
between adjacent rising edges of incoming receive
data. Measurement resolution is equal to the CLKIN pe-
riod with the CLKGT20 bit of MIR9 set to 0, and
52
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resolution is equal to twice the CLKIN period when the
CLKGT20 bit of MIR9 is set to 1. (For a 1 MB data rate
with CLKIN = 20 MHz and CLKGT20 = 0, resolution is
50 ns.) After each pair of rising edges is detected, the
value of the rising edge separation counter is compared
against the Baud Detect upper limit register value
(TCR17) and also against the Baud Detect lower limit
register value (TCR18). If the rising edge counter value
is between these limits, then a GOOD counter is incre-
mented. If the rising edge counter value is outside of
these limits, then a FAIL counter is incremented.
count exceeds this value, then the Baud Detect determi-
nation for Stop Diversity is TRUE. The Baud Detect de-
termination for Stop Diversity may in turn, be used in the
final determination of antenna selection, depending
upon the setting of the UBDSD bit of TCR28.
Clear Channel Assessment Logic
The Am79C930 device gathers CCA information from
one of two possible sources. One source is the
Am79C930 device’s internal CCA logic, which is de-
scribed in the following paragraphs. The other possible
CCA source is externally computed CCA information,
whichisthenpassedintotheAm79C930devicethrough
the USER5/IRQ4/EXTCHBSY pin. Regardless of the
source of CCA information, a path through the
Am79C930 TAI section is provided allowing the embed-
ded 80188 controller to either poll the status of the CCA
result or to be interrupted by any change to the CCA
status, or to be interrupted whenever the CCA status
changes to the “Busy” state. Selection of CCA source is
through the ENXCHBSY bit of TCR15.
A similar comparison is made whenever the falling edge
detection circuit locates a pair of falling edges. The
GOOD counter and the FAIL counter are shared by both
the rising edge and falling edge measurement circuits.
Both rising edge measurements and falling edge meas-
urements will contribute to the total GOOD and FAIL
counts during any Baud Determination cycle period.
Note that the falling and rising edge separation counters
begin counting at 0 and count up to 30 decimal and then
wrap back to 10 decimal before continuing. This means
that all multiples of 20 counts are aliased to a final
counter indication of 20. Neither of the rising or falling
edge separation counters is accessible to the user.
The TAI contains CCA logic that relies on two inputs to
determine whether or not a carrier is present on the me-
dium. One, both, or none of the two inputs may be se-
lected to determine whether or not a carrier is present.
Oneinputthatmaybeusedtodeterminecarriersenseis
the result of the Baud Determination of Carrier Sense as
described in the Baud Determination logic section. The
other input used by the CCA logic is whether or not the
value of the converted RSSI input exceeds a pro-
grammed lower limit (RSSI Lower Limit of TIR28).
At the end of any Baud Determination cycle, the value in
the GOOD counter is compared against the Baud De-
tect Accept Count for Carrier Sense (TCR19). If the
GOOD count is less than the value of TCR19, then the
Baud Detect determination of Carrier Sense is uncondi-
tionally FALSE. If the GOOD count exceeds the value of
TCR19, then the GOOD count is compared against the
value of the Baud Detect Ratio register (TCR21) multi-
plied by the FAIL count. If the GOOD count exceeds this
value, then the Baud Detect determination of Carrier
Sense is TRUE. The Baud Detect determination of Car-
rier Sense may, in turn, be used in the final determina-
tion of Carrier Sense (Clear Channel Assessment),
depending upon the setting of the UBDCS bit of TCR28.
Note that Baud Determination of Carrier Sense meas-
urements are made on a periodic basis where the period
and duty cycle of the measurements depends upon the
settings of the Antenna Diversity Timer (TCR4) and the
Baud Detect Start timer (TCR16).
EitherinputorbothinputsmaybeusedtomaketheCCA
decision. Each input to the CCA logic is enabled by a
specific bit of TCR28. The UBDCS bit of TCR28 is used
to select/deselect the Baud Determination of Carrier
Sense for use in CCA decisions, and the URSSI bit of
TCR28 is used to select/deselect RSSI information in
CCA decisions. Note that URSSI bit of TCR28 is also
used to select/deselect RSSI information for use in Stop
Diversity decisions.
At the end of any Baud Determination cycle, the value in
the GOOD counter is compared against the Baud De-
tect Accept Count for Stop Diversity (TCR20). If the
GOOD count is less than the value of TCR20, then the
Baud Detect determination for Stop Diversity Switching
is unconditionally FALSE. If the GOOD count exceeds
the value of TCR20, then the GOOD count is compared
against the value of the Baud Detect Ratio register
(TCR21) multiplied by the FAIL count. If the GOOD
The possible CCA results are as follows.
Am79C930
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CCA Result
(CHBSY Bit
of TIR26)
UBDCS
TCR28:1
URSSI
TCR28:0
Baud Detect Carrier
Sense Decision
RSSI >= RSSI
Lower Limit
0
0
0
1
1
1
1
1
1
0
1
1
0
0
1
1
1
1
don’t care
don’t care
don’t care
TRUE
don’t care
yes
CHBSY = TRUE
CHBSY = TRUE
CHBSY = FALSE
CHBSY = TRUE
CHBSY = FALSE
CHBSY = TRUE
CHBSY = FALSE
CHBSY = FALSE
CHBSY = FALSE
no
don’t care
don’t care
yes
FALSE
TRUE
TRUE
no
FALSE
FALSE
yes
no
The current CCA result is reported in the CHBSY bit
of TIR26.
or a soft reset. Baud detection tests continue during
antenna lock time, using the same periodicity (i.e.,
the dwell timer), even though antenna switching has
stopped. These baud tests provide input for the
CCA logic.
A rising edge of CHBSY will set the Busy Channel
Found (BCF) bit of TIR5. This bit may serve as an inter-
rupt to the 80188 core, or the interrupt due to this bit may
be masked and the bit can be polled by the 80188 core.
An antenna is deemed “satisfactory” when the combina-
tion of inputs to the Stop Diversity decision logic is
TRUE. The Stop Diversity decision is based upon the
value of one or two input conditions, where the user may
choose which conditions are examined. The following
are the two inputs that may be used for Stop
Diversity decisions:
The CCA result is also reported in the CHBSYC bit of
TIR4. This bit reports a change in state of the carrier
sense. This bit may serve as an interrupt to the 80188
core, or the interrupt due to this bit may be masked and
the bit can be polled by the 80188 core.
The current RSSI limit comparison test result may be
read from the RSALT bit (RSSI Above Limit) of TIR28.
One possible input to the Stop Diversity decision logic is
the Baud Detect for Stop Diversity determination as
described in the Baud Determination section and
summarized here. The Baud Detect for Stop Diversity
determination is made by making multiple measure-
ments of the separation between adjacent (and same–
direction) bit stream edge transitions (baud detect
tests), thencomparingthemeasuredrateofedgetransi-
tions against programmed limits and tallying the number
of passes and failures of these tests, checking to see
that the total number of passed tests exceeds a given
lower limit, and finally, checking that the ratio of passes
to fails exceeds a given threshold ratio. If this final result
is TRUE, then the Baud Detect for Stop Diversity is con-
sidered to be “TRUE.”
The CCA result has no effect on the Transmit state ma-
chine operation. That is, if the CCA result is CHBSY =
TRUE and the TXS bit (Transmit Start) of TIR8 has been
set to a 1, then the transmit state machine will proceed
withexecutionofitstransmissionsequence. Determina-
tion of exactly when to begin transmission is the respon-
sibility of the firmware that sets the TXS bit of TIR8,
based upon input derived from the CHBSY bit of TIR26
and other considerations (such as NAV value, backoff
timer, etc.).
Automatic Antenna Diversity Logic
The TAI contains automatic antenna diversity logic that
relies on carrier sense determination in order to select a
satisfactory antenna for frame reception. The general
function of the antenna diversity logic is as follows:
Note that Baud Determination of Stop Diversity meas-
urements are made on a periodic basis where the period
and duty cycle of the measurements depends upon the
settings of the Antenna Diversity Timer (TCR4) and the
Baud Detect Start timer (TCR16). The Dwell Timer
never stops running (unless set to 0).
The automatic antenna diversity logic switches the
ANTSLTandANTSLT pinsbetweentwodifferentanten-
nas repeatedly at a programmable periodic rate. Meas-
urements of signal strength and Baud Determination
testing are performed on each antenna. Antenna Diver-
sity Switching and test measurements continue until the
combination of the test outcomes dictates a stop to di-
versity switching. At such a point, a satisfactory antenna
has been found, antenna switching will cease and the
selected antenna will be used for reception until the Re-
ceive RESET (RXRES) bit of TIR16 is set, or until the
Receive Start (RXS) bit of TIR16 is set, or a hard reset,
The second possible input to the Stop Diversity decision
logic is the result of a comparison of the RSSI converted
value against a pre-programmed lower limit. If the
measured RSSI input value exceeds the programmed
lower limit, then the result of this test is considered to
be TRUE.
The two tests mentioned above may be separately
selected/deselected to serve as inputs to the Stop
54
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Diversity decision logic for determining if a satisfactory TXC As Input
antenna has been found. These inputs to the Stop Di-
versity decision logic are enabled by specific bits of
TCR28. The UBDSD bit of TCR28 is used to select/
deselect the Baud Determination of Stop Diversity for
use in Stop Diversity decisions and the URSSI bit of
TCR28 is used to select/deselect RSSI information in
Stop Diversity decisions. Note that the URSSI bit of
TCR28 is also used to select/deselect RSSI information
for use in CCA decisions.
For typical transceiver connections, the signal TXC is
defined as an input to the transceiver. However, for
some transceiver connections, the signal TXC is de-
fined as a transceiver output. The Am79C930 device
can accommodate both types of transceivers by allow-
ing the TXC pin to be defined as either output or input.
In the case where the TXC pin is as output from a trans-
ceiver, the TXCIN bit of TCR30 must be set to a 1 in
order to change the direction of the TXC signal. When
this is done, a 16-bit serial-FIFO is added into the path of
the TX data in order to accommodate a small amount of
possible mismatch between the transceiver’s TXC fre-
quency and the Am79C930 device’s internal TXC fre-
quency. When this FIFO is inserted into the transmit
datastream, anadditionaldelayof8-bittimesisincurred
between the assertion of the TXS bit of TIR8 and the as-
sertion of the first transceiver transmit control signal in
the transmit control sequence.
The possible Stop Diversity results are shown in the
table below.
The current stop diversity result is reported in the
ANTLOK bit of TIR26.
A rising edge of ANTLOK will set the ALOKI (Antenna
Lock Interrupt = Diversity switching stopped) bit of TIR5.
This bit may serve as an interrupt to the 80188 core, or
the interrupt due to this bit may be masked and the bit
can be polled by the 80188 core.
If the mismatch between the transceiver’s TXC fre-
quency and the Am79C930 device’s TXC frequency is
too large, then a serial-FIFO overflow or underflow con-
dition may occur. When this situation arises, an error will
be indicated by the ATFO or ATFU bits of TCR11.
The antenna diversity switching is signaled with the
ANTSW bit of TIR4. This bit reports a change in the an-
tenna selection. This bit may serve as an interrupt to the
80188 core, or the interrupt due to this bit may be
masked and the bit polled by the 80188 core.
IEEE 1149.1 Test Access Port Interface
The current antenna selection may be read from the
ANTSLT bit of TIR26.
An IEEE 1149.1 compatible boundary scan Test Access
Port (TAP) is provided for board level continuity test and
diagnostics. All digital input, output, and input/output
pins are tested. ADREF, TRST, TCK, TMS, TDI, TDO,
and PMX2 pins are not included in the boundary
scan test.
The current RSSI limit comparison test result may be
read from the RSALT bit (RSSI Above Limit) of TIR28.
Automatic Antenna Diversity switching may be disabled
through appropriate setting of the ANTSEN bit of TIR26.
Manual setting of the antenna selection is then allowed
through the ANTS bit of TIR26.
Stop Diversity
Baud Detect Stop
Stop Diversity
Decision
Result
(ANTLOK Bit
of TIR26)
UBDSD
URSSI
STPEN
RSSI >= RSSI
Lower Limit
TCR28[2]
TCR28[0]
TCR28[3]
X
0
0
0
1
1
1
1
1
1
X
0
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
don’t care
don’t care
don’t care
don’t care
TRUE
don’t care
don’t care
yes
ANTLOK = FALSE
ANTLOK = TRUE
ANTLOK = TRUE
ANTLOK = FALSE
ANTLOK = TRUE
ANTLOK = FALSE
ANTLOK = TRUE
ANTLOK = FALSE
ANTLOK = FALSE
ANTLOK = FALSE
no
don’t care
don’t care
yes
FALSE
TRUE
TRUE
no
FALSE
yes
FALSE
no
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The following is a brief summary of the IEEE 1149.1
compatible test functions implemented in the
Am79C930 device:
TAP FSM
The TAP engine is a 16-state FSM, driven by the Test
Clock (TCK) and the Test Mode Select (TMS) pins. This
FSM is in its reset state at power up or after H_RESET.
The TRST pin is supported in order to ensure that the
FSM is in the TEST_LOGIC_RESET state before test-
ing is begun.
Boundary Scan Circuit
The boundary scan test circuit uses five pins: TRST,
TCK, TMS, TDI, and TDO. These five pins are collec-
tively labeled the TAP. The boundary scan test circuit in-
cludes a finite state machine (FSM), an instruction
register, and a data register array. Internal pull-up resis-
torsareprovidedfortheTDIandTMSpins. TheTCKpin
must not be left unconnected.
Supported Instructions
In addition to the minimum IEEE 1149.1 requirements
(BYPASS, EXTEST, and SAMPLE instructions), one
additional instruction (IDCODE) is provided as addi-
tional support for board level testing. All unused instruc-
tion decodes are reserved.
Instruction Name
Instruction Code
Mode
Selected Data Register
Description
EXTEST
ID_CODE
SAMPLE
Reserved
BYPASS
0000
0001
Test
BSR
ID
External Test
Normal
Normal
Reserved
Normal
REG ID Code Inspection
Sample Boundary
Reserved
0010
BSR
0011–1110
1111
Reserved
Bypass
Bypass Scan
Instruction Register and Decoding Logic
Device ID Register Contents:
After H_RESET or S_RESET, the IDCODE instruction
is always loaded into the IEEE 1149.1 register. The de-
coding logic gives signals to control the data flow in the
DATA registers according to the current instruction.
Bits 31–28:
Bits 27–12:
Bits 11–1:
Version
Part Number (0010 1000 0101 0000)
Manufacturer ID. The 11 bit manufacturer
ID code for AMD is 00000000001 in accor-
dance with JEDEC publication 106-A.
Boundary Scan Register (BSR)
Each BSR cell has two stages. A flip-flop and a latch
are used for the SERIAL SHIFT STAGE and for the
PARALLEL OUTPUT STAGE, respectively.
Bit 0:
Always a logic 1
This is an internal scan path for AMD internal
testing use.
There are four possible operation modes in the
BSR cell:
Power Saving Modes
Power Down Function
1
2
3
4
Capture
TheAm79C930BIUincludesfiveregistersthatareused
to invoke a power-down function that will support the
IEEE 802.11 (draft) specified power down by allowing
variable lengths of power-down and power-up time. The
registers include the Processor Interface Register
(MIR0), which contains the Power Down command bit, a
Power Down Length Count set of registers (MIR2,3,4),
and a Power Up Clock Timer (MIR1) register. The power
down sequence is executed by the firmware running
on the embedded 80188, either independently, or in
response to a request from the host. In the PCMCIA
Shift
Update
System Function
Other Data Registers
(1) BYPASS REGISTER (1 BIT)
(2) DEVICE ID REGISTER (32 BITS)
(3) INSCAN0
56
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mode, the host requests a power down by writing to the
Power Down bit (bit 2) of the PCMCIA Card Configura-
tion and Status Register. In the ISA Plug and Play mode,
the host requests a power down by writing to the ISA
Power Down bit, bit 7 of SIR3. In either case, the power
downrequestwillgenerateaninterrupttothe80188em-
bedded core. In response to the interrupt, the 80188
core should be programmed to perform a power down
sequence, as follows:
If the Am79C930 device is operating in the ISA Plug and
Play mode, then SIR0, SIR1, SIR2, and SIR3 registers
will be the only locations that are still accessible when
theAm79C930deviceisinthepowerdownmode. SIR4,
SIR5, SIR6, and SIR7, Plug and Play registers, and
SRAM and Flash memory locations will not be accessi-
ble in the power down mode when ISA Plug and Play
mode has been selected. This means that Plug and Play
state changes will not be possible in the power
down mode.
To power down the Am79C930 device, the 80188 core
should write a time value to the Power Down Length
Count registers. This time value is the intended duration
of the power down period. Then the 80188 core should
write a time value to the Power Up Clock Timer regis-
ters. This time value is the time needed for the buffered
CLKIN signal to return to stable operation from a
stopped state. Then the 80188 core should write to ap-
propriate TIR registers to power down the transceiver.
The 80188 core should now signal an interrupt to the
host that it is about to enter the power down mode. This
communication is necessary, since some of the
Am79C930 system resources will not be available dur-
ing power down mode, and the driver should not attempt
accesses to the unavailable resources, or else an unac-
ceptably long waiting period will occur before the
Am79C930 device finally wakes up and responds to the
access. The host should respond to the
80188-generated interrupt, and the 80188 will respond
by writing a 1 to the Power Down bit in the Processor In-
terface Register (MIR0). The Power Down command
will cause the internally routed CLKIN signal to the
80188 and the TAI to stop running, thereby, bringing the
80188 itself into a power savings mode. At this point in
the sequence, the driver software will no longer have ac-
cess to the SRAM and Flash memory devices. Only the
PCMCIA CCR registers and SIR0, SIR1, SIR2 and SIR3
will remain accessible to the host.
When the power down command is executed, the clock
to most of the circuits of the device is suspended while
power is maintained, such that all state information is
preserved. Outputs that were driving active high or ac-
tive low signals at the time of execution of the power
down command will continue to hold in the state that
they were in at the time of execution of the power down
command. Outputs that were held in a high impedance
state will remain in a high impedance state. Note that
some outputs may still change state, as some sections
of the device are not affected by power down (e.g., the
system interface signals that are used to access the
PCMCIA configuration registers and SIR0, SIR1, SIR2,
and SIR3). Transitions on device inputs which lead to
circuits that are affected by the power down will not be
seen by the circuit, since the circuit is powered down.
Whenthepowerdownmodeisexited, theinternallysus-
pended clock will resume and logical operations will
continue from the point of suspension with no loss of
state information.
When the Power Down Length Counter reaches the
value of the Power Up Clock Timer, then the PWRDWN
output will be deasserted. When the Power Down
Length Counter reaches 0, then the signal on the CLKIN
input to the Am79C930 will once again be sent to all
parts of the device. The time between the deassertion of
PWRDWNandthereapplicationoftheCLKINtointernal
circuits allows the clock to stabilize before it is distrib-
uted to the 80188 core and the TAI.
When the power down command is executed, the
PWRDWNoutputwillbecomeactive. Thisoutputcanbe
used to power down additional devices which are part
of the entire Am79C930-based subsystem, such as a
radio transceiver. (Note that the CLKIN clock signal to
internal Am79C930 circuits will be gated off inside of the
Am79C930 device, even when the external oscillator
continues to drive the Am79C930 CLKIN input.)
A discrete power up timer, which would indicate the time
duration that the Am79C930 device should remain
awake, is not included in the Am79C930 device, but a
firmware implementation of such a function is possible
byusingtheFreecountofMIR5, MIR6, andMIR7and/or
80188 controller timers.
In the power down mode, slave accesses to the
Am79C930 device will become limited to the PCMCIA
Card Configuration Option Register, the PCMCIA Card
Configuration and Status Register, and SIR0, SIR1,
SIR2, and SIR3 if the Am79C930 device is in PCMCIA
mode. All other registers will be inaccessible, including
SRAM and Flash memory locations either through the
memory window or through SIR4, SIR5, SIR6, or SIR7.
(Note that a CIS READ operation will cause power down
exit, but will proceed normally.)
Writing a 1 to the Power Down bit of the PCMCIA Card
Configuration and Status Register will cause a request
for a power down to be generated to the 80188 core via
an interrupt bit in MIR0. The decision to power down will
be made by the 80188 controller, and the actual power
down command will be executed by the 80188 controller
by shutting off the transceiver and any other resources
and then writing to the power down command bit (PDC)
of MIR0.
Am79C930
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Writing a 1 to the Power Down bit of the ISA Power
Down bit of SIR3 will cause a request for a power down
to be generated to the 80188 core via an interrupt bit in
MIR0. The decision to power down will be made by the
80188 controller, and the actual power down command
will be executed by the 80188 controller by shutting off
thetransceiverandanyotherresourcesandthenwriting
to the power down command bit (PDC) of MIR0.
upper layers of the application and the Am79C930 de-
vice; and (2) the Am79C930 MAC firmware, which runs
on the embedded 80188 CPU, performs IEEE 802.11
(draft) MAC protocol functions and sends status infor-
mation to the device driver. The device driver communi-
cates with the Am79C930 device through the
system interface, usually by reading and writing to the
SRAM, with occasional accesses to Am79C930 device
registers. The Am79C930 device appears to the
device driver as a series of I/O mapped registers,
memory-mapped SRAM, and Flash memory. The MAC
firmware uses most of the Am79C930 device registers,
the SRAM, and the Flash memory to perform the IEEE
802.11 (draft) MAC functions. The Am79C930 device
driver also uses the SRAM to pass command and status
information to and from the Am79C930 device.
Writing a 0 to the Power Down bit of the PCMCIA Card
Configuration and Status Register will cause the Power
Down mode to be exited early by forcing the PDLC value
to 0. Because of this transition to 0, the PUCT value will
most likely not be encountered, and no power up ramp
time will occur (i.e., the PWRDWN signal will be deas-
serted at the same time that the CLKIN is reapplied to
the internal circuitry.).
Am79C930 System Interface Resources
Writing a 0 to the ISA Power Down bit of SIR3 will cause
the Power Down mode to be exited early by simulating
the effect of the Power Down Length Counter expiring.
Driver interaction with the Am79C930 device takes
place through the system interface.
The purpose of the Am79C930 device driver is to move
dataframesinandoutoftheAm79C930-basedwireless
communications system. The device driver will move
outgoing data frames into shared memory space and
then pass a command to the Am79C930 device indicat-
ing that the outgoing data is present and ready for trans-
mission. The device driver will respond to interrupts
from the Am79C930 device indicating that incoming
data has been placed into shared memory by the
Am79C930 device and is present and ready for proc-
essing by the device driver. The Am79C930 device also
uses the interrupt to indicate other changes in
Am79C930devicestatus. Commandsotherthan“trans-
mit” may be passed to the Am79C930 device by
the driver.
Writing a 1 to the Exit Power Down bit of SIR0 will cause
the Power Down mode to be exited early by forcing the
PDLC value to 0. Because of this transition to 0, the
PUCT value will most likely not be encountered, and no
power up ramp time will occur (i.e., the PWRDWN signal
will be deasserted at the same time that the CLKIN is
reapplied to the internal circuitry.).
Performing a CIS READ operation while the Am79C930
device is in the power down mode will cause an early
exit of the power down mode in exactly the same man-
ner as if the PCMCIA Card Configuration and Status
Register Power Down bit had been reset by writing a 0
to it.
Applicability to IEEE 802.11 Power Down Modes
In order to accommodate these basic functions of the
driver, theAm79C930deviceincludesanumberofcom-
mand and status registers as well as direct system inter-
face access to up to 128K of shared memory space
(SRAM). The device driver also has access to the 128K
ofFlashmemoryspacethatisusedtostorethefirmware
for the embedded 80188 core.
The power down functionality described above can be
applied to the IEEE 802.11 (draft) power down modes
by setting appropriate time values in the Power Down
Length Count register. This allows the Am79C930 de-
vice to power up at the IEEE 802.11 (draft) specified tim-
ing intervals in order to listen to the network for TIM and
DTIM messages. After listening for a specific amount of
time, the Am79C930 device can interrupt the driver soft-
ware with the intent of requesting the driver to re-initiate
the power down sequence. The free-running counter
can be used to calculate the proper Power Down Length
Count register values for each power down cycle.
The following sections describe the resources available
to the device driver through the system interface. Later
sections will describe the resources available to the
MAC firmware through the 80188 embedded core.
PCMCIA Mode Resources — The first table indicates
the range of I/O and memory addresses to which the
Am79C930 device will respond while operating in the
PCMCIA mode:
Software Access
TheAm79C930deviceisdirectlydrivenbytwopiecesof
software: (1) the device driver, which runs on the host
machine’s CPU, performs transfers of data between the
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Am79C930 Device PCMCIA Mode Resource Requirements
Common
Common
Attribute
Attribute
Memory Range
Memory Size
I/O Range
I/O Size
Memory Range
Memory Size
0000h – 7FFFh
32 Kbytes
OR
0000h – 0027h
OR
40
OR
0000h – 0803h
2 K+4 bytes
0 bytes
0000h – 000Fh
16
bytes
The I/O range is adjusted through bit 2 (EIOW = Expand
I/O Window) of SIR1 = Bank Switching Select register).
performed with the Am79C930 device’s CE1 signal ac-
tive. This means that there is aliasing of addresses in I/O
space. This decode function is unaffected by the setting
of the SIR1[2:0] register bits.
Note that since the Am79C930 device’s memory
mapped resources are all accessible through the Local
Memory Address Register and I/O Data Ports
(SIR2,3,4,5,6,7), it is possible to assign the Am79C930
device no memory space. (This is accomplished by
setting the MemSpace field of the TPCE_FS byte of
the Configuration Table Entry Tuple to 00b. This will
inform the PCMCIA configuration utility that the
Am79C930-based design does not require any Com-
mon Memory space.) By assigning no memory space to
the Am79C930 device, the Am79C930 device will
become an I/O only device. Such an arrangement may
be convenient for systems in which there is not enough
total available memory space to allow the Am79C930
device to use a full 32K block of memory.
PCMCIA Common Memory Resources — While the
common memory space of the Am79C930 device only
accommodates access to 32 Kbytes of memory, the
Am79C930 device uses device select and bank select
bits in SIR1 in order to access a total of 256K of memory
space. Note that PCMCIA accesses to Common mem-
ory locations 7C00h–7FFFh (1K total space) will some-
times correspond to the same physical locations as
PCMCIA accesses to Attribute memory locations
0000h–07FFh (2K total space), i.e., the correspon-
dence will occur only when the device and bank select
bits of SIR1 are pointing at the upper page of the 128K
Flash memory address space. (Note that for Attribute
memory accesses, only the even-valued addresses are
defined to exist. Therefore, 2K total Attribute memory
addresseshavebeenmappedto1Kofphysicalspacein
the Flash memory.) The following table indicates the
mapping of the 256 Kbytes of physical memory space
into the 32 Kbytes of Common memory:
Note that when this option is chosen, the total amount of
bus bandwidth required to perform all of the necessary
accesses to the Am79C930-based design will be in-
creased somewhat, because of the indirect nature of the
I/O method of access to Am79C930-based resources.
Note that the Am79C930 device always decodes
the lowest 6 bits of address when an I/O access is
Am79C930 Device PCMCIA Mode Common Memory Map
PCMCIA Address in
Common Memory
SIR1[5:3]
Size of Space
Physical Memory
0000h – 7FFFh
0000h – 7FFFh
0000h – 7FFFh
0000h – 7FFFh
0000h – 7FFFh
0000h – 7FFFh
0000h – 7FFFh
0000h – 7FFFh
000
001
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
256 Kbytes
SRAM Memory 0 0000h – 0 7FFFh
SRAM Memory 0 8000h – 0 FFFFh
SRAM Memory 1 0000h – 1 7FFFh
SRAM Memory 1 8000h – 1 FFFFh
Flash Memory 0 0000h – 0 7FFFh
Flash Memory 0 8000h – 0 FFFFh
Flash Memory 1 0000h – 1 7FFFh
Flash Memory 1 8000h – 1 FFFFh
010
011
100
101
110
111
TOTAL:
Am79C930
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following
Some of the Am79C930 device’s PCMCIA Common
Memory locations have predefined uses and, therefore,
are not freely available to the device driver. The
table
indicates
restricted
space
within PCMCIA Common Memory map of the
Am79C930 device:
Am79C930 Device PCMCIA Mode Common Memory Restricted Space
PCMCIA Address
Size of
Physical Memory and
in Common Memory
SIR1[5:3]
Restricted Space
Description of Reserved Use
0000h – 03FFh
0400h – 041Fh
000
1 Kbytes
SRAM Memory 0 0000h – 0 03FFh
This space is reserved for the interrupt
vector table of the embedded 80188
core.
000
000
32 bytes
32 bytes
SRAM Memory 0 0400h – 0 041Fh
This SRAM space is inaccessible to
the 80188 embedded core, since the
80188 core maps the 32 TIR registers
of the TAI into this portion of 80188
memory space.
0420h – 043Fh
SRAM Memory 0 0420h – 0 042Fh
This SRAM space is inaccessible to
the 80188 embedded core, since the
80188 core maps the MIR registers of
the BIU (PIR, PDLC and PUCT) and
XCE space into this portion of 80188
memory space.
0440h – 047Fh
7C00h – 7FEFh
000
111
64 bytes
SRAM Memory 0 0440h – 0 047Fh
This SRAM space is reserved for future
use and may be decoded for non-
SRAM purposes in the future.
1K–16 bytes
Flash Memory 1 FC00h – 1 FFEFh
These bytes of the Flash memory also
map into PCMCIA Attribute Memory
space 0000h – 03FFh, which is used
for storing the CIS for the device.
Therefore, this space cannot be used
for non-CIS purposes.
7FF0h – 7FFFh
111
16 bytes
Flash Memory 1 FFF0h – 1 FFFFh
These 16 bytes of Flash memory
space are reserved because they are
the location of the embedded 80188
core’s instruction pointer following a
Am79C930 device reset operation.
These 16 bytes must contain the first
80188 instructions.
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The SRAM is intended to serve as a shared memory re-
source between the driver operating through the system
interface and the 80188 core operating through the
Am79C930 memory interface bus. Even though SRAM
memory locations 0 0400h through 0 043Fh are acces-
sible from the system interface, these locations cannot
be used for driver-firmware shared memory functions,
since they are inaccessible from the 80188 core.
visible as common memory. The upper 32 bytes of the
2K of attribute memory space must not be used for
PCMCIA CIS information, since these bytes map to the
upper 16 bytes of the Flash memory, which will be used
bythe80188coreoftheAm79C930astheinitialinstruc-
tion locations after reset.
Note that the Configuration Tuple must contain the
value 800h for the TPCC_RADR field, since the Card
Configuration Registers within the Am79C930 device
are located at this fixed offset.
PCMCIA Attribute Memory Resources — The
PCMCIA standard requires that each PCMCIA device
contain a Card Information Structure (CIS). The CIS
contains information that is used to provide possible
configuration options to the system.
The PCMCIA Card Configuration registers that are sup-
ported are the Configuration Option Register and the
CardConfigurationandStatusRegister. Thesetworeg-
isters are physically located in the Bus Interface Unit
and logically exist only in PCMCIA Attribute Memory
space. They are located at Attribute Memory locations
0800h and 0802h, respectively. The location of these
registers is fixed. Therefore, the information pro-
grammed into the CIS must give the value 2K (=0800h)
as the Card Configuration Registers Base Address in
the TPCC_RADR field of the Configuration Tuple.
The PCMCIA standard requires that the first tuple of the
CIS should be located at Attribute memory byte 0h. 1K
of Flash memory space is mapped into the lowest 2K of
PCMCIA attribute memory space to accommodate this
requirement. Since odd addressed bytes of Attribute
memory are undefined, these addresses are not
mapped to the Flash memory. The 1K of Flash memory
space that is mapped to Attribute memory space is also
Am79C930 Device PCMCIA Mode Attribute Memory Map
PCMCIA Address
in Attribute Memory
SIR1[5:3]
Size of Space
Physical Memory
0000h – 07FFh
(even values only)
XXX*
2 Kbytes
Flash Memory 1 FC00h – 1 FFFFh
(only 1 K of Flash memory is
allocated, since odd addressed
PCMCIA attribute memory locations
are undefined)
0800h
XXX*
1 byte
Configuration Option Register
in BIU
0801h
0802h
XXX*
XXX*
1 byte
1 byte
Device responds with undefined data
Card Configuration and Status
Register in BIU
0803h
XXX*
XXX*
1 byte
Device responds with undefined data
0804h – 7FFFh
30K–2 bytes
Device may respond to these
addresses. See note below.
*XXX = Don’t care
Note: Device will respond to any address in which A11 is equal to 1 andREG, OE, and CE1 are asserted.
The only writable PCMCIA Attribute memory locations
are the two Card Configuration Registers at Attribute
Memory locations 800h and 802h. These two registers
do not correspond to Flash memory locations. These
two registers are physically located inside of the BIU
section of the Am79C930 device. Attribute memory
locations 0000h–07FFh are mapped directly to Flash
memory and are, therefore, read-only locations. Note
that the 2K space of attribute memory 0000h–07FFh are
mapped to 1K of Flash memory space. Since PCMCIA
defines that only even addressed bytes of Attribute
memory are defined to exist, only the even
addressed 1K of the 2K attribute space is actually
physically present.
Some of the Am79C930 device’s PCMCIA Attribute
Memory locations have predefined uses and, therefore,
are not freely available to the device driver. The follow-
ing table indicates restricted space within PCMCIA At-
tribute Memory map of the Am79C930 device.
Am79C930
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Am79C930 Device PCMCIA Mode Attribute Memory Restricted Space
PCMCIA Address
in Attribute Memory SIR1[5:3] Size of Restricted Space
Physical Memory and Description of Reserved Use
7FE0h – 7FFFh
111
32 bytes of Attribute
Flash Memory 1 FFF0h – 1 FFFFh
memory, 16 bytes of actual
Flash memory space
These 16 bytes of Flash memory space are reserved
because they are the location of the embedded 80188
core’s instruction pointer following a Am79C930 device
reset operation. These 16 bytesmust contain the first 80188
instructions.
PCMCIA I/O Resources — The Am79C930 device oc-
cupies either 16 or 40 bytes of I/O space, depending
upon the setting of the EIOW bit (bit 2 of the BSS register
(SIR1)). The I/O space of the Am79C930 contains the
General Configuration Register, the Bank Switching Se-
lect Register, and the set of 32 TIR registers. Addition-
ally, all Am79C930 resources are accessible through
I/O accesses, i.e., allmemory structures are accessible
through the Local Memory Address and I/O Data
Ports (SIR2,3,4,5,6,7).
selected (SRAM or Flash), and SIR1[4:3] and
LMA[14:0] supply the address to the selected device
whenever the I/O Data Port is read or written. Whenever
any of the I/O Data Ports is accessed, then the Local
Memory Address Port value is automatically incre-
mented by a value of “1.”
Note that the Am79C930 device always decodes the
lowest 6 bits of address when an I/O access is per-
formed with the Am79C930 device’s CE1 signal active.
This means that there is aliasing of addresses in I/O
space. This decode function is unaffected by the setting
of the SIR1[2:0] register bits.
The Local Memory Address port plus SIR1[5:3] function
together as a pointer to the memory resources of the
Am79C930 device. SIR1[5] determines the device
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The following table indicates the mapping of all I/O re-
sources that are accessible through the Am79C930
PCMCIA system interface. Note that some resources
are physically located within the BIU, while others are lo-
cated in the TAI and still others exist as external Flash
and SRAM:
Am79C930 Device PCMCIA Mode I/O MAP
Resource
Name
Resource
Mnemonic
PCMCIA
I/O Address
Resource
Physical Location
of Resource
SIR1[2:0]
Size
SIR0: General
Configuration Register
SIR0: GCR
00h
01h
02h
03h
04h
XXX*
1 byte
BIU
BIU
BIU
BIU
SIR1: Bank Switching
Select Register
SIR1: BSS
SIR2: LMAL
SIR3: LMAU
SIR4: DPLL
XXX
XXX
XXX
XXX
1 byte
1 byte
1 byte
1 byte
SIR2: Local Memory
Address [7:0]
SIR3: Local Memory
Address [14:8]
SIR4: I/O Data
Port[7:0]
Indirect access to
SRAM or Flash
memory
SIR5: I/O Data
Port[15:8]
SIR5: DPLM
SIR6: DPUM
SIR7: DPUU
05h
06h
07h
XXX
XXX
XXX
1 byte
1 byte
1 byte
Indirect access to
SRAM or Flash
memory
SIR6: I/O Data
Port [23:16]
Indirect access to
SRAM or Flash
memory
SIR7: I/O Data
Port [31:24]
Indirect access to
SRAM or Flash
memory
TIR 0–7
–
–
–
–
08h – 0Fh
08h – 0Fh
08h – 0Fh
08h – 0Fh
000
001
010
011
1 byte
each location
TAI
TAI
TAI
TAI
TIR 8–15
TIR 16–23
TIR 24–31
1 byte
each location
1 byte
each location
1 byte
each location
UNDEFINED
TIR 0–31
–
–
10h – 3Fh
08h – 27h
0XX
1X
NA
UNDEFINED
TAI
1 byte
each location
UNDEFINED
–
28h – 3Fh
1XX
NA
UNDEFINED
*X = Don’t Care
ISA Plug and Play Mode Resources
configuration registers, as well as providing a mecha-
nism for access to Flash memory for reading the
Am79C930 device’s Plug and Play Resource Data.
The Am79C930 device fully supports the ISA Plug
and Play specification, revision 1.0a, including the
Plug and Play ADDRESS Auto-configuration port,
WRITE_DATA Auto-configuration port, READ_DATA
Auto-configuration port, and 19 of the Plug and Play
The following table indicates the range of I/O and mem-
ory addresses to which the Am79C930 device will re-
spond when operating in the ISA Plug and Play mode.
Am79C930
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Am79C930 Device ISA Plug And Play Mode Memory And I/O Resource Requirements
Memory Range
Memory Size
I/O Range
I/O Size
MBA*+0000h –
MBA*+7FFFh
32 Kbytes
OR
IOBA**+0000h – IOBA**+000Fh
and I/O 0279h and I/O 0A79h
16 bytes
0 bytes
and I/O 0203h – I/O 03FFh (one byte only)
*MBA = ISA Plug and Play Memory Base Address
**IOBA = ISA Plug and Play I/O Base Address
Note that since the Am79C930 device’s memory
mapped resources are all accessible through the Local
Memory Address Register and I/O Data Ports
(SIR2,3,4,5,6,7), it is possible to program the ISA Plug
and Play Memory Base Address, and Memory upper
limit Address or range length for descriptor 0, such that
the Am79C930 device is assigned no memory space.
(This is accomplished by assigning all 0s for both the
Memory Base Address and the Memory range length
value. The ISA Plug and Play utility can be instructed to
make this selection through appropriate Resource Data
programming.) By assigning no memory space to the
Am79C930 device, the Am79C930 device will become
an I/O only device. Such an arrangement may be con-
venient for systems in which there is not enough total
available memory space to allow the Am79C930 device
to use a full 32K block of memory. Note that when this
option is chosen, the total amount of bus bandwidth re-
quired to perform all of the necessary accesses to the
Am79C930-based system will be increased somewhat,
because of the indirect nature of the I/O method of ac-
cess to Am79C930-based resources.
The Am79C930 device requires the use of a single IRQ
channel. Any of the following channels within an
ISA Plug and Play system may be utilized by the
Am79C930 device:
IRQ 4, 5, 9, 10, 11 or 12.
ISA Plug and Play Memory Resources — While the
system memory space of the Am79C930 device only
accommodates access to 32 Kbytes of memory, the
Am79C930 device uses device select and bank select
bits in SIR1 in order to access a total of 256K of memory
space. Note that ISA accesses to memory locations
7C00h–7FFFh (1K total space) will sometimes
correspond to the same physical locations as ISA ac-
cesses to Plug and Play resource data locations
0000h–03FFh, i.e., the correspondence will occur only
when the device and bank select bits of SIR1 are point-
ing at the upper page of the 128K Flash memory ad-
dress space. The following table indicates the mapping
of the 256 Kbytes of physical memory space into the
32 Kbytes of memory:
Am79C930 Device ISA Plug And Play Mode Memory Map
ISA Address in Memory
MBA+0000h – MBA+7FFFh
MBA+0000h – MBA+7FFFh
MBA+0000h – MBA+7FFFh
MBA+0000h – MBA+7FFFh
MBA+0000h – MBA+7FFFh
MBA+0000h – MBA+7FFFh
MBA+0000h – MBA+7FFFh
MBA+0000h – MBA+7FFFh
SIR1[5:3]
000
Size of Space
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
32 Kbytes
256 Kbytes
Physical Memory
SRAM Memory 0 0000h – 0 7FFFh
SRAM Memory 0 8000h – 0 FFFFh
SRAM Memory 1 0000h – 1 7FFFh
SRAM Memory 1 8000h – 1 FFFFh
Flash Memory 0 0000h – 0 7FFFh
Flash Memory 0 8000h – 0 FFFFh
Flash Memory 1 0000h – 1 7FFFh
Flash Memory 1 8000h – 1 FFFFh
001
010
011
100
101
110
111
TOTAL:
*MBA = ISA Plug and Play Memory Base Address
When accessing Am79C930 memory resources
through ISA memory cycle accesses, the upper 9 bits of
the ISA memory address will be used to check for a
match of the address range assigned to the Am79C930
device by the Plug and Play configuration program (i.e.,
the Memory Base Address = MBA, and Memory range
length). The Plug and Play configuration program will
have written a memory base address value into the
Memory Base Address registers (Plug and Play ports
40h and 41h). The ISA Plug and Play memory base
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address needs to be aligned to a 32K boundary in mem-
ory space. This alignment requirement should be in-
cludedintheResourceDatathatisprogrammedintothe
Flash device and read by the Plug and Play configura-
tion utility. These conditions must be satisfied, since the
Am79C930 device’s Bus Interface Unit will only use the
upper 9 bits of the ISA memory address to determine
when an address match has been achieved.
Some of the Am79C930 device’s ISA Memory locations
have predefined uses and, therefore, are not freely
available to the device driver. The following table indi-
cates restricted space within ISA Memory map of the
Am79C930 device:
Am79C930 Device ISA Plug And Play Mode Memory Restricted Space
ISA Address
in Memory
Size of
Restricted Space
Physical Memory And
Description Of Reserved Use
SIR1[5:3]
MBA+0000h –
MBA+03FFh
000
1 Kbytes
SRAM Memory 0 0000h–0 03FFh
This space is reserved for the interrupt vector
table of the embedded 80188 core.
MBA+0400h –
MBA+041Fh
000
000
32 bytes
SRAM Memory 0 0400h–0 041Fh
This SRAM space is inaccessible to the
80188 embedded core, since the 80188
core maps the 32 TIR registers of the TAI
into this portion of 80188 memory space.
MBA+0420h –
MBA+043Fh
32 bytes
SRAM Memory 0 0420h–0 042Fh
This SRAM space is inaccessible to the
80188 embedded core, since the 80188
core maps the MIR registers of the BIU
(PIR, PDLC and PUCT) and XCE space into
this portion of 80188 memory space.
MBA+0440h –
MBA+047Fh
000
111
64 bytes
SRAM Memory 0 0440h–0 047Fh
This SRAM space is reserved for future use
and may be decoded for non-SRAM purposes
in the future.
MBA+7C00h –
MBA+7FEFh
1K–16 bytes
Flash Memory 1 FC00h–1 FFEFh
These bytes of the Flash memory also map into
the ISA Plug and Play Resource Data space.
Therefore, this space can not be used for
non-Resource Data purposes.
MBA+7FF0h –
MBA+7FFFh
111
16 bytes
Flash Memory 1 FFF0h–1 FFFFh
These 16 bytes of Flash memory space are
reserved because they are the location of
the embedded 80188 core’s instruction
pointer following a Am79C930 device reset
operation. These 16 bytes must contain the
first 80188 instructions.
*MBA = ISA Plug and Play Memory Base Address
Am79C930
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The SRAM is intended to serve as a shared memory re-
source between the driver operating through the system
interface and the 80188 core operating through the
Am79C930 memory interface bus. Even though SRAM
memory locations 0 0400h through 0 043Fh are acces-
sible from the system interface, these locations cannot
be used for driver-firmware shared memory functions,
since they are inaccessible from the 80188 core.
The next table indicates the mapping of all I/O resources
that are accessible through the Am79C930 ISA
system interface.
Note that some resources are physically located within
the BIU, while others are located in the TAI, and still oth-
ers exist as external Flash and SRAM. Also note that
additionalregistersforISAPlugandPlayexistintheBIU
and are indirectly accessed through the Plug and Play
ADDRESS, WRITE_DATA, and READ_DATA ports.
All resources are 1 byte in width.
ISA Plug and Play I/O Resources — The Am79C930
device occupies 16 bytes of I/O space. The 40-byte I/O
option is not available in the ISA Plug and Play mode of
operation. The EIOW bit (bit 2 of the BSS register
(SIR1)) will be forced to 0 when the Am79C930 device
has been placed into ISA Plug and Play mode. The I/O
space of the Am79C930 device contains the General
Configuration Register, the Bank Switching Select Reg-
ister, and the set of 32 TIR registers. Additionally, all
Am79C930 resources are accessible through I/O ac-
cesses, i.e., all memory structures are accessible
through the Local Memory Address and I/O Data
Ports (SIR2,3,4,5,6,7).
When accessing Am79C930 I/O resources through ISA
I/O cycle accesses, the upper 8 bits of the ISA system
address will be ignored. Only the lower 16 bits of
address will be used to check for a match of the address
range assigned to the Am79C930 device by the Plug
and Play configuration program (i.e., the I/O Base Ad-
dress = IOBA). (The Plug and Play configuration pro-
gram will have written an I/O base address value into the
I/O Base Address registers (Plug and Play ports 60h
and 61h) following system boot up and auto-configura-
tion.) The ISA Plug and Play I/O base address must be
aligned to a 16-byte boundary in I/O space. This align-
ment requirement should be included in the Resource
Data I/O Port Descriptor Base Alignment field that is
programmed into the Flash device and read by the Plug
and Play configuration utility. These conditions must be
satisfied for proper operation.
The Local Memory Address port plus SIR1[5:3] function
together as a pointer to the memory resources of the
Am79C930 device. SIR1[5] determines the device se-
lected (SRAM or Flash) and SIR1[4:3], and LMA[14:0]
supply the address to the selected device whenever the
I/O Data Port is read or written. Whenever any of the I/O
Data Ports is accessed, then the Local Memory Address
Port value is automatically incremented by a value of 1.
66
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P R E L I M I N A R Y
Am79C930 Device ISA Plug And Play Mode I/O MAP
Physical
Location of
Resource
ISA
I/O address
SIR1
Bits [2:0]
Resource
Size
Resource Name
Mnemonic
SIR0: General
Configuration Register
SIR0: GCR
IOBA*+0000h
IOBA+0001h
IOBA+0002h
IOBA+0003h
IOBA+0004h
XXX**
XXX
XXX
XXX
XXX
1 byte
1 byte
1 byte
1 byte
1 byte
BIU
BIU
BIU
BIU
SIR1: Bank Switching
Select Register
SIR1: BSS
SIR2: LMAL
SIR3: LMAU
SIR4: DPLL
SIR2: Local Memory
Address [7:0]
SIR3: Local Memory
Address [14:8]
SIR4: I/O Data Port [7:0]
Indirect access
to SRAM or
Flash memory
SIR5: I/O Data Port [15:8]
SIR5: DPLM
SIR6: DPUM
SIR7: DPUU
IOBA+0005h
IOBA+0006h
IOBA+0007h
XXX
XXX
XXX
1 byte
1 byte
1 byte
Indirect access
to SRAM or
Flash memory
SIR6: I/O Data Port
[23:16]
indirect access
to SRAM or
Flash memory
SIR7: I/O Data Port [31:24]
Indirect access
to SRAM or
Flash memory
TIR 0–7
–
–
IOBA+0008h –
IOBA+000Fh
000
001
010
011
0XX
1XX
1 byte
each location
TAI
TAI
TAI
TAI
na
TIR 8–15
TIR 16–23
TIR 24–31
IOBA+0008h –
IOBA+000Fh
1 byte
each location
–
IOBA+0008h –
IOBA+000Fh
1 byte
each location
–
IOBA+0008h –
IOBA+000Fh
1 byte
each location
Device does not respond
to these accesses
–
IOBA+0010h –
IOBA+0027h
NA
NA
Impossible programming of
SIR1 bits (SIR1[2] = 0
always in ISA Plug
na
na
na
and Play mode)
Plug and Play ADDRESS
Auto-Configuration Port
PPA
0279h (fixed)
(write only)
XXX
XXX
1 byte
1 byte
1 byte
BIU
BIU
Plug and Play WRITE_DATA
Auto-Configuration Port
PPWD
PPRD
0A79h (fixed)
(write only)
Plug and Play READ_DATA
Auto-Configuration Port
0203h – 03FFh
XXX
(relocatable)
(READ ONLY)
Indirect access
to ISA Plug and
Play register set
*IOBA = ISA Plug and Play I/O Base Address
**X = Don’t Care
Am79C930
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P R E L I M I N A R Y
ISAPlugandPlayRegisterSet —TheAm79C930de-
vice fully supports the ISA Plug and Play specification,
revision 1.0a.
ADDRESS Auto-configuration Port, WRITE_DATA
Auto-configuration Port, and READ_DATA Auto-con-
figuration Port are all supported and are mapped into
ISA I/O space as follows:
The Am79C930 device supports the Plug and Play
Auto-configuration scheme. The Plug and Play
Am79C930 Device ISA Plug And Play Mode Supported Auto-Configuration Ports
Port Name
ISA (IEEE P996) I/O Address
Access
ADDRESS
WRITE_DATA
READ_DATA
0279h
0A79h
Write only
Write only
Read only
0203h – 03FFh (relocatable)
The location of the READ_DATA Auto-configuration
port is only fixed within the range 0203h–03FFh. The
exactlocationisdeterminedbyawritetotheappropriate
Plug and Play Auto-configuration port (Set
READ_DATA Auto-configuration port).
All Plug and Play ports are 8 bits in width.
To fully support the Plug and Play mechanism, the fol-
lowing additional register locations are defined within
the Am79C930 device. Except for the Resource Data
register, these registers are physically located within the
BIU and are accessed indirectly, through setting the
Plug and Play Port Address in the Plug and Play
ADDRESS port (location I/O 0279h) and then by ac-
cessing either the WRITE_DATA port or the
READ_DATA port. The 80188 embedded core does not
have access to the registers in the following table.
The WRITE_DATA port and the READ_DATA port are
not active until the Initiation Key has been sent to the
Am79C930 device through the ADDRESS port. This be-
havior conforms to the requirements of the Plug and
Play specification.
The Am79C930 device implements the four Plug and
Play configuration states: “Wait for Key,” “Sleep,”
Isolation,” and “Config.”
68
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Am79C930 Device ISA Plug And Play Mode Plug And Play Register Set
ISA Plug and Play
Plug and Play Port
ADDRESS
Register Name
Set READ_DATA port
Serial Isolation
Physical Location
00h
01h
02h
03h
04h
BIU
BIU
Configuration Control
Wake [CSN]
BIU
BIU
Resource Data
Flash Memory 1 FC00h–1 FFF0h
Total of 1K–16 bytes. The uppermost 16
bytes of Flash memory space are
reserved because they are the location of
the embedded 80188 core’s instruction
pointer following an Am79C930 device
reset operation.
Status
05h
06h
BIU
BIU
BIU
NA
Card Select Number (CSN)
Logical Device Number
Unused
07h
08h–2Fh
30h
Activate
BIU
BIU
NA
I/O Range Check
Unused
31h
32h–3Fh
0 40h
Memory Base Address
bits [23:16] descriptor
BIU
Memory Base Address
bits [15:08] descriptor
0 41h
BIU
Memory Control
42h
BIU
BIU
Memory range length
0 43h
bits [23:16] for descriptor
Memory range length
0 44h
BIU
bits [25:08] for descriptor
Unused
45h–5Fh
0 60h
NA
I/O Base Address
BIU
bits [15:08] descriptor
I/O Base Address
0 61h
BIU
bits [07:00] descriptor
Memory Control
62h–6Fh
70h
BIU
BIU
BIU
NA
Interrupt request level select 0
Interrupt request type select
Unused
0 71h
72h–73h
74h
DMA Channel Select 0
Unused
BIU
NA
75h–FFh
Am79C930
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The Am79C930 device maps the Resource Data regis-
ter accesses into 1K–16 of the upper 1 Kbytes of the
Flash memory space so that Resource Data may be
read from the Flash memory. Byte 0 of the Am79C930
device’s Resource Data is mapped to location 1 FC00h
of the Flash memory. A maximum of 1K–16 bytes of Re-
source Data is allowed by the Am79C930 design.
signal, then LCS is assumed, and the access is exter-
nally directed toward the SRAM with the SCE signal, or
internally to the TAI register set, or to the external
XCE device).
Note that the BIU contains at least two separate register
spaces. The System Interface Registers (SIR) (space is
visible to the system interface, but is not visible to the
embedded 80188. The MAC Interface Registers (MIR)
space is visible to the embedded 80188, but is not vis-
ible to the system interface. Communication between
the device driver and the 80188 core occurs indirectly,
as the bits of the MIR0 register will affect bits in the
General Configuration Register (SIR0) and vice versa.
Note that a total of 16 bytes of space is reserved for the
MIR registers, while currently only 10 MIR registers are
defined. The remaining 6 MIR locations are reserved.
Also note that all 32 TIR registers are visible to both the
80188 core and the system interface.
Note that the upper 16 bytes of the Flash memory are
reserved for use by the firmware and the embedded
80188 core for 80188 core initialization. The upper 16
bytes of the Flash memory may not be used to store ISA
Plug and Play Resource Data.
MAC Firmware Resources
The Am79C930 device contains an embedded 80188
corethatcanbeusedtoperformthemajorityofthetasks
necessary to implement the MAC portion of the IEEE
802.11 (draft) standard. The following section describes
the resources that are available to the 80188 core and,
hence, to firmware written for the embedded 80188.
Am79C930 80188 memory resources may be mapped
using either of two schemes. One scheme makes 256K
separate memory locations usable as 128K of Flash
memory space, 128K–128 bytes of SRAM, 64 bytes of
BIU, TAI, and XCE resources and 64 bytes of reserved
space. The other mapping scheme will alias the Flash
memory into a portion of the SRAM space. The following
text and tables describe each of the mapping schemes.
MAC (80188 core) Memory Resources — The
Am79C930 device contains several resources that are
accessible through the 80188 core. These resources in-
clude: up to 128K–128 bytes of SRAM, up to 128 Kbytes
of Flash memory, 16 MIR registers, 32 TIR registers,
and 16 bytes of peripheral device space attached to the
XCE pin. All of the resources that are available to the
80188 core are mapped into 80188 memory space. The
LMCS and UMCS registers of the 80188 core must be
properlyprogrammedtogenerateUCS andLCS signals
in order to take full advantage of all of the resources pro-
vided by the Am79C930 device and associated SRAM,
Flash and XCE devices.
The first mapping scheme (scheme “A”) places SRAM,
the 32 TIR registers, the 16 MIR registers, and the 16
XCE locations into the lower 128K of memory space.
The Flash memory is mapped into the upper 128K of
memory space. This scheme requires that the LMCS
register of the 80188 core be set to 1FF8h. The UMCS
register of the 80188 core must be set to E038h. Also re-
quired is that bit 6 of the MIR0 register (the mapping se-
lect bit) is set to 0.
(In reality, only UCS is used internally. When an access
is performed without the presence of an active UCS
70
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80188 Core Memory Map Using Scheme “A”, LMCS=1FF8h, UMCS=E038h, MIR0[6]=0
Active
80188 Address
in Memory
Active 80188
Chip Select
Am79C930
Chip Select
Size of
Space
Physical Location of Memory
SRAM Memory 0 0000h–0 03FFh
TIR 0–31
0 0000h–0 03FFh
0 0400h–0 041Fh
0 0420h–0 042Fh
0 0430h–0 043Fh
0 0440h–0 047Fh
LCS
LCS
LCS
LCS
LCS
SCE
none
none
XCE
none
1 Kbytes
32 bytes
16 bytes
16 bytes
64 bytes
MIR 0–15
XCE locations 0–15
Reserved for future use–access to
these areas is currently undefined
0 0480h–1 FFFFh
LCS
SCE
128K–
SRAM Memory 0 0480h–1 FFFFh
1K–128 bytes
2 0000h–D FFFFh
E 0000h–F FFFFh
none
none
768 Kbytes
128 Kbytes
Undefined
UCS
FCE
Flash Memory 0 0000h–1 FFFFh
The second mapping scheme (scheme “B”) places 32K
of the SRAM, the 32 TIR registers, the 16 MIR registers,
and the 16 XCE locations into the lowest 32K of memory
space, and then maps the upper 96K of Flash memory
to memory locations 32K through 128K. All 128K of the
Flash memory is also available at the uppermost 128K
memory locations of the 80188 core’s address space.
This scheme allows the LMCS register of the 80188
core be set to 07F8h or 0FF8h or 1FF8h. The UMCS
register of the 80188 core must be set to E038h. Also
required is that bit 6 of the MIR0 register (the mapping
select bit) is set to 1. Note that with mapping scheme
“B”, a maximum of 32K–128 bytes of SRAM space is
available for use. The advantage of mapping scheme
“B” is that when all 80188 firmware can fit into 32K of
Flash memory space and the SRAM memory require-
ment for the application is less than or equal to 32K, then
all 80188 operations occur within a single 64K
memory segment.
80188 Core Memory Map Using Scheme “B”, LMCS=1FF8h, UMCS=E038h, MIR0[6]=1
Active
80188 Address
in Memory
Active 80188
Chip Select
Am79C930
Chip Select
Size of
Space
Physical Location of Memory
SRAM Memory 0 0000h–0 03FFh
TIR 0–31
0 0000h–0 03FFh
0 0400h–0 041Fh
0 0420h–0 042Fh
0 0430h–0 043Fh
0 0440h–0 047Fh
LCS
LCS
LCS
LCS
LCS
SCE
none
none
XCE
none
1 Kbytes
32 bytes
16 bytes
16 bytes
64 bytes
MIR 0–15
XCE locations 0–15
Reserved for future use–access to
these areas is currently undefined
0 0480h–0 7FFFh
LCS
SCE
32K–
SRAM Memory 0 0480h–1 FFFFh
1K–128 bytes
0 8000h–1 FFFFh
2 0000h–D FFFFh
E 0000h–F FFFFh
don’t care
none
FCE
none
FCE
96 Kbytes
768 Kbytes
96 Kbytes
Flash Memory 0 8000h–1 FFFFh
Undefined
UCS
Flash Memory 0 0000h–1 FFFFh
Am79C930
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MAC (80188
Restrictions — Some of the Am79C930 device 80188
core’s memory locations have predefined uses and,
P R E L I M I N A R Y
Resources
core)
Memory
therefore, are not freely available to the firmware. The
following table indicates restricted space within the
80188 core memory map of the Am79C930 device:
Restricted Space In The 80188 Core Memory Map Using Scheme RAS or RBS,
LMCS=1FF8h, UMCS=E038h, MIR0[7]=0 or 1
80188 Address
in Memory
Active 80188
Chip Select
Size of
Space
Physical Location of Memory
0 0440h–0 047Fh
LCS
64 bytes
Reserved for future use – DO NOT access these
locations
F FC00h–F FFEFh
UCS
1K–16 bytes
Flash Memory 1 FC00h–1 FFEFh
These locations are reserved for use as PCMCIA CIS or
for use as ISA Plug and Play Resource Data, depending
upon the operating mode of the device. These locations
must not be used by the 80188 firmware.
Flash Memory 1 FFF0h–1 FFFFh
F FFF0h–F FFFFh
UCS
16 bytes
These locations must be used to store the first
instructions for the 80188 firmware, since the 80188
core’s instruction pointer will point to location F FFF0h
after a Am79C930 reset. (Note that 80188 location F
FFF0h will appear as 1 FFF0h on the memory interface
bus, since only 17 address bits are available at the
memory interface bus.)
total:
1 Kbytes
MAC (80188 core) Interrupt Channel Allocation —
The TAI and BIU sections of the Am79C930 device both
generate interrupts to the 80188 core. TAI generated in-
terrupts will always appear on the INT0 input of the
80188core. BIUgeneratedinterruptswillalwaysappear
on the INT1 input of the 80188 core. Firmware should
appropriately recognize the source of each interrupt.
device to allow an interrupt to be generated to the
Am79C930 device’s internal 80188 core.
The BIU sourced interrupts are created by software ma-
nipulation, i.e., a bit in the driver software’s I/O space is
written to, and this in turn generates an interrupt to the
80188 microcontroller within the Am79C930 device.
In summary, the embedded 80188 controller can be in-
terrupted from any of several sources: driver software,
internally generated interrupt sources, and from an ex-
ternal source through the USER1/IRQ12 pin.
Interrupt Channel Allocation in the 80188 Core
80188 Interrupt Channel
Interrupt Source
INT0
INT1
TAI
BIU
MAC (80188 core) DMA Channel Allocation — The
TAIsectionoftheAm79C930devicegeneratesDMAre-
quests to the 80188 core whenever either the transmit
FIFO (TX FIFO) or the receive FIFO (RX FIFO) of the
TAI needs servicing. DRQ0 becomes asserted when-
ever the RX FIFO is NOT empty, regardless of the state
oftheRXSbitofTIR16. DRQ1becomesassertedwhen-
ever the TX FIFO isnot full, regardless of the state of the
TXS bit of TIR8. Appropriate programming of the DMA
resources of the 80188 embedded controller is required
inordertoinsureproperresponsetotheserequests. For
example, when no TX operation is desired, then the
DMA controller for DRQ1 should be disabled.
The interrupt mode used by the 80188 core should be
Master Mode Fully Nested, since no subunit of the
Am79C930 device would respond to 80188 Interrupt
Acknowledge cycles if they occurred. Note that when
using the Master Mode Fully Nested interrupt mode of
the 80188 core, no Interrupt Acknowledge cycles are
generated; instead, the interrupt vector for each inter-
rupt is generated internally. Internally generated
interrupt vectors reside in the lower portion of 80188
memory space.
TAI sourced interrupts may occur due to various condi-
tions that are signaled by TAI internal state machines.
TheTIR4andTIR5registerscontainmostofthebitsthat
signal the various state-machine generated interrupts.
The TCR11 location contains a few more interrupt
sources. One of the TCR11 interrupt sources is through
an external pin, USER1/IRQ12. This allows the user to
connect an external interrupt source to the Am79C930
Note that the use of the 80188 controller’s DMA re-
sources is not required for any given Am79C930-based
implementation, since both the RX FIFO and the TX
FIFO are directly accessible as registers. That is, it is
possible to use 80188 MOV instructions to load TX data
into the TX FIFO. The TX FIFO may be loaded by writing
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to TIR10. It is also possible to use 80188 MOV instruc-
All TIR registers.
tions to unload RX data from the RX FIFO. The RX FIFO
may be unloaded by reading from TIR18.
All TCR registers.
All TAI state machines.
All PCMCIA registers.
All ISA PnP registers.
DMA Channel Allocation In The 80188 Core
80188 DMA Channel
DRQ0
DMA Request Source
TAI RX FIFO NOT EMPTY
TAI TX FIFO NOT FULL
DRQ1
The ISA PnP state machine is returned to its
idle state.
Loopback Operation
The 80188 controller is held in RESET as long as the
RESET pin is held asserted.
The Am79C930 device contains a loopback mode that
is invoked by writing a 1 to the LOOPB bit of TCR3[7].
The sleep state machine is returned to its idle state
(i.e., awake).
When LOOPB is set to a 1, then the Am79C930 device
will perform an internal loopback of all transmissions.
The data path transmitted will move out of the TX FIFO
and be serialized.
The memory bus arbitration state machine is re-
turned to its idle state.
Use of shared resources can be controlled by the order
of writing to the TXS and RXS bits of TIR8 and TIR16,
respectively. The bit (of TXS and RXS) that is set last
will determine the owner of the SFD detection logic
shared resource.
The BIU will be reset to an inactive state, such that all
tri-stateable outputs will be put into a high-impedance
state. The internal slave state machine will revert to the
idle state; any slave operation that was in progress at
the time of the RESET operation will be abruptly discon-
tinued. The BIU will recognize a new slave access from
the host beginning four CLKIN clocks of the deassertion
of the RESET pin.
LED Support
Two pins are provided with the necessary drive capabil-
ity to directly drive a standard indicator LED. The output
value for these pins is directly programmable through
TIR register bits that are accessible to both the 80188
embedded core through the memory interface and to
the driver software through the system interface. These
two pins are also programmable as inputs so that alter-
native functionality may be defined for these pins.
The embedded 80188 controller will be reset by the as-
sertion of the RESET pin, provided that the minimum
pulse width requirement for the RESET signal is met.
Any TX or RX operation that was in progress at the TAI
at the time of the RESET assertion will be discontinued
abruptly. All RX and TX FIFO data will remain in the
FIFOs. RX and TX FIFOs can only be cleared by asser-
tion of the RXFR and TXFR bits of TIR16 and TIR8. TAI
Unit will not resume TX and RX operations until the
80188 core instructs it to do so.
RESET Methods
There are multiple reset conditions that can be
applied to the Am79C930 device. Each of the reset con-
ditions and its effect on the device are indicated in the
following sections.
SWRESET (SIR0[7])
RESET Pin
The SWRESET bit of SIR0[7] can be used to reset the
system interface section of the Am79C930 device.
When the SWRESET bit is asserted, then the BIU sec-
tion of the Am79C930 device will be reset, including the
arbitration state machine that translates 80188 cycles
into memory bus cycles.
There is a single RESET input to the Am79C930 device.
When the RESET pin is asserted for the specified mini-
mum time and then the RESET pin is deasserted, gen-
erally speaking, all major state machines in the
Am79C930 device and all registers in the Am79C930
device are reset to their default values, with the excep-
tions noted below.
The following registers and state machines are RESET
to their default values by assertion of the SWRESET bit
of SIR0[7]:
The following registers and state machines are RESET
to their default values by assertion of the RESET pin:
(Note that some register locations’ default values
are UNDEFINED):
(Note that some register locations’ default values
are UNDEFINED):
All SIR registers, except SIR0[7] and all of SIR2[7:0]
and SIR3[6:0] which are unaffected.
All SIR registers, except SIR2[7:0] and
SIR3[6:0], which are unaffected.
All MIR registers.
All MIR registers.
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The sleep state machine is returned to its idle state
(i.e., awake).
standalone 80188 controller having its RESET pin as-
serted. TAIsectionoftheAm79C930devicewillalsobe-
come reset with all registers returning to their default
states, as will a few bits in the MIR register set.
The memory bus arbitration state machine is re-
turned to its idle state.
Thefollowingisacompletelistofregistersandstatema-
chines that will become reset to default values with the
assertion of the CORESET bit of SIR0[6]:
The following registers and state machines which are
UNAFFECTED by assertion of the SWRESET bit
of SIR0[7]:
(Note that some register locations’ default values
are UNDEFINED):
SIR0[7] and all of SIR2[7:0] and SIR3[6:0] are unaf-
fected by SWRESET.
All TIR registers.
TIR registers are unaffected by SWRESET.
TCR registers are unaffected by SWRESET.
TAI state machines are unaffected by SWRESET.
The 80188 controller is unaffected by SWRESET.
PCMCIA registers are unaffected by SWRESET.
ISA PnP registers are unaffected by SWRESET.
All TCR registers.
MIR8[1:0] are reset to 11b.
MIR9[5:4] are reset to 11b.
All TAI state machines are reset by the assertion
of CORESET.
The 80188 controller is held in RESET as long as the
CORESET bit is held at a 1 level.
The ISA PnP state machine is unaffected
by SWRESET.
The following registers and state machines are
UNAFFECTED by assertion of the CORESET bit
of SIR0[6]:
It is generally recommended that the SWRESET bit of
SIR0[7] should NOT be SET to a 1 unless the
CORESET bit of SIR0[6] has first been set to a 1. This
recommendation is to insure that the memory bus arbi-
tration state machine is not reset while the 80188 em-
bedded controller is executing an access. The proper
sequence for using the SWRESET bit should be:
The ISA PnP state machine is unaffected
by CORESET.
The sleep state machine is unaffected
by CORESET.
1. SET the CORESET bit SIR0[6] to a 1.
2. SET the SWRESET bit SIR0[7] to a 1.
3. RESET the SWRESET bit SIR0[7] to a 0.
4. RESET the CORESET bit SIR0[6] to a 0.
The memory bus arbitration state machine is unaf-
fected by CORESET.
PCMCIA COR SRESET
The PCMCIA Configuration Option Register contains a
reset bit in location [7] which is labeled SRESET. When
SRESET is asserted, the entire Am79C930 device will
become reset as though the RESET pin had been as-
serted, except that the asynchronous logic which is
used to perform PCMCIA register accesses isnot reset.
An option to this procedure is to first insure that the
80188 controller is in the HALT state before the
SWRESET bit is asserted. However, note that the
FLASHWAIT and SRAMWAIT values are reset by
SWRESET; therefore, if 80188 operations are resumed
after the SWRESET has been performed, the perform-
ance of the 80188 may be affected.
Thefollowingisacompletelistofregistersandstatema-
chines that will become reset to default values with the
assertion of the COR SRESET bit of PCMCIA COR[7]:
(Note that some register locations’ default values
are UNDEFINED):
The user may decide not to follow these recommenda-
tions, but in such a case, it should be recognized that
the 80188 may suffer from unpredictable behavior as
a result.
All PCMCIA registers, except COR[7].
All MIR registers.
CORESET (SIR0[6])
The CORESET bit of SIR0[6] can be used to reset the
embedded controller and TAI sections of the
Am79C930 device, along with a few locations in the MIR
register space. When the CORESET bit is asserted,
then the 80188 section of the Am79C930 device will be
placed into reset, with behavior identical to that of a
All SIR registers, except SIR0[7], SIR2[7:0],
and SIR3[6:0].
The memory bus arbitration state machine is re-
turned to its idle state.
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The sleep state machine is returned to its idle state SRES (TIR0[5])
(i.e., awake).
The SRES bit of TIR0[5] can be used to reset the TAI
section of the Am79C930 device. When the SRES bit is
asserted, then the TAI section of the Am79C930 will
be reset.
The following registers and state machines are
UNAFFECTED by assertion of the PCMCIA COR
SRESET bit of COR[7]:
The following registers and state machines are RESET
to their default values by assertion of the SRES bit
of TIR0[5]:
All TIR registers are unaffected by COR SRESET.
All TCR registers are unaffected by COR SRESET.
(Note that some register locations’ default values
are UNDEFINED)
All TAI state machines are unaffected by
COR SRESET.
All TIR registers, except TIR0[7:0] which
is unaffected.
The 80188 controller is unaffected by
COR SRESET.
All TCR registers are reset to default values
by SRES.
It is generally recommended that the SRESET bit of
COR[7] should not be SET to a 1 unless the CORESET
bit of SIR0[6] has first been set to a 1. This recommen-
dation is to insure that the memory bus arbitration state
machine is not reset while the 80188 embedded control-
ler is executing an access. The proper sequence for us-
ing the COR SRESET bit should be:
All TAI state machines are reset to idle states
by SRES.
The following registers and state machines are
UNAFFECTED by assertion of the SRES bit of TIR[5]:
1. SET the CORESET bit SIR0[6] to a 1.
The sleep state machine is unaffected by SRES.
2. SET the COR SRESET bit PCMCIA COR[7] to
a 1.
The memory bus arbitration state machine is unaf-
fected by SRES.
3. RESET the COR SRESET bit PCMCIA COR[7]
to a 0.
All SIR registers are unaffected by SRES.
All MIR registers are unaffected by SRES.
The 80188 controller is unaffected by SRES.
PCMCIA registers are unaffected by SRES.
ISA PnP registers are unaffected by SRES.
The ISA PnP state machine is unaffected by SRES.
4. RESET the CORESET bit SIR0[6] to a 0.
An option to this procedure is to first insure that the
80188 controller is in the HALT state before the COR
SRESET bit is asserted. Note however, that the
FLASHWAIT and SRAMWAIT values are reset by
COR SRESET; therefore, if 80188 operations are re-
sumed after the COR SRESET has been performed, the
performance of the 80188 may be affected.
REGISTER DESCRIPTIONS
The Am79C930 device has five distinct areas of register
storage: System Interface Register (SIR), MAC Inter-
face Register (MIR), Transceiver Attachment Interface
Unit Register (TIR), Transceiver Attachment Interface
Uniit Configuration Register (TCR), and the PCMCIA (or
ISA Plug and Play) register sets.
The user may decide not to follow these recommenda-
tions, but in such a case, it should be recognized that
the 80188 may suffer from unpredictable behavior as
a result.
ISA PnP RESET
The ISA PnP Configuration Control Register may be
used to reset the Am79C930 device. Writing the value
“111b” to bits two through zero of this register (i.e., bits
[2:0]) will cause an internal RESET pulse to occur within
theAm79C930device). TheRESETpulsewilllastfor14
CLKIN periods.
The SIR space contains eight registers which are used
by the host driver to control Am79C930 device opera-
tions and to collect status, namely, the General Configu-
ration Register and the Bank Switching Select Register.
The Local Memory Address and Local Memory Data
registers may be used instead of system-memory-
mapped transfers to SRAM and Flash locations in order
to eliminate the need for system memory space alloca-
tion. These registers are only accessible at the system
interface; they are inaccessible from the 80188 core.
This RESET will have the same effect as asserting the
RESET pin of the Am79C930 device, except that, as
stated above, the ISA PnP RESET is limited to a dura-
tion of 14 CLKIN periods.
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The MIR space contains 16 registers which are used by
the firmware to control allow communication between
the firmware (MAC layer) and the device driver. This
register set also contains the power down registers.
These registers are only accessible through the 80188
core; they are inaccessible from the system interface.
Note that all register locations are defined to be 8 bits
in width.
Some register bits indicate the value “pin” for their de-
fault reset value. Such register bits have a pin as an op-
tional data source and such pins are by default defined
as inputs; hence, the register bit value of “pin” indicates
that the default register bit value depends upon the
value of a pin and is therefore system dependent.
The TIR space contains 32 registers which are used by
the 80188 core to control the Am79C930 device’s TAI
unit, to collect TAI status, and to transfer data to and
from the TAI. These registers are accessible from both
the system interface and the 80188 core.
Some register bits indicate the value “–” for their default
resetvalue. Suchregisterbitshaveanundefineddefault
value, even though repeated read accesses may yield a
consistent result for some bit locations thus marked.
AMD reserves the right to modify the behavior of these
bits at any time in the future (such as in a revision of this
device) and, therefore, all values read from these loca-
tions should be regarded as unknown until such time as
a use has been assigned to them. Note also that all such
bits have a write value that must be used when write
accesses to other bit locations in the register occur. This
write value is usually 0. Users must strictly obey
prescribed write values to avoid future software
incompatibility problems.
The TCR space contains 32 registers which are used by
the 80188 core to define the functionality of the
Am79C930 device’s TAI unit. These registers are indi-
rectly accessible from both the system interface and the
80188 core through an address and data port that are
part of the TIR set of registers.
The PCMCIA register set consists of two Card Configu-
ration Registers (CCR) and the Configuration Informa-
tion Space (CIS). Full support of the PCMCIA standard
(version 2.1) is facilitated through these registers. The
CCR space is only accessible through the system inter-
face. The CIS space is accessible from both the system
interface and from the 80188 core, although the 80188
core should never need to access the CIS.
System Interface Registers (SIR space)
The SIR space contains eight registers which are used
by the host driver to control Am79C930 device opera-
tions and to collect status, namely, the General Configu-
ration Register and the Bank Switching Select Register.
The Local Memory Address and Local Memory Data
registers may be used instead of system-memory-
mapped transfers to SRAM locations in order to elimi-
nate the need for system memory space allocation.
These registers are only accessible at the system inter-
face; they are inaccessible from the 80188 core.
The ISA Plug and Play register set consists of three ba-
sic registers which allow an indirect access to an addi-
tional 19 Plug and Play configuration registers plus a
double indirect access to 1K–16 bytes of Plug and Play
Resource Data space. The Plug and Play register space
is only accessible through the system interface, except
that the Resource Data space is also mapped into a por-
tion of the 80188 core memory space.
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SIR0: General Configuration Register (GCR)
This register is used to control general functions related
to the Am79C930, particularly interrupts to and from the
80188 core and power down functions.
Bit
Name
Reset Value
Description
7
SWRESET
0
Software Reset. When SWRESET is set to a 1, the BIU will be
RESET, with the exception of the SWRESET bit and the software
reset bit in the PCMCIA Card Configuration Register. The 80188
embedded controller will not be reset. TAI will not be reset.
SWRESET is unaffected by the RESET bit of the PCMCIA Configu-
ration Option Register.
6
CORESET
0
Core Reset. When CORESET is set to a 1, the 80188 embedded
controller and the TAI are held in RESET. In addition, the
FLASHWAIT and SRAMWAIT fields of MIR8 and MIR9 are set to
their default states of “11b” The reset to the 80188 core and the TAI
remains active as long as CORESET has the value 1. During the
reset time, the Am79C930 memory interface bus is directly acces-
sible through the system interface.
5
4
DISPWDN
ECWAIT
0
0
Disable Power Down Mode. When DISPWDN is set to a 1, the
Am79C930 device will be prevented from entering the power down
mode. If the Am79C930 device is already in the power down mode
when DISPWDN notes a transition from 0 to 1, then the power down
mode will be exited within three CLKIN periods.
Embedded Controller WAIT Mode. When ECWAIT is set to 1, the
RDY input to the 80188 core will be held deasserted forcing the
80188 core into a WAIT state. At the same time, the system inter-
face side of the BIU will be placed into direct access mode, such
that system interface access cycles will have direct access to the
Am79C930 memory interface. When ECWAIT is reset to a 0, the
RDY line to the 80188 core will be reasserted, the 80188 core
will resume operation and system interface direct access mode will
cease. ECWAIT also functions to determine the source of
interrupts to the system (through the system interface interrupt
pin(s)) as follows:
ECWAIT
(SIR0[4])
Source of Interrupts
Sent To System
0
MIR0[2] (note that this bit
is set by 80188 firmware)
1
TAI interrupt
3
ECINT
0
Embedded Controller Interrupt. ECINT indicates that an interrupt
for the system has been generated by either the 80188 core or the
TAI. Only one interrupt source is operable at one time. The oper-
able interrupt source is determined by the setting of the 80188
WAIT mode bit (SIR0[4]). This bit will stay set until the driver soft-
ware clears the interrupt by writing a 1 to this bit.
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2
1
INT2EC
0
0
Interrupt to Embedded Controller. When INT2EC is set to a 1, an
interrupt is sent to the 80188 core. INT2EC will stay set at 1 until the
80188 core clears this bit by writing a 1 to bit 3 of the MIR0 register.
Writing a 0 to INT2EC will have no effect on the value of INT2EC.
ENECINT
Enable Embedded Controller Interrupts. When set to 1, enables
80188 core-generated interrupts to be passed to the BIU, where
they will appear as interrupts on the ECINT bit of SIR0 and also on
the system interface interrupt pin. When set to 0, no 80188 core-
generated interrupts will be passed to the BIU.
0
DAM
0
Direct Access Mode. DAM is a read-only bit that indicates that the
80188 embedded controller has set the SIDA bit of MIR0 (bit 7),
thereby giving the system interface direct accessibility to the mem-
ory interface of the Am79C930 device. The 80188 embedded con-
troller should only give such access to the system interface when
the 80188 follows such action with a HALT instruction, otherwise
80188 accesses to the memory interface may interfere with the di-
rect access given to the system interface. This mode can be re-
leased if the system interface interrupts the 80188. An 80188
interrupt will cause the 80188 to exit the HALT state and will allow
the 80188 to reset the SIDA bit to 0. The value of the DAM bit is the
same as the value of the SIDA bit of MIR0 (bit 7).
SIR1: Bank Switching Select Register (BSS)
This register contains Bank Select bits for various
Am79C930 resources and other control bits.
Bit
Name
Reset Value
Description
7
ECATR
0
Embedded Controller ALE Test Read. Contains latched ALE value
from the 80188 core. Writing a 0 will clear this bit. Whenever the
80188 core ALE signal becomes active (1), then this bit will become
1 and will stay 1 until either it is written as a 0 or a reset occurs.
6
5
Reserved
FS
–
0
Read only as a 0.
Flash Select. When FS is set to 1, common memory accesses
across the host bus will be made to the Flash memory, not SRAM.
When FS is reset to 0, the host accesses are directed to the SRAM.
4:3
2
MBS
00
0
Memory Bank Select. These two bits act as Am79C930 memory in-
terface bus address bits MA[16:15] during system interface ac-
cesses to Flash and SRAM.
EIOW
Expand I/O Window. When EIOW is reset to 0, the TAI can only be
accessed through system interface addresses I/O offsets 0008h
through 000Fh and the TAI Bank Select bits must be used to access
the full set of TIR registers. When EIOW is set to 1, the TAI address
space is mapped to system interface addresses I/O offsets 0008h
through 0027h.
EIOW is always 0 when the Am79C930 device has been set to the
ISA Plug and Play mode of operation. EIOW is not writeable when
the Am79C930 device has been set to the ISA Plug and Play mode
of operation.
1:0
TBS
00
TAI Bank Select. When the EIOW bit is set to 0, then the TBS bits
will act as Am79C930 memory interface bus address bits MA[4:3]
during system interface accesses to the TIR registers.
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SIR2: Local Memory Address Register [7:0] (LMA)
This register is the beginning address on the local bus
for system interface I/O transfers that are made to the
I/O Data Port. This register automatically increments by
“1” following each read or write operation of any section
of the I/O Data Port. (MA[16:15] will be given the values
of BSS[4:3] – memory bank select bits.)
Bit
Name
Reset Value
Description
7:0
LMA[7:0]
–
These 8 bits act as Am79C930 memory interface bus address bits
MA[7:0] during system interface accesses to Flash and SRAM
whenever any section of the I/O Data port is read or written. The
LMA[14:0] value is automatically incremented by R1S after any
section of the I/O Data Port is read or written.
Note that these bits are unaffected by any RESET operation.
SIR3: Local Memory Address Register [14:8] (LMA)
This register is the beginning address on the local bus
for system interface I/O transfers that are made to the
I/O Data Port. This register automatically increments by
“1” following each read or write operation of any of the
I/O Data Ports in which the LMA [7:0] register produces
a carry out from bit LMA[7].
Bit
Name
Reset Value
Description
7
ISAPWRDWN
0
Requests the 80188 to enter power down mode if the device is op-
erating in the ISA Plug and Play mode. If already in power down
mode, this bit will indicate 1. If written with a 0 while in power down
mode, power down mode is exited. When written with a 1, value
read will remain 0 until the device actually enters the power down
mode. When written with a 1, the PWRDWN bit generates an inter-
rupt to the 80188, requesting that the 80188 core place the
Am79C930 device into the power down state. The interrupt is sig-
naled in MIR0, bit 5. The PWRDWN bit of SIR3 is identical in func-
tion to the PCMCIA Card Configuration and Status Register’s
Power Down bit, but this bit is only functional when the ISA Plug and
Play mode has been selected. This bit is reserved and should be
written as 0 when the PCMCIA mode of operation has been
selected. Reads of this bit produce undefined data when in
PCMCIA mode.
6:0
LMA[14:8]
–
These seven bits act as Am79C930 memory interface bus address
bits MA[14:8] during system interface accesses to Flash and SRAM
whenever any section of the I/O Data port is read or written. The
LMA[14:0] value is automatically incremented by “1” after any of the
I/O Data Ports is read or written. (Note that MA[16:15] will be given
the values of SIR1[4:3] – memory bank select bits.)
Note that these bits are unaffected by any RESET operation.
SIR4: I/O Data Port A (IODPA)
This register directly accesses the Am79C930 memory
interface data bus at the memory interface bus address
specified by the current value of the LMA registers and
the SIR1[5:3] bits. Each read or write operation of any of
the I/O Data Ports causes an increment of “1” to the LSB
of the LMA. All four I/O Data Ports will use the same
LMA and SIR1[5:3] values. That is, each I/O Data Port is
equivalent to the others, except for their location in sys-
tem I/O space. Different I/O Data Ports do not imply a
built in offset of LMA values.
Bit
Name
Reset Value
Description
7:0
IODPA[7:0]
–
These eight bits act as Am79C930 memory interface bus data bits
MD[7:0] during system interface accesses to Flash and SRAM
whenever any section of the I/O Data port is read or written.
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SIR5: I/O Data Port B (IODPB)
This register is a system interface I/O address alias of
I/O Data Port A.
Bit
Name
Reset Value
Description
7:0
IODPB[7:0]
–
Aliased to I/O Data Port A.
SIR6: I/O Data Port C (IODPC)
This register is a system interface I/O address alias of
I/O Data Port A.
Bit
Name
Reset Value
Description
7:0
IODPC[7:0]
–
Aliased to I/O Data Port A.
SIR7: I/O Data Port D (IODPD)
This register is a system interface I/O address alias of
I/O Data Port A.
Bit
Name
Reset Value
Description
7:0
IODPD[7:0]
–
Aliased to I/O Data Port A.
MAC Interface Registers (MIR Space)
The MAC Interface Unit Register (MIR) space contains
16 registers which are used by the firmware to allow
communication between the firmware (MAC layer) and
the device driver. This register set also contains the
power down registers. These registers are only accessi-
ble through the 80188 core; they are inaccessible from
the system interface.
MIR0: Processor Interface Register (PIR)
This register is used to communicate to and from the
driver at the system interface.
Bit
Name
Reset Value
Description
7
SIDA
0
System Interface Direct Access. When SIDA is set to 1, then the
system interface side of the BIU is in direct memory access mode,
such that system interface access cycles will have direct access to
the Am79C930 memory interface. This mode should only be in-
voked if the 80188 will be placed into HALT mode by an appropriate
instruction within the 80188 firmware during the time that SIDA is
set to 1. When SIDA is reset to 0, then system interface accesses to
the Am79C930 memory interface will be translated by the internal
BIU arbitration state machine.
6
5
ECMRMS
SPDREQ
0
0
Embedded Controller Memory Resource Mapping Scheme. When
ECMRMS is set to 1, the top 96K of Flash memory is mapped to
80188 memory locations 8000h to 1FFFFh. All of Flash memory is
still available at the “normal” locations E0000h to FFFFFh. When
ECMRMS is reset to 0, Flash memory is mapped only to locations
E0000h to FFFFFh.
System Power Down Request. SPDREQ will indicate a 1 when the
device driver writes a 1 to the PCMCIA Power Down Request bit in
the PCMCIA Card Configuration and Status Register or when the
device driver writes a 1 to the SIR3 ISAPWRDWN bit. When
SPDREQ is a 1, an interrupt to the 80188 will be generated.
SPDREQ will become cleared when the 80188 core writes a 1
to SPDREQ.
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4
3
PDC
0
0
Power Down Command. When PDC is set to 1, the power down cy-
cle of the BIU power down state machine will begin. PDC will auto-
matically clear itself after completion of the power down operation.
SYSINT
System Interrupt. SYSINT Indicates a 1 after the system issues an
interrupt command to the 80188 core by writing to the INT2EC bit of
the GCR register (SIR0). SYSINT will become cleared to a 0 when
the 80188 core writes a 1 to SYSINT.
2
INT2SYS
0
Interrupt To System. When INT2SYS is set to a 1, an interrupt is
generated to the system, provided that the ECWAIT bit (SIR0[4]0 is
set to 0. INT2SYS will stay set at 1 until the system clears it by
writing a 1 to ECINT (bit 3 of SIR0). Writing a 0 to INT2SYS will have
no effect.
1
0
SYSINTM
PWDNDN
0
0
System Interrupt Mask. When SYSINTM is set to a 1, system-gen-
erated interrupts (through the SYSINT bit of MIR0) are allowed to
be passed to the 80188. When SYSINTM is reset to 0, no
system-generated interrupts will be passed to the 80188.
Power Down Done. When Power Down mode is completed, then
PWDNDN will automatically become set to 1 and an interrupt to the
80188 core will be generated. The 80188 core may clear the
PWDNDN bit by first writing a 1 to PWDNDN and then writing a 0 to
PWDNDN. Note that PWDNDN will read as a 0, after writing a 1 to
PWDNDN, but a 0 must still be written to PWDNDN in order to com-
plete the reset operation. If a 0 is not written to PWDNDN, then the
PWDNDN will be permanently held in reset.
MIR1: Power Up Clock Time [3:0] (PUCT)
This register is used to determine the length of time that
will be used to allow the CLKIN buffer circuit to power up
and stabilize before the end of the power down cycle.
The length of the power up phase will be the value of the
PUCT times 0.5 msec.
Bit
Name
Reset Value
Description
7:4
PUCT[3:0]
0000b
Length of the power up stabilization time for the CLKIN buffer cir-
cuitry. The resolution of the power up clock timer is in increments of
16x (Period of PMX). The nominal PMX1/2 crystal value is
32.768 kHz, resulting in a resolution of 16 x 31.25 µs = 500 µs.
3:0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
MIR2: Power Down Length Count [7:0] (PDLC)
This register is used to determine the length of power
down cycles. Before execution of the power down se-
quence, the 80188 core must load the PDLC counter.
Upon execution of the power down sequence, the PDLC
value will be counted down to zero and the power down
cycle will end.
Bit
Name
Reset Value
Description
0
PDLC[7:0]
00h
Lower 8 bits of the length of the power down cycle counter. The
resolution of the power down length counter is in increments of
PMX1/2 periods. The nominal PMX1/2 crystal Value is 32.768 kHz,
resulting in a resolution of 31.25 µs.
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MIR3: Power Down Length Count [15:8] (PDLC)
This register is used to determine the length of power
down cycles. Before execution of the power down se-
quence, the 80188 core must load the PDLC counter.
Upon execution of the power down sequence, the PDLC
value will be counted down to zero and the power down
cycle will end.
Bit
Name
Reset Value
Description
0
PDLC[15:8]
00h
Middle 8 bits of the length of the power down counter. The resolu-
tion of the power down length counter is in increments of PMX1/2
periods. The nominal PMX1/2 crystal value is 32.768 kHz, resulting
in a resolution of 31.25 µs.
MIR4: Power Down Length Count [22:16] (PDLC)
This register is used to determine the length of power
down cycles. Before execution of the power down se-
quence, the 80188 core must load the PDLC counter.
Upon execution of the power down sequence, the PDLC
value will be counted down to zero and the power down
cycle will end.
Bit
Name
Reset Value
Description
7
PERMAREST
0
When set to a 1, this bit prevents the normal termination of the
power down sequence, such that the PDLC and PUCT counts are
ignored, and the power down mode is only exited when the
PCMCIA PWRDWN bit is written with a 0, or when the SIR0
DISPWDN bit is written with a 1.
6:0
PDLC[22:16]
00h
Upper 7 bits of the length of the power down counter. The resolution
of the power down length counter is in increments of PMX1/2 peri-
ods. The nominal PMX1/2 crystal value is 32.768 kHz, resulting in a
resolution of 31.25 µs.
MIR5: Free Count [7:0] (FCNT)
This register is a read-only register. Do not write to this
register or unexpected consequences will result.
that uses the PMX1/2 clock as its basis. The free run-
ning count is reset only when the reset pin is asserted.
Timer resolution is 31.25 µs when PMX1/2 has a fre-
quency of 32.768 kHz.
Thisregistergivesthevalueofthelowestbyteofthefree
running count. The free running count is a 24-bit counter
Bit
Name
Reset Value
Description
Least significant byte of the free running count.
7:0
FCNT[7:0]
00h
MIR6: Free Count [15:8] (FCNT)
Thisregistergivesthevalueofthelowestbyteofthefree
running count. The free running count is a 24-bit counter
that uses the 32 kHz clock as its basis. The free running
count is reset only when the reset pin is asserted. Timer
resolution is 31.25 µs when PMX1/2 has a frequency of
32.768 kHz.
Bit
Name
Reset Value
Description
7:0
FCNT[15:8]
00h
Middle byte of the free running count.
MIR7: Free Count [23:16] (FCNT)
Thisregistergivesthevalueofthelowestbyteofthefree
running count. The free running count is a 24-bit counter
that uses the 32 kHz clock as its basis. The free running
count is reset only when the reset pin is asserted. Timer
resolution is 31.25 µs when PMX1/2 has a frequency of
32.768 kHz.
Bit
Name
Reset Value
Description
7:0
FCNT[23:16]
00h
Most significant byte of the free running count.
82
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Description
MIR8: Flash Wait States
This register gives the Flash Wait states.
Bit
Name
Reset Value
7:4
3
Reserved
HOSTALLOW
Reserved
–
1
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
When this bit equals 1, then the host can access memory; if 0, then
the host access is blocked completely
2
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
1:0
FLASHWAIT[1:0]
11b
These bits must be set equal to or greater than the number of wait
states that are generated internally in the 80188 core as defined by
the programming of the R1 and R0 bits of the 80188 UMCS register.
Wait states programmed into FLASHWAIT will cause wait states to
be inserted into 80188 access to Flash and system accesses to
Flash. Each wait state added to a Flash access is equivalent to two
CLKIN periods. These bits are interpreted as follows:
Number Of Wait
States Used By
Arbitration Logic For
FLASHWAIT[1:0]
Flash Accesses
11
10
01
00
3
2
1
0
MIR9: TCR Mask STSCHG Data
This register contains TCR Mask, STSCHG Data, and
SRAM Wait States.
Bit
Name
Reset Value
Description
7
CLKGT20
1
CLKIN input is greater than 20 MHz. This bit must be set to a 1 by
the 80188 code whenever the Am79C930 device is operating in a
system that uses a source for the CLKIN input that is greater than
20 MHz in frequency. This information is needed in order to insure
that the TAI section of the Am79C930 device is not pushed beyond
design limits. Specifically, when CLKGT20 is set to 1, then the
CLKIN signal is divided by 2 before being fed to the TAI section.
CLKGT20 is also used to calibrate the time delay generated by the
HOSTLONGWAIT counter. Specifically, if CLKGT20 = 1, then the
number of CLKIN cycles that are counted for a system access
WAIT period is 192 CLKIN periods; if CLKGT20 = 0, then the num-
ber of CLKIN cycles that are counted for a system access WAIT pe-
riod is 96 CLKIN periods. This time adjustment is needed in order to
avoid creating a PCMCIA WAIT signal that exceeds the 12.1 µs
limit indicated in the PCMCIA specification.
If the source for the CLKIN input is a 20 MHz or slower clock signal,
then this bit should remain reset at 0.
The CLKGT20 bit has an effect on the network data rate. See the
table in the Data Rate bit section in TCR30[2:0].
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6
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
5:4
SRAMWAIT[1:0]
11b
These bits must be set equal to or greater than the number of wait
states that are generated internally in the 80188 core as defined by
the programming of the R1 and R0 bits of the 80188 LMCS register.
Wait states programmed into SRAMWAIT will cause wait states to
be inserted into 80188 access to SRAM and system accesses to
SRAM. Each wait state added to an SRAM access is equivalent to
two CLKIN periods. These bits are interpreted as follows.
Number Of Wait
States Used By
Arbitration Logic For
SRAMWAIT[1:0]
SRAM
11
10
01
00
3
2
1
0
3
HOSTLONGWAIT
0
When HOSTLONGWAIT is set to a 1, 96, or 192 CLKIN periods
(depending upon the setting of the CLKGT20 bit of MIR9) of
READY DELAY are added to all system access cycles that are di-
rected to Flash, SRAM and TAI registers. (Note that accesses to
PCMCIA registers, SIR registers and ISA PnP register are unaf-
fected.) This delay is nominally 4.8 µs when CLKIN = 20 MHz and
CLKGT20 is set to 0, and nominally 4.8 µs when CLKIN = 40 MHz
and CLKGT20 is set to 1.
When HOSTLONGWAIT is set to a 0, all host (system) access cy-
cles will be delayed according to their position in the arbitration
queue, where the only other master competing is the 80188 core
and the requesting device has priority over the current master (i.e.,
worst case READY delay with HOSTLONGWAIT set to 0 is equal to
1 access performed by other master plus the number of wait states
for the device being accessed.)
System write accesses will be posted and, therefore, may not im-
mediatelyexperiencethe“longwait”delay. However, thepostedac-
cess must internally wait for the “longwait“ before becoming
completedandthiswillcauseasubsequentsystemaccesstoexpe-
rience the full 4.8 µs wait time plus an additional 4.8 µs wait time for
a total of 9.6 µs. Note, however, that the average wait time per host
cycle in this case will still be 4.8 µs.
2
1
0
INITDN
0
0
0
Initialization Done. When set to a 0, this bit enables the pull up and
pull down devices that are attached to the various multi-function
pins. When set to a 1, the pull up and pull down devices are
disabled, reducing standby current consumption to the minimum
possible level.
TCR Mask
STSCHGD
TCR Mask. When set to a 1, writes to TCR13, TCR14, and TCR15
are ignored. This bit is provided as a security measure against acci-
dental reprogramming of network interface pin function by poorly
directed system accesses which could cause output-to-output con-
nections to become established.
STSCHG Data. If the STSCHGFN bit of TCR15 has been set to a 1,
and the WAKEUP bit of the PCMCIA CCSR is set to a 1, then this bit
may be written with a 1 and writing a 0 to this bit has no effect. If the
STSCHGFN bit of TCR15 has been set to a 1, then STSCHGD is
reset to a 0 automatically whenever the WAKEUP bit of the
84
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PCMCIA CCSR is RESET to a 0. If the STSCHGFN bit of TCR15
has been set to a 0, then the value that is written to this bit will be
inverted and driven to the STSTCHG pin of the Am79C930 device.
The value that is read from this bit always represents the inverse of
the current value of the STSTCHG pin of the Am79C930 device.
THIS FUNCTION IS ONLY AVAILABLE IN PCMCIA MODE.
The complete control of the function of the STSCHG/BALE pin is
described in the Multi-Function Pin section.
MIR10: Reserved
This register is reserved.
Bit
Name
Reset Value
Description
7:0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
MIR11: Reserved
This register is reserved.
Bit
Name
Reset Value
Description
7:0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
MIR12: Reserved
This register is reserved.
Bit
Name
Reset Value
Description
7:0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
MIR13: Reserved
This register is reserved.
Bit
Name
Reset Value
Description
7:0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
MIR14: Reserved
This register is reserved.
7:0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
MIR15: Reserved
This register is reserved.
Bit
Name
Reset Value
Description
7:0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
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The set of 64 TAI registers is intended primarily for use
Transceiver Attachment Interface
Registers (TIR Space)
by the 80188 firmware. However, access through the
system interface bus to the TAI register set is provided
to allow for direct access by driver code for diagnostic
and other purposes.
The Transceiver Attachment Interface (TAI) Unit con-
tains a total of 64 registers. Thirty-two of the registers
are directly accessible from the 80188 embedded core
and from the system interface through the BIU. The
other 32 registers are indirectly accessed by first writing
an INDEX value into the TCR Index Register (TIR24)
and then executing a read or write operation to the TCR
Data Port (TIR25). Since the indirectly accessible regis-
ters are used mostly for TAI configuration purposes, this
set of registers is labeled TAI Configuration Registers
(TCR). The following section describes the directly ac-
cessible registers of the TAI, or TIR.
The exact location of the TIR register set as viewed from
the system interface will depend upon the choice of
mapping scheme as indicated by the Expand I/O Win-
dow bit (bit 2 of the BSS register (SIR1)). The following
tables give the address for each of the directly accessi-
ble TIRs for each of the system interface modes for each
of the two mapping schemes, as well as the address for
each register as it appears in the memory map of the
80188 embedded core.
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TIR mapping with SIR1 bit 2 (EIOW) set to “0” = normal
TIR window mode. Note that EIOW = 0 is the only setting
of EIOW that is allowed while operating in ISA PnP
mode. TIR uses eight I/O addresses:
TIR
Register
Number
SIR1[1:0]
(TAI Bank
Select)
ISA Plug
and Play
I/O Address
80188 Core
Address in
Memory
PCMCIA
I/O Address
TIR Register Name
Network Control
0
00
00
00
00
00
00
00
00
01
01
01
01
01
01
01
01
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
IOBA+0008h
IOBA+0009h
IOBA+000Ah
IOBA+000Bh
IOBA+000Ch
IOBA+000Dh
IOBA+000Eh
IOBA+000Fh
IOBA+0008h
IOBA+0009h
IOBA+000Ah
IOBA+000Bh
IOBA+000Ch
IOBA+000Dh
IOBA+000Eh
IOBA+000Fh
IOBA+0008h
IOBA+0009h
IOBA+000Ah
IOBA+000Bh
IOBA+000Ch
IOBA+000Dh
IOBA+000Eh
IOBA+000Fh
IOBA+0008h
IOBA+0009h
IOBA+000Ah
IOBA+000Bh
IOBA+000Ch
IOBA+000Dh
IOBA+000Eh
IOBA+000Fh
mem 400h
mem 401h
mem 402h
mem 403h
mem 404h
mem 405h
mem 406h
mem 407h
mem 408h
mem 409h
mem 40Ah
mem 40Bh
mem 40Ch
mem 40Dh
mem 40Eh
mem 40Fh
mem 410h
mem 411h
mem 412h
mem 413h
mem 414h
mem 415h
mem 416h
mem 417h
mem 418h
mem 419h
mem 41Ah
mem 41Bh
mem 41Ch
mem 41Dh
mem 41Eh
mem 41Fh
1
Network Status
2
Serial Device
3
Fast Serial Port Control
Interrupt Register 1
Interrupt Register 2
Interrupt Mask 1
4
5
6
7
Interrupt Mask 2
8
Transmit Control
9
Transmit Status
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
TX FIFO Data
Transmit Sequence Control
Byte Counter LSB
Byte Counter MSB
Byte Counter Limit LSB
Byte Counter Limit MSB
Receiver Control
Receiver Status
RX FIFO Data
Antenna Slot
CRC32 Correct Count LSB
CRC32 Correct Count MSB
CRC8 Correct Count LSB
CRC8 Correct Count MSB
Configuration Index
Configuration Data Port
Antenna Diversity & A/D
SAR
RSSI Lower Limit
USER Pin Data
Dummy Register
TEST Register
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TIR mapping with SIR1 bit 2 (EIOW) set to “1” = Ex-
panded TIR window mode. Note that the setting
EIOW = 1 is only allowed while operating in PCMCIA
mode. TIR uses 32 I/O addresses:
TIR
Register
Number
SIR1[1:0]
(TAI Bank
Select)
80188 Core
Address in
Memory
PCMCIA
I/O Address
TIR Register Name
Network Control
0
XX*
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
mem 400h
mem 401h
mem 402h
mem 403h
mem 404h
mem 405h
mem 406h
mem 407h
mem 408h
mem 409h
mem 40Ah
mem 40Bh
mem 40Ch
mem 40Dh
mem 40Eh
mem 40Fh
mem 410h
mem 411h
mem 412h
mem 413h
mem 414h
mem 415h
mem 416h
mem 417h
mem 418h
mem 419h
mem 41Ah
mem 41Bh
mem 41Ch
mem 41Dh
mem 41Eh
mem 41Fh
1
Network Status
2
Serial Device
3
Fast Serial Port Control
Interrupt Register 1
Interrupt Register 2
Interrupt Mask 1
4
5
6
7
Interrupt Mask 2
8
Transmit Control
9
Transmit Status
10
TX FIFO Data
11
Transmit Sequence Control
Byte Counter LSB
Byte Counter MSB
Byte Counter Limit LSB
Byte Counter Limit MSB
Receiver Control
12
13
14
15
16
17
Receiver Status
18
RX FIFO Data
19
Antenna Slot
20
CRC32 Correct Count LSB
CRC32 Correct Count MSB
CRC8 Correct Count LSB
CRC8 Correct Count MSB
Configuration Index
Configuration Data Port
Antenna Diversity & A/D
SAR
21
22
23
24
25
26
27
28
RSSI Lower Limit
USER Pin Data
29
30
31
Dummy Register
TEST Register
*XX = Don’t care.
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TIR0: Network Control
General control for the transceiver device attached to
the transceiver interface pins.
Bit
Name
Reset Value
Description
7
LNK
pin
Link LED. The inverse of the LNK bit value is driven onto the LNK
pin when the LNK pin has been enabled for output.
The value read from LNK will always represent the inversion of the
current value of the LNK pin. The control of the function of the LNK
pin is described in the Multi-Function Pin section.
6
ACT
pin
Activity LED. The inverse of the ACT bit value is driven onto the
ACT pin when the ACT pin has been enabled for output.
The value read from ACT will always represent the inversion of the
current value of the ACT pin. The control of the function of the ACT
pin is described in the Multi-Function Pin section.
5
4
SRES
0
0
TAI reset. Active high. Asserting this bit will reset the TAI portion of
the Am79C930 device, except for this register (i.e., TIR0).
SSTRB
Software Strobe. This bit is intended for software development use.
The value written to this bit will be sent to the test output when the
device is programmed for test mode.
3
2
Reserved
RXP
–
0
Reserved. Must be written as a 0. Reads of these bits produce
undefined data.
RX Power control. The inverse of the RXP bit value is driven onto
the RXPE pin when the RXPE pin has been enabled for output.
The value read from RXP will always represent the inverted logical
sense of the current value of the RXPE pin. The control of the func-
tion of the RXPE pin is described in the Multi-Function Pin section.
1
0
LFPE
HFPE
0
0
Low Frequency Power control. The inverse of the LFPE bit value is
driven onto the LFPE pin when the LFPE pin has been enabled
for output.
The value read from LFPE will always represent the inverted logical
sense of the current value of the LFPE pin. The control of the func-
tion of the LFPE pin is described in the Multi-Function Pin section.
High Frequency Power control. The inverse of the HFPE bit value is
driven onto the HFPE pin when the HFPE pin has been enabled
for output.
The value read from HFPE will always represent the inverted
logical sense of the current value of the HFPE pin. The control of
the function of the HFPE pin is described in the Multi-Function
Pin section.
TIR1: Network Status
The TAI Network status register is a general network
status register.
Bit
Name
Reset Value
Description
7
TSTO
0
–
Test Output. This bit is the result of the test multiplexer.
6–3
Reserved
Reserved. Must be written as a 0. Reads of these bits produce
undefined data.
2
IRQ
0
Interrupt Request. This bit represents the current value of the IRQ
output pin. When IRQ has the value 1, then an interrupt request
is active.
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1
0
RXDRQ
TXDRQ
0
1
Receive FIFO DMA Request. This bit represents the current
value of the RXDRQ signal to the DRQ0 input of the 80188
embedded core.
Transmit FIFO DMA Request. This bit represents the current
value of the TXDRQ signal to the DRQ1 input of the 80188
embedded core.
TIR2: Serial Device
TAI Serial Device register. This register is used to con-
trol the serial device interface.
Bit
Name
Reset Value
Description
7
Reserved
SDS[3:1]
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
6–4
000b
Serial Device Select. Each of these bits controls one of the Serial
Device Select outputs of the Am79C930. Bit values are inverted as
they appear at the pins. As an example, writing a 1 to the SDS[3] bit
will cause the SDSEL3 output to be driven to a 0.
The value read from SDS[x] will always represent the current value
of the SDSEL[x] pin without inversion. The control of the function of
the SDSEL[x] pins are found in the Multi-Function Pin section.
3
SDCP
0
Serial Device Clock Auto pulse generation. When set to a 1, this bit
causes the SDCLK pin to become active for the duration of the WR#
signal at the 80188 interface of the TAI whenever the internal
Am79C930 TAI chip select has been activated and the memory bus
address present is 00010b, with higher order bits of MA as DON’T
CARE (i.e., a WRITE to TIR2 is occurring). The value of the SDCLK
pin during this strobe period depends upon the setting of the SDC
bit. The SDC bit gives the “inactive” state of the SDCLK pin. If SDCP
is set to 1, then the SDCLK pin is complemented from its inactive
state while either the 80188 WR# signal is active with the TAI chip
select also active. When SDCP is set to 0, then the SDC bit has di-
rect control of the SDCLK pin.
The value of the SDC bit must not be changed when the SDCP bit is
set to a 1. To change the value of SDC, first set SDCP to a 0.
The complete control of the function of the SDCLK pin is described
in the Multi-Function Pin section.
2
SDC
0
Serial Device Clock. The SDC bit value is driven onto the SDCLK
pin when the SDCLK pin has been enabled for output.
The value of the SDC bit must not be changed when the SDCP bit is
set to a 1. To change the value of SDC, first set SDCP to a 0.
The value read from SDC will always represent the current value of
the SDCLK pin. The control of the function of the SDCLK pin is de-
scribed in the Multi-Function Pin section.
1
0
SDDT
SDD
0
0
Serial Device Data Tristate. When SDDT is set to 1, the SDDATA
pin of the Am79C930 device is tri-stated. When SDDT is set to 0,
the SDDATA pin is driven with the value of the SDD bit.
The complete control of the function of the SDDATA pin is de-
scribed in the Multi-Function Pin section.
Serial Device Data. The SDD bit value is driven onto the SDDATA
pin when the SDDATA pin has been enabled for output.
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The value read from SDD will always represent the current value of
the SDDATA pin. The complete control of the function of the
SDDATA pin is described in the Multi-Function Pin section.
When the fast serial port (TIR3) is used, then the value written to
SDD will be exclusive OR’d (XOR) with the data from the FSD bits
of TIR3 before the FSD bits are sent to the SDDATA pin.
TIR3: Fast Serial Port Control
This register provides a relatively quick write access to
the Serial Port signals of the device (i.e., SDCLK and
SDDATA). The SDSEL3-1 signals must be previously
set with an access to the Serial Port control register
(TIR2). The SDDT bit of TIR2 must be set to 0 or the fast
write will fail. A write to the TIR3 register will initiate the
fast serial transfer. A read from this register will not
cause any activity at the serial port pins. The clock for
the serial port write operation will be created from the
CLKIN signal when the CLKGT20 bit of MIR9 is set to 0
and from the CLKIN signal divided by two when the
CLKGT20 bit of MIR9 is set to 1. Timing for the fast read
operation is as follows:
tA
tA
tA
tA
tA
tA
SDCLK
2 X tA
2 X tA
2 X tA
SDDATA
tA = period of CLKIN when CLKGT20 = 0
tA = (period of CLKIN) X 2 when CLKGT20 = 1
20138B-8
Figure 3. Serial Port Fast Read Timing
Bit
Name
Reset Value
Description
7:5
BCNT[2:0]
–
Byte Count. From 1 to 5 bits of the FSD[4:0] data may be sent dur-
ing one fast access to the serial port. The value of BCNT[2:0] deter-
mines exactly how many bits will be sent for any access. The value
BCNT[2:0] = 1 represents a value of one bit to be sent.
4:0
FSD[4:0]
–
Fast Serial Data[4:0] This is the data that is sent out during the Fast
Serial port access. Bit 0 is sent first. FSD bit values are exclusive
OR’d (XOR) with the value written to the SDD bit of TIR2[0] before
being sent to the SDDATA pin.
TIR4: Interrupt Register 1
The TAI Interrupt Register 1 provides interrupt status in-
formation. Any interrupt bit may be cleared by writing a 1
to the bit location. Writing a 0 to a bit location has no ef-
fect on the bit value. When the unmask bit for any
interrupt is set to 0, then the bit in the Interrupt register
may still become set, but no interrupt to the 80188 em-
bedded controller will occur.
Bit
Name
Reset Value
Description
7
6
CHBSYC
ANTSW
0
0
CHBSY Change of state. Indicates that there is a change of state in
the CCA indication.
Antenna Switch. This bit will become set at the end of each time slot
as programmed in the Antenna Diversity Timer Register (TCR4) to
indicate that the channel tests for this antenna selection have been
completed. This bit is reset to 0 when the RXRES bit of TIR16 is set
to 1, or if a 1 is written to ANTSW.
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5
4
MOREINT
TXCNT
1
0
MORE Interrupts. MOREINT will become set whenever there are
interrupt bits set in Interrupt Register 3 (TCR11). Note that
MOREINT bit does not reflect the state of interrupt status bits from
Interrupt Register 2 (TIR5). There is an unmask bit for MOREINT,
and there are also individual unmask bits for the interrupts in Inter-
rupt Register 3 (TCR11).
TX Count reached. TXCNT becomes set to a 1 when the TX Byte
count limit of TIR14 and TIR15 has been reached as indicated by
the TIR12 and TIR13 counter. Note that reaching the byte count
limit will not cause TX operations to automatically cease. TX data
transmission ceases only when the TX FIFO has become empty.
3
2
TXDONE
CRCS
0
0
TXDONE. Indicates that the CRC has been sent for the current TX
frame. If the option for NO TX CRC has been selected, then
TXDONE will be set to a 1 when the last data bit for the frame has
been sent.
CRC Start. CRCS will be set to a 1 by the Am79C930 device when
the first bit of the CRC is being transmitted. If the NO TX CRC option
has been set, then CRCS will not become set.
1
0
SDSNT
TXFBN
0
1
Start of Frame Delimiter Sent during a TX operation.
TX FIFO Byte Needed. Indicates that the TX FIFO is not full.
TIR5: Interrupt Register
The TAI Interrupt Register 2 provides interrupt status in-
formation. Any interrupt bit may be cleared by writing a 1
to the bit location. Writing a 0 to a bit location has no ef-
fect on the bit value. When the unmask bit for any
interrupt is set to 0, then the bit in the Interrupt register
may still become set, but no interrupt to the 80188 em-
bedded controller will occur.
Bit
Name
Reset Value
Description
7
RXCNT
0
RX Count reached. RXCNT becomes set to a 1 when the RX Byte
count limit of TIR14 and TIR15 has been reached as indicated by
the TIR12 and TIR13 counter. Note that reaching the byte count
limit will not cause RX operations to automatically cease. RX
data reception ceases only when the RX FIFO is reset by the
80188 controller.
6
5
CRC8G
0
0
CRC8 Good. The CRC8 machine has detected a good CRC and
has latched the byte count that was active at the time that the CRC
was good.
CRC32G
CRC32 Good. The CRC32 machine has detected a good CRC and
has latched the byte count that was active at the time that the CRC
was good.
4
3
RXFOR
RXFBA
0
0
RX FIFO Overrun. The RX FIFO encountered an overrun condition.
RX FIFO Byte Available. The RX FIFO has at least one byte of data
available for removal. The status register for the RX FIFO indicates
the exact number of bytes in the RX FIFO.
2
1
0
SDF
BCF
1
0
0
Start Delimiter Found. The SFD has been found, indicating that the
receive state machine will now begin placing received bytes into the
RX FIFO.
Busy Channel Found. BCF is set to 1 by the Am79C930 device
when a busy channel has been found by the CCA logic. That is,
whenever CHBSY=1, which implies that the channel is busy.
ALOKI
Antenna Lock Interrupt. ALOKI becomes set when the antenna se-
lection logic has chosen an antenna based upon the programmed
antenna selection criteria.
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(Generated from the internal signal stop_d, which indicates that an-
tenna diversity operation has selected an antenna.) Assertion of
ALOKI indicates the cessation of antenna diversity activity so that
the incoming network signal can be tracked and decoded by the
DPLL. ALOKI will be set to a 1 by the Am79C930 device when the
conditions for stopping the antenna diversity switching as set up in
the Baud Detect Circuit Control Registers, TCR17, TCR18, TCR20,
TCR21, TCR22, and TCR23, and the RSSI Limit Register TIR28,
and the CCA, and Antenna Diversity Control Register TCR28, have
been met.
TIR6: Interrupt Unmask Register 1
Interrupt Unmask Register 1. Each bit in this register will
unmask the corresponding interrupt of Interrupt Regis-
ter 1 (TIR4) when the unmask bit is set to 1. When the
unmask bit for any interrupt is set to 0, then the bit in the
Interrupt register may still become set, but no interrupt
to the 80188 embedded controller will occur.
Bit
Name
Reset Value
Description
7
6
5
4
3
2
1
0
CHBSYCU
ANTSWU
MOREINTU
TXCNTUN
TXDONE
CRCSU
0
0
0
0
0
0
0
0
CHBSY Change Interrupt Unmask.
Antenna Switch Interrupt Unmask.
MOREINT Interrupt Unmask.
TX Byte Count Interrupt Unmask.
TXDONE Interrupt Unmask.
CRC Start Interrupt Unmask.
SDSNTU
TXFBNU
Start of Frame Delimiter Sent Interrupt Unmask.
TX FIFO Byte Needed Interrupt Unmask.
TIR7: Interrupt Unmask Register 2
Interrupt Unmask Register 2.
bit is set to 1. When the unmask bit for any interrupt is set
to 0, then the bit in the Interrupt register may still become
set, but no interrupt to the 80188 embedded controller
will occur.
Each bit in this register will unmask the corresponding
interrupt of Interrupt Register 2 (TIR5) when the unmask
Bit
Name
Reset Value
Description
7
6
5
4
3
2
1
0
RXCNTU
CRC8GU
CRC32GU
RXFORU
RXFBAU
SDFU
0
0
0
0
0
0
0
0
RX Byte Count Interrupt Unmask.
CRC8 Good Interrupt Unmask.
CRC32 Good Interrupt Unmask.
RX FIFO Overrun Interrupt Unmask.
RX FIFO Byte Available Interrupt Unmask.
Start Delimiter Found Interrupt Unmask.
Busy Channel Found Interrupt Unmask.
Antenna Lock Interrupt Found Interrupt Unmask.
BCFU
ALOKIU
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TIR8: Transmit Control
This register is the Transmitter Control register.
Bit
Name
Reset Value
Description
7
TXRES
0
Transmit Reset. When this bit is set to 1, the internal Transmit Re-
set signal is asserted. When this bit is set to 0, the internal Transmit
Reset signal is deasserted. The transmit FIFO is NOT reset
by TXRES.
6
5
TXFR
0
0
Transmit FIFO Reset. When this bit is set to 1, the internal Transmit
FIFO Reset signal is asserted. When this bit is set to 0, the internal
Transmit FIFO Reset signal is deasserted.
DMA_SEL
DMA Select. When this bit is set to 1, the TXFIFO Not_Full signal is
routed to both of the 80188 DMA channels. When this bit is set to 0,
the TXFIFO Not_Full signal is routed to only DMA channel 1 of
the 80188.
4
EN_TX_CRC
0
Enable CRC-based Transmission. When this bit is set to 1, the in-
itiation of a transmission will commence when the logical AND of
the TXS bit (TIR8, bit 0) and the CRC32_GOOD output of the
CRC32 block becomes TRUE. Typically, the EN_TX_CRC bit and
the TXS bit are set together during a reception, such that if the re-
ception concludes with a correct CRC32 indication, then the trans-
mit state machine will automatically be started. When this bit is set
to 0, initiation of transmission will commence solely on the basis of
the setting of the TXS bit (TIR8, bit 0).
3
RATE_SW
–
Rate Switch. When this bit is set to 1, the rate of data transmission
will automatically change immediately following the transmission of
the last bit of the PFLth byte that follows the last bit of the Start of
Frame Delimiter, where PFL is defined in TCR3, bits [3:0}. Since
the PFL field of TCR3 is typically used to demark the PHY HEADER
from the MAC data (and hence, it is used to determine the starting
point for MAC CRC32 calculation), the rate switch will typically oc-
cur on the PHY/MAC boundary. The rate of transmission will
change from DR to DR XOR 0x1, where DR is the Data Rate field as
defined in TCR30, bits [2:0}. When this bit is set to 0, no rate switch
will occur. RX operations are unaffected by this bit. For rate switch-
ing on the RX side, an external decode to RX clock and TX data is
typically performed.
2–1
TCRC[1:0]
00b
Transmit CRC type. These two bits are used to determine the na-
ture of the CRC field that is appended to the current frame. These
bits must be stable throughout any given transmission. The follow-
ing interpretations have been assigned to these bits:
TCRC[1:0]
Transmitted CRC
00
01
10
11
No CRC is appended
CRC8 is appended
CRC32 is appended
No CRC is appended
0
TXS
0
Transmit Start.
When this bit is set to 1, then the transmit state machine begins op-
eration. The transmit state machine is edge-sensitive; that is, this
bit must be reset to 0 and set again to 1 before a subsequent trans-
mission will begin. The transmit busy bit will be set in the transmit
status register (TIR9) to indicate the state of transmit. Resetting this
bit to 0 during transmission will not cause the current transmission
to be aborted. Transmission abort is performed with the TXRES bit.
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TIR9: Transmit Status
Transmit Status register. Indicates the current status of
the Transmit portion of the TAI. Writes to these bits have
no effect.
Bit
Name
Reset Value
Description
7
TXCRC
0
Transmit CRC. TXCRC becomes set when the CRC is being ap-
pended to the end of the transmit frame. TXCRC is reset when the
transmission of the last bit of the CRC is completed.
6
TXSDD
0
Transmit Start Delimiter. TXSDD becomes set after the Start of
Frame Delimiter has been sent. This signal is deasserted when the
RESET pin is asserted or the CORESET bit is set to 1 (SIR0), when
the TXRES bit is set to 1 (TIR8), or when RXRES bit is set to 1
(TIR16), or when the RXS bit is set to 1 (TIR16), or the SRES bit is
set to 1 (TIR0). If a CRC is appended to the frame, then TXSDD will
be reset after the last bit of the CRC is appended to the frame.
5
Reserved
TXFC[3:0]
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
4–1
8h
Transmit FIFO Count. TXFC indicates the current count of the num-
ber of spaces available in the TX FIFO. The TX FIFO holds 8 bytes.
A TXFC value of “8h” indicates an empty TX FIFO, i.e., 8 spaces are
available. A TXFC value of “0h” indicates a full TX FIFO, i.e., 0
spaces are available.
0
TXBSY
0
TX Busy. This bit is set to 1 by the Am79C930 device when the
transmit operation begins and remains set until the transmission
has completed. Specifically, the TXBSY bit will be active whenever
the internal O_TX signal is active as indicated in the TX timing dia-
gram found in the Am79C930-based TX Power Ramp Control
section. When the TXC pin is configured as an input, then the
TXBSY signal will remain active until both the byte-wide TX FIFO
and the 16-bit serial FIFO have emptied. A write to this bit has
no effect.
TIR10: TX FIFO Data Register
This register is the TX FIFO Data Register. This
register allows direct access to the TX FIFO in the TAI.
When written, the TX FIFO write pointer is automatically
incremented. When read, the TX FIFO read pointer is
automatically incremented.
Bit
Name
Reset Value
Description
7:0
TXF[7:0]
–
Transmit FIFO data port. When written, data is placed into the sys-
tem side of the transmit FIFO. When read, data is removed from the
network side of the transmit FIFO. Reads of this register should be
for diagnostic purposes only and will not be necessary during nor-
mal operation. TX FIFO write and read pointers are automatically
incremented when writes and reads occur, respectively.
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TIR11: Transmit Sequence Control
This register is the Transmit Sequence Control. The
bits in this register determine the function of the transmit
sequence signals.
Bit
Name
Reset Value
Description
7
RXCD
pin
RXC/IRQ10 pin Data. The value that is written to this bit will be
driven out to the RXC pin when the RXCEN bit of TCR15 has been
set to a 1 and the RXCFN bit of TCR28 has been set to a 0.
The value that is read from RXCD represents the current value of
the RXC/IRQ10 pin. The control of the function of the RXC/IRQ10
pin is described in the Multi-Function Pin section.
6
5
4
USER6D
USER5D
LLOCKE
pin
pin
pin
USER6/IRQ5 pin Data. The value that is written to USER6D may be
driven out to the USER6/IRQ5 pin, depending upon the values of
the USER6EN bit (TCR15[3]), the USER6FN bit (TCR7[6]), the ISA
PnP registers 70h and 71h, and the operating mode of the
Am79C930 device.
The value read from USER6D will always represent the current
value of the USER6/IRQ5 pin. The control of the function of the
USER6/IRQ5 pin is described in the Multi-Function Pin section.
USER5/IRQ4 pin Data. The value that is written to USER5D may be
driven out to the USER5/IRQ4 pin, depending upon the values of
the USER5EN bit (TCR15[2]), the USER5FN bit (TCR7[5]), the ISA
PnP registers 70h and 71h, and the operating mode of the
Am79C930 device.
The value read from USER5D will always represent the current
value of the USER5/IRQ4 pin. The control of the function of the
USER5/IRQ4 pin is described in the Multi-Function Pin section.
LLOCKE pin data value. The value that is written to LLOCKE may
be driven out to the LLOCKE/SA15 pin, depending upon the values
of the LLOCKEN bit (TCR14[6]), and the operating mode of the
Am79C930 device (i.e., PCMCIA or ISA).
The value read from LLOCKE will always represent the current
value of the LLOCKE/SA15 pin. The control of the function of the
LLOCKE/SA15 pin is described in the Multi-Function Pin section.
3
2
RCEN
0
0
Register Control Enable. Used to control the functional timing of
the TXCMD, TXMOD and TXPE pin values as defined in the
Multi-Function Pin section. See the Multi-Function Pin section de-
scription for each of these pins for more details.
TXMOD
TXMOD pin control. Used to control the functional timing of the
TXCMD, pin value as defined in the Multi-Function Pin section. See
the Multi-Function Pin section description for more details.
1
0
TXPE
0
0
TXPE pin control. The TXPE bit affects the value of theTXPE pin as
described in the Multi-Function Pin section.
TXCMD
TXCMD and TXCMD pin control. The TXCMD bit affects the value
of the the TXCMD andTXCMD pins as described in theMulti-Func-
tion Pin section.
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TIR12: Byte Count Register LSB
This register is the Byte count register LSB. This register
contains the lower 8 bits of the 12-bit byte count for
receive and transmit messages. This is a working
register; access by software is not needed for
normal operation.
Bit
Name
Reset Value
Description
7:0
BC[7:0]
00h
Byte Count. Lower eight bits of current byte count for both transmit
and receive operations. During transmit operations, the byte count
reflects the number of bytes that have been transmitted following
the transmission of the Start of Frame Delimiter. CRC is not in-
cluded in this count for TX. During receive operations, the byte
count reflects the number of bytes that have been written into the
RX FIFO. This total excludes Preamble and Start Of Frame
Delimiter bytes, but includes any PHY field and CRC bytes.
Write accesses to this register from the software will cause
unexpected results.
TIR13: Byte Count Register MSB
This register is the Byte count register MSB. This regis-
ter contains the upper 4 bits of the 12-bit byte count for
receive and transmit messages. This is a working
register; access by software is not needed for
normal operation.
Bit
Name
Reset Value
Description
7–4
3–0
Reserved
BC[11:8]
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
0h
Byte Count. Upper 4 bits of current byte count for both transmit and
receive operations. During transmit operations, the byte count re-
flects the number of bytes that have been transmitted following the
transmission of the Start of Frame Delimiter. CRC is not included in
this count for TX. During receive operations, the byte count reflects
the number of bytes that have been written into the RX FIFO. This
total excludes Preamble and Start Of Frame Delimiter bytes, but in-
cludes any PHY field and CRC bytes. Write accesses to this regis-
ter from the software will cause unexpected results.
TIR14: Byte Count Limit LSB
This register is the Byte Count Limit LSB register.
Bit
Name
Reset Value
Description
7–0
BCLT[7:0]
00h
Byte Count Limit. Lower eight bits of byte count limit for both trans-
mit and receive operations, depending upon which operation is
currently occurring. During transmit operations, when the byte
count limit is reached, an interrupt to the 80188 controller will be
generated if the TXBCNT interrupt has been unmasked. During TX,
the byte counter counts all bytes beginning with the first byte after
the SFD field has been detected and does not count the CRC bytes
appended to the TX frame. During RX, when the byte count limit is
reached, an interrupt to the 80188 controller will be generated if the
RXBCNT interrupt has been unmasked. During RX, the byte
counter counts all bytes that follow the Start of Frame Delimiter.
Byte count limit has no effect on state machine or
FIFO operations.
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TIR15: Byte Count Limit MSB
This register is the Byte Count Limit MSB register.
Bit
Name
Reset Value
Description
7–4
3–0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
BCLT[11:8]
0h
Byte Count Limit. Upper 4 bits of byte count limit for both transmit
and receive operations, depending upon which operation is cur-
rently occurring. During transmit operations, when the byte count
limit is reached, an interrupt to the 80188 controller will be gener-
ated if the TXBCNT interrupt has been unmasked. During TX, the
byte counter counts all bytes beginning with the first byte after the
SFD field has been detected and does not count the CRC bytes ap-
pended to the TX frame. During RX, when the byte count limit is
reached, an interrupt to the 80188 controller will be generated if the
RXBCNT interrupt has been unmasked. During RX, the byte
counter counts all bytes that follow the Start of Frame delimiter.
Byte count limit has no effect on state machine or FIFO operations.
TIR16: Receiver Control
This register is the Receiver Control register. This regis-
ter allows basic control of the receive function.
Bit
Name
Reset Value
Description
7
RXRES
0
Receive Reset. When this bit is set to 1, the internal Receive Reset
signal is asserted. When this bit is set to 0, the internal Receive Re-
set signal is deasserted. The Receive FIFO is not reset by RXRES.
6
RXFR
0
Receive FIFO Reset. When this bit is set to 1, the internal Receive
FIFO Reset signal is asserted. When this bit is set to 0, the internal
Receive FIFO Reset signal is deasserted.
5–1
0
Reserved
RXS
–
0
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
Receive Start. When this bit is set to 1, then the receive state ma-
chine begins operation. DRQ indications based upon RX FIFO
status are independent of the value of this bit. The receive state
machine is edge-sensitive, that is, this bit must be reset to 0 and set
again to 1 before a subsequent reception will begin. The receive
busy bit will be set in the Receive Status register (TIR17) to indicate
the state of reception. Resetting this bit to 0 during a reception will
not cause the current reception to be aborted. Receive abort is per-
formed with the RXRES bit.
TIR17: Receive Status Register
This register is the RX Status register. Indicates the cur-
rent status of the Receive portion of the TAI.
Bit
Name
Reset Value
Description
7
CRC32
0
CRC32 Good. The CRC32 machine has detected a good CRC and
has latched the byte count that was active at the time that the CRC
was good.
6
CRC8
0
CRC8 Good. The CRC8 machine has detected a good CRC and
has latched the byte count that was active at the time that the CRC
was good.
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5
RXFOR
0
0
Receive FIFO Overrun. This bit is set whenever the RX FIFO expe-
riences an overrun. This bit is cleared by resetting the RX FIFO.
4–1
RXFC[3:0]
Receive FIFO Count. These bits indicate the current count of the
number of bytes contained in the RX FIFO. The RX FIFO holds 15
bytes. An RXFC value of “0h” indicates an empty RX FIFO. An
RXFC value of “Fh” indicates a full RX FIFO.
0
RXBSY
0
RX Busy. This bit is set to 1 by the Am79C930 device when the RXS
bit of TIR16 is set to a one, and remains set until the RXRES bit of
TIR16 is set to a one, or until any other global reset is activated
(e.g., RESET pin of Am79C930 asserted or the CORESET bit of
SIR0 is set).
TIR18: RX FIFO Data Register
This register is the RX FIFO Data register. This register
allows direct access to the RX FIFO in the TAI. When
read, the RX FIFO read pointer is automatically
incremented. When written, the RX FIFO write pointer is
automatically incremented.
Bit
Name
Reset Value
Description
7:0
RXF[7:0]
–
Receive FIFO data port. When read, data is removed from the sys-
tem side of the receive FIFO. When written, data is placed into the
network side of the receive FIFO. Writes to this register should be
for diagnostic purposes only and will not be necessary during nor-
mal operation. RX FIFO write and read pointers are automatically
incremented when writes and reads occur, respectively.
TIR19: Reserved
This register is reserved.
Bit
Name
Reset Value
Description
7–0
Reserved
–
Reserved. Must be written as a 0. Reads of these bits produce
undefined data.
TIR20: CRC32 Correct Byte Count LSB
This register is the CRC32 Correct Byte Count
LSB register.
Bit
Name
Reset Value
Description
7–0
C32C[7:0]
–
CRC32 Correct Count. The value in this register indicates the lower
8 bits of the 12-bit byte position when the CRC32 value was last cor-
rect. CRC32value001hcorrespondstothefirstbyteofthereceived
message following the Start of Frame Delimiter. If the value in this
register (and TIR21) does not match the length value indicated in
the frame header (plus overhead for PHY and MAC headers and
CRC) for frames that employ 32-bit CRC values, then the frame
should be rejected by the MAC firmware. Note that all bytes begin-
ning with the first byte following the Start of Frame Delimiter and in-
cluding the CRC bytes are included in the CRC32 Correct Count
value, but the bytes that are included in the CRC32 calculation are
dependent upon the setting of the PFL bits of TCR3.
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TIR21: CRC32 Correct Byte Count MSB
This register is the CRC32 Correct Byte Count
MSB register.
Bit
Name
Reset Value
Description
7–4
3–0
Reserved
–
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
C32C[11:8]
CRC32 Correct Count. The value in this register indicates the upper
4 bits of the 12-bit byte position when the CRC32 value was last cor-
rect. CRC32value001hcorrespondstothefirstbyteofthereceived
message following the Start of Frame Delimiter. If the value in this
register (and TIR20) does not match the length value indicated in
the frame header (plus overhead for PHY and MAC headers and
CRC) for frames that employ 32-bit CRC values, then the frame
should be rejected by the MAC firmware. Note that all bytes begin-
ning with the first byte following the Start of Frame Delimiter and in-
cluding the CRC bytes are included in the CRC32 Correct Count
value, but the bytes that are included in the CRC32 calculation are
dependent upon the setting of the PFL bits of TCR3.
TIR22: CRC8 Correct Byte Count LSB
This register is the CRC8 Correct Byte Count
LSB register.
Bit
Name
Reset Value
Description
7–0
C32C[7:0]
–
CRC8 Correct Count. The value in this register indicates the lower 8
bits of the 12-bit byte position when the CRC8 value was last cor-
rect. CRC8 value 001h corresponds to the first byte of the received
message following the Start of Frame Delimiter. If the value in this
register (and TIR22) does not match the length value indicated in
the frame header (plus overhead for PHY and MAC headers and
CRC) for frames that employ 8-bit CRC values, then the frame
should be rejected by the MAC firmware. Note that all bytes begin-
ning with the first byte following the Start of Frame Delimiter and in-
cluding the CRC bytes are included in the CRC8 Correct Count
value, but the bytes that are included in the CRC8 calculation are
dependent upon the setting of the PFL bits of TCR3.
TIR23: CRC8 Correct Byte Count MSB
This register is the CRC8 Correct Byte Count
MSB register .
Bit
Name
Reset Value
Description
7–4
3–0
Reserved
C8C[11:8]
–
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
CRC8 Correct Count. The value in this register indicates the upper
4 of the 12-bit byte position when the CRC8 value was last correct.
CRC8 value 001h corresponds to the first byte of the received mes-
sage following the Start of Frame Delimiter. If the value in this regis-
ter (and TIR22) does not match the length value indicated in the
frame header (plus overhead for PHY and MAC headers and CRC)
for frames that employ 8-bit CRC values, then the frame should be
rejected by the MAC firmware. Note that all bytes beginning with the
first byte following the Start of Frame Delimiter and including the
CRC bytes are included in the CRC8 Correct Count value, but the
bytesthatareincludedintheCRC8calculationaredependentupon
the setting of the PFL bits of TCR3.
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TIR24: TCR Index Register
This register is the TCR Index register. This register is
used as an address into indirect TAI register space. The
value in the TCR Index Register is used as an address
that points at one of 64 registers that are accessed
through the TCR Data Port.
Bit
Name
Reset Value
Description
7:6
5:0
Reserved
TCRI[5:0]
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
00h
TCRIndexvalue. ThevalueintheTCRIndexRegisterisusedasan
address that points at one of 64 registers that are accessed through
the TCR Data Port.
TIR25: Configuration Data Port
This register is the Configuration Data Port register.
This register is used as the data port allowing access
to 64 indirectly accessed registers. The register that is
accessed through the Configuration Data Port is deter-
mined by the current setting of the Configuration Index
Register.
Bit
Name
Reset Value
Description
7–0
CD[7:0]
–
Configuration Register Data. This register is used as the data port
allowing access to 64 indirectly accessed registers. The register
that is accessed through the Configuration Data Port is determined
by the current setting of the Configuration Index Register.
TIR26: Antenna Diversity and A/D Control
This register is the Antenna Diversity and A/D
Control register.
Bit
Name
Reset Value
Description
7
CHBSY
0
Channel Busy. The Am79C930 device will set this bit to a 1 when
the clear channel assessment logic determines that a carrier is pre-
sent. The Am79C930 device will set this bit to a 0 when the clear
channel assessment logic determines that a carrier is not present.
Writes by firmware will have no effect on this bit.
6
ANTLOK
0
Antenna Selection Locked. The Am79C930 device will set
ANTLOK to a 1 when it has determined that criteria for antenna se-
lection have been passed. The Am79C930 device will set ANTLOK
to a 0 when the RXS bit of TIR16 is set 1.
5
4
ANTSLT
ANTS
0
0
Antenna Selection. This bit gives the current value of the ANTSLT
pin, whether determined by register bit programming or internal an-
tenna selection logic. This bit is read only.
Antenna Switch. If ANTSEN is set to 1, then the software may di-
rectly control the value of the ANTSLT and ANTSLT pins with this
bit. If ANTSEN is set to 0, then writes to this bit will have no effect on
thevalueoftheANTSLTandANTSLTpins. Note:Antennadiversity
is disabled with the ANTSEN bit (bit 3 of TIR26).
3
ANTSEN
0
Antenna Switch Enable. ANTSEN and ANTSLTLFN (TCR30[7])
are combined with the PCMCIA pin setting to determine the func-
tionality of the ANTSLT and ANTSLT pins.
The complete control of the function of the ANTSLT and ANTSLT
pins are described in the Multi-Function Pin section.
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2
ADDA
0
A/D D/A mode. ADDA is used with ENEXT (TCR25[6]), ENSAR
(TCR25[5]), and UXA2DST (TCR25[7]) to determine the mode of
operation of the A/D portion of the Am79C930 device according to
the following table:
ADDA
TIR26[2]
ENEXT
TCR25[6]
ENSAR
TCR25[5]
UXA2DST
TCR25[7]
A/D
mode
0
0
0
0
0
0
1
1
0
0
0
0
1
1
X
X
0
0
1
1
0
1
0
1
0
1
internal_A
reserved
internal_B
internal_C
external
0
1
X
X
X
X
reserved
reserved
D/A mode
For a complete description of the operation of each of the above
modes, see the RSSI A/D subsection of the TAI section.
1
0
SRCS
0
0
A/D Source Select. When SRCS is set to 0, then ADIN1 is the input
to the A/D converter for internal A/D modes. When SRCS is set to 1,
then ADIN2 is the input to the A/D converter for internal A/D modes.
SRCS has no effect when external or D/A mode has been selected.
STRTC
Start Conversion. Whenever a 1 is written to STRTC (i.e., even if
the bit value is already 1), the A/D begins the conversion process on
the current comparator input, unless a conversion cycle is currently
under way. STRTC is intended for use only at times when the A/D
conversion process is not controlled by the antenna diversity logic.
That is, whenever RXS=0, writing a 1 to STRTC will; however,
initiate a conversion cycle regardless of the state of the RXS bit
of TIR16.
TIR27: Serial Approximation Register
This register is the SAR register. Contains the A/D con-
verter’s Serial Approximation Register value. A read
from this register will give the current value of the SAR in
the A/D circuit.
Bit
Name
Reset Value
Description
7
CACT
0
Conversion Active. When an A/D conversion is being performed,
the Am79C930 device will set this bit to a 1. When the conversion
operation has completed, the Am79C930 device will reset this bit to
a 0.
6–0
SAR[6:0]
pin
Serial Approximation Register. Contains the A/D converter’s Serial
Approximation Register value. A read from this register will give the
current value of the SAR in the A/D circuit. When CACT is a 1, then
this value is not stable. A write to this register will cause the written
value to be driven onto the SAR[6:0] pins if the ADDA bit of TIR26 is
set to 1. If the ADDA bit of TIR26 is set to 0, then a write to SAR[6:0]
bits of TIR27 will have no effect on the internal A/D conversion proc-
ess or on the SAR[6:0] output pins.
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TIR28: RSSI Lower Limit
This register is the RSSI Lower Limit register. The value
in this register is compared against converted RSSI in-
put values. When the converted RSSI value is equal to
or exceeds the value in this register, then an indication
will be sent to the clear channel assessment logic.
Bit
Name
Reset Value
Description
7
RSALT
0
RSSI Equal or Above Limit. When the converted RSSI input value
equals or exceeds the value in the RSSI lower limit register, then
the Am79C930 device will set this bit to a 1. When the converted
RSSI input value is less than the value in the RSSI lower limit regis-
ter, then the Am79C930 device will set this bit to a 0.
6–0
RLLT[6:0]
00h
RSSI Lower Limit. The value in this register is compared against
converted RSSI input values. When the converted RSSI value
equals or exceeds the value in this register, then an indication will
be sent to the clear channel assessment logic.
TIR29: USER Pin Data
This register is the USER Pin Data register. This register
allows access to the USER[4:0] pins.
Bit
Name
Reset Value
Description
7
USER7DL
pin
USER7 pin Data. The value that is written to this bit will be inverted
and then driven out to the USER7 pin of the Am79C930 device
when the system interface mode is PCMCIA and the USER7EN bit
of TCR14 is set to ONE. In all other cases, the value of USR7DL will
have no effect on the value of the USER7 pin. The value that is read
from this bit represents the inverted value of the USER7 pin of the
Am79C930 device at any time in any mode.
The complete control of the function of the USER7/IRQ11 pin is de-
scribed in the Multi-Function Pin section.
6
Reserved
Reserved
–
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
5
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
4–0
USERDT[4:0]
pin
USER Pin Data[4:0]. The value that is written to any bit of this regis-
ter will be driven out to the corresponding USER pin of the
Am79C930 device when the corresponding USEREN bit of TCR14
has been set to a 1 and the PCMCIA pin is set to 1. The value that is
read from any bit of this register represents the current value of the
corresponding USER pin of the Am79C930 device regardless of
USEREN bit or PCMCIA pin settings.
The complete control of the function of each of the USER pins is de-
scribed in the Multi-Function Pin section.
TIR30: Test Dummy Register
This register is the TEST dummy register.
Bit
Name
Reset Value
Description
7–0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
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TIR31: TEST
The TAI TEST register is a reserved location.
Bit
Name
Reset Value
Description
7
Reserved
TC[6:0]
0
These bit must be set to 0. Do not write to this register.
6–0
00h
Test Command. The bits in this register are decoded to generate a
test mode for the TAI.
(TIR24) and then executing a read or write operation to
TAI Configuration Register Space (TCR)
the Configuration Data Port (TIR25). Since the indirectly
accessible registers are used mostly for TAI configura-
tion purposes, this set of registers is labeled TAI Con-
figuration Registers (TCR). The following section
describes the indirectly accessible Configuration Regis-
ters of the TAI, or TCR.
The Transceiver Attachment Interface (TAI) Unit con-
tains a total of 64 registers. Thirty-two of the registers
are directly accessible from the 80188 embedded core
and from the system interface through the BIU. The
other 32 registers are indirectly accessed by first writing
an INDEX value into the Configuration Register Index
TCR0: Network Configuration
This register is the Network Configuration register.
CONFIGURATION REGISTER INDEX:
00h
Bit
Name
Reset Value
Description
7–5
DRB[2:0]
0h
Dribbling Bits. The value of DRB sets the amount of time that drib-
bling bits will be generated following the end of CRC during frame
transmission. Power will be removed from the transmitter following
the end of the dribbling bit period. With respect to external transmit
timing signals, the value of DRB will determine the amount of time
that passes from the sending of the last valid TX CRC bit until the
deassertion of the TXP_ONsignal. Dribbling bit resolution is equal
to 40 times the CLKIN period when the CLKGT20 bit of MIR9 is set
to 0 and is equal to 80 times the CLKIN period when the CLKGT20
bit of MIR9 is set to 1. For a 1 Mbs data rate with CLKIN = 20 MHz
and CLKGT20 = 0, the resolution is 2 µ.
4–2
HDB[2:0]
0h
Header Bits. The value of HDB sets the amount of time that header
bits will be generated before the first bit of preamble is sent to the
transmitter during frame transmission. The count begins at the time
that power is applied to the transmitter. With respect to external
transmit timing signals, the value of HDB will determine the amount
of time that passes from the assertion of the TXP_ON and signal to
the delivery of the first valid TX data bit to the TXDATA pin. Header
bit resolution is equal to 40 times the CLKIN period when the
CLKGT20 bit of MIR9 is set to 0 and is equal to 80 times the CLKIN
period when the CLKGT20 bit of MIR9 is set to 1. For a 1 Mbs data
rate with CLKIN = 20MHz and CLKGT20 = 0, the resolution is 2 µ.
1–0
SD[1:0]
0h
Start Delimiter. The value in this register determines the number
of bytes of preamble that will be verified before the start of
frame detect indication is asserted during frame reception and
transmission. The following interpretations have been assigned to
these bits.
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Programmed
Register
SD[1:0]
Start of Frame Detect Operation
00
01
10
11
Start of Frame Detect Off
None
TCR10
Search for 8 bit Start of Frame Delimiter
Search for 16 bit Start of Frame Delimiter
Search for 24 bit Start of Frame Delimiter
TCR9, TCR10
TCR8, TCR9
TCR10
TCR1: Transmit Configuration
This register is the Transmit Configuration register.
CONFIGURATION REGISTER INDEX: 01h
Description
Bit
Name
Reset Value
7
TXENDCB
0
Transmit Enable DC Bias Control. When TXENDCB is set to a 1,
then the DC Bias Control algorithm is enabled. When TXENDCB is
reset to a 0, then the DC Bias Control algorithm is disabled.
6–5
4
Reserved
TXDI
0
0
0
Reserved. These bits may be written with any value. The value writ-
ten to these bits will be returned when read. The value of these bits
will not affect device function.
Transmit Data Invert. When set to a 1, the outgoing transmit serial
data stream is inverted. When set to a 0, the outgoing transmit se-
rial data stream is not inverted.
3–2
TXDLC
Transmit Data Pin Control. These bits are used to control the state
of the TXDL pin when no transmit activity is present. The following
interpretations have been assigned to these bits:
TXDATA Pin
Default state
TXDLC[1:0]
00
01
10
11
last bit transmitted
high impedance
low
high
1–0
TXDC
01b
Transmit Data Pin Control. These bits are used to control the state
of the TXDL pin when no transmit activity is present. The following
interpretations have been assigned to these bits:
TXDATA pin
TXDC[1:0]
default state
00
01
10
11
last bit transmitted
low
low
high
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TCR2: Clock Recovery
This
register
is
the
Clock
Recovery
Configuration register.
Bit Name
Reset Value
Description
CONFIGURATION REGISTER INDEX:
02h
7
WNS2
0
Bit Stuffing Start. When WNS2 is set to a 1, then the bit stuffing op-
eration on RX and TX frames will begin after the PHY header field
has passed. When WNS2 is set to a 0, then the bit stuffing function
on RX and TX frames will begin operation immediately following
Start of Frame Delimiter detection. Note that bit stuffing may be dis-
abled with control bits in TCR1 (TX) and TCR3 (RX).
6
5
CLKRS
ECLK
0
0
Clock Recovery Select. This bit selects between the two clock
recovery circuits.
External Receive Clock Select. When this bit is set to 1, then the
device will expect a receive clock on the RXCIN pin. When this bit is
set to a 0, then the internal clock recovery circuit selected by the
CLKRS bit will be used to internally generate a recovered receive
clock from the incoming receive data stream.
4:0
CLKP[4:0]
0
Clock Phase. These bits are used to select the phase of the recov-
ered RX clock relative to the RX data edges. Valid values are 0
through 19 decimal, where each bit of resolution represents a shift
in the phase of the sample point by one CLKIN period when the
CLKGT20 bit of MIR9 is set to 0, and two CLKIN periods when the
CLKGT20 bit of MIR9 is set to 1.
TCR3: Receive Configuration
This register is the Receive Configuration register.
CONFIGURATION REGISTER INDEX: 03h
Bit
Name
Reset Value
Description
7
6
LOOPB
WNS
0
0
Loopback. When set to a 1, a loopback mode is enabled. When set
to a 0, normal receive and transmit paths are followed.
Endian Mode Select. When set to a 1, this bit selects big endian
(MS bit first) as the data format. The setting of this bit only affects
the operation of the parallel-to-serial conversion register in the
transmit path and the serial-to-parallel conversion register in the re-
ceive path. No other areas are affected, i.e., start of frame detection
is always performed on the bit stream as it will appear on the me-
dium. When set to 0, little endian mode (LS bit first) is selected.
5
RXENDCB
0
Receive Enable DC Bias Control. When RXENDCB is set to a 1,
then the receive machine will automatically remove the DC Bias
Control effects from the input data stream. When RXENDCB is
reset to a 0, then the receive stream DC Bias removal circuit will
be disabled.
4
RXDI
0
0
Receive Data Invert. When set to a 1, the incoming receive serial
data stream is inverted. When set to a 0, the incoming receive serial
data stream is not inverted.
3:0
PFL[3:0]
Physical layer Field Length [3:0]. These bits are used to determine
the number of bytes of PHY header that are allowed to pass before
the Am79C930 device begins calculating the CRC8 and CRC32
and DC bias control. The Physical layer Field Length value is used
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to delay the start of CRC8 and CRC32 and DC bias control
calculation for both receive and transmit frames. The physical
header field is assumed to begin after the Start of Frame Delimiter
has been detected.
TCR4: Antenna Diversity Timer
This register is the Antenna Diversity Timer register
used to control antenna dwell time during antenna
diversity measurements.
CONFIGURATION REGISTER INDEX:
04h
Bit
Name
Reset Value
Description
7
ANTEN
0
Antenna Diversity Enable. When set to a 1, the internal antenna di-
versity logic is used to select the antenna. When set to a 0, software
has control over antenna selection through the ANTS bit of
TIR26[4] and the ANTSLTLD bit of TCR7[1]. Dwell times for an-
tenna measurements are still used to obtain RSSI data when this bit
is set to 0, but final antenna selection will be controlled by software.
6
Reserved
ADT[5:0]
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
5–0
00h
Antenna Diversity Timer. Dwell time per antenna in time steps of
CLKIN period times 20 when the CLKGT20 bit of MIR9 is set to 0,
and time steps of CLKIN period times 40, when the CLKGT20 bit of
MIR9 is set to 1. When the value in this register is “00,” then the di-
versity switching function is disabled.
TCR5: TX Ramp Up Timing
This register is the TX Ramp Up Timing register. This
register determines the ramp up timing of the TX
enable signals.
CONFIGURATION REGISTER INDEX:
05h
Bit
Name
Reset Value
Description
7:4
TGAP1[3:0]
0h
Transmit Timing Gap 1. These bits are used to determine the gap
between the assertion of the T1 signal and the assertion of the T2
signal. T1 and T2 can be used to control the timing of the TXCMD
and TXPE pins, respectively. The interval is programmable with a
resolution equal to 20 times the CLKIN period when the CLKGT20
bit of MIR9 is set to 0 and a resolution equal to 40 times the CLKIN
period when the CLKGT20 bit of MIR9 is set to 1. For a 1Mbs data
rate with CLKIN = 20MHz and CLKGT20 = 0, the resolution is 1 µ.
3:0
TGAP2[3:0]
0h
Transmit Timing Gap 2. These bits are used to determine the gap
between the assertion of the T2 signal and the assertion of the T3
signal. The interval is programmable with a resolution equal to 20
times the CLKIN period when the CLKGT20 bit of MIR9 is set to 0
and a resolution equal to 40 times the CLKIN period when the
CLKGT20 bit of MIR9 is set to 1. For a 1 Mbs data rate with CLKIN =
20 MHz and CLKGT20 = 0, the resolution is 1 µ.
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TCR6: TX Ramp Down Timing
This register is the TX Ramp Down Timing register.
This register determines the ramp down timing of the TX
enable signals.
CONFIGURATION REGISTER INDEX:
06h
Bit
Name
Reset Value
Description
7:4
TGAP3[3:0]
0h
Transmit Timing Gap 3. These bits are used to determine the gap
between the deassertion of theT3 signal and the deassertion of the
T2 signal. T3 and T2 can be used to control the timing of the
TXMOD and TXPE pins. The interval is programmable with a reso-
lution equal to 20 times the CLKIN period when the CLKGT20 bit of
MIR9 is set to 0 and a resolution equal to 40 times the CLKIN period
when the CLKGT20 bit of MIR9 is set to 1. For a 1 Mbs data rate with
CLKIN = 20 MHz and CLKGT20 = 0, the resolution is 1 µ.
3:0
TGAP4[3:0]
0h
Transmit Timing Gap 4. These bits are used to determine the gap
between the deassertion of theT2 signal and the deassertion of the
T1 signal. T2 and T1 can be used to control the timing of the TXPE
and TXCMD pins. The interval is programmable with a resolution
equal to 20 times the CLKIN period when the CLKGT20 bit of MIR9
is set to 0 and a resolution equal to 40 times the CLKIN period when
the CLKGT20 bit of MIR9 is set to 1. For a 1Mbs data rate with
CLKIN = 20 MHz and CLKGT20 = 0, the resolution is 1 µ.
TCR7: Pin Data A
This register is the Pin Data A register. This register is
TXDATA and TXCMD pins and to configure the function
used to deliver and retrieve data from the ANTSLT,
of the USER5 and USER6 pins.
CONFIGURATION REGISTER INDEX:
07h
Bit
Name
Reset Value
Description
7
CTSEN
0
CTS Enable. When CTSEN is set to a 1, then the USER1/IRQ12 pin
input value will be used to gate the start of the internal TX state ma-
chine. With CTSEN set to a 1, T1, T2, etc., signaling will not follow
the assertion of the TXS bit of TIR8 until USER1/IRQ12/EXTCTS
becomes active (HIGH), and then normal timing forT1, T2, etc., will
be produced.
When CTSEN is set to a 0, then TX state machine operations pro-
ceed without delay, following the assertion the TXS bit of TIR8, re-
gardless of the value of USER1/IRQ12/EXTCTS.
6
USER6FN
0
USER6 Function. USER6FN, the PCMCIA mode pin, USER6EN
(TCR15[3]), and the ISA Plug and Play registers 70h and 71h are
used to determine the function of the USER6/IRQ5 pin.
In addition, the USER6/IRQ5 pin may be used to produce interrupts
to the 80188 embedded controller. This capability is controlled by
the ENXSDF bit of TCR28 and the SDFU bit of TIR5 and operates
independently of the bits mentioned above.
The control of the function of the USER6/IRQ5 pin is described in
the Multi-Function Pin section.
5
USER5FN
0
USER5 Function. USER5FN, the PCMCIA mode pin, USER5EN
(TCR15[2]), and ISA PnP registers 70h and 71h are used to deter-
mine the function of the USER5/IRQ4 pin.
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In addition, the USER5/IRQ4 pin may be used to produce interrupts
to the 80188 embedded controller. This capability is controlled by
the ENXCHBSY bit of TCR28 and the CHBSYCU bit of TIR5 and
operates independently of the bits mentioned above.
The control of the function of the USER5/IRQ4 pin is described in
the Multi-Function Pin section.
4–3
U1INTCNT
00b
USER1 Interrupt control bits. The USER1/IRQ12 pin can be used
to signal an interrupt to the 80188 embedded controller. The
U1INTCNT bits have the following interpretation and operate inde-
pendently of the operating mode of the Am79C930 device (i.e.,
the U1INTCNT bits operate in both PCMCIA and ISA Plug and
Play modes.):
U1INT Bit
U1INTCNT
TCR7[4:3]
USER1 Pin
Event
(TCR11[3])
Result
00
01
10
11
X
0 => interrupt
disabled
rising edge
falling edge
1 => interrupt
signaled
1 => interrupt
signaled
rising or
falling edge
1 => interrupt
signaled
Note that the USER1 pin function has no effect on the use of the
USER1/IRQ12 pin as an interrupt signaling pin. If the
USER1/IRQ12 pin is to be used as a 80188 controller interrupt
source in the ISA Plug and Play mode, then it is imperative that the
ISA Plug and Play resource data structure loaded into the accom-
panying flash device as part of the Am79C930 device based design
should not include IRQ12 as a choice of IRQ level for possible se-
lection by the ISA Plug and Play configuration software. When this
procedure is followed, then the system designer can be assured
that the IRQ12 function will not be used by the Am79C930 device,
and therefore, the USER1/IRQ12 pin will remain in the high-imped-
ance state and will be available for connection to an interrupt gener-
ating source in the design.
2
1
TXCMDT
0
1
TXCMD Data. The value written to the TXCMDT bit is used in some
modes to determine the output value of the TXCMD/LA21 pin.
Reads from TXCMDT always return the current value of the
TXCMD/LA21 pin.
The control of the function of the TXCMD/LA21 pin is described in
the Multi-Function Pin section.
ANTSLTLD
ANTSLTL Data. The value that is written to this bit will be driven out
to the ANTSLT pin of the Am79C930 device when the ANTSLTLFN
bit of TCR30 has been set to a 1 and the ANTSLTLEN bit of TCR15
has also been set to a 1 and the PCMCIA pin is set to 1. The value
that is read from this bit represents the current value of theANTSLT
pin of the Am79C930 device.
A complete description of the control of the function of theANTSLT
pin is described in the Multi-Function Pin section.
0
TXDATALD
1
TXDATAL Data. The value that is written to this bit will be driven out
to theTXDATApin of the Am79C930 device when the TXDATALFN
bit of TCR30 has been set to a 1 and the TXDATALEN bit of TCR15
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has also been set to a 1 and the PCMCIA pin is set to 1. The value
that is read from this bit represents the current value of theTXDATA
pin of the Am79C930 device.
A complete description of the control of the function of theTXDATA
pin is described in the Multi-Function Pin section.
TCR8: Start Delimiter LSB
This register is the Start Delimiter LSB register.
CONFIGURATION REGISTER INDEX:
08h
Bit
Name
Reset Value
Description
7–0
SDLT[7:0]
00h
Start of Frame Delimiter. This register contains the LSB of the 24-bit
start delimiter field that is used for start of frame recognition during
reception and transmission in order to determine the start of MAC
CRC calculation. (Note that PFL of TCR3 may also affect start of
MAC CRC calculation start.) All, none or part of the 24-bit Start De-
limiter may be used for start of frame recognition by appropriate set-
tings of the SD[1:0] bits in the Network Configuration Register
(TCR0). Start of Frame detection is performed on the bits in the or-
der that they appear on the medium, with the SDLT LSB, bit 0, being
checked against the first bit to arrive at the Am79C930 (RX case)
or the first bit to leave the Am79C930 (TX case) and continuing in
that order.
TCR9: Start Delimiter CSB
This register is the Start Delimiter CSB register.
CONFIGURATION REGISTER INDEX:
09h
Bit
Name
Reset Value
Description
7–0
SDLT[15:8]
00h
Start of Frame Delimiter. This register contains the Center Signifi-
cant Byte (CSB) of the 24-bit start delimiter field that is used for start
of frame recognition during reception and transmission in order to
determine the start of MAC CRC calculation. (Note that PFL of
TCR3 may also affect start of MAC CRC calculation start.) All, none
or part of the 24-bit Start Delimiter may be used for start of frame
recognition by appropriate settings of the SD[1:0] bits in the Net-
work Configuration Register (TCR0). Start of Frame detection is
performed on the bits in the order that they appear on the medium,
with the SDLT LSB, bit 0, being checked against the first bit to arrive
at the Am79C930 (RX case) or the first bit to leave the Am79C930
(TX case) and continuing in that order.
TCR10: Start Delimiter MSB
This register is the Start Delimiter MSB register.
CONFIGURATION REGISTER INDEX:
0Ah
Bit
Name
Reset Value
Description
7–0
SDLT[23:16]
00h
Start of Frame Delimiter. This register contains the MSB of the
24-bit start delimiter field that is used for start of frame recognition
during reception and transmission in order to determine the start of
MAC CRC calculation. (Note that PFL of TCR3 may also affect start
of MAC CRC calculation start.) All, none or part of the 24-bit Start
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Delimiter may be used for start of frame recognition by appropriate
settings of the SD[1:0] bits in the Network Configuration Register
(TCR0). Start of Frame detection is performed on the bits in the or-
der that they appear on the medium, with the SDLT LSB, bit 0, being
checked against the first bit to arrive at the Am79C930 (RX case) or
the first bit to leave the Am79C930 (Tx case) and continuing in
that order.
TCR11: Interrupt Register 3
This register is the TAI Interrupt Register 3. Provides in-
terrupt status information. Any interrupt bit may be
cleared by writing a 1 to the bit location. Writing a 0 to a
bit location has no effect on the bit value. An interrupt in
TCR11 will be signaled in TIR4 through the MOREINT
bit when the associated unmask bit has been set in
TCR12.
CONFIGURATION REGISTER INDEX:
0Bh
Bit
Name
Reset Value
Description
7:4
3
Reserved
U1INT
–
0
Reserved. Must be written as a 0. Reads of these bits produce
undefined data.
USER1 Interrupt. When U1INT is set to 1, it indicates that a change
of state has occurred at the USER1/IRQ12 pin. The change of state
required to signal an interrupt on the U1INT bit is determined by the
settings of the U1INTSC bits of TCR7[4:3]. This function may be
disabled with an appropriate setting of the U1INTSC bits. A corre-
sponding unmask bit for this interrupt source exists in TCR12.
2
RUNERR
1
Run Length Error. When RUNERR is set to a 1, it indicates that the
total number of 1s during a received message exceeds the total
number of 0s at any given time by 25, or that the total number of 0s
in the message at any given time exceeds the number of 1s in the
message by 27. This function may be disabled with the DISRNR bit
of TCR27.
1
0
ATFO
ATFU
0
0
Asynchronous Transmit FIFO Overflow. When ATFO is set to 1, it
indicates that the asynchronous transmit FIFO has overflowed.
Asynchronous Transmit FIFO Underflow. When ATFU is set to 1, it
indicates that the asynchronous transmit FIFO has underflowed.
TCR12: Interrupt Unmask Register 3
This register is the Interrupt Unmask Register 3.
Each bit in this register will unmask the corresponding
interrupt of the Interrupt Register 2 (TIR5) when the un-
mask bit is set to 1.
CONFIGURATION REGISTER INDEX:
0Ch
Bit
Name
Reset Value
Description
7:4
Reserved
–
Reserved. Must be written as a 0. Reads of these bits produce
undefined data.
3
2
1
0
U1INTU
RUNERRU
ATFOU
0
0
0
0
USER1 Interrupt Unmask.
RUNERR Interrupt Unmask.
Asynchronous Transmit FIFO Overflow Interrupt Unmask.
Asynchronous Transmit FIFO Underflow Interrupt Unmask.
ATFUU
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TCR13: Pin Configuration A
This register is the Pin Configuration A register. This
register is used to set the state of various pins as outputs
or as high impedance inputs.
CONFIGURATION REGISTER INDEX:
0Dh
Bit
Name
Reset Value
Description
7
LNKEN
1
Link LED Enable. LNKEN can be used to control the function of the
LNK LED output. The control of the function of the LNK pin is de-
scribed in the Multi-Function Pin section.
6
5
4
3
2
1
0
LFPEEN
HFPEEN
1
1
1
1
1
1
1
LFPE Enable. LFPEEN is used to determine the function of the
LFPE pin. The control of the function of theLFPE pin is described in
the Multi-Function Pin section.
HFPE Enable. HFPEEN is used to determine the function of the
HFPE pin. The control of the function of the HFPE pin is described
in the Multi-Function Pin section.
SDCLKEN
SDS3LEN
SDS2LEN
SDS1LEN
RXPELEN
SDCLK Enable. SDCLKEN is used to determine the function of the
SDCLK pin. The control of the function of the SDCLK pin is de-
scribed in the Multi-Function Pin section.
SDSEL3 Enable. SDS3LEN is used to determine the function of the
SDSEL3 pin. The control of the function of the SDSEL[3] pin is de-
scribed in the Multi-Function Pin section.
SDSEL2 Enable. SDS2LEN is used to determine the function of the
SDSEL2 pin. The control of the function of the SDSEL[2] pin is de-
scribed in the Multi-Function Pin section.
SDSEL1 Enable. SDS1LEN is used to determine the function of the
SDSEL1 pin. The control of the function of the SDSEL[1] pin is de-
scribed in the Multi-Function Pin section.
RXPE Enable. RXPELEN is used to determine the function of the
RXPE pin. The control of the function of the RXPE pin is described
in the Multi-Function Pin section.
TCR14: Pin Configuration B
This register is the Pin Configuration B register. This
register is used to set the state of the USER[4:0] pins as
outputs or as high impedance inputs.
CONFIGURATION REGISTER INDEX:
0Eh
Bit
Name
Reset Value
Description
7
USER7EN
0
USER7 Enable. USER7EN, the ISA PnP registers 70h and 71h,
and the PCMCIA pin setting are used to determine the function of
the USER7 pin. The USER7 pin can be programmed to function as
either an input or an output.
The control of the function of the USER7/IRQ11 pin is described in
the Multi-Function Pin section.
6
LLOCKEN
0
LLOCKE Enable. LLOCKEN and the PCMCIA pin are used to de-
termine the direction of the LLOCKE/SA15 pin. When LLOCKEN is
set to a 1 and the PCMCIA pin is set to 1, then the LLOCKE/SA15
pin is enabled to drive both high and low output values. LLOCKE
output values are determined by the LLOCKE bit of TIR11. When
LLOCKEN is reset to a 0, then the LLOCKE pin is forced to a high-
impedance state. Reads of the LLOCKE bit of TIR11 will yield the
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value that is present on the LLOCKE pin, regardless of the setting of
the PCMCIA pin.
The control of the function of the LLOCKE/SA15 pin is described in
the Multi-Function Pin section.
5
Reserved
–
Reserved. Must be written as a 0. Reads of these bits produce
undefined data.
4:0
USEREN[4:0]
00h
USER[4:0] Enable. These five bits are used to determine the direc-
tion of the USER[4:0] pins. When any bit of the USEREN register is
set to a 1, then the corresponding USER device pin is enabled to
drive both high and low output values. USER output values are de-
termined by the individual bit settings of the USERDT register
(TIR29). When any bit of the USEREN register is reset to a 0, then
the corresponding USER device pin is forced to a high-impedance
state. Reads of the USERDT register (TIR29) will yield the value
that is present on any particular USER pin.
The control of the function of each of the USER pins is described in
the Multi-Function Pin section.
TCR15: Pin Configuration C
This register is the Pin Configuration C register. This
USER5, USER6, RXC, TXCMD,TXDATA, andANTSLT
register is used to set the state of the ACT, STSCHG,
pins as outputs or as high impedance inputs.
CONFIGURATION REGISTER INDEX:
0Fh
Bit
Name
Reset Value
Description
7
ANTSLTLEN
0
ANTSLT Enable. ANTSLTLEN, the ANTSLTLFN bit of TCR30, the
ANTSEN bit of TIR26, and the PCMCIA pin are used to determine
the function of the ANTSLT/LA23 pin.
The control of the function of the ANTSLT/LA23 pin is described in
the Multi-Function Pin section.
6
5
4
TXDLEN
TXCMEN
RXCEN
0
0
0
TXDATA Enable. TXDLEN, the TXDLFN bit of TCR30, and the
PCMCIA pin are used to determine the direction of the TXDATA/
LA20 pin.
The control of the function of the TXDATA/LA20 pin is described in
the Multi-Function Pin section.
TXCMD Enable. TXCMEN, the TXCMFN bit of TCR30, the RCEN
bit of TIR11 and the PCMCIA pin are used to determine the direc-
tion of the TXCMD/LA21 pin.
The control of the function of the TXCMD/LA21 pin is described in
the Multi-Function Pin section.
RXC Enable. RXCEN is used with RXCFN (TCR28[7]), the ISA
PnP interrupt level select register, the ISA PnP interrupt type regis-
ter, and the PCMCIA pin to determine the function of the RXC/
IRQ10 pin.
The control of the function of the RXC/IRQ10 pin is described in the
Multi-Function Pin section.
3
USER6EN
0
USER6 Enable. USER6EN, the USER6FN bit of TCR15, the ISA
PnP interrupt level select register, the ISA PnP interrupt type regis-
ter, and the PCMCIA pin are used to determine the function of the
USER6IRQ5 pin.
The control of the function of the USER6/IRQ5 pin is described in
the Multi-Function Pin section.
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In addition to these bits, the USER6/IRQ5 pin may be used to pro-
duce interrupts to the 80188 embedded controller. This capability is
controlled by the ENXSDF bit of TCR28 and the SDFU bit of TIR5
and operates independently of the bits in the table above.
2
USER5EN
0
USER5 Enable. USER5EN, the USER5FN bit of TCR15, the ISA
PnP interrupt level select register, the ISA PnP interrupt type regis-
ter, and the PCMCIA pin are used to determine the function of the
USER5IRQ4 pin.
The control of the function of the USER5/IRQ4 pin is described in
the Multi-Function Pin section.
In addition to these bits, the USER5/IRQ4 pin may be used to pro-
duce interrupts to the 80188 embedded controller. This capability is
controlled by the ENXCHBSY bit of TCR28 and the CHBSYCU bit
of TIR5 and operates independently of the bits in the table above.
1
0
ACTEN
1
1
Activity LED Enable. This bit can be used to control the ACT LED
output. The control of the function of the ACT pin is described in the
Multi-Function Pin section.
STSCHGFN
STSCHG Function. This bit is used to determine the function of the
STSCHG pin. When this bit is set to a 1, then the value of the
STSCHG pin is equal to the NAND result of the MIR9 STSCHGD bit
value and the PCMCIA CCSR WAKEUP bit value. When this bit is
set to a 0, then the value of the STSCHG pin is equal to the inver-
sion of the MIR9 STSCHGD bit value. THIS FUNCTION IS ONLY
AVAILABLE IN PCMCIA MODE.
The complete control of the function of the STSCHG/BALE pin is
described in the Multi-Function Pin section.
TCR16: Baud Detect Start
This register is the Baud Detect Start register. This reg-
ister is used to program the start time for the Baud de-
tection circuit. The start time is compared against the
current value of the antenna diversity timer and the baud
detect test begins when the compare is TRUE. Note that
the antenna diversity timer is a count down timer with an
initial value specified in TCR4. If the automatic antenna
diversity logic is disabled, then the antenna diversity
timer continues to run and provide a reference point for
the start of the Baud Detect Start value.
CONFIGURATION REGISTER INDEX:
10h
Bit
Name
Reset Value
Description
7–6
5–0
Reserved
BDS[5:0]
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
00h
Baud Detect Start. The value in this register is used to determine
when the baud detection circuit will begin examining incoming RXD
data. The baud detection begins when the antenna diversity timer
of TCR4 reaches the value specified here as BDS[5:0]. The an-
tenna diversity timer is a count down timer operating at a resolution
equal to 20 times the CLKIN period when the CLKGT20 bit of MIR9
is set to 0 and a resolution equal to 40 times the CLKIN period when
the CLKGT20 bit of MIR9 is set to 1. For a 1 Mbs data rate with
CLKIN = 20 MHz and CLKGT20 = 0, the resolution is 1 µ.
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TCR17: Baud Detect Lower Limit
This register is the Baud Detect Lower Limit
register (TCR17).
CONFIGURATION REGISTER INDEX:
11h
Bit
Name
Reset Value
Description
7–6
5–0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
BDLLT[5:0]
00h
Baud Detect Lower Limit. This register is used to program the lower
limit for the Baud detection circuit. The lower limit defines the short-
est time between like transitions (i.e., rising edge to rising edge or
falling edge to falling edge) that is expected for a given baud rate. If
like transitions are separated by values below this limit, then the
baud detect test for that pair of like transitions will fail.
Note that the rising edge baud counter will begin counting from 0
and when it reaches a value of 29, the next increment will cause the
counter to wrap to a value of 10 decimal. The falling edge baud
counter operates in an identical manner. Therefore, rising edges
that are separated by 20, 40, 60, 80, etc. CLKIN periods (with
CLKGT20=0 each baud tick is one CLKIN period, with
CLKGT20=1, each baud tick is two CLKIN periods) will all yield a
rising edge baud counter value of 20. The same is true for the falling
edge baud counter. This information should be used to appropri-
ately program the Baud Detect Lower Limit register.
The resolution of the value in this register is the period of the CLKIN
signal when the CLKGT20 bit of MIR9 is set to 0 or twice the period
of the CLKIN signal when the CLKGT20 bit of MIR9 is set to 1. With
CLKIN = 20 MHz and CLKGT20=0, a value of 14h (=20 decimal)
represents the nominal pulse width value for 1 Mbit/s network data
rate operation.
TCR18: Baud Detect Upper Limit.
This register is the Baud Detect Upper Limit register.
CONFIGURATION REGISTER INDEX:
12h
Bit
Name
Reset Value
Description
7–6
5–0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
BDULT[5:0]
00h
Baud Detect Upper Limit. This register is used to program the upper
limit for the Baud detection circuit. The upper limit defines the long-
est time between like transitions (i.e., rising edge to rising edge or
falling edge to falling edge) that is expected for a given baud rate. If
like transitions are separated by values above this limit, then the
baud detect test for that pair of like transitions will fail.
Note that the rising edge baud counter will begin counting from 0
and when it reaches a value of 29, the next increment will cause the
counter to wrap to a value of 10 decimal. The falling edge baud
counter operates in an identical manner. Therefore rising edges
that are separated by 20, 40, 60, 80, etc. CLKIN periods (with
CLKGT20=0 each baud tick is one CLKIN period, with
CLKGT20=1, each baud tick is two CLKIN periods) will all yield a
rising edge baud counter value of 20. The same is true for the falling
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edge baud counter. This information should be used to appropri-
ately program the Baud Detect Upper Limit register.
The resolution of the value in this register is the period of the CLKIN
signal when the CLKGT20 bit of MIR9 is set to 0 or twice the period
of the CLKIN signal when the CLKGT20 bit of MIR9 is set to 1. With
CLKIN = 20 MHz and CLKGT20=0, a value of 14h (=20 decimal)
represents the nominal like transition separation value for a 1Mbit/s
network data rate.
TCR19: Baud Detect Accept Count for Carrier Sense
This register is the Baud Detect Accept Count for Carrier
Sense register. When the number of positive baud de-
tect test results in the baud detection circuit reaches the
value in this register, then the total number of tests taken
to that point will be considered adequate to make a valid
determination of positive carrier sense. The number of
positive baud detect test results is reset to 0 each time
that the antenna selection is changed.
CONFIGURATION REGISTER INDEX:
13h
Bit
Name
Reset Value
Description
7–6
5–0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
BDCS[5:0]
00h
Baud Detect accept count for Carrier Sense. When the number of
positive baud detect test results in the baud detection circuit
reaches the value in this register, then the total number of tests
taken to that point will be considered adequate to make a valid de-
termination of positive carrier sense. The number of positive baud
detect test results is reset to 0 each time that the antenna selection
is changed.
TCR20: Baud Detect Accept Count for Stop Diversity
This register is the Baud Detect Accept Count for Stop
Diversityregister. Whenthenumberofpositivebaudde-
tect test results in the baud detection circuit reaches the
value in this register, then the total number of tests taken
to that point will be considered adequate to make a valid
determination of satisfactory antenna selection. The
number of positive baud detect test results is reset to 0
each time that the antenna selection is changed.
CONFIGURATION REGISTER INDEX:
14h
Bit
Name
Reset Value
Description
7–6
5–0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce unde-
fined data.
BDSD[5:0]
00h
Baud Detect accept count for Stop Diversity. When the number of
positive baud detect test results in the baud detection circuit
reaches the value in this register, then the total number of tests
taken to that point will be considered adequate to make a valid de-
termination of satisfactory antenna selection. The number of posi-
tive baud detect test results is reset to 0 each time that the antenna
selection is changed.
TCR21: Baud Detect Ratio
This register is the Baud Detect Ratio register. This reg-
ister is used to set the ratio of good to bad baud detec-
tions which will be used as the minimum ratio to
determine that a valid signal is present on the medium.
The value in this register is treated as a radix 2 positive
real number with two decimal places. The lowest practi-
cal value possible is 0.25 (=00.01) and the highest prac-
tical value is 3.75 (=11.11).
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15h
CONFIGURATION REGISTER INDEX:
Bit
Name
Reset Value
Description
3–0
BDRN[3:0]
0h
Baud Detect Ratio. These bits are used to set the ratio of good to
bad baud detections which will be used as the minimum ratio to de-
termine that a valid signal is present on the medium. The value in
this register is treated as a radix 2 positive real number with two
decimalplaces. Thelowestpracticalvaluepossibleis0.25(=00.01)
and the highest practical value is 3.75 (=11.11).
TCR22: Baud Detect Accept Count
ThisregisteristheBaudDetectAcceptCountregister. A
read-only register that indicates the current number of
good transitions detected by the baud detector.
CONFIGURATION REGISTER INDEX:
16h
Bit
Name
Reset Value
Description
7–6
5–0
Reserved
ACPT[5:0]
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
00h
Accept[5:0] The value of these bits indicates the current number
of good transitions detected by the baud detector. This is a
read-only register.
TCR23: Baud Detect Fail Count
This register is the Baud Detect Fail Count register. A
read-only register that indicates the current number of
bad transitions detected by the baud detector.
CONFIGURATION REGISTER INDEX:
17h
Bit
Name
Reset Value
Description
7–6
5–0
Reserved
FAIL[5:0]
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
00h
Fail[5:0] The value of these bits indicates the current number of
bad transitions detected by the baud detector. This is a
read-only register.
TCR24: RSSI Sample Start
This register is the RSSI Sample Start register. The
value in this register is used to determine when to cap-
ture a sample of the RSSI input for A/D conversion dur-
ing antenna diversity operation. The register value is a
measure of the time of RSSI sample relative to the an-
tenna switching event. A register value of 0 means that
no RSSI samples will be taken.
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18h
CONFIGURATION REGISTER INDEX:
Bit
Name
Reset Value
Description
7:6
5:0
Reserved
SS[5:0]
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
00h
RSSI Sample Start. The value in this register is used to determine
when to capture a sample of the RSSI input for A/D conversion dur-
ing antenna diversity operation. The register value is a measure of
the time of RSSI sample relative to the end of the current antenna
dwell time (i.e., SS=03h implies that the RSSI sample will be con-
verted at 3 µs before the current antenna dwell time ends).
The resolution of the RSSI sample timer is equal to 20 times the
CLKIN period when the CLKGT20 bit of MIR9 is set to 0 and is equal
to 40 times the CLKIN period when the CLKGT20 bit of MIR9 is set
to 1. For a 1 Mbs data rate with CLKIN = 20 MHz and CLKGT20 = 0,
the resolution is 1 µ. With CLKIN=20 MHz and CLKGT20 = 0, a
value of SS[5:0] = 00100 means that the RSSI sample will be taken
4 µ before the next antenna switch event occurs. A register value of
0 means that no RSSI samples will be taken.
The time value represented by the bits in SS[5:0] must be less than
the time value of the bits in the ADT[5:0] field of TCR4 minus the
time value of the bits of the A2DT[3:0] field of TCR25 minus 9
CLKIN periods (18 CLKIN periods if CLKGT20=1).
TCR25: RSSI Configuration
This register is the RSSI Configuration register.
This register is used to setup some A/D
converter parameters.
CONFIGURATION REGISTER INDEX:
19h
Bit
Name
Reset Value
Description
7
UXA2DST
0
Use external A/D conversion Start signal. When UXA2DST is set to
0, then the A/D conversion process starts when the Antenna Dwell
timer reaches the value programmed in the SS bits of TCR24.
When UXA2DST is set to 1, then an external stimulus from the
USER6/IRQ5/EXTA2DSTpinisrequiredtobegineachA/Dconver-
sion cycle. Rising edges of USER6/IRQ5/EXTA2DST initiate new
conversion cycles. A/D sample and conversion timing will proceed
as programmed in the TCR25 register A2DT field.
6
5
ENEXT
0
Enable External. Setting ENEXT to a 1 enables the external A/D
mode of the Am79C930 device, allowing the Am79C930 device to
use the digital values supplied by an external A/D converter in CCA
and antenna diversity decisions. ENEXT is used in conjunction with
ENSAR (TCR25[5]) and ADDA (TIR26[2]) to configure the
Am79C930 device A/D mode according to the table listed in section
RSSI A/D Unit.
ENSAR
0
–
Enable SAR. Setting ENSAR to a 1 enables the SAR[6:0] pins to
drive as outputs. ENSAR is used in conjunction with ENINT
(TCR25[6]) and ADDA (TIR26[2]) to configure the Am79C930 de-
vice A/D mode according to the table listed in the RSSI A/D unit de-
scription of in section RSSI A/D Unit.
4
Reserved
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
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3–0
A2DT[3:0]
1010b
A/D sampling Time[3:0]. The value in the A2DT[3:0] field deter-
mines the duration of time required to convert the A/D input. Each
bit of resolution is equal to 4 times the CLKIN period when the
CLKGT20 bit of MIR9 is set to 0 and is equal to 8 times the CLKIN
period when the CLKGT20 bit of MIR9 is set to 1. For a 1Mbs data
rate with CLKIN = 20 MHz and CLKGT20 = 0, the resolution is 200
n. The A2DT value is used by all A/D modes, including the mode
that uses the internal A/D converter. The internal A/D converter
requires 600 nsec to convert – note that the default value of this reg-
ister is 2.0 µs for a CLKIN equal to 20MHz with the CLKGT20 bit set
to 0.
Note that the actual time for conversion is less than the A2DT pro-
grammed value by 1.5 CLKIN periods (with CLKGT20=0, it is 3
CLKINperiodsifCLKGT20=1). Thisfactisimportantwhenusingan
external A/D converter in the external A/D mode.
Minimum value in the A2DT[3:0] field must be 0001. A value of 0000
is not allowed.
ADT[5:0]=TCR4[5:0]
ANTSLT
3 X tA
CCA_TEST
(Internal Signal)
SS[5:0]=TCR24[5:0]
START_A2D
(Internal Signal)
A2DT[3:0]=TCR25[3:0]+4 X tA
2 X tA
CACT=TIR27[7]
SAR[ 6:0]
When ENSAR = 1
tA
1 X tA
ADIN1
(when ENEXT=1)
6 X tA
6 X tA
3 X tA
3 X tA
ADIN2
(when ENEXT=1)
SAR_LATCH
(Internal Signal)
tA = period of CLKIN when CLKGT20 = 0
tA = (period of CLKIN) X 2 when CLKGT20 = 1
20138B-9
Note: ADIN1, ADIN2, and SAR_LATCH signals are only valid as shown when ENEXT (TCR25[6]) has been set to a 1.
Figure 3. Analog-to-Digital State Machine Timing
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TCR26: Reserved
This register is the TAI reserved location register.
CONFIGURATION REGISTER INDEX: 1Ah
Bit
Name
Reset Value
Description
7–0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
TCR27: TIP LED Scramble
This register is the Network Interface Polarity register.
This register is used to set the polarity of some of the
transceiver interface output pins.
CONFIGURATION REGISTER INDEX:
1Bh
Bit
Name
Reset Value
Description
7
DISRNR
0
Disable RUNERR. When DISRNR is set to a 1, then the RUNERR
bit of TCR11 will always be held at a 0 value. When DISRNR is set
to a 0, then the RUNERR bit of TCR11 will function as described in
the TCR11 bit description.
6
5
4
Reserved
Reserved
LNKDR
–
0
0
Reserved. Must be written as a 0. Reads of these bits produce
undefined data.
Reserved. Must be written as a 0. Reads of these bits produce
undefined data.
LNK pin drive. When set to a 0, the drive of theLNK pin will be open
drain. When set to a 1, the drive of the LNK pin will be totem pole,
i.e., both high and low output values will be driven.
Complete control of the function of the LNK pin is described in the
Multi-Function Pin section.
3
2
ACTDR
0
0
ACT pin drive. When set to a 0, the drive of theACT pin will be open
drain. When set to a 1, the drive of the ACT pin will be totem pole,
i.e., both high and low output values will be driven.
Complete control of the function of the ACT pin is described in the
Multi-Function Pin section.
FDETPOL
FDET Polarity. When this bit is set to a 0, then the polarity of the
FDET output will be low assert, such that when the SFD pattern has
been recognized in the incoming receive data stream or the outgo-
ing transmit data stream, theFDET pin will be driven to a LOW logic
level. When this bit is set to a 1, then the polarity of theFDET output
will be high assert, such that when the SFD pattern has been recog-
nized in the incoming receive data stream or the outgoing transmit
data stream, the FDET pin will be driven to a HIGH logic level.
1
TXPEPOL
0
0
TXPE Polarity. When this bit is set to a 0, then the polarity of the
TXPE output will be low assert, such that when the TGAP1 counter
expires, the TXPE pin will be driven to a LOW logic level. When this
bit is set to a 1, then the polarity of the TXPE output will be high as-
sert, such that when the TGAP1 counter expires, the TXPE pin will
be driven to a HIGH logic level.
0
TXMODPOL
TXMOD Polarity. When this bit is set to a 0, then the polarity of the
TXMOD output will be low assert, such that when the TGAP2
counter expires, the TXMOD pin will be driven to a LOW logic level.
When this bit is set to a 1, then the polarity of theTXMOD output will
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be high assert, such that when the TGAP2 counter expires, the
TXMOD pin will be driven to a HIGH logic level.
TCR28: Clear Channel Assessment Configuration
This register is the Clear Channel Assessment
Configuration register. The bits in this register are used
to determine which features will be used to determine
clear channel assessment.
CONFIGURATION REGISTER INDEX:
1Ch
Bit
Name
Reset Value
Description
7
RXCFN
0
RXC Function. When RXCFN is set to a 1, then the RXC pin will be
driven with the internal RXC clock value, regardless of its source.
That is, the RXC source may be either the result of the DPLL locking
operation, or it may directly reflect the value of the RXCIN pin, de-
pending upon the selection of the ECLK bit of TCR2.
Complete control of the function of the RXC/IRQ10 pin is described
in the Multi-Function Pin section.
6
ENXSDF
0
Enable External Start Delimiter Found. When ENXSDF is set to a 1,
then the internal SDF result is not used. Instead, the value of the
USER6/IRQ5 pin is used as the source for SDF indication. When
ENXSDF is set to 1, then changes to the value of the USER6/IRQ5
pin are used to determine the status of the SDF interrupt of TIR5 (bit
2). When ENXSDF is set to 0, then the source for SDF indication is
the internal SDF determination logic. The current drive and function
settings for the USER6/IRQ5 pin have no effect on the use of the
value of this pin for the SDF function.
5
ENXCHBSY
0
Enable External CHBSY. When ENXCHBSY is set to a 1, then the
internal CCA result is not used. Instead, the value of the
USER5/IRQ4 pin is used as the source for CCA information. When
ENXCHBSY is set to 1, the value of the USER5/IRQ4 pin is used to
set the value of the CHBSY bit of TIR26 (bit 7), and changes to
the value of the USER5/IRQ4 pin are used to determine the status
of the CHBSYC interrupt of TIR4 (bit 7) and the BCF interrupt bit
of TIR5.
When ENXCHBSY is set to a 1, then antenna diversity switching is
disabled and the receive function of the Am79C930 device must be
enabled by a positive indication of SDF on the USER6/IRQ5
input pin.
When ENXCHBSY is set to 0, then the source for CCA indication is
the internal CCA determination logic. The current drive andfunction
settings for the USER6/IRQ5 pin have no effect on the use of the
value of this pin for the SDF function.
4
RUPD
0
Receive Use Preamble Detect. When RUPD is set to a 1, then the
stop diversity decision is used to enable the receive state machine.
That is, when the decision is made to stop switching antenna selec-
tions, then the receive state machine will enable the receive data
path to the RX FIFO. When RUPD is reset to a 0, then the receive
data path to the RX FIFO is enabled when SFD is detected.
3
2
STPEN
UBDSD
0
0
Stop Antenna Diversity Enable. Setting this bit to a 1 allows
the clear channel assessment logic to stop the antenna
diversity operation.
Use Baud Detect of Stop Diversity in Antenna Diversity decision.
When this bit is set to a 1, the Baud Detect Count for Stop Diversity
becomes one input to the stop diversity decision logic. When this bit
Am79C930
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is set to a 0, the Baud Detect Count for Stop Diversity is not used in
the stop diversity decision logic.
1
0
UBDCS
URSSI
0
0
Use Baud Detect of Carrier Sense in CCA decision. When this bit is
set to a 1, the Baud Detect Count for Carrier Sense becomes one
input to the clear channel assessment logic. When this bit is set to a
0, the Baud Detect Count for Carrier Sense is not used in the clear
channel assessment decision.
Use RSSI in CCA and Stop Diversity decisions. When this bit is set
to a 1, the RSSI converted value comparison to the RSSI lower limit
becomes one input to the clear channel assessment logic and also
becomes one input to the Stop Diversity decision logic. When this
bit is set to a 0, the RSSI converted value comparison to the RSSI
lower limit is not used in the clear channel assessment logic and is
also not used in the Stop Diversity decision logic.
TCR29: Reserved
This register is a TAI reserved location.
CONFIGURATION REGISTER INDEX:
1Dh
Bit
Name
Reset Value
Description
7–0
Reserved
–
Reserved. Must be written as a 0. Reads of this bit produce
undefined data.
TCR30: Pin Function and Data Rate
This register is the Pin Function and Data Rate control
register. This register contains bits that control the
function of the ANTSLT, TXDATA, TXCMD, and TXC
pins as well as control bits to set the network data rate.
CONFIGURATION REGISTER INDEX:
1Eh
Bit
Name
Reset Value
Description
7
ANTSLTLFN
0
ANTSLT Function. ANTSLTLFN, ANTSLTLEN (TCR15[7]),
ANTSEN (TIR26[3]), and the PCMCIA pin are used to determine
the direction and data of the ANTSLT pin.
The control of the function of the ANTSLT/LA23 pin is described in
the Multi-Function Pin section.
6
TXDLFN
0
TXDATA Function. TXDLFN, TXDLEN (TCR15[6]), and the
PCMCIA pin are used to determine the direction and data of the
TXDATA pin.
The control of the function of the TXDATA/LA23 pin is described in
the Multi-Function Pin section.
5
4
TXCMFN
0
–
TXCMD Function. TXCMFN, TXCMEN (TCR15[5]), RCEN
(TIR11[3]), and the PCMCIA pin are used to determine the function
of the TXCMD pin.
USER7FN
Reserved. Must be written as 0. Reads of this produce
undefined data.
The control of the function of the TXCMD/LA21 pin is described in
the Multi-Function Pin section.
3
TXCIN
1
TXC Input. When set to a 0, the TXC pin functions as an output, pro-
viding a divide by X version of the CLKIN input, where X is deter-
mined by the setting of the DR bits of TCR30. When set to a 1, the
TXC pin functions as an input, allowing the data rate of the transmit
operations to be set by an external source. When TXCIN is set to 1,
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then a 16-bit deep serial FIFO is inserted into the TX data path. This
FIFO allows for some mismatch to be tolerated in the clock rates
between the Am79C930 internal transmit clock and the external
TXC clock that is connected to the TXC input. Because of this inter-
nal FIFO, the appearance of transmit data from the setting of the
TXS bit in TIR8 will be delayed by 8 bit times whenever the TXCIN
bit has the value of 1.
The control of the function of the TXC pin is described in the Multi-
Function Pin section.
2:0
DR[2:0]
001b
Data Rate. The value in this register determines the data rate for the
network. The TXC output pin will be affected. The following inter-
pretations have been assigned to these bits:
DR[2:0]
TCR30[2:0]
CLKGT20
MIR9[7]
Network
Data Rate
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
reserved
fCLKIN÷20
fCLKIN÷40
fCLKIN÷80
reserved
fCLKIN÷200
fCLKIN÷2000
reserved
fCLKIN÷20
fCLKIN÷40
fCLKIN÷80
fCLKIN÷160
reserved
fCLKIN÷400
fCLKIN÷4000
reserved
The Data Rate bits are used together with the CLKGT20 bit to con-
trol clock divider circuits in the DPLL section of the TAI and in the
Transmit State machine section of the TAI. Specifically, the DPLL
clock source will always be set at a rate of 20 times the desired Net-
work Data rate in order to provide the appropriate amount of over-
sampling to insure proper DPLL tracking of the incoming signal.
The Transmit State machine section of the TAI logic will receive a
divided clock that is equal to the desired Network Data Rate.
Note that if the CLKIN frequency is greater than 20 MHz, then the
CLKGT20 bit must be set to 1.
TCR31: Device Revision
This register is the Device Revision register.
CONFIGURATION REGISTER INDEX:
1Fh
Bit
Name
Reset Value
Description
7–0
REV[7:0]
01h
Revision Number. The value in this field contains the revision num-
ber for the current device. The lowest revision number is 01h.
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PCMCIA Configuration Option Register
PCMCIA CCR Registers and PCMCIA
CIS Space
This register is used to configure the Am79C930 device
and to issue a soft reset to the Am79C930 device.
The PCMCIA Configuration Option Register is located
at the fixed attribute memory location 0802h. Therefore,
the information programmed into the CIS must give the
value 2K (=0800h) as the Card Configuration Registers
Base Address in the TPCC_RADR field of the Configu-
ration Tuple. The Configuration Option Register is lo-
cated at TPCC_RADR + 2.
Two bytes of attribute memory space have been
used by the Am79C930 device for storage of two card
configuration registers. These two registers are found
at attribute memory locations 800h and 802h. The
Configuration Option Register is located at Attribute
memory location 800h and the Card Configuration
and Status Register is located at Attribute memory
location 802h.
The following tables indicate the bits that are supported
in the Configuration Option Registers:
Because the location of these registers is fixed at 800h
and 802 in attribute memory space, then the value of the
CCROffsetlocatedintheTPCC_RADRfieldoftheCon-
figuration Tuple must be equal to 800h.
Bit
Name
Reset Value
Description
7
SRESET
0
Resets Am79C930 device. Setting this bit to 1 places the
Am79C930 device into the reset state, which is equivalent to the as-
sertion of the PCMCIA RESET signal. This bit does not reset itself
back to 0.
6
LevelReq
0
0
Level Mode Interrupts when LevelReq = 1. Pulse Mode Interrupts
when LevelReq = 0.
5:0
Conf Index
Configuration Index. This field is written with the index number of
the entry in the card’s Configuration Table which the system
chooses for this card. When Conf Index = “00000,” then the
Am79C930 device is in memory only mode. When any of these five
bits is set to 1, then the I/O interface is enabled, meaning that I/O
transfers are allowed.
PCMCIA Card Configuration and Status Register
This register contains information about the
card’s condition.
Therefore, the information programmed into the CIS
must give the value 2K (=0800h) as the Card Configura-
tionRegistersBaseAddressintheTPCC_RADRfieldof
the Configuration Tuple. The Card Configuration and
Status Register is located at TPCC_RADR + 2.
The PCMCIA Card Configuration and Status Register is
located at the fixed attribute memory location 0802h.
Bit
Name
Reset Value
Description
7:6
5
Reserved
IOIS8
–
0
Read only as a 0.
This bit is written by the host to indicate that the host is only capable
of 8-bit I/O accesses. This bit is ignored by the Am79C930 device,
since the Am79C930 device is only capable of 8-bit I/O accesses.
4
Wakeup
0
WAKEUP is used with the STSCHGFN bit of TCR15 to determine
the function of the STSCHG pin. When the STSCHGFN bit of
TCR15 is set to 1, then the WAKEUP bit is NANDed with the value
of the STSCHGD bit of MIR8 and the result is driven onto the
STSCHG pin.
When the STSCHGFN bit of TCR15 is set to 0, then the STSCHG
pin becomes an output that is controlled by the STSCHGD bit
of MIR8.
3
2
Read-back
0
0
Read/Write bit – serves no other function.
Power Down
Requests the 80188 to enter power down mode. If already in power
down mode, this bit will indicate 1. When written with a 1, value read
will remain 0 until the device actually enters the power down mode.
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When written with a 1, the PWRDWN bit generates an interrupt to
the 80188, requesting that the 80188 core place the Am79C930 de-
vice into the power down state. The interrupt is signaled in MIR0, bit
5. If written with a 0 while in power down mode, power down mode is
exited. When written with a 1, value read will remain 0 until the de-
vice actually enters the power down mode.
1
0
Interrupt
–
–
Represents the internal interrupt level. This signal remains true un-
til the interrupt has been serviced (not pulse generated).
Reserved
Read only as a 0.
PCMCIA Card Information Structure (CIS)
The PCMCIA CIS space has been allocated to reside in
the flash memory space of a design based on the
Am79C930 device. This space corresponds to 1K–16
bytes of the uppermost 1K of flash memory. Since only
even addressed bytes of attribute memory space are
defined to exist in the PCMCIA specification, only even
addressesofthe2K–32CISrangewillmapintotheflash
memory, and hence, the 2K–32 address range for the
Am79C930 CIS space is mapped to only 1K–16 bytes of
flash space.
Note that the address range is limited to 2K–32 rather
than a complete 2K of space. This is because the upper-
most 16 bytes of the flash memory must be reserved for
the initial instructions for the 80188 core, since the
80188 core will automatically access these locations for
its initial instruction fetch following a Am79C930 device
reset operation.
Am79C930
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ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature: . . . . . . . . . . . . –65 to +150°C
Ambient Temperature Under Bias: . . . –65 to +125°C
Commercial (C) Devices
Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C
Supply Voltage to AVSS
Supply Voltages
or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.3 to +6 V
(AVDD, VCC, VDDT, VDDU1, VDDU2, VDDM, VDDP, VDD5)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5 V ± 5%
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect
device reliability.
All inputs within the range: . . . . . AVSS – 0.5 V ≤ VIN ≤
AVDD + 0.5 V, or
DVSS – 0.5 V ≤ VIN ≤
DVDD + 0.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS
5.0 V Am79C930 DC Characteristics
Parameter
Symbol
Parameter Description
Input LOW Voltage
Test Conditions
Min
Max
Units
VIL
0.8
V
V
V
VIH
Input HIGH Voltage
Output LOW Voltage
2.0
VOL
IOL1 = 4 mA
IOL2 = 12 mA
IOL3 = 24 mA
(Note 1, 5)
0.45
0.45
0.45
VOH
Output HIGH Voltage (Note 2)
IOH = –.4 mA (Note 5)
IOL = 0.2 mA
2.8
V
V
VOLC
Output LOW Voltage for
CMOS only load
0.1 X VDD
VOHC
Output HIGH Voltage for
CMOS only load
IOH = –0.2 mA
0.9 X VDD
V
IIX
Input Leakage Current (Note 3)
XTAL1 Input LOW Voltage Threshold
XTAL1 Input HIGH Voltage Threshold
XTAL1 Input LOW Current
VDD = 5 V, VIN = 0 V
VIN = External Clock
VIN = External Clock
VIN = External Clock (Active)
VIN = VSS (Power Down)
VIN = External Clock (Active)
VIN = VDD (Power Down)
VOUT = 0.4 V
–10
–0.5
3.5
10
0.8
µA
V
VILX
VIHX
IILX
VDD + 0.5
–100
+10
V
µA
µA
µA
µA
µA
µA
mA
–10
–10
IIHX
XTAL1 Input HIGH Current
100
400
IOZL
IOZH
IDDF
Output Leakage Current (Note 4)
Output Leakage Current (Note 4)
Power Supply Current
VOUT = VDD
10
CLKIN = 40 MHz,
150
PMX1 = 32.768 kHz
IDDS
Power Supply Current
Power Supply Current
CLKIN = 20 MHz,
PMX1 = 32.768 kHz
85
45
mA
mA
IDDPD1
Power Down mode
CLKIN = internally cutoff,
PMX1 = 32.768 kHz,
no host interface
accesses occurring
VIN ≤ VIL or VIN ≥ VIH
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DC CHARACTERISTICS (continued)
5.0 V Am79C930 DC Characteristics
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Units
IDDPD2
Power Supply Current
Power Down mode
CLKIN = internally cutoff,
PMX1 = 32.768 kHz,
no host interface
40
mA
accesses occurring
VIN ≤ VOL or VIN ≥ VOH
IDDPD3
Power Supply Current
Power Down mode
CLKIN = internally cutoff,
PMX1 = 32.768 kHz,
no host interface
900
µA
accesses occurring
VIN ≤ VOLC or VIN ≥ VOHC
CIN
CO
Input Pin Capacitance
FC = 1 MHz (Note 6)
FC = 1 MHz (Note 6)
FC = 1 MHz (Note 6)
12
12
12
pF
pF
pF
I/O or Output Pin Capacitance
BCLK Pin Capacitance
CCLK
Notes:
1. IOL1 = 4mA applies to the following pins: STSCHG, PWRDWN, MA[16:0], MD[7:0], FCE, SCE, XCE, MOE, MWE, TDO,
LFPE, LFCLK, LLOCKE, HFPE, INPACK, HFCLK, ANTSLT, ANTSLT, TXCMD, TXCMD, TXPE, TXDATA, TXDATA,
TXMOD, RXPE, FDET, SDCLK, SDDATA, SDSEL[3:1], SAR[6:0], USER[4:2], USER[0], TXC, ADIN1, ADIN2.
IOL2 = 12 mA applies to the following pins: ACT, LNK
IOL3 = 24 mA applies to the following pins: D[7:0], WAIT, IREQ, USER5, USER6, RXC, USER7, USER[1]
2. VOH does not apply to open-drain output pins.
3. Does not apply to PMX1, PMX2, and ADREF.
4. IOZH and IOZL apply to all three-state output pins and bidirectional pins.
5. Outputs are CMOS and will be driven to rail if the load is not resistive to supply.
6. Not 100% tested. Value determined by characterization.
Am79C930
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ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature: . . . . . . . . . . . . –65 to +150°C
Ambient Temperature Under Bias: . . . –65 to +125°C
Commercial (C) Devices
Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C
Supply Voltage to AVSS
or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.3 to +6 V
Supply Voltages (AVDD, VCC, VDDT, VDDU1, VDDU2, VDDM,
VDDP, VDD5) . . . . . . . . . . . . . . . . . . . . . . 3.0 V to 3.6 V
Supply Voltages
(AVDD, VDD5) . . . . . . . . . . . . . . . . . . . . . . . . +5 V ± 5%
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect
device reliability.
All inputs within the range: . . . . . AVSS – 0.5 V ≤ VIN ≤
AVDD + 0.5 V, or
DVSS – 0.5 V ≤ VIN ≤
DVDD + 0.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
3.3 V Am79C930 DC CHARACTERISTICS
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Units
VIL
VIH
VOL
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
–0.3
2.0
0.8
V
V
V
VDD + 0.3
IOL1 = 2.4 mA
IOL2 = 12 mA
IOL3 = 8 mA
(Note 1, 5)
0.4
0.4
0.4
VOH
Output HIGH Voltage (Note 2)
IOH = –0.4 mA (Note 5)
IOL = 0.2 mA
2.4
V
V
VOLC
Output LOW Voltage for
CMOS only load
VOHC
Output HIGH Voltage for
CMOS only load
IOL = –0.2 mA
VDD – 0.2
V
IIX
Input Leakage Current (Note 3)
XTAL1 Input LOW Voltage Threshold
XTAL1 Input HIGH Voltage Threshold
XTAL1 Input LOW Current
VDD = 5 V, VIN = 0 V
VIN = External Clock
VIN = External Clock
VIN = External Clock (Active)
VIN = DVSS (Power Down)
VIN = External Clock (Active)
VIN = VDD (Power Down)
VOUT = 0.4 V
–10
–0.5
3.5
10
0.8
µA
V
VILX
VIHX
IILX
VDD + 0.5
–100
+10
V
µA
µA
µA
µA
µA
µA
mA
–10
–10
IIHX
XTAL1 Input HIGH Current
100
400
IOZL
IOZH
IDDF
Output Leakage Current (Note 4)
Output Leakage Current (Note 4)
Power Supply Current
VOUT = VDD
10
CLKIN = 40 MHz,
105
PMX1 = 32.768 kHz
IDDS
Power Supply Current
Power Supply Current
CLKIN = 20 MHz,
PMX1 = 32.768 kHz
60
15
mA
mA
IDDPD1
Power Down mode
CLKIN = internally cutoff,
PMX1 = 32.768 kHz,
no host interface
accesses occurring
VIN ≤ VIL or VIN ≥ VIH
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DC CHARACTERISTICS (continued)
3.3 V Am79C930 DC Characteristics
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Units
IDDPD2
Power Supply Current
Power Down mode
CLKIN = internally cutoff,
PMX1 = 32.768 kHz,
no host interface
5
mA
accesses occurring
VIN ≤ VIL or VIN ≥ VOH
IDDPD3
Power Supply Current
Power Down mode
CLKIN = internally cutoff,
PMX1 = 32.768 kHz,
no host interface
900
µA
accesses occurring
VIN ≤ VOLC or VIN ≥ VOHC
CIN
CO
Input Pin Capacitance
FC = 1 MHz (Note 6)
FC = 1 MHz (Note 6)
FC = 1 MHz (Note 6)
12
12
12
pF
pF
pF
I/O or Output Pin Capacitance
BCLK Pin Capacitance
CCLK
Notes:
1. IOL1 = 2.4mA applies to the following pins: STSCHG, PWRDWN, MA[16:0], MD[7:0], FCE, SCE, XCE, MOE, MWE, TDO,
LFPE, LFCLK, LLOCKE, HFPE, INPACK, HFCLK, ANTSLT, ANTSLT, TXCMD, TXCMD, TXPE, TXDATA, TXDATA,
TXMOD, RXPE, FDET, SDCLK, SDDATA, SDSEL[3:1], SAR[6:0], USER[4:2], USER[0], TXC, ADIN1, ADIN2.
IOL2 = 12 mA applies to the following pins: ACT, LNK
IOL3 = 8 mA applies to the following pins: D[7:0], WAIT, IREQ, USER5, USER6, RXC, USER7, USER[1]
2. VOH does not apply to open-drain output pins.
3. Does not apply to PMX1, PMX2, and ADREF.
4. IOZH and IOZL apply to all three-state output pins and bidirectional pins.
5. Outputs are CMOS and will be driven to rail if the load is not resistive to supply.
6. Not 100% tested. Value determined by characterization.
Am79C930
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P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature: . . . . . . . . . . . . –65 to +150°C
Ambient Temperature Under Bias: . . . –65 to +125°C
Commercial (C) Devices
Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C
Supply Voltage to AVSS
or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.3 to +6 V
Supply Voltages (VCC, VDDT, VDDU1, VDDU2, VDDM, VDDP)
. . . . . . . . . . . . . . . . . . . . +5 V ± 5% or 3.0 V to 3.6 V
Supply Voltages
(AVDD, VDD5) . . . . . . . . . . . . . . . . . . . . . . . . +5 V ± 5%
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect
device reliability.
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
IEEE 1149.1 DC CHARACTERISTICS (5.0 and 3.3 V)
Parameter
Symbol
Parameter Description
TCK, TMS, TDI, TRST
TCK, TMS, TDI, TRST
TDO
Test Conditions
Min
2.0
2.4
Max
Units
V
VIL
0.8
VIH
V
VOL
VOH
IIL
IOL = 2.0 mA
0.4
V
TDO
IOH = –0.4 mA
V
TCK, TRST
TCK, TRST
TMS, TDI
VDD = 5.5 V, VI = 0.5 V
VDD = 5.5 V, VI = 2.7 V
VDD = 5.5 V, VI = 0.5 V
VDD = 5.5 V, VI = 2.7 V
VOUT = 0.4 V
–400
–200
–400
–200
µA
µA
µA
µA
µA
µA
IIH
IIL
IIH
TMS, TDI
IOZL
IOZH
TDO
–10
TDO
VOUT = VDD
+10
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P R E L I M I N A R Y
AC CHARACTERISTICS
OPERATING RANGES
Commercial (C) Devices
5.0 AND 3.3 V PCMCIA INTERFACE
Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (VCC, VDDT, VDDU1, VDDU2, VDDM, VDDP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 V to 5.25 V
Storage Temperature: . . . . . . . . . . . . –65 to +150*C
Ambient Temperature Under Bias: . . . –65 to +125*C
Supply Voltages
(AVDD, VDD5) . . . . . . . . . . . . . . . . . . . . . . . . +5 V ± 5%
Supply Voltage to AVSS
or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.3 to +6 V
All inputs within the range: VSS – 0.5 V ≤ VIN ≤ VDD + 0.1 X
VDD – where VSS and VDD are appropriate reference pins
for a given input pin. (See section on power supply
pin descriptions.)
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect
device reliability.
CL = 50 pF unless otherwise noted
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
PCMCIA MEMORY READ ACCESS
Parameter
Symbol
tAVQV
tAVGL
Parameter Description
Address access time
Address setup to OE ↓
Address hold from OE ↑
CE access time
Test Conditions
Min
0
Max
Unit
ns
Note 1
550
5
ns
tGHAX
tELQV
20
0
ns
Note 1
550
ns
tELGL
CE setup to OE ↓
0
ns
tGHEH
CE hold from OE ↑ (READ) or
CE hold from WE ↑ (WRITE)
20
0
ns
ns
ns
ns
ns
ns
ns
tGLQV
tGLWTV
tWTLWTH
tGLQNZ
tQVWTH
tGHQZ
OE acess time
Note 1
200
35
WAIT valid from OE ↓
WAIT pulse width
Notes 2, 3
Note 3
53 X TCLKIN
Data Bus driven from OE
Data setup to WAIT ↑
Data disabled from OE ↑
0
0
Note 3
90
Notes:
1. Assumes no wait state access is programmed.
2. The max value for this parameter assumes the following worst case situation:
Value
Worst Case
0
1
FLASH and SRAM wait states set at “3.”
Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2
PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3
4
Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
After completion of first embedded 80188 access to FLASH, posted PCMCIA WRITE executes to SRAM;
PCMCIA READ stycle is being held in wait state.
5
6
After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.
After completion of second embedded 80188 access to FLASH, PCMCIA READ cycle is allowed to proceed onto
memory bus to SRAM; host is still held in wait state.
7
At SRAM READ cycle completion, data is delivered to PCMCIA bus and wait state is exited.
3. Parameter is not included in production test.
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Test Conditions
PCMCIA MEMORY WRITE ACCESS
Parameter
Symbol
Parameter Description
Address setup to WE ↓
Address setup to WE ↑
Min
20
Max
Unit
ns
tAVWL
tAVWH
100
ns
tWMAX
Write recovery time
(Address hold from WE ↑ )
20
140
0
ns
ns
ns
tELWH
tELWL
tGHEH
CE setup to WE ↑
CE setup to WE ↓
CE hold from OE ↑ (READ) or CE
hold from WE ↑ (WRITE)
20
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tGHWL
tWHGL
OE setup to WE ↓
OE hold from WE ↑
WE pulse width
10
tWLWH
tWLWTV
tWTLWTH
tWTHWH
tDVWH
120
35
WAIT valid from WE ↓
WAIT pulse width
Notes 1, 2
53 X TCLKIN
WE hold from WAIT ↑
Data setup to WE ↑
Data hold from WE ↑
Data disabled from OE ↑
Data disabled from WE ↓
Data enabled from WE ↑
Data enabled from OE ↓
0
60
30
tWMDX
tGHQZ
Note 2
Note 2
Note 2
Note 2
90
90
tWLQZ
tWHQNZ
tGLQNZ
5
5
Notes:
1. The max value for this parameter assumes the following worst case situation:
Value
Worst Case
0
1
FLASH and SRAM wait states set at “3.”
Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2
PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3
4
Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
After completion of first embedded 80188 access to FLASH, posted PCMCIA WRITE executes to SRAM;
PCMCIA READ stycle is being held in wait state.
5
6
After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.
After completion of second embedded 80188 access to FLASH, PCMCIA READ cycle is allowed to proceed onto
memory bus to SRAM; host is still held in wait state.
7
At SRAM READ cycle completion, data is delivered to PCMCIA bus and wait state is exited.
2. Parameter is not included in production test.
132
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P R E L I M I N A R Y
Test Conditions
PCMCIA I/O READ ACCESS
Parameter
Symbol
Parameter Description
Address setup to IORD ↓
Address hold from IORD ↑
REG setup to IORD ↓
REG hold from IORD ↑
CE setup to IORD ↓
Min
70
20
5
Max
Unit
tAVIGL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIGHAX
tRGLIGL
tIGHRGH
tELIGL
0
5
tIGHEH
tIGLIGH
tIGLIAL
CE hold from IORD ↑
IORD width
20
165
0
INPACK ↓ delay from IORD ↓
INPACK ↑ delay from IORD ↑
WAIT ↓ delay from IORD ↓
WAIT width
45
tIGHIAH
tIGLWTL
tWTLWTH
tWTHQV
tIGLQNZ
tIGLQV
45
35
53 X TCLKIN
0
Notes 1, 2
Note 2
Data delay from WAIT ↑
Data enabled from IORD ↓
Data delay from IORD ↓
Data hold from IORD ↑
Data disabled from IORD ↑
0
0
100
20
tIGHQX
tIGHQZ
Note 2
Notes:
1. The max value for this parameter assumes the following worst case situation:
Value
Worst Case
0
1
FLASH and SRAM wait states set at “3.”
Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2
PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3
4
Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
After completion of first embedded 80188 access to FLASH, posted PCMCIA WRITE executes to SRAM;
PCMCIA READ stycle is being held in wait state.
5
6
After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.
After completion of second embedded 80188 access to FLASH, PCMCIA READ cycle is allowed to proceed
onto memory bus to SRAM; host is still held in wait state.
7
At SRAM READ cycle completion, data is delivered to PCMCIA bus and wait state is exited.
2. Parameter is not included in production test.
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P R E L I M I N A R Y
Test Conditions
PCMCIA I/O WRITE ACCESS
Parameter
Symbol
Parameter Description
Address setup to IOWR ↓
Address hold from IOWR ↑
REG setup to IOWR ↓
REG hold from IOWR ↑
CE setup to IOWR ↓
CE hold from IOWR ↑
IOWR width
Min
70
20
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVIWL
tIWHAX
tRGLIWL
tIWHRGH
tELIWL
0
5
tIWHEH
20
165
tIWLIWH
tIWLWTL
tWTLWTH
tWTHIWH
tDVIWL
WAIT ↓ delay from IOWR ↓
WAIT width
35
Notes 1, 2
53 X TCLKIN
IOWR ↑ from WAIT ↑
Data setup to IOWR ↓
Data hold from IOWR ↑
0
60
30
tIWHDX
Notes:
1. The max value for this parameter assumes the following worst case situation:
Value
Worst Case
0
1
FLASH and SRAM wait states set at “3.”
Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2
PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3
4
Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
After completion of first embedded 80188 access to FLASH, posted PCMCIA WRITE executes to SRAM;
PCMCIISA READ stycle is being held in wait state.
5
6
After completion of posted PCMCIA WRITE cycle, new embedded 80188 access to FLASH begins.
After completion of second embedded 80188 access to FLASH, PCMCIA READ cycle is allowed to proceed onto
memory bus to SRAM; host is still held in wait state.
7
At SRAM READ cycle completion, data is delivered to PCMCIA bus and wait state is exited.
2. Parameter is not included in production test.
134
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P R E L I M I N A R Y
AC CHARACTERISTICS
OPERATING RANGES
Commercial (C) Devices
5.0 AND 3.3 V ISA INTERFACE
Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (VCC,VDDT, VDDU1, VDDU2, VDDM, VDDP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 V to 5.25 V
Storage Temperature: . . . . . . . . . . . . –65 to +150°C
Ambient Temperature Under Bias: . . . –65 to +125°C
Supply Voltages
(AVDD, VDD5) . . . . . . . . . . . . . . . . . . . . . . . . +5 V ± 5%
Supply Voltage to AVSS
or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.3 to +6 V
All inputs within the range: VSS – 0.5 V ≤ VIN ≤ VDD + 0.1 X
VDD – where VSS and VDD are appropriate reference pins
for a given input pin. (See section on power supply
pin descriptions.)
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect
device reliability.
CL = 50 pF unless otherwise noted
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
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P R E L I M I N A R Y
Test Conditions
ISA ACCESS
Parameter
Symbol
Parameter Description
Min
60
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ti1
ti2
LA[23:17] valid setup to BALE ↓
BALE ↑ to BALE ↓ pulse width
LA[23:17] valid hold from BALE ↓
LA[23:17] valid setup to CMD ↓
SA[16:0] valid setup to CMD ↓
CMD ↓ to CMD ↑ pulse width
SA[16:0] valid setup to BALE ↓
Data valid delay from RCMD ↓
Data valid setup to WCMD ↓
SA[16:0] valid hold from CMD ↑
CMD ↑ to CMD ↓ pulse width
Data valid hold from RCMD ↑
Data valid hold from WCMD ↑
Data disabled from RCMD ↑
IOCHRDY ↓ delay from CMD ↓
25
ti3
12
ti4
Note 1
Note 1
Note 4
80
ti7
25
ti8
6*TCLKIN
20
ti9
ti10
ti11
ti12
ti13
ti14
ti15
ti16
ti20
ti21
Notes 2, 5, 6
Note 3
53 X TCLKIN
–75
20
55
0
Note 1
Note 1
Note 2
Note 3
20
Note 2, 6
Notes 1, 7
Notes 5, 6, 7
20
60
IOCHRDY ↓ to IOCHRDY ↑
0
130 +
pulse width
53 X TCLKIN
ti22
ti23
ti25
ti26
ti30
ti31
ti32
ti34
CMD ↑ delay from IOCHRDY ↑
BALE ↑ delay from CMD ↑
Notes 1, 7
Note 1
35
20
ns
ns
ns
ns
ns
ns
ns
ns
Data valid delay from IOCHRDY ↑ Note 7
–TCLKIN
–15
80
25
LA[23:17] valid hold from CMD ↓
AEN valid setup to CMD ↓
AEN valid hold from CMD ↑
AEN valid setup to BALE ↓
Data enabled from RCMD ↓
Note 1
Note 1
Note 1
15
60
Notes 2, 4
0
110
Notes:
1. CMD = one of: MEMR, MEMW, IOR or IOW.
2. RCMD = one of: MEMR, or IOR.
3. WCMD = one of: MEMW, or IOW.
4. If no wait states are incurred.
5. The max value for this parameter assumes the following worst case situation:
Value
Worst Case
0
1
FLASH and SRAM wait states set at “3.”
Host performs ISA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2
ISA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3
4
Host performs ISA READ cycle immediately following completion of ISA WRITE cycle.
After completion of first embedded 80188 access to FLASH, posted ISA WRITE executes to SRAM;
ISA READ stycle is being held in wait state.
5
6
After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.
After completion of second embedded 80188 access to FLASH, ISA READ cycle is allowed to proceed
onto memory bus to SRAM; host is still held in wait state.
7
At SRAM READ cycle completion, data is delivered to ISA bus and wait state is exited.
6. Parameter is not included in production test.
7. Parameter only applies when IOCHRDY is deasserted.
136
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P R E L I M I N A R Y
AC CHARACTERISTICS
OPERATING RANGES
Commercial (C) Devices
5.0 V MEMORY BUS INTERFACE
Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (VCC, VDDT, VDDU1, VDDU2, VDDM, VDDP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 V to 5.25 V
Storage Temperature: . . . . . . . . . . . . –65 to +150°C
Ambient Temperature Under Bias: . . . –65 to +125°C
Supply Voltages
(AVDD, VDD5) . . . . . . . . . . . . . . . . . . . . . . . . +5 V ± 5%
Supply Voltage to AVSS
or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.3 to +6 V
All inputs within the range: VSS – 0.5 V ≤ VIN ≤ VDD + 0.1 X
VDD – where VSS and VDD are appropriate reference pins
for a given input pin. (See section on power supply
pin descriptions.)
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect
device reliability.
CL = 50 pF unless otherwise noted
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
MEMORY BUS READ ACCESS
Parameter
Symbol
Parameter Description
Test Conditions
Min
2
Max
60
Unit
ns
tmAD
MA[16:0] valid from CLKIN ↓
CE active delay from CLKIN ↓
MOE active delay from CLKIN ↓
tmCD
Note 1
2
60
ns
tmOD
2
60
ns
tmOLZ
MOE ↓ to MD[7:0] driven
(Note 3)
0 wait states
1 wait state
2 wait states
0
30
80
130
ns
ns
ns
tmAA
tmACS
tmOE
Address Read Access Time
(Note 3)
0 wait states
1 wait state
2 wait states
55
105
155
ns
ns
ns
CE Read Access Time
(Notes 1, 3)
0 wait states
1 wait state
2 wait states
55
105
155
ns
ns
ns
MOE Read Access Time
(Note 3)
0 wait states
1 wait state
2 wait states
30
80
130
ns
ns
ns
tmRI
tmAH
tmCH
tmH
CE Inactive Time
Notes 1, 2
Note 1
0
ns
ns
ns
ns
ns
MA[16:0] valid hold from MOE ↑
CE valid hold from MOE ↑
MD[7:0] valid hold from MOE ↑
MD[7:0] inactive from MOE ↑
TCLKIN-10
TCLKIN-10
Note 2
Note 2
0
0
tmHZ
2 X TCLKIN-15
Notes:
1. CE = one of: FCE, SCE, XCE
2. Parameter not included in the production test.
3. Value is dependent upon TCLKIN value. Value given is for CLKIN = 40 MHz.
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P R E L I M I N A R Y
MEMORY BUS WRITE ACCESS
Parameter
Symbol
Parameter Description
Test Conditions
Min
2
Max
60
Unit
ns
tmAD
MA[16:0] valid from CLKIN ↓
CE active delay from CLKIN ↓
tmCD
tmWD
tmCQ
tmCV
Note 1
2
60
ns
MWE active delay from CLKIN ↓
MD[16:0] driven from CLKIN ↓
MD[16:0] valid from CLKIN ↓
Address Setup Time to MWE ↓
2
60
ns
2
ns
60
ns
tmAS
TCLKIN-20
ns
tmAW
Address Write Access Time
(Note 3)
0 wait states
1 wait state
2 wait states
95
145
195
ns
ns
ns
tmCW
tmWP
CE Write Access Time
(Notes 1, 3)
0 wait states
1 wait state
2 wait states
95
145
195
ns
ns
ns
MWE Write Access Time
(Note 3)
0 wait states
1 wait state
2 wait states
90
140
190
ns
ns
ns
tmWQ
tmAH
tmCH
tmWI
MWE ↓ to MD[7:0] driven
MA[16:0] valid hold from MWE ↑
CE valid hold from MWE ↑
CE Inactive Time
–10
TCLKIN-10
TCLKIN-10
0
ns
ns
ns
ns
Note 1
Note 1, 2
tmSW
MD[7:0] valid setup to MWE ↑
0 wait states
1 wait state
2 wait states
80
130
180
ns
ns
ns
tmHW
MD[7:0] valid hold from MWE ↑
MD[7:0] inactive from MWE ↑
Note 2
Note 2
TCLKIN-15
ns
ns
tmHWZ
2 X TCLKIN-10 2 X TCLKIN+10
Notes:
1. CE = one of: FCE, SCE, XCE
2. Parameter not included in the production test.
3. Value is dependent upon TCLKIN value. Value given is for CLKIN = 40 MHz.
138
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P R E L I M I N A R Y
AC CHARACTERISTICS
OPERATING RANGES
Commercial (C) Devices
3.3 V MEMORY BUS INTERFACE
Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (VCC,VDDT, VDDU1, VDDU2, VDDM, VDDP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 V to 5.25 V
Storage Temperature: . . . . . . . . . . . . –65 to +150°C
Ambient Temperature Under Bias: . . . –65 to +125°C
Supply Voltages
(AVDD, VDD5) . . . . . . . . . . . . . . . . . . . . . . . . +5 V ± 5%
Supply Voltage to AVSS
or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.3 to +6 V
All inputs within the range: VSS – 0.5 V ≤ VIN ≤ VDD + 0.1 X
VDD – where VSS and VDD are appropriate reference pins
for a given input pin. (See section on power supply
pin descriptions.)
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect
device reliability.
CL = 50 pF unless otherwise noted
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
MEMORY BUS READ ACCESS
Parameter
Symbol
Parameter Description
Test Conditions
Min
2
Max
100
100
100
Unit
ns
tmAD
MA[16:0] valid from CLKIN ↓
CE active delay from CLKIN ↓
MOE active delay from CLKIN ↓
tmCD
Note 1
2
ns
tmOD
2
ns
tmOLZ
MOE ↓ to MD[7:0] driven
(Note 3)
0 wait states
1 wait state
2 wait states
0
70
170
270
ns
ns
ns
tmAA
tmACS
tmOE
Address Read Access Time
(Note 3)
0 wait states
1 wait state
2 wait states
120
220
320
ns
ns
ns
CE Read Access Time
(Notes 1, 3)
0 wait states
1 wait state
2 wait states
120
220
320
ns
ns
ns
MOE Read Access Time
(Note 3)
0 wait states
1 wait state
2 wait states
70
170
270
ns
ns
ns
tmRI
tmAH
tmCH
tmH
CE Inactive Time
Notes 1, 2
Note 1
0
ns
ns
ns
ns
ns
MA[16:0] valid hold from MOE ↑
CE valid hold from MOE ↑
MD[7:0] valid hold from MOE ↑
MD[7:0] inactive from MOE ↑
TCLKIN-10
TCLKIN-10
Note 2
Note 2
0
0
tmHZ
2 X TCLKIN-15
Notes:
1. CE = one of: FCE, SCE, XCE
2. Parameter not included in the production test.
3. Value is dependent upon TCLKIN value. Value given is for CLKIN = 20 MHz.
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P R E L I M I N A R Y
MEMORY BUS WRITE ACCESS
Parameter
Symbol
Parameter Description
Test Conditions
Min
2
Max
100
100
100
Unit
ns
tmAD
MA[16:0] valid from CLKIN ↓
CE active delay from CLKIN ↓
tmCD
tmWD
tmCQ
tmCV
Note 1
2
ns
MWE active delay from CLKIN ↓
MD[7:0] driven from CLKIN ↓
MD[7:0] valid from CLKIN ↓
Address Setup Time to MWE ↓
2
ns
2
ns
100
ns
tmAS
TCLKIN-20
ns
tmAW
Address Write Access Time
(Note 3)
0 wait states
1 wait state
2 wait states
160
260
360
ns
ns
ns
tmCW
tmWP
CE Write Access Time
(Notes 1, 3)
0 wait states
1 wait state
2 wait states
160
260
360
ns
ns
ns
MWE Write Access Time
(Note 3)
0 wait states
1 wait state
2 wait states
150
250
350
ns
ns
ns
tmWQ
tmAH
tmCH
tmWI
MWE ↓ to MD[7:0] driven
MA[16:0] valid hold from MWE ↑
CE valid hold from MWE ↑
CE Inactive Time
–10
TCLKIN-10
TCLKIN-10
0
ns
ns
ns
ns
Note 1
Note 1, 2
tmSW
MD[7:0] valid setup to MWE ↑
0 wait states
1 wait state
2 wait states
130
230
330
ns
ns
ns
tmHW
MD[7:0] valid hold from MWE ↑
MD[7:0] inactive from MWE ↑
Note 2
Note 2
TCLKIN-15
ns
ns
tmHWZ
2 X TCLKIN-10 2 X TCLKIN+10
Notes:
1. CE = one of: FCE, SCE, XCE
2. Parameter not included in the production test.
3. Value is dependent upon TCLKIN value. Value given is for CLKIN = 20 MHz.
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P R E L I M I N A R Y
AC CHARACTERISTICS
5.0 V TAI INTERFACE
OPERATING RANGES
Commercial (C) Devices
Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (VCC,VDDT, VDDU1, VDDU2, VDDM, VDDP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 V to 5.25 V
Storage Temperature: . . . . . . . . . . . . –65 to +150°C
Ambient Temperature Under Bias: . . . –65 to +125°C
Supply Voltages
(AVDD, VDD5) . . . . . . . . . . . . . . . . . . . . . . . . +5 V ± 5%
Supply Voltage to AVSS
or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.3 to +6 V
All inputs within the range: VSS – 0.5 V ≤ VIN ≤ VDD + 0.1 X
VDD – where VSS and VDD are appropriate reference pins
for a given input pin. (See section on power supply
pin descriptions.)
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect
device reliability.
CL = 50 pF unless otherwise noted
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
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P R E L I M I N A R Y
5.0 V TAI INTERFACE AC CHARACTERISTICS
Parameter
Symbol
TCLKIN
TCLIN
Parameter Description
CLKIN Period
Test Conditions
MIR9[7]=1
MIR9[7]=1
MIR9[7]=1
MIR9[7]=0
MIR9[7]=0
MIR9[7]=0
Note 8
Min
25
5
Max
Unit
ns
CLKIN Low time
CLKIN High time
CLKIN Period
ns
TCHIN
TCLKIN
TCLIN
5
ns
50
22
22
CLKIN Low time
CLKIN High time
CLKIN Fall time
CLKIN Rise time
RXC Period
TCHIN
TINHL
3
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TINLH
Note 8
TRXC
Note 5
500
240
240
TCLRX
TCHRX
TRXHL
TRXLH
TTXC
RXC Low time
Note 5
RXC High time
Note 5
RXC Fall time
Note 8
10
10
RXC Rise time
Note 8
TXC Period
Notes 1, 5, 7
Notes 1, 5, 7
Notes 1, 5, 7
Notes 1, 8
Notes 1, 8
Notes 2, 7
Notes 2, 7
Notes 2, 7
Notes 2, 8
Notes 2, 8
Note 6
500
245
245
TCLTX
TCHTX
TTXHL
TTXLH
TTXCO
TCLTXO
TCHTXO
TTXHLO
TTXLHO
tRXDS
TXC Low time
TXC High time
TXC Fall time
5
5
TXC Rise time
TXC Period
500
285
185
TXC Low time
TXC High time
TXC Fall time
15
15
TXC Rise time
RXD setup time to RXC ↑
RXD hold time from RXC ↑
TXD delay from TXC ↓
TXD setup time to TXC ↑
TXD hold time from TXC ↑
TXD delay from TXC ↓
110
10
tRXDH
Note 6
tTXDD
Notes 1, 3
Notes 2, 4
Notes 2, 4
Notes 2, 3
10
200
150
tTXDS
TCLTX-165
TCHTX
0
tTXDH
tTXDV
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P R E L I M I N A R Y
Notes:
1. Only applicable when TXC has been configured as an INPUT.
2. Only applicable when TXC has been configured as an OUTPUT.
3. MIN value not tested.
4. Parameter calculated from other parameters.
5. Clock period must correlate to data rate as specified in DR bits of TCR30. Note that data rate is a function of DR and TCLKIN and
CLKGT20 bit of MIR9.
6. The values for these parameters are given for the case with CLKP = 0 (TCR2[4:0]). For nonzero values of CLKP, use the
following formulas:
If CLKGT20 = 0 (MIR9[7]),
tRXDSmin = 110–CLKP X TCLKIN
tRXDHmin = 10+CLKP X TCLKIN
tRXDSmin = 110–CLKP X TCLKIN X 2
tRXDHmin = 10+CLKP X TCLKIN X 2
If CLKGT20 = 1 (MIR9[7]),
7. Values given are for data rate of 2Mb/s. For other data rates,
TTXC is 1/DR, where DR = data rate in Hertz,
TCLTX is 60% of TTXC minus TTXHL,
TCHTX is 40% of TTXC minus TTXHL,
TTXCO is 1/DR, where DR = data rate in Hertz,
TCLTXO is 60% of TTXCO minus TTXHLO,
TCHTXO is 40% of TTXCO minus TTXHLO,
TTXHLO is 15 ns, regardless of DR value,
TTXLHO is 15 ns, regardless of DR value.
8. Parameter not included in the production test.
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P R E L I M I N A R Y
AC CHARACTERISTICS
3.3 V TAI INTERFACE
OPERATING RANGES
Commercial (C) Devices
Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (VCC,VDDT, VDDU1, VDDU2, VDDM, VDDP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 V to 5.25 V
Storage Temperature: . . . . . . . . . . . . –65 to +150°C
Ambient Temperature Under Bias: . . . –65 to +125°C
Supply Voltages
(AVDD, VDD5) . . . . . . . . . . . . . . . . . . . . . . . . +5 V ± 5%
Supply Voltage to AVSS
or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.3 to +6 V
All inputs within the range: VSS – 0.5 V ≤ VIN ≤ VDD + 0.1 X
VDD – where VSS and VDD are appropriate reference pins
for a given input pin. (See section on power supply
pin descriptions.)
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect
device reliability.
CL = 50 pF unless otherwise noted
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
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P R E L I M I N A R Y
3.3 V TAI INTERFACE AC CHARACTERISTICS
Parameter
Symbol
Parameter Description
CLKIN Period
Test Conditions
Min
50
Max
Unit
tCLKIN
tCLIN
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLKIN Low time
CLKIN High time
CLKIN Fall time
CLKIN Rise time
RXC Period
22
tCHIN
tINHL
22
Note 8
3
3
tINLH
Note 8
tRXC
Note 5
1000
480
tCLRX
tCHRX
tRXHL
tRXLH
tTXC
RXC Low time
Note 5
RXC High time
Note 5
480
RXC Fall time
Note 8
20
20
RXC Rise time
Note 8
TXC Period
Notes 1, 5, 7
Notes 1, 5, 7
Notes 1, 5, 7
Notes 1, 8
Notes 1, 8
Notes 2, 7
Notes 2, 7
Notes 2, 7
Notes 2, 8
Notes 2, 8
Note 6
1000
495
tCLTX
tCHTX
tTXHL
tTXLH
tTXCO
tCLTXO
tCHTXO
tTXHLO
tTXLHO
tRXDS
tRXDH
tTXDD
tTXDS
tTXDH
tTXDV
TXC Low time
TXC High time
495
TXC Fall time
5
5
TXC Rise time
TXC Period
1000
585
TXC Low time
TXC High time
385
TXC Fall time
15
15
TXC Rise time
RXD setup time to RXC ↑
RXD hold time from RXC ↑
TXD delay from TXC ↓
TXD setup time to TXC ↑
TXD hold time from TXC ↑
TXD delay from TXC ↓
110
10
Note 6
Notes 1, 3
Notes 2, 4
Notes 2, 4
Notes 2, 3
10
200
150
TCLTX-165
TCHTX
0
Notes:
1. Only applicable when TXC has been configured as an INPUT.
2. Only applicable when TXC has been configured as an OUTPUT.
3. MIN value not tested.
4. Parameter calculated from other parameters.
5. Clock period must correlate to data rate as specified in DR bits of TCR30. Note that data rate is a function of DR and TCLKIN and
CLKGT20 bit of MIR9.
6. The values for these parameters are given for the case with CLKP = 0 (TCR2[4:0]). For nonzero values of CLKP, use the
following formulas:
If CLKGT20 = 0 (MIR9[7]),
tRXDSmin = 110–CLKP X TCLKIN
tRXDHmin = 10+CLKP X TCLKIN
tRXDSmin = 110–CLKP X TCLKIN X 2
tRXDHmin = 10+CLKP X TCLKIN X 2
If CLKGT20 = 1 (MIR9[7]),
7. Values given are for data rate of 1Mb/s. For other data rates,
tTXC is 1/DR, where DR = data rate in Hertz,
tCLTX is 60% of TTXC minus TTXHL,
tCHTX is 40% of TTXC minus TTXHL,
tTXCO is 1/DR, where DR = data rate in Hertz,
tCLTXO is 60% of TTXCO minus TTXHLO,
tCHTXO is 40% of TTXCO minus TTXHLO,
tTXHLO is 15 ns, regardless of DR value,
tTXLHO is 15 ns, regardless of DR value.
8. Parameter not included in the production test.
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P R E L I M I N A R Y
AC CHARACTERISTICS
OPERATING RANGES
Commercial (C) Devices
5.0 AND 3.3 V USER
Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C
PROGRAMMABLE PINS
Supply Voltages (VCC,VDDT, VDDU1, VDDU2, VDDM, VDDP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 V to 5.25 V
ABSOLUTE MAXIMUM RATINGS
Storage Temperature: . . . . . . . . . . . . –65 to +150°C
Ambient Temperature Under Bias: . . . –65 to +125°C
Supply Voltages
(AVDD, VDD5) . . . . . . . . . . . . . . . . . . . . . . . . +5 V ± 5%
Supply Voltage to AVSS
or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.3 to +6 V
All inputs within the range: VSS – 0.5 V≤ VIN ≤ VDD + 0.1 X
VDD – where VSS and VDD are appropriate reference pins
for a given input pin. (See section on power supply
pin descriptions.)
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect
device reliability.
CL = 50 pF unless otherwise noted
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Units
tu1
Data change delay from
55
ns
CLKIN ↓
tu2
tu3
Pin drive disable delay from
CLKIN ↓
55
55
ns
ns
Note 1
Note 1
Pin drive enable delay from
CLKIN ↓
Note:
1. Parameter is not included in production test.
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P R E L I M I N A R Y
AC CHARACTERISTICS
OPERATING RANGES
Commercial (C) Devices
5.0 AND 3.3 V IEEE 1149.1 INTERFACE
Temperature (TA) . . . . . . . . . . . . . . . . . 0°C to + 70°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (VCC,VDDT, VDDU1, VDDU2, VDDM, VDDP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 V to 5.25 V
Storage Temperature: . . . . . . . . . . . . –65 to +150°C
Ambient Temperature Under Bias: . . . –65 to +125°C
Supply Voltages
(AVDD, VDD5) . . . . . . . . . . . . . . . . . . . . . . . . +5 V ± 5%
Supply Voltage to AVSS
or DVSS (AVDD, DVDD): . . . . . . . . . . . . . . –0.3 to +6 V
All inputs within the range: VSS – 0.5 V ≤ VIN ≤ VDD + 0.1 X
VDD – where VSS and VDD are appropriate reference pins
for a given input pin. (See section on power supply
pin descriptions.)
Stresses above those listed under Absolute Maximum
Ratings may cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to Absolute
Maximum Ratings for extended periods may affect
device reliability.
CL = 50 pF unless otherwise noted
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Parameter
Symbol
Parameter Description
TCK period
Test Conditions
Min
100
16
10
3
Max
Units
ns
t25
t30
t31
t32
t34
TDI, TMS setup time to TCK ↑
TDI, TMS hold time from TCK ↑
TDO valid delay from TCK ↓
ns
ns
60
60
ns
All outputs (non-test) valid delay
3
ns
from TCK ↓
t35
t36
t37
All outputs (non-test) float delay
from TCK ↓
70
ns
ns
ns
Note 1
All inputs (non-test) setup time to
TCK ↑
8
All inputs (non-test) hold time from
25
TCK ↑
Note:
1. Parameter is not included in production test.
ANALOG-TO-DIGITAL (A/D)
CONVERTER CHARACTERISTICS
Resolution: . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 bits
Resolution Tested: . . . . . . . . . . . . . . . . . . . . . . 4 bits
Sample Rate: . . . . . . . . . . . . . . 1.66 MSPS (600 ns)*
Recommended A/D Ref Range: . . . . 1.25 to 1.75 V**
Range of ADIN1 + ADIN2: . . . . . . . 0 to (ADREF x 2)
*User should program a 0011 in A2DT[3:0] of TCR25.
**ADREF is doubled internally.
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P R E L I M I N A R Y
TIMING WAVEFORMS
PCMCIA Bus Interface Waveforms
t
AVQV
t
GHAX
A , REG
n
t
ELQV
CE
OE
t
t
ELGL
GHEH
t
GLQV
t
t
GLWTV
AVGL
(high)
WE
t
WAIT
WTLWTH
t
t
GHQZ
QVWTH
t
GLQNZ
D
o
(Dout)
20138B-10
Figure 4. PCMCIA MEMORY READ Access Timing Diagram
t
t
AVWH
ELWH
A , REG
n
t
WMAX
CE
OE
t
t
GHEH
ELWL
t
WHGL
t
WLWH
t
WLWTV
WE
t
t
AVWL
WTHWH
t
WTLWTH
WAIT
t
t
t
WMDX
GHWL
DVWH
D (Din)
i
t
t
WLQZ
GHQZ
t
WHQNZ
D
o
(Dout)
t
GLQNZ
20138B-11
Figure 5. PCMCIA MEMORY WRITE Access Timing Diagram
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P R E L I M I N A R Y
A
n
t
t
IGHAX
AVIGL
REG
CE
t
RGLIGL
t
IGHRGH
t
IGHEH
t
ELIGL
t
IORD
INPACK
WAIT
IGLIGH
t
t
IGHIAH
IGLIAL
t
t
WTHQV
IGLWTL
t
WTLWTH
t
t
t
IGHQX
IGLQV
IGQNZ
D
o
(Dout)
t
IGHQZ
20138B-12
Figure 6. PCMCIA I/O READ Access Timing Diagram
A
n
t
tI
WHAX
AVIWL
REG
CE
t
RGLIWL
t
IWHRGH
t
tI
ELIWL
WHEH
t
IOWR
WAIT
IWLIWH
tI
WLWTL
tWTHIWH
t
WTLWTH
t
t
IWHDX
DVIWL
D (Din)
i
20138B-13
Figure 7. PCMCIA I/O WRITE Access Timing Diagram
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P R E L I M I N A R Y
ISA Bus Interface Waveforms
t 1
i
t 3
i
LA
SA
n
n
t 9
i
t 2
i
t 12
i
BALE
AEN
t 30
t 32
i
t 26
t 23
t 31
i
i
i
i
t 10
i
t 7
i
t 13
i
CMD**
t 8
i
t 4
i
t 20
i
t 22
i
IOCHRDY
t 21
i
t 16
t 14
i
i
t 34
i
t 25
i
SD
out
(read)
t 11
i
t 15
i
SD (write)
in
20138B-14
**CMD = one of: MEMR, MEMW, IOR, IOW
Figure 8. ISA All Access Timing Diagram
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P R E L I M I N A R Y
Memory Bus Interface Waveforms
CLKIN
CLKOUT
(internal)
t
AH
AD
t
AD
m
m
t
t
MA
t
AA
m
n
m
t
ACS
m
CD
m
FCE,
SCE,
XCE
t
RI
m
t
CD
m
t
OE
m
t
CH
m
MOE
MWE
t OD
m
t
OD
m
t
HZ
H
(high)
m
t
RDSC
m
t
RDHC
m
t
OLZ
m
t
m
valid
MD (Din)
i
data sampled at this point
20138B-15
Figure 9. Memory Bus READ Access Timing Diagram
CLKIN
CLKOUT
(internal)
t
AH
m
t
AD
m
MA
t
t
AW
CW
t
t
AD
n
m
m
m
m
FCE,
SCE,
XCE
CD
t
WI
m
t
CH
m
t
CD
m
(high)
MOE
MWE
t WD
m
t
t
AS
m
WD
m
t
WP
m
t
HWZ
m
t HWC
m
t HW
m
t
WQ
m
t
SW
m
valid
MD
o
(Dout)
t
m
t
m
CQ
CV
t
HWZC
m
20138B-16
Figure 10. Memory Bus WRITE Access Timing Diagram
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P R E L I M I N A R Y
CLOCK WAVEFORMS
t
CLIN
2.0 V
0.8 V
t
CHIN
CLKIN
0.8 V
0.8 V
0.8 V
t
INLH
t
INHL
t
CLKIN
t
CLTX
2.0 V
0.8 V
t
CHTX
TXC
t
TXLH
t
TXHL
t
TXC
t
CLRX
2.0 V
0.8 V
t
CHRX
RXC
t
RXLH
t
RXHL
t
RXC
20138B-17
Figure 11. CLOCK Timing Diagram
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P R E L I M I N A R Y
TAI WAVEFORMS
CLKIN
CLKOUT
(internal)
t 1
n
ICO*
RCO**
RCO**
RCO**
t 2
n
t 3
n
t 4
n
20138B-18
**ICO = Internally Controlled Output
Figure 12. TAI Timing Diagram
RXC
RXD
t
t
RXDS
RXDS
TXC
(input)
t
TXDD
TXD
TXC
(output)
t
t
TXDH
t
TXDS
TXDV
TXD
20138B-19
Figure 13. Serial Data Timing Diagram
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P R E L I M I N A R Y
PROGRAMMABLE INTERFACE WAVEFORMS
CLKIN
CLKOUT
(internal)
WAIT or
IOCHRDY
t 1
u
RCO**
(data change)
t 2
u
RCO**
(drive change)
t 3
u
RCO**
(drive change)
20138B-20
**RCO = Register Controlled Output
Figure 14. Programmable Interface Timing Diagram
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P R E L I M I N A R Y
IEEE 1149.1 INTERFACE WAVEFORMS
t
25
TCK
t
t
t
t
t
30
32
34
36
31
TDI, TMS
TDO
t
35
Output
Signals
t
37
Input
Signals
20138B-21
Figure 15. IEEE 1149.1 Timing Diagram
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P R E L I M I N A R Y
AC TEST REFERENCE WAVEFORMS
5.0 V PCMCIA AC Test Reference Waveform
This waveform indicates the AC testing method em-
ployed for all signals that are PCMCIA bus signals when
the PCMCIA power supply pins are set to 5.0 V (i.e.,
VDDP pins = 5.0 V).
2.8
2.4
0.8
input
0.5
2.8
2.4
0.8
output
0.5
measured parameter value
20138B-22
Figure 16. 5.0 V PCMCIA AC Test Reference Waveform
3.3 V PCMCIA AC Test Reference Waveform
This waveform indicates the AC testing method em-
ployed for all signals that are PCMCIA bus signals when
the PCMCIA power supply pins are set to 3.3 V (i.e.,
VDDP pins = 3.3 V).
2.4
2.0
0.8
input
0.4
2.4
2.0
0.8
output
0.4
measured parameter value
20138B-23
Figure 17. 3.3 V PCMCIA AC Test Reference Waveform
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P R E L I M I N A R Y
5.0 V NON-PCMCIA AC TEST REFERENCE WAVEFORM
This waveform indicates the AC testing method em-
ployed for all signals that are not PCMCIA bus signals
when the appropriate power supply pins are set to
5.0 V (i.e., VDDT, VDDU1, VDDU2, VDDM pins = 5.0 V).
This includes ISA signals, TAI interface signals, Mem-
ory Bus Interface signals, IEEE 1149.1 signals and any
other signal not considered to be part of the PCMCIA
bus interface.
2.4
2.0
input
0.8
0.45
2.4
2.0
0.8
output
0.45
measured parameter value
20138B-24
Figure 18. 5.0 V Non-PCMCIA AC Test Reference Waveform
3.3 V NON-PCMCIA AC TEST REFERENCE WAVEFORM
This waveform indicates the AC testing method em-
ployed for all signals that are not PCMCIA bus signals
when the appropriate power supply pins are set to 3.3 V
(i.e., VDDT, VDDU1, VDDU2, VDDM pins = 3.3 V). This
includes ISA signals, TAI interface signals, Memory Bus
Interface signals, IEEE 1149.1 signals and any
other signal not considered to be part of the PCMCIA
bus interface.
2.4
2.0
input
0.8
0.45
2.4
2.0
0.8
output
0.45
measured parameter value
20138B-25
Figure 19. 3.3 V Non-PCMCIA AC Test Reference Waveform
Am79C930
157
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P R E L I M I N A R Y
PHYSICAL DIMENSIONS
PQT144
144-Pin Thin Quad Flat Pack (measured in millimeters)
144
1
21.80
22.20
19.80
20.20
19.80
20.20
21.80
22.20
11° – 13°
1.35
1.45
1.60 MAX
16-038-PQT-2_AH
PQT144
5-4-95 ae
11° – 13°
0.50 BSC
0.17
0.27
1.00 REF.
*For reference only. BSC is an ANSI standard for Basic Space Centering.
Trademarks
Copyright 1997 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
PCnet is a trademark of AMD.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
158
Am79C930
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APPENDIX A
Typical Am79C930 System Application
128K
Flash
128K
SRAM
PCMCIA
or
ISA PnP
Interface
Radio
or IR
Transceiver
Host
Computer
Am79C930
20183A-1
Figure 1: Typical Am79C930 System Application
The typical Am79C930 application contains
a
utilities present in the system must be disabled before
attempting this procedure.
Am79C930 device, a Flash memory device (up to 128
Kbytes), an SRAM memory device (up to 128 Kbytes), a
network transceiver unit, and a host computer system
connected to the Am79C930 subsystem through either
the PCMCIA or ISA Plug and Play system bus.
The general function of the Am79C930 device is to pro-
vide the MAC layer functions for an IEEE 802.11 (draft)
or Xircom Netwave protocol network. The following sec-
tions give a description of the interaction of the
Am79C930 device with a device driver, the Am79C930
80188 core firmware, and the network.
The Flash memory device is used to store PCMCIA CIS
or ISA Plug and Play resource data, the network ID for
the subsystem and the IEEE 802.11 (draft), and the
Xircom Netwave MAC protocol firmware that will be
executed on the Am79C930 device’s embedded 80188
core. The SRAM will be used by both the device driver
and the Am79C930 80188 core for command and status
passing, data buffer storage, and 80188 core
variable space.
Device Configuration
The PCMCIA pin is strapped in hardware to select either
PCMCIA or ISA Plug and Play mode of operation. In
either case, the host computer at system configuration
time (typically at system boot time) will read the configu-
rationinformationfromtheAm79C930subsystemFlash
memory to determine the memory, I/O space, and inter-
rupt channel requirements of the subsystem.
In addition to these hardware components, the
Am79C930 subsystem will require network application
software, a device driver, IEEE 802.11 (draft) MAC pro-
tocol firmware stored in the Flash device before power
up, and system configuration information (either
PCMCIA CIS or ISA Plug and Play Resource Data) that
is also stored in the Flash device before power up.
After allocating a portion of system resources to the
Am79C930 subsystem, the device driver will be loaded.
The device driver will set up or reserve various areas of
the SRAM for the following purposes:
Note: The Am79C930 device allows an uninitialized
Flash memory device to be built into the Am79C930
subsystem and then to be programmed within the
Am79C930 subsystem. However, normal configuration
Am79C930
A-1
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1. Command and status communication
2. Data buffer areas
After waiting for appropriate timing intervals as specified
in the IEEE 802.11 (draft) and the Xircom Netwave stan-
dards, the Am79C930 80188 core will write the transmit
command to the TAI, and the TAI will begin sending the
transmit data stream to the transceiver. During the
transmission procedure, the TX FIFO will require occa-
sional refilling. The request for additional TX data will be
acknowledged by the Am79C930 80188 core until the
entire TX frame has been sent to the transceiver.
When the last byte of data has been sent, a Cyclic
Redundancy Check (CRC) field will automatically be
appended to the frame by the TAI unit when the CRC
function has been enabled. Preamble and Start of
Frame Delimiters will not be automatically generated by
the TAI unit and, therefore, must be supplied by the firm-
ware as part of the data that is loaded into the TX FIFO.
CRC bytes are automatically appended by the TAI after
the TX FIFO empties.
3. Am79C930 80188 core variable space
After performing these functions, the device driver will
enable the 80188 core by writing to a register to release
the RESET of the Am79C930 80188 core. The
Am79C930 80188 core will then begin fetching instruc-
tions from the Flash memory and will eventually execute
code that causes it to recognize the command area that
the driver has set up in the SRAM.
The Am79C930 80188 core will begin by initializing reg-
isters contained within the TAI unit. Once this has been
completed, status will be written to the SRAM command
and status area, and an interrupt will be sent first to the
systeminterface’sstatusregisterandthentothesystem
interface bus. The device driver will acknowledge and
clear the interrupt, and then will write the next command
to the SRAM command and status area, setting an inter-
rupt for the Am79C930 80188 core.
When all bytes, including CRC bytes, have been sent to
the transceiver, TX status information will be gathered
and placed in the SRAM for delivery to the device driver.
Then, an interrupt to the system will be generated.
Flash memory information for system configuration
(PCMCIA CIS or ISA Plug and Play Resource Data) will
normally be pre-programmed in the Flash memory
along with network ID; however, this information may be
written to the Flash memory the first time through the
system interface, before the RESET of the Am79C930
80188 core is released.
Frame Reception
Frame reception is initiated by the network. When the
appropriate network signaling is recognized (a Pream-
ble plus Start of Frame Delimiter) in the TAI unit, the TAI
will begin placing received data into the receive (RX)
FIFO. As the RX FIFO becomes filled with data, it will re-
quest that data be removed by asserting the DMA chan-
nel 0 input of the Am79C930 80188 core. The 80188
core will move the received data from the RX FIFO into
the SRAM data buffer space and will examine the desti-
nation address. If the address does not match the ad-
dress of the Am79C930 subsystem, then the frame will
be rejected by the Am79C930 device. If the frame ad-
dress does match the address of the Am79C930
subsystem, then the frame will be accepted. When all
bytes of the receive frame have been placed into the
SRAM’s data buffer space and the receive status has
been placed into the SRAM, the Am79C930 80188 core
will send an interrupt to the system. The device driver
will respond to the interrupt by reading the command
and status area of the SRAM. Then the device driver will
move the received frame from the SRAM into the sys-
tem memory. Finally, the device driver will write status to
the SRAM to release the data buffer back to the
Am79C930 80188 core for use in a later reception.
Note: Normal system configuration utilities must be dis-
abled before this is attempted.
Frame Transmission
Frame transmission is initiated by the device driver. The
device driver first places the frame data into the SRAM
in the transmit data buffer area. Then the device driver
writes the appropriate set of transmit commands to the
command area of the SRAM and sets an interrupt bit in
one of the system interface registers. An interrupt to the
Am79C930 80188 core will be generated, and the
Am79C930 80188 core will respond by examining the
command area of the SRAM. The transmit command
will instruct the Am79C930 80188 core to move the
transmit data from the data buffer area of SRAM into the
TAI unit’s transmit (TX) FIFO. The move may be accom-
plished either through the use of programmed I/O
moves or DMA moves. DMA channel 1 of the 80188
core is reserved for use by the TX FIFO.
A-2
Am79C930
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Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am186, Am386, Am486, Am29000, bIMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, MACE, Magic Packet, PCnet,
PCnet-FAST, PCnet-FAST+, PCnet-Mobile, QFEX, QFEXr, QuASI, QuEST, QuIET, TAXIchip, TPEX, andTPEX Plus are trademarks of Advanced
Micro Devices, Inc.
Microsoft is a registered trademark of Microsoft Corporation.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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