CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
18-Mbit (512K x 36/1M x 18) Pipelined SRAM
Features
Functional Description [1]
• Supports bus operation up to 250 MHz
The
CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/
CY7C1382FV25 SRAM integrates 512K x 36 and 1M x 18
SRAM cells with advanced synchronous peripheral circuitry
and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive edge triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• 2.5V core power supply
• Fast clock-to-output times, 2.6 ns (for 250-MHz device)
• Provides high-performance 3-1-1-1 access rate
chip enable (CE ), depth expansion chip enables (CE and
1
2
®
®
CE
), burst control inputs (ADSC, ADSP, and ADV), write
• User selectable burst counter supporting Intel Pentium
3
enables (BW , and BWE), and global write (GW).
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed writes
X
Asynchronous inputs include the output enable (OE) and the
ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or
address strobe controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the advance pin (ADV).
• Asynchronous output enable
• Single Cycle Chip Deselect
• CY7C1380DV25/CY7C1382DV25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non
Pb-free 165-ball FBGA package.
CY7C1380FV25/CY7C1382FV25 available in Pb-free and
non Pb-free 119-ball BGA package
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
on page 9 for further details). Write cycles can be one
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• ZZ sleep mode option
to two or four bytes wide as controlled by the byte write control
inputs. GW when active
causes all bytes to be written.
LOW
The
CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/
CY7C1382FV25 operates from a +2.5V core power supply
while all outputs may operate with a +2.5 supply. All inputs and
outputs are JEDEC-standard and JESD8-5-compatible.
Selection Guide
250 MHz
200 MHz
3.0
167 MHz
3.4
Unit
ns
Maximum Access Time
2.6
350
70
Maximum Operating Current
Maximum CMOS Standby Current
300
275
mA
mA
70
70
Notes:
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.
2. CE , CE are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable
3
2
Cypress Semiconductor Corporation
Document #: 38-05546 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised Feburary 15, 2007
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Pin Configurations
100-pin TQFP Pinout (3 Chip Enable)
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQc
VDDQ
VSSQ
DQC
3
4
5
6
DQC
7
NC
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
DQC
9
9
VSSQ
10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
11
DQC
12
DQC
13
NC
14
VDD
NC
VSS
NC
VDD
ZZ
15
CY7C1382DV25
(1M x 18)
CY7C1380DV25
(512K X 36)
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
ZZ
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
NC
NC
NC
Document #: 38-05546 Rev. *E
Page 3 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Pin Configurations (continued)
119-Ball BGA
Pinout
CY7C1380FV25 (512K x 36)
1
2
3
4
5
6
7
V
A
A
A
A
V
DDQ
A
ADSP
ADSC
DDQ
B
C
NC/288M
NC/144M
A
A
A
A
A
A
A
A
NC/576M
NC/1G
V
DD
DQ
DQP
V
NC
CE
V
DQP
DQ
D
E
F
C
C
SS
SS
SS
SS
SS
SS
B
B
DQ
DQ
DQ
V
V
V
V
DQ
DQ
DQ
B
C
C
1
B
V
V
DDQ
OE
ADV
GW
DDQ
C
B
DQ
DQ
DQ
V
BW
V
BW
V
DQ
DQ
V
DQ
G
H
J
C
C
C
C
C
B
B
B
B
DQ
DQ
SS
SS
B
V
NC
V
NC
V
DDQ
DDQ
DD
DD
DD
DQ
DQ
V
CLK
NC
V
DQ
DQ
K
D
D
D
SS
SS
A
A
A
L
M
N
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
BW
BW
D
D
D
A
A
A
D
A
V
V
V
V
V
V
DDQ
BWE
A1
DDQ
SS
SS
SS
SS
DQ
DQ
D
A
P
R
DQ
DQP
A
V
A0
V
DQP
A
DQ
D
D
SS
SS
A
NC
NC
MODE
V
NC
A
NC
DD
NC/72M
TMS
A
A
A
NC/36M
NC
ZZ
T
U
V
TDI
TCK
TDO
V
DDQ
DDQ
CY7C1382FV25 (1M x 18)
2
A
1
3
A
A
A
4
5
A
A
A
6
A
A
A
7
A
B
C
D
E
F
V
V
DDQ
ADSP
ADSC
DDQ
NC/288M
A
NC/576M
NC/144M
A
V
NC/1G
NC
DD
DQ
NC
DQ
V
NC
CE
V
DQP
A
B
SS
SS
SS
SS
SS
SS
NC
V
V
V
V
NC
DQ
DQ
B
A
1
V
NC
DQ
V
OE
ADV
GW
DDQ
A
DDQ
G
H
J
NC
NC
NC
DQ
DQ
BW
V
B
A
B
DQ
NC
V
NC
V
DDQ
B
SS
SS
A
V
V
NC
V
NC
V
DDQ
DD
DD
DD
NC
DQ
V
CLK
NC
V
NC
DQ
DQ
K
L
B
SS
SS
A
DQ
NC
DQ
NC
NC
BW
B
A
A
V
V
V
V
V
NC
DQ
V
DDQ
M
N
P
BWE
A1
DDQ
B
SS
SS
SS
SS
DQ
NC
V
NC
DQ
B
SS
A
NC
DQP
V
A0
NC
B
SS
A
NC
A
A
MODE
A
V
NC
A
A
A
NC
ZZ
R
T
DD
NC/72M
NC/36M
TCK
U
V
TMS
TDI
TDO
NC
V
DDQ
DDQ
Document #: 38-05546 Rev. *E
Page 4 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Pin Configurations (continued)
165-Ball FBGA Pinout (3 Chip Enable)
CY7C1380DV25 (512K x 36)
1
2
3
4
5
6
7
8
9
10
A
11
NC
NC/288M
NC/144M
DQPC
A
B
C
D
CE1
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
CE
ADSC
A
BWE
GW
VSS
ADV
ADSP
VDDQ
VDDQ
3
A
CE2
VDDQ
VDDQ
CLK
VSS
VSS
A
NC/576M
DQPB
DQB
OE
VSS
VDD
NC
NC/1G
DQB
DQC
DQC
VSS
DQC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
E
F
DQC
DQC
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQB
DQB
ZZ
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
NC/72M
TDI
A1
TDO
A0
MODE
NC/36M
A
A
TMS
TCK
A
A
A
A
R
CY7C1382DV25 (1M x 18)
1
2
A
3
4
5
NC
6
7
8
9
10
A
11
A
NC/288M
NC/144M
NC
A
BWB
NC
CE
CE1
CE2
BWE
GW
VSS
ADSC
OE
ADV
ADSP
VDDQ
VDDQ
3
A
BWA
VSS
VSS
CLK
VSS
VSS
A
NC/576M
DQPA
DQA
B
C
D
NC
VDDQ
VDDQ
VSS
VDD
VSS
NC/1G
NC
NC
DQB
VSS
VDD
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
E
F
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQA
DQA
ZZ
NC
G
H
J
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
NC/72M
TDI
A1
TDO
MODE
NC/36M
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05546 Rev. *E
Page 5 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Pin Definitions
Name
IO
Description
A , A , A
Input-
Synchronous
Address inputs used to select one of the address locations. Sampled at the rising
0
1
[2]
edge of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled
1
2
3
active. A1: A0 are fed to the two-bit counter.
Input-
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to
BW , BW
A
B
Synchronous
the SRAM. Sampled on the rising edge of CLK.
BW , BW
C
D
GW
Input-
Global write enable input, active LOW. When asserted LOW on the rising edge of
Synchronous
CLK, a global write is conducted (all bytes are written, regardless of the values on BW
and BWE).
X
Input-
Synchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
BWE
CLK
Input-
Clock
Clock input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Input-
Synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
CE
1
2
conjunction with CE and CE to select or deselect the device. ADSP is ignored
if CE
2
3
1
CE is sampled only when a new external address is loaded.
is HIGH.
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE and CE to select or deselect the device. CE is sampled only
1
CE
Input-
Synchronous
1
3
2
when a new external address is loaded.
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE and CE to select or deselect the device. CE is sampled only
Input-
Synchronous
CE
3
1
2
3
when a new external address is loaded.
Input-
Output enable, asynchronous input, active LOW. Controls the direction of the IO
OE
Asynchronous
pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are
tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle
when emerging from a deselected state.
Input-
Advance input signal, sampled on the rising edge of CLK, active LOW. When
ADV
Synchronous
asserted, it automatically increments the address in a burst cycle.
Input-
Synchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are
ADSP
both asserted, only ADSP is recognized. ASDP is ignored when CE is deasserted
1
HIGH.
Input-
Synchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
ADSC
ZZ
Input-
Asynchronous
ZZ sleep input. This active HIGH input places the device in a non-time critical sleep
condition with data integrity preserved. For normal operation, this pin has to be LOW
or left floating. ZZ pin has an internal pull down.
IO-
Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise
of the read cycle. The direction of the pins is controlled by OE. When OE is asserted
DQs, DQP
X
Synchronous
LOW, the pins behave as outputs. When HIGH, DQs and DQP are placed in a tri-state
X
condition.
V
V
Power Supply
Ground
Power supply inputs to the core of the device.
Ground for the core of the device.
DD
SS
Document #: 38-05546 Rev. *E
Page 6 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Pin Definitions (continued)
Name
IO
Description
V
V
IO Ground
Ground for the IO circuitry.
SSQ
DDQ
IO Power Supply Power supply for the IO circuitry.
MODE
TDO
TDI
Input-
Static
Selects burst order. When tied to GND selects linear burst sequence. When tied to
or left floating selects interleaved burst sequence. This is a strap pin and must
remain static during device operation. Mode pin has an internal pull up.
V
DD
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
Synchronous
JTAG feature is not used, this pin must be disconnected. This pin is not available on
TQFP packages.
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous
feature is not used, this pin can be disconnected or connected to V . This pin is not
DD
available on TQFP packages.
TMS
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous
feature is not used, this pin can be disconnected or connected to V . This pin is not
DD
available on TQFP packages.
TCK
NC
JTAG-Clock
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be
connected to V . This pin is not available on TQFP packages.
SS
–
–
No Connects. Not internally connected to the die
NC/(36M,72M,
144M, 288M,
576M, 1G)
These pins are not connected. They will be used for expansion to the 36M, 72M,
144M, 288M, 576M and 1G densities.
Single Read Accesses
Functional Overview
This access is initiated when the following conditions are
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE , CE , CE are all asserted active, and (3) the write signals
1
2
3
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE
1
Maximum access delay from the clock rise (t ) is 2.6 ns
CO
is HIGH. The address presented to the address inputs (A) is
stored into the address advancement logic and the address
register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
output registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single Read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output will tri-state
immediately.
(250-MHz device).
The
CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/
CY7C1382FV25 supports secondary cache in systems using
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486™ processors. The
®
linear burst sequence is suited for processors that use a linear
burst sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with either the processor address strobe (ADSP) or
the controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
Single Write Accesses Initiated by ADSP
(BWE) and byte write select (BW ) inputs. A global write
X
enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self timed write circuitry.
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE , CE , CE are all asserted active. The address
1
2
3
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
Three synchronous chip selects (CE , CE , CE ) and an
asynchronous output enable (OE) provide for easy bank
1
2
3
memory array. The write signals (GW, BWE, and BW ) and
X
selection and output tri-state control. ADSP is ignored if CE
is HIGH.
1
ADV inputs are ignored during this first cycle.
Document #: 38-05546 Rev. *E
Page 7 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW is
Burst Sequences
The
CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/
CY7C1382FV25 provides a two-bit wraparound counter, fed
by A1: A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow
a linear burst sequence. The burst sequence is user selectable
through the MODE input.
HIGH, then the write operation is controlled by BWE and BW
signals.
X
The
CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/
CY7C1382FV25 provides byte write capability that is
described in the write cycle descriptions table. Asserting the
byte write enable input (BWE) with the selected byte write
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
(BW ) input, will selectively write to only the desired bytes.
X
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self timed write mechanism has
been provided to simplify the write operations.
Sleep Mode
The
CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation sleep mode. Two
clock cycles are required to enter into or exit from this sleep
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the sleep mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
CY7C1382FV25 is a common IO device, the output enable
(OE) must be deserted HIGH before presenting data to the
DQs inputs. Doing so will tri-state the output drivers. As a
safety precaution, DQs are automatically tri-stated whenever
a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
the sleep mode. CE , CE , CE , ADSP, and ADSC must
1
2
3
ADSC write accesses are initiated when the following
conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP
is deasserted HIGH, (3) CE , CE , CE are all asserted active,
remain inactive for the duration of t
returns LOW.
after the ZZ input
ZZREC
1
2
3
and (4) the appropriate combination of the write inputs (GW,
Interleaved Burst Address Table
(MODE = Floating or VDD
BWE, and BW ) are asserted active to conduct a write to the
X
)
desired byte(s). ADSC triggered write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a byte
write is conducted, only the selected bytes are written. Bytes
not selected during a byte write operation will remain
unaltered. A synchronous self timed write mechanism has
been provided to simplify the write operations.
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
The
CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/
CY7C1382FV25 is a common IO device, the output enable
(OE) must be deserted HIGH before presenting data to the
DQs inputs. Doing so will tri-state the output drivers. As a
safety precaution, DQs are automatically tri-stated whenever
a write cycle is detected, regardless of the state of OE.
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
ZZ > V – 0.2V
Min.
Max.
80
Unit
mA
ns
I
t
t
t
t
DDZZ
DD
ZZ > V – 0.2V
2t
ZZS
DD
CYC
ZZ recovery time
ZZ < 0.2V
2t
ns
ZZREC
ZZI
CYC
ZZ Active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2t
ns
CYC
0
ns
RZZI
Document #: 38-05546 Rev. *E
Page 8 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Operation
Add. Used CE
CE
CE ZZ ADSP ADSC ADV WRITE OE CLK
DQ
1
2
3
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Sleep Mode, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
None
None
H
L
L
L
L
X
L
L
L
L
L
X
X
H
X
L
X
X
H
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
None
X
L
L
None
H
H
X
L
None
X
X
H
H
H
H
H
X
X
X
L
None
X
X
X
L
X
Tri-State
Q
External
External
External
External
External
Next
L-H
L
L
H
X
L
L-H Tri-State
L
H
H
H
H
H
X
L-H
L-H
D
Q
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
L
L
H
H
H
H
H
L
L
H
L
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H Tri-State
X
X
X
H
H
H
Q
Next
L
H
L
Next
L
Q
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Next
Next
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
X
H
X
H
H
X
X
H
X
H
H
H
H
H
H
H
H
H
L
L
H
L
H
X
X
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H Tri-State
L-H
L-H Tri-State
Q
H
X
X
L-H
L-H
D
D
L
Notes:
4. X = Don't Care, H = Logic HIGH, L = Logic LOW.
5. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
6. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks after
X
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't
care for the remainder of the write cycle
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05546 Rev. *E
Page 9 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Truth Table for Read/Write [6, 9]
Function (CY7C1380DV25/CY7C1380FV25)
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BW
X
H
H
H
H
H
H
H
H
L
BW
X
H
H
H
H
L
BW
X
H
H
L
BW
A
D
C
B
Read
Read
X
H
L
Write Byte A – (DQ and DQP )
L
A
A
Write Byte B – (DQ and DQP )
L
H
L
B
B
Write Bytes B, A
Write Byte C – (DQ and DQP )
L
L
L
H
H
L
H
L
C
C
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
L
L
L
L
H
L
L
L
L
Write Byte D – (DQ and DQP )
L
H
H
H
H
L
H
H
L
H
L
D
D
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
L
L
L
L
H
L
L
L
L
L
L
H
H
L
H
L
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
L
L
L
L
L
L
H
L
L
L
L
L
Write All Bytes
X
X
X
X
X
Truth Table for Read/Write [6, 9]
Function (CY7C1382DV25/CY7C1382FV25)
GW
H
BWE
BW
X
BW
A
B
Read
Read
H
L
L
L
L
L
X
X
H
L
H
H
H
L
Write Byte A – (DQ and DQP )
H
A
A
Write Byte B – (DQ and DQP )
H
H
L
B
B
Write Bytes B, A
Write All Bytes
Write All Bytes
H
L
H
L
L
L
X
X
Note:
9. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document #: 38-05546 Rev. *E
Page 10 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1380DV25/CY7C1382DV25 incorporates a serial
boundary scan test access port (TAP). This part is fully
compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3V or 2.5V IO logic levels.
The CY7C1380DV25/CY7C1382DV25 contains
a
TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V ) to prevent clocking of the device. TDI and TMS are
SS
internally pulled up and may be unconnected. They may
TAP Controller Block Diagram
alternately be connected to V
through a pull up resistor.
DD
TDO must be left unconnected. Upon power up, the device will
come up in a reset state which will not interfere with the
operation of the device.
0
Bypass Register
2
1
0
0
0
TAP Controller State Diagram
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
Selection
TDI
TDO
TEST-LOGIC
1
Circuitr
y
.
.
.
2
1
RESET
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
x
.
.
.
.
.
2
1
0
0
Boundary Scan Register
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
TCK
1
1
TMS
TAP CONTROLLER
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
1
0
PAUSE-IR
1
0
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (V ) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
DD
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
At power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
1
0
1
0
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
The 0 or 1 next to each state represents the value of TMS at
the rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the TAP Controller Block
Diagram. Upon power up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary ‘01’ pattern to
allow for fault isolation of the board-level serial test data path.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
Document #: 38-05546 Rev. *E
Page 11 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Bypass Register
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. The SAMPLE Z command
places all SRAM outputs into a High-Z state.
(V ) when the BYPASS instruction is executed.
SS
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is
captured in the boundary scan register.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO balls when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD, and SAMPLE
Z
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. As there is
a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
instructions can be used to capture the contents of the input
and output ring.
The boundary scan order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus
hold times (t and t ). The SRAM clock input might not be
CS
CH
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
TAP Instruction Set
Overview
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in Identification
Codes on page 15. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail below.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required; that is, while data
captured is shifted out, the preloaded data is shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the Shift-DR controller
state.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
IDCODE
The IDCODE instruction causes a vendor specific 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The boundary scan register has a special bit located at bit #85
(for 119-BGA package) or bit #89 (for 165-fBGA package).
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it will directly control the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
Document #: 38-05546 Rev. *E
Page 12 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
instruction. When HIGH, it will enable the output buffers to
drive the output bus. When LOW, this bit will place the output
bus into a High-Z condition.
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is powered
up, and also when the TAP controller is in the Test-Logic-Reset
state.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the Shift-DR state. During Update-DR, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
TH
CYC
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range
Parameter
Clock
Description
Min.
Max.
Unit
t
t
t
t
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
TCYC
TF
20
20
20
TH
ns
TL
Output Times
t
t
TCK Clock LOW to TDO Valid
10
ns
ns
TDOV
TDOX
TCK Clock LOW to TDO Invalid
0
Setup Times
t
t
t
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
ns
TMSS
TDIS
CS
Hold Times
t
t
t
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
TMSH
TDIH
CH
Capture Hold after Clock Rise
Notes:
10. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
11. Test conditions are specified using the load in TAP AC test conditions. t /t = 1ns.
R
F
Document #: 38-05546 Rev. *E
Page 13 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
2.5V TAP AC Test Conditions
2.5V TAP AC Output Load Equivalent
Input pulse levels.................................................V to 2.5V
1.25V
SS
Input rise and fall time..................................................... 1 ns
Input timing reference levels.........................................1.25V
Output reference levels.................................................1.25V
Test load termination supply voltage.............................1.25V
50Ω
TDO
ZO= 50 Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < T < +70°C; V = 2.5V ±0.125V unless otherwise noted)
A
DD
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
V
V
V
V
V
V
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
I
I
I
I
= –1.0 mA, V
= –100 µA, V
= 2.5V
= 2.5V
2.0
2.1
OH1
OH
OH
OL
OL
DDQ
DDQ
V
OH2
OL1
OL2
IH
= 8.0 mA, V
= 100 µA
= 2.5V
0.4
0.2
V
DDQ
V
V
V
= 2.5V
= 2.5V
= 2.5V
V
DDQ
DDQ
DDQ
1.7
–0.3
–5
V
+ 0.3
V
DD
0.7
5
V
IL
I
GND < V < V
µA
X
IN
DDQ
Identification Register Definitions
CY7C1380DV25/ CY7C1382DV25/
CY7C1380FV25
(512K x 36)
CY7C1382FV25
(1 Mbit x 18)
Instruction Field
Revision Number (31:29)
Description
000
01011
000
01011
Describes the version number.
Reserved for internal use.
Device Depth (28:24)
Device Width (23:18) 119-BGA
Device Width (23:18) 165-FBGA
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
101000
000000
100101
00000110100
1
101000
000000
010101
00000110100
1
Defines the memory type and architecture.
Defines the memory type and architecture.
Defines the width and density
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Instruction
Bypass
ID
3
3
1
1
32
85
89
32
85
89
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball FBGA package)
Note:
12. All voltages referenced to V (GND).
SS
Document #: 38-05546 Rev. *E
Page 14 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use. This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use. This instruction is reserved for future use.
Do Not Use. This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Bit #
1
Ball ID
Bit #
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Ball ID
F6
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Ball ID
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
Bit #
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Ball ID
L1
H4
T4
T5
T6
R5
L5
2
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
B6
D4
B4
F4
M2
N1
3
4
P1
5
K1
6
L2
7
R6
U6
R7
T7
P6
N7
M6
L7
N2
P2
8
9
R3
10
11
12
13
14
15
16
17
18
19
20
21
22
T1
R1
T2
L3
R2
K6
P7
N6
L6
G1
H2
D1
E2
G2
H1
J3
T3
L4
N4
P4
K7
J5
M4
A5
K4
E4
Internal
H6
G7
2K
Notes:
13. Balls that are NC (No Connect) are preset LOW.
14. Bit #85 is preset HIGH.
Document #: 38-05546 Rev. *E
Page 15 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
165-Ball BGA Boundary Scan Order [13, 15]
Bit #
1
Ball ID
N6
Bit #
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Ball ID
D10
C11
A11
B11
A10
B10
A9
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
G1
D2
E2
2
N7
3
N10
P11
P8
4
F2
5
G2
H1
H3
J1
6
R8
7
R9
8
P9
B9
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
C10
A8
K1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
L1
B8
M1
J2
A7
B7
K2
B6
L2
A6
M2
N1
N2
P1
B5
A5
A4
B4
R1
R2
P3
B3
A3
A2
R3
P2
H10
G11
F11
E11
D11
G10
F10
E10
B2
C2
R4
P4
B1
A1
N5
P6
C1
D1
R6
Internal
E1
F1
Note:
15. Bit #89 is preset HIGH.
Document #: 38-05546 Rev. *E
Page 16 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
DC Input Voltage ................................... –0.5V to V + 0.5V
Maximum Ratings
DD
Current into Outputs (LOW) ........................................ 20 mA
Exceeding the maximum ratings may impair the useful life of
the device. For user guidelines, not tested.
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current .................................................... >200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on V Relative to GND ....... –0.3V to +3.6V
DD
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
/V
Supply Voltage on V
Relative to GND ...... –0.3V to +V
DD
DD DDQ
DDQ
2.5V ± 5%
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to V
+ 0.5V
DDQ
Electrical Characteristics
Over the Operating Range
Parameter
Description
Power Supply Voltage
IO Supply Voltage
Test Conditions
Min.
Max.
Unit
V
V
2.375
2.375
2.0
2.625
DD
DDQ
OH
OL
IH
V
V
V
V
V
I
for 2.5V IO
for 2.5V IO, I = −1.0 mA
V
V
DD
Output HIGH Voltage
Output LOW Voltage
V
OH
for 2.5V IO, I = 1.0 mA
0.4
V
OL
Input HIGH Voltage
Input LOW Voltage
for 2.5V IO
for 2.5V IO
1.7
–0.3
–5
V
+ 0.3V
0.7
V
DD
V
IL
Input Leakage Current GND ≤ V ≤ V
except ZZ and MODE
5
µA
X
I
DDQ
Input Current of MODE Input = V
–30
–5
µA
µA
SS
Input = V
5
DD
Input Current of ZZ
Input = V
Input = V
µA
SS
DD
30
5
µA
I
I
Output Leakage Current GND ≤ V ≤ V
Output Disabled
–5
µA
OZ
I
DD,
V
Operating Supply
V
f = f
= Max., I
= 0 mA,
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
350
300
275
160
150
140
70
mA
mA
mA
mA
mA
mA
mA
DD
DD
DD
OUT
CYC
Current
= 1/t
MAX
I
Automatic CE
Power Down
Current—TTL Inputs
V = Max, Device Deselected, 4.0-ns cycle, 250 MHz
DD
SB1
V
≥ V or V ≤ V
IN
IH
IN
IL
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
f = f
= 1/t
MAX CYC
I
I
Automatic CE
Power Down
Current—CMOS Inputs f = 0
V = Max, Device Deselected, All speeds
DD
SB2
SB3
V
≤ 0.3V or V > V – 0.3V,
IN
IN
DDQ
Automatic CE
Power Down
Current—CMOS Inputs f = f
V
V
= Max, Device Deselected, or 4.0-ns cycle, 250 MHz
135
130
125
80
mA
mA
mA
mA
DD
≤ 0.3V or V > V
– 0.3V
IN
IN
DDQ
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
= 1/t
MAX
CYC
I
Automatic CE
V = Max, Device Deselected, All speeds
DD
SB4
Power Down
Current—TTL Inputs
V
≥ V or V ≤ V , f = 0
IN
IH IN IL
Notes:
16. Overshoot: V (AC) < V +1.5V (pulse width less than t
/2), undershoot: V (AC) > –2V (pulse width less than t /2).
CYC
IH
DD
CYC
IL
17. T
: assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
power up
DD
IH
DD
DDQ
DD
Document #: 38-05546 Rev. *E
Page 17 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Capacitance [18]
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
pF
C
C
C
Input Capacitance
T = 25°C, f = 1 MHz,
5
5
5
8
8
8
9
9
9
IN
A
V
/V
= 2.5V
DD DDQ
Clock Input Capacitance
Input/Output Capacitance
pF
CLK
IO
pF
Thermal Resistance [18]
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
Θ
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard
testmethodsandproceduresfor
measuring thermal impedance,
in accordance with
28.66
23.8
20.7
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
4.08
6.2
4.0
°C/W
JC
EIA/JESD51.
AC Test Loads and Waveforms
2.5V IO Test Load
R = 1667Ω
2.5V
OUTPUT
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
GND
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Note:
18. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05546 Rev. *E
Page 18 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Switching Characteristics
Over the Operating Range
250 MHz
200 MHz
167 MHz
Parameter
Description
(Typical) to the First Access
DD
Min.
Max
Min.
Max.
Min.
Max
Unit
t
V
1
1
1
ms
POWER
Clock
t
t
t
Clock Cycle Time
Clock HIGH
4.0
1.7
1.7
5
6
ns
ns
ns
CYC
CH
2.0
2.0
2.2
2.2
Clock LOW
CL
Output Times
t
t
t
t
t
t
t
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
2.6
3.0
3.4
ns
ns
ns
ns
ns
ns
ns
CO
1.0
1.0
1.3
1.3
1.3
1.3
DOH
CLZ
Clock to Low-Z
Clock to High-Z
2.6
2.6
3.0
3.0
3.4
3.4
CHZ
OEV
OELZ
OEHZ
OE LOW to Output Valid
OE LOW to Output Low-Z
OE HIGH to Output High-Z
0
0
0
2.6
3.0
3.4
Setup Times
t
t
t
t
t
t
Address Setup Before CLK Rise
ADSC, ADSP Setup Before CLK Rise
ADV Setup Before CLK Rise
1.2
1.2
1.2
1.2
1.2
1.2
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
AS
ADS
ADVS
WES
DS
GW, BWE, BW Setup Before CLK Rise
X
Data Input Setup Before CLK Rise
Chip Enable Setup Before CLK Rise
CES
Hold Times
t
t
t
t
t
t
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
AH
ADH
ADVH
WEH
DH
GW, BWE, BW Hold After CLK Rise
X
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
CEH
Notes:
19. Timing reference level is 1.5V when V
= 1.25V when V
= 2.5V.
DDQ
DDQ
20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
21. This part has a voltage regulator internally; t
can be initiated.
is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
POWER
22. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
CHZ CLZ OELZ
23. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
OEHZ
OELZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
24. This parameter is sampled and not 100% tested.
Document #: 38-05546 Rev. *E
Page 19 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Switching Waveforms
Read Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,
BWx
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV
suspends
burst.
t
t
OEV
CO
t
t
OEHZ
t
t
CHZ
OELZ
DOH
t
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Data Out (Q)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note:
25. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document #: 38-05546 Rev. *E
Page 20 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Switching Waveforms (continued)
Write Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
ADDRESS
BWE,
t
t
AH
AS
A1
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BW
X
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
Data In (D)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Note:
26.
Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW and BW LOW.
X
Document #: 38-05546 Rev. *E
Page 21 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Switching Waveforms (continued)
Read/Write Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
BWE,
t
t
WEH
WES
BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
High-Z
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
Notes:
27.
ADSP or ADSC.
The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by
28. GW is HIGH.
Document #: 38-05546 Rev. *E
Page 22 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Switching Waveforms (continued)
ZZ Mode Timing
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
29. Device must be deselected when entering ZZ sleep mode. See cycle descriptions table for all possible signal conditions to deselect the device.
30. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05546 Rev. *E
Page 23 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Ordering Information
Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Part and Package Type
167
CY7C1380DV25-167AXC
CY7C1382DV25-167AXC
CY7C1380FV25-167BGC
CY7C1382FV25-167BGC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1380FV25-167BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382FV25-167BGXC
CY7C1380DV25-167BZC
CY7C1382DV25-167BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1380DV25-167BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382DV25-167BZXC
CY7C1380DV25-167AXI
CY7C1382DV25-167AXI
CY7C1380FV25-167BGI
CY7C1382FV25-167BGI
CY7C1380FV25-167BGXI
CY7C1382FV25-167BGXI
CY7C1380DV25-167BZI
CY7C1382DV25-167BZI
CY7C1380DV25-167BZXI
CY7C1382DV25-167BZXI
CY7C1380DV25-200AXC
CY7C1382DV25-200AXC
CY7C1380FV25-200BGC
CY7C1382FV25-200BGC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Industrial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
200
Commercial
CY7C1380FV25-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382FV25-200BGXC
CY7C1380DV25-200BZC
CY7C1382DV25-200BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1380DV25-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382DV25-200BZXC
CY7C1380DV25-200AXI
CY7C1382DV25-200AXI
CY7C1380FV25-200BGI
CY7C1382FV25-200BGI
CY7C1380FV25-200BGXI
CY7C1382FV25-200BGXI
CY7C1380DV25-200BZI
CY7C1382DV25-200BZI
CY7C1380DV25-200BZXI
CY7C1382DV25-200BZXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Industrial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Document #: 38-05546 Rev. *E
Page 24 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Ordering Information (continued)
Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
250
CY7C1380DV25-250AXC
CY7C1382DV25-250AXC
CY7C1380FV25-250BGC
CY7C1382FV25-250BGC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1380FV25-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
CY7C1382FV25-250BGXC
CY7C1380DV25-250BZC
CY7C1382DV25-250BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1380DV25-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1382DV25-250BZXC
CY7C1380DV25-250AXI
CY7C1382DV25-250AXI
CY7C1380FV25-250BGI
CY7C1382FV25-250BGI
CY7C1380FV25-250BGXI
CY7C1382FV25-250BGXI
CY7C1380DV25-250BZI
CY7C1382DV25-250BZI
CY7C1380DV25-250BZXI
CY7C1382DV25-250BZXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Industrial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Document #: 38-05546 Rev. *E
Page 25 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Package Diagrams
Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-085050)
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
1.00 REF.
0.20 MIN.
51-85050-*B
DETAIL
A
Document #: 38-05546 Rev. *E
Page 26 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Package Diagrams (continued)
Figure 2. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.75 0.15(119X)
Ø1.00(3X) REF.
1
2
3
4
5
6
7
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
G
H
J
K
L
J
K
L
M
N
P
R
T
M
N
P
R
T
U
U
1.27
0.70 REF.
A
3.81
12.00
7.62
B
14.00 0.20
0.15(4X)
30° TYP.
51-85115-*B
SEATING PLANE
C
Document #: 38-05546 Rev. *E
Page 27 of 29
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Package Diagrams (continued)
Figure 3. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-085180)
BOTTOM VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
-0.06
Ø0.50
(165X)
+0.14
1
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
A
B
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00
5.00
10.00
13.00 0.10
B
B
13.00 0.10
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDECREFERENCE: MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
SEATING PLANE
C
51-85180-*A
Intel and Pentium are registered trademarks, and i486 is a trademark of Intel Corporation. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05546 Rev. *E
Page 28 of 29
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Document History Page
DocumentTitle:CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/CY7C1382FV25,18-Mbit(512Kx36/1Mx18)Pipelined
SRAM
Document Number: 38-05546
Issue Orig. of
REV. ECN NO.
Date
Change
Description of Change
**
254515 See ECN RKF New data sheet
*A
288531 See ECN SYT Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 225 and 133 Mhz Speed Bin
Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA Packages
Added comment of ‘Pb-free BG packages availability’ below the Ordering Information
*B
326078 See ECN
PCI Address expansion pins/balls in the pinouts for all packages are modified as per
JEDEC standard
Added description on EXTEST Outut Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed Device Width (23:18) for 119-BGA from 000000 to 101000
Added seperate row for 165 -FBGA Device Width (23:18)
Changed Θ and Θ for TQFP Packagefrom 31 and 6 °C/W to 28.66 and 4.08 °C/W
JA
JC
respectively
Changed Θ and Θ for BGA Package from 45 and 7 °C/W to 23.8 and 6.2 °C/W
JA
JC
respectively
Changed Θ and Θ for FBGA Package from 46 and 3 °C/W to 20.7 and 4.0 °C/W
JA
JC
respectively
Modified V
V
test conditions
OL, OH
Removed comment of ‘Pb-free BG packages availability’ below the Ordering Infor-
mation
Updated Ordering Information Table
*C
418125 See ECN NXR Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Changed the description of I from Input Load Current to Input Leakage Current on
X
page# 18
Changed the I current values of MODE on page # 18 from –5 µA and 30 µA
X
to –30 µA and 5 µA
Changed the I current values of ZZ on page # 18 from –30 µA and 5 µA
X
to –5 µA and 30 µA
Changed V < V to V < V on page # 18
IH
DD
IH
DD
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
*D
*E
475009 See ECN VKN Added the Maximum Rating for Supply Voltage on V
Relative to GND
DDQ
Changed t , t from 25 ns to 20 ns and t
from 5 ns to 10 ns in TAP AC Switching
TH TL
TDOV
Characteristics table.
Updated the Ordering Information table.
793579 See ECN VKN Added Part numbers CY7C1380FV25 and CY7C1382FV25
Added footnote# 3 regarding Chip Enable
Updated Ordering Information table
Document #: 38-05546 Rev. *E
Page 29 of 29
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