SiI 141B PanelLink® Digital Receiver
General Description
May 2001
Features
The SiI 141B uses PanelLink Digital technology to support displays
ranging from VGA to High Refresh XGA (25-86 MHz), which is ideal for LCD
desktop monitor applications. With a flexible single or dual pixel out interface
and selectable output drive, the SiI 141B receiver supports up to true color
panels (24 bit/pixel, 16.7M colors) in 1 pixel/clock mode (18 bit/pixel in 2
pixel/clock mode). PanelLink also features an inter-pair skew tolerance up to
1 full input clock cycle. The SiI 141B is pin for pin compatible with the SiI
141 but incorporates a number of enhancements. These include an
improved jitter tolerant PLL design, new HSYNC filter and power down when
the clock is inactive. All PanelLink products are designed on a scaleable
CMOS architecture to support future performance requirements while
maintaining the same logical interface. System designers can be assured
that the interface will be fixed through a number of technology and
performance generations.
•
Scaleable Bandwidth: 25-86 MHz (VGA to High
Refresh XGA)
Low Power: 3.3V core operation & power-down mode
Automatic power down when clock is inactive
High Skew Tolerance: 1 full input clock cycle (15ns at
65 MHz)
Pin-compatible with SiI 101, SiI 141
Sync Detect: for Plug & Display “Hot Plugging”
Cable Distance Support: over 5m with twisted-pair,
fiber-optics ready
•
•
•
•
•
•
•
Compliant with DVI 1.0 (DVI is backwards compatible
with VESA® P&DTM and DFP)
PanelLink Digital technology simplifies PC design by resolving many of
the system level issues associated with high-speed digital design, providing
the system designer with a digital interface solution that is quicker to market
and lower in cost.
SiI 141B Pin Diagram
24-bit Input Data for 1-pixel/clock mode
8-bit Channel 1 Data
8-bit Channel 2 Data
8-bit Channel 0 Data
1-pixel/clock
1-pixel/clock
1-pixel/clock
18-bit Even Data for 2-pixel/clock mode
6-bit Odd Channel 0
Data 2-pixel/clock
6-bit Even Channel 2
Data 2-pixel/clock
6-bit Even Channel 1
Data 2-pixel/clock
DE
Q20
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Q4
20
19
18
17
16
15
14
13
12
11
10
9
Q3
Q21
Q2
Q22
Q1
Q23
Q0
OGND
Q24
OVCC
VSYNC
OGND
HSYNC
GND
CTL3
CTL2
CTL1
SCDT
DFO
OVCC
Q25
SiI141B
VCC
Q26
80-Pin TQFP
(Top View)
Q27
Q28
8
Q29
7
Q30
6
Q31
PIXS
OGND
PDO
5
Q32
4
Q33
3
Q34
2
PD
1
RESERVED
Q35
DIFFERENTIAL SIGNAL
MISC.
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SiI 141B
SiI-DS-0037-C
DC Specifications
Under normal operating conditions unless otherwise specified. Low drive strength values, when ST=0, are shown in brackets.
Symbol
IOHD
Parameter
Output High Drive
Conditions
VOUT = 2.4
Min
Typ
Max
Units
Data and Controls
ST=1
ST=0
5.0
2.5
10.3
5.2
17.6
8.8
mA
IOLD
IOHC
IOLC
Output Low Drive
Data and Controls
VOUT = 0.4
ST=1
ST=0
VOUT = 2.4
ST=1
ST=0
VOUT = 2.0
ST=1
ST=0
-5.5
-2.8
-8.3
-4.2
-11.2
-5.6
mA
mA
ODCK High Drive
ODCK Low Drive
10.1
5.0
20.6
10.3
35.1
17.6
-11.1
-5.5
75
-16.7
-8.3
-22.4
-11.2
1000
mA
mV
µA
VID
Differential Input Voltage
Single Ended Amplitude
Output leakage current to ground in
high impedance mode (PD, PDO =
LOW)
IPDL
10
IPD
Power-down Current1
Power-down Current
50
4
125
100
7
155
µA
mA
mA
ICLKI
IPDO
ICCR
RXC± Inactive
Power-down-output Current
Receiver Supply Current
CLOAD = 10pF
ODCK=86MHz, 1-pixel/clock mode2
157
172
182
194
mA
mA
REXT_SWING = 510 Ω
Typical Pattern3
CLOAD = 10pF
REXT_SWING = 510 Ω
Worst Case Pattern4
1
Notes:
The transmitter must be in power-down mode, powered off, or disconnected for the current to be under this maximum.
For worst case I/O power consumption.
The Typical Pattern contains a gray scale area, checkerboard area, and text.
Black and white checkerboard pattern, each checker is one pixel wide.
2
3
4
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SiI 141B
SiI-DS-0037-C
AC Specifications
Under normal operating conditions unless otherwise specified. Low drive strength values, when ST=0, are given below.
Symbol
TDPS
Parameter
Intra-Pair (+ to -) Differential Input Skew
Conditions
86 MHz
Min
Typ
Max
470
7
Units
ps
TCCS
Channel to Channel Differential Input Skew
86 MHz
ns
65 MHz
86 MHz
TIJIT
Worst Case Differential Input Clock Jitter tolerance1,2
465
ps
350
3.5
4.5
3.5
4.5
1.6
2.1
1.6
2.1
3.0
4.2
3.0
4.2
1.5
1.9
1.5
1.9
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DLHT
Low-to-High Transition Time: Data and Controls
(43 MHz, 2-pixel/clock, PIXS=1)
Low-to-High Transition Time: Data and Controls
(65 MHz, 1-pixel/clock, PIXS=0)
Low-to-High Transition Time: ODCK
(43 MHz, 2-pixel/clock, PIXS=1)
Low-to-High Transition Time: ODCK
(65 MHz, 1-pixel/clock, PIXS=0)
High-to-Low Transition Time: Data and Controls
(43 MHz, 2-pixel/clock, PIXS=1)
High-to-Low Transition Time: Data and Controls
(65 MHz, 1-pixel/clock, PIXS=0)
High-to-Low Transition Time: ODCK
(43 MHz, 1-pixel/clock, PIXS=0)
High-to-Low Transition Time: ODCK
(65 MHz, 1-pixel/clock, PIXS=0)
CL = 10pF; ST = 1
CL = 5pF; ST = 0
CL = 10pF; ST = 1
CL = 5pF; ST = 0
CL = 10pF; ST = 1
CL = 5pF; ST = 0
CL = 10pF; ST = 1
CL = 5pF; ST = 0
CL = 10pF; ST = 1
CL = 5pF; ST = 0
CL = 10pF; ST = 1
CL = 5pF; ST = 0
CL = 10pF; ST = 1
CL = 5pF; ST = 0
CL = 10pF; ST = 1
CL = 5pF; ST = 0
CL = 10pF; ST = 1
DHLT
TSETUP
Data, DE, VSYNC, HSYNC, and CTL[3:1] Setup Time to
ODCK falling edge (OCK_INV = 0) or to ODCK rising
edge (OCK_INV = 1)
3.6
3.0*
18.4
19.0*
8.0
8.4*
24.0
24.5*
11.6
25
23.3
12.5
5.0
4.4
9.0
8.2
6
ns
ns
CL = 5pF; ST = 0
*OCK_INV = 1
THOLD
Data, DE, VSYNC, HSYNC, and CTL[3:1] Hold Time from CL = 10pF; ST = 1
ODCK falling edge, (OCK_INV = 0) or from ODCK rising
edge (OCK_INV = 1)
*OCK_INV = 0
ns
ns
CL = 5pF; ST = 0
RCIP
FCIP
RCIP
FCIP
RCIH
ODCK Cycle Time (1 pixel/clock)
ODCK Frequency (1 pixel/clock)
ODCK Cycle Time (2 pixels/clock)
ODCK Frequency (2 pixels/clock)
ODCK High Time
40
86
80
43
ns
MHz
ns
MHz
CL = 10pF, ST=1
CL = 5pF, ST=0
CL = 10pF, ST=1
CL = 5pF, ST=0
CL = 10pF, ST=1
CL = 5pF, ST=0
CL = 10pF, ST=1
CL = 5pF, ST=0
65 MHz, One Pixel / Clock, PIXS = 0 3
43 MHz, Two Pixel / Clock, PIXS = 1 3
ns
ns
RCIL
ODCK Low Time
65 MHz, One Pixel / Clock, PIXS = 0 3
43 MHz, Two Pixel / Clock, PIXS = 1 3
5
9
9
ns
ns
THSC
TFSC
Link disabled (DE inactive) to SCDT low1
Link disabled (Tx power down) to SCDT low 5
Link enabled (DE active) to SCDT high6
160
200
ms
ms
Falling
DE edges
250
40
10
100
8
TCLKPD
TCLKPU
TPDL
Delay from RXC+/- Inactive to high impedance outputs
Delay from RXC+/- active to data active
Delay from PD/ PDO Low to high impedance outputs
RXC+/- = 25MHz
RXC+/- = 25MHz
µs
µs
ns
1
Notes:
Jitter defined as per DVI 1.0 Specification, Section 4.6 Jitter Specification.
2
3
4
Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electrical Measurement Procedures.
Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle.
The setup and hold timing for the data and controls relative to the ODCK rising edge (OCK_INV=1) is by design the same
as the falling edge timing.
5
Measured when transmitter was powered down (see SiI/AN-0005 “PanelLink Basic Design /Application Guide,” Section 2.4).
6 Refer to the transmitter datasheet for minimum DE high and low time
7 Data is active (i.e. not tri-stated) but not valid yet. Data and controls are valid only when SCDT goes high. See TFSC and
Figure 7.
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SiI 141B
SiI-DS-0037-C
Timing Diagrams
2.0 V
2.0 V
SiI141B
10pF (5pF)
0.8 V
0.8 V
DLHT
DHLT
Figure 1. Digital Output Transition Times
RCIP
RCIH
2.0 V
2.0 V
2.0 V
0.8 V
0.8 V
RCIL
Figure 2. Receiver Clock Cycle/High/Low Times
RX0
VDIFF = 0V
RX1
RX2
TCCS
VDIFF = 0V
Figure 3. Channel-to-Channel Skew Timing
Output Timing
ODCK_INV = 1
ODCK_INV = 0
TSETUP
THOLD
QE[23:0]/QO[23:0],
DE, VSYNC, HSYNC,
CTL[3:1]
Figure 4. Output Data Setup/Hold Times to ODCK
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SiI 141B
SiI-DS-0037-C
PD
TPDL
Q[35:0], DE,
VSYNC, HSYNC,
CTL[3:1]
Figure 5. Output Signals Disabled Timing from PD Active
TCLKPD
RXC
...
Q[35:0], DE,
VSYNC, HSYNC,
CTL[3:1]
...
Figure 6. Output Signals Disabled Timing from Clock Inactive
TCLKPU +.T.F.SC
...
RXC
SCDT
Figure 7. Wake-up on Clock Detect
THSC
DE
SCDT
TFSC
DE
SCDT
Figure 8. SCDT Timing from DE Inactive/Active
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SiI 141B
SiI-DS-0037-C
Output Pin Description
Pin Name
Pin #
Type Description
Q35 – Q0
See
Out
Output Data [35:0].
Output data is synchronized with output data clock (ODCK).
When PIXS is low Q35-Q24 are low and Q23-Q0 output 24-bit/pixel data.
SiI 141B
Pin
When PIXS is high Q17-Q0 output the even numbered pixels (pixel 0, 2, 4, ... , etc.) and Q35-Q18 output
the odd numbered pixels (pixel 1, 3, 5, ... , etc.).
Diagram
Refer to the TFT Signal Mapping (SiI/AN-0008) and DSTN Signal Mapping (SiI/AN-0007) application notes
which tabulate the relationship between the input data to the transmitter and output data from the receiver.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak
internal pull-down device brings each output to ground.
ODCK
DE
36
41
Out
Out
Output Data Clock.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak
internal pull-down device brings each output to ground.
Output Data Enable.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak
internal pull-down device brings each output to ground.
HSYNC
VSYNC
CTL1
CTL2
CTL3
12
14
8
9
10
Out
Out
Out
Out
Out
Horizontal Sync output control signal.
Vertical Sync output control signal.
General output control signal 1. This pin is not controlled by PDO.
General output control signal 2
General output control signal 3.
A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak
internal pull-down device brings each output to ground.
Configuration Pin Description
Pin Name
Pin # Type Description
OCK_INV
80
In
ODCK Polarity. A low level selects normal ODCK output, which enables data latching on the falling
edge. A high level (3.3V) selects inverted ODCK output, which enables data latching on the rising edge.
Both conditions are for color TFT panel support. For color 24-bit DSTN panel support, please refer to the
DSTN Signal Mapping (SiI/AN-0008-A) application note.
PIXS
DF0
5
6
In
In
Pixel Select. A low level indicates that output data is one pixel (up to 24-bit) per clock and a high level
(3.3V) indicates that output data is two pixels (up to 36-bit) per clock.
Output Data Format. This pin controls clock and data output format. A low level indicates that ODCK
runs continuously for color TFT panel support and a high level (3.3V) indicates that ODCK is stopped
(LOW) for color 24-bit DSTN panel support when DE is low. Refer to the TFT Signal Mapping (SiI/AN-
0007-A) and DSTN Signal Mapping (SiI/AN-0008-A) application notes for a table on TFT or DSTN panel
support.
HSYNC_DEJTR
ST
75
79
In
In
A low level enables the HSYNC de-jitter circuitry. A high level disables the de-jitter circuitry. If left
unconnected, the circuitry defaults to disabled.
Output Driver Strength. A low level indicates low drive. A high level indicates high drive.
Power Management Pin Description
Pin Name Pin # Type Description
SCDT
PD
7
2
Out
In
SyncDetect. A high level is output when DE is toggling. A low level is output when DE is inactive. See page
9.
Power Down (active low). A high level (3.3V) indicates normal operation and a low level indicates power down
mode. During power down mode all internal circuitry is powered down and digital I/O are set the same as
when PDO is asserted. (see PDO pin description).
PDO
3
In
Power Down Output (active low). A high level indicates normal operation. A low level puts the output drivers
only into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground.
There is an internal pull-up resistor on PDO that defaults the chip to normal operation if left unconnected.
SCDT and CTL1 are not tri-stated by this pin. See explanation of clock detect on page 8-9.
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SiI 141B
SiI-DS-0037-C
Differential Signal Data Pin Description
Pin Name Pin #
Type
Description
RX0+
RX0-
RX1+
RX1-
RX2+
RX2-
RXC+
RXC-
EXT_RES
70
71
67
68
64
65
74
73
76
Analog TMDS Low Voltage Differential Signal input data pairs.
Analog TMDS Low Voltage Differential Signal input clock pair.
Analog Impedance Matching Control. Resistor value should be ten times the characteristic impedance of the cable.
In the common case of 50Ω transmission line, an external 530Ω resistor must be connected between AVCC
and this pin.
Reserved Pin Description
Pin Name
Pin #
Type
Description
RSVD
1
Out
This signal must be left unconnected.
Power and Ground Pin Description
Pin Name
VCC
Pin #
39
50
61
11
37
62
15
28
48
4
Type
Description
Power Core VCC, must be set to 3.3V.
GND
OVCC
OGND
Ground Digital GND.
Power Output VCC, must be set to 3.3V.
Ground Output GND.
13
26
46
63
69
66
72
77
78
AVCC
AGND
Power Analog VCC, must be set to 3.3V.
Ground Analog GND.
PVCC
PGND
Power PLL VCC, must be set to 3.3V.
Ground PLL GND.
Application Information
The SiI141B is pin for pin compatible with the SiI141 but includes two new features, HSYNC de-jitter and power
down when the clock is inactive.
HSYNC de-jitter enables the 141B to operate properly even when the HSYNC signal contains jitter. Pin 75 is used
to enable or disable this capability (a reserved pin tied high on the SiI141). Tying this pin low enables the HSYNC
de-jitter circuitry while tying it high disables the circuitry. The HSYNC de-jitter circuitry operates normally with most
VESA standard timings. Some DOS mode resolutions do not have timings that are a multiple of eight (HSYNC
and VSYNC total times and front and back porch times are multiples of eight pixel times). If they are not a multiple
of eight, operation is not guaranteed and the HSYNC de-jitter circuitry should be turned off. When HSYNC de-
jitter is enabled, the circuitry will introduce anywhere from 0 to 7 CLK delays in the HSYNC signal relative to the
output data.
The SiI141B includes a new power saving feature, power down with clock detect circuit. The SiI141B will go into a
low power mode when there is no video clock coming from the transmitter. In this mode the entire chip is powered
down except the clock detect circuitry. During this mode digital I/O are set to a high impedance (tri-state) mode. A
weak internal pull-down device brings each output to ground. The device power down and wake-up times are
shown in Figures 6 and 7.
The SiI141B also includes a sync detect feature for pin compatibility with SiI141. In both the SiI141 and SiI141B,
SCDT goes low when DE is inactive.
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SiI 141B
SiI-DS-0037-C
In some application, SCDT is connected to the PDO pin to provide a power savings mode. In others, SCDT is
connected to an external circuit to signal when an incoming video signal is available. These external devices may
use an internal pull up which can cause problems.
If SCDT is connected to an external circuit which has an internal pull up, then SCDT will not stay low when no
video signal is present. The recommended circuit to keep SCDT low is shown Figure 9. For most applications,
Silicon Image recommends a pull down resistor of 1.5 KΩ. However, conditions within every design may vary.
Please use the calculations below to determine the proper pull-down resistor value.
internal pull up
SCDT(pin# 7)
weak internal
pull down
R
external
chip
pull down resister
SiI141B
Figure 9. Schematic for SCDT connected to external device with pull up
The external pull down resistor value depends on the pull-up circuit in the external device and can be calculated
with Equation [1] and [2] if the pull up is a passive circuit. If the pull up is an active circuit, please consult the
manufacture of the other device.
The calculation for the maximum resistor value is shown in the equation [1] below. In powered down mode, low
power consumption is achieved by making the resistor value as large as possible. Equation [1] determines the
maximum value of R while ensuring that SCDT stays lower than VIL of the external chip when SCDT goes into high
impedance. The small current flowing into the SiI141B internal pull down resistor is ignored in equation [1].
R
Equation [1a]
×VCCMAX <VIL
RPull −Up + R
(RPull −Up ×VIL )
R <
Equation [1b]
(
Vcc max −VIL )
Example :
Pull-up resistor value is 10 KΩ, VIL of external chip is 0.8V, and maximum Vcc is 3.6V
R < 2,857ohms = (10 KΩ x 0.8V) / (3.6V – 0.8V)
The resistor value should be smaller than 2,857 KΩ.
The calculation for the minimum resistor value is shown in the equation [2]. The minimum value is set so the
SCDT voltage exceeds VIH of the external chip in normal operation. In equation [2], the small current flowing into
the SiI141B internal pull-down resistor is ignored.
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SiI 141B
SiI-DS-0037-C
VCC
VIH
IOHDMIN
Equation [2]
R >
or R >
IOHDMIN
Example :
When ST(pin# 79) = 1,Vcc = 3.3V
R > 660Ω = Vcc (or VIH of external chip) / Min IOHD = 3.3V / 5.0mA
The resistor value should be larger than 660ohms
When ST(pin# 79) = 0,Vcc = 3.3V
R > 1,320Ω = Vcc (or VIH of external chip) / Min IOHD = 3.3V / 2.5mA
The resistor value should be larger than 1,320ohms.
These examples assume Vcc (or VIH) of 3.3V, with a lower VIH, the minimum pull down resistor value may be
smaller.
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SiI 141B
SiI-DS-0037-C
80-pin TQFP Package Dimensions
Lead Length
1.00mm
80-pin Plastic TQFP
Lead Width
0.22mm
Lead Pitch
0.50mm
Device #
Lot #
Date Code #
SiI Rev. #
SiI141BCT80
LNNNNN.NLLL
XXYY
X.XX
Body Thickness
1.0mm
Package Height
1.15mm max.
Clearance
0.15mm max.
Body Size 12.00mm
Footprint 14.00mm
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SiI 141B
SiI-DS-0037-C
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Copyright Notice
This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or send/transmit any part of this
documentation without the express written permission of Silicon Image, Inc.
Trademark Acknowledgment
Silicon Image, the Silicon Image logo, PanelLink and the PanelLink Digital logo are trademarks or registered trademarks of Silicon Image,
Inc. All other trademarks are the property of their respective holders.
Disclaimer
This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the information in this document
as necessary. The customer should make sure that they have the most recent data sheet version. Silicon Image, Inc. holds no responsibility
for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not
infringe upon any patents. Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to
infringe upon such rights.
Ordering Information
Part Number: SiI141BCT80
Revision History
Revision
Date Comment
A
B
C
11/00 Full release
1/01
5/01
Added application information concerning HSYNC de-jitter and power down on clock
Updated EXT_RES value for 50Ω transmission line.
© 2001 Silicon Image, Inc. 5/01 SiI-DS-0037-C
Silicon Image, Inc.
1060 E. Arques Ave
Sunnyvale, CA 94086
USA
Tel: 408-616-4000
Fax: 408-830-9530
E-Mail: [email protected]
Web:
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